NXP i.MX21 Reference guide

NXP i.MX21 Reference guide
i.MX21
Applications Processor
Reference Manual
Document Number: MC9328MX21RM
Rev. 3
04/2007
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Contents – Concise
Part 1: Device Introduction
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Chapter 2 Signal Descriptions and Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Chapter 3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Part 2: Core Technology
Chapter 4 ARM9 Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 5 ARM926EJ-S Interrupt Controller (AITC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 6 Phase-Locked Loop (PLL), Clock and Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 7 AHB-Lite IP Interface (AIPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
5-1
6-1
7-1
Part 3: System Control
Chapter 8 System Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Chapter 9 Internal ROM, System Boot Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Chapter 10 Multi-layer AHB Crossbar Switch (MAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Chapter 11 JTAG Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Chapter 12 Watchdog Timer Module (WDOG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Chapter 13 Real-Time Clock (RTC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Chapter 14 General-Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
Chapter 15 General-Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
Chapter 16 Pulse-Width Modulator (PWM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
Part 4: Memory Interfaces
Chapter 17 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 18 Direct Memory Access Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 19 NAND Flash Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 20 External Interface Module (EIM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 21 Bus Master Interface (BMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17-1
18-1
19-1
20-1
21-1
Part 5: InterChip Connectivity
Chapter 22 I2C Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
Chapter 23 Configurable Serial Peripheral Interface (CSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
Chapter 24 Synchronous Serial Interface (SSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
Part 6: Peripherals
Chapter 25 CMOS Sensor Interface (CSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 26 Liquid Crystal Display Controller (LCDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 27 Smart Liquid Crystal Display Controller (SLCDC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 28 enhanced Multimedia Accelerator (eMMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 29 MultimediaCard/Secure Digital Host Controller (MMC/SDHC) . . . . . . . . . . . . . . . . . . .
Chapter 30 Digital Audio Mux (AUDMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25-1
26-1
27-1
28-1
29-1
30-1
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Part 7: Connectivity and Expansion
Chapter 31 Universal Asynchronous Receiver/Transmitters (UART) Modules . . . . . . . . . . . . . . . . .
Chapter 32 Universal Serial Bus On-The-Go (USB OTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 33 PCMCIA/CF Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 34 Keypad Port (KPP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 35 Fast InfraRed Interface (FIRI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 36 1-Wire Interface (1-Wire®) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31-1
32-1
33-1
34-1
35-1
36-1
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Contents – Full
Part 1: Device Introduction
Chapter 1
Introduction
1.1
i.MX21 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2
i.MX21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2.1
ARM926EJ-S Core Complex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2.2
System Control and Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2.2.1
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2.2.2
Real-Time Clock/Sampling Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.2.3
Three General-Purpose 32-Bit Counters/Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.2.4
Pulse-Width Modulator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.2.5
General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.2.6
Endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.3
Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.2.3.1
SDRAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.2.3.2
Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.2.3.3
NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.2.3.4
External Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.2.4
Bus Master Interface (BMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.2.5
Inter-Chip Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.2.5.1
Inter-IC (I2C) Bus Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.2.5.2
Three Configurable Serial Peripheral Interfaces for High Speed Data Transfer . . . . . . 1-7
1.2.5.3
Two Synchronous Serial Interfaces with Inter-IC Sound (I2S) and AC97 Host Controller
Module (SSI/I2S/AC97) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.2.6
Peripheral Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.2.6.1
CMOS Sensor Interface (CSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.2.7
Display and Video Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.2.7.1
LCD Controller (LCDC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.2.7.2
Smart LCD Controller (SLCDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.2.8
enhanced Multimedia Accelerator (eMMA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.2.8.1
Video Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.2.8.2
Video Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.2.8.3
Image Pre-processor (PrP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.2.8.4
Postprocessor (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.2.8.5
Two Multimedia Card and Secure Digital Host Controller Modules . . . . . . . . . . . . . . 1-12
1.2.8.6
Digital Audio Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.2.9
Connectivity and Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.2.9.1
Four Universal Asynchronous Receiver/Transmitters
(UART1, UART2, UART3, and UART4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.2.9.2
USB On-The-Go (USB OTG) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.2.10
Debug Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.2.10.1
PCMCIA/CF Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.2.10.2
Keypad Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
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1.2.10.3
1.2.10.4
1.2.11
1.2.12
Fast Infra-Red Interface (FIRI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-Wire‚ Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electronic and Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-16
1-17
1-17
1-17
Chapter 2
Signal Descriptions and Pin Assignments
2.1
2.2
2.3
2.4
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
I/O Power Supply and Signal Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Chapter 3
Memory Map
3.1
3.1.1
3.2
Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Detailed Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Part 2: Core Technology
Chapter 4
ARM9 Platform
4.1
4.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Chapter 5
ARM926EJ-S Interrupt Controller (AITC)
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Interrupt Control Register (INTCNTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Normal Interrupt Mask Register (NIMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Interrupt Enable Number Register (INTENNUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Interrupt Disable Number Register (INTDISNUM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Interrupt Enable Register High (INTENABLEH)
and Low (INTENABLEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.1.6
Interrupt Type Register High (INTTYPEH) and Low (INTTYPEL). . . . . . . . . . . . . . . . . 5-11
5.1.7
Normal Interrupt Priority Level Registers (NIPRIORITYn) . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.1.8
Normal Interrupt Vector and Status Register (NIVECSR). . . . . . . . . . . . . . . . . . . . . . . . . 5-20
5.1.9
Fast Interrupt Vector and Status Register (FIVECSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
5.1.10
Interrupt Source Register High (INTSRCH) and Low (INTSRCL). . . . . . . . . . . . . . . . . . 5-22
5.1.10.1
Interrupt Assignments High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
5.1.10.2
Interrupt Assignments Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
5.1.11
Interrupt Force Register High (INTFRCH) and Low (INTFRCL). . . . . . . . . . . . . . . . . . . 5-26
5.1.12
Normal Interrupt Pending Register High (NIPNDH) and Low (NIPNDL) . . . . . . . . . . . . 5-27
5.1.13
Fast Interrupt Pending Register High (FIPNDH) and Low (FIPNDL) . . . . . . . . . . . . . . . 5-28
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5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
ARM926EJ-S Interrupt Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ARM926EJ-S Prioritization of Exception Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AITC Prioritization of Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assigning and Enabling Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enabling Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Controlling Bus Arbitration With AITC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Interrupt Entry Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Writing Reentrant Normal Interrupt Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-29
5-29
5-29
5-29
5-29
5-30
5-30
5-31
Chapter 6
Phase-Locked Loop (PLL), Clock and Reset Controller
6.1
Clock Controller Architecture Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1.1
OSC32K – 32/32.768 kHz Reference Oscillator (Analog). . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.1.2
OSC26M – 26 MHz Reference Oscillator (Analog) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.1.2.1
OSC26M Start-Up Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.1.3
High Frequency Clock Source and Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.1.3.1
FPM – Frequency Premultiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.1.4
Output Frequency Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.1.5
DPLL Phase and Frequency Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.2
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.2.1
PLL Operation at Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.2.2
PLL Operation at Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.2.3
i.MX21 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.2.3.1
Doze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.2.3.2
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.2.4
SDRAM Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.2.5
Power Management in the PLL Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.3
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.3.1
Clock Source Control Register (CSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
6.3.2
MPLL Control Register 0 (MPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.3.2.1
MPLL Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.3.3
Programming the Serial Peripheral PLL (SPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
6.3.4
SPLL Control Register 0 (SPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6.3.5
SPLL Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6.3.6
Oscillator 26M Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.3.6.1
Adjusting the 26 MHz Oscillator Trim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.3.7
Peripheral Clock Divider Register 0 (PCDR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
6.3.8
Peripheral Clock Divider Register 1 (PCDR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
6.3.9
Peripheral Clock Control Register 0 (PCCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.3.10
Peripheral Clock Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
6.3.11
Clock Control Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
6.3.12
Wakeup Guard Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
6.4
Functional Description of the Reset Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
6.4.1
Global Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
6.4.2
ARM9 Platform Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
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Chapter 7
AHB-Lite IP Interface (AIPI) Module
7.1
7.1.1
7.1.2
7.2
7.3
7.3.1
7.3.2
7.3.3
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Size Registers[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AIPI1 and AIPI2 Peripheral Widths and PSR Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Aborted Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2
7-3
7-4
7-4
7-6
7-6
7-6
7-6
Part 3: System Control
Chapter 8
System Control
8.1
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1
Silicon ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.2
Function Multiplexing Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.1.3
Global Peripheral Control Register (GPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.1.4
Well Bias System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.1.5
Well Bias Control Register (WBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.1.6
Driving Strength Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.1.7
Driving Strength Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.1.8
Driving Strength Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
8.1.9
Driving Strength Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
8.1.10
Driving Strength Control Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
8.1.11
Driving Strength Control Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
8.1.12
Driving Strength Control Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
8.1.13
Driving Strength Control Register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
8.1.14
Driving Strength Control Register 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
8.1.15
Driving Strength Control Register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
8.1.16
Driving Strength Control Register 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
8.1.17
Driving Strength Control Register 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
8.1.18
Priority Control and Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
8.2
System Boot Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
Chapter 9
Internal ROM, System Boot Manager
9.1
Bootstrap Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.1
UART/USB Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.2
Enter Bootstrap Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.3
Bootstrap Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.3.1
Bootstrap Protocol and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.3.1.1
Synchronization Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-2
9-2
9-2
9-3
9-3
9-4
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9.1.3.1.2
9.1.3.1.3
9.1.3.1.4
Write Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Download Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Bootstrap End Indication Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Chapter 10
Multi-layer AHB Crossbar Switch (MAX)
10.1 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2 General Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.3.1
Master Priority Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.3.2
Alternate Master Priority Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.3.3
Slave General Purpose Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.3.4
Alternate Slave General Purpose Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.3.5
Master General Purpose Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.4 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10.4.1
Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10.4.2
Arbitration During Undefined Length Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.3
Fixed Priority Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.4
Round-Robin Priority Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.4.5
Priority Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.4.5.1
Context Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
Chapter 11
JTAG Controller
11.1
11.2
11.3
11.4
11.5
11.5.1
11.5.2
11.6
11.6.1
11.6.2
11.6.3
11.6.4
11.7
11.8
11.8.1
11.8.2
11.8.3
11.9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Controller Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ARM926 Platform JTAG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
i.MX21 JTAG Controller MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ENABLE_Extra Debug Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACCESS_GENERIC_MBIST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BYPASS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extra Debug Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ID Check TMS Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write to ExtraDebug Register TMS Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS Sequence to Read ExtraDebug Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
i.MX21 JTAG Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-1
11-1
11-2
11-3
11-3
11-3
11-3
11-4
11-4
11-5
11-5
11-5
11-5
11-5
11-5
11-6
11-7
11-8
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Chapter 12
Watchdog Timer Module (WDOG)
12.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.1
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.2
Watchdog During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.3
Watchdog After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.3.1
Initial Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.3.2
Countdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.3.3
Reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.3.4
Time-Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.4
Low-Power and DEBUG Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.4.1
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.4.2
DEBUG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 Watchdog Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.1
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.2
WDOG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.1
Watchdog Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.2
Watchdog Service Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.3
Watchdog Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-1
12-1
12-1
12-1
12-2
12-2
12-2
12-2
12-2
12-2
12-3
12-3
12-3
12-4
12-4
12-4
12-5
12-5
Chapter 13
Real-Time Clock (RTC)
13.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.2 Prescaler and Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.2.1
Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.2.2
Sampling Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.2.3
Minute Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3.1
RTC Days Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3.2
RTC Hours and Minutes Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.3.3
RTC Seconds Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.3.4
RTC Day Alarm Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.3.5
RTC Hours and Minutes Alarm Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13.3.6
RTC Seconds Alarm Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.3.7
RTC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.3.8
RTC Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
13.3.9
RTC Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.3.10 Stopwatch Minutes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
Chapter 14
General-Purpose Timers (GPT)
14.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.1.1
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
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14.1.2
Operation During Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.1.3
Capture Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.1.4
Compare Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.1.5
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.2.1
GPT Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
14.2.2
GPT Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
14.2.3
GPT Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
14.2.4
GPT Capture Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.2.5
GPT Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.2.6
GPT Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Chapter 15
General-Purpose I/O (GPIO)
15.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.2 GPIO Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.3 External Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.5 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.5.1
Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.5.2
Output Configuration Register 1 (OCR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.5.3
Output Configuration Register 2 (OCR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.5.4
Input Configuration Register A1 (ICONFA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.5.5
Input Configuration Register A2 (ICONFA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
15.5.6
Input Configuration Register B1 (ICONFB1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
15.5.7
Input Configuration Register B2 (ICONFB2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
15.5.8
Data Register (DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
15.5.9
GPIO IN USE Register (GIUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
15.5.9.1
GPIO IN USE Register A (PTA_GIUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
15.5.9.2
GPIO IN USE Register B (PTB_GIUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
15.5.9.3
GPIO IN USE Register C (PTC_GIUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17
15.5.9.4
GPIO IN USE Register D (PTD_GIUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17
15.5.9.5
GPIO IN USE Register E (PTE_GIUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18
15.5.9.6
GPIO IN USE Register F (PTF_GIUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18
15.5.10 Sample Status Register (SSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19
15.5.11 Interrupt Configuration Register 1 (ICR 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20
15.5.11.1
Interrupt Configuration Register 2 (ICR 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
15.5.12 Interrupt Mask Register (IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22
15.5.13 Interrupt Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23
15.5.14
General Purpose Register (GPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24
15.5.15
Software Reset Register (SWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25
15.5.16
Pull-Up Enable Register (PUEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-26
15.5.17 Port Interrupt Mask Register (PMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-27
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Chapter 16
Pulse-Width Modulator (PWM)
16.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.1.1
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.1.2
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.1.3
Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.2.1
PWM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.2.2
PWM Sample Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.2.3
PWM Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.2.4
PWM Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-1
16-1
16-2
16-2
16-2
16-3
16-5
16-6
16-7
Part 4: Memory Interfaces
Chapter 17
SDRAM Memory Controller
17.1 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.1.1
SDRAM Command Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.1.2
Page and Bank Address Comparators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.1.3
Row/Column Address Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.1.4
Data Aligner/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.1.5
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.1.6
Refresh Request Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.1.7
Powerdown Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.1.8
DMA Operation with the SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.1.9
External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.1.10 SDCLK—SDRAM Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.1.11 SDCKE0, SDCKE1—SDRAM Clock Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.1.12
CSD0, CSD1—SDRAM Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.1.13 DQ [31:0]—Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.1.14 MA [11:0]—Multiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.1.15 SDBA [4:0], SDIBA [3:0]—Non-Multiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.1.16 DQM3, DQM2, DQM1, DQM0—Data Qualifier Mask . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.1.17 SDWE—Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.1.18 RAS—Row Address Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.1.19 CAS—Column Address Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.1.20 Pin Configuration for SDRAMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
17.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
17.2.1
SDRAM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.2.2
SDRAM Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15
17.2.3
Miscellaneous Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
17.3 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
17.3.1
SDRAM Command Encodings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
17.3.2
Normal Read/Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
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17.3.3
Precharge Command Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.3.4
Auto-Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.3.5
Set Mode Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.3.6
Manual Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4 General Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.1
Address Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.1.1
Multiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.1.2
Non-Multiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.1.3
Bank Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.2
Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.3
Self-Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.3.1
Self-Refresh During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.3.2
Self-Refresh During Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.3.3
Powerdown Operation During Reset and Low-Power Modes . . . . . . . . . . . . . . . . . .
17.4.4
Power-Down Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.4.1
Precharge Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.4.2
Active Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.4.3
Refresh During Precharge Power-Down/Active Power-Down . . . . . . . . . . . . . . . . .
17.5 SDRAM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.1
SDRAM Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.2
Configuring Controller for SDRAM Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.2.1
CAS Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.2.2
Row Precharge Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.2.3
Row-to-Column Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.2.4
Row Cycle Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.2.5
Refresh Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.2.6
Memory Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.2.7
Address Muxing Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.3
SDRAM Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.4
Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.5
SDRAM Memory Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17-33
17-35
17-36
17-38
17-39
17-40
17-40
17-41
17-41
17-42
17-44
17-44
17-44
17-45
17-47
17-48
17-48
17-48
17-51
17-51
17-52
17-52
17-52
17-52
17-53
17-53
17-53
17-62
17-79
17-81
17-86
Chapter 18
Direct Memory Access Controller (DMAC)
18.1 DMA Request and Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.1.1
DMA Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.1.2
External DMA Request and Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.2 DMA Request Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.3.1
General Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10
18.3.1.1
DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10
18.3.1.2
DMA Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11
18.3.1.3
DMA Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12
18.3.1.4
DMA Burst Time-Out Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13
18.3.1.5
DMA Request Time-Out Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14
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18.3.1.6
DMA Transfer Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.1.7
DMA Buffer Overflow Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.1.8
DMA Burst Time-Out Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.2
2D Memory Registers (A and B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.2.1
W-Size Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.2.2
X-Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.2.3
Y-Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.3
Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.3.1
Channel Source Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.3.2
Destination Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.3.3
Channel Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.3.4
Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.3.5
Channel Request Source Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.3.6
Channel Burst Length Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.3.7
Channel Request Time-Out Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.3.8
Channel Bus Utilization Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.3.9
Channel Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.4 DMA Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.5 Special Cases of Burst Length and Access Size Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.5.1
Memory Increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.5.2
Memory Decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.6 Special Cases When CCNR and CNTR Values Differ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.6.1
CNTR Not A Multiple of Destination Access Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.6.2
BL is Not a Multiple of Destination Access Size, CNTR Is. . . . . . . . . . . . . . . . . . . . . . .
18.7 Application Note. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.8 DMA Burst Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.9 Glossary of Terms Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18-15
18-16
18-17
18-17
18-19
18-20
18-21
18-21
18-22
18-23
18-24
18-26
18-29
18-30
18-31
18-33
18-34
18-35
18-36
18-36
18-36
18-37
18-37
18-37
18-38
18-38
18-39
Chapter 19
NAND Flash Memory Controller
19.1 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.1.1
BOOTLOADER on Cold Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.1.2
NAND Flash Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.1.3
ECC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.1.4
Address Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.1.5
RAM Buffer (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.1.6
Register (Command/Address/Status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.1.7
Read and Write Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.1.8
Data Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.1.9
Host Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.1.10 AHB Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.2 External . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.2.1
Flash Chip Enable (NFCE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.2.2
Flash Read Enable (NFRE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.2.3
Flash Write Enable (NFWE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19-2
19-3
19-3
19-3
19-4
19-4
19-4
19-4
19-5
19-5
19-5
19-5
19-5
19-5
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19.2.4
Flash Command Latch Enable (NFCLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.2.5
Flash Address Latch Enable (NFALE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.2.6
Flash Write Protect (NFWP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.2.7
NFRB—Flash Ready/Busy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.2.8
WARM Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.2.9
Pin Configuration for the NAND Flash Controller (NFC) . . . . . . . . . . . . . . . . . . . . . . . . . 19-7
19.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7
19.3.1
Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7
19.3.2
Spare Area Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8
19.3.3
Internal SRAM Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10
19.3.4
NAND Flash Block Address for Lock Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10
19.3.5
Buffer Number for Page Data Transfer To/From Flash Memory. . . . . . . . . . . . . . . . . . . 19-11
19.3.6
NAND Flash Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11
19.3.7
NAND Flash Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12
19.3.8
NFC Internal Buffer Lock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12
19.3.9
Controller Status/Result of Flash Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13
19.3.10 ECC Error Position of Main Area Data Error (8-bit NAND Flash) . . . . . . . . . . . . . . . . . 19-13
19.3.11 ECC Error Position of Main Area Data Error
(16-Bit NAND Flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14
19.3.12 ECC Error Position of Spare Area Data Error
(8-bit NAND Flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14
19.3.13 ECC Error Position of Spare Area Data Error
(16-bit NAND Flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15
19.3.14 Nand Flash Write Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15
19.3.15 Start Address for Write Protection Unlock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16
19.3.16 End Address for Write Protection Unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16
19.3.17 NAND Flash Write Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16
19.3.18 NAND Flash Operation Configuration (Configuration 1) . . . . . . . . . . . . . . . . . . . . . . . . 19-17
19.3.19 NAND Flash Operation Configuration (Configuration 2) . . . . . . . . . . . . . . . . . . . . . . . . 19-18
19.4 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19
19.5 General Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19
19.5.1
Basic Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20
19.5.1.1
Preset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20
19.5.1.2
NAND Flash Command Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21
19.5.1.3
NAND Flash Address Input Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22
19.5.1.4
NAND Flash Data Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23
19.5.1.5
NAND Flash Data Output Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24
19.5.2
Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24
19.5.2.1
NAND Flash Read ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25
19.5.2.2
NAND Flash Read Status Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26
19.5.2.3
NAND Flash Read Data Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27
19.5.2.4
Program NAND Flash Data Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28
19.5.2.5
Erase NAND Flash Data Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-29
19.5.2.6
Hot Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-30
19.5.3
ECC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-30
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19.5.3.1
ECC Operation Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.5.3.2
ECC Bypass Operation Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.5.3.3
ECC Operation Guidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.5.4
Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.5.4.1
Write Protection for RAM Buffer (LSB 1KB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.5.4.2
Write Protection for NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.5.4.2.1
Write Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.5.4.2.2
Write Protection Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.5.4.2.3
Write Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.5.4.3
Lock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.5.4.4
Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.5.4.5
Lock-Tight Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.6 AHB Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19-30
19-31
19-31
19-31
19-31
19-32
19-32
19-32
19-33
19-33
19-34
19-34
19-35
Chapter 20
External Interface Module (EIM)
20.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.2 EIM I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
20.2.1
Chip Select Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
20.2.2
Burst Mode Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
20.3 Pin Configuration for EIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
20.4 Typical EIM System Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
20.5 EIM Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
20.5.1
Configurable Bus Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
20.5.2
Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
20.5.3
Burst Clock Divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
20.5.4
Burst Clock Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9
20.5.5
Page Mode Emulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9
20.5.6
PSRAM mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9
20.5.7
Mixed Burst Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9
20.5.8
DTACK Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10
20.5.9
Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11
20.6 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11
20.6.1
Chip Select 0 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12
20.6.1.1
Chip Select 0 Upper Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12
20.6.1.2
Chip Select 0 Lower Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13
20.6.2
Chip Select 1 through Chip Select 5 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14
20.6.2.1
Chip Select 1 through Chip Select 5 Upper Control Registers. . . . . . . . . . . . . . . . . . 20-14
20.6.2.2
Chip Select 1 through Chip Select 5 Lower Control Registers . . . . . . . . . . . . . . . . . 20-15
20.6.3
EIM Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-23
Chapter 21
Bus Master Interface (BMI)
21.1
BMI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
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21.2 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
21.3 Pin Configuration for BMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
21.4 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.4.1
BMI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
21.4.2
BMI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.4.3
BMI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
21.4.4
BMI RxFIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
21.4.5
BMI TxFIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10
Part 5: InterChip Connectivity
Chapter 22
I2C Module
22.1
22.2
22.2.1
22.2.2
22.2.3
22.2.4
22.3
22.4
22.4.1
22.5
22.5.1
22.5.2
22.5.3
22.5.4
22.5.5
22.6
22.6.1
22.6.2
22.6.3
22.6.4
22.6.5
22.6.6
22.6.7
22.6.8
I2C System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
I2C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
Pin Configuration for I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
IP Bus Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
Generation of Transfer Error on IP Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
I2C Address Register (IADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
I2C Frequency Divider Register (IFDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
I2C Control Register (I2CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
I2C Status Register (I2SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9
I2C Data I/O Register (I2DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10
2
I C Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11
Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11
Generation of START. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11
Post-Transfer Software Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11
Generation of STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
Generation of Repeated START. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
Arbitration Lost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
Timing Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13
Chapter 23
Configurable Serial Peripheral Interface (CSPI)
23.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.1.1
Phase and Polarity Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.1.2
Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23-2
23-2
23-2
23-3
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23.2.1
23.2.2
23.2.3
23.2.4
23.2.5
23.2.6
23.2.7
23.2.8
Rx Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
Tx Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6
Interrupt Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9
CSPI Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12
CSPI Sample Period Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13
DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14
CSPI Soft Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-16
Chapter 24
Synchronous Serial Interface (SSI)
24.1 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
24.2 SSI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
24.3 SSI Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
24.3.1
SSI Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.3.2
SSI Clock and Frame Sync Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4
24.4 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
24.4.1
SSI Transmit Data Registers 0 and 1 (STX0/1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7
24.4.2
SSI Transmit FIFO 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
24.4.3
SSI Transmit Shift Register (TXSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
24.4.4
SSI Receive Data Registers 0 and 1 (SRX0/1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10
24.4.5
SSI Receive FIFO 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10
24.4.6
SSI Receive Shift Register (RXSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11
24.4.7
SSI Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
24.4.8
SSI Interrupt Status Register (SISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14
24.4.9
SSI Interrupt Enable Register (SIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19
24.4.9.1
Receive Interrupt Enable Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-20
24.4.9.2
Transmit Interrupt Enable Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-20
24.4.10 SSI Transmit Configuration Register (STCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-21
24.4.11 SSI Receive Configuration Register (SRCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23
24.4.12 SSI Transmit and Receive Clock Control Registers
(STCCR and SRCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24
24.4.12.1
Prescale Modulus Select Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26
24.4.13 SSI FIFO Control/Status Register (SFCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28
24.4.14 SSI Test Register (STR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-31
24.4.15 SSI Option Register (SOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-32
24.4.16 SSI AC97 Control Register (SACNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33
24.4.17
SSI AC97 Command Address Register (SACADD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-34
24.4.18 SSI AC97 Command Data Register (SACDAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-34
24.4.19 SSI AC97 Tag Register (SATAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-35
24.4.20 SSI Transmit Time Slot Mask Register (STMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-36
24.4.21
SSI Receive Time Slot Mask Register (SRMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-36
24.5 SSI Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-37
24.6 SSI Date and Control Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-37
24.7 SSI Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-41
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24.7.1
Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.1.1
Normal Mode Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.1.2
Normal Mode Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.2
Network Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.2.1
Network Mode Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.2.2
Network Mode Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.8 Gated Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.9 I2S Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.10 AC97 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.10.1 AC97 Fixed Mode Operation (SACNT[1]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.10.2 AC97 Variable Mode Operation (SACNT[1]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.11 External Frame and Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.12 SSI Reset and Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24-43
24-43
24-43
24-45
24-46
24-47
24-48
24-50
24-51
24-52
24-53
24-53
24-53
Part 6: Peripherals
Chapter 25
CMOS Sensor Interface (CSI)
25.1 CSI Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1
25.2 CSI Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2
25.2.1
Signals from CSI to eMMA Pre-Processor Block (PrP). . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.3 Principles of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.3.1
Gated Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
25.3.2
Non-Gated Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
25.3.3
CCIR656 Interlace Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
25.3.4
CCIR656 Progressive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6
25.3.5
Error Correction for CCIR656 Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7
25.4 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7
25.4.1
Start Of Frame Interrupt (SOF_INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7
25.4.2
End Of Frame Interrupt (EOF_INT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8
25.4.3
Change Of Field Interrupt (COF_INT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8
25.4.4
CCIR Error Interrupt (ECC_INT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8
25.4.5
Data Packing Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8
25.4.6
RX FIFO Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9
25.4.6.1
RGB565 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9
25.4.6.2
RGB888 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9
25.4.7
STAT FIFO Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10
25.5 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11
25.5.1
CSI Control Register 1 (CSICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12
25.5.2
CSI Control Register 2 (CSICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
25.5.3
CSI Control Register 3 (CSICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17
25.5.4
CSI Status Register (CSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18
25.5.5
CSI STATFIFO Register (CSISTATFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20
25.5.6
CSI RxFIFO Register (CSIRFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20
25.5.7
CSI RX Count Register (CSIRXCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21
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Chapter 26
Liquid Crystal Display Controller (LCDC)
26.1 LCDC Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
26.1.1
LCD Screen Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
26.1.2
Graphic Window on Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3
26.1.3
Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4
26.1.4
Display Data Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4
26.1.5
Black-and-White Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7
26.1.6
Gray-Scale Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7
26.1.7
Color Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8
26.1.8
Frame Rate Modulation Control (FRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-10
26.1.9
Panel Interface Signals and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-11
26.1.9.1
Pin Configuration for LCDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-11
26.1.9.2
Passive Matrix Panel Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12
26.1.9.3
Passive Panel Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13
26.1.10 8 bpp Mode Color STN Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-14
26.1.10.1
Active Matrix Panel Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-15
26.1.10.2
Active Panel Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-16
26.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-17
26.2.1
LCDC Screen Start Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-21
26.2.2
LCDC Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-22
26.2.3
LCDC Virtual Page Width Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-23
26.2.4
LCDC Panel Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-24
26.2.5
LCDC Horizontal Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-26
26.2.6
LCDC Vertical Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27
26.2.7
LCDC Panning Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-28
26.2.8
LCDC Cursor Position Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-29
26.2.9
LCDC Cursor Width Height and Blink Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-30
26.2.10 LCDC Color Cursor Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-31
26.2.11 LCDC Sharp Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-32
26.2.12 LCDC PWM Contrast Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-34
26.2.13 LCDC Refresh Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-35
26.2.14 LCDC DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-36
26.2.15 LCDC Interrupt Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-37
26.2.16 LCDC Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-38
26.2.17 LCDC Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-39
26.2.18
LCDC Graphic Window Start Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-41
26.2.19 LCDC Graphic Window Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-42
26.2.20
LCDC Graphic Window Virtual Page Width Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 26-43
26.2.21 LCDC Graphic Window Panning Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-44
26.2.22 LCDC Graphic Window Position Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-45
26.2.23 LCDC Graphic Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-46
26.2.24 LCDC Graphic Window DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-47
26.2.25 BGLUT and GWLUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-48
26.2.25.1
Four Bits Per Pixel Gray-Scale Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-48
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26.2.25.2
26.2.25.3
26.2.25.4
26.2.25.5
Four Bits Per Pixel Passive Matrix Color Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Eight Bits Per Pixel Passive Matrix Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Four Bits Per Pixel Active Matrix Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Eight Bits Per Pixel Active Matrix Color Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26-48
26-49
26-49
26-50
Chapter 27
Smart Liquid Crystal Display Controller (SLCDC)
27.1 SLCDC Module Pin List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2
27.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2
27.2.1
Word Size Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3
27.2.2
Image Endianess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3
27.2.3
Accessing the LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4
27.2.3.1
Automatic SLCDC Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4
27.2.3.1.1
Automatic Display Data Transfers (AUTOMODE[1:0]=10) . . . . . . . . . . . . . . . . . 27-4
27.2.3.1.2
Automatic Command Data Transfers (AUTOMODE[1:0]=00). . . . . . . . . . . . . . 27-15
27.2.3.1.3
Automatic Command Data Transfers (AUTOMODE[1:0]=01). . . . . . . . . . . . . . 27-16
27.2.3.2
Direct Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-16
27.2.4
Aborting SLCDC Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-16
27.2.5
Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-17
27.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-17
27.3.1
Data Buffer Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-18
27.3.2
Data Buffer Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-19
27.3.3
Command Buffer Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-20
27.3.4
Command Buffer Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-21
27.3.5
Command String Size Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-21
27.3.6
FIFO Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-22
27.3.7
LCD Controller Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-23
27.3.8
LCD Transfer Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-24
27.3.9
SLCDC Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-25
27.3.10 LCD Clock Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-28
27.3.11 LCD Write Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-29
27.4 LCD Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-29
27.4.1
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-29
27.4.2
Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-32
27.5 LCD Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-33
27.6 R-AHB Interface and SLCDC FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-33
Chapter 28
enhanced Multimedia Accelerator (eMMA)
28.1 eMMA Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.1.1
Pre-Processor (PrP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.1.2
Encoder and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.1.3
Post-Processor (PP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.2 Post-Processor (PP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-2
28-3
28-4
28-4
28-4
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28.2.1
Color Space Conversion (CSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6
28.2.2
Input Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8
28.2.3
Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-9
28.2.4
Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10
28.2.5
Relationship of Register Fields Related to the Input Frame . . . . . . . . . . . . . . . . . . . . . . . 28-10
28.2.6
Relationship of Register Fields Related to Output Frame . . . . . . . . . . . . . . . . . . . . . . . . 28-11
28.3 Post Processor (PP) Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-12
28.3.1
PP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-13
28.3.2
PP Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-14
28.3.3
PP Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-15
28.3.4
PP Source Y Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-15
28.3.5
PP Source Cb Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-16
28.3.6
PP Source Cr Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-16
28.3.7
PP Destination RGB Frame Start Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-17
28.3.8
PP Quantizer Start Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-17
28.3.9
PP Process Frame Parameter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-18
28.3.10 PP Source Frame Width Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-19
28.3.11 PP Destination Display Width Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-20
28.3.12 PP Destination Image Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-21
28.3.13
PP Destination Frame Format Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-22
28.3.14 PP Resize Table Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-23
28.3.15 PP CSC COEF 123 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-24
28.3.16 PP CSC COEF_4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-25
28.3.17 PP Resize Coefficient Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-26
28.4 Pre-Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-27
28.4.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-28
28.4.2
Input Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-28
28.4.2.1
Input Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-28
28.4.2.2
Resize Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-28
28.4.2.3
Output Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-29
28.4.2.4
Output Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-29
28.4.2.5
Output Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-29
28.4.3
Resize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-29
28.4.3.1
Bilinear Resize in PrP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-29
28.4.3.2
Averaging Resize in PrP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-30
28.4.3.3
Combined Bilinear and Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-31
28.4.3.4
Resize Output Image Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-31
28.4.3.5
Channel-1 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-31
28.4.3.6
Channel-2 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-32
28.4.4
Color Space Conversion (CSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-32
28.4.5
RGB to YUV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-32
28.4.5.1
YUV to RGB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-33
28.4.5.2
Clipping of RGB and YUV Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-33
28.4.6
Frame Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-33
28.4.7
LOOP Mode (LEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-34
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28.4.8
Channel-1 and Channel-2 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.4.9
Channel-2 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.4.10 Line Buffer Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.4.11 Relationship of Register Fields Related to the Input Frame . . . . . . . . . . . . . . . . . . . . . . .
28.4.12
Relationship of Register Fields Related to Channel-1 Output Frame . . . . . . . . . . . . . . .
28.4.13 CSI Frame Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.4.14 CSI-PrP Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5 Pre-Processor (PrP) Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.1
PrP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.2
PrP Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.3
PrP Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.4
PrP Source Y Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.5
PrP Source Cb Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.6
PrP Source Cr Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.7
PrP Destination RGB1 Frame Start Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.8
PrP Destination RGB2 Frame Start Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.9
PrP Destination Y Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.10 PrP Destination Cb Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.11 PrP Destination Cr Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.12 PrP Source Frame Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.13 PrP Destination Channel-1 Line Stride Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.14 PrP Source Pixel Format Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.15 PrP Channel-1 Pixel Format Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.16 PrP Destination Channel-1 Output Image Size Register . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17 PrP Destination Channel-2 Output Image Size Register . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17.1
PrP Source Line Stride Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17.2
PrP CSC Coefficient 012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17.3
PrP CSC Coefficient 345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17.4
PrP CSC Coefficient 678 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17.5
PrP Channel-1 Horizontal Resize Coefficient-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17.6
PrP Channel-1 Horizontal Resize Coefficient-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17.7
PrP Channel-1 Horizontal Resize Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17.8
PrP Channel-1 Vertical Resize Coefficient-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17.9
PrP Channel-1 Vertical Resize Coefficient-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17.10
PrP Channel-1 Vertical Resize Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17.11
PrP Channel-2 Horizontal Resize Coefficient-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17.12
PrP Channel-2 Horizontal Resize Coefficient-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17.13
PrP Channel-2 Horizontal Resize Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17.14
PrP Channel-2 Vertical Resize Coefficient-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17.15
PrP Channel-2 Vertical Resize Coefficient-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.17.16
PrP Channel-2 Vertical Resize Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-34
28-35
28-35
28-35
28-36
28-37
28-38
28-40
28-41
28-43
28-44
28-45
28-46
28-46
28-47
28-47
28-48
28-48
28-49
28-49
28-50
28-51
28-52
28-54
28-55
28-56
28-56
28-58
28-59
28-60
28-61
28-62
28-63
28-64
28-65
28-66
28-67
28-68
28-69
28-70
28-71
Chapter 29
MultimediaCard/Secure Digital Host Controller (MMC/SDHC)
29.1
Host Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
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29.2 Host Controller Signal I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
29.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
29.3.1
MMC/SD Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
29.3.2
MMC/SD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
29.3.3
MMC/SD Clock Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7
29.3.4
MMC/SD Command and Data Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9
29.3.5
MMC/SD Response Time Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10
29.3.6
MMC/SD Read Time Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11
29.3.7
MMC/SD Block Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-12
29.3.8
MMC/SD Number of Block Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13
29.3.9
MMC/SD Revision Number Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14
29.3.10
MMC/SD Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14
29.3.11 Commands and Arguments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-17
29.3.11.1
MMC/SD Command Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-18
29.3.11.2
MMC/SD Higher Argument Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-19
29.3.11.3
MMC/SD Lower Argument Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-19
29.3.12 MMC/SD Response FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-20
29.3.13 MMC/SD Buffer Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-21
29.4 Host Controller Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-22
29.4.1
DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-22
29.4.2
Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-23
29.4.3
Command and Data Interpreter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-26
29.4.4
System Clock Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-28
29.4.5
Command Response Timing on SDHC Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-30
29.4.6
Response Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-33
29.5 Functional Example on MMC/SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-36
29.5.1
Command Submit—Response Receive Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . 29-36
29.5.2
Card Identification Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-36
29.5.2.1
Card Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-37
29.5.2.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-37
29.5.2.3
Voltage Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-37
29.5.2.4
Card Registry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-39
29.5.3
Card Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-40
29.5.3.1
Block Access—Block Write and Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-40
29.5.3.2
Stream Access—Stream Write and Stream Read (MMC Only). . . . . . . . . . . . . . . . . 29-42
29.5.3.3
Erase—Group Erase and Sector Erase (MMC Only) . . . . . . . . . . . . . . . . . . . . . . . . . 29-44
29.5.3.4
Wide Bus Selection/Deselection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-45
29.5.4
Protection Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-45
29.5.4.1
Card Internal Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-45
29.5.4.2
Mechanical Write Protect Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-45
29.5.4.3
Password Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-46
29.5.5
Card Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-48
29.5.6
SD Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-50
29.5.7
SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-51
29.5.7.1
SDIO Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-51
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29.5.7.2
SDIO Suspend/Resume. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.5.7.3
SDIO Read Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.5.8
Application Specified Command Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.6 Commands for MMC/SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29-52
29-52
29-53
29-54
Chapter 30
Digital Audio Mux (AUDMUX)
30.1 Internal Network Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4
30.2 Tx/Rx Switch and External Network Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4
30.3 Frame Sync and Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5
30.4 Synchronous Mode (4-Wire Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6
30.5 Asynchronous Mode (6-Wire Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7
30.6 SSI to Peripheral Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7
30.7 SSI to SAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11
30.8 Peripheral Port to Peripheral Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11
30.9 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-14
30.9.1
Host Port Configuration Register (HPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-15
30.9.2
Peripheral Port Configuration Register (PPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-17
30.10 Peripheral Connectivity through AUDMUX Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 30-19
30.10.1 Generic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19
30.10.2 AUDMUX Configuration with SSI1 and SAP as Master. . . . . . . . . . . . . . . . . . . . . . . . . 30-20
30.10.3 Tx-Rx Switch Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-21
30.10.4 Internal/External Network Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-22
Part 7: Connectivity and Expansion
Chapter 31
Universal Asynchronous Receiver/Transmitters (UART) Modules
31.1 Module Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2
31.2 Pin Configuration for UART1, UART2, UART3, and UART4. . . . . . . . . . . . . . . . . . . . . . . . 31-2
31.3 General UART Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4
31.3.1
RTS—UART Request To Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5
31.3.2
RTS Edge Triggered Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5
31.3.3
CTS—Clear To Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6
31.3.4
Programmable CTS Deassertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6
31.3.5
TXD—UART Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6
31.3.6
RXD—UART Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6
31.4 Sub-Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7
31.4.1
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8
31.4.2
Transmitter FIFO Empty Interrupt Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8
31.4.3
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9
31.4.4
Idle Line Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-10
31.4.4.1
Idle Condition Detect Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-10
31.4.5
Ageing Character Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-11
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31.4.6
Receiver Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.4.7
Receiving a BREAK Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.4.8
Vote Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.4.9
Binary Rate Multiplier (BRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.4.10 Baud Rate Automatic Detection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.4.10.1
Baud Rate Automatic Detection Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.4.10.2
Baud Rate Automatic Detection Protocol Improved . . . . . . . . . . . . . . . . . . . . . . . . .
31.4.10.2.1
New Baudrate Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.4.10.2.2
New Autobaud Counter Stopped Bit and Interrupt . . . . . . . . . . . . . . . . . . . . . . .
31.4.11 Escape Sequence Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.5 Infrared Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.5.1
Generalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.5.2
Inverted Transmission and Reception Bits (INVT and INVR) . . . . . . . . . . . . . . . . . . . .
31.5.3
InfraRed Special Case (IRSC) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.5.4
IRDA Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.5.5
Conclusion about IRDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6.1
UART Receiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6.2
UART Transmitter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6.3
UART Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6.4
UART Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6.5
UART Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6.6
UART Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6.7
UART FIFO Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6.8
UART Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6.9
UART Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6.10 UART Escape Character Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6.11 UART Escape Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6.12 UART BRM Incremental Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6.13 UART BRM Modulator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6.14 UART Baud Rate Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6.15 One Millisecond Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.6.16 UART Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.7 UART Operation in Low-Power System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31-11
31-12
31-12
31-13
31-15
31-15
31-16
31-16
31-17
31-17
31-18
31-18
31-19
31-19
31-20
31-20
31-21
31-22
31-24
31-25
31-27
31-30
31-32
31-33
31-35
31-37
31-39
31-40
31-41
31-42
31-43
31-44
31-45
31-46
Chapter 32
Universal Serial Bus On-The-Go (USB OTG)
32.1 USB OTG Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.1.1
Host Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.1.2
Function Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.1.3
USB On-The-Go Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.2 USB OTG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.3 OTG-IP CORE Operational Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.3.1
Host Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.3.2
Function Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-1
32-2
32-2
32-2
32-2
32-3
32-3
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32.3.3
Software HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3
32.4 HNP and SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3
32.5 USB Host Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4
32.5.1
Endpoint Transfer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4
32.5.2
Data Buffer Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4
32.6 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5
32.6.1
Creating a Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5
32.6.2
Post Transfer Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5
32.6.3
Endpoint Descriptor Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5
32.6.4
NAK Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-6
32.6.5
STALL Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-6
32.6.6
USB Mux Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-7
32.7 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-8
32.7.1
Hardware Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9
32.7.2
USB OTG Module Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-11
32.7.3
USB OTG Module Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-12
32.7.4
USB OTG Module Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-13
32.7.5
USB OTG Module Reset Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-14
32.7.6
Frame Interval Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-15
32.7.7
Frame Remaining Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-16
32.7.8
USB OTG HNP Control Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-17
32.7.9
HNP Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-19
32.7.10 HNP Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-20
32.7.11 USB Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-21
32.7.12 Host Endpoint Transfer Descriptor WORD0 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-23
32.7.12.1
Control/Bulk Transfer Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-25
32.8 Interrupt Transfer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-27
32.8.1
Interrupt Transfer Descriptor DWORD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-28
32.8.2
Interrupt Transfer Descriptor DWORD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-29
32.9 Isochronous Transfer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-29
32.10 Host Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-31
32.10.1 Effect of Resets on Host Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-32
32.10.2 Host Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-33
32.10.3 System Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-34
32.10.4
System Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-35
32.10.5 X Buffer Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-36
32.10.6 Y Buffer Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-37
32.10.7 XY Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-38
32.10.8 X Filled Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-39
32.10.9 Y Filled Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-40
32.10.10 ETD Enable Set Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-41
32.10.11 ETD Enable Clear Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-42
32.10.12 Immediate Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-43
32.10.13 ETD Done Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-44
32.10.14 ETD Done Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-45
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32.10.15 Frame Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.10.16 Low Speed Threshold Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.10.17 Root Hub Descriptor A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.10.18 Root Hub Descriptor B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.10.19 Root Hub Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.10.20 Port Status 1–3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.11 USB Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.11.1 OTG-IPFC Operation: Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.11.2 Transfer Anticipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.11.3 Transfer Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.11.4 Function Endpoint Type Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.11.5 Control/Bulk/Interrupt Endpoint Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.11.5.1
Isochronous Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.11.6 Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12 Effect of Different Resets on Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12.1 Function Command Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12.2 Device Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12.3 System Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12.4 System Interrupt Enables Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12.5 X Buffer Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12.6 Y Buffer Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12.7 XY Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12.8 X Filled Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12.9 Y Filled Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12.10 Endpoint Enables Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12.11 Endpoint Ready Set Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12.12 Immediate Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12.13 Endpoint Done Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12.14 Endpoint Done Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12.15 Endpoint Toggle Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.12.16 Frame Number and Endpoint Ready Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.13 AHB/DMA IP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.14 AHB HCLK Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.14.1 DMA Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.14.2 DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.14.3 DMA Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.14.4 DMA Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.14.5 DMA Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.14.6
ETD DMA Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.14.7 EP DMA Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.14.8 ETD DMA Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.14.9 EP DMA Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.14.10 ETD DMA Enable X Trigger Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.14.11 EP DMA Enable X Trigger Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.14.12 ETD DMA Enable XY Trigger Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-46
32-47
32-48
32-49
32-50
32-51
32-53
32-54
32-54
32-54
32-55
32-56
32-57
32-58
32-58
32-59
32-60
32-61
32-62
32-63
32-64
32-65
32-66
32-67
32-68
32-69
32-70
32-71
32-72
32-73
32-74
32-75
32-75
32-75
32-75
32-77
32-78
32-79
32-80
32-80
32-81
32-82
32-83
32-84
32-85
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32.14.13 EP DMA Enable XY Trigger Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-86
32.14.14 ETD DMA Burst4 Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-87
32.14.15 EP DMA Burst4 Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-88
32.14.16 Misc Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-89
32.14.17 ETD DMA Channel Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-90
32.14.18 EP DMA Channel Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-91
32.14.19 ETD<n>System Memory Start Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-92
32.14.20 EP<n>System Memory Start Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-93
32.14.21 ETD<n>DMA Buffer Xfer Ptr Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-94
32.14.22 EP<n>DMA Buffer Xfer Ptr Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-95
32.15 OTG-I2C Transceiver Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-95
32.15.1 Interrupt Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-96
32.15.2 Software Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-96
32.15.3 Hardware Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-96
32.15.4 Accessing the OTG Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-97
32.15.5 Product and Vendor ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-97
32.15.6
OTG Transceiver Control Register
I2C-OTG Transceiver Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-97
32.15.7
OTG Transceiver Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-98
32.15.8 Interrupt Source and Latch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-100
32.15.9 Interrupt Mask True and False Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-102
32.15.10 OTG Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-103
32.15.11 Device Address and I2C Operations Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-104
32.15.12 I2C Interrupt and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-105
32.16 Wake-Up Events and Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-106
32.16.1 Software Requirements for Wake-Up Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-107
32.16.1.1
Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-107
32.16.1.2
Function Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-108
Chapter 33
PCMCIA/CF Interface
33.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1
33.1.1
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2
33.1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3
33.1.3
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3
33.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3
33.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6
33.3.1
PCMCIA Input Pins Register (PIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-7
33.3.2
PCMCIA Status Change Register (PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-8
33.3.3
PCMCIA Enable Register (PER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10
33.3.4
PCMCIA Base Registers 0–4 (PBR0–PBR4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-12
33.3.5
PCMCIA Option Registers 0–4 (POR0–POR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-13
33.3.6
PCMCIA Offset Registers 0–4 (POFR0–POFR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-17
33.3.7
PCMCIA General Control Register (PGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-18
33.3.8
PCMCIA General Status Register (PGSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-19
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33.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33.4.1
Windowing Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33.4.1.1
Window Overlapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33.4.2
WAIT Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33.4.2.1
Error Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33.4.3
Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33.4.4
Reset and Tri-state Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33.4.5
Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33.4.6
16-bit/8-bit Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33.4.7
Data and Control Signals Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33.4.8
True IDE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33.4.8.1
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33.4.8.2
Data Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33.4.9
Card Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33.5 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33-19
33-19
33-20
33-20
33-20
33-20
33-21
33-21
33-21
33-22
33-23
33-23
33-24
33-24
33-25
Chapter 34
Keypad Port (KPP)
34.1 KPP Peripheral Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2
34.1.1
Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2
34.1.2
Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3
34.1.3
Generation of Transfer Error Signal on IP bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3
34.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4
34.2.1
Keypad Control Register (KPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4
34.2.2
Keypad Status Register (KPSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5
34.2.3
Keypad Data Direction Register (KDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-6
34.2.4
Keypad Data Register (KPDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-7
34.3 Keypad Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8
34.3.1
Keypad Matrix Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8
34.3.2
Keypad Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8
34.3.3
Keypad Matrix Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8
34.3.4
Keypad Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8
34.3.5
Glitch Suppression on Keypad Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-9
34.3.6
Multiple Key Closures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-9
34.3.7
Typical Keypad Configuration and Scanning Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 34-10
Chapter 35
Fast InfraRed Interface (FIRI) Module
35.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35.3 IrDA Standards Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35.3.1
IrDA Medium InfraRed and Fast InfraRed Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35.3.1.1
MIR Packet Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35.3.1.2
FIR Packet Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35-2
35-2
35-3
35-3
35-4
35-4
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35.3.1.3
MIR CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-4
35.3.1.4
FIR CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-4
35.3.1.5
MIR Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5
35.3.1.6
FIR Modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5
35.3.2
Transmitter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5
35.3.2.1
MIR Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5
35.3.2.2
FIR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5
35.3.2.3
Serial Infrared Interaction Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-6
35.3.2.4
Software Packet Assembly Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-6
35.3.3
Receiver Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-6
35.3.3.1
MIR Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-6
35.3.3.2
FIR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-6
35.3.3.3
Software Packet Disassembly Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-7
35.3.4
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-7
35.4 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-7
35.5 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-7
35.5.1
FIRI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-8
35.5.2
FIRI Transmitter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-9
35.5.3
FIRI Transmitter Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-10
35.5.4
FIRI Receiver Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-11
35.5.5
FIRI Transmit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-13
35.5.6
FIRI Receive Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-14
35.6 Software Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-15
Chapter 36
1-Wire Interface (1-Wire®)
36.1
36.2
36.3
36.4
36.5
36.5.1
36.5.2
36.5.3
36.5.4
36.5.5
36.6
36.6.1
36.6.2
36.6.3
36.7
Peripheral Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Enable and AIPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Sequence with Reset Pulse Presence Pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write 1 and Read Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Time Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36-1
36-2
36-2
36-2
36-2
36-3
36-3
36-3
36-4
36-5
36-5
36-5
36-6
36-8
36-8
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About This Book
This reference manual describes the features and operation of the i.MX21 microprocessor, the seventh
generation of the DragonBall family of products. It provides the details of how to initialize, configure, and
program the i.MX21. The manual presumes basic knowledge of ARM926EJ-S™ architecture.
Audience
The i.MX21 reference manual is intended to provide a design engineer with the necessary data to
successfully integrate the i.MX21 into a wide variety of applications. It is assumed that the reader has a
good working knowledge of the ARM926EJ-S processor. For programming information about the
ARM926EJ-S processor, see the documents listed in the Suggested Reading section of this preface.
Organization
The i.MX21 reference manual is organized into 8 parts, consisting of 37 chapters that cover the operation
and programming of the i.MX21 device. Summaries of the chapters follow.
Part 1 Device Introduction
Chapter 1, “Introduction,”
This chapter contains an high-level summary of the i.MX21 device and includes device
feature list, overview of system modules, and system block diagrams.
Chapter 2, “Signal Descriptions and Pin Assignments,”
This chapter contains listings of the i.MX21 input and output signals, organized into
functional groups.
Chapter 3, “Memory Map,”
The Memory Map chapter provides a complete listing of all of the register, internal and
external module memory assignments.
Part 2 Core Technology
Chapter 4, “ARM9 Platform,”
A brief summary of the ARM9™ platform and its operational features is covered in this
chapter.
Chapter 5, “ARM926EJ-S Interrupt Controller (AITC),”
This chapter describes the operation of the 32-bit peripheral which collects interrupt
requests from up to 64 sources and provides an interface to the ARM926EJ-S core.
Chapter 6, “Phase-Locked Loop (PLL), Clock and Reset Controller,”
This chapter provides detailed information about the operation and programming of the
clock generation module as well as the recommended circuit schematics for external
clock circuits. It also describes and provides programming information about the
operation of the power control module and the system power states.
Chapter 7, “AHB-Lite IP Interface (AIPI) Module,”
This chapter provides an overview of the two AHB-Lite to IP bus interface (AIPI)
modules. The AIPIAHB-Lite IP interface module (AIPI Ver1.0) acts as an interface
between the ARM® advanced high-performance bus “lite” (AHB-Lite) and lower
bandwidth peripherals.
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Part 3 System Control
Chapter 8, “System Control,”
This chapter describes the operation of and programming models for the system multiplex
control, peripheral control, ID register, and I/O drive control registers.
Chapter 9, “Internal ROM, System Boot Manager,”
This chapter describes the system boot up sequence of the i.MX21 microprocessor. The
operation of bootstrap models is described in detail. This chapter also provides the
programming information necessary to allow a system to initialize a target system and
download a program or data to the target system’s RAM using the UART controller.
Chapter 10, “Multi-layer AHB Crossbar Switch (MAX),”
This chapter provides an overview of the generic MAX (Multi-Layer AHB Crossbar
Switch) which allows concurrent support of up to 8 simultaneous connections between 6
master ports and 4 slave ports.
Chapter 11, “JTAG Controller,”
The operation and configuration of the JTAG controller module is described in this
chapter. The JTAG controller supports debug access to ARM926 core, i.MX21 BIST test
(excluding ARM926 platform BIST, Boot ROM and VectorRAM bist) and tristate enable
of the I/O pads.
Chapter 12, “Watchdog Timer Module (WDOG),”
The operation of the watchdog timer module is described in this chapter. It includes
information of how the watchdog timer protects against system failures by providing a
method of escaping from unexpected events or programming errors.
Chapter 13, “Real-Time Clock (RTC),”
This chapter describes the operation of the real-time clock module, which is composed of
a prescaler, time-of-day (TOD) clock, TOD alarm, programmable real-time interrupt,
watchdog timer, and minute stopwatch as well as control registers and bus interface
hardware.
Chapter 14, “General-Purpose Timers (GPT),”
This chapter describes the two 16-bit timers that can be used as both watchdogs and
alarms.
Chapter 15, “General-Purpose I/O (GPIO),” This chapter discusses all GPIO lines found in the i.MX21. Because
each pin is individually configurable, a detailed description of the operation is provided.
Chapter 16, “Pulse-Width Modulator (PWM),”
This chapter describes the operation and configuration of the pulse-width modulator.
Programming information is also provided.
Part 4 Memory Interfaces
Chapter 17, “SDRAM Memory Controller,”
The operation and programming of the SDRAM controller is described in this chapter.
This module provides a glueless interface to 8-bit or 16-bit DRAM supporting Fast Page
Mode, and synchronous DRAM.
Chapter 18, “Direct Memory Access Controller (DMAC),”
This chapter describes the operation of the direct memory access controller contained in
the i.MX21. The DMA controller provides memory channels and I/O channels to support
a wide variety of DMA operations.
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Chapter 19, “NAND Flash Memory Controller,”
This chapter describes the NAND Flash Controller that allows standard NAND Flash
chips to interface with AMBA™ AHB of the i.MX21.
Chapter 20, “External Interface Module (EIM),”
This chapter describes the external interface module and defines how the module handles
the interface to devices external to the i.MX21, including generation of chip-selects for
external peripherals and memory.
Chapter 21, “Bus Master Interface (BMI),”
This chapter describes the unique interface requirement for Bus master interface module.
This BMI module enables high speed connection between i.MX21 and the alternate bus
master devices in the system.
Part 5 InterChip Connectivity
Chapter 22, “I2C Module,”
This chapter describes the I2C module of the i.MX21 including I2C protocol, clock
synchronization, and the registers in the I2C programming mode.
Chapter 23, “Configurable Serial Peripheral Interface (CSPI),”
The programming and operation of the two identical serial peripheral interface modules
are described in this chapter.
Chapter 24, “Synchronous Serial Interface (SSI),”
This chapter presents the Synchronous Serial Interface and discusses the architecture,
programming model, operating modes, and initialization of the SSI.
Part 6 Peripherals
Chapter 25, “CMOS Sensor Interface (CSI),”
The CSI module is a logic interface that enables the i.MX21 to connect directly to external
CMOS image sensors. This chapter describes the CSI module, and discusses the
architecture, the programming model, and the software initialization sequence.
Chapter 26, “Liquid Crystal Display Controller (LCDC),”
This chapter describes the operation and programming of the liquid crystal display
controller, which provides display data for external LCD drivers or for an LCD panel.
Chapter 27, “Smart Liquid Crystal Display Controller (SLCDC),”
This chapter describes the operation and programming of the Smart Liquid Crystal
Display controller module which transfers data from the display memory buffer to the
external display device transparently with minimal software intervention.
Chapter 28, “enhanced Multimedia Accelerator (eMMA),”
This chapter describes the operation and configuration of the eMMA module which
performs computing extensive video processing functions. It consists of four blocks:
video encoding, video decoding, post-processing, and pre-processing.
Chapter 29, “MultimediaCard/Secure Digital Host Controller (MMC/SDHC),”
This chapter describes the Multimedia Card (MMC) host controller which controls
flash-based mass storage products. This chapter also describes the secure digital feature
of the MMC, its operation and programming information.
Chapter 30, “Digital Audio Mux (AUDMUX),”
This chapter describes the operation and configuration of the Digital Audio Mux
(AUDMUX) which provides a programmable interconnect fabric for voice, audio and
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synchronous data routing between i.MX21 SSI modules and external SSI, audio and voice
codecs.
Part 7 Connectivity and Expansion
Chapter 31, “Universal Asynchronous Receiver/Transmitters (UART) Modules,”
This chapter describes the capabilities and operation of the i.MX21’s UARTs. It also
discusses how to configure and program the UART modules.
Chapter 32, “Universal Serial Bus On-The-Go (USB OTG),”
This chapter describes the operation and configuration of the USB full speed OTG
module that provides USB On-The-Go (OTG) compliant functionality to i.MX21.
Chapter 33, “PCMCIA/CF Interface,”
This chapter describes the configuration and operation of the i.MX21 PCMCIA host
adapter module that provides all control logic for PCMCIA socket interface.
Chapter 34, “Keypad Port (KPP),”
This chapter describes the configuration and operation of the keypad port that supports up
to an 8 ¥ 8 keypad.
Chapter 35, “Fast InfraRed Interface (FIRI) Module,”
This chapter describes Fast InfraRed Interface module (FIRI), which is integrated in the
i.MX21. It is capable to establish standard speed half duplex links via LED and IR
detector. It supports 0.576 Mbit/sec, 1.152 Mbit/sec MIR physical layer protocol and
4Mbit/sec FIR physical layer protocol defined by IrDA, version 1.4. In addition, i.MX21
can support SIR protocol by the UART module.
Chapter 36, “1-Wire Interface (1-Wire®),”
This chapter describes the The 1-Wire® interface that provides the communication line to
a 1Kbit Add-Only Memory (DS2502). The 1-Wire module is a peripheral device to the
ARM926 core and communicates with it via the IP interface
Document Revision History
The following table provides revision history for this release. This history includes technical content
revisions only and not stylistic or grammatical changes.
Table 0-1. i.MX21 Reference Manual Revision History for Rev. 3
Revision Location
Revision
Throughout Book
Several minor technical corrections throughout Book, such as naming signals
consistently.
Throughout Book
Incorporated silicon M55B content and values from MC9328MX21RMAD1 i.MX21
Reference Manual Addendum into this i.MX21 Reference Manual.
Throughout Book
Removed Security Feature, chapters, references.
Several Locations
Noted AC97 fixed mode only supports 48 kHz sampling rate.
Chapter 2, “Signal Descriptions and
Pin Assignments.”
• Changes to External DMA and CSPI portions of Signal Description table.
• Changes to NVDD3 Multiplexing scheme portion of Signal Multiplexing table.
Old Chapter 6, “ROM Patch Module” Removed the ARM926EJ-S ROM Patch Module chapter and all references.
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Table 0-1. i.MX21 Reference Manual Revision History for Rev. 3
Revision Location
Revision
Chapter 6, “Phase-Locked Loop
(PLL), Clock and Reset Controller.”
Changes to recommended settings for frequency stability:
32.768 kHz, 240 target frequency, PD from 1 to 0, and
26 MHz, 240 target frequency, all settings.
• Clarification of ipg_clk_xxx as PERCLK.
• Added statement regarding PERCLK to Table 6-1 PLL Clock Controller Signal
Descriptions for PERCLK1–4, and LDCCLK.
• Peripheral Clock Divider Register 0 (PCDR0)
Corrected bit 26 number and bit 21 type from r to rw.
• Peripheral Clock Divider Register 1 (PCDR1)
• Changed reset values of bits 11 and 1 from 1 to 0.
Chapter 8, “System Control.”
Replaced Silicon ID Register and register description table with silicon M55B values.
Chapter 9, “Internal ROM, System
Boot Manager.”
• Removed content from the iROM, System Boot Manager and Bootstrap chapters,
and renamed from System Boot to Internal ROM, System Boot Manager and
removed previous chapters 10 and 11. Reorganized new chapter 10.
• Extensive changes to all figures.
• Removal of HAB section and all references to HAB
Chapter 17, “SDRAM Memory Controller,” Section 17.2.1 on page -8
• Changed SDRAM Control Register description table to accurately reflect register
display from Reserved[3] to SRC [3:0].
• SDRAM Mode Register Description
Switched Burst Type (BT) bit A3 settings.
Chapter 19, “NAND Flash Memory
Controller.”
• Replaced first paragraph in Functional Overview to reflex limits of the Write
Protection Unlock registers.
• Removed reference that system boot from and 8-bit device with 2 Kbyte page size is
not supported. M55B silicon supports this system boot operation.
Chapter 23, “Configurable Serial
Peripheral Interface (CSPI).”
• CSPI Control Register Description Table
Changed Bit Count description in reference to the ss rising edge.
Chapter 26, “Liquid Crystal Display
Controller (LCDC).”
• Supported Panel Characteristics table
Changed CSTN Panel Interface value from 12 to 8.
• Corrected Register description name:
Was: LCD Graphic Window DMA Control Register
To: LCD DMA Control Register
Chapter 27, “Smart Liquid Crystal
Display Controller (SLCDC).”
• SLCDC Serial Interface Timing Diagram and Table
Changed symbol identification to “T” nomenclature.
• SLCDC Parallel Interface Timing Diagram and Table
Changed symbol identification to “T” nomenclature.
Chapter 31, “Universal Asynchronous Receiver/Transmitters (UART)
Modules.”
• General UART Definitions, Figure 31-1
Changed CTS/RTS directions between the Computer UART and the i.MX21 UART.
Chapter 33, “PCMCIA/CF Interface.”
• Changed features list to include memory space up to 32 kbytes in size.
• PCMCIA Base Registers 0–4 (PBR0–PBR4)
Changed PBA field from 10–0 to 14–4.
• PCMCIA Offset Registers 0–4 (POR0–POR4)
Changed POFA field from 10–0 to 14–4.
• Replaced BSIZE value table
• Replaced BSIZE mask table
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Suggested Reading
The following documents are required for a complete description of the i.MX21 and are necessary to
design properly with the device. Especially for those not familiar with the ARM926EJ-S processor or
previous DragonBall products, the following documents will be helpful when used in conjunction with this
manual.
AMBA AHB specifications, (ARM Ltd.)
ARM926EJ-S Platform specifications (also named ARM926p Platform)
Hip7a KiloBit Single Port HP SRAM Compiler, MEMCTC (May 8, 2002)
Hip7A SAMI ROM Compiler, MEMCTC (November 16, 2001)
Hip7A KiloBit HD VIA ROM Compiler, MEMCTC (June 28, 2002)
ARM926EJ-S Platform Test Guide (ARM Ltd.)
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)
ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)
ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)
MC9328MX1 i.MX Integrated Portable System Processor Reference Manual (order number
MC9328MX1RM)
MC9328MXL i.MX Integrated Portable System Processor Reference Manual (order number
MC9328MXLRM)
MC9328MX21 Application Processor Data Sheet—266 MHz (order number MC9328MX21)
MC94MX21 Application Processor Data Sheet—333–350 MHz (order number MC94MX21)
The manuals may be found at the ARM Ltd. World Wide Web site at http://www.arm.com and Freescale
Semiconductors World Wide Web site at http://www.freescale.com/imx. These documents may be
downloaded directly from the World Wide Web site, or printed versions may be ordered. The World Wide
Web site may also have useful application notes.
Conventions
This reference manual uses the following conventions:
•
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
•
Logic level one is a voltage that corresponds to Boolean true (1) state.
•
Logic level zero is a voltage that corresponds to Boolean false (0) state.
•
To set a bit or bits means to establish logic level one.
•
To clear a bit or bits means to establish logic level zero.
•
A signal is an electronic construct whose state conveys or changes in state convey information.
•
A pin is an external physical connection. The same pin can be used to connect a number of signals.
•
Asserted means that a discrete signal is in active logic state.
— Active low signals change from logic level one to logic level zero.
— Active high signals change from logic level zero to logic level one.
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•
Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
•
LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and
high bytes or words are spelled out.
•
Numbers preceded by a percent sign (%) are binary. Numbers preceded by a 0x are hexadecimal.
Definitions, Acronyms, and Abbreviations
The following list defines acronyms and abbreviations used in this document.
ADC
analog-to-digital converter
AFE
analog front end
API
application programming interface
BCD
binary coded decimal
BER
bit error ratio
CGM
clock generation module
CMOS
complimentary metal-oxide semiconductor
CRC
cyclic redundancy check
CSIC
complex instruction set computer
DAC
digital-to-analog converter
DDR RAM
double data rate RAM
DMA
direct memory access
DRAM
dynamic random access memory
DSP
digital signal processor
FEC
forward error correction
FIFO
first in first out
FIRI
fast IR interface
GPIO
general purpose input/output
I/O
Input/Output
ICE
in-circuit emulation
IrDa
infrared data association
JTAG
joint test action group
MAP
mold array process
MAPBGA
mold array process ball grid array
MIPS
million instructions per second
MMC
multimedia card
PLL
phase locked loop
PWM
pulse-width modulator
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RTC
real-time clock
SD
secure digital
SDRAM
synchronous dynamic random access memory
SPI
serial peripheral interface
SRAM
static random access memory
TQFP
thin quad flat pack
UART
universal asynchronous receiver/transmitter
USB
universal serial bus
USB OTG
USB On-The-Go
XTAL
crystal
BE / LE
big endian / little endian
BIST
built in self-test
CCM
clock control module, also called “clkctl” module
LV
low voltage
LWB
late-write buffer
MCTL
memory controller
RAM
random access memory
ROM
read only memory
R-AHB bus
reduced advanced high-performance bus (AHB), related to ARM bus architecture
SRAM
static RAM
ARM
Advanced RISC Machines processor architecture
API
Application Programming Interface
Fabrication Path
Path within ROM Bootstrap for fabrication test execution
Flash Path
Path within ROM Bootstrap leading towards executing a Flash application.
GPCR
Global Peripheral Control Registry of the i.MX21.
HW
Hardware
iRAM
Processor-internal RAM
iROM
Processor-internal ROM
NANDFC
NAND Flash Controller
NAND Flash
A Flash ROM Technology
ROM Bootstrap
Internal boot code encompassing main boot flow as well as exception vectors,
USB/UART Bootloader blocks.
RAM Path
Path within ROM Bootstrap leading towards downloading and executing a RAM
application
SIDR
Silicon ID Register of the i.MX21
Sync Flash
A Flash ROM Technology
TBD
To Be Determined
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UART
Universal Asynchronous Receiver/Transmitter
USB
Universal Serial Bus
V-Sync Flash
A Flash ROM Technology
Word
32 bits
TYPE
Identifier that distinguishes a production or engineering device.
UID
Unique ID; a field in the processor and CSF identifying a device or group of devices
WTLS
Wireless Transport layer Security, a part of the Wireless Application Protocol
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Part 1
Device Introduction
Chapter 1, “Introduction,” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 1-1
Chapter 2, “Signal Descriptions and Pin Assignments,” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 2-1
Chapter 3, “Memory Map,” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 3-1
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Chapter 1
Introduction
The DragonBall family of microprocessors has demonstrated leadership in the portable handheld market.
Following on the success of the DragonBall MX (Media Extensions) series, the MC9328MX21 (i.MX21)
provides a leap in performance with an ARM926EJ-S™ microprocessor core that provides accelerated
Java support in addition to highly integrated system functions. DragonBall products specifically address
the needs of the smartphone and portable product markets with their intelligent integrated peripherals,
advanced processor core, and power management capabilities.
The i.MX21 processor features the advanced and power-efficient ARM926EJ-S core operating at speeds
up to 266 MHz (for higher frequency devices, refer to that device’s data sheet. See section "Suggested
Reading" in the Chapter , “About This Book.” ). On-chip modules such as an MPEG4 codec, LCD
controller, USB OTG, CMOS sensor interface, and an AC97 host controller offer designers a rich suite of
peripherals that can enhance any product seeking to provide a rich multimedia experience. For cost
sensitive applications, the NAND Flash controller allows the use of low cost Nand Flash devices to be used
as primary or secondary non-volatile storage. The on-chip ECC and parity checking circuitry of the Nand
Flash controller frees the CPU for other tasks. WLAN, Bluetooth and expansion options are provided
through PCMCIA/CF, USB, and MMC/SD host controllers.
The i.MX21 processor is packaged in a 289-pin plastic ball grid array (PBGA).
A summary of the main features of the i.MX21 processor includes:
• Seventh generation of industry-leading DragonBall family for the personal, portable product
market
• High level of on-chip integration
• Very low-power system design without compromised performance
• Optimized for multimedia applications
• Optimized for Bluetooth applications with high-speed interfaces to external Bluetooth solutions
• Dedicated graphics accelerator port
• Supports a wide variety of applications including the most popular smartphones, PDAs, and
next-generation wireless communicators
1.1
i.MX21 Block Diagram
Figure 1-1 is a simplified functional block diagram of the i.MX21 processor.
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1-1
Introduction
Connectivity
System Control
i.MX21
JTAG/Multi ICE
CSPI x 3
SSI x 2
System Boot
I2C
Clock Management
Audio Mux
ARM9 Platform
UART x 4
ARM926EJ-S
MAX
Timers x 3
I Cache
MMU
PWM
D Cache
Bus Control
Internal Control
Memory Control
Standard System I/O
1-WIRE
IrDA
USB OTG/ 2 Hosts
Memory Expansion
WDOG
RTC
PCMCIA/CF
GPIO
DMA
Human Interface
MMC/SD x 2
Enhanced Multimedia Accelerator
(eMMA)
Memory Interface
SDRAMC
LCD Controller
Pre- and Post- Processing
WEIM/BMI
SLCD Controller
Video Accelerator
Keypad
NANDFC
Figure 1-1. MC9328MX21 Functional Block Diagram
1.2
i.MX21 Features
The MC9328MX21 boasts a robust array of features that can support a wide variety of applications. This
chapter provides a brief description of the i.MX21 processor’s features.
1.2.1
ARM926EJ-S Core Complex
The ARM926EJ-S Core Complex (also known as the ARM926 platform) consists of the ARM926EJ-S
processor, a 6 × 4 Multi-Layer AHB crossbar switch, and a primary AHB complex.
• ARM926EJ-S microprocessor core
— 16K instruction cache and 16K data cache
— High-performance ARM® 32-bit RISC engine
— Thumb® 16-bit compressed instruction set for a leading level of code density
— Efficient execution of Java byte codes
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•
•
•
•
•
— EmbeddedICE™ JTAG software debug
— 100 percent user code binary compatibility with ARM7TDMI®
— Advanced Microcontroller Bus Architecture (AMBA™) system-on-chip multi-master bus
interface
— Support for mixed loads of real-time and user applications via cache locking facilities
— Virtual Memory Management Unit (VMMU)
ARM Interrupt Controller (AITC)
— The AITC is connected to the primary AHB as a slave device and provides support for up to
64 interrupt sources. It generates normal and fast interrupts to the processor core. The AITC
supports a hardware assisted vectoring mode for automatic vectoring to reduce interrupt
latency.
Digital Phase-Locked Loops (DPLLs) and Power Control Module
— Digital phase-locked loops (DPLLs) and clock controller for all internal clock generation
— MCUPLL generates system and CPU clocks from a 26MHz crystal
— USBPLL generates 48 MHz clock for the USB OTG from either a 26 MHz crystal or 32kHz
— Support for three power modes for different power consumption needs: run, doze, and stop.
AHB to IP bus interfaces (AIPIs)
— Provide a communication interface between the high-speed AHB to a lower-speed IP bus for
slave peripherals
The Multi-Layer 6 × 4 AHB Crossbar Switch
— The crossbar switch allows for concurrent transactions to proceed from any input port (bus
master) to any output port (bus slave). That is, it is possible for all four output ports to be active
at the same time as a result of four independent input or output requests.
CPU and System speed
— ARM926EJ-S core: up to 266 MHz
— System Clock: up to 133 MHz
— External memory interface: same clock source as system, up to 133 MHz at 1.8V supply
— System clock is derived from the CPU clock through an integer divider
1.2.2
System Control and Timers
The i.MX21 processor contains various timers and system control features to optimize the control of both
the internal modules and external devices.
1.2.2.1
Watchdog Timer
The Watchdog Timer module (WDOG Timer) provides the following:
• Programmable time out of 0.5 s to 64 s
• Resolution of 0.5 s
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Introduction
1.2.2.2
Real-Time Clock/Sampling Timer
The Real-Time Clock (RTC) module maintains the system clock, provides stopwatch, alarm, and interrupt
functions, and supports the following features:
• 32.768 kHz and 32 kHz input operation
• Full clock features: seconds, minutes, hours, days
• Capable of counting up to 512 days
• Minute countdown timer with interrupt
• Programmable daily alarm with interrupt
• Sampling timer with interrupt
• Once-per-second, once-per-minute, once-per-hour, and once-per-day interrupts
• Interrupt generation for digitizer sampling or keyboard debouncing
1.2.2.3
Three General-Purpose 32-Bit Counters/Timers
The General-Purpose Timer (GPT) module contains three identical general-purpose 32-bit timers with
programmable prescalers and compare and capture registers with the following features:
• Automatic interrupt generation
• Programmable timer input/output pins
• Input capture capability with programmable trigger edge
• Output compare with programmable mode
1.2.2.4
Pulse-Width Modulator Module
The following features characterize the Pulse-Width Modulator (PWM) module:
• 4 × 16 FIFO to minimize interrupt overhead
• 16-bit resolution
• Sound and melody generation
1.2.2.5
General-Purpose I/O Ports
The GPIO module provides six general purpose I/O ports. Each single GPIO port is a 32-bit port that may
be multiplexed with one or more dedicated functions. The GPIO features are:
• Supports level or edge trigger interrupt and is system wake-up capable
• Most I/O signals are multiplexed with dedicated functions for pin efficiency
1.2.2.6
Endianness
The i.MX21 processor system supports only little endian.
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1.2.3
Memory Interface
The memory interfaces of the i.MX21 processor consist of the SDRAM controller, the Direct Memory
Access controller, the NAND Flash controller and the External Interface module. The individual features
of these controllers are provided in this section.
1.2.3.1
SDRAM Controller
The SDRAM controller (SDRAMC) consists of 7 major blocks, including the SDRAM command
controller, page and bank address comparators, row/column address multiplexer, data aligner/multiplexer,
configuration registers, refresh request counter, and the powerdown timer. The features offered by the
SDRAMC are as follows:
• Support for four banks of single data rate 64 Mbit, 128 Mbit, and 256 Mbit SDRAM
— Two independent chip-selects with up to 64 Mbyte per chip-select
— Up to four banks active simultaneously for each chip-select
— JEDEC standard pinout and operation
— Boot capability from CSD1
• PC133-compliant interface
— 133 MHz system clock achievable with “-8” option PC133-compliant memories
— Single and fixed-length (4-word) burst access
— Access time of 8-1-1-1 at 133 MHz
• Software configurable for differing system requirements
— 16-bit or 32-bit bus width
— Configurable row cycle delay (tRC), row precharge delay (tRP), row-to-column delay (tRCD),
and column-to-data delay (CAS latency)
• Built-in auto-refresh timer and state machine
• Hardware-supported self-refresh entry and exit: capability to maintain valid data during system
reset and low-power modes
• Auto-powerdown (clock suspend) timer
1.2.3.2
Direct Memory Access Controller
The Direct Memory Access Controller (DMAC) provides 16 channels to support linear memory, 2D
memory, FIFO and end-of-burst enable FIFO transfers to support a wide variety of DMA operations.
Features include:
• Supports 16 channels linear memory, 2D memory and FIFO for both source and destination
• Supports 8-bit, 16-bit, or 32-bit FIFO port size and memory port size data transfer
• DMA burst length is configurable up to maximum of 16 words, 32 half-words, or 64 bytes for each
channel
• Bus utilization control for a channel that is not triggered by DMA request
• Interrupts provided to interrupt handler on bulk data transfer complete or transfer error
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DMA burst time-out error to terminate DMA cycle when the burst cannot be completed in a
programmed timing period
Dedicated external DMA request and grant signal
Support increment, decrement and no increment for source and destination addressing
Supports DMA chaining
1.2.3.3
NAND Flash Controller
The NAND Flash controller (NFC) interfaces standard NAND Flash parts to the i.MX21 processor and
hides the complexities of accessing NAND Flash. The NFC features include:
• Contains hardware bootloader for automatic boot up from NAND Flash devices
• Supports all 8-bit/16-bit NAND Flash devices regardless of density and organization
• Supports 512 byte and 2 Kbyte page sizes
• Internal 2 Kbyte of buffer RAM used as boot RAM during cold startup and as read/write page
buffers to relieve CPU intervention
• Automatic ECC detection and selectable correction
• Data protection for ram buffer and NAND Flash pages
1.2.3.4
External Interface Module
The External Interface module (EIM) handles the interface to devices external to the i.MX21 processor,
including generation of chip selects for external peripherals and memory, and provides the following
features:
• Six Chip Selects (CS0-5) for external devices, each with 16 Mbyte of address space
• CS0 supports boot from ROM, NAND, or NOR Flash of up to 32 Mbyte of address space
• Programmable protection, port size, and wait states for each chip-select
• Internal/external boot ROM selection
• Selectable bus watchdog counter
• Burst support for external AMD™ or Intel® flash with 32-bit data path
• External Data Transfer Acknowledge (DTACK) support for slower devices connected on CS5
1.2.4
Bus Master Interface (BMI)
The BMI module enables high speed connection between the i.MX21 processor and the alternate bus
master devices in the system. The BMI provides support for the following functions:
• Supports 8- or 16-bit data bus mode
• Supports external bus master read or write to CPU using memory access timing
• Supports CPU write to external bus slave using memory access timing
• Supports ATI graphic chip burst read/write accesses timing
• High communication speed
• Supports DMA
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1.2.5
Inter-Chip Connectivity
This section describes how the modules within the i.MX21 processor interface with each other and
provides a high-level overview on how the architecture of the busses are configured and multiplexed.
1.2.5.1
Inter-IC (I2C) Bus Module
I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange,
minimizing the interconnection between devices. This bus is suitable for applications requiring occasional
communications over a short distance between many devices. The flexible I2C allows additional devices
to be connected to the bus for expansion and system development. The I2C features include:
• Multiple-master operation
• Software-programmable for 1 of 64 different serial clock frequencies
• Interrupt-driven, byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation and detection
• Repeated START signal generation
• Acknowledge bit generation and detection
• Bus-busy detection
1.2.5.2
Three Configurable Serial Peripheral Interfaces for High Speed Data
Transfer
The i.MX21 processor has three Configurable Serial Peripheral Interface (CSPI) modules which allow
rapid data communication with fewer software interrupts than conventional serial communications. Each
CSPI is equipped with data FIFO and is a master/slave configurable serial peripheral interface module,
allowing the i.MX21 processor to interface with external SPI master or slave devices.
• Master/slave configurable
• Two chip selects each for master mode operation
• Up to 16-bit programmable data transfer
• 8 × 16 FIFO for both transmit and receive data
1.2.5.3
Two Synchronous Serial Interfaces with Inter-IC Sound (I2S) and AC97
Host Controller Module (SSI/I2S/AC97)
Features include the following:
• Supports generic SSI interface for timeslot based communication with synchronous voice codecs
• Timeslot mode supports up to 4 channels for communication among devices Bluetooth voice port,
voice codecs and baseband audio ports
• Supports Philips standard Inter-IC Sound (I2S) bus for external digital audio chip interface at
44.1 kHz and 48 kHz
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AC97 Host Controller mode with support for 2 audio channels supporting variable and fixed rate
transfers. Fixed mode only supports 48 kHz sampling rate.
Used together with the Digital Audio Mux (AUDMUX) module to provide flexible audio and voice
routing options
1.2.6
Peripheral Support
The i.MX21 processor provides a CMOS sensor interface (CSI) that allows the integration of a extensive
variety of popular camera features.
1.2.6.1
CMOS Sensor Interface (CSI)
The CSI features include the following:
• Configurable interface supports wide variety of popular CMOS sensors that output data in YUV,
RGB, or Bayer format
• Supports CCIR656 format
• Statistic data generation for auto exposure and auto white balance control which is required for
Bayer data
• DMA support for image data transfer
• Private data bus to eMMA Pre-processor module for video and image preprocessing
1.2.7
Display and Video Modules
There are two separate LCD controllers in the i.MX21 processor—the LCDC and SLCDC that support
both dumb and smart LCD panels. A dumb LCD panel has no built-in memory and requires an external
controller to send display data at a fixed rate. Such panels typically support high refresh rates suitable for
graphics, games, and video applications. The LCD controller in the i.MX21 processor is an AHB master
and can transfer display data from system memory (SDRAM).
Smart panels have built-in memory and a display controller. An advantage of the built-in memory and
controller, is that the refresh function is done by the local LCD controller and only data that is changing
must be updated thus offering a reduced transfer rate and lower power operation.
Both LCD controllers in the i.MX21 processor provide glueless connection to external gray-scale or color
LCD panels.
The video input port in the i.MX21 processor supports a direct interface to commonly available CMOS
sensors. Together with other system resources (DMA and hardware Pre-processor), viewfinder functions
can be achieved with extremely low CPU MIPS and low system power consumption.
1.2.7.1
LCD Controller (LCDC)
The LCDC features include the following:
• Software programmable screen size (up to 800 × 600) to support single (non-split) monochrome,
color STN panels and color TFT panels
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Support color depth for CSTN panels: 4- or 8-bit mapping from 256 × 18 table, 12-bit true color
Support color depth for TFT panels: 4- or 8-bit mapping from 256 × 18 table, 16-bit/18-bit/24-bit
true color
Up to 16 grey levels out of 16 palettes
Capable of directly driving popular LCD drivers from manufacturers including Motorola, Sharp,
Hitachi, and Toshiba
Support for data bus width of 16-bit or 18-bit TFT panels
Support for data bus width of 8-bit, 4-bit, 2-bit, and 1-bit monochrome LCD panels
Direct interface to Sharp® 320 × 240 and 240 × 320 HR-TFT panels and other generic panels
Support for logical operation between color hardware cursor and background
LCD contrast control using 8-bit PWM
Support for self-refresh LCD modules
Hardware panning (soft horizontal scrolling)
Windowing support for one graphic or text overlay
1.2.7.2
Smart LCD Controller (SLCDC)
The SLCDC transparently and efficiently transfers image data from system memory to an external LCD
controller. The SLCDC module contains a DMA controller that transfers image and control data from
system memory to the SLCDC FIFO where it is formatted and sent out to the external LCD controller.
The SLCDC can be configured to write image data to an external LCD controller via a 4-line serial, 3-line
serial, an 8- or 16- bit parallel interface. The SLCDC has two FIFOs where command and display data are
loaded via DMA. The display data is tagged with commands that are used by the SLCDC to communicate
display information and data to the Smart LCD panel.
The command tagged data format of the SLCDC provides flexibility and ease of connection to existing
and new smart LCD panels.
1.2.8
enhanced Multimedia Accelerator (eMMA)
The i.MX21 processor comes with an enhanced Multimedia Accelerator (eMMA) comprising an ISO/IEC
14496-2 compliant MPEG-4 encoder and decoder, independent Pre-processing and Post-processing stages
which provide exceptional image and video quality. The eMMA represents a major breakthrough to solve
the problem of high MIPS requirement for video encode and decode operations in mobile and wireless
applications. Tight integration and memory pipelining coupled with AHB master mode operation ensures
minimal system loading. To further offload the CPU, live video stream data enters the eMMA module
directly through an internal private data interface. The eMMA architecture is shown in Figure 1-2.
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Introduction
IP bus
IP bus Interface
Video
Video
Post
Pre-
Encoder
Decoder
Processing
Processing
Sensor data
From CSI
Bus Arbitration
AHB bus
Figure 1-2. eMMA Architecture
1.2.8.1
Video Encoder
eMMA provides the following video encoder capabilities:
• Supports MPEG4 and H.263 (Short Video Header)
• Fully conforms to ISO/IEC 14496-2 Visual Simple Profiles Levels 0 to 3
• Supports real-time encoding images of sizes from 32 × 32 up to CIF or QVGA at 30 fps
• Input data format is YUV 4:2:0 (Planar)
• Supports camera stabilization
1.2.8.2
Video Decoder
eMMA provides the following video decoder capabilities:
• Supports MPEG4 and H.263 (Short Video Header)
• Fully conforms to ISO/IEC 14496-2 Visual Simple Profile Levels 0 to 3
• Supports real-time decoding of image sizes up to CIF or QVGA at 30 fps
• Output data format is YUV 4:2:0 (Planar)
1.2.8.3
Image Pre-processor (PrP)
The image Pre-processor block, shown in Figure 1-3, performs color space conversion and image resizing
for viewfinder display and data formatting for video encoder and still image for input to a hardware or
software based video encoder or image compressor. The Pre-processor has two media input and output
paths and can accept input from system memory or from a private data bus connected to the CMOS Sensor
Interface (CSI) module. The Pre-processor can apply frame rate control on the live video stream from the
CSI module to adjust for different processing load conditions. The Pre-processor’s two output channels
are used to output RGB data for display of local camera view and to output image data for compression by
the hardware encoder or a software encoder (still image or video encode).
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System
Memory
CMOS
Sensor
Interface
Main
Color Space
Resize
Conversion
Second
Resize
Frame
YUV
Compression
4:2:2,4:2:0,
4:4:4
or video encode
RGB
Display
Viewfinder
Buffer
Buffer
(RGB/YUV)
Pre-processor
Optional data paths using dumb CMOS sensors
Figure 1-3. Pre-processor Data Flow
Pre-processor features:
• Data input:
— System memory
— Private DMA between CMOS Sensor Interface module and pre-processor
• Data input formats:
— Arbitrarily unpacked RGB input
— YUV 4:2:2 (Interleaved)
— YUV 4:2:0 (Planar)
• Input image size: 2044 × 2044
• Image scaling:
— Main resize ratio: 8:1–1:1 in integral steps, Horizontal 9:8/vertical 6:5 and Horizontal
9:8/Vertical 1:1
— Secondary resize ratio for viewfinder: 8:1–1:1 in integral steps
• Output data format:
— RGB565
— YUV 4:2:2 (Interleaved)
— YUV 4:2:0 (Planar)
• RGB data and one YUV data format can be generated concurrently
1.2.8.4
Postprocessor (PP)
The Postprocessor, shown in Figure 1-4, performs Deblock, Dering, Image Resize and Color Space
Conversion (CSC) functions on the input image data. These functions provide flexibility to meet various
RGB formats and YUV formats for display. Besides working in tandem with the decoder sub-block in the
eMMA, the Postprocessor can also be used by software decoders (other than MPEG4) to touch up the final
output before display. The sub-blocks that perform Deblock, Dering, Resize and CSC operations can be
selectively bypassed through software configuration. Figure 1-4 shows the flow for video postprocessing.
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MPEG4
Decoder
Current/
Ref
Postprocessor
Frame
Deblock
Dering
Image
Color
Resize
Conversion
RGB
Display
Buffer
Current/
Ref
Frame
Figure 1-4. Postprocessor
Postprocessor features:
• Input data:
— From system memory
• Input format:
— YUV 4:2:0 (Planar)
• Output format:
— YUV422
— RGB444
— RGB565
— RGB666
— RGB888 (unpacked)
• Input Size: Maximum size of 2044 × 2044
• Image Resize:
— Upscaling ratios ranging from 1:1 to 1:4 in fractional steps
— Downscaling ratios ranging from 1:1 to 2:1 in fractional steps and a fixed 4:1
— Ratios provide scaling between QCIF, CIF, QVGA (320 × 240) and QVGA (240 × 320)
1.2.8.5
Two Multimedia Card and Secure Digital Host Controller Modules
The Multimedia Card/Secure Digital Host module (MMC/SD) integrates MMC support with SD memory
and I/O functions. The features include:
• Fully compatible with the MMC system specification version 2.2
• Fully compatible with the SD Memory Card specification 1.0 and SD I/O specification 1.0 with 1
and 4 channel(s)
• Up to ten MMC cards and one SD supported by standard (maximum data rate with up to ten cards)
• Supports hot swappable operation
• Data rates from 25 Mbps to 100 Mbps
• Dedicated power pin
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Part of the External Memory Interface (EMI) complex comprising the Nand Flash Controller,
Wireless External Interface to Memory (WEIM) and SDRAM Controller
1.2.8.6
Digital Audio Mux
The Digital Audio Mux (AUDMUX) provides a programmable interconnect fabric for voice, audio and
synchronous data routing between the i.MX21 processor’s SSI modules and external SSI, audio and voice
codecs. The AUDMUX features include:
• Supports 1 host and 3 peripheral interfaces
• Flexible audio, voice and data routing without host processor intervention
• Built-in support for network mode connection of host and peripheral interfaces
• Separate and simultaneous audio paths from hosts to peripherals
• External 4-wire connection to synchronous devices, audio and voice codecs
1.2.9
Connectivity and Expansion
There are multiple peripheral modules in the i.MX21 processor that provide external connection
capability. All peripherals that have FIFOs support DMA transfers to and from the FIFOs. This minimizes
CPU intervention and reduces interrupt overhead to the system. The exception to this is the Pulse Width
Modulator that includes FIFOs, however, does not support DMA.
1.2.9.1
Four Universal Asynchronous Receiver/Transmitters
(UART1, UART2, UART3, and UART4)
The UART modules are capable of standard RS-232 non-return-to-zero (NRZ) encoding format and
IrDA-compatible infrared modes. Each UART provides serial communication capability with external
devices through an RS-232 cable or through use of external circuitry that converts infrared signals to
electrical signals (for reception) or transforms electrical signals to signals that drive an infrared LED (for
transmission) to provide low speed IrDA compatibility to the i.MX21 processor. Features include:
• Supports serial data transmit/receive operation: 7 or 8 data bits, 1 or 2 stop bits, programmable
parity (even, odd, or none)
• Automatic baud rate detection
• 32-bytes FIFO for transmit and 32 half-words FIFO for receive data
• IrDA Serial Infra-Red (SIR) mode support
1.2.9.2
USB On-The-Go (USB OTG) Controller
The USB controller in the i.MX21 processor implements the USB On-The-Go (USB OTG) supplement.
The USB OTG module is complaint to the USB 2.0 and operates at full and low speeds as specified in USB
2.0. The OTG port is capable of connecting to a USB host or client device and uses the Host Negotiation
Protocol (HNP) and Session Request Protocol (SRP) to switch between Host and Function roles. One of
the dual host ports is dedicated for connection to a smartphone USB client device and the other host port
is available for connection to other client devices. The connection to the smartphone forms the
interprocessor link as an alternate to a UART-based link.
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Introduction
Built-in switching logic implements a bypass mode in which the internal host port is bypassed to allow an
external USB host and the smartphone USB client to be directly connected. This feature enables the
external USB host to directly control the smartphone modem for debug or for production programming.
Figure 1-5 shows the USB OTG block.
The USB OTG module is a bus master and takes ownership of the bus for DMA. This allows the USB OTG
to continue operation while the CPU is in a low power mode.
DMAIP
OTGIP
USB Core
AHB
DMA
Master
Control
Registers
ETD Memory
DMA
Registers
AHB
Host
Host SIE
Controller
Root Hub
Host1
Host2
Data
OTG
Memory
Slave
Function
Controller
Function
SIE
EP Memory
Figure 1-5. USB On-The-Go Controller Block Diagram
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Compliant with the USB 2.0 specification for operation at full speed (12 Mbit/sec) and low speed
(1.5 Mbit/sec)
Fully compliant with the USB On-The-Go specification
Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) Protocol (SRP) must be
implemented in software
Transaction scheduling and transfer level protocol implemented in hardware including bandwidth
management, data toggle and retry
AMBA AHB 2.0 Bus Master DMA Controller:
— 32 DMA Channels for Host Controller EndPoint Transfer Descriptors
— 32 DMA Channels for Function Controller EndPoint Descriptors
USB function supports 32 physical endpoints:
— 16 IN endpoints and 16 OUT endpoints
— Programmable for type (control, interrupt, bulk, isochronous), packet size, and buffering
Double buffering support for all four types of host and function controller transactions
Separate descriptor and data memory space
Direct device to device transfers in one frame
Power savings mode for Host Controller and suspend mode for Function Controller
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All USB host ports support external transceiver bypass mode
1.2.10
Debug Capability
The i.MX21 processor offers designers and programers with full-debug capabilities through
industry-standard JTAG interface and the ability to bootload using either a serial or USB interface.
• UART Bootstrap mode function:
— Allows system initialization and program or data download to system memory via USB or
UART1
— Accepts execution command to run program stored in system memory
— Supports memory/register read/write operation of selectable data size of byte, half-word, or
word
— Provides a 16-byte instruction buffer for ARM instruction storage and execution
• USB Bootstrap mode function
— Supports bootstrapping through USB OTG port
• JTAG port to support generic ARM debug tools
1.2.10.1
PCMCIA/CF Interface
The PCMCIA/CF host controller module provides all the control logic for a PCMCIA socket interface and
requires only additional external analog power switching logic and buffering. The controller supports one
PCMCIA socket and includes the following features:
• PCMCIA/CF host controller interface compliant with the PCMCIA standard release 2.1 (for I/O
Cards) and fully compliant with the Compact Flash Specification V1.4
• Supports one PCMCIA or CF socket
• Supports hot-insertion, card detection and removal
• Mapping to common memory space, attribute memory space and I/O space. Each space is up to
32 kbyte in size.
• Supports 5 programmable memory and IO windows.
• Generates a single interrupt to the CPU
• Programmable card access timing to interface with slower devices
• Supports TrueIDE mode
• Provides special control signals for external buffering to separate high and low speed paths
1.2.10.2
Keypad Port
The Keypad Port is a 16-bit peripheral which can be used either for keypad matrix scanning or as general
purpose I/O. Features include:
• Supports up to 8 × 8 external key pad matrix
• Open drain design
• Glitch suppression circuit prevents erroneous key detection
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Multiple keys detection
Standby key press detection
1.2.10.3
Fast Infra-Red Interface (FIRI)
The Fast Infra-Red Interface (USB device module) in the i.MX21 processor implements both the Medium
Infra-Red (MIR) and Fast Infra-Red (FIR) protocols. In MIR mode, the FIRI supports wireless
communications at 0.576 Mbps and 1.152 Mbps and uses a framed transmission protocol which follows
the High-Level Data Link Controller (HDLC) protocol. In FIR mode, the module operates at 4 Mbps with
4 Pulse Position Modulation (4PPM) defined by IrDA, version 1.4.
In addition to the MIR and FIR modes, the i.MX21 processor supports SIR protocol on all 4 of the UART
modules. Only UART1 may be used together with the FIRI as these two modules share their pins for
transparent speed and protocol stepping from SIR to MIR or SIR to FIR modes.
Figure 1-6 shows the FIRI sharing pins with the UART module and pin selection is controlled via GPIO
configuration.
i.MX21
IR Module
USB Device
Module
IOMUX
LED
UART
IR Detector
GPIO
Figure 1-6. Fast Infra-Red Interface
The USB device module can be divided to the following functional parts:
• Packet assembler
• Searcher
• 4PPM modulator/demodulator
• CRC32 encoder and decoder
• DMA capable receive and transmit FIFOs
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1.2.10.4
1-Wire® Interface
The 1-Wire module is a peripheral device that communicates with the ARM926EJ-S Core and provides a
communication line to a 1 Kbit Add-Only Memory (DS2502). The 1-Wire interface features include:
• Supports 1-Wire interface to a 1Kbit Add-Only Memory (DS2502)
• Implements 1-Wire protocol defined by Dallas Semiconductors
1.2.11
Power Management
The i.MX21 processor’s power management features are as follows:
• Support for 3 power modes of operation: RUN, DOZE, and STOP
• Aggressive clock gating within modules to minimize CMOS switching power
• Active well biasing technique to reduce standby mode current consumption
• Voltage/frequency scalable capability (Lib or silicon characterization is needed)
1.2.12
Electronic and Package Information
The i.MX21 processor features the following electronic and package information:
• Operating voltage
— I/O voltage: 1.7 V to 2.0 V or 2.7 V to 3.3 V
— Internal logic voltage: 1.45 V to 1.65 V
• Package
— Type: 0.65 mm and 0.5 mm pitch MAPBGA
— Dimensions: 14mm × 14mm for 0.65 mm type
— Pins: 289
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Chapter 2
Signal Descriptions and Pin Assignments
This chapter identifies and describes the i.MX21 signals and their pin assignments. It also contains a short
section on power-up sequence of the i.MX21.
2.1
Signal Descriptions
Table 2-1 provides complete information on the signal multiplexing of the i.MX21 signals.
The connections of the pins in Table 2-1 depends solely upon the user application, however there are a few
factory test signals that are not used in a normal application. Following is a list of these signals and how
they are to be terminated for proper operation of the i.MX21 processor:
• CLKMODE[1:0]: To ensure proper operation, leave these signals as no connects.
• OSC26M_TEST: To ensure proper operation, leave this signal as no connect.
• EXT_48M: To ensure proper operation, connect this signal to ground.
• EXT_266M: To ensure proper operation, connect this signal to ground.
• TEST_WB[2:0]: These signals are also multiplexed with GPIO PORT E as well as alternate
keypad signals. If not utilizing these signals for GPIO functionality or for their other multiplexed
function, then configure as GPIO input with pull up enabled, and leave as a no connect.
• TEST_WB[4:3]: To ensure proper operation, leave these signals as no connects.
Table 2-1. i.MX21 Signal Descriptions
Signal Name
Function/Notes
External Bus/Chip Select (EIM)
A [25:0]
Address bus signals
D [31:0]
Data bus signals
EB0
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24], shared with SDRAM
DQM0.
EB1
Byte Strobe—Active low external enable byte signal that controls D [23:16], shared with SDRAM DQM1.
EB2
Byte Strobe—Active low external enable byte signal that controls D [15:8], shared with SDRAM DQM2
and PCMCIA PC_REG.
EB3
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0], shared with SDRAM
DQM3 and PCMCIA PC_IORD.
OE
Memory Output Enable—Active low output enables external data bus, shared with PCMCIA PC_IOWR.
CS [5:0]
Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR) in the System Control chapter. By default CSD [1:0] is
selected. DTACK is multiplexed with CS4.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
2-1
Signal Descriptions and Pin Assignments
Table 2-1. i.MX21 Signal Descriptions (continued)
Signal Name
Function/Notes
ECB
Active low input signal sent by flash device to the EIM whenever the flash device must terminate an
on-going burst sequence and initiate a new (long first access) burst sequence.
LBA
Active low signal sent by flash device causing the external burst device to latch the starting burst
address.
BCLK
RW
DTACK
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW signal—Indicates whether external access is a read (high) or write (low) cycle. This signal is also
shared with the PCMCIA PC_WE.
DTACK signal—External input data acknowledge signal, multiplexed with CS4.
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode upon system reset is determined by the
settings of these pins. To hardwire these inputs low, terminate with a 1 KΩ resister to ground. For a logic
high, terminate with a 1 KΩ resistor to VDDA. Do not change the state of these inputs after power-up.
Boot 3 should always be tied to logic low.
SDRAM Controller
SDBA [4:0]
SDRAM non-interleave mode bank address signals. These signals are multiplexed with address signals
A[20:16].
SDIBA [3:0]
SDRAM interleave addressing mode bank address signals. These signals are multiplexed with address
signals A[24:21].
MA [11:0]
SDRAM address signals. MA[9:0] are multiplexed with address signals A[10:1].
DQM [3:0]
SDRAM data qualifier mask multiplexed with EB[3:0]. DQM3 corresponds to D[31:24], DQM2
corresponds to D[23:16], DQM1 corresponds to D[15:8], and DQM0 corresponds to D[7:0].
CSD0
SDRAM Chip Select signal. This signal is multiplexed with the CS2 signal. This signal is selectable by
programming the Function Multiplexing Control Register in the System Control chapter.
CSD1
SDRAM Chip Select signal. This signal is multiplexed with the CS3 signal. This signal is selectable by
programming the Function Multiplexing Control Register in the System Control chapter.
RAS
SDRAM Row Address Select signal.
CAS
SDRAM Column Address Select signal
SDWE
SDRAM Write Enable signal
SDCKE0
SDRAM Clock Enable 0
SDCKE1
SDRAM Clock Enable 1
SDCLK
SDRAM Clock
Clocks and Resets
EXTAL26M
Crystal input (26MHz), or a 16 MHz to 32 MHz oscillator (or square-wave) input when the internal
oscillator circuit is shut down. When using an external signal source, feed this input with a square wave
signal switching from GND to VDDA.
XTAL26M
Oscillator output to external crystal. When using an external signal source, float this output.
EXTAL32K
32 kHz or 32.768 kHz crystal input. When using an external signal source, feed this input with a square
wave signal switching from GND to QVDD5.
XTAL32K
CLKO
Oscillator output to external crystal. When using an external signal source, float this output.
Clock Out signal selected from internal clock signals. Please refer to clock controller for internal clock
selection.
i.MX21 Reference Manual, Rev. 3
2-2
Freescale Semiconductor
Signal Descriptions and Pin Assignments
Table 2-1. i.MX21 Signal Descriptions (continued)
Signal Name
Function/Notes
EXT_48M
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
EXT_266M
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
RESET_IN
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all modules
(except the reset module, SDRAMC module, and the clock control module) are reset.
RESET_OUT
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the
following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
POR
Power On Reset—Active low Schmitt trigger input signal. The POR signal is normally generated by an
external RC circuit designed to detect a power-up event.
CLKMODE[1:0]
These are special factory test signals. To ensure proper operation, leave these signals as no connects.
OSC26M_TEST
This is a special factory test signal. To ensure proper operation, leave this signal as a no connect.
TEST_WB[2:0]
These are special factory test signals. However, these signals are also multiplexed with GPIO PORT E
as well as alternate keypad signals. If not using these signals for GPIO functions or for other multiplexed
functions, then configure as GPIO input with pull-up enabled, and leave as a no connect.
TEST_WB[4:3]
These are special factory test signals. To ensure proper operation, leave these signals as no connects.
WKGD
Battery indicator input used to qualify the walk-up process. Also multiplexed with TIN.
JTAG
For termination recommendations, see the Table “JTAG pinouts” in the Multi-ICE® User Guide from ARM® Limited.
TRST
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
TDO
Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK
Test Clock to synchronize test logic and control register access through the JTAG port.
TMS
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of
TCK.
JTAG_CTRL
JTAG Controller select signal—JTAG_CTRL is sampled during the rising edge of TRST. Must be pulled
to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal test purposes
only.
RTCK
JTAG Return Clock used to enhance stability of JTAG debug interface devices. This signal is multiplexed
with 1-Wire, therefore using 1-Wire renders RTCK unusable and vice versa.
CMOS Sensor Interface
CSI_D [7:0]
Sensor port data
CSI_MCLK
Sensor port master clock
CSI_VSYNC
Sensor port vertical sync
CSI_HSYNC
Sensor port horizontal sync
CSI_PIXCLK
Sensor port data latch clock
LCD Controller
LD [17:0]
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. LD[15:0] signals are
multiplexed with SLCDC1_DAT[15:0] from SLCDC1 and BMI_D[15:0]. LD[17] signal is multiplexed with
BMI_WRITE of BMI. LD[16] is multiplexed with BMI_READ_REQ of BMI and EXT_DMAGRANT.
FLM_VSYNC
(or simply referred
to as VSYNC)
Frame Sync or Vsync—This signal also serves as the clock signal output for gate
driver (dedicated signal SPS for Sharp panel HR-TFT). This signal is multiplexed with BMI_RXF_FULL
and BMI_WAIT of the BMI.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
2-3
Signal Descriptions and Pin Assignments
Table 2-1. i.MX21 Signal Descriptions (continued)
Signal Name
Function/Notes
LP_HSYNC (or simply Line Pulse or HSync
referred to as HSYNC)
LSCLK
OE_ACD
CONTRAST
SPL_SPR
Shift Clock. This signal is multiplexed with the BMI_CLK_CS from BMI.
Alternate Crystal Direction/Output Enable.
This signal is used to control the LCD bias voltage as contrast control. This signal is multiplexed with the
BMI_READ from BMI.
Sampling start signal for left and right scanning. This signal is multiplexed with the SLCDC1_CLK.
PS
Control signal output for source driver (Sharp panel dedicated signal). This signal is multiplexed with the
SLCDC1_CS.
CLS
Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated signal). This
signal is multiplexed with the SLCDC1_RS.
REV
Signal for common electrode driving signal preparation (Sharp panel dedicated signal). This signal is
multiplexed with SLCDC1_D0.
Smart LCD Controller
SLCDC1_CLK
SLCDC Clock output signal. This signal is multiplexed and available at 2 alternate locations. These are
SPL_SPR and SD2_CLK signals of LCDC and SD2, respectively.
SLCDC1_CS
SLCDC Chip Select output signal. This signal is multiplexed and available at 2 alternate signal locations.
These are PS and SD2_CMD signals of LCDC and SD2, respectively.
SLCDC1_RS
SLCDC Register Select output signal. This signal is multiplexed and available at 2 alternate signal
locations. These are CLS and SD2_D3 signals of LCDC and SD2, respectively.
SLCDC1_D0
SLCDC serial data output signal. This signal is multiplexed and available at 2 alternate signal locations.
These are and REV and SD2_D2 signals of LCDC and SD2, respectively. This signal is inactive when a
parallel data interface is used.
SLCDC1_DAT[15:0]
SLCDC Data output signals for connection to a parallel SLCD panel interface. These signals are
multiplexed with LD[15:0] while an alternate 8-bit SLCD muxing is available on LD[15:8]. Further
alternate muxing of these signals are available on some of the USB OTG and USBH1 signals.
SLCDC2_CLK
SLCDC Clock input signal for pass through to SLCD device. This signal is multiplexed with SSI3_CLK
signal from SSI3.
SLCDC2_CS
SLCDC Chip Select input signal for pass through to SLCD device. This signal is multiplexed with
SSI3_TXD signal from SSI3.
SLCDC2_RS
SLCDC Register Select input signal for pass through to SLCD device. This signal is multiplexed with
SSI3_RXD signal from SSI3.
SLCDC2_D0
SLCD Data input signal for pass through to SLCD device. This signal is multiplexed with SSI3_FS signal
from SSI3.
Bus Master Interface (BMI)
BMI_D[15:0]
BMI_CLK_CS
BMI bidirectional data bus. Bus width is programmable between 8-bit or 16-bit.These signals are
multiplexed with LD[15:0] and SLCDC_DAT[15:0].
BMI bidirectional clock or chip select signal.This signal is multiplexed with LSCLK of LCDC.
BMI_WRITE
BMI bidirectional signal to indicate read or write access. This is an input signal when the BMI is a slave
and an output signal when BMI is the master of the interface. BMI_WRITE is asserted for write and
negated for read.This signal is muxed with LD[17] of LCDC.
BMI_READ
BMI output signal to enable data read from external slave device. This signal is not used and driven high
when BMI is slave.This signal is multiplexed with CONTRAST signal of LCDC.
i.MX21 Reference Manual, Rev. 3
2-4
Freescale Semiconductor
Signal Descriptions and Pin Assignments
Table 2-1. i.MX21 Signal Descriptions (continued)
Signal Name
Function/Notes
BMI_READ_REQ
BMI Read request output signal to external bus master. This signal is active when the data in the TXFIFO
is larger or equal to the data transfer size of a single external BMI access.This signal is muxed with
LD[16] of LCDC.
BMI_RXF_FULL
BMI Receive FIFO full active high output signal to reflect if the RxFIFO reaches water mark value.This
signal is muxed with VSYNC of the LCDC.
BMI_WAIT
BMI Wait—Active low signal to wait for data ready (read cycle) or accepted (write_cycle). Also
multiplexed with VSYNC.
External DMA
EXT_DMAREQ
EXT_DMAGRANT
External DMA Request input signal. This signal is multiplexed with CSPI1_RDY.
External DMA Grant output signal. This signal is multiplexed with LD[16] of LCDC and CSPI1_SS1 of
CSPI1.
NAND Flash Controller
NF_CLE
NAND Flash Command Latch Enable output signal. Multiplexed with PC_POE of PCMCIA.
NF_CE
NAND Flash Chip Enable output signal. This signal is multiplexed with PC_CE1 of PCMCIA.
NF_WP
NAND Flash Write Protect output signal. This signal is multiplexed with PC_CE2 of PCMCIA.
NF_ALE
NAND Flash Address Latch Enable output signal. This signal is multiplexed with PC_OE of PCMCIA.
NF_RE
NAND Flash Read Enable output signal. This signal is multiplexed with PC_RW of PCMCIA.
NF_WE
NAND Flash Write Enable output signal. This signal is multiplexed with and PC_BVD2 of PCMCIA.
NF_RB
NAND Flash Ready Busy input signal. This signal is multiplexed with PC_RST of PCMCIA.
NF_IO[15:0]
NAND Flash Data input and output signals. NF_IO[15:7] signals are multiplexed with A[25:21] and
A[15:13]. NF_IO[7:0] signals are multiplexed with several PCMCIA signals.
PCMCIA Controller
PC_A[25:0]
PCMCIA Address signals. These signals are multiplexed with A[25:0].
PC_D[15:0]
PCMCIA Data input and output signals. These signals are multiplexed with D[15:0].
PC_CD1
PCMCIA Card Detect1 input signal. This signal is multiplexed with NFIO[7] signal of NF.
PC_CD2
PCMCIA Card Detect2 input signal. This signal is multiplexed with NFIO[6] signal of NF.
PC_WAIT
PCMCIA Wait input signal to extend current access. This signal is multiplexed with NFIO[5] signal of NF.
PC_READY
PCMCIA Ready input signal indicates card is ready for access. Multiplexed with NFIO[4] signal of NF.
PC_RST
PCMCIA Reset output signal. This signal is multiplexed with NFRB signal of NF.
PC_OE
PCMCIA Memory Read Enable output signal asserted during common or attribute memory read cycles.
This signal is multiplexed with NFALE signal of NF.
PC_WE
PCMCIA Memory Write Enable output signal asserted during common or attribute memory cycles. This
signal is shared with RW of the EIM.
PC_VS1
PCMCIA Voltage Sense1 input signal. This signal is multiplexed with NFIO[2] signal of NF.
PC_VS2
PCMCIA Voltage Sense2 input signal. This signal is multiplexed with NFIO[1] signal of NF.
PC_BVD1
PCMCIA Battery Voltage Detect1 input signal. This signal is multiplexed with NFIO[0] signal of NF.
PC_BVD2
PCMCIA Battery Voltage Detect2 input signal. This signal is multiplexed with NF_WE signal of NF.
PC_SPKOUT
PC_REG
PCMCIA Speaker Out output signal. This signal is multiplexed with PWMO signal.
PCMCIA Register Select output signal. This signal is shared with EB2 of EIM.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
2-5
Signal Descriptions and Pin Assignments
Table 2-1. i.MX21 Signal Descriptions (continued)
Signal Name
Function/Notes
PC_CE1
PCMCIA Card Enable1 output signal. This signal is multiplexed with NFCE signal of NF.
PC_CE2
PCMCIA Card Enable2 output signal. This signal is multiplexed with NFWP signal of NF.
PC_IORD
PCMCIA IO Read output signal. This signal is shared with EB3 of EIM.
PC_IOWR
PCMCIA IO Write output signal. This signal is shared with OE signal of EIM.
PC_WP
PCMCIA Write Protect input signal. This signal is multiplexed with NFIO[3] signal of NF.
PC_POE
PCMCIA Output Enable signal to enable voltage translation buffers and transceivers. This signal is
multiplexed with NFCLE signal of NF.
PC_RW
PCMCIA Read Write output signal to control external transceiver direction. Asserted high for read
access and negated low for write access. This signal is multiplexed with NFRE signal of NF.
PC_PWRON
PCMCIA input signal to indicate that the card power has been applied and stabilized.
CSPI
CSPI1_MOSI
Master Out/Slave In signal
CSPI1_MISO
Master In/Slave Out signal
CSPI1_SS[2:0]
Slave Select (Selectable polarity) signal. CSPI1_SS2 is also multiplexed with USBG_RXDAT and
CSPI1_SS1 is multiplexed with EXT_DMAGRANT.
CSPI1_SCLK
Serial Clock signal
CSPI1_RDY
Serial Data Ready signal. Also multiplexed with EXT_DMAREQ.
CSPI2_MOSI
Master Out/Slave In signal. This signal is multiplexed with USBH2_TXDP signal of USB OTG.
CSPI2_MISO
Master In/Slave Out signal. This signal is multiplexed with USBH2_TXDM signal of USB OTG.
CSPI2_SS[2:0]
Slave Select (Selectable polarity) signals. These signals are multiplexed with USBH2_FS,
USBH2_RXDP and USBH2_RXDM signal of USB OTG
CSPI2_SCLK
Serial Clock signal. This signal is multiplexed with USBH2_OE signal of USB OTG
CSPI3_MOSI
Master Out/Slave In signal. This signal is multiplexed with SD1_CMD.
CSPI3_MISO
Master In/Slave Out signal. This signal is multiplexed with SD1_D0.
CSPI3_SS
Slave Select (Selectable polarity) signal multiplexed with SD1_D3.
CSPI3_SCLK
Serial Clock signal. This signal is multiplexed with SD1_CLK.
General Purpose Timers
TIN
Timer Input Capture or Timer Input Clock—The signal on this input is applied to all 3 timers
simultaneously. This signal is muxed with the Walk-up Guard Mode WKGD signal in the PLL, Clock, and
Reset Controller module.
TOUT1
(or simply TOUT)
Timer Output signal from General Purpose Timer1 (GPT1). This signal is multiplexed with SYS_CLK1
and SYS_CLK2 signal of SSI1 and SSI2. The pin name of this signal is simply TOUT.
TOUT2
Timer Output signal from General Purpose Timer1 (GPT2). This signal is multiplexed with PWMO.
TOUT3
Timer Output signal from General Purpose Timer1 (GPT3). This signal is multiplexed with PWMO.
USB On-The-Go
USB_BYP
USB Bypass input active low signal. This signal can only be used for USB function, not for GPIO.
USB_PWR
USB Power output signal
USB_OC
USB Over current input signal. This signal can only be used for USB function, not for GPIO.
i.MX21 Reference Manual, Rev. 3
2-6
Freescale Semiconductor
Signal Descriptions and Pin Assignments
Table 2-1. i.MX21 Signal Descriptions (continued)
Signal Name
Function/Notes
USBG_RXDP
USB OTG Receive Data Plus input signal. This signal is muxed with SLCDC1_DAT15.
USBG_RXDM
USB OTG Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT14.
USBG_TXDP
USB OTG Transmit Data Plus output signal. This signal is muxed with SLCDC1_DAT13.
USBG_TXDM
USB OTG Transmit Data Minus output signal. This signal is muxed with SLCDC1_DAT12.
USBG_RXDAT
USB OTG Transceiver differential data receive signal. Multiplexed with CSPI1_SS2.
USBG_OE
USB OTG Output Enable signal. This signal is muxed with SLCDC1_DAT11.
USBG_ON
USB OTG Transceiver ON output signal. This signal is muxed with SLCDC1_DAT9.
USBG_FS
USB OTG Full Speed output signal. This signal is multiplexed with external transceiver USBG_TXR_INT
signal of USB OTG. This signal is muxed with SLCDC1_DAT10.
USBH1_RXDP
USB Host1 Receive Data Plus input signal. This signal is multiplexed with UART4_RXD and
SLCDC1_DAT6. It also provides an alternative multiplex for UART4_RTS, where this signal is selectable
by programming the Function Multiplexing Control Register in the System Control chapter.
USBH1_RXDM
USB Host1 Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT5. It also provides
an alternative multiplex for UART4_CTS.
USBH1_TXDP
USB Host1 Transmit Data Plus output signal. This signal is multiplexed with UART4_CTS and
SLCDC1_DAT4. It also provides an alternative multiplex for UART4_RXD, where this signal is selectable
by programming the Function Multiplexing Control Register in the System Control chapter.
USBH1_TXDM
USB Host1 Transmit Data Minus output signal. Multiplexed with UART4_TXD and SLCDC1_DAT3.
USBH1_RXDAT
USB Host1 Transceiver differential data receive signal. Multiplexed with USBH1_FS.
USBH1_OE
USB Host1 Output Enable signal. This signal is muxed with SLCDC1_DAT2.
USBH1_FS
USB Host1 Full Speed output signal. Multiplexed with UART4_RTS and SLCDC1_DAT1 and
USBH1_RXDAT.
USBH_ON
USB Host transceiver ON output signal. This signal is muxed with SLCDC1_DAT0.
USBH2_RXDP
USB Host2 Receive Data Plus input signal. This signal is multiplexed with CSPI2_SS[1] of CSPI2.
USBH2_RXDM
USB Host2 Receive Data Minus input signal. This signal is multiplexed with CSPI2_SS[2] of CSPI2.
USBH2_TXDP
USB Host2 Transmit Data Plus output signal. This signal is multiplexed with CSPI2_MOSI of CSPI2.
USBH2_TXDM
USB Host2 Transmit Data Minus output signal. This signal is multiplexed with CSPI2_MISO of CSPI2.
USBH2_OE
USB Host2 Output Enable signal. This signal is multiplexed with CSPI2_SCLK of CSPI2.
USBH2_FS
USB Host2 Full Speed output signal. This signal is multiplexed with CSPI2_SS[0] of CSPI2.
USBG_SCL
USB OTG I2C Clock input/output signal. This signal is multiplexed with SLCDC1_DAT8.
USBG_SDA
USB OTG I2C Data input/output signal. This signal is multiplexed with SLCDC1_DAT7.
USBG_TXR_INT
USB OTG transceiver interrupt input. Multiplexed with USBG_FS.
Secure Digital Interface
SD1_CMD
SD Command bidirectional signal—If the system designer does not want to make use of the internal
pull-up, via the Pull-up enable register, a 4.7k–69k external pull-up resistor must be added. This signal
is multiplexed with CSPI3_MOSI.
SD1_CLK
SD Output Clock. This signal is multiplexed with CSPI3_SCLK.
SD1_D[3:0]
SD Data bidirectional signals—If the system designer does not want to make use of the internal pull-up,
via the Pull-up enable register, a 50k–69k external pull-up resistor must be added. SD1_D[3] is muxed
with CSPI3_SS while SD1_D[0] is muxed with CSPI3_MISO.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
2-7
Signal Descriptions and Pin Assignments
Table 2-1. i.MX21 Signal Descriptions (continued)
Signal Name
Function/Notes
SD2_CMD
SD Command bidirectional signal. This signal is multiplexed with SLCDC1_CS signal from SLCDC1.
SD2_CLK
SD Output Clock signal. This signal is multiplexed with SLCDC1_CLK signal from SLCDC1.
SD2_D[3:0]
SD Data bidirectional signals. SD2_D[3:2] are multiplexed with SLCDC1_RS and SLCDC_D0 signals
from SLCDC1.
UARTs – IrDA/Auto-Bauding
UART1_RXD
Receive Data input signal
UART1_TXD
Transmit Data output signal
UART1_RTS
Request to Send input signal
UART1_CTS
Clear to Send output signal
UART2_RXD
Receive Data input signal. This signal is multiplexed with KP_ROW6 signal from KPP.
UART2_TXD
Transmit Data output signal. This signal is multiplexed with KP_COL6 signal from KPP.
UART2_RTS
Request to Send input signal. This signal is multiplexed with KP_ROW7 signal from KPP.
UART2_CTS
Clear to Send output signal. This signal is multiplexed with KP_COL7 signal from KPP.
UART3_RXD
Receive Data input signal. This signal is multiplexed with IR_RXD from FIRI.
UART3_TXD
Transmit Data output signal. This signal is multiplexed with IR_TXD from FIRI.
UART3_RTS
Request to Send input signal
UART3_CTS
Clear to Send output signal
UART4_RXD
Receive Data input signal which is multiplexed with USBH1_RXDP and USBH1_TXDP.
UART4_TXD
Transmit Data output signal which is multiplexed with USBH1_TXDM.
UART4_RTS
Request to Send input signal which is multiplexed with USBH1_FS and USBH1_RXDP.
UART4_CTS
Clear to Send output signal which is multiplexed with USBH1_TXDP and USBH1_RXDM.
Serial Audio Port – SSI (configurable to I2S protocol and AC97)
SSI1_CLK
Serial clock signal which is output in master or input in slave
SSI1_TXD
Transmit serial data
SSI1_RXD
Receive serial data
SSI1_FS
Frame Sync signal which is output in master and input in slave
SYS_CLK1
SSI1 master clock. Multiplexed with TOUT.
SSI2_CLK
Serial clock signal which is output in master or input in slave.
SSI2_TXD
Transmit serial data signal
SSI2_RXD
Receive serial data
SSI2_FS
Frame Sync signal which is output in master and input in slave.
SYS_CLK2
SSI2 master clock. Multiplexed with TOUT.
SSI3_CLK
Serial clock signal which is output in master or input in slave. Multiplexed with SLCDC2_CLK
SSI3_TXD
Transmit serial data signal which is multiplexed with SLCDC2_CS
SSI3_RXD
Receive serial data which is multiplexed with SLCDC2_RS
SSI3_FS
Frame Sync signal which is output in master and input in slave. Multiplexed with SLCDC2_D0.
SAP_CLK
Serial clock signal which is output in master or input in slave.
i.MX21 Reference Manual, Rev. 3
2-8
Freescale Semiconductor
Signal Descriptions and Pin Assignments
Table 2-1. i.MX21 Signal Descriptions (continued)
Signal Name
Function/Notes
SAP_TXD
Transmit serial data
SAP_RXD
Receive serial data
SAP_FS
Frame Sync signal which is output in master and input in slave.
I2C
I2C_CLK
I2C Clock
I2C_DATA
I2C Data
1-Wire
OWIRE
1-Wire input and output signal. This signal is multiplexed with JTAG RTCK.
PWM
PWMO
PWM Output. This signal is multiplexed with PC_SPKOUT of PCMCIA, as well as TOUT2 and TOUT3
of the General Purpose Timer module.
General Purpose Input/Output
PF[16]
Dedicated GPIO. When unused, program this signal as an input with the on-chip pull-up resistor enabled.
Keypad
KP_COL[7:0]
Keypad Column selection signals. KP_COL[7:6] are multiplexed with UART2_CTS and UART2_TXD
respectively. Alternatively, KP_COL6 is also available on the internal factory test signal TEST_WB2. The
Function Multiplexing Control Register in the System Control chapter must be used in conjunction with
programming the GPIO multiplexing (to select the alternate signal multiplexing) to choose which signal
KP_COL6 is available.
KP_ROW[7:0]
Keypad Row selection signals. KP_ROW[7:6] are multiplexed with UART2_RTS and UART2_RXD
signals respectively. Alternatively, KP_ROW7 and KP_ROW6 are available on the internal factory test
signals TEST_WB0 and TEST_WB1 respectively. The Function Multiplexing Control Register in the
System Control chapter must be used in conjunction with programming the GPIO multiplexing (to select
the alternate signal multiplexing) to choose which signals KP_ROW6 and KP_ROW7 are available.
Noisy Supply Pins
NVDD
Noisy Supply for the I/O pins. There are six (6) I/O voltages, NVDD1 through NVDD6.
NVSS
Noisy Ground for the I/O pins
Supply Pins – Analog Modules
VDDA
QVSS (internally
connected to AVSS)
Supply for analog blocks
Quiet GND for analog blocks (QVSS and AVSS are synonymous)
Internal Power Supplies
QVDD
Power supply pins for silicon internal circuitry
QVSS
Quiet GND pins for silicon internal circuitry
QVDDX
Power supply pin for the ARM core. Externally connect directly to QVDD
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
2-9
I/O Power Supply and Signal Multiplexing Scheme
This section describes detailed information about both the power supply for each I/O pin and its function multiplexing scheme. The
user can reference information provided in Table 2-2 to configure the power supply scheme for each device in the system (memory
and external peripherals). The function multiplexing information also shown in Table 2-2 allows the user to select the function of each
pin by configuring the appropriate GPIO registers when those pins are multiplexed to provide different functions. In some cases, the
use of the Function Multiplexing Control Register (FMCR) in the System Control chapter may be required to select multiplexed
functionality. Table 2-1 on page 2-1 indicates which signals require the use of the FMCR.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
Default
L
A25_NFIO15
KP
KP/I1
D31
L
A24_NFIO14
KP
KP/I1
D30
L
A23_NFIO13
KP
KP/I1
D29
L
A22_NFIO12
KP
KP/I1
D28
L
A21_NFIO11
KP
KP/I1
D27
L
A20
KP
KP/I1
D26
L
A19
KP
KP/I1
D25
L
A18
KP
KP/I1
D24
L
A17
KP
KP/I1
D23
NVDD1
F3
A25_NFIO15
B
NVDD1
F2
D31
B
NVDD1
F1
A24_NFIO14
B
NVDD1
G4
D30
B
NVDD1
G3
A23_NFIO13
B
NVDD1
G2
D29
B
NVDD1
G1
A22_NFIO12
B
NVDD1
H4
D28
B
NVDD1
H3
A21_NFIO11
B
NVDD1
H2
D27
B
NVDD1
H1
A20
O
NVDD1
J4
D26
B
NVDD1
J1
A19
O
NVDD1
J3
D25
B
NVDD1
J2
A18
O
NVDD1
K4
D24
B
NVDD1
K2
A17
O
NVDD1
K3
D23
B
NVDD1
H7
NVDD1
NVDD1
K1
A16
NVDD1
K7
NVSS1
NVDD1
L4
D22
B
NVDD1
L2
A15_NFIO10
B
NVDD1
L3
D21
B
BOUT
AOUT
CIN
BIN
AIN
PU
Mux
OD
GPIO
PU
Signal
Dir
OD
Signal
PU
Alternate
Dir
Primary
BGA
Pins
I/O
Supply
Voltage
Reset
(At/After)
Table 2-2. i.MX21 Signal Multiplexing Scheme
(Note: See end of table for table footnotes and table legend)
NVDD1
O
L
A16
NVSS1
KP
KP/I1
D22
L
A15_NFIO10
KP
KP/I1
D21
Signal Descriptions and Pin Assignments
2-10
2.2
NVDD1
M3
D20
QVDD
D5
QVDD
B
KP
Reset
(At/After)
BOUT
AOUT
CIN
BIN
AIN
PU
Mux
OD
GPIO
PU
B
Signal
Dir
A14_NFIO9
OD
L1
Signal
PU
NVDD1
Alternate
Dir
Primary
I/O
Supply
Voltage
BGA
Pins
Freescale Semiconductor
Table 2-2. i.MX21 Signal Multiplexing Scheme (continued)
(Note: See end of table for table footnotes and table legend)
Default
L
A14_NFIO9
KP/I
1
D20
QVDD
i.MX21 Reference Manual, Rev. 3
QVSS
D6
QVSS
NVDD1
M2
A13_NFIO8
B
QVSS
NVDD1
M1
D19
B
NVDD1
N2
A12
O
NVDD1
M4
D18
B
NVDD1
N1
A11
KP
L
A13_NFIO8
KP/I1
D19
L
A12
KP/I1
D18
O
L
A11
KP/I1
D17
NVDD1
N3
D17
B
NVDD1
P2
A10
O
NVDD1
N4
D16
B
NVDD1
P1
A9
O
NVDD1
P3
D15
B
NVDD1
R2
A8
O
NVDD1
P4
D14
B
NVDD1
J7
NVDD1
NVDD1
R1
A7
NVSS1
L7
NVSS1
NVDD1
R3
D13
B
NVDD1
T2
A6
O
KP
KP
KP
KP
KP
L
A10
KP/I1
D16
L
A9
1
D15
L
A8
KP/I1
D14
KP/I
NVDD1
O
L
A7
NVSS1
R4
D12
B
NVDD1
T1
A5
O
NVDD1
U1
D11
B
NVDD1
V1
A4
O
2-11
NVDD1
V2
EB0/DQM0
O
NVDD1
T4
D10
B
NVDD1
U2
EB1/DQM1
O
NVDD1
V3
D9
B
NVDD1
U3
EB2/DQM2/PC_REG
NVDD1
W1
A3
NVDD1
T3
EB3/DQM3/PC_IORD
O
NVDD1
V4
D8
B
KP
KP
KP/I1
D13
L
A6
1
D12
L
A5
KP/I1
D11
L
A4
H
EB0/DQM0
KP/I
KP/I1
D10
H
EB1/DQM1
KP/I1
D9
O
H
EB2/DQM2/PC_REG
O
L
A3
H
EB3/DQM3/PC_IORD
KP/I1
D8
KP
KP
KP
Signal Descriptions and Pin Assignments
NVDD1
KP
B
NVDD1
U5
CS4
O
KP
PF21 PUEN
DTACK
Reset
(At/After)
D7
PF22 PUEN
BOUT
W3
AOUT
NVDD1
CIN
O
BIN
O
A2
AIN
CS5
W2
PU
V5
NVDD1
Mux
NVDD1
OD
O
GPIO
PU
OE/PC_IOWR
Signal
Dir
U4
OD
Signal
PU
NVDD1
Alternate
Dir
BGA
Pins
Primary
I/O
Supply
Voltage
Default
H
OE/PC_IOWR
Pull-H
PF22
L
A2
KP/I1
D7
Pull-H
PF21
i.MX21 Reference Manual, Rev. 3
NVSS1
N10
NVSS1
NVDD1
W4
A1
NVSS1
NVDD1
N12
NVDD1
NVDD1
T5
CS3/CSD1
O
NVDD1
W5
CS2/CSD0
O
NVDD1
U6
D6
B
NVDD1
W6
A0
O
L
A0
NVDD1
T6
CS1
O
H
CS1
NVDD1
V6
D5
B
NVDD1
T7
BCLK
O
O
L
A1
NVDD1
KP
KP
H
CSD1
H
CSD0
KP/I1
D6
KP/I1
D5
H
BCLK
NVDD1
V7
CS0
O
H
CS0
NVDD1
U7
ECB
I
PU
H
ECB
NVDD1
W7
D4
B
KP
KP/I1
D4
NVDD1
N7
LBA
O
H
LBA
NVDD1
V8
RW/PC_WE
O
H
RW/PC_WE
NVDD1
U8
D3
B
KP
KP/I1
KP
1
KP/I
D3
D2
Freescale Semiconductor
NVDD1
W8
D2
B
NVDD1
T8
MA11
O
NVDD1
V9
D1
B
NVDD1
U9
MA10
O
NVDD1
W9
D0
B
KP
KP/I1
D0
NVDD1
V10
JTAG_CTRL
I
PU
Pull-H
JTAG_CTRL
QVDD
K12
QVDD
QVDD
QVSS
K13
QVSS
QVSS
NVDD1
N13
NVDD1
NVDD1
W10
SDCLK
NVSS1
N11
NVSS1
NVDD1
U10
PC_PWRON
L
KP
MA11
KP/I1
D1
L
MA10
NVDD1
O
H2
SDCLK
L
PC_PWRON
NVSS1
I
PD
Signal Descriptions and Pin Assignments
2-12
Table 2-2. i.MX21 Signal Multiplexing Scheme (continued)
(Note: See end of table for table footnotes and table legend)
Dir
Reset
(At/After)
Default
Signal
RAS
O
H
RAS
BOUT
AOUT
CIN
BIN
AIN
PU
Mux
OD
GPIO
PU
Signal
Dir
T9
OD
NVDD1
Alternate
PU
Primary
I/O
Supply
Voltage
BGA
Pins
Freescale Semiconductor
Table 2-2. i.MX21 Signal Multiplexing Scheme (continued)
(Note: See end of table for table footnotes and table legend)
NVDD1
T10
CAS
O
H
CAS
NVDD1
V11
SDWE
O
H
SDWE
i.MX21 Reference Manual, Rev. 3
NVDD1
N9
SDCKE0
O
H
SDCKE0
NVDD1
W11
SDCKE1
O
H
SDCKE1
NVDD1
U11
Reserved
I
PF16 PUEN
Pull-H
PF16
NVDD1
V12
CLKO
O
PF15 PUEN
N/A
CLKO
NVDD1
M11
NFIO7
B
PF14 PUEN
PC_CD1
Pull-H
NFIO7
NVDD1
V13
NFIO6
B
PF13 PUEN
PC_CD2
Pull-H
NFIO6
NVDD1
T11
NFIO5
B
PF12 PUEN
PC_WAIT
Pull-H
NFIO5
NVDD1
U12
NFIO4
B
PF11 PUEN
PC_READY
Pull-H
NFIO4
NVDD1
T12
NFIO3
B
PF10 PUEN
PC_WP
Pull-H
NFIO3
NVDD1
L11
NFIO2
B
PF9 PUEN
PC_VS1
Pull-H
NFIO2
NFIO1
NVDD1
U13
NFIO1
B
PF8 PUEN
PC_VS2
Pull-H
NVDD1
W12
NFIO0
B
PF7 PUEN
PC_BVD1
Pull-H
NFIO0
NVDD1
T13
NFWE
O
PF6 PUEN
PC_BVD2
H
NFWE
NVDD1
W13
NFRE
O
PF5 PUEN
PC_RW
H
NFRE
U14
NFALE
O
PF4 PUEN
PC_OE
L
NFALE
U15
NFCLE
O
PF3 PUEN
PC_POE
L
NFCLE
NVDD1
L12
NFWP
O
PF2 PUEN
PC_CE2
H
NFWP
NVDD1
T15
NFCE
O
PF1 PUEN
PC_CE1
H
NFCE
NVDD1
M12
NFRB
I
PF0 PUEN
PC_RST
Pull-H
NFRB
NVDD1
M13
EXT_48M
I
N/A3
EXT_48M
NVDD1
R17
EXT_266M
I
N/A3
EXT_266M
NVDD2
M7
NVDD2
NVDD2
R16
SD1_CLK
O
CSPI3_SCLK
O
PE23 PUEN
Pull-H
NVDD2
P17
SD1_CMD
B
CSPI3_MOSI
O
PE22 PUEN
Pull-H
PE22
NVDD2
T17
SD1_D3
B
CSPI3_SS
O
PE21 PUEN
Pull-H
PE21
NVDD2
P16
SD1_D2
B
PE20 PUEN
Pull-H
PE20
PE19 PUEN
Pull-H
PE19
PE18 PUEN
Pull-H
PE18
NVDD2
PE23
2-13
NVDD2
N18
SD1_D1
B
NVDD2
N16
SD1_D0
B
NVSS2
R18
NVSS2
NVSS2
VDDA
V18
VDDA
VDDA
CSPI3_MISO
I
Signal Descriptions and Pin Assignments
NVDD1
NVDD1
Dir
Reset
(At/After)
Default
Signal
EXTAL26M
I
N/A
EXTAL26M
BOUT
AOUT
CIN
BIN
AIN
PU
Mux
OD
GPIO
PU
Signal
Dir
W16
OD
VDDA
Alternate
PU
BGA
Pins
Primary
I/O
Supply
Voltage
i.MX21 Reference Manual, Rev. 3
QVSS
V14
QVSS
VDDA
W17
XTAL26M
O
N/A
XTAL26M
QVSS
VDDA
V17
OSC26M_TEST
I
N/A3
OSC26M_TEST
5
See
RESET_IN
L/H
5
See
6
See
6
See
6
See
6
See
RESET_OUT
VDDA
T14
RESET_IN
I
VDDA
V15
RESET_OUT
O
VDDA
U16
POR
I
VDDA
U18
BOOT3
I
VDDA
U17
BOOT2
I
VDDA
T16
BOOT1
I
VDDA
V16
BOOT0
I
PU
PE17 PUEN
POR
BOOT3
BOOT2
BOOT1
BOOT0
3
CLKMODE1
CLKMODE0
VDDA
T18
CLKMODE1
I
PU
N/A
VDDA
T19
CLKMODE0
I
PU
N/A3
QVDD
L9
QVDD
QVDD
QVSS
L10
QVSS
QVSS
QVDD
V19
EXTAL32K
I
N/A
EXTAL32K
QVDD
U19
XTAL32K
I
N/A
XTAL32K
NVDD3
R19
TRST
I
PU
Pull-H
TRST
NVDD3
P19
TMS
I
PU
Pull-H
TMS
NVDD3
N17
TCK
I
PU
Pull-H
TCK
NVDD3
P18
TDI
I
PU
Pull-H
TDI
NVDD3
K11
TDO
O
H
TDO
NVDD3
N19
RTCK
O
PE16 PUEN
L
RTCK
OWIRE
B
OD
Freescale Semiconductor
NVDD3
M18
UART1_RTS
I
PE15 PUEN
Pull-H
UART1_RTS
NVDD3
M19
UART1_CTS
O
PE14 PUEN
H
UART1_CTS
NVDD3
K10
UART1_RXD
I
PE13 PUEN
Pull-H
UART1_RXD
NVDD3
L13
UART1_TXD
O
PE12 PUEN
H
UART1_TXD
NVDD3
L17
UART3_RTS
I
PE11 PUEN
Pull-H
PE11
NVDD3
L18
UART3_CTS
O
PE10 PUEN
Pull-H
PE10
NVDD3
M17
UART3_RXD
I
PE9 PUEN
Pull-H
PE9
NVDD3
L19
UART3_TXD
O
PE8 PUEN
Pull-H
PE8
NVDD3
M16
UART2_RXD
I
KP_ROW6
B
PE7 PUEN
Pull-H
UART2_RXD
NVDD3
L16
UART2_TXD
O
KP_COL6
B
ODEN PE6 PUEN
H
UART2_TXD
IR_RXD
IR_TXD
Signal Descriptions and Pin Assignments
2-14
Table 2-2. i.MX21 Signal Multiplexing Scheme (continued)
(Note: See end of table for table footnotes and table legend)
Dir
PU
Reset
(At/After)
i.MX21 Reference Manual, Rev. 3
Default
Signal
K17
KP_COL5
B
PU ODEN
Pull-H
KP_COL5
NVDD3
K18
KP_COL4
B
PU ODEN
Pull-H
KP_COL4
NVDD3
K16
KP_COL3
B
PU ODEN
Pull-H
KP_COL3
NVDD3
K19
KP_COL2
B
PU ODEN
Pull-H
KP_COL2
NVDD3
J17
KP_COL1
B
PU ODEN
Pull-H
KP_COL1
NVDD3
J18
KP_COL0
B
PU ODEN
Pull-H
KP_COL0
NVDD3
J13
TEST_WB0
B
KP_ROW7
B
PE2 PUEN
Pull-H3
TEST_WB0
NVDD3
J19
TEST_WB1
B
KP_ROW6
B
PE1 PUEN
Pull-H3
TEST_WB1
NVDD3
H17
TEST_WB2
B
KP_COL6
B
ODEN PE0 PUEN
Pull-H3
TEST_WB2
TEST_WB3
TEST_WB4
BOUT
AOUT
CIN
BIN
AIN
PU
Mux
OD
GPIO
PU
Signal
Dir
NVDD3
Alternate
OD
Primary
I/O
Supply
Voltage
BGA
Pins
Freescale Semiconductor
Table 2-2. i.MX21 Signal Multiplexing Scheme (continued)
(Note: See end of table for table footnotes and table legend)
VDDA
H18
TEST_WB3
I
Pull-H3
VDDA
H16
TEST_WB4
I
Pull-H3
NVDD3
H19
PWMO
O
NVDD3
J16
UART2_RTS
I
NVDD3
G18
UART2_CTS
O
NVDD3
J10
KP_ROW5
B
PU
NVDD3
G19
KP_ROW4
B
PU
Pull-H
KP_ROW4
NVDD3
G17
KP_ROW3
B
PU
Pull-H
KP_ROW3
QVDD
W14
QVDD
QVSS
W15
QVSS
NVDD3
J11
KP_ROW2
B
PU
Pull-H
KP_ROW2
NVDD3
G16
KP_ROW1
B
PU
Pull-H
KP_ROW1
NVDD3
F18
KP_ROW0
B
PU
Pull-H
KP_ROW0
NVDD3
J12
CSPI1_MOSI
B
PD31 PUEN
Pull-H
PD31
NVDD3
F17
CSPI1_MISO
B
PD30 PUEN
Pull-H
PD30
NVDD3
H10
CSPI1_SCLK
B
PD29 PUEN
Pull-H
PD29
NVDD3
F19
CSPI1_SS0
B
PD28 PUEN
Pull-H
PD28
Pull-H
PD27
PE5 PUEN
KP_ROW7
B
PE4 PUEN
KP_COL7
B
ODEN PE3 PUEN
PC_SPKOUT
TOUT2
TOUT3
Pull-H
PE5
Pull-H
UART2_RTS
H
UART2_CTS
Pull-H
KP_ROW5
QVDD
QVSS
NVDD3
F16
CSPI1_SS1
B
PD27 PUEN
NVDD3
E18
CSPI1_SS2
B
PD26 PUEN
USBG_
RXDAT
Pull-H
PD26
NVDD3
H11
CSPI1_RDY
I
PD25 PUEN
EXT_
DMAREQ
Pull-H
PD25
2-15
NVDD3
E19
CSPI2_MOSI
B
PD24 PUEN
USBH2_TXDP
Pull-H
PD24
NVDD3
E17
CSPI2_MISO
B
PD23 PUEN
USBH2_TXDM
Pull-H
PD23
Signal Descriptions and Pin Assignments
EXT_
DMA
GRANT
Dir
Reset
(At/After)
Default
Signal
D19
CSPI2_SCLK
B
PD22 PUEN
USBH2_OE
Pull-H
PD22
NVDD3
D18
CSPI2_SS0
B
PD21 PUEN
USBH2_FS
Pull-H
NVSS3
N8
NVSS3
NVSS3
QVDD
W18
QVDD
QVDD
QVSS
W19
QVSS
QVSS
NVDD3
M8
NVDD3
BOUT
AOUT
CIN
BIN
AIN
PU
Mux
OD
GPIO
PU
Signal
Dir
OD
NVDD3
Alternate
PU
BGA
Pins
Primary
I/O
Supply
Voltage
PD21
NVDD3
i.MX21 Reference Manual, Rev. 3
NVDD3
C19
CSPI2_SS1
B
PD20 PUEN
USBH2_
RXDP
NVDD3
B19
CSPI2_SS2
B
PD19 PUEN
USBH2_
RXDM
NVDD3
C18
I2C_CLK
B
OD
OD
NVDD3
B18
I2C_DATA
B
NVDD3
C17
SSI3_CLK
B
PD18 PUEN
SLCDC2_CLK
I
Pull-H
PD20
Pull-H
PD19
Pull-H
PD18
PD17 PUEN
Pull-H
PD17
PC31 PUEN
Pull-H
PC31
NVDD3
B17
SSI3_TXD
B
SLCDC2_CS
I
PC30 PUEN
Pull-H
PC30
NVDD3
C16
SSI3_RXD
B
SLCDC2_RS
I
PC29 PUEN
Pull-H
PC29
SLCDC2_D0
I
NVDD3
A19
SSI3_FS
B
NVDD3
D17
SSI2_CLK
B
NVDD3
A18
SSI2_TXD
B
NVDD3
A17
SSI2_RXD
B
PC28 PUEN
Pull-H
PC28
PC27 PUEN
Pull-H
PC27
PC26 PUEN
Pull-H
PC26
PC25 PUEN
Pull-H
PC25
NVDD3
B16
SSI2_FS
B
PC24 PUEN
Pull-H
PC24
NVDD3
A16
SSI1_CLK
B
PC23 PUEN
Pull-H
PC23
NVDD3
C15
SSI1_TXD
B
PC22 PUEN
Pull-H
PC22
NVDD3
D16
SSI1_RXD
B
PC21 PUEN
Pull-H
PC21
Freescale Semiconductor
NVDD3
B15
SSI1_FS
B
PC20 PUEN
Pull-H
PC20
NVDD3
E16
SAP_CLK
B
PC19 PUEN
Pull-H
PC19
NVDD3
A15
SAP_TXD
B
PC18 PUEN
Pull-H
PC18
NVDD3
D15
SAP_RXD
B
PC17 PUEN
Pull-H
PC17
NVDD3
B14
SAP_FS
B
PC16 PUEN
Pull-H
PC16
NVDD3
C14
TIN
I
PC15 PUEN
Pull-H
PC15
Pull-H
PC14
WKGD
SYS_
CLK
NVDD3
A14
TOUT
O
PC14 PUEN
SYS_CLK
NVDD3
D14
USBG_RXDP
I
PC13 PUEN
SLCDC1_DAT15
Pull-H
PC13
NVDD3
C13
USBG_RXDM
I
PC12 PUEN
SLCDC1_DAT14
Pull-H
PC12
NVDD3
G13
USBG_TXDP
O
PC11 PUEN
SLCDC1_DAT13
Pull-H
PC11
Signal Descriptions and Pin Assignments
2-16
Table 2-2. i.MX21 Signal Multiplexing Scheme (continued)
(Note: See end of table for table footnotes and table legend)
Dir
Reset
(At/After)
Default
Signal
B13
USBG_TXDM
O
PC10 PUEN
SLCDC1_DAT12
Pull-H
PC10
NVDD3
H13
USBG_OE
O
PC9 PUEN
SLCDC1_DAT11
Pull-H
NVSS3
M9
NVSS3
NVDD3
L8
NVDD3
i.MX21 Reference Manual, Rev. 3
NVDD3
A13
NVDD3
NVDD3
NVDD3
NVDD3
BOUT
AOUT
CIN
BIN
AIN
PU
Mux
OD
GPIO
PU
Signal
Dir
OD
NVDD3
Alternate
PU
Primary
I/O
Supply
Voltage
BGA
Pins
Freescale Semiconductor
Table 2-2. i.MX21 Signal Multiplexing Scheme (continued)
(Note: See end of table for table footnotes and table legend)
PC9
NVSS3
NVDD3
USBG_FS
O
PC8 PUEN
D13
USBG_ON
O
B12
USBG_SCL
B
OD
G12
USBG_SDA
B
OD
D12
USBH1_RXDP
I
NVDD3
C12
USBH1_RXDM
I
NVDD3
H12
USBH1_TXDP
NVDD3
D11
NVDD3
UART4_RXD
I
O
UART4_CTS
O
USBH1_TXDM
O
UART4_TXD
O
A12
USBH1_OE
B
NVDD3
A11
USBH1_FS
O
NVDD3
G11
USBH_ON
NVDD3
C11
USB_OC
NVDD3
B11
USBG_TXR_
INT
SLCDC1_DAT10
Pull-H
PC8
PC7 PUEN
SLCDC1_DAT9
Pull-H
PC7
PC6 PUEN
SLCDC1_DAT8
Pull-H
PC6
PC5 PUEN
SLCDC1_DAT7
PB31 PDEN
SLCDC1_DAT6
PB30 PDEN
SLCDC1_DAT5
PB29 PDEN
SLCDC1_DAT4
PB28 PDEN
UART4_RTS
UART4_CTS
PC5
Pull-L
PB31
Pull-L
PB30
Pull-L
PB29
SLCDC1_DAT3
Pull-L
PB28
PB27 PUEN
SLCDC1_DAT2
Pull-H
PB27
PB26 PDEN
SLCDC1_DAT1
Pull-L
PB26
O
PB25 PUEN
SLCDC1_DAT0
Pull-H
PB25
I
PB24 PUEN
Pull-H
PB24
USB_PWR
O
PB23 PUEN
Pull-L
USB_PWR
I
PB22 PUEN
Pull-H
USB_BYP
UART4_RTS
I
UART4_RXD
Pull-H
USBH1_
RXDAT
G10
USB_BYP
J9
NVDD4
NVDD4
C10
CSI_HSYNC
I
PB21 PUEN
Pull-H
PB21
NVDD4
A10
CSI_VSYNC
I
PB20 PUEN
Pull-H
PB20
NVDD4
D10
CSI_D7
I
PB19 PUEN
Pull-H
PB19
NVDD4
B10
CSI_D6
I
PB18 PUEN
Pull-H
PB18
NVDD4
H9
CSI_D5
I
PB17 PUEN
Pull-H
PB17
NVDD4
A9
CSI_PIXCLK
I
PB16 PUEN
Pull-H
PB16
NVDD4
C9
CSI_MCLK
O
PB15 PUEN
Pull-H
PB15
NVDD4
B9
CSI_D4
I
PB14 PUEN
Pull-H
PB14
NVDD4
G9
CSI_D3
I
PB13 PUEN
Pull-H
PB13
NVDD4
D9
CSI_D2
I
PB12 PUEN
Pull-H
PB12
NVDD4
C8
CSI_D1
I
PB11 PUEN
Pull-H
PB11
NVDD4
A8
CSI_D0
I
PB10 PUEN
Pull-H
NVSS4
K8
NVSS4
NVDD4
PB10
NVSS4
Signal Descriptions and Pin Assignments
2-17
NVDD3
NVDD4
Reset
(At/After)
BOUT
AOUT
CIN
BIN
AIN
PU
Mux
OD
GPIO
PU
Signal
Dir
OD
K9
PU
QVDDX
Signal
Alternate
Dir
BGA
Pins
Primary
I/O
Supply
Voltage
QVDDX
Default
QVDDX
i.MX21 Reference Manual, Rev. 3
QVSS
M10
QVSS
QVSS
NVDD5
J8
NVDD5
NVDD5
NVDD5
D8
SD2_CLK
O
PB9 PDEN
SLCDC1_CLK
Pull-L
PB9
NVDD5
B8
SD2_CMD
B
PB8 PUEN
SLCDC1_CS
Pull-H
PB8
NVDD5
C7
SD2_D3
B
PB7 PUEN
SLCDC1_RS
Pull-H
PB7
NVDD5
A7
SD2_D2
B
PB6 PUEN
SLCDC1_D0
Pull-H
PB6
NVDD5
D7
SD2_D1
B
PB5 PUEN
Pull-H
PB5
NVDD5
B7
SD2_D0
B
PB4 PUEN
Pull-H
PB4
PA31 PUEN
Pull-H
PA31
Pull-H
PA30
Pull-H
PA29
NVSS5
H8
NVSS5
NVDD6
A6
OE_ACD
O
NVDD6
B6
CONTRAST
O
BMI_READ
O
PA30 PUEN
O
BMI_RXF_FUL
L
O
PA29 PUEN
NVDD6
C6
VSYNC
NVSS5
BMI_WAIT
NVDD6
A5
HSYNC
O
PA28 PUEN
Pull-H
PA28
NVDD6
E4
SPL_SPR
O
PA27 PDEN
SLCDC1_CLK
Pull-L
PA27
NVDD6
B5
PS
O
PA26 PDEN
SLCDC1_CS
Pull-L
PA26
NVDD6
D4
CLS
O
PA25 PDEN
SLCDC1_RS
Pull-L
PA25
PA24 PDEN
SLCDC1_D0
NVDD6
A4
REV
O
Pull-L
PA24
NVDD6
C5
LD17
O
BMI_WRITE
B
PA23 PUEN
Pull-H
PA23
O
PA22 PUEN EXT_DMAGRANT
Pull-H
PA22
Freescale Semiconductor
NVDD6
B4
LD16
O
BMI_READ_R
EQ
NVDD6
E3
LD15
O
BMI_D15
B
PA21 PUEN
SLCDC1_DAT15
SLCDC1_
DAT7
Pull-H
PA21
NVDD6
A3
LD14
O
BMI_D14
B
PA20 PUEN
SLCDC1_DAT14
SLCDC1_
DAT6
Pull-H
PA20
NVDD6
D3
LD13
O
BMI_D13
B
PA19 PUEN
SLCDC1_DAT13
SLCDC1_
DAT5
Pull-H
PA19
NVDD6
A2
LD12
O
BMI_D12
B
PA18 PUEN
SLCDC1_DAT12
SLCDC1_
DAT4
Pull-H
PA18
NVSS6
G8
NVSS6
NVDD6
G7
NVDD6
NVSS6
NVDD6
NVDD6
B3
LD11
O
BMI_D11
B
PA17 PUEN
SLCDC1_DAT11
SLCDC1_
DAT3
NVDD6
C4
LD10
O
BMI_D10
B
PA16 PUEN
SLCDC1_DAT10
SLCDC1_
DAT2
Pull-H
PA17
Pull-H
PA16
Signal Descriptions and Pin Assignments
2-18
Table 2-2. i.MX21 Signal Multiplexing Scheme (continued)
(Note: See end of table for table footnotes and table legend)
Dir
Reset
(At/After)
i.MX21 Reference Manual, Rev. 3
Default
Signal
O
BMI_D9
B
PA15 PUEN
SLCDC1_DAT9
SLCDC1_
DAT1
Pull-H
PA15
LD8
O
BMI_D8
B
PA14 PUEN
SLCDC1_DAT8
SLCDC1_
DAT0
Pull-H
PA14
B1
LD7
O
BMI_D7
B
PA13 PUEN
SLCDC1_DAT7
Pull-H
PA13
C3
LD6
O
BMI_D6
B
PA12 PUEN
SLCDC1_DAT6
Pull-H
PA12
B2
LD5
O
BMI_D5
B
PA11 PUEN
SLCDC1_DAT5
Pull-H
PA11
NVDD6
E2
LD4
O
BMI_D4
B
PA10 PUEN
SLCDC1_DAT4
Pull-H
PA10
NVDD6
C2
LD3
O
BMI_D3
B
PA9
PUEN
SLCDC1_DAT3
Pull-H
PA9
NVDD6
D1
LD2
O
BMI_D2
B
PA8
PUEN
SLCDC1_DAT2
Pull-H
PA8
NVDD6
C1
LD1
O
BMI_D1
B
PA7
PUEN
SLCDC1_DAT1
Pull-H
PA7
NVDD6
D2
LD0
O
BMI_D0
B
PA6
PUEN
SLCDC1_DAT0
NVDD6
F4
LSCLK
O
BMI_CLK_CS
B
PA5
PUEN
BOUT
AOUT
CIN
BIN
NVDD6
AIN
NVDD6
PU
NVDD6
Mux
E1
OD
LD9
GPIO
PU
A1
OD
NVDD6
Signal
Dir
NVDD6
Alternate
PU
Primary
I/O
Supply
Voltage
BGA
Pins
Freescale Semiconductor
Table 2-2. i.MX21 Signal Multiplexing Scheme (continued)
(Note: See end of table for table footnotes and table legend)
Pull-H
PA6
Pull-H
PA5
2-19
Signal Descriptions and Pin Assignments
KP- Keeper Circuit permanently On when in Primary / Alternate Mode.
PU-Pull Up permanently On when in Primary / Alternate Mode.
PUEN-Pull Up controllable from Module when in Primary / Alternate Mode.
OD-Open Drain permanently On when in Primary / Alternate Mode.
ODEN-Open Drain controllable from Module when in Primary / Alternate Mode.
1. Data Bus resets to a keeper circuit (state retention circuit) and input.
2. At POR, SDCLK is low then toggles for approximately 300ms during chip reset, then idles at logic high.
3. The default for this signal is as an input and is pulled high internally. To enable the GPIO PF16 function, the user must set bit 16 in the GPIO In Use Register
Port F. However, if this signal is not used, then it may be left as a no connect.
4. Refer to section 2.4 for recommended termination of these signals.
5. Reset-in and POR need to be connected to reset circuitry.
6. Boot signals should be connected to logic high or low depending on customer applications. Boot 3 should always be tied low.
Signal Descriptions and Pin Assignments
2.3
Power-Up Sequence
The i.MX21 processor consists of three major sets for power supply voltage named QVDD (core logic
supply), VDDA (analog supply), and NVDD (IO supply). The External Voltage Regulators and power-on
devices must provide the applications processor with a specific sequence of power and resets to ensure
proper operation.
It is important that the applications processor power supplies be powered-up in a certain order to avoid
high current situations. The required order is:
1. NVDD (1.8/3.0V) and VDDA (formally AVDD) (3.0V)
2. QVDD (1.5V) and QVDDX (1.5V)
2.4
Package Information
Table 2-3 identifies the pin assignments for the ball grid array (BGA). The connections of these pins
depend solely upon the user application, however there are a few factory test signals that are not used in a
normal application. Following is a list of these signals and how they are to be terminated for proper
operation of the i.MX21 processor:
• CLKMODE[1:0]: To ensure proper operation, leave these signals as no connects.
• OSC26M_TEST: To ensure proper operation, leave this signal as no connect.
• EXT_48M: To ensure proper operation, connect this signal to ground.
• EXT_266M: To ensure proper operation, connect this signal to ground.
• TEST_WB[2:0]: These signals are also multiplexed with GPIO PORT E as well as alternate
keypad signals. If not utilizing these signals for GPIO functionality or for their other multiplexed
function, then configure as GPIO input with pull up enabled, and leave as a no connect.
• TEST_WB[4:3]: To ensure proper operation, leave these signals as no connects.
Most of the signals shown in Table 2-3 are multiplexed with other signals. For simplicity only the primary
signal names are shown. Please refer to Table 2-2 for complete information on the signal multiplexing
schemes of these signals.
i.MX21 Reference Manual, Rev. 3
2-20
Freescale Semiconductor
Freescale Semiconductor
Table 2-3. i.MX21 Pin Assignment
1
2
3
4
5
6
OE_
ACD
7
8
9
10
SD2_D2
CSI_
D0
CSI_
PIXCLK
CSI_
VSYNC
11
12
USBH1_ USBH1_
FS
OE
14
15
16
17
18
19
USBG_
FS
13
TOUT
SAP_
TXDAT
SSI1_
CLK
SSI2_
RXDAT
SSI2_TXDAT
SSI3_
FS
i.MX21 Reference Manual, Rev. 3
LD9
LD12
LD14
REV
HSYNC
B
LD7
LD5
LD11
LD16
PS
CON
SD2_D0
TRAST
SD2_
CMD
CSI_
D4
CSI_D6
USB_
PWR
USBG_
SCL
USBG_
TXDM
SAP_
FS
SSI1_
FS
SSI2_
FS
SSI3_
TXDAT
I2C_DATA
CSPI2_
SS2
C
LD1
LD3
LD6
LD10
LD17
VSYNC SD2_D3
CSI_
D1
CSI_
MCLK
CSI_
HSYNC
USB_
OC
USBH1_
RXDM
USBG_
RXDM
TIN
SSI1_
TXDAT
SSI3_
RXDAT
SSI3_
CLK
I2C_CLK
CSPI2_
SS1
D
LD2
LD0
LD13
CLS
QVDD
SD2_
CLK
CSI_
D2
CSI_D7
USBH1_ USBH1_
TXDM
RXDP
USBG_
ON
USBG_
RXDP
SAP_
RXDAT
SSI1_
RXDAT
SSI2_
CLK
CSPI2_SS0
CSPI2_
SCLK
E
LD8
LD4
LD15
SPL_
SPR
SAP_
CLK
CSPI2_
MISO
CSPI1_SS2
CSPI2_
MOSI
F
A24_
NFIO14
D31
A25_
LSCLK
NFIO15
CSPI1_
SS1
CSPI1_
MISO
KP_ROW0
CSPI1_
SS0
G
A22_
NFIO12
D29
A23_
NFIO13
D30
NVDD6
NVSS6
CSI_D3
USB_
BYP
USBH_
ON
USBG_
SDA
USBG_
TXDP
KP_
ROW1
KP_
ROW3
UART2_CTS
KP_
ROW4
H
A20
D27
A21_
NFIO11
D28
NVDD1
NVSS5
CSI_D5
CSPI1_
SCLK
CSPI1_
RDY
USBH1_
TXDP
USBG_
OE
TEST_
WB4
TEST_
WB2
TEST_WB3
PWMO
J
A19
A18
D25
D26
NVDD1 NVDD5
NVDD4
KP_
ROW5
KP_
ROW2
CSPI1_
MOSI
TEST_
WB0
KP_COL0
TEST_
WB1
K
A16
A17
D23
D24
NVSS1
NVSS4
QVDDX
UART1_
RXD
TDO
QVDD
QVSS
KP_
COL3
KP_COL5
KP_COL4
KP_
COL2
L
A14_
NFIO9
A15_
NFIO10
D21
D22
NVSS1
NVDD3
QVDD
QVSS
NFIO2
NFWP
UART1_
TXD
UART2_
TXD
UART3_
RTS
UART3_CTS
UART3_
TXD
M
D19
A13_
NFIO8
D20
D18
NVDD2 NVDD3
NVSS3
QVSS
NFIO7
NFRB
EXT_
48M
UART2_
RXD
UART3_
RXD
UART1_RTS
UART1_
CTS
N
A11
A12
D17
D16
NVSS1
NVSS1
NVDD1
NVDD1
SD1_
D0
TCK
SD1_D1
RTCK
P
A9
A10
D15
D14
SD1_
D2
SD1_
CMD
TDI
TMS
R
A7
A8
D13
D12
SD1_
CLK
EXT_
266M
NVSS2
TRST
T
A5
A6
EB3
D10
CS3
CS1
BCLK
MA11
RAS
CAS
NFIO5
NFIO3
NFWE
RESET_
IN
NFCE
BOOT1
SD1_D3
CLKMODE1
CLK
MODE0
U
D11
EB1
EB2
OE
CS4
D6
ECB
D3
MA10
PC_
PWRON
PF16
NFIO4
NFIO1
NFALE
NFCLE
POR
BOOT2
BOOT3
XTAL32K
V
A4
EB0
D9
D8
CS5
D5
CS0
RW
D1
JTAG_
CTRL
SDWE
CLKO
NFIO6
QVSS
RESET_
OUT
BOOT0
OSC26M_
TEST
VDDA
EXTAL
32K
W
A3
A2
D7
A1
CS2
A0
D4
D2
D0
SDCLK
SDCKE1
NFIO0
NFRE
QVDD
QVSS
EXTAL
26M
XTAL26M
QVDD
QVSS
QVSS
SD2_D1
LBA
NVSS3 SDCKE0
UART2_
KP_COL1
RTS
2-21
Signal Descriptions and Pin Assignments
A
Signal Descriptions and Pin Assignments
i.MX21 Reference Manual, Rev. 3
2-22
Freescale Semiconductor
Chapter 3
Memory Map
This chapter describes the memory maps and the chip configuration registers of the i.MX21 processor.
3.1
Memory Space
Figure 3-1 on page 3-2 shows a detailed block diagram of the interconnection of the various modules in
i.MX21. The i.MX21 with a 32-bit address bus is capable of addressing a 4 Gbyte physical address space.
This space is divided into sections of 512 Mbyte regions within which various memories and peripherals
are mapped.
Table 3-1 shows a simplified breakdown of the eight 512 Mbyte regions decoded within the 4 Gbyte
address space.
Table 3-1. 4 Gbyte Memory Map Breakdown
3.1.1
Address
Size
Usage
0x00000000
512 Mbyte
ROM, Primary AHB Slaves, and Peripherals
0x20000000
512 Mbyte
Reserved
0x40000000
512 Mbyte
Reserved
0x60000000
512 Mbyte
Reserved
0x80000000
512 Mbyte
Secondary AHB Slave Port 1
0xA0000000
512 Mbyte
Secondary AHB Slave Port 2
0xC0000000
512 Mbyte
Secondary AHB Slave Port 3
0xE0000000
512 Mbyte
Primary AHB (RAM)
Detailed Memory Map
Figure 3-2 on page 3-3 shows the memory space breakout view for i.MX21. The left-most column shows
the eight 512 Mbyte regions. The middle column shows the breakout of primary and secondary AHB
slaves and the right-most column shows the breakout of the AIPI1 and AIPI2 address spaces.
Table 3-2 to Table 3-6 show the detailed breakdown of the complete memory map according to the
512 Mbyte regions. Table 3-7 and Table 3-8 show the detailed breakdown of the AIPI1 and AIPI2 modules
and the different IP peripherals accessed over the AIPI1 and AIPI2.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-1
Memory Map
IP Module
AHB Master Module
Memory
AHB-Lite Slave Module
Misc. Blocks
Analog Blocks
DFTCHOP
UDPLL
OSC32K
CPUMP
TCU
OSC26M
IOPAD
SLID
SROUTER
MDPLL
FPM
JTAGC
IOMUX
AUDMUX
WDOG
IPMUX
GPT1
Notes
• eMMA includes PP, PRP, VENC, VDEC
• EMI includes WEIM, SDRC, PCMCIA &
NANDFC
• ABCD includes Address Decoder, AHB
Mux, Arbiter & Bus Watchdog Timer
GPT2
ARM926 PLATFORM
PATCH
GPT3
PAHBMUX
REAL TIME DBG I/F
LCDC
SLCDC
NEXUS
0
ARB1
1
NEX
DMA
AIPI#2
BROM
PWM
VRAM
RTC
AIPI#1
ARM926EJ-S
MCTL
USBOTG
TARB
AITC
KPP
PRIMARY AHB
DMA
I-AHB
D-AHB
ABM1
eMMA
ABM2
ABM3
ABM4
CRM
CCM
FIRI
0
1
2
3
4
5
0
SEC
ABCD
Secondary AHB1
1
CSI
1-WIRE
BWT
ADEC
Secondary AHB2
2
BMI
BWT
UART1
ADEC
Secondary AHB3
3
BWT
EMI
ADEC
6 X 4 AHB CROSS-BAR-SWITCH
UART2
UART3
UART4
GPIO
SDHC2
SDHC1
I2C
SSI2
SSI1
CSPI3
CSPI2
CSPI1
Figure 3-1. Memory Space Breakout View for i.MX21
NOTE
Accesses to locations defined as Reserved (other than aliased RAM space)
results in an AHB error response. Accesses to unimplemented locations
within the AITC and ROMPATCH register space will be terminated and
write accesses will have no effect and read accesses will return all zeros.
i.MX21 Reference Manual, Rev. 3
3-2
Freescale Semiconductor
Memory Map
Base Address
$1002 0000
$1002 0FFF
16 Kbyte
$0000 0000
$1000 0000
BROM
$0000 3FFF
AIPI1
4 Mbyte
$0000 4000
128 Kbyte $1000 0FFF
$1000 1000
$1000 0000
$1000 1FFF
$1000 2000
Reserved
$0040 3FFF
$1001 FFFF
$1002 0000
BROM
$007F FFFF
$0080 0000
Reserved
$0FFF FFFF
$1000 0000
$1004 0FFF
$1004 1000
$1004 1FFF
$1004 2000
272 Kbyte
Internal
Registers
$1000 3FFF
4 Kbyte
$1003 FFFF
$1004 0000
248 Mbyte
$1004 2FFF
$1004 3000
$1004 3FFF
AITC
4 Kbyte
Reserved
4 Kbyte
Reserved
4 Kbyte
752 Kbyte
64 Mbyte
$C000 0000
$1000 7000
$1000 7FFF
$1000 C000
$1000 DFFF
$1000 E000
64 Mbyte
Reserved
$1000 FFFF
$1001 0000
64 Mbyte
CS1
(Flash)
active low
$CFFF FFFF
$D000 0000
CSI (4KB)
Reserved
BMI (4KB)
$C000 0000
External
Memory
(384 Mbyte)
512 Mbyte
$D7FF FFFF
512 Mbyte
VRAM
(6 Kbyte)
$1001 9000
$1001 A000
$1001 AFFF
$1001 B000
$1001 BFFF
$1001 C000
$1001 CFFF
$1001 D000
Reserved
Reserved
$1001 8FFF
$1001 9FFF
64 Mbyte
PCMCIA/CF
Reserved
EMI (16 Kbyte)
$1001 7000
$1001 8000
16 Mbyte
$D3FF FFFF
$D400 0000
$1001 6FFF
$1001 7FFF
CS5
(Spare)
active low
Reserved
$1001 5000
$1001 6000
16 Mbyte
$D2FF FFFF
$D300 0000
$1001 4FFF
$1001 5FFF
CS4
(Spare)
active low
512 Mbyte
$1001 3000
$1001 4000
16 Mbyte
$D1FF FFFF
$D200 0000
$1001 2FFF
$1001 3FFF
CS3
(Spare)
active low
512 Mbyte
$1001 1000
$1001 2000
CS2
(Ext SRAM)
active low
$7FFF FFFF
$1001 0FFF
$1001 1FFF
16 Mbyte
$D0FF FFFF
$D100 0000
$1000 EFFF
$1000 F000
CS0
(Flash)
active low
$CBFF FFFF
$CC00 0000
$1000 CFFF
$1000 D000
CSD1
(SDRAM)
active low
1536MB
$1000 AFFF
$1000 BFFF
64 Mbyte
$C7FF FFFF
$C800 0000
$FFFF FFFF
$1000 6FFF
$1000 B000
CSD0
(SDRAM)
active low
$C3FF FFFF
$C400 0000
$2000 0000
$E000 0000
$1000 6000
$1000 A000
$1FFF FFFF
$DFFF FFFF
$1000 5FFF
$1000 9FFF
Reserved
$BFFF FFFF
$1000 5000
$1000 9000
255 Mbyte +
$A000 0000
$1000 4FFF
$1000 8FFF
$1004 4000
$9FFF FFFF
$1000 4000
$1000 8000
Reserved
$1004 3FFF
$8000 0000
$1000 2FFF
$1000 3000
AIPI2
3 Mbyte +
1008 Kbyte
$0040 4000
128 Kbyte
$1001 DFFF
$1001 E000
$1001 EFFF
$1001 F000
$1001 FFFF
$1002 1000
AIPI1
AIPI2
DMA
LCDC
WDOG
SLCDC
GPT1
Reserved
$1002 4000
GPT2
USBOTG
$1002 5000
GPT3
USBOTG
$1002 6000
PWM
eMMA
$1002 7000
RTC
CRM
$1002 8000
KPP
FIRI
$1002 9000
OWIRE
Reserved
$1002 A000
UART1
Reserved
$1002 B000
UART2
Reserved
$1002 C000
UART3
Reserved
$1002 D000
UART4
Reserved
$1002 E000
CSPI1
Reserved
$1002 F000
CSPI2
Reserved
SSI1
Reserved
SSI2
Reserved
I2C
Reserved
SDHC1
Reserved
SDHC2
Reserved
GPIO
Reserved
AUDMUX Reserved
CSPI3
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved
CS5Reserved
(Spare)
active low
Reserved
JAM
Reserved
$1002 1FFF
$1002 2000
$1002 2FFF
$1002 3000
$1002 3FFF
$1002 4FFF
$1002 5FFF
$1002 6FFF
$1002 7FFF
$1002 8FFF
$1002 9FFF
$1002 AFFF
$1002 BFFF
$1002 CFFF
$1002 DFFF
$1002 EFFF
$1002 FFFF
$1003 0000
$1003 0FFF
$1003 1000
$1003 1FFF
$1003 2000
$1003 2FFF
$1003 3000
$1003 3FFF
$1003 4000
$1003 4FFF
$1003 5000
$1003 5FFF
$1003 6000
$1003 6FFF
$1003 7000
$1003 7FFF
$1003 8000
$1003 8FFF
$1003 9000
$1003 9FFF
$1003 A000
$1003 AFFF
$1003 B000
$1003 BFFF
$1003 C000
$1003 CFFF
$1003 D000
$1003 DFFF
$1003 E000
$1003 EFFF
$1003 F000
$1003 FFFF
MAX
Figure 3-2. i.MX21 Physical Memory Map (4 Gbyte)
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-3
Memory Map
Table 3-2. Primary AHB Memory Map (Lower)
Address
Secondary AHB Slave Port 1
Size
0x0000 0000 – 0x0000 3FFF
BROM
16 Kbyte
0x0000 4000 – 0x0040 3FFF
Reserved
4 Mbyte
0x0040 4000 – 0x0040 5FFF
BROM
8 Kbyte
0x0040 6000 – 0x007F FFFF
BROM (Hole)
3MB + 1000 Kbyte
0x0080 0000 – 0x0FFF FFFF
Reserved
248 Mbyte
0x1000 0000 – 0x1001 FFFF
AIPI1
128 Kbyte
0x1002 0000 – 0x1003 FFFF
AIPI2
128 Kbyte
0x1004 0000 – 0x1004 0FFF
AITC
4 Kbyte
0x1004 1000 – 0x1004 1FFF
Reserved
4 Kbyte
0x1004 2000 – 0x1004 2FFF
Reserved
4 Kbyte
0x1004 3000 – 0x1004 3FFF
Reserved
4 Kbyte
0x1004 4000 – 0x7FFF FFFF
Reserved
255 Mbyte + 752 Kbyte
Table 3-2 shows the memory map of the Primary AHB address space in the first 512 Mbyte region. The
BROM is split into two sections of 16 Kbyte and 8 Kbyte. The BROM (Hole) indicates that there is no
BROM code present in this region. The AIPI1 and AIPI2 address space contains AIPI control registers and
the IP slave registers. The AIPI1 and AIPI2 maps are shown in Table 3-7 and Table 3-8, respectively.
Table 3-3. Secondary AHB Port 1 Memory Map
Address
Secondary AHB Port 1
Size
0x8000 0000 – 0x8000 0FFF
CSI
4 Kbyte
0x8000 1000 – 0x9FFF FFFF
Reserved
511 Mbyte + 1020 Kbyte
Table 3-3 and Table 3-4 show the CSI and BMI modules connected to the Secondary AHB Ports 1 and 2
respectively. The CSI and BMI do not have an IP interface and are accessed directly over the AHB.
Table 3-4. Secondary AHB Port 2 Memory Map
Address
Secondary AHB Slave Port 2
Size
0xA000 0000 – 0xA000 0FFF
BMI
4 Kbyte
0xA000 1000 – 0xBFFF FFFF
Reserved
511 Mbyte + 1020 Kbyte
Table 3-5 shows the memory map breakdown for the Secondary AHB Port 3. The SDRAMC, WEIM,
PCMCIA and NANDFC module control registers and external memory are addressed via this region. The
external memory regions (memory or external peripherals) are accessed via the respective chip selects.
CSD1 and CSD0 are SDRAMC chip selects and CS5 to CS0 WEIM Chip Selects. CSD1 and CS0 chip
select spaces are available for external boot.
0xD4000 0000 to 0xD7FF_FFFF is allocated for PCMCIA IO and Memory Space.
i.MX21 Reference Manual, Rev. 3
3-4
Freescale Semiconductor
Memory Map
Table 3-5. Secondary AHB Port 3 Memory Map
Address
Secondary AHB Port 3
Size
0xC000 0000 – 0xC3FF FFFF
External Memory (CSD0)
64 Mbyte
0xC400 0000 – 0xC7FF FFFF
External Memory (CSD1)
64 Mbyte
0xC800 0000 – 0xCBFF FFFF
External Memory (CS0)
64 Mbyte
0xCC00 0000 – 0xCFFF FFFF
External Memory (CS1)
64 Mbyte
0xD000 0000 – 0xD0FF FFFF
External Memory (CS2)
16 Mbyte
0xD100 0000 – 0xD1FF FFFF
External Memory (CS3)
16 Mbyte
0xD200 0000 – 0xD2FF FFFF
External Memory (CS4)
16 Mbyte
0xD300 0000 – 0xD3FF FFFF
External Memory (CS5)
16 Mbyte
0xD400 0000 – 0xD7FF FFFF
PCMCIA/CF IO and Memory Space
64 Mbyte
0xD800 0000 – 0xDEFF FFFF
Reserved
112 Mbyte
0xDF00 0000 – 0xDF00 0FFF
SDRAMC
4 Kbyte
0xDF00 1000 – 0xDF00 1FFF
EIM
4 Kbyte
0xDF00 2000 – 0xDF00 2FFF
PCMCIA
4 Kbyte
0xDF00 3000 – 0xDF00 3FFF
NANDFC
4 Kbyte
0xDF00 4000 – 0xDFFF FFFF
Reserved
15 Mbyte + 1008 Kbyte
Table 3-6 shows the last region of address space that is part of the Primary AHB Memory Map. The
Vector-RAM is mapped into this region and i.MX21 uses the high memory (0xFFFF FF00 to 0xFFFF
FFFF) to store the interrupt vector table (64 words). This region is aliased on a 128 Kbyte boundary.
Table 3-6. Primary AHB Memory Map (Upper)
Address
Primary AHB
Size
0xE000 0000 – 0xFFFF E7FF
Reserved (aliased)
511 Mbyte + 1018 Kbyte
0xFFFF E800 – 0xFFFF FFFF
VRAM
6 Kbyte
The next two tables, Table 3-7 and Table 3-8 show the detailed break down of the address space controlled
by AIPI1 and AIPI2. More details on the AIPI can be found in the AIPI chapter.
Table 3-7. AIPI1 Memory Map
Address
AIPI1 Memory Map
Size
0x1000 0000 – 0x1000 0FFF
AIPI1 (Slot 0)
4 Kbyte
0x1000 1000 – 0x1000 1FFF
DMA
4 Kbyte
0x1000 2000 – 0x1000 2FFF
WDOG
4 Kbyte
0x1000 3000 – 0x1000 3FFF
GPT1
4 Kbyte
0x1000 4000 – 0x1000 4FFF
GPT2
4 Kbyte
0x1000 5000 – 0x1000 5FFF
GPT3
4 Kbyte
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-5
Memory Map
Table 3-7. AIPI1 Memory Map (continued)
Address
AIPI1 Memory Map
Size
0x1000 6000 – 0x1000 6FFF
PWM
4 Kbyte
0x1000 7000 – 0x1000 7FFF
RTC
4 Kbyte
0x1000 8000 – 0x1000 8FFF
KPP
4 Kbyte
0x1000 9000 – 0x1000 9FFF
OWIRE
4 Kbyte
0x1000 A000 – 0x1000 AFFF
UART1
4 Kbyte
0x1000 B000 – 0x1000 BFFF
UART2
4 Kbyte
0x1000 C000 – 0x1000 CFFF
UART3
4 Kbyte
0x1000 D000 – 0x1000 DFFF
UART4
4 Kbyte
0x1000 E000 – 0x1000 EFFF
CSPI1
4 Kbyte
0x1000 F000 – 0x1000 FFFF
CSPI2
4 Kbyte
0x1001 0000 – 0x1001 0FFF
SSI1
4 Kbyte
0x1001 1000 – 0x1001 1FFF
SSI2
4 Kbyte
0x1001 2000 – 0x1001 2FFF
I2C
4 Kbyte
0x1001 3000 – 0x1001 3FFF
SDHC1
4 Kbyte
0x1001 4000 – 0x1001 4FFF
SDHC2
4 Kbyte
0x1001 5000 – 0x1001 5FFF
GPIO
4 Kbyte
0x1001 6000 – 0x1001 6FFF
AUDMUX
4 Kbyte
0x1001 7000 – 0x1001 7FFF
CSPI3
4 Kbyte
0x1001 7000 – 0x1001 FFFF
Reserved (Slot 24–31)
8 × 4 Kbyte (32 Kbyte)
Table 3-8. AIPI2 Memory Map
Address
AIPI2 Memory Map
Size
0x1002 0000 – 0x1002 0FFF
AIPI2 (Slot 0)
4 Kbyte
0x1002 1000 – 0x1002 1FFF
LCDC
4 Kbyte
0x1002 2000 – 0x1002 2FFF
SLCDC
4 Kbyte
0x1002 3000 – 0x1002 3FFF
Reserved
4 Kbyte
0x1002 4000 – 0x1002 4FFF
USB OTG
4 Kbyte
0x1002 5000 – 0x1002 5FFF
USB OTG
4 Kbyte
0x1002 6000 – 0x1002 6FFF
eMMA
4 Kbyte
0x1002 7000 – 0x1002 7FFF
CRM
4 Kbyte
0x1002 8000 – 0x1002 8FFF
FIRI
4 Kbyte
0x1002 B000 – 0x1002 DFFF
Reserved (Slots 11–29)
76 Kbyte
i.MX21 Reference Manual, Rev. 3
3-6
Freescale Semiconductor
Memory Map
Table 3-8. AIPI2 Memory Map (continued)
Address
AIPI2 Memory Map
Size
0x1003 E000 – 0x1003 EFFF
JAM
4 Kbyte
0x1003 F000 – 0x1003 FFFF
MAX
4 Kbyte
3.2
Register Map
The internal registers in the i.MX21 are listed in Table 3-9.
Table 3-9. Register Map
Module Name
Address
Register Name
Description
AIPI1
0x1000 0000
PSR0
Peripheral Size Register0
AIPI1
0x1000 0004
PSR1
Peripheral Size Register1
AIPI1
0x1000 0008
PAR
Peripheral Access Register
DMAC
0x1000 1000
DCR
DMA Control Register
DMAC
0x1000 1004
DISR
DMA Interrupt Status Register
DMAC
0x1000 1008
DIMR
DMA Interrupt Mask Register
DMAC
0x1000 100C
DBTOSR
DMA Burst Time-Out Status Register
DMAC
0x1000 1010
DRTOSR
DMA Request Time-Out Status Register
DMAC
0x1000 1014
DSESR
DMA Transfer Error Status Register
DMAC
0x1000 1018
DBOSR
DMA Buffer Overflow Status Register
DMAC
0x1000 101C
DBTOCR
DMA Burst Time-Out Control Register
DMAC
0x1000 1040
WSRA
W-Size Register A
DMAC
0x1000 1044
XSRA
X-Size Register A
DMAC
0x1000 1048
YSRA
Y-Size Register A
DMAC
0x1000 104C
WSRB
W-Size Register B
DMAC
0x1000 1050
XSRB
X-Size Register B
DMAC
0x1000 1054
YSRB
Y-Size Register B
DMAC
0x1000 1080
SAR0
Channel 0 Source Address Register
DMAC
0x1000 1084
DAR0
Channel 0 Destination Address Register
DMAC
0x1000 1088
CNTR0
Channel 0 Count Register
DMAC
0x1000 108C
CCR0
Channel 0 Control Register
DMAC
0x1000 1090
RSSR0
DMAC
0x1000 1094
BLR0
DMAC
0x1000 1098
RTOR0
BUCR0
Channel 0 Request Time-Out Register
Channel 0 Bus Utilization Control Register
DMAC
0x1000 109C
CCNR0
Channel 0 Channel Counter Register
Channel 0 Request Source Select Register
Channel 0 Burst Length Register
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-7
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
DMAC
0x1000 10C0
SAR1
Channel 1 Source Address Register
DMAC
0x1000 10C4
DAR1
Channel 1 Destination Address Register
DMAC
0x1000 10C8
CNTR1
Channel 1 Count Register
DMAC
0x1000 10CC
CCR1
Channel 1 Control Register
DMAC
0x1000 10D0
RSSR1
DMAC
0x1000 10D4
BLR1
DMAC
0x1000 10D8
RTOR1
BUCR1
Channel 1 Request Time-Out Register
Channel 1 Bus Utilization Control Register
DMAC
0x1000 10DC
CCNR1
Channel 1 Channel Counter Register
DMAC
0x1000 1100
SAR2
Channel 2 Source Address Register
DMAC
0x1000 1104
DAR2
Channel 2 Destination Address Register
DMAC
0x1000 1108
CNTR2
Channel 2 Count Register
DMAC
0x1000 110C
CCR2
Channel 2 Control Register
DMAC
0x1000 1110
RSSR2
DMAC
0x1000 1114
BLR2
DMAC
0x1000 1118
RTOR2
BUCR2
Channel 2 Request Time-Out Register
Channel 2 Bus Utilization Control Register
DMAC
0x1000 111C
CCNR2
Channel 2 Channel Counter Register
DMAC
0x1000 1140
SAR3
Channel 3 Source Address Register
DMAC
0x1000 1144
DAR3
Channel 3 Destination Address Register
DMAC
0x1000 1148
CNTR3
Channel 3 Count Register
DMAC
0x1000 114C
CCR3
Channel 3 Control Register
DMAC
0x1000 1150
RSSR3
DMAC
0x1000 1154
BLR3
DMAC
0x1000 1158
RTOR3
BUCR3
Channel 3 Request Time-Out Register
Channel 3 Bus Utilization Control Register
DMAC
0x1000 115C
CCNR3
Channel 3 Channel Counter Register
DMAC
0x1000 1180
SAR4
Channel 4 Source Address Register
DMAC
0x1000 1184
DAR4
Channel 4 Destination Address Register
DMAC
0x1000 1188
CNTR4
Channel 4 Count Register
DMAC
0x1000 118C
CCR4
Channel 4 Control Register
DMAC
0x1000 1190
RSSR4
DMAC
0x1000 1194
BLR4
Channel 1 Request Source Select Register
Channel 1 Burst Length Register
Channel 2 Request Source Select Register
Channel 2 Burst Length Register
Channel 3 Request Source Select Register
Channel 3 Burst Length Register
Channel 4 Request Source Select Register
Channel 4 Burst Length Register
i.MX21 Reference Manual, Rev. 3
3-8
Freescale Semiconductor
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
DMAC
0x1000 1198
RTOR4
BUCR4
Channel 4 Request Time-Out Register
Channel 4 Bus Utilization Control Register
DMAC
0x1000 119C
CCNR 4
Channel 4 Channel Counter Register
DMAC
0x1000 11C0
SAR5
Channel 5 Source Address Register
DMAC
0x1000 11C4
DAR5
Channel 5 Destination Address Register
DMAC
0x1000 11C8
CNTR5
Channel 5 Count Register
DMAC
0x1000 11CC
CCR5
Channel 5 Control Register
DMAC
0x1000 11D0
RSSR5
DMAC
0x1000 11D4
BLR5
DMAC
0x1000 11D8
RTOR5
BUCR5
Channel 5 Request Time-Out Register
Channel 5 Bus Utilization Control Register
DMAC
0x1000 11DC
CCNR5
Channel 5 Channel Counter Register
DMAC
0x1000 1200
SAR6
Channel 6 Source Address Register
DMAC
0x1000 1204
DAR6
Channel 6 Destination Address Register
DMAC
0x1000 1208
CNTR6
Channel 6 Count Register
DMAC
0x1000 120C
CCR6
Channel 6 Control Register
DMAC
0x1000 1210
RSSR6
DMAC
0x1000 1214
BLR6
DMAC
0x1000 1218
RTOR6
BUCR6
Channel 6 Request Time-Out Register
Channel 6 Bus Utilization Control Register
DMAC
0x1000 121C
CCNR6
Channel 6 Channel Counter Register
DMAC
0x1000 1240
SAR7
Channel 7 Source Address Register
DMAC
0x1000 1244
DAR7
Channel 7 Destination Address Register
DMAC
0x1000 1248
CNTR7
Channel 7 Count Register
DMAC
0x1000 124C
CCR7
Channel 7 Control Register
DMAC
0x1000 1250
RSSR7
DMAC
0x1000 1254
BLR7
DMAC
0x1000 1258
RTOR7
BUCR7
Channel 7 Request Time-Out Register
Channel 7 Bus Utilization Control Register
DMAC
0x1000 125C
CCNR7
Channel 7 Channel Counter Register
DMAC
0x1000 1280
SAR8
Channel 8 Source Address Register
DMAC
0x1000 1284
DAR8
Channel 8 Destination Address Register
DMAC
0x1000 1288
CNTR8
Channel 8 Count Register
DMAC
0x1000 128C
CCR8
Channel 8 Control Register
Channel 5 Request Source Select Register
Channel 5 Burst Length Register
Channel 6 Request Source Select Register
Channel 6 Burst Length Register
Channel 7 Request Source Select Register
Channel 7 Burst Length Register
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-9
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
DMAC
0x1000 1290
RSSR8
DMAC
0x1000 1294
BLR8
DMAC
0x1000 1298
RTOR8
BUCR8
Channel 8 Request Time-Out Register
Channel 8 Bus Utilization Control Register
DMAC
0x1000 129C
CCNR8
Channel 8 Channel Counter Register
DMAC
0x1000 12C0
SAR9
Channel 9 Source Address Register
DMAC
0x1000 12C4
DAR9
Channel 9 Destination Address Register
DMAC
0x1000 12C8
CNTR9
Channel 9 Count Register
DMAC
0x1000 12CC
CCR9
Channel 9 Control Register
DMAC
0x1000 12D0
RSSR9
DMAC
0x1000 12D4
BLR9
DMAC
0x1000 12D8
RTOR9
BUCR9
Channel 9 Request Time-Out Register
Channel 9 Bus Utilization Control Register
DMAC
0x1000 12DC
CCNR9
Channel 9 Channel Counter Register
DMAC
0x1000 1300
SAR10
Channel 10 Source Address Register
DMAC
0x1000 1304
DAR10
Channel 10 Destination Address Register
DMAC
0x1000 1308
CNTR10
Channel 10 Count Register
DMAC
0x1000 130C
CCR10
Channel 10 Control Register
DMAC
0x1000 1310
RSSR10
DMAC
0x1000 1314
BLR10
DMAC
0x1000 1318
RTOR10
BUCR10
Channel 10 Request Time-Out Register
Channel 10 Bus Utilization Control Register
DMAC
0x1000 131C
CCNR10
Channel 10 Channel Counter Register
DMAC
0x1000 1340
SAR11
Channel 11 Source Address Register
DMAC
0x1000 1344
DAR11
Channel 11 Destination Address Register
DMAC
0x1000 1348
CNTR11
Channel 11 Count Register
DMAC
0x1000 134C
CCR11
Channel 11 Control Register
DMAC
0x1000 1350
RSSR11
DMAC
0x1000 1354
BLR11
DMAC
0x1000 1358
RTOR11
BUCR11
Channel 11 Request Time-Out Register
Channel 11 Bus Utilization Control Register
DMAC
0x1000 135C
CCNR11
Channel 11 Channel Counter Register
DMAC
0x1000 1380
SAR12
Channel 12 Source Address Register
DMAC
0x1000 1384
DAR12
Channel 12 Destination Address Register
Channel 8 Request Source Select Register
Channel 8 Burst Length Register
Channel 9 Request Source Select Register
Channel 9 Burst Length Register
Channel 10 Request Source Select Register
Channel 10 Burst Length Register
Channel 11 Request Source Select Register
Channel 11 Burst Length Register
i.MX21 Reference Manual, Rev. 3
3-10
Freescale Semiconductor
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
DMAC
0x1000 1388
CNTR12
Channel 12 Count Register
DMAC
0x1000 138C
CCR12
Channel 12 Control Register
DMAC
0x1000 1390
RSSR12
DMAC
0x1000 1394
BLR12
DMAC
0x1000 1398
RTOR12
BUCR12
Channel 12 Request Time-Out Register
Channel 12 Bus Utilization Control Register
DMAC
0x1000 139C
CCNR12
Channel 14 Channel Counter Register
DMAC
0x1000 13C0
SAR13
Channel 13 Source Address Register
DMAC
0x1000 13C4
DAR13
Channel 13 Destination Address Register
DMAC
0x1000 13C8
CNTR13
Channel 13 Count Register
DMAC
0x1000 13CC
CCR13
Channel 13 Control Register
DMAC
0x1000 13D0
RSSR13
DMAC
0x1000 13D4
BLR13
DMAC
0x1000 13D8
RTOR13
BUCR13
Channel 13 Request Time-Out Register
Channel 13 Bus Utilization Control Register
DMAC
0x1000 13DC
CCNR13
Channel 13 Channel Counter Register
DMAC
0x1000 1400
SAR14
Channel 14 Source Address Register
DMAC
0x1000 1404
DAR14
Channel 14 Destination Address Register
DMAC
0x1000 1408
CNTR14
Channel 14 Count Register
DMAC
0x1000 140C
CCR14
Channel 14 Control Register
DMAC
0x1000 1410
RSSR14
DMAC
0x1000 1414
BLR14
DMAC
0x1000 1418
RTOR14
BUCR14
Channel 14 Request Time-Out Register
Channel 14 Bus Utilization Control Register
DMAC
0x1000 141C
CCNR14
Channel 14 Channel Counter Register
DMAC
0x1000 1440
SAR15
Channel 15 Source Address Register
DMAC
0x1000 1444
DAR15
Channel 15 Destination Address Register
DMAC
0x1000 1448
CNTR15
Channel 15 Count Register
DMAC
0x1000 144C
CCR15
Channel 15 Control Register
DMAC
0x1000 1450
RSSR15
DMAC
0x1000 1454
BLR15
DMAC
0x1000 1458
RTOR15
BUCR15
Channel 15 Request Time-Out Register
Channel 15 Bus Utilization Control Register
DMAC
0x1000 145C
CCNR15
Channel 15 Channel Counter Register
Channel 12 Request Source Select Register
Channel 12 Burst Length Register
Channel 13 Request Source Select Register
Channel 13 Burst Length Register
Channel 14 Request Source Select Register
Channel 14 Burst Length Register
Channel 15 Request Source Select Register
Channel 15 Burst Length Register
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-11
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
WDOG
0x1000 2000
WCR
Watchdog Control Register
WDOG
0x1000 2002
WSR
Watchdog Service Register
WDOG
0x1000 2004
WRSR
Watchdog Reset Status Register
GPT1
0x1000 3000
TCTL1
GPT Control Register 1
GPT1
0x1000 3004
TPRER1
GPT Prescaler Register 1
GPT1
0x1000 3008
TCMP1
GPT Compare Register 1
GPT1
0x1000 300C
TCR1
GPT Capture Register 1
GPT1
0x1000 3010
TCN1
GPT Counter Register 1
GPT1
0x1000 3014
TSTAT1
GPT Status Register 1
GPT2
0x1000 4000
TCTL2
GPT Control Register 2
GPT2
0x1000 4004
TPRER2
GPT Prescaler Register 2
GPT2
0x1000 4008
TCMP2
GPT Compare Register 2
GPT2
0x1000 400C
TCR2
GPT Capture Register 2
GPT2
0x1000 4010
TCN2
GPT Counter Register 2
GPT2
0x1000 4014
TSTAT2
GPT Status Register 2
GPT3
0x1000 5000
TCTL3
GPT Control Register 3
GPT3
0x1000 5004
TPRER3
GPT Prescaler Register 3
GPT3
0x1000 5008
TCMP3
GPT Compare Register 3
GPT3
0x1000 500C
TCR3
GPT Capture Register 3
GPT3
0x1000 5010
TCN3
GPT Counter Register 3
GPT3
0x1000 5014
TSTAT3
GPT Status Register 3
PWM
0x1000 6000
PWMC
PWM Control Register
PWM
0x1000 6004
PWMS
PWM Sample Register
PWM
0x1000 6008
PWMP
PWM Period Register
PWM
0x1000 600C
PWMCNT
PWM Counter Register
RTC
0x1000 7000
HOURMIN
RTC Hours and Minutes Counter Register
RTC
0x1000 7004
SECONDS
RTC Seconds Counter Register
RTC
0x1000 7008
ALRM_HM
RTC Hours and Minutes Alarm Register
RTC
0x1000 700C
ALRM_SEC
RTC Seconds Alarm Register
RTC
0x1000 7010
RCCTL
RTC Control Register
RTC
0x1000 7014
RTCISR
RTC Interrupt Status Register
RTC
0x1000 7018
RTCIENR
RTC Interrupt Enable Register
RTC
0x1000 701C
STPWCH
Stopwatch Minutes Register
i.MX21 Reference Manual, Rev. 3
3-12
Freescale Semiconductor
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
RTC
0x1000 7020
DAYR
RTC
0x1000 7024
DAYALARM
RTC Day Alarm Register
KPP
0x1000_8000
KPCR
Keypad Control Register
KPP
0x1000_8002
KPSR
Keypad Status Register
KPP
0x1000_8004
KDDR
Keypad Data Direction Register
KPP
0x1000_8006
KPDR
Keypad Data Register
O-Wire
0x1000 9000
CONTROL
O-Wire
0x1000 9002
TIME_DIVIDER
O-Wire
0x1000 9004
RESET
UART1
0x1000_A000
UXRD_1
UART1 Receiver Register
UART1
0x1000_A040
UTXD_1
UART1 Transmitter Register
UART1
0x1000_A080
UCR1_1
UART1 Control Register
UART1
0x1000_A084
UCR2_1
UART1 Control Register 2
UART1
0x1000_A088
UCR3_1
UART1 Control Register 3
UART1
0x1000_A08C
UCR4_1
UART1 Control Register 4
UART1
0x1000_A090
UFCR_1
UART1 FIFO Control Register
UART1
0x1000_A094
USR1_1
UART1 Status Register 1
UART1
0x1000_A098
USR2_1
UART1 Status Register 2
UART1
0x1000_A09C
UESC_1
UART1 Escape Character Register
UART1
0x1000_A0A0
UTIM_1
UART1 Escape Timer Register
UART1
0x1000_A0A4
UBIR_1
UART1 BRM Incremental Register
UART1
0x1000_A0A8
UBMR_1
UART1 BRM Modulator Register
UART1
0x1000_A0AC
UBRC_1
UART1 Baud Rate Count Register
UART1
0x1000_A0B0
ONEMS_1
UART1 One Millisecond Register
UART1
0x1000_A0B4
UTS_1
UART2
0x1000_B000
UXRD_2
UART2 Receiver Register
UART2
0x1000_B040
UTXD_2
UART2 Transmitter Register
UART2
0x1000_B080
UCR1_2
UART2 Control Register
UART2
0x1000_B084
UCR2_2
UART2 Control Register 2
UART2
0x1000_B088
UCR3_2
UART2 Control Register 3
UART2
0x1000_B08C
UCR4_2
UART2 Control Register 4
UART2
0x1000_B090
UFCR_2
UART2 FIFO Control Register
UART2
0x1000_B094
USR1_2
UART2 Status Register 1
RTC Days Counter Register
1-Wire Control Register
1-Wire Time Divider Register
1-Wire Reset Register
UART1 Test Register 1
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-13
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
UART2
0x1000_B098
USR2_2
UART2 Status Register 2
UART2
0x1000_B09C
UESC_2
UART2 Escape Character Register
UART2
0x1000_B0A0
UTIM_2
UART2 Escape Timer Register
UART2
0x1000_B0A4
UBIR_2
UART2 BRM Incremental Register
UART2
0x1000_B0A8
UBMR_2
UART2 BRM Modulator Register
UART2
0x1000_B0AC
UBRC_2
UART2 Baud Rate Count Register
UART2
0x1000_B0B0
ONEMS_2
UART2 One Millisecond Register
UART2
0x1000_B0B4
UTS_2
UART3
0x1000_C000
UXRD_3
UART3 Receiver Register
UART3
0x1000_C040
UTXD_3
UART3 Transmitter Register
UART3
0x1000_C080
UCR1_3
UART3 Control Register
UART3
0x1000_C084
UCR2_3
UART3 Control Register 2
UART3
0x1000_C088
UCR3_3
UART3 Control Register 3
UART3
0x1000_C08C
UCR4_3
UART3 Control Register 4
UART3
0x1000_C090
UFCR_3
UART3 FIFO Control Register
UART3
0x1000_C094
USR1_3
UART3 Status Register 1
UART3
0x1000_C098
USR2_3
UART3 Status Register 2
UART3
0x1000_C09C
UESC_3
UART3 Escape Character Register
UART3
0x1000_C0A0
UTIM_3
UART3 Escape Timer Register
UART3
0x1000_C0A4
UBIR_3
UART3 BRM Incremental Register
UART3
0x1000_C0A8
UBMR_3
UART3 BRM Modulator Register
UART3
0x1000_C0AC
UBRC_3
UART3 Baud Rate Count Register
UART3
0x1000_C0B0
ONEMS_3
UART3 One Millisecond Register
UART3
0x1000_C0B4
UTS_3
UART4
0x1000_D000
UXRD_4
UART4 Receiver Register
UART4
0x1000_D040
UTXD_4
UART4 Transmitter Register
UART4
0x1000_D080
UCR1_4
UART4 Control Register
UART4
0x1000_D084
UCR2_4
UART4 Control Register 2
UART4
0x1000_D088
UCR3_4
UART4 Control Register 3
UART4
0x1000_D08C
UCR4_4
UART4 Control Register 4
UART4
0x1000_D090
UFCR_4
UART4 FIFO Control Register
UART4
0x1000_D094
USR1_4
UART4 Status Register 1
UART4
0x1000_D098
USR2_4
UART4 Status Register 2
UART2 Test Register 1
UART3 Test Register 1
i.MX21 Reference Manual, Rev. 3
3-14
Freescale Semiconductor
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
UART4
0x1000_D09C
UESC_4
UART4 Escape Character Register
UART4
0x1000_D0A0
UTIM_4
UART4 Escape Timer Register
UART4
0x1000_D0A4
UBIR_4
UART4 BRM Incremental Register
UART4
0x1000_D0A8
UBMR_4
UART4 BRM Modulator Register
UART4
0x1000_D0AC
UBRC_4
UART4 Baud Rate Count Register
UART4
0x1000_D0B0
ONEMS_4
UART4 One Millisecond Register
UART4
0x1000_D0B4
UTS_4
CSPI1
0x1000 E000
RXDATA1
Receive Data Register 1
CSPI1
0x1000 E004
TXDATA1
Transmit Data Register 1
CSPI1
0x1000 E008
CONTROL_REG1
CSPI Control Register 1
CSPI1
0x1000 E00C
INT_REG1
Interrupt Control/Status Register 1
CSPI1
0x1000 E010
TEST_REG
CSPI Test Register 1
CSPI1
0x1000 E014
PERIOD1
CSPI1
0x1000 E018
CSPI_DMA1
CSPI1
0x1000 E01C
CSPI_RESET1
CSPI2
0x1000 F000
RXDATA2
Receive Data Register 2
CSPI2
0x1000 F004
TXDATA2
Transmit Data Register 2
CSPI2
0x1000 F008
CONTROL_REG2
CSPI Control Register 2
CSPI2
0x1000 F00C
INT_REG2
CSPI2
0x1000 F010
TEST_REG 2
CSPI2
0x1000 F014
PERIOD2
CSPI2
0x1000 F018
CSPI_DMA2
CSPI2
0x1000 F01C
CSPI_RESET2
SSI 1
0x1001 0000
STX0
SSI Transmit Data Register 0
SSI 1
0x1001 0004
STX1
SSI Transmit Data Register 1
SSI 1
0x1001 0008
SRX0
SSI Receive Data Register 0
SSI 1
0x1001 000C
SRX1
SSI Receive Data Register 1
SSI 1
0x1001 0010
SCR
SSI Control Register
SSI 1
0x1001 0014
SISR
SSI Interrupt Status Register
SSI 1
0x1001 0018
SIER
SSI Interrupt Enable Register
SSI 1
0x1001 001C
STCR
SSI Transmit Configuration Register
SSI 1
0x1001 0020
SRCR
SSI Receive Configuration Register
SSI 1
0x1001 0024
STCCR
SSI Transmit Clock Control Register
UART4 Test Register 1
CSPI Sample Period Control Register 1
CSPI DMA Register 1
CSPI 1 Soft Reset Register
Interrupt Control/Status Register 2
CSPI Test Register 2
CSPI Sample Period Control Register 2
CSPI DMA Register 2
CSPI 2 Soft Reset Register
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-15
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
SSI 1
0x1001 0028
SRCCR
SSI Receive Clock Control Register
SSI 1
0x1001 002C
SFCSR
SSI FIFO Control/Status Register
SSI 1
0x1001 0030
STR
SSI Test Register
SSI 1
0x1001 0034
SOR
SSI Option Register
SSI 1
0x1001 0038
SACNT
SSI 1
0x1001 003C
SACADD
SSI AC97 Command Address Register
SSI 1
0x1001 0040
SACDAT
SSI AC97 Command Data Register
SSI 1
0x1001 0044
SATAG
SSI AC97 Tag Register
SSI 1
0x1001 0048
STMSK
SSI Transmit Time Slot Mask Register
SSI 1
0x1001 004C
SRMSK
SSI Receive Time Slot Mask Register
SSI 2
0x1001 1000
STX0
SSI Transmit Data Register 0
SSI 2
0x1001 1004
STX1
SSI Transmit Data Register 1
SSI 2
0x1001 1008
SRX0
SSI Receive Data Register 0
SSI 2
0x1001 100C
SRX1
SSI Receive Data Register 1
SSI 2
0x1001 1010
SCR
SSI Control Register
SSI 2
0x1001 1014
SISR
SSI Interrupt Status Register
SSI 2
0x1001 1018
SIER
SSI Interrupt Enable Register
SSI 2
0x1001 101C
STCR
SSI Transmit Configuration Register
SSI 2
0x1001 1020
SRCR
SSI Receive Configuration Register
SSI 2
0x1001 1024
STCCR
SSI Transmit Clock Control Register
SSI 2
0x1001 1028
SRCCR
SSI Receive Clock Control Register
SSI 2
0x1001 102C
SFCSR
SSI FIFO Control/Status Register
SSI 2
0x1001 1030
STR
SSI Test Register
SSI 2
0x1001 1034
SOR
SSI Option Register
SSI 2
0x1001 1038
SACNT
SSI 2
0x1001 103C
SACADD
SSI AC97 Command Address Register
SSI 2
0x1001 1040
SACDAT
SSI AC97 Command Data Register
SSI 2
0x1001 1044
SATAG
SSI AC97 Tag Register
SSI 2
0x1001 1048
STMSK
SSI Transmit Time Slot Mask Register
SSI 2
0x1001 104C
SRMSK
SSI Receive Time Slot Mask Register
I 2C
0x1001 2000
IADR
I2C Address Register
I2C
0x1001 2004
IFDR
I2C Frequency Divider Register
I2C
0x1001 2008
I2CR
I2C Control Register
SSI AC97 Control Register
SSI AC97 Control Register
i.MX21 Reference Manual, Rev. 3
3-16
Freescale Semiconductor
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
I2C
0x1001 200C
I2SR
I2C Status Register
I2C
0x1001 2010
I2DR
I2C Data I/O Register
SDHC1
0x1001 3000
STR_STP_CLK
SDHC1
0x1001 3004
STATUS (Read Only)
SDHC1
0x1001 3008
CLK_RATE
SDHC1
0x1001 300C
CMD_DAT_CONT
SDHC1
0x1001 3010
RESPONSE_TO
SDHC1
0x1001 3014
READ_TO
MMC/SD1 Read Time Out Register
SDHC1
0x1001 3018
BLK_LEN
MMC/SD1 Block Length Register
SDHC1
0x1001 301C
NOB
MMC/SD1 Number of Block Register
SDHC1
0x1001 3020
REV_NO
MMC/SD1 Revision Number Register
SDHC1
0x1001 3024
INT_CNTL
MMC/SD1 Interrupt Control Register
SDHC1
0x1001 3028
CMD
SDHC1
0x1001 302C
ARGH
MMC/SD1 Higher Argument Register
SDHC1
0x1001 3030
ARGL
MMC/SD1 Lower Argument Register
SDHC1
0x1001 3034
RES_FIFO (Read Only)
MMC/SD1 Response FIFO Register
SDHC1
0x1001 3038
BUFFER_ACCESS
MMC/SD1 Buffer Access Register
SDHC2
0x1001 4000
STR_STP_CLK
MMC/SD2 Clock Control Register
SDHC2
0x1001 4004
STATUS (Read Only)
SDHC2
0x1001 4008
CLK_RATE
SDHC2
0x1001 400C
CMD_DAT_CONT
SDHC2
0x1001 4010
RESPONSE_TO
SDHC2
0x1001 4014
READ_TO
MMC/SD2 Read Time Out Register
SDHC2
0x1001 4018
BLK_LEN
MMC/SD2 Block Length Register
SDHC2
0x1001 401C
NOB
MMC/SD2 Number of Block Register
SDHC2
0x1001 4020
REV_NO
MMC/SD2 Revision Number Register
SDHC2
0x1001 4024
INT_CNTL
MMC/SD2 Interrupt Control Register
SDHC2
0x1001 4028
CMD
SDHC2
0x1001 402C
ARGH
MMC/SD2 Higher Argument Register
SDHC2
0x1001 4030
ARGL
MMC/SD2 Lower Argument Register
SDHC2
0x1001 4034
RES_FIFO (Read Only)
MMC/SD2 Response FIFO Register
SDHC2
0x1001 4038
BUFFER_ACCESS
GPIO
0x1001 5000
PTA_DDIR
MMC/SD1 Clock Control Register
MMC/SD1 Status Register
MMC/SD1 Clock Rate Register
MMC/SD1 Command and Data Control Register
MMC/SD1 Response Time Out Register
MMC/SD1 Command Number Register
MMC/SD2 Status Register
MMC/SD2 Clock Rate Register
MMC/SD2 Command and Data Control Register
MMC/SD2 Response Time Out Register
MMC/SD2 Command Number Register
MMC/SD2 Buffer Access Register
Data Direction Register, Port A
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-17
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
GPIO
0x1001 5004
PTA_OCR1
Output Configuration Register 1 (OCR1), Port A
GPIO
0x1001 5008
PTA_OCR2
Output Configuration Register 2 (OCR2), Port A
GPIO
0x1001 500C
PTA_ICONFA1
Input Configuration Register A1 (ICONFA1), Port A
GPIO
0x1001 5010
PTA_ICONFA2
Input Configuration Register A1 (ICONFA2), Port A
GPIO
0x1001 5014
PTA_ICONFB1
Input Configuration Register B1 (ICONFB1), Port A
GPIO
0x1001 5018
PTA_ICONFB2
Input Configuration Register B2 (ICONFB2), Port A
GPIO
0x1001 501c
PTA_DR
GPIO
0x1001 5020
PTA_GIUS
GPIO In Use Register, Port A
GPIO
0x1001 5024
PTA_SSR
Sample Status Register, Port A
GPIO
0x1001 5028
PTA_ICR1
Interrupt Configuration Register 1, Port A
GPIO
0x1001 502C
PTA_ICR2
Interrupt Configuration Register 2, Port A
GPIO
0x1001 5030
PTA_IMR
Interrupt Mask Register, Port A
GPIO
0x1001 5034
PTA_ISR
Interrupt Status Register, Port A
GPIO
0x1001 5038
PTA_GPR
General Purpose Register, Port A
GPIO
0x1001 503c
PTA_SWR
Software Reset Register, Port A
GPIO
0x1001 5040
PTA_PUEN
Pull_up Enable Register, Port A
GPIO
0x1001_5100
PTB_DDIR
Data Direction Register, Port B
GPIO
0x1001 5104
PTB_OCR1
Output Configuration Register 1 (OCR1), Port B
GPIO
0x1001 5108
PTB_OCR2
Output Configuration Register 2 (OCR2), Port B
GPIO
0x1001 510c
PTB_ICONFA1
Input Configuration Register A1 (ICONFA1), Port B
GPIO
0x1001 5110
PTB_ICONFA2
Input Configuration Register A1 (ICONFA2), Port B
GPIO
0x1001 5114
PTB_ICONFB1
Input Configuration Register B1 (ICONFB1), Port B
GPIO
0x1001 5118
PTB_ICONFB2
Input Configuration Register B2 (ICONFB2), Port B
GPIO
0x1001 511c
PTB_DR
GPIO
0x1001 5120
PTB_GIUS
GPIO In Use Register, Port B
GPIO
0x1001 5124
PTB_SSR
Sample Status Register, Port B
GPIO
0x1001 5128
PTB_ICR1
Interrupt Configuration Register 1, Port B
GPIO
0x1001 512C
PTB_ICR2
Interrupt Configuration Register 2, Port B
GPIO
0x1001 5130
PTB_IMR
Interrupt Mask Register, Port B
GPIO
0x1001 5134
PTB_ISR
Interrupt Status Register, Port B
GPIO
0x1001 5138
PTB_GPR
General Purpose Register, Port B
GPIO
0x1001 513c
PTB_SWR
Software Reset Register, Port B
GPIO
0x1001 5140
PTB_PUEN
Pull_up Enable Register, Port B
Data Register, Port A
Data Register, Port B
i.MX21 Reference Manual, Rev. 3
3-18
Freescale Semiconductor
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
GPIO
0x1001_5200
PTC_DDIR
Data Direction Register, Port C
GPIO
0x1001 5204
PTC_OCR1
Output Configuration Register 1 (OCR1), Port C
GPIO
0x1001 5208
PTC_OCR2
Output Configuration Register 2 (OCR2), Port C
GPIO
0x1001 520c
PTC_ICONFA1
Input Configuration Register A1 (ICONFA1), Port C
GPIO
0x1001 5210
PTC_ICONFA2
Input Configuration Register A1 (ICONFA2), Port C
GPIO
0x1001 5214
PTC_ICONFB1
Input Configuration Register B1 (ICONFB1), Port C
GPIO
0x1001 5218
PTC_ICONFB2
Input Configuration Register B2 (ICONFB2), Port C
GPIO
0x1001 521C
PTC_DR
GPIO
0x1001 5220
PTC_GIUS
GPIO In Use Register, Port C
GPIO
0x1001 5224
PTC_SSR
Sample Status Register, Port C
GPIO
0x1001 5228
PTC_ICR1
Interrupt Configuration Register 1, Port C
GPIO
0x1001 522C
PTC_ICR2
Interrupt Configuration Register 2, Port C
GPIO
0x1001 5230
PTC_IMR
Interrupt Mask Register, Port C
GPIO
0x1001 5234
PTC_ISR
Interrupt Status Register, Port C
GPIO
0x1001 5238
PTC_GPR
General Purpose Register, Port C
GPIO
0x1001 523c
PTC_SWR
Software Reset Register, Port C
GPIO
0x1001 5240
PTC_PUEN
Pull_up Enable Register, Port C
GPIO
0x1001 5300
PTD_DDIR
Data Direction Register, Port D
GPIO
0x1001 5304
PTD_OCR1
Output Configuration Register 1 (OCR1), Port D
GPIO
0x1001 5308
PTD_OCR2
Output Configuration Register 2 (OCR2), Port D
GPIO
0x1001 530c
PTD_ICONFA1
Input Configuration Register A1 (ICONFA1), Port D
GPIO
0x1001 5310
PTD_ICONFA2
Input Configuration Register A1 (ICONFA2), Port D
GPIO
0x1001 5314
PTD_ICONFB1
Input Configuration Register B1 (ICONFB1), Port D
GPIO
0x1001 5318
PTD_ICONFB2
Input Configuration Register B2 (ICONFB2), Port D
GPIO
0x1001 531c
PTD_DR
GPIO
0x1001 5320
PTD_GIUS
GPIO In Use Register, Port D
GPIO
0x1001 5324
PTD_SSR
Sample Status Register, Port D
GPIO
0x1001 5328
PTD_ICR1
Interrupt Configuration Register 1, Port D
GPIO
0x1001 532C
PTD_ICR2
Interrupt Configuration Register 2, Port D
GPIO
0x1001 5330
PTD_IMR
Interrupt Mask Register, Port D
GPIO
0x1001 5334
PTD_ISR
Interrupt Status Register, Port D
GPIO
0x1001 5338
PTD_GPR
General Purpose Register, Port D
GPIO
0x1001 533c
PTD_SWR
Software Reset Register, Port D
Data Register, Port C
Data Register, Port D
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-19
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
GPIO
0x1001 5340
PTD_PUEN
Pull_up Enable Register, Port D
GPIO
0x1001 5400
PTE_DDIR
Data Direction Register, Port E
GPIO
0x1001 5404
PTE_OCR1
Output Configuration Register 1 (OCR1), Port E
GPIO
0x1001 5408
PTE_OCR2
Output Configuration Register 2 (OCR2), Port E
GPIO
0x1001 540c
PTE_ICONFA1
Input Configuration Register A1 (ICONFA1), Port E
GPIO
0x1001 5410
PTE_ICONFA2
Input Configuration Register A1 (ICONFA2), Port E
GPIO
0x1001 5414
PTE_ICONFB1
Input Configuration Register B1 (ICONFB1), Port E
GPIO
0x1001 5418
PTE_ICONFB2
Input Configuration Register B2 (ICONFB2), Port E
GPIO
0x1001 541c
PTE_DR
GPIO
0x1001 5420
PTE_GIUS
GPIO In Use Register, Port E
GPIO
0x1001 5424
PTE_SSR
Sample Status Register, Port E
GPIO
0x1001 5428
PTE_ICR1
Interrupt Configuration Register 1, Port E
GPIO
0x1001 542C
PTE_ICR2
Interrupt Configuration Register 2, Port E
GPIO
0x1001 5430
PTE_IMR
Interrupt Mask Register, Port E
GPIO
0x1001 5434
PTE_ISR
Interrupt Status Register, Port E
GPIO
0x1001 5438
PTE_GPR
General Purpose Register, Port E
GPIO
0x1001 543c
PTE_SWR
Software Reset Register, Port E
GPIO
0x1001 5440
PTE_PUEN
Pull_up Enable Register, Port E
GPIO
0x1001 5500
PTF_DDIR
Data Direction Register, Port F
GPIO
0x1001 5504
PTF_OCR1
Output Configuration Register 1 (OCR1), Port F
GPIO
0x1001 5508
PTF_OCR2
Output Configuration Register 2 (OCR2), Port F
GPIO
0x1001 550C
PTF_ICONFA1
Input Configuration Register A1 (ICONFA1), Port F
GPIO
0x1001 5510
PTF_ICONFA2
Input Configuration Register A1 (ICONFA2), Port F
GPIO
0x1001 5514
PTF_ICONFB1
Input Configuration Register B1 (ICONFB1), Port F
GPIO
0x1001 5518
PTF_ICONFB2
Input Configuration Register B2 (ICONFB2), Port F
GPIO
0x1001 551c
PTF_DR
GPIO
0x1001 5520
PTF_GIUS
GPIO In Use Register, Port F
GPIO
0x1001 5524
PTF_SSR
Sample Status Register, Port F
GPIO
0x1001 5528
PTF_ICR1
Interrupt Configuration Register 1, Port F
GPIO
0x1001 552C
PTF_ICR2
Interrupt Configuration Register 2, Port F
GPIO
0x1001 5530
PTF_IMR
Interrupt Mask Register, Port F
GPIO
0x1001 5534
PTF_ISR
Interrupt Status Register, Port F
GPIO
0x1001 5538
PTF_GPR
General Purpose Register, Port F
Data Register, Port E
Data Register, Port F
i.MX21 Reference Manual, Rev. 3
3-20
Freescale Semiconductor
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
GPIO
0x1001 553c
PTF_SWR
Software Reset Register, Port F
GPIO
0x1001 5540
PTF_PUEN
Pull_up Enable Register, Port F
GPIO
0x1001 5600
PMASK
GPIO Port Interrupt Mask
AUDMUX
0x1001 6000
HPCR1
Host Port Configuration Register 1
AUDMUX
0x1001 6004
HPCR2
Host Port Configuration Register 2
AUDMUX
0x1001 6008
HPCR3
Host Port Configuration Register 3
AUDMUX
0x1001 6010
PPCR1
Peripheral Port Configuration Register 1
AUDMUX
0x1001 6014
PPCR2
Peripheral Port Configuration Register 2
AUDMUX
0x1001 601C
PPCR3
Peripheral Port Configuration Register 3
CSPI3
0x1001 7000
RXDATA3
Receive Data Register 3
CSPI3
0x1001 7004
TXDATA3
Transmit Data Register 3
CSPI3
0x1001 7008
CONTROL_REG3
CSPI Control Register 3
CSPI3
0x1001 700C
INT_REG3
CSPI3
0x1001 7010
TEST_REG3
CSPI3
0x1001 7014
PERIOD3
CSPI3
0x1001 7018
CSPI_DMA3
CSPI3
0x1001 701C
CSPI_RESET3
AIPI2
0x1002 0000
PSR0
Peripheral Size Register0
AIPI2
0x1002 0004
PSR1
Peripheral Size Register1
AIPI2
0x1002 0008
PAR
LCDC
0x1002 1000
LSSAR
LCDC
0x1002 1004
LSR
LCDC
0x1002 1008
LVPWR
LCDC
0x1002 100C
LCPR
LCDC
0x1002 1010
LCWHBR
LCDC
0x1002 1014
LCCMR
LCDC
0x1002 1018
LPCR
LCD Panel Configuration Register
LCDC
0x1002 101C
LHCR
LCD Horizontal Configuration Register
LCDC
0x1002 1020
LVCR
LCD Vertical Configuration Register
LCDC
0x1002 1024
LPOR
LCD Panning Offset Register
LCDC
0x1002 1028
LSCR
LCD Sharp Configuration Register
LCDC
0x1002 102C
LPCCR
LCDC
0x1002 1030
LDCR
Interrupt Control/Status Register 3
CSPI Test Register 3
CSPI Sample Period Control Register 3
CSPI DMA Register 3
CSPI Soft Reset Register 3
Peripheral Access Register
LCD Screen Start Address Register
LCD Size Register
LCD Virtual Page Width Register
LCD Cursor Position Register
LCD Cursor Width Height and Blink Register
LCD Color Cursor Mapping Register
LCD PWM Contrast Control Register
LCD DMA Control Register
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-21
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
LCDC
0x1002 1034
LRMCR
LCD Refresh Mode Control Register
LCDC
0x1002 1038
LICR
LCD Interrupt Configuration Register
LCDC
0x1002 103C
LIER
LCD Interrupt Enable Register
LCDC
0x1002 1040
LISR
LCD Interrupt Status Register
LCDC
0x1002 1050
LGWSAR
LCDC
0x1002 1054
LGWSR
LCDC
0x1002 1058
LGWVPWR
LCDC
0x1002 105C
LGWPOR
LCDC
0x1002 1060
LGWPR
LCD Graphic Window Position Registration Register
LCDC
0x1002 1064
LGWCR
LCD Graphic Window Control Register
LCDC
0x1002 1068
LGWDCR
SLCDC
0x1002 2000
DATA_BASE_ADDR
SLCDC
0x1002 2004
DATA_BUFF_SIZE
SLCD Data Buffer Size Register
SLCDC
0x1002 2008
CMD_BASE_ADDR
SLCD Command Buffer Base Address Register
SLCDC
0x1002 200C
CMD_BUFF_SIZE
SLCD Command Buffer Size Register
SLCDC
0x1002 2010
CMD_STR_SIZE
SLCD Command String Size Register
SLCDC
0x1002 2014
FIFO_CONFIG
SLCD FIFO Configuration Register
SLCDC
0x1002 2018
LCD_CONFIG
SLCD Configuration Register
SLCDC
0x1002 201C
LCD_XFER_CONFIG
SLCDC
0x1002 2020
DMA_CTRL_STAT
SLCD DMA Control/Status Register
SLCDC
0x1002 2024
LCD_CLK_CONFIG
SLCD Clock Configuration Register
SLCDC
0x1002 2028
LCD_WRITE_DATA
SLCD Write Data Register
USBOTG
0x1002 4000
USB_HDW_MODE
USB OTG Hardware Mode Register
USBOTG
0x1002 4004
USB_INT_STATUS
USB OTG Module Interrupt Status Register
USBOTG
0x1002 4008
USB_INT_EN
USBOTG
0x1002 400C
USB_CLK_CTRL
USB OTG Clock Control Register
USBOTG
0x1002 4010
USB_RST_CTRL
USB OTG Reset Control Register
USBOTG
0x1002 4014
USB_FRAME_INTV
USB OTG Frame Interval Register
USBOTG
0x1002 4018
USB_FRAME_REMAIN
USBOTG
0x1002 401C
USB_HNP_CSR
USB OTG HNP Control Status Register
USBOTG
0x1002 402C
USB_HNP_ISR
USB OTG HNP Interrupt Status Register
USBOTG
0x1002 4030
USB_HNP_IEN
USB OTG HNP Interrupt Enable Register
USBOTG
0x1002 4040
USB_FUNC_CMD_STAT
LCD Graphic Window Start Address Register
LCD Graphic Window Size Register
LCD Graphic Window Virtual Page Width Register
LCD Graphic Window Panning Offset Register
LCD Graphic Window DMA Control Register
SLCD Data Base Address Register
SLCD Transfer Configuration Register
USB OTG Module Interrupt Status Enable Register
USB OTG Frame Remaining Register
USB OTG Function Command Status Register
i.MX21 Reference Manual, Rev. 3
3-22
Freescale Semiconductor
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
USBOTG
0x1002 4044
USB_DEV_ADD
USBOTG
0x1002 4048
USB_SYS_INT_STAT
USB OTG System Interrupt Status Register
USBOTG
0x1002 404C
USB_SYS_INT_EN
USB OTG System Interrupt Enable Register
USBOTG
0x1002 4050
USB_XBUFF_INT_STAT
USB OTG X Buffer Interrupt Status Register
USBOTG
0x1002 4054
USB_YBUFF_INT_STAT
USB OTG Y Buffer Interrupt Status Register
USBOTG
0x1002 4058
USB_XYINT_INT_EN
USBOTG
0x1002 405C
USB_XFILL_STAT
USB OTG X Filled Status Register
USBOTG
0x1002 4060
USB_YFILL_STAT
USB OTG Y Filled Status Register
USBOTG
0x1002 4064
USB_ENDPT_EN
USB OTG Endpoint Enable Register
USBOTG
0x1002 4068
USB_ENDPT_RDY
USB OTG Endpoint Ready Register
USBOTG
0x1002 406C
USB_IMM_INT
USBOTG
0x1002 4070
USB_ENDPT_DONE_STAT
USB OTG Endpoint Done Status Register
USBOTG
0x1002 4074
USB_ENDPT_DONE_EN
USB OTG Endpoint Done Enable Register
USBOTG
0x1002 4078
USB_ENDPT_TOGGBITS
USB OTG EndpointToggle Bits Register
USBOTG
0x1002 407C
USB_FRAME_NO
USB OTG Frame Number Register
USBOTG
0x1002 4080
USB_HOST_CTRL
USB OTG Host Control Register
USBOTG
0x1002 4088
USB_SYS_ISR
USB OTG System Interrupt Status Register
USBOTG
0x1002 408C
USB_SYS_IEN
USB OTG System Interrupt Enable Register
USBOTG
0x1002 4098
USB_XBUF_ISR
USB OTG X Buffer Interrupt Status Register
USBOTG
0x1002 409C
USB_YBUF_ISR
USB OTG Y Buffer Interrupt Status Register
USBOTG
0x1002 40A0
USB_XYINT_EN
USB OTG XY Interrupt Enables Register
USBOTG
0x1002 40A8
USB_XFILL_STAT
USB OTG X Filled Status Register
USBOTG
0x1002 40AC
USB_YFILL_STAT
USB OTG Y Filled Status Register
USBOTG
0x1002 40C0
USB_ETD_EN
USBOTG
0x1002 40C8
NOT DEFINED
USB OTG
0x1002 40CC
USB_IM_INT
USB OTG
0x1002 40D0
USB_ETD_DONE
USB OTG ETD Done Status Register
USBOTG
0x1002 40D4
USB_ETD_DONE_EN
USB OTG ETD Done Enable Register
USBOTG
0x1002 40E0
USB_FR_NUM
USBOTG
0x1002 40E4
USB_LSTR
USB OTG Low Speed Threshold Register
USBOTG
0x1002 40E8
USB_RHD_A
USB OTG Root Hub DescriptorA Register
USBOTG
0x1002 40EC
USB_RHD_B
USB OTG Root Hub DescriptorB Register
USBOTG
0x1002 40F0
USB_RH_STAT
USB OTG Device Address Register
USB OTG XY Interrupt Enable Register
USB OTG Immediate Interrupt Register
USB OTG ETD Enable Register
–
USB OTG Immediate Interrupt Register
USB OTG Frame Number Register
USB OTG Root Hub Status Register
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-23
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
USBOTG
0x1002 40F4
USB_PORT_STAT1
USB OTG Port Status 1 Register
USBOTG
0x1002 40F8
USB_PORT_STAT2
USB OTG Port Status 2 Register
USBOTG
0x1002 40FC
USB_PORT_STAT3
USB OTG Port Status 3 Register
USBOTG
0x1002 4600
USB_CTRL
USBOTG
0x1002 4800
USB_DMA_REV
USBOTG
0x1002 4804
USB_DMA_INT_STAT
DMA Interrupt Status Register
USBOTG
0x1002 4808
USB_DMA_INT_EN
DMA Interrupt Enable Register
USBOTG
0x1002 480C
USB_ETDDMA_ER_STAT
ETD DMA Error Status Register
USBOTG
0x1002 4810
USB_EPDMA_ER_STAT
USBOTG
0x1002 4814
through
0x1002 481C
Reserved
USBOTG
0x1002 4820
USB_ETD_DMA_EN
USBOTG
0x1002 4824
USB_EP_DMA_EN
USBOTG
0x1002 4828
USB_ETDMA_XTRG_REQ
USBOTG
0x1002 482C
USB_EPMA_XTRG_REQ
USBOTG
0x1002 4830
USB_ETDMA_XYTRG_REQ
USBOTG
0x1002 4834
USB_EPMA_XYTRG_REQ
USBOTG
0x1002 4838
Reserved
Reserved
USBOTG
0x1002 483C
Reserved
Reserved
USBOTG
0x1002 4840
USB_MISC_CNTL
USBOTG
0x1002 4900
through
0x1002 497C
USB_ETD0_SYSMEM_ADR
through
USB_ETD31_SYSMEM_ADR
ETD 0: ETD 0 Sys Memory Start Address Register
through ETD 31: ETD 31 Sys Memory Start Address
Register
USBOTG
0x1002 4980
USB_EP0_OUT_MEM_ADR
EP 0 OUT: EP 0 Sys Memory Start Address Register
USBOTG
0x1002 4984
USB_EP0_IN_MEM_ADR
USBOTG
0x1002 4988
USB_EP1_OUT_MEM_ADR
USBOTG
0x1002 498C
USB_EP1_IN_MEM_ADR
USBOTG
0x1002 4990
USB_EP2_OUT_MEM_ADR
USBOTG
0x1002 4994
USB_EP2_IN_MEM_ADR
USBOTG
0x1002 4998
USB_EP3_OUT_MEM_ADR
USBOTG
0x1002 499C
USB_EP3_IN_MEM_ADR
USBOTG
0x1002 49A0
USB_EP4_OUT_MEM_ADR
USBOTG
0x1002 49A4
USB_EP4_IN_MEM_ADR
USB Control Register
DMA Revision Register
EP DMA Error Status Register
Reserved
ETD DMA Enable Register
EP DMA Enable Register
ETD DMA Enable XTrigger Request Register
EP DMA Enable XTrigger Request Register
ETD DMA Enable XYTrigger Request Register
EP DMA Enable XYTrigger Request Register
Misc Control Register
EP 0 IN: EP 0 Sys Memory Start Address Register
EP 1 OUT: EP 1 Sys Memory Start Address Register
EP 1 IN: EP 1 Sys Memory Start Address Register
EP 2 OUT: EP 2 Sys Memory Start Address Register
EP 2 IN: EP 2 Sys Memory Start Address Register
EP 3 OUT: EP 3 Sys Memory Start Address Register
EP 3 IN: EP 3 Sys Memory Start Address Register
EP 4OUT: EP 4 Sys Memory Start Address Register
EP 4 IN: EP 4 Sys Memory Start Address Register
i.MX21 Reference Manual, Rev. 3
3-24
Freescale Semiconductor
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
USBOTG
0x1002 49A8
USB_EP5_OUT_MEM_ADR
EP 5 OUT: EP 5 Sys Memory Start Address Register
USBOTG
0x1002 49AC
USB_EP5_IN_MEM_ADR
USBOTG
0x1002 49B0
USB_EP6_OUT_MEM_ADR
USBOTG
0x1002 49B4
USB_EP6_IN_MEM_ADR
USBOTG
0x1002 49B8
USB_EP7_OUT_MEM_ADR
USBOTG
0x1002 49BC
USB_EP7_IN_MEM_ADR
USBOTG
0x1002 49C0
USB_EP8_OUT_MEM_ADR
USBOTG
0x1002 49C4
USB_EP8_IN_MEM_ADR
USBOTG
0x1002 49C8
USB_EP9_OUT_MEM_ADR
USBOTG
0x1002 49CC
USB_EP9_IN_MEM_ADR
USBOTG
0x1002 49D0
USB_EP10_OUT_MEM_ADR
USBOTG
0x1002 49D4
USB_EP10_IN_MEM_ADR
USBOTG
0x1002 49D8
USB_EP11_OUT_MEM_ADR
USBOTG
0x1002 49DC
USB_EP11_IN_MEM_ADR
USBOTG
0x1002 49E0
USB_EP12_OUT_MEM_ADR
USBOTG
0x1002 49E4
USB_EP12_IN_MEM_ADR
USBOTG
0x1002 49E8
USB_EP13_OUT_MEM_ADR
USBOTG
0x1002 49EC
USB_EP13_IN_MEM_ADR
USBOTG
0x1002 49F0
USB_EP14_OUT_MEM_ADR
USBOTG
0x1002 49F4
USB_EP14_IN_MEM_ADR
USBOTG
0x1002 49F8
USB_EP15_OUT_MEM_ADR
USBOTG
0x1002 49FC
USB_EP15_IN_MEM_ADR
EP 15 IN: EP 15 Sys Memory Start Address Register
USBOTG
0x1002 4A00
through
0x1002 4A7C
USB_ETD0 DMABUF XFER
through
USB_ETD31 DMABUF XFER
ETD 0: ETD0 DMA Buffer Transfer Pointer Register
through ETD 31: ETD31 DMA Buffer Transfer Pointer
Register
USBOTG
0x1002 4A80
USB_EP0_OUT_BUF_INDX
EP 0 OUT: EP 0 Current buffer index register
USBOTG
0x1002 4A84
USB_EP0_IN_BUF_INDX
USBOTG
0x1002 4A88
USB_EP1_OUT_BUF_INDX
USBOTG
0x1002 4A8C
USB_EP1_IN_BUF_INDX
USBOTG
0x1002 4A90
USB_EP2_OUT_BUF_INDX
EP 5 IN: EP 5 Sys Memory Start Address Register
EP 6 OUT: EP 6 Sys Memory Start Address Register
EP 6 IN: EP 6 Sys Memory Start Address Register
EP 7 OUT: EP 7 Sys Memory Start Address Register
EP 7 IN: EP 7 Sys Memory Start Address Register
EP 8 OUT: EP 8 Sys Memory Start Address Register
EP 8 IN: EP 8 Sys Memory Start Address Register
EP 9 OUT: EP 9 Sys Memory Start Address Register
EP 9 IN: EP 9 Sys Memory Start Address Register
EP 10 OUT: EP 10 Sys Memory Start Address
Register
EP 10 IN: EP 10 Sys Memory Start Address Register
EP 11 OUT: EP 11 Sys Memory Start Address
Register
EP 11 IN: EP 11 Sys Memory Start Address Register
EP 12OUT: EP 12 Sys Memory Start Address
Register
EP 12 IN: EP 12 Sys Memory Start Address Register
EP 13 OUT: EP 13 Sys Memory Start Address
Register
EP 13 IN: EP 13 Sys Memory Start Address Register
EP 14 OUT: EP 14 Sys Memory Start Address
Register
EP 14 IN: EP 14 Sys Memory Start Address Register
EP 15 OUT: EP 15 Sys Memory Start Address
Register
EP 0 IN: EP 0 Current buffer index register
EP 1 OUT: EP 1 Current buffer index register
EP 1 IN: EP 1 Current buffer index register
EP 2 OUT: EP 2 Current buffer index register
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-25
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
USBOTG
0x1002 4A94
USB_EP2_IN_BUF_INDX
USBOTG
0x1002 4A98
USB_EP3_OUT_BUF_INDX
USBOTG
0x1002 4A9C
USB_EP3_IN_BUF_INDX
USBOTG
0x1002 4AA0
USB_EP4_OUT_BUF_INDX
USBOTG
0x1002 4AA4
USB_EP4_IN_BUF_INDX
USBOTG
0x1002 4AA8
USB_EP5_OUT_BUF_INDX
USBOTG
0x1002 4AAC
USB_EP5_IN_BUF_INDX
USBOTG
0x1002 4AB0
USB_EP6_OUT_BUF_INDX
USBOTG
0x1002 4AB4
USB_EP6_IN_BUF_INDX
USBOTG
0x1002 4AB8
USB_EP7_OUT_BUF_INDX
USBOTG
0x1002 4ABC
USB_EP7_IN_BUF_INDX
USBOTG
0x1002 4AC0
USB_EP8_OUT_BUF_INDX
USBOTG
0x1002 4AC4
USB_EP8_IN_BUF_INDX
USBOTG
0x1002 4AC8
USB_EP9_OUT_BUF_INDX
USBOTG
0x1002 4ACC
USB_EP9_IN_BUF_INDX
USBOTG
0x1002 4AD0
USB_EP10_OUT_BUF_INDX
USBOTG
0x1002 4AD4
USB_EP10_IN_BUF_INDX
USBOTG
0x1002 4AD8
USB_EP11_OUT_BUF_INDX
USBOTG
0x1002 4ADC
USB_EP11_IN_BUF_INDX
USBOTG
0x1002 4AE0
USB_EP12_OUT_BUF_INDX
USBOTG
0x1002 4AE4
USB_EP12_IN_BUF_INDX
USBOTG
0x1002 4AE8
USB_EP13_OUT_BUF_INDX
USBOTG
0x1002 4AEC
USB_EP13_IN_BUF_INDX
USBOTG
0x1002 4AF0
USB_EP14_OUT_BUF_INDX
USBOTG
0x1002 4AF4
USB_EP14_IN_BUF_INDX
USBOTG
0x1002 4AF8
USB_EP15_OUT_BUF_INDX
USBOTG
0x1002 4AFC
USB_EP15_IN_BUF_INDX
USBOTG
0x1002 4B00
through
0x1002 4FFF
Reserved
USBOTG
0x1002 5000
through
0x1002 5FFF
Data Memory
eMMA
0x1002 6000
PP_CNTL
Description
EP 2 IN: EP 2 Current buffer index register
EP 3 OUT: EP 3 Current buffer index register
EP 3 IN: EP 3 Current buffer index register
EP 4OUT: EP 4 Current buffer index register
EP 4 IN: EP 4 Current buffer index register
EP 5 OUT: EP 5 Current buffer index register
EP 5 IN: EP 5 Current buffer index register
EP 6 OUT: EP 6 Current buffer index register
EP 6 IN: EP 6 Current buffer index register
EP 7 OUT: EP 7 Current buffer index register
EP 7 IN: EP 7 Current buffer index register
EP 8 OUT: EP 8 Current buffer index register
EP 8 IN: EP 8 Current buffer index register
EP 9 OUT: EP 9 Current buffer index register
EP 9 IN: EP 9 Current buffer index register
EP 10 OUT: EP 10 Current buffer index register
EP 10 IN: EP 10 Current buffer index register
EP 11 OUT: EP 11 Current buffer index register
EP 11 IN: EP 11 Current buffer index register
EP 12OUT: EP 12 Current buffer index register
EP 12 IN: EP 12 Current buffer index register
EP 13 OUT: EP 13 Current buffer index register
EP 13 IN: EP 13 Current buffer index register
EP 14 OUT: EP 14 Current buffer index register
EP 14 IN: EP 14 Current buffer index register
EP 15 OUT: EP 15 Current buffer index register
EP 15 IN: EP 15 Current buffer index register
Reserved
USB OTG Data Memory
PP Control Register
i.MX21 Reference Manual, Rev. 3
3-26
Freescale Semiconductor
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
eMMA
0x1002 6004
PP_INTRCNTL
PP Interrupt Control Register
eMMA
0x1002 6008
PP_INTRSTATUS
PP interrupt Status Register
eMMA
0x1002 600C
PP_SOURCE_Y_PTR
eMMA
0x1002 6010
PP_SOURCE_CB_PTR
PP Source “CB” Frame Data Pointer Register
eMMA
0x1002 6014
PP_SOURCE_CR_PTR
PP Source “CR” Frame Data Pointer Register
eMMA
0x1002 6018
PP_DEST_RGB_PTR
PP Destination “RGB” Frame Start Address Register
eMMA
0x1002 601C
PP_QUANTIZER_PTR
PP Quantizer Start Address Register
eMMA
0x1002 6020
PP_PROCESS_FRAME_PARA
PP Process Frame Parameter, Width And Height
Register
eMMA
0x1002 6024
PP_SOURCE_FRAME_WIDTH
PP Source Frame Width Register
eMMA
0x1002 6028
PP_DEST_DISPLAY_WIDTH
eMMA
0x1002 602C
PP_DEST_IMAGE_SIZE
eMMA
0x1002 6030
PP_DEST_FRAME_FMT_CNTL
eMMA
0x1002 6034
PP Resize Table index Reg
eMMA
0x1002 6038
PP_CSC_COEFF_012
PP CSC Coefficient 0, 1, and 2 Register
eMMA
0x1002 603C
PP_CSC_COEFF_34
PP CSC Coefficient 3 and 4 Register
eMMA
0x1002 6100
through
0x1002 619C
PP_RESIZE_COEF_TBL
PP Resize Coefficient Table Register
eMMA
0x1002 6400
PrP_CNTL
eMMA
0x1002 6404
PrP_INTRCNTL
PrP Interrupt Control Register
eMMA
0x1002 6408
PrP_INTRSTATUS
PrP interrupt Status Register
eMMA
0x1002 640C
PrP_SOURCE_Y_PTR
eMMA
0x1002 6410
PrP_SOURCE_CB_PTR
PrP Source “CB” Frame Start Address Register
eMMA
0x1002 6414
PrP_SOURCE_CR_PTR
PrP Source “CR” Frame Start Address Register
eMMA
0x1002 6418
PrP_DEST_RGB1_PTR
PrP Destination “RGB” Frame-1 Start Address
Register
eMMA
0x1002 641C
PrP_DEST_RGB2_PTR
PrP Destination “RGB” Frame-2 Start Address
Register
eMMA
0x1002 6420
PrP_DEST_Y_PTR
eMMA
0x1002 6424
PrP_DEST_CB_PTR
PrP Destination “CB” Frame Start Address Register
eMMA
0x1002 6428
PrP_DEST_CR_PTR
PrP Destination “CR” Frame Start Address Register
eMMA
0x1002 642C
PrP_SOURCE_FRAME_SIZE
eMMA
0x1002 6430
PrP_CH1_LINE_STRIDE
eMMA
0x1002 6434
PrP_SRC_PIXEL_FORMAT_CNTL
PP Source “Y” FramE Data Pointer Register
PP Destination Display Width Register
PP Destination Image Size Register
PP Destination Frame Format Control Register
PP Resize Table Index Register
PrP Control Register
PrP Source “Y” Frame Start Address Register
PrP Destination “Y” Frame Start Address Register
PrP Source Frame Size Register
PrP Channel-1 Line stride Register
PrP Source Pixel Format Control Register
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-27
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
eMMA
0x1002 6438
PrP_CH1_PIXEL_FORMAT_CNTL
eMMA
0x1002 643C
PrP_CH1_OUT_IMAGE_SIZE
PrP CH1 Output Image Size Register
eMMA
0x1002 6440
PrP_CH2_OUT_IMAGE_SIZE
PrP CH2 Output Image Size Register
eMMA
0x1002 6444
PrP_SOURCE_LINE_STRIDE
PrP Source Line Stride Register
eMMA
0x1002 6448
PrP_CSC_COEFF_012
PrP CSC Coefficients 0, 1, and 2 Register
eMMA
0x1002 644C
PrP_CSC_COEFF_345
PrP CSC Coefficients 3, 4, and 5 Register
eMMA
0x1002 6450
PrP_CSC_COEFF_678
PrP CSC Coefficients 6, 7, and 8 Register
eMMA
0x1002 6454
PrP_CH1_HRESIZE_COEFF1
PrP CH1 Horizontal Resize Coefficients
Register
eMMA
0x1002 6458
PrP_CH1_HRESIZE_COEFF2
PrP CH1 Horizontal Resize Coefficients
Register
eMMA
0x1002 645C
PrP_CH1_HRESIZE_VALID
eMMA
0x1002 6460
PrP_CH1_VRESIZE_COEFF1
PrP CH1 Vertical Resize Coefficients
Register
eMMA
0x1002 6464
PrP_CH1_VRESIZE_COEFF2
PrP CH1 Vertical Resize Coefficients
Register
eMMA
0x1002 6468
PrP_CH1_VRESIZE_VALID
PrP CH1 Vertical Resize Valid Register
eMMA
0x1002 646C
PrP_CH2_HRESIZE_COEFF1
PrP CH2 Horizontal Resize Coefficients
Register
eMMA
0x1002 6470
PrP_CH2_HRESIZE_COEFF2
PrP CH2 Horizontal Resize Coefficients
Register
eMMA
0x1002 6474
PrP_CH2_HRESIZE_VALID
eMMA
0x1002 6478
PrP_CH2_VRESIZE_COEFF1
PrP CH2 Vertical Resize Coefficients
Register
eMMA
0x1002 647C
PrP_CH2_VRESIZE_COEFF2
PrP CH2 Vertical Resize Coefficients
Register
eMMA
0x1002 6480
PrP_CH2_VRESIZE_VALID
PLLCLK
0x1002 7000
CSCR
PLLCLK
0x1002 7004
MPCTL0
MPLL Control Register 0
PLLCLK
0x1002 7008
MPCTL1
MPLL Control Register 1
PLLCLK
0x1002 700C
SPCTL0
SPLL Control Register 0
PLLCLK
0x1002 7010
SPCTL1
SPLL Control Register 1
PLLCLK
0x1002 7014
OSC26MCTL
Oscillator 26M Register
PLLCLK
0x1002 7018
PCDR0
Peripheral Clock Divider Register 0
PLLCLK
0x1002 701C
PCDR1
Peripheral Clock Divider Register 1
PLLCLK
0x1002 7020
PCCR0
Peripheral Clock Control Register 0
PrP CH1 Pixel Format Control Register
PrP CH1 Horizontal Resize Valid Register
PrP CH2 Horizontal Resize Valid Register
PrP CH2 Vertical Resize Valid Register
Clock Source Control Register
i.MX21 Reference Manual, Rev. 3
3-28
Freescale Semiconductor
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
PLLCLK
0x1002 7024
PCCR1
Peripheral Clock Control Register 1
PLLCLK
0x1002 7028
CCSR
Clock Control Status Register
PLLCLK
0x1002 702C
PMCTL
PMOS Control Register
PLLCLK
0x1002 7030
PMCOUNT
PMOS Counter Register
PLLCLK
0x1002 7034
WKGDCTL
Wakeup Guard Mode Control Register
SYSCTRL
0x1002 7804
SIDR
Silicon ID Register
SYSCTRL
0x1002 7814
FMCR
Function Multiplexing Control Register
SYSCTRL
0x1002 7818
GPCR
Global Peripheral Control Register
SYSCTRL
0x1002 781C
WBCR
Well Bias Control Register
SYSCTRL
0x1002 7820
DSCR1
Driving Strength Control Register 1
SYSCTRL
0x1002 7824
DSCR2
Driving Strength Control Register 2
SYSCTRL
0x1002 7828
DSCR3
Driving Strength Control Register 3
SYSCTRL
0x1002 782C
DSCR4
Driving Strength Control Register 4
SYSCTRL
0x1002 7830
DSCR5
Driving Strength Control Register 5
SYSCTRL
0x1002 7834
DSCR6
Driving Strength Control Register 6
SYSCTRL
0x1002 7838
DSCR7
Driving Strength Control Register 7
SYSCTRL
0x1002 783C
DSCR8
Driving Strength Control Register 8
SYSCTRL
0x1002 7840
DSCR9
Driving Strength Control Register 9
SYSCTRL
0x1002 7844
DSCR10
Driving Strength Control Register 10
SYSCTRL
0x1002 7848
DSCR11
Driving Strength Control Register 11
SYSCTRL
0x1002 784C
DSCR12
Driving Strength Control Register 12
SYSCTRL
0x1002 7850
PCSR
Priority Control and Select Register
FIRI
0x1002 8000
FIRITCR
FIRI Transmit Control Register
FIRI
0x1002 8004
FIRITCTR
FIRI Transmit Count Register
FIRI
0x1002 8008
FIRIRCR
FIRI Receive Control Register
FIRI
0x1002 800C
FIRITSR
FIRI Transmit Status Register
FIRI
0x1002 8010
FIRIRSR
FIRI Receive Status Register
FIRI
0x1002 8014
FIRIXMITFIFO
Transmitter FIFO
FIRI
0x1002 8018
FIRIRCVRFIFO
Receiver FIFO
FIRI
0x1002 801C
FIRICR
FIRI Control Register
MAX
0x1003 F000
MPR0
Master Priority Register for Slave Port 0
MAX
0x1003 F100
MPR1
Master Priority Register for Slave Port 1
MAX
0x1003 F200
MPR2
Master Priority Register for Slave Port 2
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-29
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
MAX
0x1003 F300
MPR3
MAX
0x1003 F004
AMPR0
Alternate Master Priority Register for Slave Port 0
MAX
0x1003 F104
AMPR1
Alternate Master Priority Register for Slave Port 1
MAX
0x1003 F204
AMPR2
Alternate Master Priority Register for Slave Port 2
MAX
0x1003 F304
AMPR3
Alternate Master Priority Register for Slave Port 3
MAX
0x1003 F010
SGPCR0
General Purpose Control Register for Slave Port 0
MAX
0x1003 F110
SGPCR1
General Purpose Control Register for Slave Port 1
MAX
0x1003 F210
SGPCR2
General Purpose Control Register for Slave Port 2
MAX
0x1003 F310
SGPCR3
General Purpose Control Register for Slave Port 3
MAX
0x1003 F014
ASGPCR0
Alternate SGPCR for Slave Port 0
MAX
0x1003 F114
ASGPCR1
Alternate SGPCR for Slave Port 1
MAX
0x1003 F214
ASGPCR2
Alternate SGPCR for Slave Port 2
MAX
0x1003 F314
ASGPCR3
Alternate SGPCR for Slave Port 3
MAX
0x1003 F800
MGPCR0
General Purpose Control Register for Master Port 0
MAX
0x1003 F900
MGPCR1
General Purpose Control Register for Master Port 1
MAX
0x1003 FA00
MGPCR2
General Purpose Control Register for Master Port 2
MAX
0x1003 FB00
MGPCR3
General Purpose Control Register for Master Port 3
MAX
0x1003 FC00
MGPCR4
General Purpose Control Register for Master Port 4
MAX
0x1003 FD00
MGPCR5
General Purpose Control Register for Master Port 5
AITC
0x1004 0000
INTCNTL
Interrupt Control Register
AITC
0x1004 0004
NIMASK
Normal Interrupt Mask Register
AITC
0x1004 0008
INTENNUM
Interrupt Enable Number Register
AITC
0x1004 000C
INTDISNUM
Interrupt Disable Number Register
AITC
0x1004 0010
INTENABLEH
Interrupt Enable Register High
AITC
0x1004 0014
INTENABLEL
Interrupt Enable Register Low
AITC
0x1004 0018
INTTYPEH
Interrupt Type Register High
AITC
0x1004 001C
INTTYPEL
Interrupt Type Register Low
AITC
0x1004 0020
NIPRIORITY7
Normal Interrupt Priority Level Register 7
AITC
0x1004 0024
NIPRIORITY6
Normal Interrupt Priority Level Register 6
AITC
0x1004 0028
NIPRIORITY5
Normal Interrupt Priority Level Register 5
AITC
0x1004 002C
NIPRIORITY4
Normal Interrupt Priority Level Register 4
AITC
0x1004 0030
NIPRIORITY3
Normal Interrupt Priority Level Register 3
AITC
0x1004 0034
NIPRIORITY2
Normal Interrupt Priority Level Register 2
Master Priority Register for Slave Port 3
i.MX21 Reference Manual, Rev. 3
3-30
Freescale Semiconductor
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
AITC
0x1004 0038
NIPRIORITY1
Normal Interrupt Priority Level Register 1
AITC
0x1004 003C
NIPRIORITY0
Normal Interrupt Priority Level Register 0
AITC
0x1004 0040
NIVECSR
Normal Interrupt Vector and Status Register
AITC
0x1004 0044
FIVECSR
Fast Interrupt Vector and Status Register
AITC
0x1004 0048
INTSRCH
Interrupt Source Register High
AITC
0x1004 004C
INTSRCL
Interrupt Source Register Low
AITC
0x1004 0050
INTFRCH
Interrupt Force Register High
AITC
0x1004 0054
INTFRCL
Interrupt Force Register Low
AITC
0x1004 0058
NIPNDH
Normal Interrupt Pending Register High
AITC
0x1004 005C
NIPNDL
Normal Interrupt Pending Register Low
AITC
0x1004 0060
FIPNDH
Fast Interrupt Pending Register High
AITC
0x1004 0064
FIPNDL
Fast Interrupt Pending Register Low
CSI
0x8000 0000
CSICR1
CSI Control Register 1
CSI
0x8000 0004
CSICR2
CSI Control Register 2
CSI
0x8000 0008
CSISR
CSI
0x8000 000C
CSISTATR
CSI
0x8000 0010
CSIRXR
CSI
0x8000 0014
CSIRXCNT
CSI RX Count Register
CSI
0x8000 0018
CSIDEBUG
CSI Debug Register
CSI
0x8000 001C
CSICR3
CSI Control Register 3
BMI
0xA000 0000
BMICTLR1
BMI Control Register 1
BMI
0xA000 0004
BMICTLR2
BMI Control Register 2
BMI
0xA000 0008
BMISTR
BMI Status Register
BMI
0xA000 000C
BMIRXD
BMI RxFIFO
BMI
0xA000_0010
BMITXD
BMI TxFIFO
SDRAMC
0xDF00 0000
SDCTL0
SDRAM 0 Control Register
SDRAMC
0xDF00 0004
SDCTL1
SDRAM 1 Control Register
SDRAMC
0xDF00 0014
MISC
SDRAMC
0xDF00 0018
SDRST
WEIM
0xDF00 1000
CS0U
Chip Select 0 Upper Control Register
WEIM
0xDF00 1004
CS0L
Chip Select 0 Lower Control Register
WEIM
0xDF00 1008
CS1U
Chip Select 1 Upper Control Register
WEIM
0xDF00 100C
CS1L
Chip Select 1 Lower Control Register
CSI Status Register
CSI Statistic FIFO Register
CSI RxFIFO Register
SDRAM Miscellaneous Register
SDRAM Reset Register
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-31
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
WEIM
0xDF00 1010
CS2U
Chip Select 2 Upper Control Register
WEIM
0xDF00 1014
CS2L
Chip Select 2 Lower Control Register
WEIM
0xDF00 1018
CS3U
Chip Select 3 Upper Control Register
WEIM
0xDF00 101C
CS3L
Chip Select 3 Lower Control Register
WEIM
0xDF00 1020
CS4U
Chip Select 4 Upper Control Register
WEIM
0xDF00 1024
CS4L
Chip Select 4 Lower Control Register
WEIM
0xDF00 1028
CS5U
Chip Select 5 Upper Control Register
WEIM
0xDF00 102C
CS5L
Chip Select 5 Lower Control Register
WEIM
0xDF00 1030
EIM
EIM Configuration Register
PCMCIA
0xDF00 2000
PIPR
PCMCIA input pins register
PCMCIA
0xDF00 2004
PSCR
PCMCIA
0xDF00 2008
PER
PCMCIA Enable Register
PCMCIA
0xDF00 200C
PBR0
PCMCIA Base Register 0
PCMCIA
0xDF00 2010
PBR1
PCMCIA Base Register 1
PCMCIA
0xDF00 2014
PBR2
PCMCIA Base Register 2
PCMCIA
0xDF00 2018
PBR3
PCMCIA Base Register 3
PCMCIA
0xDF00 201C
PBR4
PCMCIA Base Register 4
PCMCIA
0xDF00 2028
POR0
PCMCIA Option Register 0
PCMCIA
0xDF00 202C
POR1
PCMCIA Option Register 1
PCMCIA
0xDF00 2030
POR2
PCMCIA Option Register 2
PCMCIA
0xDF00 2034
POR3
PCMCIA Option Register 3
PCMCIA
0xDF00 2038
POR4
PCMCIA Option Register 4
PCMCIA
0xDF00 2044
POFR0
PCMCIA Offset Register 0
PCMCIA
0xDF00 2048
POFR1
PCMCIA Offset Register 1
PCMCIA
0xDF00 204C
POFR2
PCMCIA Offset Register 2
PCMCIA
0xDF00 2050
POFR3
PCMCIA Offset Register 3
PCMCIA
0xDF00 2054
POFR4
PCMCIA Offset Register 4
PCMCIA
0xDF00 2060
PGCR
PCMCIA General Control Register
PCMCIA
0xDF00 2064
PGSR
PCMCIA General Status Register
NANDFC
0xDF00 3E00
NFC_BUFSIZE
NANDFC
0xDF00 3E02
BLOCK_ADD_LOCK
NANDFC
0xDF00 3E04
RAM_BUFFER_ADDRESS
PCMCIA Status Changed Register
Internal SRAM Size
NAND Flash Block Address for Lock Check
Buffer Number for Page Data Transfer To/From Flash
Memory
i.MX21 Reference Manual, Rev. 3
3-32
Freescale Semiconductor
Memory Map
Table 3-9. Register Map (continued)
Module Name
Address
Register Name
Description
NANDFC
0xDF00 3E06
NAND_FLASH_ADD
NAND Flash Address
NANDFC
0xDF00 3E08
NAND_FLASH_CMD
NAND Flash Command
NANDFC
0xDF00 3E0A
NFC_CONFIGURATION
NFC Internal Buffer Lock Control
NANDFC
0xDF00 3E0C
ECC_STATUS_RESULT
Controller Status/Result of Flash Operation
NANDFC
0xDF00 3E0E
ECC_RSLT_MAIN_AREA
ECC Error Position of Main Area Data Error
NANDFC
0xDF00 3E10
ECC_RSLT_SPARE_AREA
ECC Error Position of Spare Area Data Error
NANDFC
0xDF00 3E12
NF_WR_PROT
NANDFC
0xDF00 3E14
UNLOCK_START_BLK_ADD
Nand Flash Write Protection
Start Address for Write Protection Unlock
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
3-33
Memory Map
i.MX21 Reference Manual, Rev. 3
3-34
Freescale Semiconductor
Part 2
Core Technology
Chapter 4, “ARM9 Platform,” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 4-1
Chapter 5, “ARM926EJ-S Interrupt Controller (AITC),” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 5-1
Chapter 6, “Phase-Locked Loop (PLL), Clock and Reset Controller,” . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 6-1
Chapter 7, “AHB-Lite IP Interface (AIPI) Module,” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 7-1
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
1
i.MX21 Reference Manual, Rev. 3
2
Freescale Semiconductor
Chapter 4
ARM9 Platform
4.1
Introduction
The ARM926EJ-S™ is a member of the ARM9 family of general-purpose microprocessors. The
ARM926EJ-S processor is targeted at multi-tasking applications where full memory management, high
performance, low die size, and low-power are essential for mobile computing.
The ARM926EJ-S processor supports 16-bit and 32-bit ARM Thumb® instruction sets. These instruction
sets allows the processor to be utilized in applications that need to balance high performance execution
and high code density. The ARM926EJ-S processor includes features for efficient execution of Java byte
codes, providing Java performance similar to Just-In-Time (JIT) compilation, but without the associated
code overhead.
4.2
Features
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debug through the JTAG/Multi-ICE port on the i.MX21. The ARM926EJ-S
processor has a Harvard cached architecture and provides a complete high-performance processor
subsystem, that includes the following:
• ARM9EJ-S integer core
• Memory Management Unit (MMU)
• Separate instruction and data AMBA AHB interfaces
• 16 Kbyte instruction and data caches
The ARM926EJ-S processor implements ARM architecture version 5TEJ (ARMv5TEJ).
Refer to the ARM926EJ-S Technical Reference Manual (Document Number: ARM DDI0198B) for more
information.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
4-1
ARM9 Platform
i.MX21 Reference Manual, Rev. 3
4-2
Freescale Semiconductor
Chapter 5
ARM926EJ-S Interrupt Controller (AITC)
The ARM926EJ-S™ Interrupt Controller (AITC) is a 32-bit peripheral which collects interrupt requests
from up to 64 sources and provides an interface to the ARM926EJ-S core. The AITC includes software
controlled priority levels for normal interrupts. The AITC block diagram is shown in Figure 5-1 on page
5-2.
The AITC performs the following functions:
• Supports up to 64 interrupt sources
• Supports fast and normal interrupts
• Selects normal or fast interrupt request for any interrupt source
• Indicates pending interrupt sources via a register for normal and fast interrupts
• Indicates highest priority interrupt number via register (can be used as a table index)
• Independently enable or disable any interrupt source
• Provides a mechanism for software to schedule an interrupt
• Supports up to 16 software controlled priority levels for normal interrupts and priority masking
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
5-1
ARM926EJ-S Interrupt Controller (AITC)
aitc_fiq
64
INTENABLE
fipend
64
64
intin
FORCE
64
64
64
64
nipend
INTTYPE
6
Priority
Encoder
Software
Priority
Encoder
fivector
nivector
6
aitc_irq
aitc_rdata_ovr
NM
32
haddr
Equals to
0x0000_0018?
Equals to
0x0000_001C?
Opcode
Generator
32
aitc_rdata
hready
FM
Figure 5-1. AITC Block Diagram
The interrupt controller consists of a set of control registers and associated logic to perform interrupt
masking, and priority support of normal interrupts.
The interrupt source registers (INTSRCH / INTSRCL) are a pair of 32-bit status registers with a single
interrupt source associated with each of the 64 bits. An interrupt line or set of interrupt lines are routed
from each interrupt source to the INTSRCH or INTSRCL register. This allows up to 64 distinct interrupt
sources in an implementation. Interrupt requests may be forced to be asserted by way of the interrupt force
registers (INTFRCH / INTFRCL). Each bit in this register is logically “OR-ed” with the corresponding
hardware request line prior to feeding the INTSRCH or INTSRCL register inputs.
There is a corresponding set of interrupt enable registers (INTENABLEH / INTENABLEL), also 32-bits
wide which allow individual bit masking of the INTSRCH / INTSRCL registers. There is also a
corresponding set of interrupt type register (INTTYPEH / INTTYPEL) which selects whether an interrupt
source will generate a normal or fast interrupt to the ARM926EJ-S core.
There is a corresponding set of normal interrupt pending registers (NIPNDH / NIPNDL) which indicate
pending normal interrupt requests. These registers are equivalent to the logical AND of the interrupt source
registers (INTSRCH / INTSRCL), the interrupt enable registers (INTENABLEH / INTENABLEL), and
the NOT of the interrupt type registers (INTTYPEH / INTTYPEL). (Refer to Figure 5-1 on page 5-2) The
NIPNDH / NIPNDL register bits are bit-wise “NOR-ed” together to form the nIRQ signal routed to the
ARM926EJ-S core. This core input signal is maskable by the normal interrupt disable bit (I bit) in the
processor status register (CPSR). The normal interrupt vector register (NIVECSR) indicates the vector
index of highest priority pending normal interrupt.
i.MX21 Reference Manual, Rev. 3
5-2
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
There is a corresponding set of fast interrupt pending registers (FIPNDH / FIPNDL) which indicate
pending fast interrupt requests. These registers are equivalent to the logical AND of the interrupt source
registers (INTSRCH / INTSRCL), the interrupt enable registers (INTENABLEH / INTENABLEL), and
the interrupt type registers (INTTYPEH / INTTYPEL). (Refer to Figure 5-1 on page 5-2) The FIPNDH /
FIPNDL register bits are bit-wise “NOR-ed” together to form the nFIQ signal routed to the ARM926EJ-S
core. This core input signal is maskable by the fast interrupt disable bit (F bit) in the CPSR. The fast
interrupt vector register (FIVECSR) indicates the vector index of highest priority pending fast interrupt.
All interrupt controller registers are readable and writable in privileged mode only. Writes attempted to
read-only registers will be ignored. These registers can be only modified using 32-bit writes.
The INTFRCH / INTFRCL registers are provided for software generation of interrupts. By enabling
interrupts for these bit positions, software can force an interrupt request. This register can also be used to
debug hardware interrupt service routines by providing an alternate method of interrupt assertion.
The interrupt requests are prioritized in the following sequence:
1. Fast interrupt requests, in order of highest number
2. Normal interrupt requests, in order of highest priority level, then highest source number with the
same priority
The AITC provides 16 software controlled priority levels for normal interrupts. Every interrupt can be
placed in any priority level. The AITC also provides a normal interrupt priority level mask (NIMASK)
which disables any interrupt with a priority level lower than or equal to the mask. If a level 0 normal
interrupt and a level 1 normal interrupt are asserted at the same time, the level 1 normal interrupt will be
selected assuming that NIMASK has not disabled level 1 normal interrupts. If two level 1 normal interrupts
are asserted at the same time, the level 1 normal interrupt with the highest source number will be selected,
also assuming that NIMASK has not disabled level 1 normal interrupts.
5.1
Programming Model
The AITC module has 26 registers. All of these registers are single cycle access as the AITC sits on the
native bus of the ARM926EJ-S core. This section provides detailed descriptions of the various AITC
registers and are summarized in Table 5-1.
Table 5-1. AITC Register Summary
Name
31 30 29 28 27 26
INTCNTL R 0 0 0 0 0 0
(0x1004 0000) W
25
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
ABFLAG ABFEN
NIDIS FIDIS NIAD FIAD
0 0 0 0 0 0 0 0 0 0 000 0 0 0 0 0 0
R 0 0 0 0 0 0
NIMASK
(0x1004 0004) W
0
0
0
0
0
0
0
0 0 0 0 0 0 0 0 0 0 000 0
INTENNUM R 0 0 0 0 0 0
(0x1004 0008) W
0
0
0
0
0
0
0
0 0 0 0 0 0 0 0 0 0 000 0 0 0 0 0 0
INTDISNUM R 0 0 0 0 0 0
(0x1004 000C) W
0
0
0
0
0
0
0
0 0 0 0 0 0 0 0 0 0 000 0 0 0 0 0 0
INTENABLEH R
(0x1004 0010) W
NIMASK
ENNUM
DISNUM
INTENABLE[63:32]
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
5-3
ARM926EJ-S Interrupt Controller (AITC)
Table 5-1. AITC Register Summary (continued)
Name
31 30 29 28 27 26
25
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTENABLEL R
(0x1004 0014) W
INTENABLE[31:0]
INTTYPEH R
(0x1004 0018) W
INTTYPE[63:32]
INTTYPEL R
(0x1004 001C) W
INTTYPE[31:0]
NIPRIORITY7 R
(0x1004 0020) W
NIPR63
NIPR62
NIPR61
NIPR60
NIPR59
NIPR58
NIPR57
NIPR56
NIPRIORITY6 R
(0x1004 0024) W
NIPR55
NIPR54
NIPR53
NIPR52
NIPR51
NIPR50
NIPR49
NIPR48
NIPRIORITY5 R
(0x1004 0028) W
NIPR47
NIPR46
NIPR45
NIPR44
NIPR43
NIPR42
NIPR41
NIPR40
NIPRIORITY4 R
(0x1004 002C) W
NIPR39
NIPR38
NIPR37
NIPR36
NIPR35
NIPR34
NIPR33
NIPR32
NIPRIORITY3 R
(0x1004 0030) W
NIPR31
NIPR30
NIPR29
NIPR28
NIPR27
NIPR26
NIPR25
NIPR24
NIPRIORITY2 R
(0x1004 0034) W
NIPR23
NIPR22
NIPR21
NIPR20
NIPR19
NIPR18
NIPR17
NIPR16
NIPRIORITY1 R
(0x1004 0038) W
NIPR15
NIPR14
NIPR13
NIPR12
NIPR11
NIPR10
NIPR9
NIPR8
NIPRIORITY0 R
(0x1004 003C) W
NIPR7
NIPR6
NIPR5
NIPR4
NIPR3
NIPR2
NIPR1
NIPR0
NIVECSR R
(0x1004 0040) W
NIVECTOR
NIPRILVL
FIVECSR R
(0x1004 0044) W
FIVECTOR
INTSRCH R
(0x1004 0048) W
INTIN[63:32]
INTSRCL R
(0x1004 004C) W
INTIN[31:0]
INTFRCH R
(0x1004 0050) W
FORCE[63:32]
INTFRCL R
(0x1004 0054) W
FORCE[31:0]
R
NIPNDH
(0x1004 0058) W
NIPEND[63:32]
R
NIPNDL
(0x1004 005C) W
NIPEND[31:0]
R
FIPNDH
(0x1004 0060) W
FIPEND[63:32]
R
FIPNDL
(0x1004 0064) W
FIPEND[31:0]
i.MX21 Reference Manual, Rev. 3
5-4
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
5.1.1
Interrupt Control Register (INTCNTL)
The interrupt control register (INTCNTL) controls the interrupts in the AITC. Both normal interrupts and
fast interrupts can be enabled to jump directly to the interrupt service routine. For fast interrupts, it may be
faster to begin to fast interrupt routine at 0x0000_001C instead of jumping to a service routine.
The vector table can be sourced in high memory, 0xFFFF_FF00 to 0xFFFF_FFFF, or in low memory. If
the vector table is located in low memory (MD=1), a register has been provided to control where the vector
table is located.
This register is located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed to
in privileged mode. This register can be only modified using 32-bit writes.
INTCNTL
BIT
Interrupt Control Register
31
30
29
28
27
26
25
24
23
ABFLAG ABFEN
0x10040000
22
21
20
19
18
17
NIDIS FIDIS NIAD FIAD
16
MD
TYPE
rw
rw
rw
rw
rw
rw
r / w1c
rw
rw
rw
rw
rw
rw
r
r
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POINTER
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-2. Interrupt Control Register Description
Name
Description
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–26
Settings
N/A
ABFLAG
Bit 25
Core Arbitration Prioritization Risen Flag—This status bit indicates that the 0 = AITC is not affecting the bus
AITC is asserting the aitc_rise_arb signal to rise the priority level of the ARM
arbitration priority levels
core in the bus arbitration logic. This signal is directly tied to the aitc_rise_arb 1 = AITC is rising ARM core priority
output signal.
level in bus arbitration logic.
When the ABFEN bit is cleared, this bit will indicate the current value of the
aitc_rise_arb signal to the ARM core. This bit will be set if the nFIQ is asserted
and the FIAD bit is set or if the nIRQ is asserted and the NIAD bit is set.
When the ABFEN bit is set, this bit will be keep the “1” until written to with a
“1”. This bit will remain set on either of the above conditions normally set the
ABFLAG bit.
ABFEN
Bit 24
ABFLAG Sticky Enable—This bit controls whether the ABFLAG bit is sticky. 0 = ABFLAG bit is normal
This allows the arbitration logic to keep the ARM core at the higher priority
1 = ABFLAG bit is sticky and requires
level until the ABFLAG bit is written.
a write of 1 to clear the bit.
Reserved
Bit 23
Reserved—This bit is reserved and should read 0.
NIDIS
Bit 22
Normal Interrupt Disable—This bit, when set, disables the generation of the 0 = Does not affect the normal
normal interrupt signal. This bit is similar to the I bit of the ARM926EJ-S core.
interrupt generation
1 = Disable all normal interrupts
N/A
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
5-5
ARM926EJ-S Interrupt Controller (AITC)
Table 5-2. Interrupt Control Register Description (continued)
Name
Description
Settings
FIDIS
Bit 21
Fast Interrupt Disable—This bit, when set, disables the generation of the fast 0 = Does not affect the fast interrupt
interrupt signal. This bit is similar to the F bit of the ARM926EJ-S core.
generation
1 = Disable all fast interrupts
NIAD
Bit 20
Normal Interrupt Arbiter Rise ARM Level—This bit, when asserted,
0 = Disregard the normal interrupt
increases the bus arbitration priority of the ARM core when the normal
flag when evaluating bus
interrupt signal (nIRQ) is asserted. If an alternate master has ownership of the
requests
bus when a normal interrupt occurs, the bus will be given back to the
1 = Normal interrupt flag increases
processor core after the DMA device has completed its accesses. The NIAD
the bus arbitration priority of the
bit does not affect alternate master accesses that are in progress.
ARM core to decrease the
To prevent an alternate master from accessing the bus during an interrupt
latency of the interrupt service
service routine, the interrupt flag must not be cleared until the end of the
routine.
service routine. Another option is to use the ABFEN and ABFLAG bits.
FIAD
Bit 19
Fast Interrupt Arbiter Rise ARM Level—This bit functions the same as the 0 = Disregard the fast interrupt flag
NIAD bit except for the fast interrupts (nFIQ).
when evaluating bus requests
1 = Fast interrupt flag increases the
bus arbitration priority of the
ARM core to decrease the
latency of the interrupt service
routine.
Reserved Reserved—These bits are reserved and should read 0.
Bits 18–17
N/A
MD
Bit 16
0 = Interrupt vector table located in
high memory from
0xFFFF_FF00 to 0xFFFF_FFFF
1 = Interrupt vector table located in
low memory from POINTER to
POINTER+0xFF
Interrupt Vector Table Mode—Indicates whether the interrupt vector is
located in high memory or low memory.
Reserved Reserved—These bits are reserved and should read 0.
Bits 15–12
N/A
POINTER
Bits 11–2
Interrupt Vector Table Pointer—Indicates start of the vector table when in
low memory (MD=1).
The value stored in the 10 bits, times
4, must be set greater than or equal
to 0x0000_0024 and less than or
equal to 0x0000_0F00.
Only word-aligned tables are
allowed, and two zeros are added in
the LSBs when this value is used by
the AITC. The value stored here is
left shifted by two bits, so the actual
table vector can be directly written
into the appropriate bits.
Reserved
Bits 1–0
Reserved—These bits are reserved and should read 0.
N/A
i.MX21 Reference Manual, Rev. 3
5-6
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
5.1.2
Normal Interrupt Mask Register (NIMASK)
The normal interrupt mask register (NIMASK) controls the normal interrupt mask level. All normal
interrupts with a priority level lower than or equal to the NIMASK will be disabled. The priority level of
normal interrupts are determined by the normal interrupt priority level registers (NIPRIORITY7,
NIPRIORITY6, NIPRIORITY5, NIPRIORITY4, NIPRIORITY3, NIPRIORITY2, NIPRIORITY1, and
NIPRIORITY0). The reset state of this register will not disable any normal interrupts.
Writing all 1’s, or -1, to the NIMASK will set the normal interrupt mask to -1 which will not disable any
normal interrupt priority levels.
This hardware mechanism can be used to create reentrant normal interrupt routines by disabling lower
priority normal interrupts. Refer to Section 5.2.7 for more details on the use of the NIMASK register.
This register is located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed to
in privileged mode. This register can be only modified using 32-bit writes.
NIMASK
Normal Interrupt Mask Register
0x10040004
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESE
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIMASK
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESE
T
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Table 5-3. Normal Interrupt Mask Register Description
Name
Description
Settings
Reserved
Bits 31–5
Reserved—These bits are reserved and should read 0.
N/A
NIMASK
Bits 4–0
Normal Interrupt Mask—Controls normal interrupt mask 0 = Disable priority level 0 normal interrupts
level. All normal interrupts of priority level lower than or 1 = Disable priority level 1 and lower normal interrupts
equal to the NIMASK will be disabled.
...
0xE (14) = Disable priority level 14 and lower normal
interrupts
0xF (15) = Disable all normal interrupts
0x10–0x1F = Do not disable any normal interrupts
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
5-7
ARM926EJ-S Interrupt Controller (AITC)
5.1.3
Interrupt Enable Number Register (INTENNUM)
The interrupt enable number register (INTENNUM) provides a hardware accelerated enabling of
interrupts. Any write to this register will enable one interrupt source. If the 6 LSBs are equal 000000, then
interrupt source 0 is enabled. If the 6 LSBs equal 000001, then interrupt source 1 is enabled. And so forth.
This register is decoded into a one hot mask which will be logically OR-ed with the INTENABLEH /
INTENABLEL register.
This hardware mechanism alleviates the need for an atomic read/modify/write sequence to enable an
interrupt source. To enable interrupts 10 and 20, the software need only preform two writes to the AITC:
first write 10 to INTENNUM register, then write 20 to INTENNUM register (the order of the writes is
irrelevant).
This register is located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed to
in privileged mode. This register can be only modified using 32-bit writes. This register will always read
back all 0s.
INTENNUM
Interrupt Enable Number Register
0x10040008
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESE
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENNUM
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
slfclr
slfclr
slfclr
slfclr
slfclr
slfclr
RESE
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-4. Interrupt Enable Number Register Description
Name
Description
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–6
ENNUM
Bits 5–0
Settings
N/A
Interrupt Enable Number—Writing to this register will enable the interrupt source 0 = Enable interrupt source 0
associated with this value.
1 = Enable interrupt source 1
...
63 = Enable interrupt source 63
i.MX21 Reference Manual, Rev. 3
5-8
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
5.1.4
Interrupt Disable Number Register (INTDISNUM)
The interrupt disable number register (INTDISNUM) provides a hardware accelerated disabling of
interrupts. Any write to this register will disable one interrupt source. If the 6 LSBs are equal 000000, then
interrupt source 0 is disabled. If the 6 LSBs equal 000001, then interrupt source 1 is disabled. And so forth.
This register is decoded into a one hot mask which will be inverted and logically AND-ed with the
INTENABLEH / INTENABLEL register.
This hardware mechanism alleviates the need for an atomic read/modify/write sequence to disable an
interrupt source. To disable interrupts 10 and 20, the software need only preform two writes to the AITC:
first write 10 to INTDISNUM register, then write 20 to INTDISNUM register (the order of the writes is
irrelevant).
This register is located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed to
in privileged mode. This register can be only modified using 32-bit writes. This register will always read
back all 0s.
INTDISNUM
Interrupt Disable Number Register
0x1004000C
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DISNUM
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
slfclr
slfclr
slfclr
slfclr
slfclr
slfclr
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-5. Interrupt Disable Number Register Description
Name
Description
Settings
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
N/A
DISNUM
Bits 5–0
Interrupt Disable Number—Writing to this register will disable the interrupt
source associated with this value.
0 = Disable interrupt source 0
1 = Disable interrupt source 1
...
63 = Disable interrupt source 63
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
5-9
ARM926EJ-S Interrupt Controller (AITC)
5.1.5
Interrupt Enable Register High (INTENABLEH)
and Low (INTENABLEL)
The interrupt enable register high (INTENABLEH) and the interrupt enable register low (INTENABLEL)
are used to enable pending interrupt requests to the core. Each bit in this register corresponds to an interrupt
source available in the system. The reset state of these registers are all interrupts masked.
This register can be updated by various methods: writing directly to the INTENABLEH / INTENABLEL
registers, setting bits with the INTENNUM register, or clearing bits with the INTDISNUM register.
These registers are located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed
to in privileged mode. These registers can be only modified using 32-bit writes.
INTENABLEH
BIT
31
Interrupt Enable Register High
30
29
28
27
26
25
24
23
0x10040010
22
21
20
19
18
17
16
INTENABLE[63:48]
TYPE
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTENABLE[47:32]
TYPE
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INTENABLEL
BIT
31
Interrupt Enable Register Low
30
29
28
27
26
25
24
23
0x10040014
22
21
20
19
18
17
16
INTENABLE[31:16]
TYPE
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTENABLE[15:0]
TYPE
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-6. Interrupt Enable Register High and Low Register Description
Name
INTENABLE
Bits 31–0
Description
Settings
Interrupt Enable—This bit enables the corresponding interrupt source 0 = Interrupt disabled
to request a normal interrupt or a fast interrupt. A reset operation clears 1 = Interrupt enabled and will
this bit.
generate a normal or fast
If an enable bit is set and the corresponding interrupt source is asserted,
interrupt upon assertion
the interrupt controller will assert a normal or a fast interrupt request
depending on associated INTTYPEH/INTTYPEL setting.
i.MX21 Reference Manual, Rev. 3
5-10
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
5.1.6
Interrupt Type Register High (INTTYPEH) and Low (INTTYPEL)
The interrupt type register high (INTTYPEH) and the interrupt type register low (INTTYPEL) are used to
select whether a pending interrupt source, when enabled with the INTENABLEH / INTENABLEL, will
create a normal interrupt or a fast interrupt to the core. Each bit in this register corresponds to an interrupt
source available in the system. The reset state of these registers will cause all enabled interrupt sources to
generate a normal interrupt.
These registers are located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed
to in privileged mode. These registers can be only modified using 32-bit writes.
INTTYPEH
BIT
31
Interrupt Type Register High
30
29
28
27
26
25
24
23
0x10040018
22
21
20
19
18
17
16
INTTYPE[63:48]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESE
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTTYPE[47:32]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESE
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INTTYPEL
BIT
Interrupt Type Register Low
31
30
29
28
27
26
25
24
23
0x1004001C
22
21
20
19
18
17
16
INTTYPE[31:16]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTTYPE[15:0]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-7. Interrupt Type Register High and Low Register Description
Name
INTTYPE
Bits 31–0
Description
Settings
Interrupt Type—This bit controls whether the
0 = Interrupt source will generate a normal
corresponding interrupt source will request a normal
interrupt (nIRQ)
interrupt or a fast interrupt.
1 = Interrupt source will generate a fast interrupt
If a INTTYPE bit is set and the corresponding interrupt
(nFIQ)
source is asserted, the interrupt controller will assert a fast
interrupt request.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
5-11
ARM926EJ-S Interrupt Controller (AITC)
5.1.7
Normal Interrupt Priority Level Registers (NIPRIORITYn)
The normal interrupt priority level registers (NIPRIORITY7, NIPRIORITY6, NIPRIORITY5,
NIPRIORITY4, NIPRIORITY3, NIPRIORITY2, NIPRIORITY1, and NIPRIORITY0) provide a
software controllable prioritization of normal interrupts. Normal interrupts with a higher priority level will
preempt normal interrupts with a lower priority. The reset state of these registers forces all normal
interrupts to the lowest priority level.
If a level 0 normal interrupt and a level 1 normal interrupt are asserted at the same time, the level 1 normal
interrupt will be selected assuming that NIMASK has not disabled level 1 normal interrupts. If two level
1 normal interrupts are asserted at the same time, the level 1 normal interrupt with the highest source
number will be selected, also assuming that NIMASK has not disabled level 1 normal interrupts.
These registers are located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed
to in privileged mode. These registers can be only modified using 32-bit writes.
NIPRIORITY7
BIT
31
Normal Interrupt Priority Level Register 7
30
29
28
27
NIPR63
26
25
24
23
NIPR62
22
0x10040020
21
20
19
NIPR61
18
17
16
NIPR60
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPR59
NIPR58
NIPR57
NIPR56
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-8. Normal Interrupt Priority Level Register 7 Description
Name
NIPR63
Bits 31–28
NIPR62
Bits 27–24
NIPR61
Bits 23–20
NIPR60
Bits 19–16
NIPR59
Bits 15–12
NIPR58
Bits 11–8
NIPR57
Bits 7–4
NIPR56
Bits 3–0
Description
Settings
Normal Interrupt Priority Level—Selects the software controlled priority 0 = Lowest priority normal interrupt
level for the associated normal interrupt source.
...
These registers do not affect the prioritization of fast interrupt priorities. 15 = Highest priority normal interrupt
i.MX21 Reference Manual, Rev. 3
5-12
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
NIPRIORITY6
BIT
31
Normal Interrupt Priority Level Register 6
30
29
28
27
NIPR55
26
25
24
23
NIPR54
22
0x10040024
21
20
19
NIPR53
18
17
16
NIPR52
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPR51
NIPR50
NIPR49
NIPR48
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-9. Normal Interrupt Priority Level Register 6 Description
Name
NIPR55
Bits 31–28
NIPR54
Bits 27–24
NIPR53
Bits 23–20
NIPR52
Bits 19–16
NIPR51
Bits 15–12
NIPR50
Bits 11–8
NIPR49
Bits 7–4
NIPR48
Bits 3–0
Description
Normal Interrupt Priority Level—Selects the software controlled
priority level for the associated normal interrupt source.
These registers do not affect the prioritization of fast interrupt priorities.
Settings
0 = Lowest priority normal interrupt
...
15 = Highest priority normal interrupt
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
5-13
ARM926EJ-S Interrupt Controller (AITC)
NIPRIORITY5
BIT
31
Normal Interrupt Priority Level Register 5
30
29
28
27
NIPR47
26
25
24
23
22
NIPR46
0x10040028
21
20
19
NIPR45
18
17
16
NIPR44
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPR43
NIPR42
NIPR41
NIPR40
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-10. Normal Interrupt Priority Level Register 5 Description
Name
NIPR47
Bits 31–28
NIPR46
Bits 27–24
NIPR45
Bits 23–20
NIPR44
Bits 19–16
NIPR43
Bits 15–12
NIPR42
Bits 11–8
NIPR41
Bits 7–4
NIPR40
Bits 3–0
Description
Normal Interrupt Priority Level—Selects the software controlled
priority level for the associated normal interrupt source.
Settings
0 = Lowest priority normal interrupt
...
15 = Highest priority normal interrupt
These registers do not affect the prioritization of fast interrupt
priorities.
i.MX21 Reference Manual, Rev. 3
5-14
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
NIPRIORITY4
BIT
31
Normal Interrupt Priority Level Register 4
30
29
28
27
NIPR39
26
25
24
23
NIPR38
22
0x1004002C
21
20
19
NIPR37
18
17
16
NIPR36
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPR35
NIPR34
NIPR33
NIPR32
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-11. Normal Interrupt Priority Level Register 4 Description
Name
NIPR39
Bits 31–28
NIPR38
Bits 27–24
NIPR37
Bits 23–20
NIPR36
Bits 19–16
NIPR35
Bits 15–12
NIPR34
Bits 11–8
NIPR33
Bits 7–4
NIPR32
Bits 3–0
Description
Settings
Normal Interrupt Priority Level—Selects the software controlled priority 0 = Lowest priority normal interrupt
level for the associated normal interrupt source.
...
These registers do not affect the prioritization of fast interrupt priorities. 15 = Highest priority normal interrupt
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
5-15
ARM926EJ-S Interrupt Controller (AITC)
NIPRIORITY3
BIT
31
Normal Interrupt Priority Level Register 3
30
29
28
27
NIPR31
26
25
24
23
NIPR30
22
0x10040030
21
20
19
NIPR29
18
17
16
NIPR28
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPR27
NIPR26
NIPR25
NIPR24
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-12. Normal Interrupt Priority Level Register 3 Description
Name
NIPR31
Bits 31–28
NIPR30
Bits 27–24
NIPR29
Bits 23–20
NIPR28
Bits 19–16
NIPR27
Bits 15–12
NIPR26
Bits 11–8
NIPR25
Bits 7–4
NIPR24
Bits 3–0
Description
Settings
Normal Interrupt Priority Level—Selects the software controlled priority 0 = Lowest priority normal interrupt
level for the associated normal interrupt source.
...
15 = Highest priority normal interrupt
These registers do not affect the prioritization of fast interrupt priorities.
i.MX21 Reference Manual, Rev. 3
5-16
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
NIPRIORITY2
BIT
31
Normal Interrupt Priority Level Register 2
30
29
28
27
NIPR23
26
25
24
23
NIPR22
22
0x10040034
21
20
19
NIPR21
18
17
16
NIPR20
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPR19
NIPR18
NIPR17
NIPR16
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-13. Normal Interrupt Priority Level Register 2 Description
Name
NIPR23
Bits 31–28
NIPR22
Bits 27–24
NIPR21
Bits 23–20
NIPR20
Bits 19–16
NIPR19
Bits 15–12
NIPR18
Bits 11–8
NIPR17
Bits 7–4
NIPR16
Bits 3–0
Description
Settings
Normal Interrupt Priority Level—Selects the software controlled priority 0 = Lowest priority normal interrupt
level for the associated normal interrupt source.
...
15 = Highest priority normal interrupt
These registers do not affect the prioritization of fast interrupt priorities.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
5-17
ARM926EJ-S Interrupt Controller (AITC)
NIPRIORITY1
BIT
31
Normal Interrupt Priority Level Register 1
30
29
28
27
NIPR15
26
25
24
23
NIPR14
22
0x10040038
21
20
19
NIPR13
18
17
16
NIPR12
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPR11
NIPR10
NIPR9
NIPR8
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-14. Normal Interrupt Priority Level Register 1 Description
Name
NIPR15
Bits 31–28
NIPR14
Bits 27–24
NIPR13
Bits 23–20
NIPR12
Bits 19–16
NIPR11
Bits 15–12
NIPR10
Bits 11–8
NIPR9
Bits 7–4
NIPR8
Bits 3–0
Description
Settings
Normal Interrupt Priority Level—Selects the software controlled priority 0 = Lowest priority normal interrupt
level for the associated normal interrupt source.
...
15 = Highest priority normal interrupt
These registers do not affect the prioritization of fast interrupt priorities.
i.MX21 Reference Manual, Rev. 3
5-18
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
NIPRIORITY0
BIT
31
Normal Interrupt Priority Level Register 0
30
29
28
27
NIPR7
26
25
24
23
NIPR6
22
0x1004003C
21
20
19
NIPR5
18
17
16
NIPR4
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPR3
NIPR2
NIPR1
NIPR0
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-15. Normal Interrupt Priority Level Register 0 Description
Name
NIPR7
Bits 31–28
NIPR6
Bits 27–24
NIPR5
Bits 23–20
NIPR4
Bits 19–16
NIPR3
Bits 15–12
NIPR2
Bits 11–8
NIPR1
Bits 7–4
NIPR0
Bits 3–0
Description
Normal Interrupt Priority Level—Selects the software controlled
priority level for the associated normal interrupt source.
Settings
0 = Lowest priority normal interrupt
...
15 = Highest priority normal interrupt
These registers do not affect the prioritization of fast interrupt priorities.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
5-19
ARM926EJ-S Interrupt Controller (AITC)
5.1.8
Normal Interrupt Vector and Status Register (NIVECSR)
The normal interrupt vector and status register (NIVECSR) provides the priority of the highest pending
normal interrupt and provides the vector index of the interrupt’s service routine. This hardware mechanism
replaces the previous necessity for core support of the FF1 command. This number can be directly used as
an index into a vector table to select the highest pending normal interrupt source.
This read-only register is located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be
accessed to in privileged mode.
NIVECSR
BIT
Normal Interrupt Vector and Status Register
31
30
29
28
27
26
25
24
23
0x10040040
22
21
20
19
18
17
16
NIVECTOR
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPRILVL
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 5-16. Normal Interrupt Vector and Status Register Description
Name
Description
Settings
NIVECTOR Normal Interrupt Vector—Indicates vector index for the
Bits 31–16 highest pending normal interrupt.
-1 = No normal interrupt request pending
0 = Interrupt 0 highest priority pending normal
interrupt
1 = Interrupt 1 highest priority pending normal
interrupt
...
63 = Interrupt 63 highest priority pending normal
interrupt
64+ (not -1) = unused, will not occur
NIPRILVL
Bits 15–0
-1 = No normal interrupt request pending
0 = Highest priority normal interrupt is level 0
1 = Highest priority normal interrupt is level 1
...
15 = Highest priority normal interrupt is level 15
16+ (not -1) = unused, will not occur
Normal Interrupt Priority Level—Indicates the priority
level of the highest priority normal interrupt. This number
can be written to the NIMASK to disable the current priority
normal interrupts to build a reentrant normal interrupt
system.
i.MX21 Reference Manual, Rev. 3
5-20
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
5.1.9
Fast Interrupt Vector and Status Register (FIVECSR)
The fast interrupt vector and status register (FIVECSR) provides the vector index for the highest priority
active fast interrupt’s service routine (the higher the source number of the fast interrupt, the higher the
priority level). This hardware mechanism replaces the previous necessity for core support of the FF1
command. This number can be directly used as an index into a vector table to select the highest pending
fast interrupt source.
This read-only register is located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be
accessed to in privileged mode.
FIVECSR
BIT
Fast Interrupt Vector and Status Register
31
30
29
28
27
26
25
24
23
0x10040044
22
21
20
19
18
17
16
FIVECTOR[31:16]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESE
T
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIVECTOR[15:0]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESE
T
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 5-17. Fast Interrupt Vector and Status Register Description
Name
FIVECTOR
Bits 31–0
Description
Fast Interrupt Vector—Indicates vector index for the
highest pending fast interrupt.
Settings
-1 = No fast interrupt request pending
0 = Interrupt 0 highest pending fast interrupt
1 = Interrupt 1 highest pending fast interrupt
...
63 = Interrupt 63 highest pending fast interrupt
64+ (not -1) = unused, will not occur
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
5-21
ARM926EJ-S Interrupt Controller (AITC)
5.1.10
Interrupt Source Register High (INTSRCH) and Low (INTSRCL)
The interrupt source register high (INTSRCH) and the interrupt source register low (INTSRCL) are each
32 bits wide. INTSRCH and INTSRCL reflect the status of all interrupt request inputs into the interrupt
controller. Unused bit positions always read zero (no request pending). The state of this register out of reset
is determined by the peripheral circuits generating the requests; normally, the requests would be inactive.
These read-only registers are located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only
be accessed in privileged mode.
INTSRCH
BIT
Interrupt Source Register High
31
30
29
28
27
26
25
24
23
0x10040048
22
21
20
19
18
17
16
INTIN[63:48]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESE
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTIN[47:32]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESE
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note: The state of this register out of reset is determined by the peripheral circuits generating the requests; normally, the requests
would be inactive. This read-only register must be accessed with 32-bit reads only.
INTSRCL
BIT
Interrupt Source Register Low
31
30
29
28
27
26
25
24
23
0x1004004C
22
21
20
19
18
17
16
INTIN[31:16]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTIN[15:0]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note: The state of this register out of reset is determined by the peripheral circuits generating the requests; normally, the requests
would be inactive. This read-only register must be accessed with 32 bit reads only.
Table 5-18. Interrupt Source Register High and Low Description
Name
INTIN
Bits 31–0
Description
Settings
Interrupt Source—Indicates the state of the corresponding hardware interrupt 0 = Interrupt source negated
source.
1 = Interrupt source asserted
i.MX21 Reference Manual, Rev. 3
5-22
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
5.1.10.1
Interrupt Assignments High
Table 5-19 and Table 5-20 show the interrupt assignments of INTSRCH and INTSRCL.
Table 5-19. Interrupt Source High (INTSRCH) Assignment
Name
Interrupt Source Module
Notes
Reserved
Bit 31
Reserved
–
Reserved
Bit 30
Reserved
–
INT_LCDC
Bit 29
LCD Controller (LCDC)
–
INT_SLCDC
Bit 28
Smart LCD Controller (SLCDC)
–
Reserved
Bit 27
Reserved
–
INT_USBCTRL
Bit 26
–
USB OTG Control Interrupt
INT_USBMNP
Bit 25
USBOTG
USBOTG HNP Interrupt
INT_USBFUNC
Bit 24
USBOTG
USBOTG Function Interrupt
INT_USBHOST
Bit 23
USBOTG
USBOTG Host Interrupt
INT_USBDMA
Bit 22
USBOTG
USBOTG DMA Interrupt
INT_USBWKUP
Bit 21
USBOTG
USBOTG Wakeup Interrupt
INT_EMMAPP
Bit 20
eMMA
eMMA Post Processor Interrupt
INT_EMMAPRP
Bit 19
eMMA
eMMA Pre Processor Interrupt
INT_EMMADEC
Bit 18
eMMA
eMMA Decoder Interrupt
INT_EMMAENC
Bit 17
eMMA
eMMA Encoder Interrupt
Reserved
Bit 16
Reserved
Reserved for OWIRE
INT_DMACH15
Bit 15
DMA Channel 15
DMA Channel Interrupts
INT_DMACH14
Bit 14
DMA Channel 14
–
INT_DMACH13
Bit 13
DMA Channel 13
–
INT_DMACH12
Bit 12
DMA Channel 12
–
INT_DMACH11
Bit 11
DMA Channel 11
–
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
5-23
ARM926EJ-S Interrupt Controller (AITC)
Table 5-19. Interrupt Source High (INTSRCH) Assignment (continued)
Name
5.1.10.2
Interrupt Source Module
Notes
INT_DMACH10
Bit 10
DMA Channel 10
–
INT_DMACH9
Bit 9
DMA Channel 9
–
INT_DMACH8
Bit 8
DMA Channel 8
–
INT_DMACH7
Bit 7
DMA Channel 7
–
INT_DMACH6
Bit 6
DMA Channel 6
–
INT_DMACH5
Bit 5
DMA Channel 5
–
INT_DMACH4
Bit 4
DMA Channel 4
–
INT_DMACH3
Bit 3
DMA Channel 3
–
INT_DMACH2
Bit 2
DMA Channel 2
–
INT_DMACH1
Bit 1
DMA Channel 1
–
INT_DMACH0
Bit 0
DMA Channel 0
–
Interrupt Assignments Low
Table 5-20. Interrupt Source Low (INTSRCL) Assignment
Name
Interrupt Source Module
Notes
INT_CSI
Bit 31
CMOS Sensor Interface (CSI)
–
INT_BMI
Bit 30
Bus Master Interface (BMI)
–
INT_NFC
Bit 29
Nand Flash Controller (NFC)
–
INT_PCMCIA
Bit 28
PCMCIA/CF Host Controller (PCMCIA)
–
INT_WDOG
Bit 27
Watchdog (WDOG)
–
INT_GPT1
Bit 26
General Purpose Timer (GPT1)
–
INT_GPT2
Bit 25
General Purpose Timer (GPT2)
–
INT_GPT3
Bit 24
General Purpose Timer (GPT3)
–
INT_PWM
Bit 23
Pulse Width Modulator (PWM)
–
i.MX21 Reference Manual, Rev. 3
5-24
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
Table 5-20. Interrupt Source Low (INTSRCL) Assignment (continued)
Name
Interrupt Source Module
Notes
INT_RTC
Bit 22
Real-Time Clock (RTC)
–
INT_KPP
Bit 21
Key Pad Port (KPP)
–
INT_UART1
Bit 20
UART1
–
INT_UART2
Bit 19
UART2
–
INT_UART3
Bit 18
UART3
–
INT_UART4
Bit 17
UART4
–
INT_CSPI1
Bit 16
Configurable SPI (CSPI1)
–
INT_CSPI2
Bit 15
Configurable SPI (CSPI2)
–
INT_SSI1
Bit 14
Synchronous Serial Interface 1(SSI1)
–
INT_SS2
Bit 13
Synchronous Serial Interface (SSI2)
–
INT_I2C
Bit 12
I2C Bus Controller (I2C)
–
INT_SDHC1
Bit 11
Secure Digital Host Controller (SDHC1)
–
INT_SDHC2
Bit 10
Secure Digital Host Controller (SDHC2)
–
INT_FIRI
Bit 9
Fast Infra Red Interface (FIRI)
–
INT_GPIO
Bit 8
General Purpose Input/Output (GPIO)
–
Reserved
Bit 7
Reserved
–
INT_CSPI3
Bit 6
Configurable SPI (CSPI3)
–
Reserved
Bits 5–0
Unused
–
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
5-25
ARM926EJ-S Interrupt Controller (AITC)
5.1.11
Interrupt Force Register High (INTFRCH) and Low (INTFRCL)
The interrupt force register high (INTFRCH) and the interrupt force register low (INTFRCL) are each 32
bits wide. The interrupt force registers allow for software generation of interrupts for each of the possible
interrupt sources for functional or debug purposes. The system level design may reserve one or more
sources for software purposes to allow software to self-schedule interrupts by forcing one or more of these
“sources” in the appropriate interrupt force register(s).
These registers are located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed
to in privileged mode. These registers can be only modified using 32-bit writes.
INTFRCH
BIT
Interrupt Force Register High
31
30
29
28
27
26
25
24
23
0x10040050
22
21
20
19
18
17
16
FORCE[63:48]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FORCE[47:32]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INTFRCL
BIT
Interrupt Force Register Low
31
30
29
28
27
26
25
24
23
0x10040054
22
21
20
19
18
17
16
FORCE[31:16]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FORCE[15:0]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-21. Interrupt Force Register High and Low Description
Name
FORCE
Bits 31–0
Description
Interrupt Source Force Request—Used to force a request for the
corresponding interrupt source.
Settings
0 = Standard interrupt operation
1 = Interrupt forced asserted
i.MX21 Reference Manual, Rev. 3
5-26
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
5.1.12
Normal Interrupt Pending Register High (NIPNDH) and Low
(NIPNDL)
The normal interrupt pending register high (NIPNDH) and the normal interrupt pending register low
(NIPNDL) are 32-bit wide registers used to monitor the outputs of the enable and masking operations.
These registers are actually only a set of buffers; therefore, the reset state of these registers are determined
by the normal interrupt enable registers, the interrupt mask register, and the interrupt source registers. The
value reflected in these registers is unaffected by the value of the NIMASK register.
These read-only registers are located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only
be accessed to in privileged mode.
NIPNDH
BIT
Normal Interrupt Pending Register High
31
30
29
28
27
26
25
24
23
0x10040058
22
21
20
19
18
17
16
NIPEND[63:48]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPEND[47:32]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NIPNDL
BIT
Normal Interrupt Pending Register Low
31
30
29
28
27
26
25
24
23
0x1004005C
22
21
20
19
18
17
16
NIPEND[31:16]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NIPEND[15:0]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-22. Normal Interrupt Pending Register High and Low Description
Name
Description
Settings
NIPEND Normal Interrupt Pending Bit—If a normal interrupt enable bit is set and the 0 = No normal interrupt request
Bits 31–0 corresponding interrupt source is asserted, the interrupt controller will assert 1 = Normal interrupt request pending
a normal interrupt request. The normal interrupt pending bits reflect the
interrupt input lines which are asserted and are currently enabled to generate
a normal interrupt.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
5-27
ARM926EJ-S Interrupt Controller (AITC)
5.1.13
Fast Interrupt Pending Register High (FIPNDH) and Low (FIPNDL)
The fast interrupt pending register high (FIPNDH) and the fast interrupt pending register low (FIPNDL)
are 32-bit wide registers used to monitor the outputs of the enable and masking operations. These registers
are actually only a set of buffers; therefore, the reset state of these registers are determined by the fast
interrupt enable registers, the interrupt mask register, and the interrupt source registers.
These read-only registers are located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only
be accessed to in privileged mode.
FIPNDH
BIT
Fast Interrupt Pending Register High
31
30
29
28
27
26
25
24
23
0x10040060
22
21
20
19
18
17
16
FIPEND[63:48]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIPEND[47:32]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FIPNDL
BIT
Fast Interrupt Pending Register Low
31
30
29
28
27
26
25
24
23
0x10040064
22
21
20
19
18
17
16
FIPEND[31:16]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIPEND[15:0]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-23. Fast Interrupt Pending Register High and Low Description
Name
FIPEND
Bits 31–0
Description
Settings
Fast Interrupt Pending Bit—If a fast interrupt enable bit is set and the
0 = No fast interrupt request
corresponding interrupt source is asserted, the interrupt controller will assert 1 = Fast interrupt request pending
a fast interrupt request. The fast interrupt pending bits reflect the interrupt
input lines which are asserted and are currently enabled to generate a fast
interrupt.
i.MX21 Reference Manual, Rev. 3
5-28
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
5.2
5.2.1
ARM926EJ-S Interrupt Controller Operation
ARM926EJ-S Prioritization of Exception Sources
The ARM926EJ-S core imposes the following priority among the various exceptions:
• Reset (highest priority)
• Data Abort
• Fast Interrupt
• Normal Interrupt
• Prefetch Abort
• Undefined Instruction and SWI (lowest priority)
5.2.2
AITC Prioritization of Interrupt Sources
The AITC module prioritizes the various interrupt sources by source number where higher source numbers
have higher priority. Fast interrupt always have higher priority over normal interrupts.
The interrupt requests are prioritized in the following sequence:
1. Fast interrupt requests, in order of highest source number
2. Normal interrupt requests, in order of highest priority level, then in order of highest source number
with the same priority level
5.2.3
Assigning and Enabling Interrupt Sources
The interrupt controller provides for flexible assignment of any interrupt source to either of the two core
interrupt request inputs. This is done by setting the appropriate bits in the INTENABLEH / INTENABLEL
registers and the INTTYPEH / INTTYPEL registers. Usually, interrupt assignment is done once during
system initialization and does not affect interrupt latency.
Interrupt assignment is the first of three steps required to enable an interrupt source, and this is done at chip
integration. The second step is to program the source to generate interrupt requests. The final step is to
enable the interrupt inputs in the core by clearing the normal interrupt disable (I) and/or the fast interrupt
disable (F) bits in the program status register (CPSR).
5.2.4
Enabling Interrupt Sources
There are two methods of enabling or disabling interrupts in the AITC. The first method is directly reading
the INTENABLEH / INTENABLEL registers, logically OR or BIT CLEAR these registers with a
generated masks, then writing back to the INTENABLEH / INTENABLEL registers.
The second method is performing an atomic write to the source number to INTENNUM register. The
AITC will decode this 6 bit register and enable one of the 64 interrupt sources. The AITC will
automatically generate a “one hot” enable mask and logically OR this mask to the correct INTENABLEH
or INTENABLEL register. To disable interrupts is exactly the same except the source number is written
to the INTDISNUM register.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
5-29
ARM926EJ-S Interrupt Controller (AITC)
5.2.5
Controlling Bus Arbitration With AITC
The AITC has some logic to rise the priority level of the ARM core when either a fast or normal interrupt
occurs. When a fast interrupt occurs and the FIAD bit is set, the AITC will assert the aitc_rise_arb signal.
When a normal interrupt occurs and the NIAD bit is set, the AITC will assert the aitc_rise_arb signal. This
signal will rise the priority level of the ARM core, so that it has priority of all other alternate masters. This
signal will not stop the current alternate master transfer instead will prevent/limit future bus arbitration
away from the ARM core.
The AITC includes some logic in the ABFLAG and ABFEN bits. The ABFLAG bit indicates the AITC is
currently asserted the aitc_rise_arb signal to the bus arbitration logic. The ABFEN bit changes the
ABFLAG from a read-only status bit to a “sticky” write-1-to-clear status bit.
5.2.6
Typical Interrupt Entry Sequences
The following is a typical pipeline sequence for the ARM926EJ-S core when a normal interrupt occurs.
Assuming single cycle memories, it takes approximately 6 clocks from the acknowledgment of the normal
interrupt within the ARM926EJ-S until the first opcode of the interrupt routine is fetched.
Table 5-24. Typical Hardware Accelerated Normal Interrupt Entry Sequence
TIME
ADDR
-2
-1
nIRQ assert
Last ADDR
before nIRQ
+4 / +2
+8 / +4
0x0000_0018
+4
+8
Fetch
0
1
2
3
4
5
Link
Adjust
Fetch
Dec
Exec
Data
Wrbk
Fetch
Dec
6
7
8
Fetch
Dec
Exec
Fetch
Dec
nIRQ ack
Dec
Exec
Fetch
Dec
Fetch
Fetch
Vector Table
Vector
n/a
nIRQ Routine
+4
+8
Fetch
The following is a typical pipeline sequence for the ARM926EJ-S core when a fast interrupt occurs,
assuming that the FIQ service routine begins at 0x0000_001C and single cycle memories.
i.MX21 Reference Manual, Rev. 3
5-30
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
Table 5-25. Typical Fast Interrupt Entry Sequence
TIME
ADDR
-2
-1
nFIQ assert
Last ADDR before nFIQ
+4 / +2
+8 / +4
Fetch
0
1
2
Link
Adjust
Fetch
Dec
Exec
Fetch
Dec
nFIQ ack
Dec
Exec
Fetch
Dec
Fetch
0x0000_001c
+4
+8
5.2.7
3
Fetch
Writing Reentrant Normal Interrupt Routines
The AITC can be used to create a reentrant normal interrupt system. This enables preempting of lower
priority level interrupts by higher priority level interrupts. This requires a small amount of software
support and overhead.
1. Push the link register (LR_irq) on to the stack (SP_irq)
2. Push the saved status register (SPSR_irq) on to the stack
3. Read the current value of NIMASK and push this value on to the stack
4. Read current priority level via NIVECSR
5. Interrupts of the equal or lesser priority than the current priority level must be masked via the
NIMASK register by writing value from NIVECSR
6. Clear the I bit in the ARM926EJ-S core via a MSR / MRS command sequence (now a higher
priority normal interrupt can preempt a lower priority one)
Also change the operating mode of the core to System Mode from IRQ mode
7. Push System Mode link register (LR) on to the stack (SP_user)
8. The traditional interrupt service routine is now included
9. Pop System Mode link register (LR) from the stack (SP_user)
10. Set I bit in the ARM926EJ-S core via a MSR / MRS command sequence (thus disabling all normal
interrupts)
Also change the operating mode of the core to IRQ Mode from System mode
11. Pop the original value of normal interrupt mask and write to the NIMASK register
12. The saved status register must be popped from the stack (SP_irq)
13. The link register must be popped from the stack into the PC
14. Return from nIRQ
NOTE
Steps 1, 2, 13, and 14 are automatically done by most C compilers and are
included for completeness.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
5-31
ARM926EJ-S Interrupt Controller (AITC)
i.MX21 Reference Manual, Rev. 3
5-32
Freescale Semiconductor
Chapter 6
Phase-Locked Loop (PLL), Clock and Reset Controller
There are two clock controller modules in the i.MX21. The ARM9 platform clock controller and the PLL
Clock Controller module which produces the clock signals used and distributed by the ARM9 platform
clock controller. The PLL Clock Controller generates clock signals used throughout the i.MX21 chip and
also for external peripherals. The PLL Clock Controller also serves as the interface between the ARM9
platform and the peripherals on the i.MX21.
The primary function of the ARM9 platform clock controller is to take the clock signals from the PLL
Clock Controller distribute them to various peripherals on the ARM9 platform. The clock control module
contains the logic to turn clocks on or off and determine when the ARM9’s clock can be turned off. This
module also synchronizes the JTAG interface to the CLK domain. The ARM9 platform clock controller is
not a user programmable or accessible module where the PLL Clock Controller is, and is described in this
chapter.
6.1
Clock Controller Architecture Block Diagram
There are two DPLLs in the PLL Clock Controller —the MCU/System PLL (MPLL) and the Serial
Peripheral PLL (SPLL) use digital and mixed analog/digital circuits to provide clock frequencies for
wireless communication and other applications. The MPLL primarily generates the CLK signal to the
ARM9 and HCLK (also called System clock) for the system bus and for most of the on-chip peripherals
including the clock for LCDC pixel clock, NAND Flash Controller clock and FIRI MIR clock. The SPLL
produces the primary clock to the clock dividers for USB OTG, SSI1,SSI2 and FIRI FIR clock.
Both DPLLs (MPLL and SPLL) accept either the output of the FPM or the OSC26M as a source from
which to generate the required frequencies for ARM9 platform and/or peripherals using a fractional
frequency multiplication method, detailed information about the calculation of the DPLL settings is shown
in Section 6.1.4 on page -5.
To produce the wide range of on-chip clock frequencies required by the i.MX21, the core clock generator
uses a two-stage phase locked loop. The first stage is a Frequency Pre-Multiplier PLL (FPM) which
multiplies the input frequency by a factor of 512. If the input crystal frequency is 32.768 kHz, the
premultiplier multiplies it by a factor of 512 to 16.78 MHz (16.384 MHz. for a 32 kHz crystal). The output
of the FPM is one of the clock sources for the MPLL and SPLL. Power management of i.MX21 is
accomplished by controlling the clock output of the MPLL and SPLL units.
The distribution of clocks in the i.MX21 is shown in the general block diagram of the entire module
(Figure 6-1). The signals are described in Table 6-1 on page 6-3. There are two external clock sources to
the PLL Clock Controller:
• 32 kHz external crystal
• 26 MHz external source/crystal
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
6-1
6-2
OSC26M_EN
CLK48M
SP_SEL
FPM_EN
CLK48DIV
PREMULT
(FPM)
MCU &
System
PLL
(MPLL)
Serial
Peripheral
PLL
(SPLL)
SPLL Reference Clock
CLK48DIV_CLKO
0
1
0
1
MPLL Reference Clock
div 1,2,...8
3-bit
PRESC
SYNC
Logic
PERDIV1
Clk
Gating
SSI1DIV
SSI2DIV
Clk
Gating
CLK0SEL[4:0]
Refer to the CCSR for a
listing of possible outputs
SSI2_SEL
0
1
1
Clk
Gating
USBDIV
Clk
Gating
SSI1_SEL
0
FIRI_DIV
Clk
Gating
Clk
Gating PERDIV4
Clk
Gating PERDIV3
Clk
Gating PERDIV2
NFCDIV
Clk
Gating
CLKO
SSI2CLK
SSI1CLK
CLK48M
FIRICLK
PERCLK4
PERCLK3
PERCLK2
PERCLK1
NFCCLK
HCLK
FCLK
ipg_clk_32k_always2
BCLKDIV
1
0
0
1
FIR_SEL
SPLL_CLK
(SPCLK)
CLK26M
CLK32
OSC26M
DIV1P5
MPLL_CLK
OSC26
OSC32
MPCLK_SEL
CLK32
MCUDPLL_LF
Clk
Gating
Clk
Gating
Clk
Gating
Clk
Gating
SPLLEN
MPLLEN
MCUCLKEN
Shutdown &
Wake-Up
Logic
“OR” of all
Module Enables
MODULE_EN
PERCLK
(ipg_clk)
IPDIV
CPU
Clk
Gating
a9p_clk_off
AIPI 1 and 2
BUS_I/f
HCLK
CLK
CLK_ALWAYS
Clock Gating & Power Management
To System Bus
To ARM9 platform
To ARM9 platform &
JTAG circuit during
debug mode
Phase-Locked Loop (PLL), Clock and Reset Controller
Settings in the Clock Source Control Register (CSCR) are used to independently configure the external
clock sources applied to the MPLL and SPLL.
Gated CLK to individual Peripherals
(ipg_clk_s1/s2, ipg_clk_xxx (module clocks) )
PREMCLK
Figure 6-1. i.MX21 Clock Distribution Block Diagram
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
Phase-Locked Loop (PLL), Clock and Reset Controller
Table 6-1. PLL Clock Controller Descriptions
Signal Names
Description
CLK_ALWAYS
Fast clock used by the logic inside the ARM9 platform and the JTAG circuit to detect the debug mode
and exit Wait-For-Interrupt (WFI) mode. It is required to be always on even when CLK is stopped during
debug mode.
CLK
Fast clock used only by ARM9 platform for internal operations such as executing instructions from the
cache. It can be gated during doze and stop mode when all the criteria to enter a low power are met.
HCLK
System clock—This signal appears as the BCLK input to the CPU and the HCLK to the system. This is
a continuous clock (when the system is not in sleep mode) It can be gated during doze and stop mode
when all the criteria to enter a low power are met
HCLKEN
Used to signify the rising edge of CLK that corresponds to the rising edge of HCLK. Used by the ARM9
platform only.
PERCLK
Peripheral Clock to all modules, also known as ipg_clk.
SPCLK
Serial peripheral (SPLL) clock
CLK48M
Divided to 48 MHz clock for the USB OTG Module
SSI1CLK
Divided clock output for the SSI1 module
SSI2CLK
Divided clock output for the SSI2 module
FIRICLK
Divided clock output for the FIRI module
NFCCLK
Divided clock output for the Nand Flash Controller module. In normal operation, the maximum frequency
of the NFCCLK will be equal or less than PERCLK (ipg_clk).
PERCLK1
Divided clock output for the peripheral set 1 (UART, Timer, PWM). In normal operation, the maximum
frequency of the PERCLK1 will be equal or less than PERCLK (ipg_clk).
PERCLK2
Divided clock output for the peripheral set 2 (SDHC, CSPI). In normal operation, the maximum
frequency of the PERCLK2 will be equal or less than PERCLK (ipg_clk).
PERCLK3
Divided clock output for LCDC. In normal operation, the maximum frequency of the PERCLK3 will be
equal or less than PERCLK (ipg_clk).
PERCLK4
Divided clock output for the CSI.
CLKO
Selected internal clock output to the CLKO pin.
A9P_CLK_OFF
Control signal from ARM9 platform clock controller
CLK48DIV_CLKO
Clock output from the 3-bit CLK48DIV, used to divide the CLK48M and output on the CLKO pin.
ipg_clk_s1, ipg_clk_s2 Internal clock signals used for AIPI1 module accesses (ipg_clk_s1) or AIPI2 module accesses
(ipg_clk_s2). These clocks can be programmed to run continuously or toggle whenever there is an AIPI1
or AIPI2 module access, as determined by the CLOCK_GATING_EN bit in the GPCR in the System
Control Chapter.
6.1.1
OSC32K – 32/32.768 kHz Reference Oscillator (Analog)
The i.MX21 can use either a 32 kHz or a 32.768 kHz crystal as the external low frequency source.
Throughout this chapter, the low frequency crystal is referred to as the 32 kHz crystal regardless of which
frequency of crystal is used. The signal from the external 32 kHz crystal is the source of the CLK32 signal
that is sent to the real time clock (RTC). The output of the 32 kHz crystal is also input to the FPM
(Frequency PreMultiplier) to produce the 16.384 MHz signal that is input to the DPLLs (it is 16.78 MHz
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
6-3
Phase-Locked Loop (PLL), Clock and Reset Controller
if a 32.768 kHz crystal is used). The output of the MPLL is sent to the prescaler (PRESC) module to
produce the clock (CLK) signal for the ARM core as well as the HCLK for the system bus and module
operation.
See Section 6.1.5 on page -5 for more detailed information on phase and frequency jitter specifications
using this configuration.
6.1.2
OSC26M – 26 MHz Reference Oscillator (Analog)
The OSC26M oscillator provides a stable frequency reference for the MPLL and SPLL. This oscillator is
designed to work in conjunction with a external 26 MHz crystal with the integrated biasing resistor and
loading capacitors (19 pF) to generate the 26 MHz reference clock (CLK26M).
6.1.2.1
OSC26M Start-Up Considerations
Startup of the 26 MHz oscillator introduces a system level issue that must be addressed by the system
programmer. On power up or after a system reset the 6-bit AGC control field in the Oscillator 26M Control
Register (OSC26MCTL) is automatically reset to logic ‘1’ (0x2F) to prevent a condition in which the
oscillator may not start. Setting the AGC field to its maximum value applies the maximum supply to the
OSC amp, resulting in the highest possible gain. After the oscillator has started up and a valid clock signal
is generated, the oscillator peak level must be trimmed using the microprocessor to incrementally trim
down the supply level for the oscillator by decrementing the AGC field. Outputs from two comparators
generate a 2-bit value in the OSC26M_PEAK field of the OSC26MCTL register to indicate if the current
oscillation peak level is too high, too low, or in range.
For a detailed description of the OSC26M startup programming algorithm please refer to Section 6.3.6 on
page -19.
6.1.3
High Frequency Clock Source and Distribution
Two DPLLs on the i.MX21 (MPLL and SPLL) are used to generate two separate clock frequencies from
either the Frequency Pre-multiplier (FPM) or an external high frequency source (CLK26M). The clock
source for each DPLL is individually selected using bits in the Clock Source Control Register (CSCR).
The MCU/System PLL (MPLL) is configured by the MPCTL registers (MPCTL0, MPCTL1) to produce
system clock signals that are divided down to output the FCLK (for example 266 MHz) and the HCLK
(for example 133 MHz) clock signals. MPLL serves as the clock source for the PERCLK4, PERDIV3,
PERDIV2 and PERDIV1. FCLK serves as the clock source for the NFCDIV divider. These dividers
produce the clock signals for the following:
• NAND Flash Controller (NFC)
• Peripheral set 1 (PERCLK1): UART, Timer, and PWM
• Peripheral set 2 (PERCLK2): SDHC and CSPI
• LCDC Pixel Clock (PERCLK3)
• CSI (PERCLK4)
i.MX21 Reference Manual, Rev. 3
6-4
Freescale Semiconductor
Phase-Locked Loop (PLL), Clock and Reset Controller
The Serial Peripheral PLL (SPLL) is configured by the SPCTL registers (SPCTL0, SPCTL1) and produces
the input signals for USBDIV, SSI1DIV, SSI2DIV and FIRIDIV dividers that generate the clock signals
for serial peripherals that require special clock frequencies:
• CLK48M—for the USB OTG
• SSI1CLK—Clock signal for SSI1
• SSI2CLK—Clock signal for SSI2
• FIRICLK—Clock signal for FIRI
The FIRIDIV divider divides down the input clock frequency as determined by the setting of the
FIRI_DIV setting in the Peripheral Clock Divider Register (PCDR) to provide required frequencies for
FIR/MIR modes of operation.
The clock source for the SSI1DIV, SSI2DIv and the FIRIDIV dividers can be the MPLL or SPLL. Source
selection is controlled by the respective bits in the Clock Source Control register (CSCR).
6.1.3.1
FPM – Frequency Premultiplier
The Frequency Premultiplier is a digital phase locked loop which accepts the low frequency clock source
of 32 kHz or 32.768 kHz and multiplies the frequency by a factor of 512 for input to the MPLL and SPLL.
6.1.4
Output Frequency Calculations
Both DPLLs produce a high frequency clock that exhibits both a low frequency jitter and a low phase jitter.
The DPLL output clock frequency (fdpll) is determined by the Equation 6-1:
fdpll = 2fref • MFI + MFN / (MFD+1)
PD+1
Eqn. 6-1
where:
• fref is the reference frequency (512 × 32 kHz, 512 × 32.768 kHz, or 26 MHz)
• MFI is an integer part of a multiplication factor (MF)
• MFN is the numerator and MFD is the denominator of the MF
• PD is the predivider factor
6.1.5
DPLL Phase and Frequency Jitter
Spectral purity of the DPLL output clock is characterized by both phase and frequency jitter. Phase jitter
is a measure of clock phase fluctuations relative to an ideal clock phase. The output clock also can be
skewed relative to the reference clock. Frequency jitter is a measure of clock period fluctuations relative
to an ideal clock period. Frequency jitter is calculated as a difference of phase jitter values for adjacent
clocks.
DPLL jitter requirements vary according to system configuration. For many stand-alone processors and
asynchronous multiprocessor applications, only the frequency jitter value is important (slow phase jitter
and clock skew do not affect system performance). In these systems, it is not necessary to adjust the output
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
6-5
Phase-Locked Loop (PLL), Clock and Reset Controller
clock phase with an input clock phase. The clock generation mode in which slow phase fluctuations are
permissible is called Frequency Only Lock (FOL) mode.
Phase error is sometimes important for synchronous applications and sampling analog-to-digital (A/D) and
digital-to-analog (D/A) precision converters. The DPLL mode providing minimum phase jitter and skew
elimination is Frequency and Phase Lock (FPL) mode. The modes to the MPLL and SPLL in i.MX21 are
programmable by setting the corresponding bits in the MPCTL0 and SPCTL0 registers.
6.2
Power Management
The PLL clock controller module is designed with clock control at various stages of clock supply to
achieve optimum power savings. The operation of the PLL and clock controller at different stages of power
management is described in the following sections.
6.2.1
PLL Operation at Power-Up
The crystal oscillator begins oscillating within several hundred milliseconds of initial power-up. While
system reset remains asserted the PLL begins the lockup sequence and locks 1 ms after the crystal
oscillator becomes stable. Both DPLLs are enabled on power-up. The system reset is held asserted by the
PLL Clock Controller for 300 ms + 14 cycles of the 32 kHz as shown in Figure 6-3 on page 6-32.
6.2.2
PLL Operation at Wake-Up
When the device is awakened from stop mode by a wake-up event, the DPLL locks within 350 μs. The
crystal oscillator is always on after initial power-up, so crystal startup time is not a factor. The PLL output
clock starts operating as soon as it achieves lock.
6.2.3
i.MX21 Low-Power Modes
i.MX21 provides two power saving modes—Doze mode and Sleep mode:
• In Doze mode, the ARM9 executes a wait for interrupt (WFI) instruction. System clocks are still
active.
• In Sleep mode, the ARM9 executes a wait for interrupt (WFI) instruction. The output of the MPLL
and SPLL are shut down and only the 32 kHz clock is running.
These modes are controlled by the clock control logic and a sequence of CPU instructions. Most of the
peripheral modules can enable or disable the incoming clock signal through clock gating circuitry from the
peripheral bus. Each module has a module enable bit which, when disabled, disables the operational clock
to the module.
6.2.3.1
Doze Mode
Doze mode is defined as when the ARM9 executes a wait for interrupt instruction. after which the buffered
clock supply to the MCU is turned off.
i.MX21 Reference Manual, Rev. 3
6-6
Freescale Semiconductor
Phase-Locked Loop (PLL), Clock and Reset Controller
The sequence of operation to set the system to Doze mode:
1. Enable desired interrupts for wake-up from Doze mode
2. Disable watchdog timer interrupt
3. Execute wait-for-interrupt instruction
The ARM9 executes a wait for interrupt instruction if all required conditions are met (no irq, fiq or debug
requests pending), the ARM9 PLATFORM generates an A9P_CLK_OFF signal to the PLL Clock
Controller Module. The CLK signal to the MCU is immediately turned off when the A9P_CLK_OFF
signal goes active. CLK_ALWAYS and system bus (HCLK) remains running. HCLK is required by the
Cross Bar Switch within the ARM9 platform for continuous operation of peripheral modules. When an
unmasked interrupt event occurs, the CLK signal to the ARM9 is re-enabled.
6.2.3.2
Sleep Mode
Sleep Mode is defined as when all the DPLLs clock outputs are disabled. A sequence of operations and
criteria must be satisfied before the system turns off the MPLL and SPLL. The Sleep Mode sequence is
initiated when the MPEN bit in the CSCR register is cleared disabling the MPLL. This action also
automatically turns off the SPLL.
The sequence of operation to perform to put the system into SLEEP mode:
1. Disable AHB peripherals from bus accesses
2. Enable desired interrupts to be used for system wake-up
3. Disable watchdog timer interrupt
4. Set the required value to the SD_CNT (CSCR register) for shutdown countdown
5. Disable the MPLL by clearing the MPEN bit (CSCR register)
6. Execute wait-for-interrupt instruction
The example of programming setup to enter Sleep mode is as follows:
Example 6-1. Programming Setup for Sleep Mode
MRS
AND
MSR
LDR
LDRH
ORR
STRH
LDR
LDR
ORR
STR
BIC
STR
LDR
MCR
r0, CPSR
r1, r0, #(ENABLE_IRQ+ENABLE_FIQ+MODE_BITS)
CPSR_c, r1
r3, =WDG_BASEADDR
r4, [r3, #0x0]
r4, r4, #0x00000001
r4, [r3, #0x0]
r1, =CRM_BASEADDR
r2, [r1, #0x0]
r2, r2, #0x0100_0000
r2, [r1, #0x0]
r2, r2, #0x00000001
r2, [r1, #0x0]
r1, 0x00000000
p15, 0, r1, c7, c0, 4
; Enable interrupts
; Disable WDG Timer
; Set SDCNT to ‘01’
; Disable MPEN
; WFI
The MPLL and SPLL are turned off when the countdown value in SD_CNT is satisfied. For the MPLL,
there are a number of conditions that must be satisfied before the Clock Controller module turns off the
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
6-7
Phase-Locked Loop (PLL), Clock and Reset Controller
DPLL. The conditions to be satisfied before the PLL Clock Controller actually turns off the MPLL are as
follows:
1. Clock Controller Module has successfully mastered the system bus
2. The A9P_CLK_OFF signal from the ARM9 PLATFORM is active
3. SDRAM controller has successfully placed the external SDRAM into self-refresh mode
4. After the above conditions are satisfied the countdown based on the value in the SD_CNT field
will be initiated
5. SD_CNT countdown completes
When the conditions listed above are satisfied the MPLL and the SPLL will be turned off. The Frequency
Premultiplier (FPM) is also disabled in the Sleep mode. The FPM_EN bit (CSCR register) must not be
cleared if the FPM is providing the clock source to the DPLL.
When an unmasked interrupt event occurs, the FPM and then the MPLL are re-enabled and the MPLL
enable bit (MPEN) automatically restored to its enable setting. The SPLL is restored to its original state
based on the setting of the SPEN bit before Sleep mode. If the SPPLL was not enabled before entering
sleep mode the SPPLL will not be enabled.
The total start-up time from Sleep mode is the sum of the FPM lock time and the DPLL lock time.
In Sleep Mode, the i.MX21 retains all RAM data and register configuration values. Data to output
terminals is also maintained and thus will continue to sink/source static current.
NOTE
System software must ensure that if there are any clocks being sourced by the
i.MX21 processor to external peripherals (for example, CSI_MCLK), then the
corresponding PLL must not be turned off. In such cases, the i.MX21 processor
must remain in doze mode.
6.2.4
SDRAM Power Modes
When the SDRAM controller (SDRAMC) is enabled, the external SDRAM operates in distributed-refresh
mode or in self-refresh mode (as shown in Table 6-2). The SDRAM wake-up latency is approximately 20
system clock cycles (HCLK). The SDRAMC can wake up from self-refresh mode when it is in a SDRAM
cycle.
In Doze and Run mode, the Power Down timers within the SDRAMC can be enabled to cause the SDRAM
to enter Power Down Mode on detecting no activity. The SDRAMC still controls the refresh and it will
take the SDRAM out of the Power Down mode to perform refresh when needed and then put it back into
the Power Down Mode. In Power Down mode the clock to the SDRAM is gated off and the CKE pin goes
low. In addition since the SDRAM will be in self refresh just when the system get into sleep mode, no bus
cycle can access the SDRAM to cause it to exit the self refresh mode. Exit from self refresh mode will
happen when the chip will exit the sleep mode and re-enable the MPEN.
I
Table 6-2. SDRAM/SyncFlash Operation During Power Modes
SDRAM
SDRAM
1
Run
Doze
Distributed-refresh, Note 1
Distributed-refresh,
Stop
1
Self-refresh
The Power Down Timers can be enabled and once the timer expires, it will enter low power mode.
i.MX21 Reference Manual, Rev. 3
6-8
Freescale Semiconductor
Phase-Locked Loop (PLL), Clock and Reset Controller
6.2.5
Power Management in the PLL Clock Controller
The i.MX21 has a very efficient clock control scheme that enables clocking control of the modules and
devices at various stages. Power management in i.MX21 is achieved by controlling the duty cycles of the
clock system efficiently. The clocking control scheme is shown in Table 6-3.
Table 6-3. Power Management in the Clock Controller
Device/Signal
Shut-Down Conditions
MPLL
When 0 is written to the MPEN bit and the PLL shut-down count times out
(for details see the SD_CNT settings in Table 6-5).
When IRQ or FIQ is asserted
SPLL
When 0 is written to the SPEN bit.
When the SPEN bit is set to 1.
FPM
When 0 is written to the FPMEN bit.
When the FPMEN bit is set to 1.
Continuously running.
Continuously running
CLK32
Wake-Up Conditions
Most modules in the i.MX21 have a module enable bit assigned which must be enabled before the module
is active. Enabling the module enables the clock source for the module to be provided for its main
operations. The clock input to the dividers from the SPLL is also controlled separately in the same manner.
6.3
Programming Model
The PLL Clock Controller module includes six user-accessible 32-bit registers. Table 6-4 summarizes
these registers and their addresses.
Table 6-4. PLL Clock Controller Module Register Summary
Description
Name
Address
Clock Source Control Register
CSCR
0x10027000
MPLL Control Register 0
MPCTL0
0x10027004
MPLL Control Register 1
MPCTL1
0x10027008
SPLL Control Register 0
SPCTL0
0x1002700C
SPLL Control Register 1
SPCTL1
0x10027010
Oscillator 26M Register
OSC26MCTL
0x10027014
Peripheral Clock Divider Register 0
PCDR0
0x10027018
Peripheral Clock Divider Register 1
PCDR1
0x1002701C
Peripheral Clock Control Register 0
PCCR0
0x10027020
Peripheral Clock Control Register 1
PCCR1
0x10027024
Clock Control Status Register
CCSR
0x10027028
PMOS Switch Control Register
PMCTL
0x1002702C
PMOS Switch Counter Register
PMCOUNT
0x10027030
Wakeup Guard Mode Control Register
WKGDCTL
0x10027034
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
6-9
Phase-Locked Loop (PLL), Clock and Reset Controller
6.3.1
Clock Source Control Register (CSCR)
The Clock Source Control Register controls the various clock sources to the internal modules of the
i.MX21.
CSCR
Clock Source Control Register
BIT
31
30 29 28 27 26
PRESC
TYPE
24
23
22
21
20
19
18
17
16
SPLL_
MPLL_
SP MCU_
SSi2_SEL SSI1_SEL FIR_SEL
RESTART RESTART
_SEL SEL
SD_CNT
rw
rw rw rw rw rw
rw
rw
r
rw
rw
rw
rw
rw
rw
rw
0
1
1
1
0
0
0
1
1
0
0
0
5
4
3
2
1
0
RESET
BIT
USB_DIV
25
Addr
0x10027000
1
1
0
1
0x7718
15
TYPE
RESET
14 13 12 11 10
9
BCLKDIV
IPDIV
8
7
6
OSC26M_ OSC26M_
FPM_EN SPEN MPEN
DIV1P5
DIS
r
r
rw rw rw rw
rw
r
r
r
r
rw
rw
rw
rw
rw
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
1
0x0607
Table 6-5. Clock Source Control Register Description
Name
Description
Settings
PRESC
Bit 31–29
Prescaler—Defines the MPU PLL clock 3-bit
prescaler.
0 = Prescaler divides by 1
1 = Prescaler divides by 2
2 = Prescaler divides by 3
3 = Prescaler divides by 4
4 = Prescaler divides by 5
5 = Prescaler divides by 6
6 = Prescaler divides by 7
7 = Prescaler divides by 8
USB_DIV
Bits 28–26
USB Clock Divider—Contains the 3-bit integer
divider value for the generation of the CLK48M.
000 = SPLL_CLK divided by 1
001 = SPLL_CLK divided by 2
...
111 = SPLL_CLK divided by 8
SD_CNT
Bits 25–24
Shut-Down Control—Contains the value that
determines the duration of the DPLL clock output
before it goes off after a 0 is written to the MPEN or
SPEN bit.
Note: The power controller requests the bus before
SPLL shutdown. Any unmasked interrupt
event enables the MPLL.
00 = DPLL shuts down after next rising edge of
CLK32 is detected and the current bus cycle is
completed. A minimum of 16 HCLK cycles is
occurs after writing 0 to MPEN bit.
01 = DPLL shuts down after the second rising edge
of CLK32 is detected and the current bus cycle
is completed.
10 = DPLL shuts down after the third rising edge of
CLK32 is detected and the current bus cycle is
completed.
11 = DPLL shuts down after forth rising edge of
CLK32 is detected and the current bus cycle is
completed.
Reserved
Bit 23
Reserved—This bit is reserved and should read 0.
i.MX21 Reference Manual, Rev. 3
6-10
Freescale Semiconductor
Phase-Locked Loop (PLL), Clock and Reset Controller
Table 6-5. Clock Source Control Register Description (continued)
Name
Description
Settings
SPLL_RESTART SPLL Restart—Restarts the SPLL at new assigned 0 = No Effect
Bit 22
frequency. SPLL_RESTART self-clears after 1 (min) 1 = Restarts SPLL at new frequency
or 2 (max) cycles of CLK32.
MPLL_RESTART MPLL Restart—Restarts the MPLL at a new
Bit 21
assigned frequency. MPLL_RESTART self-clears
after 1 (min) or 2 (max) cycles of CLK32.
0 = No Effect
1 = Restarts MPLL at new frequency
SSI2_SEL
Bit 20
SSI2 Baud Source Select—Selects the clock source 0 = Source clock to SSI2 fractional divider from SPLL
to the SSI2 fractional divider (SSI2_DIV).
1 = Source clock to SSI2 fractional divider from MPLL
SSI1_SEL
Bit 19
SSI1 Baud Source Select—Selects the clock source 0 = Source clock to SSI1 fractional divider from SPLL
to the SSI1 fractional divider (SSI1_DIV).
1 = Source clock to SSI1 fractional divider from MPLL
FIR_SEL
Bit 18
FIR and MIR Select—Selects the clock source to the 0 = Source clock to FIRI baud clock divider from
FIR module divider FIRI_DIV during FIR or MIR
MPLL
1 = Source clock to FIRI baud clock divider from
mode.
SPLL
SP_SEL
Bit 17
SPLL Select—Selects the clock source of the SPLL 0 = Clock source is the internal premultiplier
1 = Clock source is the external high frequency clock
input. When set, the external high frequency clock
input is selected.
MCU_SEL
Bit 16
MPLL Select—Selects the clock source of the MPLL 0 = Clock source is the internal premultiplier
1 = Clock source is the external high frequency clock
input. When set, the external high frequency clock
input is selected.
Reserved
Bits 15–14
Reserved—These bits are reserved and should read 0.
BCLKDIV
Bits 13–10
System Bus Clock Divider—Contains the 4-bit
0000 = BCLK divided by 1
integer divider value for the generation of the HCLK. 0001 = BCLK divided by 2
...
1111 = BCLK divided by 16
IPDIV
Bits 9
Peripheral Clock Divider—Contains the 1-bit
integer divider value for the generation of the
peripheral clock ipg_clk (PERCLK) for the system
peripherals.
User should not set this bit to 0 in normal operation
Reserved
Bits 8–5
Reserved—These bits are reserved and should read 0.
0 = only for test purpose
1 = HCLK divided by 2
OSC26M_DIV1P5 Oscillator 26M Divide—Divides osc26m output by 1 0 = osc26m output divide by 1 (default)
Bit 4
or 1.5.
1 = osc26m output divide by 1.5
OSC26M_DIS
Bit 3
Oscillator Disable—Disables the internal (chip
0 = Enable the internal 26 MHz oscillator circuit
inside) 26 MHz oscillator circuit when this bit is set to 1 = Disable the internal 26 MHz oscillator circuit
1.
FPM_EN
Bit 2
Frequency Premultiplier Enable—Enables the
0 = Disable the frequency premultiplier circuit
FPM when set. When clear, the FPM is disabled. The 1 = Enable the frequency premultiplier circuit
bit is set automatically on system reset. When the
software writes a 0 to this bit, the FPM is shut down
immediately. This bit must remain at 1 prior and
during sleep mode if the FPM is providing the source
to the DPLL.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
6-11
Phase-Locked Loop (PLL), Clock and Reset Controller
Table 6-5. Clock Source Control Register Description (continued)
Name
Description
Settings
SPEN
Bit 1
Serial Peripheral PLL Enable— Enables/disables
the SPLL. When software writes 0 to SPEN, the
SPLL shuts down after timeout determined by
SD_CNT. SPEN sets automatically when SPLLEN
asserts, and on system reset.
0 = Serial Peripheral PLL disabled
1 = Serial Peripheral PLL enabled
MPEN
Bit 0
MPLL Enable—Enables/disables the MPLL. When
software writes 0 to MPEN, the MPLL shuts down
after SDCNT timeout. MPEN sets automatically
when MPLLEN asserts, and on system reset.
0 = MCU and Serial PLL disabled
1 = MCU and Serial PLL enabled
NOTE
When the PRESC and BCLKDIV are to be modified at the same time, it
must be performed in 2 programming steps; first step is to program the
BCLKDIV followed by PRESC.
6.3.2
MPLL Control Register 0 (MPCTL0)
The MCU & System PLL Control Register 0 (MPCTL0) is a 32-bit register that controls the operation of
the MPLL. The MPCTL0 control bits are described in the following sections. The following is the
recommended procedure for changing the MPLL settings:
1. Program the desired values of PD, MFD, MFI, and MFN into the MPCTL0.
2. Set the MPLL_RESTART bit in the CSCR (it will self-clear).
3. New MPLL settings will take effect.
4. The new PLL clock output is valid upon the assertion of the DPLL lock flag.
MPCTL0
BIT
MCU & System PLL Control Register 0
31
30
29
28
CPLM
TYPE
27
26
25
24
23
22
Addr
0x10027004
21
PD
20
19
18
17
16
MFD
rw
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
7
6
5
4
3
2
1
0
RESET
0x0007
BIT
15
14
13
12
11
10
9
8
MFI
TYPE
MFN
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
RESET
0x1C07
i.MX21 Reference Manual, Rev. 3
6-12
Freescale Semiconductor
Phase-Locked Loop (PLL), Clock and Reset Controller
Table 6-6. MPLL Register 0 Description
Name
Description
Settings
CPLM
Bit 31
Phase Lock Mode—The DPLL operates in the Frequency Only Lock mode (FOL) when the 0 = FOL
CPLM bit is cleared, and in Frequency and Phase Lock mode (FPL) when the bit is set. The 1 = FPL
FPL mode can be used for both an integer and fractional multiplication factor, but phase
skew elimination is accomplished only for integer MF.
Reserved
Bit 30
Reserved—This bit is reserved and should read 0.
PD
Bits 29–26
Predivider Factor—Defines the predivider factor (PD) applied to the MPLL input frequency.
PD is an integer between 0 and 15 (inclusive). PD is chosen to ensure that the resulting
output frequency remains within the specified range. When a new value is written into PD
bits, the MPLL loses its lock; after a time delay, the MPLL re-locks. The output of the MPLL
is determined by Equation 6-1.
0000 = 0
0001 = 1
…
1111 = 15
MFD
Bits 25–16
Multiplication Factor (Denominator Part)—Defines the denominator part of the BRM
value for the MF. When a new value is written into the MFD bits, the MPLL loses its lock;
after a time delay, the PLL re-locks.
0x000 = Reserved
0x001 = 1
…
0x3FF = 1023
Reserved
Bits 15–14
Reserved—These bits are reserved and should read 0.
MFI
Bits 13–10
Multiplication Factor (Integer)—Defines the integer part of the BRM value for the MF. The
MFI is encoded so that MFI < 5 results in MFI = 5. When a new value is written into the MFI
bits, the PLL loses its lock: after a time delay, the PLL re-locks. The VCO oscillates at a
frequency determined by Equation 6-1. Where PD is the division factor of the predivider,
MFI is the integer part of the total MF, MFN is the numerator of the fractional part of the MF,
and MFD is its denominator part. The MF is chosen to ensure that the resulting VCO output
frequency remains within the specified range.
0000 = 0
0101 = 5
0110 = 6
...
1111 = 15
MFN
Bits 9–0
Multiplication Factor (Numerator)—Defines the numerator of the BRM value for the MF.
When a new value is written into the MFN bits, the MPLL loses its lock; after a time delay,
the PLL re-locks.
0x000 = 0
0x001 = 1
...
0x3FE = 1022
0x3FF = Reserved
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
6-13
Phase-Locked Loop (PLL), Clock and Reset Controller
Recommended settings for the MPLL and SPLL, which produces the least amount of signal jitter, are
shown in Table 6-7.
Table 6-7. Recommended Settings for Frequency Stability
Ref Frequency
Target
Frequency
MFI
MFN
MFD
PD
MPCTL0/SPCTL0
Setting
Actual
Calculated
Frequency
32.768kHz
288MHz
8
365
626
0
0x0272216D
287.9687378
266MHz
7
115
123
0
0x007B1C73
266.0000537
258MHz
7
368
532
0
0x02141D70
258.0480615
240MHz
7
137
897
0
0x03811C89
240.00013
240MHz
14
191
625
0
0x067138BF
239.9999509
288MHz
8
101
127
0
0x007F2065
288
266MHz
8
2
16
0
0x00102002
265.9990588
258MHz
7
7
7
0
0x00071C07
258.048
240MHz
7
83
255
0
0x00FF1c53
240
288MHz
5
7
12
0
0x000C1407
288
266MHz
5
3
25
0
0x00191403
266
240MHz
4
16
25
0
0x00191010
240
288MHz
7
35
51
0
0x00331C23
266
32.000kHz
26MHz
26/1.5MHz
fdpll = 2fref • MFI + MFN / (MFD+1)
PD+1
6.3.2.1
MPLL Control Register 1
The MCU & System PLL Control Register 1 (MPCTL1) is a 32-bit register that directs the operation of
the on-chip MCU PLL. The MPCTL1 control bits are described in Table 6-8.
MPCTL1
MCU & System PLL Control Register 1
Addr
0x10027008
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
BIT
0x0000
15
14
13
12
11
10
9
8
7
LF
TYPE
RESET
BRMO
r
r
r
r
r
r
r
r
1
0
0
0
0
0
0
0
r
rw
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0x8000
i.MX21 Reference Manual, Rev. 3
6-14
Freescale Semiconductor
Phase-Locked Loop (PLL), Clock and Reset Controller
Table 6-8. MCU & System PLL Control Register 1 Description
Name
Description
Settings
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
LF
Bit 15
Lock Flag—Indicates whether the MPLL is locked. When set, the MPLL clock output is 0 = MPLL is not locked
valid. When cleared, the MPLL clock output remains at logic high.
1 = MPLL is locked
Reserved
Bits 14–7
Reserved—These bits are reserved and should read 0.
BRMO
Bit 6
BRM Order—Controls the BRM order which affect the jitter performance of the MPLL. 0 = BRM contains
The first order BRM is used if a MF fractional part is both more than 1/10 and less than
first order
9/10. In other cases, the second order BRM is used. The BRMO bit is cleared by a
1 = BRM contains second
hardware reset. A delay of reference cycles is required between two write accesses to
order
BRMO.
Reserved
Bits 5–0
Reserved—These bits are reserved and should read 0.
6.3.3
Programming the Serial Peripheral PLL (SPLL)
One of the clock frequencies that the SPLL generates is for the USB OTG module (CLK48M). Its
frequency is set to 48 MHz using the SPLL control registers assuming a default input clock frequency
16.384 MHz. This input clock frequency assumes a 32 kHz crystal input. The predivider/multiplier output
depends on the input clock frequency. Recommended settings are provided for the Serial Peripheral PLL
as shown in Table 6-9.
Table 6-9. Serial PLL Multiplier Factor
PLL
Input
Frequency
Premultiplier
PD
MFD
MFI
MFN
PLL
Output
Frequency
USBDIV[2:0]
32 kHz
16.384 MHz
0
255
7
83
240 MHz
100
48 MHz
32 kHz
16.384 MHz
0
127
8
101
288 MHz
101
48 MHz
32.768 kHz
16.778 MHz
0
897
7
137
240.00013 MHz
100
48.000026 MHz
32.768 kHz
16.778 MHz
0
944
8
551
288 MHz
101
48 MHz
–
0
12
5
7
288 MHz
101
48 MHz
26 MHz
USB OTG
Clock
Frequency
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
6-15
Phase-Locked Loop (PLL), Clock and Reset Controller
6.3.4
SPLL Control Register 0 (SPCTL0)
The Serial Peripheral PLL Control Register 0 (SPCTL0) is a 32-bit register that controls the operation of
the SPLL. The SPCTL0 control bits are described in the following sections. The following is a procedure
for changing the Serial Peripheral PLL settings:
1. Program the desired values of PD, MFD, MFI, and MFN into the SPCTL0.
2. Set the SPLL_RESTART bit in the CSCR (it will self-clear).
3. New PLL settings will take effect.
4. The new PLL clock output is valid upon the assertion of the DPLL lock flag.
SPCTL0
BIT
Serial Peripheral PLL Control Register 0
31
30
29
28
27
26
25
24
23
22
21
rw
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
0
0
0
0
0
0
0
0
1
1
7
6
5
CPLM
TYPE
RESET
BIT
Addr
0x1002700C
PD
RESET
19
18
17
16
rw
rw
rw
rw
rw
1
1
1
1
1
4
3
2
1
0
MFD
0x807F
15
14
13
12
11
10
9
8
MFI
TYPE
20
MFN
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
1
0
0
0
0
0
0
1
1
0
0
1
0
1
0x2065
Table 6-10. SPLL Control Register 0 Description
Name
Description
Settings
CPLM
Bit 31
Phase Lock Mode—The DPLL operates in the Frequency Only Lock mode (FOL) when the 0 = FOL
CPLM bit is cleared, and in Frequency and Phase Lock mode (FPL) when the bit is set. The 1 = FPL
FPL mode can be used for both an integer and fractional multiplication factor, but phase skew
elimination is accomplished only for integer MF.
Reserved
Bit 30
Reserved—These bit is reserved and should read 0.
PD
Predivider Factor—Defines the predivider factor (PD) that is applied to the PLL input
Bits 29–26 frequency. PD is an integer between 0 and 15 (inclusive). The SPLL oscillates at a frequency
determined by Equation 6-1. The PD is chosen to ensure that the resulting VCO output
frequency remains within the specified range. When a new value is written into the PD bits, the
SPLL loses its lock: after a time delay, the SPLL re-locks.
0000 = 0
0001 = 1
…
1111 = 15
MFD
Multiplication Factor (Denominator Part)—Defines the denominator part of the BRM value 0x000 = Reserved
Bits 25–16 for the MF. When a new value is written into the MFD9–MFD0 bits, the PLL loses its lock: after 0x001 = 1
a time delay, the PLL re-locks.
…
0x3FF = 1023
Reserved Reserved—These bits are reserved and should read 0.
Bits 15–14
i.MX21 Reference Manual, Rev. 3
6-16
Freescale Semiconductor
Phase-Locked Loop (PLL), Clock and Reset Controller
Table 6-10. SPLL Control Register 0 Description (continued)
Name
Description
MFI
Multiplication Factor (Integer Part)—Defines the integer part of the BRM value for the MF.
Bits 13–10 The MFI is decoded so that MFI < 5 results in MFI = 5.
The SPLL oscillates at a frequency determined by Equation 6-1.
Where PD is the division factor of the predivider, MFI is the integer part of the total MF, MFN
is the numerator of the fractional part of the MF, and MFD is the denominator part of the MF.
The MF is chosen to ensure that the resulting VCO output frequency remains within the
specified range. When a new value is written into the MFI bits, the SPLL loses its lock; after a
time delay, the SPLL re-locks.
MFN
Bits 9–0
Settings
0000–0101 = 5
0110 = 6
...
1111 = 15
Multiplication Factor (Numerator Part)—Defines the numerator part of the BRM value for the 0x000 = 0
MF. When a new value is written into the MFN bits, the PLL loses its lock; after a time delay, 0x001 = 1
the PLL re-locks.
...
0x3FE = 1022
0x3FF = Reserved
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
6-17
Phase-Locked Loop (PLL), Clock and Reset Controller
6.3.5
SPLL Control Register 1
The Serial PLL control register 1 (SPCTL1) is a 32-bit read/write register that directs the operation of the
SPLL. The SPCTL1 control bits are described in this section.
SPCTL1
Serial Peripheral PLL Control Register 1
Addr
0x10027010
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
LF
TYPE
BRMO
r
r
r
r
r
r
r
r
r
rw
r
r
r
r
r
r
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x8000
Table 6-11. Serial Peripheral PLL Control Register 1 Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
LF
Bit 15
Lock Flag—Indicates whether the SPLL is locked. When set, the S PLL clock
output is valid. When cleared, the SPLL clock output remains at logic high.
Reserved
Bits 14–7
Reserved—These bits are reserved and should read 0.
BRMO
Bit 6
BRM Order Bit—Controls the BRM order which affects the jitter performance of
the DPLL. The first order BRM is used if a MF fractional part is both more than
1/10 and less than 9/10. In other cases, the second order BRM is used. The
BRMO bit is cleared by a hardware reset.
Reserved
Bits 5–0
Reserved—These bits are reserved and should read 0.
Settings
0 = SPLL is not locked
1 = SPLL is locked
0 = BRM has first order
1 = BRM has second order
i.MX21 Reference Manual, Rev. 3
6-18
Freescale Semiconductor
Phase-Locked Loop (PLL), Clock and Reset Controller
6.3.6
Oscillator 26M Register
This register is use to program the 26 MHz oscillator test modes as well as the gain control. Trimming of
the oscillator is necessary only on initial power up; the trim may be stored in Flash for future reference.
OSC26MCTL
BIT
31
Oscillator 26M Control Register
30
29
28
27
26
25
24
23
22
Addr
0x10027014
21
20
19
18
17
16
OSC26M_PEAK
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AGC
TYPE
r
r
rw
rw
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
RESET
0x3F00
Table 6-12. Oscillator 26M Control Register Description
Name
Reserved
Bits 31–18
Description
Settings
Reserved—These bits are reserved and should read 0.
OSC26M_PEAK OSC26M_PEAK—These bits are the status values from the oscillator 00 = Amplitude in desired operating
Bits 17–16
indicates the current amplitude.
range.
01 = Amplitude too low; trim higher.
10 = Amplitude too high; trim lower.
11 Invalid state.
AGC
Bits 13–8
Automatic Gain Control—These bits set the magnitude of the crystal oscillations based on the
OSC26M_PEAK status. The optimum setting of these bits is determined using the algorithm in Section 6.3.6.1
on page -19.
Reserved
Bits 7–0
Reserved—These bits are reserved and should read 0.
6.3.6.1
Adjusting the 26 MHz Oscillator Trim
To ensure a proper startup of the 26 MHz oscillator on power-up or system reset use the following steps
to determine the optimum trim of the oscillator AGC.
26 MHz Oscillator Trim Programming Algorithm
1. At power up or system reset, OSC26M_AGC[5:0] bits in the OSC26MCTL register are reset to
logic 1 (done in hardware, no software interaction required).
2. Read the peak amplitude value in bits OSC26M_PEAK[1:0] in the OSC26MCTL register.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
6-19
Phase-Locked Loop (PLL), Clock and Reset Controller
3. If the amplitude is not in the desired range, adjust by decrementing the OSC26M_AGC[5:0] by 1
count.
4. Wait at least 30.5 us (1 cycle of 32 kHz clock) for system to update OSC26M_PEAK bits.
5. Repeat steps 2 to 4 until trimmed in desired range.
6. Decrement 4 additional counts to provide a margin of error for temperature drift.
7. Store trim value in an external memory—that is, Flash, for future use.
It is suggested that the proceeding algorithm be run to determine the optimum AGC setting. Once this is
done on power-up or system reset the software must read the trim value from the external memory and
write it to the OSC26M_AGC[5:0].
6.3.7
Peripheral Clock Divider Register 0 (PCDR0)
The Peripheral Clock Divider Register 0 (PCDR0) contains the divider values for the peripheral clock
dividers in the PLL Clock Controller. Peripherals in i.MX21 requires special clock frequency which is
divided down from the MPLL and the SPLL clock output. Each of these peripheral modules receive their
clock input from the respective clock divider. These modules will still have the clock gating scheme as
with other modules for power saving advantages. Table 6-15 lists the clock sources associated with the
i.MX21 peripherals given in the PCDR0.
PCDR0
BIT
Peripheral Clock Divider Register 0
31
30
29
28
27
26
25
24
23
22
Addr
0x10027018
21
20
SSI2DIV
TYPE
19
18
17
16
SSI1DIV
rw
rw
rw
rw
rw
rw
r
r
r
r
rw
rw
rw
rw
rw
rw
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
6
5
4
3
2
1
0
RESET
0x6419
BIT
15
14
13
12
11
10
9
8
NFCDIV
TYPE
7
CLKO_48MDIV
FIRI_DIV
rw
rw
rw
rw
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
RESET
0x3007
Table 6-13. Peripheral Clock Divider Register 0 Description
Name
Description
SSI2DIV
Bits 31–26
SSI2 Baud Clock Divider—Contains the 6-bit fractional divider that
produces the clock for the SSI2CLK clock signal for the peripherals.
Reserved
Bits 25–22
These bits are reserved and should read 0.
Settings
000000, 000001 = Divide by 62
Others = clkin / (SSI2DIV[high:1] +
0.5 * SSI2DIV[0])
i.MX21 Reference Manual, Rev. 3
6-20
Freescale Semiconductor
Phase-Locked Loop (PLL), Clock and Reset Controller
Table 6-13. Peripheral Clock Divider Register 0 Description (continued)
Name
Description
Settings
SSI1DIV
Bits 21–16
SSI1 Baud Clock Divider—Contains the 6-bit fractional divider that
produces the clock for the SSI1CLK clock signal for the peripherals.
000000, 000001 = Divide by 62
Others = clkin / (SSI1DIV[high:1] +
0.5 * SSI1DIV[0])
NFCDIV
Bits 15–12
Nand Flash Controller Clock Divider—Contains the 4-bit divider that 0000 = Divide by 1
produces the clock for the NFCCLK clock signal for the Nand Flash
0001 = Divide by 2
Controller.
…
1111 = Divide by 16
Reserved
Bits 11–8
These bits are reserved and should read 0.
CLKO_48MDIV Clock Out 48M Clock Divider 1—Contains the 3-bit divider that
Bits 7–5
divides the CLK48M to output at CLKO pin, where the output of the
divider is labeled CLK48DIV_CLKO.
000 = Divide by 1
001 = Divide by 2
…
111 = Divide by 8
FIRI_DIV
Bits 4–0
00000 = Divide by 1
00001 = Divide by 2
…
11111 = Divide by 32
FIRI Divider—Contains the 5-bit integer divider that produces the
FIRICLK clock signal for the peripherals during MIR/FIR mode.
6.3.8
Peripheral Clock Divider Register 1 (PCDR1)
The Peripheral Clock Divider Register 1 (PCDR1) contains the divider values for the peripheral clock
dividers in the PLL Clock Controller. Peripherals in i.MX21 requires special clock frequency which is
divided down from the MPLL and the SPLL clock output. Each of these peripheral modules receive their
clock input from the respective clock divider. These modules will still have the clock gating scheme as
with other modules for power saving advantages. Table 6-15 lists the clock sources associated with the
i.MX21 peripherals given in the PCDR1.
PCDR1
BIT
Peripheral Clock Divider Register 1
31
30
29
28
27
26
25
24
23
22
Addr
0x1002701C
21
20
PERDIV4
TYPE
19
18
17
16
PERDIV3
r
r
rw
rw
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
6
5
4
3
2
1
0
RESET
0x0307
BIT
15
14
13
12
11
10
9
8
7
PERDIV2
TYPE
PERDIV1
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
RESET
0x070F
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
6-21
Phase-Locked Loop (PLL), Clock and Reset Controller
Table 6-14. Peripheral Clock Divider Register 1 Description
Name
Description
Settings
Reserved
Bits 31–30
These are reserved bits and should read 0.
PERDIV4
Bits 29-24
Peripheral Clock Divider 4—Contains the 6-bit integer divider that produces
the PERCLK4 clock signal for the CSI MCLK Clock.
Reserved
Bits 23–22
These are reserved bits and should read 0.
PERDIV3
Bits 21–16
Peripheral Clock Divider 3—Contains the 6-bit integer divider that produces
the PERCLK3 clock signal for the LCDC Pixel Clock.
Reserved
Bits 15–14
These are reserved bits and should read 0.
PERDIV2
Bits 13–8
Peripheral Clock Divider 2—Contains the 6-bit integer divider that produces
the PERCLK2 clock signal for the peripheral 2set (CSPI and SDHC).
Reserved
Bits 7–6
These are reserved bits and should read 0.
PERDIV1
Bits 5–0
Peripheral Clock Divider 1—Contains the 6-bit integer divider that produces
the PERCLK1 clock signal for the peripheral 1 set (UART, GPT, PWM).
000000 = Divide by 1
000001 = Divide by 2
…
111111 = Divide by 64
000000 = Divide by 1
000001 = Divide by 2
…
111111 = Divide by 64
000000 = Divide by 1
000001 = Divide by 2
…
111111 = Divide by 64
000000 = Divide by 1
000001 = Divide by 2
…
111111 = Divide by 64
Table 6-15. Clock Sources for i.MX21 Peripherals
Clock Source
6.3.9
Peripherals
PERCLK4
CSI
PERCLK3
LCDC
PERCLK2
SDHC, CSPI
PERCLK1
UART, GPT, PWM
Peripheral Clock Control Register 0 (PCCR0)
The Peripheral Clock Control Register 0 (PCCR0) provides additional power saving capabilities by
controlling the clocks in the i.MX21 modules. It also controls the clock source for Bootstrap mode. The
PCCR0 allows for gating of HCLK to modules or peripherals that access the AHB bus and perform AHB
bus transfers and also allows for gating of the ipg clk (PERCLK) to specific peripherals.
i.MX21 Reference Manual, Rev. 3
6-22
Freescale Semiconductor
Phase-Locked Loop (PLL), Clock and Reset Controller
29
28
HCLK_BROM_EN
HCLK_EMMA_EN
HCLK_LCDC_EN
HCLK_SLCDC_EN
HCLK_USBOTG_EN
HCLK_BMI_EN
PERCLK4_EN
SLCDC_EN
FIRI_BUAD_EN
NFC_EN
PERCLK3_EN
SSI1_BAUD_EN
SSI2_BAUD_EN
BIT
31
TYPE
0
30
27
26
25
24
23
Addr
0x10027020
HCLK_DMA_EN
Peripheral Clock Control Register 0
HCLK_CSI_EN
PCCR0
22
21
20
19
18
17
16
rw
rw
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
6
5
4
3
2
1
0
RESET
BIT
15
EMMA_EN
USBOTG_EN
DMA_EN
I2C_EN
GPIO_EN
SDHC2_EN
SDHC1_EN
FIRI_EN
SSI2_EN
SSI1_EN
CSPI2_EN
CSPI1_EN
UART4_EN
UART3_EN
UART2_EN
UART1_EN
0x3108
14
13
12
11
10
9
8
7
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
RESET
0x4003
Table 6-16. Peripheral Clock Control Register 0 Description
Name
Description
Settings
HCLK_CSI_EN
Bit 31
CMOS Sensor Interface Clock Enable—
0 = CSI HCLK clock input is disabled (default).
Enables/Disables HCLK clock input to the CSI module. 1 = CSI HCLK clock input is enabled.
HCLK_DMA_EN
Bit 30
DMA Clock Enable—Enables/Disables HCLK clock
input to the DMA module.
Reserved
Bit 29
Reserved
HCLK_BROM_EN
Bit 28
BROM Clock Enable—Enables/Disables HCLK clock 0 = BROM HCLK clock input is disabled.
input to the BROM module.
1 = BROM HCLK clock input is enabled
(default).
HCLK_EMMA_EN
Bit 27
EMMA Clock Enable—Enables/Disables HCLK clock 0 = EMMA HCLK clock input is disabled
input to the EMMA module.
(default).
1 = EMMA HCLK clock input is enabled.
HCLK_LCDC_EN
Bit 26
LCDC Clock Enable—Enables/Disables HCLK clock
input to the LCDC module.
0 = DMA HCLK clock input is disabled.
(default)
1 = DMA HCLK clock input is enabled.
0 = LCDC HCLK clock input is disabled
(default).
1 = LCDC HCLK clock input is enabled.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
6-23
Phase-Locked Loop (PLL), Clock and Reset Controller
Table 6-16. Peripheral Clock Control Register 0 Description (continued)
Name
Description
Settings
HCLK_SLCDC_EN
Bit 25
SLCDC Clock Enable—Enables/Disables HCLK clock 0 = SLCDC HCLK clock input is disabled
input to the SLCDC module.
(default).
1 = SLCDC HCLK clock input is enabled.
HCLK_USBOTG_EN
Bit 24
USB OTG Clock Enable—Enables/Disables HCLK
clock input to the USB OTG module.
0 = USB OTG HCLK clock input is disabled.
1 = USB OTG HCLK clock input is enabled
(default).
HCLK_BMI_EN
Bit 23
BMI Clock Enable—Enables/Disables HCLK clock
input to the BMI module.
0 = BMI HCLK clock input is disabled (default).
1 = BMI HCLK clock input is enabled.
PERCLK4_EN
Bit 22
PERCLK4 Clock Enable—Enables/Disables
peripheral clock input to CSI module.
0 = CSI peripheral clock input is disabled
(default).
1 = CSI peripheral clock input is enabled.
SLCDC_EN
Bit 21
SLCDC Clock Enable—Enables/Disables peripheral 0 = SLCDC ipg clock input is disabled
clock ipg clock (PERCLK) input to the SLCDC module.
(default).
1 = SLCDC ipg clock input is enabled.
FIRI_BAUD_EN
Bit 20
FIRI Baud Clock Enable—Enables/Disables baud
rate clock input to the FIRI module.
0 = FIRI baud clock input is disabled (default).
1 = FIRI baud clock input is enabled.
NFC_EN
Bit 19
Nand Flash Controller Clock
Enable—Enables/Disables clock input to the NFC
module.
0 = NFC clock input is disabled.
1 = NFC clock input is enabled (default).
PERCLK3_EN
Bit 18
PERCLK3 Clock Enable—Enables/Disables pixel
clock input to the LCDC module.
0 = LCDC pixel clock input is disabled
(default).
1 = LCDC pixel clock input is enabled.
SSI1_BAUD_EN
Bit 17
SSI 1 Baud Clock Enable—Enables/Disables baud
rate clock input to the SSI1 module.
0 = SSI1 Baud clock input is disabled (default).
1 = SSI1 Baud clock input is enabled.
SSI2_BAUD_EN
Bit 16
SSI 2 Baud Clock Enable—Enables/Disables baud
rate clock input to the SSI2 module.
0 = SSI2 Baud clock input is disabled (default).
1 = SSI2 Baud clock input is enabled.
EMMA_EN
Bit 15
EMMA Clock Enable—Enables/Disables peripheral
0 = EMMA ipg clock input is disabled (default).
clock ipg clock (PERCLK) input to the EMMA module. 1 = EMMA ipg clock input is enabled.
USBOTG_EN
Bit 14
USB OTG Clock Enable—Enables/Disables
peripheral clock ipg clock (PERCLK) input to the
USB OTG module.
DMA_EN
Bit 13
DMA Clock Enable—Enables/Disables ipg clock input 0 = DMA IPG clock input is disabled. (default).
to the DMA module.
1 = DMA ipg clock input is enabled.
I2C_EN
Bit 12
I2C Clock Enable—Enables/Disables peripheral clock 0 = I2C ipg clock input is disabled (default).
ipg clock (PERCLK) input to the I2C module.
1 = I2C ipg clock input is enabled.
GPIO_EN
Bit 11
GPIO Clock Enable—Enables/Disables peripheral
clock ipg clock (PERCLK) input to the GPIO module.
SDHC2_EN
Bit 10
SDHC2 Clock Enable—Enables/Disables peripheral 0 = SDHC2 ipg clock input is disabled
clock ipg clock (PERCLK) input to the SDHC2 module.
(default).
1 = SDHC2 ipg clock input is enabled.
SDHC1_EN
Bit 9
SDHC1 Clock Enable—Enables/Disables peripheral 0 = SDHC1 ipg clock input is disabled
clock ipg clock (PERCLK) input to the SDHC1 module.
(default).
1 = SDHC1 ipg clock input is enabled.
0 = USB OTG ipg clock input is disabled.
1 = USB OTG ipg clock input is enabled
(default).
0 = GPIO ipg clock input is disabled (default).
1 = GPIO ipg clock input is enabled.
i.MX21 Reference Manual, Rev. 3
6-24
Freescale Semiconductor
Phase-Locked Loop (PLL), Clock and Reset Controller
Table 6-16. Peripheral Clock Control Register 0 Description (continued)
Name
Description
Settings
FIRI_EN
Bit 8
FIRI Clock Enable—Enables/Disables peripheral
clock ipg clock (PERCLK) input to the FIRI module.
0 = FIRI ipg clock input is disabled (default).
1 = FIRI ipg clock input is enabled.
SSI2_EN
Bit 7
SSI2 Clock Enable—Enables/Disables peripheral
clock ipg clock (PERCLK) input to the SSI2 module.
0 = SSI2 ipg clock input is disabled. (default).
1 = SSI2 ipg clock input is enabled
SSI1_EN
Bit 6
SSI1 Clock Enable—Enables/Disables peripheral
clock ipg clock (PERCLK) input to the SSI1 module.
0 = SSI1 ipg clock input is disabled. (default)
1 = SSI1 ipg clock input is enabled.
CSPI2_EN
Bit 5
CSPI2 Clock Enable—Enables/Disables peripheral
0 = CSPI2 ipg clock input is disabled (default).
clock ipg clock (PERCLK) input to the CSPI2 module. 1 = CSPI2 ipg clock input is enabled.
CSPI1_EN
Bit 4
CSPI1Clock Enable—Enables/Disables peripheral
0 = CSPI1 ipg clock input is disabled (default).
clock ipg clock (PERCLK) input to the CSPI1 module. 1 = CSPI1 ipg clock input is enabled.
UART4_EN
Bit 3
UART4 Clock Enable—Enables/Disables peripheral 0 = UART4 ipg clock input is disabled
clock ipg clock (PERCLK) input to the UART4 module.
(default).
1 = UART4 ipg clock input is enabled.
UART3_EN
Bit 2
UART3 Clock Enable—Enables/Disables peripheral 0 = UART3 ipg clock input is disabled
clock ipg clock (PERCLK) input to the UART3 module.
(default).
1 = UART3 ipg clock input is enabled.
UART2_EN
Bit 1
UART2 Clock Enable—Enables/Disables peripheral 0 = UART2 ipg clock input is disabled.
clock ipg clock (PERCLK) input to the UART2 module. 1 = UART2 ipg clock input is enabled (default).
UART1_EN
Bit 0
UART1 Clock Enable—Enables/Disables peripheral 0 = UART1 ipg clock input is disabled.
clock ipg clock (PERCLK) input to the UART1 module. 1 = UART1 ipg clock input is enabled (default).
NOTE
PERCLK1 and PERCLK2 are gated only when all of the corresponding
modules driven from these clocks are disabled at the module itself and in the
PCCR0 and PCCR1 registers.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
6-25
Phase-Locked Loop (PLL), Clock and Reset Controller
6.3.10
Peripheral Clock Control Register 1
The Peripheral Clock Control Register 1 (PCCR1) provides additional power saving capabilities by
controlling the clocks in the i.MX21 modules. It also controls the clock source for Bootstrap mode. The
PCCR1 allows for gating of the ipg clk (PERCLK) to specific peripherals.
RTC_EN
PWM_EN
GPT3_EN
GPT2_EN
GPT1_EN
30
29
28
27
26
25
22
21
20
19
18
17
16
CSPI3_EN
31
24
TYPE
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
23
Addr
0x10027024
WDT_EN
BIT
KPP_EN
Peripheral Clock Control Register 1
OWIRE_EN
PCCR1
rw
rw
rw
rw
r
r
r
r
r
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 6-17. Peripheral Clock Control Register 1 Description
Name
Description
Settings
OWIRE_EN OWIRE Clock Enable—Enables/Disables peripheral clock ipg
Bit 31
clock (PERCLK) input to the 1-Wire module.
0 = 1-Wire ipg clock input is disabled (default).
1 = 1-Wire ipg clock input is enabled.
KPP_EN
Bit 30
KPP Clock Enable—Enables/Disables peripheral clock ipg
clock (PERCLK) input to the KPP module.
0 = KPP ipg clock input is disabled (default).
1 = KPP ipg clock input is enabled.
RTC_EN
Bit 29
RTC Clock Enable—Enables/Disables peripheral clock ipg
clock (PERCLK) input to the RTC module.
0 = RTC ipg clock input is disabled (default).
1 = RTC ipg clock input is enabled.
PWM_EN
Bit 28
PWM Clock Enable—Enables/Disables peripheral clock ipg
clock (PERCLK) input to the PWM module.
0 = PWM ipg clock input is disabled (default).
1 = PWM ipg clock input is enabled.
GPT3_EN
Bit 27
GPT3 Clock Enable—Enables/Disables peripheral clock ipg
clock (PERCLK) input to the GPT3 module.
0 = GPT3 ipg clock input is disabled (default).
1 = GPT3 ipg clock input is enabled.
GPT2_EN
Bit 26
GPT2 Clock Enable—Enables/Disables peripheral clock ipg
clock (PERCLK) input to the GPT2 module.
0 = GPT2 ipg clock input is disabled (default).
1 = GPT2 ipg clock input is enabled.
GPT1_EN
Bit 25
GPT1 Clock Enable—Enables/Disables peripheral clock ipg
clock (PERCLK) input to the GPT1 module.
0 = GPT1 ipg clock input is disabled (default).
1 = GPT1 ipg clock input is enabled.
WDT_EN
Bit 24
WDT Clock Enable—Enables/Disables peripheral clock ipg
clock (PERCLK) input to the WDT module.
0 = WDT ipg clock input is disabled (default).
1 = WDT ipg clock input is enabled.
i.MX21 Reference Manual, Rev. 3
6-26
Freescale Semiconductor
Phase-Locked Loop (PLL), Clock and Reset Controller
Table 6-17. Peripheral Clock Control Register 1 Description (continued)
Name
Description
Settings
CSPI3_EN
Bit 23
CSPI3 Clock Enable—Enables/Disables peripheral clock ipg
clock (PERCLK) input to the CSPI3 module.
Reserved
Bit 22–0
Reserved—These bits are reserved and should read 0.
6.3.11
Clock Control Status Register
0 = CSPI3 ipg clock input is disabled (default).
1 = CSPI3 ipg clock input is enabled.
The Clock Control Status Register (CCSR) provides information on the configuration of the Analog and
Digital block. The clocks within the chip can also be monitored by the CLKO_SEL programming.
CCSR
Clock Control Status Register
Addr
0x10027028
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
32K_SR
TYPE
CLKO_SEL
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
RESET
0x0300
Table 6-18. Clock Control Status Register Description
Name
Description
Settings
Reserved
Bit 31–16
Reserved—These bit are reserved and should read 0.
32K_SR
Bit 15
32K Status Register—The 32K_SR contains the status information of the 32KHz 0 = CLK32 in low phase
1 = CLK32 in high phase
clock. The bit value is cleared to zero during the assertion of the
HARD_ASYNC_RESET signal. The sampled 32KHz clock phase is continuously
registered into the bit upon the deassertion of the HARD_ASYNC_RESET signal.
Reserved
Bit 14–5
Reserved—These bits are reserved and should read 0.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
6-27
Phase-Locked Loop (PLL), Clock and Reset Controller
Table 6-18. Clock Control Status Register Description (continued)
Name
Description
CLKO_SEL CLKO Select—Selects the clock signal source that is output on the CLKO pin.
Bits 4–0
Settings
00000 = CLK32
00001 = PREMCLK
00010 = CLK26M
00011 = MPLL Reference CLK
00100 = SPLL Reference CLK
00101 = MPLL CLK
00110 = SPLL CLK
00111 = FCLK
01000 = HCLK
01001 = PERCLK (IPG_CLK)
01010 = PERCLK1
01011 = PERCLK2
01100 = PERCLK3
01101 = PERCLK4
01110 = SSI 1 Baud
01111 = SSI 2 Baud
10000 = NFC Baud
10001 = FIRI Baud
10010 = CLK48M Always
10011 = CLK32K Always
10100 = CLK48M
10101 = CLK48DIV_CLKO
i.MX21 Reference Manual, Rev. 3
6-28
Freescale Semiconductor
Phase-Locked Loop (PLL), Clock and Reset Controller
6.3.12
Wakeup Guard Mode Control Register
The Wakeup Guard Mode Control Register (WKGDCTL) provides the configuration of the wakeup guard
mode. This is a write once only bit in order to be compatible with the watchdog behavior. After
enable/disable, it will not be modifiable. When enabled, the battery detector external to the chip provides
a glitch free signal through the TIN pin. Battery must be intact for the chip to wakeup from sleep.
WKGDCTL
Wakeup Guard Mode Control Register
Addr
0x10027034
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
WKGD_EN
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 6-19. Wakeup Guard Mode Control Register
Name
Reserved
Bit 31–1
Description
Settings
Reserved—These bit are reserved and should read 0.
WKDG_EN Wakeup Guard Mode Enable— Enables /disables the wakeup guard logic. 0 = Wakeup guard mode is disabled.
Bits 0
Write- once-only bit and can only be cleared through system reset. Once
1 = Wakeup guard mode is enabled.
enabled, the battery indicator through TIN will be used to qualify the wakeup
process. When battery is intact—that is, TIN=1, wakeup from sleep proceed
as per normal. When WKGD_EN=1 and battery is removed, the 32 kHz to
the watchdog module is gated off. Clock resumed when battery is back in
place.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
6-29
Phase-Locked Loop (PLL), Clock and Reset Controller
6.4
Functional Description of the Reset Module
The reset module controls or distributes all of the system reset signals used by the i.MX21. A simplified
block diagram of the reset module is shown in Figure 6-2. The reset module generates two distinct
events—a global reset and an ARM9 platform reset.
RESET_POR
POR
RESET_POR
300ms
Counter
RESET_DRAM
7-cycle
stretcher
CLK32
POR_TIMEOUT
(programmed values)
CLK32
GLOBAL_RESET_INT
HRESET
14-cycle
stretcher
syn logic
HARD_ASYNC_RESET
CLK32
hclk
RESET
4-cycle
qualifier
WDOG_RESET
Rising edge
detector
CLK32
RSR
IP bus
EXT_RESET
Figure 6-2. Reset Module Clock Diagram
6.4.1
Global Reset
A global reset is produced by the simultaneous assertion of the following resets:
• RESET_DRAM
• HRESET
• HARD_ASYNC_RESET
• RESET_POR
There is one source capable of generating a global reset: A low condition on the POR pin when the 32 kHz
crystal oscillator is running.
The HRESET and HARD_ASYNC_RESET are armed simultaneously; they remain in that state for 14
CLK32 cycles.
RESET_DRAM is deasserted seven CLK32 cycles before HRESET and HARD_ASYNC_RESET are
deasserted. The SDRAM executes the necessary self refresh operations during this time.
i.MX21 Reference Manual, Rev. 3
6-30
Freescale Semiconductor
Phase-Locked Loop (PLL), Clock and Reset Controller
The timing diagram in Figure 6-2 shows the relationship of the reset signal timings. See Table 6-20 for
reset module signal and pin definitions.
The following signal conditions are not capable of generating a global reset, however their assertion will
reset the ARM9 platform:
• An external qualified low condition on the RESET_IN pin
• A low condition on WDOG_RESET
Furthermore, these reset conditions will not reset the SDRAMC, Real Time Clock, WatchDog module, or
allow a change in boot mode—that is, changes made to BOOT[3:0] during these resets conditions will not
take affect. Only the global reset is capable of this.
The source of the last hardware reset can be determined in the watchdog status register.
NOTE
Due to the asynchronous nature of the RESET_IN signal, the time period
required to qualify the signal may vary, and the HRESET timing relative to
the rising edge of the RESET_IN is also affected. A RESET_IN signal
shorter than three CLK32 cycles will not be qualified, a RESET_IN signal
equal to or longer than four CLK32 cycles will always be qualified, and any
period length that is more than three and less than four CLK32 cycles is
undefined.
POR is the reset signal for all the reset module flip-flops. For this reason, an
external reset signal is qualified if it lasts more than four CLK32 cycles
when POR is deasserted.
During power on the user must ensure that POR stay asserted (low) long
enough for the 32kHz crystal to stabilize.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
6-31
Phase-Locked Loop (PLL), Clock and Reset Controller
POR
Can be adjusted depending on the crystal
start-up time 32kHz or 32.768kHz
RESET_POR
Exact 300ms
7 cycles @ CLK32
RESET_DRAM
14 cycles @ CLK32
HRESET
RESET_OUT
CLK32
HCLK
Figure 6-3. DRAM and Internal Reset Timing Diagram
6.4.2
ARM9 Platform Reset
Any qualified global reset signal resets the ARM9 platform and all related peripherals to their default state.
After the internal reset is deasserted, the ARM9 processor begins fetching code from the internal bootstrap
ROM or CS0 space. The memory location of the fetch depends on the configuration of the BOOT pins and
the value of the TEST pin on the rising edge of the HRESET.
Table 6-20. Reset Module Pin and Signal Descriptions
Signal Name
Direction
Signal Description
CLK32
IN
32 kHz Clock—A 32 kHz clock signal derived from the 32K crystal oscillator circuit in the
PLL Clock Controller.
POR
IN
Power-On Reset—An internal active Schmitt trigger signal from the POR pin. The POR
signal is normally generated by an external RC circuit designed to detect a power-up event.
RESET_IN
IN
Reset—An external active low Schmitt trigger signal from the RESET_IN pin. When this
signal goes active, all modules (except the SDRAMC, Real Time Clock, WatchDog, and the
BOOT[3:0] signals) are reset.
WDOG_RESET
IN
Watchdog Timer Reset—An active low signal generated by the watchdog timer when a
time-out period has expired. Resets the same modules as RESET_IN.
HARD_ASYN_RESET
OUT
Hard Asynchronous Reset—An active low signal that resets all peripheral modules except
the watchdog module’s status register. The rising edge of this signal is synchronous with
IPG_CLK.
HRESET
OUT
Hard Reset—An active low signal that resets the ARM9 platform. This signal is deasserted
during the low phase of HCLK. This signal also appears on the RESET_OUT pin of the
i.MX21.
RESET_DRAM
OUT
DRAM Reset—An active low signal that resets the SDRAM controller.
i.MX21 Reference Manual, Rev. 3
6-32
Freescale Semiconductor
Chapter 7
AHB-Lite IP Interface (AIPI) Module
This chapter provides an overview of the AHB-Lite to IP bus interface (AIPI) module. The AIPI acts as
an interface between the advanced ARM High-performance Bus “Lite” (AHB-Lite) and lower bandwidth
peripherals conforming to the Freescale IP Bus Specification. There are two AIPI modules in i.MX21.
The following list summarizes the key features of the AIPI:
• All peripheral read transactions require a minimum of 2 system clocks (R-AHB side) and all write
transactions require a minimum of 3 system clocks (R-AHB side).
• The AIPI supports 8-bit, 16-bit and 32-bit IP bus peripherals. (Byte, half word and word reads and
write are supported to each.)
• The AIPI supports multi-cycle accesses (16-bit operations to 8-bit peripherals and 32-bit
operations to 16-bit and 8-bit peripherals).
• The AIPI supports 31 external IP bus peripherals each with a 4 Kbyte memory map (a slot).
Table 7-1. AHB-Lite To IP Bus V2.0 Interface Operation (Little Endian)
Transfer
Size
Byte
haddr
[1]
[0]
0
0
0
IP Bus
Size
ips_addr
Active Bus Section (R-AHB to IP Bus)
[1]
[0]
R-AHB[31:24]
R-AHB[23:16]
R-AHB[15:8]
R-AHB[7:0]
0
0
–
–
–
ips_data[7:0]
1
0
1
–
–
ips_data[7:0]
–
1
0
1
0
–
ips_data[7:0]
–
–
1
1
1
1
ips_data[7:0]
–
–
–
0
0
0
X
–
–
–
ips_data[7:0]
0
1
–
–
ips_data[15:8]
–
1
0
-
ips_data[7:0]
–
–
1
1
ips_data[15:8]
–
–
–
0
0
–
–
–
ips_data[7:0]
0
1
–
–
ips_data[15:8]
–
1
0
–
ips_data[23:16]
–
–
1
1
ips_data[31:24]
–
–
–
8 bit
16 bit
1
32 bit
X
X
X
X
X
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
7-1
AHB-Lite IP Interface (AIPI) Module
Table 7-1. AHB-Lite To IP Bus V2.0 Interface Operation (Little Endian) (continued)
Transfer
Size
Half Word
haddr
[1]
[0]
0
NA
IP Bus
Size
8 bit
1
16 bit
1
0
32 bit
1
NA
NA
8 bit
[0]
R-AHB[31:24]
R-AHB[23:16]
R-AHB[15:8]
R-AHB[7:0]
0
0
–
–
–
ips_data[7:0]
1
–
–
ips_data[7:0]
–
0
–
ips_data[7:0]
–
–
1
ips_data[7:0]
–
–
–
0
X
–
–
ips_data[15:8]
ips_data[7:0]
1
X
ips_data[15:8]
ips_data[7:0]
–
–
X
X
–
–
ips_data[15:8]
ips_data[7:0]
X
X
ips_data[31:24]
ips_data[23:16]
–
–
0
0
–
–
–
ips_data[7:0]
1
–
–
ips_data[7:0]
–
0
–
ips_data[7:0]
–
–
1
ips_data[7:0]
–
–
–
0
X
–
–
ips_data[15:8]
ips_data[7:0]
1
X
ips_data[15:8]
ips_data[7:0]
–
–
X
X
ips_data[31:24]
ips_data[23:16]
ips_data[15:8]
ips_data[7:0]
1
16 bit
32 bit
7.1
Active Bus Section (R-AHB to IP Bus)
[1]
1
0
Word
ips_addr
Programming Model
There are three registers that reside inside the AIPI. These registers correspond to the first slot (4 Kbyte
memory region) of each of the 2 AIPIs in i.MX21 at 0x1000_0000 and 0x1002_0000, respectively. All
three registers are 32-bit registers and can only be accessed in supervisor mode. Additionally, these
registers can only be read from or written to by a 32-bit access.
Two system clocks are required for read accesses and three system clocks are required for write accesses
to the AIPI registers.
CAUTION
Writing to reserved register locations within the 4 Kbyte memory map of the
AIPI register space (other than the three AIPI registers) will result in
unknown behavior and an abort exception.
Access to Reserved or Unoccupied locations in the AIPI space will result in
an abort exception.
i.MX21 Reference Manual, Rev. 3
7-2
Freescale Semiconductor
AHB-Lite IP Interface (AIPI) Module
7.1.1
Peripheral Size Registers[1:0]
These registers are used to tell the AIPI what size of IP bus peripheral is in each IP bus peripheral location.
Peripheral locations that are not occupied should have their corresponding bits in the peripheral size
registers (PSRs) programmed to 1 in each register.
The least significant bit in the PSRs is a read-only bit as it governs the AIPI registers themselves. They are
set and cleared appropriately to indicate the registers are 32-bit.
PSR0
Addr
0x1000_0000
0x1002_0000
Peripheral Size Register 0
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
PSR1
Addr
0x1000_0004
0x1002_0004
Peripheral Size Register 1
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
The PSRs work together to indicate the size of the IP bus peripheral occupying the corresponding location,
or to indicate there is no IP bus peripheral occupying the corresponding location. Table 7-2 shows how to
program the PSR registers based on the size or availability of an IP bus peripheral.
Table 7-2. PSR 1–0 Data Bus Size Encoding
PSR 1–0
IP Bus Peripheral SIZE [x]
00
8-bit
01
16-bit
10
32-bit
11
Unoccupied
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
7-3
AHB-Lite IP Interface (AIPI) Module
7.1.2
Peripheral Access Register
The peripheral access register (PAR) tells the AIPI whether the IP bus peripheral corresponding to the bit
location in this register may be accessed in user mode. If the peripheral may be accessed in supervisor
mode only and a user mode access is attempted, an abort is generated and no IP bus activity occurs.
The least significant bit in the PAR is a read-only bit as it governs the AIPI registers themselves. It is set
to indicate supervisor access only.
Peripheral Access Register1
PAR
Addr
0x1000_0008
0x1002_0008
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A “1” indicates the corresponding peripheral is a supervisor access only peripheral. A “0” indicates the decision is left
up to the peripheral (the AIPI allows user accesses).
7.2
AIPI1 and AIPI2 Peripheral Widths and PSR Setting
Table 7-5 shows the data bus widths of the peripherals on the AIPI1 and the AIPI2 interfaces. System
software should make use of information in the column, “Data Bus Width” to configure the PSR registers,
accordingly.
Table 7-3 and Table 7-4 show PSR settings for AIPI1 and AIPI2.
Table 7-5 shows the peripheral sizes for the occupied, reserved and unoccupied locations. All reserved
locations must be programmed as 32-bit locations.
Table 7-3. AIPI1 PSR Setting
PSR
Setting
PSR[1]
0xFFFB_FCFB
PSR[0]
0x0004_0304
Table 7-4. AIPI2 PSR Setting
PSR
Setting
PSR[1]
0xFFFF_FFFF
PSR[0]
0x3FFC_0000
i.MX21 Reference Manual, Rev. 3
7-4
Freescale Semiconductor
AHB-Lite IP Interface (AIPI) Module
Table 7-5. i.MX21 AIPI Peripheral Access Sizes and IP Access Types
Location
Peripheral
PSR[1]
PSR[0]
Data Bus
Width
16-bit
8-bit
Read
Write
Read
Write
AIPI1
0
AIPI1 Control
1
0
32-bit
–
–
–
–
1
DMA
1
0
32-bit
Y
Y
Y
Y
2
WDOG
0
1
16-bit
Y
Y
3
GPT1
1
0
32-bit
N
N
N
N
4
GPT2
1
0
32-bit
N
N
N
N
5
GPT3
1
0
32-bit
N
N
N
N
6
PWM
1
0
32-bit
N
N
N
N
7
RTC
1
0
32-bit
Y
Y
Y
Y
8
KPP
0
1
16-bit
–
N
N
9
1-Wire
0
1
16-bit
–
N
N
10
UART1
1
0
32-bit
N
Y
N
Y
11
UART2
1
0
32-bit
N
Y
N
Y
12
UART3
1
0
32-bit
N
Y
N
Y
13
UART4
1
0
32-bit
N
Y
N
Y
14
CSPI1
1
0
32-bit
N
N
N
N
15
CSPI2
1
0
32-bit
N
N
N
N
16
SSI1
1
0
32-bit
N
N
N
N
17
SSI2
1
0
32-bit
N
N
N
N
18
I2C
0
1
16-bit
Y
Y
19
SDHC1
1
0
32-bit
N
N
N
N
20
SDHC2
1
0
32-bit
N
N
N
N
21
GPIO
1
0
32-bit
N
N
N
N
22
AUDMUX
1
0
32-bit
N
N
N
N
23
CSPI3
1
0
32-bit
N
N
N
N
23-31
Reserved
1
0
32-bit
N
N
N
N
–
–
AIPI2
0
AIPI2
1
0
32-bit
–
1
LCDC
1
0
32-bit
N
N
N
N
2
SLCDC
1
0
32-bit
N
N
N
N
3
Reserved
1
0
32-bit
N
N
N
N
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
7-5
AHB-Lite IP Interface (AIPI) Module
Table 7-5. i.MX21 AIPI Peripheral Access Sizes and IP Access Types (continued)
Location
Peripheral
PSR[1]
PSR[0]
Data Bus
Width
16-bit
8-bit
Read
Write
Read
Write
4
USB OTG
1
0
32-bit
N
N
Y
Y
5
USB OTG
1
0
32-bit
N
N
N
N
6
EMMA
1
0
32-bit
N
N
N
N
7
CRM
1
0
32-bit
Y
Y
Y
Y
8
FIRI
1
0
32-bit
Y
Y
Y
Y
9
Reserved
–
–
–
–
–
–
–
10-17
Reserved
1
0
32-bit
N
N
N
N
18-29
Unoccupied
1
1
–
N
N
N
N
7.3
Interface Timing
This section describes AIPI interface timing characteristics.
7.3.1
Read Cycles
Two clock read accesses are possible with the AIPI when the requested access size is equal to or smaller
than the size of the targeted IP bus peripheral. If the requested access size is larger than that of the targeted
IP bus peripheral (for example, a 32-bit access to a 16 bit peripheral) then a minimum of three clocks are
required to complete the access.
7.3.2
Write Cycles
Three clock write accesses are possible with the AIPI when the requested access size is equal to or smaller
than the size of the targeted IP bus peripheral. If the requested access size is larger than that of the targeted
IP bus peripheral (for example, a 32-bit access to a 16 bit peripheral) then a minimum of four clocks are
required to complete the access.
7.3.3
Aborted Cycles
The AIPI follows a standard procedure when a cycle is aborted and the abort is initiated by the AIPI itself
or the targeted IP bus peripheral. The AIPI either fails to initiate or immediately terminates any IP bus
activity that is ongoing.
There are several conditions that can cause the AIPI to abort the current operation and report an error. The
first is the case in which the targeted IP bus peripheral asserts its internal error signal. In this case the AIPI
immediately terminates access to the targeted IP bus peripheral. Whether the current IP bus access is a
multi-cycle access or a single cycle access has no bearing on the behavior of the AIPI. The AIPI responds
identically in both cases.
i.MX21 Reference Manual, Rev. 3
7-6
Freescale Semiconductor
AHB-Lite IP Interface (AIPI) Module
The second case that can cause an error response to the AHB-Lite is when a user-mode access is attempted
to an IP bus peripheral whose corresponding PAR bit indicates it is a supervisor-only peripheral. In this
case the AIPI does not initiate any IP bus activity but instead responds immediately by following the abort
procedure described above.
The third case that can cause an error response to the AHB-Lite is when an access is attempted to a location
at which the PSRs indicate there is no IP bus peripheral. In this case the AIPI does not initiate any IP bus
activity but instead responds immediately by following the abort procedure described above.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
7-7
AHB-Lite IP Interface (AIPI) Module
i.MX21 Reference Manual, Rev. 3
7-8
Freescale Semiconductor
Part 3
System Control
Chapter 8, “System Control,” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 8-1
Chapter 9, “Internal ROM, System Boot Manager,” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 9-1
Chapter 10, “Multi-layer AHB Crossbar Switch (MAX),” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 10-1
Chapter 11, “JTAG Controller,” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 11-1
Chapter 12, “Watchdog Timer Module (WDOG),” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 12-1
Chapter 13, “Real-Time Clock (RTC),” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 13-1
Chapter 14, “General-Purpose Timers (GPT),” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 14-1
Chapter 15, “General-Purpose I/O (GPIO),” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 15-1
Chapter 16, “Pulse-Width Modulator (PWM),” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 16-1
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
1
i.MX21 Reference Manual, Rev. 3
2
Freescale Semiconductor
Chapter 8
System Control
This chapter describes the system control module of the i.MX21 microprocessor. The system control
module enables system software to control, customize, or read the status of the following functions:
• Chip ID
• Multiplexing of I/O signals
• I/O Driving Strength
• Well Bias Control
• System boot mode selection
8.1
Programming Model
The system control module includes one 128-bit Silicon ID and fifteen user-accessible 32-bit registers.
Table 8-1 summarizes these registers and their addresses.
Table 8-1. System Control Module Register Summary
Description
Name
Address
Silicon ID Register
SIDR
0x10027804
Function Multiplexing Control Register
FMCR
0x10027814
Global Peripheral Control Register
GPCR
0x10027818
Well Bias Control Register
WBCR
0x1002781C
Driving Strength Control Register 1
DSCR1
0x10027820
Driving Strength Control Register 2
DSCR2
0x10027824
Driving Strength Control Register 3
DSCR3
0x10027828
Driving Strength Control Register 4
DSCR4
0x1002782C
Driving Strength Control Register 5
DSCR5
0x10027830
Driving Strength Control Register 6
DSCR6
0x10027834
Driving Strength Control Register 7
DSCR7
0x10027838
Driving Strength Control Register 8
DSCR8
0x1002783C
Driving Strength Control Register 9
DSCR9
0x10027840
Driving Strength Control Register 10
DSCR10
0x10027844
Driving Strength Control Register 11
DSCR11
0x10027848
Driving Strength Control Register 12
DSCR12
0x1002784C
Priority Control and Select Register
PCSR
0x10027850
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
8-1
System Control
8.1.1
Silicon ID Register
This register consists of laser programmable Silicon ID and Unique Identifier. The Unique Identifier is 48
laser programmable bits where the Silicon ID and Unique Identifier are accessible by the IP bus interface
to the MCU. The 96-bit register can only be accessed in 32-bit access mode. The register bit[31:0] is
located on 0x10027804. The settings for the bits in the register are listed in Table 8-2 (As laser fuse:
Fuse-burn means logic 0, Fuse-non-burn means logic 1).
SIDR
BIT
Silicon ID Register
95
94
93
92
91
90
89
88
87
0x10027804
86
85
84
83
82
81
80
CID
TYPE
RESET
BIT
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
1
0
0
0
0
0
0
0
1
1
1
0
1
70
69
68
67
66
65
64
0x101D
79
78
77
76
75
74
73
72
71
CID
TYPE
RESET
BIT
TYPE
RESET
BIT
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
1
0
0
0
0
0
0
0
1
1
1
0
1
54
53
52
51
50
49
48
0x101D
63
62
61
60
59
58
57
56
55
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
38
37
36
35
34
33
32
0x0000_0000
47
46
45
44
43
42
41
40
39
SUID
TYPE
RESET
BIT
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
0x0000_0000
31
30
29
28
27
26
25
24
23
SUID
TYPE
RESET
BIT
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
0x0000
15
14
13
12
11
10
9
8
7
SUID
TYPE
RESET
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
i.MX21 Reference Manual, Rev. 3
8-2
Freescale Semiconductor
System Control
Table 8-2. Silicon ID Register Description
Name
Description
Settings
CID
Bits 95–64
Chip ID—Contains the chip identification number of the i.MX21 (mask 0M55B = 0x101D101D
set number identification).
1M55B = 0x201D101D
Note: Refer to the MC9328MX21RM Addendum if your silicon ID is the M55B = 0x201D101D
older, nL45X silicon version, for specific PCMCIA register and
signal differences.
Reserved
Bits 63–48
Reserved—These bits are reserved and should read 0.
SUID
Bits 47–0
Silicon Unique ID—Contains the chip unique identification number of
the i.MX21, the ID number is laser programmed during package.
8.1.2
Blown[x]=1
Intact[x]= 0
Function Multiplexing Control Register
The Function Multiplexing Control Register (FMCR) controls the multiplexing of the signal lines shared
by the SLCDC module, UART module, and Keypad module as well as the SDRAM chip select lines. The
FMCR also allows control or indicates the boot status of the NAND Flash page size and data port size.
Finally, the FMCR contains a bit setting for the Well Bias control to enable optimal power savings during
STOP mode when Well Bias Mode is enabled (refer to Section 8.1.4 on page -7 for more information on
the Well Bias feature). See Table 8-3 for detailed description of bit settings.
23
22
21
20
19
18
KP_COL6_CTL
KP_ROW7_CTL
KP_ROW6_CTL
BIT
31
30
29
28
27
26
25
TYPE
rw
rw
rw
rw
rw
rw
1
1
1
1
1
1
1
24
Addr
0x10027814
UART4_RTS_CTL
Function Multiplexing Control Register
UART4_RXD_CTL
FMCR
17
16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
1
1
1
1
1
1
1
1
4
3
2
1
0
RESET
10
9
8
7
6
5
CRM_SPA_SEL
Reserved
NF_FMS
NF_16BIT_SEL
SLCDC_SEL
SDCS1_SEL
SDCS0_SEL
0xFFFF
BIT
15
14
13
12
TYPE
rw
rw
rw
1
1
1
1
11
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
1
1
1
1
1
0
0
1
0
1
1
RESET
0xFFCB
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
8-3
System Control
Table 8-3. Function Multiplexing Control Register Description
Name
Reserved
Bits 31–26
Description
Settings
Reserved—These bits are reserved and should read 1.
UART4_RXD_CTL UART4 RXD Control—When set, the alternate signal of
0 = The USBH1_TXDP (PB29) GPIO’s
Bit 25
USBH1_RXDP (PB31) is input to RXD of UART4. When 0, the
AOUT is input to RXD of UART4.
USBH1_TXDP (PB29) GPIO’s AOUT is input to RXD of UART4. 1 = The alternate signal of
With either setting, the user must also ensure that the proper
USBH1_RXDP (PB31) is input to
GPIO registers have been programmed to select the desired
RXD of UART4.
multiplexing.
UART4_RTS_CTL UART4 RTS Control—When set, the alternate signal of
0 = The USBH1_RXDP (PB31) GPIO’s
Bit 24
USBH1_FS (PB26) is input to RTS of UART4. When 0, the
AOUT is input to RTS of UART4.
USBH1_RXDP (PB31) GPIO’s AOUT is input to RTS of UART4. 1 = The alternate signal of USBH1_FS
With either setting, the user must also ensure that the proper
(PB26) is input to RTS of UART4.
GPIO registers have been programmed to select the desired
multiplexing.
Reserved
Bits 23–19
Reserved—These bits are reserved and should read 1.
KP_COL6_CTL
Bit 18
Keypad Column 6 Control—When set, the alternate signal of 0 = The alternate signal of TEST_WB2
UART2_TXD (PE6) is input to column 6 of keypad. When 0, the
(PE0) is input to column 6 of
alternate signal of TEST_WB2 (PE0) is input to column 6 of
keypad.
keypad. With either setting, the user must also ensure that the 1 = The alternate signal of UART2_TXD
proper GPIO registers have been programmed to select the
(PE6) is input to column 6 of
desired multiplexing.
keypad.
KP_ROW7_CTL
Bit 17
0 = The alternate signal of TEST_WB0
Keypad Row 7 Control—When set, the alternate signal of
(PE2) is input to row 7 of keypad.
UART2_RTS (PE4) is input to row 7of keypad. When 0, the
alternate signal of TEST_WB0 (PE2) is input to row 7 of keypad. 1 =The alternate signal of UART2_RTS
(PE4) is input to row 7of keypad.
With either setting, the user must also ensure that the proper
GPIO registers have been programmed to select the desired
multiplexing.
KP_ROW6_CTL
Bit 16
Keypad Row 6 Control—When set, the alternate signal of
0 = The alternate signal of TEST_WB1
UART2_RXD (PE7) is input to row 6 of keypad. When 0, the
(PE1) is input to row 6 of keypad.
alternate signal of TEST_WB1 (PE1) is input to row 6 of keypad. 1 = The alternate signal of UART2_RXD
With either setting, the user must also ensure that the proper
(PE7) is input to row 6 of keypad.
GPIO registers have been programmed to select the desired
multiplexing.
Reserved
Bits 15–13
Reserved—These bits are reserved and should read 1.
CRM_SPA_SEL
Bit 12
CRM Set Point Adjust Select—When enabling Well Bias, the
user should set this bit to 1 for optimal power savings during
STOP mode. A setting of 0 is reserved when Well Bias is
enabled.
Reserved
Bit 11
Reserved—This bit is reserved and should read 1.
Reserved
Bits 10–6
Reserved—These bits are reserved and should read 1.
0 = Reserved when Well Bias is
enabled.
1 = Selects Well Bias optimal power
savings when Well Bias is enabled.
This bit has no effect when Well Bias is
disabled.
i.MX21 Reference Manual, Rev. 3
8-4
Freescale Semiconductor
System Control
Table 8-3. Function Multiplexing Control Register Description (continued)
Name
Description
Settings
NF_FMS
Bit 5
Flash Memory Select—When Boot[3:0] = 0010 or 0011, the
0 = NAND Flash with 512B page size
NF_FMS will be set, otherwise it will be 0. After Bootup, this bit
(64Mb/128Mb/256Mb/512Mbyte/
is user programmable.
1Gbyte DDP)
1 = NAND Flash with 2 Kbyte page size
(1Gbyte/2Gbyte DDP/2Gbyte)
Note: DDP means Double Density
Package.
NF_16BIT_SEL
Bit 4
Nand Flash 16-bit Select—Selects 16-bit NF. Setting this bit by 0 = NAND Flash 8-bit
SW will force to select NAND Flash 16-bit mode and the NAND 1 = NAND Flash 16-bit
Flash upper data presents to the pins. Clearing this bit by SW will
force the NF to 8-bit mode and the A[25:21]signals become the
function pins. The muxing is done in the EMI module, not I/O
mux module. During system boot up, if the BOOT[3:0] input pins
are configured to select 16-bit mode, this NF_16BIT_SEL bit is
set.
Reserved
Bit 3
Reserved—This bit is reserved and should read 0.
SLCDC_SEL
Bit 2
SLCDC Select—Select whether a BaseBand chip (BB) or the 0 = On Chip SLCDC drives the SLCDC
port.
i.MX21 Application Processor drives the SLCDC display port in
1 = BB can write directly to the SLCDC
serial mode.
port.
SDCS1_SEL
Bit 1
SDRAM Chip Select—Selects the function of the CS3/CSD1
pin.
0 = CS3 selected
1 = CSD1 selected
SDCS0_SEL
Bit 0
SDRAM Chip Select—Selects the function of the CS2/CSD0
pin.
0 = CS2 selected
1 = CSD0 selected
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
8-5
System Control
8.1.3
Global Peripheral Control Register (GPCR)
The Global Peripheral Control Register (GPCR) displays the current boot mode of the i.MX21. The clock
gating to the IP modules can be controlled by this register. Descriptions of the register settings appear in
Table 8-4.
GPCR
BIT
Global Peripheral Control Register
31
30
29
28
27
26
25
24
23
22
Addr
0x10027818
21
20
19
18
17
16
BOOT
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
6
5
4
CLOCK_GATING_EN
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
rw
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
RESET
0x000C
Table 8-4. Global Peripheral Control Register Description
Name
Description
Settings
Reserved
Bits 31–20
Reserved—These bits are reserved and should read 0.
BOOT
Bits 19–16
Boot Mode—These are 4-bit system boot mode for 0000 = Bootstrap from UART/USB
the i.MX21.
0001 = Bootstrap from UART/USB
0010 = 8-bit NAND Flash (2 Kbyte per page)
0011 = 16-bit Nand Flash (2 Kbyte per page)
0100 = 16-bit Nand Flash (512Bytes per page)
0101 = 16-bit CS0
0110 = 32-bit CS0
0111 = 8 bit Nand Flash (512Bytes per page)
1xxx = Reserved for Test Modes
Reserved
Bit 15–4
Reserved—These bits are reserved and should read 0.
CLOCK_GATING_EN Clock Gating Enable—When set to 1, the peripheral register access clocks ipg_clk_s1 and ipg_clk_s2
Bit 3
will be gated by the aipi1_ips_module_en and aipi2_ips_module_en. For example, when there is a
register read or write access to the peripherals of AIPI1, the ipg_clk_s1 clock will be running, otherwise
if no access is taking place the clock will shut off and when there is a register read or write access to
the peripherals of AIPI2, the ipg_clk_s2 clock will be running, otherwise if no access is taking place the
clock shuts off.
When this bit is cleared to 0 then ipg_clk_s1 and ipg_clk_s2 will become a continuous clock, regardless
of peripheral accesses.
It is recommended for maximum power savings to ensure this bit is set to 1.
Reserved
Bit 2–0
Reserved—These bit are reserved and should read 0.
i.MX21 Reference Manual, Rev. 3
8-6
Freescale Semiconductor
System Control
8.1.4
Well Bias System
The i.MX21 processor employs an innovative system feature to help reduce leakage current of the
ARM926 core logic during STOP mode called Well Biasing. The Well Bias System reduces the leakage
current of the QVDDx sub-system (mainly the ARM core logic) during STOP (low-power) mode by
increasing the threshold voltage of the QVDDx sub-system transistors. The following section describes
how to enable and take advantage of this power saving feature.
8.1.5
Well Bias Control Register (WBCR)
The Well Bias Control Register (WBCR) allows the user to enable the Well Biasing System. At default
the Well Biasing System is disabled. To enable the Well Biasing System and take advantage of this power
saving feature, the following bit settings must occur in the WBCR: the CRM_WBS bits must set to 01, the
CRM_WBFA bit must be set to 1, and the CRM_WBM bits must be set to 001. In addition, the
CRM_SPA_SEL bit in the FMCR must also be set to 1.
WBCR
Well Bias Control Register
Addr
0x1002781C
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
Reserved
TYPE
11
10
9
8
Reserved
7
6
CRM_WBS
Reserved
CRM_WBFA
CRM_WBM
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 8-5. Well Bias Control Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
Reserved
Bits 15–13
Reserved—These bits are reserved and should read 0.
Reserved
Bits 12–8
Reserved—These bits are reserved and should read 0.
Settings
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
8-7
System Control
Table 8-5. Well Bias Control Register Description (continued)
Name
Description
Settings
CRM_WBS
Bits 7–6
Well Bias Switching Mode—For proper operation in Well Bias mode, 00 = Reserved
these bits should be set to 01.
01 = Suggested mode when Well Bias
enabled
10 = Reserved
11 = Reserved
These bits have no effect when Well
Bias is disabled.
Reserved
Bits 5–4
Reserved—These bits are reserved and should read 0.
CRM_WBFA
Bit 3
Well Bias Frequency Adjust—For optimal power savings, the user
should set this bit to 1 when Well Bias is enabled.
CRM_WBM
Bits 2–0
000 = Well Bias not applied
CRM_WBM—Enables or disables Well Bias System during STOP
mode. To enable Well Bias during STOP mode, these bits must be set 001 = Well Bias @ STOP
to 001. To disable Well Bias, these bits must be set to 000. All other bit 010–111 = Reserved
settings are reserved.
8.1.6
0 = Reserved
1 = Suggested setting for optimal power
savings when Well Bias is enabled
This bit has no effect when Well Bias is
disabled.
Driving Strength Control Register 1
The Driving Strength Control Register 1 (DSCR1) controls the driving force parameters of the all the slow
I/O signals in the i.MX21. Descriptions of the register settings appear in Table 8-6.
DSCR1
BIT
TYPE
Driving Strength Control Register 1
31
30
29
28
27
26
25
r
r
r
r
r
r
r
0
0
0
0
0
0
0
24
23
Addr
0x10027820
22
21
20
19
18
17
16
DS_SLOW8
DS_SLOW7
DS_SLOW6
rw
rw
rw
0
0
1
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0040
BIT
TYPE
15
14
12
11
10
9
8
DS_SLOW5
DS_SLOW4
DS_SLOW3
DS_SLOW2
DS_SLOW1
rw
rw
rw
rw
rw
r
0
13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
i.MX21 Reference Manual, Rev. 3
8-8
Freescale Semiconductor
System Control
Table 8-6. Driving Strength Control Register 1 Description
Name
Description
Settings
Reserved
Bits 31–25
Reserved—These bits are reserved and should read 0.
DS_SLOW8
Bits 24–22
Driving Strength Slow I/O—Controls the driving strength of the LCDC and BMI I/O signals. 000 = 2 mA
001 = 4 mA
011 = 8 mA
111 = 12 mA
DS_SLOW7
Bits 21–19
Driving Strength Slow I/O—Controls the driving strength of the SDI2 I/O signals.
000 = 2 mA
001 = 4 mA
011 = 8 mA
111 = 12 mA
DS_SLOW6
Bits 18–16
Driving Strength Slow I/O—Controls the driving strength of the CSI I/O signals.
000 = 2 mA
001 = 4 mA
011 = 8 mA
111 = 12 mA
Reserved
Bits 15
Reserved—This bit is reserved and should read 0.
DS_SLOW5
Bits 14–12
Driving Strength Slow I/O—Controls the driving strength of the OSBOTG and UART4 I/O 000 = 2 mA
signals.
001 = 4 mA
011 = 8 mA
111 = 12 mA
DS_SLOW4
Bits 11–9
Driving Strength Slow I/O—Controls the driving strength of the SSI1, SSI2, SAP, GPT and 000 = 2 mA
SSI3 I/O signals.
001 = 4 mA
011 = 8 mA
111 = 12 mA
DS_SLOW3
Bits 8–6
Driving Strength Slow I/O—Controls the driving strength of the I2C, CSPI1 and CSPI2 I/O 000 = 2 mA
signals.
001 = 4 mA
011 = 8 mA
111 = 12 mA
DS_SLOW2
Bits 5–3
Driving Strength Slow I/O—Controls the driving strength of the RESET_OUT, KP, JTAG,
UART1, UART2, UART3 and PWM I/O signals.
000 = 2 mA
001 = 4 mA
011 = 8 mA
111 = 12 mA
DS_SLOW1
Bits 2–0
Driving Strength Slow I/O—Controls the driving strength of the SD1 I/O signals.
000 = 2 mA
001 = 4 mA
011 = 8 mA
111 = 12 mA
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
8-9
System Control
8.1.7
Driving Strength Control Register 2
The Driving Strength Control Register 2 (DSCR2) controls the driving force parameters of the fast I/O
signals in the i.MX21. Descriptions of the register settings appear in Table 8-7.
DSCR2
BIT
TYPE
Driving Strength Control Register 2
31
30
r
0
0
29
28
27
26
25
24
23
Addr
0x10027824
22
21
20
19
18
17
DS_D22
DS_D23
DS_D24
DS_D25
DS_D26
rw
rw
rw
rw
rw
0
0
0
0
0
0
16
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
TYPE
15
14
r
0
0
13
12
11
10
9
8
DS_D27
DS_D28
DS_D29
DS_D30
DS_D31
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 8-7. Driving Strength Control Register 2 Description
Name
Description
Settings
Reserved
Bit 31
Reserved—This bit is reserved and should read 0.
DS_D22
Bits 30–28
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D22. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D23
Bits 27–25
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D23. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D24
Bits 24–22
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D24. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D25
Bits 21–19
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D25. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D26
Bits 18–16
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D26. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
Reserved
Bit 15
Reserved—This bit is reserved and should read 0.
i.MX21 Reference Manual, Rev. 3
8-10
Freescale Semiconductor
System Control
Table 8-7. Driving Strength Control Register 2 Description (continued)
Name
Description
Settings
DS_D27
Bits 14–12
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D27. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D28
Bits 11–9
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D28. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D29
Bits 8–6
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D29. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D30
Bits 5–3
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D30. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D31
Bits 2–0
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D31. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
8.1.8
Driving Strength Control Register 3
The Driving Strength Control Register 3 (DSCR3) controls the driving force parameters of the fast I/O
signals in the i.MX21. Descriptions of the register settings appear in Table 8-8.
DSCR3
BIT
TYPE
Driving Strength Control Register 3
31
30
r
0
0
29
28
27
26
25
24
23
Addr
0x10027828
22
21
20
19
18
17
DS_D12
DS_D13
DS_D14
DS_D15
DS_D16
rw
rw
rw
rw
rw
0
0
0
0
0
0
16
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
TYPE
15
14
r
0
0
13
12
11
10
9
8
DS_D17
DS_D18
DS_D19
DS_D20
DS_D21
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
8-11
System Control
Table 8-8. Driving Strength Control Register 3 Description
Name
Description
Settings
Reserved
Bit 31
Reserved—This bit is reserved and should read 0.
DS_D12
Bits 30–28
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D12.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D13
Bits 27–25
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D13.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D14
Bits 24–22
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D14.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D15
Bits 21–19
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D15.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D16
Bits 18–16
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D16.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
Reserved
Bit 15
Reserved—This bit is reserved and should read 0.
DS_D17
Bits 14–12
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D17.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D18
Bits 11–9
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D18.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D19
Bits 8–6
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D19.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D20
Bits 5–3
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D20.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D21
Bits 2–0
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D21.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
i.MX21 Reference Manual, Rev. 3
8-12
Freescale Semiconductor
System Control
8.1.9
Driving Strength Control Register 4
The Driving Strength Control Register 4 (DSCR4) controls the driving force parameters of the fast I/O
signals in the i.MX21. Descriptions of the register settings appear in Table 8-9.
DSCR4
BIT
TYPE
Driving Strength Control Register 4
31
30
r
0
0
29
28
27
26
25
24
23
Addr
0x1002782C
22
21
20
19
18
17
DS_D2
DS_D3
DS_D4
DS_D5
DS_D6
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
16
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
TYPE
15
14
r
0
0
13
12
11
10
9
8
7
DS_D7
DS_D8
DS_D9
DS_D10
DS_D11
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 8-9. Driving Strength Control Register 4 Description
Name
Description
Settings
Reserved
Bits 31
Reserved—This bit is reserved and should read 0.
DS_D2
Bits 30–28
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D2.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D3
Bits 27–25
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D3.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D4
Bits 24–22
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D4.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D5
Bits 21–19
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D5.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D6
Bits 18–16
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D6.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
Reserved
Bits 15
Reserved—This bit is reserved and should read 0.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
8-13
System Control
Table 8-9. Driving Strength Control Register 4 Description (continued)
Name
Description
Settings
DS_D7
Bits 14–12
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D7.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D8
Bits 11–9
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D8.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D9
Bits 8–6
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D9.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D10
Bits 5–3
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D10.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D11
Bits 2–0
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin D11.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
8.1.10
Driving Strength Control Register 5
The Driving Strength Control Register 5 (DSCR5) controls the driving force parameters of the fast I/O
signals in the i.MX21. Descriptions of the register settings appear in Table 8-10.
DSCR5
BIT
TYPE
Driving Strength Control Register 5
31
30
r
0
0
29
28
27
26
25
24
23
Addr
0x10027830
22
21
20
19
18
17
16
DS_A18
DS_A19
DS_A20
DS_A21_NFIO11
DS_A22_NFIO12
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
DS_A23_NFIO13
TYPE
0
0
10
9
8
DS_A24_NFIO14 DS_A25_NFIO15
rw
r
0
11
rw
0
0
0
rw
0
0
0
0
0
DS_D0
DS_D1
rw
rw
0
0
0
0
0
RESET
0x0000
i.MX21 Reference Manual, Rev. 3
8-14
Freescale Semiconductor
System Control
Table 8-10. Driving Strength Control Register 5 Description
Name
Description
Settings
Reserved
Bit 31
Reserved—This bit is reserved and should read 0.
DS_A18
Bits 30–28
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on 000 = 3.5 mA
pin A18.
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A19
Bits 27–25
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on 000 = 3.5 mA
pin A19.
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A20
Bits 24–22
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on 000 = 3.5 mA
pin A20.
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A21_NFIO11
Bits 21–19
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on 000 = 3.5 mA
pin A21_NFIO11.
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A22_NFIO12
Bits 18–16
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on 000 = 3.5 mA
pin A22_NFIO12.
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
Reserved
Bit 15
Reserved—This bit is reserved and should read 0.
DS_A23_NFIO13
Bits 14–12
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on 000 = 3.5 mA
pin A23_NFIO13.
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A24_NFIO14
Bits 11–9
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on 000 = 3.5 mA
pin A24_NFIO14.
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A25_NFIO15
Bits 8–6
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on 000 = 3.5 mA
pin A25_NFIO15.
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D0
Bits 5–3
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on 000 = 3.5 mA
pin D0.
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_D1
Bits 2–0
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on 000 = 3.5 mA
pin D1.
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
8-15
System Control
8.1.11
Driving Strength Control Register 6
The Driving Strength Control Register 6 (DSCR6) controls the driving force parameters of the fast I/O
signals in the i.MX21. Descriptions of the register settings appear in Table 8-11.
DSCR6
BIT
TYPE
Driving Strength Control Register 6
31
30
r
0
0
29
28
27
26
25
24
23
Addr
0x10027834
22
21
20
19
18
17
DS_A8
DS_A9
DS_A10
DS_A11
DS_A12
rw
rw
rw
rw
rw
0
0
0
0
0
0
16
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
TYPE
15
14
12
11
10
9
8
DS_A13_NFIO8
DS_A14_NFIO9
DS_A15_NFIO10
DS_A16
DS_A17
rw
rw
rw
rw
rw
r
0
13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 8-11. Driving Strength Control Register 6 Description
Name
Description
Settings
Reserved
Bit 31
Reserved—This bit is reserved and should read 0.
DS_A8
Bits 30–28
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin A8. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A9
Bits 27–25
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin A9. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A10
Bits 24–22
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
A10.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A11
Bits 21–19
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
A11.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A12
Bits 18–16
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
A12.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
Reserved
Bit 15
Reserved—This bit is reserved and should read 0.
i.MX21 Reference Manual, Rev. 3
8-16
Freescale Semiconductor
System Control
Table 8-11. Driving Strength Control Register 6 Description (continued)
Name
Description
Settings
DS_A13_NFIO8
Bits 14–12
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
A13_NFIO8.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A14_NFIO9
Bits 11–9
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
A14_NFIO9.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A15_NFIO10
Bits 8–6
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
A15_NFIO10.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A16
Bits 5–3
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
A16.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A17
Bits 2–0
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
A17.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
8.1.12
Driving Strength Control Register 7
The Driving Strength Control Register 7 (DSCR7) controls the driving force parameters of the fast I/O
signals in the i.MX21. Descriptions of the register settings appear in Table 8-12.
DSCR7
BIT
TYPE
Driving Strength Control Register 7
31
30
r
0
0
29
28
27
26
25
24
23
Addr
0x10027838
22
21
20
19
18
17
DS_BCLK
DS_OE_B
DS_A0
DS_A1
DS_A2
rw
rw
rw
rw
rw
0
0
0
0
0
0
16
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
TYPE
15
14
r
0
0
13
12
11
10
9
8
DS_A3
DS_A4
DS_A5
DS_A6
DS_A7
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
8-17
System Control
Table 8-12. Driving Strength Control Register 7 Description
Name
Description
Settings
Reserved
Bits 31
Reserved—This bit is reserved and should read 0.
DS_BCLK
Bits 30–28
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin BCLK 000 = 3.5 mA
(EIM Burst Clock).
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_OE_B
Bits 27–25
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin OE_B. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A0
Bits 24–22
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin A0.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A1
Bits 21–19
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin A1.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A2
Bits 18–16
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin A2.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
Reserved
Bit 15
Reserved—This bit is reserved and should read 0.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A3
Bits 14–12
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin A3.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A4
Bits 11–9
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin A4.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A5
Bits 8–6
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin A5.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A6
Bits 5–3
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin A6.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_A7
Bits 2–0
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin A7.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
i.MX21 Reference Manual, Rev. 3
8-18
Freescale Semiconductor
System Control
8.1.13
Driving Strength Control Register 8
The Driving Strength Control Register 8 (DSCR8) controls the driving force parameters of the fast I/O
signals in the i.MX21 Driving Strength Control Register. Descriptions of the register settings appear in
Table 8-13.
DSCR8
BIT
TYPE
Driving Strength Control Register 8
31
30
28
27
26
25
24
23
22
21
20
19
18
17
16
DS_CS0_B
DS_CS1_B
DS_CS2_B
DS_CS3_B
DS_CS4_B
rw
rw
rw
rw
rw
r
0
29
Addr
0x1002783C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
TYPE
15
14
r
0
0
13
12
11
10
9
8
DS_CS5_B
DS_EB3_B
DS_EB2_B
DS_EB1_B
DS_EB0_B
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 8-13. Driving Strength Control Register 8 Description
Name
Description
Settings
Reserved
Bit 31
Reserved—This bit is reserved and should read 0.
DS_CS0_B
Bits 30–28
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin CS0_B.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_CS1_B
Bits 27–25
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin CS1_B.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_CS2_B
Bits 24–22
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin CS2_B.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_CS3_B
Bits 21–19
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin CS3_B.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_CS4_B
Bits 18–16
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin CS4_B.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
8-19
System Control
Table 8-13. Driving Strength Control Register 8 Description (continued)
Name
Description
Settings
Reserved
Bit 15
Reserved—This bit is reserved and should read 0.
DS_CS5_B
Bits 14–12
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin CS5_B.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_EB3_B
Bits 11–9
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin EB3_B.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_EB2_B
Bits 8–6
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin EB2_B.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_EB1_B
Bits 5–3
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin EB1_B.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_EB0_B
Bits 2–0
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin EB0_B.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
8.1.14
Driving Strength Control Register 9
The Driving Strength Control Register 9 (DSCR9) controls the driving force parameters of the fast I/O
signals in the i.MX21 Driving Strength Control Register. Descriptions of the register settings appear in
Table 8-14.
DSCR9
BIT
TYPE
Driving Strength Control Register 9
31
30
r
0
0
29
28
27
26
25
24
23
DS_CAS_B
DS_RAS_B
DS_SDCLK
rw
rw
rw
0
0
0
0
0
0
Addr
0x10027840
22
21
20
19
18
r
17
16
r
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
TYPE
15
14
r
0
0
13
12
11
10
9
8
DS_MA10
DS_MA11
DS_RW_B
DS_LBA_B
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
r
0
0
0
0
RESET
0x0000
i.MX21 Reference Manual, Rev. 3
8-20
Freescale Semiconductor
System Control
Table 8-14. Driving Strength Control Register 9 Description
Name
Description
Settings
Reserved
Bit 31
Reserved—This bit is reserved and should read 0.
DS_CAS_B
Bits 30–28
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
CAS_B.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_RAS_B
Bits 27–25
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
RAS_B.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_SDCLK
Bits 24–22
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
SDCLK.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
Reserved
Bits 21–15
Reserved—These bits are reserved and should read 0.
DS_MA10
Bits 14–12
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
MA10.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_MA11
Bits 11–9
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
MA11.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_RW_B
Bits 8–6
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
RW_B.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_LBA_B
Bits 5–3
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
LBA_B.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
Reserved
Bits 2–0
Reserved—These bits are reserved and should read 0.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
8-21
System Control
8.1.15
Driving Strength Control Register 10
The Driving Strength Control Register 10 (DSCR10) controls the driving force parameters of the fast I/O
signals in the i.MX21 Driving Strength Control Register. Descriptions of the register settings appear in
Table 8-15.
DSCR10
Driving Strength Control Register 10
BIT
31
TYPE
r
RESET
BIT
TYPE
RESET
0
30
29
28
27
26
25
24
23
Addr
0x10027844
22
21
20
19
18
17
16
DS_NFIO3
DS_NFIO4
DS_NFIO5
DS_NFIO6
DS_NFIO7
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
7
6
0
0
0
0
5
4
3
2
0
0
1
0
0x0000
15
14
r
0
0
13
12
11
10
9
8
DS_CLKO
DS_PF16
DS_SDCKE1
DS_SDCKE0
DS_SDWE_B
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 8-15. Driving Strength Control Register 10 Description
Name
Description
Settings
Reserved
Bit 31
Reserved—This bit is reserved and should read 0.
DS_NFIO3
Bits 30–28
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin NFIO3. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_NFIO4
Bits 27–25
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin NFIO4. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_NFIO5
Bits 24–22
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin NFIO5. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_NFIO6
Bits 21–19
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin NFIO6. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_NFIO7
Bits 18–16
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin NFIO7. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
Reserved
Bit 15
Reserved—This bit is reserved and should read 0.
i.MX21 Reference Manual, Rev. 3
8-22
Freescale Semiconductor
System Control
Table 8-15. Driving Strength Control Register 10 Description (continued)
Name
Description
Settings
DS_CLKO
Bits 14–12
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin CLKO. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_PF16
Bits 11–9
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin PF16. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_SDCKE1
Bits 8–6
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
SDCKE1.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_SDCKE0
Bits 5–3
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
SDCKE0.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_SDWE_B
Bits 2–0
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin
SDWE_B.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
8.1.16
Driving Strength Control Register 11
The Driving Strength Control Register 11 (DSCR11) controls the driving force parameters of the fast I/O
signals in the i.MX21 Driving Strength Control Register. Descriptions of the register settings appear in
Table 8-6.
DSCR11
BIT
TYPE
Driving Strength Control Register 11
31
30
r
0
0
29
28
27
26
25
24
23
Addr
0x10027848
22
21
20
19
18
17
16
DS_NFRB
DS_NFCE_B
DS_NFWP_B
DS_NFCLE
DS_NFALE
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
TYPE
15
14
12
11
10
9
8
DS_NFRE_B
DS_NFWE_B
DS_NFIO0
DS_NFIO1
DS_NFIO2
rw
rw
rw
rw
rw
r
0
13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
8-23
System Control
Table 8-16.
Name
Description
Settings
Reserved
Bit 31
Reserved—This bit is reserved and should read 0.
DS_NFRB
Bits 30–28
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin NFRB.
DS_NFCE_B
Bits 27–25
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin NFCE_B. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_NFWP_B
Bits 24–22
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin NFWP_B. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_NFCLE
Bits 21–19
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin NFCLE.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_NFALE
Bits 18–16
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin NFALE.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
Reserved
Bit 15
Reserved—This bit is reserved and should read 0.
DS_NFRE_B
Bits 14–12
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin NFRE_B. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_NFWE_B
Bits 11–9
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin NFWE_B. 000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_NFIO0
Bits 8–6
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin NFIO0.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_NFIO1
Bits 5–3
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin NFIO1.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_NFIO2
Bits 2–0
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin NFIO2.
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
000 = 3.5 mA
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
i.MX21 Reference Manual, Rev. 3
8-24
Freescale Semiconductor
System Control
8.1.17
Driving Strength Control Register 12
The Driving Strength Control Register 12 (DSCR12) controls the driving force parameters of the fast I/O
signals in the i.MX21 Driving Strength Control Register. Descriptions of the register settings appear in
Table 8-17.
DSCR12
Driving Strength Control Register 12
BIT
31
TYPE
r
30
29
28
27
r
0
0
0
26
25
24
r
0
0
0
23
Addr
0x1002784C
22
21
rw
0
0
20
19
18
17
r
16
r
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
TYPE
14
13
12
11
r
r
0
0
0
10
9
8
DS_LSCLK
DS_CSI_MCLK
DS_CSI_PIXCLK
rw
rw
rw
r
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 8-17. Driving Strength Control Register 12 Description
Name
Description
Settings
Reserved
Bits 31–9
Reserved—These bits are reserved and should read 0.
DS_LSCLK
Bits 8–6
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin 000 = 3.5 mA
LSCLK.
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_CSI_MCLK
Bits 5–3
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin 000 = 3.5 mA
CSI_MCLK.
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
DS_CSI_PIXCLK
Bits 2–0
Driving Strength Fast I/O—Controls the driving strength of fast I/O signals on pin 000 = 3.5 mA
CSI_PIXCLK.
001 = 4.5 mA
011 = 5.5 mA
111 = 6.5 mA
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
8-25
System Control
8.1.18
Priority Control and Select Register
The Priority Control and Select Register (PCSR) consist of the slave alternate context priority select to the
ARM9 platform. Descriptions of the register settings appear in Table 8-18.
PCSR
BIT
Priority Control and Select Register Description
31
30
29
28
27
26
25
24
23
22
21
Addr
0x10027850
20
19
18
17
16
s3_
s2_
s1_
s0_
ampr_sel ampr_sel ampr_sel ampr_sel
TYPE
RESE
T
0
BIT
15
0
0
0
0
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
0
0
0
0
1
1
0
0x0000
14
13
12
11
TYPE
RESE
T
rw
r
10
9
8
7
6
r
0
0
0
0
0
0
0
0
0
0
0x0003
Table 8-18. Global Peripheral Control Register Description
Name
Description
Settings
Reserved
Bits 31–20
Reserved—These bits are reserved and should read 0.
s3_ampr_sel
s2_ampr_sel
s1_ampr_sel
s0_ampr_sel
Bits 19–16
Slave Alternate Context Priority Select—Inputs to the ARM9 0 = Priority determination and control is made
platform to select the priority determination and control source
by regular registers.
for the appropriate slave port. (Note s0 is the primary AHB and 1 = Priority determination and control is made
does not come out of the ARM9 platform.
by alternate registers set in the Crossbar
switch.
Reserved
Bits 15–0
Reserved—These bits are reserved and should read 0.
8.2
System Boot Mode Selection
The operational system boot mode of the i.MX21 upon POR reset is determined by the configuration of
the four external input pins, BOOT[3:0]. The settings of these pins control where the system is boot from
and the memory port size.
NOTE
The BOOT pins must not change once the i.MX21 is out of POR reset. For
proper operation, BOOT[3] must always be tied to VSS.
i.MX21 Reference Manual, Rev. 3
8-26
Freescale Semiconductor
System Control
Table 8-19. System Boot Mode Selection
Inputs
BOOT[3:0]
Output Signals Active Device
Boot Address
0000
iROM (Bootstrap USB/UART)
0x00000030
0001
iROM (Bootstrap USB/UART)
0x00000030
0010
iROM (8-bit 2 Kbyte NAND Flash)
0xDF003000
0011
iROM (16-bit 2 Kbyte NAND Flash)
0xDF003000
0100
iROM (16-bit 512 byte NAND Flash)
0xDF003000
0101
iROM (16-bit CS0 at D[15:0] (NOR Flash))
0xC8000000
0110
iROM (32-bit CS0 at D[31:0] (NOR Flash))
0xC8000000
0111
iROM (8-bit 512 byte NAND Flash)
0xDF003000
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
8-27
System Control
i.MX21 Reference Manual, Rev. 3
8-28
Freescale Semiconductor
Chapter 9
Internal ROM, System Boot Manager
This chapter describes the system boot up sequence of the i.MX21 processor. The system bootup is
designed according to the configuration of the external BOOT pins, and hence sub-divided into
Boot-external, Boot-internal, In-Factory test, Bootstrap mode and Normal flash bootup modes.
The i.MX21 processor comes with a 24 Kbyte internal ROM (iROM) which contains a System Boot
Manager to process the serial bootstrap operations according to all possible scenarios from power-up. The
iROM is controlled by various pins and laser fuse configurations, for details please refer to Chapter 8,
“System Control.”
The system Boot Manager allows multiple-layers of boot-up, for example, NAND Flash boot-up. Different
from NOR Flash, NAND Flash requires setting up the file system and caching system to access inner
memory content. Before the file system is setup, only the first page of content is accessible (2–16 Kbytes).
To interface with an external terminal such as a PC, a bootstrap program with a proprietary protocol is
designed to interact with the external computer through the use of a serial channel UART, or USB. The
bootstrap program must be entered when the corresponding boot pins are selected (please refer to
Chapter 8, “System Control,” for details of the pin selection). When programmed in this manner, the
system will automatically detect the existence of a serial channel during power-up.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
9-1
Internal ROM, System Boot Manager
Reset
Code Location Key:
iROM
RAM
BOOT[3:0]=”1xxx”
Factory test
purposes only
Yes
Factory
Test
?
No
Re-Flash/
Flash ROM
No
Bootstrap
Mode
?
Yes
NAND
Download
RAM App
(USB/RS232)
Flash
No
?
Yes
NAND Startup
Code
RAM App
Flash App
Figure 9-1. iROM Boot Flow Diagram (Simplified)
9.1
Bootstrap Mode Operation
The bootstrap program is a program that resides in the internal ROM of i.MX21. It is activated when the
BOOT[3:0] selection pins are configured as Bootstrap Mode. The program handles the commands from
either the USB or UART1 to establish a channel to interface with the i.MX21 processor’s hardware and an
external machine such as a PC. The program downloads a binary image to memory so as to execute in run
time or perform Flash update.
9.1.1
UART/USB Configuration
The configuration for RS 232 is using baud rate 115200, 8 Data bits, No Parity, 1 Stop bits and No Flow
Control. The Configuration for USB is for Control Endpoint 0 with Max Packet Size equal 8 byte. Bulk
IN at Endpoint 2 with Max Packet Size equal 64 bytes, Bulk OUT at Endpoint 1 with Max Packet Size
equal 64 bytes.
9.1.2
Enter Bootstrap Mode Configuration
The i.MX21 processor enters bootstrap mode under the following conditions:
1. BOOT[3:0] is selected for bootstrap mode
i.MX21 Reference Manual, Rev. 3
9-2
Freescale Semiconductor
Internal ROM, System Boot Manager
9.1.3
Bootstrap Flow
The overall flow of the bootstrap program is shown in Figure 9-2.
When the USB is selected to be used,
the PC must be powered up and the
USB cable must be connected before
the i.MX21 is powered up.
Enter Bootstrap Mode
UART & USB Enable
Yes
USB?
No
Complete Enumeration
Synchronizing between
PC USB Host & i.MX21
Synchronization
Synchronizing between
PC Serial Port & i.MX21
Operation
Write Register
Write Register
i.MX 21
Memory
Initialization
Unlimited Access (all registers are accessible)
by WRITE COMMAND & RESPONSE B
Init Memory
Completed?
No
Yes
Download Binary to Memory
i.MX21 => USB Host
to indicate the End
Download
Operation
Bootstrap End
Indication Operation
Exit from Bootstrap enter iROM
Figure 9-2. Flow Diagram for Bootstrap Mode
9.1.3.1
Bootstrap Protocol and Definition
In this section, bootstrap protocol and the command, response definition is defined. For the i.MX21
processor’s boot-up sequence, please refer to System Boot.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
9-3
Internal ROM, System Boot Manager
9.1.3.1.1
Synchronization Operation
When bootstrap is first entered, the status of the iROM can be obtained by issuing the command shown in
Figure 9-3.
PC to i.MX21:
SYNC COMMAND
i.MX21 to PC:
RESPONSE
Figure 9-3. iROM Status Command
The SYNC COMMAND is composed of 16 bytes using the format shown in Table 9-1. The RESPONSE
is 4 bytes long and indicates that there is communication with the processor.
:
Table 9-1. Synch Command Definition
Header
(2 bytes)
Address
(4 bytes)
Format
(1 byte)
Bytecount
(4 bytes)
Data
(4 bytes)
End
(1 byte)
0505
00000000
00
00000000
00000000
00
9.1.3.1.2
Write Register Operation
To write to a register through bootstrap, requires a specific protocol. After the command is sent from the
PC to the i.MX21 processor, two responses are returned from i.MX21. The second response, RESPONSE
C, is used to indicate whether the write operation is successful.
PC to i.MX21:
WRITE COMMAND
i.MX21 to PC:
RESPONSE C
RESPONSE B
Figure 9-4. Write Register Command
WRITE COMMAND is 16 bytes long using the format shown in Table 9-2.
Table 9-2. Write Register Command Definition
Header
(2 bytes)
Address
(4 bytes)
Format
(1 byte)
Bytecount
(4 bytes)
Data
(4 bytes)
End
(1 byte)
0202
Address to be written
Format to be written
(08: byte access
10: halfword access
20: word access)
00
Data to be written to
the register
00
RESPONSE B indicates the type of silicon. It is composed of 8 bytes using the format shown in Table 9-3.
Table 9-3. Response B Definition
Development part
Byte 0
Byte 1
Byte 2
Byte 3
56
78
78
56
RESPONSE C indicates the success of a write operation as shown in Table 9-4.
i.MX21 Reference Manual, Rev. 3
9-4
Freescale Semiconductor
Internal ROM, System Boot Manager
Table 9-4. Response C Definition
9.1.3.1.3
Byte 0
Byte 1
Byte 2
Byte 3
12
8A
8A
12
Download Operation
To download a binary file to the memory, after the memory is initialized. The following command can be
issued:
PC to i.MX21:
DOWNLOAD COMMAND
i.MX21 to PC:
BINARY DATA
RESPONSE B
Figure 9-5. Download Command
The DOWNLOAD COMMAND is 16 bytes long using the formats shown in Table 9-5.
Table 9-5. Download Command Definition
Header
(2 bytes)
Address
(4 Bytes)
Format
(1 byte)
Bytecount
(4 bytes)
Data
(4 bytes)
End
(1 byte)
Image file
0404
Start address where the binary
data is to be downloaded
00
Number of byte to
be written in Hex
(max 0x1F0000)
Start address in memory
where data is to be written
00
Image file
0404
Start address where the binary
data is to be downloaded
00
Number of byte to
be written in Hex
Start address in memory
where data is to be written
AA
RESPONSE B is 8 bytes long using the format shown in Table 9-6.
Table 9-6. Response B Silicon Type Definition
Development part
BYTE 0
BYTE 1
BYTE 2
BYTE 3
56
78
78
56
After the RESPONSE B is received by the i.MX21 processor, the attached PC can start to download the
binary data to i.MX21 until all the BYTECOUNT is downloaded. Each time the Image File is downloaded
through HEADER (0404), the maximum data to be download is 0x1F0000. Thus, if the Image File size is
greater then 0x1F0000, it will send the command repeatedly with END (0x00). After all the data is
downloaded, PC must send a DOWNLOAD command with END (AA) to the target execution address.
9.1.3.1.4
Bootstrap End Indication Operation
After all the bootstrap operations are completed, the i.MX21 processor will send RESPONSE D to PC after
the Application Pointer was sent to indicate bootstrap was completed. After RESPONSE D is complete,
the i.MX21 processor executes the image.
i.MX21 to PC:
RESPONSE D
Figure 9-6. Bootstrap End Indication Operation Diagram
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
9-5
Internal ROM, System Boot Manager
RESPONSE D is indicates the success of the write operation as shown in Table 9-7.
Table 9-7. Bootstrap End Indication Operation Diagram
BYTE 0
BYTE 1
BYTE 2
BYTE 3
88
88
88
88
i.MX21 Reference Manual, Rev. 3
9-6
Freescale Semiconductor
Chapter 10
Multi-layer AHB Crossbar Switch (MAX)
This section provides an overview of the MAX (Multi-Layer AHB Crossbar Switch). The purpose of the
MAX is to concurrently support simultaneous connections between 6 master ports and 4 slave ports.
The features of MAX include the following:
• Supports concurrent transfers between 6 master ports and 4 slave ports. The MAX has the ability
to gain control of all the slave ports and prevent any masters from making accesses to the slave
ports.
• The MAX can put each slave port into a low-power park mode so that a slave port will not dissipate
any power transitioning address, control, or data signals when not being actively accessed by a
master port.
• Each slave port can also support multiple master priority schemes.
• The MAX allows for concurrent transactions to occur from any master port to any slave port. It is
possible for all master ports and slave ports to be in use at the same time as a result of independent
master requests. If a slave port is simultaneously requested by more than one master port,
arbitration logic selects the higher priority master and grants it ownership of the slave port. All
other masters requesting that slave port are stalled until the higher priority master completes its
transactions.
10.1
Limitations
The MAX routes bus transactions initiated on the master ports to the appropriate slave ports. There is no
provision included to route transactions initiated on the slave ports to other slave ports or to master ports.
Simply put, the slave ports do not support the bus request/bus grant protocol, the MAX assumes it is the
sole master of each slave port.
10.2
General Operation
When a master makes an access to the MAX the access will be immediately taken by the MAX. If the
targeted slave port of the access is available then the access will be immediately presented on the slave
port. It is possible to make single clock (zero wait state) accesses through the MAX. If the targeted slave
port of the access is busy or parked on a different master port the requesting master will simply see wait
states inserted until the targeted slave port can service the master’s request. The latency in servicing the
request will depend on each master’s priority level and the responding peripheral’s access time.
Since the MAX appears to be just another slave to the master device, the master device will have no
knowledge of whether or not it actually owns the slave port it is targeting. While the master does not have
control of the slave port it is targeting it will simply be wait stated.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
10-1
Multi-layer AHB Crossbar Switch (MAX)
A master will be given control of the targeted slave port only after a previous access to a different slave
port has completed, regardless of its priority on the newly targeted slave port. This prevents deadlock from
occurring when a master has an outstanding request to one slave port that has a long response time, has a
pending access to a different slave port, and a lower priority master is also making a request to the same
slave port as the pending access of the higher priority master.
Once the master has control of the slave port it is targeting the master will remain in control of that slave
port until it gives up the slave port by running an IDLE cycle or by leaving that slave port for its next
access. The master could also lose control of the slave port if another higher priority master makes a
request to the slave port; however, if the master is running a locked or fixed length burst transfer it will
retain control of the slave port until that transfer is completed. Based on the AULB bit in the MGPCR
(Master General Purpose Control Register) the master will either retain control of the slave port when
doing undefined length incrementing burst transfers or will lose the bus to a higher priority master.
The MAX will terminate all master IDLE transfers (as opposed to allowing the termination to come from
one of the slave busses). Additionally, when no master is requesting access to a slave port the MAX will
drive IDLE transfers onto the slave bus. When a slave bus is being IDLEd by the MAX it can park the
slave port on the master port indicated by the PARK bits in the SGPCR (Slave General Purpose Control
Register) or ASGPCR (Alternate SGPCR). This can be done in an attempt to save the initial clock of
arbitration delay that would otherwise be seen if the master had to arbitrate to gain control of the slave port.
The slave port can also be put into low power park mode in an attempt to save power.
10.3
Programming Model
This section provides the register programming information for the MAX registers.
There are four registers that reside in each slave port of the MAX and one register that resides in each
master port of the MAX. These registers are IP bus compliant registers. Read and write transfers both
require two IP bus clock cycles. The registers can only be read from and written to in supervisor mode.
Additionally, these registers can only be read from or written to by 32-bit accesses.
CAUTION
The MAX registers are fully decoded and an error response is returned if an
unimplemented location is accessed within the MAX.
The slave registers also feature a bit, which when written with a 1, will prevent the registers from being
written to again. The registers will still be readable, but future write attempts will have no effect on the
registers and will be terminated with an error response.
10.3.1
Master Priority Register
The Master Priority Register (MPR) sets the priority of each master port on a per slave port basis and
resides in each slave port.
The Master Priority Register can only be accessed in supervisor mode with 32-bit accesses. Once the RO
(Read Only) bit has been set in the slave General Purpose Control Register the Master Priority Register
can only be read from, attempts to write to it will have no effect on the MPR and result in an error response.
i.MX21 Reference Manual, Rev. 3
10-2
Freescale Semiconductor
Multi-layer AHB Crossbar Switch (MAX)
Additionally, no two available master ports may be programmed with the same priority level. Attempts to
program two or more available masters with the same priority level will result in an error response and the
MPR will not be updated.
MPR0
MPR1
MPR2
MPR3
BIT
Master Priority Register for Slave Port 0
Master Priority Register for Slave Port 1
Master Priority Register for Slave Port 2
Master Priority Register for Slave Port 3
31
30
29
28
27
26
25
24
23
Addr
0x1003_F000
0x1003_F100
0x1003_F200
0x1003_F300
22
NAME
21
20
19
18
MSTR_5
17
16
MSTR_4
TYPE
r
rw
rw
rw
r
rw
rw
rw
r
rw
rw
rw
r
rw
rw
rw
RESET
0
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
MSTR_3
MSTR_2
MSTR_1
MSTR_0
TYPE
r
rw
rw
rw
r
rw
rw
rw
r
rw
rw
rw
r
rw
rw
rw
RESET
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
Table 10-1. Master Priority Register Description
Name
Description
Settings
Reserved
Bit 31–23
Reserved—These bits are reserved for future expansion. These are read as zero and should be written with zero
for upward compatibility.
MSTR_5
Bits 22–20
Master 5 Priority—These bits set the arbitration priority for master
port 5 on the associated slave port. These bits are initialized by
hardware reset. The reset value is 101.
Reserved
Bit 19
Reserved—This bit is reserved for future expansion. It is read as zero and should be written with zero for upward
compatibility.
MSTR_4
Bits 18–16
Master 4 Priority—These bits set the arbitration priority for master
port 4 on the associated slave port. These bits are initialized by
hardware reset. The reset value is 100.
Reserved
Bit 15
Reserved—This bit is reserved for future expansion. It is read as zero and should be written with zero for upward
compatibility.
MSTR_3
Bits 14–12
Master 3 Priority—These bits set the arbitration priority for master
port 3 on the associated slave port. These bits are initialized by
hardware reset. The reset value is 011.
Reserved
Bit 11
Reserved—This bit is reserved for future expansion. It is read as zero and should be written with zero for upward
compatibility.
MSTR_2
Bits 10–8
Master 2 Priority—These bits set the arbitration priority for master
port 2 on the associated slave port. These bits are initialized by
hardware reset. The reset value is 010.
000 = This master has the highest priority
when accessing the slave port.
111 = This master has the lowest priority
when accessing the slave port.
000 = This master has the highest priority
when accessing the slave port.
111 = This master has the lowest priority
when accessing the slave port.
000 = This master has the highest priority
when accessing the slave port.
111 = This master has the lowest priority
when accessing the slave port.
000 = This master has the highest priority
when accessing the slave port.
111 = This master has the lowest priority
when accessing the slave port.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
10-3
Multi-layer AHB Crossbar Switch (MAX)
Table 10-1. Master Priority Register Description (continued)
Name
Description
Settings
Reserved
Bit 7
Reserved—This bit is reserved for future expansion. It is read as zero and should be written with zero for upward
compatibility.
MSTR_1
Bits 6–4
Master 1 Priority—These bits set the arbitration priority for master
port 1 on the associated slave port. These bits are initialized by
hardware reset. The reset value is 001.
Reserved
Bit 3
Reserved—This bit is reserved for future expansion. It is read as zero and should be written with zero for upward
compatibility.
MSTR_0
Bits 2–0
Master 0 Priority—These bits set the arbitration priority for master
port 0 on the associated slave port. These bits are initialized by
hardware reset. The reset value is 000.
10.3.2
Alternate Master Priority Register
000 = This master has the highest priority
when accessing the slave port.
111 = This master has the lowest priority
when accessing the slave port.
000 = This master has the highest priority
when accessing the slave port.
111 = This master has the lowest priority
when accessing the slave port.
The Alternate Master Priority Register (AMPR) sets the alternate priority of each master port on a per slave
port basis.
The AMPR has identical function as the MPR. The purpose of the AMPR is to allow the user to set up an
alternate set of priorities in the event they want to do some sort of context switching. A hardware input to
the MAX controls (on a slave port by slave port basis) whether or not the slave port uses the MPR or the
AMPR.
AMPR0
AMPR1
AMPR2
AMPR3
BIT
Alternate Master Priority Register for Slave Port 0
Alternate Master Priority Register for Slave Port 1
Alternate Master Priority Register for Slave Port 2
Alternate Master Priority Register for Slave Port 3
31
30
29
28
27
26
25
24
23
22
NAME
21
0x1003_F004
0x1003_F104
0x1003_F204
0x1003_F304
20
19
18
MSTR_5
17
16
MSTR_4
TYPE
r
rw
rw
rw
r
rw
rw
rw
r
rw
rw
rw
r
rw
rw
rw
RESET
0
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
MSTR_3
MSTR_2
MSTR_1
MSTR_0
TYPE
r
rw
rw
rw
r
rw
rw
rw
r
rw
rw
rw
r
rw
rw
rw
RESET
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
Please reference Table 10-1 for descriptions of bit fields in the AMPR as they are identical.
The Alternate Master Priority Register can only be accessed in supervisor mode with 32-bit accesses. Once
the RO (Read Only) bit has been set in the General Purpose Control Register the Alternate Master Priority
Register can only be read from, attempts to write to it will have no effect on the AMPR and result in an
error response.
i.MX21 Reference Manual, Rev. 3
10-4
Freescale Semiconductor
Multi-layer AHB Crossbar Switch (MAX)
Additionally, no two available master ports may be programmed with the same priority level. Attempts to
program two or more available masters with the same priority level will result in an error response and the
AMPR will not be updated.
10.3.3
Slave General Purpose Control Register
The Slave General Purpose Control Register (SGPCR) controls several features of each slave port.
The Read Only (RO) bit will prevent any registers associated with this slave port from being written to
once set. This bit may be written with 0 as many times as the user desires, but once it is written to a 1 only
a reset condition will allow it to be written again.
The Halt Low Priority (HLP) bit will set the priority of the max_halt_request input to the lowest
possible priority for initial arbitration of the slave ports. By default it is the highest priority. Please note,
setting this bit will not effect the max_halt_request from attaining highest priority once it has control
of the slave ports.
The PCTL bits determine how the slave port will park when no master is actively making a request. The
available options are to park on the master defined by the PARK bits, park on the last master to use the
slave port, or go into a low-power park mode which will force all the outputs of the slave port to inactive
states when no master is requesting an access. The low power park feature can result in an overall power
savings if a the slave port is not saturated; however, it will force an extra clock of latency whenever any
master tries to access it when it is not in use because it will not be parked on any master.
The PARK bits determine which master the slave will park on when no master is making an active request
and the max_halt_request input is negated. Please use caution to only select master ports that are
actually present in the design. If the user programs the PARK bits to a master not present in the current
design implementation undefined behavior will result.
The SGPCR can only be accessed in supervisor mode with 32-bit accesses. After the RO (Read Only) bit
has been set in the SGPCR the SGPCR can only be read, attempts to write to it will have no effect on the
SGPCR and result in an error response.
SGPCR0
SGPCR1
SGPCR2
SGPCR3
Slave General Purpose Control Register for Slave Port 0
Slave General Purpose Control Register for Slave Port 1
Slave General Purpose Control Register for Slave Port 2
Slave General Purpose Control Register for Slave Port 3
BIT
31
30
NAME
RO
HLP
TYPE
rw
1
RESET
BIT
0x1003_F010
0x1003_F110
0x1003_F210
0x1003_F310
29
28
27
26
25
24
23
22
21
20
19
18
17
16
rw
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
ARB
PCTL
PARK
TYPE
r
r
r
r
r
r
rw
rw
r
r
rw
rw
r
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Once this bit is written to a 1 only hardware reset will return it to a 0.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
10-5
Multi-layer AHB Crossbar Switch (MAX)
Table 10-2. Slave General Purpose Control Register Description
Name
Description
Setting
RO
Bit 31
Read Only—This bit is used to force all of a slave port’s registers 0 = All this slave port’s registers can be written.
to be read only. Once written to 1 it can only be cleared by
1 = All this slave port’s registers are read only
hardware reset. This bit is initialized by hardware reset. The
and cannot be written (attempted writes
reset value is 0
have no effect and result in an error
response).
HLP
Bit 30
Halt Low Priority—This bit is used to set the initial arbitration
priority of the max_halt_request input. This bit is initialized by
hardware reset. The reset value is 0
Reserved
Bits 29–10
Reserved—These bits are reserved for future expansion. They are read as zero and should be written with zero
for upward compatibility.
ARB
Bits 9–8
Arbitration Mode—These bits are used to select the arbitration 00 Fixed Priority.
policy for the slave port. These bits are initialized by hardware
01 Round Robin (rotating) Priority.
reset. The reset value is 00
10 Reserved
11 Reserved
Reserved
Bits 7–6
Reserved—These bits are reserved for future expansion. They are read as zero and should be written with zero
for upward compatibility.
PCTL
Bits 5–4
Parking Control—These bits determine the parking control
used by this slave port.These bits are initialized by hardware
reset. The reset value is 00.
Reserved
Bit 3
Reserved—This bit is reserved for future expansion. It is read as zero and should be written with zero for upward
compatibility.
PARK
Bits 2–0
PARK—These bits are used to determine which master port this
slave port parks on when no masters are actively making
requests and the PCTL bits are set to 00. These bits are
initialized by hardware reset. The reset value is 000
10.3.4
Alternate Slave General Purpose Control Register
0 = The max_halt_request input has the highest
priority for arbitration on this slave port.
1 = The max_halt_request input has the lowest
initial priority for arbitration on this slave
port.
00 = When no master is making a request the
arbiter will park the slave port on the
master port defined by the PARK bit field.
01 = When no master is making a request the
arbiter will park the slave port on the last
master to be in control of the slave port.
10 = When no master is making a request the
arbiter will park the slave port on no
master and will drive all outputs to a
constant safe state.
11 = Reserved
000 = Park on Master Port 0
001 = Park on Master Port 1
010 = Park on Master Port 2
011 = Park on Master Port 3
100 = Park on Master Port 4
101 = Park on Master Port 5
11x = Reserved
The Alternate Slave General Purpose Control Register (ASGPCR) has identical function as the SGPCR
with the notable exception that it lacks the RO (Read Only) bit contained in the SGPCR. The purpose of
the ASGPCR is the same as the AMPR, to allow the user to set up an alternate set of general control fields
in the event they want to do some sort of context switching. A hardware input to the MAX controls (on a
slave port by slave port basis) whether or not the slave port uses the SGPCR or ASGPCR.
i.MX21 Reference Manual, Rev. 3
10-6
Freescale Semiconductor
Multi-layer AHB Crossbar Switch (MAX)
NOTE
The ASGPCR does not contain a RO (Read Only) bit. The RO bit in the
SGPCR has control over the ASGPCR’s ability to be written.
ASGPCR0
ASGPCR1
ASGPCR2
ASGPCR3
BIT
Alternate SGPCR for Slave Port 0
Alternate SGPCR for Slave Port 1
Alternate SGPCR for Slave Port 2
Alternate SGPCR for Slave Port 3
31
NAME
30
0x1003_F014
0x1003_F114
0x1003_F214
0x1003_F314
29
28
27
26
25
24
23
22
21
20
19
18
17
16
HLP
TYPE
r
rw
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
ARB
PCTL
PARK
TYPE
r
r
r
r
r
r
rw
rw
r
r
rw
rw
r
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Please reference Table 10-3 for descriptions of bit fields in the ASGPCR as they are identical except for
the RO bit.
The ASGPCR can only be accessed in supervisor mode with 32-bit accesses. Once the RO (Read Only)
bit has been set in the SGPCR the ASGPCR can only be read from, attempts to write to it will have no
effect on the ASGPCR and result in an error response.
10.3.5
Master General Purpose Control Register
The Master General Purpose Control Register (MGPCR) presently controls only whether the master’s
undefined length burst accesses will be allowed to complete uninterrupted or whether they can be broken
by requests from higher priority masters.
The AULB (Arbitrate on Undefined Length Bursts) bit determines whether the MAX will arbitrate away
the slave port the master owns when the master is performing undefined length burst accesses. Arbitration
occurs transparently and masters who lose control only see that their target slave is not ready to accept new
cycles.
The MGPCR can only be accessed in supervisor mode with 32-bit accesses.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
10-7
Multi-layer AHB Crossbar Switch (MAX)
MGPCR0
MGPCR1
MGPCR2
MGPCR3
MGPCR4
MGPCR5
BIT
Master General Purpose Control Register for Master Port 0
Master General Purpose Control Register for Master Port 1
Master General Purpose Control Register for Master Port 2
Master General Purpose Control Register for Master Port 3
Master General Purpose Control Register for Master Port 4
Master General Purpose Control Register for Master Port 5
0x1003_F800
0x1003_F900
0x1003_FA00
0x1003_FB00
0x1003_FC00
0x1003_FD00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
NAME
AULB
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 10-3. Master General Purpose Control Register Description
Name
Description
Setting
Reserved
Bits 31–1
Reserved—These bits are reserved for future expansion. They are read as zero and should be written with zero
for upward compatibility.
AULB
Bit 0
Arbitrate on Undefined Length Bursts—These bits are 000=No arbitration will be allowed during an
used to select the arbitration policy during undefined
undefined length burst.
length bursts by this master. These bits are initialized by 001=Arbitration will be allowed at any time during an
hardware reset. The reset value is 000.
undefined length burst.
010=Arbitration will be allowed after four beats of an
undefined length burst.
011=Arbitration will be allowed after eight beats of an
undefined length burst.
100=Arbitration will be allowed after 16 beats of an
undefined length burst.
101=Reserved
110=Reserved
111=Reserved
10.4
Function
This section describes the functionality of the MAX in greater detail.
10.4.1
Arbitration
The MAX supports two types of arbitration schemes, a simple fixed priority comparison algorithm and a
round robin priority—that is, the ID is defined by the master port number and not the AHB hmaster signal.
The desired algorithm is selected by the ARB bits in the SGPCR0 to SGPCR3 registers. The default setting
of the ARB is to use a simple fixed priority comparison algorithm. In this simple fixed priority comparison
algorithm, each master is assigned a unique priority level in the MPR and gains control over the slave port.
In round robin (rotating) priority, all masters essentially have the same priority, and upon completion of
i.MX21 Reference Manual, Rev. 3
10-8
Freescale Semiconductor
Multi-layer AHB Crossbar Switch (MAX)
one master's access, the next master will initiate access, and upon completion, will move onto the next
master, and so on, until all masters complete one access. Control then rotates back around to the first master
to start the process again.
10.4.2
Arbitration During Undefined Length Bursts
Arbitration points during an undefined length burst are defined by the current master’s MGPCR AULB
field setting. When a defined length is imposed on the burst via the AULB bits the undefined length burst
will be treated as a single or series of single back to back fixed length burst accesses.
Example: A master runs an undefined length burst and the AULB bits in the MGPCR indicate arbitration
will occur after the fourth beat of the burst. The master runs two sequential beats and then starts what will
be an 12 beat undefined length burst access to a new address within the same slave port region as the
previous access. The MAX will not allow an arbitration point until the fourth overall access (second beat
of the second burst). At that point all remaining accesses will be open for arbitration until the master loses
control of the slave port.
Assume the master loses control of the slave port after the fifth beat of the second burst. Once the master
regains control of the slave port no arbitration point will be available until after the master has run four
more beats of its burst. After the fourth beat of the (now continued) burst (ninth beat of the second burst
from the master’s perspective) is taken all beats of the burst will once again be open for arbitration until
the master loses control of the slave port. Assume the master again loses control of the slave port on the
fifth beat of the third (now continued) burst (10th beat of the second burst from the master’s perspective).
Once the master regains control of the slave port it will be allowed to complete its final two beats of its
burst without facing arbitration. Note that fixed length burst accesses will not be affected by the AULB
bits. All fixed length burst accesses will lock out arbitration until the last beat of the fixed length burst.
10.4.3
Fixed Priority Operation
When operating in fixed-priority mode, each master is assigned a unique priority level in the MPR (Master
Priority Register) and AMPR (Alternate Master Priority Register). If two masters both request access to a
slave port the master with the highest priority in the selected priority register will gain control over the
slave port. Any time a master makes a request to a slave port the slave port checks to see if the new
requesting master’s priority level is higher than that of the master that currently has control over the slave
port (unless the slave port is in a parked state). The slave port does an arbitration check at every clock edge
to ensure that the proper master (if any) has control of the slave port. If the new requesting master’s priority
level is higher than that of the master that currently has control of the slave port the new requesting master
will be granted control over the slave port at the next clock edge.
The exception to this rule is if the master that currently has control over the slave port is running a fixed
length burst transfer or a locked transfer. In this case the new requesting master will have to wait until the
end of the burst transfer or locked transfer before it will be granted control of the slave port. If the master
is running an undefined length burst transfer the new requesting master must wait until an arbitration point
for the undefined length burst transfer before it will be granted control of the slave port. Arbitration points
for an undefined length burst are defined in the MGPCR for each master.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
10-9
Multi-layer AHB Crossbar Switch (MAX)
If the new requesting master’s priority level is lower than that of the master that currently has control of
the slave port the new requesting master will be forced to wait until the master that currently has control
of the slave port either runs an IDLE cycle or runs a non IDLE cycle to a location other than the current
slave port.
10.4.4
Round-Robin Priority Operation
When operating in round-robin mode, each master is assigned a relative priority based on the master
number. This relative priority is compared to the ID of the last master to perform a transfer on the slave
bus. The highest priority requesting master will become owner of the slave bus as the next transfer
boundary (accounting for locked and fixed-length burst transfers). Priority is based on how far ahead the
ID of the requesting master is to the ID of the last master (ID is defined by master port number, not the
hmaster field).
Once granted access to a slave port, a master may perform as many transfers as desired to that port until
another master makes a request to the same slave port. The next master in line will be granted access to
the slave port on the next clock cycle if the current master has no pending access request.
As an example of arbitration in round-robin mode, assume the MAX is implemented with master ports 0,
1, 2, 3, 4 and 5. If the last master of the slave port was master 1, and master 0, 4 and 5 make simultaneous
requests, (master ports 2 and 3 make no requests), they will be serviced in the order 4, 5 and then 0.
Parking may still be used in a round-robin mode, but will not affect the round-robin pointer unless the
parked master actually performs a transfer. Hand-off will occur to the next master in line after one cycle
of arbitration. If the slave port is put into low power park mode the round-robin pointer will be reset to
point at master port 0, giving it the highest priority.
10.4.5
Priority Assignment
Each master port needs to be assigned a unique 3 bit priority level. If an attempt is made to program
multiple master ports with the same priority level within a register (MPR or AMPR) the MAX will respond
with an error and the registers will not be updated.
10.4.5.1
Context Switching
The MAX has a hardware input per slave port (sX_ampr_sel) which is used to select which registers
the master priority levels and general purpose control bits will be taken from. When sX_ampr_sel is 0
the MPR and SGPCR will be selected, when sX_ampr_sel is 1 the AMPR and the ASGPCR will be
selected. This hardware input is useful for context switching so the user does not have to rewrite the MPR
or SGPCR if a particular slave port would temporarily benefit from modifying the master priority levels
or functions affected by the bits in the SGPCR.
i.MX21 Reference Manual, Rev. 3
10-10
Freescale Semiconductor
Chapter 11
JTAG Controller
The JTAG Controller module supports Debug access to arm926 core, i.MX21 BIST test (excluding
arm926 platform BIST, BootROM and VectorRAM bist) and tristate enable of the I/O pads. The overall
strategy is to achieve good test and debug features without much increase on pin count and reduce the
complexity on I/O muxing. The TAP ports—TCK, TDI, TMS, TRST and TDO—are not muxed with scan
chains and are not used for any scan control.
The JTAG Controller is compatible with IEEE1149.1 Standard Test Access Port and Boundary Scan
Architecture, but without the logic and instructions needed for Boundary scan.
11.1
Features
The Test and debug features of JTAG provide the following capabilities:
• Provide debug access to the ARM926 core and execute its specific JTAG instructions
independently
• BIST test of i.MX21 RAMs excluding ARM926 platform BIST, BootROM, and VectorRAM
BIST (reserved for internal factory testing)
• Controls tristate enable of I/O pads (reserved for internal factory testing)
11.2
Implementation
The JTAG Controller consists of the JTAG Controller state machine, Instruction Register (IR), Bypass
Register, Instruction decode and various user specific data registers collectively reside inside the
ExtraDebug register.
TDO output from the JTAG Controller is the muxed output based on whether i.MX21 JTAG controller or
ARM926 platform JTAG mode is active. It changes on falling edge of TCK.
The TDO output enable is selected based on whether i.MX21 JTAG controller or ARM926 platform JTAG
mode is active.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
11-1
JTAG Controller
TCK
TRST_N
TMS
TAP_STATE
Reset
RTI
DR
IR
Capture
Shift IR
EIR
Update
RTI
TDI
TDO
TDO_EN
Figure 11-1. JTAG Signals Timing Diagram
•
Test Mode Select (TMS)—Input from external pin by default connects to the ARM926 platform
after gating with the laser fuse output. At the rising edge of TRST, the ipp_jtag_control input
controls whether the TMS pin should be connected to ARM926 platform or to i.MX21 JTAG
controller. When ipp_jtag_control input is HIGH (by default), the TMS pin will be connected to
ARM926 platform after gating with the laser fuse output. The TMS input of i.MX21 JTAG
controller will be held HIGH in this case. When ipp_jtag_control input is LOW, the TMS pin will
be connected to i.MX21 JTAG controller. The TMS input of ARM926 platform will be held HIGH
here.
Test Reset (TRST)—Input from external pin will be connected to both ARM926 platform and
i.MX21 JTAG controller.
The Test Data Input (TDI)—Input from external pin will be connected to both ARM926 platform
and i.MX21 JTAG controller.
Test Clock (TCK)—Input from external pin will be connected to both ARM926 platform and
i.MX21 JTAG controller.
•
•
•
11.3
JTAG Controller Pin List
The signals associated with the JTAG controller are listed in Table 11-1.
Table 11-1. JTAG Controller Pin List
Pin Name
Direction
Description
ipp_tdo
Output
ipp_tck
Input
Test Clock
Test Clock input is used to synchronize the Test Logic. This includes an internal pull-up resistor.
ipp_tdi
Input
Test Data Input
TDI is captured during rising edge of TCK. TDI includes an internal pull-up resistor.
TMS
Input
Test Mode Select
TMS is captured during rising edge of TCK. TMS includes an internal pull-up resistor. TMS
input for the arm926 platform and JTAG controller is gated by the system logic.
TRST
Input
Test Reset
TRST includes an internal pull-up resistor
Test Data Output
TDO is asserted during rising edge of TCK
i.MX21 Reference Manual, Rev. 3
11-2
Freescale Semiconductor
JTAG Controller
Table 11-1. JTAG Controller Pin List (continued)
Pin Name
Direction
JTAG_CTRL
Input
jtagc_tristate_en
Output
Tristate enable to all output and bidirectional pads
RTCK
Output
JTAG optional return clock for devices that support the return clock signal to help enhance
stable communication. This signal is multiplexed with the One Wire signal.
11.4
Description
Control whether ARM926 or JTAG has access of JTAG ports
1=ARM mode (required for debugger support)
0=JTAG mode (internal factory test mode only)
This pin is captured during rising edge of TRST
JTAG Overview
The following sections provide and overview of the JTAG controller operation and the different
operational modes:
Internal signals:
ARM926EJ-S
+ ICE
TRST
ARM
JTAG
CNTLR
jtag_tms
External signals:
TDI
JTAG_CNTL
TCK
jtag_tdo
i.MX21
JTAG
Controller
TMS
TDO
RTCK (optional)
Figure 11-2. i.MX21 JTAG Block Diagram
11.5
JTAG Modes
Two JTAG modes are created based on the I/O pin ipp_jtag_control. These modes are used to maintain
compatibility to ARM MCU Multi-ICE™ products as well as maintain IEEE JTAG standards.
11.5.1
ARM926 Platform JTAG Mode
This mode will connect the processed TMS input to the ARM926 platform. TRST must be asserted to
leave this mode.
11.5.2
i.MX21 JTAG Controller MODE
This mode connects the processed TMS input to the i.MX21 JTAG controller. This provides a dedicated
user-accessible test access port that uses the same communication style as the IEEE1149.1 Standard. TRST
or POR must be asserted to leave this mode.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
11-3
JTAG Controller
In this mode, i.MX21 JTAG controller supports the following capabilities:
• Query identification information (manufacturer, part number and version) of i.MX21 (IDCODE)
• Supports BIST test of all RAMs in i.MX21
• Tristate I/O pads for iddq test (ENABLE_EXTRADEBUG)
• BYPASS instruction
11.6
JTAG Instruction Register
The JTAG instruction register is 3 bits wide and the field definitions are shown in Table 11-2.
Table 11-2. JTAG Instruction Register
Bit2
Bit1
Bit0
Instruction
0
0
0
Reserved
0
0
1
Reserved
0
1
0
IDCODE
0
1
1
ENABLE_ExtraDebug
1
0
0
Reserved
1
0
1
ACCESS_GENERIC_MBIST
1
1
0
Reserved
1
1
1
BYPASS
The instruction register is reset to 3’b010 which is equivalent to the IDCODE instruction.
During the capture-IR state, the parallel inputs to the instruction register are loaded with the code 01 in the
least significant bits as required by the IEEE standard, the most significant bits are loaded with the values
0, leading to a capture value of 3’b001.
11.6.1
IDCODE Instruction
Selects the ID register and the system logic controls the I/O pins. This instruction is a public instruction to
allow the manufacturer, part number and the version of the IC to be available through TAP. The following
table shows the ID register configuration.
Table 11-3. ID Configuration Register
31
28
27
22
21
17
16
12
11
1
Customer Part Number
Version
Information
0000
0
1
Manufacturer Identity
Design Center
Number
Device Number
01110
0111010001
00000001110
1
i.MX21 Reference Manual, Rev. 3
11-4
Freescale Semiconductor
JTAG Controller
11.6.2
ENABLE_Extra Debug Instruction
The Extradebug register consists of 44 bits maximum comprising a 40-bits register (maximum), a 3-bit
address field and one read/write bit. The register data field does not need to be filled in during register read.
The particular Extradebug register connected between TDI and TDO is selected by the ExtraDebug
Controller based on the currently decoded address during Update_DR state. All communication with the
ExtraDebug controller is done through the Select-DR-Scan path of the i.MX21 JTAG Controller.
11.6.3
ACCESS_GENERIC_MBIST Instruction
This instruction is reserved for manufacturing test. IT allows access to i.MX21 Generic BIST Engines
through the TDI/TDO during Shift_DR state.
11.6.4
BYPASS Instruction
Selects the single bit Bypass register and the system logic controls the I/O pins. This creates a shift register
path from TDI to the bypass register and finally to TDO.
When the bypass register is selected by the current instruction, the shift-register stage is set to a logic zero
on the rising edge of TCK in the capture-DR controller state. The first bit to be shifted out after selecting
the bypass register will always be a logic zero.
11.7
Extra Debug Register
Accessed through the Select-DR-Scan path, the ExtraDebug shift register consists of 44 bits (maximum)
comprising a 40 bit data field (max length, see extradebug register description), a 3 bit address field and
read/write bit. The write actually takes place when the JTAG TAP controller enters the Update-DR state.
On a read, the data field is ignored (the user should shift only 4 times to enter Read=1 and the address),
the read will take place on the next path through DR at the Capture-DR state, the data will be shifted-out
during the Shift-DR state.
On the second path for the read access (where the value of the register is shifted out), the command
converter shifts in 0 so the machine will decode Write to Core Status Register which has not effect on the
circuit.
11.8
11.8.1
TMS Sequences
ID Check TMS Sequence
The Table 11-4 shows the TMS sequence to check the ID Code value, starting from any point in the state
machine.
Table 11-4. TMS Sequence to Check ID Code
Step
TCK
TMS
State
0
x5
1
Test Logic Reset
1
x1
0
Run-Test/Idle
Comment
SEQUENCE IS: IDCODE READ
–
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
11-5
JTAG Controller
Table 11-4. TMS Sequence to Check ID Code (continued)
Step
TCK
TMS
State
Comment
2
x1
1
Select DR
–
3
x1
1
Select IR
4
x1
0
Capture IR
5
x1
0
Shift IR
6
x2
0
Shift
–
7
x1
1
Exit1
–
8
x1
1
Update
9
x1
0
Run-Test/Idle
10
x1
1
Select DR
11
x1
0
Capture DR
12
x1
0
Shift DR
13
x31
0
Shift
–
14
x1
1
Exit1
–
15
x1
1
Update
–
16
x1
0
Run-Test/Idle
–
11.8.2
IR Path: Loading ‘Idcode’ instruction
–
Shift ‘Idcode’ instruction= 3'b010 through TDI
Select ‘Idcode’ register
–
DR Path:
Reading Idcode register
Capture Idcode value
Shift out Idcode on 32bits
Write to ExtraDebug Register TMS Sequence
The following table shows the TMS sequence to Write to any of the ExtraDebug registers, starting from
any point in the state machine.
Table 11-5. TMS Sequence to Write ExtraDebug Register
Step
TCK
TMS
State
Comment
0
x5
1
Test Logic Reset
1
x1
0
Run-Test/Idle
–
2
x1
1
Select DR
–
3
x1
1
Select IR
4
x1
0
Capture IR
5
x1
0
Shift IR
6
x2
0
Shift
–
7
x1
1
Exit1
–
8
x1
1
Update
9
x1
0
Run-Test/Idle
10
x1
1
Select DR
SEQUENCE IS: WRITE ExtraDebug Register
IR Path: Select ExtraDebug register.
–
Shift ‘Enable ExtraDebug’ instruction = 3'b011 through TDI
Select ExtraDebug register
–
DR Path: Select Extradebug register to write data
i.MX21 Reference Manual, Rev. 3
11-6
Freescale Semiconductor
JTAG Controller
Table 11-5. TMS Sequence to Write ExtraDebug Register (continued)
Step
TCK
TMS
State
Comment
11
x1
0
Capture DR
–
12
x1
0
Shift DR
13
x43
0
Shift
–
14
x1
1
Exit1
–
15
x1
1
Update
16
x1
0
Run-Test/Idle
11.8.3
Shift In Writ bit(1’b0) + Register Address + Data
Write to the ExtraDebug register
–
TMS Sequence to Read ExtraDebug Register
The following table shows the TMS sequence to READ any of the ExtraDebug registers, starting from any
any point in the state machine.
Table 11-6. TMS Sequence to Read ExtraDebug Register
Step
TCK
TMS
State
Comment
0
x5
1
Test Logic Reset
1
x1
0
Run-Test/Idle
–
2
x1
1
Select DR
–
3
x1
1
Select IR
4
x1
0
Capture IR
5
x1
0
Shift IR
6
x2
0
Shift
–
7
x1
1
Exit1
–
8
x1
1
Update
9
x1
0
Run-Test/Idle
10
x1
1
Select DR
11
x1
0
Capture DR
12
x1
0
Shift DR
13
x3
0
Shift
–
14
x1
1
Exit1
–
15
x1
1
Update
16
x1
0
Run-Test/Idle
17
x1
1
Select DR
18
x1
0
Capture DR
19
x1
0
Shift DR
SEQUENCE IS: READ ExtraDebug Register
IR Path: Select ExtraDebug register.
–
Shift ‘Enable ExtraDebug’ instruction = 3'b011 through TDI
Select ExtraDebug register
–
DR Path: Select Extradebug register to Read
–
Shift In Read bit(1’b1) + Register Address
Decode the 4 bits shifted in
–
2nd DR Path: ExtraDebug Read access
Read the ExtraDebug register
Shift out the captured value
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
11-7
JTAG Controller
Table 11-6. TMS Sequence to Read ExtraDebug Register (continued)
Step
TCK
TMS
State
Comment
20
x39
0
Shift
–
21
x1
1
Exit1
–
22
x1
1
Update
–
23
x1
0
Run-Test/Idle
–
11.9
i.MX21 JTAG Restrictions
TRST must be externally asserted to force the selection of ARM926 platform tap or i.MX21 JTAG
controller. During POR assertion, arm926 platform tap is selected.
If TMS either remains unconnected or connected to VDD, then the TAP Controller cannot leave the
Test-Logic-Reset state regardless of TCK.
i.MX21 Reference Manual, Rev. 3
11-8
Freescale Semiconductor
Chapter 12
Watchdog Timer Module (WDOG)
12.1
Overview
The Watchdog Timer module (WDOG Timer) protects against system failures by providing a method of
escaping from unexpected events or programming errors. Once activated, the timer must be serviced by
software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the
WDOG Timer module either asserts the WDOG interrupt signal or a system reset signal WDOG_RESET
depending on software configuration. The WDOG Timer interrupt module generates a system reset
(WDOG_RESET signal) under any of the following conditions:
• Clearing the SRS bit in the Watchdog Control Register (WCR)
• A Power On Reset has occurred (POR)
• An External Reset has occurred (EXT_RST)
The WDOG signal is asserted by software writing to the WCR, or upon a watchdog time-out. The module
can be activated/deactivated any number of times.
12.1.1
Timing Specifications
The Watchdog Timer provides time-out periods from 0.5 seconds up to 128 seconds with a time resolution
of 0.5 seconds. It uses the 32 kHz clock as an input to pre-scalers. The pre-scalers divide the clock by a
fixed value of 16384 (div4 and div4K) to achieve the resolution of 0.5 seconds and a frequency of 2 Hz
(refer to Figure 12-1 on page 12-3). The output of the pre-scaler circuitry is connected to the input of a
8-bit counter to obtain a range of 0.5 to 128 seconds. The user can determine the time-out period by writing
to the Watchdog Time-out field (WT[7:0]) in the Watchdog Control Register (WCR).
12.1.2
Watchdog During Reset
When a hard reset (HARD_ASYNC_RESET) is asserted all registers except WRSR are reset to their reset
values and the counter is placed in the idle state until the watchdog is enabled. The Watchdog Reset Status
Register (WRSR) contains the source of the reset event and is not reset by hard reset.
12.1.3
Watchdog After Reset
The following sub-sections define the state of the Watchdog Timer after reset.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
12-1
Watchdog Timer Module (WDOG)
12.1.3.1
Initial Load
The Watchdog Time-out Field (WT) of the Watchdog Control Register (WCR), must have some value
written to it prior to enabling the Watchdog timer by setting the Watchdog Enable (WDE) bit in the WCR.
A time-out value is loaded into the counter after the service sequence is written to the Watchdog Service
Register (WSR) or after the Watchdog has been enabled. The service sequence is described in Section
12.1.3.3. When the Watchdog is enabled inside debug mode by setting the WDE bit and clearing the
WDBG bit, the service sequence must be run immediately after it, to reload the counter with contents of
WT field of WCR register.
12.1.3.2
Countdown
The counter begins to count down from its initial programmed value after the Watchdog timer is enabled.
If any system errors have occurred which prevents the software from servicing the Watchdog Service
Register (WSR), the timer will time-out when the counter reaches zero. If the WSR is serviced prior to the
counter reaching zero, the Watchdog will reload its counter to the time-out value indicated by bits WT[7:0]
of the WCR and re-start the countdown. A reset will reset the counter and place it in the idle state at any
time during the countdown.
12.1.3.3
Reload
The proper service sequence is to write a 0x5555 followed by a 0xAAAA to the WSR. In order to reload
the counter, the writes must take place within the time-out value defined by bits WT[7:0] of the WCR. Any
number of instructions can be executed between the two writes. This service sequence is also used to
activate the counter during the initial load. See Section 12.1.3.1, “Initial Load,” on page -2.
If the WSR is not loaded with a 0x5555 prior to a write of 0xAAAA to the WSR, the counter will not be
reloaded. If any value other than 0xAAAA is written to the WSR after 0x5555, the counter will not be
reloaded.
12.1.3.4
Time-Out
If the counter reaches zero, the Watchdog will output either a system reset or the WDOG interrupt signal
depending on the state of the WRE bit in the WCR. A 0 written to the WRE bit will configure the Watchdog
to generate a system reset. A 1 will configure the Watchdog to generate the WDOG interrupt signal.
12.1.4
Low-Power and DEBUG Modes
The Watchdog is affected by the low-power and DEBUG modes. A diagram of low-power control is
shown in Figure 12-1.
12.1.4.1
Low-Power Modes
The Watchdog Timer can be configured for continual operation or it can be suspended during low-power
modes. If the Watchdog Low Power Enable (WDZST) bit in the WCR is set to ‘0”, the Watchdog continues
to operate during low-power mode. If the Low Power Enable (WDZST) bit is set to 1, then the Watchdog
i.MX21 Reference Manual, Rev. 3
12-2
Freescale Semiconductor
Watchdog Timer Module (WDOG)
operation is suspended. Upon exiting low-power mode, the Watchdog operation returns to what it was
prior to entering the mode.
12.1.4.2
DEBUG Mode
The Watchdog Timer can be configured for continual operation or be suspended. If the Watchdog DEBUG
Enable (WDBG) bit is set to 1 in the Watchdog Control Register (WCR), then the Watchdog Timer module
operation is suspended. At this point, the counter is stopped, but register read and write accesses continue
to function normally. Also, while in DEBUG mode, the WDE bit can be enabled-disabled directly.
Watchdog Reset Status Register (WRSR)
Watchdog Service Register (WSR)
Watchdog Control Register (WCR)
WDZST
WDBG
WDE
LOW POWER mode
WDZST
Logic
WDBG
DEBUG (from MCU)*
(time-out)
Logic
8-bit counter
WDE
32KHZ
Pre scaler
~8KHz
(div by 4)
Pre-scaler
~2Hz
(div by 4096)
DEBUG is an active low signal from the MCU indicating DEBUG mode.
Figure 12-1. Low-Power Control
12.2
12.2.1
Watchdog Reset Control
Reset Sources
The watchdog-generated reset signal WDOG_RESET is asserted through software writes to the Software
Reset Signal (SRS) bit of the WCR. The WDOG_RESET can also be generated as a result of a WDOG
time-out, a power-on-reset (POR), or an external reset (EXT_RST).
WDOG_RESET is active for 0.5 seconds for time-outs but is deasserted early if a hard reset is detected.
In case of software reset, it gets asserted 3 clocks after the resetting of the SRS bit and remains asserted
for 3 PER_CLOCK cycles. If a hard reset occurs before this time, it deasserts before 3 clock periods have
elapsed.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
12-3
Watchdog Timer Module (WDOG)
For power on reset and external reset, it is asserted as long as they remain active.
The watchdog-generated reset signal WDOG_RESET is an output to the PLL Clock Controller and Reset
Module which generates a HARD_ASYNC_RESET on assertion of WDOG_RESET.
12.2.2
WDOG Operation
WDOG can be asserted through software writes to the WDOG Assertion (WDA) bit of the WCR. It can
also be generated as a result of a WDOG time-out.
If asserted by a software write to WDA bit, WDOG remains asserted as long as WDA bit is 0. If it is
generated by a counter time-out, it is asserted for 0.5 sec. Either a hard reset (HARD_ASYNC_RESET)
or Power On Reset (POR) can deassert WDOG before the 0.5 sec.
12.3
Programming Model
The Watchdog Timer has three registers in its programming model: Watchdog Control Register (WCR),
Watchdog Service Register (WSR), and Watchdog Reset Status Register (WRSR). This section provides
detailed descriptions of the WDOG registers.
12.3.1
Watchdog Control Register
The WCR is a 16-bit read/write (byte writable) register. It controls the Watchdog operation. All bits except
for bits[5:4] are cleared during reset. Bits[5:4] are set to 1 during reset.
WCR
BIT
Watchdog Control Register
15
14
13
12
11
10
9
8
7
Addr
0x10002000
6
WT
5
4
WDA
SRS
3
2
1
0
WRE WDE WDBG WDZST
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Table 12-1. Watchdog Control Register Description
Name
Description
Settings
WT
Bits 15–8
Watchdog Time-Out Field—This 8-bit field contains the time-out value and is Set to desired time-out value.
loaded into the Watchdog counter after the service routine has been performed.
After reset, WT must be written before enabling the Watchdog.
Reserved
Bits 7–6
Reserved—These bits are reserved and should always read as zero and must be written with zeros for future
compatibility.
WDA
Bit 5
Watchdog Assertion—Controls the software assertion of the WDOG signal.
SRS
Bit 4
Software Reset Signal—Controls the software assertion of the
0 = Assert system reset signal
WDOG-generated reset signal. This bit is automatically set to 1 after it has been 1 = No effect on system
asserted to 0.
Note: This bit does not generate software reset to the module.
0 = Assert WDOG output
1 = No effect on system
i.MX21 Reference Manual, Rev. 3
12-4
Freescale Semiconductor
Watchdog Timer Module (WDOG)
Table 12-1. Watchdog Control Register Description (continued)
Name
Description
Settings
0 = Generate a reset signal
1 = Generate WDOG interrupt
WRE
Bit 3
WDOG or WDOG_RESET Enable—Determines if the watchdog will generate
the reset signal or WDOG upon a watchdog time-out. Write once-only.
WDE
Bit 2
Watchdog Enable—Enables or disables the WDOG module. Software can only 0 = Disable Watchdog
write 1 in this bit. It is not possible to reset this bit by a software write, once the 1 = Enable Watchdog
bit is set
WDBG
Bit 1
Watchdog DEBUG Enable—Determines the operation of the WDOG module
during DEBUG mode. Write once-only.
WDZST
Bit 0
Watchdog Low Power—Determines the operation of the WDOG module during 0 = Continue timer operation
Low power modes. Write once-only.
1 = Suspend watchdog timer
0 = Continue timer operation
1 = Suspend watchdog timer
NOTE
WDE bit is not used for clock gating in i.MX21.
12.3.2
Watchdog Service Register
When enabled, the Watchdog requires that a service sequence be written to the Watchdog Service Register
(WSR) as described in Table 12-2.
WSR
BIT
Watchdog Service Register
15
14
13
12
11
10
9
8
Addr
0x10002002
7
6
5
4
3
2
1
0
WSR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 12-2. Watchdog Service Register Description
Name
WSR
Bits 15–0
12.3.3
Description
Settings
Watchdog Service Register—This 16-bit field contains The service sequence must be performed as follows:
the watchdog service sequence.
a. Write $5555 to the Watchdog Service Register
Note: Both writes must occur in the order listed prior to
(WSR).
the time-out, but any number of instructions can be
b. Write $AAAA to the Watchdog Service Register
executed between the two writes.
(WSR).
Watchdog Reset Status Register
The WRSR is a read-only register which records the source of the output reset assertion. It is not cleared
by reset. It records the source of the output reset assertion. Therefore, one and only one bit in the WRSR
will always be asserted high. And every time the register will represent the source of last reset.
RESET can be generated by the following sources as listed in priority from highest to lowest: Power-on
reset, External reset, Watchdog Time-out, and Software reset.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
12-5
Watchdog Timer Module (WDOG)
WRSR
BIT
Watchdog Reset Status Register
15
14
13
12
11
10
9
8
7
6
Addr
0x10002004
5
4
3
PWR
EXT
2
1
0
TOUT
SFTW
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
?
?
?
?
?
?
Table 12-3. Watchdog Reset Status Register Description
Name
Description
Settings
Reserved
Bits 15–5
Reserved—These bits are read as 0 and should be written as 0 for future compatibility.
PWR
Bit 4
Power-On Reset—Indicates whether the reset was a result 0 = Reset is not a result of a power-on reset
of a power-on reset.
1 = Reset is a result of a power-on reset
EXT
Bit 3
External Reset—Indicates whether the reset was a result 0 = Reset is not a result of an external reset
of an external reset.
1 = Reset is a result of an external reset
Reserved
Bits 2
Reserved—These bits are read as 0 and should be written as 0 for future compatibility.
TOUT
Bit 1
Time-out—Indicates whether the reset was a result of
WDOG time-out.
SFTW
Bit 0
Software Reset—Indicates whether the reset was a result 0 = Reset is not a result of a software reset
of a software reset.
1 = Reset is a result of a software reset
0 = Reset is not the result of WDOG time-out
1 = Reset is the result of a WDOG time-out
Note: Do not write to this register. Attempting to write to the WRSR register will generate a bus error.
i.MX21 Reference Manual, Rev. 3
12-6
Freescale Semiconductor
Chapter 13
Real-Time Clock (RTC)
This section discusses how to operate and program the real-time clock (RTC) module that maintains the
system clock, provides stopwatch, alarm, and interrupt functions, and supports the following features:
• Full clock—days, hours, minutes, seconds
• Minute countdown timer with interrupt
• Programmable daily alarm with interrupt
• Sampling timer with interrupt
• Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts
• Operation at 32.768 kHz or 32 kHz, or 38.4 kHz (determined by reference clock crystal)
As shown in the RTC block diagram (Figure 13-1), the real-time clock module consists of the following
blocks:
• Prescaler
• Time-of-day (TOD) clock counter
• Alarm
• Sampling timer
• Minute stopwatch
• Associated control and bus interface hardware
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
13-1
Real-Time Clock (RTC)
CLK2HZ
32.768K OR 32K OR 38.4K
CLK32HZ
TOD CLOCK
SAMPLING
TIMER
PRESCALER
1 PPS
SECOND
1 PPM
MINUTE
1 PPH
HOUR
1 PPD
DAY
CLOCK
CONTROL
RTC_INT
INTERRUPT
CONTROL
INTERRUPT
ENABLE
INTERRUPT
STATUS
ALARM COMPARATOR
SECOND
LATCH
MINUTE
LATCH
HOUR
LATCH
ADDRESS
IPBUS
DECODE
DATA
MINUTE STOPWATCH
BUS CONTROL
Figure 13-1. Real-Time Clock Block Diagram
13.1
Operation
The prescaler converts the incoming crystal reference clock to a 1 Hz signal which is used to increment
the seconds, minutes, hours, and days TOD counters. The RTC also generates 32 Hz and 2Hz clock signal.
The 32Hz clock is used by the LCDC to divide using the BD value to blink the cursor on/off and it is also
is also reflected as an interrupt to AITC when SAM3 interrupt is enabled. The 2 Hz clock output can be
used for flashing a LED or blinking the dots on the time display on the smartphone on/off without
intervention by the ARM9 platform. The alarm functions, when enabled, generate RTC interrupts when
the TOD settings reach programmed values. The sampling timer generates fixed-frequency interrupts, and
the minute stopwatch allows for efficient interrupts on minute boundaries.
13.2
Prescaler and Counter
The prescaler divides the reference clock down to 1 Hz. The reference frequencies of 32.768 kHz,
38.4 kHz and 32 kHz are supported. The counter portion of the RTC module consists of four groups of
counters that are physically located in three registers:
• The 6-bit seconds counter is located in the SECONDS register
• The 6-bit minutes counter and the 5-bit hours counter are located in the HOURMIN register
• The 16-bit day counter is located in the DAYR register
These counters cover a 24-hour clock over 65536 days. All three registers can be read or written at any
time.
i.MX21 Reference Manual, Rev. 3
13-2
Freescale Semiconductor
Real-Time Clock (RTC)
Interrupts signal when each of the four counters increments, and can be used to indicate when a counter
rolls over. For example, each tick of the seconds counter causes the 1Hz interrupt flag to be set. When the
seconds counter rolls from 59 to 00, the minute counter increments and the MIN interrupt flag is set. The
same is true for the minute counter with the HR signal, and the hour counter with the DAY signal.
13.2.1
Alarm
There are three alarm registers that mirror the three counter registers. An alarm is set by accessing the
real-time clock alarm registers (ALRM_HM, ALRM_SEC, and DAYALARM) and loading the exact time
that the alarm should generate an interrupt. When the TOD clock value and the alarm value coincide, if the
ALM bit in the real-time clock interrupt enable register (RTCIENR) is set, an interrupt occurs.
NOTE
If the alarm is not disabled, it will reoccur every 65536 days. If a single alarm is
desired, the alarm function must be disabled using the Alarm bit (ALM) in the RTC
Interrupt Enable Register (RTCIENR).
13.2.2
Sampling Timer
The sampling timer is provided to support application software. The sampling timer generates a periodic
interrupt with the frequency specified by the SAMx bits of the RTCIENR register. This timer can be used
for digitizer sampling, keyboard debouncing, or communication polling. The sampling timer operates only
if the real-time clock is enabled. The following table lists the interrupt frequencies of the sampling timer
for the possible reference clocks.
Multiple SAMx bits may be set in the RTC Interrupt Enable Register (RTCIENR). The corresponding bits
in the RTC Interrupt Status Register (RTCISR) will be set at the noted frequencies.
Table 13-1. Sampling Timer Frequencies
13.2.3
Sampling
Frequency
32.768 kHz
Reference Clock
32 kHz
Reference Clock
38.4 kHz
Reference Clock
SAM7
512 Hz
500 Hz
600 Hz
SAM6
256 Hz
250 Hz
300 Hz
SAM5
128 Hz
125 Hz
150 Hz
SAM4
64 Hz
62.5 Hz
75 Hz
SAM3
32 Hz
31.25 Hz
37.5 Hz
SAM2
16 Hz
15.625 Hz
18.75 Hz
SAM1
8 Hz
7.8125 Hz
9.375 Hz
SAM0
4 Hz
3.90625 Hz
4.6875 Hz
Minute Stopwatch
The minute stopwatch performs a countdown with a one minute resolution. It can be used to generate an
interrupt on a minute boundary. For example, to turn off the LCD controller after five minutes of inactivity,
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
13-3
Real-Time Clock (RTC)
program a value of 0x04 into the Stopwatch Count (CNT) field of the Stopwatch Minutes (STPWCH)
register (see Table 13-12 for a complete list of settings for the STPWCH register). At each minute, the
value in the stopwatch is decremented. When the stopwatch value reaches -1, the interrupt occurs. The
value of the register does not change until it is reprogrammed. Note that the actual delay includes the
seconds from setting the stopwatch to the next minute tick.
13.3
Programming Model
The RTC module includes ten 32-bit registers. Table 13-2 summarizes these registers and their addresses.
Table 13-2. RTC Module Register Summary
Description
13.3.1
Name
Address
RTC Days Counter Register
DAYR
0x10007020
RTC Hours and Minutes Counter Register
HOURMIN
0x10007000
RTC Seconds Counter Register
SECONDS
0x10007004
RTC Day Alarm Register
DAYALARM
0x10007024
RTC Hours and Minutes Alarm Register
ALRM_HM
0x10007008
RTC Seconds Alarm Register
ALRM_SEC
0x1000700C
RTC Control Register
RCCTL
0x10007010
RTC Interrupt Status Register
RTCISR
0x10007014
RTC Interrupt Enable Register
RTCIENR
0x10007018
Stopwatch Minutes Register
STPWCH
0x1000701C
RTC Days Counter Register
The real-time clock days counter register (DAYR) is used to program the day for the TOD clock. When
the HOUR field of the HOURMIN register rolls over from 23 to 00, the day counter increments. It can be
read or written at any time. After a write, the time changes to the new value. This register cannot be reset
since the real-time clock is always enabled at reset.
NOTE
This day counter only supports halfword and word write operations. That means
that all 16 bits must be set simultaneously.
i.MX21 Reference Manual, Rev. 3
13-4
Freescale Semiconductor
Real-Time Clock (RTC)
DAYR
Addr
0x10007020
RTC Days Counter Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DAYS
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
RESET
0x????
Table 13-3. RTC Days Counter Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
DAYS
Bits 15–0
Day Setting—Indicates the current day count.
13.3.2
DAYS can be set to any value between 0
and 65535.
RTC Hours and Minutes Counter Register
The real-time clock hours and minutes counter register (HOURMIN) is used to program the hours and
minutes for the TOD clock. It can be read or written at any time. After a write, the time changes to the new
value. This register cannot be reset since the real-time clock is always enabled at reset.
HOURMIN
Addr
0x10007000
RTC Hours and Minutes Counter Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
HOURS
TYPE
MINUTES
r
r
r
rw
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
0
0
0
?
?
?
?
?
0
0
?
?
?
?
?
?
RESET
0x????
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
13-5
Real-Time Clock (RTC)
Table 13-4. RTC Hours and Minutes Counter Register Description
Name
Description
Settings
Reserved
Bits 31–13
Reserved—These bits are reserved and should read 0.
HOURS
Bits 12–8
Hour Setting—Indicates the current hour.
Reserved
Bits 7–6
Reserved—These bits are reserved and should read 0.
MINUTES
Bits 5–0
Minute Setting—Indicates the current minute.
13.3.3
HOURS can be set to any value
between 0 and 23.
MINUTES can be set to any value
between 0 and 59.
RTC Seconds Counter Register
The real-time clock seconds register (SECONDS) is used to program the seconds for the TOD clock. It
can be read or written at any time. After a write, the time changes to the new value. This register cannot
be reset since the real-time clock is always enabled at reset.
SECONDS
Addr
0x10007004
RTC Seconds Counter Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SECONDS
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
?
?
?
?
?
?
RESET
0X00??
=
Table 13-5. RTC Seconds Counter Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
SECONDS
Bits 5–0
Seconds Setting—Indicates the current second.
13.3.4
Settings
SECONDS can be set to any value
between 0 and 59.
RTC Day Alarm Register
The real-time clock day alarm (DAYALARM) register is used to configure the day for the alarm. The alarm
settings can be read or written at any time.
i.MX21 Reference Manual, Rev. 3
13-6
Freescale Semiconductor
Real-Time Clock (RTC)
DAYALARM
Addr
0x10007024
RTC Day Alarm Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DAYSAL
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-6. RTC Day Alarm Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
DAYSAL
Bits 15–0
Day Setting of the Alarm—Indicates the current day setting of
the alarm.
13.3.5
DAYSAL can be set to any value between 0
and 65535.
RTC Hours and Minutes Alarm Register
The real-time clock hours and minutes alarm (ALRM_HM) register is used to configure the hours and
minutes setting for the alarm. The alarm settings can be read or written at any time.
ALRM_HM
Addr
0x10007008
RTC Hours and Minutes Alarm Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
HOURS
TYPE
MINUTES
r
r
r
rw
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
13-7
Real-Time Clock (RTC)
Table 13-7. RTC Hours and Minutes Alarm Register Description
Name
Description
Settings
Reserved
Bits 31–13
Reserved—These bits are reserved and should read 0.
HOURS
Bits 12–8
Hour Setting of the Alarm—Indicates the current hour setting of HOURS can be set to any value between 0
the alarm.
and 23.
Reserved
Bits 7–6
Reserved—These bits are reserved and should read 0.
MINUTES
Bits 5–0
Minute Setting of the Alarm—Indicates the current minute
setting of the alarm.
13.3.6
MINUTES can be set to any value
between 0 and 59.
RTC Seconds Alarm Register
The real-time clock seconds alarm (ALRM_SEC) register is used to configure the seconds setting for the
alarm. The alarm settings can be read or written at any time.
ALRM_SEC
Addr
0x10007000C
RTC Seconds Alarm Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SECONDS
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-8. RTC Seconds Alarm Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
SECONDS
Bits 5–0
Seconds Setting of the Alarm—Indicates the current seconds
setting of the alarm.
13.3.7
Settings
SECONDS can be set to any value
between 0 and 59.
RTC Control Register
The real-time clock control (RTCCTL) register is used to enable the real-time clock module and specify
the reference frequency information for the prescaler.
i.MX21 Reference Manual, Rev. 3
13-8
Freescale Semiconductor
Real-Time Clock (RTC)
RCCTL
Addr
0x10007010
RTC Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
EN
TYPE
XTL
SWR
r
r
r
r
r
r
r
r
rw
rw
rw
r
r
r
r
rw
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
RESET
0x0080
Table 13-9. RTC Control Register Description
Name
Description
Settings
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
EN
Bit 7
Enable—Enables/Disables the real-time clock. The software reset bit 0 = Disable the real-time clock
(SWR) has no effect on this bit.
1 = Enable the real-time clock
XTL
Bits 6–5
Crystal Selection—Selects the proper input crystal frequency. It is
important to set these bits correctly or the real-time clock will be
inaccurate.
Reserved
Bits 4–1
Reserved—These bits are reserved and should read 0.
SWR
Bit 0
Software Reset—Resets the module to its default state. However, a
software reset will have no effect on the clock enable (EN) bit.
13.3.8
00 = 32.768 kHZ
01 = 32 kHz
10 = 38.4 kHz
11 = 32.768 kHz
0 = No effect.
1 = Reset the module to its default state.
RTC Interrupt Status Register
The real-time clock interrupt status register (RTCISR) indicates the status of the various real-time clock
interrupts. When an event of the types included in this register occurs, then the bit will be set in this
register, regardless of whether the interrupt is enabled. These bits are cleared by writing a value of 1, which
also clears the interrupt. Interrupts may occur while the system clock is idle or in sleep mode. For more
information about the frequency of the sampling timer interrupts (SAM7–SAM0), refer to Table 13-1.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
13-9
Real-Time Clock (RTC)
RTCISR
Addr
0x10007014
RTC Interrupt Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
HR
1HZ
DAY
ALM
MIN
SW
RESET
0x0000
BIT
15
SAM7
TYPE
14
13
12
11
10
9
8
SAM6 SAM5 SAM4 SAM3 SAM2 SAM1 SAM0
2HZ
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-10. RTC Interrupt Status Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
SAM7
Bit 15
Sampling Timer Interrupt Flag at SAM7 Frequency—Indicates that an
0 = No SAM7 interrupt occurred.
interrupt has occurred. If enabled, this bit is periodically set at a rate of 512, 1 = A SAM7 interrupt occurred.
600, or 500 Hz. The actual rate of the interrupt depends on the input clock
value. See Table 13-1 on page 13-3.
SAM6
Bit 14
Sampling Timer Interrupt Flag at SAM6 Frequency—Indicates that an
0 = No SAM6 interrupt occurred.
interrupt has occurred. If enabled, this bit is periodically set at a rate of 256, 1 = A SAM6 interrupt occurred.
250, or 300 Hz. The actual rate of the interrupt depends on the input clock
value. See Table 13-1 on page 13-3.
SAM5
Bit 13
Sampling Timer Interrupt Flag at SAM5 Frequency—Indicates that an
0 = No SAM5 interrupt occurred.
interrupt has occurred. If enabled, this bit is periodically set at a rate of 128, 1 = A SAM5 interrupt occurred.
125, or 150 Hz. The actual rate of the interrupt depends on the input clock
value. See Table 13-1 on page 13-3.
SAM4
Bit 12
Sampling Timer Interrupt Flag at SAM4 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 64,
62.5, or 75 Hz. The actual rate of the interrupt depends on the input clock
value. See Table 13-1 on page 13-3.
0 = No SAM4 interrupt occurred.
1 = A SAM4 interrupt occurred.
SAM3
Bit 11
Sampling Timer Interrupt Flag at SAM3 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 32,
31.25, or 37.5 Hz. The actual rate of the interrupt depends on the input
clock value. See Table 13-1 on page 13-3.
0 = No SAM3 interrupt occurred.
1 = A SAM3 interrupt occurred.
SAM2
Bit 10
Sampling Timer Interrupt Flag at SAM2 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 16,
15.625, or 18.75 Hz. The actual rate of the interrupt depends on the input
clock value. See Table 13-1 on page 13-3.
0 = No SAM2 interrupt occurred.
1 = A SAM2 interrupt occurred.
i.MX21 Reference Manual, Rev. 3
13-10
Freescale Semiconductor
Real-Time Clock (RTC)
Table 13-10. RTC Interrupt Status Register Description (continued)
Name
Description
Settings
SAM1
Bit 9
Sampling Timer Interrupt Flag at SAM1 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 8,
7.8125, or 9.375 Hz. The actual rate of the interrupt depends on the input
clock value. See Table 13-1 on page 13-3.
0 = No SAM1 interrupt occurred.
1 = A SAM1 interrupt occurred.
SAM0
Bit 8
Sampling Timer Interrupt Flag at SAM0 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 4,
3.90625, or 4.6875 Hz. The actual rate of the interrupt depends on the
input clock value. See Table 13-1 on page 13-3.
0 = No SAM0 interrupt occurred.
1 = A SAM0 interrupt occurred.
2HZ
Bit 7
2 Hz Flag—Indicates that an interrupt has occurred. If enabled, this bit is
set at every 2 Hz frequency.
0 = No 2 Hz interrupt occurred.
1 = A 2 Hz interrupt has occurred.
Reserved
Bit 6
Reserved—This bit is reserved and should read 0.
HR
Bit 5
Hour Flag—Indicates that the hour counter has incremented. If enabled,
this bit is set on every increment of the hour counter in the time-of-day
clock.
1HZ
Bit 4
1 Hz Flag—Indicates that the second counter has incremented. If enabled, 0 = No 1 Hz interrupt occurred.
this bit is set on every increment of the second counter of the time-of-day
1 = A 1 Hz interrupt has occurred.
clock.
DAY
Bit 3
Day Flag—Indicates that the day counter has incremented. If enabled, this 0 = No 24-hour rollover interrupt
bit is set on every increment of the day counter of the time-of-day clock.
occurred.
1 = A 24-hour rollover interrupt has
occurred.
ALM
Bit 2
Alarm Flag—Indicates that the real-time clock matches the value in the
alarm registers. Note that the alarm will reoccur every 512 days. For a
single alarm, clear the interrupt enable for this bit in the interrupt service
routine.
0 = No alarm interrupt occurred.
1 = An alarm interrupt has
occurred.
MIN
Bit 1
Minute Flag—Indicates that the minute counter has incremented. If
enabled, this bit is set on every increment of the minute counter in the
time-of-day clock.
0 = No 1-minute interrupt occurred.
1 = A 1-minute interrupt has
occurred.
SW
Bit 0
Stopwatch Flag—Indicates that the stopwatch countdown timed out.
0 = The stopwatch did not time out.
1 = The stopwatch timed out.
13.3.9
0 = No 1-hour interrupt occurred.
1 = A 1-hour interrupt has occurred
RTC Interrupt Enable Register
The real-time clock interrupt enable register (RTCIENR) is used to enable/disable the various real-time
clock interrupts. When an event of the types included in this register occurs, the corresponding bit gets set
in the RTC Interrupt Status Register (RTCISR). An interrupt will occur if the corresponding bit is enabled
in this register. For more information about the frequency of the sampling timer interrupts
(SAM7–SAM0), refer to Table 13-1 on page 13-3.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
13-11
Real-Time Clock (RTC)
RTCIENR
BIT
31
TYPE
RESET
Addr
0x10007018
RTC Interrupt Enable Register
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
0x0000
BIT
15
SAM7
TYPE
RESET
14
13
12
11
10
9
8
SAM6 SAM5 SAM4 SAM3 SAM2 SAM1 SAM0
2HZ
5
4
3
2
1
0
HR
1HZ
DAY
ALM
MIN
SW
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 13-11. RTC Interrupt Enable Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
SAM7
Bit 15
Sampling Timer Interrupt Flag at SAM7 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 7. The
frequency of this interrupt is shown in Table 13-1 on page 13-3.
0 = The SAM7 interrupt is disabled.
1 = The SAM7 interrupt is enabled.
SAM6
Bit 14
Sampling Timer Interrupt Flag at SAM6 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 6. The
frequency of this interrupt is shown in Table 13-1 on page 13-3.
0 = The SAM6 interrupt is disabled.
1 = The SAM6 interrupt is enabled.
SAM5
Bit 13
Sampling Timer Interrupt Flag at SAM5 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 5. The
frequency of this interrupt is shown in Table 13-1 on page 13-3.
0 = The SAM5 interrupt is disabled.
1 = The SAM5 interrupt is enabled.
SAM4
Bit 12
Sampling Timer Interrupt Flag at SAM4 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 4. The
frequency of this interrupt is shown in Table 13-1 on page 13-3.
0 = The SAM4 interrupt is disabled.
1 = The SAM4 interrupt is enabled.
SAM3
Bit 11
Sampling Timer Interrupt Flag at SAM3 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 3. The
frequency of this interrupt is shown in Table 13-1 on page 13-3.
0 = The SAM3 interrupt is disabled.
1 = The SAM3 interrupt is enabled.
SAM2
Bit 10
Sampling Timer Interrupt Flag at SAM2 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 2. The
frequency of this interrupt is shown in Table 13-1 on page 13-3.
0 = The SAM2 interrupt is disabled.
1 = The SAM2 interrupt is enabled.
SAM1
Bit 9
Sampling Timer Interrupt Flag at SAM1 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 1. The
frequency of this interrupt is shown in Table 13-1 on page 13-3.
0 = The SAM1 interrupt is disabled.
1 = The SAM1 interrupt is enabled.
SAM0
Bit 8
Sampling Timer Interrupt Flag at SAM0 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 0. The
frequency of this interrupt is shown in Table 13-1 on page 13-3.
0 = The SAM0 interrupt is disabled.
1 = The SAM0 interrupt is enabled.
2HZ
Bit 7
2 Hz Interrupt Enable—Enables/Disables an interrupt at a 2 Hz rate.
0 = The 2 Hz interrupt is disabled.
1 = The 2 Hz interrupt is enabled.
Reserved
Bit 6
Reserved—This bit is reserved and should read 0.
i.MX21 Reference Manual, Rev. 3
13-12
Freescale Semiconductor
Real-Time Clock (RTC)
Table 13-11. RTC Interrupt Enable Register Description (continued)
Name
Description
Settings
HR
Bit 5
Hour Interrupt Enable—Enables/Disables an interrupt whenever the
hour counter of the real-time clock increments.
0 = The 1-hour interrupt id disabled.
1 = The 1-hour interrupt is enabled.
1HZ
Bit 4
1 Hz Interrupt Enable—Enables/Disables an interrupt whenever the
second counter of the real-time clock increments.
0 = The 1 Hz interrupt is disabled.
1 = The 1 Hz interrupt is enabled.
DAY
Bit 3
Day Interrupt Enable—Enables/Disables an interrupt whenever the
hours counter rolls over from 23 to 0 (midnight rollover).
0 = The 24-hour interrupt is disabled.
1 = The 24-hour interrupt is enabled.
ALM
Bit 2
Alarm Interrupt Enable—Enables/Disables the alarm interrupt.
0 = The alarm interrupt is disabled.
1 = The alarm interrupt is enabled.
MIN
Bit 1
Minute Interrupt Enable—Enables/Disables an interrupt whenever the
minute counter of the real-time clock increments.
0 = The 1-minute interrupt is disabled.
1 = The 1-minute interrupt is enabled.
SW
Bit 0
Stopwatch Interrupt Enable—Enables/Disables the stopwatch interrupt. 0 = Stopwatch interrupt is disabled.
1 = Stopwatch interrupt is enabled.
Note: The stopwatch counts down and remains at decimal -1 until it is
reprogrammed. If this bit is enabled with -1 (decimal) in the STPWCH
register, an interrupt will be posted on the next minute tick.
13.3.10 Stopwatch Minutes Register
The stopwatch minutes (STPWCH) register contains the current stopwatch countdown value. When the
minute counter of the TOD clock increments, the value in this register decrements.
STPWCH
BIT
TYPE
RESET
31
Addr
0x1000701C
Stopwatch Minutes Register
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
0x0000
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
CNT
RESET
0x003F
Table 13-12. Stopwatch Minutes Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
CNT
Bits 5–0
Stopwatch Count—Contains the stopwatch countdown value.
Settings
These bits can be set to any
value between 0 and 62.
Note: The stopwatch counter is decremented by the minute (MIN) tick output
from the real-time clock, so the average tolerance of the count is 0.5 minutes. For Once the countdown has
completed, the value will
better accuracy, enable the stopwatch by polling the MIN bit of the RTCISR
not change until a nonzero
register or by polling the minute interrupt service routine.
value (1–62) is written.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
13-13
Real-Time Clock (RTC)
i.MX21 Reference Manual, Rev. 3
13-14
Freescale Semiconductor
Chapter 14
General-Purpose Timers (GPT)
The GPT module of the i.MX21 contains three identical general-purpose 32-bit timers (GPT) with
programmable prescalers and compare and capture registers. Each timer’s counter value can be captured
using an external event and can be configured to trigger a capture event on either the leading or trailing
edges of an input pulse. Each GPT can also generate an interrupt when the timer reaches a programmed
value. Each GPT has an11-bit prescaler providing a programmable clock frequency derived from the
IPG_CLK_PERCLK1 (or simply PERCLK1 from the PLL, Clock, and Reset Controller chapter).
Figure 14-1 illustrates the general-purpose timer block diagram for one of the timers.
The General-Purpose Timers have the following features:
• Programmable sources for the clock input, including external clock
• Input capture capability with programmable trigger edge
• Output compare with programmable mode
• Free-run and restart modes
• Software reset function
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
14-1
General-Purpose Timers (GPT)
.
1/4
IPG_CLK_PERCLK (PERCLK1)
Prescaler
11bit
1... 2048
IPG_CLK_32K
FRR
(From 32kHz crystal input)
Prescaler
clock output
sync
Timer
Counter
register
TIN
sync
Input
Capture
Logic
Timer
Input Capture
register
Module
Interrupt Line
IP-Bus REG r/w
IRQEN
comp
status
Timer
Output Compare
register
cmp
Output
Control
Logic
TOUT
Figure 14-1. General-Purpose Timer Block Diagram
14.1
Operation
After a hardware reset the Counter, Control, Prescaler, Status and Capture registers of the GPT are reset.
The Compare value is set to 0xFFFFFFFF. The output pin (TOUT) is also reset. The GPT is enabled when
the TEN bit in the GPT Control Register (TCTL) is set and the counter starts runnning. It is recommended
that all the registers be set to appropiate values first before enabling the GPT. When the TEN bit is cleared
the counter value freezes or clears depending on CC bit in GPT Control Register (TCTL). All other register
values are retained.
There is a Software Reset bit (SWR) in the TCTL register. When this bit is set the GPT generates a reset
signal. The software reset results in all the registers in the GPT being reset except for the TEN bit which
is not cleared by software reset if set. The software reset can be asserted with the TEN bit off, however,
the IPG_CLK clock (module clock) signals to GPT must be on for the software reset to be functional.
14.1.1
Clocks
The clock that feeds the prescaler can be selected from the
• IPG_CLK_PERCLK1 (divided by 1 or by 4). The frequency of IPG_CLK_PERCLK1 is constant
and is independent of changes to the IPG_CLK. The module internally synchronizes PERCLK1 to
the IPG_CLK. This clock is synchronized inside the module to IPG_CLK. Hence the frequency of
this clock has to be at least 1/4 that of IPG_CLK if the prescaler is programmed to divide by 1.
i.MX21 Reference Manual, Rev. 3
14-2
Freescale Semiconductor
General-Purpose Timers (GPT)
The clock input source is determined by the CLKSOURCE field of the GPT control register. The
CLKSOURCE value should only be changed when the GPT is disabled. The GPT prescaler register
(TPRER) selects the divide ratio of the input clock that drives the main counter (TCN). The prescaler can
divide the input clock by a value between 1 and 2048.
14.1.2
Operation During Low-Power Mode
In low-power mode when the IPG_CLK (module clock used for register accesses) and
IPG_CLK_PERCLK clocks are switched off, the GPT halts and the counter (TEN) freezes at its current
value. Since all clocks to the counter are synchronized with IPG_CLK the counter stops counting as and
when the IPG_CLK is turned off. Thus when IPG_CLK is switched off this clock will be off and even
though 32KHz, IPG_CLK_PERCLK1 (PERCLK1) or IPP_GPT_TIN (Timer input from TIN pin) clock
is available at the module input, the counter freezes and all GPT operations are halted.
14.1.3
Capture Event
Each of the three GP Timers have a 32-bit capture register that takes a snapshot of the counter when a
defined transition of TIN is detected by the capture edge detector. The type of transition that triggers this
capture is selected by the CAP field of the GPT Control Register (TCTL). Each transition must be valid
for at least two IPG_CLK periods to ensure a capture event is triggered.
When a capture event occurs, the corresponding status bit is set in the GPT status register (TSTAT) and an
interrupt is posted if the capture function is enabled and if the CAPTEN bit of the GPT control register is
set. If another capture event occurs the new count value will still be captured in the capture register even
if the interrupt is not serviced and capture status bit is set.
14.1.4
Compare Event
Each GPT has a 32-bit compare register. When the value in this register matches with the value of the
counter register a compare event occurs. On a compare event the appropriate GPT output pin (TOUT) is
toggled or an active low pulse (for one count period) is generated on it according to the setting of Output
Mode (OM) bit in the GPT control register. When in toggle mode the toggling takes place at the end of the
count period in which the match has occurred.
• The Timer output of GPT1, TOUT1, is available at TOUT pin.
• The Timer output of GPT2, TOUT2, is available at the Bin output at the PWM pin.
• The Timer output of GPT3, TOUT3, is available at the Cin output at the PWM pin.
NOTE
TOUT2 and TOUT3 are muxed via the IOMUX, see Chapter 47, GPIO,
and made available at the PWM pin as alternate functions.
The corresponding status bit is set in the status register and an interrupt is posted if the COMPEN bit of
the GPT control register is set. The GPT output pin continues to produce an output on a compare event
even if the interrupt is not serviced and compare status bit is set.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
14-3
General-Purpose Timers (GPT)
14.1.5
Modes of Operation
The GPT can be configured for free-run or restart modes by programming the Free-run / Restart bit (FRR)
of the GPT control register.
• Restart mode: In restart mode, when a compare event occurs, the counter resets to 0x00000000.
Subsequently it resumes counting up.
• Freerun mode: In free-run mode, when a compare event occurs, it has no effect on the counter
value. The counter continues counting until 0xFFFFFFFF is reached and then it is reset to
0x00000000 and resumes counting.
14.2
Programming Model
The General-Purpose Timer modules each have six user-accessible 32-bit registers. They are shown with
offsets from their respective base addresses in the detailed register descriptions.
Table 14-1 summarizes the general-purpose timer registers and their addresses. Table 14-2 provides the
detailed register summary.
Table 14-1. GP Timer Register Summary
Description
Name
Address
GPT Control Register 1
TCTL1
0x10003000
GPT Control Register 2
TCTL2
0x10004000
GPT Control Register 3
TCTL3
0x10005000
GPT Prescaler Register 1
TPRER1
0x10003004
GPT Prescaler Register 2
TPRER2
0x10004004
GPT Prescaler Register 3
TPRER3
0x10005004
GPT Compare Register 1
TCMP1
0x10003008
GPT Compare Register 2
TCMP2
0x10004008
GPT Compare Register 3
TCMP3
0x10005008
GPT Capture Register 1
TCR1
0x1000300C
GPT Capture Register 2
TCR2
0x1000400C
GPT Capture Register 3
TCR3
0x1000500C
GPT Counter Register 1
TCN1
0x10003010
GPT Counter Register 2
TCN2
0x10004010
GPT Counter Register 3
TCN3
0x10005010
GPT Status Register 1
TSTAT1
0x10003014
GPT Status Register 2
TSTAT2
0x10004014
GPT Status Register 3
TSTAT3
0x10005014
i.MX21 Reference Manual, Rev. 3
14-4
Freescale Semiconductor
General-Purpose Timers (GPT)
.
Name
TCTL1
R
(0x10003000)
W
TCTL2
(0x10004000) R
TCTL3
(0x10005000) W
TPRER1
R
(0x10003004)
W
TPRER2
(0x10004004) R
TPRER3
(0x10005004) W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CC
OM
FRR
CAPT
EN
COMP
EN
0
0
0
0
0
0
0
0
0
CAP
SWR
0
0
0
0
0
0
0
0
0
0
0
0
TEN
PRESCALER
TCMP1
R
(0x10003008)
W
TCMP2
(0x10004008) R
TCMP3
(0x10005008) W
COMPARE VALUE
COMPARE VALUE
TCR1
R
(0x1000300c)
W
TCR2
(0x1000400c) R
TCR3
(0x1000500c) W
CAPTURE VALUE
TCN1
R
(0x10003010)
W
TCN2
(0x10004010) R
TCN3
(0x10005010) W
COUNTER VALUE
TSTAT1
R
(0x10003014)
W
TSTAT2
(0x10004014) R
TSTAT3
(0x10005014) W
CLK SOURCE
CAPTURE VALUE
COUNTER VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CAPT
COMP
W1C
W1C
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
14-5
General-Purpose Timers (GPT)
14.2.1
GPT Control Register
The GPT control (TCTL) register controls the overall operation of the timer.
TCTL1
TCTL2
TCTL3
GPT Control Register 1
GPT Control Register 2
GPT Control Register 3
0x10003000
0x10004000
0x10005000
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CC
OM
FRR
SWR
CAP
CAPT EN COMP EN
CLK SOURCE
TEN
TYPE
slfclr
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 14-2. GPT Control Registers 1, 2, and 3 Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should not be used.
SWR
Bit 15
SOFTWARE RESET—GPT is reset when this bit is set to 1. This bit 0 = GPT is not reset
is set when the module is in reset state and is cleared when the reset 1 = GPT is reset
procedure is over. The reset signal is asserted 2 clock cycles
(IPG_CLK) after this bit is set and the reset remains asserted for 3
clock cycles. The whole reset procedure is complete 5 clock cycles
after this bit is asserted
This software reset does not reset the TEN bit.
Reserved
Bits 14–11
Reserved—These bits are reserved and should not be used.
CC
Bit 10
Counter Clear—This bit determines whether the counter is to be
cleared when TEN=0 (timer disabled).
0= counter is halted at the current count
when TEN = 0.
1 = counter will be reset when TEN=0.
OM
Bit 9
Output Mode—This bit controls the output mode of the timer after
compare event occurs.
0 = Active-low pulse for one clock
period.
1 = Toggle output.
FRR
Bit 8
Free-Run / Restart—This bit controls how the timer operates after
a compare event occurs. In free-run mode, the timer continues
counting till 0xffffffff. In restart mode, the counter resets to
0x00000000 and resumes counting.
0 = Restart mode
1 = Free-run mode
i.MX21 Reference Manual, Rev. 3
14-6
Freescale Semiconductor
General-Purpose Timers (GPT)
Table 14-2. GPT Control Registers 1, 2, and 3 Description
Name
Description
Settings
CAP
Bits 7–6
Capture Edge—This field controls the operation of the capture
00 = Capture function disabled
function. The value in the counter is loaded into the Capture register 01 = Capture on rising edge and
on the detection of an event on the TIN pin. The event which will
generate interrupt
trigger this capture is determined by this field.
10 = Capture on falling edge and
generate interrupt
11 = Capture on rising or falling edge
and generate interrupt
CAPT EN
Bit 5
Capture Interrupt Enable—This bit enables the capture interrupt.
0 = Capture interrupt disabled.
1 = Capture interrupt enabled.
COMP EN
Bit 4
Compare Interrupt Enable—This bit enables the compares
interrupt.
0 = Compare interrupt disabled.
1 = Compare interrupt enabled.
CLKSOURCE
Bits 3–1
Clock Source—This field controls the source of the clock to the
prescaler. The stop-count freezes the timer at its current value.
Note: This field value should only be changed when the GPT is
disabled.
000 = Stop count (clock disabled).
001 = PERCLK1 to prescaler.
010 = PERCLK1 divided by 4 to
prescaler.
011 = TIN to prescaler.
1xx = 32kHz clock to prescaler.
TEN
Bit 0
Timer Enable—TEN bit enables the general-purpose timer. The bit 0 = Timer is disabled
can be cleared either by writing 0 or by a hardware reset. The bit
1 = Timer is enabled.
cannot be cleared by asserting the software reset.
14.2.2
GPT Prescaler Register
The GPT prescaler register (TPRER) controls the divide value of the prescaler.
.
TPRER1
TPRER2
TPRER3
GPT Prescaler Register 1
GPT Prescaler Register 2
GPT Prescaler Register 3
0x10003004
0x10004004
0x10005004
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PRESCALER
TYPE
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
14-7
General-Purpose Timers (GPT)
Table 14-3. GPT Prescaler Register 1, 2, and 3 Description
Name
Description
Settings
Reserved
Bits 31–11
Reserved—These bits are reserved and should read 0.
PRESCALER
Bits 10–0
Counter Clock Prescaler—This field determines the division value of the
0x00 = Divide by 1
prescaler between 1 and 2048. 0x00 divides by 1 and 0x7FF divides by 2048. ...
0x7ff = Divide by 2048
14.2.3
GPT Compare Register
The GPT compare (TCMP) register contains the value that is compared with the free-running counter. A
compare event is generated when the counter matches the value in this register. This register reset to
0xFFFFFFFF.
TCMP1
TCMP2
TCMP3
BIT
GPT Compare Register 1
GPT Compare Register 2
GPT Compare Register 3
31
30
29
28
27
26
25
24
0x10003008
0x10004008
0x10005008
23
22
21
20
19
18
17
16
COMPARE VALUE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
COMPARE VALUE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 14-4. GPT Compare Registers 1, 2, and 3 Description
Name
COMPARE
Bits 31–0
Description
Compare Value—A compare event occurs when the counter value matches the value in this field.
i.MX21 Reference Manual, Rev. 3
14-8
Freescale Semiconductor
General-Purpose Timers (GPT)
14.2.4
GPT Capture Register
This register is read only, and resets to 0x00000000. The GPT capture register (TCR) stores the counter
value when a capture event occurs.
TCR1
TCR2
TCR3
BIT
GPT Capture Register 1
GPT Capture Register 2
GPT Capture Register 3
31
30
29
28
27
26
25
24
0x1000300C
0x1000400C
0x1000500C
23
22
21
20
19
18
17
16
CAPTURE VALUE
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CAPTURE VALUE
Table 14-5. GPT Capture Registers 1, 2, and 3 Description
Name
Description
CAPTURE
Bits 31–0
14.2.5
Capture Value—This field stores the counter value at the time of a capture event.
GPT Counter Register
The read-only GPT counter (TCN) register can be read at anytime without disturbing the current count.
TCN1
TCN2
TCN3
BIT
GPT Counter Register 1
GPT Counter Register 2
GPT Counter Register 3
31
30
29
28
27
26
25
24
0x10003010
0x10004010
0x10005010
23
22
21
20
19
18
17
16
COUNTER VALUE
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
COUNTER VALUE
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 14-6. GPT Counter Registers 1, 2, and 3 Description
Name
COUNT
Bits 31–0
Description
Count Value—This field contains the current count value.
Whenever there is an update of compare register the counter is reset to zero and the count starts afresh.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
14-9
General-Purpose Timers (GPT)
14.2.6
GPT Status Register
The GPT status (TSTAT) register (write 1 to clear) indicates the GPT’s status. When a capture event occurs,
the CAPT bit is set. When a compare event occurs, the COMP bit is set. These bits can only be cleared by
writing 1 to clear the interrupt status.
TSTAT1
TSTAT2
TSTAT3
GPT Status Register 1
GPT Status Register 2
GPT Status Register 3
0x10003014
0x10004014
0x10005014
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CAPT
COMP
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
W1C
W1C
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 14-7. GPT Status Registers 1, 2, and 3 Description
Name
Description
Settings
Reserved
Bits 31–2
Reserved—These bits are reserved and should read 0.
CAPT
Bit 1
Capture Event—This bit indicates that a capture event has
occurred.
0 = No capture event
1 = A capture event has occurred
COMP
Bit 0
Compare Event—This bit indicates that a compare event has
occurred.
0 = No compare event
1 = A compare event has occurred
i.MX21 Reference Manual, Rev. 3
14-10
Freescale Semiconductor
Chapter 15
General-Purpose I/O (GPIO)
The GPIO module in i.MX21 provides six general purpose I/O (GPIO) ports (PA, PB, PC, PD, PE and PF).
Each single GPIO port is a 32-bit port that may be multiplexed with one or more dedicated functions.
This chapter contains the description of the top level I/O multiplexing strategy in the i.MX21 which
consists of two parts:
• Software controllable multiplexing done in the GPIO module
• Hardware multiplexing by the IOMUX module
The I/O multiplexing strategy is designed to configure the inputs and outputs of the i.MX21 chip in
different modes. It allows a user to use the same I/O pad for alternative purposes of the chip. The design
of I/O multiplexer is targeted to be as flexible as possible. Please refer to chapter 2, “Signal Descriptions
and Pin Assignments” for detailed I/O multiplexing information.
Figure 15-1 shows the block diagram of the GPIO and IOMUX modules partition at the top level of
i.MX21. Make note that the signals A_IN, B_IN, C_IN, A_OUT and B_OUT are internal signals and do
not represent individual port signals. Figure 15-2 on page 15-2 shows a block diagram of an individual port
of the GPIO module.
IOMUX (Part of GPIO)
Primary Function
1
GP
GOUT
B_IN
1
GPIO
INUSE
Pin
I/O
C_IN
0
GDIR
1
MUX
A_IN
0
MUX
Alternate Function
MUX
0
A_OUT
B_OUT
PUEN
GIN
Figure 15-1. Functional Block Diagram of GPIO
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
15-1
General-Purpose I/O (GPIO)
OCR1
OCR2
DDIR[i]
G_DIR[31:0]
A_IN[i]
G_DIR[i]
G_OUT[i]
MUX
B_IN[i]
C_IN[i]
PAD
i
G_IN[i]
DR
ICONFA1
SSR
ICONFA2
ISR[i]
1’b0
1’b1
MUX
A_OUT[i]
Interrupt
Module
ISR
ICONFB1
ICONFB2
MUX
ISR[i]
1’b0
1’b1
B_OUT[i]
ICR1
ICR2
IMR
GP
IN_USE_RESET_SEL [31:0]
GPR[31:0]
GIUS
IN_USE[31:0]
PUEN
PUEN[31:0]
Figure 15-2. GPIO Block Diagram for an Individual Port
15.1
Overview
The GPIO module provides General Purpose I/O capability to the device. Each I/O port can be programed
as either a general purpose input or general purpose output. Besides GPIO functionality, pins can be
changed from their default dedicated functions to alternate functions. Input and output signals of
peripherals are connected to the IOMUX module at the dedicated (primary) or alternate inputs. In the
output direction, one out of three alternate sources (originating from peripherals) can be selected. From the
input direction, one out of two alternate destinations (input to a peripheral) can be selected.
15.2
GPIO Features
The following list contains the GPIO features.
• Six 32-bit ports. Each with direction-configurable pins.
i.MX21 Reference Manual, Rev. 3
15-2
Freescale Semiconductor
General-Purpose I/O (GPIO)
•
•
•
•
•
•
•
•
•
•
15.3
Software control for input/output pin configuration through 32-bit direction register.
Software control for multiplexing one out of four different sources for every output. Three of them
are functional pins from internal modules while the fourth is from the data register of the module
Software control for routing of every input to two different destinations.
Input data can be sampled to the data register.
Inputs can be internally tied to a logic 1 or 0 to ensure any transitions attempted to be processed
are ignored.
One 32-bit general purpose register is dedicated to each GPIO port. These registers may be used
for software control of IOMUX block of the GPIO.
Every input is configurable as an interrupt and each interrupt can be defined as either:
— rising-edge triggered
— falling-edge triggered
— level sensitive
The interrupts can be masked using a 32-bit mask register.
Two levels of interrupt masking are provided. Interrupts can be individually masked at the bit level
or at the port level.
Software reset function: when the SWR bit (SWR register, 0 bit) is written as a 1, the entire GPIO
module is reset immediately, and this reset signal is asserted for 3 system cycles. After this, the
reset signal will be released automatically.
External Signals Description
Please refer to chapter 2, “Signal Descriptions and Pin Assignments” for details of the I/O multiplexing
scheme and external connection to the GPIO module.
15.4
Interrupts
Every external input passes through the interrupt module in the GPIO module. Inside this module, the
interrupts may be defined as rising-edge triggered, or falling-edge triggered. Each interrupt can be masked
and also be designated as a high-level interrupt, or a low-level sensitive interrupt. The interrupt status
register bits corresponding to the interrupts waiting for service are stored as a value of 1. The interrupt
status register is Write 1 to Clear (w1c). The user is responsible for clearing the interrupt status register bit
after it has been serviced.
15.5
Programming Model
GPIO has six ports and each port has 17 registers. In total, the GPIO has 102 registers. The registers, other
than the Sample Status Register (SSR) and the Interrupt Status Register (ISR), have both read and write
capability. The Sample Status Register is a read only register, while the Interrupt Status Register is a w1c
register; the register can be read, but writing a 1 to any register bit clears the bit. Writing a value of 0 to
the bit has no effect.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
15-3
General-Purpose I/O (GPIO)
While there are six GPIO ports, each capable of representing 32 GPIO configurable pins as inputs or
outputs, not all bits are mapped to a pin and hence these bits do not have any effect and are marked as
reserved. These reserved bits are indicated in the Section 15.5.9, “GPIO IN USE Register (GIUS).”
In Table 15-1shows the absolute address of each memory mapped register.
Table 15-1. GPIO Register Summary
Description
Data Direction Register (DDIR)
Name
Address
PTA_DDIR
0x1001 5000
–
PTB_DDIR
0x1001 5100
–
PTC_DDIR
0x1001 5200
–
PTD_DDIR
0x1001 5300
–
PTE_DDIR
0x1001 5400
–
PTF_DDIR
0x1001 5500
PTA_OCR1
0x1001 5004
–
PTB_OCR1
0x1001 5104
–
PTC_OCR1
0x1001 5204
–
PTD_OCR1
0x1001 5304
–
PTE_OCR1
0x1001 5404
–
PTF_OCR1
0x1001 5504
Output Configuration Register 1 (OCR1)
Output Configuration Register 2 (OCR2)
PTA_OCR2
0x1001 5008
–
PTB_OCR2
0x1001 5108
–
PTC_OCR2
0x1001 5208
–
PTD_OCR2
0x1001 5308
–
PTE_OCR2
0x1001 5408
–
PTF_OCR2
0x1001 5508
PTA_ICONFA1
0x1001 500c
–
PTB_ICONFA1
0x1001 510c
–
PTC_ICONFA1
0x1001 520c
–
PTD_ICONFA1
0x1001 530c
–
PTE_ICONFA1
0x1001 540c
–
PTF_ICONFA1
0x1001 550c
Input Configuration Register A1 (ICONFA1)
Input Configuration Register A2 (ICONFA2)
PTA_ICONFA2
0x1001 5010
–
PTB_ICONFA2
0x1001 5110
–
PTC_ICONFA2
0x1001 5210
–
PTD_ICONFA2
0x1001 5310
–
PTE_ICONFA2
0x1001 5410
–
PTF_ICONFA2
0x1001 5510
i.MX21 Reference Manual, Rev. 3
15-4
Freescale Semiconductor
General-Purpose I/O (GPIO)
Table 15-1. GPIO Register Summary (continued)
Description
Name
Address
PTA_ICONFB1
0x1001 5014
–
PTB_ICONFB1
0x1001 5114
–
PTC_ICONFB1
0x1001 5214
–
PTD_ICONFB1
0x1001 5314
–
PTE_ICONFB1
0x1001 5414
–
PTF_ICONFB1
0x1001 5514
PTA_ICONFB2
0x1001 5018
–
PTB_ICONFB2
0x1001 5118
–
PTC_ICONFB2
0x1001 5218
–
PTD_ICONFB2
0x1001 5318
–
PTE_ICONFB2
0x1001 5418
–
PTF_ICONFB2
0x1001 5518
PTA_DR
0x1001 501c
–
PTB_DR
0x1001 511c
–
PTC_DR
0x1001 521c
–
PTD_DR
0x1001 531c
–
PTE_DR
0x1001 541c
–
PTF_DR
0x1001 551c
PTA_GIUS
0x1001 5020
–
PTB_GIUS
0x1001 5120
–
PTC_GIUS
0x1001 5220
–
PTD_GIUS
0x1001 5320
–
PTE_GIUS
0x1001 5420
–
PTF_GIUS
0x1001 5520
PTA_SSR
0x1001 5024
–
PTB_SSR
0x1001 5124
–
PTC_SSR
0x1001 5224
–
PTD_SSR
0x1001 5324
–
PTE_SSR
0x1001 5424
–
PTF_SSR
0x1001 5524
PTA_ICR1
0x1001 5028
–
PTB_ICR1
0x1001 5128
–
PTC_ICR1
0x1001 5228
–
PTD_ICR1
0x1001 5328
–
PTE_ICR1
0x1001 5428
–
PTF_ICR1
0x1001 5528
PTA_ICR2
0x1001 502c
–
PTB_ICR2
0x1001 512c
–
PTC_ICR2
0x1001 522c
–
PTD_ICR2
0x1001 532c
–
PTE_ICR2
0x1001 542c
–
PTF_ICR2
i.MX21 Reference Manual, Rev. 3
0x1001 552c
Input Configuration Register B1 (ICONFB1)
Input Configuration Register B2 (ICONFB2)
Data Register (DR)
GPIO In Use Register (GIUS)
Sample Status Register (SSR)
Interrupt Configuration Register 1 (ICR1)
Interrupt Configuration Register 2 (ICR2)
Freescale Semiconductor
15-5
General-Purpose I/O (GPIO)
Table 15-1. GPIO Register Summary (continued)
Description
Name
Address
PTA_IMR
0x1001 5030
–
PTB_IMR
0x1001 5130
–
PTC_IMR
0x1001 5230
–
PTD_IMR
0x1001 5330
–
PTE_IMR
0x1001 5430
–
PTF_IMR
0x1001 5530
PTA_ISR
0x1001 5034
–
PTB_ISR
0x1001 5134
–
PTC_ISR
0x1001 5234
–
PTD_ISR
0x1001 5334
–
PTE_ISR
0x1001 54 34
Interrupt Mask Register (IMR)
Interrupt Status Register (ISR)
–
PTF_ISR
0x1001 5534
PTA_GPR
0x1001 5038
–
PTB_GPR
0x1001 5138
–
PTC_GPR
0x1001 5238
–
PTD_GPR
0x1001 5338
–
PTE_GPR
0x1001 5438
–
PTF_GPR
0x1001 5538
PTA_SWR
0x1001 503c
–
PTB_SWR
0x1001 513c
–
PTC_SWR
0x1001 523c
–
PTD_SWR
0x1001 533c
–
PTE_SWR
0x1001 543c
General Purpose Register (GPR)
Software Reset Register (SWR)
–
PTF_SWR
0x1001 553c
PTA_PUEN
0x1001 5040
–
PTB_PUEN
0x1001 5140
–
PTC_PUEN
0x1001 5240
–
PTD_PUEN
0x1001 5340
–
PTE_PUEN
0x1001 5440
–
PTF_PUEN
0x1001 5540
PMASK
0x1001 5600
Pull_Up Enable Register (PUEN)
GPIO Port Interrupt Mask (PMASK)
i.MX21 Reference Manual, Rev. 3
15-6
Freescale Semiconductor
General-Purpose I/O (GPIO)
15.5.1
Data Direction Register
The data direction registers determine whether each pin of the port is an input or an output pin.
Data Direction Registers
Addr
0x10015000
0x10015100
0x10015200
0x10015300
0x10015400
0x10015500
PTA_DDIR
PTB_DDIR
PTC_DDIR
PTD_DDIR
PTE_DDIR
PTF_DDIR
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DDIR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DDIR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 15-2. Data Direction Register Description
Name
DDIR
Bits 31–0
Description
Settings
Data Direction—This is a read/write register which defines the current direction of 0 = Pin number i is input
the 32 pins of a port in the GPIO module.
1 = Pin number i is output
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
15-7
General-Purpose I/O (GPIO)
15.5.2
Output Configuration Register 1 (OCR1)
Each port consists of 32-pins. Because the output configuration for each pin is described using a two-bit
combination the output configuration of the pins is controlled by two identical 32-bit registers (OCR1 and
OCR2). The Output Configuration register 1 (OCR1) configures the output signal for lower 16 pins (0–15)
of the associated port.
Output Configuration Register 1
Addr
0x10015004
0x10015104
0x10015204
0x10015304
0x10015404
0x10015504
PTA_OCR1
PTB_OCR1
PTC_OCR1
PTD_OCR1
PTE_OCR1
PTF_OCR1
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OCR1
pin 15
pin 14
pin 13
pin 12
pin 11
pin 10
pin 9
pin 8
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OCR1
pin 7
pin 6
pin 5
pin 4
pin 3
pin 2
pin 1
pin 0
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 15-3. Output Configuration Register 1 Description
Name
OCR1
Bits 31–0
Description
Output Configuration Register 1—This is a read/write register that
selects how each pin (0–15) is used as an output by the GPIO.
Settings
OCR1
[2i +1]
OCR1
[2i]
Output Selected
0
0
Input A_IN[i]
0
1
Input B_IN[i]
1
0
Input C_IN[i]
1
1
Data Register [i]
i.MX21 Reference Manual, Rev. 3
15-8
Freescale Semiconductor
General-Purpose I/O (GPIO)
15.5.3
Output Configuration Register 2 (OCR2)
The Output Configuration register 2 (OCR2) specifies the output signal for upper 16 pins (16-31) of the
associated port. The output configuration for each pin is described with a two-bit combination.
Output Configuration Register 2
Addr
0x10015008
0x10015108
0x10015208
0x10015308
0x10015408
0x10015508
PTA_OCR2
PTB_OCR2
PTC_OCR2
PTD_OCR2
PTE_OCR2
PTF_OCR2
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OCR2
pin 31
pin 30
pin 29
pin 28
pin 27
pin 26
pin 25
pin 24
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OCR2
pin 23
pin 22
pin 21
pin 20
pin 19
pin 18
pin 17
pin 16
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 15-4. Output Configuration Register 2 Description
Name
OCR2
Bits 31–0
Description
Output Configuration Register 2—This is a read/write register
that selects how each pin (16–31) is used as an output by the
GPIO.
Settings
OCR2
[2i - 32 +1]
OCR2
[2i - 32]
Output Selected
0
0
Input A_IN[i]
0
1
Input B_IN[i]
1
0
Input C_IN[i]
1
1
Data Register [i]
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
15-9
General-Purpose I/O (GPIO)
15.5.4
Input Configuration Register A1 (ICONFA1)
The input configuration registers (ICONFA1) specify the signal or value driven to the A_OUT signals that
is connected to internal modules of the i.MX21. Each port pin is defined by two bits in the input
configuration registers. Please refer to Chapter 2, “Signal Descriptions and Pin Assignments,” for detailed
I/O pin information.
Input Configuration Register A1
Addr
0x1001500C
0x1001510C
0x1001520C
0x1001530C
0x1001540C
0x1001550C
PTA_ICONFA1
PTB_ICONFA1
PTC_ICONFA1
PTD_ICONFA1
PTE_ICONFA1
PTF_ICONFA1
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ICONFA1
pin 15
pin 14
pin 13
pin 12
pin 11
pin 10
pin 9
pin 8
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICONFA1
pin 7
pin 6
pin 5
pin 4
pin 3
pin 2
pin 1
pin 0
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 15-5. Input Configuration Register A1 Description
Name
ICONFA1
Bits 31–0
Description
Settings
Input Configuration—Corresponds to port pins
0–15 and defines which one of the four options is
driven to A_OUT [i]. Each port pin [i] (i = 0–15)
requires two ICONFA1 bits to determine the input
value.
ICONFA1
[2i +1]
ICONFA1
[2i]
Output selected
0
0
GPIO_In [i]
0
1
Interrupt Status register [i]
1
0
0
1
1
1
i.MX21 Reference Manual, Rev. 3
15-10
Freescale Semiconductor
General-Purpose I/O (GPIO)
15.5.5
Input Configuration Register A2 (ICONFA2)
The input configuration registers (ICONFA2) specify the signal or value driven to the A_OUT signals
connected to internal modules. There are two bits in the input configuration registers for each port pin.
Please refer to Chapter 2, “Signal Descriptions and Pin Assignments,” for detail I/O pin information.
Input Configuration Register A2
Addr
0x10015010
0x10015110
0x10015210
0x10015310
0x10015410
0x10015510
PTA_ICONFA2
PTB_ICONFA2
PTC_ICONFA2
PTD_ICONFA2
PTE_ICONFA2
PTF_ICONFA2
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ICONFA2
pin 31
pin 30
pin 29
pin 28
pin 27
pin 26
pin 25
pin 24
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICONFA2
pin 23
pin 22
pin 21
pin 20
pin 19
pin 18
pin 17
pin 16
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 15-6. Input Configuration Register A2 Description
Name
ICONFA2
Bits 31–0
Description
Settings
Input Configuration—Corresponds to pins 16–31
of the port and defines which one of the four options
is driven to a_OUT [i]. Each port pin [i] (i = 16 through
31) requires two ICONFA2 bits to determine the
input value.
ICONFA2
[2i +1]
ICONFA2
[2i]
Output selected
0
0
GPIO_In [i]
0
1
Interrupt Status register [i]
1
0
0
1
1
1
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
15-11
General-Purpose I/O (GPIO)
15.5.6
Input Configuration Register B1 (ICONFB1)
The input configuration registers ICONFB1 specify the signal or value driven to the B_OUT signals
connected to internal modules. There are two bits in the input configuration registers for each port pin.
Please refer to Chapter 2, “Signal Descriptions and Pin Assignments,” for detail I/O pin information.
Input Configuration Register B1
Addr
0x10015014
0x10015114
0x10015214
0x10015314
0x10015414
0x10015514
PTA_ICONFB1
PTB_ICONFB1
PTC_ICONFB1
PTD_ICONFB1
PTE_ICONFB1
PTF_ICONFB1
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ICONFB1
pin 15
pin 14
pin 13
pin 12
pin 11
pin 10
pin 9
pin 8
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICONFB1
pin 7
pin 6
pin 5
pin 4
pin 3
pin 2
pin 1
pin 0
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 15-7. Input Configuration Register B1 Description
Name
ICONFB1
Bits 31–0
Description
Input Configuration—Corresponds to pins 0–15 of
the port and defines which one of the four options is
driven to b_OUT [i]. Each port pin [i] (i = 0 through 15)
requires two ICONFB1 bits to determine the input
value.
Settings
ICONFB1
[2i +1]
ICONFB1
[2i]
Output selected
0
0
GPIO_In[i]
0
1
Interrupt Status register [i]
1
0
0
1
1
1
i.MX21 Reference Manual, Rev. 3
15-12
Freescale Semiconductor
General-Purpose I/O (GPIO)
15.5.7
Input Configuration Register B2 (ICONFB2)
The input configuration registers ICONFB2 specify the signal or value driven to the B_OUT signals
connected to internal modules. There are two bits in the input configuration registers for each port pin.
Please refer to Chapter 2, “Signal Descriptions and Pin Assignments,” for detail I/O pin information.
Input Configuration Register B2
Addr
0x10015018
0x10015118
0x10015218
0x10015318
0x10015418
0x10015518
PTA_ICONFB2
PTB_ICONFB2
PTC_ICONFB2
PTD_ICONFB2
PTE_ICONFB2
PTF_ICONFB2
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ICONFB2
pin 31
pin 30
pin 29
pin 28
pin 27
pin 26
pin 25
pin 24
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICONFB2
pin 23
pin 22
pin 21
pin 20
pin 19
pin 18
pin 17
pin 16
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 15-8. Input Configuration Register B2 Description
Name
ICONFB2
Bits 31–0
Description
Settings
Input Configuration—Corresponds to pins 16–31
of the port and defines which one of the four options
is driven to b_OUT [i]. Each port pin [i] (i = 16
through 31) requires two ICONFB2 bits to
determine the input value.
ICONFB2
[2i - 32 +1]
ICONFB2
[2i - 32]
Output selected
0
0
GPIO_In[i]
0
1
Interrupt Status register [i]
1
0
0
1
1
1
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
15-13
General-Purpose I/O (GPIO)
15.5.8
Data Register (DR)
The Data Register holds data for output from an associated port when a pin is configured as an output and
the Data Register is chosen using Output Configuration Register 1 and Output Configuration Register 2.
Data Register
ADDR
0x1001501c
0x1001511c
0x1001521c
0x1001531c
0x1001541c
0x1001551c
PTA_DR
PTB_DR
PTC_DR
PTD_DR
PTE_DR
PTF_DR
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DR
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DR
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 15-9. Data Register Description
Name
DR
Bits 31–0
Description
Data Register—Contains the GPIO output values when the Output
Configuration Registers select the Data Register as the output for the pin
(selection 11).
Settings
0 = Drives the output signal low
1 = Drives the output signal high
i.MX21 Reference Manual, Rev. 3
15-14
Freescale Semiconductor
General-Purpose I/O (GPIO)
15.5.9
GPIO IN USE Register (GIUS)
The GPIO In Use Registers control a multiplexer in the IOMUX module. The settings in these registers
choose whether a pin is utilized for a peripheral function or for its GPIO function. If the register is set to
a zero for a corresponding pin, then this register is used in conjunction with the GPR register to control the
peripheral functionality. Reset values for individual registers are shown in the following sections
GPIO In Use Register
Addr
0x10015020
0x10015120
0x10015220
0x10015320
0x10015420
0x10015520
PTA_GIUS
PTB_GIUS
PTC_GIUS
PTD_GIUS
PTE_GIUS
PTF_GIUS
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
GIUS
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
6
5
4
3
2
1
0
Reset Value—INUSE_RESET_SEL[31:16]
Bit
15
14
13
12
11
10
9
8
7
GIUS
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
Reset Value—INUSE_RESET_SEL[15:0]
Table 15-10. GPIO In Use Register Description
Name
GIUS
Bits 31–0
Description
GPIO In Use—Informs the IOMUX module whether the port pin is
utilized for its GPIO function. When the pin is utilized for its GPIO
function, the multiplexed functions are not available.
The reset value of this register is determined by the input value of the
signal INUSE_RESET_SEL [31:0].
Settings
0 = Pin utilized for multiplexed function
1 = Pin utilized for GPIO function
The following sections describe the GPIO In Use (GIUS) reset values for the various ports. Additionally,
the registers also indicate the reserved bits (unimplemented GPIO bits) of the GPIO ports.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
15-15
General-Purpose I/O (GPIO)
15.5.9.1
GPIO IN USE Register A (PTA_GIUS)
The reset value of the PTA_GIUS register is (0xFFFF_FFE0).
GPIO In Use Register A
Addr
0x10015020
PTA_GIUS
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
GIUS
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
GIUS
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
1
1
1
1
1
1
1
1
1
1
1
15.5.9.2
Reserved
0
0
0
GPIO IN USE Register B (PTB_GIUS)
The reset value of the PTB_GIUS register is (0xFF3F_FFF0).
GPIO In Use Register B
Addr
0x10015120
PTB_GIUS
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
GIUS
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GIUS
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
1
1
1
1
1
1
1
1
1
1
1
1
Reserved
0
0
0
0
i.MX21 Reference Manual, Rev. 3
15-16
Freescale Semiconductor
General-Purpose I/O (GPIO)
15.5.9.3
GPIO IN USE Register C (PTC_GIUS)
The reset value of the PTC_GIUS register is (0xFFFF_FFE0).
GPIO In Use Register C
Addr
0x10015220
PTC_GIUS
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
GIUS
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
GIUS
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
1
1
1
1
1
1
1
1
1
1
1
15.5.9.4
Reserved
0
0
0
GPIO IN USE Register D (PTD_GIUS)
The reset value of the PTD_GIUS register is (0xFFFE_0000).
GPIO In Use Register D
Addr
0x10015320
PTD_GIUS
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
GIUS
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reser
ved
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
GIUS
Type
Reset
Reserved
0
0
0
0
0
0
0
0
0
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
15-17
General-Purpose I/O (GPIO)
15.5.9.5
GPIO IN USE Register E (PTE_GIUS)
The reset value of the PTE_GIUS register is (0x00FC_0F20).
GPIO In Use Register E
Addr
0x10015420
PTE_GIUS
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
GIUS
Type
Reserved
Reset
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GIUS
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
0
17
16
15.5.9.6
GPIO IN USE Register F (PTF_GIUS)
The reset value of the PTF_GIUS register is (0x0060_0000).
PTF_GIUS
Bit
GPIO In Use Register F
31
30
29
28
27
26
25
24
23
Addr
0x10015520
22
21
rw
rw
20
19
18
GIUS
Type
Reserved
Reserved
rw
Reset
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GIUS
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
i.MX21 Reference Manual, Rev. 3
15-18
Freescale Semiconductor
General-Purpose I/O (GPIO)
15.5.10 Sample Status Register (SSR)
The read-only Sample Status Registers contain the value of the GPIO pins for each associated port. The
register is updated on every clock tick. The contents are used as a status indicator when the pins are
configured as inputs.
Sample Status Register
Addr
0x10015024
0x10015124
0x10015224
0x10015324
0x10015424
0x10015524
PTA_SSR
PTB_SSR
PTC_SSR
PTD_SSR
PTE_SSR
PTF_SSR
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SSR
Type
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSR
Type
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 15-11. Sample Status Register Description
Name
SSR
Bits 31–0
Description
Settings
Sample Status—Contains the value of the GPIO pin [i]. It is sampled on every clock. 0 = Pin value is low
1 = Pin value is high
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
15-19
General-Purpose I/O (GPIO)
15.5.11 Interrupt Configuration Register 1 (ICR 1)
This register specifies the external interrupt configuration for each of the lower 16 interrupts of a port.
There are two bits in the register for each port pin.
Interrupt Configuration Register 1
Addr
0x10015028
0x10015128
0x10015228
0x10015328
0x10015428
0x10015528
PTA_ICR1
PTB_ICR1
PTC_ICR1
PTD_ICR1
PTE_ICR1
PTF_ICR1
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ICR1
pin 15
pin 14
pin 13
pin 12
pin 11
pin 10
pin 9
pin 8
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICR1
pin 7
pin 6
pin 5
pin 4
pin 3
pin 2
pin 1
pin 0
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 15-12. Interrupt Configuration Register 1 Description
Name
ICR1
Bits 31–0
Description
Interrupt Configuration—Corresponds to interrupts
0–15 of the port and defines which one of the four options
is the sensitivity of the interrupt. Each interrupt [i] (i= 0
through 15) requires two ICR1 bits to determine the
sensitivity.
Settings
ICR1 [2i +1]
ICR1 [2i]
Sensitivity selected
0
0
Rising edge sensitive
0
1
Falling edge sensitive
1
0
High level sensitive
1
1
Low level sensitive
i.MX21 Reference Manual, Rev. 3
15-20
Freescale Semiconductor
General-Purpose I/O (GPIO)
15.5.11.1 Interrupt Configuration Register 2 (ICR 2)
This register specify the external interrupt configuration for each of the upper 16 interrupts of the port.
There are two bits in the register for each port pin.
Interrupt Configuration Register 2
Addr
0x1001502c
0x1001512c
0x1001522c
0x1001532c
0x1001542c
0x1001552c
PTA_ICR2
PTB_ICR2
PTC_ICR2
PTD_ICR2
PTE_ICR2
PTF_ICR2
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ICR2
Pin
Number
pin 31
pin 30
pin 29
pin 28
pin 27
pin 26
pin 25
pin 24
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICR2
Pin
Number
pin 23
pin 22
pin 21
pin 20
pin 19
pin 18
pin 17
pin 16
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 15-13. Interrupt Configuration Register 2 Description
Name
ICR2
Bits 31–0
Description
Interrupt Configuration—Corresponds to interrupts
16–31 of the port and defines which one of the four
options is the sensitivity of the interrupt. Each
interrupt [i] (i= 16 through 31) requires two ICR2 bits
to determine the sensitivity.
Settings
ICR2
[2i - 32 +1]
ICR2
[2i -32]
Sensitivity selected
0
0
Rising edge sensitive
0
1
Falling edge sensitive
1
0
High level sensitive
1
1
Low level sensitive
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
15-21
General-Purpose I/O (GPIO)
15.5.12 Interrupt Mask Register (IMR)
The Interrupt Mask Registers (IMR) determine if an interrupt will be asserted when an interrupt event
occurs and when the pin and corresponding bit is configured in an interrupt mode. An interrupt is asserted
when corresponding bits in the IMR and ISR are set.
Interrupt Mask Register
Addr
0x10015030
0x10015130
0x10015230
0x10015330
0x10015430
0x10015530
PTA_IMR
PTB_IMR
PTC_IMR
PTD_IMR
PTE_IMR
PTF_IMR
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IMR
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IMR
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 15-14. Interrupt Mask Register Description
Name
IMR
Bits 31–0
Description
Interrupt Mask—Masks the interrupts for this module.
Settings
0 = Interrupt is masked
1 = Interrupt is not masked
i.MX21 Reference Manual, Rev. 3
15-22
Freescale Semiconductor
General-Purpose I/O (GPIO)
15.5.13 Interrupt Status Register (ISR)
The Interrupt Status Registers (ISR) indicate if an interrupt has occurred. When an interrupt event occurs,
the bit in this register is set. The condition necessary to set the bit is determined by the Interrupt
Configuration Registers (ICR) and the inputs satisfying the interrupt condition.
Interrupt Status Register
Addr
0x10015034
0x10015134
0x10015234
0x10015334
0x10015434
0x10015534
PTA_ISR
PTB_ISR
PTC_ISR
PTD_ISR
PTE_ISR
PTF_ISR
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ISR
Type
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ISR
Type
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 15-15. Interrupt Status Register Description
Name
ISR
Bits 31–0
Description
Settings
Interrupt Status—Indicates whether the interrupt [i] has occurred for in the GPIO 0 = Interrupt has not occurred
module. The bits of this register are write 1 to clear.
1 = Interrupt has occurred
The w1c bits will be cleared when a value of 1 is written to the associated bit.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
15-23
General-Purpose I/O (GPIO)
15.5.14 General Purpose Register (GPR)
The General Purpose Registers (GPR) control a multiplexer in the IOMUX module. When the
corresponding bit in the associated GIUS register is set to zero, the settings in these registers determine
whether a pin is utilized for its primary peripheral function or for its alternate peripheral function. When
the corresponding bit in the GIUS is set, the settings of this register have no effect.
PTA_GPR
PTB_GPR
PTC_GPR
PTD_GPR
PTE_GPR
PTF_GPR
Bit
General Purpose Register
31
30
29
28
27
26
25
24
23
Addr
0x10015038
0x10015138
0x10015238
0x10015338
0x10015438
0x10015538
22
21
20
19
18
17
16
GPR
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPR
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 15-16. General Purpose Register Description
Name
GPR
Bits 31–0
Description
Settings
General Purpose Register—Selects between the primary and alternate
0 = Select primary pin function
functions of the pin. When the associated bit in the GIUS register is set, this bit 1 = Select alternate pin function
has no meaning.
Note: Ensure that this bit is cleared when there is no alternate function for a
particular pin.
i.MX21 Reference Manual, Rev. 3
15-24
Freescale Semiconductor
General-Purpose I/O (GPIO)
15.5.15 Software Reset Register (SWR)
The Software Reset Register (SWR) controls the reset of the individual ports in the GPIO module. When
the SWR bit of the Software Reset Register is set, the GPIO circuitry for the individual port resets
immediately.
The total time of the software reset sequence will take six clock cycles. The reset will be asserted from the
third cycle and remains asserted for three clocks.
PTA_SWR
PTB_SWR
PTC_SWR
PTD_SWR
PTE_SWR
PTF_SWR
Software Reset Register
Addr
0x1001503c
0x1001513c
0x1001523c
0x1001533c
0x1001543c
0x1001553c
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Type
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SWR
Type
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
slfclr
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 15-17. Software Reset Register
Name
Description
Reserved
bits 31–1
Reserved—These bits are reserved and should read 0
SWR
Bit 0
Software Reset—Controls software reset of the port. The reset
signal is active for 3 system clock cycles and then it is released
automatically.
Settings
0 = No effect
1 = GPIO circuitry for Port X reset
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
15-25
General-Purpose I/O (GPIO)
15.5.16 Pull-Up Enable Register (PUEN)
The Pull-Up Enable (PUEN) Registers enable or disable a 69 kOhm pull-up resistor on the associated pin.
The pull-up can be applied to any GPIO pin regardless of whether it is configured as primary, alternate or
GPIO function. The pin is tri-stated when the pull-up is disabled and the pin is not driven.
NOTE
Bits 27–24 on Port A (PTA_PUEN) enables or disables a 69 kOhm
pull-down resistor on the associated pin.
Bits 31–28, 26, and 9 on Port B (PTB_PUEN) enables or disables a 69
kOhm pull-down resistor on the associated pin.
Pull-Up Enable Register
Addr
0x10015040
0x10015140
0x10015240
0x10015340
0x10015440
0x10015540
PTA_PUEN
PTB_PUEN
PTC_PUEN
PTD_PUEN
PTE_PUEN
PTF_PUEN
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PUEN
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PUEN
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 15-18. Pull-Up Enable Register Description
Name
PUEN [i]
Bits 31–0
Description
Settings
Pull-Up Enable—Determines whether the corresponding pad is pulled up to 0 = Pin [i] is tri-stated when not
a logic-high or tri-stated. When the pin is configured as an input, clearing this
driven internally or externally
bit causes the signal to be tri-stated when not driven by an external source. 1 = Pin [i] is pulled high1 when not
When the pin is configured as an output, clearing this bit causes the signal to
driven internally or externally
be tri-stated when it is not enabled.
i.MX21 Reference Manual, Rev. 3
15-26
Freescale Semiconductor
General-Purpose I/O (GPIO)
15.5.17 Port Interrupt Mask Register (PMASK)
The GPIO has six ports, each with interrupt generation capability. The PMASK register provides interrupt
masking capability at the port level while the Interrupt Mask Register provides control over individual
interrupts. If a bit is zero, then all interrupts for that port are masked. A software reset on a port (SWR is
set) will clear the corresponding mask bit of the port in this register.
PMASK
Port Interrupt Mask Register
Addr
0x10015600
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Type
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PTF
PTE
PTD
PTC
PTB
PTA
Type
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
Reset
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Table 15-19. Port Interrupt Mask Register Description
Name
Description
Settings
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
PTF
Bit 5
Port F—The bit helps in masking the Port F interrupt. The bit clears during software 0 = Interrupt is masked
reset of Port F.
1 = Interrupt is not masked
PTE
Bit 4
Port E—The bit helps in masking the Port E interrupt. The bit clears during software 0 = Interrupt is masked
reset of Port E.
1 = Interrupt is not masked
PTD
Bit 3
Port D—The bit helps in masking the Port D interrupt. The bit clears during software 0 = Interrupt is masked
reset of Port D.
1 = Interrupt is not masked
PTC
Bit 2
Port C—The bit helps in masking the Port C interrupt. The bit clears during software 0 = Interrupt is masked
reset of Port C.
1 = Interrupt is not masked
PTB
Bit 1
Port B—The bit helps in masking the Port B interrupt. The bit clears during software 0 = Interrupt is masked
reset of Port B.
1 = Interrupt is not masked
PTA
Bit 0
Port A—The bit helps in masking the Port A interrupt. The bit clears during software 0 = Interrupt is masked
reset of Port A.
1 = Interrupt is not masked
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
15-27
General-Purpose I/O (GPIO)
i.MX21 Reference Manual, Rev. 3
15-28
Freescale Semiconductor
Chapter 16
Pulse-Width Modulator (PWM)
The pulse-width modulator (PWM) of the i.MX21 is a 16-bit PWM module which is optimized to generate
sound from stored sample audio images and it can also generate tones. It uses 16-bit resolution and a 4 × 16
data FIFO to generate sound.
The following features characterize the PWM:
• 16-bit resolution
• 4 × 16 FIFO to minimize interrupt overhead
• 2 stage input clock divider (2, 4, 8, 16-divider and 7-bit prescaler)
• Sound and melody generation
• Software reset function
16.1
Operation
The output of the PWM is a toggling signal whose frequency and duty cycle can be modulated by suitable
programming of its registers. It has a 16-bit up counter which counts from 0x0000 until the Counter value
equals the [Value in Period register] + 1. When this match occurs the Counter is reset to 0x0000.
At the beginning of a count period cycle, the PWMO pin is set to one and the counter begins counting up
from 0x0000. The sample value in the Sample FIFO is compared on each count or prescaler clock. When
the sample and count values match, the PWMO signal is cleared to zero. The counter continues counting
until the Period match occurs and subsequently another period cycle begins.
When the PWM is enabled the counter starts running and generates output with the reset values in the
period and sample registers. It is recommended that the programming of these registers be done before
pwm is enabled.
A hardware reset results in all the PWM count and sample registers begin cleared and the FIFO being
flushed. The control register shows that FIFO is empty and FIFO can be written into, and PWM is disabled.
A software reset has the same result and can be given even when the PWM enable bit is off. The clocks
from CRM to PWM should be on for the software reset to be functional.
16.1.1
Clocks
The clock input source is determined by the CLKSRC field of the PWM control register. The CLKSRC
value should only be changed when the PWM is disabled.
The PWM divider divides the selected clock by 2,4,8,16 according to the CLKSEL bits in the control
register. Furthermore the clock can be divided by 1–128 by a prescaler by appropriately setting the
PRESCALE field in the control register.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
16-1
Pulse-Width Modulator (PWM)
The PWM clock gating is done inside the CRM module and the appropriate bit in PCCR register of CRM
should be set for PWM to receive the clocks.
16.1.2
FIFO
Digital sample values can be loaded into the pulse-width modulator as 16-bit words in the same endian
format as the processor is using. The endianess can be changed by suitably using the BCTR and HCTR
bits of the control register. A 4-word(16-bit) FIFO minimizes interrupt overhead. A maskable interrupt is
generated when there are 1 or 0 words in the FIFO, in which case, the software can write three 16-bit
samples into the FIFO.
A write in the sample register results in the value being stored into the FIFO if it is not full. A write when
FIFO is full is ignored and FIFO contents remain unchanged. The FIFO can only be written to when the
PWM is disabled. Attempting to read data written to the FIFO when the PWM is enabled may result in
invalid data.
A read on the sample register yields the current FIFO value being or will be used by PWM for generation
on the output signal. Therefore a write and subsequent read on the sample register may result in different
values being obtained.
16.1.3
Low-Power Mode
In Low Power mode when the clocks are switched off the PWM ceases to count. The counter freezes at its
current value and all PWM operations are ceased.
16.2
Programming Model
The PWM module includes 4 user-accessible 32-bit registers. The Control Register which contains the
control and status bits for configuring and monitoring the PWM.The Sample Register which is the entry
point for the 4 × 16 FIFO and can be read to get the sample value begin used. It determines the duty cycle
of the output signal. The Period Register which determines the period of the output signal. The Counter
Register which can be read to get the present count value.
The Table 16-1 summarizes these registers and their addresses.
i.MX21 Reference Manual, Rev. 3
16-2
Freescale Semiconductor
Pulse-Width Modulator (PWM)
Table 16-1. PWM Register Summary
Name
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
PWMC
(0x10006000) R CLK
W SRC
R
IRQ
PRESCALAR
0
0
0
0
0
RTC
0
0
0
0
IRQ EN
FIFOAV
EN
HCTR BCTR
0
SWR
REPEAT
CLKSEL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
PWMS
(0x10006004) R
SAMPLE
W
R
0
0
0
0
0
0
0
0
0
W
PWMP
(0x10006008) R
PERIOD
W
R
0
0
0
0
0
0
0
0
0
W
PWMCNT
(0x1000600c) R
COUNT
W
16.2.1
PWM Control Register
The pulse-width modulator control register (PWMC) controls how the overall pulse-width modulator
operates. You can also find out the status of the FIFO with this register.
PWMC
BIT
PWM Control Register
31
30
29
28
27
26
25
24
23
0x10006000
22
21
20
19
18
17
16
HCTR BCTR SWR
TYPE
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
rw
rw
r0
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLK SRC
PRESCALAR
IRQ
IRQ EN FIFOAV
EN
REPEAT
CLKSEL
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rtc
rw
r
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
16-3
Pulse-Width Modulator (PWM)
Table 16-2. PWM Control Register Description
Name
Description
Settings
Reserved
Bits 31–19
Reserved—These bits are reserved and should read zero.
HCTR
Bit 18
Half-Word Data Swap Control—This bit determines which half word data from 0 = Half word swapping does
the 32-bit IP-Bus interface is written into the lower 16 bits of the sample register.
not take place
1 = Half words from write data
bus are swapped
BCTR
Bit 17
Byte Data Swap Control—This bit determines the byte ordering of the 16-bit
data when it goes into the FIFO from the sample register.
SWR
Bit 16
Software Reset—PWM is Reset when this bit is set to 1. This bit is set when the 0 = PWM is out of reset
module is in reset state and is cleared when the reset procedure is over. The
1 = PWM is undergoing reset
reset signal is asserted 2 clock cycles after this bit is set and the reset remains
asserted for 3 clock cycles. The whole reset procedure is complete 5 clock cycles
after this bit is asserted.
CLKSRC
Bit 15
Select Clock Source—This bit is used to select the clock for the PWM counter. 0 = perclk (fixed freq.
This field value should only be changed when the PWM is disabled.
functional clock)
1 = 32 KHz clock (Low freq
clock)
PRESCALAR Counter Clock Prescaler Value—This bit field determines the value by which
Bits 14–8
the clock will be divided before it goes to the counter.
0 = Byte ordering remains the
same
1 = Byte ordering is reversed
0000000 = [clock freq] / 1
0000001 = [clock freq] / 2
...
1111111 = [clock freq] / 128
IRQ
Bit 7
Fifo Empty Interrupt Status—This bit indicates that the FIFO has one or no
0 = FIFO is not empty
word remaining. It is a signal to fill the FIFO by writing no more than three 16-bit 1 = FIFO has one or no
words into the Sample register.This bit automatically clears itself after this
sample bytes
register is read, thus eliminating an extra write cycle in the interrupt service
routine.
IRQEN
Bit 6
Fifo Empty Interrupt Enable—This bit controls the pulse-width modulator
interrupt. While this bit is low, the interrupt is disabled.
FIFOAV
Bit 5
0 = FIFO cannot be written
FIFO Available—This read-only bit indicates that the FIFO is available for at
into
least one word of sample data. Data words can be loaded into the FIFO as long
1 = FIFO can be written into
as this bit is set. If the FIFO is loaded while this bit is cleared, the write will be
ignored.
EN
Bit 4
PWM Enable—This bit enables the pulse-width modulator. If this bit is not
enabled the following events occur:
• The clock prescaler is reset and frozen.
• The counter is reset and frozen.
When the pulse-width modulator is enabled, it begins a new period, and the
following events occur:
• The output pin is set to start a new period.
• The prescaler and counter are released and counting begins.
0 = FIFO interrupt disabled
1 = FIFO interrupt enabled
0 = The pulse-width
modulator is disabled
1 = The pulse-width
modulator is enabled
i.MX21 Reference Manual, Rev. 3
16-4
Freescale Semiconductor
Pulse-Width Modulator (PWM)
Table 16-2. PWM Control Register Description (continued)
Name
Description
Settings
REPEAT
Bits 3–2
Sample Repeat—This bit field determines the no of times each sample from the 00 = Use each sample once
FIFO is to be used.
01 = Use each sample twice
10 = Use each sample four
times
11 = Use each sample eight
times
CLKSEL
Bits 1–0
Divide Value—This bit filed selects the divide value of the divider chain which
divides the clock going to the counter.
16.2.2
00 = Divide by 2
01 = Divide by 4
10 = Divide by 8
11 = Divide by 16
PWM Sample Register
The pulse-width modulator sample (PWMS) register is the input to the FIFO. When you write successive
audio sample values to this register, they are automatically loaded into the FIFO in big-endian format.
16-bit words are loaded into the FIFO. The FIFO can only be written into when PWM is disabled. The read
may result in invalid data. The pulse-width modulator will run at the last set duty-cycle setting even if all
the values of the FIFO has been utilized until the FIFO is reloaded or the pulse-width modulator is
disabled. When a new value is written the duty cycle changes after the present period is over.
A value of zero in the sample register will result in ipp_pwm_pwmo being always low and hence no output
waveform. If the value in this register is higher than the PERIOD + 1, the output will never be reset, which
results in a 100% duty-cycle.
PWMS
PWM Sample Register
0x10006004
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SAMPLE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 16-3. PWM Sample Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read zero.
SAMPLE
Bits 15–0
Sample Value—This is the input to the 4
being currently used.
× 16 FIFO. The value in this register denotes the value of the sample
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
16-5
Pulse-Width Modulator (PWM)
16.2.3
PWM Period Register
The read/write pulse-width modulator period register (PWMP) controls the pulse-width modulator period.
After the counter value matches PERIOD + 1, the counter is reset to start another period. Therefore,
PWMO (Hz) = PCLK(Hz) / (period +2). A value of Zero in the period register a period of two clock cycles
for the output signal. Writing 0xFFFF to this register will achieve the same result as writing 0xFFFE.
Writing into the period register results in the counter being loaded with zero and the start of a new count
period.
PWMP
PWM Period Register
0x10006008
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PERIOD
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
Table 16-4. PWM Period Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
PERIOD
Bits 15–0
Period Value—This register determines the Period of the count cycle. 0x0000 = Count upto 0x0001
The counter counts upto [Period Value] +1 and is then reset to 0x0000. ...
0xfffe = Count upto 0xffff
0xffff = Count upto 0xffff
i.MX21 Reference Manual, Rev. 3
16-6
Freescale Semiconductor
Pulse-Width Modulator (PWM)
16.2.4
PWM Counter Register
The read-only pulse-width modulator counter register (PWMCNT) contains the current count value and
can be read at any time without disturbing the counter.
PWMCNT
PWM Counter Register
0x1000600C
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
COUNT
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 16-5. PWM Counter Register Description
Name
Description
Reserved Reserved—These bits are reserved and should read zero.
Bits 31–16
COUNT
Bits 15–0
Counter Value—This is the counter register value and denotes the current count state the Counter register is in.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
16-7
Pulse-Width Modulator (PWM)
i.MX21 Reference Manual, Rev. 3
16-8
Freescale Semiconductor
Part 4
Memory Interfaces
Chapter 17, “SDRAM Memory Controller,” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 17-1
Chapter 18, “Direct Memory Access Controller (DMAC),” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 18-1
Chapter 19, “NAND Flash Memory Controller,” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 19-1
Chapter 20, “External Interface Module (EIM),” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 20-1
Chapter 21, “Bus Master Interface (BMI),” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 21-1
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
1
i.MX21 Reference Manual, Rev. 3
2
Freescale Semiconductor
Chapter 17
SDRAM Memory Controller
This chapter describes the SDRAM Controller of the i.MX21 and how to configure and program it to work
with a wide variety of SDRAM devices. The block diagram of the SDRAM Controller is shown in
Figure 17-1.
The SDRAM Controller includes these distinctive features:
• Supports 4 banks of 64, 128, 256, or 512 Mbit synchronous DRAMs
• Includes 2 independent chip selects
— Up to 64 Mbytes per chip select
— Up to four banks simultaneously active per chip select
— JEDEC standard pinout/operation
• Supports SDRAM-interface burst memory
• PC133 compliant interface
— 133 MHz system clock achievable with “-75” option PC133 compliant memories
— single and fixed-length (8-word) word access
— Typical access time of 8-1-1-1-1-1-1-1 at 133 MHz
• Software configurable bus width, row and column sizes and delays for differing system
requirements
• Built in auto-refresh timer and state machine
• Hardware supported self-refresh entry and exit which keeps data valid during system reset and low
power modes
• Auto power-down (precharge and active power-down) timer
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-1
SDRAM Memory Controller
ahb_addr[25:2
SDBA[4:0]
ahb_addr[12:9]/ahb_addr[20:17]
ahb_addr[31:0]
ahb_data[31:0]
ROW / COLUMN
ADDRESS MUX
PAGE & BANK
ADDRESS
COMPARATORS
SDIBA [3:0]
MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
CONFIGURATION
REGISTERS
DQM3
DQM2
DQM1
DQM0
REFRESH
REQUEST
COUNTER
clk32
CSD0
CSD1
POWERDOWN
TIMER
m_rst
SDRAM
COMMAND
CONTROLLER
sd_rst
mpen
RAS
CAS
SDWE
SDCKE0
SDCKE1
SDCLK
AHB BUS
sd_lpack
ahb_data[31:0]
bigendian
DATA
ALIGNER
MUX
DQ[31:0]
Figure 17-1. SDRAM Controller Block Diagram
17.1
Functional Overview
The SDRAM Controller consists of 7 major blocks, including the SDRAM command controller, page and
bank address comparators, row/column address multiplexer, data aligner/multiplexer, configuration
registers, refresh request counter, and the powerdown timer.
i.MX21 Reference Manual, Rev. 3
17-2
Freescale Semiconductor
SDRAM Memory Controller
17.1.1
SDRAM Command Controller
The command controller handles the majority of the actions within the SDRAM controller including
sequencing accesses to the memories, initializing the DRAM, keeping track of active banks within each
memory region, scheduling refresh operations, transitioning into and out of low power modes, and
controlling the address and data multiplexers.
17.1.2
Page and Bank Address Comparators
There are a total of 8 address comparators. Each chip select has a unique comparator for each of its four
banks. The comparators are used to determine if a requested access falls within the address range of a
currently active DRAM page.
17.1.3
Row/Column Address Multiplexer
All synchronous DRAMs incorporate a multiplexed address bus, although the address folding points vary
according to memory density, data I/O size, and processor data bus width. The address folding point is
described as the point where the column address bits end and the row (or bank) address begin. The
SDRAM Controller takes these variables into account and provides the proper alignment of the
multiplexed address through the row/column address multiplexer, non-multiplexed address pins, and the
connections between the controller and the memory devices.
17.1.4
Data Aligner/Multiplexer
The data alignment block is responsible for aligning the data between the internal AHB bus and the
external memory device(s) including little endian byte swapping. It is also used to concatenate data when
a 32-bit AHB access has been broken down into 2 external 16-bit accesses.
17.1.5
Configuration Registers
Configuration registers determine the operating mode of the SDRAM Controller by selecting memory
device density and bus width, the number of memory devices, CAS latency, row to column delay, and the
burst length. Enable bits are provided for refresh and the auto-powerdown timer. Control bits provide a
mechanism for software-initiated SDRAM initialization, SDRAM mode register settings, and all bank
precharge and auto-refresh cycles.
17.1.6
Refresh Request Counter
SDRAM memories require a periodic refresh to retain data. The refresh request counter generates requests
to the SDRAM Command Controller to perform these refresh cycles. Requests are scheduled according to
a 32 KHz clock input. 1, 2 or 4 refresh cycles are generated per clock.
17.1.7
Powerdown Timer
The powerdown timer detects periods of inactivity to the SDRAM and disables the clock when the inactive
period surpasses the selected timeout. Data is retained during the powerdown state. Subsequent requests
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-3
SDRAM Memory Controller
to the SDRAM incur only a minimal added start-up delay (beyond the normal access time). The
powerdown timer may be programmed to expire anytime the controller is not actively reading/writing the
memory, after 64 or 128 clocks of inactivity, or may be disabled entirely.
17.1.8
DMA Operation with the SDRAM Controller
The DMA controller has the capability to perform burst transfers of byte and half word data types while
the SDRAM controller support is restricted to burst transfers of word (32-bit) data types. Therefore, when
using the DMA in conjunction with the SDRAM controller, ensure that all burst transfers to/from the
SDRAM controller are of word data types. This is configured in the DMA Channel Control Register. When
choosing SDRAM memory as the source or destination address, set the SDRAMC as a 32-bit port. Refer
to Chapter 18, “Direct Memory Access Controller (DMAC),” for more details.
17.1.9
External Interface
This section discusses input and output signals between the SDRAM Controller and the external memory
devices. Other than the chip select outputs (CSD0 / CSD1) and clock enables (SDCKE0 / SDCKE1), all
signals are shared between the two chip select regions. The interface signals are summarized in Table 17-1
and detailed in Section 17.1.10 through Section 17.1.20. Interconnect and timing diagrams are included as
part of the detailed discussion on controller operation in Section 17.3, “Operating Modes.”
All external interface signals are referenced to the SDRAM clock, SDCLK.
Table 17-1. SDRAM Interface Pin Characteristics
SDRAMC Signal Name
i.MX21 Pin Name
Function
Direction
Reset State
SDCLK
SDCLK
Clock to SDRAM
Output
Enabled
SDCKE0
SDCLKE0
Clock enable to SDRAM 0
Output
High
SDCKE1
SDCLKE1
Clock enable to SDRAM 1
Output
High
CSD0
CS2
Chip select to SDRAM array 0
Output
High
CSD1
CS3
Chip select to SDRAM array 1
Output
High
MA [9:0]
A [10:1]
Multiplexed address bus
Output
Low
MA[11:10]
MA[11:10]
Multiplexed address bus signals 11 and 10
Output
Low
SDBA [4:0] / arm_addr [25:21]
A [20:16]
Non-multiplexed address bus
Output
Low
SDIBA [3:0] /
arm_addr [12:9] /
arm_addr[20:17]
A [24:21]
Non-multiplexed address bus
Output
Low
DQM3
DQM3
Data qualifier mask byte 3 (D [31:24])
Output
Low
DQM2
DQM2
Data qualifier mask byte 2 (D [23:16])
Output
Low
DQM1
DQM1
Data qualifier mask byte 1 (D [15:8])
Output
Low
DQM0
DQM0
Data qualifier mask byte 0 (D [7:0])
Output
Low
DQ [31:0]
D [31:0]
Data I/O bus
I/O
Unknown
i.MX21 Reference Manual, Rev. 3
17-4
Freescale Semiconductor
SDRAM Memory Controller
Table 17-1. SDRAM Interface Pin Characteristics (continued)
SDRAMC Signal Name
i.MX21 Pin Name
Function
Direction
Reset State
SDWE
SDWE
Write enable
Output
High
RAS
RAS
Row address strobe
Output
High
CAS
CAS
Column address strobe
Output
High
17.1.10 SDCLK—SDRAM Clock
The SDCLK output provides the timing reference for the memory devices. All other SDRAM interface
signals are referenced to this clock. SDCLK is synchronous to the system clock, but is gated off during
low power operating modes when both SDCKE0 and SDCKE1 are negated.
17.1.11 SDCKE0, SDCKE1—SDRAM Clock Enables
The SDCKE0 and SDCKE1 pins are clock enable outputs to the SDRAM memory devices. SDCKE0
corresponds to SDRAM array 0 and SDCKE1 to SDRAM array 1. When these pins are asserted high, the
memory’s clock input is active, which means that a stable clock is being supplied. The low assertion
deactivates the memory’s clock input. A low assertion of SDCKEx initiates Power-Down, Self Refresh,
and Suspend modes to the SDRAM.
17.1.12 CSD0, CSD1—SDRAM Chip Select
CSD0 and CSD1 are used to select SDRAM Array 0 and SDRAM Array 1, respectively. When a valid
command is present on the other control signals, the chip select signals are used to indicate which device
the command is directed towards. these signals are multiplexed with chip select signals CS2 and CS3
respectively.
17.1.13 DQ [31:0]—Data Bus
The 32 data lines are used to transfer data between the SDRAM Controller and memory. Data bit 31 is the
most significant bit and bit 0 is the least significant. The memory alignment can be set to the upper 16 bits
[31:16], lower 16 bits [15:0] or 32 bits by programming the DSIZ field in the SDCTLs registers. See
Section 17.2.1, “SDRAM Control Registers.” The SDRAM Controller data bus DQ[31:0] are multiplexed
on the external data bus D[31:0].
17.1.14 MA [11:0]—Multiplexed Address Bus
The multiplexed address bus specifies the SDRAM page and the location within the page targeted by the
current access. The multiplexed address pins are used in conjunction with some of the non-multiplexed
ARM926EJ-S processor address signals to comprise the complete SDRAM address. Connections between
the SDRAM Controller and memory vary depending on the SDRAM device density. See Section 17.4.1,
“Address Multiplexing,” and specifically Table 17-12 through Table 17-19 for details on supported
SDRAM configurations. The SDRAM Controller multiplexed address bus MA [9:0] are multiplexed on
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-5
SDRAM Memory Controller
the external address bus A [10:1] while MA[11:10] are not multiplexed with any address signals (they are
simply brought out as MA[11:10]).
17.1.15 SDBA [4:0], SDIBA [3:0]—Non-Multiplexed Address Bus
The non-multiplexed address pins specify the SDRAM bank to which the current command is targeted.
The SDRAM Controller address signals SDBA [4:0] refer to non-interleaved bank addressing while
SDIBA [3:0] refer to the interleaved bank addressing. SDBA[4:0] sample the address signals
ahb_addr[25:12] and is multiplexed out on the external address bus signals A [20:16]. SDIBA [3:0] sample
the address signals ahb_addr [12:9] or ahb_addr [20:17] and these signals are multiplexed out on the
external address bus A [24:21]. In some density/width configurations, these pins also supply the most
significant bits of the row address. Table 17-10 and Table 17-11 document which address pins are used for
any given configuration.
17.1.16 DQM3, DQM2, DQM1, DQM0—Data Qualifier Mask
During read cycles, the DQMx pins controls the SDRAM data output buffers. DQMx asserted high
disables the output buffers leaving them in a high-impedance state. DQMx asserted low allows the data
buffers to drive normally.
During write cycles, DQMx controls which bytes are written in the SDRAM. DQMx asserted low enables
a write to the corresponding byte, while DQMx asserted high leaves the byte unchanged.
DQM3 corresponds to the most significant byte and DQM0 to the least significant. Sixteen bit memories
require only two DQM connections. Memories aligned to the upper data bus (D [31:16]) connect to DQM3
and DQM2, while memories aligned to the lower data bus (D [15:0]) connect to DQM1 and DQM0.
Memory alignment is selected in the SDCTLx Registers.
17.1.17 SDWE—Write Enable
Write enable is part of the three bit command field (RAS and CAS make up the other two bits) used by the
SDRAM. Generally, SDWE will be asserted low if a command transfers data to the memory. A detailed
summary of the supported SDRAM commands is provided in Table 17-8.
17.1.18 RAS—Row Address Strobe
Row address strobe is also part of the SDRAM command field. It is generally used to indicate an operation
affecting an entire bank or row. When RAS is asserted (low), a new SDRAM row address must be latched.
Table 17-8 provides details on SDRAM command encoding.
17.1.19 CAS—Column Address Strobe
The column address strobe is the third signal comprised in the command field. It generally signifies a
column oriented command. When CAS is asserted (low), the column address has changed. Table 17-8
provides details on SDRAM command encoding.
i.MX21 Reference Manual, Rev. 3
17-6
Freescale Semiconductor
SDRAM Memory Controller
17.1.20 Pin Configuration for SDRAMC
Table 17-2 lists the pins used for the SDRAMC module. These pins are multiplexed with other functions
on the device, and must be configured for SDRAM operation.
Table 17-2. Pin Configuration
Pin
Setting
SDCLK
Not Multiplexed
SDCKE0
Not Multiplexed
SDCKE1
Not Multiplexed
Set-Up Procedure
CSD0
Alternate Function of Set bit 0 (SDCS0_SEL) in the Function Multiplexing Control Register of the System Control
Module.
CS2/CSD0 pin
CSD1
Alternate Function of Set bit 1 (SDCS1_SEL) in the Function Multiplexing Control Register of the System Control
CS3/CSD1 pin
Module.
MA[11:10]
Not Multiplexed
MA [9:0]
Multiplexed with
A [10:1]
Internal Signal from SDRAMC Asserted for SDRAM Accesses
SDBA [4:0] Multiplexed with
A [20:16]
Internal Signal from SDRAMC Asserted for SDRAM Accesses
SDIBA [3:0] Multiplexed with
A [24:21]
Internal Signal from SDRAMC Asserted for SDRAM Accesses
DQM3
Not Multiplexed
DQM2
Not Multiplexed
DQM1
Not Multiplexed
DQM0
Not Multiplexed
SDWE
Not Multiplexed
RAS
Not Multiplexed
CAS
Not Multiplexed
17.2
Programming Model
The SDRAM module includes four 32-bit registers. Table 17-3 summarizes these registers and their
addresses. Registers are accessible in supervisor mode only. Attempts to access the registers in user mode
will result in a transfer error (TEA) being returned on the ARM926EJ-S processor’s local bus.
Table 17-3. SDRAM Module Register Summary
Description
Name
Address
SDRAM 0 Control Register
SDCTL0
0xDF000000
SDRAM 1 Control Register
SDCTL1
0xDF000004
SDRAM Reset Register
SDRST
0xDF000018
Miscellaneous Register
MISCELLANEOUS
0xDF000014
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-7
SDRAM Memory Controller
The SDRAM arrays are mapped according to Table 17-4. A 64 Mbyte space is allocated to each chip
select. Memories smaller than the allocated region are redundantly mapped throughout the remainder of
the region. Attempted accesses to a disabled chip select region (SDE bit of the SDCTLx = 0) and User
accesses to a protected (SP bit of the SDCTL = 1) region will result in a transfer error.
Table 17-4. SDRAM Array Memory Map
17.2.1
Address
Use
Access
0xC000 0000–0xC3FF FFFF
SDRAM 0 Memory Array
R/W
0xC400 0000–0xC7FF FFFF
SDRAM 1 Memory Array
R/W
SDRAM Control Registers
There are two SDRAM Control Registers, one for each of the two memory regions. SDCTL0 defines the
operating characteristics for the SDRAM 0 region (selected by CSD0), while SDCTL1 does the same for
the SDRAM 1 region (selected by CSD1). Bit field assignments within the registers are identical.
SDCTL0
SDCTL1
BIT
31
30
SDE
TYPE
Addr
0xDF000000
0xDF000004
SDRAM 0 Control Register
SDRAM 1 Control Register
29
28
SMODE
27
26
25
SP
24
23
22
21
ROW
20
COL
19
18
17
IAM
16
DSIZ
rw
rw
rw
rw
rw
r
rw
rw
r
r
rw
rw
rw
rw**
rw
rw
0
0
0
0
0
0
0
1
0
0
0
0
0
0**
0
0
6
5
4
3
2
1
0
RESET
0x0100*
BIT
15
14
SREFR
TYPE
13
12
11
PWDT
10
9
CI
8
7
SCL
SRP
SRCD
SRC
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
RESET
0x0300
* For SDCTL1, the reset is 0x0106.
** For SDCTL1, the reset value is 1. Bit 18, need to be cleared by software for proper operation.
i.MX21 Reference Manual, Rev. 3
17-8
Freescale Semiconductor
SDRAM Memory Controller
Table 17-5. SDRAM 0 Control Register and SDRAM 1 Control Register Description
Name
SDE
Bit 31
Description
Settings
SDRAM Controller Enable—Enables/Disables the SDRAM controller. 0 = Disabled
The module is disabled on reset. Disabling the module shuts off all
1 = Enabled
clocks within the module with the exception of register accesses.
SMODE
SDRAM Controller Operating Mode—Determines the operating
Bits 30–28 mode of the SDRAM controller. The controller is capable of operating in
seven different modes. These modes are primarily used for SDRAM
initialization. Any access to the SDRAM memory space, while in one of
the alternate modes, will result in the corresponding special cycle being
run. Moving from Normal to any other mode does not close (precharge)
any banks that may be open (activated). Under most circumstances,
software should run a precharge-all cycle when transitioning out of
Normal Read/Write mode. Operating mode details are provided in
Section 17.5, “SDRAM Operation,” . Reset initializes the operating
mode to “Normal Read/Write”.
000 = Normal Read/Write
001 = Precharge Command
010 = Auto-Refresh Command
011 = Set Mode Register Command
100 = Manual Self Refresh Command
101 = Reserved
110 = Reserved
111 = Reserved
SP
Bit 27
Supervisor Protect—Restricts user accesses within the chip select
region.
0 = User mode accesses are allowed to
this chip select region.
1 = User mode accesses are prohibited.
An attempted access to this chip
select region while in user mode will
result in a TEA being returned back
to the CPU. The chip select will not
be asserted.
Reserved
Bit 26
Reserved—This bit is reserved and should read 0.
ROW
Row Address Width—Specifies the number of row addresses used by
Bits 25–24 the memory array. This number does not include the bank, column, or
data qualifier addresses. Parameters affected by the programming of
this field include the page-hit address comparators and the bank
address bit locations (non-interleaved mode only).
00 = 11
01 = 12
10 = 13
11 = Reserved
Reserved Reserved—These bits are reserved and should read 0.
Bits 23–22
COL
Column Address Width—Specifies the number of column addresses
Bits 21–20 in the memory array and will determine the break point in the address
multiplexer. Column width is the number of multiplexed column
addresses and does not include bank and row addresses, or addresses
used to generate the DQM signals.
00 = 8
01 = 9
10 = reserved
11 = reserved
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-9
SDRAM Memory Controller
Table 17-5. SDRAM 0 Control Register and SDRAM 1 Control Register Description (continued)
Name
Description
Settings
IAM
Bit 19
Interleaved Address Mode—Controls bank address alignment. Bank 0 = Linear Address Map. Addresses flow
addresses fall between the row and column addresses, resulting in an
through each page in the first bank,
interleaved memory map with the banks alternately striped through the
into the second bank, and so on.
memory region. They are more significant than row and column
Linear Addressing is best suited to
addresses and result in a linear addressing of the banks through the
applications with large continuous
memory map.
blocks of linear accessed data such
as an LCD display buffer.
Bank address bit placement has a significant effect on how well the
1 = Interleaved Address Map. Addresses
SDRAM page buffers are utilized, with a corresponding impact on
flow through one page in the first
system performance.
bank, to one page in the second, to
the third, etc. The banks alternate at
The SDRAM Controller supports two bank address alignments which
each SDRAM page boundary.
will satisfy most system requirements.
Interleaved Mapping is better suited
for ARM9 code space. The
See Figure 17-2 for memory bank interleaving options.
interleaving of the banks eliminates
the need to continually open and close
Note: Memory address linearity is of little concern to the user when the
pages when loops and LRW
memory is comprised of RAM devices. It is recommended that
constants cross page boundaries,
the user choose linear addressing (IAM = 0) for block oriented
resulting in higher system throughput.
devices.
Reserved
Bit 18
Reserved—For SDCTL0 these bit is reserved and should read 0.
For SDCTL1 these bit is reserved but read as 1. For proper operation this bit need to be cleared (by writing “0”) by
software if SDCTL1 is used.
00 = 16-bit memory aligned to D [31:16]
DSIZ
SDRAM Memory Data Width—Defines the width of the SDRAM
Bits 17–16 memory and its alignment on the external data bus. 16-bit ports may be 01 = 16-bit memory aligned to D [15:0]
aligned to either the high or low half-word to equalize capacitive loading 1x = 32-bit memory
on the bus. Data qualifier mask control outputs must be matched to the
selected data bus alignment. Memories aligned to D [31:16] use DQM3
and DQM2. Memories aligned to D [15:0] use DQM1 and DQM0.
SREFR
SDRAM Refresh Rate—Enables/Disables SDRAM refresh cycles and
Bits 15–14 controls the refresh rate. Refresh cycles are referenced to a 32 KHz
clock. At each rising edge, 1, 2, or 4 rows will be refreshed. Multiple
refresh cycles are separated by the row cycle delay specified in the
SRC control field.
Note: If SREF!=2’b00 the SDCTL will issue AUTO_REFRESH
commands (each 32k clk, to the respective CS) regardless of
SDE bits.
Power-Down Timeout—Determines if and when the SDRAM will be
PWDT
Bits 13–12 placed in a power-down condition. The power-down timeout can be
triggered on either the absence of an active bank (PWDT = 00,
precharge power-down) or based on a clock count from the last access
(PWDT = 10 or 11, active power-down). Count-based timeouts do not
force the SDRAM into an idle condition (for example, any active banks
remain open). Section 17.4.4, “Power-Down Low-Power Mode,”
provides a comprehensive description of this operating mode.
SREFR
[1:0]
Rows
Each
Refresh
Clock
00
~Row/
64ms
@ 32
KHz
Row
Rate
@
32 KHz
Refresh Disabled
01
1
2048
31.25 μS
10
2
4096
15.62 μS
11
4
8192
7.81 μS
00 = Disabled
01 = Anytime all banks are inactive
(precharge power-down)
10 = 64 clocks after completion of last
access (active power-down)
11 = 128 clocks after completion of last
access (active power-down)
i.MX21 Reference Manual, Rev. 3
17-10
Freescale Semiconductor
SDRAM Memory Controller
Table 17-5. SDRAM 0 Control Register and SDRAM 1 Control Register Description (continued)
Name
Description
Settings
CI
Cache Inhibit—Defines the size of memory, starting from the lowest
Bits 11–10 location on the chip select space, to be cache inhibit. This function is not
necessary and should be disabled in a system having MMU which can
mark cache inhibit space itself.
00 = Disabled
01 = 1Mbytes
10 = 2Mbytes
11 = 4Mbytes
SCL
Bits 9–8
SDRAM CAS Latency—Determines the latency between a read
command and the availability of data on the bus. This field does not
affect the second and subsequent data words in a burst, and has no
effect on write cycles.
00 = Reserved
01 = 1 clock
10 = 2 clocks
11 = 3 clocks
Note: See Figure 17-3 on page 17-13 is
the CAS Latency Timing diagram.
Reserved
Bit 7
Reserved—This bit is reserved and should read 0.
SRP
Bit 6
SDRAM Row Precharge Delay—Determines the number of idle clocks 0 = 3 clocks inserted
inserted between a precharge command and the next row activate
1 = 2 clocks inserted
command to the same bank.
SRCD
Bits 5–4
SDRAM Row to Column Delay—Determines the number of clocks
inserted between a row activate command and a subsequent read or
write command to the same bank. See Figure 17-5.
00 = 4 clocks inserted
01 = 1 clock inserted
10 = 2 clocks inserted
11 = 3 clocks inserted
SRC
Bits 3–0
SDRAM Row Cycle Delay—Determines the minimum delay (in
number of clocks) between a refresh and any subsequent refresh or
read/write access. This delay corresponds to the minimum row cycle
time captured in the tRC/tRFC memory timing spec. An example timing
diagram for SRC = 3 can be found in Figure 17-6.
Note: The SRC control field is not used to enforce
tRC timing for row activate to row activate within the same bank
as this is implicitly guaranteed by the sum of
tRCD + tCL + tRP.
0000 = 10 clocks
0001 = 1 clock
0010 = 2 clocks
0011 = 3 clocks
0100 = 4 clocks
0101 = 5 clocks
0110 = 6 clocks
0111 = 7 clocks
1000 = 8 clocks
1001 = 9 clocks
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-11
SDRAM Memory Controller
IAM = 0
Linear Address Map
IAM = 1
Interleaved Address Map
Page n
Page n
•••
Page n
Page 1
Page n
Page 0
Page n
Page n
•••
•••
•••
Page 1
Page 0
Page n
•••
Increasing Addresses
Bank 3
Bank 2
•••
•••
Bank 1
Page 1
Page 1
Bank 0
Page 1
Page 1
Page 0
Page 1
Page n
Page 0
•••
Page 0
Page 1
Page 0
Page 0
Page 0
Figure 17-2. Memory Bank Interleaving Options
i.MX21 Reference Manual, Rev. 3
17-12
Freescale Semiconductor
SDRAM Memory Controller
SDCLK
COMMAND
READ
NOP
TLZ
TOH
D
DOUT
TAC
CAS Latency = 1
SDCLK
COMMAND
READ
NOP
NOP
TLZ
TOH
D
DOUT
TAC
CAS Latency = 2
SDCLK
COMMAND
READ
NOP
NOP
NOP
TLZ
D
TOH
DOUT
TAC
CAS Latency = 3
Figure 17-3. CAS Latency Timing
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-13
SDRAM Memory Controller
SDCLK
COMMAND
PRE
ACT
NOP
tRP = 2
SDCLK
COMMAND
PRE
NOP
NOP
ACT
tRP = 3
Figure 17-4. Precharge Delay Timing
SDCLK
COMMAND
ACTIVE
READ/WRITE
tRCD = 1
SDCLK
COMMAND
ACTIVE
NOP
READ/WRITE
tRCD = 2
SDCLK
COMMAND
ACTIVE
NOP
NOP
READ/WRITE
tRCD = 3
Figure 17-5. Row to Column Delay Timing
i.MX21 Reference Manual, Rev. 3
17-14
Freescale Semiconductor
SDRAM Memory Controller
SDCLK
COMMAND
REF
NOP
NOP
NOP
REF
NOP
NOP
TRC (SRC = 3)
NOP
ACT
TRC
Figure 17-6. Row Cycle Timing
17.2.2
SDRAM Reset Register
The write-only SDRAM Reset Register controls the reset pulse timing.
SDRST
BIT
SDRAM Reset Register
31
Addr
0xDF000018
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
w
w
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RST
TYPE
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-6. SDRAM Reset Register Description
Name
Description
RST
Bits 31–30
Software Initiated Local Module Reset Bits—Generates local module
reset to SDRAM controller
Reserved
Bits 29–0
Reserved—These bits are reserved and should read 0.
Settings
00 = No effect to the SDRAMC
01 = One HCLK Cycle Reset Pulse
10 = One HCLK Cycle Reset Pulse
11 = Two HCLK Cycle Reset Pulse
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-15
SDRAM Memory Controller
17.2.3
Miscellaneous Register
MISCELLANEOUS
BIT
31
Miscellaneous Register
Addr
0xDF000014
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
rw
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
OMA
TYPE
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
RMA0
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-7. Miscellaneous Register Description
Name
Description
Settings
OMA
Bit 31
Multiplexed Address Override—Enables/Disables the MA0 pinto be a
0 = Address from internal address
meaningful bit. The multiplexed address, original MA0, is always zero at read
multiplexed is routed out to
access in 16-bit port memory configuration. Working with bit 0 in tandem, this
MA0
overrides the original MA0 generated by the internal address multiplexer
1 = Force RMA0, bit 0, out to MA0
during access to 16-bit device.
pin
Reserved
Bits 30–1
Reserved—These bits are reserved and should read 0.
RMA0
Bit 0
MA0 Replacement—Contains Value of MA0 when OMA is set.
17.3
Operating Modes
Each of the SDRAM Controller operating modes are described in this section, including details on basic
operation, relationship to SDRAM operating modes, and any special precautions to observe. State and
timing diagrams are included where appropriate.
17.3.1
SDRAM Command Encodings
Table 17-8 summarizes the command encodings used by this controller. This command list is a subset of
the commands defined by the JEDEC standard. The encodings are based from the view of the SDRAM
memory to the controller and therefore use the SDRAM memory signal names.
i.MX21 Reference Manual, Rev. 3
17-16
Freescale Semiconductor
SDRAM Memory Controller
Table 17-8. SDRAM Command Encoding
Function
Symbol
CKEn-1
CKEn
CS
RAS
CAS
WE
A11
A10
BA[1:0]
A[9:0]
Deselect
DSEL
H
X
H
X
X
X
X
X
X
X
No Operation
NOP
H
X
L
H
H
H
X
X
X
X
Read
READ
H
X
L
H
L
H
V
L
V
V
Write
WRIT
H
X
L
H
L
L
V
L
V
V
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
V
Burst Terminate
TBST
H
X
L
H
H
L
X
X
V
X
Precharge Select Bank
PRE
H
X
L
L
H
L
X
L
V
X
Precharge All Banks
PALL
H
X
L
L
H
L
X
H
X
X
Auto-Refresh
CBR
H
X
L
L
L
H
X
X
X
X
Self Refresh Entry
SLFRSH
H
L
L
L
L
H
X
X
X
X
Self Refresh Exit
SLFRSHX
L
H
H
X
X
X
X
X
X
X
Power-Down Entry
PWRDN
H
L
X
X
X
X
X
X
X
X
Power-Down Exit
PWRDNX
L
H
H
X
X
X
X
X
X
X
Mode Register Set
MRS
H
X
L
L
L
L
L
L
V
V
Assertion of the sd_rst signal initializes the controller into the idle state. While disabled, the controller
remains in the idle state with the internal clocks stopped.
Read/write cycles, refresh and low-power mode requests, and Power-Down time-outs will all trigger
transitions out of the idle state. State transitions due to a read or write request depend on the operating
mode. Other transitions require the corresponding function to be enabled in the SDCTL register. Some
state transitions have been removed from the figure to minimize complexity and allow an easier
understanding of the basic controller operation.
The following subsections document the operation of each of the operating modes.
17.3.2
Normal Read/Write Mode
The Normal Read/Write mode (SMODE = 000) is used for general read and write access to the SDRAM,
Both single and burst accesses are supported, although burst requests are limited to a length of 8 words (8
half-words to 16-bit memories).
Read or write requests to the SDRAM Controller initiate a check to see whether the page is already open.
This check consists of comparing the request address against the last row accessed within the
corresponding bank. If the rows are different, that means that a precharge has occurred since the last
access, or there has never been an access to the bank. In that case, the access must follow the “off-page”
sequence. If the requested row and last row match, the shorter “on-page” access is used.
An off-page sequence must first activate the requested row, an operation which is analogous to a
conventional DRAM RAS cycle. An activate cycle is the first operation depicted in Figure 17-7 on page
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-17
SDRAM Memory Controller
17-19. During the activate cycle, the appropriate chip select is driven low, the row addresses are placed on
the multiplexed address pins, the non-multiplexed addresses are driven to their respective values, write
enable is driven high, CAS is driven high, and RAS is driven low. These latter three pins form the SDRAM
command word. The data bus is unused during the activate command.
Once the selected row has been activated, the read operation begins after the row to column delay (tRCD)
has been met. This delay is either 2 or 3 clocks, as determined by the SRCD field of the appropriate Control
Register. During the read cycle, the chip select is once again asserted, the column addresses are driven onto
the multiplexed address bus, the non-multiplexed addresses remain driven to the value presented during
the activate cycle, the write enable is driven high, RAS is driven high, and CAS is driven low. After the
CAS latency has expired, data is transferred across the data bus. CAS latency is programmable via the SCL
field of the Control Register. As data is being returned across the AHB, transfer acknowledge is asserted
back to the CPU indicating that the CPU should latch data. While data is still on the bus, the SDRAM
Controller must begin monitoring transfer request since the CPU is free to issue the next bus request on
the same edge that data is being latched.
Data transfers can be either single operand or a burst of up to 8 operands. Burst requests are designated as
such by the p_burst attribute. This AHB signal is asserted low for all but the last operand of a burst transfer.
Non-burst transfers do not assert the signal.
SDRAM memories assume that all transfers are burst transfers unless terminated early. Burst transfers can
be terminated by a variety of mechanisms: another read or write cycle, a precharge operation, or through
a burst terminate command. Burst terminate commands are the general mechanism used by the SDRAM
Controller for early burst termination, The burst terminate command is subject to the CAS latency and
must be pipelined similar to the Read command, as shown in Figure 17-7 and Figure 17-8 on page 17-20.
SDRAM write cycles are different than read cycles in one important aspect. Whereas read data was
delayed by the CAS latency, write data has no delay and is supplied at the same time as the Write
command. Figure 17-13 illustrates an off-page write cycle followed by an on-page write cycle. Note that
the write data is driven during the same clock that the Write command is issued. A Burst Terminate
command cancels the burst operation, but again without the CAS latency. When the SDRAM Controller
issues a burst write sequence, it also supplies the corresponding column address and write command with
each data word. Therefore when programming the SDRAM memory mode register the write burst length
must be set to single location writes.
i.MX21 Reference Manual, Rev. 3
17-18
Freescale Semiconductor
SDRAM Memory Controller
hclk
ahb_addr
ADDRA
ADDRB
ahb_rw
ahb_data
DATAA
ready
SDCLK
RAS, CAS, SDWE
ROWA
COLA
COLA
tRCD Minimum
ADDR
ACT
READ
COLB
tCL
TBST
NOP
NOP
NOP
READ
CSDx
D
DATAA
Figure 17-7. Off-Page Single Read Timing Diagram (32-Bit Memory)
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-19
SDRAM Memory Controller
hclk
ahb_addr
ADDRB
ahb_rw
ahb_data
DATAA
ready
SDCLK
ADDR
COLUMNA
COLUMNA
COLUMNB
tCL
RAS, CAS,
SDWE
READ
TBST
NOP
NOP
NOP
READ
CSDx
D
DATAA
Figure 17-8. On-Page Single Read Timing Diagram (32-Bit Memory)
i.MX21 Reference Manual, Rev. 3
17-20
Freescale Semiconductor
SDRAM Memory Controller
hclk
ahb_addr
ADDRA
ADDRB
ahb_rw
ahb_data
DATAA1
DATAA2
DATAA3
DATAA4
ready
SDCLK
ADDR
ROWA
RAS, CAS, SDWE
ACT
COLA
tRCD Minimum
COLB
tCL=2
READ
NOP
NOP
NOP
NOP
DATAA1
DATAA2
DATAA3
READ
CSDx
D
DATAA4
Figure 17-9. Off-Page Burst Read Timing Diagram (32-Bit Memory)
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-21
SDRAM Memory Controller
S1
hclk
ahb_addr
A1n
A2n A3n A4n
A1b
ahb_treq
ahb_rw
ahb_burst
ahb_data
D1n D2n D3n D4n
D1b
ready
O
Lb
C
K,
BA
N
N
BA
BA
N
K,
ADDR
K,
C
O
Ln
R
O
W
SDCLK
SRCD
RAS, CAS, SDWE
ACT NOP REA NOP NOP NOP NOP NOP NOP NOP NOP REA TBST NOP NOP
SCL
D
SCL
D1n D2n D3n D4n
D1n
DQMx
Figure 17-10. On-Page Burst Read Timing Diagram (32-Bit Memory)
i.MX21 Reference Manual, Rev. 3
17-22
Freescale Semiconductor
SDRAM Memory Controller
S1
hclk
ahb_addr
A1n
A2n
A3n
A4n
ahb_treq
ahb_rw
ahb_burst
ahb_data
D1n
D2n
D3n
D4n
ready
O
C
O
Ln
W
s_clk
K,
BA
N
BA
N
K,
R
ADDR
SRCD
RAS,CAS,SDW
ACT NOP REA NOP NOP NOP NOP NOP NOP NOP NOP NOP
1
D4n
D
4n
+
D3n
1
D2n
D
3n
+
D
2n
+1
D
1n
+
D1n
1
SCL
D
DQMx
Figure 17-11. Off-Page Burst Read Timing Diagram (16-bit Memory)
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-23
SDRAM Memory Controller
S1
hclk
ahb_addr
A1n
A2n
A3n
A4n
ahb_treq
ahb_rw
ahb_burst
ahb_data
D1n
D2n
D3n
D4n
ready
Ln
s_clk
BA
N
K,
C
O
ADDR
CAS,RAS,SDWE
REA NOP NOP NOP NOP NOP NOP NOP NOP NOP
SCL
D
D10 D11
D20 D21
D30 D31
D40 D41
DQMx
Figure 17-12. On-Page Burst Read Timing Diagram (16-Bit Memory)
i.MX21 Reference Manual, Rev. 3
17-24
Freescale Semiconductor
SDRAM Memory Controller
hclk
ahb_addr
ADDRB
ADDRA
ahb_rw
ahb_data
DATAA
DATAB
ready
SDCLK
ADDR
ROWA
COLUMNA
COLUMNB
tRCD
RAS, CAS, SDWE
ACT
WRIT
TBST
WRIT
TBST
CSDx
D
DATAA
DATAB
Figure 17-13. Off-Page Write Followed by On-Page Write Timing Diagram
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-25
SDRAM Memory Controller
S1
hclk
AHB_addr
A1n
A2n
A3n
A4n
ahb_treq
ahb_rw
ahb_burst
D1n
ahb_data
D2n
D3n
D4n
ahb_ready
R
O
W
n
SDCLK
COL2n
COL3n
COL4n
WRIT
WRIT
WRIT
WRIT
D1n
D2n
D3n
D4n
N
K,
BANK, COL1n
BA
ADDR
SRCD
CAS,RAS,SDWE
D
ACT
NOP
TBST
Figure 17-14. Off-Page Burst Write Timing Diagram
i.MX21 Reference Manual, Rev. 3
17-26
Freescale Semiconductor
SDRAM Memory Controller
S1
hclk
AHB_addr
A2n
A1n
A3n
A4n
ahb_treq
ahb_rw
ahb_burst
ahb_data
D1n
D2n
D3n
D4n
COL2n
COL3n
COL4n
WRIT
WRIT
WRIT
WRIT
D1n
D2n
D3n
D4n
ahb_ready
SDCLK
ADDR
CAS,RAS,SDWE
D
BANK, COL1n
TBST
Figure 17-15. On-Page Burst Write Timing Diagram
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-27
SDRAM Memory Controller
S1
hclk
AHB_addr
A1n
ahb_treq
ahb_rw
ahb_burst
D1n
ahb_data
ahb_ready
O
W
n
SDCLK
COL2n
N
K,
R
BANK, COL1n
BA
ADDR
SRCD
CAS,RAS,SDWE
D
ACT
NOP
WRIT
D10
WRIT
TBST
NOP
D11
Figure 17-16. Off-Page Write Timing Diagram (16-Bit Memory)
i.MX21 Reference Manual, Rev. 3
17-28
Freescale Semiconductor
SDRAM Memory Controller
S1
hclk
AHB_addr
A1n
ahb_treq
ahb_rw
ahb_burst
ahb_data
D1n
ahb_ready
SDCLK
ADDR
BANK, COL1n
COL2n
CAS,RAS,SDWE
WRIT
WRIT
D
D10
TBST
NOP
NOP
D11
Figure 17-17. On-Page Write Timing Diagram (16-Bit Memory)
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-29
SDRAM Memory Controller
S1
hclk
ahb_addr
A1
A2
ahb_treq
ahb_rw
ahb_burst
ahb_data
D1
D2
ahb_ready
SDCLK
ADDR
ROW
CAS,RAS,SDWE
BANK, COL1
BANK, COL2
SRCD
ACT
NOP
WRIT
TBST
READ
TBST
SCL
D
D1
D2
Figure 17-18. Single Write Followed by On-Page Read Timing Diagram
i.MX21 Reference Manual, Rev. 3
17-30
Freescale Semiconductor
SDRAM Memory Controller
S1
hclk
ahb_addr
A1n
A2n A3n A4n
A1b
ahb_treq
ahb_rw
ahb_burst
ahb_data
D2n D3n D4n
D1n
D1b
ahb_ready
O
Lb
C
O
L4
m
BA
N
K,
C
L3
n
L2
n
O
C
O
C
BA
N
BA
N
K,
R
ADDR
K,
O
W
n
C
O
L1
n
SDCLK
SRCD
CAS,RAS,SDW
ACT NOP WRIT WRIT WRIT WRIT TBST REA TBST
SCL
D
D1n D2n D3n D4n
D1b
Figure 17-19. Burst Write Followed by On-Page Read Timing Diagram
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-31
SDRAM Memory Controller
S1
hclk
ahb_addr
A1n
A2b
ahb_treq
ahb_rw
ahb_burst
ahb_data
D1n
D2b
ahb_ready
SDCLK
O
W
n
ADDR
BANK, COLb
BA
N
K,
R
BANK, COLn
CAS,RAS,SDWE
SRCD
ACT
NOP
READ
TBST
NOP
NOP
NOP
WRIT
TBST
SCL
D
D1n
D2b
DQMx
Figure 17-20. Single Read Followed by On-Page Write Timing Diagram
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17-32
Freescale Semiconductor
SDRAM Memory Controller
S1
hclk
ahb_addr
A1n
A2n
A3n
A4n
A1b
ahb_treq
ahb_rw
ahb_burst
D1n D2n D3n D4n
ahb_data
D1b
ready
O
O
BA
BA
N
N
K,
K,
C
C
K,
R
BA
N
ADDR
Lb
Ln
O
W
SDCLK
SRCD
CAS,RAS,SDW
ACT NOP REA NOP NOP NOP NOP NOP NOP NOP NOP NOP WRIT TBST
SCL
D1n D2n D3n D4n
D
D1b
DQMx
Figure 17-21. Burst Read Followed by On-Page Write Timing Diagram
17.3.3
Precharge Command Mode
The Precharge Command Mode (SMODE = 001) is used during SDRAM device initialization, and to
manually deactivate an/all active bank/s. While in this mode, an access (either read or write) to the
SDRAM address space will generate a precharge command cycle. SDRAM address bit A10 determines
whether a single bank, or all banks, are precharged by the command. (See Figure 17-22). Accessing an
address with the SDRAM address A10 low will precharge only the bank selected by the bank address.
Conversely, accesses with A10 high will precharge all banks regardless of the bank address. Note that A10
is the SDRAM pin, not the ARM926EJ-S processor’s address. Translation of the SDRAM A10 to the
corresponding ARM926EJ-S processor’s address is dependent on the memory configuration. The
precharge command access is two clocks in length on the AHB, and one cycle to the SDRAM.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-33
SDRAM Memory Controller
hclk
ahb_addr
SDCTL
SDRAMX
SDCTL
SDRAMX
ahb_rw
ahb_data
SMODE = PRE_CMD
0
SMODE = NORMAL
ready
SDCLK
ADDR
SDRAMx
Row
SDRAMx,
with A10-0
tRP Min applies only to same bank.
RAS, CAS, SDWE
PRE
NOP
NOP
NOP
ACT
CSDx
D
Figure 17-22. Precharge Bank Timing Diagram
i.MX21 Reference Manual, Rev. 3
17-34
Freescale Semiconductor
SDRAM Memory Controller
hclk
ahb_addr
SDCTL
SDRAMX
SDCTL
SDRAMX
ahb_rw
ahb_data
SMODE = PRE_CMD
0
SMODE = NORMAL
ready
SDCLK
ADDR
SDRAMx
with A10 = 0
SDRAMx
Row
tRP Min
RAS, CAS, SDWE
PRE
NOP
NOP
NOP
ACT
CSDx
D
Figure 17-23. Precharge All Timing Diagram
17.3.4
Auto-Refresh Mode
The Auto-Refresh Mode (SMODE = 010) is used to manually request SDRAM refresh cycles. It is
normally used only during device initialization, since the SDRAM Controller will automatically generate
refresh cycles when properly configured. The auto-refresh command refreshes all banks in the device, so
the address supplied during the refresh command only needs to specify the correct SDRAM device. The
lower address lines are ignored. Either a read or write cycle may be used. If a write is used, the data will
be ignored and the external data bus will not be driven. The cycle will be 2 clocks on the AHB and a single
clock to the SDRAM device.
The SDRAM Controller guarantees that the SDRAM is in the idle state before the auto-refresh command
is given. If one or more rows are active, a precharge-all command will be issued prior to the auto-refresh
command. The precharge-all command adds one additional clock to the access time.
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Freescale Semiconductor
17-35
SDRAM Memory Controller
hclk
ahb_addr
SDCTL
SDRAMx
SDRAMx
ahb_rw
ahb_data
SMODE = REF
0
0
ready
SDCLK
ADDR
SDRAMx
SDRAMx
SDRAMx
tRC Minimum
RAS, CAS, SDWE
PALL
CBR
NOP
NOP
CBR
NOP
NOP
CSDx
D
Figure 17-24. Software Initiated Auto-Refresh Timing Diagram
NOTE
SDRAM devices require a minimum delay of tRC between refresh cycles.
The SDRAM Controller incorporates a timer to guarantee this timing is met.
The timer is user configurable through the SRC field in the SDCTLx
register.
17.3.5
Set Mode Register Mode
The Set Mode Register mode (SMODE = 011) is used to program the SDRAM mode register. This mode
differs from normal SDRAM write cycles because the data to be written is transferred across the address
bus. Reads of the mode register are not allowed.
Either a read or write cycle may be used for this transfer. In the case of a write, the AHB data will be
ignored and the external data bus will not be driven. The row and bank address signals are used to transfer
the data. The cycle will be 2 clocks on the AHB and a single clock to the SDRAM device.
Figure 17-25 and Figure 17-26 illustrate the bus sequence for a mode register set operation. Mode register
set commands must be issued while the SDRAM is idle.
The SDRAM Controller does not guarantee that the SDRAMs have returned to the idle state before issuing
the mode register set command. Therefore, software must generate a precharge all sequence before issuing
i.MX21 Reference Manual, Rev. 3
17-36
Freescale Semiconductor
SDRAM Memory Controller
the mode register set command if there is any possibility that one or more banks could be active. Also keep
in mind that the row cycle time (tRC) must be met before the mode register set command is issued.
Section 17.5.4, “Mode Register Programming,” provides a detailed example of the mode register data
value calculation and mapping to the ARM926EJ-S processor’s address.
(Read | Write) & SMODE = pre_cmd
Precharge
All
Active
Idle
(Read | Write) & SMODE = set_mode
ILLEGAL SDRAM TRANSITION
Set
Mode Reg
(Read | Write) & SMODE = set_mode
Figure 17-25. Set Mode Register State Diagram
hclk
ahb_addr
SDRAMx
SDCTL
SDRAMx
ahb_rw
ahb_data
0
SMODE = SET_MODE
DON’T CARE
ready
SDCLK
ADDR
SDRAMx
MODE
tRC Minimum
RAS, CAS, SDWE
REFRESH
CSDx
MRS
Self-Refresh and
D
Figure 17-26. Set Mode Register Timing Diagram
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-37
SDRAM Memory Controller
17.3.6
Manual Self Refresh Mode
This mode allows the software to control a Self refresh mode entry of the external SDRAM if refresh has
been enabled. When this mode is selected (SMODE=100) and refresh is enabled the controller will finish
any active accesses and send a self refresh command to the external memory. No access is allowed while
SMODE bits are set in the manual self refresh mode. If refresh has not been enabled, the SDRAM
Controller places the memories in a lower power consumption mode known as Powerdown.
When a different mode is selected on the SMODE bits, the controller will take the external SDRAM out
of self refresh mode and will begin issuing auto refresh cycles (if refresh has been enabled).
After exiting manual self refresh mode, the software should wait a tRC period of time before issuing
“normal” accesses to the SDRAM.
sd_lpack
hclk
ahb_ad
ahb_rw
ahb_da
SMOD=SREF
ready
SDCLK
SDCKEx
ADDR
RAS,
CAS,
SDWE
A10 = 1
≥ tRP
PRE-ALL
SLFRRSH
CSDx
D
Figure 17-27. Software Initiated Self-Refresh Entry Timing Diagram
i.MX21 Reference Manual, Rev. 3
17-38
Freescale Semiconductor
SDRAM Memory Controller
SMOD!=SREF
ahb_data
sd_lpack
m_clk
ahb_addr
ahb_rw
ahb_data
ready
SDCLK
SDCKEx
ADDR
≥ tRC + 1 Clock
RAS,
CAS,
SDWE
NOP
NOP
NOP
REF A
CSDx
D
Figure 17-28. Software Initiated Self-Refresh Exit Timing Diagram
17.4
General Operation
The general operation of the SDRAM Controller includes address multiplexing, refresh and self-refresh
are discussed. The SDRAM Controller is designed to support a broad range of broad range of JEDEC
standard SDRAM configurations including devices of 64-, 128-, and 256-Mbit densities. Given the
physical size constraints of the target applications, the design was optimized for memory device data
widths of 16 and 32 bits. Table 17-9 summarizes the devices targeted by the design; however, the controller
is capable of interfacing with devices of other widths and densities. However, only devices with 4 banks
are supported. 133 MHz system bus operation is possible with PC133 compliant Single Data Rate memory
devices.
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Freescale Semiconductor
17-39
SDRAM Memory Controller
Table 17-9. JEDEC Standard Single Data Rate SDRAMs
SDRAM Configuration
Size
64 Mbit
128 Mbit
256 Mbit
Bus Width
16
32
16
32
16
32
Depth
4 Mword
2 Mword
8 Mword
4 Mword
16 Mword
8 Mword
Refresh Rows
4096
(15.62 μS)
4096
(15.62 μS)
4096
(15.62 μS)
4096
(15.62 μS)
8192
(7.81 μS)
4096
(15.62 μS)
# Banks
4
4
4
4
4
4
Bank Address
2
2
2
2
2
2
Row Address
12
11
12
12
13
12
Column Address
8
8
9
8
9
9
Data Qualifiers
2
4
2
4
2
4
17.4.1
Address Multiplexing
The JEDEC standard SDRAMs around which the controller was optimized use an asymmetrical array
architecture with more row than column address lines. The SDRAM Controller multiplexes only those
pins which change between the row and column addresses. The remaining (most significant) row
addresses and the bank addresses are not multiplexed.
17.4.1.1
Multiplexed Address Bus
The SDRAM Controller multiplexed address bus is aligned to the column addresses so that the ARM
address line A1 always appears on pin MA0. With this alignment, the “folding point” in the multiplexor
is driven solely by the number of column address bits, although interleave mode causes a two bit shift to
account for the bank addresses. Column bus widths of 8 to 11 bits are supported in non-interleave mode,
although only 8 and 9 bit widths are allowed in interleave mode. Table 17-10 summarizes the multiplex
options supported by the controller. Column addresses through A10 are driven regardless of the
multiplexor configuration, although some of the lines will be unused for the smaller page sizes.
Memory width does not affect the multiplexer; however, it does affect how the memories are connected to
the SDRAM Controller pins. The width of the multiplexed bus is one bit larger than in previous
generations of the SDRAMC so that 16- and 32-bit memory systems can be supported with a minimal
impact on the multiplex hardware. 16-bit memories utilize column address bits MA [n:0] for a 2n+1
byte/page memory, whereas 32-bit memory systems are shifted left by one bit and use MA [n+1:1]. This
is demonstrated in the last two rows of Table 17-10 by the grayed out boxes. Note that the AP signal is
duplicated in two bit positions to permit this signal to always appear on memory pin A10. Compare
Figure 17-27 and Figure 17-28 as an example of the connection differences between 16- and 32-bit
memory systems.
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17-40
Freescale Semiconductor
SDRAM Memory Controller
Table 17-10. Address Multiplexing by Column Width
Column Bits
IAM
=0
IAM
=1
SDRAM Controller Pin
Memory
Width
MA 11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
ROW
8
–
16, 32
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
9
–
16, 32
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
10
8
16, 32
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
11
9
16, 32
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
COLUMN
ALL
16
AP
AP
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
32
AP
AP
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
Indicates address lines not required for this memory width.
17.4.1.2
Non-Multiplexed Address Bus
The most significant row address bits are not sampled when the column addresses are being driven, and
therefore do not need to be multiplexed. The SDRAM Controller implementation takes advantage of this
fact and uses the existing non-multiplexed address bus to provide these signals. Addresses A21 through
A25 are needed across the supported configurations. The specific connections which will need to be made
are dependent on the memory device type, density and bank interleave mode. These
configuration-dependent connections are handled through the design of the external hardware. Examples
are provided in Section 17.5, “SDRAM Operation,” .
17.4.1.3
Bank Addresses
Bank address connections are summarized in Table 17-11 while Figure 17-29 on page 17-43 illustrates the
logical structure of how the internal ARM address signals are multiplexed out to the SDRAM memory
bank address signals. Linear bank addressing (IAM = 0) utilizes the most-significant addresses to specify
the active bank, where the actual bits used are dependent on the density of the memory system. In
interleaved bank mode (IAM = 1), memory density has no affect on the selection of bank addresses.
Instead, the bank addresses are totally dependent on the page size of the memory system, as determined
by the number of column address bits and the memory data width. Page size and density for a number of
potential configurations are documented in Table 17-11 through Table 17-19. For undocumented
configurations, the following equations can be used to calculate page size and density.
Page Size (bytes) = 2#Column Address Bits × (Memory Width in Bits / 8)
Eqn. 17-1
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Freescale Semiconductor
17-41
SDRAM Memory Controller
Density (bytes) = 2(# Column Address Bits + # Row Address Bits)
× (Memory Width in Bits / 2)
Eqn. 17-2
Table 17-11. Bank Address Bit Assignment
IAM
Density (Bytes)
Page Size (Bytes)
BA1
BA0
0
8M
X
ARM_A22
ARM_A21
16M
ARM_A23
ARM_A22
32M
ARM_A24
ARM_A23
64M
ARM_A25
ARM_A24
512
ARM_A10
ARM_A9
1024
ARM_A11
ARM_A10
2048
ARM_A12
ARM_A11
1
17.4.2
X
Refresh
SDRAM Controller hardware satisfies all SDRAM refresh requirements after an initial configuration by
the user software. 0, 1, 2, or 4 refresh cycles are scheduled at 31.25 μS (nominal 32 KHz clock) intervals,
providing 0, 2048, 4096, or 8192 refresh cycles every 64 ms. The refresh rate is programmed through the
SREFR field in the SDCTLx registers. Each array can have a different rate, allowing a mix of SDRAM
devices (different density). Refresh is disabled by hardware reset.
A refresh request is made pending at each rising edge on the 32 KHz clock. In response to this request, the
hardware gains control of the SDRAM as soon as any in-process bus cycle completes. Once it has gained
control of the memory, commands are issued to precharge all banks. Following a row precharge delay
(tRP), an auto-refresh command is issued. At tRC intervals, additional auto-refresh cycles are issued until
the specified number of cycles have been run. Figure 17-29 illustrates a 2 refresh sequence.
Burst transfers in progress when the refresh request arrives are allowed to complete prior to the refresh
operation. SDRAM bus accesses queued after the refresh request are held off until the refresh completes.
In Figure 17-30, an access is queued just as the refresh begins. This cycle is delayed until the precharge
and single refresh (SREFR = 01) cycles are run. Bus cycles targeted to other memory or peripheral devices
are allowed to progress normally while the refresh is in progress. None of the pins shared between the
SDRAM and other devices are required for the refresh operation.
i.MX21 Reference Manual, Rev. 3
17-42
Freescale Semiconductor
SDRAM Memory Controller
32KHz
hclk
ahb_addr
ahb_rw
ahb_data
DATAA
ready
SDCLK
ADDR
A10 = 1
≥ tRP
RAS,
CAS,
SDWE
PRE-ALL
≥ tRC
REF A
REF A
CSDx
D
DATAA
Figure 17-29. Hardware Refresh Timing Diagram
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-43
SDRAM Memory Controller
32KHz
hclk
ahb_addr
SDRAMx
ahb_rw
ahb_data
ready
SDCLK
ROWx
ADDR
≥ tRC (Minimum)
tRP (Minimum)
RAS,
CAS,
SDWE
PRE-ALL
REF A
ACT
CSDx
D
Figure 17-30. Hardware Refresh with Pending Bus Cycle Timing Diagram
17.4.3
Self-Refresh
SDRAM data must be retained during system reset and power conservation modes if refresh has been
enabled. The SDRAM Controller detects these conditions and places the memory in self-refresh. If refresh
has not been enabled, the SDRAM Controller places the memories in a lower power consumption mode
known as Powerdown. This operation is described in Section 17.4.3.3, “Powerdown Operation During
Reset and Low-Power Modes.” Self refresh mode can also be initiated manually by setting the SMODE
bits to ‘100’. Refer to Section 17.3.6 for more details on manual self refresh.
17.4.3.1
Self-Refresh During Reset
The assertion of system reset triggers the SDRAM Controller to place the memory in self-refresh provided
refresh had been previously enabled. Refresh during system reset is disabled by an SDRAM Controller
reset. It remains disabled until the refresh rate is programmed to a non-zero value. Once enabled,
self-refresh is invoked anytime system reset is asserted without a corresponding SDRAM reset.
17.4.3.2
Self-Refresh During Low-Power Mode
Low-power mode (STOP) also forces the SDRAM into self-refresh mode if refresh is enabled. Any time
“mpen” is sampled low, the SDRAM Controller assumes that the bus masters are entering a low-power
condition and it begins the self-refresh sequence once any in-progress bus access has completed. A
Precharge All command is issued to close any open memory pages, the Self-Refresh command is issued,
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17-44
Freescale Semiconductor
SDRAM Memory Controller
and the clock enable is brought low. Once the memories are safely in their low-power state, the SDRAMC
tells the system clock controller to enter sleep mode.
17.4.3.3
Powerdown Operation During Reset and Low-Power Modes
The powerdown mode is used instead of self-refresh whenever system reset or any of the low power modes
occur and refresh has not been enabled. This memory operating mode does not remove power, as the name
might imply. It simply lowers power consumption by disabling the clock input buffer and halting all
internal activity. Since powerdown can only be entered if all banks are idle, a Precharge All command must
be issued to the memories prior to stopping the clock. Figure 17-33 illustrates the powerdown sequence
following assertion of system reset.
mpen
sd_lpack
hclk
ahb_add
ahb_r
ahb_dat
DATAA
ready
SDCLK
SDCKEx
ADDR
A10 = 1
≥ tRP
RAS,
CAS,
SDWE
PRE-ALL
SLFRRSH
CSDx
D
DATAA
Figure 17-31. Self-Refresh Entry Due to Low-Power Mode Timing Diagram
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-45
SDRAM Memory Controller
mpen
sd_lpac
hclk
ahb_a
ahb_r
ahb_d
ready
SDCLK
SDCKEx
ADDR
RAS,
CAS,
SDWE
≥ tRC + 1 Clock
NOP
NOP
NOP
REF A
CSDx
D
Figure 17-32. Low-Power Mode Self-Refresh Exit Timing Diagram
i.MX21 Reference Manual, Rev. 3
17-46
Freescale Semiconductor
SDRAM Memory Controller
m_rst
sd_lpac
hclk
ahb_a
ahb_r
ahb_d
ready
SDCLK
SDCKE
ADDR
A10 = 1
RAS,
CAS,
SDWE
PRE-ALL
NOP
NOP
CSDx
D
DATAA
Figure 17-33. Power-Down Mode Resulting From Reset With Refresh Disabled
17.4.4
Power-Down Low-Power Mode
SDRAM memories incorporate a command sequence to disable the clock input buffer and suspend internal
activity, lowering power consumption as much as an order of magnitude. The SDRAM Controller
implements a Power-Down timeout mechanism to take advantage of this feature. Several software
selectable time-outs are provided to accommodate for varying system conditions, with the timeout
condition being specified in the Power-Down Timeout (PWDT) field in the SDCTLx register. The feature
is disabled out of reset.
SDRAM Power-Down actually consists of two sub-modes: Active Power-Down and Precharge
Power-Down. The distinguishing factor between them is whether banks remain active while the clock is
stopped. Active Power-Down allows banks to remain activated, while Precharge Power-Down/Deep
Power-Down Mode does not.
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Freescale Semiconductor
17-47
SDRAM Memory Controller
17.4.4.1
Precharge Power-Down
Programming PWDT [1:0] = 01 causes the SDRAM Controller to place the memories in powerdown mode
anytime the controller detects that no banks are active. This mode is useful in applications where a memory
array is accessed infrequently and the chances of another access to the same page are minimal.
Reading or writing to memory activates a page within the addressed bank. Reset, software generated
precharge, and hardware initiated refresh are three ways to close an active bank. The periodically occurring
refresh will be the normal means that invokes the powerdown mode. At each refresh interval, all banks
will be closed by a precharge-all command, followed by the refresh operation. The controller will then
issue the powerdown command to the memories. A few cycle delay is incurred with the first read or write
cycle in order to restart the clocks, but only on the first cycle. After that, the clocks will continue to run
until the next refresh operation or until any active banks are manually precharged.
Page misses on read and write cycles cause the addressed bank to be closed (precharged) and a new page
opened within the bank. This operation does not cause the clocks to stop, nor does manually precharging
only a single bank within the memory. All banks within the memory must be inactive before the
powerdown mode is invoked.
17.4.4.2
Active Power-Down
The second Power-Down mode is selected whenever PWDT [1:0] = 1x. In this mode the clocks are
stopped after a selectable delay from the last access to the array. Active banks are not closed prior to
disabling the SDRAM clock. Either 64 (PWDT [1:0] = 10) or 128 (PWDT [1:0] = 11) cycle delays are
possible. SDRAM clocks are counted from the end of the last read or write access. Subsequent read or
write accesses, and self-refresh modes reset the counter. Auto-refresh cycles do not affect the counter;
however, if the counter expires during a refresh operation the clock will be disabled immediately following
the refresh.
17.4.4.3
Refresh During Precharge Power-Down/Active Power-Down
Refresh requests queued while the clock is suspended will restart the clock, run the appropriate number of
refresh cycles, and then disable the clock again.
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17-48
Freescale Semiconductor
SDRAM Memory Controller
32KHz
hclk
ahb_addr
ahb_r
ahb_data
read
SDCLK
SDCKEx
ADDR
ROWx
tRP (Minimum)
RAS,
CAS,
SDWE
PRE-ALL
REF A
NOP
CSDx
D
Figure 17-34. Precharge Power-Down Mode Entry Timing Diagram
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Freescale Semiconductor
17-49
SDRAM Memory Controller
hclk
ahb_addr
ADDRA
ADDRB
ahb_rw
ahb_data
DATAA
ready
SDCLK
SDCKEx
ADDR
RAS,
CAS,
SDWE
ROWA
COLUMNA
tRCD Minimum
NOP
ACT
COLUMNA
COLUMN
SDRAMx B
tCL=2
READ
TBST
NOP
NOP
READ
CSDx
D
DATAA
Figure 17-35. Power-Down Exit Timing Diagram
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Freescale Semiconductor
SDRAM Memory Controller
hclk
ahb_add
ADDRB
ahb_rw
ahb_data
DATAA
ready
SDCLK
SDCKEx
64 Clocks or 128 Clocks
ADDR C0LUMNA
RAS,
CAS,
SDWE
C0LUMNA
C0LUMN
SDRAMx B
tCL = 2
READ
TBST
NOP
READ
CSDx
D
DATAA
Figure 17-36. Active Power-Down Timing Diagram (64 Clock Example)
17.5
SDRAM Operation
The following subsections provide details on selecting compatible SDRAM memories and configuring the
controller to work with the memory system.
17.5.1
SDRAM Selection
Table 17-9 lists the memories around which the controller is optimized, but many other memory types are
also suitable for use. Important characteristics to consider when choosing a memory module are:
• The page comparators expect 4 bank memories. 2 bank devices are not supported. Their use will
result in the memory and controller losing synchronization when crossing page boundaries.
• Page (column) addressing must match one of the supported sizes.
• Memory density can be larger or smaller than those directly supported, although some memory
may be inaccessible or redundantly mapped. In linear mode (IAM bit of the Control Register is 0),
the bank addresses are the most significant addresses and connecting a memory smaller than the
selected density will result in one or more banks being inaccessible.
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Freescale Semiconductor
17-51
SDRAM Memory Controller
•
The controller is designed for memories meeting PC133 timing specifications at 133 MHz system
operation. Use of non-compliant memories or other system clock rates require a thorough analysis
of all timing parameters.
17.5.2
Configuring Controller for SDRAM Memory Array
Configuration register programming options and controller-memory physical connections provide
flexibility to accommodate different memory types and system configurations. Options are broadly
grouped into 3 categories:
• Physical Characteristics: row and column address bus widths, data bus width, and interleave mode
• Timing Parametrics: CAS latency, row precharge and cycle delays, and refresh rate
• Functional Features: Power-Down timer and supervisor/user protection
Table 17-12 through Table 17-19 are provided to assist the designer with the selection of the correct
physical parameters for a number of preferred memory configurations. Timing parametrics are addressed
in the following subsections.
17.5.2.1
CAS Latency
CAS latency is determined by the operating frequency and access time of the memories. For a 133 MHz
system clock frequency and PC133 compliant memories, the CAS latency will generally be programmed
to 3 clocks, although the memory specifications should always be consulted to confirm this value. CAS
latency must be programmed in two places: the chip select Control Register and the SDRAM Mode
Register. See Table 17-5 for a description of the control register encoding and Section 17.5.4, “Mode
Register Programming,” for the details on programming the SDRAM mode register.
17.5.2.2
Row Precharge Delay
Row precharge delay is defined as the delay between a precharge command and the next row activate
command to the same bank. The SDRAM memory specification provides the minimum precharge delay
as tRP, usually in terms of ns. Therefore the user will have to calculate the number clocks needed for the
row precharge delay and program this value into the SRP bit in SDRAM Control register described in
Table 17-5. For example, a tRP specification of 15 ns with a 133 MHz clock (7.52 ns period) results in
1.995 clocks, rounded to 2.
17.5.2.3
Row-to-Column Delay
The row-to-column delay is defined as the delay between a row activate command and a subsequent read
or write command. The SDRAM memory specification provides the minimum row-to-column (or
ACTIVE to READ or WRITE) delay as tRCD, usually in terms of ns. Given the system bus speed, the user
must calculate the number of clocks needed after an activate command is given before the subsequent read
or write command and program this value into the SRCD bit field in the SDRAM Control register, as
described in Table 17-5. For example, a tRCD specification of 15 ns with a 133 MHz clock (7.52 ns period)
results in 1.995 clocks, rounded to 2.
i.MX21 Reference Manual, Rev. 3
17-52
Freescale Semiconductor
SDRAM Memory Controller
17.5.2.4
Row Cycle Delay
Row cycle delay is defined as the delay between a refresh and any subsequent refresh or read/write access.
The SDRAM memory data sheet usually denotes this timing parameter as the Auto Refresh period tRFC,
and is specified in terms of ns. Given the system bus speed, the user must calculate the number of clocks
after a refresh command is given before the next refresh or read/write command is issued. This value must
then be programmed into the SRC bit field in the SDRAM Control register. For example, a tRFC
specification of 66 ns with a 133 MHz clock results in a minimum of 8.78 clocks, rounded to 9. Therefore,
SRC must be set for 9 clocks.
17.5.2.5
Refresh Rate
The refresh rate is the rate by which the SDRAM controller is required to refresh each row in the SDRAM
memory. The SDRAM memory specification provides the total number of rows per bank, and the
corresponding refresh rate must be programmed into the SREFR field in the SDRAM control register (See
Table 17-5). For example, if the SDRAM memory contains 8192 rows, or requires 8192 AUTO REFRESH
cycles every 64 ms, then the refresh rate can be calculated as 64 ms / 8192 rows = 7.81 μs per row.
Therefore the user programs the SREFR field with 11. Refer to Section 17.4.2, “Refresh,” on page -42 for
more information.
17.5.2.6
Memory Configuration Examples
Nine different SDRAM configurations are demonstrated. These examples are 64 Mbit, 128 Mbit, and 256
Mbit SDRAM memories in single x16, dual x16, and single x32 configurations. All examples use bank
address interleaving (Control Register bit IAM = 1).
All single-configuration 16-bit examples are shown connected to the lower half of the data bus.
Alternatively, the memory can be connected to the upper half of the data bus by swapping the data
connections to D [31:16] and the data qualifier mask connections to DQM3 and DQM2. In this case, it will
be necessary to program the DSIZ field in the Control Register to a value of 0 (configurations shown
require a value of 1).
For a more comprehensive look at the memory configuration schemes, refer to the address muxing tables
in section 17.5.2.7 "Address Muxing Tables".
NOTE
The following examples assume that the number of rows and columns for
each given SDRAM density follow the JEDEC standard. The SDRAM
Controller can interface to SDRAMS which do not follow the JEDEC
standards for row and column sizes, however the user must ensure that the
SDRAM Control Register bits ROW and COL are programmed to the
appropriate number of rows and columns given in the SDRAM data sheet.
These examples do not cover non-JEDEC standard SDRAMS.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-53
SDRAM Memory Controller
Table 17-12. Single 8Mx16 Control Register Values
Control Field
Value
Density
16 Mbyte
Page Size
1024
ROW
12
COL
9
DSIZ
16 (D [15:0])
IAM
Interleaved
A23
A22
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RAS
CAS
CSD0
SDWE
RAS
CAS
CS
WE
DQM3
DQM2
DQMH
DQM1
DQM0
DQML
D[15:0]
DQ[15:0]
SDCLK
CLK
SDCKE0
CKE
SDRAM
CONTROLLER
8M x 16
SDRAM
Figure 17-37. Single 128 Mbit (8M x 16) Connection Diagram (IAM = 1)
i.MX21 Reference Manual, Rev. 3
17-54
Freescale Semiconductor
SDRAM Memory Controller
Table 17-13. Single 16Mx16 Control Register Values
Control Field
Value
Density
32 Mbyte
Page Size
1024
ROW
13
COL
9
DSIZ
16 (D [15:0])
IAM
Interleaved
A23
A22
A19
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RAS
CAS
CSD0
SDWE
RAS
CAS
CS
WE
DQM3
DQM2
DQMH
DQM1
DQM0
DQML
D[15:0]
DQ[15:0]
SDCLK
CLK
SDCKE0
CKE
SDRAM
CONTROLLER
16M x 16
SDRAM
Figure 17-38. Single 256 Mbit (16M x 16) Connection Diagram (IAM = 1)
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-55
SDRAM Memory Controller
Table 17-14. Dual 4Mx16 Control Register Values
Control Field
Value
Density
16 Mbyte
Page Size
1024
ROW
12
COL
8
DSIZ
32 (D [31:0])
IAM
Interleaved
CLK
CKE
BA1
BA0
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
SDCLK
SDCKE
A23
A22
A18
MA[11:10],A[10:2]
RAS
CAS
CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
DQ[15:0]
D[31:16]
D[15:0]
4M x 16
SDRAM
SDRAM
CONTROLLER
CLK
CKE
BA1
BA0
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
4M x 16
SDRAM
Figure 17-39. Dual 64 Mbit (4M x 16 x 2) Connection Diagram (IAM = 1)
i.MX21 Reference Manual, Rev. 3
17-56
Freescale Semiconductor
SDRAM Memory Controller
Table 17-15. Dual 8Mx16 Control Register Values
Control Field
Value
Density
32 Mbyte
Page Size
2048
ROW
12
COL
9
DSIZ
32 (D [31:0])
IAM
Interleaved
CLK
CKE
BA1
BA0
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
SDCLK
SDCKE
A24
A23
A19
MA[11,10],A[10:2]
RAS
CAS
CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
D[31:16]
D[15:0]
DQ[15:0]
SDRAM
CONTROLLER
8M x 16
SDRAM
CLK
CKE
BA1
BA0
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
8M x 16
SDRAM
Figure 17-40. Dual 128 Mbit (8M x 16 x 2) Connection Diagram (IAM = 1)
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-57
SDRAM Memory Controller
Table 17-16. Dual 16Mx16 Control Register Values
Control Field
Value
Density
64 Mbyte
Page Size
2048
ROW
13
COL
9
DSIZ
32 (D [31:0])
IAM
Interleaved
CLK
CKE
BA1
BA0
A12
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
SDCLK
SDCKE
A24
A23
A20
A19
MA[11,10],A[10:2]
RAS
CAS
CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
D[31:16]
DQ[15:0]
D[15:0]
16M x 16
SDRAM
SDRAM
CONTROLLER
CLK
CKE
BA1
BA0
A12
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
16M x 16
SDRAM
Figure 17-41. Dual 256 Mbit (16M x 16 x 2) Connection Diagram (IAM = 1)
i.MX21 Reference Manual, Rev. 3
17-58
Freescale Semiconductor
SDRAM Memory Controller
Table 17-17. Single 2Mx32 Control Register Values
Control Field
Value
Density
8 Mbyte
Page Size
1024
ROW
11
COL
8
DSIZ
32 (D [31:0])
IAM
Interleaved
A23
A22
BA1
BA0
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RAS
CAS
CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
RAS
CAS
CS
WE
DQM3
DQM2
DQM1
DQM0
D[31:0]
DQ[31:0]
SDCLK
SDCKE
CLK
CKE
SDRAM
CONTROLLER
2M x 32
SDRAM
Figure 17-42. Single 64 Mbit (2M x 32) Connection Diagram (IAM = 1)
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-59
SDRAM Memory Controller
Table 17-18. Single 4Mx32 Control Register Values
Control Field
Value
Density
16 Mbyte
Page Size
1024
ROW
12
COL
8
DSIZ
32 (D [31:0])
IAM
Interleaved
A23
A22
A18
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RAS
CAS
CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
RAS
CAS
CS
WE
DQM3
DQM2
DQM1
DQM0
D[31:0]
DQ[31:0]
SDCLK
SDCKE
CLK
CKE
SDRAM
CONTROLLER
4M x 32
SDRAM
Figure 17-43. Single 128 M Mbit (4M x 32) Connection Diagram (IAM = 1)
NOTE
JEDEC has not issued a standard pinout and array configuration for the 128
Mbit density memories in a x32 package option. This connection diagram is
based on the PC133 Standard.
i.MX21 Reference Manual, Rev. 3
17-60
Freescale Semiconductor
SDRAM Memory Controller
Table 17-19. Single 8Mx32 Control Register Values
Control Field
Value
Density
32 Mbyte
Page Size
1024
ROW
12
COL
9
DSIZ
32 (D [31:0])
IAM
Interleaved
A24
A23
A19
BA1
BA0
A11
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RAS
CAS
CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
RAS
CAS
CS
WE
DQM3
DQM2
DQM1
DQM0
D[31:0]
DQ[31:0]
SDCLK
SDCKE
CLK
CKE
SDRAM
CONTROLLER
8M x 32
SDRAM
Figure 17-44. Single 256 Mbit (8M x 32) Connection Diagram (IAM = 1)
NOTE
JEDEC has not issued a standard pinout and array configuration for the 256
Mbit density memories in a ×32 package option. This connection diagram
is based on the PC133 Standard.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-61
SDRAM Memory Controller
17.5.2.7
Address Muxing Tables
The following tables detail the address multiplexing scheme from the ARM AHB through the SDRAM
controller and out to the external address bus, and illustrates how the SDRAM memory address bus is
interfaced to the external address bus for common memory configurations.
ARM_A1
C0
MA0
ARM_A2
C1
MA1
ARM_A3
C2
MA2
ARM_A4
C3
MA3
ARM_A5
C4
MA4
ARM_A6
C5
MA5
ARM_A7
C6
MA6
ARM_A8
C7
MA7
ARM_A9
C8
MA8
ARM_A10
R0
MA0
ARM_A11
R1
MA1
ARM_A12
R2
MA2
ARM_A13
R3
MA3
ARM_A14
R4
MA4
ARM_A15
R5
MA5
ARM_A16
R6
MA6
ARM_A17
R7
MA7
ARM_A18
R8
MA8
ARM_A19
R9
MA9
ARM_A20
R10
MA10
ARM_A21
R11
MA11
ARM_A22
BA0
ARM_A22
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
Rotate Columns bits around
row/column folding point
MA11
SDRAM
Controller
row/column
Address
Muxing
ARM_A22
BA1
SDRAM
Controller
Muxing
Scheme
ARM_A23
Bank, Row,
Column
ARM_A23
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
ARM_A23
Table 17-20. 8Mx16x1 IAM=0 SDRAM Address Translation Table
i.MX21
A6
A5
A4
A3
A2
A1
A4
A3
A2
A1
A0
A9
A8
A5
A10
A9
A7
MA10
A10
A6
MA11
A11
A8
A17
BA0
A7
A18
SDRAM
Address
Signals
BA1
i.MX21 to
SDRAM interface
External
Address
Signals
i.MX21 Reference Manual, Rev. 3
17-62
Freescale Semiconductor
Freescale Semiconductor
A3
A2
A1
A23
A22
A2
A1
A0
BA1
BA0
A7
A6
A4
A8
A7
A3
A9
A8
A5
A10
A9
A4
MA10
SDRAM
Address
Signals
A10
ARM_A10
ARM_A11
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
SDRAM
Controller
row/column
Address
Muxing
A6
MA11
C0
C8
MA8
MA0
BA0
ARM_A10
C1
BA1
ARM_A11
MA1
R0
MA0
C2
R1
MA1
MA2
R2
MA2
C3
R3
MA3
MA3
R4
MA4
C4
R5
MA5
MA4
R6
MA6
C5
R7
MA7
MA5
R8
MA8
C6
R9
MA9
MA6
R10
MA10
C7
R11
SDRAM
Controller
Muxing
Scheme
MA7
Bank, Row,
Column
MA11
ARM_A1
ARM_A2
ARM_A3
ARM_A4
ARM_A5
ARM_A6
ARM_A7
ARM_A8
ARM_A9
ARM_A10
ARM_A11
ARM_A12
ARM_A13
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
ARM_A19
ARM_A20
ARM_A21
ARM_A22
ARM_A23
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
A5
i.MX21
External
Address
Signals
A11
SDRAM Memory Controller
Table 17-21. 8Mx16x1 IAM=1 SDRAM Address Translation Table
Rotate Columns bits around
row/column folding point
i.MX21 to
SDRAM interface
i.MX21 Reference Manual, Rev. 3
17-63
17-64
A6
A5
A4
A3
A2
A1
A5
A4
A3
A2
A1
A0
A10
A9
A7
MA10
A10
A6
MA11
A11
A8
A17
A12
A7
A18
SDRAM
Address
Signals
BA0
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
ARM_A22
ARM_A23
ARM_A24
SDRAM
Controller
row/column
Address
Muxing
A9
A19
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
C8
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
MA8
C4
C3
C2
C1
C0
MA4
MA3
MA2
MA1
MA0
C5
R10
MA10
MA5
R11
MA11
C6
R12
ARM_A22
MA6
BA0
ARM_A23
C7
BA1
SDRAM
Controller
Muxing
Scheme
MA7
Bank, Row,
Column
ARM_A24
ARM_A1
ARM_A2
ARM_A3
ARM_A4
ARM_A5
ARM_A6
ARM_A7
ARM_A8
ARM_A9
ARM_A10
ARM_A11
ARM_A12
ARM_A13
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
ARM_A19
ARM_A20
ARM_A21
ARM_A22
ARM_A23
ARM_A24
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
A8
i.MX21
External
Address
Signals
BA1
SDRAM Memory Controller
Table 17-22. 16Mx16x1 IAM=0 SDRAM Address Translation Table
Rotate Columns bits around
row/column folding point
i.MX21 to
SDRAM interface
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
Freescale Semiconductor
A4
A3
A2
A1
A23
A22
A3
A2
A1
A0
BA1
BA0
A8
A7
A5
A9
A8
A4
A10
A9
A6
MA10
A10
A5
MA11
SDRAM
Address
Signals
A11
ARM_A10
ARM_A11
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
ARM_A24
SDRAM
Controller
row/column
Address
Muxing
A7
A19
C8
MA8
C0
BA0
ARM_A10
MA0
BA1
ARM_A11
C1
R0
MA0
MA1
R1
MA1
C2
R2
MA2
MA2
R3
MA3
C3
R4
MA4
MA3
R5
MA5
C4
R6
MA6
MA4
R7
MA7
C5
R8
MA8
MA5
R9
MA9
C6
R10
MA10
MA6
R11
MA11
C7
R12
SDRAM
Controller
Muxing
Scheme
MA7
Bank, Row,
Column
ARM_A24
ARM_A1
ARM_A2
ARM_A3
ARM_A4
ARM_A5
ARM_A6
ARM_A7
ARM_A8
ARM_A9
ARM_A10
ARM_A11
ARM_A12
ARM_A13
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
ARM_A19
ARM_A20
ARM_A21
ARM_A22
ARM_A23
ARM_A24
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
A6
i.MX21
External
Address
Signals
A12
SDRAM Memory Controller
Table 17-23. 16Mx16x1 IAM=1 SDRAM Address Translation Table
Rotate Columns bits around
row/column folding point
i.MX21 to
SDRAM interface
i.MX21 Reference Manual, Rev. 3
17-65
17-66
i.MX21
i.MX21 to
External
Address
Signals
SDRAM interface
A18
A17
A16
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
SDRAM
Address
Signals
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SDRAM
Controller
row/column
Address
Muxing
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
ARM_A21
ARM_A22
C0
MA1
R0
MA1
C1
R1
MA2
MA2
R2
MA3
C2
R3
MA4
MA3
R4
MA5
C3
R5
MA6
MA4
R6
MA7
C4
R7
MA8
MA5
R8
MA9
C5
R9
MA10
MA6
R10
MA11
C6
R11
ARM_A21
MA7
BA0
ARM_A22
C7
BA1
SDRAM
Controller
Muxing
Scheme
MA8
Bank, Row,
Column
ARM_A23
ARM_A2
ARM_A3
ARM_A4
ARM_A5
ARM_A6
ARM_A7
ARM_A8
ARM_A9
ARM_A10
ARM_A11
ARM_A12
ARM_A13
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
ARM_A19
ARM_A20
ARM_A21
ARM_A22
ARM_A23
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
ARM_A23
SDRAM Memory Controller
Table 17-24. 4Mx16x2 IAM=0 SDRAM Address Translation Table
Rotate Columns bits around
row/column folding point
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
i.MX21
External
Address
Signals
A18
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
A23
A22
SDRAM
Address
Signals
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA1
BA0
SDRAM
Controller
row/column
Address
Muxing
Freescale Semiconductor
ARM_A10
ARM_A11
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
C0
MA1
BA0
ARM_A10
C1
BA1
ARM_A11
MA2
R0
MA1
C2
R1
MA2
MA3
R2
MA3
C3
R3
MA4
MA4
R4
MA5
C4
R5
MA6
MA5
R6
MA7
C5
R7
MA8
MA6
R8
MA9
C6
R9
MA10
MA7
R10
MA11
C7
R11
SDRAM
Controller
Muxing
Scheme
MA8
Bank, Row,
Column
ARM_A23
ARM_A2
ARM_A3
ARM_A4
ARM_A5
ARM_A6
ARM_A7
ARM_A8
ARM_A9
ARM_A10
ARM_A11
ARM_A12
ARM_A13
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
ARM_A19
ARM_A20
ARM_A21
ARM_A22
ARM_A23
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
ARM_A23
SDRAM Memory Controller
Table 17-25. 4Mx16x2 IAM=1 SDRAM Address Translation Table
Rotate Columns bits around
row/column folding point
i.MX21 to
SDRAM interface
i.MX21 Reference Manual, Rev. 3
17-67
i.MX21
External
Address
Signals
A19
A18
A17
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
SDRAM
Address
Signals
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SDRAM
Controller
row/column
Address
Muxing
17-68
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
ARM_A22
ARM_A23
R8
R7
R6
R5
R4
R3
R2
R1
R0
C8
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA9
C4
C3
C2
C1
C0
MA5
MA4
MA3
MA2
MA1
C5
R9
MA10
MA6
R10
MA11
C6
R11
ARM_A21
MA7
BA0
ARM_A22
C7
BA1
SDRAM
Controller
Muxing
Scheme
MA8
Bank, Row,
Column
ARM_A23
ARM_A2
ARM_A3
ARM_A4
ARM_A5
ARM_A6
ARM_A7
ARM_A8
ARM_A9
ARM_A10
ARM_A11
ARM_A12
ARM_A13
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
ARM_A19
ARM_A20
ARM_A21
ARM_A22
ARM_A23
ARM_A24
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
ARM_A24
SDRAM Memory Controller
Table 17-26. 8Mx16x2 IAM=0 SDRAM Address Translation Table
Rotate Columns bits around
row/column folding point
i.MX21 to
SDRAM interface
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
i.MX21
External
Address
Signals
A19
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
A24
A23
SDRAM
Address
Signals
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA1
BA0
SDRAM
Controller
row/column
Address
Muxing
Freescale Semiconductor
ARM_A11
ARM_A12
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
C0
C8
MA9
MA1
BA0
ARM_A11
C1
BA1
ARM_A12
MA2
R0
MA1
C2
R1
MA2
MA3
R2
MA3
C3
R3
MA4
MA4
R4
MA5
C4
R5
MA6
MA5
R6
MA7
C5
R7
MA8
MA6
R8
MA9
C6
R9
MA10
MA7
R10
MA11
C7
R11
SDRAM
Controller
Muxing
Scheme
MA8
Bank, Row,
Column
ARM_A24
ARM_A2
ARM_A3
ARM_A4
ARM_A5
ARM_A6
ARM_A7
ARM_A8
ARM_A9
ARM_A10
ARM_A11
ARM_A12
ARM_A13
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
ARM_A19
ARM_A20
ARM_A21
ARM_A22
ARM_A23
ARM_A24
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
ARM_A24
SDRAM Memory Controller
Table 17-27. 8Mx16x2 IAM=1 SDRAM Address Translation Table
Rotate Columns bits around
row/column folding point
i.MX21 to
SDRAM interface
i.MX21 Reference Manual, Rev. 3
17-69
17-70
A7
A6
A5
A4
A3
A2
A5
A4
A3
A2
A1
A0
MA10
A9
A8
MA11
A10
A6
A17
A11
A9
A18
A12
A7
A19
SDRAM
Address
Signals
BA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
ARM_A22
ARM_A23
ARM_A24
ARM_A25
SDRAM
Controller
row/column
Address
Muxing
A10
A20
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
C8
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA9
C4
C3
C2
C1
C0
MA5
MA4
MA3
MA2
MA1
C5
R10
MA11
MA6
R11
ARM_A22
C6
R12
ARM_A23
MA7
BA0
ARM_A24
C7
BA1
SDRAM
Controller
Muxing
Scheme
MA8
Bank, Row,
Column
ARM_A25
ARM_A2
ARM_A3
ARM_A4
ARM_A5
ARM_A6
ARM_A7
ARM_A8
ARM_A9
ARM_A10
ARM_A11
ARM_A12
ARM_A13
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
ARM_A19
ARM_A20
ARM_A21
ARM_A22
ARM_A23
ARM_A24
ARM_A25
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
A8
i.MX21
External
Address
Signals
BA1
SDRAM Memory Controller
Table 17-28. 16Mx16x2 IAM=0 SDRAM Address Translation Table
Rotate Columns bits around
row/column folding point
i.MX21 to
SDRAM interface
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
Freescale Semiconductor
A5
A4
A3
A2
A24
A23
A3
A2
A1
A0
BA1
BA0
A9
A7
A6
A10
A8
A4
MA10
A9
A7
MA11
A10
A5
A19
SDRAM
Address
Signals
A11
ARM_A11
ARM_A12
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
ARM_A24
ARM_A25
SDRAM
Controller
row/column
Address
Muxing
A8
A20
C8
MA9
C0
BA0
ARM_A11
MA1
BA1
ARM_A12
C1
R0
MA1
MA2
R1
MA2
C2
R2
MA3
MA3
R3
MA4
C3
R4
MA5
MA4
R5
MA6
C4
R6
MA7
MA5
R7
MA8
C5
R8
MA9
MA6
R9
MA10
C6
R10
MA11
MA7
R11
ARM_A24
C7
R12
SDRAM
Controller
Muxing
Scheme
MA8
Bank, Row,
Column
ARM_A25
ARM_A2
ARM_A3
ARM_A4
ARM_A5
ARM_A6
ARM_A7
ARM_A8
ARM_A9
ARM_A10
ARM_A11
ARM_A12
ARM_A13
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
ARM_A19
ARM_A20
ARM_A21
ARM_A22
ARM_A23
ARM_A24
ARM_A25
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
A6
i.MX21
External
Address
Signals
A12
SDRAM Memory Controller
Table 17-29. 16Mx16x2 IAM=1 SDRAM Address Translation Table
Rotate Columns bits around
row/column folding point
i.MX21 to
SDRAM interface
i.MX21 Reference Manual, Rev. 3
17-71
SDRAM Memory Controller
ARM_A2
C0
MA1
ARM_A3
C1
MA2
ARM_A4
C2
MA3
ARM_A5
C3
MA4
ARM_A6
C4
MA5
ARM_A7
C5
MA6
ARM_A8
C6
MA7
ARM_A9
C7
MA8
ARM_A10
R0
MA1
ARM_A11
R1
MA2
ARM_A12
R2
MA3
ARM_A13
R3
MA4
ARM_A14
R4
MA5
ARM_A15
R5
MA6
ARM_A16
R6
MA7
ARM_A17
R7
MA8
ARM_A18
R8
MA9
ARM_A19
R9
MA10
ARM_A20
R10
MA11
ARM_A21
BA0
ARM_A21
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
Rotate Columns bits around
row/column folding point
A7
A6
A5
A4
A3
A2
A4
A3
A2
A1
A0
A8
A5
A10
A9
A8
MA10
A10
A6
MA11
BA0
A9
A16
SDRAM
Address
Signals
A7
A17
i.MX21 to
SDRAM interface
i.MX21
External
Address
Signals
BA1
SDRAM
Controller
row/column
Address
Muxing
ARM_A21
BA1
SDRAM
Controller
Muxing
Scheme
ARM_A22
Bank, Row,
Column
ARM_A22
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
ARM_A22
Table 17-30. 2Mx32 IAM=0 SDRAM Address Translation Table
i.MX21 Reference Manual, Rev. 3
17-72
Freescale Semiconductor
SDRAM Memory Controller
ARM_A2
C0
MA1
ARM_A3
C1
MA2
ARM_A4
C2
MA3
ARM_A5
C3
MA4
ARM_A6
C4
MA5
ARM_A7
C5
MA6
ARM_A8
C6
MA7
ARM_A9
C7
MA8
ARM_A10
BA0
ARM_A10
ARM_A10
ARM_A11
BA1
ARM_A11
ARM_A11
ARM_A12
R0
MA1
MA1
ARM_A13
R1
MA2
MA2
ARM_A14
R2
MA3
MA3
ARM_A15
R3
MA4
MA4
ARM_A16
R4
MA5
MA5
ARM_A17
R5
MA6
MA6
ARM_A18
R6
MA7
MA7
ARM_A19
R7
MA8
MA8
ARM_A20
R8
MA9
MA9
ARM_A21
R9
MA10
Rotate Columns bits around
row/column folding point
A5
A4
A3
A2
A23
A22
A2
A1
A0
BA1
BA0
A6
A3
A8
A7
A6
A9
A8
A4
A10
A9
A7
MA10
SDRAM
Address
Signals
A5
MA11
i.MX21 to
SDRAM interface
i.MX21
External
Address
Signals
A10
SDRAM
Controller
row/column
Address
Muxing
MA10
R10
SDRAM
Controller
Muxing
Scheme
MA11
Bank, Row,
Column
MA11
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
ARM_A22
Table 17-31. 2Mx32 IAM=1 SDRAM Address Translation Table
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-73
17-74
A9
A8
A7
A6
A5
A4
A3
A2
A6
A5
A4
A3
A2
A1
A0
MA10
A9
A7
MA10
MA11
A10
A10
MA11
A16
A11
A8
ARM_A21
A17
SDRAM
Address
Signals
BA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
ARM_A22
Bank, Row,
Column
BA1
BA0
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
C7
C6
C5
C4
C3
C2
C1
C0
SDRAM
Controller
Muxing
Scheme
ARM_A23
ARM_A22
ARM_A21
MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
ARM_A2
ARM_A3
ARM_A4
ARM_A5
ARM_A6
ARM_A7
ARM_A8
ARM_A9
ARM_A10
ARM_A11
ARM_A12
ARM_A13
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
ARM_A19
ARM_A20
ARM_A21
ARM_A22
ARM_A23
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
ARM_A23
i.MX21
External
Address
Signals
A18
SDRAM
Controller
row/column
Address
Muxing
BA1
SDRAM Memory Controller
Table 17-32. 4Mx32 IAM=0 SDRAM Address Translation Table
Rotate Columns bits around
row/column folding point
i.MX21 to
SDRAM interface
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
i.MX21
External
Address
Signals
A18
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
A23
A22
SDRAM
Address
Signals
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA1
BA0
SDRAM
Controller
row/column
Address
Muxing
Freescale Semiconductor
ARM_A10
ARM_A11
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
Bank, Row,
Column
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
BA1
BA0
C7
C6
C5
C4
C3
C2
C1
C0
SDRAM
Controller
Muxing
Scheme
ARM_A23
MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
ARM_A11
ARM_A10
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
ARM_A2
ARM_A3
ARM_A4
ARM_A5
ARM_A6
ARM_A7
ARM_A8
ARM_A9
ARM_A10
ARM_A11
ARM_A12
ARM_A13
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
ARM_A19
ARM_A20
ARM_A21
ARM_A22
ARM_A23
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
ARM_A23
SDRAM Memory Controller
Table 17-33. 4Mx32 IAM=1 SDRAM Address Translation Table
Rotate Columns bits around
row/column folding point
i.MX21 to
SDRAM interface
i.MX21 Reference Manual, Rev. 3
17-75
i.MX21
External
Address
Signals
A19
A18
A17
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
SDRAM
Address
Signals
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SDRAM
Controller
row/column
Address
Muxing
17-76
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
ARM_A22
ARM_A23
R8
R7
R6
R5
R4
R3
R2
R1
R0
C8
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA9
C4
C3
C2
C1
C0
MA5
MA4
MA3
MA2
MA1
C5
R9
MA10
MA6
R10
MA11
C6
R11
ARM_A22
MA7
BA0
ARM_A23
C7
BA1
SDRAM
Controller
Muxing
Scheme
MA8
Bank, Row,
Column
ARM_A24
ARM_A2
ARM_A3
ARM_A4
ARM_A5
ARM_A6
ARM_A7
ARM_A8
ARM_A9
ARM_A10
ARM_A11
ARM_A12
ARM_A13
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
ARM_A19
ARM_A20
ARM_A21
ARM_A22
ARM_A23
ARM_A24
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
ARM_A24
SDRAM Memory Controller
Table 17-34. 8Mx32 IAM=0 SDRAM Address Translation Table
Rotate Columns bits around
row/column folding point
i.MX21 to
SDRAM interface
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
i.MX21
External
Address
Signals
A19
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
A24
A23
SDRAM
Address
Signals
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA1
BA0
SDRAM
Controller
row/column
Address
Muxing
Freescale Semiconductor
ARM_A11
ARM_A12
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
C0
C8
MA9
MA1
BA0
ARM_A11
C1
BA1
ARM_A12
MA2
R0
MA1
C2
R1
MA2
MA3
R2
MA3
C3
R3
MA4
MA4
R4
MA5
C4
R5
MA6
MA5
R6
MA7
C5
R7
MA8
MA6
R8
MA9
C6
R9
MA10
MA7
R10
MA11
C7
R11
SDRAM
Controller
Muxing
Scheme
MA8
Bank, Row,
Column
ARM_A24
ARM_A2
ARM_A3
ARM_A4
ARM_A5
ARM_A6
ARM_A7
ARM_A8
ARM_A9
ARM_A10
ARM_A11
ARM_A12
ARM_A13
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
ARM_A19
ARM_A20
ARM_A21
ARM_A22
ARM_A23
ARM_A24
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
ARM_A24
SDRAM Memory Controller
Table 17-35. 8Mx32 IAM=1 SDRAM Address Translation Table
Rotate Columns bits around
row/column folding point
i.MX21 to
SDRAM interface
i.MX21 Reference Manual, Rev. 3
17-77
17-78
A7
A6
A5
A4
A3
A2
A5
A4
A3
A2
A1
A0
MA10
A9
A8
MA11
A10
A6
A17
A11
A9
A18
A12
A7
A19
SDRAM
Address
Signals
BA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
ARM_A22
ARM_A23
ARM_A24
ARM_A25
SDRAM
Controller
row/column
Address
Muxing
A10
A20
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
C8
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA9
C4
C3
C2
C1
C0
MA5
MA4
MA3
MA2
MA1
C5
R10
MA11
MA6
R11
ARM_A22
C6
R12
ARM_A23
MA7
BA0
ARM_A24
C7
BA1
SDRAM
Controller
Muxing
Scheme
MA8
Bank, Row,
Column
ARM_A25
ARM_A2
ARM_A3
ARM_A4
ARM_A5
ARM_A6
ARM_A7
ARM_A8
ARM_A9
ARM_A10
ARM_A11
ARM_A12
ARM_A13
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
ARM_A19
ARM_A20
ARM_A21
ARM_A22
ARM_A23
ARM_A24
ARM_A25
i.MX21 AHB
Address
Bus
(denoted as
ARM_Axx)
A8
i.MX21
External
Address
Signals
BA1
SDRAM Memory Controller
Table 17-36. 16Mx32 IAM=0 SDRAM Address Translation Table
Rotate Columns bits around
row/column folding point
i.MX21 to
SDRAM interface
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
SDRAM Memory Controller
ARM_A2
C0
MA1
ARM_A3
C1
MA2
ARM_A4
C2
MA3
ARM_A5
C3
MA4
ARM_A6
C4
MA5
ARM_A7
C5
MA6
ARM_A8
C6
MA7
ARM_A9
C7
MA8
ARM_A10
C8
MA9
ARM_A11
BA0
ARM_A11
ARM_A11
ARM_A12
BA1
ARM_A12
ARM_A12
ARM_A13
R0
MA1
MA1
ARM_A14
R1
MA2
MA2
ARM_A15
R2
MA3
MA3
ARM_A16
R3
MA4
MA4
ARM_A17
R4
MA5
MA5
ARM_A18
R5
MA6
MA6
ARM_A19
R6
MA7
MA7
ARM_A20
R7
MA8
MA8
ARM_A21
R8
MA9
MA9
ARM_A22
R9
MA10
MA10
ARM_A23
R10
17.5.3
A6
A5
A4
A3
A2
A24
A23
A3
A2
A1
A0
BA1
BA0
A9
A7
A4
A10
A8
A7
MA10
A9
A5
MA11
A10
A8
A19
A11
A6
A20
SDRAM
Address
Signals
Rotate Columns bits around
row/column folding point
i.MX21 to
SDRAM interface
A12
i.MX21
External
Address
Signals
MA11
MA11
ARM_A24
R11
ARM_A24
SDRAM
Controller
row/column
Address
Muxing
ARM_A24
R12
SDRAM
Controller
Muxing
Scheme
ARM_A25
Bank, Row,
Column
ARM_A25
i.MX21 AHB
Address Bus
(denoted as
ARM_Axx)
ARM_A25
Table 17-37. 16Mx32 IAM=1 SDRAM Address Translation Table
SDRAM Reset Initialization
SDRAM initialization must follow a defined sequence following the power-on condition. The steps are as
follows:
1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP conditions at
the command inputs.
2. Maintain stable power, clock and NOP conditions for a minimum of 200 μs.
3. Issue precharge commands for all banks either with precharge all or precharge individual bank
commands.
4. After all banks are in the idle state for a minimum time of tRP, issue 8 or more auto-refresh
commands.
5. Issue a mode register set command to initialize the mode register.
6. SDRAM is now ready for normal operation.
The SDRAM Controller accomplishes steps 1 and 2 in hardware, but relies on software assistance to
complete the remaining actions. The 200 μs stabilization period is guaranteed by the use of 2 reset signals
whose negations are separated by this amount. An SDRAM reset signal (SD_RST) is asserted coincident
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-79
SDRAM Memory Controller
with the system reset used by the rest of the chip, but it negates 200 μs prior to the negation of system reset.
The SDRAM Controller leaves the SDRAM arrays in a NOP condition following the negation of the
DRAM reset.
VCC
SYSTEM
CLOCK
DRAM
RESET
200 μs Minimum
HARD_ASYN_
RESET
SDCLK
SDRAM
COMMAND
NOP
PRE
ALL
AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO MODE NORMAL
REF REF REF REF REF REF REF REF SET
SDRAM Software Initialization Sequence
Figure 17-45. SDRAM Power-On Initialization Sequence
Following negation of system reset, initialization software must complete steps 3 through 5 using the
special operating modes enabled by the SMODE field in the SDRAM Control Register. To precharge the
SDRAM array, the SDRAM Controller operating mode is set to “precharge command” and an access is
made to the SDRAM address range with address bit A10 = 1. Instead of running a normal read or write
cycle, the controller issues a precharge all command to the addressed array. The operating mode is then
switched to “auto-refresh” and 8 accesses made to the SDRAM address space. Each of the accesses will
result in a refresh command to the addressed array. A “mode register set” command is required to complete
the initialization sequence. The value written is system dependent. Consult Section 17.5.4, “Mode
Register Programming,” for details. Finally, the controller is placed back in the normal mode of operation
so that subsequent accesses to the address space will result in normal read and write cycles to the SDRAM
array.
Although the initialization sequence described in the previous paragraphs is only required at power-on, it
may be repeated at any time the programmer deems necessary.
i.MX21 Reference Manual, Rev. 3
17-80
Freescale Semiconductor
SDRAM Memory Controller
Example 17-1. init_sdram
init_sdram:
ldr
ldr
st
st
ldr
ldr
ld
ld
ldr
st
st
movi
L1
ld
ld
decgt
bt
ldr
st
st
ldr
ld
ldr
ld
ldr
st
st
r2,CSD_REGS
r3,PRE_ALL_CMD
r3,(0,r2)
r3,(4,r2)
r4,SDRAM_ARRAY_0
r5,SDRAM_ARRAY_1
r3,(0,r4)
r3,(0,r5)
r3,AUTO_REF_CMD
r3,(0,r2)
r3,(4,r2)
r6,7
r3,(0,r4)
r3,(0,r5)
r6
L1
r3,SET_MODE_REG_CMD
r3,(0,r2)
r3,(4,r2)
r3,MODE_REG_VAL0
r3,(0,r3)
r3,MODE_REG_VAL1
r3,(0,r3)
r3,NORMAL_MODE
r3,(0,r2)
r3,(4,r2)
CSD_REGS
.long
SDRAM_ARRAY_0:
.long
SDRAM ARRAY_1:
.long
PRE_ALL_CMD
.long
AUTO_REF_CMD
.long
SET_MODE_REG_CMD.long
MODE_REG_VAL0
.long
MODE_REG_VAL1
.long
NORMAL_MODE
.long
17.5.4
// base address of registers
//
//
//
//
//
//
put array 0 in precharge command mode
put array 1 in precharge command mode
get address of first array
get address of second array
precharge array 0
precharge array 1
//
//
//
//
//
put array 0 in auto-refresh mode
put array 1 in auto-refresh mode
load loop counter
run auto-refresh cycle to array 0
run auto-refresh cycle to array 1
// 8 refresh cycles complete?
//
//
//
//
//
//
setup CSD0 for mode register write
setup CSD1 for mode register write
array 0 mode register value
New mode register value on address bus
array 1 mode register value
Write CSD1 mode register
// setup CSD0 for normal operation
// setup CSD1 for normal operation
0xDF000000
0xC0000000
0xC4000000
0xXXXXXXXX
0xXXXXXXXX
0xXXXXXXXX
0xXXXXXXXX
0xXXXXXXXX
0xXXXXXXXX
Mode Register Programming
The mode register is used to set the SDRAM operating characteristics including CAS latency, burst length,
burst mode, and write data length. The settings depend on system characteristics including the operating
frequency, memory device type, burst buffer/cache line length, and bus width. Operating characteristics
vary by device type, so the data sheet must be consulted to determine the actual value to be written. In
order to demonstrate the procedure, the following system characteristics will be used:
• 2 JEDEC Standard 64 Mbit (4M x 16) SDR SDRAMs configured as a x32 memory in bank
interleaved mode (IAM = 1)
• 133 MHz System Clock Frequency
• Sequential burst, burst length of 8
• Single word writes—that is, no bursting on writes
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-81
SDRAM Memory Controller
Table 17-38 illustrates the Mode Register bit assignments for the 64 Mbit SDRAM.
64 Mbit SDRAM Mode Register
TYPE
BA0
BA1
A11
A10
A9
A8
A7
0
0
0
0
WM
0
0
A6
A5
A4
LTMODE
A3
BT
A2
A1
A0
BL
Table 17-38. SDRAM Mode Register Description
Name
Description
Settings
WM
Bit A9
Write Mode—Selects between burst writes and single location writes
0 = Burst Writes
1 = Single Word Writes
LTMODE
Bits A6–A4
Latency Mode—Sets latency between column address and data
000 = Reserved
001 = 1 clock
010 = 2 clocks
011 = 3 clocks
1xx = Reserved
BT
Bit A3
Burst Type—Selects burst type
0 = Sequential
1 = Interleave
BL
Bits A2–A0
Burst Length—A burst length of four matches the M340 cache line length when the 000 = 1
SDRAM is 32 bits wide. A 16 bit wide SDRAM requires a burst length of eight
001 = 2
because the four 32-bit line fill cycles will be decomposed into eight 16-bit accesses. 010 = 4
011 = 8
111 = Full Page
10x = Reserved
1x0 = Reserved
For this example:
• Sequential burst (BT = 0)
• Burst length of 8 (BL = 011)
• Single word writes (WM = 1)
• 3 Clock Latency (LTMODE = 011)
Once the mode register value has been determined, it must be converted to an address. The mode register
is written via the address bus and the memory data sheet will specify the SDRAM address bits on which
to place the data. One final transformation is necessary to align the address to the multiplexed outputs of
the SDRAM Controller. Memory density and bus width determine the alignment of the SDRAM to the
controller pins and must be taken into account during the calculation. Table 17-39 provides an example
calculation using the same system characteristics used in the previous example.
i.MX21 Reference Manual, Rev. 3
17-82
Freescale Semiconductor
SDRAM Memory Controller
Table 17-39. Example Address Calculation for Mode Set
Mode
Register
Program
Value
SDRAM
Pin
Controller
Pin
ARM9
Address
0
0
0
0
WM
0
0
LTMODE
BT
BL
0
0
0
0
1
0
0
0
1
1
0
0
1
1
BA0
BA1
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ARM_
MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1
A23
ARM_ ARM_ ARM_ ARM_ ARM_ ARM ARM ARM ARM ARM ARM ARM ARM ARM
A11
A10
A23
A22
A21 _A20 _A19 _A18 _A17 _A16 _A15 _A14 _A13 _A12
BA0
BA1
ARM_ ARM_ ARM_ ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM
A23
A22
A21 _A20 _A19 _A18 _A17 _A16 _A15 _A14 _A13 _A12 _A11 _A10
ARM_A31–
ARM_A24
Mode
Address
CSDx Base
0
0
1
0
0
0
1
1
0
0
1
1
0
0
The following two tables illustrate the mode register bits relative to the internal AHB bus for common
SDRAM memory configurations.
Table 17-40. i.MX21 SDRAM Mode Register Bits Relative to
i.MX21 Internal Address Bus for x16 Configurations
i.MX21 CSDx Base
ARM_A9
ARM_A10
A0[M0]
BA0[M12]
A0[M0]
ARM_A11
A1[M1]
BA1[M13]
A1[M1]
ARM_A12
A2[M2]
A0[M0]
A2[M2]
ARM_A13
A3[M3]
A1[M1]
A3[M3]
ARM_A14
A4[M4]
A2[M2]
A4[M4]
ARM_A15
A5[M5]
A3[M3]
A5[M5]
ARM_A16
A6[M6]
A4[M4]
A6[M6]
0
ARM_A17
x
A7[M7]
0
A5[M5]
0
A7[M7]
0
ARM_A18
x
A8[M8]
x
A6[M6]
0
A8[M8]
16Mx16x
1
ARM_A19
0
A9[M9]
0
A7[M7]
x
A9[M9]
0
ARM_A20
0
A10[M10]
0
A8[M8]
x
A10[M10]
x
ARM_A21
1
A11[M11]
16Mbyte
A9[M9]
0
A11[M11]
ARM_A24
0
ARM_A22
ARM_A25
x
BA0[M12]
ARM_A26
0
A10[M10]
ARM_A27
0
A12[M12]
ARM_A28
0
ARM_A23
ARM_A29
x
BA1[M13]
ARM_A30
x
A11[M11]
ARM_A31
0
BA0[M13]
IAM
8Mx16x1
BA1[M14]
Memory
Configuration
i.MX21 Internal Address Bus (Denoted as ARM_Axx)
0
0
0
SDRAM Memory Address and Mode Register Bits
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
17-83
17-84
ARM_A24
ARM_A23
ARM_A22
ARM_A21
ARM_A20
0
x
x
0
0
0
x
0
0
BA1[M13]
BA0[M12]
A11[M11]
A10[M10]
16Mbyte
1
x
x
0
0
0
x
0
0
A11[M11]
A10[M10]
A9[M9]
8Mx16x2
0
x
x
0
0
0
x
0
x
x
0
0
0
x
0
A10[M10] BA0[M12]
A10[M10]
1
A11[M11] BA1[M13]
A11[M11]
32Mbyte
16Mx16x2
0
x
x
0
0
0
x
BA0[M13]
i.MX21 CSDx Base
A12[M12]
ARM_A9
ARM_A11
ARM_A12
ARM_A13
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
ARM_A19
ARM_A20
ARM_A21
ARM_A9
A0[M0]
A1[M1]
A2[M2]
A3[M3]
A4[M4]
A5[M5]
A6[M6]
A7[M7]
A8[M8]
A9[M9]
ARM_A22
ARM_A23
ARM_A10
0
BA0[M13]
0
ARM_A10
i.MX21 Internal Address Bus (denoted as ARM_Axx)
A0[M0]
BA0[M12]
Table 17-41. SDRAM Mode Register Bits Relative to
i.MX21 Internal Address Bus for x32 Configurations
BA1[M14]
ARM_A12
ARM_A13
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
SDRAM Memory Address and Mode Register Bits
0
ARM_A11
A1[M1]
BA1[M13]
A3[M3]
A4[M4]
A5[M5]
A6[M6]
A7[M7]
A8[M8]
0
A0[M0]
BA0[M12]
A0[M0]
A1[M1]
A1[M1]
A2[M2]
A3[M3]
A4[M4]
A5[M5]
A6[M6]
A7[M7]
A2[M2]
0
A0[M0]
A1[M1]
0
A2[M2]
BA1[M13]
A3[M3]
A4[M4]
A5[M5]
A6[M6]
A7[M7]
A8[M8]
A2[M2]
A1[M1]
A2[M2]
A3[M3]
A4[M4]
A5[M5]
A6[M6]
A7[M7]
A0[M0]
A3[M3]
A4[M4]
A5[M5]
A6[M6]
A7[M7]
A8[M8]
A9[M9]
i.MX21 CSDx Base
A10[M10]
A11[M11]
ARM_A24
0
A12[M12]
ARM_A25
x
ARM_A19
ARM_A25
4Mx16x2
BA1[M14]
ARM_A26
0
A9[M9]
ARM_A26
ARM_A27
0
A8[M8]
ARM_A27
ARM_A28
0
A9[M9]
ARM_A28
ARM_A29
x
A8[M8]
ARM_A29
ARM_A30
x
A10[M10]
ARM_A30
ARM_A31
1
A9[M9]
ARM_A31
Memory
Configuration
IAM
32Mbyte
A11[M11]
IAM
Memory
Configuration
SDRAM Memory Controller
Table 17-40. i.MX21 SDRAM Mode Register Bits Relative to
i.MX21 Internal Address Bus for x16 Configurations (continued)
i.MX21 Internal Address Bus (Denoted as ARM_Axx)
0
0
0
SDRAM Memory Address and Mode Register Bits
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
A9[M9]
A8[M8]
A7[M7]
x
0
0
0
x
0
0
0
BA1[M12]
BA0[M11]
A10[M10]
8Mbyte
1
x
x
0
0
0
x
0
0
0
A10[M10]
A9[M9]
A8[M8]
4Mx32x1
0
x
x
0
0
0
x
0
0
BA1[M13]
BA0[M12]
A11[M11]
A10[M10]
16Mbyte
1
x
x
0
0
0
x
0
0
A11[M11]
A10[M10]
A9[M9]
8Mx32x1
0
x
x
0
0
0
x
0
x
x
0
0
0
x
0
A10[M10] BA0[M12]
A10[M10]
1
A11[M11] BA1[M13]
A11[M11]
32Mbyte
16Mx32x1
0
x
x
0
0
0
x
1
x
x
0
0
0
x
A12[M12] BA1[M14]
A11[M11] BA0[M13]
A12[M12]
64Mbyte
i.MX21 CSDx Base
Freescale Semiconductor
A0[M0]
BA0[M11]
A0[M0]
BA0[M12]
A1[M1]
BA1[M12]
A1[M1]
BA1[M13]
0
0
A0[M0]
BA0[M12]
A0[M0]
BA0[M13]
A3[M3]
A4[M4]
A5[M5]
A6[M6]
A7[M7]
A8[M8]
A2[M2]
A1[M1]
A2[M2]
A3[M3]
A4[M4]
A5[M5]
A6[M6]
A0[M0]
A3[M3]
A4[M4]
A5[M5]
A6[M6]
A7[M7]
A8[M8]
0
A2[M2]
A1[M1]
A2[M2]
A3[M3]
A4[M4]
A5[M5]
A6[M6]
A7[M7]
0
A0[M0]
A1[M1]
A1[M1]
BA1[M14]
0
A2[M2]
BA1[M13]
A3[M3]
A4[M4]
A5[M5]
A6[M6]
A7[M7]
A8[M8]
A2[M2]
A1[M1]
A2[M2]
A3[M3]
A4[M4]
A5[M5]
A6[M6]
A7[M7]
A0[M0]
A3[M3]
A4[M4]
A5[M5]
A6[M6]
A7[M7]
A8[M8]
A9[M9]
0
A0[M0]
A1[M1]
A2[M2]
A3[M3]
A4[M4]
A5[M5]
A6[M6]
A7[M7]
A8[M8]
A9[M9]
ARM_A13
ARM_A12
ARM_A11
ARM_A10
ARM_A9
BA1[M14]
BA0[M13]
ARM_A14
ARM_A15
ARM_A16
ARM_A17
ARM_A18
ARM_A19
ARM_A20
ARM_A21
A0[M0]
A1[M1]
A2[M2]
A3[M3]
A4[M4]
A5[M5]
A6[M6]
A10[M10]
x
A9[M9]
A11[M11]
0
A7[M7]
ARM_A23
A12[M12]
2Mx32x1
A9[M9]
ARM_A24
x
A8[M8]
ARM_A25
0
A9[M9]
ARM_A26
0
A8[M8]
ARM_A27
0
A10[M10]
ARM_A28
x
ARM_A22
ARM_A29
x
A9[M9]
ARM_A30
1
A11[M11]
ARM_A31
64Mbyte
A10[M10]
IAM
Memory
Configuration
SDRAM Memory Controller
Table 17-41. SDRAM Mode Register Bits Relative to
i.MX21 Internal Address Bus for x32 Configurations (continued)
i.MX21 Internal Address Bus (denoted as ARM_Axx)
0
0
0
0
0
0
0
0
SDRAM Memory Address and Mode Register Bits
i.MX21 Reference Manual, Rev. 3
17-85
SDRAM Memory Controller
17.5.5
SDRAM Memory Refresh
SDRAM memory specifications generally specify an interval during which all rows in the device must be
refreshed. The memory refresh requirements are outlined in Table 17-42. The SDRAM Controller refresh
rate (SREFR field of the Control Register) is programmable to meet these varying requirements. Refresh
must be enabled prior to storing data in the memory.
Table 17-42. SDRAM Memory Refresh
Device
Size
Array Size
Refresh
Interval
Refresh Rate
Requirement
SREFR
Value
64 MBit
4096 rows
64 ms
1 row every 15.6 µseconds
2 rows refreshed during
each 32 KHz clock
10
128 MBit
4096 rows
64 ms
1 row ever 15.6 µseconds
2 rows refreshed during
each 32 KHz clock
10
256 MBit
8192 rows
64 ms
1 row every 7.8 µseconds
4 rows refreshed during
each 32 KHz clock
11
NOTE
The memory datasheet should always be consulted to determine the correct
refresh interval and array architecture (number of rows). Refresh clock rates
other the nominal value require recalculation of the value to be programmed
into REFR.
i.MX21 Reference Manual, Rev. 3
17-86
Freescale Semiconductor
Chapter 18
Direct Memory Access Controller (DMAC)
The Direct Memory Access Controller (DMAC) of the i.MX21 provides 16 channels supporting linear
memory, 2D memory, FIFO transfers to provide support for a wide variety of DMA operations.
The i.MX21 DMAC features are as follows:
• Sixteen channels support linear memory, 2D Memory, FIFO for both source and destination.
• DMA chaining for variable length buffer exchanges and high allowable interrupt latency
requirement.
• Increment, decrement, and no-change support for source and destination addresses.
• Each channel is configurable to response to any of the 32 DMA request signals.
• Supports 8, 16, or 32-bit FIFO and memory port size data transfers.
• DMA burst length configurable up to a maximum of 16 words, 32 half-words, or 64 bytes for each
channel.
• Bus utilization control for the channel that is not trigger by a DMA request.
• Burst time-out errors terminate the DMA cycle when the burst cannot be completed within a
programmed time count.
• Buffer overflow error terminates the DMA cycle when the internal buffer receives more than 64
bytes of data.
• Transfer error terminates the DMA cycle when a transfer error is detected during a DMA burst.
• DMA request time-out errors are generated for channels that are triggered by DMA requests to
interrupt the CPU when a DMA burst does not start on that channel after a programmed time count.
• Interrupts provided to the interrupt controller (and subsequently to the core) on bulk data transfer
complete or transfer error.
• Each peripheral supporting DMA transfer generates a DMA_REQ signal to the DMA controller,
assuming that each FIFO has a unique system address and generates a dedicated dma_req signal to
the DMA controller. For example, a USB device with 8 end-points has 8 DMA request signals to
the DMA if they all support DMA transfer.
• The DMA controller provides an acknowledge signal to the peripheral after a DMA burst is
complete. This signal is sometimes used by the peripheral to clear status bits.
• Repeat data transfer function supports automatic USB host–USB device bulk/iso data stream
transfer.
• Dedicated external DMA request and grant signal.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-1
Direct Memory Access Controller (DMAC)
AHB
Bus
CSPI
IP Bus
AIPI
AHB
CSI
Crossbar
(MAX)
AHB
Bus
IP Bus
AHB
Switch
DMA
IP Bus
DMA_REQ[31:0], DMA_ACK,
I2S
UART
Figure 18-1. Block Diagram of the DMAC in i.MX21
The DMA has a FIFO for storing data read from the AHB Bus. This FIFO is 32 bits wide and 16 deep to
store up to 64 bytes. This FIFO is common for all channels and is used for the active channel.
18.1
DMA Request and Acknowledge
Initiation of a DMA cycle can be done through software control (setting CEN = 1 and REN =0 in the
channel control register) or by assertion of a DMA request (setting CEN = 1 and REN =1 in the channel
control register). A DMA cycle consists of a number of DMA bursts depending on the burst length and the
count register settings. Table 18-1 contains the DMA request map.
18.1.1
DMA Request
The DMA request is an active low signal asserted by the peripheral. The sampling of the signal is done
when REN and CEN bits in Channel Control register are set and there is no other ongoing DMA transfer
on the AHB bus. There is no configurable priority associated with any request. However, the 16 channels
have a fixed priority; channel 15 has the highest priority and channel 0 has the lowest priority. The priority
of any request depends on the channel number to which the request is mapped (through Request Source
Select register settings). The DMAC does not store the DMA request inputs, it processes on the highest
priority channel request out of the asserted channel requests (when no other transfer is taking place). A
peripheral must keep the request asserted until it is serviced by the DMAC. There are 32 input DMA
request signals available. One DMA request will initiate one DMA burst. Once a DMA burst has started,
the DMA request can be de-asserted by the peripheral. The peripheral should de-assert the DMA request
based on data read from or written into the peripheral. If the request is not de-asserted till the end of the
DMA burst, it can initiate another DMA burst.
18.1.2
External DMA Request and Grant
After assertion of External DMA Request the DMA burst will start when the corresponding DMA channel
becomes the current highest priority channel. The External DMA Request should be kept asserted until it
is serviced by the DMAC. One External request will initiate at least one DMA burst.
i.MX21 Reference Manual, Rev. 3
18-2
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
The output External Grant signal from the DMAC is an active-low signal. This signal will be asserted
during the time when a DMA burst is ongoing for an External DMA Request, when the following
conditions are true:
— The DMA channel for which the DMA burst is ongoing has request source as external DMA
Request (as per RSSR settings).
— REN and CEN bit of this channel are set
— External DMA Request is asserted
Once the grant is asserted the External DMA Request will not be sampled until completion of the DMA
burst. The priority of the external request will become low, for the next consecutive burst, if another DMA
request signal is asserted.
NOTE
Refer to Chapter 2, “Signal Descriptions and Pin Assignments,” for signal
multiplexing of the EXT_DMAREQ and EXT_DMAGRANT signals.
The waveforms are shown for the worst case—that is, smallest burst (1 byte read/write). Minimum and
maximum timings for the External request and External grant signal are present in the data sheet.
Figure 18-2 shows the minimum time for which the External Grant signal remains asserted if External
DMA request is de-asserted immediately after sensing grant signal active.
Ext_DMAReq
Ext_DMAGrant
tmin_assert
Figure 18-2. Assertion of DMA External Grant Signal
Figure 18-3 shows the safe max. time for which External DMA request can be kept asserted, after sensing
grant signal active such that a new burst is not initiated.
Ext_DMAReq
Ext_DMAGrant
tmax_req_assert
tmax_read
Data read from
External device
tmax_write
Data written to
External device
NOTE: Assuming in worst case the data is read/written from/to External device as per the above waveform.
Figure 18-3. Safe Maximum Timings for External Request De-Assertion
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-3
Direct Memory Access Controller (DMAC)
18.2
DMA Request Mapping
Table 18-1 shows the connection of the requests from various modules in the i.MX21 to the DMA Request
input of the DMA controller.
Table 18-1. DMA Request Mapping
DMA Request Number
Module Assigned
Channel Name
DMA_REQ[31]
CSI
CSI_RX_FIFO
DMA_REQ[30]
CSI
CSI_STAT_FIFO
DMA_REQ[29]
BMI
BMI_RX_FIFO
DMA_REQ[28]
BMI
BMI_TX_FIFO
DMA_REQ[27]
UART1
UART1_TX_FIFO
DMA_REQ[26]
UART1
UART1_RX_FIFO
DMA_REQ[25]
UART2
UART2_TX_FIFO
DMA_REQ[24]
UART2
UART2_RX_FIFO
DMA_REQ[23]
UART3
UART3_TX_FIFO
DMA_REQ[22]
UART3
UART3_RX_FIFO
DMA_REQ[21]
UART4
UART4_TX_FIFO
DMA_REQ[20]
UART4
UART4_RX_FIFO
DMA_REQ[19]
CSPI1
CSPI1_TX_FIFO
DMA_REQ[18]
CSPI1
CSPI1_RX_FIFO
DMA_REQ[17]
CSPI2
CSPI2_TX_FIFO
DMA_REQ[16]
CSPI2
CSPI2_RX_FIFO
DMA_REQ[15]
SSI1
SSI1_TX1_FIFO
DMA_REQ[14]
SSI1
SSI1_RX1_FIFO
DMA_REQ[13]
SSI1
SSI1_TX0_FIFO
DMA_REQ[12]
SSI1
SSI1_RX0_FIFO
DMA_REQ[11]
SSI2
SSI2_TX1_FIFO
DMA_REQ[10]
SSI2
SSI2_RX1_FIFO
DMA_REQ[9]
SSI2
SSI2_TX0_FIFO
DMA_REQ[8]
SSI2
SSI2_RX0_FIFO
DMA_REQ[7]
SDHC1
SDHC1
DMA_REQ[6]
SDHC2
SDHC2
DMA_REQ[5]
FIRI
FIRI_TX_FIFO
DMA_REQ[4]
FIRI
FIRI_RX_FIFO
DMA_REQ[3]
External DMA request
–
DMA_REQ[2]
CSPI3
CSPI3_TX_FIFO
DMA_REQ[1]
CSPI3
CSPI3_RX_FIFO
DMA_REQ[0]
Reserved
–
i.MX21 Reference Manual, Rev. 3
18-4
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
18.3
Programming Model
The DMA Controller module registers are 32-bit registers. The registers are divided into four groups
according to the register functions as follows.
• General registers for all functional blocks (see Section 18.3.1 on page -10)
• 2D memory registers to control the display width and the x and y of the window (see Section 18.3.2
on page -17)
• Channel registers to control and configure channels 0–15 (see Section 18.3.3 on page -21)
• Test Registers
The base address of DMA Controller for i.MX21 is 0x10001000. Table 18-2 summarizes the registers and
offset addresses.
Table 18-2. DMAC Register Summary
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DAM
0
DEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
DCR (0x000)
R
W
R
W
DISR (0x004)
R
DRST
0
0
W
R
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH 6 CH5 CH4 CH3 CH2 CH1 CH0
W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C
DIMR (0x008)
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH 6 CH5 CH4 CH3 CH2 CH1 CH0
W
DBTOSR (0x00C)
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH 6 CH5 CH4 CH3 CH2 CH1 CH0
W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C
DRTOSR (0x010)
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH 6 CH5 CH4 CH3 CH2 CH1 CH0
W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C
DSESR (0x014)
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH 6 CH5 CH4 CH3 CH2 CH1 CH0
W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C
DBOSR (0x018)
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH 6 CH5 CH4 CH3 CH2 CH1 CH0
W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-5
Direct Memory Access Controller (DMAC)
Table 18-2. DMAC Register Summary (continued)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
DBTOCR (0x01C)
R
W
R
EN
CNT [14: 0]
W
WSRA (0x040)
R
0
0
0
0
0
0
0
0
0
W
R
WS [15: 0]
W
XSRA (0x044)
R
0
0
0
0
0
0
0
0
0
W
R
XS [15: 0]
W
YSRA (0x048)
R
0
0
0
0
0
0
0
0
0
W
R
YS [15: 0]
W
WSRB (0x04C)
R
0
0
0
0
0
0
0
0
0
W
R
WS [15: 0]
W
XSRB (0x050)
R
0
0
0
0
0
0
0
0
0
W
R
XS [15: 0]
W
YSRB (0x054)
R
0
0
0
0
0
0
0
0
0
W
R
YS [15: 0]
W
SAR0 (0x080)
SAR1 (0x0C0)
SAR2 (0x100)
SAR3 (0x140)
SAR4 (0x180)
SAR5 (0x1C0)
SAR6 (0x200)
SAR7 (0x240)
SAR8 (0x280)
SAR9 (0x2C0)
SAR10 (0x300)
SAR11 (0x340)
SAR12 (0x380)
SAR13 (0x3C0)
SAR14 (0x400)
SAR15 (0x440)
R
SA [31: 16]
W
R
SA [15: 0]
W
i.MX21 Reference Manual, Rev. 3
18-6
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
Table 18-2. DMAC Register Summary (continued)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
CEN
Name
DAR0 (0x084)
DAR1 (0x0C4)
DAR2 (0x104)
DAR3 (0x144)
DAR4 (0x184)
DAR5 (0x1C4)
DAR6 (0x204)
DAR7 (0x244)
DAR8 (0x284)
DAR9 (0x2C4)
DAR10 (0x304)
DAR11 (0x344)
DAR12 (0x384)
DAR13 (0x3C4)
DAR14 (0x404)
DAR15 (0x444)
CNTR0 (0x088)
CNTR1 (0x0C8)
CNTR2 (0x108)
CNTR3 (0x148)
CNTR4 (0x188)
CNTR5(0x1C8)
CNTR6 (0x208)
CNTR7 (0x248)
CNTR8 (0x288)
CNTR9(0x2C8)
CNTR10 (0x308)
CNTR11 (0x348)
CNTR12 (0x388)
CNTR13 (0x3C8)
CNTR14 (0x408)
CNTR15 (0x448)
CCR0 (0x08C)
CCR1 (0x0CC)
CCR2 (0x10C)
CCR3 (0x14C)
CCR4 (0x18C)
CCR5(0x1CC)
CCR6(0x20C)
CCR7(0x24C)
CCR8(0x28C)
CCR9 (0x2CC)
CCR10 (0x30C)
CCR11 (0x34C)
CCR12 (0x38C)
CCR13 (0x3CC)
CCR14 (0x40C)
CCR15 (0x44C)
R
DA [31: 16]
W
R
DA [15: 0]
W
R
0
0
0
0
0
0
0
0
CNT [23: 16]
W
R
CNT [15: 0]
W
R
0
0
0
ACRP
T
0
0
0
0
0
0
0
0
0
0
0
W
R
DMOD
SMOD
MDIR MSEL
DSIZ
SSIZ
REN RPT
FRC
W
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-7
Direct Memory Access Controller (DMAC)
Table 18-2. DMAC Register Summary (continued)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
RSSR0 (0x090)
RSSR1 (0x0D0)
RSSR2 (0x110)
RSSR3 (0x150)
RSSR4 (0x190)
RSSR5 (0x1D0)
RSSR6 (0x210)
RSSR7 (0x250)
RSSR8 (0x290)
RSSR9 (0x2D0)
RSSR10 (0x310)
RSSR11 (0x350)
RSSR12 (0x390)
RSSR13 (0x3D0)
RSSR14 (0x410)
RSSR15 (0x450)
BLR0 (0x094)
BLR1 (0x0D4)
BLR2 (0x114)
BLR3 (0x154)
BLR4 (0x194)
BLR5 (0x1D4)
BLR6 (0x214)
BLR7 (0x254)
BLR8 (0x294)
BLR9 (0x2D4)
BLR10 (0x314)
BLR11 (0x354)
BLR12 (0x394)
BLR13 (0x3D4)
BLR14 (0x414)
BLR15 (0x454)
RTOR0 (0x098)
RTOR1 (0x0D8)
RTOR2 (0x118)
RTOR3 (0x158)
RTOR4 (0x198)
RTOR5 (0x1D8)
RTOR6 (0x218)
RTOR7 (0x258)
RTOR8 (0x298)
RTOR9 (0x2D8)
RTOR10 (0x318)
RTOR11 (0x358)
RTOR12 (0x398)
RTOR13 (0x3D8)
RTOR14 (0x418)
RTOR15 (0x458)
R
W
R
RSS [4: 0]
W
R
0
0
0
W
R
BL [5: 0]
W
R
0
0
0
0
W
R
EN
CLK PSC
CNT [12: 0]
W
i.MX21 Reference Manual, Rev. 3
18-8
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
Table 18-2. DMAC Register Summary (continued)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
BUCR0 (0x098)
BUCR1 (0x0D8)
BUCR2 (0x118)
BUCR3 (0x158)
BUCR4 (0x198)
BUCR5 (0x1D8)
BUCR6 (0x218)
BUCR7 (0x258)
BUCR8 (0x298)
BUCR9 (0x2D8)
BUCR10 (0x318)
BUCR11 (0x358)
BUCR12 (0x398)
BUCR13 (0x3D8)
BUCR14 (0x418)
BUCR15 (0x458)
CCNR0 (0x09C)
CCNR1 (0x0DC)
CCNR2 (0x11C)
CCNR3 (0x15C)
CCNR4 (0x19C)
CCNR5 (0x1DC)
CCNR6 (0x21C)
CCNR7 (0x25C)
CCNR8 (0x29C)
CCNR9 (0x2DC)
CCNR10 (0x31C)
CCNR11 (0x35C)
CCNR12 (0x39C)
CCNR13 (0x3DC)
CCNR14 (0x41C)
CCNR15 (0x45C)
R
W
R
BU_CNT [15: 0]
W
R
0
0
0
0
0
0
0
0
CCNR[23:16]
W
R
CCNR [15: 0]
W
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-9
Direct Memory Access Controller (DMAC)
18.3.1
General Registers
This section describes the function of the general registers.
18.3.1.1
DMA Control Register
The DMA Control Register (DCR) controls the input of the system clock and the resetting of the DMA
module.
DCR
DMA Control Register
Addr
0x10001000
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DAM DRST DEN
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
Slf Clr
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-3. DMA Control Register Description
Name
Description
Settings
Reserved
Bits 31–3
Reserved—These bits are reserved and should read 0.
DAM
Bit 2
DMA Access Mode—Specifies user or privileged access to be performed by DMA. 1 = User access
0 = Privileged access
DRST
Bit 1
DMA Soft Reset—Generates a 3-cycle reset pulse that resets the entire DMA
module, bringing the module to its reset condition. DRST always reads 0.
DEN
Bit 0
DMA Enable—Enables/Disables the system clock to the DMA module. However the 0 = DMA disable
bit is not used for clock gating in i.MX21 as the clock is controlled from CRM in
1 = DMA enable
i.MX21.
0 = No effect
1 = Generates a 3-cycle
reset pulse
i.MX21 Reference Manual, Rev. 3
18-10
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
18.3.1.2
DMA Interrupt Status Register
The DMA Interrupt Status Register (DISR) contains the interrupt status of each channel in the DMAC.
The status bit is set whenever the corresponding DMA channel data transfer is complete. When any bit in
the DMA Interrupt Status Register (DISR) is set and the corresponding bit in the interrupt mask register is
cleared, a dma_int is asserted to the interrupt controller (AITC). When an interrupt occurs, the interrupt
service routine must check the DISR to determine the interrupting channel. Clear each bit by writing a
value of 1 to it.
DISR
DMA Interrupt Status Register
Addr
0x10001004
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
RESET
0x0000
BIT
15
14
13
12
11
10
9
CH15 CH 14 CH 13 CH 12 CH 11 CH 10 CH9
TYPE
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-4. DMA Interrupt Status Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
CH15–CH0
Bits 15–0
Channel 15 to 0 Interrupt Status—Indicates the interrupt status for each DMA
channel.
Settings
0 = No interrupt
1 = Interrupt is pending
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-11
Direct Memory Access Controller (DMAC)
18.3.1.3
DMA Interrupt Mask Register
The DMA Interrupt Mask Register (DIMR) masks both normal interrupts and error interrupts generated
by the corresponding channel. There is one control bit for each channel. When an interrupt is masked, the
interrupt controller does not generate an interrupt request to the AITC, however the status of the interrupt
can be observed from the interrupt status register, burst time-out status register, request time-out status
register, or the transfer error status register. At reset, all the interrupts are masked and all the bits in this
register are set to 1.
DIMR
DMA Interrupt Mask Register
Addr
0x10001008
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
RESET
0x0000
BIT
15
14
13
12
11
10
9
CH15 CH 14 CH 13 CH 12 CH 11 CH 10 CH9
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
0xFFFF
Table 18-5. DMA Interrupt Mask Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
CH15–CH0
Bits 15–0
Channel 15 to 0—Controls the interrupts for each DMA channel.
Settings
0 = Enables interrupts
1 = Disables interrupts
i.MX21 Reference Manual, Rev. 3
18-12
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
18.3.1.4
DMA Burst Time-Out Status Register
A burst time-out is set when a DMA burst cannot be completed within the number of clock cycles specified
in the DMA Burst Time-Out Control Register (DBTOCR) of the channel. When any bit is set in this
register and the corresponding bit in the interrupt mask register is cleared, a DMA Error interrupt is
asserted to the interrupt controller (AITC). The DMA burst time-out status register (DBTOSR) indicates
the channel, if any, that is currently being serviced and whether a burst time-out was detected. Each bit is
cleared by writing 1 to it.
DBTOSR
DMA Burst Time-Out Status Register
Addr
0x1000100C
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
RESET
0x0000
BIT
15
14
13
12
11
10
9
CH15 CH 14 CH 13 CH 12 CH 11 CH 10 CH9
TYPE
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-6. DMA Burst Time-Out Status Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
CH15–CH0
Bits 15–0
Channel 15 to 0—Indicates the burst time-out status of each DMA channel.
Settings
0 = No burst time-out
1 = Burst time-out
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-13
Direct Memory Access Controller (DMAC)
18.3.1.5
DMA Request Time-Out Status Register
A DMA request time-out is set when there is no DMA burst started on the channel (when REN =1, either
due to no DMA Request or the DMA channel not acquiring the bus) within the pre-assigned number of
clock cycles specified in the Request Time-Out control register (RTOR) for the channel. When any bit is
set in this register and the corresponding bit in the interrupt mask register is cleared, a DMA Error Interrupt
is asserted to the AITC. The DMA Request Time-Out Status Register (DRTOSR) indicates the enabled
channel, if any, that detected a DMA request time-out. Clear each bit by writing 1 to it.
DRTOSR
DMA Request Time-Out Status Register
Addr
0x10001010
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
RESET
0x0000
BIT
15
14
13
12
11
10
9
CH15 CH 14 CH 13 CH 12 CH 11 CH 10 CH9
TYPE
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-7. DMA Request Time-Out Status Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
CH15–CH0
Bits 15–0
Channel 15 to 0—Indicates the request time-out status of each DMA
channel.
Settings
0 = No DMA request time-out
1 = DMA request time-out
i.MX21 Reference Manual, Rev. 3
18-14
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
18.3.1.6
DMA Transfer Error Status Register
A DMA transfer error is set when the DMA data transfer results in an error. When any bit is set in this
register and the corresponding bit in the interrupt mask register is cleared, a DMA Error Interrupt is
asserted to the AITC. The DMA Transfer Error Status Register (DSESR) indicates the channel, if any,
detected a transfer error during a DMA burst. Clear each bit by writing 1 to it.
DSESR
DMA Transfer Error Status Register
Addr
0x10001014
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
RESET
0x0000
BIT
15
14
13
12
11
10
9
CH15 CH 14 CH 13 CH 12 CH 11 CH 10 CH9
TYPE
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-8. DMA Transfer Error Status Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
CH15–CH0
Bits 15–0
Channel 15 to 0—Indicates the DMA transfer error status of each DMA
channel.
Settings
0 = No transfer error
1 = Transfer error
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-15
Direct Memory Access Controller (DMAC)
18.3.1.7
DMA Buffer Overflow Status Register
The DMA Buffer Overflow Status Register (DBOSR) indicates whether the internal FIFO buffer of the
DMA Controller overflowed during a data transfer. Before a channel can be enabled for DMA, the
corresponding bit in this register must be cleared. When any bit in this register is set and the corresponding
bit in the interrupt mask register is cleared, a DMA Error Interrupt is asserted to the AITC.
DBOSR
DMA Buffer Overflow Status Register
Addr
0x10001018
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
RESET
0x0000
BIT
15
14
13
12
11
10
9
CH15 CH 14 CH 13 CH 12 CH 11 CH 10 CH9
TYPE
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-9. DMA Buffer Overflow Status Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
CH15–CH0
Bits 15–0
Channel 15 to 0—Indicates the buffer overflow error status of each 0 = No buffer overflow occurred
DMA channel.
1 = Buffer overflow occurred
i.MX21 Reference Manual, Rev. 3
18-16
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
18.3.1.8
DMA Burst Time-Out Control Register
This register sets the time-out for a DMA burst (common for all DMA channels), so that the DMA
controller can release the AHB and IP buses in the event of an error. An internal counter starts counting
when a DMA burst starts, and resets to zero when the burst is completed. When the counter reaches the
count value set in the register, it asserts an interrupt and sets the corresponding error bit in the DMA Burst
Time-Out Status register. The system clock is used as the input clock to the counter.
DBTOCR
DMA Burst Time-Out Control Register
Addr
0x1000101C
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
EN
TYPE
CNT
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-10. DMA Burst Time-Out Control Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
EN
Bit 15
Enable—Enables/Disables the burst time-out.
CNT
Bits 14–0
Count—This count is the number of system clock cycles to be used for the time-out value
18.3.2
0 = Disables burst time-out
1 = Enables burst time-out
2D Memory Registers (A and B)
There are two sets of 2D memory registers that allow every channel to select any register set to define the
respective 2D memory size. Each data transfer performed by DMA is strictly as per Source and destination
sizes specified in the Channel Control Register (this is valid for ALL 4 modes—that is, Linear memory,2D
memory, FIFO mode.
In the case of a transfer to, or a transfer from 2D Memory, the Channel Count register value is ignored and
number of bytes transferred is equal to the size of the 2D Memory. The Size of the 2D Memory is computed
as follows.
Size (in number of bytes) = No of bytes per row (value in X register) * No. of rows (Value in Y Register)
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-17
Direct Memory Access Controller (DMAC)
At a time any number of channels can be programmed for 2D Memory (even all 16 Channels). 2D Memory
can be selected for a channel as source or destination or even for both source and destination. In the later
condition, only the selected set of the 2D Registers (selected as per the setting of the MSEL bit in the
Channel Control Register) is used for both source and destination.
The advantage of having 2 sets of registers, which are usable by all DMA channels, is that this allows the
developer to have two different window size settings for 2D memory. Each channel can be programmed
to use any one of the 2 settings.
In Figure 18-4, the shaded portion shows the data transfer zone in the 2D memory for X= 4, Y = 4, and W
(display size) = 6 with memory increment option and starting address 0x001.
W
Starting Address (SSA)
X
002
003
004
005 006
007
008
009
00A
00B 00C
00D
00E
00F
010
011 012
013
014
015
016
017 018
Y
001
Figure 18-4. 2D Memory Increment Diagram
In Figure 18-5, the shaded portion shows the data transfer zone in the 2D memory for X= 4, Y = 5, and W
= 6 with memory decrement option and starting address as 0x11C.
Starting
Address
W
X
117
118
119
11A
11B
110
111
112
113
114
115
10A
10B
10C
10D
10E
104
105
106
107
108
0FE
0FF
100
101
102
11C
10F
Y
116
109
103
Figure 18-5. 2D Memory Decrement Diagram
i.MX21 Reference Manual, Rev. 3
18-18
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
18.3.2.1
W-Size Registers
The W-Size registers (WSRA and WSRB) define the number of bytes that make up the width of the
display. This allows the DMA controller to calculate the next starting address of another row by adding
the source/destination address to the contents of the W-Size register.
WSRA
WSRB
Addr
0x10001040
0x1000104C
W-Size Register A
W-Size Register B
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WS
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-11. W-Size Registers Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
WS
Bits 15–0
W-Size—Contains the number of bytes that make up the display width.
W and X must follow the relation: W ≥ X
W and Access Size must follow the relation: W ≥ access size.
Wsize needs to be a multiple of Source or Destination Access size whichever is a 2D memory.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-19
Direct Memory Access Controller (DMAC)
18.3.2.2
X-Size Registers
The X-Size registers (XSRA and XSRB) contain the number of bytes per row of the window. The value
of this register is used by the DMA controller to determine when to jump to the next row.
XSRA
XSRB
Addr
0x10001044
0x10001050
X-Size Register A
X-Size Register B
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
XS
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-12. X-Size Registers Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
XS
Bits 15–0
X-Size—Contains the number of bytes per row that define the X-Size of the 2D memory.
The value in the X Register should follow the following 2 rules:
• X ≥ Burst Length (BL)
• X/ BL = Whole number.
i.MX21 Reference Manual, Rev. 3
18-20
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
18.3.2.3
Y-Size Registers
The Y-Size registers (YSRA and YSRB) contain the number of rows in the 2D memory window. This
setting is used by the DMA controller to calculate the total size of the transfer.
YSRA
YSRB
Addr
0x10001048
0x10001054
Y-Size Register A
Y-Size Register B
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
YS
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-13. Y-Size Registers Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
YS
Bits 15–0
Y-Size—Contains the number of rows that make up the 2D memory window.
18.3.3
Channel Registers
Channels 0 to 15 support linear memory, 2D memory, FIFO transfer.
The DMA request (dma_req [31:0]) signals do not have any configurable priority. The only priority
available is the priority that is defined for each channel: channel 15 has the highest priority and channel 0
has the lowest priority. The channel priority is used only when more than one request occurs at the same
time. Otherwise, channels are serviced on a first come, first serve basis.
Each channel generates a normal interrupt to the interrupt handler when the data count reaches the selected
value. Each channel generates an error interrupt to the interrupt handler when any of the following
conditions exist:
• A DMA request time-out is true
• A DMA burst time-out is true during a burst cycle
• The internal buffer overflows during a burst cycle
• A transfer error acknowledge is asserted during a burst cycle
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-21
Direct Memory Access Controller (DMAC)
18.3.3.1
Channel Source Address Registers
Each of the channel source address registers contain the source address for the DMA cycle. The
implementation must ensure that the source address register’s value is stored internally before use to allow
the software to modify the register value for DMA chaining (see section 18.4 "DMA Chaining", on page
35). The value should be stored when the CEN bit is set or at the end of the transfer when the RPT bit is
found set (before initiating the new transfer). If the memory direction bit (MDIR) in the channel control
register (CCR) is clear (indicating a memory address increment), then the channel source address register
contains the starting address of the memory block. If MDIR is set (indicating a memory address
decrement), then the channel source address register contains the ending address of the memory block.
SAR0
SAR1
SAR2
SAR3
SAR4
SAR5
SAR6
SAR7
SAR8
SAR9
SAR10
SAR11
SAR12
SAR13
SAR14
SAR15
Channel 0 Source Address Register
Channel 1 Source Address Register
Channel 2 Source Address Register
Channel 3 Source Address Register
Channel 4 Source Address Register
Channel 5 Source Address Register
Channel 6 Source Address Register
Channel 7 Source Address Register
Channel 8 Source Address Register
Channel 9 Source Address Register
Channel 10 Source Address Register
Channel 11 Source Address Register
Channel 12 Source Address Register
Channel 13 Source Address Register
Channel 14 Source Address Register
Channel 15 Source Address Register
BIT
31
30
29
28
27
26
25
24
TYPE
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0x10001080
0x100010C0
0x10001100
0x10001140
0x10001180
0x100011C0
0x10001200
0x10001240
0x10001280
0x100012C0
0x10001300
0x10001340
0x10001380
0x100013C0
0x10001400
0x10001440
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
SA
RESET
BIT
0x0000
15
14
13
12
11
10
9
8
SA
TYPE
RESET
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0x0000
Table 18-14. Channel Source Address Register Description
Name
SA
Bits 31–0
Description
Source Address—Contains the source address from where data is read during a DMA transfer. DMA will not
perform misaligned accesses. That is to say, for 32-bit transfers, the lower two bits of this address are ignored. 8-bit
accesses begin from the address in this register. Software must take care if the system does not support non-word
aligned accesses in this case.
i.MX21 Reference Manual, Rev. 3
18-22
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
18.3.3.2
Destination Address Registers
Each of the destination address registers (DARx) contain the destination address for a DMA cycle. The
implementation needs to ensure that the Destination Address Register’s value is stored internally before
use to allow the software to modify the register value for DMA Chaining (see section 18.4 "DMA
Chaining", on page 35). The value should be stored when the CEN bit is set or at the end of the transfer
when the RPT bit is found set (before initiating the new transfer). If the memory direction bit (MDIR) in
the channel control register (CCR) is clear (indicating a memory address increment), then the destination
address register contains the starting address of the memory block. If MDIR is set (indicating a memory
address decrement), then the destination address register contains the ending address of the memory block.
DAR0
DAR1
DAR2
DAR3
DAR4
DAR5
DAR6
DAR7
DAR8
DAR9
DAR10
DAR11
DAR12
DAR13
DAR14
DAR15
BIT
Channel 0 Destination Address Register
Channel 1 Destination Address Register
Channel 2 Destination Address Register
Channel 3 Destination Address Register
Channel 4 Destination Address Register
Channel 5 Destination Address Register
Channel 6 Destination Address Register
Channel 7 Destination Address Register
Channel 8 Destination Address Register
Channel 9 Destination Address Register
Channel 10 Destination Address Register
Channel 11 Destination Address Register
Channel 12 Destination Address Register
Channel 13 Destination Address Register
Channel 14 Destination Address Register
Channel 15 Destination Address Register
27
26
25
24
23
22
DA
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0x0000
31
30
29
28
rw
0
rw
0
rw
0
rw
0
BIT
15
14
13
12
11
10
9
TYPE
rw
0
rw
0
rw
0
rw
0
rw
0
rw
0
rw
0
TYPE
RESET
RESET
8
7
DA
rw
rw
0
0
0x0000
Addr
0x10001084
0x100010C4
0x10001104
0x10001144
0x10001184
0x100011C4
0x10001204
0x10001244
0x10001284
0x100012C4
0x10001304
0x10001344
0x10001384
0x100013C4
0x10001404
0x10001444
19
18
21
20
17
16
rw
0
rw
0
rw
0
rw
0
rw
0
rw
0
6
5
4
3
2
1
0
rw
0
rw
0
rw
0
rw
0
rw
0
rw
0
rw
0
Table 18-15. Channel Destination Address Registers Description
Name
DA
Bits 31–0
Description
Destination Address—Contains the destination address to which data is written to during a DMA transfer. The
DMAC will not perform misaligned accesses. That is, for a 32-bit transfers the lower two bits of this address are
ignored. 8-bit accesses begin from the address in this register. Software must take care if the system does not
support non-word aligned accesses in this case.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-23
Direct Memory Access Controller (DMAC)
18.3.3.3
Channel Count Registers
The DEN bit in the DCR should be set to enable write to this register.
The implementation needs to ensure that the Count register’s value is stored internally before use to allow
the software to modify the register value for DMA Chaining (see section 18.4 "DMA Chaining", on page
35). The value should be stored in an Internal Count Register when the CEN bit is set or at the end of the
transfer when the RPT bit is found set (before initiating the new transfer).
Each of the channel count registers (CNTRx) contain the number of bytes of data to be transferred. There
is an internal counter that counts up (number of bytes—4 for word, 2 for halfword and 1 for byte) for every
DMA transfer. The internal counter is compared with the Internal Count Register after every transfer.
When the counter value matches with the register value, the channel is disabled until the CEN bit is cleared
and set again, or the RPT bit in the corresponding channel control register is set to 1. The internal counter
is reset to 0 when the channel is enabled again.
The length of the last DMA burst can be shorter than the regular burst length specified in the burst length
register. However, when data is transferred out from an I/O FIFO and the last burst is less than BL, the I/O
device must generate a DMA request for the last transfer. When data is transferred to an I/O FIFO and the
last burst is less than BL, only the remaining number of data is transferred.
i.MX21 Reference Manual, Rev. 3
18-24
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
CNTR0
CNTR1
CNTR2
CNTR3
CNTR4
CNTR5
CNTR6
CNTR7
CNTR8
CNTR9
CNTR10
CNTR11
CNTR12
CNTR13
CNTR14
CNTR15
BIT
Addr
0x10001088
0x100010C8
0x10001108
0x10001148
0x10001188
0x100011C8
0x10001208
0x10001248
0x10001288
0x100012C8
0x10001308
0x10001348
0x10001388
0x100013C8
0x10001408
0x10001448
Channel 0 Count Register
Channel 1 Count Register
Channel 2 Count Register
Channel 3 Count Register
Channel 4 Count Register
Channel 5 Count Register
Channel 6 Count Register
Channel 7 Count Register
Channel 8 Count Register
Channel 9 Count Register
Channel 10 Count Register
Channel 11 Count Register
Channel 12 Count Register
Channel 13 Count Register
Channel 14 Count Register
Channel 15 Count Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CNT
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
CNT
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-16. Channel Count Registers Description
Name
Description
Reserved
Bits 31–24
Reserved—These bits are reserved and should read 0.
CNT
Bits 23–0
Count—Contains the number of bytes of data to be transferred during a DMA cycle.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-25
Direct Memory Access Controller (DMAC)
18.3.3.4
Channel Control Registers
Each of the channel control registers (CCRx) controls and displays the status of a DMA channel operation.
The DMA controller has the capability to perform burst transfers of byte and half word data types while
the SDRAM controller and EIM support is restricted to burst transfers of word (32-bit) data types.
Therefore, when using the DMA in conjunction with the SDRAM controller and EIM, ensure that all burst
transfers to/from the SDRAM controller and EIM are of word data types. This is configured in the DMA
Channel Control Register. When choosing SDRAM memory as the source or destination address, set the
SDRAMC and EIM as a 32-bit port.
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
CCR7
CCR8
CCR9
CCR10
CCR11
CCR12
CCR13
CCR14
CCR15
Addr
0x1000108C
0x100010CC
0x1000110C
0x1000114C
0x1000118C
0x100011CC
0x1000120C
0x1000124C
0x1000128C
0x100012CC
0x1000130C
0x1000134C
0x1000138C
0x100013CC
0x1000140C
0x1000144C
Channel 0 Control Register
Channel 1 Control Register
Channel 2 Control Register
Channel 3 Control Register
Channel 4 Control Register
Channel 5 Control Register
Channel 6 Control Register
Channel 7 Control Register
Channel 8 Control Register
Channel 9 Control Register
Channel 10 Control Register
Channel 11 Control Register
Channel 12 Control Register
Channel 13 Control Register
Channel 14 Control Register
Channel 15 Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESE
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
7
6
5
4
3
2
1
0
0x0000
14
13
ACRPT
12
11
DMOD
10
SMOD
9
8
MDIR
MSE
L
DSIZ
SSIZ
RE
N
RP
FRC CEN
T
TYPE
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESE
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 18-17. Channel Control Registers Description
Name
Description
Settings
Reserved
Bits 31–15
Reserved—These bits are reserved and should read 0.
ACRPT
Bits 14
Auto Clear RPT—This bit is to be sampled at the end of the transfer along 0 = Do not modify RPT
with the RPT bit. When this bit and RPT are set, a new transfer is initiated 1 = Reset RPT at end of current
and RPT is reset before issuing any interrupts.
transfer.
i.MX21 Reference Manual, Rev. 3
18-26
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
Table 18-17. Channel Control Registers Description (continued)
Name
Description
Settings
DMOD
Bits 13–12
Destination Mode—Selects the destination transfer mode.
00 = Linear memory
01 = 2D memory
10 = FIFO
11 = Reserved
SMOD
Bits 11–10
Source Mode—Selects the source transfer mode.
00 = Linear memory
01 = 2D memory
10 = FIFO
11 = Reserved
MDIR
Bit 9
Memory Direction—Selects the memory address direction.
0 = Memory address increment
Note: When address increment is chosen, the data transfer starts from the 1 = Memory address decrement
values in the source and destination address registers. When address
decrement is chosen, the data transfer will be done till the addresses
mentioned in source and destination address register—that is, no data
read or write will be done at the address mentioned in source and
destination address registers.
MSEL
Bit 8
Memory Select—Selects the 2D memory register set when either source 0 = 2D memory register set A
and/or destination is programmed to 2D memory mode.
selected
1 = 2D memory register set B
selected
DSIZ
Bits 7–6
Destination Size—Selects the destination size of a data transfer.
1. If the number of bytes to be written is less than the DSIZ setting, then
only that many bytes will be valid in the DMA write cycle to the AHB.
However all DMA write cycles to the destination will be of DSIZ size.
2. DMA always writes data as per DSIZ in all modes —that is, Linear
memory, 2D memory and FIFO mode.
00 = 32-bit destination port
01 = 8-bit destination port
10 = 16-bit destination port
11 = Reserved
SSIZ
Bits 5–4
Source Size—Selects the source size of data transfer.
1. If the number of bytes to be read is less than the SSIZ setting, then
only that many bytes will be used by the DMA. However, all DMA
read cycles to the source will be of “SSIZ” size.
2. DMA always reads data as per SSIZ in all modes—that is, Linear
memory, 2D memory and FIFO mode.
00 = 32-bit source port
01 = 8-bit source port
10 = 16-bit source port
11 = Reserved
REN
Bit 3
Request Enable—Enables/Disables the DMA request signal. When REN 0 = Disables the DMA request signal
(when the peripheral asserts a
is set, the DMA burst is initiated by the dma_req signal from the I/O FIFO.
When REN is cleared, DMA transfer is initiated by CEN.
DMA request, no DMA transfer
is triggered); DMA transfer is
initiated by CEN only
1 = Enables the DMA request signal
(when the peripheral asserts a
DMA request, a DMA transfer is
triggered)
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-27
Direct Memory Access Controller (DMAC)
Table 18-17. Channel Control Registers Description (continued)
Name
Description
Settings
RPT
Bit 2
Repeat—This is a status/control bit. The software has a priority and can 0 = Disables repeat function
write to this bit at any time. This bit Enables/Disables the data transfer
1 = Enables repeat function
repeat function. When enabled and when the counter reaches the value
set in Internal Count Register:
a. The Source addr, Destination addr and Count Register values are
stored (reloaded) for the next DMA Burst.
b. If the ACRPT bit is set, RPT bit is cleared.
c. The next DMA cycle is enabled.
After this an interrupt is asserted, if the corresponding channel bit in the
Interrupt Mask Register is cleared. Data transfer is carried out
continuously until the channel is disabled or it completes the last DMA
burst after RPT is cleared.
The status information in this bit is that it gets cleared when ACRPT is set
as described above.
Note: Implementation must ensure that the RPT bit is sampled only at the
time the counter reaches the value in the Internal Count Register
before asserting the interrupt. The RPT bit should be allowed to be
modified at all other times by the software (for example in the
interrupt subroutine).
FRC
Bit 1
Force a DMA Cycle—Forces a DMA burst to occur when the DMA cycle 0 = No effect
is software enabled or DMA Request Enabled. When FRC bit is set, it will 1 = Force DMA cycle
remain set till a DMA burst for this channel starts as per channel priority,
and will get cleared after the DMA burst for the channel starts.
When set, software will read this bit as’1’ till it gets cleared automatically
or cleared by software.
CEN
Bit 0
DMA Channel Enable—Enables/Disables the DMA channel.
0 = Disables the DMA channel
Note:
1 = Enables the DMA channel
1. To re-program a particular channel after completion of a DMA cycle refer
Section 24.11 Application Note.
2. Disabling CEN during an ongoing burst on the AHB will stop the burst in
between the transfer
i.MX21 Reference Manual, Rev. 3
18-28
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
18.3.3.5
Channel Request Source Select Registers
Each of the 32-bit channel request source select registers (RSSRx) selects one of the 32 DMA request
signals (DMA_REQ [31:0]) to initiate a DMA transfer for the corresponding channel.
RSSR0
RSSR1
RSSR2
RSSR3
RSSR4
RSSR5
RSSR6
RSSR7
RSSR8
RSSR9
RSSR10
RSSR11
RSSR12
RSSR13
RSSR14
RSSR15
Channel 0 Request Source Select Register
Channel 1 Request Source Select Register
Channel 2 Request Source Select Register
Channel 3 Request Source Select Register
Channel 4 Request Source Select Register
Channel 5 Request Source Select Register
Channel 6 Request Source Select Register
Channel 7 Request Source Select Register
Channel 8 Request Source Select Register
Channel 9 Request Source Select Register
Channel 10 Request Source Select Register
Channel 11 Request Source Select Register
Channel 12 Request Source Select Register
Channel 13 Request Source Select Register
Channel 14 Request Source Select Register
Channel 15 Request Source Select Register
0x10001090
0x100010D0
0x10001110
0x10001150
0x10001190
0x100011D0
0x10001210
0x10001250
0x10001290
0x100012D0
0x10001310
0x10001350
0x10001390
0x100013D0
0x10001410
0x10001450
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
RSS
TYPE
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-18. Channel Request Source Select Registers Description
Name
Description
Reserved
Bits 31–5
Reserved—These bits are reserved and should read 0.
RSS
Bits 4–0
Request Source Select—Selects one of the 32 dma_req signals that
initiates a DMA transfer cycle for the channel.
Settings
00000 = select dma_req[0]
00001 = select dma_req [1]
...
11111 = select dma_req [31]
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-29
Direct Memory Access Controller (DMAC)
18.3.3.6
Channel Burst Length Registers
The Channel Burst Length registers (BLRx) control the burst length of a DMA cycle. For a FIFO channel
setting, the burst length is normally assigned according to the FIFO size of the selected I/O device, or by
the FIFO level at which its dma_req signal is asserted.
For example, when the UART RxD FIFO is 12 ¥ 8 and it asserts dma_req when it receives more than 8
bytes of data, BL is 8. When the memory port size also is 8-bit, the DMA burst is 8-byte reads followed
by 8-byte writes.
When the memory port access size is smaller than the I/O port access size, the burst length of the byte
writes is doubled. For example, the I/O port is 32-bit, the memory port is 16-bit, and the burst length is set
to 32. In this configuration, the DMA performs 8 word burst reads and 16 halfword burst writes for I/O to
memory transfer.
When the burst length is not programmed as a multiple of access sizes of source and destination, please
see section 21.9 for the behavior of DMA.
BLR0
BLR1
BLR2
BLR3
BLR4
BLR5
BLR6
BLR7
BLR8
BLR9
BLR10
BLR11
BLR12
BLR13
BLR14
BLR15
Addr
0x10001094
0x100010D4
0x10001114
0x10001154
0x10001194
0x100011D4
0x10001214
0x10001254
0x10001294
0x100012D4
0x10001314
0x10001354
0x10001394
0x100013D4
0x10001414
0x10001454
Channel 0 Burst Length Register
Channel 1 Burst Length Register
Channel 2 Burst Length Register
Channel 3 Burst Length Register
Channel 4 Burst Length Register
Channel 5 Burst Length Register
Channel 6 Burst Length Register
Channel 7 Burst Length Register
Channel 8 Burst Length Register
Channel 9 Burst Length Register
Channel 10 Burst Length Register
Channel 11 Burst Length Register
Channel 12 Burst Length Register
Channel 13 Burst Length Register
Channel 14 Burst Length Register
Channel 15 Burst Length Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
BL
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
i.MX21 Reference Manual, Rev. 3
18-30
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
Table 18-19. Channel Burst Length Registers Description
Name
Description
Settings
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
BL
Bits 5–0
Burst Length—Contains the number of data bytes that are 000000 = 64 bytes read follow 64 bytes write
transferred in a DMA burst.
000001 = 1byte read follow 1 byte write
000010 = 2 bytes read follow 2 bytes write
....
111111 = 63 bytes read follow 63 bytes write
18.3.3.7
Channel Request Time-Out Registers
The Channel Request Time-Out registers (RTOx) set the time-out for DMA Request from the selected
request source of the channel, which detects any discontinuity of data transfer. The request time-out takes
effect only when the corresponding request enable (REN) bit in the channel control register (CCR) is set.
An Internal Request Time-out Counter starts counting when a DMA channel is enabled and a burst on that
channel ends. The Internal Request Time-out Counter is reset to zero when another burst for that channel
starts. When the counter reaches the count value set in this register, it asserts an interrupt (if it not masked)
and sets its error bit in the DMA request time-out status register (RTOSR). The input clock of the counter
is selectable from either the system clock (HCLK) or input crystal (CLK32K).
The Internal Request Time-out Counter will not generate an error status (or count) for the first burst of a
DMA cycle. It can be programmed to count (and can generate an error status as described above) for all
other bursts in the DMA cycle.
NOTE
This register shares the same address as the bus utilization control register.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-31
Direct Memory Access Controller (DMAC)
.
RTOR0
RTOR1
RTOR2
RTOR3
RTOR4
RTOR5
RTOR6
RTOR7
RTOR8
RTOR9
RTOR10
RTOR 11
RTOR 12
RTOR 13
RTOR 14
RTOR 15
Channel 0 Request Time-Out Register
Channel 1 Request Time-Out Register
Channel 2 Request Time-Out Register
Channel 3 Request Time-Out Register
Channel 4 Request Time-Out Register
Channel 5 Request Time-Out Register
Channel 6 Request Time-Out Register
Channel 7 Request Time-Out Register
Channel 8 Request Time-Out Register
Channel 9 Request Time-Out Register
Channel 10 Request Time-Out Register
Channel 11 Request Time Out Register
Channel 12 Request Time Out Register
Channel 13 Request Time Out Register
Channel 14 Request Time Out Register
Channel 15 Request Time Out Register
0x10001098
0x100010D8
0x10001118
0x10001158
0x10001198
0x100011D8
0x10001218
0x10001258
0x10001298
0x100012D8
0x10001318
0x10001358
0x10001398
0x100013D8
0x10001418
0x10001458
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
EN
CLK
PSC
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNT
RESET
0x0000
Table 18-20. Channel Request Time-Out Registers Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
EN
Bit 15
Enable—Enables/Disables the DMA request time-out.
0 = Disables DMA request time-out
1 = Enables DMA request time-out
CLK
Bit 14
Clock Source—Selects the counter of input clock source.
0 = HCLK
1 = 32.768 kHz
PSC
Bit 13
Prescaler Count—Sets the prescaler of the input clock.
0 = Divide by 1
1 = Divide by 256
CNT
Bits 12–0
Request Time-Out Count—Contains the time-out count down value for the internal counter in number of clocks.
This value remains unchanged through out the DMA cycle.
i.MX21 Reference Manual, Rev. 3
18-32
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
18.3.3.8
Channel Bus Utilization Control Registers
The Bus Utilization Control register (BUCRx) controls the bus utilization of an enabled channel when the
request enable (REN) bit in channel control register (CCR) is cleared. The channel does not request a
DMA transfer until the internal bus_untilization_counter reaches the count value set in this register except
for the very first burst. This counter is cleared when the channel burst is started. When this count value is
set to zero, the DMA carries on burst transfers one after another until it reaches the value set in Channel
Count register. In this case, the user must be careful not to violate the maximum bus request latency of
other devices.
NOTE
This register shares the same address of request time-out register.
BUCR0
BUCR1
BUCR2
BUCR3
BUCR4
BUCR5
BUCR6
BUCR7
BUCR8
BUCR9
BUCR10
BUCR11
BUCR12
BUCR13
BUCR14
BUCR15
Channel 0 Bus Utilization Control Register
Channel 1 Bus Utilization Control Register
Channel 2 Bus Utilization Control Register
Channel 3 Bus Utilization Control Register
Channel 4 Bus Utilization Control Register
Channel 5 Bus Utilization Control Register
Channel 6 Bus Utilization Control Register
Channel 7 Bus Utilization Control Register
Channel 8 Bus Utilization Control Register
Channel 9 Bus Utilization Control Register
Channel 10 Bus Utilization Control Register
Channel 11 Bus Utilization Control Register
Channel 12 Bus Utilization Control Register
Channel 13 Bus Utilization Control Register
Channel 14 Bus Utilization Control Register
Channel 15 Bus Utilization Control Register
0x10001098
0x100010D8
0x10001118
0x10001158
0x10001198
0x100011D8
0x10001218
0x10001258
0x10001298
0x100012D8
0x10001318
0x10001358
0x10001398
0x100013D8
0x10001418
0x10001458
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
BIT
0x0000
15
14
13
12
11
10
9
8
BU_CNT
TYPE
RESET
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 18-21. Channel Bus Utilization Control Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
BU_CNT
Bits 15–0
Bus Utilization Clock Count—Sets the number of system clocks that must occur before the channel starts the
next burst.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
18-33
Direct Memory Access Controller (DMAC)
18.3.3.9
Channel Counter Registers
The Channel Counter Registers indicates the number of bytes transferred for the channel. It is reset to zero
after channel is enabled and keeps incrementing for each transfer during the DMA burst. This counter will
retain its value after the channel is disabled, till it is enabled again. If the RPT bit is found set at the end of
the last burst of the DMA cycle, this counter retains its value and will be reset to zero only at the start of
the another DMA burst—that is, the first burst of the new DMA cycle. If a DMA channel is disabled before
the completion of the DMA cycle, this counter will retain the value of the number of data transferred in
that DMA cycle. When the peripheral responds with a error response during a DMA data transfer, the
CCNR value will not be increment for that AHB cycle as no data was transferred in that cycle.
CCNR0
CCNR1
CCNR2
CCNR3
CCNR4
CCNR5
CCNR6
CCNR7
CCNR8
CCNR9
CCNR10
CCNR11
CCNR12
CCNR13
CCNR14
CCNR15
BIT
Addr
0x1000109C
0x100010DC
0x1000111C
0x1000115C
0x1000119C
0x100011DC
0x1000121C
0x1000125C
0x1000129C
0x100012DC
0x1000131C
0x1000135C
0x1000139C
0x100013DC
0x1000141C
0x1000145C
Channel 0 Channel Counter Register
Channel 1 Channel Counter Register
Channel 2 Channel Counter Register
Channel 3 Channel Counter Register
Channel 4 Channel Counter Register
Channel 5 Channel Counter Register
Channel 6 Channel Counter Register
Channel 7 Channel Counter Register
Channel 8 Channel Counter Register
Channel 9 Channel Counter Register
Channel 10 Channel Counter Register
Channel 11 Channel Counter Register
Channel 12 Channel Counter Register
Channel 13 Channel Counter Register
Channel 14 Channel Counter Register
Channel 15 Channel Counter Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CCNR[23:16]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
CCNR[15:0]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-22. Channel Counter Register Description
Name
Description
Reserved
Bits 31–24
Reserved—These bits are reserved and should read 0.
CCNR
Bits 23–0
Channel Counter—Indicates the number of bytes transferred for the channel.
i.MX21 Reference Manual, Rev. 3
18-34
Freescale Semiconductor
Direct Memory Access Controller (DMAC)
18.4
DMA Chaining
This refers to the use of the same DMA Channel to automatically transfer a second data buffer (of maybe
a different length) between another 2 sets of Source and Destination addresses, with an increase in the
allowable value of the interrupt service time. This is possible because the ISR execution (that is, setup for
next transfer) can go in parallel to the next buffer transfer from the DMA (when RPT bit is set).
To achieve DMA Chaining:
• Source Address Register for each Channel are double buffered internally.
• Destination Address Register for each Channel are double buffered internally.
• Channel Count Register for each Channel are double buffered internally.
With this the Host can update the values in these 3 register during an ongoing DMA Transfer for the same
channel in preparation for the next DMA transfer. With the use of RPT and ACRPT bits the second transfer
can occur for different source, destination addresses and different amount of data.
As an example, consider a Data Transfer of 14 K bytes from memory to a FIFO using 4K buffers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The driver writes 4K of data into buffer 1, sets the source register to buffer 1 and count to 4K, sets
ACRPT, then enables the transfer. The DMA hardware will immediately latch the registers and
start the transfer.
The driver immediately writes 4K of data into buffer 2, sets the same source register to buffer 2,
count to 4K, and sets the RPT bit.
Transfer of buffer 1 completes, the DMA hardware samples the RPT bit, finds it set, latches the
register (now set for buffer 2), clears the RPT bit because ACRPT is set, and starts the next transfer.
It then generates the 1st interrupt.
Driver ISR writes 4K of new data to buffer 1, sets the source register to buffer 1 and count to 4K,
and sets the RPT bit again.
Transfer of buffer 2 completes, the DMA hardware samples the RPT bit, finds it set, latches the
registers (now set for buffer 1), clears the RPT bit because ACRPT is still set, and starts the next
transfer.
It then generates the 2nd interrupt.
Driver ISR writes 2K of new data to buffer 2, sets the source register to buffer 2 and count to 2K,
and sets the RPT bit again.
Transfer of buffer 1 completes, the DMA hardware samples the RPT bit, finds it set, latches the
register (now set for buffer 2), clears the RPT bit because ACRPT is still set, and starts the next
transfer.
It then generates the 3rd interrupt.
Driver ISR has no more data to send so does nothing.
Transfer of buffer 2 completes, the DMA hardware samples the RPT bit, finds it clear so it stops
the transfer.
It then generates the 4th interrupt.
Driver ISR disables the DMA and the transfer is complete.
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Direct Memory Access Controller (DMAC)
18.5
Special Cases of Burst Length and Access Size Settings
DMA burst length should normally be programmed as a multiple of the source and destination access sizes.
The following sub-sections discuss the behavior that occurs when the burst length is not a multiple of
access size.
18.5.1
Memory Increment
The following are the possible adverse effects:
1. Unknown data can be written at some locations, however, there is no data loss.
2. Number of bytes transferred can be more than the count value set.
These effects are explained in the examples below:
Example 1: Source is Linear memory with access size of 1 byte. Destination is linear memory with access
size of 2 bytes. Burst Length is programmed as 3 bytes with memory increment. Source Addr Register:
0x0000_1000. Destination Addr Reg: 0x0000_2000
For the first burst DMA would read 3 bytes from addresses: 1000, 1001, and 1002. During the write cycle
of the 1st burst DMA would write 2 bytes each at addresses 2000 and 2002. One extra memory location
(0x2003) is written with unknown data from the DMA internal FIFO (8’h00 after hardware reset).
Example 2: Source is Linear Memory with access size of 2 bytes. Destination is linear memory with access
size of 2 bytes. Burst Length is programmed as 3 bytes with memory increment. Source Addr Register:
0x0000_1000. Destination Addr Reg: 0x0000_2000
For the first burst, DMA would read 2 bytes each from addresses 1000 and 1002. During the write cycle
of the 1st burst DMA would write 2 bytes each at addresses 2000 and 2002. One extra data byte is
transferred per burst. When programmed with a count of say 9 bytes, DMA would perform data transfer
of 12 bytes.
18.5.2
Memory Decrement
Possible Adverse Effects:
1. Unknown data can be written at some locations. In certain cases there can be data loss.
These effects are explained in the examples below:
For Example: Source is linear memory with access size of 1 byte. Destination is linear memory with access
size of 2 bytes. Burst Length is programmed as 3 bytes with memory decrement. Source Addr Register:
0x0000_1000. Destination Addr Reg: 0x0000_2000
For the first burst DMA would read 3 bytes from addresses: 0FFD, 0FFE, and 0FFF. During write cycle
of the 1st burst, DMA would write 2 bytes each at addresses 1FFC and 1FFE. An extra byte is written at
the address 1FFF with unknown data from the DMA internal FIFO (8’h00 after hardware reset).
For the second burst DMA would read 3 bytes from the addresses: 0FFA, 0FFB, and 0FFC. During write
cycle of the 2nd burst, DMA would write 2 bytes each at addresses 1FFA and 1FFC. In this case data
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Direct Memory Access Controller (DMAC)
written at 1FFC and 1FFD in the first burst have been overwritten. Data written at 1FFD will be unknown
data from the DMA internal FIFO (8’h00 after hardware reset).
Please note the following:
1. In the case of 2D Memory writing extra bytes would mean writing beyond the limits of X-Size
programmed in a row.
2. Similarly for linear memory, this can lead data overflowing the allocated buffer for DMA.
18.6
Special Cases When CCNR and CNTR Values Differ
There are two combinations of events that can cause the values of the CCNR and the CNTR to differ. This
situations are discussed in greater detail in the following sections.
18.6.1
CNTR Not A Multiple of Destination Access Size
If Counter (CNTR) register value is not a multiple of destination access size then the CCNR value will not
match the value programmed in CNTR after completion of the DMA cycle for the channel. Table 18-23
illustrates the values of CCNR with different combinations of source and destination access sizes when
CNTR = 5 bytes. This table holds good when BL = 3 bytes or BL = 4 bytes.
Table 18-23. CNNR Value Combinations
No. of Bytes Read by DMA
Source Size
(Bytes)
Destination
Size (Bytes)
2
18.6.2
No. of Bytes Written by DMA
CCNR (Bytes)
Memory
Increment
Memory
Decrement
Memory
Increment
Memory
Decrement
2
6
6
6
6
6
4
4
8
8
8
8
8
2
4
6
6
8
8
8
4
2
8
8
6
6
6
1
2
5
5
6
6
6
1
4
5
5
8
8
8
BL is Not a Multiple of Destination Access Size, CNTR Is
If BL register value is not a multiple of destination access size but CNTR is then the value of CCNR will
not match the value programmed in CNTR after completion of the DMA cycle for the channel.
Table 18-24 illustrates the values of CCNR with different combinations of source and destination access
sizes when BL = 3 bytes and CNTR = 4 bytes.
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Direct Memory Access Controller (DMAC)
Table 18-24. CCNR Value Combinations
No. of Bytes Read by DMA
Source Size
(Bytes)
Destination
Size (Bytes)
2
No. of Bytes Written by DMA
CCNR
(Bytes)
Memory
Increment
Memory
Decrement
Memory
Increment
Memory
Decrement
2
6
6
6
6
6
4
4
8
8
8
8
8
2
4
6
6
8
8
8
4
2
8
8
6
6
6
1
2
4
4
6
6
6
1
4
4
4
8
8
8
NOTE
In case of memory decrement there might be some cases where DMA
overwrites data written by itself so the number of bytes seen by the user can
be different than those mentioned in the tables above.
18.7
Application Note
Following is the sequence to re-program a channel for data transfer:
1. Clear the status register bit corresponding to that channel
(DISR,DBTOSR,DSESR,DRTOSR,DBOSR) after the DMA cycle is completed.
2. Change SMOD (source mode) to 2’b00 and clear CEN.
3. Re-program all registers corresponding to that particular channel, except CCR.
4. Program CCR and set CEN bit to 1.
NOTE
This sequence applies to all 16 channels in all modes—that is, Linear
memory, 2D memory, and FIFO.
18.8
DMA Burst Termination
The DMAC needs to terminate its burst in case of:
• Transfer error response from slave
• Burst time-out error.
• Buffer overflow error.
• Channel disable (by software using CEN bit).
CAUTION
DMA burst termination may not occur immediately.
The burst termination occurs immediately in DMAC only on occurrence of Transfer Error response from
Slave.
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Direct Memory Access Controller (DMAC)
In other cases—that is, Burst time-out, Buffer overflow and Channel disable (by software using CEN bit)
it takes about 2 more AHB transfers to terminate the burst after these are sensed. The burst termination is
not done immediately to avoid AHB protocol violation.
In case the burst hangs and hready is not asserted for a large number of cycles then this must be handled
by the watchdog timer in the ABCD Module in i.MX21 or by the system software.
18.9
Glossary of Terms Used
DMA burst—This refers to the burst cycles on the AHB Bus performed by the DMA.
DMA cycle—A DMA cycle can consists of a number of DMA bursts depending on the Channel Burst
Length and Channel Count register settings. For example, For BL = 4 and CNTR = 8, the DMA cycle will
consist of 2 DMA bursts.
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Direct Memory Access Controller (DMAC)
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Chapter 19
NAND Flash Memory Controller
This chapter describes the NAND Flash Controller on i.MX21. The NAND Flash Controller includes the
following distinctive features.
• NAND Flash Interface: 8-bits / 16-bits (Pin Option)
• Internal RAM buffer (2 Kbyte) that is used as Boot RAM at booting and for buffering at normal
operation
• Internal RAM buffer is memory mapped to the same AHB region as the registers
• Supports all 512B and 2 Kbyte page sized NAND Flash products regardless of density and/or
organization
Along with these features is a host interface with the following functional features:
• Internal Bootcode loader during power-up (that can be enabled or disabled) Supports burst mode
read and write using 16-bits or 32-bits bus transfers
• Error Correction Code (ECC) mode with detection and can be bypassed using single-bit
auto-correction
• Multiple resets
— Cold reset/ Warm reset / Hot reset (Reset of NAND Flash Controller and NAND Flash)
• Data Protection
— Write Protection mode to the lower 1 Kbyte of RAM buffer space
— Block based write protection of NAND Flash
— Automatic Write protection of RAM buffer and NAND Flash during power-up
These features are combined with the ability to handshake with a NAND Flash through the use of interrupt
pins that indicate if the NAND Flash is Ready or Busy.
Figure 19-2 shows a block diagram of the NAND Flash Controller.
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19-1
NAND Flash Memory Controller
NF8BOOT_B
LOGIC
NF16BOOT_B
READ &
WRITE
CONTROL
RAM
BUFFER
(SRAM)
ECC
CONTROL
BOOTLOADER
NF_16BIT_SEL
CLE
ALE
CE
HOST CONTROL
WE
DATA
OUTPUT
CONTROL
REGISTER
(COMMAND
ADDRESS /
STATUS)
ADRESS
CONTROL
NAND FLASH CONTROL
AHB BUS INTERFACE
AHB BUS
RE
WP
R/nB
fDin
fDout
Figure 19-1. NAND Flash Controller Block Diagram
19.1
Functional Overview
The NAND Flash Controller interface with standard NAND Flash parts to the i.MX21 and hides the
complexities of accessing the NAND Flash. It provides a glueless interface to both 8-bit and 16-bit NAND
Flash parts with page sizes of 512 bytes or 2 Kbytes. The maximum density the NAND Flash Controller
can support is limited by the Write Protection Unlock registers (Unlock_Start_Blk_Add and
Unlock_End_Blk_Add). The limitation comes from the fact that these are 16-bit registers. Assuming the
Unlock_Start_Blk_Add register starts at address 0x0000 and the Unlock_End_Blk_Add ends at address
0xFFFF, this yields a maximum of 64 k blocks (65,536 blocks). To calculate that maximum supported
density, one also has to take into account the NAND Flash page size, either 512 bytes or 2 Kbytes. Thus
the maximum densities that can be supported according to the respective page size are as follows:
512 byte page size with 32 pages/block: 512 bytes/page × 32 pages/block × 8bits/byte × 64 k-blocks = 8 Gbit
2 Kbyte page size with 64 pages/block: 2 Kbyte/page × 64 pages/block × 8bits/byte × 64 k-blocks = 64 Gbit.
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NAND Flash Memory Controller
The NAND Flash Controller is comprised of control logic and 2 Kbytes of internal RAM buffer. This
2 Kbytes buffer is used as BootRAM during cold reset (when boot from NAND Flash is chosen), and is
used as regular RAM buffer after the boot procedure (to cache data to/from flash). The internal RAM
buffers can be accessed as half-words (16-bits) or words (32-bits) and byte mode access is not supported.
The NAND Flash Controller provides a host transparent mechanism to input commands and addresses into
the NAND Flash to read, write (program), erase or query status from the NAND Flash.
When the host needs to read from NAND Flash, it configures the controller with the appropriate read
command and address and waits for an interrupt. The controller then transfers a page from the NAND
Flash into the RAM buffer and generates an interrupt to signal that the read operation has completed. When
this interrupt occurs the host can read the content from the internal RAM buffer.
When the host needs to program (write) the NAND Flash, it configures the controller and fills the RAM
buffer with the content to be programmed, followed by a program command to the controller. The
controller then performs the programming, and at the end it will assert an interrupt to the host. The host
then checks the status of the operation by reading the status registers.
19.1.1
BOOTLOADER on Cold Reset Operation
Cold reset of the NFC and NAND Flash takes place during Power-On-Reset (POR).
The i.MX21 can be externally configured via its BOOT[3:0] pins to boot off the NAND Flash. The
controller does this by copying 2 Kbytes of data from Block 0 of the NAND Flash to the internal RAM
buffer (called BootRAM when used for booting).
The BOOTLOADER hardware module in the controller is responsible for automatically loading 2 Kbytes
from the NAND Flash device into the internal 2 Kbyte RAM buffer. After exiting from the reset state, the
ARM926EJ-S™ can read the first instruction from the BootRAM.
19.1.2
NAND Flash Control
The NAND Flash Control generates all the control signals that control the NAND Flash: nCE (Flash Chip
Enable), nRE (Read Enable for read operations), nWE (Flash Write Enable), CLE (Flash Command Latch
Enable, ALE (Flash Address Latch Enable). It monitors the R/nB (Flash Ready/Busy indication) signal to
check if the NAND Flash is in the middle of an operation.
19.1.3
ECC Control
The ECC (Error Correction Code) block performs singe-bit error correction within each 512byte/2 Kbyte
page and multi-bit error detection.
While the NFC accesses NAND Flash for a Program operation, it generates a code (24bits for the main
area data and 10bits for the spare area data). For Read operations, it generates an ECC code and detects
the number of errors and the error position, and corrects when there is a single-bit error. The ECC code is
updated by the NFC automatically. After a Read operation, the host can know whether there is error or not
by reading the status register (see section Table 19-3. "NFC Module Register Summary", on page 9). The
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19-3
NAND Flash Memory Controller
Error type is divided into three types: no error, a single bit error (correctable), and a 2 or more bits of error
(uncorrectable).
The NFC generates the ECC for verification during a Read or Program operation. The generated ECC is
never available in the internal RAM buffer. The ECC is directly programmed into the NAND Flash spare
area during Program operation. The host can find out the generated ECC only by reading back the
programmed page. Likewise, a Read operation will always read the NAND Flash spare area data and hence
the generated ECC for verification is never available in the RAM buffer. Only the programmed ECC is
available, always.
The ECC hardware always performs error detection. However error correction can be controlled
(bypassed). This allows the host to examine the content in error, before software based correction or to
employ proprietary ECC algorithms, if necessary.
19.1.4
Address Control
This module is responsible for address control and generation. It defines RAM buffer address generation
(RAM buffer address for Data In/Data Out). It takes into account the Lock State Sequence (see section
19.5.4 "Write Protection", on page 31) and contains the Flash Memory Lock Address Comparator and
RAM buffer Lock Address Comparator that are used to determine if the area is protected. It also generates
the RAM buffer address for Bootload and the RAM buffer address for error correction.
19.1.5
RAM Buffer (SRAM)
The internal RAM Buffer is a 2,112 byte single port RAM buffer that is based on a synchronous high
performance design. The full single port architecture share I/O and control for both NAND flash side and
AHB side.
This memory has 528 words of 32 bits each, of which 512 words are used for the 4 main buffers, and the
remaining 16 words form the spare area used for ECC and other data. This reflects the page organization
of the NAND Flash device.
19.1.6
Register (Command/Address/Status)
This module contains 15 registers of 16-bits each. With these registers the host can control the NFC, read
status on various operations, and perform direct command or address insertion to the NAND Flash.
19.1.7
Read and Write Control
The Read and Write Control block contains a connection to the internal bus which is connected to the RAM
buffer and registers. On this internal bus, the block handles synchronous read and asynchronous write
operations. It supports synchronous burst read lengths of 16-bit and 32-bit words.
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NAND Flash Memory Controller
19.1.8
Data Output Control
This module controls the data output (32-bits on the internal bus) which is driven to the AHB interface. It
includes RAM buffer data output, register data output, and RAM buffer synchronization of the read mode
pipe line.
19.1.9
Host Control
This module defines Host control which is connected to the AHB Interface through the internal bus.
19.1.10 AHB Interface
The AHB Interface is an adapter between AMBA AHB and the internal bus.
On the AHB side it supports 16-bit and 32-bit bus widths, burst and non-burst operations and on the
internal bus side it supports 16-bit and 32-bit bus width with synchronous burst read and write.
This bus interface supports Little Endian byte ordering only.
When the transaction from the AHB is 16 bits, the interface translates the transaction to the internal bus.
When the transaction is 32bits to/from registers, the interface breaks the transaction into two 16-bit
transactions on the internal bus.
When the transaction from the AHB is a burst-read or write transaction, the interface creates a synchronous
burst read cycle on the internal bus.
19.2
External
This section describes the input and output signals between the NAND Flash Controller.
The external interface is connected to the external memory device and is summarized in Table 19-2 and
detailed in Section 19.2.1, “Flash Chip Enable (NFCE),” on page -5.
19.2.1
Flash Chip Enable (NFCE)
This output signal is the NAND Flash selection control. When NAND Flash is in the Busy state, NFCE
high is ignored, and the device does not return to standby mode.
19.2.2
Flash Read Enable (NFRE)
This output signal is the NAND Flash serial data-out control, and when active drives the flash data onto
the NAND Flash I/O bus. When writing a burst into the NAND Flash, NFRE increments the NAND Flash
internal column address counter by one.
19.2.3
Flash Write Enable (NFWE)
This output signal controls writes to the NAND Flash I/O port. Commands, address, and data are latched
on the rising edge of the NFWE signal.
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NAND Flash Memory Controller
19.2.4
Flash Command Latch Enable (NFCLE)
The CLE output signal controls the activating path for commands sent to the command register of the
NAND Flash. This signal is active high, and commands are latched into the command register of NAND
Flash through the I/O ports on the rising edge of the NFWE signal.
19.2.5
Flash Address Latch Enable (NFALE)
The NFALE output signal controls the activating path for address to the internal address registers of the
NAND Flash. Addresses are latched on the rising edge of NWFWE when NFALE is high.
19.2.6
Flash Write Protect (NFWP)
The NFWP signal provides inadvertent program and erase protection during power transitions and is
automatically controlled by the NFC. This signal status is activated to Low only during power-up.
19.2.7
NFRB—Flash Ready/Busy
NFRB input indicates the status of the NAND Flash operation. When low, it indicates that a Program,
Erase, or random Read operation of the NAND Flash is in progress and returns to high state upon
completion. It is an open drain output and a 100 K Ohm pull-up resistor is internally connected (Internal
to the memory device). It does not float to a high-impedance condition when the device is deselected or
when outputs are disabled.
19.2.8
WARM Reset Operation
A warm reset occurs when the RESET pin of i.MX21 is asserted or when an internal WATCHDOG timeout
occurs. This makes the controller and NAND Flash stop the current operation and all internal registers go
to the default state. The device is guaranteed to be reset in case RESET pulse is longer than 20 times the
clock period of the NFC. Warm reset has no effect on the contents of main and spare area buffers.
CAUTION
When a warm reset is triggered by the RESET pin (RESET_IN) or an internal
WATCHDOG timeout, the system bootloader does not reload 2 Kbytes of data from
Block 0 of the NAND Flash to the internal RAM buffer (BootRAM). To reboot the
system successfully, the bootcode in BootRAM loaded during a cold (POR) reset
period must remain unchanged. Therefore, system designers are advised to
minimize the bootcode to 512 bytes (1 Kbyte) and always reserve the first 512 bytes
(1 Kbyte) in the RAM buffer for maintaining the bootcode. The remaining RAM
Buffer can still be used for subsequent NAND Flash read or re-programming and
does not affect normal NAND Flash operation. Note that the NAND Flash
controller reads a maximum of 528 bytes per page read and it is recommended when
reading from 2 Kbytes page size NAND Flash memories to transfer each 528 byte
read from the NAND Flash controller RAM to another memory location such as
SDRAM. Refer to Section 23.3.19, NAND Flash Operation Configuration
(Configuration 2), bit FDO for more details on NAND Flash data output (reads).
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NAND Flash Memory Controller
19.2.9
Pin Configuration for the NAND Flash Controller (NFC)
Table 19-1shows the required GPIO configuration to enable the NFIO pins. The GPR (General Purpose
Register) and GPIO In Use register (GIUSR) for Port F are configured to select 8-bit NFIO function after
POR.
Table 19-1. GPIO Configuration for NAND Flash Controller
NFC Pin
Pin Description
GPIO Port
Configuration to Enable NFIO
NFIO15–11 Alternate function of Address bus A25–A21
–
Set GPR bits 31–27 if 16-bit NAND Flash device is used
NFIO10–8 Alternate function of Address bus A15–A13
–
Set GPR bits 25–23 if 16-bit NAND Flash device is used
NFIO7–0
Primary function
PF14–PF7
Clear GPR bits 14–7
NFWE_B
Primary function
PF6
Clear GPR bit 6
NFRE_B
Primary function
PF5
Clear GPR bit 5
NFALE
Primary function
PF4
Clear GPR bit 4
NFCLE
Primary function
PF3
Clear GPR bit 3
NFWP_B
Primary function
PF2
Clear GPR bit 2
NFCE_B
Primary function
PF1
Clear GPR bit 1
NFRB
Primary function
PF0
Clear GPR bit 0
19.3
Programming Model
There are 10 NFC Control (Write) Registers and 5 Status (Read) registers. This section describes the
memory map of the NFC. In general it is divided into four parts:
1. Main area RAM buffer memory which is used for data loading from the NAND Flash or
programming the NAND Flash.
2. Spare area RAM buffer memory that is used for ECC (Error Correction) Code and can also be used
for other functions like Logical Sector Number, Bad Block Information, and Wrap Count.
3. Registers which control the NFC and provide a current status of the last operation.
4. Reserved area.
Note that all registers and internal memory are memory mapped to the same AHB region.
19.3.1
Memory Mapping
The NFC internal memory arrays are mapped to the address 0xDF00_3000-0xDF00_3FFF. Both Registers
and Internal memory are mapped to this region. The memory mapping arrays are mapped according to
Table 19-2.
Table 19-2. NFC Array—Internal Register Summary
Address
Use
Access
0xDF00_3000h – 0xDF00_31FEh
Main area Buffer 0
R/W
0xDF00_3200h – 0xDF00_33FEh
Main area Buffer 1
R/W
0xDF00_3400h – 0xDF00_35FEh
Main area Buffer 2
R/W
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NAND Flash Memory Controller
Table 19-2. NFC Array—Internal Register Summary (continued)
19.3.2
Address
Use
Access
0xDF00_3600h – 0xDF00_37FEh
Main area Buffer 3
R/W
0xDF00_3800h – 0xDF00_380Eh
Spare area Buffer 0
R/W
0xDF00_3810h – 0xDF00_381Eh
Spare area Buffer 1
R/W
0xDF00_3820h – 0xDF00_382Eh
Spare area Buffer 2
R/W
0xDF00_3830h – 0xDF00_383Eh
Spare area Buffer 3
R/W
0xDF00_3840h – 0xDF00_3BFEh
Reserved
–
0xDF00_3E00 – 0xDF00_3E1C
Registers
R/W
Spare Area Buffer
The main area buffer is a data block whereas the spare area buffer is used for several functions including
Error Correction. There is a difference in the memory organization of this memory region depending on
whether the NFC is interfaced to an 8-bit or 16-bit NAND Flash bus width. In Figure 19-2, 8-bit
organization is shown and in Figure 19-3, 16 bit configuration is shown.
Address
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
800h (SB0)
LSN(2nd)
LSN(1st)
802h (SB0)
WC(1st)
LSN(3rd)
804h (SB0)
BI
WC(2nd)
806h (SB0)
ECC Code for Main area data (2nd)
ECC Code for Main area data (1st)
808h (SB0)
ECC Code for Spare area data (1st)
ECC Code for Main area data (3rd)
80Ah (SB0)
Reserved
ECC Code for Spare area data (2nd)
80Ch (SB0)
Reserved
Reserved
80Eh (SB0)
Reserved
Reserved
0
810h–81Eh (SB1)
820h–82Eh (SB2)
SB1 – SB3 have same assignment like SB0.
830h–83Eh (SB3)
Figure 19-2. Spare Area Buffer (NAND Flash with 8-Bit I/O Bus)
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NAND Flash Memory Controller
Address
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
800h (SB0)
LSN(2nd)
LSN(1st)
802h (SB0)
WC(1st)
LSN(3rd)
804h (SB0)
Reserved
WC(2nd)
806h (SB0)
ECC Code for Main area data (2nd)
ECC Code for Main area data (1st)
808h (SB0)
ECC Code for Spare area data (1st)
ECC Code for Main area data (3rd)
80Ah (SB0)
BI
ECC Code for Spare area data (2nd)
80Ch (SB0)
Reserved
Reserved
80Eh (SB0)
Reserved
Reserved
0
810h–81Eh (SB1)
820h–82Eh (SB2)
SB1 – SB3 have same assignment like SB0.
830h–83Eh (SB3)
Figure 19-3. Spare Area Buffer (NAND Flash with 16-Bit I/O Bus)
Note: LSN—Logical Sector Number
Note: WC—Wrap Count and other bytes have same wrap count information and used as error correction for wrap count itself.
Note: BI—Bad block Information
The host can use all of the spare area except BI and ECC code areas. This includes reserved (unused)
locations in the spare area.
The NFC automatically generates ECC code for both main and spare areas during data transfer to the
NAND Flash. Though, the ECC code is written to the spare area of the NAND Flash, it is not updated into
the spare area in RAM.
When programming or reading the spare area, the spare area buffer number (SB 0–3) is chosen through
the Start buffer register.
The NFC module includes 15 registers of 16 bits each. Table 19-3 summarizes these registers and their
addresses. Registers are accessible in supervisor mode only and result in an exception otherwise.
Table 19-3. NFC Module Register Summary
Description
Name
Address
Internal SRAM Size
NFC_BUFSIZE
0xDF00_3E00
NAND Flash Block Address for Lock Check
Block_Add_Lock
0xDF00_3E02
Buffer Number for Page Data Transfer To/From Flash Memory
RAM_Buffer_Address
0xDF00_3E04
NAND Flash Address
NAND_Flash_Add
0xDF00_3E06
NAND Flash Command
NAND_Flash_CMD
0xDF00_3E08
NFC Internal Buffer Lock Control
NFC_Configuration
0xDF00_3E0A
Controller Status/Result of Flash Operation
ECC_Status_Result
0xDF00_3E0C
ECC Error Position of Main Area Data Error
ECC_Rslt_Main_area
0xDF00_3E0E
ECC Error Position of Spare Area Data Error
ECC_Rslt_Spare_area
0xDF00_3E10
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
19-9
NAND Flash Memory Controller
Table 19-3. NFC Module Register Summary (continued)
Description
Name
Address
Nand Flash Write Protection
NF_WR_Prot
0xDF00_3E12
Start Address for Write Protection Unlock
Unlock_Start_Blk_Add
0xDF00_3E14
End Address for Write Protection Unlock
Unlock_End_Blk_Add
0xDF00_3E16
NAND Flash Write Protection Status
NAND_Flash_WR_Pr_St
0xDF00_3E18
NAND Flash Operation Configuration (Configuration 1)
NAND_Flash_Config1
0xDF00_3E1A
NAND Flash Operation Configuration (Configuration 2)
NAND_Flash_Config2
0xDF00_3E1C
19.3.3
Internal SRAM Size
This is a read only register.
NFC_BUFSIZE
BIT
NFC_BUFSIZE
15
14
13
12
11
10
9
8
7
Addr
0xDF00_3E00
6
5
4
3
2
1
0
BUFSIZE
TYPE
0
0
0
0
0
0
0
0
0
0
0
0
r
r
r
r
0
0
0
1
RESET
0x0001
Table 19-4. Internal SRAM Size Register Description
Name
Description
Reserved
Bits 15–4
Reserved
BUFSIZE
Bits 3–0
Buffer Size—The size of internal RAM buffer.
19.3.4
Settings
0000= 1 kbyte
0001= 2 kbytes (Default)
0010= 3 kbytes
0011= 4 kbytes
0100–1111 = Reserved
NAND Flash Block Address for Lock Check
Block_Add_Lock
NAND Flash Block Address for Lock Check
Addr
0xDF00_3E02
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
i.MX21 Reference Manual, Rev. 3
19-10
Freescale Semiconductor
NAND Flash Memory Controller
Table 19-5. NAND Flash Block Address for Lock Check Register Description
Name
Description
Reserved
Bits 15–0
19.3.5
Reserved—These bits are reserved and should read 0.
Buffer Number for Page Data Transfer To/From Flash Memory
RAM_Buffer_Address
BIT
15
Buffer Number for Page Data Transfer To/From Flash Memory Addr
0xDF00_3E04
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RBA
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-6. Buffer Number for Page Data Transfer To/From Flash Memory Register Description
Name
Description
Settings
Reserved
Bits 15–2
Reserved
RBA
Bits 1–0
RAM Buffer Address—Specifies the RAM buffer number to use for data
transfer to or from the NAND Flash.
19.3.6
NAND Flash Address
NAND_Flash_Add
BIT
00= 1st internal RAM buffer
01= 2nd internal RAM buffer
10= 3rd internal RAM buffer
11= 4th internal RAM buffer
15
NAND Flash Address
14
13
12
11
10
9
8
Addr
0xDF00_3E06
7
6
5
4
3
2
1
0
ADD
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-7. NAND Flash Address Register Description
Name
ADD
Bits 15–0
Description
NAND Flash Address—NAND Flash address which will be read, programmed or erased. This address is
entered into NAND Flash.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
19-11
NAND Flash Memory Controller
19.3.7
NAND Flash Command
NAND_Flash_CMD
BIT
15
NAND Flash Command
14
13
12
11
10
9
8
Addr
0xDF00_3E08
7
6
5
4
3
2
1
0
CMD
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
RESET
0x0000
Table 19-8. NAND Flash Command Register Description
Name
CMD
Bits 15–0
Description
NAND Flash Command—This CMD is entered into NAND Flash.
19.3.8
NFC Internal Buffer Lock Control
NFC_Configuration
BIT
15
NFC Internal Buffer Lock Control
14
13
12
11
10
9
8
7
6
Addr
0xDF00_3E0A
5
4
3
2
BLS
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
RESET
0x0001
Table 19-9. NFC Internal Buffer Lock Control Register Description
Name
Description
Reserved
Bits 15–2
Reserved—These bits are reserved and should read 0.
BLS
Bits 1–0
Buffer Lock Set—This field specifies the buffer lock status of first 2 page buffer.
Settings
00 = Locked
01 = Locked (default)
10 = Unlocked
11 = Locked
i.MX21 Reference Manual, Rev. 3
19-12
Freescale Semiconductor
NAND Flash Memory Controller
19.3.9
Controller Status/Result of Flash Operation
ECC_Status_Result
BIT
15
Controller Status/Result of Flash Operation
14
13
12
11
10
9
8
7
6
Addr
0xDF00_3E0C
5
4
3
2
1
ERm
TYPE
0
ERs
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-10. Controller Status/Result of Flash Operation Register Description
Name
Description
Settings
Reserved
Bits 15–4
Reserved—These bits are reserved and should read 0.
ERm
Bits 3–2
ECC Error for Main Area Data—Shows the number of errors in a
page as a result of ECC check at the page read operation. ECC
algorithm of NFC cannot correct more than 1 error bit per page and 2
or more error bits are considered uncorrectable.
00 = No Error
01 = 1-bit Error (Correctable Error)
10 = 2-bits Error (Uncorrectable Error)
11 = Reserved
ERs
Bits 1–0
ECC Error for Spare Area Data—Shows the number of errors in a
page as a result of ECC check at the page read operation. ECC
algorithm of NFC cannot correct more than 1 error bit per page and 2
or more error bits are considered uncorrectable.
00 = No Error
01 = 1-bit Error (Correctable Error)
10 = 2-bits Error (Uncorrectable Error)
11 = Reserved
19.3.10 ECC Error Position of Main Area Data Error (8-bit NAND Flash)
ECC_Rslt_Main_area
BIT
15
ECC Error Position of Main Area Data Error
14
13
12
11
10
9
8
7
6
5
Addr
0xDF00_3E0E
4
3
ECC Result 1
TYPE
2
1
0
ECC Result 2
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-11. ECC Error Position of Main Area Data Error (8-bit NAND Flash) Register Description
Name
Description
Reserved
Bits 15–12
Reserved—These bits are reserved and should read 0.
ECC Result 1
Bits 11–3
ECC Error Address of Main area Register
ECC Result 1—Byte position of ECC error within the page (512 bytes).
ECC Result 2
Bits 2–0
ECC Error Address of Main area Register
ECC Result 2—Bit position of ECC error within the byte for 8-bit NAND Flash.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
19-13
NAND Flash Memory Controller
19.3.11 ECC Error Position of Main Area Data Error
(16-Bit NAND Flash)
ECC Error Position of Main Area Data Error
Addr
0xDF00_3E0E
ECC_Rslt_Main_area
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
ECC Result 1
TYPE
2
1
0
ECC Result 2
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-12. ECC Error Position of Main Area Data Error (16-Bit NAND Flash) Register Description
Name
Description
Reserved
Bits 15–12
Reserved
ECC Result 1
Bits 11–4
ECC Error Address of Main area Register
ECC Result 1—half-word position of ECC error within the page (256 half-words).
ECC Result 2
Bits 3–0
ECC Error Address of Main area Register
ECC Result 2—Bit position of ECC error within the half-word.
19.3.12 ECC Error Position of Spare Area Data Error
(8-bit NAND Flash)
ECC Error Position of Spare Area Data Error
Addr
0xDF00_3E10
ECC_Rslt_Spare_area
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
ECC Result 4
TYPE
1
0
Result 3
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-13. ECC Error Position of Spare Area Data Error
(8-Bit NAND Flash) Register Description
Name
Description
Reserved
Bits 15–5
Reserved—These bits are reserved and should read 0.
ECC Result 4
Bits 4–3
ECC Error Address of Spare area Register
ECC Result 4—Byte position of ECC error in the Logical Sector Number.
ECC Result 3
Bits 2–0
ECC Error Address of Spare area Register
ECC Result 3—Bit position of ECC error within the byte.
Settings
00 = 1st byte
01 = 2nd byte
10 = 3rd byte
–
i.MX21 Reference Manual, Rev. 3
19-14
Freescale Semiconductor
NAND Flash Memory Controller
19.3.13 ECC Error Position of Spare Area Data Error
(16-bit NAND Flash)
ECC Error Position of Spare Area Data Error
Addr
0xDF00_3E10
ECC_Rslt_Spare_area
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
Result 4
TYPE
2
1
0
Result 3
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-14. ECC Error Position of Spare Area Data Error (16bit NAND Flash) Register Description
Name
Description
Reserved
Bits 15–5
Reserved—These bits are reserved and should read 0.
ECC Result 4
Bit 4
ECC Error Address of Spare Area Register
ECC Result 4—Half-word position of ECC error in the Logical Sector Number.
ECC Result 3
Bits 3–0
ECC Error Address of Spare Area Register
ECC Result 3—Bit position of ECC error within the half-word.
19.3.14 Nand Flash Write Protection
NF_WR_Prot
BIT
15
Nand Flash Write Protection
14
13
12
11
10
9
8
7
Addr
0xDF00_3E12
6
5
4
3
2
1
0
WPC
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
RESET
0x0002
Table 19-15. Nand Flash Write Protection Register Description
Name
Description
Settings
Reserved Reserved—These bits are reserved and should read 0.
Bits 15–3
WPC
Bits 2–0
Write Protection Command—The Command field
specifies the operation which the controller will perform.
0004h (0000 0100) = Unlock NAND Flash block(s)
according to given block address range.
0002h (0000 0010) = Lock all NAND Flash block(s).
0001h (0000 0001) = Lock-tight locked block(s).
For more information on write protection of the NAND Flash, refer to Section 19.5.4, “Write Protection,”
on page -31.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
19-15
NAND Flash Memory Controller
19.3.15 Start Address for Write Protection Unlock
Unlock_Start_Blk_Add
BIT
15
Start Address for Write Protection Unlock
14
13
12
11
10
9
8
Addr
0xDF00_3E14
7
6
5
4
3
2
1
0
USBA
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-16. Start Address for Write Protection Unlock Register Description
Name
Description
USBA
Bits 15–0
Unlock Start Block Address—Starting address of blocks that are in Write Protection mode and to be unlocked.
This address is used in the Unlock Block command.
19.3.16 End Address for Write Protection Unlock
Unlock_End_Blk_Add
BIT
End Address for Write Protection Unlock
15
14
13
12
11
10
9
8
Addr
0xDF00_3E16
7
6
5
4
3
2
1
0
UEBA
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-17. End Address for Write Protection Unlock Register Description
Name
Description
UEBA
Bits 15–0
Unlock End Block Address—Ending address of blocks that are in Write Protection mode and to be
unlocked.This address is used in the Unlock Block command.
19.3.17 NAND Flash Write Protection Status
NAND_Flash_WR_Pr_St
BIT
TYPE
15
14
NAND Flash Write Protection Status
13
12
11
10
9
8
7
6
5
Addr
0xDF00_3E18
4
3
2
1
0
US
LS
LTS
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
RESET
0x0002
i.MX21 Reference Manual, Rev. 3
19-16
Freescale Semiconductor
NAND Flash Memory Controller
Table 19-18. NAND Flash Write Protection Status Register Description
Name
Description
Settings
Reserved
Bits 15–3
Reserved—These bits are reserved and should read 0.
US
Bit 2
Unlocked Status—Specifies whether there are any
unlocked blocks in the NAND Flash.
LS
Bit 1
Locked Status—Specifies that all NAND Flash blocks 0 = Not all NAND Flash blocks are in locked status
are in locked status.
1 = All NAND Flash blocks are in locked status
LTS
Bit 0
Lock-Tighten Status—Specifies that Locked block(s) 0 = Locked block(s) is (are) not lock-tightened
is (are) lock-tightened.
1 = Locked block(s) is (are) lock-tightened
0 = No unlocked block in the NAND Flash
1 = There are unlocked blocks the in NAND Flash
19.3.18 NAND Flash Operation Configuration (Configuration 1)
NAND Flash Operation Configuration (Configuration 1)
NAND_Flash_Config1
BIT
15
14
13
12
11
10
9
8
7
6
5
Addr
0xDF00_3E1A
4
3
2
1
0
INT_MASK ECC_EN SP_EN
TYPE
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
r
r
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
RESET
0x0008
Table 19-19. NAND Flash Operation Configuration (Configuration 1) Register Description
Name
Reserved
Bits 15–5
Description
Settings
Reserved—These bits are reserved and should read 0.
INT_MASK Interrupt Mask—This field determines whether NFC
Bit 4
generate interrupt or mask interrupt.
0 = Unmask interrupt
1= Mask interrupt
ECC_EN
Bit 3
ECC Operation Enable—This field determines whether
ECC auto-correction is executed or bypassed
0 = ECC auto-correction is bypassed
1 = ECC auto-correction is executed
SP_EN
Bit 2
Spare Area Enable—This field determines whether NFC
0 = NAND Flash main and spare area data is
reads/writes only NAND Flash spare area data or both NAND
enabled.
Flash main and spare area data
1 = NAND Flash spare only data is enabled.
Reserved
Bits 1–0
Reserved—These bits are reserved and should read 0.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
19-17
NAND Flash Memory Controller
19.3.19 NAND Flash Operation Configuration (Configuration 2)
Note that INT (Bit 15) reset value is zero, but soon after power-up it will change to a value of one. When
performing boot from NAND Flash, the INT bit will change from zero to one after the transfer of bootcode
has been accomplished. For more information take a look on Section 19.1.1, “BOOTLOADER on Cold
Reset Operation,” on page -3.
NAND_Flash_Config2
BIT
15
14
NAND Flash Operation Configuration (Configuration 2) Addr
0xDF00_3E1C
13
12
11
10
9
8
7
6
5
INT
TYPE
RESET
4
3
FDO
2
FDI
1
0
FADD FCMD
rw
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 19-20. NAND Flash Operation Configuration (Configuration 2) Register Description
Name
Description
Settings
INT
Bit 15
Interrupt—This bit is set to 1 by the NFC when basic 0 = Basic operation or bootloading is still running
operation and bootloading is done, or when warm or hot 1 = Basic operation or bootloading is done.
reset is released. An interrupt event occurs when it is
set to 1 and interrupts from NFC are unmasked.
This bit is cleared by writing a 0. The host should clear
this bit before initiating a new operation.
Basic operation:
NAND Flash command input
NAND Flash address input
NAND Flash Data input
NAND Flash Data output
Reserved
Bits 14–6
Reserved—These bits are reserved and should be set to 0.
FDO
Bits 5–3
NAND Flash Data Output—This field activates NAND Use only 1 of the following options:
FDO[2:0] =
Flash Data Output to NFC.
Note: Output is with respect to the NAND Flash device. 001 = One page data out 1.
010 = NAND Flash ID data out
100 = NAND Flash status register dataout
FDI
Bit 2
NAND Flash Data Input—This field activates NAND
Flash Data Input from NFC.
Note: Input is with respect to NAND Flash device.
0 = To activate another basic operation or change
interrupt bit.
1 = To activate NAND Flash Data Input operation.
FADD
Bit 1
NAND Flash Address Input—This field specifies the
NAND Flash Address Input.
0 = To activate another basic operation or change
interrupt bit.
1 = To activate NAND Flash Address Input operation.
FCMD
Bit 0
NAND Flash Command Input—This field specifies the 0 = To activate another basic operation or change
NAND Flash Command Input.
interrupt bit.
1 = To activate NAND Flash Command Input operation.
1
One page size is determined by SP_EN register bit and NFC_FMS input. It is 528bytes or 16bytes no matter if NFC_FMS is
0 or 1.
i.MX21 Reference Manual, Rev. 3
19-18
Freescale Semiconductor
NAND Flash Memory Controller
NOTE
1) When the basic operation is completed, the FCMD/FADD/FDI/FDO bits
will be reset to 0 automatically.
2) Only one operation among FCMD/FADD/FDI/FDO can be activated.
Activate only one option (INT can be activated with one of
FCMD/FADD/FDI/FDO operations).
19.4
Operating Modes
The NAND Flash Controller operating modes are described in this section. Table 19-21 shows the possible
operating modes of the NAND Flash Controller. The BOOT[3:0] are external pins that select system boot
options. NFC_FMS and NF_16BIT_SEL are bits that are automatically set or cleared by the hardware
when NAND Flash boot options are chosen. When other boot options are chosen, these bits are set by
software to indicate to the NAND Flash Controller on the configuration and organization of the NAND
Flash attached to the NAND Flash Controller. NFC_FMS and NF_16BIT_SEL are bits in the Function
Multiplexing Control Register (FMCR). This register is described in the System Control, chapter.
Table 19-21. NAND Flash Operating Modes
BOOT[3:0] NFC_FMS NF_16BIT_SEL
Description
0011
1
1
Boot from a 16-bit NAND Flash (2 kbytes per page). NFC_FMS and NF_16BIT_SEL
are configured internally by hardware.
0100
0
1
Boot from a 16-bit NAND Flash (512 bytes per page). NFC_FMS and
NF_16BIT_SEL are configured internally by hardware.
0010
1
0
Boot from an 8-bit NAND Flash (2 kbytes per page). NFC_FMS and 16BIT_SEL are
configured internally by hardware.
0111
0
0
Boot from an 8-bit NAND Flash (512 bytes per page). NFC_FMS and
NF_16BIT_SEL are configured internally by hardware.
X
0
0
No boot from NAND Flash. Host configures NAND Flash as 8-bit with 512 bytes per
page.
X
0
1
No boot from NAND Flash. Host configures NAND Flash as 16-bit with 512 bytes per
page.
X
1
0
No boot from NAND Flash. Host configures NAND Flash as 8-bit with 2 kbytes per
page.
X
1
1
No boot from NAND Flash. Host configures NAND Flash as 16-bit with 2 kbytes per
page.
19.5
General Operation
This section describes how to operate the NFC using the NFC control registers and interrupts. The NFC
operations are divided into the following operations.
•
•
•
•
Basic Operations
Normal operations
ECC operations to the internal memory and the flash device
Write protection operation to the internal memory and the flash device
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
19-19
NAND Flash Memory Controller
Normal Operations are used to operate the NAND Flash. These operations are composed of a sequence of
Basic Operations. Basic and Normal Operations are described in the following sections along with flow
charts.
This section also provides memory configuration examples.
19.5.1
Basic Operation
Normal operation (for example Read NAND Flash data, etc.) are composed of Basic Operations. A Basic
Operation is used to build higher levels of operations. The basic operations are as follows.
• Preset Operation
• NAND Flash Command Input Operation
• NAND Flash Address Input Operation
• NAND Flash Data Input Operation
• NAND Flash Data Output Operation
Each of these operations are detailed in the following sections.
19.5.1.1
Preset Operation
The sequence of events of the NAND Flash controller during Preset operation is shown in Figure 19-4.
Start
Set NFC Configuration
Register(E0Ah)
if needed
Set NAND Flash Address for Lock check
Register(E02h)
Set NAND Flash Write Protection Command
Register(E12h), Unlock Start Block Address
Register(E14h), Unlock End Block Address
Register(E16h), if needed.
Set NAND Flash Configuration1 Register(E1Ah)
(Set ECC_EN & SP_EN & RW_SET)
Pre-Setting is completed
Figure 19-4. Preset Operation
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NAND Flash Memory Controller
19.5.1.2
NAND Flash Command Input Operation
The sequence of events of the NAND Flash controller during Input operation is shown in Figure 19-5.
Start
Write NAND Flash Command to NAND Flash
Command Register(E08h)
Set NAND Flash Operation Configuration2
Register(E1Ch)
(Set INT to 0 & FCMD to 1 & other bits to 0)
Wait
INT = 1?
No
Yes
NAND Flash Command
input is completed
Figure 19-5. NAND Flash Command Input Operation
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Freescale Semiconductor
19-21
NAND Flash Memory Controller
19.5.1.3
NAND Flash Address Input Operation
The sequence of events of the NAND Flash controller during Flash Address Input operation is shown in
Figure 19-6.
Start
Write NAND Flash Address to NAND Flash
Address Register(E06h)
Set NAND Flash Operation Configuration2
Register(E1Ch)
(Set INT to 0 & FADD to 1 & other bits to 0)
Wait
INT = 1?
No
Yes
Is Address cycle
completed?
Yes
No
NAND Flash Address
input is completed
Figure 19-6. NAND Flash Address Input Operation
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NAND Flash Memory Controller
19.5.1.4
NAND Flash Data Input Operation
The sequence of events of the NAND Flash controller during Flash Data Input operation is shown in
Figure 19-7.
Start
Set RAM Buffer Address Register(E04h)
where data is loaded from host
Write the NAND Flash data to RAM Buffer
Set NAND Flash Operation Configuration2
Register(E1Ch)
(Set INT to 0 & FDI to 1 & other bits to 0)
Wait
INT = 1?
No
Yes
NAND Flash Data Input
is completed
Figure 19-7. NAND Flash Data Input Operation
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NAND Flash Memory Controller
19.5.1.5
NAND Flash Data Output Operation
The sequence of events of the NAND Flash controller during Flash Data Output operation is shown in
Figure 19-8.
Start
Set NAND Flash Operation Configuration1
Register(E1Ah)
(Set RW_SET to 10 & ECC_EN & SP_EN)
Set RAM Buffer Address Register(E04h)
where data is loaded from NAND Flash
Set NAND Flash Operation Configuration2
Register(E1Ch)
(Set INT to 0 & FDO & other bits to 0)
Wait
INT = 1?
No
Yes
Read the NAND Flash data from RAM Buffer
NAND Flash Data Output
is completed
Figure 19-8. NAND Flash Data Output Operation
19.5.2
Normal Operation
Normal Operations are composed of Basic Operations. The following is a list of Normal Operations:
• NAND Flash Read ID Operation
• NAND Flash Read Status Operation
• NAND Flash Read Data Operation
• Program NAND Flash Data Operation
• Erase NAND Flash Data Operation
• Hot Reset
Each of these operations are detailed in the following sections.
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NAND Flash Memory Controller
19.5.2.1
NAND Flash Read ID Operation
The sequence of events of the NAND Flash controller during Flash Read ID operation is shown in
Figure 19-9.
Start
Preset operation.
Set RAM Buffer Address Register(E04h)
(Set RBA to load NAND Flash ID)
NAND Flash Command Input operation.
(Command: 90h)
NAND Flash Address Input operation.
NAND Flash Data Output operation.
Read ID data from assigned RAM buffer
(refer to NAND Flash ID Data assignment
on next page)
End
Figure 19-9. Read NAND Flash ID Operation
The assignment of NAND Flash ID data is stored in RAM buffer (8-bit NAND Flash) and is formatted as
shown in Figure 19-10.
1st half-word
RAM Buffer of RBA
address
2nd half-word
3rd half-word
1st byte of ID 2nd byte of ID 3rd byte of ID 4th byte of ID 5th byte of ID 6th byte of ID
LSB
MSB
Figure 19-10. NAND (8-Bit) Flash ID Data Format in RAM Buffer
The assignment of NAND Flash ID data stored in RAM buffer (16-bit NAND Flash) is formatted as shown
in Figure 19-11.
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19-25
NAND Flash Memory Controller
1st half-word
RAM Buffer of RBA address 1st Byte of ID
2nd half-word
XXh
LSB
2nd Byte of ID XXh 3rd Byte of ID
XXh
MSB
4th half-word
RAM Buffer of RBA address 4th Byte of ID
LSB
3rd half-word
5th half-word
XXh
5th Byte of ID
6th half-word
XXh 6th Byte of ID
XXh
MSB
Figure 19-11. NAND (16-Bit) Flash ID Data Format in RAM Buffer
19.5.2.2
NAND Flash Read Status Operation
The sequence of events of the NAND Flash controller during Flash Read Status operation is shown in
Figure 19-12.
Start
Preset Operation
Set RAM Buffer Address Register(E04h)
(Set RBA to load NAND Flash Status Data)
NAND Flash Command Input Operation
(Command: 70h)
NAND Flash Data Output Operation
Read ID Data from Assigned RAM Buffer
(refer to NAND Flash Status Data assignment)
End
Figure 19-12. Read NAND Flash Status Operation
The assignment of NAND Flash Status data is stored in RAM buffer (8-bit/16-bit NAND Flash) formatted
as shown in Figure 19-13.
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NAND Flash Memory Controller
1st half-word
RAM Buffer of RBA address 1st Byte of Status
XXh
LSB
--------
MSB
Figure 19-13. NAND (8-Bit/16-Bit) NAND Flash Status Format in RAM Buffer
19.5.2.3
NAND Flash Read Data Operation
The sequence of events of the NAND Flash controller during Flash Read Data operation is shown in
Figure 19-14.
Start
Preset Operation
Set RAM Buffer Address Register(E04h)
(Set RBA to load NAND Flash data)
NAND Flash Command Input Operation
(Command: NAND Flash Read Command)
NAND Flash Address Input Operation
(Address: NAND Flash address to be Read)
NAND Flash Command Input operation
(Command: NAND Flash Read Confirm Command
which is required at 1Gb/2Gb NAND Flash)
NAND Flash Data Output Operation
Check ECC Status Register(E0Ch)
and do next step according to the result
End
Figure 19-14. Read NAND Flash Data Operation
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Freescale Semiconductor
19-27
NAND Flash Memory Controller
19.5.2.4
Program NAND Flash Data Operation
The sequence of events of the NAND Flash controller during Program NAND Flash Data operation is
shown in Figure 19-15.
Start
Preset Operation
Set NAND Flash Address for Lock check
Register(E02h)
Set RAM Buffer Address Register(E04h)
(Set RBA to load data to be
programmed from Host)
NAND Flash Command Input operation
(Command: Data Loading Command)
NAND Flash Address Input operation
(Address: NAND Flash address
to be Programmed)
NAND Flash Data input operation
NAND Flash Command Input operation
(Command: Confirm Command)
NAND Flash Status Read Operation
End
Figure 19-15. Program NAND Flash Data Operation
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NAND Flash Memory Controller
19.5.2.5
Erase NAND Flash Data Operation
The sequence of events of the NAND Flash controller during Erase NAND Flash Data operation is shown
in Figure 19-16.
Start
Preset operation.
Set NAND Flash Address for Lock check
Register(E02h)
NAND Flash Command Input operation.
(Command: Erase Command)
NAND Flash Address input operation.
NAND Flash Command Input operation.
(Command: Confirm Command)
NAND Flash Status Read Operation
End
Figure 19-16. Erase NAND Flash Operation
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19-29
NAND Flash Memory Controller
19.5.2.6
Hot Reset
The Hot Reset operation resets the NAND Flash device. The NAND Flash device stops its current
operation and its internal registers go to their default state.
Start
Preset Operation.
NAND Flash Command
Input Operation
(Command: ffh)
End
Figure 19-17. Hot Reset Operation
19.5.3
ECC Operation
The following sections discuss the details of ECC operation.
19.5.3.1
ECC Operation Case
When NFC accesses NAND Flash for program operation, it generates ECC code (24 bits for main area
data and 10 bits for LSN of spare area data). For a read operation it generates ECC code, detects number
of error bits, and corrects a 1-bit error.
Table 19-22 shows the ECC code assignment of the NAND Flash spare area. This ECC code is updated
by the NFC automatically. After a read operation, a host can know whether there was an error by reading
the status register (Table 19-3). There are three error types: no error, 1-bit error (correctable), and 2 or more
bit errors (uncorrectable).
The generated ECC code during a read or program operation is not updated to the internal buffer RAM. It
is updated to the NAND Flash spare area directly during a program operation. A host can read the
generated ECC code by reading back the programmed NAND Flash spare area.
Table 19-22. ECC Code / Result Readability
Read Operation
Operation ECC code from spare area buffer
ECC Operation Invalid (Pre-written ECC code1)
ECC Auto-correction Bypass
1
2
Invalid (Pre-written ECC code)
Program Operation
ECC result
from register
ECC code from
spare area buffer
ECC result
from register
Valid
Invalid (old data2)
–
Valid
Invalid (old data)
–
Pre-written ECC code—ECC code previously written to NAND Flash spare area in program operation.
Old data—ECC code is not updated to spare buffer, so ECC code placement of spare buffer remains old data.
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NAND Flash Memory Controller
19.5.3.2
ECC Bypass Operation Case
In ECC bypass operation, the NFC generates ECC result that indicate the error position (refer to
Table 19-22), but does not correct the error. After a Read operation, a host can know if there was an error
by reading the status register (see Table 19-3).
As stated above, there are three error types: no error, 1-bit error (correctable), and 2 or more bit errors
(uncorrectable). In the 1-bit error case, the host can correct the error after reading the ECC Result register.
The ECC Bypass operation does not affect the Program operation. ECC is always generated and written
to the NAND Flash Spare area always.
19.5.3.3
ECC Operation Guidance
For ECC generation and correction done by the NFC, it is recommended that the user program with an
ECC operation and Read with an ECC operation. For ECC generation by the NFC and correction done by
the Host, it is recommended that the user program with an ECC operation and Read with ECC bypassed
operation.
The ECC result from the ECC result register after a read operation in both ECC operation and ECC bypass
cases are always valid.
NOTE
When NFC reads NAND Flash data (page or Spare area data), the ECC code
in the RAM buffer (Main or Spare) is the ECC Code from the NAND Flash
and not what was internally generated by the NFC. The NFC generated ECC
code is never updated to the internal buffer areas.
19.5.4
Write Protection
The following sections discuss the details of the Write Protection mechanism within the NFC.
19.5.4.1
Write Protection for RAM Buffer (LSB 1KB)
NFC offers a software Write Protection feature for the first two pages (main and spare area data) of the
RAM buffer, which protects the RAM buffer data. This software Write Protection of the RAM buffer
feature is used by setting a two bit value of the NFC configuration register ([1:0]). The default state is the
Locked state; These two pages of RAM buffer (LSB) move to the locked state after a cold or warm reset.
When this occurs, Write protection is enabled.
Write protection for the main or spare memory regions in the RAM buffer are described in Table 19-23. A
state diagram of RAM buffer Write Protection is shown in Figure 19-18.
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NAND Flash Memory Controller
Table 19-23. Write Protection for Main/Spare RAM Buffer
Main Area
Spare Area
1st page RAM buffer
Available for Write
Protection
2nd page RAM buffer
3rd page RAM buffer
Not Available for
Write Protection
Operation
4th page RAM buffer
NFC Configuration
Register[1:0] = 00/01/11
NFC Configuration
Register[1:0] = 10
Unlocked
Device in
Cold or
Warm Reset
Initial State
Locked
Figure 19-18. State Diagram of RAM Buffer Write Protection
19.5.4.2
19.5.4.2.1
Write Protection for NAND Flash
Write Protection Modes
NFC offers both hardware and software Write Protection features for NAND Flash. The software Write
Protection feature is used by executing the Lock block command or Lock-tight block command, and the
hardware Write Protection feature is used by executing cold reset or warm reset.
19.5.4.2.2
Write Protection Commands
Individual instant secured blocks protect code and data by allowing any block to be locked or
lock-tightened. This Write Protection scheme offers two levels of protection. The first allows
software-only control of Write Protection (useful for frequently changed data blocks), while the second
requires hardware interaction before locking can be changed (protects infrequently changed code blocks).
The following list summarizes the locking functionality.
• All blocks power-up in a locked state. Unlock commands can unlock these blocks.
• The Lock-tight command locks blocks and prevents it from being unlocked. Lock-tight state can
be returned to lock state only when Cold/Warm reset is executed.
• Writing to Unlock the start/end address register during Lock-tighten status does not affect the
unlock address, since the NFC has another Unlock address register internally to prevent this.
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NAND Flash Memory Controller
19.5.4.2.3
Write Protection Status
The current NFC Write Protection status can be read in the NAND Flash Write Protection status register
(NAND_Flash_WR_Pr_St). There are three bits—US, LS, LTS, which are not cleared by hot reset. These
Write Protection status registers are updated as soon as the Write Protection command is executed.
Figure 19-19 shows the state diagram of the NAND Flash Write Protection.
No Cold Reset and No Warm reset
&
Start block address +
End block address +
Unlock block Command
Unlocked
No Cold reset and No
Warm reset
&
Lock block Command
No Cold reset and
No Warm reset
&
Start block address +
End block address +
Unlock block Command
Cold or
Warm
Reset
Initial state
Locked
No Cold reset and No
Warm reset
&
Lock-tight block
Command
No Cold reset and No
Warm reset
&
Lock-tight block
Command
Lock-Tight
Cold reset or Warm reset
Figure 19-19. State Diagram of NAND Flash Write Protection
19.5.4.3
Lock Sequence
Use the following command sequence to Lock a block.
1. Command sequence: Lock block Command (02h).
2. All blocks default to locked after initial cold reset or warm reset.
3. Partial block lock is not available; Lock block operation is based on all block units.
4. Unlocked blocks can be locked by using the Lock block command, and a block’s lock status can
be changed to unlock or lock-tight using the appropriate software commands.
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NAND Flash Memory Controller
Locked
Figure 19-20. Lock Sequence
19.5.4.4
Unlock Sequence
Use the following command sequence:
1. Start block address + End block address + Unlock Block Command(04h)
2. Unlocked blocks can be programmed or erased
3. An unlocked block’s status can be changed to the locked or lock-tighten state using the appropriate
software commands
4. Only one sequential area can be released to from locked state to unlocked state; Unlocking multiple
areas is not available
Lock-Tighten
Figure 19-21. Unlocked Blocks During Command Sequence
19.5.4.5
Lock-Tight Sequence
Command Sequence, Lock-tight block Command (01h):
1. Lock-tightened blocks offer the user an additional level of write protection beyond that of a regular
lock block. A block that is lock-tightened cannot have its state changed by software and can only
be unlocked by a Cold or Warm reset. Unlocking multiple areas is not available.
2. Only locked blocks can be lock-tighten by lock-tight command. Lock-tighten blocks revert to the
locked state at cold or warm reset.
Lock-Tighten
Legend:
Locked block(s)
Unlocked block(s)
Lock-tighten block(s)
Figure 19-22. Sequential Area Affected by Lock-Tight Command
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NAND Flash Memory Controller
19.6
AHB Bus Operation
The connection of the Host is done through the AHB Interface. This AHB Interface supports Reads and
Write, Burst or Non-Burst operations and 16-bits or 32-bits bus transfers. The bus is Little Endian byte
ordering only.
An operation on the AHB bus starts the NON-SEQ command on the htrans signals, and with the hsel signal
of the NFC. It ends on the next IDLE or NON-SEQ command on the htrans signals.
There are a different number of Wait States on the AHB bus depending on the current operation, and the
previous operation. Table 19-24 shows the number of wait states on the AHB bus for Non-Burst operations
or the first operation of a Burst.
Table 19-24. Single (Non-Burst) AHB Operation Wait-States on AHB Bus
IDLE
AHB IDLE
(No AHB
Operations)
WRITE
WRITE of 16 or 32 bits
(AHB Word or Half Word)
to REGISTER or MEMORY
Region
READ
READ of 16 or 32 bits
(AHB Word or Half Word)
to REGISTER or MEMORY
Region
WR16
WRITE of 16 bits (AHB Half Word) to
REGISTER or MEMORY region
2
2
2
WR32
WRITE of 32 bits (AHB Half Word) to
REGISTER or MEMORY region
5
5
5
R16-REG
READ of 16 bits (AHB Half Word) to
REGISTER region
5
5
6
R16-MEM
READ of 16 bits (AHB Half Word) to
MEMORY region
7
7
8
R32-REG
READ of 32bits (AHB Word) to
REGISTER region
6
6
7
R32-MEM
READ of 32 bits (AHB Word) to
MEMORY region
8
8
9
Previous Operation
Next Operation
An extension to burst operation would be as follows:
1. For WRITE BURST the first cycle would be according to Table 16-25 and the rest would take 0
wait states For example Writing a burst of Four 32 bit words to the Internal Memory buffer (no
matter what was the previous operation) would result in 2-1-1-1 access cycles.
2. For READ BURST the first cycle would be according to Table 19-24 and the rest of the burst
would be ZERO wait states. For example Reading a burst of Four 32 bit words from Internal
Memory buffer that occurs after any NFC read would result in 3-1-1-1 access cycles.
Table 19-25 summarizes the number of Wait States for all kinds of burst modes available in the NFC
module. It is divided into the latency of the first cycle, and the latency of the remaining cycles.
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19-35
NAND Flash Memory Controller
Table 19-25. Burst Wait-States on AHB Bus
LATENCY
(Number of Wait States for the
First Cycle in Burst)
BURST W.S.
Number of Wait States for the Second
and Above Cycles in Burst
WR16
WRITE of 16 bits (AHB Half Word) to
REGISTER or MEMORY region
Always 2 W.S.
2 W.S.
WR32
WRITE of 32 bits (AHB Half Word) to
REGISTER or MEMORY region
Always 5 W.S.
5 W.S.
R16
READ of 16 bits (AHB Half Word) to
REGISTER or MEMORY region
4, 5, 6 or 7 W.S.
(According to Table 19-24)
No W.S.
(Zero W.S.)
R32
READ of 16 bits (AHB Half Word) to
REGISTER or MEMORY region
5, 6, 7 or 8 W.S.
(According to Table 19-24)
1 W.S.
(One W.S.)
AHB Bus Operation
Table 19-26 shows example memory parts that are suitable for use with the corresponding configurations.
These bits are configured by hardware when NAND Flash boot is selected and configured by host software
otherwise.
Table 19-26. Settings for Samsung Flash Memory
NFC_FMS
NF_16BIT_SEL
Memory Device
0
0
SAMSUNG K9F5608
(32M × 8-bit)
Page size is 528 bytes (512 bytes + 16 bits)
0
1
SAMSUNG K9F5616
(16M × 16-bit)
Page size is 528 bytes (512 bytes + 16 bits)
1
0
SAMSUNG K9F1G08
(128M × 8-bit)
Page size is 2112 bytes (2048 bytes + 64 bits)
1
1
SAMSUNG K9F1G16
(64M × 16-bit)
Page size is 2112 bytes (2048 bytes + 64 bits)
i.MX21 Reference Manual, Rev. 3
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Freescale Semiconductor
Chapter 20
External Interface Module (EIM)
20.1
Overview
The External Interface Module (EIM) handles the interface to devices external to the i.MX21 chip,
including generation of chip selects for external peripherals and memory, and provides the following
features:
• Six chip selects for external devices: CS[1:0], covering a range of 64 Mbytes, and CS[5:2],
covering a range of 16 MBytes each
• Selectable protection for each chip select
• Reset programmable data port size for CS[0] depending on BOOT mode
• Programmable data port size for each chip select
• Address suppression during burst mode operations
• Synchronous burst mode support for burst flash devices
• Synchronous burst mode support for PSRAM (Pseudo-SRAM) devices
• Programmable wait-state generator for each chip select
• Supports positive edge triggered DTACK signal operations for CS[5]
• Supports level sensitive DTACK signal operations for CS[3:0] and CS[5]
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
20-1
External Interface Module (EIM)
External
External
Interface
Module
ahb_hrdata[31:0]
Address & Data
hresp0
Post AHB
Mux
hready
signals
hsel_eim_reg
hwdata[31:0]
hwrite
htrans[1:0]
Chip Select
Control
haddr[31:0]
AHB Inputs
eim_data_out[31:0]
hsize[1:0]
eim_hresp0
eim_hrdata[31:0]
eim Outputs
to AHB
eim_hready
A[25:0]
D[31:0]
eim_data_in[31:0]
eim_dtack
DTACK
eim_cs[5:0]
CS[5:0]
eim_oe
eim_eb[3:0]
eim_rw
hrpot1
Burst Control
Internal Bus (AHB)
hsel_eim_cs[5:0]
eim_addr[25:0]
eim_bclk
eim_lba
eim_ecb
OE
EB[3:0]
RW
BCLK
(burst clock)
LBA
ECB
bigend
eim_boot_dsz[2:0]
I/O Pad
Driver Control
hreset
System Inputs/Outputs
hclk
Clocks
hclk
eim_wr_oe[3:0]
(internal signal)
Figure 20-1. EIM Block Diagram
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20-2
Freescale Semiconductor
External Interface Module (EIM)
20.2
EIM I/O Signals
The EIM I/O signals provide communication and control pathways between external devices and the
i.MX21 chip. A summary of the I/O signal pins is provided in Table 20-1. Each signal is described in the
following sections.
Table 20-1. EIM I/O Signal Descriptions
Direction
Pin name
D[31:0]
Description
Bidirectional External Data bus
A[25:0]
Output
External Address bus outputs
CS[5:0]
Output
Active Low External Chip Selects
EB[3:0]
Output
Active low external Enable Byte signals. EB[0] controls D[31:24] data bits, EB[1] controls
D[23:16] data bits, EB[2] controls D[15:8] data bits, EB[3] controls D[7:0] data bits.
OE
Output
Active Low output enable for external data bus
BCLK (burst clock)
Output
Clock used for external synchronous memories
LBA
Output
Active low Load Burst Address indicates to external synchronous memories that
Address is valid for latching
RW
Output
Indicates if external access is a read (high) or write (low) cycle
ECB
Input
Input signal that identifies when to end an external access, active low
DTACK
Input
This signal is the external input data acknowledge signal multiplexed with CS[4].
20.2.1
Chip Select Signals
The CS[5] output signals are active-low and are asserted based on a decode of the internal address bus bits
[31:24] of the accessed address. Table 20-2 specifies the address range for each Chip Select output
provided by external address decoder.
Table 20-2. Chip Select Address Range (Provided by External Address Decoder)
[x]
CSEN Bit in CS[x]
Lower Register
Internal Address [31:24]
Decode
Chip Select
Active
Memory map Address range
all
cleared
–
inactive
–
0
set
0xC8, 0xC9,0xCA,0xCB
CS[0]
0xC8000000–0xCBFFFFFF
1
set
0xCC,0xCD,0xCE,0xCF
CS[1]
0xCC000000–0xCFFFFFFF
2
set
0xD0
CS[2]
0xD0000000–0xD0FFFFFF
3
set
0xD1
CS[3]
0xD1000000–0xD1FFFFFF
4
set
0xD2
CS[4]
0xD2000000–0xD2FFFFFF
5
set
0xD3
CS[5]
0xD3000000–0xD3FFFFFF
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Freescale Semiconductor
20-3
External Interface Module (EIM)
20.2.2
Burst Mode Signals
The burst mode signals for the EIM module are described in Table 20-3.
Table 20-3. Burst Mode Signal Description
Description
Name
BCLK
Burst Clock—The BCLK output signal is used to clock external burst capable devices to synchronize the loading
(burst clock) and incrementing of addresses, and delivery of burst read data to the EIM. This signal is derived from the internal
system clock HCLK and its behavior is affected by the BCM bit in the EIM configuration register and the SYNC,
BCD, PME, and BCS bits in the EIM chip select control registers. Note, this signal is not to be confused with the
internal ARM CPU BCLK signal. The BCLK signal name used throughout this chapter is referenced only to the
external burst clock.
LBA
Load Burst Address—The LBA active-low output signal is asserted during burst mode accesses to cause the
external burst capable device to load a new starting burst address. Assertion of LBA indicates that a valid address
is present on the address bus. Its behavior is affected by the SYNC, BCD, PME and BCS bits in the EIM chip select
control registers.
ECB
End Current Burst—The ECB active-low input signal is asserted by external burst capable devices to indicate
the end of the current (continuous) burst sequence. Following assertion, the EIM terminates the current burst
sequence and initiates a new one.
For synchronous PSRAM devices, this input may be used as the WAIT input during burst transfers. In this case,
the memory device asserts this signal to insert wait states during refresh collisions or during a row boundary
crossing. For this scenario the EIM “WAIT” mode should be used (EW=1) in order not to terminate the burst. The
EIM then samples the data once WAIT is negated. The EW bit, which selects the EIM WAIT mode operation for
the ECB signal, can be found in the EIM chip select control register.
For burst memories the ECB/WAIT output should be configured to change one cycle before data is ready (before
delay).
20.3
Pin Configuration for EIM
Table 20-4 lists the pins used for the EIM module. Some of them are multiplexed with other functions on
the device.
Table 20-4. Pin Configuration
Internal EIM signals
i.MX21 Pins
Setting
eim_data_out[31:0]
D [31:0]
Dynamically multiplexed
eim_data_in[31:0]
D [31:0]
Dynamically multiplexed
eim_addr[24:0]
A [24:0]
Some of the Address signals are multiplexed with the NFIO
signals (refer to the Signal and Pins Chapter)
eim_cs[5]
CS5
Multiplexed with GPIO PF22
eim_cs[4]
CS4
Multiplexed with GPIO PF21 and DTACK
eim_cs[3]
CS3
Multiplexed with CSD1
eim_cs[2]
CS2
Multiplexed with CSD0
eim_cs[1]
CS1
Not multiplexed
eim_cs[0]
CS0
Not multiplexed
eim_eb[3:0]
EB3 … EB0
Dynamically multiplexed with the SDRAM DQM signals
i.MX21 Reference Manual, Rev. 3
20-4
Freescale Semiconductor
External Interface Module (EIM)
Table 20-4. Pin Configuration (continued)
Internal EIM signals
i.MX21 Pins
Setting
eim_oe
OE
Not Multiplexed
eim_dtack
CS4
System GPIO muxing (multiplexed with DTACK)
eim_bclk
BCLK
Not multiplexed
eim_lba
LBA
Not multiplexed
eim_rw
RW
Not multiplexed
eim_ecb
ECB
Not multiplexed
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
20-5
External Interface Module (EIM)
20.4
Typical EIM System Connections
Figure 20-2 shows an example of a typical set of EIM interfaces to external memory and peripherals.
Figure 20-3 on page 20-7 shows the EIM interface to two supported external burst flash devices.
A [25:0]
A [16:0]
CS2
EB0
CS
EB [0]
OE
D [31:0]
EB [0]
EB [1]
CS1
RW
RW
D [31:16]
A [19:1]
EB [2]
OE
D [15:0]
A0
CS3
UBS
LBS
D [7:0]
SRAM
64Kx16
WE
OE
Data [15:0]
Address [18:0]
WE
NOR
FLASH
512Kx16
OE
Data [15:0]
RS
E
RW
ECB
Address [15:0]
CS
CS0
EB2
Data [7:0]
CS
OE
i.MX21
EIM
WE
SRAM
128Kx8
OE
D [31:24]
A [16:1]
EB1
Address [16:0]
ACIA
R/W
Data [7:0]
LBA
BCLK
A0
CS5
E
RW
CS4
RS
D [7:0]
LCD
CONTROL
R/W
Data [7:0]
EB3
Figure 20-2. Example of EIM Interface to Memory and Peripherals
i.MX21 Reference Manual, Rev. 3
20-6
Freescale Semiconductor
External Interface Module (EIM)
A [20:1]
A [24:0]
Address [19:0]
ADV#
LBA
EB [0]
CS0
EB0
CE#
WE#
OE
OE
BCLK
OE#
NOR
BURST
FLASH
CLK
WAIT#
ECB
D [31:16]
D [31:0]
DQ [15:0]
1Mx16
i.MX21
EIM
A [20:1]
Address [19:0]
ADV#
CS1
CE#
EB1
WE#
CS3
OE
OE#
CS4
BCLK
CLK
CS5
NOR
BURST
FLASH
WAIT#
D [31:16]
DQ [15:0]
1Mx16
A [16:1]
EB2
EB [2]
EB3
EB [3]
CS2
Address [15:0]
UBS
LBS
CS
RW
RW
WE
OE
OE
D [15:1]
SRAM
64Kx16
Data [15:0]
Figure 20-3. Example for EIM Interface to Burst Memory
20.5
20.5.1
EIM Functionality
Configurable Bus Sizing
The EIM supports byte, halfword, and word operands, allowing access to 8-bit ports, 16-bit ports, and
32-bit ports. It does not support misaligned transfers.
The port size is programmable via the DSZ bits in the corresponding chip select control register. In
addition, the portion of the data bus used for transfer to or from an 8-bit port or 16-bit port is programmable
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
20-7
External Interface Module (EIM)
via the same bits. An 8-bit port can reside on external data bus bits D[31:24], D[23:16], D[15:8] or D[7:0].
A 16-bit port can reside on external data bus bits D[31:16] or D[15:0].
Word access to or from an 8-bit port requires four external bus cycles to complete the transfer. Word access
to or from a 16-bit port requires two external bus cycles to complete the transfer. Halfword access to or
from an 8-bit port requires two external bus cycles to complete the transfer. In the case of a multi-cycle
transfer, the lower two address bits [1:0] are incremented appropriately.
The EIM has a data multiplexer that routes the four bytes of the AHB interface data bus to the required
positions to allow proper interfacing to memory and peripherals.
NOTE
The EIM does not support 8-bit or 16-bit internal AHB burst accesses. The
ARM core only issues 32-bit word burst accesses, but the bus masters such
as the DMA are also capable of 8-bit and 16-bit internal burst transfers.
When programming these bus masters, the user must configure them to
access the EIM using 32-bit burst transfers. Hence, internal byte and
half-word burst transfers to/from the EIM are not allowed.
20.5.2
Burst Mode Operation
When there are sequential accesses, the EIM attempts to burst read data from as many sequential address
locations as possible, limited only by the length of the burst flash internal page buffer, or the non-sequential
nature of the ARM926EJ-S processor code or data stream. The EIM only displays the first address
accessed in a burst sequence unless the page mode emulation (PME) bit is set. To enable burst accesses
from the EIM, the SYNC bit must be set, along with proper settings for BCD, DOL, WSC, and BCS.
For the first access in a burst sequence, the EIM asserts load burst address (LBA), causing the external
burst device to latch the starting burst address, and then toggles the burst clock (BCLK) for a predefined
number of cycles in order to latch the first unit of data. Subsequently read data units are burst from the
external device in fewer clock cycles, realizing an overall increase in bus bandwidth.
Burst accesses is terminated by the EIM when it detects that the next ARM926EJ-S processor access is not
sequential, or when the external burst device needs additional cycles to retrieve the next requested memory
location. In the latter case, the burst flash device provides an ECB signal to the EIM whenever it either
terminates the on-going burst sequence and initiates a new (long first access) burst sequence or waits for
ECB negation (see EW bit description for the details).
The synchronous mode is also used for burst PSRAM, which supports burst writes. For this, the PSR bit
needs to be set in the chip select control register.
20.5.3
Burst Clock Divisor
In some cases it is necessary to slow the external bus in relation to the internal bus to allow accesses to
burst devices that have a maximum operating frequency that is lower than the operating frequency of the
internal AHB bus. The internal bus frequency (HCLK) can be divided by 2, 3, or 4 for presentation on the
external bus in burst mode operation. In fact, when connecting to a 32-bit data bus burst flash, the
minimum value BCD should be set for is divide by two. This is due to the one wait state latency required
i.MX21 Reference Manual, Rev. 3
20-8
Freescale Semiconductor
External Interface Module (EIM)
by the EIM to capture data and present it to the AHB bus. For a 16-bit data bus, BCD can be set to divide
by one since it takes two external data fetches to form one 32-bit data word. In either case, check the burst
flash data sheet to ensure the burst clock does not violate the burst flash maximum burst clock timing.
Programming the BCD bits to various values (see Table 20-6) affects two signals on the external bus, LBA
(load burst address) and BCLK (burst clock). The LBA signal is asserted immediately and remains
asserted until the first falling edge of the BCLK signal. The BCLK signal runs with a 50% duty cycle until
a non-sequential internal request is received or an external ECB signal is recognized.
When programming these bits, ensure that the WSC and DOL bit fields are coordinated to provide the
desired external bus waveforms. For example, when the BCD bits are programmed to 01, the DOL bits
should be programmed to 0001, 0011, 0101, … When the BCD bits are programmed to 10, the DOL should
be programmed to 0010, 0101, 1000, …
20.5.4
Burst Clock Start
To allow greater flexibility in achieving the minimum number of wait states on bursted accesses, the user
can determine when they want the BCLK (burst clock) to start toggling. This allows the BCLK to be
skewed from the point of data capture on the system clock by any number of system clock phases. Use
caution when setting these bits in conjunction with the BCD, WSC, and DOL bits. See the external timing
diagrams for some examples of how to use the BCS, BCD, WSC, and DOL bits together.
20.5.5
Page Mode Emulation
Setting the PME bit along with SYNC bit causes the EIM to perform bursted accesses by emulating page
mode operation. The LBA signal remains asserted for the entire access, the burst clock does not send a
signal, and the external address asserts for each access made. The initial access timing is dictated by the
WSC bits and the page mode access timing is dictated by the DOL bits.
The EIM can take advantage of improved page timing for sequential accesses only. Accesses that are on
the page but are not sequential in nature have their timing dictated by the WSC bits. The page size can be
set via the PSZ bits to 4, 8, 16, or 32 words (the word size is determined by the data width of the external
memory, such as determined by the DSZ bits).
20.5.6
PSRAM mode operation
A control bit PSR is provided to enable PSRAM operation. Bit CRE and an unused address line A[25] can
be used to drive the control register enable (CRE) PSRAM input for PSRAM configuration registers
loading. The PSRAM CRE signal should be connected to A[25] for this purpose and the bit CRE set when
programming the PSRAM control registers.
20.5.7
Mixed Burst Mode Support
To provide mixed sequential/wrap accesses of different lengths, the EIM tests the internal AHB hburst
signal to indicate the burst access type and size and will generate additional LBA signals whenever there
appears to be an unequal wrap condition. The chip select control register bits PSZ and WRAP should be
programmed to notify EIM about the current memory wrap condition for proper external address
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
20-9
External Interface Module (EIM)
generation. In other words, the EIM chip select control register bits PSZ and WRAP should be
programmed to match the external device’s memory wrap condition. In the case where the wrap
boundaries in both the PSZ and AHB access do not match, the EIM puts the address of the next access on
the address bus and generates LBA signal. Burst accesses from AHB must be word width. The EIM does
not support burst accesses of byte or half-word width.
20.5.8
DTACK Signal Operation
When enabled, the DTACK input signal is used to externally terminate a data transfer. For DTACK
enabled operations, a bus time-out monitor generates a bus error when an external bus cycle is not
terminated by the DTACK input signal after 1024 HCLK clock cycles have elapsed, where HCLK is the
internal system clock driven from the PLL module. For a 133MHz HCLK setting, this time equates to
7.7us. Refer to the PLL Control Chapter for more information on how to generate different HCLK
frequencies.
There are two modes of operation for the DTACK input signal: rising edge detection or level sensitive
detection with a programmable insensitivity time. DTACK is only used during external asynchronous data
transfers, thus the SYNC bit in the chip select control registers must be cleared.
During edge detection mode, the EIM will terminate an external data transfer following the detection of
the DTACK signal’s rising edge, so long as it occurs within the 1024 HCLK cycle time. Edge detection
mode is used for devices that follow the PCMCIA standard. Note that DTACK rising edge detection mode
can only be used for CS[5] operations. To configure CS[5] for DTACK rising edge detection, the following
bits must be programmed in the Chip Select 5 Control Register and EIM Configuration Register:
• WSC bit field set to 0x3F and CSA (or CSN) set to 1 or greater in the Chip Select 5 Control
Register
• AGE bit set in the EIM Configuration Register
Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements
of the external device. The requirement of setting CSA or CSN is needed to allow the EIM to wait for the
rising edge of DTACK during back-to-back external transfers, such as during DMA transfers or an internal
32-bit access through an external 16-bit data port.
During level sensitive detection, the EIM will first hold off sampling the DTACK signal for at least 2
HCLK cycles, and up to 5 HCLK cycles as programmed by the DCT bits in the Chip Select Control
Register. After this insensitivity time, the EIM will sample DTACK and if it detects that DTACK is logic
high, it will continue the data transfer at the programmed number of wait states. However, if the EIM
detects that DTACK is logic low, it will wait until DTACK goes to logic high to continue the access, so
long as this occurs within the 1024 HCLK cycle time. If at anytime during an external data transfer
DTACK goes to logic low, the EIM will wait until DTACK returns to logic high to resume the data transfer.
Level detection is often used for asynchronous devices such graphic controller chips. Level detection may
be used with any chip select except CS[4] as it is multiplexed with the DTACK signal. To configure a chip
select for DTACK level sensitive detection, the following bits must be programmed in the Chip Select
Control Register and EIM Configuration Register:
• EW bit set, WSC set to > 1, and CSN set to < 3 in the Chip Select Control Register
i.MX21 Reference Manual, Rev. 3
20-10
Freescale Semiconductor
External Interface Module (EIM)
•
•
BCD/DCT set to desired “insensitivity time” in the Chip Select Control Register. The “insensitivity
time” is dictated by the external device’s timing requirements.
AGE bit cleared in the EIM Configuration Register
Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements
of the external device.
20.5.9
Error Conditions
The following conditions cause an error condition to be asserted to the ARM926EJ-S processor:
• Access to a disabled chip select (access to a mapped chip select address space where the CSEN bit
in the corresponding chip select control register is clear)
• Write access to a write-protected chip select address space (the WP bit in the corresponding chip
select control register is set)
• User access to a supervisor-protected chip select address space (the SP bit in the corresponding
chip select control register is set)
• User read or write access to a chip select control register or the EIM configuration register
• Byte or halfword access to a chip select control register or the EIM configuration register
• DTACK acknowledge is absent for more then 1024 HCLK clock cycles.
20.6
Programming Model
The EIM module includes thirteen user-accessible 32-bit registers. There is a common register called the
EIM Configuration Register that contains control bits that configure the EIM for certain operation modes.
The other twelve registers are pairs of control registers for each chip select. This registers are accessible
only in supervisor mode with word (32-bit) reads and writes.
Decoding is provided by external address decoder, so shadowing can occur with these registers. The user
should not attempt to address these registers at any other address location other than those listed in
Table 20-5.
Table 20-5. EIM Module Register Summary (Provided by External Address Decoder)
Description
Name
Address
Chip Select 0 Upper Control Register
CS0U
0xDF001000
Chip Select 0 Lower Control Register
CS0L
0xDF001004
Chip Select 1 Upper Control Register
CS1U
0xDF001008
Chip Select 1 Lower Control Register
CS1L
0xDF00100C
Chip Select 2 Upper Control Register
CS2U
0xDF001010
Chip Select 2 Lower Control Register
CS2L
0xDF001014
Chip Select 3 Upper Control Register
CS3U
0xDF001018
Chip Select 3 Lower Control Register
CS3L
0xDF00101C
Chip Select 4 Upper Control Register
CS4U
0xDF001020
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
20-11
External Interface Module (EIM)
Table 20-5. EIM Module Register Summary (Provided by External Address Decoder) (continued)
20.6.1
Description
Name
Address
Chip Select 4 Lower Control Register
CS4L
0xDF001024
Chip Select 5 Upper Control Register
CS5U
0xDF001028
Chip Select 5 Lower Control Register
CS5L
0xDF00102C
EIM Configuration Register
EIM_CNF
0xDF001030
Chip Select 0 Control Registers
The layout of the Chip Select 0 control registers are slightly different from the other Chip Select control
registers because it reset state depends on the internal eim_boot_dsz[2:0] input, which is derived from the
external BOOT[3:0] settings.
The 64 bits of control are divided into two registers, Chip Select 0 Upper Control Register and Chip Select
0 Lower Control Register.
• Bits [63:32] are located in Chip Select 0 Upper Control Register.
• Bits [31:0] are located in Chip Select 0 Lower Control Register.
20.6.1.1
Chip Select 0 Upper Control Register
Chip Select 0 Upper Control Register1
CS0U
BIT
TYPE
60
59
58
57
56
55
63
62
61
SP
WP
BCD/DCT
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
38
37
36
35
34
33
32
BCS/RWA
54
Addr
0xDF001000
PSZ
53
52
51
PME SYNC
50
49
48
DOL/RWN
RESET
0x0000
BIT
47
46
45
44
43
CNC
TYPE
42
41
40
WSC
39
EW
WWS
EDC
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
RESET
0x3E00
1—For
bit descriptions, see Table 20-6.
i.MX21 Reference Manual, Rev. 3
20-12
Freescale Semiconductor
External Interface Module (EIM)
20.6.1.2
Chip Select 0 Lower Control Register
Chip Select 0 Lower Control Register1
CS0L
BIT
31
30
29
28
27
26
OEA
TYPE
25
24
23
22
OEN
Addr
0xDF001004
21
20
19
18
WEA
17
16
WEN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x2000
BIT
15
14
13
12
CSA
TYPE
11
10
EBC
9
8
7
DSZ
CSN
PSR
CRE WRAP CSEN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
1
*
*
*
0
0
0
0
0
0
0
1
RESET
0x0801
1—For
bit descriptions, see Table 20-6.
*—Configurable on reset, depends on BOOTMODE signals setting.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
20-13
External Interface Module (EIM)
20.6.2
Chip Select 1 through Chip Select 5 Control Registers
The layout of the control registers for Chip Selects 1 through 5 are identical.
The 64 bits of control per chip select are divided into an Upper and a Lower register.
• Bits [63:32] are located in Chip Select x Upper Control Register.
• Bits [31:0] are located in Chip Select x Lower Control Register.
20.6.2.1
Chip Select 1 through Chip Select 5 Upper Control Registers
Chip Select 1 Upper Control Register1
Chip Select 2 Upper Control Register1
Chip Select 3 Upper Control Register1
Chip Select 4 Upper Control Register1
Chip Select 5 Upper Control Register1
CS1U
CS2U
CS3U
CS4U
CS5U
BIT
TYPE
60
59
58
57
56
55
63
62
61
SP
WP
BCD/DCT
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
38
37
36
35
34
33
32
BCS/RWA
54
0xDF001008
0xDF001010
0xDF001018
0xDF001020
0xDF001028
PSZ
53
52
51
PME SYNC
50
49
48
DOL/RWN
RESET
0x0000
BIT
47
46
45
44
43
CNC
TYPE
42
41
40
WSC
39
EW
WWS
EDC
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
1—For
bit descriptions, see Table 20-6.
i.MX21 Reference Manual, Rev. 3
20-14
Freescale Semiconductor
External Interface Module (EIM)
20.6.2.2
Chip Select 1 through Chip Select 5 Lower Control Registers
Chip Select 1 Lower Control Register1
Chip Select 2 Lower Control Register1
Chip Select 3 Lower Control Register1
Chip Select 4 Lower Control Register1
Chip Select 5 Lower Control Register1
CS1L
CS2L
CS3L
CS4L
CS5L
BIT
31
30
29
28
27
26
OEA
TYPE
25
24
23
22
OEN
0xDF00100C
0xDF001014
0xDF00101C
0xDF001024
0xDF00102C
21
20
19
18
WEA
17
16
WEN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
CSA
TYPE
11
10
EBC
9
8
7
DSZ
CSN
PSR
CRE WRAP CSEN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0800
1—For
bit descriptions, see Table 20-6.
Table 20-6. Chip Select Control Registers Description
Name
Description
Settings
SP
Bit 63
Supervisor Protect—Prevents accesses to the address
range defined by the corresponding chip select when the
access is attempted in the User mode of ARM9 core
operation.
SP is cleared by a hardware reset.
0 = User mode accesses are allowed in the range of
chip select
1 = User mode accesses are prohibited; attempts to
access an address mapped by this chip select in
User mode results in a error respond on the
AHB and no assertion of the chip select output
WP
Bit 62
Write Protect—Prevents writes to the address range
defined by the corresponding chip select.
WP is cleared by a hardware reset.
0 = Writes are allowed in the range of chip select
1 = Writes are prohibited; attempts to write to an
address mapped by this chip select result in a
error respond on the AHB and no assertion of
the chip select output
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
20-15
External Interface Module (EIM)
Table 20-6. Chip Select Control Registers Description (continued)
Name
BCD/DCT
Bits 61–60
BCS/RWA
Bits 59–56
PSZ
Bits 55–54
Description
Burst Clock Divisor/ DTACK Check Time—
SYNC = 1 (BCD):
Contains the value used to program the burst clock divisor.
See Section 20.5.3, “Burst Clock Divisor,” for more
information on the burst clock divisors.
SYNC = 0 (DCT):
Contains the value used to program the DTACK
“insensitivity” capture time (number of HCLK cycles the
EIM holds off sampling the DTACK signal) when EW = 1,
when level sensitive DTACK has been enabled. The DCT
setting determines the number of HCLK cycles between
the CS assertion and the first sampling of the DTACK
signal by the EIM. A setting of “00” dictates a minimum
HCLK time of 2 HCLK cycles.
BCD/DCT is cleared by a hardware reset.
Burst Clock Start / Read/Write Assertion —
If SYNC = 1 it determines the number of half cycles (HCLK
cycles) after LBA assertion before the first rising edge of
burst clock (BCLK) is seen and is controlled by the BCS bit
field. A value of 0 results in a half clock delay, not an
immediate assertion. When the BCM bit is set (BCM = 1)
in the EIM configuration register, this overrides the BCS
bits.
If SYNC = 0 this bit field determines when RW is asserted
during write cycles and is controlled by the RWA bit field.
BCS/RWA is cleared by a hardware reset.
Note: If RWA=0 and RWN is set to any value greater than
or equal to 1, then the RW signal will assert one half HCLK
cycle after start of access (as if RWA were set to 1).
Programming RWA to a value other than zero in this
condition will follow the settings indicated in the bit settings
description.
Page Size—Indicates the number of words (where “word”
is defined by the port size or DSZ bits) in a page in memory.
This ensures that the EIM does not burst pass a page
boundary when the PME bit is set (along with SYNC=1 to
enable page mode).
When PME = 0:
If WRAP = 1 the PSZ bits notify the EIM about the current
memory word burst length (where “word” is defined by the
port size or DSZ bits) and where to “wrap” in case of an
unaligned access.
If WRAP = 0, the PSZ bits simply notify the EIM the current
memory word burst length.
In either case, when SYNC = 1 and PME = 0, a PSZ setting
of ‘11’ indicates a continuous burst.
PSZ is cleared by a hardware reset.
Settings
SYNC = 1 (BCD):
00 = Divisor is 1
01 = Divisor is 2
10 = Divisor is 3
11 = Divisor is 4
SYNC = 0 (DCT):
00 = 2 HCLK cycles between the CS assertion and
the first sampling of the DTACK signal
01 = 3 HCLK cycles between the CS assertion and
the first sampling of the DTACK signal
10 = 4 HCLK cycles between the CS assertion and
the first sampling of the DTACK signal
11 = 5 HCLK cycles between the CS assertion and
the first sampling of the DTACK signal
SYNC = 1 (BCS):
0000 = 1 half HCLK cycle before burst clock (BCLK)
0001 = 2 half HCLK cycles before BCLK
...
1111 = 16 half HCLK cycles before BCLK
SYNC = 0 (RWA):
0000 = RW asserts 0 half HCLK cycles after start of
external access
0001 = RW asserts 1 half HCLK cycle after start of
external access
...
1111 = RW asserts 15 half HCLK cycles after start of
external access
Note: The RW assertion time (as affected by RWA,
RWN, and WSC bits) must be programmed to be
greater than or equal to one HCLK cycle.
00 = 4 words in a page
01 = 8 words in a page
10 = 16 words in a page
11 = 32 words in a page
i.MX21 Reference Manual, Rev. 3
20-16
Freescale Semiconductor
External Interface Module (EIM)
Table 20-6. Chip Select Control Registers Description (continued)
Name
Description
Settings
PME
Bit 53
Page Mode Emulation—Enables/Disables page mode
0 = Disables page mode emulation
emulation in burst mode (SYNC=1). When PME is set, the 1 = Enables page mode emulation
external address asserts for each piece of data requested.
Additionally, the LBA and BCLK signals behave as they do
when an asynchronous access is performed.
PME is cleared by a hardware reset.
SYNC
Bit 52
Synchronous Burst Mode Enable—Enables/Disables
0 = Disables synchronous burst mode
synchronous burst mode. When enabled, the EIM is
1 = Enables synchronous burst mode
capable of interfacing to burstable flash devices through
additional burst control signals: BCLK, LBA, and ECB. The
sequencing of these additional I/Os is controlled by other
EIM configuration register bit settings as defined below.
SYNC is cleared by a hardware reset.
DOL/RWN
Bits 51–48
Data Output Length / Read/Write Negation—if SYNC =
1 it specifies the expected number of system clock cycles
(HCLK) required for burst read data to be valid on the data
bus before it is latched by the EIM. As system clock
frequencies increase, it may become necessary to delay
sampling the data for multiple system clock periods in order
to meet burst flash max frequency specifications and/or
EIM data setup time requirements. If SYNC = 0 this bit field
determines when RW is negated (deasserted) during a
write cycle. DOL has no effect on EIM data latching when
SYNC = 0.
DOL/RWN is cleared by a hardware reset.
SYNC = 1 (DOL):
0000 = 1 system clock HCLK delay
0001 = 2 system clock HCLK delay
0010 = 3 system clock HCLK delay
...
1111 = 16 system clock HCLK delay
SYNC = 0 (RWN):
0000 = RW deasserts 0 half HCLK clocks before end
of external access
0001 = RW deasserts 1 half HCLK clock before end
of external access
...
1111 = RW deasserts 15 half HCLK clocks before
end of external access
Note: The RW assertion time (as affected by RWA,
RWN, and WSC bits) must be programmed to be
greater than or equal to one HCLK cycle.
CNC
Bits 47–46
Chip Select Negation Clock Cycles—Specifies the
minimum number of HCLK clock cycles a chip select must
remain negated (deasserted) after it is negated.
CNC has no effect on write accesses when any CSA or
CSN bit is set. CNC is cleared by a hardware reset.
00 = Minimum Negation is 0 clock cycles
01 = Minimum Negation is 1 clock cycle
10 = Minimum Negation is 2 clock cycles
11 = Minimum Negation is 3 clock cycles
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
20-17
External Interface Module (EIM)
Table 20-6. Chip Select Control Registers Description (continued)
Name
Description
Settings
WSC
Bits 45–40
Wait State Control—
See Table 20-7
For SYNC = 0:
WSC programs the number of wait-states for an access to
the external device connected to the chip select.
Table 20-7 shows the encoding of this field. When WWS is
cleared, setting:
WSC = 000000 results in 2 clock transfers
WSC = 000001 results in 2 clock transfers
WSC = 001110 results in 15 clock transfers
WSC = 111110 results in 63 clock transfers
WSC = 111111 is not available (reserved) for CS0, CS1,
CS2, CS3 and CS4, but it is available (the external DTACK)
for CS5.
For SYNC = 1:
WSC programs the number of system clock cycles
required for the initial access of a burst sequence initiated
by the EIM to an external burst device. See Table 20-7 and
to the EIM synchronous burst read timing diagrams for
further detail.
WSC is set to 111110 by a hardware reset for CS0.
WSC is cleared by a hardware reset for CS1–CS5.
For SYNC=0, and for CS5:
A WSC setting of 0x3F in conjunction with the AGE bit set
to 1 in the EIM Configuration Register will enable CS5 for
DTACK rising edge triggered operation.
Note: WSC bits should be configured to more than one
wait states.
EW
Bit 39
ECB/WAIT—determines how the EIM supports the ECB
input. There are two modes:
For SYNC = 1:
ECB mode (EW=0): if ECB (End Current Burst) goes to low
state in the middle of access then the EIM starts a new
access by asserting the current AHB address to ADDR
pins and along with an LBA assertion.
WAIT mode (EW=1): if ECB goes to low state in the middle
of access then the EIM will wait until ECB/WAIT goes high
to continue current access.
For SYNC = 0:
Setting EW while SYNC = 0 will enable the chip select for
DTACK level sensitive operation. In addition, the AGE bit in
the EIM Configuration Register must be cleared and the
BCD/DCT bits set to the desired insensitivity time.
EW is cleared by a hardware reset.
WWS
Bits 38–36
SYNC = 1:
0 = ECB mode
1 = WAIT mode
SYNC = 0:
0 = DTACK level sensitive operation disabled
1 = DTACK level sensitive operation enabled
Write Wait State—Determines whether additional
See Table 20-7
wait-states are required for write cycles. This is useful for
writing to memories that require additional data setup time.
WWS is cleared by a hardware reset.
i.MX21 Reference Manual, Rev. 3
20-18
Freescale Semiconductor
External Interface Module (EIM)
Table 20-6. Chip Select Control Registers Description (continued)
Name
Description
Settings
EDC
Bits 35–32
Extra Dead Cycles—Determines whether idle HCLK
cycles are inserted after a read cycle for back-to-back
external transfers to eliminate data bus contention. This is
useful for slow memory and peripherals that use long CS
or OE to output data three-state times. Idle cycles are not
inserted for back-to-back external reads from the same
chip select.
EDC is cleared by a hardware reset.
0000 = 0 Idle Cycles Inserted
0001 = 1 Idle Cycle Inserted
...
1111 = 15 Idle Cycles Inserted
OEA
Bits 31–28
OE Assert—Determines when OE is asserted during read
cycles.
For SYNC = 0:
OEA determines the number of half HCLK clocks before
OE asserts during a read cycle. A setting of 0 causes OE
to assert when the address is placed on the external bus,
a setting of 1 causes OE to assert one half HCLK cycles
after the address is placed on the external bus, etc.
For SYNC = 1:
After the initial burst access, OE is asserted continuously
for subsequent burst accesses, and is not affected by OEA
(see burst read timing diagrams for more detail). The
behavior of OE on the initial burst access is the same as
when SYNC = 0.
When the EBC bit in the corresponding register is clear, the
EB [3:0] outputs are similarly affected.
OEA does not affect the cycle length.
OEA is cleared by a hardware reset.
0000 = OE asserts 0 half clocks (HCLK) after start of
external access
0001 = OE asserts 1 half clock (HCLK) after start of
external access
...
1111 = OE asserts 15 half clocks (HCLK) after start
of external access
OE Negate—Determines when OE is negated
(deasserted) during a read cycle. Setting the SYNC bit
(SYNC = 1) overrides OEN and OE deasserts at the end of
a read access and no sooner. When EBC in the
corresponding register is clear, the EB [3:0] outputs are
similarly affected.
OEN does not affect the cycle length.
OEN is cleared by a hardware reset.
0000 = OE deasserts 0 half clocks (HCLK) before
end of access
0001 = OE deasserts 1 half clock (HCLK) before end
of access
...
1111 = OE deasserts 15 half clocks (HCLK) before
end of access
OEN
Bits 27–24
Note: The OE assertion time (as affected by OEA,
OEN, and WSC bits) must be programmed to be
greater than or equal to one HCLK cycle.
Note: The OE assertion time (as affected by OEA,
OEN, and WSC bits) must be programmed to be
greater than or equal to one HCLK cycle.
WEA
Bits 23–20
EB [3:0] Assert—Determines when EB [3:0] is asserted
during write cycles. This is useful to meet data setup time
requirements for slow memories.
WEA does not affect the cycle length.
WEA is cleared by a hardware reset.
0000 = EB[3:0] asserts 0 half clocks (HCLK) after
start of external access
0001 = EB[3:0] asserts 1 half clock (HCLK) after start
of external access
...
1111 = EB[3:0] asserts 15 half clocks (HCLK) after
start of external access
Note: The EB[3:0] assertion time (as affected by
WEA, WEN, and WSC bits) must be programmed to
be greater than or equal to one HCLK cycle.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
20-19
External Interface Module (EIM)
Table 20-6. Chip Select Control Registers Description (continued)
Name
WEN
Bits 19–16
Description
Settings
EB [3:0] Negate During Write—Determines when EB
[3:0] outputs are negated (deasserted) during a write cycle.
This is useful to meet data hold time requirements for slow
memories.
WEN does not affect the cycle length.
WEN is cleared by a hardware reset.
0000 = EB[3:0] deasserts 0 half clocks (HCLK)
before end of access
0001 = EB[3:0] deasserts 1 half clock (HCLK) before
end of access
...
1111 = EB[3:0] deasserts 15 half clocks (HCLK)
before end of access
Note: The EB[3:0] assertion time (as affected by
WEA, WEN, and WSC bits) must be programmed to
be greater than or equal to one HCLK cycle.
CSA
Bits 15–12
Chip Select Assert—Determines when chip select is
asserted or devices that require additional address setup
time. CSA affects only external writes, and is ignored on
external reads.
However, during DTACK rising edge triggered operations
(CS5 only), CSA affects both read and write cycles.
CSA does not affect the cycle length.
CSA is cleared by a hardware reset.
0000 = CS asserts 0 HCLK clocks after start of
external access
0001 = CS asserts 1 HCLK clocks after start of
external access
...
1111 = CS asserts 15 HCLK clocks after start of
external access
EBC
Bit 11
Enable Byte Control—Indicates the access types that
assert the enable byte outputs (EB [3:0]).
The EBC bits are set by default for all CS0 to CS5
0 = Both read and write accesses assert the EB [3:0]
outputs, thus configuring the access as byte
enables.
1 = Only write accesses assert the EB [3:0] outputs,
thus configuring the access as byte write
enables; the EB [3:0] outputs are configured as
byte write enables for accesses to dual x16 or
quad x8 memories.
DSZ
Bits 10–8
Data Port Size—Defines the width of the external device’s
data port size.
At hardware reset, the value of DSZ is cleared for
CS1– CS5. For CS0, DSZ is mapped based on the value
of the BOOT[3:0] signals.
000 = 8-bit port, resides on D [31:24] pins
001 = 8-bit port, resides on D [23:16] pins
010 = 8-bit port, resides on D [15:8] pins
011 = 8-bit port, resides on D [7:0] pins
100 = 16-bit port, resides on D [31:16] pins
101 = 16-bit port, resides on D [15:0] pins
110 = 32-bit port
111 = Reserved
CSN
Bits 7–4
Chip Select Negate—Determines when chip select is
negated for devices that require additional address/data
hold times. CSN affects only external writes, and is ignored
on external reads. CSN has no affect when synchronous
mode is enabled (SYNC=1).
During DTACK rising edge triggered operations (CS5 only),
CSN affects both read and write cycles.
CSN does not affect the cycle length. CSN is cleared by a
hardware reset.
0000 = CS deasserts 0 HCLK clocks before end of
external access
0001 = CS deasserts 1 HCLK clocks before end of
external access
...
1111 = CS deasserts 15 HCLK clocks before end of
external access
i.MX21 Reference Manual, Rev. 3
20-20
Freescale Semiconductor
External Interface Module (EIM)
Table 20-6. Chip Select Control Registers Description (continued)
Name
Description
Settings
PSR
Bit 3
PSRAM Enable—Enables the PSRAM mode that allows 0 = PSRAM mode is disabled
burst writes and refresh wait. If SYNC = 0, asynchronous 1 = PSRAM mode is enabled
mode is used. If SYNC = 1, synchronous mode is used. In
PSRAM mode the ECB signal is continually sampled after
wait count programmed in the BCD/DCT expires (EIM
waits until the ECB negation to continue accesses). The
WRAP bit during writes is automatically masked
(according the first generation CellularRAMTM
Specification, WRAP is supported only for read accesses)
and wait state on read is automatically incremented. PSR
also needs to be set when programming the PSRAM
control register.
PSR is cleared by a hardware reset.
CRE
Bit 2
Control Register Enable—Indicates the CRE memory pin 0 = CRE pin (A[25]) low
state while writing to CS address space, for PSRAM control 1 = CRE pin (A[25]) high
register write. This bit will be driven on pin ADDR[25]. For
CRE to drive ADDR[25], the PSR bit also needs to be set.
CRE is cleared by a hardware reset.
WRAP
Bit 1
0 = memory is in linear addressing mode
WRAP memory mode—Indicates to the EIM that the
memory is in wrap mode. The size of wrap should be set in 1 = memory is in wrap mode, PSZ indicates memory
burst length
PSZ bits. In case wrap boundaries in both the PSZ and
AHB access do not match, the EIM issues the next address
on address bus and generates LBA signal.
WRAP is cleared by a hardware reset.
CSEN
Bit 0
Chip Select Enable—Controls the operation of the chip
0 = Chip select function is disabled; attempts to
select pin. CSEN in the CS0 control register is set at reset
access an address mapped by this chip select
to allow CS0 to select from an external boot ROM or NOR
results in an error respond on the AHB and no
Flash.
assertion of the chip select output.
CSEN is set by a hardware reset for CS0.
1 = Chip select is enabled, and is asserted when
CSEN is cleared by a hardware reset for CS1–CS5.
presented with a valid AHB access.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
20-21
External Interface Module (EIM)
Table 20-7. Chip Select Wait State and Burst Delay Encoding
Number of Wait-States
WWS = 0
WSC [5:0]
WWS = 1
WWS = 7
Read
Access
Write
Access
Read
Access
Write
Access
Read
Access
Write
Access
000000
1
1
1
1
1
7
000001
1
1
1
2
1
8
000010
2
2
2
3
2
9
000011
3
3
3
4
3
10
110111
55
55
55
56
55
62
111000
56
56
56
57
56
63
111001
57
57
57
58
57
63
111010
58
58
58
59
58
63
111011
59
59
59
60
59
63
111100
60
60
60
61
60
63
111101
61
61
61
62
61
63
111110
62
62
62
63
62
63
111111
Reserved
or External
DTACK
Reserved
or External
DTACK
Reserved
or External
DTACK
Reserved
or External
DTACK
Reserved
or External
DTACK
Reserved
or External
DTACK
...
Note: WSC = 111111 is not available (reserved) for CS0, CS1, CS2, CS3 and CS4, but it is
available (the external rising edge triggered DTACK) for CS5.
i.MX21 Reference Manual, Rev. 3
20-22
Freescale Semiconductor
External Interface Module (EIM)
20.6.3
EIM Configuration Register
The EIM Configuration Register contains the bit that controls the operation of the burst clock.
EIM_CNF
EIM Configuration Register
0xDF001030
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
BCM
AGE
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 20-8. EIM Configuration Register Description
Name
Description
Settings
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–3
BCM
Bit 2
Burst Clock Mode—Selects the burst clock mode of
operation.
BCM is cleared by a hardware reset.
AGE
Bit 1
0 = The burst clock runs only when accessing a chip
select range with the SYNC bit set; when the burst
clock is not running it remains in a logic 0 state; when
the burst clock is running it is configured by the BCD
and BCS bits in the chip select control register
1 = The burst clock runs only during chip select accesses.
The frequency of the burst clock is also affected by
the setting of the BCD bits in the chip select control
register.
Acknowledge Glue Enable—Is used to enable / disable 0 = Disable glue logic (for DTACK level sensitive
operations)
glue logic between external DTACK and internal control
logic. This glue logic is used to synchronize with the rising 1 = Enable glue logic (for DTACK rising edge triggered
edge of the external DTACK. Hence, when using DTACK
operations)
for rising edge triggered operations, the AGE bit should
be set to enable the glue logic. For DTACK level sensitive
operations, the AGE bit should be cleared.
AGE is cleared by a hardware reset.
Reserved Reserved—These bits are reserved and should read 0.
Bit 0
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
20-23
External Interface Module (EIM)
i.MX21 Reference Manual, Rev. 3
20-24
Freescale Semiconductor
Chapter 21
Bus Master Interface (BMI)
This chapter describes the unique interface requirement for the Bus Master Interface (BMI) module. The
BMI module enables high speed connection between i.MX21 and the alternate bus master devices in the
system.
The BMI provides support for the following functions:
• 8- or 16-bit data bus mode
• External bus master read or write to the CPU using memory access timing
• CPU reads or writes to the external bus slave using memory access timing
• ATI graphic chip burst read/write accesses timing
• High communication speed
• DMA support
21.1
BMI Block Diagram
Figure 21-1 shows the BMI block diagram.
D_EN
BMI_D[15:0]
DIN[15:0]
16 × 32 RxFIFO
DOUT[15:0]
AHB bus
WRITE_OUT_B
WRITE_EN
BMI_READ_B
BMI_READ_REQ
READ_B
Status reg
Control reg
BMI_INT_B
READ_REQ
Interrupt Logic
BMI_RXF_FULL
RXF_FULL
BMI_WAIT
WAIT_B
AHB I/F
Logic
CLK/CS_EN
WRITE_IN_B
BMI_WRITE
16 × 32 TxFIFO
CLK/CS_OUT
Control
BMI_CLK_CS
I/O mux
CLK/CS_IN
BMI_DMA_REQ[1:0]
Figure 21-1. BMI Block Diagram
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
21-1
Bus Master Interface (BMI)
21.2
•
•
•
•
•
•
•
•
•
•
•
21.3
Signal Description
BMI_D[15:0]—BMI data bus, bus width can be 8- to 16-bit selectable.
BMI_READ_REQ—Inform external bus master that data is ready for a read operation. This signal
is active when the data in the TXFIFO is larger or equal to the data transfer size of a single external
BMI access.
BMI_CLK/CS—When the BMI is connecting to an ATI graphic chip, this is MMDCLK, which is
used to clock in/out data to/from the data FIFO. When the BMI is connecting to external bus
master, this becomes a chip select signal. This clock frequency must be less than hclk/3. Please
refer to the respective timing diagrams and tables to get the reasonable frequency.
BMI_WRITE—Active low bidirectional signal to control data direction. When BMI is a slave, this
is input to BMI to determine read or write to BMI data FIFO. When BMI is a bus master, this is an
output write enable signal to external slave device.
BMI_READ—Active low output signal to enable external slave data output. this signal is not used
and is driven high when BMI is a slave.
BMI_RXF_FULL—Active high output signal to reflects if RxFIFO reaches water mark value.
BMI_WAIT—Active low signal to wait for data ready (read cycle) or accepted (write_cycle). This
signal is only used when the BMI is in master mode and the WAIT bit is set. This signal is
connected with the PA29 AOUT.
AHB bus—Internal ARM AHB bus.
BMI_INT_B—Active low interrupt signal to AIPI interrupt controller. This signal is asserted when
there is an Interrupt event and is negated when there is no more interrupt event is pending.
BMI_DMA_REQ[1]—Active low DMA request signal to DMA controller. This signal is asserted
whenever the RxF_FULL status bit is set, and it is negated when RxF_FULL condition is no longer
true.
BMI_DMA_REQ[0]—Active low DMA request signal to DMA controller. This signal is asserted
whenever the TxF_EMPTY status bit is set, and it is negated when TxF_EMPTY condition is no
longer true.
Pin Configuration for BMI
Table 21-1 lists the pin used for the BMI module. These pins are multiplexed with other functions on the
device and must be configured for BMI operation.
Table 21-1. BMI Pin Configuration
Pin
Setting
Configuration Procedure
BMI_D[15:0]
Alternate Function of GPIO 1. Clear bit 21–6of the Port A GPIO In Use Register (GIUS_A)
PortA[21:6]
2. Set bit 21–6 of the Port A General Purpose Register (GPR_A)
BMI_CLK_CS
Alternate Function of GPIO 1. Clear bit 5 of the Port A GPIO In Use Register (GIUS_A)
PortA[5]
2. Set bit 5 of the Port A General Purpose Register (GPR_A)
BMI_WRITE
Alternate Function of GPIO 1. Clear bit 23 of the Port A GPIO In Use Register (GIUS_A)
PortA[23]
2. Set bit 23 of the Port A General Purpose Register (GPR_A)
i.MX21 Reference Manual, Rev. 3
21-2
Freescale Semiconductor
Bus Master Interface (BMI)
Table 21-1. BMI Pin Configuration (continued)
Pin
Setting
Configuration Procedure
BMI_READ
Alternate Function of GPIO 1. Clear bit 30of the Port A GPIO In Use Register (GIUS_A)
PortA[30]
2. Set bit 30 of the Port A General Purpose Register (GPR_A)
BMI_READ_REQ
Alternate Function of GPIO 1. Clear bit 22 of the Port A GPIO In Use Register (GIUS_A)
PortA[22]
2. Set bit 22 of the Port A General Purpose Register (GPR_A)
BMI_RXF_FULL
Alternate Function of GPIO 1. Clear bit 29 of the Port A GPIO In Use Register (GIUS_A)
PortA[29]
2. Set bit 29 of the Port A General Purpose Register (GPR_A)
BMI_WAIT
AOUT of GPIO PortA[29]
21.4
1. Set bit 29 of the Port A GPIO In Use Register (GIUS_A)
2. Clear bit27-26 of the PortA GPIO Input Configuration Register
A2(ICONFA2)
Programming Model
The BMI module includes five user-accessible 32-bit registers. Only the BMI TxFIFO register (BMITXD)
can a byte or halfword write, all other access is always word size. Table 21-2 summarizes these registers
and their addresses.
Table 21-2. System Control Module Register Summary
Description
Name
Address
BMI Control Register 1
BMICTLR1
0xA000_0000
BMI Control Register 2
BMICTLR2
0xA000_0004
BMI Status Register
BMISTR
0xA000_0008
BMI RxFIFO
BMIRXD
0xA000_000C
BMI TxFIFO
BMITXD
0xA000_0010
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
21-3
Bus Master Interface (BMI)
21.4.1
BMI Control Register 1
This 32-bit register controls how the BMI operates. The bit assignments for the register are shown in the
following register display. The settings for the bits in the register are listed in Table 21-3.
BMICTLR1
BIT
BMI Control Register 1
31
30
29
28
WAIT
TYPE
27
26
25
WS
24
Addr
0xA0000000
23
DIV
22
21
20
19
TxF_Water_Mark
18
17
16
RxF_Water_Mark
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
7
6
5
4
3
2
1
0
RESET
BIT
15
DATA_LATCH
MMD_CLKOUT
READ
MASTER_SEL
RxF_OV_INT_EN
BRDY_INT_EN
WRDY_INT_EN
RxFF_INT_EN
TxFE_INT_EN
MMD_MODE_SEL
CLK_CS_POL
READ_REQ_POL
16BIT_SEL
RxFIFO_CLR
TxFIFO_CLR
BMI_EN
0x000F
14
13
12
11
10
9
8
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 21-3. BMI Control Register 1 Description
Name
Description
Settings
Reserved
Bits 31–30
Reserved—These data bits are reserved and should always read 0.
WAIT
Bit 29
WAIT—This bit is only used in master mode. When this bit is cleared, the 0 = ignore BMI_WAIT signal
CS cycle is terminated by Wait State (WS) control bits. When this bit is 1 = detect BMI_WAIT signal
set, the CS cycle is terminated upon sampling a logic high WAIT in signal
WS
Bits 28–26
Wait State—In master mode the number of wait states can be inserted
to the BMI read/write cycle. The WS is inserted to both chip low for
longer access time and chip select high for longer idle time between
read/write cycles
000 = 0 WS
001 = 1WS
010 = 2WS
…
111 = 7 WS
DIV
Bits 25–24
Int_Clk Divider—In master mode HCLK is divide by DIV to generate
Int_Clk. This clock is used to clock all output signals for the read/write
cycles.When MMD_MODE_SEL bit and MMD_CLKOUT bit both set,
HCLK is divided by DIV to generate BMI_CLK_CS.
00 = divide by 2
01 = divide by 4
10 = divide by 8
11 = divide by 16
TxF_Water_Mark
Bits 23–20
TxFIFO Interrupt and DMA Request Water Mark—Sets the interrupt
and DMA request trigger level. When the number of empty slots is equal
or greater than the water mark value, TxF_EMPTY status bit is set and
DMA request signal is driving to active level. BMI interrupt is generated
if TxFE_INT_EN is set.
0000 = Tx_EMPTY status bit is
always set
0001 = At least 1 empty slot
0010 = At least 2 empty slots
...
1111 = At least 15 empty slots
i.MX21 Reference Manual, Rev. 3
21-4
Freescale Semiconductor
Bus Master Interface (BMI)
Table 21-3. BMI Control Register 1 Description (continued)
Name
Description
Settings
RxF_Water_Mark
Bits 19–16
RxFIFO Interrupt and DMA Request Water Mark—Sets the interrupt 0000 = RxFIFO is full
and DMA request trigger level. When the number of data words (32-bit) 0001 = At least 1 data word
in the RxFIFO is equal or greater than the water mark value, RxF_FULL
ready
status bit is set and DMA request signal is driving to active level. BMI
0010 = At least 2 data words
interrupt is generated if RxFF_INT_EN is set.
ready
...
1111 = At least 15 data words
ready
DATA_LATCH
Bit 15
BMI Latch Data Edge—This bit is only useful when the MMD_CLKOUT 0 = BMI latch data on the falling
edge
bit set to 1. When ATI MMD devices write to BMI and BMI drives clock,
the BMI can latch data at both edge according to this bits. If the BMI latch 1 = BMI latch data on the next
rising edge
data on the next rising edge, the last data is latched by internal clock.
MMD_CLKOUT
Bit 14
0 = MMD drives clock
BMI Clock Direction—This bit is only useful when the
1 = BMI drives clock
MMD_MODE_SEL bit set to 1. When this bit is cleared, both
BMI_WRITE and BMI_CLK/CS are input signals to BMI driving by ATI
MMD device. When this bit is set, the BMI_CLK/CS is output signals
driven by BMI and the BMI_WRITE is input signals to BMI driving by ATI
MMD device.
READ
Bit 13
Force a READ Cycle—When BMI is configured as master mode
0 = No READ cycle or READ
(MASTER_SEL bit is set) or MMD_MODE_SEL bit and MMD_CLKOUT
command is completed.
bit are both set, writing a “1” to this bit will enable BMI to generate a read 1= READ command is ongoing
cycle. The COUNT bits in the BMICTLR2 control the read count. This bit
or pending.
is clear automatically when the read cycle is completed. This bit is
ignored in all other mode. User can read this bit to see if the read cycle
is completed before issuing the next WRITE or READ command.
MASTER_SEL
Bit 12
0 = Slave mode
Master Mode Select—Configure the BMI to master mode or slave
mode. This bit is clear automatically to select slave mode when BMI is 1 = Master mode
connecting to ATI graphic chip (MMD mode). This bit is also used to
control the direction of BMI_WRITE signals. It is output in master mode
and is input in slave mode.
RxF_OV_INT_EN
Bit 11
RxFIFO Over Flow Interrupt Enable—Enables data over flow interrupt. 0 = Disable
1 = Enable
BRDY_INT_EN
Bit 10
Data Byte Ready Interrupt Enable—Enables data byte interrupt.
0 = Disable
Interrupt is generated when there is at least one data byte in the RxFIFO. 1 = Enable
WRDY_INT_EN
Bit 9
Data Word Ready Interrupt Enable—Enables data word (32-bit)
interrupt. Interrupt is generated when there is at least one data word in
the RxFIFO.
0 = Disable
1 = Enable
RxFF_INT_EN
Bit 8
RxFIFO Full Interrupt Enable—Set this bit to enable RxFIFO full
interrupt if RxFIFO reaches or greater than water mark value.
0 = Disable
1 = Enable
TxFE_INT_EN
Bit 7
TxFIFO Empty Interrupt Enable—Set this bit to enable TxFIFO empty 0 = Disable
Interrupt when the number of empty slots in TxFIFO reaches or greater 1 = Enable
than water mark value.
MMD_MODE_SEL ATI MMD Interface Timing Select—Set this bit to select the ATI graphic 0 = Memory interface timing
Bit 6
chip interface timing mode.
mode
1 = ATI graphic chip interface
timing mode
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
21-5
Bus Master Interface (BMI)
Table 21-3. BMI Control Register 1 Description (continued)
Name
CLK_CS_POL
Bit 5
Description
Settings
Clock/Chip Select Polarity—Set this bit to invert the clock/chip select
polarity.
0 = Not inverted
1 = Inverted
READ_REQ_POL Read Request Output Polarity—Set this bit to invert the READ_REQ
Bit 4
signal output polarity.
0 = Not inverted
1 = Inverted
16BIT_SEL
Bit 3
16-Bit Data Bus Select—Set this bit to select 16-bit data bus width.
0 = 8-bit
1 = 16-bit
RxFIFO_CLR
Bit 2
Clear RxFIFO—Write a 1 to this bit to clear RxFIFO. This bit is always
read 0.
0 = No action
1 = Clear RxFIFO (This bit is
clear automatically after the
write cycle)
TxFIFO_CLR
Bit 1
Clear TxFIFO—Write a 1 to this bit to clear TxFIFO. This bit is always
read 0. When the TxFIFO is written to some data to be transfer, BMI
asserts READ_REQ to signal external bus master to read data from
BMI. If there is no read operation performed, TxFIFO is never emptied.
A clear TxFIFO will reset the TxFIFO to Empty position.
0 = No action
1 = Clear TxFIFO (This bit is
clear automatically after the
write cycle)
BMI_EN
Bit 0
BMI Module Enable—Set this bit to enable BMI module. The status
register will go to reset value when this bit is cleared.
0 = Disable
1 = Enable
i.MX21 Reference Manual, Rev. 3
21-6
Freescale Semiconductor
Bus Master Interface (BMI)
21.4.2
BMI Control Register 2
The BMI Control Register(BMICTLR2) controls how the BMI operates. The bit assignments for the
register are shown in the following register display. The settings for the bits in the register are listed in
Table 21-4.
BMICTLR2
BMI Control Register 2
Addr
0xA0000004
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
COUNT
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 21-4. BMI Control Register 2 Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
COUNT
Bits 5–0
Read Cycle Count—Reflects number of data the BMI read from the external bus.
It is valid when the BMI is configured as master or MMD_MODE_SEL and
MMD_CLKOUT bits are both set. When a read cycle is issued, this count bits
control how much data the BMI will read from the external bus.
Settings
000000 = read one data
000001 = read two data
000010 = read three data
000011 = read four data
.......
111111 = read 64 data
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
21-7
Bus Master Interface (BMI)
21.4.3
BMI Status Register
The BMI Status Register (BMISR) reflects the BMI status. See Table 21-5 for detailed description of status
bit.
BMISR
BMI Status Register
Addr
0xA0000008
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESE
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
1
0
0x0000
14
13
12
11
10
9
8
7
6
5
4
3
2
TA
RxF_OV
BRDY
WRDY
RxF_FULL
TxF_EMPTY
BCNT
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESE
T
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0x0004
Table 21-5. BMI Status Register Description
Name
Description
Settings
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
TA
Bit 7
Transfer Activity—Reflects if the BMI doing READ or WRITE operation. 0 = No READ or WRITE activity
This bit is used for master mode only.
1 = In READ or WRITE activity
RxF_OV
Bit 6
RxFIFO Over Flow—Reflects if receiving data has ever been over flow. 0 = No data over flow
When there is over flow, the new data is discarded.
1 = At least one data byte lost
BRDY
Bit 5
Data Byte Ready—Reflects if there is any data byte ready in the
0 = No data byte ready
RxFIFO. This bit is used when WRDY is clear and there could be 1,2 or 1 = At least one data byte is ready
3 bytes in the RxFIFO.
WRDY
Bit 4
Data Word Ready—Reflects if there is any complete data word ready in 0 = No data word ready
the RxFIFO.
1 = At least one data word is ready
RxF_FULL
Bit 3
RxFIFO Full—Reflects if RxFIFO reaches the water mark value
0 = Not full
1 = RxFIFO at or over water mark
value
TxF_EMPTY
Bit 2
TxFIFO Empty—Reflects if TxFIFO reaches the water mark value
0 = Not empty
1 = TxFIFO has empty slot equal or
greater than water mark value
BCNT
Bits1–0
Byte Count—Reflects number of data bytes the in the last data word
read. BCNT is updated after each 32-bit read from the RxFIFO. When
WRDY is clear and BRDY is set, CPU or DMA performs a final 32-bit data
read from the RxFIFO, then read this 2 status bits to determine how
many valid data bytes are in the last 32-bit read. If user sets the data
packet to be always word size, BRDY and BCNT are not used.
00 = No valid data in the last read
01 = 1 valid data byte, D[7:0]]
10 = 2 valid data bytes D[15:0]
11 = 3 valid data bytes D[23:0]
i.MX21 Reference Manual, Rev. 3
21-8
Freescale Semiconductor
Bus Master Interface (BMI)
21.4.4
BMI RxFIFO Register
The BMI RxFIFO Register (BMIRXD) contains received data from external bus master. CPU or DMA
data read from this register is always word size regardless number of bytes left in the FIFO.
BMIRXD
BIT
BMI RxFIFO Register
31
30
29
28
27
26
25
24
Addr
0xA000000C
23
22
21
20
19
18
17
16
D[31:16]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
D[15:0]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 21-6. BMI RxFIFO Register Description
Name
Description
D[31:16]
Bits 31–16
Data—Upper half data word.
D[15:0]
Bits 15–0
Data—Lower half data word.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
21-9
Bus Master Interface (BMI)
21.4.5
BMI TxFIFO Register
The BMI TxFIFO Register (BMTXD) is to store data to be sent to external bus devices upon BMI read
access. The DMA or CPU data write to this register can be a byte, haft word, or full word size, but all these
write operation must align to the 0xA0000010 address.
BMITXD
BIT
BMI TxFIFO Register
31
30
29
28
27
26
25
24
23
Addr
0xA0000010
22
21
20
19
18
17
16
D[31:16]
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
D[15:0]
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 21-7. BMI TxFIFO Register Description
Name
Description
D[31:16]
Bits 31–16
Data—Upper half data word.
D[15:0]
Bits 15–0
Data—Lower half data word.
i.MX21 Reference Manual, Rev. 3
21-10
Freescale Semiconductor
Part 5
InterChip Connectivity
Chapter 22, “I2C Module,” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 22-1
Chapter 23, “Configurable Serial Peripheral Interface (CSPI),” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 23-1
Chapter 24, “Synchronous Serial Interface (SSI),” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .page 24-1
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
1
i.MX21 Reference Manual, Rev. 3
2
Freescale Semiconductor
Chapter 22
I2C Module
I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange,
minimizing the interconnection between devices. This bus is suitable for applications requiring occasional
communications over a short distance between many devices. The flexible I2C allows additional devices
to be connected to the bus for expansion and system development.
The I2C operates up to 400 kbps but it depends on the pad loading and timing (for pad requirement details
please refer to Philips I2C Bus Specification, Version 2.1). The I2C system is a true multiple-master bus
including arbitration and collision detection that prevents data corruption if multiple devices attempt to
control the bus simultaneously. This feature supports complex applications with multiprocessor control
and can be used for rapid testing and alignment of end products through external connections to an
assembly-line computer.
The I2C module has the following key features:
• Compatibility with I2C bus standard
• Multiple-master operation
• Software-programmable for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven, byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation/detection
• Repeated START signal generation
• Acknowledge bit generation/detection
• Bus-busy detection
Figure 22-1 is the block diagram of the I2C module.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
22-1
I2C Module
Internal Bus
IRQ
Address
Data
Address Decode
Data MUX
Registers Interface
I2C Frequency
Divider Register
(IFDR)
I2C Control
Register
(I2CR)
I2C Status
Register
(I2SR)
Clock
Control
Start, Stop,
and
Arbitration
Control
I2C Data
I/O Register
(I2DR)
I2C Address
Register
(IADR)
In/Out
Data
Shift
Register
Address
Compare
Input
Sync
SCL
SDA
Figure 22-1. I2C Module Block Diagram
Pull-up
Rp resistors
+Vdd
Rp
SDA (Serial Data line)
SCL (Serial Clock line)
Device2
Device1
ipp_scl_out1
ipp_sda_out1
ipp_scl_out2
ipp_sda_out2
ipp_scl_in1
ipp_sda_in1
ipp_scl_in2
ipp_sda_in2
Figure 22-2. Connection of Devices to I2C Bus
i.MX21 Reference Manual, Rev. 3
22-2
Freescale Semiconductor
I2C Module
I2C System Configuration
22.1
The I2C module uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. For I2C
compliance, all devices connected to these two signals must have open drain or open collector outputs.
(There is no such requirement for inputs.) The logic AND function is exercised on both lines with external
pull-up resistors.
Out of reset, the I2C default is as slave receiver. Thus, when not programmed to be a master or responding
to a slave transmit address, the I2C module should return to the default slave receiver state. See
Section 22.6.1, “Initialization Sequence,” for exceptions.
NOTE
The I C module is designed to be compatible with the Philips I2C bus
protocol. For information on system configuration, protocol, and
restrictions, see The I2C Bus Specification, Version 2.1.
2
I2C Protocol
22.2
The I2C communication protocol consists of six components: START, Data Source/Recipient, Data
Direction, Slave Acknowledge, Data, Data Acknowledge and STOP. These are shown in Figure 22-3 and
described in the text following the figure.
MSB
SCL
SDA
A
1
LSB
2
3
4
5
6
7
8
MSB
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
START
Signal
Calling Address
B
R/W
C
XXX
ACK
Bit
D
LSB
1
2
3
D7
D6 D5
4
5
6
D4
D3
D2 D1
Data Byte
E
7
8
9
D0
No STOP
ACK Signal
Bit
F
Figure 22-3. I2C Standard Communication Protocol
1. START signal—When no other device is bus master (both SCL and SDA lines are at logic high),
a device can initiate communication by sending a START signal (see A in Figure 22-3). A START
signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the
beginning of a data transfer (each data transfer can be several bytes long) and awakens all slaves.
2. Slave address transmission—The master sends the slave address in the first byte after the START
signal (B). After the seven-bit calling address, it sends the R/W bit (C), which tells the slave data
transfer direction.
Each slave must have a unique address. An I2C master must not transmit an address that is the same
as its slave address; it cannot be master and slave at the same time.
The slave whose address matches that sent by the master pulls SDA low at the ninth clock (D) to
return an acknowledge bit.
3. Data transfer—When successful slave addressing is achieved, the data transfer can proceed (E) on
a byte-by-byte basis in the direction specified by the R/W bit sent by the calling master.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
22-3
I2C Module
Data can be changed only while SCL is low and must be held stable while SCL is high, as
Figure 22-3 shows. SCL is pulsed once for each data bit, with the MSB being sent first. The
receiving device must acknowledge each byte by pulling SDA low at the ninth clock; therefore, a
data byte transfer takes nine clock pulses.
If it does not acknowledge the master, the slave receiver must leave SDA high. The master can then
generate a STOP signal to abort the data transfer or generate a START signal (repeated start, shown
in Figure 22-4) to start a new calling sequence.
If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means
end-of-data to the slave. The slave releases SDA for the master to generate a STOP or START
signal.
4. STOP signal The master can terminate communication by generating a STOP signal to free the bus.
A STOP signal is defined as a low-to-high transition of SDA while SCL is at logical high (F). Note
that a master can generate a STOP even if the slave has made an acknowledgment, at which point
the slave must release the bus.
5. Instead of signalling a STOP, the master can repeat the START signal, followed by a calling
command, (A in Figure 22-4). A repeated START occurs when a START signal is generated
without first generating a STOP signal to end the communication. The master uses a repeated
START to communicate with another slave or with the same slave in a different mode
(transmit/receive mode) without releasing the bus.
MSB
SCL
SDA
1
LSB
2
3
4
5
6
7
8
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
START
Signal
Calling Address
LSB
MSB
9
R/W ACK
Bit
1
XX
2
3
4
5
6
7
8
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Repeated
START
Signal A
New Calling Address
Stop
R/W No
ACK
Bit
STOP
Signal
Figure 22-4. Repeated START
22.2.1
Arbitration Procedure
If multiple devices simultaneously request the bus, the bus clock is determined by a synchronization
procedure in which the low period equals the longest clock-low period among the devices and the high
period equals the shortest. A data arbitration procedure determines the relative priority of competing
devices. A device loses arbitration if it sends logic high while another sends logic low; it immediately
switches to slave-receive mode and stops driving SDA. In this case, the transition from master to slave
mode does not generate a STOP condition. Meanwhile, hardware sets I2SR[IAL] to indicate loss of
arbitration.
22.2.2
Clock Synchronization
Because wire-AND logic is used, a high-to-low transition on SCL affects devices connected to the bus.
Devices start counting their low period when the master drives SCL low. When a device clock goes low,
it holds SCL low until the clock high state is reached. However, the low-to-high change in this device clock
i.MX21 Reference Manual, Rev. 3
22-4
Freescale Semiconductor
I2C Module
may not change the state of SCL if another device clock is still in its low period. Therefore, the device with
the longest low period holds the synchronized clock SCL low. Devices with shorter low periods enter a
high wait state during this time (See Figure 22-5). When all devices involved have counted off their low
period, the synchronized clock SCL is released and pulled high. There is then no difference between device
clocks and the state of SCL, so all of the devices start counting their high periods. The first device to
complete its high period pulls SCL low again.
Wait
Start counting high period
SCL1
SCL2
SCL
Internal Counter Reset
Figure 22-5. Synchronized Clock SCL
22.2.3
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfers. Slave devices can hold
SCL low after completing one byte transfer (9 bits). In such a case, the clock mechanism halts the bus clock
and forces the master clock into wait states until the slave releases SCL.
22.2.4
Clock Stretching
Slaves can use the clock synchronization mechanism to slow down the transfer bit rate. After the master
has driven SCL low, the slave can drive SCL low for the required period and then release it. If the slave
SCL low period is longer than the master SCL low period, the resulting SCL bus signal low period is
stretched.
22.3
Pin Configuration for I2C
Two pins are required for I2C.
• I2C_CLK Bidirectional clock Pin
• I2C_DATA Bi-directional Data Pin
22.4
IP Bus Accesses
I2C module expects all reads and writes to be aligned to 32-bit boundary.
Only lower 1 byte [7:0] is written for write accesses. If write access is for more than lower 1 byte—that is,
16-bit or 32-bit write access, upper bytes [31:24], [23:16], [15:8] will be simply ignored and writes
happens only for the lower one byte [7:0]. Module takes only [7:0] bits of write data bus as input.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
22-5
I2C Module
For reads I2C drives 16-bit data bus as output. For both 8-bit and 16-bit access, it returns lower 1 byte [7:0]
out of respective register and 2nd byte [15:8] is always returned as 0. For a 32-bit read access module
drives lower 16-bits as above and upper bits are not driven from the module.
22.4.1
Generation of Transfer Error on IP Bus
On getting an IP access to an address which is not implemented transfer error is signalled—that is,
ips_xfr_err is generated. Input pin resp_sel provides configuration capability for the generation of this
error. When resp_sel is low only then above error is signalled else no error is signalled.
22.5
Programming Model
Table 22-1 lists the configuration registers used in the I2C interface.
0xBA is the base address of I2C module. For i.MX21, 0xBA=0x10012000.
Table 22-1. I2C Interface Register Summary
Address Offset
[31:24]
[23:16]
[15:8]
[7:0]
0x000
Reserved
I2C address register (IADR)
0x004
Reserved
I2C frequency divider register (IFDR)
0x008
Reserved
I2C control register (I2CR)
0x00C
Reserved
I2C status register (I2SR)
0x010
Reserved
I2C data I/O register (I2DR)
I2C Address Register (IADR)
22.5.1
The IADR holds the address the I2C responds to when addressed as a slave. Note that it is not the address
sent on the bus during the address transfer. The register does not get reset by software reset. Table 22-2
describes IADR fields.
I2C Address Register
IADR
BIT
15
14
13
12
11
10
9
8
7
0xBA+0x000
6
5
4
3
2
1
0
ADR
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 22-2. I2C Address Register Description
Name
Description
Settings
Reserved
Bits 15–8
Reserved—These bits are reserved and should read 0.
ADR
Bits 7–1
Slave Address—Contains the specific slave address to be used by the I2C module. I2C module slave address
Slave mode is the default I2C mode for an address match on the bus.
Reserved
Bit 0
Reserved—This bit is reserved and should read 0.
i.MX21 Reference Manual, Rev. 3
22-6
Freescale Semiconductor
I2C Module
I2C Frequency Divider Register (IFDR)
22.5.2
The IFDR provides a programmable prescaler to configure the clock for bit-rate selection. The register
does not get reset by software reset. Table 22-3 describes IFDR[IC].
I2C Frequency Divider Register
IFDR
BIT
15
14
13
12
11
10
9
8
7
6
$BA+0x004
5
4
3
2
1
0
IC
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 22-3. IFDR Register Description
Name
Description
Settings
Reserved
Bits 15–6
Reserved—These bits are reserved and should read 0.
IC
Bits 5–0
I2C Clock Rate—Pre-scales the clock for bit-rate selection. Due to potentially slow SCL and SDA rise See note.
and fall times, bus signals are sampled at the prescaler frequency. The serial bit clock frequency is equal
to ipg_clk divided by the divider shown below. Note that IC can be changed anywhere in a program.
Note: Software should set the desired frequency divider
IC
Divider
IC
Divider
IC
Divider
IC
Divider
0x00
30
0x10
288
0x20
22
0x30
160
0x01
32
0x11
320
0x21
24
0x31
192
0x02
36
0x12
384
0x22
26
0x32
224
0x03
42
0x13
480
0x23
28
0x33
256
0x04
48
0x14
576
0x24
32
0x34
320
0x05
52
0x15
640
0x25
36
0x35
384
0x06
60
0x16
768
0x26
40
0x36
448
0x07
72
0x17
960
0x27
44
0x37
512
0x08
80
0x18
1152
0x28
48
0x38
640
0x09
88
0x19
1280
0x29
56
0x39
768
0x0A
104
0x1A
1536
0x2A
64
0x3A
896
0x0B
128
0x1B
1920
0x2B
72
0x3B
1024
0x0C
144
0x1C
2304
0x2C
80
0x3C
1280
0x0D
160
0x1D
2560
0x2D
96
0x3D
1536
0x0E
192
0x1E
3072
0x2E
112
0x3E
1792
0x0F
240
0x1F
3840
0x2F
128
0x3F
2048
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
22-7
I2C Module
I2C Control Register (I2CR)
22.5.3
The I2CR is used to enable the I2C module and the I2C interrupt. It also contains bits that govern operation
as a slave or a master. Table 22-4 describes I2CR control register fields.
I2C Control Register
I2CR
BIT
15
14
13
12
11
10
9
8
7
IEN
$BA+0x008
6
5
4
3
2
1
0
IIEN MSTA MTX TXAK RSTA
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 22-4. I2CR Register Description
Name
Description
Settings
Reserved
Bits 15–8
Reserved—These bits are reserved and should read 0.
IEN
Bit 7
I2C Enable—Also controls the software reset of the entire I2C module.
Resetting the bit generates internal reset to the module.
If the module is enabled in the middle of a byte transfer, slave mode
ignores the current bus transfer and starts operating when the next
start condition is detected. Master mode is not aware that the bus is
busy; so initiating a start cycle may corrupt the current bus cycle,
ultimately causing either the current master or the I2C module to lose
arbitration, after which bus operation returns to normal.
Note: IEN bit is not used for gating main clock to the module in i.MX21
0 = The module is disabled, but registers
can still be accessed.
1 = The I2C module is enabled. This bit
must be set before any other I2CR bits have
any effect.
IIEN
Bit 6
I2C Interrupt Enable—This bit enables or disables I2C module
interrupts
0 = I2C module interrupts are disabled, but
currently pending interrupt condition are not
cleared.
1 = I2C module interrupts are enabled. An
I2C interrupt occurs if I2SR[IIF] is also set.
Interrupt remains asserted as long as
IIF[I2SR] and IIEN remains set together.
MSTA
Bit 5
Master/Slave Mode Select—If the master loses arbitration, MSTA is 0 = Slave mode. Changing MSTA from 1 to
cleared without generating a STOP signal.
0 generates a STOP and selects slave
Note: Module clock should be on for writing to MSTA bit.
mode.
1 = Master mode. Changing MSTA from 0 to
1 signals a START on the bus and selects
master mode.
MTX
Bit 4
Transmit/Receive Mode Select—Selects the direction of master and 0 = Receive
slave transfers.
1 = Transmit. When a slave is addressed,
software should set MTX according to
I2SR[SRW]. In master mode, MTX
should be set according to the type of
transfer required. Therefore, for
address cycles, MTX is always 1.
TXAK
Bit 3
0 = An acknowledge signal is sent to the
Transmit Acknowledge Enable—Specifies the value driven onto
bus at the ninth clock bit after receiving
SDA during acknowledge cycles for both master and slave receivers.
one byte of data.
Note: Writing TXAK applies only when the I2C bus is a receiver.
1 = No acknowledge signal response is
sent (that is, acknowledge bit = 1).
i.MX21 Reference Manual, Rev. 3
22-8
Freescale Semiconductor
I2C Module
Table 22-4. I2CR Register Description (continued)
Name
Description
Settings
RSTA
Bit 2
Repeat Start—Always read as 0. Attempting a repeat start without
bus mastership causes loss of arbitration.
Reserved
Bits 1–0
Reserved—These bits are reserved and should read 0.
0 = No repeat start
1 = Generates a repeated START
condition.
I2C Status Register (I2SR)
22.5.4
This I2SR contains bits that indicate transaction direction and status. Table 22-5 describes I2SR fields.
I2C Status Register
I2SR
BIT
15
14
13
12
11
10
9
8
$BA+0x00C
7
6
5
4
3
ICF
IAAS
IBB
IAL
2
1
0
SRW
IIF
RXAK
TYPE
r
r
r
r
r
r
r
r
r
r
r
rw
r
r
rw
r
RESET
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
Table 22-5. I2SR Register Description
Name
Description
Settings
Reserved
Bits 15–8
Reserved—These bits are reserved and should read 0.
ICF
Bit 7
Data Transferring—While one byte of data is
transferred, ICF is cleared.
IAAS
Bit 6
0 = Not addressed.
I2C Addressed as Slave—The CPU is interrupted if
I2CR[IIEN] is set. Next, the CPU must check SRW and 1 = Addressed as a slave. Set when its own address
(IADR) matches the calling address.
set its TX/RX mode accordingly. Writing to I2CR clears
this bit.
IBB
Bit 5
I2C Bus Busy—Indicates the status of the bus.
0 = Bus is idle. If a STOP signal is detected, IBB is
cleared.
1 = Bus is busy. When START is detected, IBB is set.
IAL
Bit 4
Arbitration Lost—
Set by hardware in the following circumstances:
(IAL must be cleared by software by writing zero to it.)
• SDA sampled low when the master drives high during
an address or data-transmit cycle.
• SDA sampled low when the master drives high during
the acknowledge bit of a data-receive cycle.
• For above 2 cases bit is set at the falling edge of 9th
SCL clock during ACK cycle.
• A start cycle is attempted when the bus is busy.
• A repeated start cycle is requested in slave mode.
• A stop condition is detected when the master did not
request it.
Reserved
Bit 3
Reserved—This bit is reserved and should read 0.
0 = Transfer in progress
1 = Transfer complete. Set by the falling edge of the ninth
clock of a byte transfer.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
22-9
I2C Module
Table 22-5. I2SR Register Description (continued)
Name
Description
Settings
SRW
Bit 2
Slave Read/Write—When IAAS is set, SRW indicates 0 = Slave receive, master writing to slave.
the value of the R/W command bit of the calling address 1 = Slave transmit, master reading from slave.
sent from the master. SRW is valid only when a
complete transfer has occurred, no other transfers have
been initiated, and the I2C module is a slave and has an
address match.
IIF
Bit 1
I2C Interrupt— This bit indicates that one of the I2C
interrupts is pending.
RXAK
Bit 0
Received Acknowledge—The value of SDA during the 0 = An acknowledge signal was received after the
acknowledge bit of a bus cycle.
completion of 8-bit data transmission on the bus
1 = No acknowledge signal was detected at the ninth
clock.
Must be cleared by software by writing a zero to it in the
interrupt routine.
0 = No I2C interrupt pending
1 = An interrupt is pending, which causes a processor
interrupt request (if IIEN = 1). Set when one of the
following occurs:
Complete one byte transfer (set at the falling edge of the
ninth clock)
Reception of a calling address that matches its own
specific address in slave-receive mode
Arbitration lost
I2C Data I/O Register (I2DR)
22.5.5
In master-receive mode, reading the I2DR allows a read to occur and initiates next byte data receiving. In
slave mode, the same function is available after it is addressed.
I2C Data Register
I2DR
BIT
15
14
13
12
11
10
9
8
7
Addr
$BA+0x010
6
5
4
3
2
1
0
D
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 22-6. I2C Address Register Description
Name
Description
Reserved
Bits 15–8
Reserved—These bits are reserved and should read 0.
D
Bits 7–0
Data—Holds last data byte received or next data byte to be
transferred
Settings
Write the next data byte to be transmitted
NOTE
Core written value in I2DR can not be read back by Core, only data written
by I2C bus side can be read.
i.MX21 Reference Manual, Rev. 3
22-10
Freescale Semiconductor
I2C Module
22.6
I2C Programming Examples
The following examples show programming for initialization, signalling START, post-transfer software
response, signalling STOP, and generating a repeated START.
22.6.1
Initialization Sequence
Before the interface can transfer serial data, registers must be initialized, as follows:
1. Set IFDR[IC] to obtain SCL frequency from the system bus clock. See Section 22.5.2, “I2C
Frequency Divider Register (IFDR).”
2. Update the IADR to define its slave address.
3. Set I2CR[IEN] to enable the I2C bus interface system.
4. Modify the I2CR to select master/slave mode, transmit/receive mode, and interrupt-enable or not.
NOTE
If IBSR[IBB] is set when the
bus module is enabled, execute the
following code sequence before proceeding with normal initialization code.
This issues a STOP command to the slave device, placing it in idle state as
if it were just power-cycled on.
I2C
22.6.2
Generation of START
After completion of the initialization procedure, serial data can be transmitted by selecting the master
transmitter mode. On a multiple-master bus system, IBSR[IBB] must be tested to determine whether the
serial bus is free. If the bus is free (IBB = 0), the START signal and the first byte (the slave address) can
be sent. The data written to the data register comprises the address of the desired slave and the LSB
indicates the transfer direction.
The free time between a STOP and the next START condition is built into the hardware that generates the
START cycle. Depending on the relative frequencies of the system clock and the SCL period, it may be
necessary to wait until the I2C is busy after writing the calling address to the I2DR before proceeding with
data writing to I2DR.
22.6.3
Post-Transfer Software Response
Sending or receiving a byte sets the I2SR[ICF], which indicates one byte communication is finished.
I2SR[IIF] is also set. An interrupt is generated if the interrupt function is enabled during initialization by
setting I2CR[IIEN]. Software must first clear IIF in the interrupt routine. ICF is cleared either by reading
from I2DR in receive mode or by writing to I2DR in transmit mode.
Software can service the I2C I/O in the main program by monitoring IIF if the interrupt function is
disabled. Polling should monitor IIF rather than ICF because that operation is different when arbitration is
lost.
When an interrupt occurs at the end of the address cycle, the master is always in transmit mode; that is, the
address is sent. If master receive mode is required (I2DR[R/W], I2CR[MTX] should be toggled.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
22-11
I2C Module
During slave-mode address cycles (I2SR[IAAS] = 1), I2SR[SRW] is read to determine the direction of the
next transfer. MTX is programmed accordingly. For slave-mode data cycles (IAAS = 0), SRW is invalid.
MTX should be read to determine the current transfer direction.
22.6.4
Generation of STOP
A data transfer ends when the master signals a STOP, which can occur after all data is sent.
For a master receiver to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last data byte. This is done by setting I2CR[TXAK] before reading the next-to-last
byte. Before the last byte is read, a STOP signal must be generated.
22.6.5
Generation of Repeated START
After the data transfer, if the master still wants the bus, it can signal another START followed by another
slave address without signalling a STOP.
22.6.6
Slave Mode
In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be tested to check
if a calling of its own address has just been received. If IAAS is set, software should set the
transmit/receive mode select bit (I2CR[MTX]) according to the I2SR[SRW]. Writing to the I2CR clears
the IAAS automatically. The only time IAAS is read as set is from the interrupt at the end of the address
cycle where an address match occurred; interrupts resulting from subsequent data transfers will have IAAS
cleared. A data transfer can now be initiated by writing information to I2DR for slave transmits, or read
from I2DR in slave-receive mode. A dummy read of I2DR in slave/receive mode releases SCL, allowing
the master to send data.
In the slave transmitter routine, I2SR[RXAK] must be tested before sending the next byte of data. Setting
RXAK means an end-of-data signal from the master receiver, after which software must switch it from
transmitter to receiver mode. Reading I2DR then releases SCL so that the master can generate a STOP
signal.
22.6.7
Arbitration Lost
If several devices try to engage the bus at the same time, one becomes master. Hardware immediately
switches devices that lose arbitration to slave receive mode. Data output to SDA stops, but SCL is still
generated until the end of the byte during which arbitration is lost. An interrupt occurs at the falling edge
of the ninth clock of this transfer with I2SR[IAL] = 1 and I2CR[MSTA] = 0.
If a device that is not a master tries to transmit or do a START, hardware inhibits the transmission, clears
MSTA without signalling a STOP, generates an interrupt to the CPU, and sets IAL to indicate a failed
attempt to engage the bus. When considering these cases, the slave service routine should first test IAL
and software should clear it if it is set.
i.MX21 Reference Manual, Rev. 3
22-12
Freescale Semiconductor
I2C Module
For Multi master mode, when the I2C module is enabled and when the bus is busy and as assertions begin,
the IAL bit is set for all combinations of SDA and SCL except for SDA=1 and SCA=1 which is same as
bus idle state.
22.6.8
Timing Section
This section shows the timing diagram and description table for devices on the I2C bus.
SDA
5
4
SCL
1
2
3
Figure 22-6. Timing Definition for Devices on the I2C Bus
Table 22-7. I2C Bus Device Timing Definitions1
1
Ref No.
Parameter
Maximum
(w.r.t ipg_clk)
Minimum (w.r.t ipg_clk)
1
Hold time (repeated) START condition
–
4
2
Setup time for STOP condition
–
4
3
Data hold time
(0.27) * Divider
–
4
HIGH of the SCL Period
–
(0.4) * Divider (Master mode)
5
LOW period of the SCL Clock
–
(0.4) * Divider (Master mode)
Refer to Table 22-3 for details for divider values.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
22-13
I2C Module
Clear
IIF
Y
TX
Master
Mode?
N
Y
RX
TX/Rx
?
Arbitration
Lost?
N
Last Byte
Transmitted
?
Clear IAL
Y
N
RXAK= 0
?
Last
Byte to be
Read ?
N
Y
Y
N
Y
N
End of
ADDR Cycle
(Master RX)
?
N
Write Next
Byte to I2DR
Y
Address
Cycle
2nd Last
Byte to be
Read?
(Read) Y
IAAS=1
?
Y
N Data
Cycle
SRW=1
?
Tx/Rx
?
N (WRITE)
N
Set TXAK =1
Y
IAAS=1
?
Generate
STOP Signal
TX
ACK from
Receiver
?
Y
Set TX
Mode
RX
N
Set RX
Mode
Switch to
Rx Mode
Dummy Read
from I2DR
Dummy Read
from I2DR
Switch to
Rx Mode
Dummy Read
from I2DR
Generate
STOP Signal
Read Data
from I2DR
And Store
Read Data
from I2DR
and Store
Tx Next
Byte
Write Data
to I2DR
RTE
Note: In receiver mode, after a byte transfer is complete, it is not required to set TXAK = 1. The value
of TXAK depends on the requirement of the transmitter device.
Figure 22-7. Flow-Chart of Typical I2C Interrupt Routine
i.MX21 Reference Manual, Rev. 3
22-14
Freescale Semiconductor
Chapter 23
Configurable Serial Peripheral Interface (CSPI)
The i.MX21 processor has three Configurable Serial Peripheral Interface (CSPI) modules that allow rapid
data communication with fewer software interrupts than conventional serial communications.
The primary features of the CSPIs include:
• Master/Slave configurable (CSPI1 and CSPI2 only)
• Three available chip-selects (CSPI1 and CSPI2) for master mode operation (SS0–SS2)
• Up to 32-bit programmable data transfer
• 8 × 32-bit FIFO for both Tx and Rx data
CSPI1 and CSPI2 are equipped with two data FIFOs and is a master/slave configurable serial peripheral
interface module, allowing i.MX21 to interface with both external SPI master and slave devices. CSPI3 is
also equipped with two data FIFOs however is only a master.
This section describes how CSPI communicates with external devices. CSPI has one 8 × 32-bit data-in
FIFO and one 8 × 32-bit data-out FIFO. Incorporating the CSPI1_RDY and SS control signals, it enables
fast data communication with fewer software interrupts. Figure 23-1 illustrates the configurable serial
peripheral interface block diagram.
IP BUS INTERFACE
CSPI1_RDY
CLOCK
GENERATOR
CONTROL
3
SS
SCLK
MISO
SHIFT REGISTER
MOSI
Rx FIFO
8 × 32
Tx FIFO
8 × 32
Figure 23-1. Configurable Serial Peripheral Interface Block Diagram
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
23-1
Configurable Serial Peripheral Interface (CSPI)
23.1
Operation
When CSPI is configured as master, SS (output) and CSPI1_RDY (input) signals, are used for data transfer
rate control. The sample period control register can be set if a fixed data transfer rate is required.
When CSPI is configured as slave, SS becomes an input signal and can optionally be used for data latching
and loading to the internal data shift registers, as well as incrementing internal data FIFO pointers.
Figure 23-2 shows the generic CSPI timing.
(POL=1, PHA=1)
SCLK
(POL=1, PHA=0)
SCLK
(POL=0, PHA=1)
SCLK
(POL=0, PHA=0)
SCLK
MISO
Bn Bn-1 Bn-2 Bn-3 ...
...
b1
b0
MOSI
Bn Bn-1 Bn-2 Bn-3 ...
...
b1
b0
Figure 23-2. Generic CSPI Timing
23.1.1
Phase and Polarity Configurations
The serial peripheral interface master uses the SCLK signal to transfer data in and out of the shift register.
Data is clocked using any one of four programmable clock phase and polarity combinations. During Phase
0, Polarity 0 and Phase 1, Polarity 1 operations, output data changes on the falling clock edge and input
data is shifted in on the rising edge. The most-significant bit is output when the CPU loads the transmit
data. During Phase 1, Polarity 0 and Phase 0, Polarity 1 operations, output data changes on the rising edges
of the clock and is shifted in on falling edges. The most-significant bit is output on the first rising SCLK
edge. Polarity inverts SCLK, but does not change the edge-triggered events that are internal to the serial
peripheral interface master. This flexibility allows it to operate with most serial peripheral devices.
23.1.2
Signals
The following signals are used to control the serial peripheral interface master:
• MOSI—Master Out Slave In bidirectional signal, which is TxD output signal from the data shift
register in master mode. In Slave mode it is RxD input to the data shift register.
• MISO—Master In Slave Out bidirectional signal, which is RxD input signal to the data shift
register in master mode. In Slave mode it is TxD output from the data shift register.
• SCLK—CSPI Clock bidirectional signal, which is CSPI clock output in master mode. In slave
mode it is an input CSPI clock signal.
• SS[2:0], Slave Select bidirectional signal, output in master mode, and input in slave mode.
• CSPI1_RDY—This input signal is used only in master mode. It will edge or level trigger a CSPI
burst if used. This signal is only available for CSPI1; it is not present on CSPI2 and CSPI3.
i.MX21 Reference Manual, Rev. 3
23-2
Freescale Semiconductor
Configurable Serial Peripheral Interface (CSPI)
23.2
Programming Model
The following sections provide the register summary and the programming model for the 3 CSPI modules
in the i.MX21. The Register Summary in Table 23-1 lists all registers of the CSPI module by ascending
address. The absolute address of each register is given, as is the value of each bit for reads and writes.
NOTE
CSPI3 is a master mode port only.
.
Table 23-1. CSPI Register Summary
Name
RxDataReg
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
22
21
20
19
18
17
16
6
5
4
3
2
1
0
22
21
20
19
18
17
16
RxData[31:16]
W
0x1000 E000
0x1000 F000 R
0x1001 7000 W
TxData Reg
15
14
13
12
11
10
9
31
30
29
28
27
26
25
R
15
14
13
12
11
10
9
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
R
W
R
W
0x1000 E00C
0x1000 F00C
0x1001 700C
R
Tx Data [31:16]
8
7
Tx Data [15:0]
DataRate[1:0] DR CTL[1:0]
MODE SPIEN
23
BURST
SDHC_
SWAP
SPIEN
7
6
XCH SSPOL SSCTL PHA
5
CS[1:0]
4
POL
3
DataRate[4:2]
2
1
0
BIT COUNT[4:0]
31
30
29
28
27
26
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TEEN
BO
RO
RF
RH
RR
TSHFE
TF
TH
TE
TSHFE
RFEN RHEN RREN
TFEN THEN
EN
W
R
0x1000 E010
0x1000 F010
0x1001 7010
23
W
INTREG
Test Reg
24
R
0x1000 E004
0x1000 F004 R
0x1001 7004 W
0x1000 E008
0x1000 F008
0x1001 7008
7
RxData[15:0]
W
Control Reg
8
17
16
BOEN ROEN
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LBC
INIT
SS_AS
SERT
W
R
W
SSTATUS[3:0]
RXCNT[3:0]
TXCNT[3:0]
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Period Reg W
0x1000 E014
0x1000 F014
0x1001 7014 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
CSRC
WAIT[14:0]
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
23-3
Configurable Serial Peripheral Interface (CSPI)
Table 23-1. CSPI Register Summary (continued)
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMAREG W
0x1000 E018
0x1000 F018
0x1001 7018 R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
TH
DMA
TE
DMA
0
0
0
0
W
THDEN TEDEN RFDEN RHDEN
RF
RH
DMA DMA
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset Reg W
0x1000 E01C
0x1000 F01C
0x1001 701C R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
23.2.1
Rx Data Registers
RxData1
RxData2
RxData3
BIT
START
Addr
0x1000E000
0x1000F000
0x10017000
Receive Data Register 1
Receive Data Register 2
Receive Data Register 3
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RxData
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RxData
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
.
Table 23-2. RxData Register Description
Name
RxData
Bits 31–0
Description
Rx Data—This is a 32-bit read-only register.This holds the top of the 8 × 32 RxFIFO received from external CSPI
device during data transaction.
It is not a valid value if the RR bit in the Interrupt control/status register is cleared.
i.MX21 Reference Manual, Rev. 3
23-4
Freescale Semiconductor
Configurable Serial Peripheral Interface (CSPI)
23.2.2
Tx Data Registers
These 32-bit write only registers form the top of each respective 8 × 32 TxFIFO. Writing to the associated
TxFIFO is permitted as long as it is not full even though XCH bit is set—that is, the user can write to
TXFIFO during CSPI data exchange process. Writes to this register are ignored while the SPIEN bit is
clear.
TxData1
TxData2
TxData3
BIT
Addr
0x1000E004
0x1000F004
0x10017004
Transmit Data Register 1
Transmit Data Register 2
Transmit Data Register 3
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TxData
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TxData
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 23-3. TxData Register Description
Name
TxData
Bits 31–0
Description
Tx Data—This register forms the top CSPI data to be loaded to the 8 × 32 TxFIFO. In master or slave mode,
maximum of 8 data words are loaded. Data write to this register is 32-bit size only. Number of bits to be shifted out
of a 32-bit FIFO element is determined by the BIT COUNT of control register. The unused MSBs are don’t care.
For example, to transfer 10-bit data, 32-bit word is written to this register and the 22 MSBs are don’t care and will
not be shifted out. In slave mode, if no data is loaded to this Tx data FIFO, zeroes are shifted out on the associated
MISO signal.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
23-5
Configurable Serial Peripheral Interface (CSPI)
23.2.3
Control Registers
Each Control Register is 32 bits. The 8 MSBs are reserved and read 0.
ControlReg1
ControlReg2
ControlReg3
BIT
31
Addr
0x1000E008
0x1000F008
0x10017008
Control Register 1
Control Register 2
Control Register 3
30
29 28
27
26
25
24
23
22
21
BURST
SDHC_SPIE
N
SWAP
20
19
18
CS
17
16
DataRate
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13 12
11
10
9
8
7
6
5
4
3
2
1
0
PHA POL
POL
DataRate DR CTL MODE SPIEN XCH SSPOL SSCTL
BIT COUNT
TYPE
rw
rw
rw rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 23-4. Control Register Description
Name
Description
Settings
Reserved
Bits 31–24
Reserved—These bits are reserved and should read 0.
BURST
Bit 23
Burst or Continuous Bit—Used to program the CSPI data in
0 = Idle time inserted between
continuous mode or insertion an idle time between two consecutive data
two transfers
transfers in Master mode.
1 = No idle time between
consecutive data transfers.
SDHC_SPIEN
Bit 22
SDHC SPI Mode Enable Bit—Used to enable the SDHC SPI mode
0= SDHC SPI mode disabled
Note: In SDHC SPI mode the maximum frequency of SCLK is
1= SDHC SPI mode enable
PERCLK2 divided by 3. The setting of the DATARATE[4:0] field to
%00001 is valid for SDHC SPI mode only. With this mode
disabled, the DATARATE field should be set to %00010 or higher.
SWAP
Bit 21
TxFIFO Swap Bit—Used for byte swapping of Tx FIFO and RxFIFO
data
0= No Swapping
1= Swap data
CS
Bits 20–19
Chip Select—In master mode, these two bits select the Slave by
asserting SSn.
• In Master Mode SSn are the outputs. Only the selected SSn signal
is active the remaining 3 signals are tristated
• In Slave mode, these two bits select the master. SSn are the inputs
and only one is asserted at a time.
Note: With CSPI1 and CSPI2, a setting of 11 is reserved (because SS3
isn't available on MX21). For CSPI3, only a setting of 00 is valid
(because it only has one SS). This only works on master mode for
CSPI3.
In Master Mode:
00 = SS0 is asserted
01 = SS1 is asserted
10 = SS2 is asserted
11 = Reserved
In Slave Mode:
SS0,SS1, and SS2 become
inputs
00 = SS0 is selected
01 = SS1 is selected
10 = SS2 is selected
11 = Reserved
i.MX21 Reference Manual, Rev. 3
23-6
Freescale Semiconductor
Configurable Serial Peripheral Interface (CSPI)
Table 23-4. Control Register Description (continued)
Name
Description
Settings
Data Rate
Bits 18–14
Data Rate—This field selects the bit rate (frequency of SPICLK) based
on the division of PERCLK2.
The equations used are:
• For even states other than 0: Divide ratio is 2 × 2n/2
• For odd states: Divide ratio is 3 × 2(n-1)/2
Note: Divide ratio of 3 is valid only if SDHC_SPIEN bit in
CONTROLREG is set.
00000 = Reserved
00001 = Divide by 3
00010 = Divide by 4
00011 = Divide by 6
00100 = Divide by 8
00101 = Divide by 12
00110 = Divide by 16
00111 = Divide by 24
01000 = Divide by 32
01001 = Divide by 48
01010 = Divide by 64
01011 = Divide by 96
01100 = Divide by 128
01101 = Divide by 192
01110 = Divide by 256
01111 = Divide by 384
10000 = Divide by 512
10001 = Divide by 768
10010 = Divide by 1024
All other = Reserved
DRCTL
Bits 13–12
CSPI1_RDY Control—In master mode, these two bits control the
response of the CSPI1_RDY input. Note that RDY is only available for
CSPI1. In slave mode, it is ignored.
00 = Ignored
01 = Falling edge trigger input
10 = Active low level trigger input
11 = Reserved
MODE
Bit 11
CSPI Mode Select—This bit select the Master/Slave mode of CSPI.
CSPI3 only works in master mode.
0 = CSPI is in slave mode
1 = CSPI is in master mode
SPIEN
Bit 10
CSPI Module Enable—This bit enables the serial peripheral interface. 0 = The serial peripheral interface
This bit must be asserted before initiating an exchange. Writing a 0 to
is disabled
this bit will flush the Rx and Tx FIFO.
1 = The serial peripheral interface
However, the PCCR0 register contains the master enable for the CSPI.
is enabled
XCH
Bit 9
1 = Initiates exchange (write) or
Data Exchange—In master mode, writing a 1 to this bit triggers data
busy (read)
exchange. This bit remains set while either the exchange is in progress,
or CSPI is waiting for active CSPI1_RDY input if CSPI1_RDY is enabled 0 = Idle
through DRCTL. This bit is cleared automatically when all data in
TxFIFO and shift register are shifted out. In slave mode this bit must be
clear.
Before setting the XCH bit to initiate an exchange, the user must ensure
that it has been automatically cleared which indicates that the exchange
is over.
SSPOL
Bit 8
SS Polarity Select—In both master and slave mode, this bit selects the 0 = Active low
polarity of SS signal.
1 = Active high
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
23-7
Configurable Serial Peripheral Interface (CSPI)
Table 23-4. Control Register Description (continued)
Name
Description
Settings
SSCTL
Bit 7
SS Wave Form Select—In master mode, this bit select the output
wave form for SS signal.
In slave mode, this bit controls RxFIFO advancement.
In Master Mode
0 = SS stays low between CSPI
bursts
1 = Insert pulse between CSPI
bursts
In Slave Mode
0 = RxFIFO advanced by Bit
Count
1 = RxFIFO advanced by SS
rising edge
PHA
Bit 6
Phase—This bit controls the clock/data phase relationship.
0 = Phase 0 operation
1 = Phase 1 operation
POL
Bit 5
Polarity—This bit controls the polarity of the SPICLK signal.
0 = Active high polarity (0 = idle)
1 = Active low polarity (1 = idle)
BIT COUNT
Bits 4–0
Bit Count—This field selects the length of the transfer. A maximum of
32 bits can be transferred.
In master mode, a 32-bit data word is loaded from TxFIFO to shift
register and only the least n bits (n=BIT COUNT) are shifted out. The
next 32-bit word is then loaded to shift register.
In slave mode and when SSCTL bit is 0 this field controls the number
of bits received as a data word loaded to RxFIFO. When SSCTL bit is 1
and SS rising edge is faster than BIT COUNT is treated, then this field
is don’t care.
00000 = 1-bit transfer
00001 = 2-bit transfer
…
01110 = 15-bit transfer
01111 = 16-bit transfer
…
11110 = 31-bit transfer
11111 = 32-bit transfer
0
SS0
SS_int
SS1
To CSPI
Slave Devices
SS2
The CS bit control is as follows:
00 = SS0 is asserted
01 = SS1 is asserted
CS[1:0]
10 = SS2 is asserted
11 = No slave is selected
Only the selected SSn signal is active the remaining
signals are driven to their inactive value.
Figure 23-3. In Master Mode
i.MX21 Reference Manual, Rev. 3
23-8
Freescale Semiconductor
Configurable Serial Peripheral Interface (CSPI)
SS0
From External
CSPI Master
Devices
SS_int
SS1
SS2
The CS bit control is as follows:
SS0,SS1, and SS2are inputs.
CS[1:0]
00 = SS0 is selected
01 = SS1 is selected
10 = SS2 is selected
11 = Slave select SS0, SS1 and SS2 are al
ignored
Figure 23-4. In Slave Mode
23.2.4
Interrupt Control and Status Register
The configurable serial peripheral interface control/status (INTREG) register controls how the serial
peripheral interface operates and reports its status.The register is 32 bits. The 14 MSBs are reserved and
always read as 0.
INT1
INT2
INT3
BIT
Interrupt Control/Status Register 1
Interrupt Control/Status Register 2
Interrupt Control/Status Register 3
31
30
29
28
27
26
25
0x1000E00C
0x1000F00C
0x1001700C
24 23 22 21 20
19
18
17
16
BOEN ROEN
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RFEN
RHEN
RREN
TSHFEEN
TH
TE
TYPE
rw
rw
rw
rw
rw
rw
rw
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TFEN THEN TEEN BO RO RF RH RR TSHFE TF
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
23-9
Configurable Serial Peripheral Interface (CSPI)
Table 23-5. Interrupt Control/Status Register Description
Name
Description
Settings
Reserved
Bits 31–18
Reserved—These bits are reserved and should read 0.
BOEN
Bit 17
Bit Count Overflow Interrupt Enable— This bit enables an interrupt when
bit count overflow flag BO is set.
0 = Disable
1 = Enable
ROEN
Bit 16
RxFIFO Overflow Interrupt Enable— This bit enables an interrupt when
receive overflow flag “RO” is set.
0 = Disable
1 = Enable
RFEN
Bit 15
RxFIFO Full Interrupt Enable—This bit enables an interrupt when RxFIFO
full flag “RF” is set.
0 = Disable
1 = Enable
RHEN
Bit 14
RxFIFO Half Interrupt Enable— This bit enables an interrupt when RxFIFO 0 = Disable
half flag “RH” is set.
1 = Enable
RREN
Bit 13
RxFIFO Data Ready Interrupt Enable— This bit enables an interrupt when
RxFIFO ready flag “RR” is set.
TSHFEEN
Bit 12
0 = Disable
Tx FIFO and Tx Shift Register Empty Interrupt Enable—If enabled an
interrupt is generated when both the TxFIFO and Tx Shift register are empty. 1 = Enable
This interrupt flag is cleared when a write operation is performed on the
TxFIFO.In Master mode, this interrupt is generated only after the completion
of a transmission and if SPIEN is set.
In Slave mode this interrupt is generated only after the completion of a
transmission and does not care for the CSPI1_RDY signal.
This interrupt will not be asserted before any transmission has occurred since
in this scenario also both TxFIFO and TxShift register are empty.
TFEN
Bit 11
TxFIFO Full Interrupt Enable— This bit enables an interrupt when TxFIFO 0 = Disable
full flag TF is set. When the TXFIFO full interrupt bit is set, it means there are 1 = Enable
8 words in the TXFIFO and 1 word in shift register.
THEN
Bit 10
TxFIFO Half Interrupt Enable—This bit enables an interrupt when TxFIFO 0 = Disable
half flag TH is set. When the TXFIFO half full interrupt bit is set, it means there 1 = Enable
are 4 or more words in the TXFIFO and 1 word in shift register.
TEEN
Bit 9
TxFIFO Empty Interrupt Enable—This bit enables an interrupt when TxFIFO 0 = Disable
empty flag TE is set. When the CSPI TXFIFO empty interrupt bit is set, it
1 = Enable
means no words are in the TXFIFO, however 1 or 0 words in the shift register.
BO
Bit 8
0 = No bit count overflow
Bit Count Overflow—This bit is set when CSPI is in "Slave CSPI FIFO
advanced by SS rising edge” mode and the slave is receiving more than 32 1 = At least one data word in
bits in one burst. This bit is clear after a data read from SPIRXD register.
RxFIFO has bit count
However, there is nothing to remember which data word is overflowed, hence,
overflow error
the bad data word may still be in the FIFO if it is not empty.
RO
Bit 7
RxFIFO Overflow—This bit indicates that the RxFIFO is overflow. At least
0 = RxFIFO is not overflow
one new written data word is lost. The RO flag is automatically cleared after a 1 = RxFIFO is overflow. At least
data read.
one data word in RxFIFO is
over written.
RF
Bit 6
RxFIFO Full Status—This flag is set when RxFIFO has 8 data words.
0 = Disable
1 = Enable
0 = Less than 8 data words in
RxFIFO.
1 = 8 data words in RxFIFO.
i.MX21 Reference Manual, Rev. 3
23-10
Freescale Semiconductor
Configurable Serial Peripheral Interface (CSPI)
Table 23-5. Interrupt Control/Status Register Description (continued)
Name
Description
Settings
RH
Bit 5
RxFIFO Half Status—This flag is set when RxFIFO has more than or equal
to 4 data words.
0 = Less than 4 data words in
RxFIFO.
1 = More than or equal to 4 data
words in RxFIFO.
RR
Bit 4
RxFIFO Data Ready Status—This flag is set when RxFIFO has at least one 0 = RxFIFO is empty.
data word.
1 = At least one data word is ready
in Rx FIFO.
TSHFE
Bit 3
TxFIFO and TxShift Register Empty—This flag is set when both the TxFIFO 0 = At least one data word is in
and Tx Shift register are empty after the completion of data transfer.When
TxFIFO or at least one data
TSHFE bit is set and a write is performed on the TxDATA register, the first data
bit is in Tx Shift Register.
is immediately transferred to the Tx shift register.
1 = TxFIFO and Tx Shift Register
This flag will not be asserted before any transmission has occurred since in
are empty.
this scenario also both TxFIFO and TxShift register are empty.
TF
Bit 2
TxFIFO Full Status—This flag is set when Transmit buffer has 9 data words 0 = Less than 9 data words in
(8 in TxFIFO, 1 in Tx Shift register).
buffer.
1 = 9 data words in buffer.
TH
Bit 1
TxFIFO Half Status—This flag is set when TxFIFO has more than or equal to 0 = Less than 4 empty slots in
4 empty slots (less than or equal to 5 words left for transmit—that is, 4 or more
TxFIFO.
in TxFIFO, 1 in Tx Shift register).
1 = More than or equal to 4 empty
slots in TxFIFO
TE
Bit 0
TxFIFO Empty Status—This flag is set when the TxFIFO is empty (0 in
TxFIFO, 1 or 0 words in Tx Shift register). When CSPI is enabled and TE bit
is set, the first data written to the TxFIFO is immediately loaded into the Tx
shift register.
0 = At least one data word is in Tx
FIFO.
1 = TxFIFO is empty, but data
shifting may still be on-going.
To make sure no data
transaction is on-going, read
XCH bit in control register.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
23-11
Configurable Serial Peripheral Interface (CSPI)
23.2.5
CSPI Test Register
These registers are used for test purpose and is used to report the State machine status as well as Rx and
Tx FIFO counter status.The register is 32 bits. The high 17 bits are reserved bits and always be read as 0.
Test1
Test2
Test3
Test Register 1
Test Register 2
Test Register 3
0x1000E010
0x1000F010
0x10017010
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LBC
INIT
SS_ASSERT
SSTATUS
RXCNT
TXCNT
TYPE
r
rw
rw
rw
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 23-6. Test Register Description
Name
Description
Settings
RSV
Bit 15–31
Reserved
N/A
LBC
Bit 14
Loop Back Control
0 = Disable
1 = The TX and RX are connected
internally for test purpose
INIT
Bit 13
Initialize—This bit initializes the State Machine
0 = No initialization
1 = Initialize
SS_ASSERT
Bit 12
SS Assert/Deassert—Setting this bit causes SSn to remain 0 = SSn is asserted/deasserted as per
asserted throughout the data transmission and remains
settings of the SSPOL,SSCTL bits
asserted after the TxFIFO empty and TxSHFD flags are set.
in the CONTROLREG.
If this bit is not set SSn assertion/deassertion is controlled by 1 = SSn remains asserted after TxSHFD
the SSPOL,SSCTL bits in the CONTROLREG.
flag is set.
SSTATUS
Bits 11–8
State Machine Status—This field indicates the state machine N/A
status. These bits are used for test purpose only
i.MX21 Reference Manual, Rev. 3
23-12
Freescale Semiconductor
Configurable Serial Peripheral Interface (CSPI)
Table 23-6. Test Register Description (continued)
Name
Description
Settings
RXCNT
Bits 7–4
RxFIFO Counter—This field indicates the number of data
words in RxFIFO.
0000 = RXFIFO is empty
0001 = 1 data word in RXFIFO
0010 = 2 data word in RXFIFO
0011 = 3 data word in RXFIFO
0100 = 4 data word in RXFIFO
0101 = 5 data word in RXFIFO
0110 = 6 data word in RXFIFO
0111 = 7 data word in RXFIFO
1000 = 8 data word in RXFIFO
TXCNT
Bits 3–0
TxFIFO Counter—This field indicates the number of data
words in TxFIFO. When this field is 0, there may be 1 or 0
words in the TX Shift register. When this field is equal or larger
than 1, because the first data is moved to TX Shift register,
TXCNT is equal to the actual number minus one.
0000 = TxFIFO is empty
0001 = 1 data word in TxFIFO
0010 = 2 data word in TxFIFO
0011 = 3 data word in TxFIFO
0100 = 4 data word in TxFIFO
0101 = 5 data word in TxFIFO
0110 = 6 data word in TxFIFO
0111 = 7 data word in TxFIFO
1000 = 8 data word in TxFIFO
23.2.6
CSPI Sample Period Control Register
This register controls the time inserted between data transaction in master mode. The time inserted
between samples can be from 0 to about 1 second at the resolution of bit clock or 32.768 KHz clock. The
register is 32 bits. The high 16 bits are reserved bits and always be read as 0.
.
Period1
Period2
Period3
Period Control Register 1
Period Control Register 2
Period Control Register 3
0x1000E014
0x1000F014
0x10017014
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CSRC
WAIT
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 23-7. Period Control Register Description
Name
Reserved
Bits 31–16
Description
Settings
Reserved—These bits are reserved and should read 0.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
23-13
Configurable Serial Peripheral Interface (CSPI)
Table 23-7. Period Control Register Description (continued)
Name
Description
Settings
CSRC
Bit 15
Clock Source to Counter—This bit selects between the CSPI bit clock and the
32Khz clock as the clock source for the wait period insertion counter.
0 = Bit clock
1 = 32.68KHz
WAIT
Bits 14–0
Wait—Number of clocks (either bit clock or 32Khz clock) inserted between data
transaction.
0000 = 0 clock
0001 = 1 clock
0002 = 2 clocks
…
7FFF = 32,767 clocks
23.2.7
DMA Control Register
The CSPI’s DMA control/status (DMAREG) register controls how the DMA interface of the CSPI
operates and reports its status. The register is 32 bits.
DMA1
DMA2
DMA3
Addr
0x1000E018
0x1000F018
0x10017018
DMA Register 1
DMA Register 2
DMA Register 3
BIT
31
30
29
28
27 26 25 24
23
22
21
20
TYPE
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
BIT
15
14
13
12
THDEN
TEDEN
RFDEN
RHDEN
TYPE
rw
rw
rw
rw
r
r
r
RESET
0
0
0
0
0
0
0
19 18 17 16
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
11 10 9
8
7
6
5
4
3
2
1
0
THDMA
TEDMA
RFDMA
RHDMA
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
Table 23-8. DMA Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
THDEN
Bit 15
TxFIFO Half DMA Request Enable—This bit enables the DMA Tx 0 = Disable
request if THDMA flag is set.
1 = Enable
TEDEN
Bit 14
TxFIFO Empty DMA Request Enable—This bit enables the DMA 0 = Disable
Tx request if TEDMA flag is set.
1 = Enable
RFDEN
Bit 13
RxFIFO Full DMA Request Enable—This bit enables the DMA Rx 0 = Disable
request if RFDMA flag is set.
1 = Enable
RHDEN
Bit 12
RxFIFO Half DMA Request Enable—This bit enables the DMA Rx 0 = Disable
request if RHDMA flag is set.
1 = Enable
Reserved
Bits 11–8
Reserved—These bits are reserved and should read 0.
Settings
i.MX21 Reference Manual, Rev. 3
23-14
Freescale Semiconductor
Configurable Serial Peripheral Interface (CSPI)
Table 23-8. DMA Register Description (continued)
Name
Description
Settings
THDMA
Bit 7
TxFIFO Half Status—This flag is set when TxFIFO has more than 0 = Less than 4 empty slots in TxFIFO.
or equal to 4 empty slots.
1 = More than or equal to 4 empty slots in
TxFIFO.
TEDMA
Bit 6
TxFIFO Empty Status—This flag is set when TxFIFO is empty.
RFDMA
Bit 5
RxFIFO Full Status—This flag is set when RxFIFO is full i.e it has 0 = Less than 8 data words in RxFIFO.
8 data words.
1 = 8 data words in RxFIFO.
RHDMA
Bit 4
RxFIFO Half Status—This flag is set when RxFIFO has more than 0 = Less than 4 data words in RxFIFO.
or equal to 4 data words.
1 = More than or equal to 4 data words in
RxFIFO
Reserved
Bits 3–0
Reserved—These bits are reserved and should read 0.
0 = At least one data word is in Tx FIFO.
1 = TxFIFO is empty, but data shifting may
still be on-going. To ensure no data
transaction is on-going, read XCH bit in
control register.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
23-15
Configurable Serial Peripheral Interface (CSPI)
23.2.8
CSPI Soft Reset Register
The CSPI Soft Reset registers are 32-bit registers. Soft Reset is generated by setting the start bit of the Soft
Reset register to 1.
.
Reset1
Reset2
Reset3
Soft Reset Register 1
Soft Reset Register 2
Soft Reset Register 3
0x1000E01C
0x1000F01C
0x1001701C
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
START
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 23-9. Soft Reset Register Description
Name
Description
Settings
Reserved
Bits 31–1
Reserved—These bits are reserved and should read 0.
START
Bit 0
Soft Reset Bit—Soft Reset is generated by setting this bit to 1.The soft reset is asserted for 0 = No soft reset
3 ipg_clk clock cycles and it is automatically cleared.
1 = Soft reset
This resets the following registers:
a. CONTROLREG
b. INTREG
c. DMAREG
d. TESTREG
e. PERIODREG
f. RESETREG
i.MX21 Reference Manual, Rev. 3
23-16
Freescale Semiconductor
Chapter 24
Synchronous Serial Interface (SSI)
This chapter discusses the architecture, programming model, operating modes, and initialization of the
Synchronous Serial Interface (SSI). The i.MX21 processor contains two SSI modules (SSI1 and SSI2).
These are full-duplex, serial ports that allow the i.MX21 to communicate with a variety of serial devices.
These serial devices can be standard codecs, Digital Signal Processors (DSPs), microprocessors,
peripherals that implement the Serial Peripheral Interface (SPI), and popular industry audio codecs that
implement the inter-IC sound bus standard (I2S) and Intel AC97 standard.
SSI typically are used to transfer samples in a periodic manner. The i.MX21 processor’s SSI consists of
independent transmitter and receiver sections with independent clock generation and frame
synchronization.
The capabilities of each of the SSI include:
• Independent (asynchronous) or shared (synchronous) transmit and receive sections with separate
or shared internal/external clocks and frame syncs, operating in Master or Slave mode.
• Normal mode operation using frame sync
• Network mode operation allowing multiple devices to share the port with as many as thirty-two
time slots
• Gated Clock mode operation requiring no frame sync
• 2 sets of Transmit and Receive FIFOs. Each of the four FIFOs is 8 × 24 bits. The two sets of Tx/Rx
FIFOs can be used in Network mode to provide 2 independent channels for transmission and
reception
• Programmable data interface modes such as I2S, LSB, MSB aligned
• Programmable word length (8, 10, 12, 16, 18, 20, 22, or 24 bits)
• Program options for frame sync and clock generation
• Programmable I2S modes (Master, Slave or Normal). Oversampling clock, ccm_ssi_clk available
as output from SRCK in I2S Master mode
• AC97 support
• Completely separate clock and frame sync selections for the receive and transmit sections. In AC97
standard, the clock is taken from an external source and frame sync is generated internally.
• External CCM_SSI_CLK input for use in I2S Master mode. Programmable oversampling clock
(SYS_CLK) of the sampling frequency available as output in master mode at SRCK, when
operated in sync mode.
• Programmable internal clock divider
• Time Slot Mask Registers for reduced CPU overhead (for both Tx and Rx)
• SSI power-down feature
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
24-1
Synchronous Serial Interface (SSI)
•
•
•
24.1
SSI signals are connected to IO pads through the Digital Audio Mux (AUDMUX)
Programmable wait states for CPU accesses
IP Interface for register access, compliant to SRS 3.0.2 standard
References
The following documents are identified for further reading.
• [1] Audio Codec ‘97 Specification, Revision 2.3 Rev 1.0, April 2002
• [2] I2S Bus Specification, Revised: June 5, 1996
24.2
SSI Signal Description
Table 24-1. SSI Signal Description
Name
I/O
Function
HARD_ASYNC_RESET
Input
Global hardware reset signal
IPG_CLK
Input
IP Interface working clock
IPG_CLK_S
Input
IP Interface register access clock
SSI_SRXD
Input
SSI receive data input
SSI_STXD
Output
SSI transmit data output
SSI_STCK
Input/Output
SSI transmit clock output
SSI_STFS
Input/Output
SSI transmit frame sync output
SSI_SRCK
Input/Output
SSI receive clock output
SSI_SRFS
Input/Output
SSI receive frame sync output
Note: For i.MX21, the clock gating functionality is controlled by the PLL Clock Controller (PCCR0 Register) and this signal is not
used. However, SSI still generates this signal based on SSIEN (SCR) and CLKOFF (SOR) bits.
24.3
SSI Architecture
The Synchronous Serial Interface (SSI) is connected to chip pads through the Digital Audio Mux
(AUDMUX) module. The AUDMUX can be configured to connect the two SSIs together or to external
SSIs or codecs. For more information see Chapter 30, “Digital Audio Mux (AUDMUX),” Section 30.7 on
page -11.
Figure 24-1 shows a block diagram of the SSI. It consists of three control registers to set up the port, one
status register, separate transmit and receive circuits with FIFO registers, and separate serial clock and
frame sync generation for the transmit and receive sections. The second set of Tx and Rx FIFOs, replicates
the logic used for the first set of FIFOs.
i.MX21 Reference Manual, Rev. 3
24-2
Freescale Semiconductor
Synchronous Serial Interface (SSI)
IP Bus
32-bit
Transmit Clock
STCCR
Control Reg
Tx Control &
State Machines
Receive Clock
SRCCR
Control Reg
Transmit
Config Reg
Tx Clock
Generator
STCK
Tx Sync
Generator
STFS
Rx Clock
Generator
SRCK/SYS_CLK
STCR
Receive
Config Reg
SRCR
Control Reg
SCR
Rx Control &
State Machines
Rx Sync
Generator
TXFIFO0 (8x24)
Tx Shift Reg
Load Logic
STX0 Tx0 Data Reg
TXSR
TXFIFO1 (8x24)
Tx1 Data Reg
Transmit
Shift Reg
SRX0 Rx0 Data Reg
SRFS
STX1
STXD
Rx1 Data Reg
RXFIFO0 (8x24)
SRX1
RXFIFO1 (8x24)
Rx Shift Reg
Unload Logic
RXSR
Receive
Shift Reg
SRXD
Figure 24-1. SSI Block Diagram
24.3.1
SSI Clocking
The SSI uses the following clocks:
• Bit clock—Used to serially clock the data bits in and out of the SSI port. This clock is either
generated internally or taken from an external clock source (through the Tx/Rx clock ports).
• Word clock—Used to count the number of data bits per word (8, 10, 12, 16, 18, 20, 22 or 24 bits).
This clock is generated internally from the bit clock.
i.MX21 Reference Manual, Rev. 3
Freescale Semiconductor
24-3
Synchronous Serial Interface (SSI)
•
•
Frame clock (Frame Sync)—Used to count the number of words in a frame. This signal can be
generated internally from the bit clock, or taken from external source (from the Tx/Rx frame sync
ports).
Sys clock—In master mo
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