NXP i.MXS Multimedia Applications Processors - .NET Micro Framework applications, Arm9™ Core Reference Manual

NXP i.MXS Multimedia Applications Processors - .NET Micro Framework applications, Arm9™ Core Reference Manual
Freescale Semiconductor
Addendum
Document Number: MC9328MXRMAD
Rev. 0, 11/2007
i.MX Reference Manual Addendum
Revision GPCR Register; DS_SLOW Field
Applies to:
MC9328MX1
MC9328MXL
MC9328MXS
1
Introduction
Contents
This addendum applies to the i.MX Applications
Processor Reference Manuals (Document order
numbers: MC9328MX1RM, MC9328MXLRM,
MC9328MXSRM,). The change to the reference
manuals is to Chapter 8, “Programming Model,” Section
8.1.3, “Global Peripheral Control Register Description,
Table 8-4, Global Peripheral Control Register
Description.
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
In the Global Peripheral Control Register Description
(Table 8-4) the DS_SLOW register field settings indicate
a difference between setting 10 and 11. In fact, the two
setting are the same. Therefore, replace the DS_SLOW
register field in Table 8-4 with the following:
DS_SLOW
Bits 11–10
Driving Strength Slow I/O—Controls
the driving strength of all slow I/O signals.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
00 = 26 MHz/15 pF
01 = 26 MHz/30 pF
10 = 26 MHz/45 pF
11 = 26 MHz/45 pF
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Document Number: MC9328MXRMAD
Rev. 0
11/2007
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