NXP | i.MXS | Reference guide | NXP i.MXS Reference guide

MC9328MXS
i.MX Integrated Portable
System Processor
Reference Manual
Document Number: MC9328MXSRM
Rev. 1.1
06/2007
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Contents
Chapter 1
Introduction
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
ARM920T Microprocessor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB to IP Bus Interfaces (AIPIs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Interface Module (EIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDRAM Controller (SDRAMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation Module (CGM) and Power Control Module . . . . . . . . . . . . . . . . . . . . . . . . .
Two Universal Asynchronous Receiver/Transmitters
(UART 1 and UART 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two General-Purpose 32-Bit Counters/Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-Time Clock/Sampling Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCD Controller (LCDC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse-Width Modulation (PWM) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Universal Serial Bus (USB) Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Direct Memory Access Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Serial Interface and Inter-IC Sound (SSI/I2S) Module . . . . . . . . . . . . . . . . . . . . .
Inter-IC (I2C) Bus Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose I/O (GPIO) Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootstrap Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
1-3
1-3
1-3
1-4
1-4
1-4
1-4
1-4
1-5
1-5
1-5
1-6
1-6
1-7
1-7
1-7
1-7
1-8
1-8
1-8
Chapter 2
Signal Descriptions and Pin Assignments
2.1
Signal and Pin Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Chapter 3
Memory Map
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Double Map Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-1
3-4
3-5
3-5
3-6
Chapter 4
ARM920T Processor
4.1
4.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
ARM920T Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
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4.2.1
Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2
Cache Lock-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3
Write Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4
PATAG RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.5
MMUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.6
System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.7
Control Coprocessor (CP15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
ARMv4T Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2
Modes and Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3
Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.4
Exception Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.5
Conditional Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Four Classes of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1
Data Processing Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2
Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2.1
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2.2
Block Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.3
Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.3.1
Branch with Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.4
Coprocessor Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
The ARM9 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6
The ARM Thumb Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.1
ARM920T Modes and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3
4-3
4-3
4-3
4-3
4-3
4-4
4-4
4-4
4-4
4-5
4-5
4-5
4-5
4-5
4-6
4-6
4-6
4-7
4-7
4-7
4-7
4-8
4-9
Chapter 5
Embedded Trace Macrocell (ETM)
5.1
5.2
5.3
Introduction to the ETM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Programming and Reading ETM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Pin Configuration for ETM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Chapter 6
Reset Module
6.1
6.1.1
6.1.2
6.2
6.2.1
Functional Description of the Reset Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ARM920T Processor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Source Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1
6-1
6-2
6-3
6-3
Chapter 7
AHB to IP Bus Interface (AIPI)
7.1
7.1.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
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7.1.2
General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.2.1
Peripheral Size Registers[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.2.1.1
AIPI1 Peripheral Size Register 0 and AIPI2 Peripheral Size Register 0 . . . . . . . . . . . 7-10
7.2.1.2
AIPI1 Peripheral Size Register 1 and AIPI2 Peripheral Size Register 1 . . . . . . . . . . . 7-11
7.2.2
Peripheral Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
7.2.3
Peripheral Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.2.4
Time-Out Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.3
Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
7.3.1
Data Access to 8-Bit Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
7.3.2
Data Access to 16-Bit Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
7.3.3
Data Access to 32-Bit Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
7.3.4
Special Consideration for Non-Natural Size Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
Chapter 8
System Control
8.1
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.1
Silicon ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.2
Function Multiplexing Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.3
Global Peripheral Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.4
Global Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2
System Boot Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-1
8-2
8-2
8-4
8-6
8-7
Chapter 9
Bootstrap Mode Operation
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.2
9.3
9.4
9.5
9.6
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Entering Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootstrap Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers Used in Bootloader Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Up the RS-232 Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing the Speed of Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-Record Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Buffer Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simple Read/Write Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootloader Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-1
9-1
9-2
9-2
9-3
9-3
9-3
9-3
9-5
9-7
9-7
Chapter 10
Interrupt Controller (AITC)
10.1
10.2
10.3
10.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AITC Interrupt Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-1
10-2
10-3
10-4
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10.4.1
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.4.2
Normal Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10.4.3
Interrupt Enable Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.4
Interrupt Disable Number Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.4.5
Interrupt Enable Register High and Interrupt Enable Register Low. . . . . . . . . . . . . . . . . 10-11
10.4.5.1
Interrupt Enable Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.4.5.2
Interrupt Enable Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.4.6
Interrupt Type Register High and Interrupt Type Register Low . . . . . . . . . . . . . . . . . . . 10-13
10.4.6.1
Interrupt Type Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.4.6.2
Interrupt Type Register Low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.4.7
Normal Interrupt Priority Level Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.4.7.1
Normal Interrupt Priority Level Register 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.4.7.2
Normal Interrupt Priority Level Register 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.4.7.3
Normal Interrupt Priority Level Register 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.4.7.4
Normal Interrupt Priority Level Register 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10.4.7.5
Normal Interrupt Priority Level Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
10.4.7.6
Normal Interrupt Priority Level Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
10.4.7.7
Normal Interrupt Priority Level Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21
10.4.7.8
Normal Interrupt Priority Level Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
10.4.8
Normal Interrupt Vector and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
10.4.9
Fast Interrupt Vector and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
10.4.10
Interrupt Source Register High and Interrupt Source Register Low. . . . . . . . . . . . . . . . . 10-25
10.4.10.1
Interrupt Source Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
10.4.10.2
Interrupt Source Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26
10.4.11
Interrupt Force Register High and Interrupt Force Register Low. . . . . . . . . . . . . . . . . . . 10-27
10.4.11.1
Interrupt Force Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27
10.4.11.2
Interrupt Force Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28
10.4.12
Normal Interrupt Pending Register High and Normal Interrupt Pending Register Low . 10-29
10.4.12.1
Normal Interrupt Pending Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29
10.4.12.2
Normal Interrupt Pending Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
10.4.13 Fast Interrupt Pending Register High and Fast Interrupt Pending Register Low . . . . . . . 10-31
10.4.13.1
Fast Interrupt Pending Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31
10.4.13.2
Fast Interrupt Pending Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32
10.5 ARM920T Processor Interrupt Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33
10.5.1
ARM920T Processor Prioritization of Exception Sources . . . . . . . . . . . . . . . . . . . . . . . . 10-33
10.5.2
AITC Prioritization of Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33
10.5.3
Assigning and Enabling Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33
10.5.4
Enabling Interrupts Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33
10.5.5
Typical Interrupt Entry Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34
10.5.6
Writing Reentrant Normal Interrupt Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35
Chapter 11
External Interface Module (EIM)
11.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
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11.2 EIM I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2.1
Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2.2
Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2.3
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2.4
Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.4.1
OE—Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.4.2
EB [3:0]—Enable Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.4.3
DTACK—Data Transfer Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.5
Chip Select Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.5.1
Chip Select 0 (CS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.5.2
Chip Select 1–Chip Select 5 (CS1–CS5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.6
Burst Mode Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.6.1
BCLK—Burst Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.6.2
LBA—Load Burst Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.6.3
ECB—End Current Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.3 Pin Configuration for EIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.4 Typical EIM System Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.5 EIM Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.5.1
Configurable Bus Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.5.2
Programmable Output Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.5.3
Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.5.4
Burst Clock Divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.5.5
Burst Clock Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.5.6
Page Mode Emulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.5.7
Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.6 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
11.6.1
Chip Select 0 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.6.1.1
Chip Select 0 Upper Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.6.1.2
Chip Select 0 Lower Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.6.2
Chip Select 1–Chip Select 5 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.6.2.1
Chip Select 1–Chip Select 5 Upper Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.6.2.2
Chip Select 1–Chip Select 5 Lower Control Registers. . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.6.3
EIM Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
Chapter 12
Phase-Locked Loop and Clock Controller
12.1
12.2
12.2.1
12.2.2
12.3
12.3.1
12.4
12.4.1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Frequency Clock Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Frequency Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DPLL Output Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DPLL Phase and Frequency Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC9328MXS Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Operation at Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-1
12-1
12-1
12-2
12-3
12-3
12-3
12-4
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12.4.2
PLL Operation at Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.4.3
ARM920T Processor Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.4.4
SDRAM Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.4.5
Power Management in the Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.5 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.5.1
Clock Source Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.5.2
Peripheral Clock Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.5.3
Programming Digital Phase Locked Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.5.3.1
MCU PLL Control Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.5.3.2
MCU PLL and System Clock Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.5.4
Generation of 48 MHz Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.5.4.1
System PLL Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.5.4.2
System PLL Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
Chapter 13
DMA Controller
13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.3 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.3.1
Big Endian and Little Endian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.4 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.4.1
General Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.4.1.1
DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.4.1.2
DMA Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
13.4.1.3
DMA Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.4.1.4
DMA Burst Time-Out Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.4.1.5
DMA Request Time-Out Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13.4.1.6
DMA Transfer Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
13.4.1.7
DMA Buffer Overflow Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.4.1.8
DMA Burst Time-Out Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
13.4.2
2D Memory Registers (A and B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
13.4.2.1
W-Size Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
13.4.2.2
X-Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
13.4.2.3
Y-Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
13.4.3
Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
13.4.3.1
Channel Source Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
13.4.3.2
Destination Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20
13.4.3.3
Channel Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21
13.4.3.4
Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22
13.4.3.5
Channel Request Source Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25
13.4.3.6
Channel Burst Length Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26
13.4.3.7
Channel Request Time-Out Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-27
13.4.3.8
Channel 0 Bus Utilization Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28
13.5 DMA Request Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30
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Chapter 14
Watchdog Timer Module
14.1 General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.1
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.2
Watchdog During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.2.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.2.2
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3 Watchdog After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.1
Initial Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.2
Countdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.3
Reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.4
Time-Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.5
Halting the Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4 Watchdog Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.1
Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.2
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.6 Watchdog Timer I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.7 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.7.1
Watchdog Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.7.2
Watchdog Service Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.7.3
Watchdog Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14-1
14-1
14-1
14-2
14-2
14-2
14-2
14-2
14-2
14-2
14-3
14-3
14-3
14-3
14-3
14-4
14-5
14-6
14-6
14-7
14-8
Chapter 15
Serial Peripheral Interface Module (SPI 1)
15.1 SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.2.1
Phase and Polarity Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.2.2
Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.2.3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.3.1
Receive (RX) Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.3.2
Transmit (TX) Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
15.3.3
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.3.4
Interrupt Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.3.5
Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
15.3.6
Sample Period Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
15.3.7
DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
15.3.8
Soft Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
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Chapter 16
LCD Controller
16.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.3 LCDC Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.3.1
LCD Screen Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.3.2
Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.3.3
Display Data Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.3.4
Black-and-White Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
16.3.5
Gray-Scale Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
16.3.6
Color Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
16.3.7
Frame Rate Modulation Control (FRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
16.3.8
Panel Interface Signals and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
16.3.8.1
Pin Configuration for LCDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
16.3.8.2
Passive Matrix Panel Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12
16.3.8.3
Passive Panel Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.3.9
8 bpp Mode Color STN Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14
16.3.9.1
Active Matrix Panel Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14
16.3.9.2
Active Panel Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
16.4 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18
16.4.1
Screen Start Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20
16.4.2
Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21
16.4.3
Virtual Page Width Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22
16.4.4
Panel Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23
16.4.5
Horizontal Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-26
16.4.6
Vertical Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-27
16.4.7
Panning Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28
16.4.8
LCD Cursor Position Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-29
16.4.9
LCD Cursor Width Height and Blink Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30
16.4.10
LCD Color Cursor Mapping Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-31
16.4.11 Sharp Configuration 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32
16.4.12
PWM Contrast Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-34
16.4.13
Refresh Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-35
16.4.14
DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-36
16.4.15
Interrupt Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-37
16.4.16
Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-38
16.4.17
Mapping RAM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-39
16.4.17.1
One Bit/Pixel Monochrome Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-39
16.4.17.2
Four Bits/Pixel Gray-Scale Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-39
16.4.17.3
Four Bits/Pixel Passive Matrix Color Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-40
16.4.17.4
Eight Bits/Pixel Passive Matrix Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-40
16.4.17.5
Four Bits/Pixel Active Matrix Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-41
16.4.17.6
Eight Bits/Pixel Active Matrix Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-41
16.4.17.7
Twelve Bits/Pixel and Sixteen Bits/Pixel Active Matrix Color Mode . . . . . . . . . . . . 16-42
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Chapter 17
Pulse-Width Modulator (PWM)
17.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.2 PWM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.2.1
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.2.2
Pin Configuration for PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.3 PWM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.3.1
Playback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.3.2
Tone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.3.3
Digital-to-Analog Converter (D/A) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.1
PWM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.1.1
HCTR and BCTR Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.2
PWM Sample Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.3
PWM Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.4
PWM Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17-1
17-1
17-1
17-2
17-2
17-2
17-3
17-3
17-3
17-3
17-6
17-6
17-7
17-8
Chapter 18
Real-Time Clock (RTC)
18.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.1.1
Prescaler and Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.1.2
Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.1.3
Sampling Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.1.4
Minute Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.2.1
RTC Days Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.2.2
RTC Hours and Minutes Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.2.3
RTC Seconds Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7
18.2.4
RTC Day Alarm Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8
18.2.5
RTC Hours and Minutes Alarm Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
18.2.6
RTC Seconds Alarm Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10
18.2.7
RTC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11
18.2.8
RTC Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12
18.2.9
RTC Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14
18.2.10
Stopwatch Minutes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15
Chapter 19
SDRAM Memory Controller
19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3.1
SDRAM Command Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3.2
Page and Bank Address Comparators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19-1
19-2
19-3
19-3
19-3
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19.3.3
Row and Column Address Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.3.4
Data Aligner and Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.3.5
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.3.6
Refresh Request Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.3.7
Powerdown Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.3.8
DMA Operation with the SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.3.9
SDCLK—SDRAM Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.3.10
SDCKE0, SDCKE1—SDRAM Clock Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.3.11
CSD0, CSD1—SDRAM Chip-Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.3.12
DQ [31:0]—Data Bus (Internal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.3.13
MA [11:0]—Multiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.3.14
SDBA [4:0], SDIBA [3:0]—Non-Multiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.3.15
DQM3, DQM2, DQM1, DQM0—Data Qualifier Mask . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.3.16
SDWE—Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.3.17 RAS—Row Address Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.3.18 CAS—Column Address Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.3.19
RESET_SF—Reset or Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.3.20
Pin Configuration for SDRAMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7
19.4 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8
19.4.1
SDRAM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9
19.4.2
SDRAM Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16
19.4.3
Miscellaneous Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17
19.5 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18
19.5.1
SDRAM and SyncFlash Command Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18
19.5.2
Normal Read/Write Mode (SMODE = 000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19
19.5.3
Precharge Command Mode (SMODE = 001). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24
19.5.4
Auto-Refresh Mode (SMODE = 010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25
19.5.5
Set Mode Register Mode (SMODE = 011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25
19.5.6
SyncFlash Load Command Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26
19.5.7
SyncFlash Program Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27
19.6 General Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28
19.6.1
Address Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-29
19.6.1.1
Multiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-29
19.6.1.2
Non-Multiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31
19.6.1.3
Bank Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31
19.6.2
Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-32
19.6.3
Self-Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-33
19.6.3.1
Self-Refresh During RESET_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-33
19.6.3.2
Self-Refresh During Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-33
19.6.3.3
Powerdown Operation During Reset and Low-Power Modes . . . . . . . . . . . . . . . . . . 19-33
19.6.4
Clock Suspend Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-35
19.6.4.1
Powerdown (Precharge Powerdown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-35
19.6.4.2
Clock Suspend (Active Powerdown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-36
19.6.4.3
Refresh During Powerdown or Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-36
19.7 SDRAM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-37
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19.7.1
SDRAM Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.7.2
Configuring Controller for SDRAM Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.7.2.1
CAS Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.7.2.2
Row Precharge Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.7.2.3
Row-to-Column Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.7.2.4
Row Cycle Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.7.2.5
Refresh Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.7.2.6
Memory Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.7.3
SDRAM Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.7.4
Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.7.5
Mode Register Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.7.5.1
Example 1—256 Mbit SDRAM Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.7.5.2
Example 2—64 Mbit SDRAM Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.7.6
SDRAM Memory Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.8 SyncFlash Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.8.1
SyncFlash Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.8.2
SyncFlash Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.8.3
Booting From SyncFlash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.8.4
SyncFlash Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.8.5
SyncFlash Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.8.6
Clock Suspend Timer Use with SyncFlash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.8.7
Powerdown Operation with SyncFlash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.9 Deep Powerdown Operation with SyncFlash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19-37
19-38
19-38
19-38
19-38
19-38
19-39
19-39
19-57
19-59
19-62
19-62
19-64
19-67
19-67
19-67
19-68
19-68
19-68
19-71
19-72
19-72
19-72
Chapter 20
General-Purpose Timers
20.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.1.1
Pin Configuration for General-Purpose Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.2.1
Timer Control Registers 1 and 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.2.2
Timer Prescaler Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.2.3
Timer Compare Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.2.4
Timer Capture Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.2.5
Timer Counter Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.2.6
Timer Status Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-2
20-2
20-3
20-3
20-5
20-6
20-7
20-8
20-9
Chapter 21
Universal Asynchronous Receiver/Transmitters (UART) Modules
21.1
21.2
21.2.1
21.2.2
21.3
21.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Module Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts and DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General UART Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21-1
21-1
21-2
21-3
21-4
21-4
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21.4.1
RTS—UART Request To Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
21.4.2
RTS Edge Triggered Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.4.3
DTR—Data Terminal Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.4.4
DTR Edge Triggered Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.4.5
DSR—Data Set Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.4.6
DCD—Data Carrier Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.4.7
RI—Ring Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.4.8
CTS—Clear To Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.4.9
Programmable CTS Deassertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
21.4.10
TXD—UART Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
21.4.11
RXD—UART Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
21.5 Sub-Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
21.5.1
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10
21.5.2
Transmitter FIFO Empty Interrupt Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11
21.5.3
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12
21.5.4
Idle Line Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13
21.5.4.1
Idle Condition Detect Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13
21.5.5
Receiver Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14
21.5.6
Receiving a BREAK Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14
21.5.7
Vote Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14
21.5.8
Binary Rate Multiplier (BRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15
21.5.9
Baud Rate Automatic Detection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17
21.5.9.1
Baud Rate Automatic Detection Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-18
21.5.10
Escape Sequence Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-19
21.6 Infrared Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-20
21.7 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21
21.7.1
UART Receiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23
21.7.2
UART Transmitter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-25
21.7.3
UART Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26
21.7.4
UART Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29
21.7.5
UART Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32
21.7.5.1
UART1 Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32
21.7.5.2
UART2 Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-34
21.7.6
UART Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-36
21.7.7
UART FIFO Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-38
21.7.8
UART Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-40
21.7.9
UART Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-42
21.7.10
UART Escape Character Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-44
21.7.11
UART Escape Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-45
21.7.12
UART BRM Incremental Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-46
21.7.13
UART BRM Modulator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-47
21.7.14
UART Baud Rate Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-48
21.7.15
UART BRM Incremental Preset Registers 1–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-49
21.7.16 UART BRM Modulator Preset Registers 1–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-50
21.7.17
UART Test Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-51
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21.8
UART Operation in Low-Power System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-52
Chapter 22
USB Device Port
22.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.2 Module Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
22.2.1
Universal Serial Bus Device Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.2.2
Synchronization and Transaction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.2.3
Endpoint FIFO Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.2.4
Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.2.5
USB Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.2.6
Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.2.7
Pin Configuration for USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.3.1
USB Frame Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.3.2
USB Specification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9
22.3.3
USB Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10
22.3.4
USB Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11
22.3.5
USB Descriptor RAM Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13
22.3.6
USB Descriptor RAM/Endpoint Buffer Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14
22.3.7
USB Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15
22.3.8
USB Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-17
22.3.9
USB Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18
22.3.10
Endpoint n Status/Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-19
22.3.11
Endpoint n Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-20
22.3.12
Endpoint n Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23
22.3.13
Endpoint n FIFO Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-25
22.3.14
Endpoint n FIFO Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26
22.3.15
Endpoint n FIFO Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28
22.3.16
USB Endpoint n Last Read Frame Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30
22.3.17
USB Endpoint n Last Write Frame Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-31
22.3.18
Endpoint n FIFO Alarm Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-32
22.3.19
Endpoint n FIFO Read Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-33
22.3.20
Endpoint n FIFO Write Pointer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-34
22.4 Programmer’s Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-34
22.5 Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-35
22.5.1
Configuration Download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-36
22.5.1.1
USB Endpoint to FIFO Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-37
22.5.1.2
USB Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-37
22.5.1.3
Endpoint Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-37
22.5.1.4
Enable the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-38
22.6 Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-38
22.6.1
Unable to Complete Device Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-38
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22.6.2
Aborted Device Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.6.3
Unable to Fill or Empty FIFO Due to Temporary Problem . . . . . . . . . . . . . . . . . . . . . . .
22.6.4
Catastrophic Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7 Data Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7.1
USB Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7.1.1
Short Packets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7.1.2
Sending Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7.1.3
Receiving Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7.1.4
Programming the FIFO Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7.2
USB Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7.2.1
Data Transfers to the Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7.2.2
Data Transfers to the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7.3
Control Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7.4
Bulk Traffic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7.4.1
Bulk OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7.4.2
Bulk IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7.5
Interrupt Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7.6
Isochronous Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7.6.1
Isochronous Transfers in a Nutshell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7.6.2
The SYNCH_FRAME Standard Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8 Interrupt Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.1
USB General Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.1.1
MSOF—Missed Start-of-Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.1.2
SOF—Start-of-Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.1.3
RESET_STOP—End of USB Reset Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.1.4
RESET_START—Start of USB Reset Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.1.5
WAKEUP—Resume (Wakeup) Signaling Detected . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.1.6
SUSP—USB Suspended. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.1.7
FRAME_MATCH—Match Detected in USB_FRAME Register . . . . . . . . . . . . . . .
22.8.1.8
CFG_CHG—Host Changed USB Device Configuration . . . . . . . . . . . . . . . . . . . . . .
22.8.2
Endpoint Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.2.1
FIFO_FULL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.2.2
FIFO_EMPTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.2.3
FIFO_ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.2.4
FIFO_HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.2.5
FIFO_LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.2.6
EOT—End of Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.2.7
DEVREQ—Device Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.2.8
MDEVREQ—Multiple Device Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.2.9
EOF—End of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.3
Interrupts, Missed Interrupts, and the USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.3.1
SOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.3.2
CFG_CHG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.3.3
EOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.8.3.4
DEVREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22-38
22-39
22-39
22-39
22-39
22-39
22-40
22-40
22-41
22-41
22-41
22-42
22-42
22-42
22-42
22-43
22-43
22-43
22-43
22-44
22-44
22-44
22-44
22-44
22-44
22-45
22-45
22-45
22-45
22-45
22-45
22-45
22-46
22-46
22-46
22-46
22-46
22-46
22-46
22-47
22-47
22-47
22-47
22-47
22-47
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22.9 Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.9.1
Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.9.2
USB Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.9.3
UDC Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.9.4
USB Reset Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22-47
22-48
22-48
22-48
22-48
Chapter 23
I2C Module
23.1
23.2
23.3
23.4
23.4.1
23.4.2
23.4.3
23.4.4
23.5
23.6
23.6.1
23.6.2
23.6.3
23.6.4
23.6.5
23.7
23.7.1
23.7.2
23.7.3
23.7.4
23.7.5
23.7.6
23.7.7
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
I2C System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
I2C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
Pin Configuration for I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6
I2C Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7
I2C Frequency Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8
I2C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10
I2C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11
I2C Data I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13
I2C Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13
Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14
Generation of START. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14
Post-Transfer Software Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14
Generation of STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-15
Generation of Repeated START. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-15
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-15
Arbitration Lost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-15
Chapter 24
Synchronous Serial Interface (SSI)
24.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.2 SSI Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.2.1
SSI Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.2.1.1
Normal Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.2.1.2
Master / Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.2.2
SSI Clock and Frame Sync Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.2.3
Pin Configuration for SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.2.3.1
Pin Configuration Example Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.3.1
SSI Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24-1
24-2
24-4
24-4
24-4
24-4
24-5
24-7
24-7
24-8
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24.3.2
SSI Transmit FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
24.3.3
SSI Transmit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
24.3.4
SSI Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
24.3.5
SSI Receive FIFO Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
24.3.6
SSI Receive Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13
24.3.7
SSI Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15
24.3.7.1
I2S Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19
24.3.8
SSI Transmit Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-21
24.3.9
SSI Receive Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23
24.3.10
SSI Transmit Clock Control Register and SSI Receive Clock Control Register . . . . . . . 24-27
24.3.10.1
Calculating the SSI Bit Clock from the Input Clock Value . . . . . . . . . . . . . . . . . . . . 24-28
24.3.11
SSI Time Slot Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-30
24.3.12
SSI FIFO Control/Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-31
24.3.13
SSI Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-34
24.4 SSI Data and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-35
24.4.1
SSI_TXDAT, Serial Transmit Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-35
24.4.2
SSI_RXDAT, Serial Receive Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-35
24.4.3
SSI_TXCLK, Serial Transmit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-35
24.4.4
SSI_RXCLK, Serial Receive Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-35
24.4.5
SSI_TXFS, Serial Transmit Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-36
24.4.6
SSI_RXFS, Serial Receive Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-36
24.5 SSI Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-38
24.5.1
Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-39
24.5.1.1
Normal Mode Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-39
24.5.1.2
Normal Mode Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-39
24.5.2
Network Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-41
24.5.2.1
Network Mode Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-41
24.5.2.2
Network Mode Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-42
24.6 Gated Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-43
24.7 External Frame and Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-44
24.8 SSI Reset and Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-44
Chapter 25
GPIO Module and I/O Multiplexer (IOMUX)
25.1
25.2
25.2.1
25.2.2
25.2.3
25.3
25.4
25.5
25.5.1
25.5.2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration for GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25-1
25-2
25-2
25-3
25-3
25-4
25-4
25-6
25-8
25-9
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25.5.2.1
25.5.2.2
25.5.3
25.5.3.1
25.5.3.2
25.5.3.3
25.5.3.4
25.5.4
25.5.5
25.5.6
25.5.7
25.5.7.1
25.5.7.2
25.5.8
25.5.9
25.5.10
25.5.11
25.5.12
Output Configuration Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9
Output Configuration Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10
Input Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11
Input Configuration Register A1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11
Input Configuration Register A2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12
Input Configuration Register B1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
Input Configuration Register B2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14
Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
GPIO In Use Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16
Sample Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17
Interrupt Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18
Interrupt Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18
Interrupt Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19
Interrupt Mask Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21
General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22
Software Reset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23
Pull_Up Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-24
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About This Book
This reference manual describes the features and operation of the MC9328MXS (i.MXS) microprocessor, It
provides the details of how to initialize, configure, and program the MC9328MXS. The manual presumes basic
knowledge of ARM920T™ architecture.
Audience
The MC9328MXS Reference Manual is intended to provide a design engineer with the necessary data to
successfully integrate the MC9328MXS into a wide variety of applications. It is assumed that the reader has a good
working knowledge of the ARM920T processor. For programming information about the ARM920T processor,
see the documents listed in the Suggested Reading section of this preface.
Organization
The MC9328MXS Reference Manual is organized into chapters that cover the operation and programming of the
i.MXS device. Summaries of the chapters follow.
Chapter 1
Introduction: This chapter contains a device feature list, overview of system modules,
and system block diagrams.
Chapter 2
Signal Descriptions and Pin Assignments: This chapter’s content has been moved to the
MC9328MXS Data Sheet.
Chapter 3
Memory Map: This chapter summarizes the memory organization, programming
information and a listing of all of the registers in the MC9328MXS.
Chapter 4
ARM920T Processor: This chapter provides a high-level overview of the ARM920T
processor including the ARM9 Thumb® instruction set.
Chapter 5
Embedded Trace Macrocell (ETM): This chapter provides a summary of the operation
and features of the ARM Embedded Trace Macrocell™.
Chapter 6
Reset Module: The reset module processes of all of the system reset signals required by
the MC9328MXS. This chapter gives a detailed description of the reset module and
associated timing and signals.
Chapter 7
AHB to IP Bus Interface (AIPI): This chapter provides an overview of the R-AHB to
IP bus interface. The AIPI module in the MC9328MXS acts as an interface between the
R-AHB (Reduced ARM Advanced High-performance Bus) and lower bandwidth
peripherals.
Chapter 8
System Control: This chapter describes the operation of and programming models for
the system multiplex control, peripheral control, ID register, and I/O drive control
registers.
Chapter 9
Bootstrap Mode Operation: The operation of bootstrap models is described in detail in
this chapter. This chapter describes programming information necessary to allow a system
to initialize a target system and download a program or data to the target system’s RAM
using the UART controller.
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Chapter 10
Interrupt Controller (AITC): This chapter provides a description and operational
considerations for interrupt controller operation to perform interrupt masking, priority
support, and hardware acceleration of normal interrupts.
Chapter 11
External Interface Module (EIM): This chapter describes the external interface module
and shows how the module handles the interface to devices external to the MC9328MXS,
including generation of chip selects for external peripherals and memory.
Chapter 12
Phase-Locked Loop and Clock Controller: This chapter provides detailed information
about the operation and programming of the clock generation module as well as the
recommended circuit schematics for external clock circuits. It also describes and provides
programming information about the operation of the power control module and the
system power states.
Chapter 13
DMA Controller (DMAC): This chapter describes the operation of the direct memory
access controller contained in the MC9328MXS. The DMA controller provides two
memory channels and four I/O channels to support a wide variety of DMA operations.
Chapter 14
Watchdog Timer Module: The operation of the watchdog timer module is described in
this chapter. It includes information of how the watchdog timer protects against system
failures by providing a method of escaping from unexpected events or programming
errors.
Chapter 15
Serial Peripheral Interface Module (SPI 1): The programming and operation of the
serial peripheral interface module (SPI 1) is described in this chapter.
Chapter 16
LCD Controller (LCDC): This chapter describes the operation and programming of the
liquid crystal display controller, which provides display data for external LCD drivers or
for an LCD panel.
Chapter 17
Pulse-Width Modulator (PWM): This chapter describes the operation and
configuration of the pulse-width modulator. Programming information is also provided.
Chapter 18
Real-Time Clock (RTC): This chapter describes the operation of the real-time clock
module, which is composed of a prescaler, time-of-day (TOD) clock, TOD alarm,
programmable real-time interrupt, watchdog timer, and minute stopwatch as well as
control registers and bus interface hardware.
Chapter 19
SDRAM Memory Controller (SDRAMC): The operation and programming of the
SDRAM controller is described in this chapter. This module provides a glueless interface
to 16-bit or 32-bit synchronous DRAM.
Chapter 20
General-Purpose Timers: This chapter describes the two 16-bit timers that can be used
as both watchdogs and alarms.
Chapter 21
Universal Asynchronous Receiver/Transmitters (UART): This chapter describes the
capabilities and operation of the three UARTs. It also discusses how to configure and
program the UART modules.
Chapter 22
USB Device Port: This chapter provides configuration, interface description and detailed
programming information for designers to achieve the optimum performance from the
USB device.
Chapter 23
I2C Module: This chapter describes the I2C module of the MC9328MXS including I2C
protocol, clock synchronization, and the registers in the I2C programming mode.
Chapter 24
Synchronous Serial Interface (SSI): This chapter presents the two Synchronous Serial
Interface modules and discusses the architecture, programming model, operating modes,
and initialization of the SSI.
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Chapter 25
GPIO and I/O Multiplexer (IOMUX): This chapter covers all GPIO lines found in the
MC9328MXS. Because each pin is individually configurable, a detailed description of
the operation is provided.
Document Revision History
Table 0-1 includes technical content changes made for this revision.
Table 0-1. Revision History
Location
Description of Change
Chapter 13, “DMA Controller,” Table 13-23 on
page 13-30
DMA Request table: DMA_REQ [12] change from “Reserved”
to “Ext_DMA”.
Chapter 24, “Synchronous Serial Interface (SSI),”
Section 24.7, “External Frame and Clock Operation.”
Clarification to first paragraph.
Chapter 15, “Serial Peripheral Interface Module (SPI 1),”
Section 15.3.3, “Control Register.”
BIT_COUNT field description change.
Suggested Reading
The following documents are required for a complete description of the MC9328MXS and are necessary to design
properly with the device. Especially for those not familiar with the ARM920T processor or previous DragonBall
products, the following documents will be helpful when used in conjunction with this manual.
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)
ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)
ARM Technical Refines Manual (ARM Ltd., order number ARM DDI 0151C)
EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)
MC9328MXS Product Brief (order number MC9328MXSP/D)
MC9328MXS Data Sheet (order number MC9328MXS/D)
The manuals may be found at the Motorola Semiconductors World Wide Web site at
http://www.motorola.com/semiconductors. These documents may be downloaded directly from the World Wide
Web site, or printed versions may be ordered. The World Wide Web site also may have useful application notes.
Conventions
This reference manual uses the following conventions:
•
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
•
Logic level one is a voltage that corresponds to Boolean true (1) state.
•
Logic level zero is a voltage that corresponds to Boolean false (0) state.
•
To set a bit or bits means to establish logic level one.
•
To clear a bit or bits means to establish logic level zero.
•
A signal is an electronic construct whose state conveys or changes in state convey information.
•
A pin is an external physical connection. The same pin can be used to connect a number of signals.
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•
Asserted means that a discrete signal is in active logic state.
— Active low signals change from logic level one to logic level zero.
— Active high signals change from logic level zero to logic level one.
•
Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
•
LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and
high bytes or words are spelled out.
•
Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are
hexadecimal.
Definitions, Acronyms, and Abbreviations
The following list defines acronyms and abbreviations used in this document.
ADC
analog-to-digital converter
AFE
analog front end
API
application programming interface
BCD
binary coded decimal
BER
bit error ratio
CGM
clock generation module
CRC
cyclic redundancy check
CSIC
complex instruction set computer
DAC
digital-to-analog converter
DDR RAM
double data rate RAM
DMA
direct memory access
DRAM
dynamic random access memory
FEC
forward error correction
FIFO
first in first out
GPIO
general purpose input/output
I/O
Input/Output
ICE
in-circuit emulation
IrDa
infrared
JTAG
joint test action group
MAP
mold array process
MAPBGA
mold array process ball grid array
MIPS
million instructions per second
PLL
phase locked loop
PWM
pulse-width modulator
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RTC
real-time clock
SIM
system integration module
SDRAM
synchronous dynamic random access memory
SPI
serial peripheral interface
SRAM
static random access memory
TQFP
thin quad flat pack
UART
universal asynchronous receiver/transmitter
USB
universal serial bus
XTAL
crystal
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Chapter 1
Introduction
The i.MX (Media Extensions) series provides a leap in performance with an ARM9™ microprocessor core
and highly integrated system functions. i.MX products specifically address the requirements of the
portable product market by providing intelligent integrated peripherals, an advanced processor core, and
power management capabilities.
The MC9328MXS is equipped with an optimized feature set to provide a low-cost solution for a variety
of applications. The ARM920TDMI core speed is programmable from 0 to 100 MHz, while system speed
is programmable from 0 to 96 MHz.
The MC9328MXS provides the following benefits:
• Provides uncompromising performance in a very low-power system design
• Connectivity features include SPI, UART, USB, and SSI/I2S
• Supports a wide variety of applications including the most popular PDA designs and other portable
applications
Figure 1-1. MC9328MXS Functional Block Diagram
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1-1
ARM920T Microprocessor Core
To support a wide variety of applications, the MC9328MXS boasts a robust array of features, including
the following:
• ARM920T Microprocessor Core
• AHB to IP Bus Interfaces (AIPIs)
• External Interface Module (EIM)
• SDRAM Controller (SDRAMC)
• DPLL Clock and Power Control Module
• Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2)
• One Serial Peripheral Interface (SPI)
• Two General-Purpose 32-bit Counters/Timers
• Watchdog Timer
• Real-Time Clock/Sampling Timer (RTC)
• LCD Controller (LCDC)
• Pulse-Width Modulation (PWM) Module
• Universal Serial Bus (USB) Device
• Direct Memory Access Controller (DMAC)
• Synchronous Serial Interface (SSI1) and Inter-IC Sound (I2S) Module
• Inter-IC (I2C) Bus Module
• General-Purpose I/O (GPIO) Ports
• Bootstrap Mode
• 225-pin PBGA Package
The following sections detail the features of the MC9328MXS’s functional blocks.
1.1 ARM920T Microprocessor Core
The MC9328MXS uses the ARM920T microprocessor core which has the following features:
• 100 MHz maximum processing speed
• 16 Kbyte instruction cache and 16 Kbyte data cache
• ARM9 high performance 32-bit RISC engine
• Thumb® 16-bit compressed instruction set for a leading level of code density
• EmbeddedICE™ JTAG software debug
• 100-percent user code binary compatibility with ARM7TDMI® processors
• ARM9TDMI® core, including integrated caches, write buffers, and bus interface units, provides
CPU-cache transparency
• Advanced Microcontroller Bus Architecture (AMBA™) system-on-chip multi-master bus
interface
• Flexible CPU and bus clocking relationships including asynchronous, synchronous, and
single-clock configurations
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AHB to IP Bus Interfaces (AIPIs)
•
•
Cache locking to support mixed loads of real-time and user applications
Virtual Memory Management Unit (VMMU)
1.2 AHB to IP Bus Interfaces (AIPIs)
The MC9328MXS AIPIs provide a communication interface between the high-speed AHB bus and a
lower-speed IP bus for slow slave peripherals.
1.3 External Interface Module (EIM)
The MC9328MXS EIM features:
• Up to six chip selects for external devices, each with 16 Mbyte of address space (chip selects for
ROM support a maximum of 32 Mbyte of address space)
• Programmable protection, port size, and wait states for each chip select
• Internal/external boot ROM selection
• Selectable bus watchdog counter
• Burst support for external AMD™ or Intel® flash with 32-bit data path
• Interrupt controller to handle a maximum of 63 interrupt sources
• Vectored interrupt capability with prioritization for 16 sources
1.4 SDRAM Controller (SDRAMC)
The MC9328MXS SDRAMC features:
• Supports 4 banks of 64-, 128-, or 256-Mbit synchronous DRAMs
• Includes 2 independent chip-selects
— Up to 64 Mbyte per chip-select
— Up to four banks simultaneously active per chip-select
— JEDEC standard pinout and operation
• Supports burst reads of word (32-bit) data types
• PC100 compliant interface
— 100 MHz system clock achievable with “-8” option PC100 compliant memories
— single and fixed-length (8-word) word access
— Typical access time of 8-1-1-1 at 100 MHz
• Software configurable bus width, row and column sizes, and delays for differing system
requirements
• Built in auto-refresh timer and state machine
• Hardware supported self-refresh entry and exit which keeps data valid during system reset and
low-power modes
• Auto-powerdown (clock suspend) timer
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Clock Generation Module (CGM) and Power Control Module
1.5 Clock Generation Module (CGM) and Power Control Module
The MC9328MXS CGM and Power Control Module features:
• Digital phase-locked loops (PLLs) and clock controller for all internal clocks generation
• MCUPLL generates FCLK to the CPU from either a 32 kHz or 32.768 kHz
• System PLL generates the system clock and the 48 MHz clock for the USB from a 16 MHz or
either a 32 kHz or 32.768 kHz
• Support for three power modes for different power consumption needs: run, doze, and stop
1.6 Two Universal Asynchronous Receiver/Transmitters
(UART 1 and UART 2)
The MC9328MXS UARTs features:
• Support for serial data transmit/receive operation: 7 or 8 data bits, 1 or 2 stop bits, and
programmable parity (even, odd, or none)
• Programmable baud rates up to 1.00 MHz
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx that support autobaud
• IrDA 1.0 support
1.7 Serial Peripheral Interface (SPI)
The MC9328MXS SPI features:
• Master/slave configurable
• Up to 16-bit programmable data transfer
• 8 × 16 FIFO for both Tx and Rx data
1.8 Two General-Purpose 32-Bit Counters/Timers
The MC9328MXS General-Purpose Counters/Timers features:
• Automatic interrupt generation
• Programmable timer input/output pins
• Input capture capability with programmable trigger edge
• Output compare with programmable mode
1.9 Watchdog Timer
The MC9328MXS Watchdog Timer features:
• Programmable time out of 0.5 s to 64 s
• Resolution of 0.5 s
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Real-Time Clock/Sampling Timer (RTC)
1.10 Real-Time Clock/Sampling Timer (RTC)
The MC9328MXS RTC features:
• 32.768 kHz or 32 kHz
• Full clock features: seconds, minutes, hours, and days
• Capable of counting up to 512 days
• Minute countdown timer with interrupt
• Programmable daily alarm with interrupt
• Sampling timer with interrupt
• Once-per-second, once-per-minute, once-per-hour, and once-per-day interrupts
• Interrupt generation for digitizer sampling or keyboard debouncing
1.11 LCD Controller (LCDC)
The MC9328MXS LCDC features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Software programmable screen size (a maximum of 640 × 512 pixels) to support single (non-split)
monochrome, color STN panels, and color TFT panels
Support for 4 bpp (bits per pixel), 8 bpp, and 12 bpp for passive color panels
Support for 4 bpp, 8 bpp, 12 bpp, and 16 bpp for TFT panels
— Up to 256 colors out of a palette of 4096 for 8 bpp
— True 64K color for 16 bpp
In color STN mode, the maximum bit depth is 12 bpp
In BW mode, the maximum bit depth is 4 bpp
Up to 16 grey levels out of 16 palettes
Capable of directly driving popular LCD drivers from manufacturers including Motorola, Sharp,
Hitachi, and Toshiba
Support for data bus width for 12- or 16-bit TFT panels
Panel interface of 8-, 4-, and 2-bits, and a 1-bit wide LCD panel data bus for monochrome panels
Direct interface to Sharp® 320 × 240 HR-TFT panel
Support for logical operation between color hardware cursor and background
Uses system memory as display memory
LCD contrast control using 8-bit PWM
Support for self-refresh LCD modules
Hardware panning (soft horizontal scrolling)
1.12 Pulse-Width Modulation (PWM) Module
The MC9328MXS PWM Module features:
• 4 × 16 FIFO to minimize interrupt overhead
• 16-bit resolution
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Universal Serial Bus (USB) Device
•
Sound and melody generation
1.13 Universal Serial Bus (USB) Device
The MC9328MXS USB Device features:
•
•
•
•
•
Compliant with Universal Serial Bus Specification, revision 1.1
Up to six logical endpoints—see Table 1-1 on page 1-6
Support for isochronous communications pipes
— Frame match interrupt feature notifies the user when a specific USB frame occurs
— For DMA access, the maximum packet size for the isochronous endpoint is restricted by the
FIFO size of the endpoint
— For programmed I/O, isochronous data packets range from 0 bytes to 1023 bytes
Support for control, bulk, and interrupt pipes
— Packet sizes are limited to 8, 16, 32, or 64 bytes
— Maximum packet size depends on the FIFO size of the endpoint
Support (via a register bit) for a remote wake-up feature
Full-speed (12 MHz) operation
•
Operation can be programmed for both bus-powered and self-powered mode
•
Table 1-1. Endpoint Configurations
Endpoint
Direction
Physical FIFO Size (Bytes)
Endpoint
Configuration
Maximum Packet Size (Bytes)
0
IN and OUT
32
Control
32
1–5
IN or OUT
32 or 641
Control, interrupt, bulk,
or isochronous
User configurable: 8, 16, 32, or 64
(depending on FIFO size)
1.FIFO1 and FIFO2 are 64 bytes each; FIFO3, FIFO4, and FIFO5 are 32 bytes each.
1.14 Direct Memory Access Controller (DMAC)
The MC9328MXS DMAC features:
• 11 channels to support linear memory, 2D memory, FIFO, and End-of-Burst Enable FIFO for both
source and destination
• Support for 8-, 16-, or 32-bit FIFO port size and memory port size data transfer
• Support for big-endian and little-endian
• Configurable DMA burst length for each channel up to 16 words, 32 half-words, or 64 bytes
• Bus utilization control for a channel that is not triggered by DMA requests
• Bulk data transfer complete or transfer error interrupts provided to interrupt handler (and then to
the core)
• DMA burst time-out error terminates the DMA cycle when the burst cannot be completed within
a programmed timing period
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Synchronous Serial Interface and Inter-IC Sound (SSI/I2S) Module
•
Acknowledge signal provided to peripheral after DMA burst is complete
1.15 Synchronous Serial Interface and Inter-IC Sound (SSI/I2S)
Module
The MC9328MXS SSI/I2S Module features:
• Supports generic SSI interface for external audio chip or interprocessor communication
• Supports Philips standard Inter-IC Sound (I2S) bus for external digital audio chip interface
1.16 Inter-IC (I2C) Bus Module
The MC9328MXS I2C Bus Module features:
• Support for Philips I2C-bus standard for external digital control
• Support for 3.3 V tolerant devices
• Multiple-master operation
• Software-programmable for 1 of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven, byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation and detection
• Repeated START signal generation
• Acknowledge bit generation and detection
• Bus-busy detection
1.17 General-Purpose I/O (GPIO) Ports
The MC9328MXS GPIO ports feature:
• Interrupt capability
• 97 total I/O pins multiplexed with most dedicated functions for pin efficiency
1.18 Bootstrap Mode
The MC9328MXS Bootstrap Mode features:
• Allows user to initialize system and download program or data to system memory through UART
• Accepts execution command to run program stored in system memory
• Supports memory/register read/write operation of selectable data size of byte, half-word, or word
• Provides a 32-byte instruction buffer for ARM920T core vector table storage, instruction storage
and execution
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Power Management Features
1.19 Power Management Features
The MC9328MXS provides the following power management features:
• Programmable clock synthesizer using either a 32 kHz or 32.768 kHz crystal for full frequency
control
• Low-power stop capabilities
• Modules that can be individually shut down
• Lowest power mode control
1.20 Operating Voltage Range
The MC9328MXS operating voltages are as follows:
• I/O voltage—1.7 V to 2.0 V or 2.7 V to 3.3 V
• Internal logic voltage—1.7 V to 1.9 V
1.21 Packaging
The MC9328MXS features the package:
• 225-contact PBGA 13 mm × 13 mm package, with 0.8 mm ball pitch
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Chapter 2
Signal Descriptions and Pin Assignments
2.1 Signal and Pin Information
For information about the MC9328MXS signals and their pin assignments refer to the MC9328MXS data sheet
(document order number: MC9328MXS)).
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Signal and Pin Information
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Chapter 3
Memory Map
This chapter describes the memory maps and the chip configuration registers of the MC9328MXS.
3.1 Memory Space
The ARM920T microprocessor implements a virtual addressing mechanism. Refer to the ARM920T Memory
Management Unit in the ARM9 technical reference manual for more information on this topic.
The ARM920T processor physical memory map can be divided according to the addresses shown in Figure 3-1 on
page 3-2.
3.1.1 Memory Map
The base address referred to in each peripheral register address is the address from this table. The exact address
description of each of the peripherals is described in each peripheral section.
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3-1
Memory Space
4 KB
Base Address
64 KB
$0000 0000
1 MB
Double MAP
Image
$000F FFFF
$0010 0000
$0020 0000
AIPI1
$0020 FFFF
$0021 0000
64 KB
AIPI2
1 MB
Bootstrap
ROM
$001F FFFF
$0020 0000
156 K
Internal
Registers
$0022 6FFF
$0022 7000
868 KB
Reserved
$002F FFFF
$0030 0000
1 MB
$0021 FFFF
$0022 0000
$0022 0FFF
$0022 1000
$0022 1FFF
$0022 2000
$0022 2FFF
$0022 3000
$0022 3FFF
$0022 4000
$0022 4FFF
$0022 5000
$0022 5FFF
$0022 6000
$0022 6FFF
EIM
SDRAMC
Reserved
AITC
Reserved
Reserved
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
Reserved
Reserved
$003F FFFF
$0040 0000
$0800 0000
64 MB
CSD0
(SDRAM)
active low
$0BFF FFFF
124 MB
$0C00 0000
CSD1
(SDRAM)
active low
64 MB
Reserved
$0FFF FFFF
$1000 0000
CS0
(Flash)
active low
$07FF FFFF
$0800 0000
128 MB
$11FF FFFF
$1200 0000
External
(2x64 MB)
$0FFF FFFF
$1000 0000
$16FF FFFF
$1700 0000
112 MB
External
(1x32 MB +
5x16 MB)
912 MB
$12FF FFFF
$1300 0000
$13FF FFFF
$1400 0000
Reserved
$4FFF FFFF
$5000 0000
4 KB
ARM Test
Registers
$5000 0FFF
$5000 1000
2815 MB
+
1020 KB
$14FF FFFF
$1500 0000
$15FF FFFF
$1600 0000
Reserved
$FFFF FFFF
32 MB
16 MB
CS1
(Flash)
active low
16 MB
CS2
(Ext SRAM)
active low
16 MB
CS3
(Spare)
active low
16 MB
CS4
(Spare)
active low
16 MB
CS5
(Spare)
active low
$16FF FFFF
$0020 0000
$0020 0FFF
$0020 1000
$0020 1FFF
$0020 2000
$0020 2FFF
$0020 3000
$0020 3FFF
$0020 4000
$0020 4FFF
$0020 5000
$0020 5FFF
$0020 6000
$0020 6FFF
$0020 7000
$0020 7FFF
$0020 8000
$0020 8FFF
$0020 9000
$0020 9FFF
$0020 A000
$0020 AFFF
$0020 B000
$0020 BFFF
$0020 C000
$0020 CFFF
$0020 D000
$0020 DFFF
$0020 E000
$0020 EFFF
$0020 F000
$0020 FFFF
$0021 0000
$0021 0FFF
$0021 1000
$0021 1FFF
$0021 2000
$0021 2FFF
$0021 3000
$0021 3FFF
$0021 4000
$0021 4FFF
$0021 5000
$0021 5FFF
$0021 6000
$0021 6FFF
$0021 7000
$0021 7FFF
$0021 8000
$0021 8FFF
$0021 9000
$0021 9FFF
$0021 A000
$0021 AFFF
$0021 B000
$0021 BFFF
$0021 C000
$0021 CFFF
$0021 D000
$0021 DFFF
$0021 E000
$0021 EFFF
$0021 F000
$0021 FFFF
AIPI1
4 KB
Watchdog
4 KB
Timer1
4 KB
Timer2
4 KB
RTC
4 KB
LCDC
4 KB
UART1
4 KB
UART2
4 KB
PWM
4 KB
DMAC
4 KB
Reserved
4 KB
Reserved
4 KB
Reserved
4 KB
Reserved
4 KB
Reserved
4 KB
Reserved
4 KB
AIPI2
4 KB
Reserved
4 KB
USBD
4 KB
SPI 1
4 KB
Reserved
4 KB
Reserved
4 KB
Reserved
4 KB
I2C
4 KB
SSI
4 KB
Reserved
4 KB
Reserved
4 KB
CRM
4 KB
GPIO
4 KB
Reserved
4 KB
Reserved
4 KB
Reserved
Figure 3-1. MC9328MXS MCU Physical Memory Map (4 Gbyte)
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Memory Space
Table 3-1. MCU Memory Space (Physical Addresses)
Address
Description
Size
$0000 0000 - $000F FFFF
Double Map Image
1 Mbyte
$0010 0000 - $001F FFFF
Bootstrap ROM
1 Mbyte
$0020 0000 - $0020 0FFF
AIPI1
4 kbyte
$0020 1000 - $0020 1FFF
WatchDog
4 kbyte
$0020 2000 - $0020 2FFF
TIMER1
4 kbyte
$0020 3000 - $0020 3FFF
TIMER2
4 kbyte
$0020 4000 - $0020 4FFF
RTC
4 kbyte
$0020 5000 - $0020 5FFF
LCDC
4 kbyte
$0020 6000 - $0020 6FFF
UART1
4 kbyte
$0020 7000 - $0020 7FFF
UART2
4 kbyte
$0020 8000 - $0020 8FFF
PWM
4 kbyte
$0020 9000 - $0020 9FFF
DMAC
4 kbyte
$0020 A000 - $0020 AFFF
Reserved
4 kbyte
$0020 B000 - $0020 BFFF
Reserved
4 kbyte
$0020 C000 - $0020 CFFF
Reserved
4 kbyte
$0020 D000 - $0020 DFFF
Reserved
4 kbyte
$0020 E000 - $0020 EFFF
Reserved
4 kbyte
$0020 F000 - $0020 FFFF
Reserved
4 kbyte
$0021 0000 - $0021 0FFF
AIPI2
4 kbyte
$0021 1000 - $0021 1FFF
Reserved
4 kbyte
$0021 2000 - $0021 2FFF
USBD
4 kbyte
$0021 3000 - $0021 3FFF
SPI 1
4 kbyte
$0021 5000 - $0021 5FFF
Reserved
4 kbyte
$0021 6000 - $0021 6FFF
Reserved
4 kbyte
$0021 7000 - $0021 7FFF
I2C
4 kbyte
$0021 8000 - $0021 8FFF
SSI
4 kbyte
$0021 B000 - $0021 BFFF
CRM
4 kbyte
$0021 C000 - $0021 CFFF
GPIO
4 kbyte
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Memory Space
Table 3-1. MCU Memory Space (Physical Addresses) (continued)
Address
Description
Size
$0021 D000 - $0021 DFFF
Reserved
4 kbyte
$0021 E000 - $0021 EFFF
Reserved
4 kbyte
$0021 F000 - $0021 FFFF
Reserved
4 kbyte
$0022 0000 - $0022 0FFF
EIM
4 kbyte
$0022 1000 - $0022 1FFF
SDRAMC
4 kbyte
$0022 3000 - $0022 3FFF
AITC
4 kbyte
$0022 5000 - $0022 5FFF
Reserved
4 kbyte
$0022 6000 - $0022 6FFF
Reserved
4 kbyte
$0022 7000 - $002F FFFF
Reserved
868 kbyte
$0030 0000 - $003F FFFF
Reserved
1 Mbyte
$0040 0000 - $07FF FFFF
Reserved
124 Mbyte
$0800 0000 - $0BFF FFFF
External memory (CSD0)
64 Mbyte
$0C00 0000 - $0FFF FFFF
External memory (CSD1)
64 Mbyte
$1000 0000 - $11FF FFFF
External memory (CS0)
32 Mbyte
$1200 0000 - $12FF FFFF
External memory (CS1)
16 Mbyte
$1300 0000 - $13FF FFFF
External Memory (CS2)
16 Mbyte
$1400 0000 - $14FF FFFF
External Memory (CS3)
16 Mbyte
$1500 0000 - $15FF FFFF
External Memory (CS4)
16 Mbyte
$1600 0000 - $16FF FFFF
External Memory (CS5)
16 Mbyte
$1700 0000 - $4FFF FFFF
Reserved
912 Mbyte
$5000 0000 - $5000 0FFF
ARM920T Test Registers
4 kbyte
$5000 1000 - $FFFF FFFF
Reserved
2815 Mbyte + 1020 kbyte
3.1.2 Internal Register Space
Internal registers are located from 0x00200000 to 0x00224FFF. Some of the MC9328MXS peripherals are each
allocated 4 Kbyte starting at address $00200000 and they are connected to the AIPI1 (AHB IP Interface). Any
ARM920T core write access to these modules will experience two wait states—that is, any write access will be a
three cycle long access, and any ARM920T core read access from these modules will have one wait state—that is,
any read access will be two cycle long access. The other MC9328MXS peripherals are each allocated 4 Kbyte
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Memory Space
starting at address $00210000 and they are connected to the AIPI2. Any ARM920T core write access to these
modules will have two wait states—that is, any write access will be a three cycle long access, and any ARM920T
core read access from these modules will have one wait state—any read access will be two cycle long access.
4 kbyte address space beginning at 0x00220000 to 0x00220FFF is assigned for EIM internal registers.
4 kbyte address space beginning at 0x00221000 to 0x00221FFF is assigned for SDRAMC internal registers.
4 kbyte address space beginning at 0x00223000 to 0x00223FFF is assigned for AITC internal registers.
Within each 4 kbyte peripheral space, any number of architected registers may be defined (as outlined in the
chapter for each peripheral), and software must explicitly address them making no assumptions regarding multiple
mapping.
3.1.3 External Memory
There are 240 Mbytes of the memory map allocated for external chip access, beginning at address $08000000.
There are 8 external chip selects which are allocated 64 Mbyte each for CSD1–CSD0, 16 Mbyte each for
CS5Q–CS1, and 32 Mbyte for CS0.
3.1.4 Double Map Image
The first 1 Mbyte system address space (starting at address $0) is defined as double map image space. This address
space is mapped to the first 1 Mbyte of boot ROM upon power up. In MC9328MXS the boot ROM can be either
SyncFlash, CS0, or Bootstrap ROM. After system power up, reading or writing to the double map space
($0000,0000 to $000F,FFFF) is the same as reading or writing to the first 1 Mbyte of the selected boot ROM which
is controlled by the configuration of BOOT [3:0] input pins.
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Internal Registers
3.2 Internal Registers
The internal registers in the MC9328MXS are listed in Table 3-2.
Table 3-2. Internal Registers Sorted by Address
Module Name
Address
Name
Description
USBD
0x0021213C
USB_EP5_LWFP
Endpoint 5 Last Write Frame Pointer Register
USBD
0x00212140
USB_EP5_FALRM
Endpoint 5 FIFO Alarm Register
USBD
0x00212144
USB_EP5_FRDP
Endpoint 5 FIFO Read Pointer Register
USBD
0x00212148
USB_EP5_FWRP
Endpoint 5 FIFO Write Pointer Register
SPI 1
0x00213000
RXDATAREG1
SPI 1 Rx Data Register
SPI 1
0x00213004
TXDATAREG1
SPI 1 Tx Data Register
SPI 1
0x00213008
CONTROLREG1
SPI 1 Control Register
SPI 1
0x0021300C
INTREG1
SPI 1
0x00213010
TESTREG1
SPI 1
0x00213014
PERIODREG1
SPI 1
0x00213018
DMAREG1
SPI 1
0x0021301C
RESETREG1
I2C
0x00217000
IADR
I2C Address Register
I2C
0x00217004
IFDR
I2C Frequency Divider Register
I2C
0x00217008
I2CR
I2C Control Register
I2C
0x0021700C
I2CSR
I2C Status Register
I2C
0x00217010
I2DR
I2C Data I/O Register
SSI
0x00218000
STX
SSI Transmit Data Register
SSI
0x00218004
SRX
SSI Receive Data Register
SSI
0x00218020
SFCSR
SSI
0x00218028
SOR
PLLCLK
0x0021B000
CSCR
PLLCLK
0x0021B004
MPCTL0
MCU PLL Control Register 0
PLLCLK
0x0021B0008
MPCTL1
MCU PLL and System Clock Control Register 1
SPI 1 Interrupt Control/Status Register
SPI 1 Test Register
SPI 1 Sample Period Control Register
SPI 1 DMA Control Register
SPI 1 Soft Reset Register
SSI FIFO Control/Status Register
SSI Option Register
Clock Source Control Register
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Internal Registers
Table 3-2. Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
PLLCLK
0x0021B00C
SPCTL0
System PLL Control Register 0
PLLCLK
0x0021B010
SPCTL1
System PLL Control Register 1
PLLCLK
0x0021B020
PCDR
AITC
0x00223044
FIVECSR
Fast Interrupt Vector and Status Register
AITC
0x00223048
INTSRCH
Interrupt Source Register High
AITC
0x0022304C
INTSRCL
Interrupt Source Register Low
AITC
0x00223050
INTFRCH
Interrupt Force Register High
AITC
0x00223054
INTFRCL
Interrupt Force Register Low
AITC
0x00223058
NIPNDH
Normal Interrupt Pending Register High
AITC
0x0022305C
NIPNDL
Normal Interrupt Pending Register Low
AITC
0x00223060
FIPNDH
Fast Interrupt Pending Register High
AITC
0x00223064
FIPNDL
Fast Interrupt Pending Register Low
Peripheral Clock Divider Register
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Chapter 4
ARM920T Processor
This chapter describes the operational features of the ARM920T™ high-performance processor that includes an
overall summary of both the ARM920T processor core and the Thumb® instruction set as well as the operational
modes. For detailed technical and programming information about the ARM920T processor refer to the ARM920T
Technical Reference Manual (ARM Limited: 2001, order number DDI 0151C).
4.1 Introduction
The ARM920T processor is a high-performance 32-bit RISC integer processor macrocell combining an
ARM9TDMI™ core with:
•
16 kbyte instruction and 16 kbyte data caches
•
Instruction and data Memory Management Units (MMUs)
•
Write buffer
•
AMBA™ (Advanced Microprocessor Bus Architecture) bus interface
•
Embedded Trace Macrocell (ETM) interface
An enhanced ARM® architecture v4 MMU implementation provides translation and access permission checks for
instruction and data addresses. The ARM920T high-performance processor solution gives considerable savings in
chip complexity and area, chip system design, and power consumption. The ARM920T processor is 100% user
code binary compatible with ARM7TDMI®, and backwards compatible with the ARM7™ Thumb® Family and
the StrongARM® processor families, giving designers software-compatible processors with a range of
price/performance points from 60 MIPS to 200+ MIPS.
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ARM920T Macrocell
Figure 4-1. ARM920T Core Functional Block Diagram
4.2 ARM920T Macrocell
The ARM920T macrocell is based on the ARM9TDMI™ Harvard architecture processor core, with an efficient
5-stage pipeline. The architecture of the processor core or integer unit is described in more detail later in this
chapter.
To reduce the effect of main memory bandwidth and latency on performance, the ARM920T processor includes:
•
Instruction cache
•
Data cache
•
MMU
•
TLBs
•
Write buffer
•
Physical address TAG RAM
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ARM920T Macrocell
4.2.1 Caches
Two 16 kbyte caches are implemented, one for instructions, the other for data, both with an 8-word line size. A
32-bit data bus connects each cache to the ARM9TDMI core allowing a 32-bit instruction to be fetched and fed
into the instruction Decode stage of the pipeline at the same time as a 32-bit data access for the Memory stage of
the pipeline.
4.2.2 Cache Lock-Down
Cache lock-down is provided to allow critical code sequences to be locked into the cache to ensure predictability
for real-time code. The cache replacement algorithm can be selected by the operating system as either pseudo
random or round-robin. Both caches are 64-way set associative. Lock-down operates on a per-set basis.
4.2.3 Write Buffer
The ARM920T processor also incorporates a 16-entry write buffer, to avoid stalling the processor when writes to
external memory are performed.
4.2.4 PATAG RAM
The ARM920T processor implements PATAG RAM to perform write-backs from the data cache. The physical
address of all the lines held in the data cache is stored by the PATAG memory, removing the need for address
translation when evicting a line from the cache.
4.2.5 MMUs
The standard ARM920T processor implements an enhanced ARM v4 memory management unit (MMU) to
provide translation and access permission checks for the instruction and data address ports of the ARM9TDMI
core.
The MMU features are:
•
Standard ARM9™ v4 MMU mapping sizes, domains, and access protection scheme
•
Mapping sizes are 1 Mbyte sections, 64 kbyte large pages, 4 kbyte small pages, and new 1 kbyte tiny pages
•
Access permissions for sections
•
Access permissions for large pages and small pages can be specified separately for each quarter of the page
(these quarters are called subpages)
•
16 domains implemented in hardware
•
64-entry instruction TLB and 64-entry data TLB
•
Hardware page table walks
•
Round-robin replacement algorithm (also called cyclic)
4.2.6 System Controller
The system controller oversees the interaction between the instruction and data caches and the Bus Interface Unit.
It controls internal arbitration between the blocks and stalls appropriate blocks when required.
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4-3
ARMv4T Architecture
The system controller arbitrates between instruction and data access to schedule single or simultaneous requests to
the MMUs and the Bus Interface Unit. The system controller receives acknowledgement from each resource to
allow execution to continue.
The physical address of all the lines held in the data cache is stored by the PATAG memory, removing the need for
address translation when evicting a line from the cache.
4.2.7 Control Coprocessor (CP15)
The CP15 allows configuration of the caches, the write buffer, and other ARM920T processor options.
Several registers within CP15 are available for program control, providing access to features such as:
•
Invalidate whole TLB using CP15
•
Invalidate TLB entry, selected by modified virtual address, using CP15
•
Independent lock-down of instruction TLB and data TLB using CP15 register 10
•
Big or little-endian operation
•
Low-power state
•
Memory partitioning and protection
•
Page table address
•
Cache and TLB maintenance operations
4.3 ARMv4T Architecture
The following sections summarize the registers and instruction sets of the ARMv4T architecture.
4.3.1 Registers
The ARM920T processor core consists of a 32-bit data path and associated control logic. This data path contains
31 general purpose registers, coupled to a full shifter, Arithmetic Logic Unit, and multiplier. At any one time 16
registers are visible to the user. The remainder are synonyms used to speed up exception processing. Register 15 is
the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction.
R14 holds the return address after a subroutine call. R13 is used (by software convention) as a stack pointer.
4.3.2 Modes and Exception Handling
All exceptions have banked registers for R14 and R13. After an exception, R14 holds the return address for
exception processing. This address is used both to return after the exception is processed and to address the
instruction that caused the exception.
R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast
interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without the need to save or restore
these registers.
A seventh processing mode, System mode, does not have any banked registers. It uses the User mode registers.
System mode runs tasks that require a privileged processor mode and allows them to invoke all classes of
exceptions.
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Four Classes of Instructions
4.3.3 Status Registers
All other processor states are held in status registers. The current operating processor status is in the Current
Program Status Register (CPSR). The CPSR holds:
•
Four ALU flags (Negative, Zero, Carry, and Overflow)
•
Two interrupt disable bits (one for each type of interrupt)
•
A bit to indicate ARM9 or Thumb execution
•
Five bits to encode the current processor mode
All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task
immediately before the exception occurred.
4.3.4 Exception Types
ARM9TDMI core supports five types of exception, and a privileged processing mode for each type. The types of
exceptions are:
•
Fast interrupt (FIQ)
•
Normal interrupt (IRQ)
•
Memory aborts (used to implement memory protection or virtual memory)
•
Attempted execution of an undefined instruction
•
Software interrupts (SWIs)
4.3.5 Conditional Execution
All ARM9 instructions (with the exception of BLX) are conditionally executed. Instructions optionally update the
four condition code flags (Negative, Zero, Carry, and Overflow) according to their result. Subsequent instructions
are conditionally executed according to the status of flags. Fifteen conditions are implemented.
4.4 Four Classes of Instructions
The ARM9 and Thumb instruction sets can be divided into four broad classes of instruction:
•
Data processing instructions
•
Load and store instructions
•
Branch instructions
•
Coprocessor instructions
4.4.1 Data Processing Instructions
The data processing instructions operate on data held in general purpose registers. Of the two source operands, one
is always a register. The other has two basic forms:
•
An immediate value
•
A register value optionally shifted
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Freescale Semiconductor
4-5
Four Classes of Instructions
If the operand is a shifted register, the shift amount might have an immediate value or the value of another register.
Four types of shift can be specified. Most data processing instructions can perform a shift followed by a logical or
arithmetic operation. Multiply instructions come in two classes:
•
Normal, 32-bit result
•
Long, 32-bit result variants
Both types of multiply instruction can optionally perform an accumulate operation.
4.4.2 Load and Store Instructions
The second class of instruction is load and store instructions. These instructions come in two main types:
•
Load or store the value of a single register
•
Load and store multiple register values
Load and store single register instructions can transfer a 32-bit word, a 16-bit halfword and an 8-bit byte between
memory and a register. Byte and halfword loads might be automatically zero extended or sign extended as they are
loaded. Swap instructions perform an atomic load and store as a synchronization primitive.
4.4.2.1 Addressing Modes
Load and store instructions have three primary addressing modes:
•
Offset
•
Pre-indexed
•
Post-indexed
They are formed by adding or subtracting an immediate or register based offset to or from a base register.
Register-based offsets can also be scaled with shift operations. Pre-indexed and post-indexed addressing modes
update the base register with the base plus offset calculation. As the PC is a general purpose register, a 32-bit value
can be loaded directly into the PC to perform a jump to any address in the 4 Gbyte memory space.
4.4.2.2 Block Transfers
Load and store multiple instructions perform a block transfer of any number of the general purpose registers to or
from memory. Four addressing modes are provided:
•
Pre-increment addressing
•
Post-increment addressing
•
Pre-decrement addressing
•
Post-decrement addressing
The base address is specified by a register value (that can be optionally updated after the transfer). As the
subroutine return address and the PC values are in general-purpose registers, very efficient subroutine calls can be
constructed.
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Freescale Semiconductor
The ARM9 Instruction Set
4.4.3 Branch Instructions
As well as allowing any data processing or load instruction to change control flow (by writing the PC) a standard
branch instruction is provided with 24-bit signed offset, allowing forward and backward branches of up to 32
Mbyte.
4.4.3.1 Branch with Link
There is a Branch with Link (BL) that allows efficient subroutine calls. BL preserves the address of the instruction
after the branch in R14 (the Link Register, or LR). This allows a move instruction to put the LR in to the PC and
return to the instruction after the branch.
The third type of branch (BX and BLX) switches between ARM9 and Thumb instruction sets optionally with the
return address preserving link option.
4.4.4 Coprocessor Instructions
There are three types of coprocessor instructions:
•
Coprocessor data processing instructions invoke a coprocessor-specific internal operation
•
Coprocessor register transfer instructions allow a coprocessor value to be transferred to or from an
ARM920T processor register
•
Coprocessor data transfer instructions transfer coprocessor data to or from memory, where the ARM920T
calculates the address of the transfer
4.5 The ARM9 Instruction Set
The instruction set used by the ARM920T processor is summarized in Table 4-1.
Table 4-1. ARM920T Instruction Set
Mnemonic
Operation
Mnemonic
Operation
MOV
Move
MVN
Move Not
ADD
Add
ADC
Add with Carry
SUB
Subtract
SBC
Subtract with Carry
RSB
Reverse Subtract
RSC
Reverse Subtract with Carry
CMP
Compare
CMN
Compare Negated
TST
Test
TEQ
Test Equivalence
AND
Logical AND
BIC
Bit Clear
FOR
Logical Exclusive OR
ORR
Logical (inclusive) OR
MUL
Multiply
MLA
Multiply Accumulate
SMULL
Sign Long Multiply
SMLAL
Signed Long Multiply Accumulate
UMULL
Unsigned Long Multiply
UMLAL
Unsigned Long Multiply Accumulate
CLZ
Count Leading Zeroes
BKPT
Breakpoint
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4-7
The ARM Thumb Instruction Set
Table 4-1. ARM920T Instruction Set (continued)
Mnemonic
Operation
Mnemonic
Operation
MRS
Move From Status Register
MSR
Move to Status Register
B
Branch
–
–
BL
Branch and Link
BLX
Branch and Link and Exchange
BX
Branch and Exchange
SWI
Software Interrupt
LDR
Load Word
STR
Store Word
LDRH
Load Halfword
STRH
Store Halfword
LDRB
Load Byte
STRB
Store Byte
LDRSH
Load Signed Halfword
LDRSB
Load Signed Byte
LDMIA
Load Multiple
STMIA
Store Multiple
SWP
Swap Word
SWPB
Swap Byte
CDP
Coprocessor Data Processing
–
–
MRC
Move From Coprocessor
MCR
Move to Coprocessor
LDC
Load To Coprocessor
STC
Store From Coprocessor
4.6 The ARM Thumb Instruction Set
The ARM Thumb instruction set is summarized in Table 4-2.
Table 4-2. ARM Thumb Instruction Set
Mnemonic
Operation
Mnemonic
Operation
MOV
Move
MVN
Move Not
ADD
Add
ADC
Add with Carry
SUB
Subtract
SBC
Subtract with Carry
RSB
Reverse Subtract
RSC
Reverse Subtract with Carry
CMP
Compare
CMN
Compare Negated
TST
Test
NEG
Negate
AND
Logical AND
BIC
Bit Clear
FOR
Logical Exclusive OR
ORR
Logical (inclusive) OR
LSL
Logical Shift Left
LSR
Logical Shift Right
ASR
Arithmetic Shift Right
ROR
Rotate Right
MUL
Multiply
BKPT
Breakpoint
B
Unconditional Branch
Bcc
Conditional Branch
BL
Branch and Link
BLX
Branch and Link and Exchange
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Freescale Semiconductor
The ARM Thumb Instruction Set
Table 4-2. ARM Thumb Instruction Set (continued)
Mnemonic
Operation
Mnemonic
Operation
BX
Branch and Exchange
SWI
Software Interrupt
LDR
Load Word
STR
Store Word
LDRH
Load Halfword
STRH
Store Halfword
LDRB
Load Byte
STRB
Store Byte
LDRSH
Load Signed Halfword
LDRSB
Load Signed Byte
LDMIA
Load Multiple
STMIA
Store Multiple
PUSH
Push Registers to stack
POP
Pop Registers from stack
4.6.1 ARM920T Modes and Registers
The modes and registers of the ARM920T processor are shown in Table 4-3.
Table 4-3. Register Availability by Mode
User and
System Modes
Supervisor
Mode
Abort Mode
Undefined
Mode
Interrupt Mode
Fast Interrupt
Mode
R0
R0
R0
R0
R0
R0
R1
R1
R1
R1
R1
R1
R2
R2
R2
R2
R2
R2
R3
R3
R3
R3
R3
R3
R4
R4
R4
R4
R4
R4
R5
R5
R5
R5
R5
R5
R6
R6
R6
R6
R6
R6
R7
R7
R7
R7
R7
R7
R8
R8
R8
R8
R8
R8_FIQ
R9
R9
R9
R9
R9
R9_FIQ
R10
R10
R10
R10
R10
R10_FIQ
R11
R11
R11
R11
R11
R11_FIQ
R12
R12
R12
R12
R12
R12_FIQ
R13
R13_SVC
R13_ABORT
R13_UNDEF
R13_IRQ
R13_FIQ
R14
R14_SVC
R14_ABORT
R14_UNDEF
R14_IRQ
R14_FIQ
PC
PC
PC
PC
PC
PC
CPSR
CPSR
CPSR
CPSR
CPSR
CPSR
SPSR_SVC
SPSR_ABORT
SPSR_UNDEF
SPSR_IRQ
SPSR_FIQ
= Mode-specific banked registers
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The ARM Thumb Instruction Set
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Freescale Semiconductor
Chapter 5
Embedded Trace Macrocell (ETM)
The MC9328MXS is equipped with an ARM9 Embedded Trace Macrocell™ (ETM9) module for real time
debugging which is a great help to a system designer because the MC9328MXS is a highly integrated processor, a
very limited number of pins are available for debug purposes. ETM signals in MC9328MXS are multiplexed with
other function pins. This chapter contains a brief summary of the ETM features, for details of ETM operation,
please refer to the ETM9 Technical Reference Manual Rev.2a (ARM Limited: 2001, order number DDI0157E).
5.1 Introduction to the ETM
The ETM provides instruction and data trace for the ARM9™ family of microprocessors. This document describes
the interface between an ARM Thumb® family processor and the ETM. For details of the interface between an
ARM7™ processor and ETM7, refer to the ETM7 Technical Reference Manual Rev.1 (ARM Limited: 2001, order
number DDI0158D). The block diagram of the ETM is shown in Figure 5-1.
Figure 5-1. ETM Block Diagram
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Freescale Semiconductor
5-1
Programming and Reading ETM Registers
5.2 Programming and Reading ETM Registers
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit shift
register comprising:
•
32-bit data field
•
7-bit address field
•
A read/write bit
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field,
and 1 into the read/write bit.
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field
is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.
For further details of ETM registers, see the Embedded Trace Macrocell specification.
5.3 Pin Configuration for ETM
The ETM module uses 13 pins on the MC9328MXS. These pins are multiplexed with other functions on the
device, and must be configured for ETM operation. Table 5-1 identifies the pin configuration, however, only the 5
pins of the 13 that are multiplexed are shown.
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 25.5.1, “Data Direction Registers,” on
page 25-8 for details.
Table 5-1. ETM Pin Configuration
Pin
Setting
Configuration Procedure
ETMTRACESYNC
Alternate function of
GPIO Port A [0]
Clear bit 0 of Port A GPIO In Use Register (GIUS_A)
Set bit 0 of Port A General Purpose Register (GPR_A)
ETMTRACECLK
Alternate function of
GPIO Port A [31]
Clear bit 31 of Port A GPIO In Use Register (GIUS_A)
Set bit 31 of Port A General Purpose Register (GPR_A)
ETMPIPESTAT [2:0]
Alternate function of
GPIO Port A [30:28]
Clear bits [30:28] of Port A GPIO In Use Register (GIUS_A)
Set bits [30:28] of Port A General Purpose Register (GPR_A)
ETMTRACEPKT [7:4]
Alternate function of
GPIO Port A [20:17]
Clear bits [20:17] of Port A GPIO In Use Register (GIUS_A)
Set bits [20:17] of Port A General Purpose Register (GPR_A)
ETMTRACEPKT [3:0]
Alternate function of
GPIO Port A [27:24]
Clear bits [27:24] of Port A GPIO In Use Register (GIUS_A)
Set bits [27:24] of Port A General Purpose Register (GPR_A)
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Freescale Semiconductor
Chapter 6
Reset Module
The reset module controls or distributes all of the system reset signals used by the MC9328MXS. This chapter
provides a detailed description of the operation of this module.
6.1 Functional Description of the Reset Module
A simplified block diagram of the reset module is shown in Figure 6-1. The reset module generates two distinct
events—a global reset and an ARM920T processor reset.
CORE_TRST
TRST
RESET_POR
300 ms
Counter
POR
7-Cycle
Stretcher
RESET_DRAM
CLK32
CLK32
14-Cycle
Stretcher
Sync
Logic
HARD_ASYN_RESET
CLK32
HCLK
RESET_IN
Watchdog
Timer
4-Cycle
Qualifier
Rising
Edge
Detector
DRAM
Controller
ARM9/
Watchdog
Timer
RESET_OUT
HRESET
CLK32
JTAG/ETM
All Modules
Except
Watchdog
Timer
IP Bus
RSR
WAT_RESET
Figure 6-1. Reset Module Block Diagram
6.1.1 Global Reset
A global reset simultaneously asserts three reset signals: HRESET, RESET_DRAM, and CORE_TRST. These
signals remain asserted for 14 CLK32 cycles. The RESET_DRAM signal is deasserted 7 CLK32 cycles before
HRESET and HARD_ASYN_RESET. This 7-cycle period provides the DRAM with time to execute any
necessary self-refresh operations. The timing diagram in Figure 6-2 on page 6-2 shows the relationship of the reset
signal timings. See Table 6-1 for reset module signal and pin definitions.
There is one source capable of generating a global reset: A high condition on the POR pin for at least 4 × 32 kHz
clocks when the 32 kHz crystal oscillator is running.
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Freescale Semiconductor
6-1
Functional Description of the Reset Module
The following signal conditions are not capable of generating a global reset, however they reset the ARM920T
core:
•
An external qualified low condition on the RESET_IN pin
•
A low condition on WAT_RESET
NOTE:
Due to the asynchronous nature of the RESET signal, the time period required to
qualify the signal may vary, and the HRESET timing relative to the rising edge of
RESET is also affected. A RESET signal shorter than 3 CLK32 cycles will not be
qualified, a RESET signal equal to or longer than 4 CLK32 cycles will always be
qualified, and any period length that is more than 3 and less than 4 CLK32 cycles
is undefined.
IMPORTANT:
POR is the reset signal for all the reset module flip-flops. For this reason, an
external reset signal is qualified if it lasts more than 4 CLK32 cycles when POR is
deasserted.
POR
RESET_POR
300 ms
7 cycles @ CLK32
RESET_DRAM
14 cycles @ CLK32
HRESET
(RESET_OUT)
CLK32
HCLK
Figure 6-2. DRAM and Internal Reset Timing Diagram
6.1.2 ARM920T Processor Reset
Any qualified global reset signal resets the ARM920T processor and all related peripherals to their default state.
After the internal reset is deasserted, the ARM920T processor begins fetching code from the internal bootstrap
ROM, sync flash, or CS0 space. The memory location of the fetch depends on the configuration of the BOOT pins
on the rising edge of HRESET (see Section 8.2, “System Boot Mode Selection,” on page 8-7).
MC9328MXS Reference Manual, Rev. 1.1
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Freescale Semiconductor
Programming Model
Table 6-1. Reset Module Pin and Signal Descriptions
Signal Name
Direction
Signal Description
CLK32
IN
32 kHz Clock—A 32 kHz clock signal derived from the input crystal oscillator circuit in the
PLL.
POR
IN
Power-On Reset—An internal active high Schmitt trigger signal from the POR pin. The
POR signal is normally generated by an external RC circuit designed to detect a power-up
event.
RESET
IN
Reset—An external active low Schmitt trigger signal from the RESET_IN pin. When
this signal goes active, all modules (except the reset module and the clock control
module) are reset.
TRST
IN
Test Reset Pin—An external active low signal from the TRST pin. The Test Reset Pin is
used to asynchronously initialize the JTAG controller.
WAT_RESET
IN
Watchdog Timer Reset—An active low signal generated by the watchdog timer when a
time-out period has expired.
CORE_TRST
OUT
Core Test Reset—An active low signal that resets the JTAG module and the ETM.
HARD_ASYN_RESET
OUT
Hard Asynchronous Reset—An active low signal that resets all peripheral modules
except the watchdog timer module. The rising edge of this signal is synchronous with
HCLK.
HRESET
OUT
Hard Reset—An active low signal that resets the ARM920T processor and the watchdog
timer module.This signal is deasserted during the low phase of HCLK. This signal also
appears on the RESET_OUT pin of the MC9328MXS.
RESET_DRAM
OUT
DRAM Reset—An active low signal that resets the DRAM controller.
6.2 Programming Model
The Reset Source Register (RSR), the only register in the reset module, can be written to or read by the ARM920T
processor through the IP bus interface.
6.2.1 Reset Source Register (RSR)
The Reset Source Register is a 16-bit read-only register used by the ARM920T processor to determine the source
of the last MC9328MXS. hardware reset. The source of the last hardware reset is defined in Table 6-2 and
Table 6-3 on page 6-4.
If several sources’ signals overlap and if the signals are released during the same CLK32 cycle (which also causes
the assertion of the RESET_OUT signal), only the highest-priority event is registered by the RSR using the
following priority order:
1. POR signal
2. Qualified external reset signal
3. Watchdog signal
Otherwise, the last signal that is released is honored.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
6-3
Programming Model
RSR
Addr
0x0021B800
Reset Source Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
WDR
EXR
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 6-2. RSR Register Description
Name
Description
Settings
Reserved
Bits 31–2
Reserved—These bits are reserved and should read 0.
WDR
Bit 1
Watchdog Reset—Indicates whether the last reset
was caused by a Watchdog count expiration.
0 = Reset was NOT a Watchdog count expiration
1 = Reset WAS a Watchdog count expiration
EXR
Bit 0
External Reset—Indicates whether the last reset was
caused by a RESET_IN pin assertion.
0 = Reset was NOT a RESET_IN pin assertion
1 = Reset WAS a RESET_IN pin assertion
Table 6-3. Hardware Reset Source Matrix
Source
WDR
EXR
POR
0
0
Qualified external reset
0
1
Watchdog time-out
1
0
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Freescale Semiconductor
Chapter 7
AHB to IP Bus Interface (AIPI)
7.1 Overview
This chapter provides an overview of the R-AHB to IP bus interface (AIPI). The AIPI module in the MC9328MXS
acts as an interface between the R-AHB (Reduced ARM Advanced High-performance Bus) and lower bandwidth
peripherals.
7.1.1 Features
The AIPI provides the following features:
•
All peripheral read transactions require a minimum of two system clocks (R-AHB side) and all write
transactions require a minimum of three system clocks (R-AHB side).
•
Support of 8-bit, 16-bit, and 32-bit IP bus peripherals.
•
Byte, half word, and word read and write are supported to and from each peripheral in both big and little
endian mode.
•
Support of multi-cycle accesses (16-bit operations to 8-bit peripherals, and 32-bit operations to 16-bit and
8-bit peripherals).
•
Ability to restrict user to limit access to peripherals in their natural size only.
•
Support of 15 external IP bus peripherals. Muxiplexers are incorporated to support the 15 separate read data
buses, and the transfer wait and transfer error from peripherals.
•
A watchdog timer is provided to time-out peripheral access if operation does not terminate with 512 clock
cycles.
•
Use of a single asynchronous reset and one global clock with both edges.
•
The AIPI module is implemented using MUX-D scan methodology for testability.
7.1.2 General Information
The AIPI is the interface between the R-AHB and on-chip IP bus peripherals as shown in Figure 7-1 on page 7-2.
IP bus peripherals are modules that contain readable/writable control and status registers. The R-AHB master reads
and writes these registers through the AIPI. The AIPI generates module enables, the module address, transfer
attributes, byte enables and write data as inputs to the IP bus peripherals. The AIPI captures read data (qualified by
IPS_XFR_WAIT) from the IP bus interface and drives it on the R-AHB. The AIPI module terminates the transfer
by asserting AIPI_HREADY_OUT.
The register maps of all IP bus peripherals are located on 4096 byte boundaries. Each IP bus peripheral is allocated
one 4-kbyte block (minimum block size) of the memory map, configured as 1024 32-bit internal registers (or 2048
16-bit internal registers, or 4096 8-bit internal registers), activated by one of 15 module enables from the AIPI. Up
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
7-1
Overview
to 15 IP bus peripherals may be implemented, occupying contiguous blocks of 4 kbytes, for a total of 60 kbytes.
The exact address assignment for the IP bus peripherals is system dependent, and is defined in the system
specification. Each IP bus peripheral will select its internal registers based on the address driven on the IPS_ADDR
signals.
The AIPI is responsible for telling the IP bus peripherals if the access is in supervisor or user mode. The AIPI may
block user mode accesses to certain IP bus peripherals or it may allow the individual IP bus peripherals to
determine if user mode accesses are allowed. Please see Section 7.2, “Programming Model,” for more
information.
The AIPI supports multi-cycle accesses to IP bus peripherals when the R-AHB master requests data transfers that
are larger than the targeted IP bus peripheral’s data bus width. Table 7-1 through Table 7-4 provides more
information on both single-cycle and multi-cycle accesses. For data access that are larger than the target IP bus
peripheral, the AIPI will duplicated the data across all the byte lanes on the AHB, i.e. for a word read from 8 bit
peripheral, the same data read will appear on byte lanes [31:24, [23:16], [15:8] and [7:0]. Similarly for a byte write
to the peripheral, the core will duplicate the same byte over the byte lanes of the AHB for the write operation.
haddr[16:0]
HWDATA[31:0]
IPS_WDATA[31:0]
HWDATA[31:0]
IPS_RDATA[15:1][31:
AIPI_HRDATA[31:0]
IPS_MODULE_EN[15:
HPROTL
IPS_ADDR1[11:1]
HTRANSL
IPS_BYTE_15_8
HSIZE[1:0]
AIPI
IPS_BYTE_23_16
HREADY_IN
IPS_BYTE_31_24
AIPI_HRESP[1:0]
IPS_RWB
IP BUS SIGNALS
IPS_BYTE_7_0
HWRITE
AIPI_HREADY_OUT
IPS_XFR_WAIT[15:1]
HCLK
IPS_XFR_ERR[15:1]
HCLK
IPS_SUPERVISOR_A
HSEL_AIPI
IPS_GATED_CLK_EN[1
HRESET
BIGEND_IN
Figure 7-1. AIPI Interface
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7-2
Freescale Semiconductor
Overview
_aipi_16
aipi
aipi_core
hwdata[31:0]
ips_wdata[31:0]
aipi_write_data_path
aipi_current_state
ips_rwb
haddr[16:0]
hsize[1:0]
ips_supervisor_access
hready_in
ips_addr[11:0]
ips_module_en[15:1]
htransl
ips_byte_31_24
hprot
aipi_control
ips_byte_23_16
hsel
ips_byte_15_8
hclk
ips_byte_7_0
hclk
ips_gated_clk_en[15:1]
aipi_hresp[1:0]
hreset
aipi_hready_out
bigend_in
aipi_hrdata
[31:0]
hwrite
aipi_read_data_path
aipi_register_data
aipi_par_en
aipi_psr_err
aipi_register_err
aipi_registers
aipi_register_wait
IP
IP bus_peripheral_size
ips_xfr_wait
aipi_timeout
ips_xfr_err
ips_rdata[31:0]
ips_rdata[15:1][31:0]
aipi_watchdog
aipi_start_transfer
aipi_data_mux
aipi_ip_decode
aipi_xfr_mux
mux_select
[3:0]
ips_xfr_wait[15:1]
ips_xfr_err[15:1]
Figure 7-2. Block Diagram of the AIPI Module
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
7-3
Overview
Table 7-1. R-AHB to IP Bus Interface Operation (Big Endian—Read Operation)
Transfer
Size
Byte
Half Word
haddr
[1]
[0]
IP
Bus
Size
0
0
8-bit
0
Active Bus Section (IP Bus to R-AHB)
[1]
[0]
R-AHB [31:24]
R-AHB [23:16]
R-AHB [15:8]
R-AHB [7:0]
0
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
0
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
0
1
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
1
1
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
0
0
X
ips_rdata[15:8]
ips_rdata[7:0]
–
–
0
1
ips_rdata[15:8]
ips_rdata[7:0]
–
–
1
0
–
–
ips_rdata[15:8]
ips_rdata[7:0]
1
1
–
–
ips_rdata[15:8]
ips_rdata[7:0]
0
0
ips_rdata[31:24]
–
–
–
0
1
–
ips_rdata[23:16]
–
–
1
0
–
–
ips_rdata[15:8]
–
1
1
–
–
–
ips_rdata[7:0]
0
NA
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
X
ips_rdata[15:8]
ips_rdata[7:0]
ips_rdata[15:8]
ips_rdata[7:0]
1
X
ips_rdata[15:8]
ips_rdata[7:0]
ips_rdata[15:8]
ips_rdata[7:0]
X
X
ips_rdata[31:24]
ips_rdata[23:16]
–
–
X
X
–
–
ips_rdata[15:8]
ips_rdata[7:0]
0
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
X
ips_rdata[15:8]
ips_rdata[7:0]
ips_rdata[15:8]
ips_rdata[7:0]
1
X
ips_rdata[15:8]
ips_rdata[7:0]
ips_rdata[15:8]
ips_rdata[7:0]
X
X
ips_rdata[31:24]
ips_rdata[23:16]
ips_rdata[15:8]
ips_rdata[7:0]
16-bit
1
32-bit
8-bit
0
1
0
16-bit
1
0
32-bit
1
NA
X
X
1
Word
ips_addr
NA
8-bit
1
16-bit
32-bit
X
X
X
MC9328MXS Reference Manual, Rev. 1.1
7-4
Freescale Semiconductor
Overview
Table 7-2. R-AHB to IP Bus Interface Operation (Big Endian—Write Operation)
Transfer
Size
Byte
Half
Word
haddr
[1]
[0]
IP
Bus
Size
0
0
8-bit
0
Active Bus Section (R-AHB to IP Bus)
[1]
[0]
R-AHB [31:24]
R-AHB [23:16]
R-AHB [15:8]
R-AHB [7:0]
0
0
ips_wdata[7:0]
–
–
–
1
0
1
–
ips_wdata[7:0]
–
–
1
0
1
0
–
–
ips_wdata[7:0]
–
1
1
1
1
–
–
–
ips_wdata[7:0]
0
0
0
X
ips_wdata[15:8]
–
–
–
0
1
–
ips_wdata[7:0]
–
–
1
0
–
–
ips_wdata[15:8]
–
1
1
–
–
–
ips_wdata[7:0]
0
0
ips_wdata[31:24]
–
–
–
0
1
–
ips_wdata[23:16]
–
–
1
0
–
–
ips_wdata[15:8]
–
1
1
–
–
–
ips_wdata[7:0]
0
NA
0
ips_wdata[7:0]
–
–
–
1
–
ips_wdata[7:0]
–
–
0
–
–
ips_wdata[7:0]
–
1
–
–
–
ips_wdata[7:0]
0
X
ips_wdata[15:8]
ips_wdata[7:0]
–
–
1
X
–
–
ips_wdata[15:8]
ips_wdata[7:0]
X
X
ips_wdata[31:24]
ips_wdata[23:16]
–
–
X
X
–
–
ips_wdata[15:8]
ips_wdata[7:0]
0
0
ips_wdata[7:0]
–
–
–
1
–
ips_wdata[7:0]
–
–
0
–
–
ips_wdata[7:0]
–
1
–
–
–
ips_wdata[7:0]
0
X
ips_wdata[15:8]
ips_wdata[7:0]
–
–
1
X
–
–
ips_wdata[15:8]
ips_wdata[7:0]
X
X
ips_wdata[31:24]
ips_wdata[23:16]
ips_wdata[15:8]
ips_wdata[7:0]
16-bit
1
32-bit
8-bit
0
1
0
16-bit
1
0
32-bit
1
NA
X
X
1
Word
ips_addr
NA
8-bit
1
16-bit
32-bit
X
X
X
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
7-5
Overview
Table 7-3. R-AHB to IP Bus Interface Operation (Little Endian—Read Operation)
Transfer
Size
Byte
Half
Word
haddr
[1]
[0]
IP
Bus
Size
0
0
8-bit
0
Active Bus Section (IP Bus to R-AHB)
[1]
[0]
R-AHB [31:24]
R-AHB [23:16]
R-AHB [15:8]
R-AHB [7:0]
0
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
0
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
0
1
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
1
1
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
0
0
X
–
–
ips_rdata[15:8]
ips_rdata[7:0]
0
1
–
–
ips_rdata[15:8]
ips_rdata[7:0]
1
0
ips_rdata[15:8]
ips_rdata[7:0]
–
–
1
1
ips_rdata[15:8]
ips_rdata[7:0]
–
–
0
0
–
–
–
ips_rdata[7:0]
0
1
–
–
ips_rdata[15:8]
–
1
0
–
ips_rdata[23:16]
–
–
1
1
ips_rdata[31:24]
–
–
–
0
NA
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
X
ips_rdata[15:8]
ips_rdata[7:0]
ips_rdata[15:8]
ips_rdata[7:0]
1
X
ips_rdata[15:8]
ips_rdata[7:0]
ips_rdata[15:8]
ips_rdata[7:0]
X
X
–
–
ips_rdata[15:8]
ips_rdata[7:0]
X
X
ips_rdata[31:24]
ips_rdata[23:16]
–
–
0
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
X
ips_rdata[15:8]
ips_rdata[7:0]
ips_rdata[15:8]
ips_rdata[7:0]
1
X
ips_rdata[15:8]
ips_rdata[7:0]
ips_rdata[15:8]
ips_rdata[7:0]
X
X
ips_rdata[31:24]
ips_rdata[23:16]
ips_rdata[15:8]
ips_rdata[7:0]
16-bit
1
32-bit
8-bit
0
1
0
16-bit
1
0
32-bit
1
NA
X
X
1
Word
ips_addr
NA
8-bit
1
16-bit
32-bit
X
X
X
MC9328MXS Reference Manual, Rev. 1.1
7-6
Freescale Semiconductor
Overview
Table 7-4. R-AHB to IP Bus Interface Operation (Little Endian—Write Operation)
Transfer
Size
Byte
Half
Word
haddr
[1]
[0]
0
0
0
IP Bus
Size
Active Bus Section (R-AHB to IP Bus)
[1]
[0]
R-AHB [31:24]
R-AHB [23:16]
R-AHB [15:8]
R-AHB [7:0]
0
0
–
–
–
ips_wdata[7:0]
1
0
1
–
–
ips_wdata[7:0]
–
1
0
1
0
–
ips_wdata[7:0]
–
–
1
1
1
1
ips_wdata[7:0]
–
–
–
0
0
0
X
–
–
–
ips_wdata[7:0]
0
1
–
–
ips_wdata[15:8]
–
1
0
–
ips_wdata[7:0]
–
–
1
1
ips_wdata[15:8]
–
–
–
0
0
–
–
–
ips_wdata[7:0]
0
1
–
–
ips_wdata[15:8]
–
1
0
–
ips_wdata[23:16]
–
–
1
1
ips_wdata[31:24]
–
–
–
0
NA
0
–
–
–
ips_wdata[7:0]
1
–
–
ips_wdata[7:0]
–
0
–
ips_wdata[7:0]
–
–
1
ips_wdata[7:0]
–
–
–
0
X
–
–
ips_wdata[15:8]
ips_wdata[7:0]
1
X
ips_wdata[15:8]
ips_wdata[7:0]
–
–
X
X
–
–
ips_wdata[15:8]
ips_wdata[7:0]
X
X
ips_wdata[31:24]
ips_wdata[23:16]
–
–
0
0
–
–
–
ips_wdata[7:0]
1
–
–
ips_wdata[7:0]
–
0
–
ips_wdata[7:0]
–
–
1
ips_wdata[7:0]
–
–
–
0
X
–
–
ips_wdata[15:8]
ips_wdata[7:0]
1
X
ips_wdata[15:8]
ips_wdata[7:0]
–
–
X
X
ips_wdata[31:24]
ips_wdata[23:16]
ips_wdata[15:8]
ips_wdata[7:0]
8-bit
16-bit
1
32-bit
8-bit
0
1
0
16-bit
1
0
32-bit
1
NA
X
X
1
Word
ips_addr
NA
8-bit
1
16-bit
32-bit
X
X
X
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
7-7
Programming Model
7.2 Programming Model
There are six registers that reside inside the AIPI module. Two system clocks are required for read accesses and
three system clocks are required for write accesses to the AIPI registers. Table 7-5 is a summary of these registers
and their addresses.
Table 7-5. AIPI Module Register Memory Map
Description
Name
Address
AIPI1 Peripheral Size Register 0
PSR0_1
0x00200000
AIPI1 Peripheral Size Register 1
PSR1_1
0x00200004
AIPI1 Peripheral Access Register
PAR_1
0x00200008
AIPI1 Peripheral Control Register
PCR_1
0x0020000C
AIPI1 Time-Out Status Register
TSR_1
0x00200010
AIPI2 Peripheral Size Register 0
PSR0_2
0x00210000
AIPI2 Peripheral Size Register 1
PSR1_2
0x00210004
AIPI2 Peripheral Access Register
PAR_2
0x00210008
AIPI2 Peripheral Control Register
PCR_2
0x0021000C
AIPI2Time-Out Status Register
TSR_2
0x00210010
AIPI1
AIPI2
Table 7-6 illustrates the peripheral address associated with the corresponding module_en number. Refer to
Chapter 3, “Memory Map,” to see the corresponding address assigned to each peripheral.
Table 7-6. Peripheral Address MODULE_EN Numbers
AIPI 1
AIPI 2
Address
MODULE_EN
Address
MODULE_EN
0x0020 1000 – 0x0020 1FFF
1
0x0021 1000 – 0x0021 1FFF
1
0x0020 2000 – 0x0020 2FFF
2
0x0021 2000 – 0x0021 2FFF
2
0x0020 3000 – 0x0020 3FFF
3
0x0021 3000 – 0x0021 3FFF
3
0x0020 4000 – 0x0020 4FFF
4
0x0021 4000 – 0x0021 4FFF
4
0x0020 5000 – 0x0020 5FFF
5
0x0021 5000 – 0x0021 5FFF
5
0x0020 6000 – 0x0020 6FFF
6
0x0021 6000 – 0x0021 6FFF
6
0x0020 7000 – 0x0020 7FFF
7
0x0021 7000 – 0x0021 7FFF
7
0x0020 8000 – 0x0020 8FFF
8
0x0021 8000 – 0x0021 8FFF
8
0x0020 9000 – 0x0020 9FFF
9
0x0021 9000 – 0x0021 9FFF
9
0x0020 A000 – 0x0020 AFFF
10
0x0021 A000 – 0x0021 AFFF
10
0x0020 B000 – 0x0020 BFFF
11
0x0021 B000 – 0x0021 BFFF
11
MC9328MXS Reference Manual, Rev. 1.1
7-8
Freescale Semiconductor
Programming Model
Table 7-6. Peripheral Address MODULE_EN Numbers (continued)
AIPI 1
AIPI 2
Address
MODULE_EN
Address
MODULE_EN
0x0020 C000 – 0x0020 CFFF
12
0x0021 C000 – 0x0021 CFFF
12
0x0020 D000 – 0x0020 DFFF
13
0x0021 D000 – 0x0021 DFFF
13
0x0020 E000 – 0x0020 EFFF
14
0x0021 E000 – 0x0021 EFFF
14
0x0020 F000 – 0x0020 FFFF
15
0x0021 F000 – 0x0021 FFFF
15
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
7-9
Programming Model
7.2.1 Peripheral Size Registers[1:0]
These registers control the size of the IP bus peripheral in each IP bus peripheral location. Peripheral locations that
are not occupied must have their corresponding bits in the PSRs (Peripheral Size Registers) programmed to 1 in
each register.
The least significant bit in the PSRs is a read only bit as it governs the AIPI registers themselves. They are set and
cleared appropriately to indicate the registers are 32 bits. Bits 31 through 16 in both registers are preset to 1 and the
fields are reserved and can only be read.
7.2.1.1 AIPI1 Peripheral Size Register 0 and AIPI2 Peripheral Size Register 0
PSR0_1
PSR0_2
BIT
Addr
0x00200000
0x00210000
AIPI1 Peripheral Size Register 0
AIPI2 Peripheral Size Register 0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PSR0_1
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PSR0_2
RESET
1
1
1
1
1
1
1
1
1
BIT
15
7
6
5
4
3
2
1
0
TYPE
0xFFFF
1
1
1
1
1
1
1
0xFFFF
14
13
12
11
10
9
8
MOD_EN_L
TYPE
rw
rw
rw
PSR0_1
RESET
1
1
1
PSR0_2
RESET
1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0x
1
0
0
1
0
0
0
0
0x
Table 7-7. AIPI1 Peripheral Size Register 0 and AIPI2 Peripheral Size Register 0 Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 1.
MOD_EN_L
Bits 15–1
Module_En (lower)—Each bit represents the lower bit of the
2-bit field (PSR1 + PSR0) that represents the Module_En
number.
Reserved
Bit 0
Reserved—This bit is reserved and should read 0.
Settings
See Table 7-9 for bit settings
MC9328MXS Reference Manual, Rev. 1.1
7-10
Freescale Semiconductor
Programming Model
7.2.1.2 AIPI1 Peripheral Size Register 1 and AIPI2 Peripheral Size Register 1
PSR1_1
PSR1_2
BIT
Addr
0x00200004
0x00210004
AIPI1 Peripheral Size Register 1
AIPI2 Peripheral Size Register 1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PSR_1
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PSR_2
RESET
1
1
1
1
1
1
1
1
1
BIT
15
7
6
5
4
3
2
1
0
TYPE
0xFFFF
1
1
1
1
1
1
1
0xFFFF
14
13
12
11
10
9
8
MOD_EN_U
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
PSR_1
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PSR_2
RESET
1
1
1
1
0
1
1
1
1
0xFFFF
1
1
1
1
0
1
1
0xFBEF
Table 7-8. AIPI1 Peripheral Size Register 1 and AIPI2 Peripheral Size Register 1 Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 1.
MOD_EN_U
Bits 15–1
Module_En (upper)—Each bit represents the upper bit of the 2-bit
field (PSR1 + PSR0) that represents the Module_En number.
Reserved
Bit 0
Reserved—This bit is reserved and should read 0.
Settings
See Table 7-9 for bit settings
The PSRs work together to indicate the size of the IP bus peripheral occupying the corresponding ips_module_en
location, or to indicate there is no IP bus peripheral occupying the corresponding ips_module_en location. A good
example of how the PSRs work is the AIPI registers themselves. When haddr[16:12] is decoded to select the AIPI
registers, {PSR1[bit0], PSR0[bit0]} returns a value of 10, indicating that the AIPI registers are word width
registers. Table 7-9 shows how to program the PSR registers based on the size or availability of an IP bus
peripheral.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
7-11
Programming Model
Table 7-9. PSR Data Bus Size Encoding
PSR[1:0] Bits
IP Bus Peripheral Size [x]
(module_en [x])
PSR1[x]
PSR0[x]
0
0
8-bit
0
1
16-bit
1
0
32-bit
1
1
Unoccupied
7.2.2 Peripheral Access Registers
These registers are used to tell the AIPI whether or not the IP bus peripheral corresponding to the bit location in the
register may be accessed in user mode. If the peripheral may be accessed in supervisor mode only and a user mode
access is attempted an abort will be generated and no IP bus activity occurs. If the peripheral can be accessed in
user mode, then the IPS_SUPERVISOR_ACCESS bit reflects whether the attempted access is in supervisor or user
mode and the peripheral itself can decide whether to accept a user access (if one is attempted) or issue an error
response.
The least significant bit in the PAR is a read only bit as it governs the AIPI registers themselves. It is set to indicate
supervisor access only. Bits 31 through 16 in both registers are preset to 1 and the fields are reserved and can only
be read.
PAR_1
PAR_2
BIT
Addr
0x00200008
0x00210008
AIPI1 Peripheral Access Register
AIPI2 Peripheral Access Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PAR_1
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PAR_2
RESET
1
1
1
1
1
1
1
1
1
BIT
15
7
6
5
4
3
2
1
0
TYPE
0xFFFF
1
1
1
1
1
1
1
0xFFFF
14
13
12
11
10
9
8
ACCESS
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
PAR_1
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PAR_2
RESET
1
1
1
1
1
1
1
1
1
0xFFFF
1
1
1
1
1
1
1
0xFFFF
MC9328MXS Reference Manual, Rev. 1.1
7-12
Freescale Semiconductor
Programming Model
Table 7-10. Peripheral Access Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 1.
ACCESS
Bits 15–1
Access Control—Each bit controls the access mode of
the corresponding peripheral.
Reserved
Bit 0
Reserved—This bit is reserved and should read 1.
0 = Assigned peripheral determines access
mode.
1 = the corresponding peripheral is a supervisor
access only peripheral.
7.2.3 Peripheral Control Register
These registers are to tell the AIPI whether or not the IP bus peripheral corresponding to the bit location in the
register can be accessed in their natural size only. When set to 1, only byte access is allowed on an 8-bit peripheral,
only halfword access is allowed on a 16-bit peripheral, and only word access is allowed on a 32-bit peripheral.
When set to 1, any access other than natural size that is attempted on the peripheral results in an error response and
no IP bus activity occurs.
The least significant bit in the PCR is a read-only bit and the AIPI registers are not governed by this bit. Bits 31
through 16 in both registers are preset to 0 and the fields are reserved and can only be read.
PCR_1
PCR_2
BIT
Addr
0x0020000C
0x0021000C
AIPI1 Peripheral Control Register
AIPI2 Peripheral Control Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PCR_1
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PCR_2
RESET
0
0
0
0
0
0
0
0
0
BIT
15
7
6
5
4
3
2
1
0
TYPE
0x0000
0
0
0
0
0
0
0
0x0000
14
13
12
11
10
9
8
ACCESS_MODE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
PCR_1
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PCR_2
RESET
0
0
0
0
0
0
0
0
0
0x0000
0
0
0
0
0
0
0
0x0000
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
7-13
Programming Model
Table 7-11. Peripheral Control Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read
zero.
ACCESS_MODE
Bits 15–1
Module Access Mode—Each bit controls the method
of access used by the corresponding peripheral
assigned to the Module_en.
Reserved
Bit 0
Reserved—This bit is reserved and should read 1.
0 = sub-word and word access is allowed on
the peripheral
1 = corresponding peripheral can only be
accessed in the natural size. i.e. byte
accesses on 8-bit peripherals, half-word
accesses on 16-bit peripherals and word
accesses on 32-bit peripherals.
7.2.4 Time-Out Status Register
These registers contain status of the AIPI module prior to the occurrence of the time-out event. The Time-Out
registers are read-only and status is updated due to time-out operation and module_en must be active. The register
is clear during initial reset.
TSR_1
TSR_2
BIT
Addr
0x00200010
0x00210010
AIPI1 Time-Out Status Register
AIPI2 Time-Out Status Register
31
30
29
28
27
26
25
24
23
22
21
TO
RW
TYPE
rw
r
r
r
r
r
r
r
r
r
r
TSR_1
RESET
0
0
0
0
0
0
0
0
0
0
TSR_2
RESET
0
0
BIT
15
20
19
18
17
16
BE4
BE3
BE2
BE1
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
ADDR
0x0000
0
0
0
0
0
0
0
0x0000
14
13
12
11
10
9
8
MODULE_EN
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
TSR_1
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TSR_2
RESET
0
0
0
0
0
0
0
0
0
0x0000
0
0
0
0
0
0
0
0x0000
MC9328MXS Reference Manual, Rev. 1.1
7-14
Freescale Semiconductor
Programming Example
Table 7-12. Time-Out Status Register Description
Name
Description
Settings
TO
Bit 31
Time-Out—This bit when set to 1 indicates a time-out event and may be
cleared by the user.
0 = No time-out event
1 = time-out event
RW
Bit 30
This bit contains the ips_rwb status prior to time-out event.
–
ADDR
Bits 29–20
Address—These bits contains the ips_addr[11:2] status prior to time-out
event.
–
BE4
Bit 19
This bit contains the ips_byte_31_24 status prior to time-out event.
–
BE3
Bit 18
This bit contains the ips_byte_23_16 status prior to time-out event.
–
BE2
Bit 17
This bit contains the ips_byte_15_8 status prior to time-out event.
–
BE1
Bit 16
This bit contains the ips_byte_7_0 status prior to time-out event.
–
MODULE_EN
Bits 15–1
Module Enable Status—These bits contains the module_en[15:1] status
prior to time-out event. Refer to Table 7-6 to determine which peripheral
is assigned to which module_en number.
Reserved
Bit 0
Reserved—This bit is reserved and should read 0.
0= Corresponding module has
not timed out
1 = Corresponding module has
timed out
7.3 Programming Example
This section covers programming examples written in assembly code to illustrate the data access through the AIPI
module.
7.3.1 Data Access to 8-Bit Peripherals
The followings codes are executed with the ARM920T core set to big and little endian modes:
LDR
LDR
LDR
STRB
STRB
STRH
STR
LDRB
LDRB
LDRH
LDR
r0,
r1,
r2,
r0,
r1,
r0,
r1,
r3,
r4,
r5,
r6,
=0x11223344
=0x55667788
=8BIT_PERIPHERAL_ADDRESS
[r2, #0x0]
[r2, #0x1]
[r2, #0x2]
[r2, #0x4]
[r2, #0x0]
[r2, #0x1]
[r2, #0x2]
[r2, #0x4]
The Table 7-13 on page 7-16 illustrates the difference in the 8-bit peripheral register content.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
7-15
Programming Example
Table 7-13. Core and 8-Bit Peripheral Register Content After Code Execution
Address
Peripheral Registers
0
44
–
1
88
–
2
44
–
3
33
–
4
88
–
5
77
–
6
66
–
7
55
–
Address
Core Registers
r3
00
00
00
44
r4
00
00
00
88
r5
00
00
33
44
r6
55
66
77
88
7.3.2 Data Access to 16-Bit Peripherals
The followings codes are executed with the ARM core set to big and little endian modes.
LDR
LDR
LDR
STRB
STRB
STRH
STR
LDRB
LDRB
LDRH
LDR
r0,
r1,
r2,
r0,
r1,
r0,
r1,
r3,
r4,
r5,
r6,
=0x11223344
=0x55667788
=16BIT_PERIPHERAL_ADDRESS
[r2, #0x0]
[r2, #0x1]
[r2, #0x2]
[r2, #0x4]
[r2, #0x0]
[r2, #0x1]
[r2, #0x2]
[r2, #0x4]
The Table 7-14 and Table 7-15 illustrate the difference in the 16-bit peripheral register content.
Table 7-14. Core and 16-Bit Peripheral Register Content (Little Endian)
Address
Peripheral Registers
0
88
44
–
2
33
44
–
4
77
88
–
MC9328MXS Reference Manual, Rev. 1.1
7-16
Freescale Semiconductor
Programming Example
Table 7-14. Core and 16-Bit Peripheral Register Content (Little Endian) (continued)
Address
6
Peripheral Registers
55
Address
66
–
Core Registers
r3
00
00
00
44
r4
00
00
00
88
r5
00
00
33
44
r6
55
66
77
88
Table 7-15. Core and 16-Bit Peripheral Register Content (Big Endian)
Address
Peripheral Registers
0
44
88
–
2
33
44
–
4
55
66
–
6
77
88
–
Address
Core Registers
r3
00
00
00
44
r4
00
00
00
88
r5
00
00
33
44
r6
55
66
77
88
7.3.3 Data Access to 32-Bit Peripherals
The followings codes are executed with the ARM core set to big and little endian modes.
LDR
LDR
LDR
STRB
STRB
STRH
STR
LDRB
LDRB
LDRH
LDR
r0,
r1,
r2,
r0,
r1,
r0,
r1,
r3,
r4,
r5,
r6,
=0x11223344
=0x55667788
=32BIT_PERIPHERAL_ADDRESS
[r2, #0x0]
[r2, #0x1]
[r2, #0x2]
[r2, #0x4]
[r2, #0x0]
[r2, #0x1]
[r2, #0x2]
[r2, #0x4]
The Table 7-16 and Table 7-17 on page 7-18 illustrate the difference in the 32-bit peripheral register content.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
7-17
Programming Example
Table 7-16. Core and 32-bit Peripheral Register Content (Little Endian)
Address
Peripheral Registers
0
33
44
88
44
4
55
66
77
88
Address
Core Registers
r3
00
00
00
44
r4
00
00
00
88
r5
00
00
33
44
r6
55
66
77
88
Table 7-17. Core and 32-bit Peripheral Register Content (Big Endian)
Address
Peripheral Registers
0
44
88
33
44
4
55
66
77
88
Address
Core Registers
r3
00
00
00
44
r4
00
00
00
88
r5
00
00
33
44
r6
55
66
77
88
7.3.4 Special Consideration for Non-Natural Size Access
A programmer must exercise care when accessing peripherals using access other than their natural size. An
example of such access includes byte access to a 32-bits peripheral and word access to 8-bit peripheral. The
examples in the previous section clearly illustrate the difference in byte accessing a 32-bits peripheral in both big
and little endian modes. An instruction such as:
STRB
r1,
[r2, #0x1]
is accessing using byte lane[15:8] in little endian, while byte lane[23:16] is accessed using big endian mode.
Therefore, if a programmer is using byte access to set up control information in 32-bit register, extreme care must
be taken to ensure the desired byte is written during the desired endian mode.
MC9328MXS Reference Manual, Rev. 1.1
7-18
Freescale Semiconductor
Chapter 8
System Control
This chapter describes the system control module of the MC9328MXS microprocessor. The system control module
enables system software to control, customize, or read the status of the following functions:
•
Multiplexing of SSI signals
•
Multiplexing of the SDRAM/SyncFlash chip select signal
•
Chip ID
•
System boot mode selection
8.1 Programming Model
The system control module includes four user-accessible 32-bit registers. Table 8-1 summarizes these registers and
their addresses.
Table 8-1. System Control Module Register Memory Map
Description
Name
Address
Silicon ID Register
SIDR
0x0021B804
Function Multiplexing Control Register
FMCR
0x0021B808
Global Peripheral Control Register
GPCR
0x0021B80C
Global Clock Control Register
GCCR
0x0021B810
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
8-1
Programming Model
8.1.1 Silicon ID Register
This 32-bit read-only register shows the chip identification. The bit assignments for the register are shown in the
following register display. The settings for the bits in the register are listed in Table 8-2.
SIDR
BIT
Addr
0x0021B804
Silicon ID Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SID
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
7
6
5
4
3
2
1
0
RESET
BIT
0x04D4
15
14
13
12
11
10
9
8
SID
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
1
0
0
1
0
0
0
0
0
0
0
1
1
1
0
1
RESET
0xC01D
Table 8-2. Silicon ID Register Description
Name
SID
Bits 31–0
Description
Silicon ID—Contains the chip identification number of the MC9328MXS.
Settings
Silicon ID:
Mask 1L = 0x04D4 C01D
Mask 2L = 0x00D4 C01D
8.1.2 Function Multiplexing Control Register
The Function Multiplexing Control Register (FMCR) controls the multiplexing of the signal lines shared by the
SSI module. It also controls the SDRAM/SyncFlash chip select lines and masking of the external bus request. See
Table 8-3 for detailed description of bit settings.
MC9328MXS Reference Manual, Rev. 1.1
8-2
Freescale Semiconductor
Programming Model
FMCR
Addr
0x0021B808
Function Multiplexing Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
BIT
15
14
13
12
11
10
9
8
7
SSI_RXFS_SEL
SSI_RXCLK_SEL
SSI_RXDAT_SEL
SSI_TXFS_SEL
SSI_TXCLK_SEL
EXT_BR_EN
SDCS1_SEL
SDCS0_SEL
0x0000
TYPE
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
RESET
0x0003
Table 8-3. Function Multiplexing Control Register Description
Name
Description
Settings
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
SSI_RXFS_SEL
Bit 7
SSI Receive Frame Sync Input Select—Selects the Receive
Frame Sync input source. See Figure 24-1 on page 24-2.
0 = input from Port C
1 = input from Port B
SSI_RXCLK_SEL
Bit 6
SSI Receive Clock Select—Selects the Receive Clock input
source. See Figure 24-1 on page 24-2.
0 = input from Port C
1 = input from Port B
SSI_RXDAT_SEL
Bit 5
SSI Receive Data Select—Selects the Receive Data input
source. See Figure 24-1 on page 24-2.
0 = input from Port C
1 = input from Port B
SSI_TXFS_SEL
Bit 4
SSI Transmit Frame Sync Select —Selects the Transmit Frame
Sync input source. See Figure 24-1 on page 24-2.
0 = input from Port C
1 = input from Port B
SSI_TXCLK_SEL
Bit 3
SSI Transmit Clock Select—Selects the Transmit Clock input
source. See Figure 24-1 on page 24-2.
0 = input from Port C
1 = input from Port B
EXT_BR_EN
Bit 2
External Bus Request Control—Chooses whether the external
bus request function is masked or enabled.
The external bus request is a test signal and the EXT_BR_EN bit
must be clear during normal operation.
0 = External bus request masked
1 = External bus request enabled
SDCS1_SEL
Bit 1
SDRAM/SyncFlash Chip-Select—Selects the function of the
CS3/CSD1 pin.
0 = CS3 selected
1 = CSD1 selected
SDCS0_SEL
Bit 0
SDRAM/SyncFlash Chip-Select—Selects the function of the
CS2/CSD0 pin.
0 = CS2 selected
1 = CSD0 selected
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
8-3
Programming Model
8.1.3 Global Peripheral Control Register
The Global Peripheral Control Register (GPCR) controls the driving force parameters of the bus and several other
functions in the MC9328MXS. Descriptions of the register settings appear in Table 8-6.
GPCR
Addr
0x0021B80C
Global Peripheral Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
RESET
10
9
HCLK_GATING_EN
12
11
rw
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
w
rw
rw
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
DS_SLOW
MEMC_TEST_EN
13
RESET
DS_DATA
TYPE
14
DS_ADDR
15
DS_CNTL
BIT
IP_CLK_GATING_EN
0x0000
0x03FC
Table 8-4. Global Peripheral Control Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
MEMC_TEST_EN
Bits15
Active high of this bit switches the inner test signals from
MEMC to GPIO for debug purposes.
Reserved
Bits 14–12
Reserved—These bits are reserved and should read 0.
DS_SLOW
Bits 11–10
Driving Strength Slow I/O—Controls the driving strength of all
slow I/O signals.
00 = 26 MHz/15 pF
01 = 26 MHz/30 pF
10 = 26 MHz/45 pF
11 = 26 MHz/greater than 45 pF
DS_CNTL
Bits 9–8
Driving Strength Bus Control Signals—Controls the driving
strength of bus control signals.
00 = 50 MHz/15 pF
01 = 50 MHz/30 pF
10 = 100 MHz/15 pF
11 = 100 MHz/30 pF
0 = Normal
1 = Switch MEMC inner test
signals to GPIO for debug
purpose.
MC9328MXS Reference Manual, Rev. 1.1
8-4
Freescale Semiconductor
Programming Model
Table 8-4. Global Peripheral Control Register Description (continued)
Name
Description
Settings
DS_ADDR
Bits 7–6
Driving Strength Address Bus—Controls the driving strength
of the address bus.
00 = 50 MHz/15 pF
01 = 50 MHz/30 pF
10 = 100 MHz/15 pF
11 = 100 MHz/30 pF
DS_DATA
Bits 5–4
Driving Strength Data Bus—Controls the driving strength of
the data bus.
00 = 50 MHz/15 pF
01 = 50 MHz/30 pF
10 = 100 MHz/15 pF
11 = 100 MHz/30 pF
IP_CLK_GATING_EN
Bit 3
IP Clock Gating Enabled—Controls ips_gated_clk signal.
0 = ips_gated_clk is continuous
clock
1 = ips_gated_clk will be gated
by aipi1_gated_clk_en or
aipi2_gated_clk_en
HCLK_GATING_EN
Bit 2
HCLK_GATING_Enabled—This bit only applies to functional
and register access clocks; DMA and AITC. The functional
clock and register access clock can be either a gated clock or
continuous clock. Low value of this bit can disable clock gating
for DMA/ AITC and make their clock become a continuous
clock. This bit is write only and when read, will always be 0.
1 = hclk gating enabled, some
hclk to DMA/AITC/ is gated clock
0 = hclk gating disabled, all hclk
becomes continuous clock
Note: Clocks of DMA/DSPA can also be turned off by
corresponding bits in GCCR. When their clocks are turned off
in GCCR, this bit has no effect on these modules because their
clocks are off. Please refer GCCR register description for detail
information.
Reserved
Bit 1–0
Reserved—These bits are reserved and should read 1.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
8-5
Programming Model
8.1.4 Global Clock Control Register
The Global Clock Control Register (GCCR) provides additional power saving capabilities by controlling the clocks
in the following MC9328MXS modules: DMA and USB. It also controls the clock source for Bootstrap mode.
GCCR
Addr
0x0021B810
Global Clock Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
2
1
0
RESET
15
14
13
12
11
10
9
8
7
6
5
4
DMA_CLK_EN
TYPE
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
USBD_CLK_EN
BIT
BROM_CLK_EN
0x0000
RESET
0x000F
Table 8-5. Global Clock Control Register Description
Name
Description
Settings
Reserved
Bits 31–5
Reserved—These bits are reserved and should read 0.
BROM_CLK_EN
Bit 4
BROM Clock Enable—Only available in Bootstrap mode.
This bit enables/disables the operational system boot mode of
the MC9328MXS upon system reset. The boot mode is
determined by the settings of these pins.
0 = Clock gating is controlled by setting
of BOOT[3:0] pins.
1 = Overrides the setting of the
BOOT[3:0] pins and forces the
HCLK to be used as clock.
DMA_CLK_EN
Bit 3
DMA Clock Enable—Enables/Disables clock input to the
DMA module.
0 = DMA clock input is disabled.
1 = DMA clock input is enabled
(default).
Reserved
Bit 2–1
Reserved—These bits are reserved
0 = Perferred setting. Used to minimize
power consumption.
1 = Default.
USBD_CLK_EN
Bit 0
USBD Clock Enable—Enables/Disables clock input to the
USB module.
0 = USB clock input is disabled.
1 = USB clock input is enabled (default).
MC9328MXS Reference Manual, Rev. 1.1
8-6
Freescale Semiconductor
System Boot Mode Selection
8.2 System Boot Mode Selection
The operational system boot mode of the MC9328MXS upon system reset is determined by the configuration of
the four external input pins BOOT[3:0]. The settings of these pins control the following functions:
•
CS0 boot function of the EIM module
•
Control of the SyncFlash chip select (CSD1) boot function of the SDRAM controller
The settings of the system control module for the system boot mode selection are displayed in Table 8-6.
The MC9328MXS always begins fetching instructions from address 0x00000000 after reset. The BOOT[3:0] pins
control the memory region that is mapped to address 0x0. The boot modes are defined in Table 8-6. The
BOOT[3:0] pins also control the initial configuration (for example bus width) for the external memory regions.
When an external chip select is enabled by the BOOT[3:0] pins, the first 1 Mbyte range (0x0000000–0x000FFFFF)
of the chip select's memory space is also mapped to address 0x0.
For example, by setting BOOT[3:0] to 0110, the MC9328MXS will boot from the CS0 memory region using a
32-bit data bus width. The first 1 Mbyte of the CS0 memory space (0x10000000–0x100FFFFF) will be mapped to
addresses 0x00000000–0x000FFFFF.
NOTE:
The BOOT pins must not change once the MC9328MXS is out of reset. To achieve
logic 0, a BOOT input must be tied to GND through a 1 kohm resistor. Otherwise,
excessive current may occur at power up. BOOT[3] must always be terminated with a
1 kohm resistor to GND.
NOTE:
If Bootstrap ROM is not selected for the boot mode, the internal ROM is not accessible.
Table 8-6. System Boot Mode Selection
Inputs
BOOT[3:0]
Output Signals
Active Device
0000
Bootstrap ROM
0001
16-bit SyncFlash D[15:0]
0010
32-bit SyncFlash
0011
8-bit CS0 at D[7:0]
0100
16-bit CS0 at D[31:16]
0101
16-bit CS0 at D[15:0]
0110
32-bit CS0 at D[31:0]
0111
Reserved
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8-7
System Boot Mode Selection
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Freescale Semiconductor
Chapter 9
Bootstrap Mode Operation
Bootstrap mode is designed to allow you to initialize a target system and download programs or data to the target
system’s RAM using the UART 1 or UART 2 controller. After a program is downloaded, it can be executed, which
gives you a simple debugging environment for failure analysis and a channel to update programs stored in flash
memory. Bootstrap mode has the following capabilities:
•
Allows you to initialize your system and download programs and data to system memory using UART 1 or
UART 2.
•
Accepts execution commands to run programs stored in system memory
•
Supports memory and register read and write operations of selectable data size (byte, half-word, or word)
•
Provides an 8-word instruction buffer for ARM920T vector table storage, instruction storage and execution
9.1 Operation
In bootstrap mode, only MC9328MXS’s UART 1 and UART 2 controllers are initialized. They are configured to
auto-baud detection mode, ignore RTS, keep CTS always active, no parity, 8-bit character length, and one stop bit.
Then they are ready to accept bootstrap data download. The first character received must be a or A. This character
determines the baud rate to be used and which UART port is being used for bootstrapping. The first character is not
part of a program or data being downloaded. To download the data or program, the code must be converted to a
bootstrap format file, which is a text file that contains bootstrap records. A DOS-executable program, STOB.EXE,
can be downloaded from the i.MX Web site to convert an S-record file to a bootstrap format file.
The MC9328MXS’s internal registers must be initialized as the target system before a program can be downloaded
to system memory. Because these internal registers can be treated as a type of memory, each of them can be
initialized by issuing a bootstrap record.
The bootstrap design provides an 8-word instruction buffer to which ARM920T core instructions can be
downloaded. The buffers are word-access only. This feature enables the ARM920T core instructions to be run even
if the memory systems are disabled or in a core stand-alone system. The instruction buffer starts at 0x00000004.
Regardless of the operation (initializing internal registers, downloading a program to system RAM, or issuing a
core instruction), bootstrap mode will only accept bootstrap record transfers that are made with the UART. The
record type determines what action will occur.
The instruction buffer allows users to download the vector table onto the buffer without the use of external ROM or
Flash, the feature provides a fast and easy environment to users when using IRQ during program debug.
9.1.1 Entering Bootstrap Mode
Bootstrap mode is the debug mode of the MC9328MXS. To enter bootstrap mode, the BOOT pins must be
properly configured during system reset. After reset, the bootstrap ROM is selected for reset vector fetch cycles.
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Freescale Semiconductor
9-1
Operation
9.1.2 Bootstrap Record Format
Only bootstrap records (b-records) are accepted for data transfers in bootstrap mode. The b-record format is shown
in Table 9-1, and Table 9-2 further defines the COUNT/MODE byte. All b-records are in uppercase. Each byte is
represented by two ASCII characters during transfer (for example, a byte of value 0x12 will be represented by the
characters 12).
Table 9-1. Bootstrap Record Format
4 Bytes
1 Byte
N (Count) Bytes
Address
Count/mode
Data
Table 9-2. Definition of COUNT/MODE Byte
Bit(s)
Definition
7–6
Data size
5
Read/write flag
4–0
Data count in number of bytes
Settings
00 = Byte
01 = Half-word
10 = Reserved
11 = Word
0 = Write
1 = Read
Value from 0 to 31
NOTE:
1. A half-word is defined as 16 bits, while a word is defined as 32 bits.
2. The address specified must fall on a data size boundary: for word access, the last 2 bits of the
address must be 0, while for half-word access, the last bit of the address must be 0. The data count
in the COUNT/MODE byte must be a multiple of the data size: for word access, the data count must
be a multiple of four, while for half-word access, the data count must be in multiple of two. If either
the address or the data count is not on an appropriate data size boundary, the bootloader program
will return a * character (asterisk) to indicate that an error has occurred, and the bootloader will then
start waiting for a new b-record.
3. During a read operation, a / character (forward slash) is returned after the last data has been returned.
4. A data count of zero (disregard the value of data size and the status of the mode flag) has a special
meaning: execute from the address specified. In this case, no data will follow the COUNT/MODE
byte.
Comments can be added to files of b-records. As described above, the shortest b-record consists of 10 ASCII
characters (when the data count is 0) of 0 to 9 or A to F (hexadecimal digits). Comments included must not contain
patterns to prevent the comments from being considered a b-record.
9.1.3 Registers Used in Bootloader Program
The bootloader program uses general-purpose registers r5 to r12 as well as r13 as the return register and r14 as the
link register. All the other registers can be used by target programs.
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Freescale Semiconductor
B-Record Example
9.1.4 Setting Up the RS-232 Terminal
To set up communication between your target system and the PC, set the communication specifications to the baud
rate desired, no parity, 8-bit character length, and 1 stop bit. You may pause after each line (b-record) is transferred
to make sure each transferred ASCII character is echoed.
After setting up the hardware, powering up the system, and entering bootstrap mode, send an a or A character to the
target system to initiate the link. Once the bootloader receives this character, it adjusts the baud rate. If the link is
successful, the bootloader will return the special character : (colon) as an acknowledgment.
9.1.5 Changing the Speed of Communication
You can change the communication baud rate after communication is set up in the RS-232 terminal. Simply issue a
b-record to re-initialize the baud control register of the UART controller. After the last character of this b-record is
sent, the echo of this last character will be transmitted at the new speed. The maximum speed recommended for
Bootstrap is 57600 baud.
9.2 B-Record Example
Before you can download a program to system memory, the target system may need to be initialized using the
internal registers. An init file can be built using a text editor. Code Example 9-1 initializes the memory location to
0x12345678 in word access mode, the location to 0x7788 in half-word access mode, and the location to 0x55 in
byte access mode.
Code Example 9-1. init.b Example
// init.b -- Initialization Example
0000C412345678
initialize 0x0000 to 0x12345678
0006427788
initialize 0x0006 to 0x7788
00090155
initialize 0x0009 to 0x55
With b-records similar to those stated above, a target program can be downloaded to memory and executed from
the address chosen with the following b-record:
1122334400
execute from 11223344
The target program may exit and return to the bootloader program by jumping to address 0x00000100, where the
bootloader program starts.
9.3 Instruction Buffer Usage
A 8-word instruction buffer is provided for ARM920T core vector table storage, instruction and data storage. The
buffer starts at 0x00000004. Up to eight instructions can be loaded to the instruction buffer for execution.Usually,
the last instruction is an unconditional jump instruction (jmp) that jumps to the start of the bootloader program
(0x00000100).
Code Example 9-2 fills memory locations starting from 0x00310000 to 0x00FF (the length of 0x100) with
0x12345678.
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Freescale Semiconductor
9-3
Instruction Buffer Usage
loop:
ldr
ldr
ldr
ldr
r1,=0x0000
r2,=0x100
r3,=0x12345678
r4,=0x00000100
str
subs
bne
mov
r3,[r1, r2]
r2,r2, #4
loop
pc, r4
Code Example 9-2. Instruction Buffer Sample
// starting address is 0x00FF
// length is 0x100
// data to fill is 0x12345678
// bootloader program
// store data
// decrement address
// loop back till r2 down to 0x0
// return to bootloader program
Because the instruction buffer is of limited size, the programmer cannot do everything at the same time. The
program can be broken into five parts, as shown in Table 9-3.
Table 9-3. Program Breakdown
Part
Code
1
ldr
mov
r4,=0x00000100
pc, r4
// bootloader address 0x00000100
// return to bootloader program
2
ldr
mov
r1,=0x0000
pc, r4
// starting address is 0x0000
// return to bootloader program
3
ldr
mov
r2,=0x00000100
pc, r4
// length is 0x100
// return to bootloader program
4
ldr
mov
r3,=0x12345678
pc, r4
// data to fill is 0x12345678
// return to bootloader program
str
subs
bne
mov
r3,[r1, r2]
r2,r2, #4
loop
pc, r4
//
//
//
//
5
loop
store data
decrement address
loop back till r2 down to 0x0
return to bootloader program
Breaking down the register initialization into three parts is not mandatory, however it produces similar b-records
and therefore is easier to manage.
The resulting b-records appear in Table 9-4.
Table 9-4. Resulting B-Records
B-Record Number
B-Record
1
00000004 08E3A04F40E1A0F004
0000000400
2
00000004 08E3A019C4E1A0F004
0000000400
3
00000004 08E3A02F40E1A0F004
0000000400
4
00000004 0CE59F3000E1A0F00412345678
0000000400
5
00000004 0FE7813002E25220041AFFFFFCE1A0F004
0000000400
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Simple Read/Write Examples
Note that all b-records start at the same address, 0x00000004, which is the starting address of the instruction buffer.
B-records 1, 2, and 3 are very similar and can be used as prototype b-records for general-purpose register
initialization.
Therefore, the resulting b-record file will be as follows:
Code Example 9-3. Bootloader B-Record
00000004 08E3A04F40E1A0F004initialize r4 to 0x00000100 (bootloader start)
0000000400
execute and return to bootloader
00000004 08E3A019C4E1A0F004initialize r1 to 0x0000 (start)
0000000400
execute and return to bootloader
00000004 08E3A02F40E1A0F004initialize r2 to 0x100 (length)
0000000400
execute and return to bootloader
00000004 0CE59F3000E1A0F00412345678initialize r3 to 0x12345678 (content)
0000000400
execute and return to bootloader
00000004 0FE7813002E25220041AFFFFFCE1A0F004memory fill
0000000400
execute and return to bootloader
9.4 Simple Read/Write Examples
Table 9-5 provides examples demonstrating how to perform memory and register reads/writes of various data
sizes. Code Example 9-4 shows an example of the code used for Vector Tables
Code Example 9-4.
NOP
IRQ_Addr
FIQ_Addr
NOP
NOP
DCD
DCD
NOP
LDR
LDR
DCD
; 0x00
C_IRQ_Handler
C_FIQ_Handler
PC, IRQ_Addr
PC, FIQ_Addr
0
;
;
;
;
;
;
;
;
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
(programmable
(programmable
(programmable
(programmable
(programmable
(programmable
(programmable
(programmable
buffer)
buffer)
buffer)
buffer)
buffer)
buffer)
buffer)
buffer)
Table 9-5. Read/Write Examples
Example Type
B-Record
Read 3 bytes starting
from location 0x00310000
0031000023
Read 3 half-words
starting from location
0x00310000
Return Value
0031000003XXYYZZ/
(where XX, YY, and ZZ are data in byte)
0031000066
0031000066XXXXYYYYZZZZ/
(6 bytes = 3 half-words)
(where XXXX, YYYY, and ZZZZ are data in half-word)
00310000EC
00310000ECXXXXXXXXYYYYYYYYZZZZZZZZ/
(12 bytes = 3 words)
(where XXXXXXXX, YYYYYYYY, and ZZZZZZZZ are data
in word)
Write 3 bytes starting from
location 0x00310000
0031000003112233
0031000003112233/
Write 3 half-words starting
from location 0x00310000
0031000046111122223333
0031000046111122223333/
Read 3 words starting
from location 0x00310000
(6 bytes = 3 half-words)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
9-5
Simple Read/Write Examples
Table 9-5. Read/Write Examples (continued)
Example Type
B-Record
Return Value
Write 3 words starting
from location 0x00310000
00310000CC1111111122222222
33333333
00310000CC111111112222222233333333/
(12 bytes = 3 words)
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Bootloader Flowchart
9.5 Bootloader Flowchart
Figure 9-1 on page 9-7 illustrates how the bootloader program operates inside the MC9328MXS. The bootloader
starts when the MC9328MXS enters bootstrap mode.
START
Initialize
UART
Receive a Bootstrap
Record
Data COUNT = 0?
YES
Run Program
Starting
at ADDR
NO
Data COUNT &
Data SIZE
Valid?
NO
ECHO *
YES
ECHO /
NO
Read?
Store Data to
ADDR
YES
Read Data From
ADDR
ECHO Data
Figure 9-1. Bootloader Program Operation
9.6 Special Notes
The following summary items may be helpful when working in bootstrap mode.
•
A b-record is a string of uppercase hex characters with optional comments that follow.
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9-7
Special Notes
•
Comments in a b-record or b-record file must not contain any word or symbol that is longer than nine
characters. However, the following characters can be used in a string of any length (all of these have an
ASCII code value that is less than 0x30):
— space
— ! (exclamation point)
— “ (quotation mark)
— # (number sign)
— $ (dollar sign)
— % (percentage symbol)
— & (ampersand)
— ( (opening parenthesis)
— ) (closing parenthesis)
— * (asterisk)
— + (plus sign)
— - (minus sign)
— . (period)
— / (forward slash)
— , (comma)
•
The bootloader program echoes all characters being received, however only those having an ASCII code
value greater than or equal to 0x30 are kept for b-record assembling. Sending a character that is not a
b-record (ASCII code value less than 0x30) will force the bootloader to start a new b-record.
•
General-purpose registers –r14 and supervisor scratch register are used by the bootloader program. Writing
to these registers may corrupt the bootloader program.
•
Please visit the DragonBall Web site for bootstrap utility programs.
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Chapter 10
Interrupt Controller (AITC)
This chapter describes the ARM9 Interrupt Controller (AITC) that is used to control and prioritize up to 64
interrupts in the MC9328MXS. This chapter describes the registers and bit settings plus all other information
necessary to write the software necessary to write interrupt service routines.
10.1 Introduction
The MC9328MXS interrupt controller (AITC) is a 32-bit peripheral that collects interrupt requests from a
maximum of 64 sources and provides an interface to the ARM920T processor.
AITC_FIQ
64
FIVECTOR
FIPEND
64
64
64
INTIN
64
FIAD
6
FORCE
64
AITC_BLOCK_ARB
Priority
Encoder
NIPEND
INTTYPE
64
Software
Priority
Encoder
NIVECTOR
INTENABLE
6
NIAD
AITC_IRQ
AITC_RDATA_OVR
NM
32
HADDR
Equals
0x00000018
Equals
0x0000001C
Opcode
Generator
32
AITC_RDATA
HREADY
FM
Figure 10-1. AITC Block Diagram
The AITC performs the following functions:
•
Supports a maximum of 64 interrupt sources
•
Supports fast and normal interrupts
•
Selects normal or fast interrupt request for any interrupt source
•
Indicates pending interrupt sources via a register for normal and fast interrupts
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10-1
Operation
•
Detects all pending interrupts and distinguishes by priority level
•
Independently enables or disables any interrupt source
•
Provides a mechanism for software to schedule an interrupt
•
Supports a maximum of 16 software controlled priority levels for normal interrupts and priority masking
10.2 Operation
The interrupt controller consists of a set of control registers and associated logic to perform interrupt masking,
priority support, and hardware acceleration of normal interrupts.
The interrupt source registers (INTSRCH and INTFRCL) are a pair of 32-bit status registers with a single interrupt
source associated with each of the 64 bits. An interrupt line or set of interrupt lines is routed from each interrupt
source to the INTSRCH or INTFRCL register. This configuration allows the ARM920T processor of the
MC9328MXS to monitor a maximum of 64 distinct interrupt sources.
Interrupt requests can be forcibly asserted through the interrupt force registers (INTFRCH and INTFRCL). Each
bit in these registers is logically ORed with the corresponding hardware request line prior to input to the INTSRCH
or INTFRCL registers.
There is a corresponding set of interrupt enable registers (INTENABLEH and INTENABLEL), each 32 bits wide,
that allow individual bit masking of the INTSRCH and INTFRCL registers. There is also a corresponding set of
interrupt type registers (INTTYPEH and INTTYPEL) that selects whether an interrupt source generates a normal
or fast interrupt to the ARM920T processor.
There is a corresponding set of normal interrupt pending registers (NIPNDH and NIPNDL) that indicate pending
normal interrupt requests, and are equivalent to the logical AND of the interrupt source registers (INTSRCH and
INTSRCL), the interrupt enable registers (INTENABLEH and INTENABLEL), and the NOT of the interrupt type
registers (INTTYPEH and INTTYPEL). The NIPNDH and NIPNDL register bits are bit-wise NORed together to
generate the nIRQ signal that is routed to the ARM920T processor. This ARM920T processor input signal is
maskable by the normal interrupt disable bit (I bit) in the program status register (CPSR). The normal interrupt
vector register (NIVECSR) indicates the vector index of highest priority pending normal interrupt.
There is a corresponding set of fast interrupt pending registers (FIPNDH and FIPNDL) that indicate pending fast
interrupt requests, and are equivalent to the logical AND of the interrupt source registers (INTSRCH and
INTSRCL), the interrupt enable registers (INTENABLEH and INTENABLEL), and the interrupt type registers
(INTTYPEH and INTTYPEL). The FIPNDH and FIPNDL register bits are bit-wise NORed together to generate
the nFIQ signal that is routed to the ARM920T processor. This ARM920T processor input signal is maskable by
the fast interrupt disable bit (F bit) in the CPSR. The fast interrupt vector register (FIVECSR) indicates the vector
index of highest priority pending fast interrupt.
All interrupt controller registers are readable and writable in supervisor mode only. Writes attempted to read-only
registers are ignored. These registers must be written with 32-bit stores only.
The INTFRCH and INTFRCL registers are provided for software generation of interrupts. By enabling interrupts
for these bit positions, software can force an interrupt request. This register also provides an alternate method of
interrupt assertion for debugging hardware interrupt service routines.
The interrupt requests are prioritized in the following order:
1. Fast interrupt requests, in order of highest number
2. Normal interrupt requests, in order of highest priority level, then highest source number with the
same priority
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AITC Interrupt Controller Signals
The AITC provides 16 software controlled priority levels for normal interrupts and every interrupt can be placed in
any priority level. The AITC also provides a normal interrupt priority level mask (NIMASK) that disables any
interrupt with a priority level less than or equal to the mask. When a level 0 normal interrupt and a level 1 normal
interrupt are asserted at the same time, the level 1 normal interrupt is selected unless NIMASK has disabled level 1
normal interrupts. When two level 1 normal interrupts are asserted at the same time, the level 1 normal interrupt
with the highest source number is selected unless NIMASK has disabled level 1 normal interrupts.
10.3 AITC Interrupt Controller Signals
The active-low INTIN [63:0] input signals indicate that a peripheral device is requesting an interrupt to the
interrupt controller. The interrupt controller recognizes an interrupt is asserted on the rising edge of the clock and
does not latch and hold the interrupt. The peripheral must keep the interrupt request asserted until the software
acknowledges and clears the interrupt request.
The interrupt source assignment of INTIN [63:0] is shown Table 10-1. Interrupt sources in the table that are labeled
‘unused’ may be used by software to force an interrupt request for a specific source using either the INTFRCH or
INTRFRCL registers.
In Table 10-1, some signals are shown with overbars to represent the logic inside the chip. However, all
asserted interrupts result in the associated bit being a 1 in the Interrupt Source Registers
Table 10-1. Interrupt Assignment
Bit #
Name of Interrupt
Bit #
Name of Interrupt
Bit #
Name of Interrupt
Bit #
Name of Interrupt
0
Unused
16 Unused
32
Unused
48 USBD_INT [1]
1
Unused
17 RTC_INT
33
Unused
49 USBD_INT [2]
2
Unused
18 RTC_SAM_INT
34
PWM_INT
50 USBD_INT [3]
3
Unused
19 UART2_MINT_PFERR
35
Unused
51 USBD_INT [4]
4
Unused
20 UART2_MINT_RTS
36
Unused
52 USBD_INT [5]
5
Unused
21 UART2_MINT_DTR
37
Unused
53 USBD_INT [6]
6
Unused
22 UART2_MINT_UARTC
38
Unused
54 Unused
7
Unused
23 UART2_MINT_TX
39
I2C_INT
55 Unused
8
Unused
24 UART2_MINT_RX
40
Unused
56 Unused
9
Unused
25 UART1_MINT_PFERR
41
SPI1_INT
57 Unused
10
MSIRQ
26 UART1_MINT_RTS
42
SSI_TX_INT
58 TIMER2_INT
11
GPIO_INT_PORTA
27 UART1_MINT_DTR
43
SSI_TX_ERR_INT
59 TIMER1_INT
12
GPIO_INT_PORTB
28 UART1_MINT_UARTC
44
SSI_RX_INT
60 DMA_ERR
13
GPIO_INT_PORTC
29 UART1_MINT_TX
45
SSI_RX_ERR_INT
61 DMA_INT
14
LCDC_INT
30 UART1_MINT_RX
46
Unused
62 GPIO_INT_PORTD
15
Unused
31 Unused
47
USBD_INT [0]
63 WDT_INT
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10-3
Programming Model
10.4 Programming Model
The AITC module includes 26 user-accessible 32-bit registers. All of these registers are single cycle access
because the AITC sits on the native bus of the ARM920T processor. Table 10-2 summarizes these registers and
their addresses. Table 10-3 provides an overview of the register fields.
Table 10-2. AITC Module Register Memory Map
Description
Name
Address
Interrupt Control Register
INTCNTL
0x00223000
Normal Interrupt Mask Register
NIMASK
0x00223004
Interrupt Enable Number Register
INTENNUM
0x00223008
Interrupt Disable Number Register
INTDISNUM
0x0022300C
Interrupt Enable Register High
INTENABLEH
0x00223010
Interrupt Enable Register Low
INTENABLEL
0x00223014
Interrupt Type Register High
INTTYPEH
0x00223018
Interrupt Type Register Low
INTTYPEL
0x0022301C
Normal Interrupt Priority Level Register 7
NIPRIORITY7
0x00223020
Normal Interrupt Priority Level Register 6
NIPRIORITY6
0x00223024
Normal Interrupt Priority Level Register 5
NIPRIORITY5
0x00223028
Normal Interrupt Priority Level Register 4
NIPRIORITY4
0x0022302C
Normal Interrupt Priority Level Register 3
NIPRIORITY3
0x00223030
Normal Interrupt Priority Level Register 2
NIPRIORITY2
0x00223034
Normal Interrupt Priority Level Register 1
NIPRIORITY1
0x00223038
Normal Interrupt Priority Level Register 0
NIPRIORITY0
0x0022303C
Normal Interrupt Vector and Status Register
NIVECSR
0x00223040
Fast Interrupt Vector and Status Register
FIVECSR
0x00223044
Interrupt Source Register High
INTSRCH
0x00223048
Interrupt Source Register Low
INTSRCL
0x0022304C
Interrupt Force Register High
INTFRCH
0x00223050
Interrupt Force Register Low
INTFRCL
0x00223054
Normal Interrupt Pending Register High
NIPNDH
0x00223058
Normal Interrupt Pending Register Low
NIPNDL
0x0022305C
Fast Interrupt Pending Register High
FIPNDH
0x00223060
Fast Interrupt Pending Register Low
FIPNDL
0x00223064
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Programming Model
Table 10-3. Register Field Summary
Name
31 30 29 28 27 26 25 24 23 22 21
R 0
0
0
0
0
0
0
0
0
0
20
19
0
INTCNTL
18
17
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
0
0
0
0
0
0
0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0 0 0 0 0 0
NIAD FIAD
W
R 0
0
0
0
0
0
0
0
0
0
0
0
0
NIMASK
NIMASK
W
R 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0 0 0 0 0 0 0 0 0
INTENNUM
W
R 0
ENNUM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0 0 0 0 0 0 0 0 0
INTDISNUM
W
DISNUM
R
INTENABLEH
INTENABLE [63:32]
W
R
INTENABLEL
INTENABLE [31:0]
W
R
INTTYPEH
INTTYPE [63:32]
W
R
INTTYPEL
INTTYPE [31:0]
W
R
NIPRIORITY7
NIPR63
NIPR62
NIPR61
NIPR60
NIPR59
NIPR58
NIPR57
NIPR56
NIPR55
NIPR54
NIPR53
NIPR52
NIPR51
NIPR50
NIPR49
NIPR48
NIPR47
NIPR46
NIPR45
NIPR44
NIPR43
NIPR42
NIPR41
NIPR40
NIPR39
NIPR38
NIPR37
NIPR36
NIPR35
NIPR34
NIPR33
NIPR32
NIPR31
NIPR30
NIPR29
NIPR28
NIPR27
NIPR26
NIPR25
NIPR24
NIPR23
NIPR22
NIPR21
NIPR20
NIPR19
NIPR18
NIPR17
NIPR16
NIPR15
NIPR14
NIPR13
NIPR12
NIPR11
NIPR10
NIPR9
NIPR8
NIPR7
NIPR6
NIPR5
NIPR4
NIPR3
NIPR2
NIPR1
NIPR0
W
R
NIPRIORITY6
W
R
NIPRIORITY5
W
R
NIPRIORITY4
W
R
NIPRIORITY3
W
R
NIPRIORITY2
W
R
NIPRIORITY1
W
R
NIPRIORITY0
W
R
NIVECTOR
NIPRILVL
NIVECSR
W
R
FIVECTOR
FIVECSR
W
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
10-5
Programming Model
Table 10-3. Register Field Summary (continued)
Name
31 30 29 28 27 26 25 24 23 22 21
20
19
R
18
17
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTIN [63:32]
INTSRCH
W
R
INTIN [31:0]
INTSRCL
W
R
INTFRCH
FORCE [63:32]
W
R
INTFRCL
FORCE [31:0]
W
R
NIPEND [63:32]
NIPNDH
W
R
NIPEND [31:0]
NIPNDL
W
R
FIPEND [63:32]
FIPNDH
W
R
FIPEND [31:0]
FIPNDL
W
10.4.1 Interrupt Control Register
The Interrupt Control Register (INTCNTL) is located on the ARM920T processor’s native bus, is accessible in 1
cycle, and can be accessed only in supervisor mode. This register must be accessed only on word (32-bit)
boundaries.
INTCNTL
BIT
TYPE
31
Addr
0x00223000
Interrupt Control Register
30
29
28
27
26
25
24
23
22
21
20
19
NIAD
FIAD
18
17
16
r
r
r
r
r
r
r
r
r
r
r
rw
rw
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MXS Reference Manual, Rev. 1.1
10-6
Freescale Semiconductor
Programming Model
Table 10-4. Interrupt Control Register Description
Name
Description
Reserved
Bits 31–21
Reserved—These bits are reserved and should read 0.
NIAD
Bit 20
Normal Interrupt Arbiter Disable—Enables/Disables the assertion of a
bus request to the ARM9 core when the normal interrupt signal (nIRQ) is
asserted. When an alternate master has ownership of the bus when a
normal interrupt occurs, the bus is given back to the ARM9 core after the
DMA device has completed its accesses, so the IRQ_DIS bit does not
affect alternate master accesses that are in progress.
Settings
0 = Disregard the normal interrupt
flag when evaluating bus
requests
1 = Normal interrupt flag prevents
alternate masters from
accessing the system bus
Note: To prevent an alternate master from accessing the bus during
an interrupt service routine, do not clear the interrupt flag until the end of
the service routine.
FIAD
Bit 19
Fast Interrupt Arbiter Disable—Enables/Disables the assertion of a
bus request to the ARM9 core when the fast interrupt signal (nFIQ) is
asserted. When an alternate master has ownership of the bus when a
fast interrupt occurs, the bus is given back to the ARM9 core after the
DMA device has completed its accesses, so the IRQ_DIS bit does not
affect alternate master accesses that are in progress.
0 = Disregard the fast interrupt flag
when evaluating bus requests
1 = Fast interrupt flag prevents
alternate masters from
accessing the system bus
Note: To prevent an alternate master from accessing the bus during
an interrupt service routine, do not clear the interrupt flag until the end of
the service routine.
Reserved
Bits 18–0
Reserved—These bits are reserved and should read 0.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
10-7
Programming Model
10.4.2 Normal Interrupt Mask Register
The Normal Interrupt Mask Register (NIMASK) controls the normal interrupt mask level. All normal interrupts
with a priority level less than or equal to the NIMASK are disabled. The priority levels of normal interrupts are
determined by the normal interrupt priority level registers (NIPRIORITY7, NIPRIORITY6, NIPRIORITY5,
NIPRIORITY4, NIPRIORITY3, NIPRIORITY2, NIPRIORITY1, and NIPRIORITY0). The reset state of this
register does not disable any normal interrupts.
Writing all 1’s, or –1, to the NIMASK sets the normal interrupt mask to –1 and does not disable any normal
interrupt priority levels.
This hardware mechanism creates reentrant normal interrupt routines by disabling lower priority normal interrupts.
Refer to Section 10.5.6, “Writing Reentrant Normal Interrupt Routines,” on page 10-35 for more details on the use
of the NIMASK register.
This register is located on the ARM920T processor’s native bus, is accessible in 1 cycle, and can be accessed only
in supervisor mode. This register must be accessed only on word (32-bit) boundaries.
NIMASK
Addr
0x00223004
Normal Interrupt Mask Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
NIMASK
TYPE
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
RESET
0x001F
Table 10-5. Normal Interrupt Mask Register Description
Name
Description
Reserved
Bits 31–5
Reserved—These bits are reserved and should read 0.
NIMASK
Bits 4–0
Normal Interrupt Mask—Controls normal interrupt
mask level. All normal interrupts of priority level less
than or equal to the NIMASK are disabled. Settings
are shown in decimal. Setting bit 4 disables all normal
interrupts.
Settings
0 = Disable priority level 0 normal interrupts
1 = Disable priority level 1 and lower normal interrupts
...
16+ = Disable all normal interrupts.
MC9328MXS Reference Manual, Rev. 1.1
10-8
Freescale Semiconductor
Programming Model
10.4.3 Interrupt Enable Number Register
The Interrupt Enable Number Register (INTENNUM) provides hardware accelerated enabling of interrupts. Any
write to INTENNUM enables one interrupt source. For example, when the 6 LSBs = 000000, interrupt source 0 is
enabled; when the 6 LSBs = 000001, interrupt source 1 is enabled, and so forth. This register is decoded into a
single hot mask that is logically ORed with the INTENABLEH and the INTENABLEL registers.
This hardware mechanism removes the requirement for an atomic read/modify/write sequence to enable an
interrupt source. For example, to enable interrupts 10 and 20, the software performs two writes to the AITC: first
write 10, then write 20 to the INTENNUM register (the order of the writes is irrelevant to the AITC).
This register is located on the ARM920T processor’s native bus, is accessible in 1 cycle, and can be accessed only
in supervisor mode. This register must be accessed only on word (32-bit) boundaries. This register is self-clearing
and therefore always reads back all 0s.
INTENNUM
Addr
0x00223008
Interrupt Enable Number Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
ENNUM
TYPE
r
r
r
r
r
r
r
r
r
r
slfclr
slfclr
slfclr
slfclr
slfclr
slfclr
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-6. Interrupt Enable Number Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
ENNUM
Bits 5–0
Interrupt Enable Number—Enables/Disables the interrupt
source associated with this value.
Settings
0x00 = Enable interrupt source 0
0x01 = Enable interrupt source 1
...
0x3F = Enable interrupt source 63
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
10-9
Programming Model
10.4.4 Interrupt Disable Number Register
The Interrupt Disable Number Register (INTDISNUM) provides hardware accelerated disabling of interrupts. Any
write to this register disables one interrupt source. When the 6 LSBs = 000000, then interrupt source 0 is disabled;
when the 6 LSBs = 000001, then interrupt source 1 is disabled, and so forth. This register is decoded into a single
hot mask that is inverted and logically ANDed with the INTENABLEH and the INTENABLEL registers.
This hardware mechanism removes the requirement for an atomic read/modify/write sequence to disable an
interrupt source. To disable interrupts 10 and 20, the software performs two writes to the AITC: first write 10, then
write 20 to INTDISNUM register (the order of the writes is irrelevant to the AITC).
This register is located on the ARM920T processor’s native bus, is accessible in 1 cycle, and can be accessed only
in supervisor mode. This register must be accessed only on word (32-bit) boundaries. This register is self-clearing
and therefore always reads back all 0s.
INTDISNUM
Addr
0x0022300C
Interrupt Disable Number Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DISNUM
TYPE
r
r
r
r
r
r
r
r
r
r
slfclr
slfclr
slfclr
slfclr
slfclr
slfclr
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-7. Interrupt Disable Number Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
DISNUM
Bits 5–0
Interrupt Disable Number—Enables/Disables the
interrupt source associated with this value.
Settings
0x00 = Disable interrupt source 0
0x01 = Disable interrupt source 1
...
0x3F = Disable interrupt source 63
MC9328MXS Reference Manual, Rev. 1.1
10-10
Freescale Semiconductor
Programming Model
10.4.5 Interrupt Enable Register High and Interrupt Enable Register Low
The Interrupt Enable Register High (INTENABLEH) and the Interrupt Enable Register Low (INTENABLEL)
registers enable pending interrupt requests to the ARM920T processor. Each bit in these registers corresponds to an
interrupt source available in the system. The reset state of both registers is all interrupts masked.
These registers are updated by the following methods:
•
Write directly to the INTENABLEH and INTENABLEL registers
•
Set bits with the INTENNUM register
•
Clear bits with the INTDISNUM register
These registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed
only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.
10.4.5.1 Interrupt Enable Register High
INTENABLEH
BIT
31
30
Addr
0x00223010
Interrupt Enable Register High
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INTENABLE [63:48]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
INTENABLE [47:32]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-8. Interrupt Enable Register High Description
Name
Description
INTENABLE
Bits 31–0
Interrupt Enable—Enables/Disables the individual bit interrupt sources to
request a normal interrupt or a fast interrupt. When INTENABLE is set and the
corresponding interrupt source is asserted, the interrupt controller asserts a
normal or a fast interrupt request depending on the associated INTTYPEH
and INTTYPEL setting.
Settings
0 = Interrupt disabled
1 = Interrupt enabled and
generates a normal or
fast interrupt upon
assertion
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
10-11
Programming Model
10.4.5.2 Interrupt Enable Register Low
INTENABLEL
BIT
31
Addr
0x00223014
Interrupt Enable Register Low
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INTENABLE [31:16]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
INTENABLE [15:0]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-9. Interrupt Enable Register Low Description
Name
Description
Settings
INTENABLE
Bits 31–0
Interrupt Enable—Enables/Disables the individual bit interrupt sources to
request a normal interrupt or a fast interrupt. When INTENABLE is set and the
corresponding interrupt source is asserted, the interrupt controller asserts a
normal or a fast interrupt request depending on the associated INTTYPEH and
INTTYPEL setting.
0 = Interrupt disabled
1 = Interrupt enabled and
generates a normal or
fast interrupt upon
assertion
MC9328MXS Reference Manual, Rev. 1.1
10-12
Freescale Semiconductor
Programming Model
10.4.6 Interrupt Type Register High and Interrupt Type Register Low
The Interrupt Type Register High (INTTYPEH) and the Interrupt Type Register Low (INTTYPEL) registers select
whether a pending interrupt source, when enabled with the INTENABLEH and INTENABLEL registers, creates a
normal interrupt or a fast interrupt to the ARM920T processor. Each bit in this register corresponds to an interrupt
source available in the system. The reset state of both registers is all interrupts generate a normal interrupt.
These registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed
only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.
10.4.6.1 Interrupt Type Register High
INTTYPEH
BIT
31
Addr
0x00223018
Interrupt Type Register High
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INTTYPE [63:48]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
INTTYPE [47:32]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-10. Interrupt Type Register High Description
Name
INTTYPE
Bits 31–0
Description
Interrupt Type—Controls whether the individual interrupt sources
request a normal interrupt or a fast interrupt.
When a INTTYPE bit is set and the corresponding interrupt source is
asserted, the interrupt controller asserts a fast interrupt request.
Settings
0 = Interrupt source generates a
normal interrupt (nIRQ)
1 = Interrupt source generates a fast
interrupt (nFIQ)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
10-13
Programming Model
10.4.6.2 Interrupt Type Register Low
INTTYPEL
BIT
31
Addr
0x0022301C
Interrupt Type Register Low
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INTTYPE [31:16]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
INTTYPE [15:0]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-11. Interrupt Type Register Low Description
Name
INTTYPE
Bits 31–0
Description
Settings
Interrupt Type—Controls whether the individual interrupt sources
request a normal interrupt or a fast interrupt.
When a bit is set in INTTYPE and the corresponding interrupt source
is asserted, the interrupt controller asserts a fast interrupt request.
0 = Interrupt source generates a
normal interrupt (nIRQ)
1 = Interrupt source generates a fast
interrupt (nFIQ)
10.4.7 Normal Interrupt Priority Level Registers
The normal interrupt priority level registers (NIPRIORITY7, NIPRIORITY6, NIPRIORITY5, NIPRIORITY4,
NIPRIORITY3, NIPRIORITY2, NIPRIORITY1, and NIPRIORITY0) provide a software controllable
prioritization of normal interrupts. Normal interrupts with a higher priority level preempt normal interrupts with a
lower priority. The reset state of these registers forces all normal interrupts to the lowest priority level.
When a level 0 normal interrupt and a level 1 normal interrupt are asserted at the same time, the level 1 normal
interrupt is selected assuming that NIMASK has not disabled level 1 normal interrupts. When two level 1 normal
interrupts are asserted at the same time, the level 1 normal interrupt with the highest source number is selected, also
assuming that NIMASK has not disabled level 1 normal interrupts.
These registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed
only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.
MC9328MXS Reference Manual, Rev. 1.1
10-14
Freescale Semiconductor
Programming Model
10.4.7.1 Normal Interrupt Priority Level Register 7
NIPRIORITY7
BIT
31
30
29
28
27
NIPR63
TYPE
Addr
0x00223020
Normal Interrupt Priority Level Register 7
26
25
24
23
NIPR62
22
21
20
19
NIPR61
18
17
16
NIPR60
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
NIPR59
TYPE
10
9
8
NIPR58
NIPR57
NIPR56
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-12. Normal Interrupt Priority Level Register 7 Description
Name
Description
NIPR63
Bits 31–28
Normal Interrupt Priority Level—Selects the software controlled
priority level for the associated normal interrupt source.
NIPR62
Bits 27–24
These registers do not affect the prioritization of fast interrupt
priorities.
Settings
0000 = Lowest priority normal interrupt
...
1111 = Highest priority normal interrupt
NIPR61
Bits 23–20
NIPR60
Bits 19–16
NIPR59
Bits 15–12
NIPR58
Bits 11–8
NIPR57
Bits 7–4
NIPR56
Bits 3–0
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
10-15
Programming Model
10.4.7.2 Normal Interrupt Priority Level Register 6
NIPRIORITY6
BIT
31
30
29
28
27
NIPR55
TYPE
Addr
0x00223024
Normal Interrupt Priority Level Register 6
26
25
24
23
NIPR54
22
21
20
19
NIPR53
18
17
16
NIPR52
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
l6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
NIPR51
TYPE
10
9
8
NIPR50
NIPR49
NIPR48
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-13. Normal Interrupt Priority Level Register 6 Description
Name
Description
Settings
NIPR55
Bits 31–28
Normal Interrupt Priority Level—Selects the software controlled
priority level for the associated normal interrupt source.
0000 = Lowest priority normal interrupt
...
1111 = Highest priority normal interrupt
NIPR54
Bits 27–24
These registers do not affect the prioritization of fast interrupt
priorities.
NIPR53
Bits 23–20
NIPR52
Bits 19–16
NIPR51
Bits 15–12
NIPR50
Bits 11–8
NIPR49
Bits 7–4
NIPR48
Bits 3–0
MC9328MXS Reference Manual, Rev. 1.1
10-16
Freescale Semiconductor
Programming Model
10.4.7.3 Normal Interrupt Priority Level Register 5
NIPRIORITY5
BIT
31
30
29
28
27
NIPR47
TYPE
Addr
0x00223028
Normal Interrupt Priority Level Register 5
26
25
24
23
NIPR46
22
21
20
19
NIPR45
18
17
16
NIPR44
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
NIPR43
TYPE
10
9
8
NIPR42
NIPR41
NIPR40
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-14. Normal Interrupt Priority Level Register 5 Description
Name
Description
NIPR47
Bits 31–28
Normal Interrupt Priority Level—Selects the software controlled
priority level for the associated normal interrupt source.
NIPR46
Bits 27–24
These registers do not affect the prioritization of fast interrupt
priorities.
Settings
0000 = Lowest priority normal interrupt
...
1111 = Highest priority normal interrupt
NIPR45
Bits 23–20
NIPR44
Bits 19–16
NIPR43
Bits 15–12
NIPR42
Bits 11–8
NIPR41
Bits 7–4
NIPR40
Bits 3–0
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
10-17
Programming Model
10.4.7.4 Normal Interrupt Priority Level Register 4
NIPRIORITY4
BIT
31
30
29
28
27
NIPR39
TYPE
Addr
0x0022302C
Normal Interrupt Priority Level Register 4
26
25
24
23
NIPR38
22
21
20
19
NIPR37
18
17
16
NIPR36
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
NIPR35
TYPE
10
9
8
NIPR34
NIPR33
NIPR32
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-15. Normal Interrupt Priority Level Register 4 Description
Name
Description
NIPR39
Bits 31–28
Normal Interrupt Priority Level—Selects the software controlled
priority level for the associated normal interrupt source.
NIPR38
Bits 27–24
These registers do not affect the prioritization of fast interrupt
priorities.
Settings
0000 = Lowest priority normal interrupt
...
1111 = Highest priority normal interrupt
NIPR37
Bits 23–20
NIPR36
Bits 19–16
NIPR35
Bits 15–12
NIPR34
Bits 11–8
NIPR33
Bits 7–4
NIPR32
Bits 3–0
MC9328MXS Reference Manual, Rev. 1.1
10-18
Freescale Semiconductor
Programming Model
10.4.7.5 Normal Interrupt Priority Level Register 3
NIPRIORITY3
BIT
31
30
29
28
27
NIPR31
TYPE
Addr
0x00223030
Normal Interrupt Priority Level Register 3
26
25
24
23
22
NIPR30
21
20
19
NIPR29
18
17
16
NIPR28
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
NIPR27
TYPE
10
9
8
NIPR26
NIPR25
NIPR24
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-16. Normal Interrupt Priority Level Register 3 Description
Name
NIPR31
Bits 31–28
NIPR30
Bits 27–24
Description
Normal Interrupt Priority Level—Selects the software
controlled priority level for the associated normal interrupt
source.
Settings
0000 = Lowest priority normal interrupt
...
1111 = Highest priority normal interrupt
These registers do not affect the prioritization of fast interrupt
priorities.
NIPR29
Bits 23–20
NIPR28
Bits 19–16
NIPR27
Bits 15–12
NIPR26
Bits 11–8
NIPR25
Bits 7–4
NIPR24
Bits 3–0
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
10-19
Programming Model
10.4.7.6 Normal Interrupt Priority Level Register 2
NIPRIORITY2
BIT
31
30
29
28
27
NIPR23
TYPE
Addr
0x00223034
Normal Interrupt Priority Level Register 2
26
25
24
23
NIPR22
22
21
20
19
NIPR21
18
17
16
NIPR20
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
NIPR19
TYPE
10
9
8
NIPR18
NIPR17
NIPR16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-17. Normal Interrupt Priority Level Register 2 Description
Name
NIPR23
Bits 31–28
NIPR22
Bits 27–24
Description
Normal Interrupt Priority Level—Selects the software
controlled priority level for the associated normal interrupt
source.
Settings
0000 = Lowest priority normal interrupt
...
1111 = Highest priority normal interrupt
These registers do not affect the prioritization of fast interrupt
priorities.
NIPR21
Bits 23–20
NIPR20
Bits 19–16
NIPR19
Bits 15–12
NIPR18
Bits 11–8
NIPR17
Bits 7–4
NIPR16
Bits 3–0
MC9328MXS Reference Manual, Rev. 1.1
10-20
Freescale Semiconductor
Programming Model
10.4.7.7 Normal Interrupt Priority Level Register 1
NIPRIORITY1
BIT
31
30
29
28
27
NIPR15
TYPE
Addr
0x00223038
Normal Interrupt Priority Level Register 1
26
25
24
23
NIPR14
22
21
20
19
NIPR13
18
17
16
NIPR12
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
NIPR11
TYPE
10
9
8
NIPR10
NIPR9
NIPR8
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-18. Normal Interrupt Priority Level Register 1 Description
Name
NIPR15
Bits 31–28
NIPR14
Bits 27–24
Description
Normal Interrupt Priority Level—Selects the software
controlled priority level for the associated normal interrupt
source.
Settings
0000 = Lowest priority normal interrupt
...
1111 = Highest priority normal interrupt
These registers do not affect the prioritization of fast interrupt
priorities.
NIPR13
Bits 23–20
NIPR12
Bits 19–16
NIPR11
Bits 15–12
NIPR10
Bits 11–8
NIPR9
Bits 7–4
NIPR8
Bits 3–0
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
10-21
Programming Model
10.4.7.8 Normal Interrupt Priority Level Register 0
NIPRIORITY0
BIT
31
30
29
28
27
26
NIPR7
TYPE
Addr
0x0022303C
Normal Interrupt Priority Level Register 0
25
24
23
22
NIPR6
21
20
19
18
NIPR5
17
16
NIPR4
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
NIPR3
TYPE
9
8
NIPR2
NIPR1
NIPR0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-19. Normal Interrupt Priority Level Register 0 Description
Name
NIPR7
Bits 31–28
NIPR6
Bits 27–24
Description
Normal Interrupt Priority Level—Selects the software
controlled priority level for the associated normal interrupt
source.
Settings
0000 = Lowest priority normal interrupt
...
1111 = Highest priority normal interrupt
These registers do not affect the prioritization of fast interrupt
priorities.
NIPR5
Bits 23–20
NIPR4
Bits 19–16
NIPR3
Bits 15–12
NIPR2
Bits 11–8
NIPR1
Bits 7–4
NIPR0
Bits 3–0
MC9328MXS Reference Manual, Rev. 1.1
10-22
Freescale Semiconductor
Programming Model
10.4.8 Normal Interrupt Vector and Status Register
The Normal Interrupt Vector and Status Register (NIVECSR) specifies the priority of the highest pending normal
interrupt and provides the vector index of the interrupt’s service routine. This number can be directly used as an
index into a vector table to select the highest pending normal interrupt source.
This read-only register is located on the ARM920T processor’s native bus, is accessible in 1 cycle, and can be
accessed only in supervisor mode. This register must be accessed only on word (32-bit) boundaries.
NIVECSR
BIT
31
Addr
0x00223040
Normal Interrupt Vector and Status Register
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
NIVECTOR
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
RESET
0xFFFF
BIT
15
14
13
12
11
10
9
8
NIPRILVL
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
0xFFFF
Table 10-20. Normal Interrupt Vector and Status Register Description
Name
Description
Settings
NIVECTOR
Bits 31–16
Normal Interrupt Vector—Indicates vector index for the
highest pending normal interrupt. Settings are shown in
decimal.
0 = Interrupt 0 highest priority pending normal
interrupt
1 = Interrupt 1 highest priority pending normal
interrupt
...
63 = Interrupt 63 highest priority pending
normal interrupt
64+ = No normal interrupt request pending
NIPRILVL
Bits 15–0
Normal Interrupt Priority Level—Indicates the priority level
of the highest priority normal interrupt. This number can be
written to the NIMASK to disable the current priority normal
interrupts to build a reentrant normal interrupt system.
Settings are shown in decimal.
0 = Highest priority normal interrupt is level 0
1 = Highest priority normal interrupt is level 1
...
15 = Highest priority normal interrupt is level 15
16+ = No normal interrupt request pending
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
10-23
Programming Model
10.4.9 Fast Interrupt Vector and Status Register
The Fast Interrupt Vector and Status Register (FIVECSR) specifies the priority of the highest pending fast interrupt
and provides the vector index for the interrupt’s service routine. This number can be directly used as an index into
a vector table to select the highest pending fast interrupt source.
This read-only register is located on the ARM920T processor’s native bus, is accessible in 1 cycle, and can be
accessed only in supervisor mode. This register must be accessed only on word (32-bit) boundaries.
FIVECSR
BIT
31
Addr
0x00223044
Fast Interrupt Vector and Status Register
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FIVECTOR [31:16]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
RESET
0xFFFF
BIT
15
14
13
12
11
10
9
8
FIVECTOR [15:0]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
0xFFFF
Table 10-21. Fast Interrupt Vector and Status Register Description
Name
FIVECTOR
Bits 31–0
Description
Fast Interrupt Vector—Indicates vector index for
the highest pending fast interrupt.
Settings
0 = Interrupt 0 is highest pending fast interrupt
1 = Interrupt 1 is highest pending fast interrupt
...
63 = Interrupt 63 is highest pending fast interrupt
64+ = not used, does not occur
MC9328MXS Reference Manual, Rev. 1.1
10-24
Freescale Semiconductor
Programming Model
10.4.10 Interrupt Source Register High and Interrupt Source Register Low
The Interrupt Source Register High (INTSRCH) and the Interrupt Source Register Low (INTSRCL) registers are
each 32 bits wide. INTSRCH and INTSRCL reflect the status of all interrupt request inputs into the interrupt
controller. Bit positions that are not used always read 0 (no request pending). The peripheral circuits generating the
requests determine the state of this register out of reset; normally, the requests are inactive.
These read-only registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be
accessed only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.
10.4.10.1 Interrupt Source Register High
INTSRCH
BIT
31
Addr
0x00223048
Interrupt Source Register High
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INTIN [63:48]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
INTIN [47:32]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-22. Interrupt Source Register High Description
Name
INTIN
Bits 31–0
Description
Interrupt Source—Indicates the state of the corresponding hardware
interrupt source.
Settings
0 = Interrupt source negated
1 = Interrupt source asserted
NOTE:
The peripheral circuits generating the requests determine the state of this register
out of reset; normally, the requests are inactive. This read-only register must be
accessed only on word (32-bit) boundaries.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
10-25
Programming Model
10.4.10.2 Interrupt Source Register Low
INTSRCL
BIT
31
Addr
0x0022304C
Interrupt Source Register Low
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INTIN [31:16]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
INTIN [15:0]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-23. Interrupt Source Register Low Description
Name
INTIN
Bits 31–0
Description
Interrupt Source—Indicates the state of the corresponding hardware
interrupt source.
Settings
0 = Interrupt source negated
1 = Interrupt source asserted
NOTE:
The state of this register out of reset is determined by the peripheral circuits
generating the requests; normally, the requests are inactive. This read-only register
must be accessed only on word (32-bit) boundaries.
MC9328MXS Reference Manual, Rev. 1.1
10-26
Freescale Semiconductor
Programming Model
10.4.11 Interrupt Force Register High and Interrupt Force Register Low
The Interrupt Force Register High (INTFRCH) and the Interrupt Force Register Low (INTFRCL) registers are each
32 bits wide. The interrupt forces registers allow for software generation of interrupts for each of the possible
interrupt sources for functional or debugging purposes. The system level design can reserve one or more sources
for software purposes to allow software to self-schedule interrupts by forcing one or more of these sources in the
appropriate interrupt force register(s).
These registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed
only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.
10.4.11.1 Interrupt Force Register High
INTFRCH
BIT
31
Addr
0x00223050
Interrupt Force Register High
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FORCE [63:48]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
FORCE [47:32]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-24. Interrupt Force Register High Description
Name
FORCE
Bits 31–0
Description
Interrupt Source Force Request—Forces a request for the
corresponding interrupt source.
Settings
0 = Standard interrupt operation
1 = Interrupt forced asserted
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
10-27
Programming Model
10.4.11.2 Interrupt Force Register Low
INTFRCL
BIT
31
Addr
0x00223054
Interrupt Force Register Low
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FORCE [31:16]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
FORCE [15:0]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-25. Interrupt Force Register Low Description
Name
FORCE
Bits 31–0
Description
Interrupt Source Force Request—Forces a request for the
corresponding interrupt source.
Settings
0 = Standard interrupt operation
1 = Interrupt forced asserted
MC9328MXS Reference Manual, Rev. 1.1
10-28
Freescale Semiconductor
Programming Model
10.4.12 Normal Interrupt Pending Register High and Normal Interrupt
Pending Register Low
The Normal Interrupt Pending Register High (NIPNDH) and the Normal Interrupt Pending Register Low
(NIPNDL) registers are 32-bits wide and monitor the outputs of the enable and masking operations. These registers
are actually only a set of buffers, so the reset state of these registers is determined by the normal interrupt enable
registers, the interrupt mask register, and the interrupt source registers.
These read-only registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be
accessed only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.
10.4.12.1 Normal Interrupt Pending Register High
NIPNDH
BIT
Addr
0x00223058
Normal Interrupt Pending Register High
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
NIPEND [63:48]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
NIPEND [47:32]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-26. Normal Interrupt Pending Register High Description
Name
Description
Settings
NIPEND
Bits 31–0
Normal Interrupt Pending Bit—Indicates whether a normal interrupt is
pending. When a normal interrupt enable bit is set and the
corresponding interrupt source is asserted, the interrupt controller
asserts a normal interrupt request. The normal interrupt pending bits
reflect the interrupt input lines that are asserted and are currently
enabled to generate a normal interrupt.
0 = No normal interrupt request
1 = Normal interrupt request pending
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
10-29
Programming Model
10.4.12.2 Normal Interrupt Pending Register Low
NIPNDL
BIT
Addr
0x0022305C
Normal Interrupt Pending Register Low
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
NIPEND [31:16]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
NIPEND [15:0]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-27. Normal Interrupt Pending Register Low Description
Name
Description
Settings
NIPEND
Bits 31–0
Normal Interrupt Pending Bit—Indicates whether a normal interrupt is
pending. When a normal interrupt enable bit is set and the
corresponding interrupt source is asserted, the interrupt controller
asserts a normal interrupt request. The normal interrupt pending bits
reflect the interrupt input lines that are asserted and are currently
enabled to generate a normal interrupt.
0 = No normal interrupt request
1 = Normal interrupt request pending
MC9328MXS Reference Manual, Rev. 1.1
10-30
Freescale Semiconductor
Programming Model
10.4.13 Fast Interrupt Pending Register High and Fast Interrupt Pending
Register Low
The Fast Interrupt Pending Register High (FIPNDH) and the Fast Interrupt Pending Register Low (FIPNDL)
registers are 32-bits wide and monitor the outputs of the enable and masking operations. These registers are
actually only a set of buffers, so the reset state of these registers is determined by the fast interrupt enable registers,
the interrupt mask register, and the interrupt source registers.
These read-only registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be
accessed only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.
10.4.13.1 Fast Interrupt Pending Register High
FIPNDH
BIT
Addr
0x00223060
Fast Interrupt Pending Register High
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FIPEND [63:48]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
FIPEND [47:32]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-28. Fast Interrupt Pending Register High Description
Name
FIPEND
Bits 31–0
Description
Settings
Fast Interrupt Pending Bit—Indicates if a fast interrupt request is
pending. When a fast interrupt enable bit is set and the corresponding
interrupt source is asserted, the interrupt controller asserts a fast
interrupt request. The fast interrupt pending bits reflect the interrupt input
lines that are asserted and are currently enabled to generate a fast
interrupt.
0 = No fast interrupt request
pending
1 = Fast interrupt request pending
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
10-31
Programming Model
10.4.13.2 Fast Interrupt Pending Register Low
FIPNDL
BIT
Addr
0x00223064
Fast Interrupt Pending Register Low
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FIPEND [31:16]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
FIPEND [15:0]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-29. Fast Interrupt Pending Register Low Description
Name
Description
Settings
FIPEND
Bits 31–0
Fast Interrupt Pending Bit—Indicates if a fast interrupt request is
pending. When a fast interrupt enable bit is set and the corresponding
interrupt source is asserted, the interrupt controller asserts a fast interrupt
request. The fast interrupt pending bits reflect the interrupt input lines that
are asserted and are currently enabled to generate a fast interrupt.
0 = No fast interrupt request
pending
1 = Fast interrupt request pending
MC9328MXS Reference Manual, Rev. 1.1
10-32
Freescale Semiconductor
ARM920T Processor Interrupt Controller Operation
10.5 ARM920T Processor Interrupt Controller Operation
This section discusses the ARM920T processor prioritization of various exceptions and interrupt sources, two
methods of enabling or disabling interrupts, and provides a typical pipeline sequence.
10.5.1 ARM920T Processor Prioritization of Exception Sources
The ARM920T processor prioritizes the various exceptions as follows:
•
Reset (highest priority)
•
Data Abort
•
Fast Interrupt
•
Normal Interrupt
•
Prefetch Abort
•
Undefined Instruction and SWI (lowest priority)
10.5.2 AITC Prioritization of Interrupt Sources
The AITC module prioritizes the various interrupt sources by source number. Higher source numbers have higher
priority. Fast interrupts always have higher priority than normal interrupts.
Interrupt requests are prioritized as follows:
1. Fast interrupt requests, in order of highest source number
2. Normal interrupt requests, in order of highest priority level, then in order of highest source number
with the same priority level
10.5.3 Assigning and Enabling Interrupt Sources
The interrupt controller provides flexible assignment of any interrupt source to either of the two ARM920T
processor interrupt request inputs. This is done by setting the appropriate bits in the INTENABLEH and
INTENABLEL registers and the INTTYPEH and INTTYPEL registers. Interrupt assignment is usually done once
during system initialization and does not affect interrupt latency.
Interrupt assignment is the first of three steps required to enable an interrupt source, and this is done by the
MC9328MXS hardware. The second step is to program the source to generate interrupt requests. The final step is
to enable the interrupt inputs in the ARM920T processor by clearing the normal interrupt disable (I) and/or the fast
interrupt disable (F) bits in the processor status register (CPSR).
10.5.4 Enabling Interrupts Sources
There are two methods of enabling or disabling interrupts in the AITC. The first method is to directly read the
INTENABLEH and INTENABLEL registers, logically OR or BIT CLEAR these registers with a generated mask,
then write back to the INTENABLEH and INTENABLEL registers.
The second method is performing an atomic write to source number of the INTENNUM register. The AITC
decodes this 6-bit register and enables one of the 64 interrupt sources. The AITC automatically generates a single
hot enable mask and logically ORs this mask to the correct INTENABLEH and INTENABLEL register. To disable
interrupts, the procedure is exactly the same except the source number is written to the INTDISNUM register.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
10-33
ARM920T Processor Interrupt Controller Operation
10.5.5 Typical Interrupt Entry Sequences
The Table 10-30 is a typical pipeline sequence for the ARM920T processor when a normal interrupt occurs.
Assuming single cycle memories, it takes approximately 6 clocks from the acknowledgement of the normal
interrupt within the ARM920T processor until the first opcode of the interrupt routine is fetched.
Table 10-30. Typical Hardware Accelerated Normal Interrupt Entry Sequence
Time
Address
–2
–1
nIRQ
Assert
Last ADDR
before nIRQ
1
2
3
4
5
Link
Adjust
Fetch
Dec
Exec
Data
Wrbk
Fetch
Dec
6
7
8
Fetch
Dec
Exec
Fetch
Dec
nIRQ
ACK
Fetch
+4 / +2
0
Dec
Exec
Fetch
Dec
+8 / +4
Fetch
0x00000018
+4
+8
Fetch
Vector Table
Vector
N/A
nIRQ Routine
+4
+8
Fetch
The Table 10-31 on page 10-34 is a typical pipeline sequence for the ARM920T processor when a fast interrupt
occurs, assuming that the FIQ service routine begins at 0x0000001C and single cycle memories.
Table 10-31. Typical Fast Interrupt Entry Sequence
Time
Address
–2
–1
nFIQ
Assert
Last ADDR before nFIQ
+4 / +2
+8 / +4
0x0000001C
Fetch
0
1
2
3
Link
Adjust
Fetch
Dec
Exec
Fetch
Dec
nFIQ
ACK
Dec
Exec
Fetch
Dec
Fetch
+4
+8
Fetch
MC9328MXS Reference Manual, Rev. 1.1
10-34
Freescale Semiconductor
ARM920T Processor Interrupt Controller Operation
10.5.6 Writing Reentrant Normal Interrupt Routines
The AITC can create a reentrant normal interrupt system. This enables preempting of lower priority level interrupts
by higher priority level interrupts. This requires a small amount of software support and overhead. The following
shows the steps necessary to accomplish this:
1. Push the link register (LR_IRQ) onto the stack (SP_IRQ).
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Push the saved status register (SPSR_IRQ) onto the stack.
Read the current value of NIMASK and push this value onto the stack.
Read current priority level via NIVECSR.
Interrupts of the equal or lesser priority than the current priority level must be masked via the
NIMASK register by writing value from NIVECSR.
Clear the I bit in the ARM920T processor via a MSR / MRS command sequence (a higher priority
normal interrupt can preempt a lower priority one) and change the operating mode of the ARM920T
processor to system mode from IRQ mode.
Push the System Mode Link Register (LR) onto the stack (SP_USER).
The traditional interrupt service routine is now included.
Pop the System Mode Link Register (LR) from the stack (SP_USER).
Set the I bit in the ARM920T processor via a MSR/MRS command sequence (disables all normal
interrupts) and change the operating mode of the ARM920T processor to IRQ mode from system
mode.
Pop the original value of the normal interrupt mask and write the value to the NIMASK register.
Pop the Saved Status Register from the stack (SP_IRQ).
Pop the link register from the stack into the PC.
Return from nIRQ.
NOTE:
These steps are still in development and are subject to change. Steps 1, 2, 13, and
14 are automatically done by most C compilers and are included for completeness.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
10-35
ARM920T Processor Interrupt Controller Operation
MC9328MXS Reference Manual, Rev. 1.1
10-36
Freescale Semiconductor
Chapter 11
External Interface Module (EIM)
11.1 Overview
The External Interface Module (EIM) handles the interface to devices external to the MC9328MXS, including
generation of chip selects for external peripherals and memory, and provides the following features:
•
Six chip selects for external devices: CS0, covering a range of 32 Mbyte, and CS1–CS5, covering a range
of 16 Mbyte each
•
Selectable protection for each chip select
•
Reset programmable data port size for CS0
•
Programmable data port size for each chip select
•
Address suppression during burst mode operations
•
Synchronous burst mode support for burst flash devices
•
Programmable wait-state generator for each chip select
•
Supports big endian and little endian modes of operation
•
Programmable general output capability for unused chip select outputs
11.2 EIM I/O Signals
The EIM I/O signals provide communication and control pathways between external devices and the
MC9328MXS. A summary of the I/O signal pins is provided in Table 11-2 on page 11-4. Each signal is described
in the following sections.
11.2.1 Address Bus
The A [24:0] signals are address bus outputs used to address external devices.
11.2.2 Data Bus
The D [31:0] signals are bidirectional data bus pins used to transfer data between the MC9328MXS and an external
device.
11.2.3 Read/Write
The R/W output signal indicates if the current bus access is in a read or write cycle. A high (logic one) level
indicates a read cycle, and a low (logic zero) level indicates a write cycle.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
11-1
EIM I/O Signals
11.2.4 Control Signals
The OE and EB [3:0] signals are used to control external device’s interface to the external data bus.
11.2.4.1 OE—Output Enable
This active-low output signal indicates the bus access is a read, and enable slave devices to drive the data bus with
read data.
11.2.4.2 EB [3:0]—Enable Bytes
These active-low output pins indicate active data bytes for the current access. They may be configured to assert for
read and write cycles or for write cycles only as programmed in the CS configuration registers. EB [0] corresponds
to D [31:24], EB [1] corresponds to D [23:16], EB [2] corresponds to D [15:8], and EB [3] corresponds to D [7:0].
In the case of a 16-bit operation, or controlling the enable byte signals for half-word operation, either EB[0] or
EB[1] may be used for D[31:16], and either EB[2] or EB[3] may be used for D[15:0]. For word addressing, any of
on the EB[3:0] signals may be used.
This is especially useful when interfacing to external devices or memories that require strict timing control over the
write enable signal. Since there is no way to control the timing of the EIM WE signal, any one of the EB[3:0]
signals (if not already being used for enable byte control), may be used as the write enable signal. The bits WEA
and WEN in the Chip Select Control registers are used to vary the timing of these signals according to the bit
settings in those registers. The corresponding EB[3:0] signal that can be used for a corresponding set of D[31:0]
signals follows the EB[3:0] to D[31:0] mapping given above.
NOTE:
The pulse of OE, R/W, EB, and CS signals cannot be configured to less than one
system clock period (HCLK).
11.2.4.3 DTACK—Data Transfer Acknowledge
The DTACK signal is the external input data acknowledge signal that only supported by CS[5]. When the external
DTACK signal is used as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus
cycle is not terminated by the external DTACK signal after 1022 clocks counts have elapsed.
The maximum wait state supported by the DTACK signal at 96 MHz is 10.645us. This can be calculated by
dividing the number of maximum wait state cycles (in this case 1022) by the system clock frequency (HCLK). For
designs requiring a longer wait state time greater than 10.645us, it is necessary to reduce the system clock
frequency HCLK to an appropriate value that is less than 96 MHz. The system clock HCLK can be divided by
setting the BLCK_DIV bits in the Clock Source Control Register to the desired value. For more detailed
information about setting the BCLK_DIV bits, see Chapter 12, “Phase-Locked Loop and Clock Controller.”
11.2.5 Chip Select Outputs
11.2.5.1 Chip Select 0 (CS0)
The CS0 output signal is active-low and is asserted based on a decode of internal address bus bits A[31:24] of the
accessed address, and at reset is based on the value of the BOOTMOD [3:0] inputs. The port size is determined by
the state of the BOOTMOD[3:0] inputs. See Section 8.2, “System Boot Mode Selection,” on page 8-7 for more
information.
MC9328MXS Reference Manual, Rev. 1.1
11-2
Freescale Semiconductor
Pin Configuration for EIM
11.2.5.2 Chip Select 1–Chip Select 5 (CS1–CS5)
The CS1 through CS5 output signals are active-low and are asserted based on a decode of the internal address bus
bits A [31:24] of the accessed address. When disabled, these pins can be used as programmable general-purpose
outputs. Table 11-1 specifies the address range for each Chip Select output.
Table 11-1. Chip Select Address Range
CSEN [x]
A [31:24]
Chip Select
Cleared
–
Inactive
Set
0001000x
CS0
Set
00010010
CS1
Set
00010011
CS2
Set
00010100
CS3
Set
00010101
CS4
Set
00010110
CS5
11.2.6 Burst Mode Signals
11.2.6.1 BCLK—Burst Clock
The BCLK output signal is used to clock external burst capable devices to synchronize the loading and
incrementing of addresses, and delivery of burst read data to the EIM. Its behavior is affected by the BCM bit in the
EIM configuration register and the SYNC, BCD, PME, and BCS bits in the EIM control registers.
11.2.6.2 LBA—Load Burst Address
The LBA active-low output signal is asserted during burst mode accesses to cause the external burst capable device
to load a new starting burst address. Assertion of LBA indicates that a valid address is present on the address bus.
Its behavior is affected by the SYNC, BCD, PME, and BCS bits in the EIM control registers.
11.2.6.3 ECB—End Current Burst
The ECB active-low input signal is asserted by external burst capable devices to indicate the end of the current
(continuous) burst sequence. Following assertion, the EIM terminates the current burst sequence and initiates a
new one.
11.3 Pin Configuration for EIM
Table 11-2 lists the pins used for the EIM module. Many of these pins are multiplexed with other functions on the
device, and must be configured for EIM operation.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
11-3
Pin Configuration for EIM
Table 11-2. EIM Pin List
Pin Name
Direction
Description
External I/O Signals
D [31:0]
Input/
Output
External 32-bit data bus
A [24:0]
Output
External address bus
CS [5:0]
Output
Active low external chip selects
DTACK
Input
EB [3:0]
Output
Active low external enable bytes signals. EB [0] controls D [31:24]*
OE
Output
Active low output enable for external data bus
BCLK (burst clock)
Output
Clock for external synchronous memories (such as burst flash) - burst clock.
LBA
Output
Active low signal sent to flash device causing the external device to latch the address.
RW
Output
Indicates whether external access is a read (high) or write (low) cycle
ECB
Input
External input data acknowledge signal for CS5
Input signal identifies when to end an external burst access
*EB [1] controls D [23:16], EB [2] controls D [15:8], EB [3] controls D [7:0]
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 25.5.1, “Data Direction Registers,” on
page 25-8 for details.
Table 11-3. Pin Configuration
Pins
Setting
Configuration Procedure
D [31:0]
Not Multiplexed
A [24]
Primary function of GPIO Port
A [0]
1. Clear bit 0 of Port A GPIO In Use Register (GIUS_A)
2. Clear bit 0 of Port A General Purpose Register (GPR_A)
A [23:16]
Primary function of GPIO Port
A [31:24]
1. Clear bits [31:24] of Port A GPIO In Use Register (GIUS_A)
2. Clear bits [31:24] of Port A General Purpose Register (GPR_A)
A [15:1]
Not Multiplexed
A [0]
Primary function of GPIO Port
A [21]
1. Clear bit 21 of Port A GPIO In Use Register (GIUS_A)
2. Clear bit 21 of Port A General Purpose Register (GPR_A)
CS [5:4]
Primary function of GPIO Port
A [23:22]
1. Clear bits [23:22] of Port A GPIO In Use Register (GIUS_A)
2. Clear bits [23:22] of Port A General Purpose Register (GPR_A)
CS [3]
Primary function of pin shared
with SDRAM’s CSD1
1. Clear bit 1 (SDCS1_SEL) of Function Muxing Control Register (FMCR)
MC9328MXS Reference Manual, Rev. 1.1
11-4
Freescale Semiconductor
Typical EIM System Connections
Table 11-3. Pin Configuration (continued)
Pins
Setting
Configuration Procedure
CS [2]
Primary function of pin shared
with SDRAM’s CSD0
1. Clear bit 0 (SDCS0_SEL) of Function Muxing Control Register (FMCR)
CS [1:0]
Not Multiplexed
DTACK
Primary function of GPIO Port
A[17
EB [3:0]
Not Multiplexed
OE
Not Multiplexed
BCLK
Primary function of GPIO Port
A [18]
1. Clear bit 18 of Port A GPIO In Use Register (GIUS_A)
2. Clear bit 18 of Port A General Purpose Register (GPR_A)
LBA
Primary function of GPIO Port
A [19]
1. Clear bit 19 of Port A GPIO In Use Register (GIUS_A)
2. Clear bit 19 of Port A General Purpose Register (GPR_A)
RW
Not Multiplexed
ECB
Primary function of GPIO Port
A [20]
1. Clear bit 17 of Port A GPIO In Use Register (GIUS_A)
2. Clear bit 17 of the Port A General Purpose Register (GPR_A
1. Clear bit 20 of Port A GPIO In Use Register (GIUS_A)
2. Clear bit 20 of Port A General Purpose Register (GPR_A)
11.4 Typical EIM System Connections
The following figures show example connections of the EIM with burst and asynchronous memories:
•
Figure 11-1 illustrates a typical set of EIM interfaces to external memory and peripherals.
•
Figure 11-2 illustrates the EIM interface to two supported external burst flash devices.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
11-5
Typical EIM System Connections
A [31:0]
A [16:0]
CS2
EB [0]
CS
EB [0]
OE
D [31:0]
EB [0]
EB [1]
CS1
RW
RW
D [31:16]
A [19:1]
EB [2]
OE
D [15:0]
A0
CS3
UBS
LBS
WE
RAM
64Kx16
OE
Data [15:0]
Address [18:0]
AMD
Flash
OE 512Kx16
WE
Data [15:0]
RS
E
R’W
ECB
Address [15:0]
CS
CS0
EB [2]
RAM
128Kx8
Data [7:0]
CS
OE
External
Interface
Module
WE
OE
D [31:24]
A [16:1]
EB [1]
Address [16:0]
D [7:0]
ACIA
R/W
Data [7:0]
LBA
BCLK
A0
CS5
CS4
EB [3]
RS
E
RW
D [7:0]
LCD
Control
R/W
Data [7:0]
Figure 11-1. Example of EIM Interface to Memory and Peripherals
MC9328MXS Reference Manual, Rev. 1.1
11-6
Freescale Semiconductor
Typical EIM System Connections
A [21:2]
A [31:0]
Address [19:0]
LBA
ADV#
CS0
CE#
EB [0]
WE#
OE
OE
BCLK
OE#
AMD
BURST
FLASH
CLK
RDY
ECB
D [31:16]
D [31:0]
DQ [15:0]
1Mx16
External
Interface
Module
A [21:2]
Address [19:0]
ADV#
CS1
CE#
WE#
EB [1]
OE
CS3
BCLK
CS4
OE#
CLK
AMD
BURST
FLASH
RDY
CS5
D [15:0]
DQ [15:0]
1Mx16
A [16:1]
EB [2]
EB [2]
EB [3]
EB [3]
UBS
LBS
CS2
RW
Address [15:0]
CS
RW
RAM
64Kx16
WE
OE
OE
D [15:1]
Data [15:0]
Figure 11-2. Example of EIM Interface to Burst Memory
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
11-7
EIM Functionality
11.5 EIM Functionality
11.5.1 Configurable Bus Sizing
The EIM supports byte, halfword, and word operands, allowing access to 8-bit ports, 16-bit ports, and 32-bit ports.
It does not support misaligned transfers.
The port size is programmable via the DSZ bits in the corresponding chip select control register. In addition, the
portion of the data bus used for transfer to or from an 8-bit port or 16-bit port is programmable via the same bits.
An 8-bit port can reside on external data bus bits D [31:24], D [23:16], D [15:8] or D [7:0]. A 16-bit port can reside
on external data bus bits D [31:16] or D [15:0].
Word access to or from an 8-bit port requires four external bus cycles to complete the transfer. Word access to or
from a 16-bit port requires two external bus cycles to complete the transfer. Half-word access to or from an 8-bit
port requires two external bus cycles to complete the transfer. In the case of a multi-cycle transfer, the lower two
address bits, A [1:0], are incremented appropriately.
The EIM has a data multiplexer that routes the four bytes of the AHB interface data bus to the required positions to
allow proper interfacing to memory and peripherals.
11.5.2 Programmable Output Generation
Unused chip select outputs can be configured to provide a programmable output signal. This functionality is not
provided for the CS [0] output signal. When the CSEN bit is cleared, CS [0] is always inactive. To operate as a
programmable output pin, the corresponding CSEN control bit must be cleared.
11.5.3 Burst Mode Operation
When burst mode is enabled, the EIM attempts to burst read data from as many sequential address locations as
possible, limited only by the length of the burst flash internal page buffer, or the non-sequential nature of the
ARM920T processor code or data stream. The EIM only displays the first address accessed in a burst sequence
unless the page mode emulation (PME) bit is set.
For the first access in a burst sequence, the EIM asserts load burst address (LBA), causing the external burst device
to latch the starting burst address, and then toggles the burst clock (BCLK) for a predefined number of cycles to
latch the first unit of data. Subsequently read data units are burst from the external device in fewer clock cycles,
realizing an overall increase in bus bandwidth.
Burst accesses is terminated by the EIM when it detects that the next ARM920T processor access is not sequential
in nature, or when the external burst device needs additional cycles to retrieve the next requested memory location.
In the latter case, the burst flash device provides an ECB signal to the EIM whenever it must terminate the
on-going burst sequence and initiate a new (long first access) burst sequence.
11.5.4 Burst Clock Divisor
In some cases it is necessary to slow the external bus in relation to the internal bus to allow accesses to burst
devices that have a maximum operating frequency that is lower than the operating frequency of the internal AHB
bus. The internal bus frequency can be divided by 2, 3, or 4 for presentation on the external bus in burst mode
operation.
MC9328MXS Reference Manual, Rev. 1.1
11-8
Freescale Semiconductor
EIM Functionality
Programming the BCD bits to various values (see Table 11-5, "Chip Select Control Registers Description") affects
two signals on the external bus, LBA (load burst address) and BCLK (burst clock). The LBA signal is asserted
immediately and remains asserted until the first falling edge of the BCLK signal. The BCLK signal runs with a
50% duty cycle until a non-sequential internal request is received or an external ECB signal is recognized.
When programming these bits, ensure that the WSC and DOL fields are coordinated to provide the desired external
bus waveforms. For example, when the BCD bits are programmed to 01, the DOL bits must be programmed to
0001, 0011, 0101, … . When the BCD bits are programmed to 10, the DOL must be programmed to 0010, 0101,
1000, … .
The BCM bit in the EIM configuration register has priority over the BCD bits. When BCM = 1, the BCLK runs at
maximum frequency.
11.5.5 Burst Clock Start
To allow greater flexibility in achieving the minimum number of wait states on burst accesses, the user can
determine when they want the BCLK (burst clock) to start toggling. This allows the BCLK to be skewed from the
point of data capture on the system clock by any number of system clock phases. Use caution when setting these
bits in conjunction with the BCD, WSC, and DOL bits. See the external timing diagrams for some examples of
how to use the BCS, BCD, WSC, and DOL bits together.
11.5.6 Page Mode Emulation
Setting the PME bit causes the EIM to perform burst accesses by emulating page mode operation. The LBA signal
remains asserted for the entire access, the burst clock does not send a signal, and the external address asserts for
each access made. The initial access timing is dictated by the WSC bits and the page mode access timing is dictated
by the DOL bits.
The EIM can take advantage of improved page timing for sequential accesses only. Accesses that are on the page,
however are not sequential in nature, have their timing dictated by the WSC bits. The page size can be set via the
PSZ bits to 4, 8, 16, or 32 words (the word size is determined by the data width of the external memory, such as the
DSZ bits).
11.5.7 Error Conditions
The following conditions cause an error condition to be asserted to the ARM920T processor:
•
Access to a disabled chip select (access to a mapped chip select address space where the CSEN bit in the
corresponding chip select control register is clear)
•
Write access to a write-protected chip select address space (the WP bit in the corresponding chip select
control register is set)
•
User access to a supervisor-protected chip select address space (the SP bit in the corresponding chip select
control register is set)
•
User read or write access to a chip select control register or the EIM configuration register
•
Byte or halfword access to a chip select control register or the EIM configuration register
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
11-9
Programming Model
11.6 Programming Model
The EIM module includes thirteen user-accessible 32-bit registers. There is a common register called the EIM
Configuration Register that contains control bits that configure the EIM for certain operation modes. The other
twelve registers are pairs of control registers for each chip select. The layout of the control register is slightly
different for the CS0 register output because CS [0] does not support the programmable output function. These
registers are accessible only in supervisor mode with word (32-bit) reads and writes.
Complete decoding is not performed, so shadowing can occur with these registers. The user must not attempt to
address these registers at any other address location other than those listed in Table 11-4.
Table 11-4. EIM Module Register Memory Map
Description
Name
Address
Chip Select 0 Upper Control Register
CS0U
0x00220000
Chip Select 0 Lower Control Register
CS0L
0x00220004
Chip Select 1 Upper Control Register
CS1U
0x00220008
Chip Select 1 Lower Control Register
CS1L
0x0022000C
Chip Select 2 Upper Control Register
CS2U
0x00220010
Chip Select 2 Lower Control Register
CS2L
0x00220014
Chip Select 3 Upper Control Register
CS3U
0x00220018
Chip Select 3 Lower Control Register
CS3L
0x0022001C
Chip Select 4 Upper Control Register
CS4U
0x00220020
Chip Select 4 Lower Control Register
CS4L
0x00220024
Chip Select 5 Upper Control Register
CS5U
0x00220028
Chip Select 5 Lower Control Register
CS5L
0x0022002C
EIM Configuration Register
EIM
0x00220030
MC9328MXS Reference Manual, Rev. 1.1
11-10
Freescale Semiconductor
Programming Model
11.6.1 Chip Select 0 Control Registers
The layout of the Chip Select 0 control registers are slightly different from the other Chip Select control registers
because CS [0] does not support the programmable output function.
The 64 bits of control are divided into two registers, Chip Select 0 Upper Control Register and Chip Select 0 Lower
Control Register.
•
Bits [63:32] are located in Chip Select 0 Upper Control Register.
•
Bits [31:0] are located in Chip Select 0 Lower Control Register.
11.6.1.1 Chip Select 0 Upper Control Register
BIT
63
62
61
60
59
58
BCD
TYPE
Addr
0x00220000
Chip Select 0 Upper Control Register1
CS0U
57
56
55
BCS
54
PSZ
53
52
PME
SYNC
51
50
49
48
DOL
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
38
37
36
35
34
33
32
RESET
0x0000
BIT
47
46
45
44
43
CNC
TYPE
42
41
40
39
WSC
WWS
EDC
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
rw
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
RESET
0x3E00
1For
bit descriptions, see Table 11-5 on page 11-13.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
11-11
Programming Model
11.6.1.2 Chip Select 0 Lower Control Register
BIT
31
30
29
28
27
26
OEA
TYPE
Addr
0x00220004
Chip Select 0 Lower Control Register1
CS0L
25
24
23
22
OEN
21
20
19
18
WEA
17
16
WEN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
CSA
TYPE
11
10
EBC
9
8
7
DSZ
SP
WP
CSEN
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
r
rw
r
r
r
rw
0
0
0
0
1
*
*
*
0
0
0
0
0
0
0
1
RESET
0x0801
1For
bit descriptions, see Table 11-5 on page 11-13.
*Configurable on reset.
11.6.2 Chip Select 1–Chip Select 5 Control Registers
The layout of the control registers for Chip Selects 1 through 5 are identical.
The 64 bits of control per chip select are divided into an Upper and a Lower register.
•
Bits [63:32] are located in Chip Select x Upper Control Register.
•
Bits [31:0] are located in Chip Select x Lower Control Register.
11.6.2.1 Chip Select 1–Chip Select 5 Upper Control Registers
For bit descriptions for all of these registers, see Table 11-5 on page 11-13.
MC9328MXS Reference Manual, Rev. 1.1
11-12
Freescale Semiconductor
Programming Model
11.6.2.2 Chip Select 1–Chip Select 5 Lower Control Registers
For bit descriptions for Chip Select 1–Chip Select 5 registers, see Table 11-5.
CS1L
CS2L
CS3L
CS4L
CS5L
BIT
Chip Select 1 Lower Control Register
Chip Select 2 Lower Control Register
Chip Select 3 Lower Control Register
Chip Select 4 Lower Control Register
Chip Select 5 Lower Control Register
31
30
29
28
27
26
OEA
TYPE
Addr
0x0022000C
0x00220014
0x0022001C
0x00220024
0x0022002C
25
24
23
22
OEN
21
20
19
18
WEA
17
16
WEN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
PA
CSEN
RESET
0x0000
BIT
15
14
13
12
CSA
TYPE
11
10
EBC
9
8
DSZ
SP
WP
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
r
rw
r
r
rw
rw
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
RESET
0x0802
Table 11-5. Chip Select Control Registers Description
Name
Description
Settings
DTACK_SEL
Bit 63
DTACK Select—This bit is used to select the
functionality of the DTACK input signal for CS5 to
support either a generic DTACK signal or the Compact
Flash/PCMCIA wait function. To select the DTACK
functionality on CS5, the WSC bits for CS5 must be set to
111111.
0 = Generic DTACK function
1 = Compact Flash/PCMCIA wait function
BCD
Bits 61–60
Burst Clock Divisor—Contains the value used to program
the burst clock divisor. See Section 11.5.4, “Burst Clock
Divisor,” for more information on the burst clock divisors.
When the BCM bit is set (BCM = 1) in the EIM configuration
register, BCD is ignored.
00 = Divisor is 1
01 = Divisor is 2
10 = Divisor is 3
11 = Divisor is 4
BCD is cleared by a hardware reset.
BCS
Bits 59–56
Burst Clock Start—Determines the number of half cycles
after LBA assertion before the first rising edge of BCLK
(burst clock) is seen. A value of 0 results in a half clock
delay, not an immediate assertion. When the BCM bit is set
(BCM = 1) in the EIM configuration register, this overrides
the BCS bits. BCS is cleared by a hardware reset.
0000 = 1 half cycle before BCLK (burst clock)
0001 = 2 half cycles before BCLK (burst
clock)
...
1111 = 16 half cycles before BCLK (burst
clock)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
11-13
Programming Model
Table 11-5. Chip Select Control Registers Description (continued)
Name
PSZ
Bits 55–54
Description
Page Size—Indicates the number of words (where “word” is
defined by the port size or DSZ bits) in a page in memory.
This ensures that the EIM does not burst past a page
boundary when the PME bit is set.
Settings
00 = 4 words in a page
01 = 8 words in a page
10 = 16 words in a page
11 = 32 words in a page
PSZ is cleared by a hardware reset.
PME
Bit 53
Page Mode Emulation—Enables/Disables page mode
emulation in burst mode. When PME is set, the external
address asserts for each piece of data requested.
Additionally, the LBA and BCLK signals behave as they do
when an asynchronous access is performed.
0 = Disables page mode emulation
1 = Enables page mode emulation
PME is cleared by a hardware reset.
SYNC
Bit 52
Synchronous Burst Mode Enable—Enables/Disables
synchronous burst mode. When enabled, the EIM is capable
of interfacing to burst flash devices through additional burst
control signals: BCLK (burst clock), LBA, and ECB. The
sequencing of these additional I/Os is controlled by other
EIM configuration register bit settings as defined below.
0 = Disables synchronous burst mode
1 = Enables synchronous burst mode
SYNC is cleared by a hardware reset.
DOL
Bits 51–48
Data Output Length—Specifies the expected number of
system clock cycles required for burst read data to be valid
on the data bus before it is latched by the EIM. The reset
value specifies that burst data is held for a single system
clock period. As system clock frequencies increase, it may
become necessary to delay sampling the data for multiple
system clock periods to meet burst flash max frequency
specifications and/or EIM data setup time requirements. DOL
has no effect on EIM data latching when SYNC = 0.
0000 = 1system clock delays
0001 = 1system clock delays
0010 = 2system clock delays
0011 = 3system clock delays
...
1111 = 15 system clock delays
DOL is cleared by a hardware reset.
CNC
Bits 47–46
Chip Select Negation Clock Cycles—Specifies the
minimum number of clock cycles a chip select must remain
negated after it is negated.
00 = Minimum negation is 0 clock cycles
01 = Minimum negation is 1 clock cycle
10 = Minimum negation is 2 clock cycles
11 = Minimum negation is 3 clock cycles
CNC has no effect on write accesses when any CSA bit is
set.
CNC is cleared by a hardware reset.
MC9328MXS Reference Manual, Rev. 1.1
11-14
Freescale Semiconductor
Programming Model
Table 11-5. Chip Select Control Registers Description (continued)
Name
WSC
Bits 45–40
Description
Settings
Wait State Control—
For SYNC = 0:
WSC programs the number of wait-states for an access to
the external device connected to the chip select. Table 11-6,
"Chip Select Wait State and Burst Delay Encoding" shows
the encoding of this field. When WWS is cleared, setting:
• WSC = 000000 results in 2 clock transfers
• WSC = 000001 results in 2 clock transfers
• WSC = 001110 results in 15 clock transfers
• WSC = 111110 results in 63 clock transfers
• WSC=111111 selects DTACK input functionality for
CS5
See Table 11-6, "Chip Select Wait State and
Burst Delay Encoding"
For SYNC = 1:
WSC programs the number of system clock cycles required
for the initial access of a burst sequence initiated by the EIM
to an external burst device. See Table 11-6, "Chip Select
Wait State and Burst Delay Encoding" and to the EIM
synchronous burst read timing diagrams for further details.
to, the WSC
WSC is set to 111110 by a hardware reset for CS0.
WSC is cleared by a hardware reset for CS1–CS5.
Reserved
Bit 39
Reserved—This bit is reserved and should read 0.
WWS
Bits 38–36
Write Wait State—Determines whether additional
wait-states are required for write cycles. This is useful for
writing to memories that require additional data setup time.
See Table 11-6, "Chip Select Wait State and
Burst Delay Encoding"
WWS is cleared by a hardware reset.
EDC
Bits 35–32
Extra Dead Cycles—Determines whether idle cycles are
inserted after a read cycle for back-to-back external transfers
to eliminate data bus contention. This is useful for slow
memory and peripherals that use long CS or OE to output
data three-state times. Idle cycles are not inserted for
back-to-back external reads from the same chip select.
0000 = 0 Idle cycles inserted
0001 = 1 Idle cycle inserted
...
1111 = 15 Idle cycles inserted
EDC is cleared by a hardware reset.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
11-15
Programming Model
Table 11-5. Chip Select Control Registers Description (continued)
Name
OEA
Bits 31–28
Description
OE Assert—Determines when OE is asserted during read
cycles.
For SYNC = 0:
OEA determines the number of half clocks before OE asserts
during a read cycle.
Settings
0000 = 0 half clocks before assertion
0001 = 1 half clock before assertion
...
1111 = 15 half clocks before assertion
For SYNC = 1:
After the initial burst access, OE is asserted continuously for
subsequent burst accesses, and is not affected by OEA (see
burst read timing diagrams for more detail). The behavior of
OE on the initial burst access is the same as when SYNC =
0.
When the EBC bit in the corresponding register is clear, the
EB [3:0] outputs are similarly affected.
The OEA bits do not affect the cycle length.
OEA is cleared by a hardware reset.
OEN
Bits 27–24
OE Negate—Determines when OE is negated during a read
cycle. Setting the SYNC bit (SYNC = 1) overrides OEN and
OE negates at the end of a read access and no sooner.
When EBC in the corresponding register is clear, the EB
[3:0] outputs are similarly affected.
0000 = 0 half clocks before end of access
0001 = 1 half clock before end of access
...
1111 = 15 half clocks before end of access
OEN does not affect the cycle length.
OEN is cleared by a hardware reset.
WEA
Bits 23–20
EB [3:0] Assert—Determines when EB [3:0] is asserted
during write cycles. This is useful to meet data setup time
requirements for slow memories.
0000 = 0 half clocks before assertion
0001 = 1 half clock before assertion
...
1111 = 15 half clocks before assertion
WEA does not affect the cycle length.
WEA is cleared by a hardware reset.
WEN
Bits 19–16
EB [3:0] Negate During Write—Determines when EB [3:0]
outputs are negated during a write cycle. This is useful to
meet data hold time requirements for slow memories.
0000 = 0 half clocks before end of access
0001 = 1 half clock before end of access
...
1111 = 15 half clocks before end of access
WEN does not affect the cycle length.
WEN is cleared by a hardware reset.
MC9328MXS Reference Manual, Rev. 1.1
11-16
Freescale Semiconductor
Programming Model
Table 11-5. Chip Select Control Registers Description (continued)
Name
CSA
Bits 15–12
Description
Chip Select Assert—Determines when chip select is
asserted and negated for devices that require additional
address setup time and additional address/data hold times.
CSA affects only external writes, and is ignored on external
reads.
CSA does not affect the cycle length.
Settings
0000 = 0 clocks before assertion and 0
clocks following negation
0001 = 1 clock before assertion and 1 clock
following negation
...
1111 = 15 clocks before assertion and 15
clocks after negation
CSA is cleared by a hardware reset.
EBC
Bit 11
Enable Byte Control—Indicates the access types that
assert the enable byte outputs (EB [3:0]).
EBC is set by a hardware reset.
DSZ
Bits 10–8
Data Port Size—Defines the width of the external device’s
data port as shown in the table, DSZ Bit Encoding, to the
right. At hardware reset, the value of DSZ is 000 for
CS1– CS5. For CS0, DSZ is mapped based on the value of
the EIM_BOOT_DSZ [2:0] bits. EIM_BOOT_DSZ [2] maps to
DSZ [2], EIM_BOOT_DSZ [1] maps to DSZ [1] and
EIM_BOOT_DSZ [0] maps to DSZ [0].
Reserved
Bit 7
Reserved—This bit is reserved and should read 0.
SP
Bit 6
Supervisor Protect—Prevents accesses to the address
range defined by the corresponding chip select when the
access is attempted in the User mode of ARM9 core
operation.
SPI is cleared by a hardware reset.
Reserved
Bit 5
Reserved—This bit is reserved and should read 0.
WP
Bit 4
Write Protect—Prevents writes to the address range
defined by the corresponding chip select.
WP is cleared by a hardware reset.
Reserved
Bits 3–2
0 = Both read and write accesses assert the
EB [3:0] outputs, thus configuring the
access as byte enables
1 = Only write accesses assert the EB [3:0]
outputs, thus configuring the access as
byte write enables; the EB [3:0] outputs
are configured as byte write enables for
accesses to dual x16 or quad x8
memories
000 = 8-bit port, resides on D [31:24] pins
001 = 8-bit port, resides on D [23:16] pins
010 = 8-bit port, resides on D [15:8] pins
011 = 8-bit port, resides on D [7:0] pins
100 = 16-bit port, resides on D [31:16] pins
101 = 16-bit port, resides on D [15:0] pins
11x = 32-bit port
0 = User mode accesses are allowed in the
range of chip select
1 = User mode accesses are prohibited;
attempts to access an address mapped
by this chip select in User mode results
in a TEA to the ARM9 core and no
assertion of the chip select output
0 = Writes are allowed in the range of chip
select
1 = Writes are prohibited; attempts to write to
an address mapped by this chip select
result in a TEA to the ARM9 core and no
assertion of the chip select output
Reserved—These bits are reserved and should read 0.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
11-17
Programming Model
Table 11-5. Chip Select Control Registers Description (continued)
Name
PA
Bit 1
Description
Settings
Pin Assert—Controls the chip select pin when it is operating
as a programmable output pin (when the CSEN bit is clear).
0 = Brings the chip select output to logic-low
1 = Brings the chip select output to logic-high
PA is not available (reserved) for CS0.
PA is set by a hardware reset for CS1–CS5.
CSEN
Bit 0
Chip Select Enable—Controls the operation of the chip
select pin.
Except for CS0, CSEN is cleared by reset, disabling the chip
select output pin. When enabled, the PA control bit is
ignored. CSEN in the CS0 control register is set at reset to
allow CS0 to select from an external boot ROM.
CSEN is set by a hardware reset for CS0.
CSEN is cleared by a hardware reset for CS1–CS5.
0 = Chip select function is disabled; attempts
to access an address mapped by this
chip select results in an error and no
assertion of the chip select output
When disabled, the pin is a general
purpose output controlled by the value
of PA control bit. When CSEN in the
CS0 control register is clear, CS0 is
inactive.
1 = Chip select is enabled, and is asserted
when presented with a valid AHB
access.
MC9328MXS Reference Manual, Rev. 1.1
11-18
Freescale Semiconductor
Programming Model
11.6.3 EIM Configuration Register
Table 11-6. Chip Select Wait State and Burst Delay Encoding
Number of Wait-States
WSC [5:0]
WWS = 0
WWS = 1
WWS = 7
Read Access
Write Access
Read Access
Write Access
Read Access
Write Access
000000
1
1
1
1
1
7
000001
1
1
1
2
1
8
000010
2
2
2
3
2
9
000011
3
3
3
4
3
10
000100
4
4
4
5
4
11
000101
5
5
5
6
5
12
000110
6
6
6
7
6
13
000111
7
7
7
8
7
14
001000
8
8
8
9
8
15
001001
9
9
9
10
9
16
001010
10
10
10
11
10
17
001011
11
11
11
12
11
18
001100
12
12
12
13
12
19
001101
13
13
13
14
13
20
001110
14
14
14
15
14
21
001111
15
15
15
16
15
22
010000
16
16
16
17
16
23
010001
17
17
17
18
17
24
010010
18
18
18
19
18
25
010011
19
19
19
20
19
26
010100
20
20
20
21
20
27
010101
21
21
21
22
21
28
010110
22
22
22
23
22
29
010111
23
23
23
24
23
30
011000
24
24
24
25
24
31
011001
25
25
25
26
25
32
011010
26
26
26
27
26
33
011011
27
27
27
28
27
34
011100
28
28
28
29
28
35
011101
29
29
29
30
29
36
011110
30
30
30
31
30
37
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
11-19
Programming Model
Table 11-6. Chip Select Wait State and Burst Delay Encoding (continued)
Number of Wait-States
WSC [5:0]
WWS = 0
WWS = 1
WWS = 7
Read Access
Write Access
Read Access
Write Access
Read Access
Write Access
011111
31
31
31
32
31
38
100000
32
32
32
33
32
39
100001
33
33
33
34
33
40
100010
34
34
34
35
34
41
100011
35
35
35
36
35
42
100100
36
36
36
37
36
43
100101
37
37
37
38
37
44
100110
38
38
38
39
38
45
100111
39
39
39
40
39
46
101000
40
40
40
41
40
47
101001
41
41
41
42
41
48
101010
42
42
42
43
42
49
101011
43
43
43
44
43
50
101100
44
44
44
45
44
51
101101
45
45
45
46
45
52
101110
46
46
46
47
46
53
101111
47
47
47
48
47
54
110000
48
48
48
49
48
55
110001
49
49
49
50
49
56
110010
50
50
50
51
50
57
110011
51
51
51
52
51
58
110100
52
52
52
53
52
59
110101
53
53
53
54
53
60
110110
54
54
54
55
54
61
110111
55
55
55
56
55
62
111000
56
56
56
57
56
63
111001
57
57
57
58
57
63
111010
58
58
58
59
58
63
111011
59
59
59
60
59
63
111100
60
60
60
61
60
63
111101
61
61
61
62
61
63
111110
62
62
62
63
62
63
MC9328MXS Reference Manual, Rev. 1.1
11-20
Freescale Semiconductor
Programming Model
Table 11-6. Chip Select Wait State and Burst Delay Encoding (continued)
Number of Wait-States
WSC [5:0]
WWS = 0
WWS = 1
WWS = 7
Read Access
Write Access
Read Access
Write Access
Read Access
Write Access
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
111111
The EIM Configuration Register contains the bit that controls the operation of the burst clock.
EIM
Addr
0x00220030
EIM Configuration Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
BCM
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 11-7. EIM Configuration Register Description
Name
Description
Settings
Reserved
Bits 31–3
Reserved—These bits are reserved and should read 0.
BCM
Bit 2
Burst Clock Mode—Selects the burst clock
mode of operation.
BCM is cleared by a hardware reset.
Reserved
Bits 1–0
0 = The burst clock runs only when accessing a chip select
range with the SYNC bit set. When the burst clock is not
running, it remains in a logic 0 state; when the burst clock
is running, it is configured by the BCD and BCS bits in the
chip select control register.
1 = The burst clock runs all the time (independent of chip
select accesses).
Reserved—These bits are reserved and should read 0.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
11-21
Programming Model
MC9328MXS Reference Manual, Rev. 1.1
11-22
Freescale Semiconductor
Chapter 12
Phase-Locked Loop and Clock Controller
12.1 Introduction
To produce the wide range of on-chip clock frequencies required by the MC9328MXS, the core clock generator
uses a two-stage phase locked loop (PLL). The first stage is a premultiplier PLL. If the input crystal frequency is
32.768 kHz, the premultiplier multiplies it by a factor of 512 to 16.78 MHz. If the input crystal frequency is 32
kHz, the premultiplier multiplies it to 16.384 MHz. The second stage is a digital PLL (DPLL) that produces an
output frequency determined by system requirements and used throughout the entire system. The two DPLLs
(MCU PLL and System PLL) use digital and mixed analog/digital chips to provide clock generation for wireless
communication and other applications. Power management of the MC9328MXS is accomplished by controlling
the operation of the premultiplier, MCU PLL and System PLL units, as shown in Figure 12-1 on page 12-2.
12.2 Clock Sources
The distribution of clocks in the MC9328MXS is shown in Figure 12-1 on page 12-2. Clock signal name
definitions are provided in Table 12-1 on page 12-2.
The 32kHz clock source can be configured in two ways. The user can place a 32 kHz or 32.768 kHz crystal across
EXTAL32K and XTAL32K with appropriate load capacitors. Alternately, an external 32 kHz or 32.768 kHz
oscillator can be used; the signal is AC coupled into EXTAL32K and XTAL32K is floated.
The 16 MHz external crystal oscillator is not recommended for use and must be disabled using the CSCR register.
Note that the 32 kHz oscillator must be used and satisfies all system requirements.
12.2.1 Low Frequency Clock Source
The MC9328MXS can use either a 32 kHz or a 32.768 kHz crystal as the external low frequency source.
Throughout this chapter, the low frequency crystal is referred to as the 32 kHz crystal. The signal from the external
32 kHz crystal is the source of the CLK32 signal that is sent to the real time clock (RTC). The output of the 32 kHz
crystal is also input to the premultiplier PLL to produce the 16.78 MHz signal that is input to the MCU PLL (it is
16.78 MHz if a 32.768 kHz crystal is used). The output of the MCU PLL is sent to the prescaler (PRESC) module
to produce the fast clock (FCLK) signal for the ARMTDMI core.
The 16.384 MHz output of the premultiplier PLL also can be a source for the System PLL by setting the
System_SEL bit in the Clock Source Control Register to produce all of the system clocks from a single 32 kHz
crystal oscillator. See Section 12.3.1, “DPLL Phase and Frequency Jitter,” for more detailed information on phase
and frequency jitter specifications using this configuration.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
12-1
Clock Sources
12.2.2 High Frequency Clock Source
The System PLL produces the USBPLLCLK signal that is the source for the following clock signals:
•
CLK48M—for the USB
•
HCLK and BCLK—HCLK is the MC9328MXS system clock and BCLK goes to the ARMTDMI core.
•
Peripheral Clocks 1, 2, and 3—The peripheral clocks (PERCLK) provide clock signals to both integrated
and external peripherals.
OSC32
OSC_EN
OSC16
0
CLK16M
CLK32
SYNC Logic
RTC
HCLK
1
System
PLL
1
System PLLCLK
USBDIV
CLK48M
USB
0
CLK16_SEL
System_SEL
FCLK
PRESC
BCLK
MCU PLL
BCLKDIV
PREMULT
HCLK
System
PERCLK1
PCLKDIV1
PERCLK2
PCLKDIV2
OSC32
XTALOSC
CPU
CLK32
Internal
Peripherals
PERCLK3
PCLKDIV3
000
SPLLEN
PLL Stop &
Wake-Up Logic
HCLK
CLK48M
CLK16M
PREMCLK
FCLK
MPLLEN
Note: PREMCLK is the signal name after
the System_SEL controlled MUX output.
PREMCLK i th
i
lt
CLKO
CLKO
CLK0SEL [2:0]
ft
th S t
SEL
t ll d MUX
t
t
Figure 12-1. Clock Controller Module
S
Table 12-1. Clock Controller Module Signal Descriptions
Signal Names
I/O
Description
Default
CLK48M
O
Continuous 48 MHz clock output when System PLL is enabled or when external
48 MHz clock is selected.
Run
FCLK
O
Fast clock (FCLK) output to the CPU.
Run
HCLK
O
System clock (HCLK) output to the CPU (as BCLK) and to the system. This is a
continuous clock (when the system is not in sleep mode) normally used for bus
non-stop system logic (such as bus arbiter or interrupt controller) when the system is
running.
Run
CLKO
O
Output internal clock to the CLKO pin.
Run
MC9328MXS Reference Manual, Rev. 1.1
12-2
Freescale Semiconductor
DPLL Output Frequency Calculation
Table 12-1. Clock Controller Module Signal Descriptions (continued)
Signal Names
PERCLK1, 2, 3
I/O
O
Description
Default
Output clocks used by the peripheral modules.
Run
12.3 DPLL Output Frequency Calculation
The DPLL (both the MCU PLL and System PLL) produce a high frequency clock that exhibits both a low
frequency jitter and a low phase jitter. The DPLL output clock frequency (fdpll) is determined by the
Equation 12-1:
fdpll = 2fref • MFI + MFN / (MFD+1)
PD + 1
Eqn. 12-1
where:
•
fref is the reference frequency
•
MFI is an integer part of a multiplication factor (MF)
•
MFN is the numerator and MFD is the denominator of the MF
•
PD is the predivider factor
12.3.1 DPLL Phase and Frequency Jitter
Spectral purity of the DPLL output clock is characterized by both phase and frequency jitter. Phase jitter is a
measure of clock phase fluctuations relative to an ideal clock phase. The output clock also can be skewed relative
to the reference clock. Frequency jitter is a measure of clock period fluctuations relative to an ideal clock period.
Frequency jitter is calculated as a difference of phase jitter values for adjacent clocks.
DPLL jitter requirements vary according to system configuration. For many stand-alone processors and
asynchronous multiprocessor applications, only the frequency jitter value is important (slow phase jitter and clock
skew do not affect system performance). In these systems, it is not necessary to adjust the output clock phase with
an input clock phase. The clock generation mode in which slow phase fluctuations are permissible is called
Frequency Only Lock (FOL) mode.
Phase error is sometimes important for synchronous applications and sampling analog-to-digital (A/D) and
digital-to-analog (D/A) precision converters. The DPLL mode providing minimum phase jitter and skew
elimination is Frequency and Phase Lock (FPL) mode. The DPLL mode is user selectable.
The DPLL communicates with the clock module. This block contains a control register and provides an interface
between the DPLL and the ARMTDMI core.
12.4 MC9328MXS Power Management
The operation of the PLL and clock controller at different stages of power management is described in the
following sections.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
12-3
MC9328MXS Power Management
12.4.1 PLL Operation at Power-Up
The crystal oscillator begins oscillating within several hundred milliseconds of initial power-up. While reset
remains asserted, the PLL begins the lockup sequence and locks 1 ms after the crystal oscillator becomes stable.
After lockup occurs, the system clock is available at the default System PLL output frequency of 96 MHz (when a
32 kHz crystal is used).
12.4.2 PLL Operation at Wake-Up
When the device is awakened from stop mode by a wake-up event, the DPLL locks within 300 μs. The crystal
oscillator is always on after initial power-up, so crystal startup time is not a factor. The PLL output clock starts
operating as soon as it achieves lock.
12.4.3 ARM920T Processor Low-Power Modes
The MC9328MXS provides two power saving modes, doze and stop:
•
In stop mode, the MCU PLL and the System PLL are shut down and only the 32 kHz clock is running.
•
In doze mode, the CPU executes a wait for interrupt instruction.
These modes are controlled by the clock control logic and a sequence of CPU instructions. Most of the peripheral
modules can enable or disable the incoming clock signal (PERCLK 1, 2, or 3) through clock gating circuitry from
the peripheral bus.
12.4.4 SDRAM Power Modes
When the SDRAM controller (SDRAMC) is enabled, the external SDRAM operates in distributed-refresh mode or
in self-refresh mode (as shown in Table 12-2). The SDRAM wake-up latency is approximately 20 system clock
cycles (HCLK). The SDRAMC can wake up from self-refresh mode when it is in a SDRAM cycle. In doze mode,
the SDRAM enters self-refresh mode. When a bus cycle accesses the SDRAM or SyncFlash, the controller wakes
up and completes the bus cycle, then returns to self-refresh mode.
Table 12-2. SDRAM/SyncFlash Operation During Power Modes
SDRAM
Run
Doze
Stop
SDRAM
Distributed-refresh
Self-refresh
Self-refresh
SyncFlash
Run
Low-power mode
Deep power-down mode
12.4.5 Power Management in the Clock Controller
Power management in the MC9328MXS is achieved by controlling the duty cycles of the clock system efficiently.
The clocking control scheme is shown in Table 12-3.
MC9328MXS Reference Manual, Rev. 1.1
12-4
Freescale Semiconductor
Programming Model
Table 12-3. Power Management in the Clock Controller
Device/Signal
System PLL
Shut-Down Conditions
Wake-Up Conditions
When 0 is written to the SPEN bit and the PLL shut-down count
times out (for details see the SD_CNT settings in Table 12-5 on
page 12-6).
When IRQ or FIQ is asserted.
When 0 is written to the MPEN bit.
When IRQ or FIQ is asserted, or 1 is
written to the MPEN bit.
Premultiplier
Same as System PLL.
Same as System PLL.
CLK32
Continuously running.
Continuously running.
MCU PLL
12.5 Programming Model
The PLL and Clock Controller module includes six user-accessible 32-bit registers. Table 12-4 summarizes these
registers and their addresses.
Table 12-4. PLL and Clock Controller Module Register Memory Map
Description
Name
Address
Clock Source Control Register
CSCR
0x0021B000
Peripheral Clock Divider Register
PCDR
0x0021B020
MCU PLL Control Register 0
MPCTL0
0x0021B004
MCU PLL and System Clock Control Register 1
MPCTL1
0x0021B008
System PLL Control Register 0
SPCTL0
0x0021B00C
System PLL Control Register 1
SPCTL1
0x0021B010
12.5.1 Clock Source Control Register
This register controls the various clock sources to the internal modules of the MC9328MXS. It allows the bypass of
the 32 kHz derived clock source to the System PLL when the design requires clock signals with greater frequency
and phase jitter performance than the internal PLL using the 32 kHz clock source provides.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
12-5
Programming Model
CSCR
Addr
0x0021B000
Clock Source Control Register
BIT
31
30
29
28
CLKO_SEL
TYPE
27
26
USB_DIV
25
24
23
SD_CNT
22
21
SPLL_
RESTART
MPLL_
RESTART
20
19
18
17
16
CLK16
_SEL
OSC
_EN
System
_SEL
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
r
r
rw
rw
rw
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
SPEN
MPEN
RESET
0x0F00
BIT
15
14
13
PRESC
TYPE
12
11
10
9
8
7
BCLK_DIV
rw
r
rw
rw
rw
rw
r
r
r
r
r
r
r
r
rw
rw
1
0
1
0
1
1
0
0
0
0
0
0
0
0
1
1
RESET
0xAC03
Table 12-5. Clock Source Control Register Description
Name
Description
Settings
CLKO_SEL
Bits 31–29
CLKO Select—Selects the clock signal source that is
output on the CLKO pin.
000 = PERCLK1
001 = HCLK
010 = CLK48M
011 = CLK16M
100 = PREMCLK
101 = FCLK
USB_DIV
Bits 28–26
USB Divider—Contains the integer divider value used to
generate the CLK48M signal for the USB modules.
000 = System PLL clock divide by 1
001 = System PLL clock divide by 2
.
.
.
111 = System PLL clock divide by 8
SD_CNT
Bits 25–24
Shut-Down Control—Contains the value that sets the
duration of System PLL clock output after 0 is written to
the SPEN bit. The power controller requests the bus
before System PLL shutdown. Any unmasked interrupt
event enables the System PLL.
00 = System PLL shuts down after next
rising edge of CLK32 is detected and the
current bus cycle is completed. A
minimum of 16 HCLK cycles is
guaranteed from writing
¡°0¡± to SPEN
bit.
01 = System PLL shuts down after the second
rising edge of CLK32 is detected.
10 = System PLL shuts down after the third
rising edge of CLK32 is detected.
11 = System PLL shuts down after forth rising
edge of CLK32 is detected.
Reserved
Bit 23
Reserved—This bit is reserved and should read 0.
MC9328MXS Reference Manual, Rev. 1.1
12-6
Freescale Semiconductor
Programming Model
Table 12-5. Clock Source Control Register Description (continued)
Name
Description
Settings
SPLL_
RESTART
Bit 22
SPLL Restart—Restarts System PLL at new assigned
frequency. SPLL_RESTART self-clears after 1 (min) or 2
(max) cycles of CLK32.
0 = No Effect
1 = Restarts System PLL at new frequency
MPLL_
RESTART
Bit 21
MPLL Restart—Restarts the MCU PLL at a new assigned
frequency. MPLL_RESTART self-clears after 1 (min) or 2
(max) cycles of CLK32.
0 = No Effect
1 = Restarts MCU PLL at new frequency
Reserved
Bits 20–19
Reserved—These bits are reserved and should read 0.
OSC_EN
Bit 17
Oscillator Enable—Enables the 16 MHz oscillator circuit
when set (available when using an external crystal input).
When clear, the oscillator circuit control is disabled which
bypasses the oscillator circuit when using external clock
input. This oscillator is not recommended for use.
0 = Disable the external 16 MHz oscillator
circuit (Recommended)
1 = Enable the external 16 MHz oscillator circuit
System_SEL
Bit 16
System Select—Selects the clock source of the System
PLL input. When set, the external high frequency clock
input is selected.
0 = Clock source is the internal premultiplier
1 = Clock source is the external high frequency
clock
PRESC
Bit 15
Prescaler—Defines the MPU PLL clock prescaler.
0 = Prescaler divides by 1
1 = Prescaler divides by 2
Reserved
Bit 14
Reserved—This bit is reserved and should read 0.
BCLK_DIV
Bits 13–10
BClock Divider—Contains the 4-bit integer divider values
for the generation of the BCLK and HCLK.
Reserved
Bits 9–2
Reserved—These bits are reserved and should read 0.
SPEN
Bit 1
System PLL Enable—Enables/Disables the System PLL.
When software writes 0 to SPEN, the System PLL shuts
down after SDCNT times out. SPEN sets automatically
when SPLLEN asserts, and on system reset.
0 = System PLL disabled
1 = System PLL enabled
MPEN
Bit 0
MCU PLL Enable—Enables/Disables the MCU PLL.
When cleared, the MCU PLL is disabled. When software
writes 0 to MPEN, the PLL shuts down immediately.
MPEN sets automatically when MPLLEN asserts, and on
system reset.
0 = MCU PLL disabled
1 = MCU PLL enabled
0000 = System PLLCLK divided by 1
0001 = System PLLCLK divided by 2
...
1111 = System PLLCLK divided by 16
12.5.2 Peripheral Clock Divider Register
Each peripheral module in the MC9328MXS uses clock signals from one of the three clock sources shown in
Table 12-6. The three peripheral clock dividers (PCLKDIV1, PCLKDIV2, PCLKDIV3) provide flexible clock
configuration capability so that a minimum set of clock frequencies can satisfy a large group of modules to achieve
better power efficiency.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
12-7
Programming Model
Table 12-6. Clock Sources for Peripherals
Clock Source
PERCLK1
UART1, UART2, Timer1, Timer2, PWM
PERCLK2
LCD, SPI 1
PERCLK3
SSI
HCLK
SDRAM, I2C, DMA
PCDR
BIT
Peripheral
Addr
0x0021B020
Peripheral Clock Divider Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PCLK_DIV3
TYPE
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
7
6
5
4
3
2
1
0
RESET
0x000B
BIT
15
14
13
12
11
10
9
8
PCLK_DIV2
TYPE
PCLK_DIV1
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
1
0
1
1
1
0
1
1
RESET
0x00BB
Table 12-7. Peripheral Clock Divider Register Description
Name
Description
Settings
Reserved
Bits 31–23
Reserved—These bits are reserved and should read 0.
PCLK_DIV3
Bits 22–16
Peripheral Clock Divider 3—Contains the 7-bit integer divider that produces
the PERCLK3 clock signal for the peripherals. The input to the PCLK_DIV3
divider circuit is System PLLCLK.
Reserved
Bits 15–8
Reserved—These bits are reserved and should read 0.
PCLK_DIV2
Bits 7–4
Peripheral Clock Divider 2—Contains the 4-bit integer divider that produces
the PERCLK2 clock signal for the peripherals. The input to the PCLK_DIV2
divider circuit is System PLLCLK.
0000 = Divide by 1
0001 = Divide by 2
…
1111 = Divide by 16
PCLK_DIV1
Bits 3–0
Peripheral Clock Divider 1—Contains the 4-bit integer divider that produces
the PERCLK1 clock signal for the peripherals. The input to the PCLK_DIV1
divider circuit is System PLLCLK.
0000 = Divide by 1
0001 = Divide by 2
…
1111 = Divide by 16
0000000 = Divide by 1
0000001 = Divide by 2
…
1111111 = Divide by 128
MC9328MXS Reference Manual, Rev. 1.1
12-8
Freescale Semiconductor
Programming Model
12.5.3 Programming Digital Phase Locked Loops
There are two DPLLs in the MC9328MXS—the MCU PLL and the System PLL. The MCU PLL primarily
generates FCLK to the CPU, and the System PLL derives all system clocks to the entire MC9328MXS and
generates clocks that produce the programmable frequency range required by modules such as the USB, UARTs,
and SSI.
The MCU PLL derives the ARM920T processor’s CPU clock FCLK, and the System PLL derives the ARM920T
processor’s CPU clock BCLK, as well as the system clocks PERCLK 1, 2, and 3, and HCLK. The MCU PLL
frequency is determined by the speed requirement of the ARM920T processor. The recommended settings for both
MCU PLL and System PLL, which produces the least amount of signal jitter, are shown in Table 12-8.
Table 12-8. Sample Frequency Table
Premultiplier Input
Crystal Frequency
PLL Input Frequency
(Premultiplier Output)
PD
MFD
MFI
MFN
PLL Output
Frequency
32 kHz
16.384 MHz
0
63
5
55
192 MHz
12.5.3.1 MCU PLL Control Register 0
The MCU PLL Control Register 0 (MPCTL0) is a 32-bit register that controls the operation of the MCU PLL. The
MPCTL0 control bits are described in the following sections. A delay of 56 FCLK cycles (about 10–30 FCLK
cycles for MCU PLL controller plus 2–26 FCLK cycles are necessary to get EDRAM_IDLE and SDRAM_IDLE
signals) is required between two write accesses to MPCTL0 register. The following is a procedure for changing the
MCU PLL settings:
1. Program the desired values of PD, MFD, MFI, and MFN into the MPCTL0.
2. Set the MPLL_RESTART bit in the CSCR (it will self-clear).
3. New PLL settings will take place.
MPCTL0
BIT
Addr
0x0021B004
MCU PLL Control Register 0
31
30
29
28
27
26
25
24
23
22
21
PD
TYPE
20
19
18
17
16
MFD
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
7
6
5
4
3
2
1
0
RESET
0x003F
BIT
15
14
13
12
11
10
9
8
MFI
TYPE
MFN
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
1
0
1
0
0
0
0
1
1
0
1
1
1
RESET
0x1437
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
12-9
Programming Model
Table 12-9. MCU PLL Control Register 0 Description
Name
Description
Settings
Reserved
Bits 31–30
Reserved—These bits are reserved and should read 0.
PD
Bits 29–26
Predivider Factor—Defines the predivider factor (PD) applied to the PLL input
frequency. PD is an integer between 0 and 15 (inclusive). PD is chosen to ensure
that the resulting output frequency remains within the specified range. When a new
value is written into PD bits, the PLL loses its lock; after a time delay, the PLL
re-locks. The output of the MCU PLL is determined by Equation 12-1.
0000 = 0
0001 = 1
…
1111 = 15
MFD
Bits 25–16
Multiplication Factor (Denominator Part)—Defines the denominator part of the
BRM value for the MF. When a new value is written into the MFD bits, the PLL loses
its lock; after a time delay, the PLL re-locks.
0x000 = Reserved
0x001 = 1
…
0x3FF = 1023
Reserved
Bits 15–14
Reserved—These bits are reserved and should read 0.
MFI
Bits 13–10
Multiplication Factor (Integer)—Defines the integer part of the BRM value for the
MF. The MFI is encoded so that MFI < 5 results in MFI = 5. When a new value is
written into the MFI bits, the PLL loses its lock: after a time delay, the PLL re-locks.
The VCO oscillates at a frequency determined by Equation 12-1. Where PD is the
division factor of the predivider, MFI is the integer part of the total MF, MFN is the
numerator of the fractional part of the MF, and MFD is its denominator part. The MF
is chosen to ensure that the resulting VCO output frequency remains within the
specified range.
0000–0101 = 5
0110 = 6
...
1111 = 15
MFN
Bits 9–0
Multiplication Factor (Numerator)—Defines the numerator of the BRM value for
the MF. When a new value is written into the MFN bits, the PLL loses its lock; after
a time delay, the PLL re-locks.
0x000 = 0
0x001 = 1
...
0x3FE = 1022
0x3FF = Reserved
MC9328MXS Reference Manual, Rev. 1.1
12-10
Freescale Semiconductor
Programming Model
12.5.3.2 MCU PLL and System Clock Control Register 1
The MCU PLL and System Clock Control Register 1 (MPCTL1) is a 32-bit register that directs the operation of the
on-chip MCU PLL. The MPCTL1 control bits are described in Table 12-10.
MPCTL1
Addr
0x0021B008
MCU PLL and System Clock Control Register 1
BIT
31
30 29
TYPE
r
r
0
0
28
27
26
25
24
23
22
21
20
19
18
17
16
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14 13
12
11
10
9
8
7
BRMO
TYPE
r
r
r
r
r
r
r
r
r
rw
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 12-10. MCU PLL and System Clock Control Register 1 Description
Name
Description
Reserved
Bits 31–7
Reserved—These bits are reserved and should read 0.
BRMO
Bit 6
BRM Order—Controls the BRM order. The first order BRM is used if a MF fractional
part is both more than 1/10 and less than 9/10. In other cases, the second order
BRM is used. The BRMO bit is cleared by a hardware reset. A delay of reference
cycles is required between two write accesses to BRMO.
Reserved
Bits 5–0
Reserved—These bits are reserved and should read 0.
Settings
0 = BRM contains
first order
1 = BRM contains
second order
12.5.4 Generation of 48 MHz Clocks
The USB interface clock (CLK48M) is used internally by the USB module. Its frequency is set to 48 MHz using
the PLL control registers assuming a default input clock frequency 16.384 MHz. This input clock frequency
assumes a 32 kHz crystal input.
The predivider/multiplier output depends on the input clock frequency as shown in Table 12-11.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
12-11
Programming Model
Table 12-11. System PLL Multiplier Factor
Premultiplier Input
Crystal Frequency
32 kHz
PLL Input Frequency
(Premultiplier Output)
PD
MFD
MFI
MFN
PLL Output
Frequency
USBDIV
1
63
5
55
96 MHz
2
16.384 MHz
USB Clock
Frequency
48 MHz
The default setting exception is USB_DIV. The user must program this to 001.
12.5.4.1 System PLL Control Register 0
The System PLL Control Register 0 (SPCTL0) is a 32-bit register that controls the operation of the System PLL.
The SPCTL0 control bits are described in the following sections. A delay of 30 System PLLCLK cycles is required
between two write accesses to SPCTL0 register. The following is a procedure for changing the System PLL
settings:
1. Program the desired values of PD, MFD, MFI, and MFN into the SPCTL0.
2. Set the SPLL_RESTART bit in the CSCR (it will self-clear).
3. New PLL settings will take place.
SPCTL0
BIT
31
30
29
28
27
26
25
24
23
22
21
PD
TYPE
Addr
0x0021B00C
System PLL Control Register 0
20
19
18
17
16
MFD
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
7
6
5
4
3
2
1
0
RESET
0x043F
BIT
15
14
13
12
11
10
9
8
MFI
TYPE
MFN
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
1
0
1
0
0
0
0
1
1
0
1
1
1
RESET
0x1437
Table 12-12. System PLL Control Register 0 Description
Name
Description
Settings
Reserved
Bits 31–30
Reserved—These bits are reserved and should read 0.
PD
Bits 29–26
Predivider Factor—Defines the predivider factor (PD) that is applied to the PLL input
frequency. PD is an integer between 0 and 15 (inclusive). The System PLL oscillates at a
frequency determined by Equation 12-1. The PD is chosen to ensure that the resulting
VCO output frequency remains within the specified range. When a new value is written
into the PD bits, the PLL loses its lock: after a time delay, the PLL re-locks.
0000 = 0
0001 = 1
…
1111 = 15
MC9328MXS Reference Manual, Rev. 1.1
12-12
Freescale Semiconductor
Programming Model
Table 12-12. System PLL Control Register 0 Description (continued)
Name
Description
Settings
MFD
Bits 25–16
Multiplication Factor (Denominator Part)—Defines the denominator part of the BRM
value for the MF. When a new value is written into the MFD9–MFD0 bits, the PLL loses
its lock: after a time delay, the PLL re-locks.
0x000 = Reserved
0x001 = 1
…
0x3FF = 1023
Reserved
Bits 15–14
Reserved—These bits are reserved and should read 0.
MFI
Bits 13–10
Multiplication Factor (Integer Part)—Defines the integer part of the BRM value for the
MF. The MFI is decoded so that MFI < 5 results in MFI = 5.
The System PLL oscillates at a frequency determined by Equation 12-1.
Where PD is the division factor of the predivider, MFI is the integer part of the total MF,
MFN is the numerator of the fractional part of the MF, and MFD is the denominator part of
the MF. The MF is chosen to ensure that the resulting VCO output frequency remains
within the specified range. When a new value is written into the MFI bits, the PLL loses its
lock; after a time delay, the PLL re-locks.
0000–0101 = 5
0110 = 6
...
1111 = 15
MFN
Bits 9–0
Multiplication Factor (Numerator Part)—Defines the numerator part of the BRM value
for the MF. When a new value is written into the MFN bits, the PLL loses its lock; after a
time delay, the PLL re-locks.
0x000 = 0
0x001 = 1
...
0x3FE = 1022
0x3FF = Reserved
12.5.4.2 System PLL Control Register 1
The System PLL control register 1 (SPCTL1) is a 32-bit read/write register in the MCU memory map that directs
the operation of the System PLL. The SPCTL1 control bits are described in this section.
SPCTL1
Addr
0x0021B010
System PLL Control Register 1
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
LF
TYPE
6
BRMO
rw
r
r
r
r
r
r
r
r
rw
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
12-13
Programming Model
Table 12-13. System PLL Control Register 1 Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
LF
Bit 15
Lock Flag—Indicates whether the System PLL is locked. When set, the
System PLL clock output is valid. When cleared, the System PLL clock
output remains at logic high.
Reserved
Bits 14–7
Reserved—These bits are reserved and should read 0.
BRMO
Bit 6
BRM Order Bit—Controls the BRM order. The first order BRM is used if a
MF fractional part is both more than 1/10 and less than 9/10. In other cases,
the second order BRM is used. The BRMO bit is cleared by a hardware
reset.
Reserved
Bits 5–0
Reserved—These bits are reserved and should read 0.
Settings
0 = System PLL is not locked
1 = System PLL is locked
0 = BRM has first order
1 = BRM has second order
MC9328MXS Reference Manual, Rev. 1.1
12-14
Freescale Semiconductor
Chapter 13
DMA Controller
The Direct Memory Access Controller (DMAC) of the MC9328MXS provides eleven channels supporting linear
memory, 2D memory, FIFO and end-of-burst enable FIFO transfers to provide support for a wide variety of DMA
operations.
13.1 Features
The MC9328MXS DMAC features are:
•
Eleven channels support linear memory, FIFO, and end-of-burst enable FIFO for both source and
destination.
•
Any one of the eleven channels can be configured to support 2D memory.
•
Increment, decrement, and no-change support for source and destination addresses.
•
Each channel is configurable to response to any of the 32 DMA request signals.
•
Supports 8, 16, or 32-bit FIFO and memory port size data transfers.
•
Supports both big and little endian.
•
DMA is configurable to a maximum of 16 words, 32 half-words, or 64 bytes for each channel.
•
Bus utilization control for the channel that is not trigger by a DMA request.
•
Burst time-out errors terminate the DMA cycle when the burst cannot be completed within a programmed
time count.
•
Buffer overflow errors terminate the DMA cycle when the internal buffer receives more than 64 bytes of
data. This is useful when the source mode is set to end-of-burst enable FIFO, in case the DMA_EOBI signal
is not detected after 64 bytes of data are received.
•
Transfer errors terminate the DMA cycle when a transfer error is detected during a DMA burst.
•
DMA request time-out errors are generated for channels that are triggered by DMA requests to interrupt the
CPU when a DMA request is not asserted after a programmed time count.
•
Interrupts provided to the interrupt controller (and subsequently to the core) on bulk data transfer complete
or transfer error.
•
Each peripheral supporting DMA transfer generates a DMA_REQ signal to the DMA controller, assuming
that each FIFO has a unique system address and generates a dedicated DMA_REQ signal to the DMA
controller. For example, an USB device with 8 end-points has 8 DMA request signals to the DMA if they
all support DMA transfer.
•
The DMA controller provides an acknowledge signal to the peripheral after a DMA burst is complete. This
signal is sometimes used by the peripheral to clear some status bits.
•
Repeat data transfer function supports automatic USB host–USB device bulk/iso data stream transfer.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
13-1
Block Diagram
13.2 Block Diagram
SPI
AIPI
IP Bus
IP Bus
AHB
SSI
DMA
I2S
IP Bus
DMA_REQ [31:0], DMA_ACK,
DMA_EOBO, DMA_EOBI,
DMA_EOBO_CNT,
DMA_EOBI_CNT
UART
MIG
Figure 13-1. DMAC in MC9328MXS
System
Registers
AHB_BUS_ARB
DMA_EOBI, DMA_EOBI_CNT
Prioritize
BUS_REQ
Channel 0
registers
Source Sel
Channel 1
registers
Source Sel
Channel n
registers
Source Sel
DMA_REQ [31:0]i
AHB_BUS_ARB
Bus Arbiter
AHB_CNTL
AHB_A [31:0]
AHB_D [31:0]
AHB I/F
Cntl Signal
Generation
BG
AHB I/F
Address
Generation
DMA_ACK,
DMA_EOBO, and
DMA_EOBO_CNT
Generation
AHB I/F
Data Buffer
Interrupt
Generation
DMA_ACK
DMA_EOBO
DMA_EOBO_CNT
DMA_ERR
DMA_INT
16 × 32 Data
FIFO
Figure 13-2. DMAC Block Diagram
MC9328MXS Reference Manual, Rev. 1.1
13-2
Freescale Semiconductor
Signal Description
DMA_REQ
DMA_DATA
DMA_ACK
Figure 13-3. DMA Request and Acknowledge Timing Diagram
Display
Linear Memory
2D Memory
W-Size
X-Size
Y-Size =
no. of
X-Size
Source or
Destination
Address
Y-Size
W-Size
Figure 13-4. 2D Memory Diagram
13.3 Signal Description
The MC9328MXS signal descriptions are identified in Table 13-1.
Table 13-1. Signal Description
Signal
Description
AHB_xxx
AHB bus signals
IP Bus
IP bus signals
DMA_REQ
DMA request signal generated by peripherals. One FIFO should generate one DMA_REQ signal. This
signal must be negated by the peripheral automatically before the rising edge of DMA_ACK. It is
usually negated when the FIFO is read.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
13-3
Programming Model
Table 13-1. Signal Description (continued)
Signal
Description
DMA_ACK
DMA request acknowledge generated by the DMA controller to signal the end of a DMA burst.
DMA_EOBI
This signal is asserted by the USB device when the last data of the burst is read from the FIFO.
DMA_EOBI_CNT
This signal is asserted by the USB device when the last data of the burst is read from the FIFO to
indicate the number of valid bytes.
DMA_EOBO
This signal is asserted by the DMA controller when the last data of the burst is written to the FIFO.
DMA_EOBO_CNT
This signal is asserted by the DMA controller when the last data of the burst is written to the FIFO to
indicate the number of valid bytes.
DMA_ERR
This signal is asserted by DMA controller when any DMA error is detected.
DMA_INT
This signal is asserted by DMA controller when data transfer is complete—that is, the data count
reaches the desired level.
13.3.1 Big Endian and Little Endian
The BIG_ENDIAN signal determines the MC9328MXS memory endian configuration. BIG_ENDIAN is a static
pin to the processor and if it is driven logic-high at power on reset the processor's memory system is configured as
big endian. If it is driven logic-low at power on reset the processor's memory system is configured as little endian.
The pin should not be changed after power on reset (POR) deasserts or during operation.
13.4 Programming Model
The DMA module includes 107 user-accessible 32-bit registers. These registers are divided into three groups by
function:
•
General registers for all functional blocks (see Section 13.4.1, on page 13-8)
•
2D memory registers to control the display width and the x and y of the window (see Section 13.4.2, on page
13-16)
•
Channel registers to control and configure channels 0–10 (see Section 13.4.3, on page 13-18)
Table 13-2 summarizes these registers and their addresses.
Table 13-2. DMA Module Register Memory Map
Description
Name
Address
DMA Control Register
DCR
0x00209000
DMA Interrupt Status Register
DISR
0x00209004
DMA Interrupt Mask Register
DIMR
0x00209008
General Registers
MC9328MXS Reference Manual, Rev. 1.1
13-4
Freescale Semiconductor
Programming Model
Table 13-2. DMA Module Register Memory Map (continued)
Description
Name
Address
DMA Burst Time-Out Status Register
DBTOSR
0x0020900C
DMA Request Time-Out Status Register
DRTOSR
0x00209010
DMA Transfer Error Status Register
DSESR
0x00209014
DMA Buffer Overflow Status Register
DBOSR
0x00209018
DMA Burst Time-Out Control Register
DBTOCR
0x0020901C
2D Memory Registers
W-Size Register A
WSRA
0x00209040
X-Size Register A
XSRA
0x00209044
Y-Size Register A
YSRA
0x00209048
W-Size Register B
WSRB
0x0020904C
X-Size Register B
XSRB
0x00209050
Y-Size Register B
YSRB
0x00209054
Channel 0 Source Address Register
Channel 0 Destination Address Register
Channel 0 Count Register
Channel 0 Control Register
Channel 0 Request Source Select Register
Channel 0 Burst Length Register
Channel 0 Request Time-Out Register
Channel 0 Bus Utilization Control Register
SAR0
DAR0
CNTR0
CCR0
RSSR0
BLR0
RTOR0
BUCR0
0x00209080
0x00209084
0x00209088
0x0020908C
0x00209090
0x00209094
0x00209098
0x00209098
Channel 1 Source Address Register
Channel 1 Destination Address Register
Channel 1 Count Register
Channel 1 Control Register
Channel 1 Request Source Select Register
Channel 1 Burst Length Register
Channel 1 Request Time-Out Register
Channel 1 Bus Utilization Control Register
SAR1
DAR1
CNTR1
CCR1
RSSR1
BLR1
RTOR1
BUCR1
0x002090C0
0x002090C4
0x002090C8
0x002090CC
0x002090D0
0x002090D4
0x002090D8
0x002090D8
Channel 2 Source Address Register
Channel 2 Destination Address Register
Channel 2 Count Register
Channel 2 Control Register
Channel 2 Request Source Select Register
Channel 2 Burst Length Register
Channel 2 Request Time-Out Register
Channel 2 Bus Utilization Control Register
SAR2
DAR2
CNTR2
CCR2
RSSR2
BLR2
RTOR2
BUCR2
0x00209100
0x00209104
0x00209108
0x0020910C
0x00209110
0x00209114
0x00209118
0x00209118
Channel Registers
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
13-5
Programming Model
Table 13-2. DMA Module Register Memory Map (continued)
Description
Name
Address
Channel 3 Source Address Register
Channel 3 Destination Address Register
Channel 3 Count Register
Channel 3 Control Register
Channel 3 Request Source Select Register
Channel 3 Burst Length Register
Channel 3 Request Time-Out Register
Channel 3 Bus Utilization Control Register
SAR3
DAR3
CNTR3
CCR3
RSSR3
BLR3
RTOR3
BUCR3
0x00209140
0x00209144
0x00209148
0x0020914C
0x00209150
0x00209154
0x00209158
0x00209158
Channel 4 Source Address Register
Channel 4 Destination Address Register
Channel 4 Count Register
Channel 4 Control Register
Channel 4 Request Source Select Register
Channel 4 Burst Length Register
Channel 4 Request Time-Out Register
Channel 4 Bus Utilization Control Register
SAR4
DAR4
CNTR4
CCR4
RSSR4
BLR4
RTOR4
BUCR4
0x00209180
0x00209184
0x00209188
0x0020918C
0x00209190
0x00209194
0x00209198
0x00209198
Channel 5 Source Address Register
Channel 5 Destination Address Register
Channel 5 Count Register
Channel 5 Control Register
Channel 5 Request Source Select Register
Channel 5 Burst Length Register
Channel 5 Request Time-Out Register
Channel 5 Bus Utilization Control Register
SAR5
DAR5
CNTR5
CCR5
RSSR5
BLR5
RTOR5
BUCR5
0x002091C0
0x002091C4
0x002091C8
0x002091CC
0x002091D0
0x002091D4
0x002091D8
0x002091D8
Channel 6 Source Address Register
Channel 6 Destination Address Register
Channel 6 Count Register
Channel 6 Control Register
Channel 6 Request Source Select Register
Channel 6 Burst Length Register
Channel 6 Request Time-Out Register
Channel 6 Bus Utilization Control Register
SAR6
DAR6
CNTR6
CCR6
RSSR6
BLR6
RTOR6
BUCR6
0x00209200
0x00209204
0x00209208
0x0020920C
0x00209210
0x00209214
0x00209218
0x00209218
Channel 7 Source Address Register
Channel 7 Destination Address Register
Channel 7 Count Register
Channel 7 Control Register
Channel 7 Request Source Select Register
Channel 7 Burst Length Register
Channel 7 Request Time-Out Register
Channel 7 Bus Utilization Control Register
SAR7
DAR7
CNTR7
CCR7
RSSR7
BLR7
RTOR7
BUCR7
0x00209240
0x00209244
0x00209248
0x0020924C
0x00209250
0x00209254
0x00209258
0x00209258
Channel 8 Source Address Register
Channel 8 Destination Address Register
Channel 8 Count Register
Channel 8 Control Register
Channel 8 Request Source Select Register
Channel 8 Burst Length Register
Channel 8 Request Time-Out Register
Channel 8 Bus Utilization Control Register
SAR8
DAR8
CNTR8
CCR8
RSSR8
BLR8
RTOR8
BUCR8
0x00209280
0x00209284
0x00209288
0x0020928C
0x00209290
0x00209294
0x00209298
0x00209298
MC9328MXS Reference Manual, Rev. 1.1
13-6
Freescale Semiconductor
Programming Model
Table 13-2. DMA Module Register Memory Map (continued)
Description
Name
Address
Channel 9 Source Address Register
Channel 9 Destination Address Register
Channel 9 Count Register
Channel 9 Control Register
Channel 9 Request Source Select Register
Channel 9 Burst Length Register
Channel 9 Request Time-Out Register
Channel 9 Bus Utilization Control Register
SAR9
DAR9
CNTR9
CCR9
RSSR9
BLR9
RTOR9
BUCR9
0x002092C0
0x002092C4
0x002092C8
0x002092CC
0x002092D0
0x002092D4
0x002092D8
0x002092D8
Channel 10 Source Address Register
Channel 10 Destination Address Register
Channel 10 Count Register
Channel 10 Control Register
Channel 10 Request Source Select Register
Channel 10 Burst Length Register
Channel 10 Request Time-Out Register
Channel 10 Bus Utilization Control Register
SAR10
DAR10
CNTR10
CCR10
RSSR10
BLR10
RTOR10
BUCR10
0x00209300
0x00209304
0x00209308
0x0020930C
0x00209310
0x00209314
0x00209318
0x00209318
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
13-7
Programming Model
13.4.1 General Registers
This section describes the function of the general registers.
13.4.1.1 DMA Control Register
The DMA Control Register (DCR) controls the input of the system clock and the resetting of the DMA module.
DCR
Addr
0x00209000
DMA Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
DRST
DEN
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
r
r
r
r
r
r
r
r
r
r
r
r
r
r
w
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-3. DMA Control Register Description
Name
Description
Settings
Reserved
Bits 31–2
Reserved—These bits are reserved and should read 0.
DRST
Bit 1
DMA Reset—Generates a 3-cycle reset pulse that resets the entire DMA
module, bringing the module to its reset condition. DRST always reads 0.
0 = No effect
1 = Generates a 3-cycle reset pulse
DEN
Bit 0
DMA Enable—Enables/Disables the system clock to the DMA module.
0 = DMA disable
1 = DMA enable
MC9328MXS Reference Manual, Rev. 1.1
13-8
Freescale Semiconductor
Programming Model
13.4.1.2 DMA Interrupt Status Register
The DMA Interrupt Status Register (DISR) contains the interrupt status of each channel in the DMAC. The status
bit is set whenever the corresponding DMA channel data transfer is complete. When any bit in the DMA Interrupt
Status Register (DISR) is set and the corresponding bit in the interrupt mask register is cleared, a DMA_INT is
asserted to the interrupt controller (AITC). When an interrupt occurs, the interrupt service routine must check the
DISR to determine the interrupting channel. Each bit is cleared by writing 1 to it. The DISR bit cannot be cleared
when the DMA channel is disabled.
DISR
Addr
0x00209004
DMA Interrupt Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
15
TYPE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-4. DMA Interrupt Status Register Description
Name
Description
Reserved
Bits 31–11
Reserved—These bits are reserved and should read 0.
CH10–CH0
Bits 10–0
Channel 10 to 0 Interrupt Status—Indicates the interrupt status for each
DMA channel.
Settings
0 = No interrupt
1 = Interrupt is pending
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
13-9
Programming Model
13.4.1.3 DMA Interrupt Mask Register
The DMA Interrupt Mask Register (DIMR) masks both normal interrupts and error interrupts generated by the
corresponding channel. There is one control bit for each channel. When an interrupt is masked, the interrupt
controller does not generate an interrupt request to the AITC, however the status of the interrupt can be observed
from the interrupt status register, burst time-out status register, request time-out status register, or the transfer error
status register. At reset, all the interrupts are masked and all the bits in this register are set to 1.
DIMR
Addr
0x00209008
DMA Interrupt Mask Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
15
TYPE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
RESET
0x07FF
Table 13-5. DMA Interrupt Mask Register Description
Name
Description
Reserved
Bits 31–11
Reserved—These bits are reserved and should read 0.
CH10–CH0
Bits 10–0
Channel 10 to 0—Controls the interrupts for each DMA channel.
Settings
0 = Enables interrupts
1 = Disables interrupts
MC9328MXS Reference Manual, Rev. 1.1
13-10
Freescale Semiconductor
Programming Model
13.4.1.4 DMA Burst Time-Out Status Register
A burst time-out is set when a DMA burst cannot be completed within the number of clock cycles specified in the
DMA Burst Time-Out Control Register (DBTOCR) of the channel. When any bit is set in this register and the
corresponding bit in the interrupt mask register is cleared, a DMA_ERR is asserted to the interrupt controller
(AITC). The DMA burst time-out status register (DBTOSR) indicates the channel, if any, that is currently being
serviced and whether a burst time-out was detected. Each bit is cleared by writing 1 to it.
DBTOSR
Addr
0x0020900C
DMA Burst Time-Out Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-6. DMA Burst Time-Out Status Register Description
Name
Description
Reserved
Bits 31–11
Reserved—These bits are reserved and should read 0.
CH10–CH0
Bits 10–0
Channel 10 to 0—Indicates the burst time-out status of each DMA channel.
Settings
0 = No burst time-out
1 = Burst time-out
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
13-11
Programming Model
13.4.1.5 DMA Request Time-Out Status Register
A DMA request time-out is set when there is no DMA request from the selected DMA_REQ source within the
pre-assigned number of clock cycles specified in the request time-out control register (DBTOCR) for the channel.
When any bit is set in this register and the corresponding bit in the interrupt mask register is cleared, a DMA_ERR
is asserted to the AITC. The DMA Request Time-Out Status Register (DRTOSR) indicates the enabled channel, if
any, that detected a DMA request time-out. Clear each bit by writing 1 to it.
DRTOSR
Addr
0x00209010
DMA Request Time-Out Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
15
TYPE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-7. DMA Request Time-Out Status Register Description
Name
Description
Reserved
Bits 31–11
Reserved—These bits are reserved and should read 0.
CH10–CH0
Bits 10–0
Channel 10 to 0—Indicates the request time-out status of each DMA
channel.
Settings
0 = No DMA request time-out
1 = DMA request time-out
MC9328MXS Reference Manual, Rev. 1.1
13-12
Freescale Semiconductor
Programming Model
13.4.1.6 DMA Transfer Error Status Register
A DMA transfer error is set when the AHB bus signal HRESP [1:0] = ERROR is asserted during a DMA transfer.
When any bit is set in this register and the corresponding bit in the interrupt mask register is cleared, a DMA_ERR
is asserted to the AITC. The DMA Transfer Error Status Register (DSESR) indicates the channel, if any, detected a
transfer error during a DMA burst. Clear each bit by writing 1 to it.
DSESR
Addr
0x00209014
DMA Transfer Error Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
15
TYPE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-8. DMA Transfer Error Status Register Description
Name
Description
Reserved
Bits 31–11
Reserved—These bits are reserved and should read 0.
CH10–CH0
Bits 10–0
Channel 10 to 0—Indicates the DMA transfer error status of each DMA
channel.
Settings
0 = No transfer error
1 = Transfer error
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
13-13
Programming Model
13.4.1.7 DMA Buffer Overflow Status Register
The DMA Buffer Overflow Status Register (DBOSR) indicates whether the internal buffer of the DMA Controller
overflowed during a data transfer. The channel is not enabled until the corresponding bit is cleared. When any bit is
set in this register and the corresponding bit in the interrupt mask register is cleared, a DMA_ERR is asserted to the
AITC.
DBOSR
Addr
0x00209018
DMA Buffer Overflow Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-9. DMA Buffer Overflow Status Register Description
Name
Description
Reserved
Bits 31–11
Reserved—These bits are reserved and should read 0.
CH10–CH0
Bits 10–0
Channel 10 to 0—Indicates the buffer overflow error status of each
DMA channel.
Settings
0 = No buffer overflow occurred
1 = Buffer overflow occurred
MC9328MXS Reference Manual, Rev. 1.1
13-14
Freescale Semiconductor
Programming Model
13.4.1.8 DMA Burst Time-Out Control Register
This register sets the time-out for DMA transfer cycle for all DMA channels, so that the DMA controller can
release the AHB and IP buses on error. An internal counter starts counting when a DMA burst cycle starts, and
resets to zero when the burst is completed. When the counter reaches the count value set in the register, it asserts an
interrupt and sets the corresponding error bit in the DMA burst time-out error register. The system clock is used as
input clock to the counter.
DBTOCR
Addr
0x0020901C
DMA Burst Time-Out Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
EN
TYPE
CNT
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-10. DMA Burst Time-Out Control Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
EN
Bit 15
Enable—Enables/Disables the burst time-out.
CNT
Bits 14–0
Count—Contains the time-out count down value.
Settings
0 = Disables burst time-out
1 = Enables burst time-out
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
13-15
Programming Model
13.4.2 2D Memory Registers (A and B)
The two sets of 2D memory registers allow any one channel of the eleven channels to select any register set to
define the respective 2D memory size.
13.4.2.1 W-Size Registers
The W-Size registers (WSRA and WSRB) define the number of bytes that make up the display width. This allows
the DMA controller to calculate the next starting address of another row by adding the source/destination address
to the contents of the W-Size register.
WSRA
WSRB
Addr
0x00209040
0x0020904C
W-Size Register A
W-Size Register B
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WS
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-11. W-Size Registers Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
WS
Bits 15–0
W-Size—Contains the number of bytes that make up the display width.
MC9328MXS Reference Manual, Rev. 1.1
13-16
Freescale Semiconductor
Programming Model
13.4.2.2 X-Size Registers
The X-Size registers (XSRA and XSRB) contain the number of bytes per row of the window. The value of this
register is used by the DMA controller to determine when to jump to the next row.
XSRA
XSRB
Addr
0x00209044
0x00209050
X-Size Register A
X-Size Register B
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
XS
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-12. X-Size Registers Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
XS
Bits 15–0
X-Size—Contains the number of bytes per row that define the X-Size of the 2D memory.
Settings
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
13-17
Programming Model
13.4.2.3 Y-Size Registers
The Y-Size registers (YSRA and YSRB) contain the number of rows in the 2D memory window. This setting is
used by the DMA controller to calculate the total size of the transfer.
YSRA
YSRB
Addr
0x00209048
0x00209054
Y-Size Register A
Y-Size Register B
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
YS
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-13. Y-Size Registers Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
YS
Bits 15–0
Y-Size—Contains the number of rows that make up the 2D memory window.
13.4.3 Channel Registers
Channels 0 to 10 support linear memory, 2D memory, FIFO, and end-of-burst enable FIFO transfer. Only one
enabled channel may be configured for 2D memory at any time.
The interrupt request DMA_REQ [31:0] does not have a priority assigned. The only priority available is the
priority that is defined for each channel: channel 10 has the highest priority and channel 0 has the lowest priority.
Channel priority is implemented only when more than one request occurs at the same time, otherwise, channels are
serviced on a first come, first serve basis.
Each channel generates a normal interrupt to the interrupt handler when the data count reaches the selected value
and the channel source mode is not set to end-of-burst enable FIFO.
Each channel generates an error interrupt to the interrupt handler when the following conditions exist:
•
A DMA request time-out is true
•
A DMA burst time-out is true during a burst cycle
•
The internal buffer overflows during a burst cycle
•
A transfer error acknowledge is asserted during a burst cycle
MC9328MXS Reference Manual, Rev. 1.1
13-18
Freescale Semiconductor
Programming Model
13.4.3.1 Channel Source Address Register
Each of the channel source address registers contain the source address for the DMA cycle. The value of the
register remains unchanged throughout the DMA process. If the memory direction bit (MDIR) in the channel
control register (CCR) is clear (indicating a memory address increment), then the channel source address register
contains the starting address of the memory block. If MDIR is set (indicating a memory address decrement), then
the channel source address register contains the ending address of the memory block.
SAR0
SAR1
SAR2
SAR3
SAR4
SAR5
SAR6
SAR7
SAR8
SAR9
SAR10
BIT
Addr
0x00209080
0x002090C0
0x00209100
0x00209140
0x00209180
0x002091C0
0x00209200
0x00209240
0x00209280
0x002092C0
0x00209300
Channel 0 Source Address Register
Channel 1 Source Address Register
Channel 2 Source Address Register
Channel 3 Source Address Register
Channel 4 Source Address Register
Channel 5 Source Address Register
Channel 6 Source Address Register
Channel 7 Source Address Register
Channel 8 Source Address Register
Channel 9 Source Address Register
Channel 10 Source Address Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SA [31:16]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SA [15:2]
TYPE
SA [1] SA [0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-14. Channel Source Address Register Description
Name
Description
SA [31:2]
Bits 31–2
Source Address—Contains the source address from where data is read during a DMA transfer.
SA [1], SA [0]
Bits 1–0
Source Address [1] and Source Address [0]—To ensure that all addresses are word-aligned these bits
are set internally to 0. These bits will be read/write as any value if and only if running in big endian and
source mode set to FIFO. This is to allow FIFO to use offset address during big endian mode.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
13-19
Programming Model
13.4.3.2 Destination Address Registers
Each of the destination address registers (DARx) contain the destination address for a DMA cycle. The value of the
register remains unchanged throughout the DMA process. If the memory direction bit (MDIR) in the channel
control register (CCR) is clear (indicating a memory address increment), then the destination address register
contains the starting address of the memory block. If MDIR is set (indicating a memory address decrement), then
the destination address register contains the ending address of the memory block.
DAR0
DAR1
DAR2
DAR3
DAR4
DAR5
DAR6
DAR7
DAR8
DAR9
DAR10
BIT
Addr
0x00209084
0x002090C4
0x00209104
0x00209144
0x00209184
0x002091C4
0x00209204
0x00209244
0x00209284
0x002092C4
0x00209304
Channel 0 Destination Address Register
Channel 1 Destination Address Register
Channel 2 Destination Address Register
Channel 3 Destination Address Register
Channel 4 Destination Address Register
Channel 5 Destination Address Register
Channel 6 Destination Address Register
Channel 7 Destination Address Register
Channel 8 Destination Address Register
Channel 9 Destination Address Register
Channel 10 Destination Address Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DA [31:16]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DA [15:2]
TYPE
DA [1] DA [0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-15. Channel Destination Address Registers Description
Name
Description
DA [31:2]
Bits 31–2
Destination Address—Contains the destination address to which data is written to during a DMA transfer.
DA [1], DA [0]
Bits 1–0
Destination Address [1] and Destination Address [0]—To ensure that all addresses are word-aligned,
these bits are set internally to 0.
MC9328MXS Reference Manual, Rev. 1.1
13-20
Freescale Semiconductor
Programming Model
13.4.3.3 Channel Count Registers
Each of the channel count registers (CNTRx) contain the number of bytes of data to be transferred. There is an
internal counter that counts up (number of bytes—4 for word, 2 for halfword and 1 for byte) for every DMA
transfer. The internal counter is compared with the register after every transfer. When the counter value matches
with the register value, the channel is disabled until the CEN bit is cleared and reset, or the RPT bit in the
associated channel control register is set to 1. The internal counter is reset to 0 when the channel is enabled again.
The length of the last DMA burst can be shorter than the regular burst length specified in the burst length register.
However, when data is transferred out from an I/O FIFO and the last burst is less than BL, the I/O device must
generate a DMA request for the last transfer. When data is transferred to an I/O FIFO and the last burst is less than
BL, only the remaining number of data is transferred.
When the source mode is set to end-of-burst enable FIFO, this register becomes a read only register and the value
of the register is the number of bytes being transferred.
CNTR0
CNTR1
CNTR2
CNTR3
CNTR4
CNTR5
CNTR6
CNTR7
CNTR8
CNTR9
CNTR10
BIT
Addr
0x00209088
0x002090C8
0x00209108
0x00209148
0x00209188
0x002091C8
0x00209208
0x00209248
0x00209288
0x002092C8
0x00209308
Channel 0 Count Register
Channel 1 Count Register
Channel 2 Count Register
Channel 3 Count Register
Channel 4 Count Register
Channel 5 Count Register
Channel 6 Count Register
Channel 7 Count Register
Channel 8 Count Register
Channel 9 Count Register
Channel 10 Count Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CNT
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNT
RESET
0x0000
Table 13-16. Channel Count Registers Description
Name
Description
Reserved
Bits 31–24
Reserved—These bits are reserved and should read 0.
CNT
Bits 23–0
Count—Contains the number of bytes of data to be transferred during a DMA cycle.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
13-21
Programming Model
13.4.3.4 Channel Control Registers
Each of the channel control registers (CCRx) controls and displays the status of a DMA channel operation.
NOTE:
While any one of the eleven channels may be configured for 2D memory, only one
enabled channel may be configured for 2D memory at any time, This constraint
does not apply to configuring the DMA channels for linear memory, FIFO, and
end-of-burst enable FIFO.
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
CCR7
CCR8
CCR9
CCR10
Addr
0x0020908C
0x002090CC
0x0020910C
0x0020914C
0x0020918C
0x002091CC
0x0020920C
0x0020924C
0x0020928C
0x002092CC
0x0020930C
Channel 0 Control Register
Channel 1 Control Register
Channel 2 Control Register
Channel 3 Control Register
Channel 4 Control Register
Channel 5 Control Register
Channel 6 Control Register
Channel 7 Control Register
Channel 8 Control Register
Channel 9 Control Register
Channel 10 Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
DMOD
TYPE
10
SMOD
9
8
MDIR MSEL
DSIZ
SSIZ
REN RPT FRC
CEN
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
w
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-17. Channel Control Registers Description
Name
Description
Reserved
Bits 31–14
Reserved—These bits are reserved and should read 0.
DMOD
Bits 13–12
Destination Mode—Selects the destination transfer mode.
Settings
00 = Linear memory
01 = 2D memory
10 = FIFO
11 = End-of-burst enable FIFO
MC9328MXS Reference Manual, Rev. 1.1
13-22
Freescale Semiconductor
Programming Model
Table 13-17. Channel Control Registers Description (continued)
Name
Description
Settings
SMOD
Bits 11–10
Source Mode—Selects the source transfer mode.
00 = Linear memory
01 = 2D memory
10 = FIFO
11 = End-of-burst enable FIFO
MDIR
Bit 9
Memory Direction—Selects the memory address direction.
0 = Memory address increment
1 = Memory address decrement
MSEL
Bit 8
Memory Select—Selects the 2D memory register set when either
source and/or destination is programmed to 2D memory mode.
0 = 2D memory register set A selected
1 = 2D memory register set B selected
DSIZ
Bits 7–6
Destination Size—Selects the destination size of a data transfer.
00 = 32-bit destination port
01 = 8-bit destination port
10 = 16-bit destination port
11 = Reserved
SSIZ
Bits 5–4
Source Size—Selects the source size of data transfer.
Note: DSIZ1:DSIZ0 always reads/writes 00 when destination
mode is programmed as end-of-burst enable FIFO, because
end-of-burst operation only works for 32-bit FIFO.
Note: SSIZ1:SSIZ0 always reads/writes 00 when destination
mode is programmed as end-of-burst enable FIFO, because end of
burst operation only works for 32-bit FIFO.
00 = 32-bit source port
01 = 8-bit source port
10 = 16-bit source port
11 = Reserved
REN
Bit 3
Request Enable—Enables/Disables the DMA request signal. When
REN is set, the DMA burst is initiated by the DMA_REQ signal from
the I/O FIFO. When REN is cleared, DMA transfer is initiated by
CEN.
0 = Disables the DMA request signal
(when the peripheral asserts a
DMA request, no DMA transfer is
triggered); DMA transfer is
initiated by CEN only
1 = Enables the DMA request signal
(when the peripheral asserts a
DMA request, a DMA transfer is
triggered)
RPT
Bit 2
Repeat—Enables/Disables the data transfer repeat function. When
enabled and when the counter reaches the value set in Count
Register, the Count Register is reset to its zero, an interrupt is
asserted, and the corresponding channel bit in the Interrupt Mask
Register is cleared. The address is reloaded from the source and
destination address register for the next DMA burst. Data transfer is
carried out continuously until the channel is disabled or it completes
the last cycle after RPT is cleared.
If enabling the repeat function, do not change source and
destination addresses on the fly. If it is necessary to change
source and destination addresses, do it after a complete DMA cycle
finishes and then re-start the channel again.
0 = Disables repeat function
1 = Enables repeat function
Note: To correctly terminate a repeat enabled channel[x], user is
required to first set RSSR[x] to 0, then set CCR[x]-REN to 1, and
finally CCR[x]-CEN to 0.
FRC
Bit 1
Force a DMA Cycle—Forces a DMA cycle to occur. FRC always
reads 0.
0 = No effect
1 = Force DMA cycle
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
13-23
Programming Model
Table 13-17. Channel Control Registers Description (continued)
Name
CEN
Bit 0
Description
Settings
DMA Channel Enable—Enables/Disables the DMA channel.
0 = Disables the DMA channel
1 = Enables the DMA channel
Note:
1. Program all of the channel settings before enabling the channel.
2. To restart a channel, clear CEN, and then set CEN to 1.
When the source mode is set to end-of-burst enable FIFO, the burst length is determined by the input signals
DMA_EOBI and DMA_EOBI_CNT, and the DMA burst (from peripheral to memory) can be terminated only by
disabling the channel (clearing the corresponding CEN bit in channel control register). The count register
(CNTR0-CNTR10) becomes read-only and indicates the number of bytes being transferred. This setting is
typically used when the channel is configured to transfer data from an endpoint FIFO of a USB device to an
endpoint data packet buffer in system memory.
When the destination mode is set to end-of-burst enable FIFO, the channel operates the same as in normal FIFO
mode, the only difference is that at the end of each burst, the DMA controller generates a DMA_EOBO and
DMA_EOBO_CNT signal to the peripheral. This setting is typically used when the I/O channel is configured to
transfer data from an endpoint data packet buffer in system memory to an endpoint FIFO of a USB device.
Table 13-18. DMA_EOBO_CNT and DMA_EOBI_CNT Settings
DMA_EOBI_CNT [1:0] or
DMA_EOBO_CNT [1:0]
Number of Bytes Per Transfer
00
4
01
1
10
2
11
3
MC9328MXS Reference Manual, Rev. 1.1
13-24
Freescale Semiconductor
Programming Model
13.4.3.5 Channel Request Source Select Registers
Each of the 32-bit channel request source select registers (RSSRx) selects one of the 32 DMA request signals
(DMA_REQ [31:0]) to initiate a DMA transfer for the corresponding channel.
RSSR0
RSSR1
RSSR2
RSSR3
RSSR4
RSSR5
RSSR6
RSSR7
RSSR8
RSSR9
RSSR10
Addr
0x00209090
0x002090D0
0x00209110
0x00209150
0x00209190
0x002091D0
0x00209210
0x00209250
0x00209290
0x002092D0
0x00209310
Channel 0 Request Source Select Register
Channel 1 Request Source Select Register
Channel 2 Request Source Select Register
Channel 3 Request Source Select Register
Channel 4 Request Source Select Register
Channel 5 Request Source Select Register
Channel 6 Request Source Select Register
Channel 7 Request Source Select Register
Channel 8 Request Source Select Register
Channel 9 Request Source Select Register
Channel 10 Request Source Select Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
RSS
TYPE
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-19. Channel Request Source Select Registers Description
Name
Description
Reserved
Bits 31–5
Reserved—These bits are reserved and should read 0.
RSS
Bits 4–0
Request Source Select—Selects one of the 32 DMA_REQ signals
that initiates a DMA transfer cycle for the channel.
Settings
00000 = select DMA_REQ [0]
00001 = select DMA_REQ [1]
...
11111 = select DMA_REQ [31]
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
13-25
Programming Model
13.4.3.6 Channel Burst Length Registers
The Channel Burst Length registers (BLRx) control the burst length of a DMA cycle. For a FIFO channel setting,
the burst length is normally assigned according to the FIFO size of the selected I/O device, or by the FIFO level at
which its DMA_REQ signal is asserted.
For example, when the UART RxD FIFO is 12 × 8 and it asserts DMA_REQ when it receives more than 8 bytes of
data, BL is 8. When the memory port size also is 8-bit, the DMA burst is 8-byte reads followed by 8-byte writes.
When the memory port size is smaller than the I/O port size, the burst length of the byte writes is doubled. For
example, the I/O port is 32-bit, the memory port is 16-bit, and the burst length is set to 32. In this configuration, the
DMA performs 8 word burst reads and 16 halfword burst writes for I/O to memory transfer.
BLR0
BLR1
BLR2
BLR3
BLR4
BLR5
BLR6
BLR7
BLR8
BLR9
BLR10
Channel 0 Burst Length Register
Channel 1 Burst Length Register
Channel 2 Burst Length Register
Channel 3 Burst Length Register
Channel 4 Burst Length Register
Channel 5 Burst Length Register
Channel 6 Burst Length Register
Channel 7 Burst Length Register
Channel 8 Burst Length Register
Channel 9 Burst Length Register
Channel 10 Burst Length Register
0x00209094
0x002090D4
0x00209114
0x00209154
0x00209194
0x002091D4
0x00209214
0x00209254
0x00209294
0x002092D4
0x00209314
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
BL
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-20. Channel Burst Length Registers Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
BL
Bits 5–0
Burst Length—Contains the number of data bytes that
are transferred in a DMA burst.
Settings
000000 = 64 bytes read follow 64 bytes write
000001 = 1byte read follow 1 byte write
000010 = 2 bytes read follow 2 bytes write
....
111111 = 63 bytes read follow 63 bytes write
MC9328MXS Reference Manual, Rev. 1.1
13-26
Freescale Semiconductor
Programming Model
13.4.3.7 Channel Request Time-Out Registers
The channel request time-out registers (RTOx) set the time-out for DMA_REQ from the selected request source of
the channel, which detects any discontinuity of data transfer. The request time-out takes effect only when the
corresponding request enable (REN) bit in the channel control register (CCR) is set. An internal counter starts
counting when a DMA channel is enabled, the burst is completed, and the counter is reset to zero when a DMA
request is detected. When the counter reaches the count value set in the register, it asserts an interrupt and sets its
error bit in the DMA request time-out status register. The input clock of the counter is selectable from either the
system clock (HCLK) or input crystal (CLK32K).
NOTE:
This register shares the same address as the bus utilization control register.
RTOR0
RTOR1
RTOR2
RTOR3
RTOR4
RTOR5
RTOR6
RTOR7
RTOR8
RTOR9
RTOR10
Channel 0 Request Time-Out Register
Channel 1 Request Time-Out Register
Channel 2 Request Time-Out Register
Channel 3 Request Time-Out Register
Channel 4 Request Time-Out Register
Channel 5 Request Time-Out Register
Channel 6 Request Time-Out Register
Channel 7 Request Time-Out Register
Channel 8 Request Time-Out Register
Channel 9 Request Time-Out Register
Channel 10 Request Time-Out Register
0x00209098
0x002090D8
0x00209118
0x00209158
0x00209198
0x002091D8
0x00209218
0x00209258
0x00209298
0x002092D8
0x00209318
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
EN
CLK
PSC
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNT
RESET
0x0000
Table 13-21. Channel Request Time-Out Registers Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
EN
Bit 15
Enable—Enables/Disables the DMA request time-out.
Settings
0 = Disables DMA request time-out
1 = Enables DMA request time-out
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
13-27
Programming Model
Table 13-21. Channel Request Time-Out Registers Description (continued)
Name
Description
Settings
CLK
Bit 14
Clock Source—Selects the counter of input clock source.
0 = HCLK
1 = 32.768 kHz
PSC
Bit 13
Prescaler Count—Sets the prescaler of the input clock.
0 = Divide by 1
1 = Divide by 256
CNT
Bits 12–0
Request Time-Out Count—Contains the time-out count down value for the internal counter. This value
remains unchanged through out the DMA process.
13.4.3.8 Channel 0 Bus Utilization Control Register
The Bus Utilization Control register (BUCRx) controls the bus utilization of an enabled channel when the request
enable (REN) bit in channel control register (CCR) is cleared. The channel does not request a DMA transfer until
the counter reaches the count value set in the register except for the very first burst. This counter is cleared when
the channel burst is started. When the count value is set to zero, the DMA carries on burst transfers one after
another until it reaches the value set in count register. In this case, the user must be careful not to violate the
maximum bus request latency of other devices.
NOTE:
This register shares the same address of request time-out register.
MC9328MXS Reference Manual, Rev. 1.1
13-28
Freescale Semiconductor
Programming Model
BUCR0
BUCR1
BUCR2
BUCR3
BUCR4
BUCR5
BUCR6
BUCR7
BUCR8
BUCR9
BUCR10
Channel 0 Bus Utilization Control Register
Channel 1 Bus Utilization Control Register
Channel 2 Bus Utilization Control Register
Channel 3 Bus Utilization Control Register
Channel 4 Bus Utilization Control Register
Channel 5 Bus Utilization Control Register
Channel 6 Bus Utilization Control Register
Channel 7 Bus Utilization Control Register
Channel 8 Bus Utilization Control Register
Channel 9 Bus Utilization Control Register
Channel 10 Bus Utilization Control Register
0x00209098
0x002090D8
0x00209118
0x00209158
0x00209198
0x002091D8
0x00209218
0x00209258
0x00209298
0x002092D8
0x00209318
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
CCNT
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-22. Channel 0 Bus Utilization Control Registers Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
CCNT
Bits 15–0
Clock Count—Sets the number of system clocks that must occur before the memory channel releases the
AHB, before the next DMA request for the channel.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
13-29
DMA Request Table
13.5 DMA Request Table
Table 13-23 identifies the dedicated DMA request signal and its associated peripheral.
Table 13-23. DMA Request Table
DMA Request
Peripheral
DMA_REQ [31]
UART 1 Receive DMA Request
DMA_REQ [30]
UART 1 Transmit DMA Request
DMA_REQ [29]
UART 2 Receive DMA Request
DMA_REQ [28]
UART 2 Transmit DMA Request
DMA_REQ [27]
Reserved
DMA_REQ [26]
Reserved
DMA_REQ [25]
USB Device End Point 5 DMA Request
DMA_REQ [24]
USB Device End Point 4 DMA Request
DMA_REQ [23]
USB Device End Point 3 DMA Request
DMA_REQ [22]
USB Device End Point 2 DMA Request
DMA_REQ [21]
USB Device End Point 1 DMA Request
DMA_REQ [20]
USB Device End Point 0 DMA Request
DMA_REQ [19]
Reserved
DMA_REQ [18]
Reserved
DMA_REQ [17]
SSI Receive DMA Request
DMA_REQ [16]
SSI Transmit DMA Request
DMA_REQ [15]
SPI 1 Transmit DMA Request
DMA_REQ [14]
SPI 1 Receive DMA Request
DMA_REQ [13]
Reserved
DMA_REQ [12]
Ext_DMA
DMA_REQ [11]
DSPA MAC DMA Request
DMA_REQ [10]
DSPA DCT DIN DMA Request
DMA_REQ [9]
DSPA DCT DOUT DMA Request
DMA_REQ [8]
Reserved
DMA_REQ [7]
Reserved
DMA_REQ [6]
Reserved
DMA_REQ [5]
Reserved
DMA_REQ [4]
Reserved
DMA_REQ [3]
Reserved
DMA_REQ [2]
Reserved
DMA_REQ [1]
Reserved
DMA_REQ [0]
Reserved
MC9328MXS Reference Manual, Rev. 1.1
13-30
Freescale Semiconductor
Chapter 14
Watchdog Timer Module
14.1 General Overview
The watchdog timer module of the MC9328MXS protects against system failures by providing a method of
escaping from unexpected events or programming errors. Once activated, the timer must be serviced by software
on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the watchdog timer
module either asserts a system reset signal WDT_RST or a interrupt request signal WDT_INT depending on
software configuration. Table 14-1 on page 14-5 shows the watchdog timer module’s input and output signals. A
state machine that demonstrates the time-out operation of the counter operation is shown in Figure 14-2 on
page 14-4.
14.2 Watchdog Timer Operation
The following sections describe the operation and programming of the watchdog timer module.
14.2.1 Timing Specifications
The watchdog timer provides time-out periods from 0.5 seconds up to 64 seconds with a time resolution of 0.5
seconds. As shown in Figure 14-1, the watchdog timer uses the CLK2HZ clock (from RTC module) as an input to
achieve the resolution of 0.5 seconds and a frequency of 2 Hz. This clock is connected to the input of a 7-bit
counter to obtain a range of 0.5 to 64 seconds. The user can determine the time-out period by writing to the
watchdog time-out field (WT[6:0]) in the Watchdog Control Register (WCR).
WHALT
WDE
7-bit Counter
CLK2HZ
0
CLK32K
1
(Time-Out)
Test Mode (TMD bit)
Figure 14-1. Watchdog Timer Functional Block Diagram
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
14-1
Watchdog After Reset
14.2.2 Watchdog During Reset
14.2.2.1 Power-On Reset
During a power-on reset (POR) all registers are reset to their reset values and the counter is placed in the idle state
until the watchdog is enabled. The Watchdog Status Register (WSTR) contains the source of the reset event and the
interrupt status bit TINT is reset to 0.
14.2.2.2 Software Reset
When software reset occurs, the software reset (SWR) bit in Watchdog Control Register (WCR) is set to 1, all
registers of the Watchdog module are reset to their reset values and the counter is placed in the idle state until the
watchdog is enabled.
14.3 Watchdog After Reset
After reset, watchdog timer operation can be divided into four states: initial load, countdown, reload, and time-out.
The following sections define each of the watchdog timer states after reset.
14.3.1 Initial Load
The Watchdog Control Register (WCR) bits WT[6:0] must be written to before the watchdog is enabled. The
watchdog is then enabled by setting the one-time writable watchdog enable (WDE) bit in the WCR. The time-out
value is loaded into the counter after the service sequence is written to the Watchdog Service Register (WSR) or
after the watchdog is enabled. The service sequence is described in Section 14.3.3, “Reload.” The counter state
machine is shown in Figure 14-2 on page 14-4.
14.3.2 Countdown
The counter is activated after the Watchdog is enabled and begins to count down from its initial programmed value.
If any system errors have occurred which prevents the software from servicing the Watchdog Service Register
(WSR), the timer will time-out when the counter reaches zero. If the WSR is serviced prior to the counter reaching
zero, the watchdog reloads its counter to the time-out value indicated by bits WT[6:0] of the WCR and re-start the
countdown. A reset will reset the counter and place it in the idle state at any time during the countdown. The
counter state machine is shown in Figure 14-2 on page 14-4.
14.3.3 Reload
The recommended service sequence is to write a $5555 followed by a $AAAA to the WSR. To reload the counter,
the writes must take place within the time-out value indicated by bits WT[6:0] of the WCR. Any number of
instructions can be executed between the two writes. This service sequence is also used to activate the counter
during the initial load. See Section 14.3.1, “Initial Load.”
If the WSR is not loaded with a $5555 prior to a write of $AAAA to the WSR, the counter will not be reloaded. If
any value other than $AAAA is written to the WSR after $5555, the counter will not be reloaded.
MC9328MXS Reference Manual, Rev. 1.1
14-2
Freescale Semiconductor
Watchdog Control
14.3.4 Time-Out
If the counter reaches zero, the TOUT bit in WSTR (Watchdog Status Register) is set to 1 indicating that watchdog
has timed out. Reading the TOUT bit will clear it.
If the counter reaches zero, the watchdog asserts either a system reset signal WDT_RST or an interrupt request
signal WDT_INT depending on the state of the WIE bit in the WCR. A 1 written to WIE configures the watchdog
to generate a interrupt request signal to the interrupt handler. When a watchdog time-out interrupt is asserted, the
TINT bit in WSTR (Watchdog Status Register) is set to 1 to indicate that an interrupt request is generated and the
reading of this bit clears the interrupt and this bit. A 0 written to the WIE bit configures the watchdog to generate a
WDT_RST signal to reset the module. The counter state machine is shown in Figure 14-2 on page 14-4.
14.3.5 Halting the Counter
The watchdog counting can be halted at any time by setting the WHALT bit (WCR[15]) to 1. The counter
immediately stops counting and the counter value is held at the last value. The WHALT bit can be cleared by
writing 0 to it or it can be automatically cleared by the occurrence of any of three system events, fast interrupt, slow
interrupt, or system reset. The counter resumes counting from the stopped value. No other configurations are
affected.
14.4 Watchdog Control
14.4.1 Interrupt Control
The watchdog timer generates interrupt request signal WDT_INT as a result of a WDOG time-out when WIE bit of
WCR set to 1. The TINT bit of WSTR is set to 1 to indicate that the interrupt request has been generated. Reading
the TINT bit clears the interrupt and this status bit.
14.4.2 Reset Sources
The watchdog timer generates reset signal WDT_RST as a result of a WDOG time-out. This signal is an output to
the Reset Module for system reset generation.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
14-3
State Machine
14.5 State Machine
Idle
No
No
Resets
Negated
?
Time-out
Value
?
Yes
No
Watchdog
Enabled
?
Yes
Yes
Start Counter
Decrement Counter
Yes
Counting
Resumed
(fiq, irq,
reset)
?
No
Counting
Halted
(WHALT=1)
?
Yes
Counter
Suspended
No
Reload Counter
Yes
WSR
Service
d
No
Count = 0
No
?
Yes
Assert Time-out
Indication
No
Interrupt
Request
?
Yes
Assert wdt_rst
Assert wdt_int
Reset
Module
Interrupt
Handler
Figure 14-2. Counter State Machine
MC9328MXS Reference Manual, Rev. 1.1
14-4
Freescale Semiconductor
Watchdog Timer I/O Signals
14.6 Watchdog Timer I/O Signals
Table 14-1shows the watchdog timer module input and output signals.
Table 14-1. Watchdog Timer I/O Signals
Signal Name
I/O
Description
FIQ
I
Fast Interrupt
IRQ
I
Normal Interrupt
IPS_HARD_ASYNC_RESET
I
WDOG global reset from reset module
IPS_CONT_CLK
I
96 MHz system clock
IPS_CONT_CLK
I
96 MHz system clock inverted
IPS_GATED_CLK
I
Bus clock
IPS_GATED_CLK
I
Bus clock inverted
CLK2HZ
I
2 Hz clock input from RTC module output
CLK32K
I
in test mode, counter clock becomes 32 kHz clock
IPS_MODULE_EN
I
Watchdog module enable
IPS_BYTE_15_8
I
Bit 15 to 8 enable
IPS_BYTE_7_0
I
Bit 7 to 0 enable
IPS_MRW
I
Module read/write signal
IPS_ADDR[11:2]
I
Module address bus
IPS_WDATA[31:0]
I
Module write data bus
SCAN_MODE
I
Indicates scan mode selection
SCAN_RESET
I
Indicates scan reset
IPS_CONT_CLK_EN
O
ips_cont_clk enable
IPS_XFR_ERR
O
Transfer error acknowledge
IPS_XFR_WAIT
O
Transfer wait acknowledge
IPS_RDATA[31:0]
O
Module read data bus
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
14-5
Programming Model
14.7 Programming Model
The watchdog timer has three registers in its programming model: Watchdog Control Register (WCR), Watchdog
Service Register (WSR), and Watchdog Status Register (WSTR).
.
Name
WCR
($00201000)
15
R
14
13
12
11
WHAL
T
10
9
8
7
6
5
0
0
0
WT[6:0]
4
WIE
3
2
1
0
TMD SWR WDEC WDE
W
WSR
($00201004)
WSTR
($00201008)
R
WSR[15:0]
W
R
0
0
0
0
0
0
0
TINT
0
0
0
0
0
0
0
TOUT
W
14.7.1 Watchdog Control Register
The WCR is a 32-bit read/write (byte writable) register. It controls the Watchdog operation. See Table 14-2 on
page 14-6 for bit descriptions and settings.
WCR
Addr
0x00201000
Watchdog Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
WIE
TMD
SWR
WDEC
WDE
RESET
0x0000
BIT
15
14
13
12
WHALT
TYPE
11
10
9
8
7
6
WT
rw
rw
rw
rw
rw
rw
rw
rw
r
r
r
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 14-2. Watchdog Control Register Description
Name
Description
Reserved
Bits 31–15
Reserved—These bits are reserved and should read 0.
WHALT
Bit 15
Watchdog Halt—When set, the watchdog counter immediately stops
counting and the counter value is held at the last value. The WHALT
bit can be cleared by writing 0 to it or it can be automatically cleared by
the occurrence of any of three system events, fast interrupt, slow
interrupt, or system reset.
Settings
0 = Counter is not halted
1 = Counter is halted
MC9328MXS Reference Manual, Rev. 1.1
14-6
Freescale Semiconductor
Programming Model
Table 14-2. Watchdog Control Register Description (continued)
Name
Description
Settings
WT
Bits 14–8
Watchdog Time-Out Field—This 7-bit field contains the time-out
value and is loaded into the Watchdog counter after the service routine
has been performed. After reset, WT[6:0] must be written before
enabling the Watchdog.
Reserved
Bits 7–5
Reserved—These bits are reserved and should read 0.
WIE
Bit 4
Watchdog Interrupt Enable—Determines if the WDT_RST is
asserted or WDT_INT is asserted upon a watchdog time-out.
1 = Assert WDT_INT
0 = Assert WDT_RST
TMD
Bit 3
Test Mode Enable—Determines if WDOG timer is in test mode.
0 = Use 2 Hz clock as counter clock
1 = Use CLK32K as counter clock
SWR
Bit 2
Software Reset Enable—Determines if a software reset is enabled.
0 = Software reset is not enabled
1 = Software reset is enabled
WDEC
Bit 1
Watchdog Enable Control—Controls the write access of the WDE
bit.
0 = WDE bit is write once only
1 = WDE bit is write multiple
WDE
Bit 0
Watchdog Enable—Enables or disables the watchdog module. Write
once-only if WDEC bit is low. Write multiple if WDEC bit is high
0 = Disable Watchdog
1 = Enable Watchdog
Note:
Set to desired time-out value.
This bit is used only for test purposes
14.7.2 Watchdog Service Register
The Watchdog Service register contains the watchdog service sequence. When Watchdog is enabled, the Watchdog
requires that a service sequence be written to the Watchdog Service Register (WSR) as described in Table 14-3.
WSR
Addr
0x00201004
Watchdog Service Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WSR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 14-3. Watchdog Service Register Description
Name
Reserved
Bits 31–16
Description
Settings
Reserved—These bits are reserved and should read 0.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
14-7
Programming Model
Table 14-3. Watchdog Service Register Description (continued)
Name
Description
WSR
Bits 15–0
Settings
Watchdog Service Register—This 15-bit field contains the
watchdog service sequence.
Both writes must occur in the order listed prior to the time-out,
however any number of instructions can be executed between
the two writes.
The service sequence must be performed
as follows:
a) Write $5555 to the Watchdog Service
Register (WSR).
b) Write $AAAA to the Watchdog Service
Register (WSR)
14.7.3 Watchdog Status Register
The WSTR is a read-only register which records the source of the RESET_OUT event and interrupt status. It is
cleared by reset. It records the source of the RESET_OUT event and interrupt status. RESET_OUT can be
generated by the following sources which are listed in priority from highest to lowest: Power-on reset, External
reset (RESET_IN), and Watchdog Time-out.
.
WSTR
Addr
0x00201008
Watchdog Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
TINT
TYPE
TOUT
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 14-4. Watchdog Status Register Description
Name
Description
Reserved
Bits 31–9
Reserved—These bits are reserved and should read 0.
TINT
Bit 8
Time-Out Interrupt—Indicates whether the time-out
interrupt generated
Reserved
Bits 7–1
Reserved—These bits are reserved and should read 0.
TOUT
Bit 0
Time-Out—Indicates whether the watchdog timer times out.
Settings
0 = No time-out interrupt generated
1 = Time-out interrupt generated
0 = Watchdog timer does not time-out.
1 = Watchdog timer times out.
MC9328MXS Reference Manual, Rev. 1.1
14-8
Freescale Semiconductor
Chapter 15
Serial Peripheral Interface Module (SPI 1)
The MC9328MXS contains one serial peripheral interface module (SPI 1).
SPI 1 signals are multiplexed with GPIO ports as primary functions. See Chapter 2, “Signal Descriptions and Pin
Assignments,” for detailed pin assignments. The user must configure the corresponding GPIO registers to make
SPI 1 signals available at the pins. See Section 15.2.3, “Pin Configuration,” for more information about selecting
SPI 1 signals.
Table 15-1. SPI 1 Signal Multiplexing
SPI Signal Names
Connect to GPIO Signal
SPI1_SPI_RDY
Primary function of GPIO port C [13]
SPI1_SCLK
Primary function of GPIO port C [14]
SPI1_SS
Primary function of GPIO port C [15]
SPI1_MISO
Primary function of GPIO port C [16]
SPI1_MOSI
Primary function of GPIO port C [17]
15.1 SPI Block Diagram
This section describes how the SPI module communicates with external devices.
The SPI module has one 8 × 16-bit receive buffer (RXFIFO) and one 8 × 16-bit transmit buffer (TXFIFO). The SPI
ready (SPI_RDY) and slave select (SS) control signals enable fast data communication with fewer software
interrupts. The block diagram is shown in Figure 15-1 on page 15-2.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
15-1
Operation
IP BUS INTERFACE
SPI_RDY
CLOCK
GENERATOR
CONTROL
SS
SCLK
MISO
SHIFT REGISTER
MOSI
RX FIFO
TX FIFO
Figure 15-1. SPI Module Block Diagram
15.2 Operation
To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as a master,
two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY signal (input).
The SPI 1 Sample Period Control Register (PERIODREG1) can also be programmed to a fixed data transfer rate.
When the SPI 1 module is configured as a slave, the user can configure the SPI 1 Control Register
(CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS becomes an input signal,
and is used to latch data into or load data out to the internal data shift registers, as well as to increment the data
FIFO. Figure 15-2 on page 15-3 shows the generic SPI timing.
15.2.1 Phase and Polarity Configurations
The SPI master uses the SCLK signal to transfer data in and out of the shift register. Data is clocked by one of four
programmable clock phase and polarity combinations, selected through the phase (PHA) and polarity (POL) bits in
the CONTROLREG1 and CONTROLREG2 registers.
In Phase 0 operation (PHA=0) and SCLK Polarity active low (POL=0), output data changes on falling edges of the
SCLK signal and input data is shifted in on rising edges. The most significant bit (MSB) is output when the CPU
loads the transmitted data.
In Phase 0 operation (PHA=0) and SCLK Polarity active high (POL=1), output data changes on rising edges of the
SCLK signal and input data is shifted in on falling edges. The most significant bit (MSB) is output on the first
rising edge of the SCLK signal.
In Phase 1 operation (PHA=1) and SCLK Polarity active low (POL=0), output data changes on rising edges of the
SCLK signal and input data is shifted in on falling edges. The MSB is output on the first rising edge of the SCLK
signal.
In Phase 1 operation (PHA=1) and SCLK Polarity active high (POL=1), output data changes on falling edges of the
SCLK signal and input data is shifted in on rising edges. The MSB is output when the CPU loads the transmitted
data.
MC9328MXS Reference Manual, Rev. 1.1
15-2
Freescale Semiconductor
Operation
This flexibility allows the SPI modules to operate with most currently available serial peripheral devices.
Figure 15-2 shows the relationship of the polarity and phase settings.
15.2.2 Signals
The following signals are used to control the serial peripheral interface master:
•
Master Out Slave In (MOSI)—In master mode, this bidirectional signal is a TX output signal from the data
shift register. In slave mode, it is an RX input.
•
Master In Slave Out (MISO)—In master mode, this bidirectional signal is a RX input signal to the data shift
register. In slave mode, it is a TX output.
•
SPI Clock (SCLK)—In master mode, this bidirectional signal is an SPI clock output. In slave mode, it is an
input.
•
Slave Select (SS)—In master mode, this bidirectional signal is an output. In slave mode, it is an input.
•
SPI Ready (SPI_RDY)—Used only in master mode to edge- or level-trigger an SPI burst.
(POL=1, PHA=1) SCLK
(POL=1, PHA=0) SCLK
(POL=0, PHA=1) SCLK
(POL=0, PHA=0) SCLK
MISO
Bn Bn-1 Bn-2 Bn-3 ...
...
B1
B0
MOSI
Bn Bn-1 Bn-2 Bn-3 ...
...
B1
B0
Figure 15-2. SPI Generic Timing
15.2.3 Pin Configuration
Table 15-1 lists the pins used for the SPI 1 module. These pins are multiplexed with other functions on the device,
and must be configured for SPI operation.
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 25.5.1, “Data Direction Registers,” on
page 25-8 for details.
Table 15-2. SPI Pin Configuration
Pin
Setting
Configuration Procedure
SPI1_SPI_RDY
Primary function of
GPIO port C [13]
1. Clear bit 13 of Port C GPIO In Use Register (GIUS_C)
2. Clear bit 13 of Port C General Purpose Register (GPR_C)
SPI1_SCLK
Primary function of
GPIO port C [14]
1. Clear bit 14 of Port C GPIO In Use Register (GIUS_C)
2. Clear bit 14 of Port C General Purpose Register (GPR_C)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
15-3
Programming Model
Table 15-2. SPI Pin Configuration (continued)
Pin
Setting
Configuration Procedure
SPI1_SS
Primary function of
GPIO port C [15]
1. Clear bit 15 of Port C GPIO In Use Register (GIUS_C)
2. Clear bit 15 of Port C General Purpose Register (GPR_C)
SPI1_MISO
Primary function of
GPIO port C [16]
1. Clear bit 16 of Port C GPIO In Use Register (GIUS_C)
2. Clear bit 16 of Port C General Purpose Register (GPR_C)
SPI1_MOSI
Primary function of
GPIO port C [17]
1. Clear bit 17 of Port C GPIO In Use Register (GIUS_C)
2. Clear bit 17 of Port C General Purpose Register (GPR_C)
15.3 Programming Model
The SPI module includes eight 32-bit registers. Table 15-3 summarizes these registers and their addresses.
Table 15-3. SPI Module Register Memory Map
Description
Name
Address
SPI 1 Rx Data Register
RXDATAREG1
0x00213000
SPI 1 Tx Data Register
TXDATAREG1
0x00213004
SPI 1 Control Register
CONTROLREG1
0x00213008
SPI 1 Interrupt Control/Status Register
INTREG1
0x0021300C
SPI 1 Test Register
TESTREG1
0x00213010
SPI 1 Sample Period Control Register
PERIODREG1
0x00213014
SPI 1 DMA Control Register
DMAREG1
0x00213018
SPI 1 Soft Reset Register
RESETREG1
0x0021301C
MC9328MXS Reference Manual, Rev. 1.1
15-4
Freescale Semiconductor
Programming Model
15.3.1 Receive (RX) Data Register
The SPI receive data register is a read-only register that forms the top word of the 8 × 16 RXFIFO. This register
holds data received from an external SPI device during a data transaction.
RXDATAREG1
Addr
0x00213000
SPI 1 Rx Data Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DATA
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 15-4. SPI 1 Rx Data Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
DATA
Bits 15–0
DATA—Holds the top word of data received into the FIFO. Not valid when the Receive Data Ready (RR) bit
in the corresponding Interrupt Control/Status Register (INTREG1) is cleared.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
15-5
Programming Model
15.3.2 Transmit (TX) Data Register
The SPI transmit data register is a write-only data register that forms the top word of the 8 × 16 TXFIFO. The
TXFIFO can be written to as long as it is not full, even when the exchange (XCH) bit in the corresponding SPI
control register (CONTROLREG1) is set. This allows user write access to the TXFIFO during an SPI data
exchange process. Writes to this register are ignored when the SPI module is disabled (SPIEN bit of the
corresponding SPI control register is cleared).
TXDATAREG1
Addr
0x00213004
SPI 1 Tx Data Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DATA
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 15-5. SPI 1 Tx Data Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
DATA
Bits 15–0
DATA—Holds the top word of data loaded into the FIFO. Data written to this register can be 8 or 16 bits. The
number of bits actually transmitted is determined by the BIT_COUNT field of the corresponding SPI control
register. If this field contains more bits than the number specified by BIT_COUNT, the extra bits are ignored.
For example, to transfer 10 bits of data, a 16-bit word must be written to this register. Bits 9-0 are shifted out
and bits 15-10 are ignored. When the SPI module is operating in slave mode, ‘0’s are shifted out when the
FIFO is not full.
MC9328MXS Reference Manual, Rev. 1.1
15-6
Freescale Semiconductor
Programming Model
15.3.3 Control Register
The SPI control register allows the user to enable the SPI module, select the operating mode, specify the divider
value, phase, and polarity of the clock, configure the SS and SPI_RDY control signals, and define the transfer
length.
CONTROLREG1
Addr
0x00213008
SPI 1 Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
PHA
POL
RESET
0x0000
BIT
15
14
13
DATARATE
TYPE
12
11
DRCTL
10
9
MODE SPIEN
8
XCH
7
SSPOL SSCTL
BIT_COUNT
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0/11
0
0
0
0
0
0
0
0
0
0
RESET
0x0000 / 0x04001
1.
In CONTROLREG2, the MODE bit is set to 1.
Table 15-6. SPI 1 Control Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
DATARATE
Bits 15–13
Data Rate—Selects the divide value of SCLK from the
PERCLK2 in the PLL and Clock Control Module.
000 = Divide by 4
001 = Divide by 8
010 = Divide by 16
011 = Divide by 32
100 = Divide by 64
101 = Divide by 128
110 = Divide by 256
111 = Divide by 512
DRCTL
Bits 12–11
SPI_RDY Control—Selects the waveform of the SPI_RDY input
signal when the SPI 1 module operates in master mode. In slave
mode, DRCTL is ignored.
00 = Ignore SPI_RDY
01 = Falling edge triggers input
10 = Active low level triggers input
11 = Reserved
MODE
Bit 10
SPI Mode Select—Selects the mode for the SPI 1 module. In
CONTROLREG2, MODE is set by the hardware.
0 = Slave mode
1 = Master mode
SPIEN
Bit 9
SPI Module Enable—Enables/Disables the serial peripheral
interface. SPIEN must be asserted before an exchange is
initiated. Writing 0 to SPIEN flushes the receive and transmit
FIFOs.
0 = Disable the SPI
1 = Enable the SPI
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
15-7
Programming Model
Table 15-6. SPI 1 Control Register Description (continued)
Name
Description
Settings
XCH
Bit 8
Exchange—Initiates a data exchange in master mode. XCH
remains set while the exchange is in progress, or while the SPI
module is waiting for an active SPI_RDY control signal input.
XCH is automatically cleared when all data in the TXFIFO and
shift register are shifted out.
In slave mode, XCH must be cleared.
0 = Idle
1 = Initiates exchange (write) or busy
(read)
SSPOL
Bit 7
SS Polarity Select—Selects the polarity of the SS signal (in
both master and slave mode).
0 = Active low
1 = Active high
SSCTL
Bit 6
SS Wave Form Select—Selects the output wave form for the
SS signal when in master mode.
In master mode:
0 = SS stays low between SPI bursts
1 = Insert pulse between SPI bursts
Controls RXFIFO advancement when in slave mode.
In slave mode:
0 = RXFIFO advanced by BIT_COUNT
1 = RXFIFO advanced by SS rising edge
PHA
Bit 5
Phase—Controls the clock/data phase relationship (see
Figure 15-2 on page 15-3).
0 = Phase 0 operation
1 = Phase 1 operation
POL
Bit 4
Polarity—Controls the polarity of the SCLK signal (see
Figure 15-2 on page 15-3).
0 = Active high polarity (0 = idle)
1 = Active low polarity (1 = idle)
BIT_COUNT
Bits 3–0
Bit Count—This field selects the length of the transfer. A
maximum of 16bits can be transferred.
0000 = 1–bit transfer
0001 = 2–bit transfer
...
1111 = 16–bit transfer
In master mode, a 16-bit data word is loaded from TxFIFO to
shift register and only the least n bits (n=BIT COUNT) are shifted
out. The next 16-bit word is then loaded to shift register.
In slave mode and when SSCTL bit is 0 this field controls the
number of bits received as a data word loaded to RxFIFO. When
SSCTL bit is 1 and SS rising edge is faster than BIT COUNT is
treated, then this field is don’t care.
MC9328MXS Reference Manual, Rev. 1.1
15-8
Freescale Semiconductor
Programming Model
15.3.4 Interrupt Control/Status Register
The SPI interrupt control status register allows the user to enable various interrupt signals and monitor the status of
those interrupts.
INTREG1
Addr
0x0021300C
SPI 1 Interrupt Control/Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
BO
RO
RF
RH
RR
TF
TH
TE
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
BOEN ROEN RFEN RHEN RREN TFEN THEN TEEN
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 15-7. SPI 1 Interrupt Control/Status Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
BOEN
Bit 15
Bit Count Overflow Interrupt Enable—Enables/Disables the Bit
Count Overflow Interrupt.
0 = Disable interrupt
1 = Enable interrupt
ROEN
BIT 14
RXFIFO Overflow Interrupt Enable—Enables/Disables the RXFIFO
Overflow Interrupt.
0 = Disable interrupt
1 = Enable interrupt
RFEN
Bit 13
RXFIFO Full Interrupt Enable—Enables/Disables the RXFIFO Full
Interrupt.
0 = Disable interrupt
1 = Enable interrupt
RHEN
Bit 12
RXFIFO Half Interrupt Enable—Enables/Disables the RXFIFO
Half-Full Interrupt.
0 = Disable interrupt
1 = Enable interrupt
RREN
Bit 11
RXFIFO Data Ready Interrupt Enable—Enables/Disables the
RXFIFO Data Ready Interrupt.
0 = Disable interrupt
1 = Enable interrupt
TFEN
Bit 10
TXFIFO Full Interrupt Enable—Enables/Disables the TXFIFO Full
Interrupt.
0 = Disable interrupt
1 = Enable interrupt
THEN
Bit 9
TXFIFO Half Interrupt Enable—Enables/Disables the TXFIFO
Half-Empty Interrupt.
0 = Disable interrupt
1 = Enable interrupt
TEEN
Bit 8
TXFIFO Empty Interrupt Enable—Enables/Disables the TXFIFO
Empty Interrupt.
0 = Disable interrupt
1 = Enable interrupt
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
15-9
Programming Model
Table 15-7. SPI 1 Interrupt Control/Status Register Description (continued)
Name
Description
Settings
BO
Bit 7
Bit Count Overflow—Indicates that a bit count overflow has occurred.
BO is applicable for the SPI 1 module only when the bits of
CONTROLREG1 are set so that
MODE = 0 and SSCTL = 1. The overflow occurs when the slave
receives more than 16 bits in one burst. BO is cleared after a data read
from the RXDATAREG1 register. There is no way to determine which
data word overflowed, so the bad data word can still be in the FIFO if it
is not empty.
0 = No bit count overflow error
1 = At least one data word in RXFIFO
has a bit count overflow error
RO
Bit 6
RXFIFO Overflow—Indicates that the RXFIFO has overflowed. At
least one newly written data word has been lost. The RO flag is
automatically cleared after a data read.
0 = No RXFIFO overflow error
1 = At least one data word in the
RXFIFO has been overwritten
RF
Bit 5
RXFIFO Full Status—Indicates that the RXFIFO is full.
0 = Less than 8 data words are in the
RXFIFO
1 = 8 data words are in the RXFIFO
RH
Bit 4
RXFIFO Half Status—Indicates that the RXFIFO is at least half-full.
0 = Less than 4 data words are in the
RXFIFO
1 = At least 4 data words are in the
RXFIFO
RR
Bit 3
RXFIFO Data Ready Status—Indicates that the RXFIFO is empty.
0 = The RXFIFO is empty
1 = At least one data word is in the
RXFIFO
TF
Bit 2
TXFIFO Full Status—Indicates that the TXFIFO is full.
0 = Less than 8 data words are in the
TXFIFO
1 = 8 data words are in the TXFIFO
TH
Bit 1
TXFIFO Half Status—Indicates that the TXFIFO is at least half-empty.
0 = Less than 4 empty slots are in the
TXFIFO
1 = At least 4 empty slots are in the
TXFIFO
TE
Bit 0
TXFIFO Empty Status—Indicates that the TXFIFO is empty.
0 = At least one data word is in the
TXFIFO
1 = The TXFIFO is empty, however
data shifting may still be
on-going. To be sure no data
transaction is on-going, check
the XCH bit(s) in the Control
Register(s).
MC9328MXS Reference Manual, Rev. 1.1
15-10
Freescale Semiconductor
Programming Model
15.3.5 Test Register
The SPI test register allows the user to internally connect the receive and transmit sections, display the status of the
state machine, and monitor the contents of the receive and transmit FIFOs.
TESTREG1
Addr
0x00213010
SPI 1 Test Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
LBC
TYPE
10
9
8
SSTATUS
RXCNT
TXCNT
r
rw
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 15-8. SPI 1 Test Register Description
Name
Description
Settings
Reserved
Bits 31–15
Reserved—These bits are reserved and should read 0.
LBC
Bit 14
Loop Back Control—Internally connects the receive and transmit
sections internally for test purposes.
Reserved
Bits 13–12
Reserved—These bits are reserved and should read 0.
SSTATUS
Bits 11–8
State Machine Status—Indicates the state machine status (used for test purposes only).
RXCNT
Bits 7–4
RXFIFO Counter—Indicates the number of data words in the RXFIFO.
0 = RX and TX sections are not
internally connected
1 = RX and TX sections are
internally connected
0000 = RXFIFO is empty
0001 = 1 data word in RXFIFO
0010 = 2 data words in RXFIFO
0011 = 3 data words in RXFIFO
0100 = 4 data words in RXFIFO
0101 = 5 data words in RXFIFO
0110 = 6 data words in RXFIFO
0111 = 7 data words in RXFIFO
1000 = 8 data words in RXFIFO
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
15-11
Programming Model
Table 15-8. SPI 1 Test Register Description (continued)
Name
Description
TXCNT
Bits 3–0
Settings
TXFIFO Counter—Indicates the number of data words in the TXFIFO.
0000 = TXFIFO is empty
0001 = 1 data word in TXFIFO
0010 = 2 data words in TXFIFO
0011 = 3 data words in TXFIFO
0100 = 4 data words in TXFIFO
0101 = 5 data words in TXFIFO
0110 = 6 data words in TXFIFO
0111 = 7 data words in TXFIFO
1000 = 8 data words in TXFIFO
15.3.6 Sample Period Control Register
The SPI sample period control register allows the user to select the clock source for the counter and to set the wait
between data transactions. The wait is only applicable when the SPI module is operating in master mode.
PERIODREG1
Addr
0x00213014
SPI 1 Sample Period Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
CSRC
TYPE
WAIT
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 15-9. SPI 1 Sample Period Control Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
CSRC
Bit 15
Clock Source—Selects the clock source for the counter.
0 = Bit clock
1 = 32.768 kHz or 32 kHz clock
WAIT
Bits 14–0
Wait—Determines the number of clocks inserted between data
transactions (when operating in master mode).
0x0000 = 0 clock
0x0001 = 1 clock
0x0002 = 2 clocks
…
0x7FFF = 32,767 clocks
MC9328MXS Reference Manual, Rev. 1.1
15-12
Freescale Semiconductor
Programming Model
15.3.7 DMA Control Register
The SPI DMA control register allows the user to enable DMA requests when the FIFOs are full, empty, or half-full.
This register also contains status bits for FIFO full, empty, and half-empty conditions.
DMAREG1
Addr
0x00213018
SPI 1 DMA Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
THDMA
TEDMA
RFDMA
RHDMA
RESET
0x0000
BIT
15
14
13
12
THDEN
TEDEN
RFDEN
RHDEN
rw
rw
rw
rw
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TYPE
11
10
9
8
RESET
0x0000
Table 15-10. SPI 1 DMA Control Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
THDEN
Bit 15
THDEN—Enables/Disables the TXFIFO Half
DMA Request.
0 = Disabled
1 = Enabled
TEDEN
Bit 14
TEDEN—Enables/Disables the TXFIFO
Empty DMA Request.
0 = Disabled
1 = Enabled
RFDEN
Bit 13
RFDEN—Enables/Disables the RXFIFO Full
DMA Request.
0 = Disabled
1 = Enabled
RHDEN
Bit 12
RHDEN—Enables/Disables the RXFIFO Half
DMA Request.
0 = Disabled
1 = Enabled
Reserved
Bits 11–8
Reserved—These bits are reserved and should read 0.
THDMA
Bit 7
TXFIFO Half Status—Indicates when the
transmit FIFO is half-empty.
0 = There are less than 4 empty slots in the TXFIFO
1 = There are at least 4 empty slots in the TXFIFO
TEDMA
Bit 6
TXFIFO Empty Status—Indicates when the
transmit FIFO is empty.
0 = There is at least one data word in the TXFIFO
1 = The TXFIFO is empty, however data shifting may still be
on-going. To be sure no data transaction is on-going,
read the XCH bit in the Control Registers.
RFDMA
Bit 5
RXFIFO Full Status—Indicates when the
receive FIFO is full.
0 = There are less than 8 data words in the RXFIFO
1 = There are 8 data words in the RXFIFO
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
15-13
Programming Model
Table 15-10. SPI 1 DMA Control Register Description (continued)
Name
Description
Settings
RHDMA
Bit 4
RXFIFO Half Status—Indicates when the
receive FIFO is half-full.
0 = There are less than 4 data words in the RXFIFO
1 = There are at least 4 data words in the RXFIFO
Reserved
Bits 3–0
Reserved—These bits are reserved and should read 0.
15.3.8 Soft Reset Register
The SPI soft reset register allows the user to reset the SPI module.
RESETREG1
Addr
0x0021301C
SPI 1 Soft Reset Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
START
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 15-11. SPI 1 Soft Reset Register Description
Name
Description
Reserved
Bits 31–1
Reserved—These bits are reserved and should read 0.
START
Bit 0
Start—Executes soft reset.
Settings
0 = No soft reset
1 = Soft reset
MC9328MXS Reference Manual, Rev. 1.1
15-14
Freescale Semiconductor
Chapter 16
LCD Controller
16.1 Introduction
The Liquid Crystal Display Controller (LCDC) provides display data for external gray-scale or color LCD panels.
The LCDC is capable of supporting black-and-white, gray-scale, passive-matrix color, and active-matrix color
LCD panels.
16.2 Features
•
Support for single (non-split) screen monochrome/color LCD panels and self-refresh type LCD panels
•
16 simultaneous gray-scale levels from a palette of 16 for monochrome display
•
Support for:
— 4/8/12 bits per pixel (bpp) for passive color panel
— 4/8/12/16 bpp for TFT panel
— Up to 256 colors out of a palette of 4096 colors for an 8 bpp display and 4096 colors for a 12 bpp display
— True 64K colors for 16 bpp
— Additional support details are shown in Table 16-1
Table 16-1. Supported Panel Characteristics
Panel Type
Monochrome
Bit/Pixel
Panel Interface (Bits)
Number of Gray Level/Color
1
1, 2, 4, 8
Black-and-white
2
1, 2, 4, 8
4
4
1, 2, 4, 8
16
CSTN
4,8,12
8
16, 256, 4096
TFT
4, 8
16
16, 256
12, 16
12, 16
4096, 64K
•
Standard panel interface for common LCD drivers
•
Panel interface of 16-, 12-, 8-, 4-, 2-, and 1-bit-wide LCD panel data bus for monochrome or color panels
•
For 4 bpp and 8 bpp a palette table is used for re-mapping of data from memory, independent of type of
panel used. For the 1 bpp, 2 bpp, 12 bpp and 16 bpp the palette table is by-passed.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-1
LCDC Operation
•
Direct interface to active color panels (TFT) such as NEC and Sharp
•
Dedicated signals facilitate interface to Sharp HR-TFT panels such as 320 × 240
•
Hardware-generated cursor with blink, color, and size programmability
•
Logical operation between color hardware cursor and background
•
Hardware panning (soft horizontal scrolling)
•
8-bit pulse-width modulator for software contrast control
AHB
Interrupt
Pan
FIFO
(Line Buffer)
DMA
Shift
4/8 Bit Color
1 bpp
2 bpp
4 bpp
16-Bit Active Color
Palette Color Look
Up Table
16-Bit Hardware
Cursor
Passive
4 bpp (Gray)
Interface
FRC Color
TFT
H/W Cursor
Non-Color
FRC Gray
Interface Buffer
Interface Logic
LCDC_CLK
(PerCLK2)
LD [15:0]
FLM/VSYNC
LP/HSYNC
LSCLK
ACD/OE
PS
CLS
REV
SPL_SPR
CONTRAST
Figure 16-1. LCDC Block Diagram
16.3 LCDC Operation
16.3.1 LCD Screen Format
The number of pixels forming the screen width and screen height of the LCD panel are software programmable.
Figure 16-2 shows the relationship between the screen size and memory window.
MC9328MXS Reference Manual, Rev. 1.1
16-2
Freescale Semiconductor
LCDC Operation
Virtual Page Width (VPW)
Screen Starting Address (SSA)
Screen Height (YMAX)
Virtual Page Height (VPH)
Screen Width (XMAX)
Figure 16-2. LCD Screen Format
The Screen Width (XMAX) and Screen Height (YMAX) parameters specify the LCD panel size. The LCDC will
start scanning the display memory at the location pointed to by the Screen Starting Address (SSA) register,
represented by the shaded area in Figure 16-2, for display on the LCD panel.
The maximum page width is specified by the Virtual Page Width (VPW) parameter. Virtual Page Height (VPH)
does not affect the LCDC and is limited only by memory size. By changing the SSA register, a screen-sized
window can be vertically or horizontally scrolled (panned) anywhere inside the virtual page boundaries. The
software must control the starting address in the SSA properly so that the scanning logic’s System Memory Pointer
(SMP) stays within the VPW and VPH limits to prevent the display of strange artifacts on the screen.
VPH is used by the programmer only for boundary checks. There is no VPH parameter internal to the LCDC.
VPW is used in calculating the RAM starting address representing the beginning of each displayed line. SSA sets
the address of data for the first line of a frame. For each subsequent line, VPW is added to an accumulation
initialized by the SSA to yield the starting address of that line.
16.3.2 Panning
Panning Offset (POS) is expressed in bits, not pixels, so when operating in any mode other than 1 bpp, only even
pixel boundaries are valid. In 12 bpp mode, the pixels are aligned to 16-bit boundaries, and POS also must align to
these boundaries.
SSA and POS are located in isolated registers and are double buffered because they are dynamic parameters likely
to change while the LCDC is running. New values of SSA and POS do not take effect until the beginning of the
next frame. A typical panning algorithm includes an interrupt at the beginning of the frame. In the interrupt service
routine, POS and/or SSA are updated (the old values are internally latched). The updates take effect on the next
frame.
16.3.3 Display Data Mapping
The LCDC supports 1/2/4 bpp in monochrome mode and 4/8/12/16 bpp in color mode. System memory data
mapping in 2/4/8/12/16 bpp modes is shown in Figure 16-4 and in Figure 16-5.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-3
LCDC Operation
NOTE:
In 12 bpp mode, 16 bits of memory are used for each set of 12 bits, leaving 4 bits
unused. In 16 bpp mode, all 16 bits are used. Refer to Figure 16-5 and Table 16-7.
P0
P1
P2
P3
LCD Screen
Figure 16-3. Pixel Location on Display Screen
MC9328MXS Reference Manual, Rev. 1.1
16-4
Freescale Semiconductor
LCDC Operation
1 bpp Mode, Little Endian
1 bpp Mode, Big Endian
Byte
Address
Sample Bit-to-Pixel Mapping
3
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
P24
P25
P26
P27
P28
P29
P30
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
P22
P23
1
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
P8
P9
P10
P11
P12
P13
P14
P15
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P0
P1
P2
P3
P4
P5
P6
P7
P17
P18
P19
P20
P21
Sample Bit-to-Pixel Mapping
0
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
1
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
P14
P15
2
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
P16
P17
P18
P19
P20
P21
P22
P23
3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P24
P25
P26
P27
P28
P29
P30
P31
P31
2
P16
Byte
Address
P0
P1
P8
P9
2 bpp Mode, Little Endian
Sample Bit-to-Pixel Mapping
3
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
P13
P14
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
1
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
P9
P4
0
Bit 7
P10
P5
Bit 6
Bit 5
P0
Bit 4
Bit 3
P11
P5
P12
P6
P13
P7
Sample Bit-to-Pixel Mapping
0
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
1
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
2
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
P0
P11
P6
P1
P10
P4
Byte
Address
P15
2
P8
P3
2 bpp Mode, Big Endian
Byte
Address
P12
P2
Bit 8
P4
P7
Bit 2
Bit 1
P2
Bit 0
P1
P5
P8
3
P3
Bit 7
Bit 6
Bit 5
P3
P6
P9
P12
4 bpp Mode, Little Endian
P2
P7
P10
Bit 4
Bit 3
P13
Bit 8
P11
Bit 2
Bit 1
P14
Bit 0
P15
4 bpp Mode, Big Endian
Byte
Address
Sample Bit-to-Pixel Mapping
Byte
Address
Sample Bit-to-Pixel Mapping
3
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
0
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
1
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
2
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
P6
P7
P0
2
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
1
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
P4
P5
P2
0
Bit 7
Bit 6
Bit 5
P2
Bit 8
P3
Bit 4
Bit 3
Bit 2
P0
Bit 1
P1
P3
P4
Bit 0
3
Bit 7
P1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
P6
8 bpp Mode, Little Endian
Bit 8
P5
Bit 1
Bit 0
P7
8 bpp Mode, Big Endian
Byte
Address
Sample Bit-to-Pixel Mapping
Byte
Address
Sample Bit-to-Pixel Mapping
3
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
0
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
1
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
2
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
P3
P0
2
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
1
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
P2
P1
Bit 8
P1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 8
P2
Bit 2
Bit 1
Bit 0
3
Bit 7
Bit 6
Bit 5
P0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P3
P0 = Red0Green0Blue0
P1 = Red1Green1Blue1
Figure 16-4. Display Data Mapping, 1/2/4/8 bpp Modes
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-5
LCDC Operation
Table 16-2. Display Mapping in 12 bpp, CSTN Panel, Little Endian
16 bpp Mode, Little Endian
Byte
Address
3
2
Sample Bit-to-Pixel Mapping
Bit 31
Bit 30
Red1 [4]
Red1 [3]
Bit 29
Bit 23
Bit 22
Bit 28
Bit 27
Bit 26
Bit 21
Bit 20
Bit 19
Bit 18
Green1 [2] Green1 [1] Green1 [0] Blue1 [4] Blue1 [3] Blue1 [2]
1
0
Bit 15
Bit 14
Red0 [4]
Red0 [3]
Bit 7
Bit 6
Bit 25
Bit 24
Red1 [2] Red1 [1] Red1 [0] Green1 [5] Green1 [4] Green1 [3]
Bit 13
Bit 12
Bit 11
Bit 17
Bit 16
Blue1 [1]
Blue1 [0]
Bit 9
Bit 8
Bit 10
Red0 [2] Red0 [1] Red0 [0] Green0 [5] Green0 [4] Green0 [3]
Bit 5
Bit 4
Bit 3
Bit 2
Green0 [2] Green0 [1] Green0 [0] Blue0 [4] Blue0 [3] Blue0 [2]
Bit 1
Bit 0
Blue0 [1]
Blue0 [0]
Bit 25
Bit 24
16 bpp Mode, Big Endian
Byte
Address
0
1
Sample Bit-to-Pixel Mapping
Bit 31
Bit 30
Red0 [4]
Red0 [3]
Bit 29
Bit 23
Bit 22
Bit 28
Bit 27
Bit 26
Red0 [2] Red0 [1] Red0 [0] Green0 [5] Green0 [4] Green0 [3]
Bit 21
Bit 20
Bit 19
Bit 18
Green0 [2] Green0 [1] Green0 [0] Blue0 [4] Blue0 [3] Blue0 [2]
2
3
Bit 15
Bit 14
Red1 [4]
Red1 [3]
Bit 13
Bit 7
Bit 6
Bit 12
Bit 11
Bit 17
Bit 16
Blue0 [1]
Blue0 [0]
Bit 9
Bit 8
Bit 10
Red1 [2] Red1 [1] Red1 [0] Green1 [5] Green1 [4] Green1 [3]
Bit 5
Bit 4
Bit 3
Bit 2
Green1 [2] Green1 [1] Green1 [0] Blue1 [4] Blue1 [3] Blue1 [2]
Bit 1
Bit 0
Blue1 [1]
Blue1 [0]
Table 16-3. Display Mapping in 12 bpp, CSTN Panel, Little Endian
Byte Address
3
2
1
0
Bit-to-Pixel Mapping
B31
B30
B29
B28
B27
B26
B25
B24
–
–
–
–
R13
R12
R11
RI0
B23
B22
B21
B20
B19
B18
B17
B16
G13
G12
G11
GI0
B13
B12
B11
BI0
B15
B14
B13
B12
B11
B10
B9
B8
–
–
–
–
R03
R02
R01
RO0
B7
B6
B5
B4
B3
B2
B1
BO
GO3
G02
G01
GO0
BO3
B02
B01
BO0
PO = RGBo P1= RGB1
MC9328MXS Reference Manual, Rev. 1.1
16-6
Freescale Semiconductor
LCDC Operation
:
Table 16-4. Display Mapping in 12 bpp, CSTN Panel, Big Endian
Byte Address
0
1
2
3
Bit-to-Pixel Mapping
B31
B30
B29
B28
B27
B26
B25
B24
–
–
–
–
R03
R02
R01
RO0
B23
B22
B21
B20
B19
B18
B17
B16
GO3
G02
G01
GO0
BO3
B02
B01
BO0
B15
B14
B13
B12
B11
B10
B9
B8
–
–
–
–
R13
R12
R11
RI0
B7
B6
B5
B4
B3
B2
B1
BO
G13
G12
G11
GI0
B13
B12
B11
BI0
PO = RGBo P1= RGB1
Figure 16-5. Display Data Mapping, 16 bpp Mode
16.3.4 Black-and-White Operation
The 1 bpp mode is also known as black-and-white mode because each pixel is always either fully on or fully off.
16.3.5 Gray-Scale Operation
The LCDC generates a maximum of 16 gray levels. These gray levels are defined by 2 or 4 bits of display data for
each pixel. Using 2 bpp, the LCDC displays 4 shades of gray, and using 4 bpp, the LCDC displays all 16 shades.
The shades of gray are obtained by controlling the number of frames in which the pixel is “on” over a period of 16
frames. This method is known as Frame Rate Control (FRC). For more information on FRC, see Section 16.3.7,
“Frame Rate Modulation Control (FRC).”
The use of the mapping RAM is shown in Figure 16-6. When using 2 bpp, the 2-bit code is mapped to one of 4 gray
levels, and when using 4 bpp, the 4-bit code is mapped to one of 16 gray levels. Because crystal formulations and
driving voltages vary, the visual gray effect may or may not be linearly related to the frame rate. A logarithmic
scale such as 0, 1/4, 1/2 and 1 might be more pleasing than a linearly spaced scale such as 0, 5/16, 11/16 and 1 for
certain graphics.
Figure 16-6 illustrates gray-scale pixel generation. The flexible mapping scheme allows the user to optimize the
visual effect for a specific panel or application.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-7
LCDC Operation
7 6 5 4 3 2 1 0
1 0
2 bpp Data
1 1 0 0
4 bpp Data
- - - - - - - - 1 1 1 0
FRC
1
To Panel
Figure 16-6. Gray-Scale Pixel Generation
16.3.6 Color Generation
The value corresponding to each color pixel on the screen is represented by a 4-, 8-, 12- or 16-bit code in the
display memory.
For the 4- and 8- bit modes use the LCDC’s color mapping RAM to map the data to a 12-bit RGB code. For passive
matrix color displays, 4-bit and 8-bit mode, the 12-bit RGB code from the mapping RAM is output to the FRC
blocks that independently process the code corresponding to the red, green, and blue components of each pixel to
generate the required shade and intensity.
For active matrix display, the 12-bit output from the mapping RAM is output to the panel.
For 12-bit mode for passive matrix color display, the mapping RAM is by-passed and output directly to the FRC
block.
In 16-bit mode, pixel data is simply moved from display memory to the 16-bit LCDC output bus.
For active matrix displays, the 16-bit RGB code from the mapping RAM is output to the panel. For passive color
display, the maximum color depth is 12-bit and 16-bit color is not supported.
Figure 16-7 and Figure 16-8 on page 16-10 illustrate passive matrix and active matrix color pixel generation.
MC9328MXS Reference Manual, Rev. 1.1
16-8
Freescale Semiconductor
LCDC Operation
7 6 5 4 3 2 1 0
1 0 1 1
4 bpp Data
1 1 0 0 1 1 0 1
8 bpp Data
0 1 0 1 1 1 0 0 1 1 0 1 1 1 0 1
R
G
12 bpp Data
B
Color
RAM
Inside
LCDC
256 rows
- - - - - - - - 1 1 1 0
FRC
FRC
FRC
1 0 1
To Panel
Figure 16-7. Passive Matrix Color Pixel Generation
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-9
LCDC Operation
.
7 6 5 4 3 2 1 0
1 0 1 1
4 bpp Data
1 1 0 0 1 1 0 1
8 bpp Data
0 1 0 1 1 1 0 0 1 1 0 1 1 1 0 1
R
G
12 bpp/16 bpp Data
B
Color
RAM
Inside
LCDC
256 rows
1 1 1 1 0 0 1 1 1 1 0 0
1 1 1 1 0 0 1 1 1 1 0 0
To Panel
Figure 16-8. Active Matrix Color Pixel Generation
16.3.7 Frame Rate Modulation Control (FRC)
Circuitry inside the LCDC generates intermediate gray-scale colors on the panel by adjusting the density of zeroes
and ones that appear over the frames. The LCDC can generate 16 simultaneous gray-scale levels.
Table 16-5. Gray Palette Density
Gray Code
(Hexadecimal)
Density
Density
(Decimal)
0
0
0
1
1/8
0.125
2
1/5
0.2
3
1/4
0.25
4
1/3
0.333
5
2/5
0.4
6
4/9
0.444
7
1/2
0.5
8
5/9
0.555
9
3/5
0.6
A
2/3
0.666
MC9328MXS Reference Manual, Rev. 1.1
16-10
Freescale Semiconductor
LCDC Operation
Table 16-5. Gray Palette Density (continued)
Gray Code
(Hexadecimal)
Density
Density
(Decimal)
B
3/4
0.75
C
4/5
0.8
D
7/8
0.875
E
14/15
0.933
F
1
1
Note:
Overbars indicate repeating decimal numbers.
16.3.8 Panel Interface Signals and Timing
The LCDC continuously provides pixel data to the LCD panel via the LCD panel interface. Panel interface signals
are illustrated in Figure 16-9 on page 16-11.
LD [15:0]
FLM/VSYNC
LP/HSYNC
LSCLK
ACD/OE
PS
CLS
REV
SPL_SPR
CONTRAST
LCD Controller
Figure 16-9. LCDC Interface Signals
The format, timing, and polarity of the panel interface signals are programmable. There are two basic modes,
passive and active, selected by the TFT register bit. The user must also select either grayscale mode or color mode.
SPL_SPR, PS, CLS, and REV are additional interface signals required for Sharp HR-TFT panels.
16.3.8.1 Pin Configuration for LCDC
Figure 16-9 shows the signals used for the LCDC. These pins are multiplexed with other functions on the device,
and must be configured for LCDC operation before they can be used.
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 25.5.1, “Data Direction Registers,” on
page 25-8 for details.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-11
LCDC Operation
Table 16-6. Pin Configuration
Pin
Setting
LD [15:0]
FLM/VSYNC
LP/HSYNC
LSCLK
ACD/OE
CONTRAST
SPL_SPR
PS
CLS
REV
Configuration Procedure
Primary function of
GPIO Port D [30:15]
1. Clear bits [30:15] of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [14]
1. Clear bit 14 of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [13]
1. Clear bit 13 of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [6]
1. Clear bit 6 of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [12]
1. Clear bit 12 of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [11]
1. Clear bit 11 of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [10]
1. Clear bit 10 of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [9]
1. Clear bit 9 of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [8]
1. Clear bit 8 of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [7]
1. Clear bit 7 of Port D GPIO In Use Register (GIUS_D)
2. Clear bits [30:15] of Port D General Purpose Register (GPR_D)
2. Clear bit 14 of Port D General Purpose Register (GPR_D)
2. Clear bit 13 of Port D General Purpose Register (GPR_D)
2. Clear bit 6 of Port D General Purpose Register (GPR_D)
2. Clear bit 12 of Port D General Purpose Register (GPR_D)
2. Clear bit 11 of Port D General Purpose Register (GPR_D)
2. Clear bit 10 of Port D General Purpose Register (GPR_D)
2. Clear bit 9 of Port D General Purpose Register (GPR_D)
2. Clear bit 8 of Port D General Purpose Register (GPR_D)
2. Clear bit 7 of Port D General Purpose Register (GPR_D)
16.3.8.2 Passive Matrix Panel Interface Signals
Figure 16-10 shows the LCD interface timing for monochrome panels and Figure 16-11 shows the LCD interface
timing for passive matrix color panels. Signal polarities are shown positive, however it can be reversed by clearing
the bits in the Panel Configuration Register (PCR). The data bus timing for passive panels is controlled by the shift
clock (LSCLK), line pulse (LP), first line marker (FLM), alternate crystal direction (ACD), and line data (LD)
signals. Operation of the panel interface is accomplished in the following steps:
1. LSCLK clocks the pixel data into the display driver’s internal shift register.
2. LP signifies the end of the current line of serial data and latches the shifted pixel data into a wide
latch.
3. FLM marks the first line of the displayed page. The LD (and the associated LP), enclosed by the
FLM signal, marks the first line of the current frame.
4. ACD toggles after a pre-programmed number of FLM pulses. This signal refreshes the LCD panel.
NOTE:
The LD bus width is programmable to 1, 2, 4, or 8 bits in monochrome mode (the
COLOR bit in the Panel Configuration register is set to 0). Data is justified to the
least significant bits of the LD [15:0] bus. Passive color displays use a fixed 2-2/3
pixels of data per 8-bit vector as shown in Figure 16-11 on page 16-13.
MC9328MXS Reference Manual, Rev. 1.1
16-12
Freescale Semiconductor
LCDC Operation
FLM
LP
LINE 1
LINE 2
LINE 3
LINE 4
LINE n
LINE 1
LP
1
2
3
59
60
m/4-1
m/4
LSCLK
LD0
[0,0]
[0,4]
[0,8]
[0,232]
[0,236]
[0,m-8]
[0,m-4]
LD1
[0,1]
[0,5]
[0,9]
[0,233]
[0,237]
[0,m-7]
[0,m-3]
LD2
[0,2]
[0,6]
[0,10]
[0,234]
[0,238]
[0,m-6]
[0,m-2]
LD3
[0,3]
[0,7]
[0,11]
[0,235]
[0,239]
[0,m-5]
[0,m-1]
Figure 16-10. LCDC Interface Timing for 4-bit Data Width Gray-Scale Panels
FLM
LP
LINE 1
LINE 2
LINE 3
LINE 4
LINE n
LINE 1
LP
1
2
3
89
90
3*m/8-1 3*m/8
LD7
R[0,0]
B[0,2]
G[0,5]
B[0,234] G[0,237]
B[0,m-6] G[0,m-3]
LD6
G[0,0]
R[0,3]
B[0,5]
R[0,235] B[0,237]
R[0,m-5] B[0,m-3]
LD5
B[0,0]
G[0,3]
R[0,6]
G[0,235] R[0,238]
G[0,m-5] R[0,m-2]
LD4
R[0,1]
B[0,3]
G[0,6]
B[0,235] G[0,238]
B[0,m-5] G[0,m-2]
LD3
G[0,1]
R[0,4]
B[0,6]
R[0,236] B[0,238]
R[0,m-4] B[0,m-2]
LD2
B[0,1]
G[0,4]
R[0,7]
G[0,236] R[0,239]
G[0,m-4] R[0,m-1]
LD1
R[0,2]
B[0,4]
G[0,7]
B[0,236] G[0,239]
B[0,m-4] G[0,m-1]
LD0
G[0,2]
R[0,5]
B[0,7]
R[0,237] B[0,239]
R[0,m-3] B[0,m-1]
LSCLK
Figure 16-11. LCDC Interface Timing for 8-Bit Data Passive Matrix Color Panels
16.3.8.3 Passive Panel Interface Timing
Figure 16-12 on page 16-14 shows the horizontal timing (timing of one line), including both the line pulse (LP) and
the data. The width of LP and delays both before and after LP are programmable. The parameters used for panel
interface timing are:
•
•
•
•
XMAX (X size) defines the number of pixels per line. XMAX is the total number of pixels per line.
H_WAIT_1 defines the delay from the end of data output to the beginning of LP.
H_WIDTH (horizontal sync pulse width) defines the width of the FLM pulse, and H_WIDTH must be at
least 1.
H_WAIT_2 defines the delay from the end of LP to the beginning of data output.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-13
LCDC Operation
NOTE:
All parameters are defined in unit of pixel clock period, unless stated otherwise.
16.3.9 8 bpp Mode Color STN Panel
Hwait2+2
Hwait2+2
VSYN
(last line)
Hwidth
4
Hwait1
XMAX
(first line)
Hwidth
HSYN
LSCLK
Ts
LD[15:0]
Figure 16-12. Horizontal Sync Pulse Timing in Passive Mode
PASS_FRAME_WAIT
YMAX
(lines)
FLM
LP
LSCLK
End of last line
Start of frame
Figure 16-13. Vertical Sync Pulse Timing Passive, Color, (Non-TFT) Mode
16.3.9.1 Active Matrix Panel Interface Signals
Figure 16-14 on page 16-16 shows the LCD interface timing for an active matrix color TFT panel. In this figure
signals are shown with negative polarity (FLMPOL=1, LPPOL=1, CLKPOL=0, OEPOL=1). In TFT mode, the
LSCLK is automatically inverted. The panel interface timing for active matrix panels is sometimes referred to as a
“digital CRT” and is controlled by the shift clock (LSCLK), horizontal sync pulse (HSYNC, the LP pin in passive
mode), vertical sync pulse (VSYNC, the FLM pin in passive mode), output enable (OE, the ACD pin in passive
mode), and line data (LD) signals. The sequence of events for active matrix interface timing is:
1. LSCLK latches data into the panel on its negative edge (when positive polarity is selected). In active
mode, LSCLK runs continuously.
MC9328MXS Reference Manual, Rev. 1.1
16-14
Freescale Semiconductor
LCDC Operation
2. HSYNC causes the panel to start a new line.
3. VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
4. OE functions as an output enable signal to the CRT. This output enable signal is similar to the
blanking output in a CRT and enables the data to be shifted onto the display. When disabled, the
data is invalid and the trace is off.
In 4- and 8-bit mode, the LD [15:12] bits define red, the LD [10:7] bits define green, and the LD [4:1] bits define
blue. In 16-bit mode, the LD [15:11] bits define red, the LD [10:5] bits define green, and the LD [4:0] bits define
blue.
The actual TFT color channel assignments are shown in Table 16-7. In 4 bpp and 8 bpp, bits LD11, LD6, LD5 and
LD0 are fixed at 0.
Table 16-7. TFT Color Channel Assignments
LD
15
LD
14
LD
13
LD
12
LD
11
LD
10
LD
9
LD
8
LD
7
LD
6
LD
5
LD
4
LD
3
LD
2
LD
1
LD
0
4 bpp
R3
R2
R1
R0
–
G3
G2
G1
G0
–
–
B3
B2
B1
B0
–
8 bpp
R3
R2
R1
R0
–
G3
G2
G1
G0
–
–
B3
B2
B1
B0
–
12 bpp
R3
R2
R1
R0
–
G3
G2
G1
G0
–
–
B3
B2
B1
B0
–
16 bpp
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-15
LCDC Operation
VSYNC
HSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n
LINE 1
HSYNC
OE
1
2
3
239
240
m-1
m
LD15
R4[0,0]
R4[0,1]
R4[0,2]
R4[0,238] R4[0,239]
R4[0,m-2] R4[0,m-1]
LD14
R3[0,0]
R3[0,1]
R3[0,2]
R3[0,238] R3[0,239]
R3[0,m-2] R3[0,m-1]
LD13
R2[0,0]
R2[0,1]
R2[0,2]
R2[0,238] R2[0,239]
R2[0,m-2] R2[0,m-1]
LD12
R1[0,0]
R1[0,1]
R1[0,2]
R1[0,238] R1[0,239]
R1[0,m-2] R1[0,m-1]
LD11
R0[0,0]
R0[0,1]
R0[0,2]
R0[0,238] R0[0,239]
R0[0,m-2] R0[0,m-1]
LD10
G5[0,0]
G5[0,1]
G5[0,2]
G5[0,238] G5[0,239]
G5[0,m-2] G5[0,m-1]
LD9
G4[0,0]
G4[0,1]
G4[0,2]
G4[0,238] G4[0,239]
G4[0,m-2] G4[0,m-1]
LD8
G3[0,0]
G3[0,1]
G3[0,2]
G3[0,238] G3[0,239]
G3[0,m-2] G3[0,m-1]
LD7
G2[0,0]
G2[0,1]
G2[0,2]
G2[0,238] G2[0,239]
G2[0,m-2] G2[0,m-1]
LD6
G1[0,0]
G1[0,1]
G1[0,2]
G1[0,238] G1[0,239]
G1[0,m-2] G1[0,m-1]
LD5
G0[0,0]
G0[0,1]
G0[0,2]
G0[0,238] G0[0,239]
G0[0,m-2] G0[0,m-1]
LD4
B4[0,0]
B4[0,1]
B4[0,2]
B4[0,238] B4[0,239]
B4[0,m-2] B4[0,m-1]
LD3
B3[0,0]
B3[0,1]
B3[0,2]
B3[0,238] B3[0,239]
B3[0,m-2] B3[0,m-1]
LD2
B2[0,0]
B2[0,1]
B2[0,2]
B2[0,238] B2[0,239]
B2[0,m-2] B2[0,m-1]
LD1
B1[0,0]
B1[0,1]
B1[0,2]
B1[0,238] B1[0,239]
B1[0,m-2] B1[0,m-1]
LD0
B0[0,0]
B0[0,1]
B0[0,2]
B0[0,238] B0[0,239]
B0[0,m-2] B0[0,m-1]
LSCLK
Figure 16-14. LCDC Interface Timing for Active Matrix Color Panels
16.3.9.2 Active Panel Interface Timing
Figure 16-15 on page 16-17 shows the horizontal timing (timing of one line), including both the horizontal sync
pulse and the data. The width of HSYNC and delays both before and after HSYNC are programmable. The timing
signal parameters are defined as follows:
•
H_WIDTH defines the width of the HSYNC pulse and must be at least 1.
•
H_WAIT_2 defines the delay from the end of HSYNC to the beginning of the OE pulse.
•
H_WAIT_1 defines the delay from end of OE to the beginning of the HSYNC pulse.
•
XMAX defines the (total) number of pixels per line.
NOTE:
All parameters are defined in pixel periods, not LSCLK periods.
MC9328MXS Reference Manual, Rev. 1.1
16-16
Freescale Semiconductor
LCDC Operation
H_WIDTH
H_WAIT_2
XMAX
H_WAIT_1
LSCLK
HSYNC
OE
DATA
VSYNC
Figure 16-15. Horizontal Sync Pulse Timing in TFT Mode
Figure 16-16 shows the vertical timing (timing of one frame). The delay from the end of one frame until the
beginning of the next is programmable. The memory timing signal parameters are:
•
V_WAIT_1 is a delay measured in lines. For V_WAIT_1= 1 there is a delay of one HSYNC
(time = one line period) before VSYNC. The HSYNC pulse is output during the V_WAIT_1 delay.
•
For V_WIDTH (vertical sync pulse width) = 0, VSYNC encloses one HSYNC pulse.
For V_WIDTH = 2, VSYNC encloses two HSYNC pulses.
•
V_WAIT_2 is a delay measured in lines. For V_WAIT_2 = 1, there is a delay of one HSYNC
(time = one line period) after VSYNC. The HSYNC pulse is output during the V_WAIT_2 delay.
End of frame
V_WIDTH
(lines)
Beginning of frame
YMAX
VSYNC
HSYNC
OE
V_WAIT_1
V_WAIT_2
Figure 16-16. Vertical Sync Pulse Timing TFT Mode
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-17
Programming Model
16.4 Programming Model
The LCDC memory space contains fifteen 32-bit registers for display parameters, a read-only status register, and a
256 x 12 Color Mapping RAM. The color mapping RAM is physically located inside the Palette Lookup Table
module.
Table 16-8 summarizes these registers and their addresses. Only WORD access is supported. Byte and halfword
access is undefined.
Table 16-8. LCDC Register Memory Map
Description
Name
Address
Screen Start Address Register
SSA
0x00205000
Size Register
SIZE
0x00205004
Virtual Page Width Register
VPW
0x00205008
LCD Cursor Position Register
CPOS
0x0020500C
LCD Cursor Width Height and Blink Register
LCWHB
0x00205010
LCD Color Cursor Mapping Register
LCHCC
0x00205014
Panel Configuration Register
PCR
0x00205018
Horizontal Configuration Register
HCR
0x0020501C
Vertical Configuration Register
VCR
0x00205020
Panning Offset Register
POS
0x00205024
Sharp Configuration 1 Register
LSCR1
0x00205028
PWM Contrast Control Register
PWMR
0x0020502C
DMA Control Register
DMACR
0x00205030
Refresh Mode Control Register
RMCR
0x00205034
Interrupt Configuration Register
LCDICR
0x00205038
Interrupt Status Register
LCDISR
0x00205040
Figure 16-9 on page 16-19 provides a quick overview of the fields of all the registers. There are intentional gaps
between the addresses for the read-write register section and the status register, and between the status register and
the mapping RAM.
MC9328MXS Reference Manual, Rev. 1.1
16-18
Freescale Semiconductor
Programming Model
Table 16-9. Register Memory Mapping Summary
Register Register
Name
Location
Register Bits
31
(15)
30
(14)
29
28
27
26
(13) (12) (11) (10)
25
(9)
24
(8)
23
(7)
22
(6)
21 20
(5) (4)
19
(3)
18
(2)
17
(1)
16
(0)
Screen Start Address - SSA
SSA
0x00205000
Screen Start Address - SSA
Screen Width - XMAX
SIZE
0x00205004
Screen Height - YMAX
VPW
0x00205008
Virtual Page Width - VPW
CC1
CPOS
CC0
OP
Cursor X Position - CXP
0x0020500C
Cursor Y Position - CYP
BK_EN
LCWHB
Cursor Width - CW
Cursor Height - CH
0x00205010
BD
LCHCC
0x00205014
Cursor Red - CUR_COL_R
TFT
PCR
COLOR
Cursor Green - CUR_COL_G
Bus Width
PBSIZ
Bits Per Pixel
BPIX
PIX
POL
FLM
POL
Cursor Blue - CUR_COL_B
END_
CLK OE SCLK END_ BYTE_
REV _VS
POL POL IDLE SEL SWAP
LP
POL
0x00205018
ACD SEL
SCLK SHARP
SEL
Crystal Direction Toggle - ACD
Pixel Clock Divider - PCD
Horizontal Sync Width - H_WIDTH
HCR
0x0020501C
Horizontal Wait 1 - H_WAIT_1
Horizontal Wait 2 - H_WAIT_2
Vertical Sync Width - V_WIDTH
VCR
0x00205020
Vertical Wait 1 - V_WAIT_1
POS
Vertical Wait 2 - V_WAIT_2
0x00205024
Panning Offset - POS
PS_RISE_DELAY
LSCR1
CLS_RISE_DELAY
0x00205028
REV_TOGGLE_DELAY
Gray 1
Gray 2
CLS High Width
PWMR
0x0020502C
LD
MSK
CC
SCR1 SCR0 _EN
Pulse Width - PW
HM
BURST
DMACR
0x00205030
TM
RMCR
0x00205034
LCDICR
0x00205038
INT
SYN
LCDISR
0x00205040
UDR ERR
_ERR _RES
LCDC
_EN
SELF
_REF
INT
CON
EOF
BOF
0x00205800
First RAM Location(R [3:0], G [3:0], B [3:0])
0x00205BFC
Last RAM Location(R [3:0], G [3:0], B [3:0])
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-19
Programming Model
16.4.1 Screen Start Address Register
The Screen Start Address Register specifies the start address of the LCD screen. See Figure 16-2.
SSA
BIT
Addr
0x00205000
Screen Start Address Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SSA
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSA
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-10. Screen Start Address Register Description
Name
Description
SSA
Bits 31–2
Screen Start Address of LCD Panel—Holds pixel data for a new frame from the SSA address. This field
must start at a location that enables a complete picture to be stored in a 4 Mbyte memory boundary (A [21:0]).
A [31:22] has a fixed value for a picture’s image.
Reserved
Bits 1–0
Reserved—These bits are reserved and should read 0.
MC9328MXS Reference Manual, Rev. 1.1
16-20
Freescale Semiconductor
Programming Model
16.4.2 Size Register
The Size Register defines the height and width of the LCD screen.
SIZE
BIT
Addr
0x00205004
Size Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
XMAX
TYPE
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
YMAX
TYPE
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-11. Size Register Description
Name
Description
Reserved
Bits 31–26
Reserved—These bits are reserved and should read 0.
XMAX
Bits 25–20
Screen Width Divided by 16—Holds screen x-axis size, divided by 16. For black-and-white panels (1 bpp),
XMAX [20] is ignored, forcing the x-axis of the screen size to be a multiple of 32 pixels/line.
Reserved
Bits 19–9
Reserved—These bits are reserved and should read 0.
YMAX
Bits 8–0
Screen Height—Specifies the height of the LCD panel in terms of pixels or lines. The lines are numbered
from 1 to YMAX for a total of YMAX lines.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-21
Programming Model
16.4.3 Virtual Page Width Register
The Virtual Page Width Register defines the width of the virtual page for the LCD panel. See Figure 16-2 on
page 16-3.
VPW
Addr
0x00205008
Virtual Page Width Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
VPW
TYPE
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-12. Virtual Page Width Register Description
Name
Description
Reserved
Bits 31–10
Reserved—These bits are reserved and should read 0.
VPW
Bits 9–0
Virtual Page Width—Defines the virtual page width of the LCD panel. The VPW bits represent the number of
32-bit words required to hold the data for one virtual line. VPW is used in calculating the starting address
representing the beginning of each displayed line.
MC9328MXS Reference Manual, Rev. 1.1
16-22
Freescale Semiconductor
Programming Model
16.4.4 Panel Configuration Register
The Panel Configuration Register defines all of the properties of the LCD screen.
PCR
Addr
0x00205018
Panel Configuration Register
BIT
31
30
TFT
COLOR
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
TYPE
29
28
27
PBSIZ
26
25
24
23
22
21
20
19
18
17
16
PIX
POL
FLM
POL
LP
POL
CLK
POL
OE
POL
SCLK
IDLE
END_
SEL
SWAP_SEL
REV_
VS
rw
rw
rw
rw
rw
rw
rw
r
r
rw
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
BPIX
RESET
0x0000
BIT
15
14
13
12
ACD
SEL
TYPE
11
10
9
8
ACD
7
6
SCLK
SEL
SHARP
PCD
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-13. Panel Configuration Register Description
Name
Description
Settings
TFT
Bit 31
Interfaces to TFT Display—Controls the format and
timing of the output control signals. Active and passive
displays use different signal timing formats as described
in Section 16.3.8, “Panel Interface Signals and Timing.”
TFT also controls the use of the FRC in color mode.
0 = The LCD panel is a passive display
1 = The LCD panel is an active display: “digital
CRT” signal format, FRC is bypassed, LD
bus width is fixed at 16-bits
COLOR
Bit 30
Interfaces to Color Display—Activates three channels of
FRC in passive mode to allow use of the special 2 2/3
pixels per output vector format.
0 = The LCD panel is a monochrome display
1 = The LCD panel is a color display
PBSIZ
Bits 29–28
Panel Bus Width—Specifies the panel bus width.
Applicable for monochrome or passive matrix color
monitors. For active (TFT) color panels, the panel bus
width is fixed at 16. For passive color panels, only an 8-bit
panel bus width is supported.
00 = 1-bit
01 = 2-bit
10 = 4-bit
11 = 8-bit
BPIX
Bits 27–25
Bits Per Pixel—Indicates the number of bits per pixel in
memory.
000 = 1 bpp, FRC bypassed
001 = 2 bpp
010 = 4 bpp
011 = 8 bpp
100 = 12 bpp/16 bpp (16 bits of memory used)
11x = reserved
1x1 = reserved
PIXPOL
Bit 24
Pixel Polarity—Sets the polarity of the pixels.
0 = Active high
1 = Active low
Note:
For a TFT panel, set COLOR=1
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-23
Programming Model
Table 16-13. Panel Configuration Register Description (continued)
Name
Description
Settings
FLMPOL
Bit 23
First Line Marker Polarity—Sets the polarity of the first
line marker symbol.
0 = Active high
1 = Active low
LPPOL
Bit 22
Line Pulse Polarity—Sets the polarity of the line pulse
signal.
0 = Active high
1 = Active low
CLKPOL
Bit 21
LCD Shift Clock Polarity—Sets the polarity of the active
edge of the LCD shift clock.
0 = Active negative edge of LSCLK (in TFT
mode, active on positive edge of LSCLK)
1 = Active positive edge of LSCLK (in TFT
mode, active on negative edge of LSCLK)
OEPOL
Bit 20
Output Enable Polarity—Sets the polarity of the output
enable signal.
0 = Active high
1 = Active low
SCLKIDLE
Bit 19
LSCLK Idle Enable—Enables/Disables LSCLK when
VSYNC is idle in TFT mode.
0 = Disable LSCLK
1 = Enable LSCLK
END_SEL
Bit 18
Endian Select—Selects the image download into
memory as big or little endian format.
0 = Little endian
1 = Big endian
SWAP_SEL
Bit 17
Swap Select—Controls the swap of data in little endian
mode (when END_SEL = 1 this bit has no effect).
0 = 16 bpp mode
1 = 8 bpp. 4 bpp, 2 bpp, 1 bpp mode
REV_VS
Bit 16
Reverse Vertical Scan—Selects the vertical scan
direction as normal or reverse (the image flips along the
x-axis). The SSA register must be changed accordingly.
0 = Vertical scan in normal direction
1 = Vertical scan in reverse direction
ACDSEL
Bit 15
ACD Clock Source Select—Selects the clock source
used by the alternative crystal direction counter.
0 = Use FRM as clock source for ACD count
1 = Use LP/HSYN as clock source for ACD
count
ACD
Bits 14–8
Alternate Crystal Direction—Toggles the ACD signal
once every 1-16 FLM cycles based on the value specified
in this field. The actual number of FLM cycles between
toggles is the programmed value plus one.
For active mode (TFT=1), this parameter is not
used.
For passive mode (TFT=0), see description.
SCLKSEL
Bit 7
LSCLK Select—Selects whether to enable or disable
LSCLK in TFT mode when there is no data output.
0 = Disable OE and LSCLK in TFT mode when
no data output
1 = Always enable LSCLK in TFT mode even if
there is no data output
SHARP
Bit 6
Sharp Panel Enable—Enables/Disables signals for
Sharp HR-TFT panels.
0 = Disable Sharp signals
1 = Enable Sharp signals
MC9328MXS Reference Manual, Rev. 1.1
16-24
Freescale Semiconductor
Programming Model
Table 16-13. Panel Configuration Register Description (continued)
Name
PCD
Bits 5–0
Description
Settings
Pixel Clock Divider—Specifies the divide ratio applied to
LCDC_CLK. The LCDC_CLK (PerCLK2) is divided down
by the Pixel Clock Divider to generate the pixel clock. The
LSCLK will be the same as pixel clock in TFT mode, and
will be 1/8 the frequency of the pixel clock in passive
mode.
TFT (TFT bit = 1)
000000 = divide ratio is 1
000001 = divide ratio is 2
000010 = divide ratio is 3
…
111111 = divide ratio is 64
For passive displays (TFT bit = 0), the frequency of
LSCLK must be < 1/9 HCLK at 12 bpp and < 1/15 HCLK
at 4 or 8 bpp. For passive matrix color panels (COLOR = 1
and PBSIZ = 11), PCD must be ≥ 2 and PCLK_DIV2
(PCDR Register) must = 0 (divide by 1). See
Phase-Locked Loop and Clock Controller chapter in this
manual for PCDR register information.
Passive (TFT bit = 0)
000000 = divide ratio is 81
000001 = divide ratio is 161
000010 = divide ratio is 24
…
111111 = divide ratio is 512
For active displays (TFT bit = 1), the frequency of LSCLK
must be < 1/5 HCLK. When PCD = 0, the pixel clock
frequency is equal to the LCDC_CLK frequency.
Note 1: Do not use. For passive panels, PCD
must be greater than or equal to 2 or 000010.
See application notes at http:\\www.freescale.com\imx.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-25
Programming Model
16.4.5 Horizontal Configuration Register
The Horizontal Configuration Register defines the horizontal sync pulse timing.
HCR
BIT
Addr
0x0020501C
Horizontal Configuration Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
H_WIDTH
TYPE
rw
rw
rw
rw
rw
rw
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0400
BIT
15
14
13
12
11
10
9
8
H_WAIT_1
TYPE
H_WAIT_2
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-14. Horizontal Configuration Register Description
Name
Description
H_WIDTH
Bits 31–26
Horizontal Sync Pulse Width—Specifies the number of pixel clk periods that HSYNC is activated. The
active time is equal to (H_WIDTH + 1) of the pixel clk period. For Sharp HR-TFT panels, H_WIDTH is
typically set to 1.
Reserved
Bits 25–16
Reserved—These bits are reserved and should read 0.
H_WAIT_1
Bits 15–8
Wait Between OE and HSYNC—Specifies the number of pixel clk periods between the last LD of each line
and the beginning of the HSYNC. Total delay time equals (H_WAIT_1 + 1). For Sharp HR-TFT panels,
H_WAIT_1 is typically set to 14.
H_WAIT_2
Bits 7–0
Wait Between HSYNC and Start of Next Line—Specifies the number of pixel clk periods between the end
of HSYNC and the beginning of the first data of next line. Total delay time equals (H_WAIT_2 + 3).
MC9328MXS Reference Manual, Rev. 1.1
16-26
Freescale Semiconductor
Programming Model
16.4.6 Vertical Configuration Register
The Vertical Configuration Register defines the vertical sync pulse timing.
VCR
BIT
Addr
0x00205020
Vertical Configuration Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
V_WIDTH
TYPE
rw
rw
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
RESET
0x0401
BIT
15
14
13
12
11
10
9
8
V_WAIT_1
TYPE
V_WAIT_2
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-15. Vertical Configuration Register Description
Name
Description
V_WIDTH
Bits 31–26
Vertical Sync Pulse Width—Specifies the width, in lines, of the VSYNC pulse for active (TFT =1) mode.
For a value of “000001”, the vertical sync pulse encompasses one HSYNC pulse. For a value of “000002”,
the vertical sync pulse encompasses two HSYNC pulses, and so on. For passive (TFT=0) mode and
non-color mode, see Figure 16-12.
Reserved
Bits 25–16
Reserved—These bits are reserved and should read 0.
V_WAIT_1
Bits 15–8
Wait Between Frames 1—Defines the delay, in lines, between the end of the OE pulse and the beginning
of the VSYNC pulse for active (TFT=1) mode. This field has no meaning in passive non-color mode. The
actual delay is (V_WAIT_1). In passive color mode, this field is the delay, measured in virtual clock periods,
between the last line of the frame to the beginning of the next frame.
V_WAIT_2
Bits 7–0
Wait Between Frames 2—Defines the delay, in lines, between the end of the VSYNC pulse and the
beginning of the OE pulse of the first line in active (TFT=1) mode. The actual delay is V_WAIT_2 ) lines.
Set this field to zero for passive non-color mode. The minimum value of this field is 0x01.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-27
Programming Model
16.4.7 Panning Offset Register
The Panning Offset Register sets up the panning for the image.
POS
Addr
0x00205024
Panning Offset Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
POS
TYPE
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-16. Panning Offset Register Description
Name
Description
Reserved
Bits 31–5
Reserved—These bits are reserved and should read 0.
POS
Bits 4–0
Panning Offset—Defines the number of bits that the
data from memory is panned to the left before
processing. POS is read by the LCDC once at the
beginning of each frame.
Settings
To achieve panning of the final image by N bits:
Bits Per Pixel
POS
Effective # of Bits
Panned on Image
1
N
N
2
2N
N
4
4N
N
8
8N
N
12
16N
N
MC9328MXS Reference Manual, Rev. 1.1
16-28
Freescale Semiconductor
Programming Model
16.4.8 LCD Cursor Position Register
The LCD Cursor Position Register is used to determine the starting position of the cursor on the LCD panel.
CPOS
BIT
31
30
29
CC
TYPE
Addr
0x0020500C
LCD Cursor Position Register
28
27
26
25
24
23
22
21
OP
20
19
18
17
16
CXP
rw
rw
r
rw
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
CYP
TYPE
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-17. LCD Cursor X Position Register Description
Name
CC
Bits 31–30
Description
Cursor Control—Controls the format of the cursor and the
type of arithmetic operations.
Settings
When OP = 0
00 = Transparent, cursor is disabled
01 = Full cursor (Black for non-color
displays; full-color for color displays)
10 = Reversed video
11 = Full (white) cursor
When OP = 1, and color mode
00 = Transparent, cursor is disabled
01 = OR between background and cursor
10 = XOR between background and cursor
11 = AND between background and cursor
Reserved
Bit 29
Reserved—This bit is reserved and should read 0.
OP
Bit 28
Arithmetic Operation Control—Enables/Disables
arithmetic operations between the background and the
cursor.
Reserved
Bits 27–26
Reserved—These bits are reserved and should read 0.
CXP
Bits 25–16
Cursor X Position—Represents the cursor’s horizontal starting position X in pixel count (from 0 to XMAX).
Reserved
Bits 15–9
Reserved—These bits are reserved and should read 0.
CYP
Bits 8–0
Cursor Y Position—Represents the cursor’s vertical starting position Y in pixel count (from 0 to YMAX).
0 = Disable arithmetic operation
1 = Enable arithmetic operation
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-29
Programming Model
16.4.9 LCD Cursor Width Height and Blink Register
The LCD Cursor Width Height and Blink Register is used to determine the width and height of the cursor, and how
it blinks.
LCWHB
BIT
31
30
29
28
27
BK_EN
TYPE
Addr
0x00205010
LCD Cursor Width Height and Blink Register
26
25
24
23
22
21
20
19
CW
18
17
16
CH
rw
r
r
rw
rw
rw
rw
rw
r
r
r
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
RESET
0X0101
BIT
15
14
13
12
11
10
9
8
BD
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
RESET
0X007F
Table 16-18. LCD Cursor Width Height and Blink Register Description
Name
Description
Settings
BK_EN
Bit 31
Blink Enable—Determines whether the blink enable cursor
will blink or remain steady.
0 = Blink is disabled
1 = Blink is enabled
Reserved
Bits 30–29
Reserved—These bits are reserved and should read 0.
CW
Bits 28–24
Cursor Width—Specifies the width of the hardware cursor in
pixels.
Reserved
Bits 23–21
Reserved—These bits are reserved and should read 0.
CH
Bits 20–16
Cursor Height—Specifies the height of the hardware cursor
in pixels.
Reserved
Bits 15–8
Reserved—These bits are reserved and should read 0.
BD
Bits 7–0
Blink Divisor—Sets the cursor blink rate. A 32 Hz clock from RTC is used to clock the 8-bit up counter. When
the counter value equals BD, the cursor toggles on/off.
This field can be any value between 1 and 31
(setting this field to zero disables the cursor)
This field can be any value between 1 and 31
(setting this field to zero disables the cursor)
MC9328MXS Reference Manual, Rev. 1.1
16-30
Freescale Semiconductor
Programming Model
16.4.10 LCD Color Cursor Mapping Register
The LCD Color Cursor Mapping Register defines the color of the cursor in passive or TFT color modes.
LCHCC
Addr
0x00205014
LCD Color Cursor Mapping Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
CUR_COL_R
TYPE
8
CUR_COL_G
CUR_COL_B
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-19. LCD Color Cursor Mapping Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
CUR_COL_R
Bits 15–11
Cursor Red Field—Defines the red component of the
cursor color in color mode.
For 8 bpp/12 bpp:
0000x = No red
...
1111x = Full red
For 16 bpp:
00000 = No red
...
11111 = Full red
CUR_COL_G
Bits 10–5
Cursor Green Field—Defines the green component of
the cursor color in color mode.
For 8 bpp/12 bpp:
0000xx = No green
....
1111xx = Full green
For 16 bpp:
000000 = No green
...
111111 = Full green
CUR_COL_B
Bits 4–0
Cursor Blue Field—Defines the blue component of
the cursor color in color mode.
For 8 bpp/12 bpp:
0000x = No blue
...
1111x = Full blue
For 16 bpp:
00000 = No blue
...
11111 = Full blue
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-31
Programming Model
16.4.11 Sharp Configuration 1 Register
For 2 bpp modes, full black and full white are the two predefined display levels. The other two intermediate
gray-scale shading densities can be adjusted within the Sharp Configuration 1 Register. This register also controls
the relative delay timing of the additional signals CLS, REV, and PS required for Sharp TFT displays. The TFT
timing diagram that shows the relationship between these signals is shown in Figure 16-17 on page 16-33.
LSCR1
BIT
Sharp Configuration 1 Register
31
30
29
28
27
26
25
24
23
22
21
PS_RISE_DELAY
TYPE
0x00205028
20
19
18
17
16
CLS_RISE_DELAY
rw
rw
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0400
BIT
15
14
13
12
11
10
9
8
7
REV_TOGGLE_DELAY
TYPE
GRAY 1
GRAY 2
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
1
1
0
1
1
1
0
0
1
1
RESET
0x0373
Table 16-20. Sharp Configuration 1 Register Description
Name
Description
PS_RISE_DELAY
Bits 31–26
PS Rise Delay—Controls the delay of the rising edge of
PS relative to the falling edge of CLS. Delay is measured
in LCDC_CLK (PerCLK2) periods.
Reserved
Bits 25–24
Reserved—These bits are reserved and should read 0.
CLS_RISE_DELAY
Bits 23–16
CLS Rise Delay—Controls the delay of the rising edge of
CLS relative to the last LD of the line. Delay is measured
in LCDC_CLK (PerCLK2) periods.
Reserved
Bits 15–12
Reserved—These bits are reserved and should read 0.
Settings
000000 = 0 LSCLK periods
000001 = 1 LSCLK period
...
111111 = 63 LSCLK periods
00000000 = 1 LSCLK period
00000001 = 2 LSCLK periods
...
11111111 = 256 LSCCLK periods
REV_TOGGLE_DELAY REV Toggle Delay—Controls the transition delay of REV
Bits 11–8
relative to the last LD of the line. Delay is measured in
LCDC_CLK (PerCLK2) periods.
0000 = 1 LSCLK period
0001 = 2 LSCLK periods
...
1111 = 16 LSCLK periods
GRAY 2
Bits 7–4
Gray-Scale 2—Represents one of the two gray-scale
shading densities.
This field is programmable to any value
between 0 and 16 (0 and 16 are
defined as two of the four colors).
GRAY 1
Bits 3–0
Gray-Scale 1—Represents the other gray-scale shading.
This field is programmable to any value
between 0 and 16 (0 and 16 are
already defined as two of the four
colors).
MC9328MXS Reference Manual, Rev. 1.1
16-32
Freescale Semiconductor
Programming Model
XMAX
LSCLK
R0-R5
G0-G5
B0-B5
D1 D2
D320
SPL
SPR
D320
1 CLK
Hwait1
Hwait1
Hwait2
LP
cls_rise_delay + 1
cls_width
CLS
PS
ps_rise_delay
rev_tog_delay +1
rev_tog_delay +1
REV
Falling edge of PS aligns with rising edge of CLS
The rising edge delay of PS is programmed by PS_RISE_DELAY
CLS_HI_WIDTH is equal to PWM_SCR0 • 256 + PWM_WIDTH in units of LSCLK.
SPL/SPR pulse width is fixed and aligned to the first data of the line.
REV toggles every LP period.
Figure 16-17. Horizontal Timing in MC9328MXS
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-33
Programming Model
16.4.12 PWM Contrast Control Register
The PWM Contrast Control Register is used to control the signal output at the CONTRAST pin, which controls the
contrast of the LCD panel.
PWMR
BIT
Addr
0x0020502C
PWM Contrast Control Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CLS_HI_WIDTH
TYPE
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
LDMSK
TYPE
9
SCR
8
CC_EN
PW
rw
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-21. PWM Contrast Control Register Description
Name
Description
Settings
Reserved
Bits 31–25
Reserved—These bits are reserved and should read 0.
CLS_HI_
WIDTH
Bit 24–16
CLS High Pulse Width—Controls the Hi Pulse width of CLS in units of SCLK. The actual pulse width =
CLS_HI_WDITH +1.
LDMSK
Bit 15
LD Mask—Enables/Disables the LD outputs to zero for panel power-off
sequence as required by Sharp TFT or other panels.
Reserved
Bits 14–11
Reserved—These bits are reserved and should read 0.
SCR
Bits 10–9
Source Select—Selects the input clock source for the PWM counter. The
PWM output frequency is equal to the frequency of the input clock divided
by 256.
00 = Line pulse
01 = Pixel clock
10 = LCD clock
11 = Reserved
CC_EN
Bit 8
Contrast Control Enable—Enables/Disables the contrast control function.
0 = Contrast control is off
1 = Contrast control is on
PW
Bits 7–0
Pulse-Width—Controls the pulse-width of the built-in pulse-width modulator, which controls the contrast of the
LCD screen.
0 = LD [15:0] is normal
1 = LD [15:0] always equals 0
MC9328MXS Reference Manual, Rev. 1.1
16-34
Freescale Semiconductor
Programming Model
16.4.13 Refresh Mode Control Register
The Refresh Mode Control Register is used to control refresh characteristics.
RMCR
Addr
0x00205034
Refresh Mode Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
LCDC_EN SELF_REF
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-22. Refresh Mode Control Register Description
Name
Description
Settings
Reserved
Bits 31–2
Reserved—These bits are reserved and should read 0.
LCDC_EN
Bit 1
LCDC Enable—Enables/Disables the LCDC.
0 = Disable the LCDC
1 = Enable the LCDC
SELF_REF
Bit 0
Self-Refresh—Enables/Disables self-refresh mode.
0 = Disable self-refresh
1 = Enable self-refresh
NOTE:
1. On entering self-refresh mode, the LSCLK and LD [15:0] signals stay low. HYSN and VSYN operate
normally.
2. Except for the SSA and Mapping RAM registers, all configurations must be performed before
enabling the LCDC to avoid a malfunction.
3. The SSA must always match the address range of the RAM selected. If the user wants to switch
between various types of RAM, the LCDC must be disabled before switching.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-35
Programming Model
16.4.14 DMA Control Register
There is a 16 × 32 bit line buffer in the LCDC that stores DMA data from system memory. The DMA Control
Register controls the DMA burst length and when to trigger a DMA burst in terms of the number of data bytes left
in the pixel buffer.
DMACR
BIT
Addr
0x00205030
DMA Control Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
BURST
TYPE
17
16
HM
rw
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
7
6
5
4
3
2
1
0
RESET
0x8008
BIT
15
14
13
12
11
10
9
8
TM
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
RESET
0x0002
Table 16-23. DMA Control Register Description
Name
Description
Settings
BURST
Bit 31
Burst Length—Determines whether the burst length is fixed or
dynamic.
0 = Burst length is dynamic
1 = Burst length is fixed
Reserved
Bits 30–20
Reserved—These bits are reserved and should read 0.
HM
Bits 19–16
DMA High Mark—Establishes the high mark for DMA requests. For dynamic burst length, once the DMA
request is made, data is loaded and the pixel buffer continues to be filled until the number of empty words left
in the DMA FIFO is equal to the high mark minus 2. For fixed burst length, the burst length (in words) of each
request is equal to the DMA high mark setting.
Reserved
Bits 15–4
Reserved—These bits are reserved and should read 0.
TM
Bits 3–0
DMA Trigger Mark—Sets the low level mark in the pixel buffer to trigger a DMA request. The low level mark
equals the number of words left in the pixel buffer.
NOTE:
For SDRAM access, a fixed burst length of 8 is recommended
fixed burst length = 1
high mark = 8
low mark = 4
For bus that is heavy loaded that requires SDRAM access, a dynamic burst length
is recommended
fixed burst length = 0
MC9328MXS Reference Manual, Rev. 1.1
16-36
Freescale Semiconductor
Programming Model
high mark = 3
low mark = 8
For an especially heavily loaded system, increasing the low mark value increases
the chance of granting of the system bus, at the expense of more frequent bus
requests.
The low mark should never be set higher than 10, and high mark should always
be set to 3.
16.4.15 Interrupt Configuration Register
The Interrupt Configuration Register is used to configure the interrupt conditions.
LCDICR
Addr
0x00205038
Interrupt Configuration Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0X0000
BIT
15
14
13
12
11
10
9
8
7
INT SYN
TYPE
INT CON
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
r
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-24. Interrupt Configuration Register Description
Name
Description
Reserved
Bits 31–3
Reserved—These bits are reserved and should read 0.
INTSYN
Bit 2
Interrupt Source—Determines if an interrupt flag is set during last
data/first data of frame loading or on last data/first data of frame
output to the LCD panel.
Note: There is a latency between loading the last/first data of
frame to output to LCD panel.
Reserved
Bit 1
Reserved—This bit is reserved and should read 0.
INTCON
Bit 0
Interrupt Condition—Determines if an interrupt condition is set at
the beginning or the end of frame condition.
Settings
0 = Interrupt flag is set on loading the last
data/first data of frame from memory
1 = Interrupt flag is set on output of the last
data/first data of frame to LCD panel
0 = Interrupt flag is set when the End of
Frame (EOF) is reached
1 = Interrupt flag is set when the Beginning
of Frame (BOF) is reached
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-37
Programming Model
16.4.16 Interrupt Status Register
The read-only Interrupt Status Register indicates whether an interrupt has occurred. The interrupt flag is cleared by
reading the register.
LCDISR
Addr
0x00205040
Interrupt Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
EOF
BOF
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
UDR_ ERR_
ERR
RES
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-25. Interrupt Status Register Description
Name
Description
Settings
Reserved
Bits 31–4
Reserved—These bits are reserved and should read 0.
UDR_ERR
Bit 3
Under Run Error—Indicates whether the LCDC FIFO has hit an under-run
condition. This is when the data output rate is faster than the data input rate
to the FIFO. Under-run can cause erroneous data output to LD. The LD data
output rate must be adjusted to prevent this error.
0 = Interrupt has not occurred
1 = Interrupt has occurred
ERR_RES
Bit 2
Error Response—Indicates whether the LCDC has issued a read data
request and has received a response from the memory controller not equal to
‘OK.’ It is cleared by reading the status register, at power on reset, or when
the LCDC is disabled.
0 = Interrupt has not occurred
1 = Interrupt has occurred
EOF
Bit 1
End of Frame—Indicates whether the end of frame has been reached. It is
cleared by reading the status register, at power on reset, or when the LCDC
is disabled.
0 = Interrupt has not occurred
1 = Interrupt has occurred
BOF
Bit 0
Beginning of Frame—Indicates whether the beginning of frame has been
reached. It is cleared by reading the status register, at power on reset, or
when the LCDC is disabled.
0 = Interrupt has not occurred
1 = Interrupt has occurred
MC9328MXS Reference Manual, Rev. 1.1
16-38
Freescale Semiconductor
Programming Model
16.4.17 Mapping RAM Registers
The mapping RAM is used for mapping 4-bit codes for grayscale to the 16 gray shades, and for mapping 4- or 8-bit
color codes to either the 4096 (for active panels) or 512 colors (for passive panels). The color RAM
(0x00205800-0x00205BFC) contains 256 entries and each entry is 12 bits wide. Each RAM entry use 4 bytes of
address space. The RAM can be accessed with word transactions only and the address must be word aligned.
Unimplemented bits are read as 0. Byte or halfword access to the RAM corrupts its contents. All read/write data
use least significant twelve bits.
In 4 bpp mode, the first sixteen RAM entries are used. In 8 bpp mode, all 256 RAM entries are used. The color
RAM is not initialized at reset. With any given panel, only one of the following settings is valid:
•
1 bpp monochrome mode
•
4 bpp gray-scale mode
•
4 bpp passive matrix color mode
•
8 bpp passive matrix color mode
•
4 bpp active matrix color mode
•
8 bpp active matrix color mode
•
12/16 bpp active matrix color mode
16.4.17.1 One Bit/Pixel Monochrome Mode
The mapping RAM is not used in this mode because the LCDC uses the display data in memory to drive the panel
directly.
16.4.17.2 Four Bits/Pixel Gray-Scale Mode
In four bits/pixel gray-scale mode, a 4-bit code represents a gray-scale level. The first 16 mapping RAM entries
must be written to define the codes for all 16 combinations.
BIT
11
10
9
8
7
6
5
4
3
2
1
0
GPM
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
0
0
0
0
0
0
0
0
?
?
?
?
RESET
Table 16-26. Four Bits/Pixel Gray-Scale Mode
Name
Description
Reserved
Bits 11–4
Reserved—These bits are reserved and should read 0.
GPM
Bits 3–0
Gray Palette Map—Represents the gray-scale level for a given pixel code.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-39
Programming Model
16.4.17.3 Four Bits/Pixel Passive Matrix Color Mode
In four bits/pixel passive matrix color mode, a 4-bit code represents a 12-bit color. Because just four bits are used
to encode the color, a maximum of 16 colors can be selected out of a palette of 4096. The first 16 mapping RAM
entries must be written to define the codes for the 16 available combinations.
BIT
11
10
9
8
7
6
5
R
TYPE
4
3
2
G
1
0
B
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
?
?
?
?
?
?
?
?
?
?
?
?
RESET
0X???
Table 16-27. Four Bits/Pixel Passive Matrix Color Mode
Name
Description
R
Bits 11–8
Red Level (color display)—Represents the red component level in the color.
G
Bits 7–4
Green Level (color display)—Represents the green component level in the color.
B
Bits 3–0
Blue Level (color display)—Represents the blue component level in the color.
16.4.17.4 Eight Bits/Pixel Passive Matrix Color Mode
In eight bits/pixel passive matrix color mode, an 8-bit code represents a 12-bit color. Because eight bits are used to
encode the color, a maximum of 256 colors can be selected out of a palette of 4096. All 256 mapping RAM entries
must be written to define the codes for the 256 available combinations.
BIT
11
10
9
8
7
6
5
R
TYPE
4
3
2
G
1
0
B
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
?
?
?
?
?
?
?
?
?
?
?
?
RESET
0x???
Table 16-28. Eight Bits/Pixel Passive Matrix Color Mode
Name
Description
R
Bits 11–8
Red Level (color display)—Represents the red component level in the color.
G
Bits 7–4
Green Level (color display)—Represents the green component level in the color.
B
Bits 3–0
Blue Level (color display)—Represents the blue component level in the color.
MC9328MXS Reference Manual, Rev. 1.1
16-40
Freescale Semiconductor
Programming Model
16.4.17.5 Four Bits/Pixel Active Matrix Color Mode
In four bits/pixel active color mode, a 4-bit code represents a 12-bit color. Because just four bits are used to encode
the color, a maximum of 16 colors can be selected out of a palette of 4096. The first 16 mapping RAM entries must
be written to define the codes for the 16 available combinations.
BIT
11
10
9
8
7
6
5
R
TYPE
4
3
2
G
1
0
B
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
?
?
?
?
?
?
?
?
?
?
?
?
RESET
0x???
Table 16-29. Four Bits/Pixel Active Matrix Color Mode
Name
Description
R
Bits 11–8
Red Level (color display)—Represents the red component level in the color.
G
Bits 7–4
Green Level (color display)—Represents the green component level in the color.
B
Bits 3–0
Blue Level (color display)—Represents the blue component level in the color.
16.4.17.6 Eight Bits/Pixel Active Matrix Color Mode
In eight bits/pixel active color mode, an 8-bit code represents a 12-bit color. Because eight bits are used to encode
the color, a maximum of 256 colors can be selected out of a palette of 4096. All 256 mapping RAM entries must be
written to define the codes for the 256 available combinations.
BIT
11
10
9
8
7
6
5
R
TYPE
4
3
2
G
1
0
B
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
?
?
?
?
?
?
?
?
?
?
?
?
RESET
0x???
Table 16-30. Eight Bits/Pixel Active Matrix Color Mode
Name
Description
R
Bits 11–8
Red Level (color display)—Represents the red component level in the color.
G
Bits 7–4
Green Level (color display)—Represents the green component level in the color.
B
Bits 3–0
Blue Level (color display)—Represents the blue component level in the color.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
16-41
Programming Model
16.4.17.7 Twelve Bits/Pixel and Sixteen Bits/Pixel Active Matrix Color Mode
In this mode the mapping RAM is not used, because the LCDC uses the display data in memory to drive the panel
directly.
MC9328MXS Reference Manual, Rev. 1.1
16-42
Freescale Semiconductor
Chapter 17
Pulse-Width Modulator (PWM)
The pulse-width modulator (PWM) of the MC9328MXS is optimized to use 16-bit resolution and a 4 × 16 data
FIFO to generate high quality sound from stored audio files and to generate tones. Figure 17-1 illustrates the block
diagram of the pulse-width modulator.
PERCLK1
CLK32
MPU Interface
4-Word FIFO
CLKSRC
Sample Compare
Divider
Prescaler
PCLK
Output
Control
PWMO
Counter
Period
Figure 17-1. Pulse-Width Modulator Block Diagram
17.1 Introduction
The PWM can be programmed to select one of two clock signals as its source frequency. The selected clock signal
is passed through a divider and a prescaler before being input to the counter. The output is available at the
pulse-width modulator output (PWMO) external pin.
17.2 PWM Signals
17.2.1 Clock Signals
As shown in Figure 17-1, the clock source (CLKSRC) bit in the PWM control (PWMC) register selects the source
clock—PERCLK1 (the default) or CLK32—to be used by the PWM. The selected clock signal is then sent through
a divider and a prescaler to produce the PCLK signal.
The clock selection (CLKSEL) field in the PWMC selects the frequency of the output of the divider chain. The
incoming clock source is divided by a binary value between 2 and 16.
For 16 kHz audio applications, CLKSEL = 01, divide by 4. For DC-level applications, CLKSEL = 11, divide by
16. See Table 17-7 on page 17-8 for a complete list of settings for the PWMC register.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
17-1
PWM Operation
Adjust the 7-bit prescaler to achieve lower sampling rates by programming the PRESCALER field in the PWMC
register with any number between 0 and 127 to scale down the incoming clock source by a corresponding factor of
1 to 128.
17.2.2 Pin Configuration for PWM
Figure 17-1 shows the signals used for the PWM module. The PWMO pin is multiplexed with other functions on
the device, and must be configured for PWM operation. Table 17-1 describes the procedure for the PWM pin
configuration.
NOTE:
The user must ensure that the data direction bit in the GPIO is set to the correct
direction for proper operation. See Section 25.5.1, “Data Direction Registers,” on
page 25-8 for details.
Table 17-1. Pin Configuration
Pin
Setting
PWMO
Primary function of
GPIO Port A [2]
Configuration Procedure
1.Clear bit 2 of Port A GPIO In Use register (GIUS_A)
2. Clear bit 2 of Port A General Purpose register (GPR_A)
17.3 PWM Operation
The pulse-width modulator has three modes of operation—playback, tone, and digital-to-analog (D/A) converter.
17.3.1 Playback Mode
In playback mode, the pulse-width modulator uses the data from a sound file to output the resulting audio through
an external speaker. To reproduce the best quality of sound from a sound file, it is necessary to use a sampling
frequency that is equal to or an even multiple of the sampling frequency used to record the sound.
The PWM produces variable-width pulses at a constant frequency. The width of the pulse is proportional to the
analog voltage of a particular audio sample. At the beginning of a sample period cycle, the PWMO pin is set to 1
and the counter begins counting up from 0x0000. The sample value is compared on each count of the prescaler
clock. When the sample and count values match, the PWMO signal is cleared to 0. The counter continues counting,
and when it overflows from 0xFFFF to 0x0000, another sample period cycle begins. The prescaler clock (PCLK)
runs 256 times faster than the sampling rate when the PERIOD field of the PWM period (PWMP) register is at its
maximum value.
Figure 17-2 illustrates how variable width pulses affect an audio waveform.
Pulse-Width Modulation Stream
Filtered Audio
Figure 17-2. Audio Waveform Generation
MC9328MXS Reference Manual, Rev. 1.1
17-2
Freescale Semiconductor
Programming Model
Digital sample values are loaded into the pulse-width modulator as 16-bit words (big endian format). A 4-word
FIFO minimizes interrupt overhead. A maskable interrupt is generated when there are 1 or 0 words in the FIFO, in
which case the software can write two 16-bit samples into the FIFO. Interrupts occur every 50 μs, if the REPEAT
field of the PWMC register is set to 0, when a 16 kHz sampling frequency is being used to play back sampled data,
when writing two 16-bit data at each interrupt.
17.3.2 Tone Mode
When the value stored in the PWMP register < 0xFFFE, the PWM operates in tone mode and generates a
continuous tone at a single frequency which is determined by the settings in the PWM registers.
17.3.3 Digital-to-Analog Converter (D/A) Mode
The pulse-width modulator outputs a frequency with a different pulse width if a low-pass filter is added at the
PWMO signal. It produces a different DC level when programmed using the sample fields in the PWM sample
(PWMS) register. When used in this manner, the PWM becomes a D/A converter.
17.4 Programming Model
The PWM module includes 4 user-accessible 32-bit registers. Table 17-2 summarizes these registers and their
addresses.
Table 17-2. PWM Module Register Memory Map
Description
Name
Address
PWM Control Register
PWMC
0x00208000
PWM Sample Register
PWMS
0x00208004
PWM Period Register
PWMP
0x00208008
PWM Counter Register
PWMCNT
0x0020800C
17.4.1 PWM Control Register
The PWM Control Register controls the operation of the pulse-width modulator, and it also contains the status of
the PWM FIFO. The register bit assignments are shown in the following register display. The register settings are
described in Table 17-3 on page 17-4.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
17-3
Programming Model
PWMC
BIT
Addr
0x00208000
PWM Control Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
HCTR BCTR
TYPE
SWR
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
IRQ
IRQ
EN
FIFO
AV
EN
REPEAT
CLKSEL
w
rw
RESET
0x0000
BIT
15
14
13
12
CLK
SRC
TYPE
11
10
9
8
PRESCALER
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
r
rw
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
RESET
0x0020*
Table 17-3. PWM Control Register Description
Name
Description
Settings
Reserved
Bits 31–19
Reserved—These bits are reserved and should read 0.
HCTR
Bit 18
Halfword FIFO Data Swapping—Swapping upper and lower write data
which to PWMS.
0 = Do not swap
1 = Swap
BCTR
Bit 17
Byte FIFO Data Swapping—Swapping bits[15:8] and bits[7:0] data
which from PWMS to FIFO.
0 = Do not swap
1 = Swap
SWR
Bit 16
Software Reset—Enables a reset of the PWM. After five system clock
cycles, the SWR bit releases automatically.
0 = No action taken
1 = Reset the PWM
CLKSRC
Bit 15
Clock Source—Selects the clock source for the pulse-width modulator.
0 = Selects PERCLK1 source
1 = Selects CLK32 source
The CLK32 frequency is
determined by the frequency of
the reference crystal.
PRESCALER
Bits 14–8
Prescaler—Scales down the incoming clock by dividing the incoming clock signal by the value contained in
the PRESCALER field+1. The prescaler is normally used to generate a low single-tone PWMO signal. For
voice modulation, these bits are set to 0 (divide by 1).
IRQ
Bit 7
Interrupt Request—Indicates that the FIFO contains 1 or 0 words,
which signals the need to write no more than three 16-bit words into the
PWMS register. The IRQ bit automatically clears itself after this register
is read, eliminating an extra write cycle in the interrupt service routine. If
the IRQEN bit is 0, the IRQ bit can be polled to indicate the status of the
period comparator. For debugging purposes, the IRQ bit can be set to
immediately post a PWM interrupt.
0 = FIFO contains more than 1
sample word
1 = FIFO contains 1 or 0 sample
words
IRQEN
Bit 6
Interrupt Request Enable—Enables/Disables the pulse-width
modulator interrupt. When IRQEN is low, the interrupt is disabled.
0 = PWM interrupt is disabled
1 = PWM interrupt is enabled
MC9328MXS Reference Manual, Rev. 1.1
17-4
Freescale Semiconductor
Programming Model
Table 17-3. PWM Control Register Description (continued)
Name
Description
Settings
FIFOAV
Bit 5
FIFO Available—Indicates that the FIFO is available for at least one word of sample data. Data words can
be written to the FIFO as long as the FIFOAV bit is set. If the FIFO is written to while the FIFOAV bit is
cleared, the write is ignored.
EN
Bit 4
Enable—Enables/Disables the pulse-width modulator. If the EN bit is
not enabled, writes to any register in the PWM are ignored.
When the pulse-width modulator is disabled, it is in low-power mode, the
output pin is forced to 0, and the following events occur:
• The clock prescaler is reset and frozen.
• The counter is reset and frozen.
• The FIFO is flushed.
When the pulse-width modulator is enabled, it begins a new period, and
the following events occur:
• The output pin is set to start a new period.
• The prescaler and counter are released and begin counting.
• The IRQ bit is set, therefore indicating that the FIFO is empty.
0 = PWM is disabled
1 = PWM is enabled
REPEAT
Bits 3–2
Sample Repeats—Selects the number of times each sample is
repeated. The repeat feature reduces the interrupt overhead, reduces
CPU loading when audio data is played back at a higher rate, and allows
the use of a lower-cost low-pass filter.
00 = No repeat
(play the sample once)
01 = Repeat one time
(play the sample twice)
10 = Repeat three times (play
the sample four times)
11 = Repeat seven times (play
the sample eight times)
For example, if the audio data is sampled at 8 kHz and the data is
played back at 8 kHz again, an 8 kHz hum (carrier) is generated during
playback. To filter this carrier, a high-quality low-pass filter is required.
For a higher playback rate, it is possible to reconstruct samples at
16 kHz by using the sample twice. This method shifts the carrier from an
audible 8 kHz to a less sensitive 16 kHz frequency range, resulting in
better output sound quality.
CLKSEL
Bits 1–0
Clock Selection—Selects the output of the sampling clock.
The approximate sampling rates are calculated using a 16 MHz clock
source (PRESCALER = 0 and PERIOD = default).
00 = Divide by 2—produces a
32 kHz sampling rate
01 = Divide by 4—produces a
16 kHz sampling rate
10 = Divide by 8—produces an
8 kHz sampling rate
11 = Divide by 16—provides a
4 kHz sampling rate
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
17-5
Programming Model
17.4.1.1 HCTR and BCTR Bit Description
When the endian format of the wave data stored in external memory is not compatible to the system endian format,
these two bits control the swapping of the data to the PWM FIFO. The data port size used by the external memory
must be used in conjunction with these two bits.
Table 17-4. HCTR and BCTR Bit Swapping
HCTR
BCTR
Swapping
0
0
No
0
1
Swapping bits[15:8] to bits[7:0] and bits[7:0] to bits[15:8]
1
0
Swapping bits[31:16] to bits[15:0] and bits[15:0] to bits[31:16]
1
1
Swapping bit[s31:16] to bits[15:0] and bits[15:0] to bits[15:0] to bits[31:16], and after that
swapping bits[15:8] to bits[7:0] and bits[7:0] to bits[15:8]
Note: Only the lower 16 bits are passed to PWM 16-bit FIFO after swapping.
17.4.2 PWM Sample Register
The PWM Sample Register is the input to the FIFO. Writing successive audio sample values to this register
automatically loads the values into the FIFO. The pulse-width modulator free-runs at the last set duty-cycle setting
until the FIFO is reloaded or the pulse-width modulator is disabled. If the value in this register is higher than the
PERIOD + 1, the output is never reset, which results in a 100% duty-cycle.
The register bit assignments are shown in the following register display. The register settings are described in
Table 17-5.
PWMS
Addr
0x00208004
PWM Sample Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SAMPLE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RESET
0xXXXX
MC9328MXS Reference Manual, Rev. 1.1
17-6
Freescale Semiconductor
Programming Model
Table 17-5. PWM Sample Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
SAMPLE
Bits 15–0
Sample—Contains a two-sample word. This word is written to the pulse-width modulator.
17.4.3 PWM Period Register
This register controls the pulse-width modulator period. When the counter value matches PERIOD + 1, the counter
is reset to start another period. The following equation applies:
PWMO (Hz) = PCLK (Hz) ÷ (PERIOD + 2)
Eqn. 17-1
Writing 0xFFFF to this register achieves the same result as writing 0xFFFE.
The register bit assignments are shown in the following register display. The register settings are described in
Table 17-6.
PWMP
Addr
0x00208008
PWM Period Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
PERIOD
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
RESET
0xFFFE
Table 17-6. PWM Period Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
PERIOD
Bits 15–0
Period—Represents the pulse-width modulator’s period control value.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
17-7
Programming Model
17.4.4 PWM Counter Register
The read-only PWM Counter Register contains the current count value and can be read at any time without
disturbing the counter. The register bit assignments are shown in the following register display. The register
settings are described in Table 17-7.
PWMCNT
Addr
0x0020800C
PWM Counter Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
COUNT
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-7. PWM Counter Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
COUNT
Bits 15–0
Count—Represents the current count value.
MC9328MXS Reference Manual, Rev. 1.1
17-8
Freescale Semiconductor
Chapter 18
Real-Time Clock (RTC)
This chapter discusses how to operate and program the real-time clock (RTC) module that maintains the system
clock, provides stopwatch, alarm, and interrupt functions, and supports the following features:
•
Full clock—days, hours, minutes, seconds
•
Minute countdown timer with interrupt
•
Programmable daily alarm with interrupt
•
Sampling timer with interrupt
•
Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts
•
Operation at 32.768 kHz or 32 kHz (determined by reference clock crystal)
As shown in the RTC block diagram (Figure 18-1), the real-time clock module consists of the following blocks:
•
Prescaler
•
Time-of-day (TOD) clock counter
•
Alarm
•
Sampling timer
•
Minute stopwatch
•
Associated control and bus interface hardware
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
18-1
Operation
CLK2HZ
32.768K OR 32K
CLK32HZ
TOD CLOCK
SAMPLING
TIMER
PRESCALER
1 PPS
1 PPM
MINUTE
1 PPH
HOUR
1 PPD
DAY
CLOCK
CONTROL
RTC_INT
RTC_SAM_INT
SECOND
INTERRUPT
CONTROL
INTERRUPT
ENABLE
INTERRUPT
STATUS
ALARM COMPARATOR
SECOND
LATCH
MINUTE
LATCH
HOUR
LATCH
ADDRESS
IPBUS
DECODE
DATA
MINUTE STOPWATCH
BUS CONTROL
Figure 18-1. Real-Time Clock Block Diagram
18.1 Operation
The prescaler converts the incoming crystal reference clock to a 1 Hz signal which is used to increment the
seconds, minutes, hours, and days TOD counters. The alarm functions, when enabled, generate RTC interrupts
when the TOD settings reach programmed values. The sampling timer generates fixed-frequency interrupts, and
the minute stopwatch allows for efficient interrupts on minute boundaries.
18.1.1 Prescaler and Counter
The prescaler divides the reference clock down to 1 Hz. The reference frequencies of 32.768 kHz and 32 kHz are
supported. The prescaler stages are tapped to support the sampling timer.
The counter portion of the RTC module consists of four groups of counters that are physically located in three
registers:
•
The 6-bit seconds counter is located in the SECONDS register
•
The 6-bit minutes counter and the 5-bit hours counter are located in the HOURMIN register
•
The 9-bit day counter is located in the DAYR register
These counters cover a 24-hour clock over 512 days. All three registers can be read or written at any time.
Interrupts signal when each of the four counters increments, and can be used to indicate when a counter rolls over.
For example, each tick of the seconds counter causes the 1 Hz interrupt flag to be set. When the seconds counter
rolls from 59 to 00, the minute counter increments and the MIN interrupt flag is set. The same is true for the minute
counter with the HR signal, and the hour counter with the DAY signal.
MC9328MXS Reference Manual, Rev. 1.1
18-2
Freescale Semiconductor
Operation
18.1.2 Alarm
There are three alarm registers that mirror the three counter registers. An alarm is set by accessing the real-time
clock alarm registers (ALRM_HM, ALRM_SEC, and DAYALARM) and loading the exact time that the alarm
should generate an interrupt. When the TOD clock value and the alarm value coincide, if the ALM bit in the
real-time clock interrupt enable register (RTCIENR) is set, an interrupt occurs.
NOTE:
If the alarm is not disabled, it will reoccur every 512 days. If a single alarm is
desired, the alarm function must be disabled through the RTC Interrupt Enable
register (RTCIENR).
18.1.3 Sampling Timer
The sampling timer is designed to support application software. The sampling timer generates a periodic interrupt
with the frequency specified by the SAMx bits of the RTCIENR register. This timer can be used for digitizer
sampling, keyboard debouncing, or communication polling. The sampling timer operates only if the real-time
clock is enabled. Table 18-1 lists the interrupt frequencies of the sampling timer for the possible reference clocks.
Multiple SAMx bits may be set in the RTC Interrupt Enable Register (RTCIENR). The corresponding bits in the
RTC Interrupt Status Register (RTCISR) will be set at the noted frequencies.
Table 18-1. Sampling Timer Frequencies
Sampling
Frequency
32.768 kHz
Reference Clock
32 kHz
Reference Clock
SAM7
512 Hz
500 Hz
SAM6
256 Hz
250 Hz
SAM5
128 Hz
125 Hz
SAM4
64 Hz
62.5 Hz
SAM3
32 Hz
31.25 Hz
SAM2
16 Hz
15.625 Hz
SAM1
8 Hz
7.8125 Hz
SAM0
4 Hz
3.90625 Hz
18.1.4 Minute Stopwatch
The minute stopwatch performs a countdown with a one minute resolution. It can be used to generate an interrupt
on a minute boundary—for example, to turn off the LCD controller after five minutes of inactivity, program a
value of 0x04 into the Stopwatch Count (CNT) field of the Stopwatch Minutes (STPWCH) register (see
Table 18-12 on page 18-16 for a complete list of settings for the STPWCH register). At each minute, the value in
the stopwatch is decremented. When the stopwatch value reaches -1, the interrupt occurs. The value of the register
does not change until it is reprogrammed. Note that the actual delay includes the seconds from setting the
stopwatch to the next minute tick.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
18-3
Programming Model
18.2 Programming Model
The RTC module includes ten 32-bit registers. Table 18-2 summarizes these registers and their addresses.
Table 18-2. RTC Module Register Memory Map
Description
Name
Address
RTC Days Counter Register
DAYR
0x00204020
RTC Hours and Minutes Counter Register
HOURMIN
0x00204000
RTC Seconds Counter Register
SECONDS
0x00204004
RTC Day Alarm Register
DAYALARM
0x00204024
RTC Hours and Minutes Alarm Register
ALRM_HM
0x00204008
RTC Seconds Alarm Register
ALRM_SEC
0x0020400C
RTC Control Register
RCCTL
0x00204010
RTC Interrupt Status Register
RTCISR
0x00204014
RTC Interrupt Enable Register
RTCIENR
0x00204018
Stopwatch Minutes Register
STPWCH
0x0020401C
18.2.1 RTC Days Counter Register
The real-time clock days counter register (DAYR) is used to program the day for the TOD clock. When the HOUR
field of the HOURMIN register rolls over from 23 to 00, the day counter increments. It can be read or written at
any time. After a write, the time changes to the new value. This register cannot be reset because the real-time clock
is always enabled at reset.
NOTE:
This day counter only supports halfword and word write operations. That means
that all 9 bits must be set simultaneously.
MC9328MXS Reference Manual, Rev. 1.1
18-4
Freescale Semiconductor
Programming Model
DAYR
Addr
0x00204020
RTC Days Counter Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DAYS
TYPE
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
?
?
?
?
?
?
?
?
?
RESET
0x0???
Table 18-3. RTC Days Counter Register Description
Name
Description
Reserved
Bits 31–9
Reserved—These bits are reserved and should read 0.
DAYS
Bits 8–0
Day Setting—Indicates the current day count.
Settings
DAYS can be set to any value between 0
and 511.
18.2.2 RTC Hours and Minutes Counter Register
The real-time clock hours and minutes counter register (HOURMIN) is used to program the hours and minutes for
the TOD clock. It can be read or written at any time. After a write, the time changes to the new value. This register
cannot be reset because the real-time clock is always enabled at reset.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
18-5
Programming Model
HOURMIN
Addr
0x00204000
RTC Hours and Minutes Counter Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
HOURS
TYPE
MINUTES
r
r
r
rw
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
0
0
0
?
?
?
?
?
0
0
?
?
?
?
?
?
RESET
0x????
Table 18-4. RTC Hours and Minutes Counter Register Description
Name
Description
Settings
Reserved
Bits 31–13
Reserved—These bits are reserved and should read 0.
HOURS
Bits 12–8
Hour Setting—Indicates the current hour.
Reserved
Bits 7–6
Reserved—These bits are reserved and should read 0.
MINUTES
Bits 5–0
Minute Setting—Indicates the current minute.
HOURS can be set to any value between 0 and 23.
MINUTES can be set to any value between 0 and 59.
MC9328MXS Reference Manual, Rev. 1.1
18-6
Freescale Semiconductor
Programming Model
18.2.3 RTC Seconds Counter Register
The real-time clock seconds register (SECONDS) is used to program the seconds for the TOD clock. It can be read
or written at any time. After a write, the time changes to the new value. This register cannot be reset because the
real-time clock is always enabled at reset.
SECONDS
Addr
0x00204004
RTC Seconds Counter Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SECONDS
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
?
?
?
?
?
?
RESET
0X00??
=
Table 18-5. RTC Seconds Counter Register Description
Name
Description
Settings
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
SECONDS
Bits 5–0
Seconds Setting—Indicates the current second.
SECONDS can be set to any value between 0 and 59.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
18-7
Programming Model
18.2.4 RTC Day Alarm Register
The real-time clock day alarm (DAYALARM) register is used to configure the day for the alarm. The alarm
settings can be read or written at any time.
DAYALARM
Addr
0x00204024
RTC Day Alarm Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DAYSAL
TYPE
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-6. RTC Day Alarm Register Description
Name
Description
Reserved
Bits 31–9
Reserved—These bits are reserved and should read 0.
DAYSAL
Bits 8–0
Day Setting of the Alarm—Indicates the current day setting of
the alarm.
Settings
DAYSAL can be set to any value between
0 and 511.
MC9328MXS Reference Manual, Rev. 1.1
18-8
Freescale Semiconductor
Programming Model
18.2.5 RTC Hours and Minutes Alarm Register
The real-time clock hours and minutes alarm (ALRM_HM) register is used to configure the hours and minutes
setting for the alarm. The alarm settings can be read or written at any time.
ALRM_HM
Addr
0x00204008
RTC Hours and Minutes Alarm Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
HOURS
TYPE
MINUTES
r
r
r
rw
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-7. RTC Hours and Minutes Alarm Register Description
Name
Description
Reserved
Bits 31–13
Reserved—These bits are reserved and should read 0.
HOURS
Bits 12–8
Hour Setting of the Alarm—Indicates the current hour setting
of the alarm.
Reserved
Bits 7–6
Reserved—These bits are reserved and should read 0.
MINUTES
Bits 5–0
Minute Setting of the Alarm—Indicates the current minute
setting of the alarm.
Settings
HOURS can be set to any value between
0 and 23.
MINUTES can be set to any value
between 0 and 59.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
18-9
Programming Model
18.2.6 RTC Seconds Alarm Register
The real-time clock seconds alarm (ALRM_SEC) register is used to configure the seconds setting for the alarm.
The alarm settings can be read or written at any time.
ALRM_SEC
Addr
0x0020400C
RTC Seconds Alarm Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SECONDS
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-8. RTC Seconds Alarm Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
SECONDS
Bits 6–0
Seconds Setting of the Alarm—Indicates the current
seconds setting of the alarm.
Settings
SECONDS can be set to any value between 0
and 59.
MC9328MXS Reference Manual, Rev. 1.1
18-10
Freescale Semiconductor
Programming Model
18.2.7 RTC Control Register
The real-time clock control (RTCCTL) register is used to enable the real-time clock module and specify the
reference frequency information for the prescaler.
RCCTL
Addr
0x00204010
RTC Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
EN
TYPE
XTL
SWR
r
r
r
r
r
r
r
r
rw
rw
rw
r
r
r
r
rw
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
RESET
0x0080
Table 18-9. RTC Control Register Description
Name
Description
Settings
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
EN
Bit 7
Enable—Enables/Disables the real-time clock. The software
reset bit (SWR) has no effect on this bit.
0 = Disable the real-time clock
1 = Enable the real-time clock
XTL
Bits 6–5
Crystal Selection—Selects the proper input crystal frequency.
It is important to set these bits correctly or the real-time clock
will be inaccurate.
00 = 32.768 kHz
01 = 32 kHz
11 = 32.768 kHz
Reserved
Bits 4–1
Reserved—These bits are reserved and should read 0.
SWR
Bit 0
Software Reset—Resets the module to its default state.
However, a software reset will have no effect on the clock
enable (EN) bit.
0 = No effect.
1 = Reset the module to its default state.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
18-11
Programming Model
18.2.8 RTC Interrupt Status Register
The real-time clock interrupt status register (RTCISR) indicates the status of the various real-time clock interrupts,
except for the 2Hz bit. When an event of the types included in this register occurs, if the corresponding bit in the
RTC Interrupt Enable Register (RTCIENR) is set, then the bit will be set in this register. These bits are cleared by
writing a value of 1, which also clears the interrupt. Interrupts may occur when the system clock is idle or in sleep
mode. For more information about the frequency of the sampling timer interrupts (SAM7-SAM0), refer to Table
18-1.
RTCISR
Addr
0x00204014
RTC Interrupt Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
HR
1HZ
DAY
ALM
MIN
SW
RESET
0x0000
BIT
15
SAM7
TYPE
14
13
12
11
10
9
8
SAM6 SAM5 SAM4 SAM3 SAM2 SAM1 SAM0
2HZ
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-10. RTC Interrupt Status Register Description
Name
Description
Settings
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
SAM7
Bit 15
Sampling Timer Interrupt Flag at SAM7 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 512,
500, or 600 Hz. The actual rate of the interrupt depends on the input clock
value. See Table 18-1.
0 = No SAM7 interrupt occurred
1 = A SAM7 interrupt occurred
SAM6
Bit 14
Sampling Timer Interrupt Flag at SAM6 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 256,
250, or 300 Hz. The actual rate of the interrupt depends on the input clock
value. See Table 18-1.
0 = No SAM6 interrupt occurred
1 = A SAM6 interrupt occurred
SAM5
Bit 13
Sampling Timer Interrupt Flag at SAM5 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 128,
125, or 150 Hz. The actual rate of the interrupt depends on the input clock
value. See Table 18-1.
0 = No SAM5 interrupt occurred
1 = A SAM5 interrupt occurred
SAM4
Bit 12
Sampling Timer Interrupt Flag at SAM4 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 64,
62.5, or 75 Hz. The actual rate of the interrupt depends on the input clock
value. See Table 18-1.
0 = No SAM4 interrupt occurred
1 = A SAM4 interrupt occurred
MC9328MXS Reference Manual, Rev. 1.1
18-12
Freescale Semiconductor
Programming Model
Table 18-10. RTC Interrupt Status Register Description (continued)
Name
Description
Settings
SAM3
Bit 11
Sampling Timer Interrupt Flag at SAM3 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 32,
31.25, or 37.5 Hz. The actual rate of the interrupt depends on the input clock
value. See Table 18-1.
0 = No SAM3 interrupt occurred
1 = A SAM3 interrupt occurred
SAM2
Bit 10
Sampling Timer Interrupt Flag at SAM2 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 16,
15.625, or 18.75 Hz. The actual rate of the interrupt depends on the input
clock value. See Table 18-1.
0 = No SAM2 interrupt occurred
1 = A SAM2 interrupt occurred
SAM1
Bit 9
Sampling Timer Interrupt Flag at SAM1 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 8,
7.8125, or 9.375 Hz. The actual rate of the interrupt depends on the input
clock value. See Table 18-1.
0 = No SAM1 interrupt occurred
1 = A SAM1 interrupt occurred
SAM0
Bit 8
Sampling Timer Interrupt Flag at SAM0 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 4,
3.90625, or 4.6875 Hz. The actual rate of the interrupt depends on the input
clock value. See Table 18-1.
0 = No SAM0 interrupt occurred
1 = A SAM0 interrupt occurred
2HZ
Bit 7
2 Hz Flag—Indicates that a 2Hz status event has occurred. If enabled, this
bit is set at intervals of every 2 Hz.
0 = No 2 Hz event occurred
1 = A 2 Hz interval event occurred
Reserved
Bit 6
Reserved—This bit is reserved and should read 0.
HR
Bit 5
Hour Flag—Indicates that the hour counter has incremented. If enabled,
0 = No 1-hour interrupt occurred
this bit is set on every increment of the hour counter in the time-of-day clock. 1 = A 1-hour interrupt occurred
1HZ
Bit 4
1 Hz Flag—Indicates that the second counter has incremented. If enabled,
this bit is set on every increment of the second counter of the time-of-day
clock.
0 = No 1 Hz interrupt occurred
1 = A 1 Hz interrupt occurred
DAY
Bit 3
Day Flag—Indicates that the day counter has incremented. If enabled, this
bit is set on every increment of the day counter of the time-of-day clock.
0 = No 24-hour rollover interrupt
occurred
1 = A 24-hour rollover interrupt
occurred
ALM
Bit 2
Alarm Flag—Indicates that the real-time clock matches the value in the
alarm registers. Note that the alarm will reoccur every 512 days. For a single
alarm, clear the interrupt enable for this bit in the interrupt service routine.
0 = No alarm interrupt occurred
1 = An alarm interrupt occurred
MIN
Bit 1
Minute Flag—Indicates that the minute counter has incremented. If
enabled, this bit is set on every increment of the minute counter in the
time-of-day clock.
0 = No 1-minute interrupt occurred
1 = A 1-minute interrupt occurred
SW
Bit 0
Stopwatch Flag—Indicates that the stopwatch countdown timed out.
0 = The stopwatch did not
time-out.
1 = The stopwatch timed out.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
18-13
Programming Model
18.2.9 RTC Interrupt Enable Register
The real-time clock interrupt enable register (RTCIENR) is used to enable/disable the various real-time clock
interrupts except the 2HZ bit (RTCIENR[7]). When an event of the types included in this register occurs, if that bit
in this register is set, then the corresponding bit will be set in the RTC Interrupt Status Register (RTCISR). For
more information about the frequency of the sampling timer interrupts (SAM7-SAM0), refer to Table 18-1.
RTCIENR
Addr
0x00204018
RTC Interrupt Enable Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
HR
1HZ
DAY
ALM
MIN
SW
RESET
0x0000
BIT
15
SAM7
TYPE
14
13
12
11
10
9
8
SAM6 SAM5 SAM4 SAM3 SAM2 SAM1 SAM0
2HZ
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-11. RTC Interrupt Enable Register Description
Name
Description
Settings
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
SAM7
Bit 15
Sampling Timer Interrupt Flag at SAM7 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 7. The
frequency of this interrupt is shown in Table 18-1.
0 = SAM7 interrupt is disabled
1 = SAM7 interrupt is enabled
SAM6
Bit 14
Sampling Timer Interrupt Flag at SAM6 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 6. The
frequency of this interrupt is shown in Table 18-1.
0 = SAM6 interrupt is disabled
1 = SAM6 interrupt is enabled
SAM5
Bit 13
Sampling Timer Interrupt Flag at SAM5 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 5. The
frequency of this interrupt is shown in Table 18-1.
0 = SAM5 interrupt is disabled
1 = SAM5 interrupt is enabled
SAM4
Bit 12
Sampling Timer Interrupt Flag at SAM4 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 4. The
frequency of this interrupt is shown in Table 18-1.
0 = SAM4 interrupt is disabled
1 = SAM4 interrupt is enabled
SAM3
Bit 11
Sampling Timer Interrupt Flag at SAM3 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 3. The
frequency of this interrupt is shown in Table 18-1.
0 = SAM3 interrupt is disabled
1 = SAM3 interrupt is enabled
SAM2
Bit 10
Sampling Timer Interrupt Flag at SAM2 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 2. The
frequency of this interrupt is shown in Table 18-1.
0 = SAM2 interrupt is disabled
1 = SAM2 interrupt is enabled
MC9328MXS Reference Manual, Rev. 1.1
18-14
Freescale Semiconductor
Programming Model
Table 18-11. RTC Interrupt Enable Register Description (continued)
Name
Description
Settings
SAM1
Bit 9
Sampling Timer Interrupt Flag at SAM1 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 1. The
frequency of this interrupt is shown in Table 18-1.
0 = SAM1 interrupt is disabled
1 = SAM1 interrupt is enabled
SAM0
Bit 8
Sampling Timer Interrupt Flag at SAM0 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 0. The
frequency of this interrupt is shown in Table 18-1.
0 = SAM0 interrupt is disabled
1 = SAM0 interrupt is enabled
2HZ
Bit 7
2 Hz Interrupt Enable—Enables/Disables the 2 Hz bit at a 2 Hz rate.
0 = The 2 Hz clock is disabled
1 = The 2 Hz clock is enabled
Reserved
Bit 6
Reserved—This bit is reserved and should read 0.
HR
Bit 5
Hour Interrupt Enable—Enables/Disables an interrupt whenever the
hour counter of the real-time clock increments.
0 = The 1-hour interrupt is disabled
1 = The 1-hour interrupt is enabled
1HZ
Bit 4
1 Hz Interrupt Enable—Enables/Disables an interrupt whenever the
second counter of the real-time clock increments.
0 = The 1 Hz interrupt is disabled
1 = The 1 Hz interrupt is enabled
DAY
Bit 3
Day Interrupt Enable—Enables/Disables an interrupt whenever the
hours counter rolls over from 23 to 0 (midnight rollover).
0 = The 24-hour interrupt is disabled
1 = The 24-hour interrupt is enabled
ALM
Bit 2
Alarm Interrupt Enable—Enables/Disables the alarm interrupt.
0 = The alarm interrupt is disabled
1 = The alarm interrupt is enabled
MIN
Bit 1
Minute Interrupt Enable—Enables/Disables an interrupt whenever the
minute counter of the real-time clock increments.
0 = The 1-minute interrupt is disabled
1 = The 1-minute interrupt is enabled
SW
Bit 0
Stopwatch Interrupt Enable—Enables/Disables the stopwatch
interrupt.
0 = Stopwatch interrupt is disabled
1 = Stopwatch interrupt is enabled
Note: The stopwatch counts down and remains at decimal -1 until it is
reprogrammed. If this bit is enabled with -1 (decimal) in the STPWCH
register, an interrupt will be posted on the next minute tick.
18.2.10 Stopwatch Minutes Register
The stopwatch minutes (STPWCH) register contains the current stopwatch countdown value. When the
minute counter of the TOD clock increments, the value in this register decrements.
STPWCH
Addr
0x0020401C
Stopwatch Minutes Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
CNT
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
RESET
0x003F
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
18-15
Programming Model
Table 18-12. Stopwatch Minutes Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
CNT
Bits 5–0
Stopwatch Count—Contains the stopwatch countdown value.
Note: The stopwatch counter is decremented by the minute (MIN)
tick output from the real-time clock, so the average tolerance of the
count is 0.5 minutes. For better accuracy, enable the stopwatch by
polling the MIN bit of the RTCISR register or by polling the minute
interrupt service routine.
Settings
These bits can be set to any
value between 0 and 62.
When the countdown has
completed, the value will not
change until a nonzero
value (1–62) is written.
MC9328MXS Reference Manual, Rev. 1.1
18-16
Freescale Semiconductor
Chapter 19
SDRAM Memory Controller
This chapter describes the SDRAM controller (SDRAMC) on the MC9328MXS.
19.1 Features
The SDRAM Controller includes these distinctive features:
•
Supports 4 banks of 64-, 128-, or 256-Mbit synchronous DRAMs
•
Includes 2 independent chip-selects
— Up to 64 Mbyte per chip-select
— Up to four banks simultaneously active per chip-select
— JEDEC standard pinout and operation
•
Supports Micron SyncFlash® SDRAM-interface burst flash memory
— Boot capability from CSD1
•
Supports burst reads of word (32-bit) data types
•
PC100 compliant interface
— 100 MHz system clock achievable with “-8” option PC100 compliant memories
— single and fixed-length (8-word) word access
— Typical access time of 8-1-1-1 at 100 MHz
•
Software configurable bus width, row and column sizes, and delays for differing system requirements
•
Built in auto-refresh timer and state machine
•
Hardware supported self-refresh entry and exit which keeps data valid during system reset and low-power
modes
•
Auto-powerdown (clock suspend) timer
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-1
Block Diagram
19.2 Block Diagram
Figure 19-1 is a block diagram of the SDRAM Controller.
i.MX BGA Contact
p_addr[25:21]
p_addr[12:9]
p_addr [31:0]
Row / Column
Address Mux
Page and Bank
Address
Comparators
SDBA[4:0]
A[15:11]
SDIBA [3:0]
A[19:16]
MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
bootmod[1:0]
p_data[31:0]
Configuration
Registers
clk32
DQM3
DQM2
DQM1
DQM0
Refresh
Request
Counter
Powerdown
Timer
SDRAM
Command
Controller
m_rst
sd_rst
p_lpmd[1:0]
DQM3
DQM2
DQM1
DQM0
CSD0
CSD1
CS2
CS3
RAS
CAS
SDWE
RAS
CAS
SDWE
SDCKE0
SDCKE1
SDCLK
SDCKE0
SDCKE1
SDCLK
RESET_SF
sd_lpack
sf_wack
prefetch
x1clk
AHB BUS
RESET_SF
p_data[31:0]
bigendian
Data
Aligner
Mux
DQ[31:0]
D[31:0]
Figure 19-1. SDRAM Controller Block Diagram
MC9328MXS Reference Manual, Rev. 1.1
19-2
Freescale Semiconductor
Functional Overview
19.3 Functional Overview
The SDRAM Controller consists of 7 major blocks, including the SDRAM command controller, page and bank
address comparators, row and column address multiplexer, data aligner–multiplexer, configuration registers,
refresh request counter, and the powerdown timer.
19.3.1 SDRAM Command Controller
The command controller handles the majority of the actions within the SDRAM controller including sequencing
accesses to the memories, initializing the DRAM, keeping track of active banks within each memory region,
scheduling refresh operations, transitioning into and out of low-power modes, and controlling the address and data
multiplexers.
19.3.2 Page and Bank Address Comparators
There are a total of 8 address comparators. Each chip-select has a unique comparator for each of its four banks. The
comparators are used to determine if a requested access falls within the address range of a currently active DRAM
page.
19.3.3 Row and Column Address Multiplexer
All synchronous DRAMs incorporate a multiplexed address bus, although the address folding points vary
according to memory density, data I/O size, and processor data bus width. The address folding point is described as
the point where the column address bits end and the row (or bank) address begin. The SDRAM Controller takes
these variables into account and provides the proper alignment of the multiplexed address through the row and
column address multiplexer, non-multiplexed address pins, and the connections between the controller and the
memory devices.
19.3.4 Data Aligner and Multiplexer
The data alignment block is responsible for aligning the data between the internal AHB bus and the external
memory device(s) including little endian byte swapping.
19.3.5 Configuration Registers
Configuration registers determine the operating mode of the SDRAM Controller by selecting memory device
density and bus width, the number of memory devices, CAS latency, row-to-column delay, and the burst length.
Enable bits are provided for refresh and the auto-powerdown timer. Control bits provide a mechanism for
software-initiated SDRAM initialization, SDRAM mode register settings, and all bank precharge and auto-refresh
cycles.
19.3.6 Refresh Request Counter
SDRAM memories require a periodic refresh to retain data. The refresh request counter generates requests to the
SDRAM Command Controller to perform these refresh cycles. Requests are scheduled according to a 32 kHz clock
input with 1, 2, or 4 refresh cycles generated per clock.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-3
Functional Overview
19.3.7 Powerdown Timer
The powerdown timer detects periods of inactivity to the SDRAM and disables the clock when the inactive period
surpasses the selected time-out. Data is retained during the powerdown state. Subsequent requests to the SDRAM
incur only a minimal added start-up delay (beyond the normal access time). The powerdown timer may be
programmed to expire anytime the controller is not actively reading or writing the memory, after 64 or 128 clocks
of inactivity, or may be disabled entirely.
19.3.8 DMA Operation with the SDRAM Controller
The DMA controller has the capability to perform burst transfers (reads and writes) of byte and half word data
types while the SDRAM controller support is restricted to internal AHB burst transfers of word (32-bit) data types.
Therefore, when using the DMA in conjunction with the SDRAM controller, ensure that all burst transfers to or
from the SDRAM controller are of word data types. This is configured in the DMA Channel Control register.
When choosing SDRAM memory as the source address, set the Source Size bits as a 32-bit port, and likewise when
setting up the destination address. Refer to the “Chapter 13, “DMA Controller,” for more details.
This section discusses input and output signals between the SDRAM Controller and the external memory devices.
Other than the chip-select outputs (CSD0 / CSD1) and clock enables (SDCKE0 / SDCKE1), all signals are shared
between the two chip-select regions. The interface signals are summarized in Table 19-1 and detailed in
Section 19.3.9 through Section 19.3.19. Interconnect and timing diagrams are included as part of the detailed
discussion on controller operation in Section 19.5, “Operating Modes.”
All external interface signals are referenced to the SDRAM clock, SDCLK.
Table 19-1. AHB Bus and Internal Interface Signals
Name
clk32
sf_wack
DQ [31:0]
Function
Direction
32.0 kHz Clock Reference
Input
WMIMI bus time-out suppression for SyncFlash low-power mode wake-up
Output
Internal data I/O bus
I/O
Table 19-2. SDRAM Interface Characteristics
SDRAMC Signal Name
BGA Contact Name
SDCLK
SDCLK
SDCKE0
Function
Direction
Reset State
Clock to SDRAM
Output
Enabled
SDCLKE0
Clock enable to SDRAM 0
Output
High
SDCKE1
SDCLKE1
Clock enable to SDRAM 1
Output
High
CSD0
CS2
Chip-select to SDRAM array 0
Output
High
CSD1
CS3
Chip-select to SDRAM array 1
Output
High
MA [11:10]
MA [11:10]
Multiplexed Address
Output
Low
MA [9:0]
A [10:1]
Multiplexed Address
Output
Low
SDBA [4:0] / A [25:21]
A [15:11]
Non-multiplexed Address
Output
Low
SDIBA [3:0] / A [12:9]
A [19:16]
Non-multiplexed Address
Output
Low
DQM3
DQM3
Data Qualifier Mask byte 3 (D [31:24])
Output
Low
MC9328MXS Reference Manual, Rev. 1.1
19-4
Freescale Semiconductor
Functional Overview
Table 19-2. SDRAM Interface Characteristics (continued)
SDRAMC Signal Name
BGA Contact Name
Function
Direction
Reset State
DQM2
DQM2
Data Qualifier Mask byte 2 (D [23:16])
Output
Low
DQM1
DQM1
Data Qualifier Mask byte 1 (D [15:8])
Output
Low
DQM0
DQM0
Data Qualifier Mask byte 0 (D [7:0])
Output
Low
DQ[31:0]
D[31:0]
Data bus
I/O
High
SDWE
SDWE
Write Enable
Output
High
RAS
RAS
Row Address Strobe
Output
High
CAS
CAS
Column Address Strobe
Output
High
RESET_SF
RESET_SF
SyncFlash Reset/Powerdown
Output
Low
19.3.9 SDCLK—SDRAM Clock
The SDCLK output provides the timing reference for the memory devices. All other SDRAM interface signals are
referenced to this clock. SDCLK is synchronous to the system clock, however it is gated off during low-power
operating modes when both SDCKE0 and SDCKE1 are negated.
19.3.10 SDCKE0, SDCKE1—SDRAM Clock Enables
The SDCKE0 and SDCKE1 pins are clock enable outputs to the SDRAM memory devices. SDCKE0 corresponds
to SDRAM array 0 and SDCKE1 to SDRAM array 1. When these pins are asserted high, the memory’s clock input
is active, which means that a stable clock is being supplied. The low assertion deactivates the memory’s clock
input. A low assertion of SDCKEx initiates Powerdown, Self Refresh, and Suspend modes to the SDRAM.
19.3.11 CSD0, CSD1—SDRAM Chip-Select
CSD0 and CSD1 are used to select SDRAM array 0 and SDRAM array 1, respectively. When a valid command is
present on the other control signals, the chip-select signals are used to indicate which device the command is
directed towards.
19.3.12 DQ [31:0]—Data Bus (Internal)
The 32 data lines are used to transfer data between the SDRAM Controller and memory. Data bit 31 is the most
significant bit and bit 0 is the least significant.
19.3.13 MA [11:0]—Multiplexed Address Bus
The multiplexed address bus specifies the SDRAM page and the location within the page targeted by the current
access. The multiplexed address pins are used in conjunction with some of the non-multiplexed ARM920T
processor address signals to comprise the complete SDRAM address. Connections between the SDRAM
Controller and memory vary depending on the SDRAM device density. See Section 19.6.1, “Address
Multiplexing,” on page 19-29 and specifically Table 19-20 and Table 19-22 for details on supported SDRAM
configurations.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-5
Functional Overview
19.3.14 SDBA [4:0], SDIBA [3:0]—Non-Multiplexed Address Bus
The non-multiplexed address pins specify the SDRAM bank to which the current command is targeted. In some
density or width configurations, these pins also supply the most significant bits of the row address. Table 19-20 on
page 19-46 and Table 19-21 on page 19-47 document which address pins are used for any given configuration.
19.3.15 DQM3, DQM2, DQM1, DQM0—Data Qualifier Mask
During read cycles, the DQMx pins control the SDRAM data output buffers. DQMx asserted high disables the
output buffers leaving them in a high-impedance state. DQMx asserted low allows the data buffers to drive
normally.
During write cycles, DQMx controls which bytes are written in the SDRAM. DQMx asserted low enables a write
to the corresponding byte, whereas DQMx asserted high leaves the byte unchanged.
DQM3 corresponds to the most significant byte and DQM0 to the least significant. Sixteen bit memories require
only two DQM connections. Memories aligned to the upper data bus (D [31:16]) connect to DQM3 and DQM2,
while memories aligned to the lower data bus (D [15:0]) connect to DQM1 and DQM0. Memory alignment is
selected in the SDCTLx Registers.
19.3.16 SDWE—Write Enable
Write enable is part of the three bit command field (RAS and CAS make up the other two bits) used by the
SDRAM. Generally, SDWE will be asserted low if a command transfers data to the memory. A detailed summary
of the supported SDRAM commands is provided in Table 19-50 on page 19-71.
19.3.17 RAS—Row Address Strobe
Row address strobe is also part of the SDRAM command field. It is generally used to indicate an operation
affecting an entire bank or row. When RAS is asserted (low), a new SDRAM row address must be latched.
Table 19-50 on page 19-71 provides details on SDRAM command encoding.
19.3.18 CAS—Column Address Strobe
The column address strobe is the third signal comprised in the command field. It generally signifies a column
oriented command. When CAS is asserted (low), the column address has changed. Table 19-50 on page 19-71
provides details on SDRAM command encoding.
19.3.19 RESET_SF—Reset or Powerdown
This output signal is only used for SyncFlash memories. When asserted low, the SyncFlash memory state machines
are reset and the device is placed in the lowest power operating mode. Bringing this signal high returns the device
to a normal operating condition, ready to accept commands following a stabilization delay.
Three conditions force the RESET_SF pin to be asserted: SDRAM reset (SD_RST), disabling the chip-select via
the SDE bit in the SDCTL1 control register, and entering one of the low-power modes. In each case, the system
integrator must guarantee that the SyncFlash stabilization period between RESET_SF negation and the first access
to the device has been met.
MC9328MXS Reference Manual, Rev. 1.1
19-6
Freescale Semiconductor
Functional Overview
NOTE:
Programming hardware-protected blocks within the SyncFlash requires RESET_SF
to be raised to 5V +/-10%. This feature is not supported by the SDRAM Controller.
19.3.20 Pin Configuration for SDRAMC
Table 19-3 lists the pins used for the SDRAM controller. These pins are multiplexed with other functions on the
device, and must be configured for SDRAM operation.
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 25.5.1, “Data Direction Registers,” on
page 25-8 for details.
Table 19-3. Pin Configuration
Pin
Setting
Set-Up Procedure
SDCLK
Not multiplexed
SDCKE0
Not multiplexed
SDCKE1
Not multiplexed
CSD0
Alternate function of CS2/CSD0 pin
Set bit 0 (SDCS0_SEL) in the Function Multiplexing Control register of
the System Control module.
CSD1
Alternate function of CS3/CSD1 pin
Set bit 1 (SDCS1_SEL) in the Function Multiplexing Control register of
the System Control module.
MA [11:10]
Not multiplexed
MA [9:0]
Multiplexed with A [10:1]
Internal signal from SDRAMC, asserted for SDRAM accesses
SDBA [4:0]
Multiplexed with A [15:11]
Internal signal from SDRAMC, asserted for SDRAM accesses
SDIBA [3:0]
Multiplexed with A [19:16]
Internal signal from SDRAMC, asserted for SDRAM accesses
DQM3
Not multiplexed
DQM2
Not multiplexed
DQM1
Not multiplexed
DQM0
Not multiplexed
SDWE
Not multiplexed
RAS
Not multiplexed
CAS
Not multiplexed
RESET_SF
Not multiplexed
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-7
Programming Model
19.4 Programming Model
The SDRAM controller includes four 32-bit registers. Table 19-4 summarizes these registers and their addresses.
Registers are accessible in supervisor mode only. Attempts to access the registers in user mode will result in a
transfer error (TEA) being returned on the ARM920T processor’s local bus.
Table 19-4. SDRAM Module Register Memory Map
Description
Name
Address
SDRAM 0 Control Register
SDCTL0
0x00221000
SDRAM 1 Control Register
SDCTL1
0x00221004
SDRAM Reset Register
SDRST
0x00221018
Miscellaneous Register
MISCELLANEOUS
0x00221014
The SDRAM arrays are mapped according to Table 19-5. A 64 Mbyte space is allocated to each chip-select.
Memories smaller than the allocated region are redundantly mapped throughout the remainder of the region.
Attempted accesses to a disabled chip-select region (SDE bit of the SDCTLx = 0) and User accesses to a protected
(SP bit of the SDCTL = 1) region will result in a transfer error.
Table 19-5. SDRAM Array Memory Map
Address
Use
Access
0x0800 0000 – 0x0BFF FFFF
SDRAM 0 Memory array
R/W
0x0C00 0000 – 0x0FFF FFFF
SDRAM 1 Memory array
R/W
MC9328MXS Reference Manual, Rev. 1.1
19-8
Freescale Semiconductor
Programming Model
19.4.1 SDRAM Control Registers
There are two SDRAM Control Registers, one for each of the two memory regions. SDCTL0 defines the operating
characteristics for the SDRAM 0 region (selected by CSD0), while SDCTL1 does the same for the SDRAM 1
region (selected by CSD1). Bit and field assignments within the registers are identical.
SDCTL0
SDCTL1
BIT
SDRAM 0 Control Register
SDRAM 1 Control Register
31
30
SDE
TYPE
Addr
0x00221000
0x00221004
29
28
SMODE
27
26
25
SP
24
23
22
21
ROW
20
COL
19
18
17
IAM
16
DSIZ
rw
rw
rw
rw
rw
r
rw
rw
r
r
rw
rw
rw
r
rw
rw
0*
0
0
0
0
0
0
1
0
0
0
0
0
0
0*
0*
7
6
5
4
3
2
1
0
RESET
0x0100*
BIT
15
14
SREFR
TYPE
13
12
11
10
9
CLKST
8
SCL
SRP
SRCD
SRC
rw
rw
rw
rw
r
r
rw
rw
r
rw
rw
rw
r
rw
rw
rw
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
RESET
0x0300
* For SDCTL1, the reset state is affected by bootmod [1:0]
Table 19-6. SDRAM 0 Control Register and SDRAM 1 Control Register Description
Name
Description
Settings
SDE
Bit 31
SDRAM Controller Enable—Enables/Disables the SDRAM
controller. The module is disabled on reset. For SDRAM 1, if the
selected boot mode is the SyncFlash memory, the module will be
enabled on reset. Disabling the module shuts off all clocks within
the module with the exception of register accesses.
0 = Disabled
1 = Enabled
SMODE
Bits 30–28
SDRAM Controller Operating Mode—Determines the operating
mode of the SDRAM controller. The controller is capable of
operating in six different modes. These modes are primarily used
for SDRAM initialization and programming of the SyncFlash
memory. Any access to the SDRAM memory space, while in one
of the alternate modes, will result in the corresponding special
cycle being run. Moving from Normal to any other mode does not
close (precharge) any banks that may be open (activated). Under
most circumstances, software must run a precharge-all cycle
when transitioning out of Normal Read/Write mode. SyncFlash
command register read/write sequences are the one exception
that does not require a software initiated precharge. Operating
mode details are provided in Section 19.7, “SDRAM Operation,”
and Section 19.8, “SyncFlash Operation.” Reset initializes the
operating mode to “Normal Read/Write”.
000 = Normal Read/Write
001 = Precharge Command
010 = Auto-Refresh Command
011 = Set Mode Register Command
100 = Reserved
101 = Reserved
110 = SyncFlash Load Command Register
111 = SyncFlash Program Read/Write
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-9
Programming Model
Table 19-6. SDRAM 0 Control Register and SDRAM 1 Control Register Description (continued)
Name
Description
SP
Bit 27
Supervisor Protect—Restricts user accesses within the
chip-select region.
Reserved
Bit 26
Reserved—This bit is reserved and should read 0.
ROW
Bits 25–24
Row Address Width—Specifies the number of row addresses
used by the memory array. This number does not include the
bank, column, or data qualifier addresses. Parameters affected
by the programming of this field include the page-hit address
comparators and the bank address bit locations (non-interleaved
mode only).
Reserved
Bits 23–22
Reserved—These bits are reserved and should read 0.
COL
Bits 21–20
Column Address Width—Specifies the number of column
addresses in the memory array and will determine the break point
in the address multiplexer. Column width is the number of
multiplexed column addresses and does not include bank and
row addresses, or addresses used to generate the DQM signals.
Settings
0 = User mode accesses are allowed to this
chip-select region.
1 = User mode accesses are prohibited. An
attempted access to this chip-select
region while in user mode will result in
a BUS ERROR being returned back to
the CPU. The chip-select will not be
asserted. Read Accesses are not
affected.
00 = 11
01 = 12
10 = 13
11 = Reserved
00 = 8
01 = 9
10 = 10
11 = 11
MC9328MXS Reference Manual, Rev. 1.1
19-10
Freescale Semiconductor
Programming Model
Table 19-6. SDRAM 0 Control Register and SDRAM 1 Control Register Description (continued)
Name
IAM
Bit 19
Description
(Bank1) Interleaved Address Mode—Controls bank address
alignment. Bank addresses fall between the row and column
addresses, resulting in an interleaved memory map with the
banks alternately striped through the memory region. They are
more significant than row and column addresses and result in a
linear addressing of the banks through the memory map.
Bank address bit placement has a significant effect on how well
the SDRAM page buffers are used, with a corresponding impact
on system performance.
The SDRAM Controller supports two bank address alignments
which will satisfy most system requirements.
See Figure 19-2 for memory bank interleaving options.
Note: Memory address linearity is of little concern to the user
when the memory is comprised of RAM devices, however, it is of
utmost importance when the memory is not-volatile and
erase/program is block oriented. Flash memories are an example
of a block oriented memory. Choosing the interleaved (IAM = 1)
address option will generally require the user to erase the
memory in multiples of 4 times the block size (for example, 256k x
4, or 1 Mbyte for the 64 Mbit Micron SyncFlash). Programming
can still occur on a page by page basis, however executing out of
the device being programmed may not be possible because the
code is likely to cross a page boundary into the bank being
programmed. If the device is programmed outside the system, the
data must be shuffled to account for the interleaved blocks. For
these reasons, it is recommended that the user choose linear
addressing (IAM = 0) for block oriented devices.
Settings
0 = Linear Address Map. Addresses flow
through each page in the first bank, into
the second bank, and so on. See
Figure 19-2. Linear Addressing is best
suited to applications with large
continuous blocks of linear accessed
data such as an LCD display buffer.
1 = Interleaved Address Map. Addresses
flow through one page in the first bank,
to one page in the second, to the third,
etc. The banks alternate at each
SDRAM page boundary. See
Figure 19-2. Interleaved Mapping is
better suited for ARM9 code space.
The interleaving of the banks
eliminates the need to continually open
and close pages when loops and LRW
constants cross page boundaries,
resulting in higher system throughput.
Reserved
Bit 18
Reserved—This bit is reserved and should read 0.
DSIZ
Bits 17–16
SDRAM Memory Data Width—Defines the width of the SDRAM
memory and its alignment on the external data bus. 16-bit ports
may be aligned to either the high or low half-word to equalize
capacitive loading on the bus. A hardware reset loads this control
field from the boot source selection (bootmod[1:0]) to the
SDRAM1 control register.
00 = 16-bit aligned to D[31:16]
01 = 16-bit aligned to D[15:0]
1x = 32-bit memory
SREFR
Bits 15–14
SDRAM Refresh Rate—Enables/Disables SDRAM refresh
cycles and controls the refresh rate. Refresh cycles are
referenced to a 32 kHz clock. At each rising edge, 1, 2, or 4 rows
will be refreshed. Multiple refresh cycles are separated by the row
cycle delay specified in the SRC control field.
See Table 19-7 on page 19-13 for bit and
field settings.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-11
Programming Model
Table 19-6. SDRAM 0 Control Register and SDRAM 1 Control Register Description (continued)
Name
Description
CLKST
Bits 13–12
Clock Suspend Time-out—Determines if and when the SDRAM
will be placed in a clock suspend condition. The suspend time-out
can be triggered either on the absence of an active bank also
called Precharge Powerdown (CLKST = 01) or on a clock count
from the last access also called Active Powerdown (CLKST = 10
or 11). Count-based time-outs do not force the SDRAM into an
idle condition (for example, any active banks remain open).
Section 19.6.4, “Clock Suspend Low-Power Mode,” provides a
comprehensive description of this operating mode.
Reserved
Bits 11–10
Reserved—These bits are reserved and should read 0
SCL
Bits 9–8
SDRAM CAS Latency—Determines the latency between a read
command and the availability of data on the bus. This field does
not affect the second and subsequent data words in a burst, and
has no effect on write cycles.
Settings
00 = Disabled
01 = Anytime all banks are inactive
10 = 64 clocks after completion of last
access (Precharge Powerdown).
11 = 128 clocks after completion of last
access (Active Powerdown).
00 = Reserved
01 = 1 clock
10 = 2 clocks
11 = 3 clocks
Note: See Figure 19-3 on page 19-14
CAS Latency Timing diagram.
Reserved
Bit 7
Reserved—This bit is reserved and should read 0.
SRP
Bit 6
SDRAM Row Precharge Delay—Determines the number of idle
clocks inserted between a precharge command and the next-row
activate command to the same bank.
0 = 3 clocks inserted
1 = 2 clocks inserted
SRCD
Bits 5–4
SDRAM Row-to-Column Delay—Determines the number of
clocks inserted between a row activate command and a
subsequent read or write command to the same bank. See
Figure 19-5.
00 = 4 clocks inserted
01 = 1 clock inserted
10 = 2 clocks inserted
11 = 3 clocks inserted
Reserved
Bit 3
Reserved—This bit is reserved and should read 0.
SRC
Bits 2–0
SDRAM Row Cycle Delay—Determines the minimum delay (in
number of clocks) between a refresh and any subsequent refresh
or read/write access. This delay corresponds to the minimum row
cycle time captured in the tRC/tRFC memory timing spec. An
example timing diagram for SRC = 3 can be found in Figure 19-6.
Note: The SRC control field is not used to enforce
tRC timing for row activate to row activate within the same bank.
The sum of tRCD + CAS latency + tRP (reads) and tRCD + tWR + tRP
(writes) must be greater than tRC (SRC).
1.
000 = 8 clocks
001 = 1 clock
010 = 2 clocks
011 = 3 clocks
100 = 4 clocks
101 = 5 clocks
110 = 6 clocks
111 = 7 clocks
Placing the MC9328MXS SDRAM controller in Bank Interleaved mode is not the same as SDRAM Interleaved
mode. For Bank Interleaved mode, the SDRAM memory must be programmed to sequential or linear mode in the
SDRAM mode register.
MC9328MXS Reference Manual, Rev. 1.1
19-12
Freescale Semiconductor
Programming Model
IAM = 0
IAM = 1
Linear Address Map
Interleaved Address Map
Page n
Page n
•••
Page n
Page 1
Page n
Page 0
Page n
Page n
•••
•••
•••
Bank 3
Bank 2
Increasing Addresses
Page 1
Page 0
Page n
•••
•••
•••
Bank 1
Page 1
Page 1
Bank 0
Page 1
Page 1
Page 0
Page 1
Page n
Page 0
•••
Page 0
Page 1
Page 0
Page 0
Page 0
Figure 19-2. Memory Bank Interleaving Options
Table 19-7. Settings for SREFR Field
SREFR
Rows
Each
Refresh
Clock
~Row/64ms
@ 32 kHz
00
Row Rate
@ 32 kHz
~Row/64ms
@
32.768 kHz
Row Rate
@
32.768 kHz
Refresh disabled
01
1
2048
31.25 μs
2097
30.52 μs
10
2
4096
15.62 μs
4194
15.26 μs
11
4
8192
7.81 μs
8388
7.63 μs
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-13
Programming Model
SDCLK
COMMAND
READ
NOP
TLZ
TOH
DQ
DOUT
TAC
CAS Latency = 1
SDCLK
COMMAND
READ
NOP
NOP
TLZ
TOH
DOUT
DATA
TAC
CAS Latency = 2
SDCLK
COMMAND
READ
NOP
NOP
NOP
TLZ
TOH
DOUT
DATA
TAC
CAS Latency = 3
Figure 19-3. CAS Latency Timing
MC9328MXS Reference Manual, Rev. 1.1
19-14
Freescale Semiconductor
Programming Model
PRE
ACT
NOP
tRP = 2
SDCLK
COMMAND
PRE
NOP
ACT
NOP
tRP = 3
Figure 19-4. Precharge Delay Timing
SDCLK
COMMAND
ACTIVE
READ/WRITE
tRCD = 1
SDCLK
COMMAND
ACTIVE
READ/WRITE
NOP
tRCD = 2
SDCLK
COMMAND
ACTIVE
NOP
NOP
READ/WRITE
tRCD = 3
Figure 19-5. Row-to-Column Delay Timing
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-15
Programming Model
SDCLK
COMMAND
REF
NOP
NOP
NOP
REF
NOP
NOP
TRC (SRC = 3)
NOP
ACT
TRC
Figure 19-6. Row Cycle Timing
19.4.2 SDRAM Reset Register
The write-only SDRAM Reset Register controls the reset pulse timing.
SDRST
BIT
Addr
0x00221018
SDRAM Reset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
w
w
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RST
TYPE
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-8. SDRAM Reset Register Description
Name
Description
RST
Bits 31–30
Software Initiated Local Module Reset Bits—Generates local
module reset to SDRAM/SyncFlash controller.
Reserved
Bits 29–0
Reserved—These bits are reserved and should read 0.
Settings
00 = No effect to the SDRAMC
01 = One HCLK cycle reset pulse
10 = One HCLK cycle reset pulse
11 = Two HCLK cycle reset pulse
MC9328MXS Reference Manual, Rev. 1.1
19-16
Freescale Semiconductor
Programming Model
19.4.3 Miscellaneous Register
MISCELLANEOUS
BIT
31
Addr
0x00221014
Miscellaneous Register
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
rw
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
OMA
TYPE
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
RMA0
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-9. Miscellaneous Register Description
Name
Description
Settings
OMA
Bit 31
Multiplexed Address Override—Enables/Disables the MA0 pin to be a
meaningful bit. The multiplexed address, original MA0, is always zero at read
access in 16-bit port memory configuration. This introduces difficulty with the
SyncFlash read-device configuration which requires that the address ranges
from 0 to 3. Working with bit 0 in tandem, this overrides the original MA0
generated by the internal address multiplexer during the 16-bit SyncFlash
read-device configuration command.
0 = Address from internal
address multiplexed is
routed out to MA0
1 = Force RMA0, bit 0, out to
MA0 pin
Reserved
Bits 30–1
Reserved—These bits are reserved and should read 0.
RMA0
Bit 0
MA0 Replacement—Contains value of MA0 when OMA is set.
Code Example 19-1 is a programming example for SyncFlash read-device configurations.
Code Example 19-1. Read-Device
HWSF_read_device_ID
ldr
r2, 0x80000001
//force ma0 to 1
ldr
r8, 0x00221014
str
r2,(r8)
ldr
ldrh
ldr
cmp
bt
r8, 0x0c000000
r2, (r8,0)
r1, 0x00d3
r1, r2
ERROR_OUT
//read SyncFlash device ID
ldr
ldr
str
r2, 0x00000000
r8, 0x00221014
r2,(r8)
//release ma0
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-17
Operating Modes
19.5 Operating Modes
Each of the SDRAM Controller operating modes is described in this section, including details on basic operation,
relationship to SDRAM/SyncFlash operating modes, and any special precautions to observe. State and timing
diagrams are included where appropriate.
19.5.1 SDRAM and SyncFlash Command Encoding
Table 19-10 summarizes the command encodings used by the SDRAM controller. This command list is a subset of
the commands defined by the JEDEC standard. Note that the SDRAM Auto, Self-Refresh, and SyncFlash Load
Command register commands share the same encoding. Also note, that encodings are based from the view of the
SDRAM memory to the controller, and therefore use SDRAM signal names. See Figure 19-46 on page 19-51 for
an example.
Table 19-10. SDRAM and SyncFlash Command Encoding
Function
Symbol
CKEn-1
CKEn
CS
RAS
CAS
WE
A11
A10
BA[1:0]
A[9:0]
Deselect
DSEL
H
X
H
X
X
X
X
X
X
X
No operation
NOP
H
X
L
H
H
H
X
X
X
X
Read
READ
H
X
L
H
L
H
V
L
V
V
Write
WRIT
H
X
L
H
L
L
V
L
V
V
Bank activate
ACT
H
X
L
L
H
H
V
V
V
V
Burst terminate
TBST
H
X
L
H
H
L
X
X
V
X
Precharge select bank
PRE
H
X
L
L
H
L
X
L
V
X
Precharge all banks
PALL
H
X
L
L
H
L
X
H
X
X
Auto-refresh
CBR
H
X
L
L
L
H
X
X
X
X
SyncFlash load
command register
LCR
H
X
L
L
L
H
X
X
V
V
Self refresh entry
SLFRSH
H
L
L
L
L
H
X
X
X
X
Self refresh exit
SLFRSHX
L
H
H
X
X
X
X
X
X
X
Power-down entry
PWRDN
H
L
X
X
X
X
X
X
X
X
Power-down exit
PWRDNX
L
H
H
X
X
X
X
X
X
X
Mode register set
MRS
H
X
L
L
L
L
L
L
V
V
Assertion of the sd_rst signal initializes the controller into the idle state. As long as the SDRAM Controller is not
the boot source, that assertion also disables the module. While disabled, the controller remains in the idle state with
the internal clocks stopped.
If the SDRAM Controller has been selected as the boot device, then the module is enabled following reset. The
reset state of the control register allows for basic read/write operations sufficient to fetch the reset vector and
execute the initialization code. A complete initialization of the controller must be performed as part of the start-up
code sequence.
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Operating Modes
Read/write cycles, refresh and low-power mode requests, and clock suspend time-outs will all trigger transitions
out of the idle state. State transitions due to a read or write request depend on the operating mode. Other transitions
require the corresponding function to be enabled in the SDCTL register. Some state transitions have been removed
to minimize complexity and allow an easier understanding of the basic controller operation.
The following subsections document the operation of each of the operating modes.
19.5.2 Normal Read/Write Mode (SMODE = 000)
The Normal Read/Write mode (SMODE = 000) is used for general read and write access to the SDRAM controller,
and for reads of the SyncFlash. SyncFlash writes use the SyncFlash Program mode (See Section 19.5.7,
“SyncFlash Program Mode.” ) Both single and burst accesses are supported, although burst requests are limited to
a length of 8 words (one word = 32 bits).
Read or write requests to the SDRAM Controller initiate a check to see whether the page is already open. This
check consists of comparing the request address against the last row accessed within the corresponding bank. If the
rows are different, it indicates that a precharge has occurred after the last access, or there has never been an access
to the bank. In that case, the access must follow the “off-page” sequence. If the requested row and last row match,
the shorter “on-page” access is used.
An off-page sequence must first activate the requested row, an operation which is analogous to a conventional
DRAM RAS cycle. An activate cycle is the first operation depicted in Figure 19-7. During the activate cycle, the
appropriate chip-select is driven low, the row addresses are placed on the multiplexed address pins, the
non-multiplexed addresses are driven to their respective values, write enable is driven high, CAS is driven high,
and RAS is driven low. These latter three pins form the SDRAM command word. The data bus is unused during
the activate command.
When the selected row has been activated, the read operation begins after the row-to-column delay (tRCD) has been
met. This delay is either 2 or 3 clocks, as determined by the SRCD field of the appropriate control register. During
the read cycle, the chip-select is once again asserted, the column addresses are driven onto the multiplexed address
bus, the non-multiplexed addresses remain driven to the value presented during the activate cycle, the write enable
is driven high, RAS is driven high, and CAS is driven low. After the CAS latency has expired, data is transferred
across the data bus. CAS latency is programmable via the SCL field of the control register. As data is being
returned across the AHB, transfer acknowledge is asserted back to the CPU indicating that the CPU must latch
data. While data is still on the bus, the SDRAM Controller must begin monitoring transfer requests because the
CPU is free to issue the next bus request on the same edge that data is being latched.
Data transfers can be either single operand or a burst of up to 8 operands. Burst requests are designated as such by
the P_BURST attribute. It is activated by the load multiple command from the ARM920T core when the data or
instruction cache is enabled. This AHB signal is asserted low for all except the last operand of a burst transfer.
Non-burst transfers do not assert the signal.
SDRAM memories assume that all transfers are burst transfers unless terminated early. Burst transfers can be
terminated by a variety of mechanisms: another read or write cycle, a precharge operation, or a burst terminate
command. Burst terminate commands are the general mechanism used by the SDRAM controller for early burst
termination. The burst terminate command is subject to the CAS latency and must be pipelined similar to the Read
command, as shown in Figure 25-7 and Figure 25-8. When a load-multiple command is executed, the SDRAM
controller will not issue a burst terminate command.
SDRAM write cycles are different than read cycles in one important aspect. Whereas read data was delayed by the
CAS latency, write data has no delay and is supplied at the same time as the Write command. Figure 25-13
illustrates an off-page write cycle followed by an on-page write cycle. Note that the write data is driven during the
same clock that the Write command is issued. The SDRAM controller only supports single burst writes and does
not issue a burst terminate after each write. Therefore, the user must make sure to program the SDRAM memory’s
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Freescale Semiconductor
19-19
Operating Modes
mode control register for single burst writes for proper operation. The SDRAM controller does, however, have the
capability to issue “single-clock-cycle” writes. This is different than the traditional burst writes, where the WRITE
command and column address are presented on the bus during the first write data, and the SDRAM memory
internally increments its address. In the case of the MC9328MXS, each data to be written to the SDRAM is
accompanied with both the WRITE command and the associated column address that is being written to. This still
achieves the same bandwidth that the burst write would. However, to take advantage of this feature, the data cache
of the ARM920T core must be enabled and the MMU set up with a page table such that the desired region of the
SDRAM memory map is cacheable. Also, the SDRAM controller does not issue a burst terminate command after
the end of a series of burst write, it simply discontinues the WRITE command.
SDCLK
ADDR
ROWA
COLA
COLA
tRCD Minimum
RAS,
CAS,
SDWE
ACT
COLB
tCL
READ
TBST
NOP
NOP
NOP
READ
CSDx
DATA
DATAA
Figure 19-7. Off-Page Single Read Timing Diagram (32-Bit Memory)
SDCLK
ADDR
COLUMNA
COLUMNA
COLUMNB
CAS Latency
RAS,
CAS,
SDWE
READ
TBST
NOP
NOP
NOP
READ
CSDx
DATA
DATAA
Figure 19-8. On-Page Single Read Timing Diagram (32-Bit Memory)
MC9328MXS Reference Manual, Rev. 1.1
19-20
Freescale Semiconductor
Operating Modes
SDCLK
ADDR
RAS,
CAS,
SDWE
ROWA
COLA
tRCD Minimum
ACT
COLB
CAS Latency = 2
READ
NOP
NOP
NOP
NOP
READ
DATAA1
DATAA2
DATAA3
CSDx
DATA
DATAA4
Figure 19-9. Off-Page Burst Read Timing Diagram (32-Bit Memory)
SDCLK
ADDR
COLa
RAS,
CAS,
SDWE
READ NOP NOP NOP NOP NOP NOP NOP NOP READ TBST NOP NOP
COLb
CAS Latency
CAS Latency
CSDx
DATA
Db1
Da1 Da2 Da3 Da4
Figure 19-10. On-Page Burst Read Timing Diagram (32-Bit Memory)
SDCLK
ADDR
ROWA
RAS,
CAS,
SDWE
ACT
COLUMNA
COLUMNB
WRIT
WRIT
DATAA
DATAB
tRCD
CSDx
DATA
Figure 19-11. Off-Page Write Followed by On-Page Write Timing Diagram
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-21
Operating Modes
SDCLK
ROWn
ADDR
COL1n
COL2n
COL3n
COL4n
WRIT
WRIT
WRIT
WRIT
D1n
D2n
D3n
D4n
tRCD
ACT
RAS, CAS, SDWE
NOP
CSDx
DATA
Figure 19-12. Off-Page Burst Write Timing Diagram
SDCLK
COL1n
ADDR
WRIT
RAS, CAS, SDWE
COL2n
COL3n
COL4n
WRIT
WRIT
WRIT
D2n
D3n
D4n
NOP
CSDx
D1n
DATA
Figure 19-13. On-Page Burst Write Timing Diagram
SDCLK
ADDR
ROW
BANK, COL1
BANK, COL2
tRCD
RAS,
CAS,
SDWE
ACT
NOP
WRIT
NOP
READ
TBST
CAS Latency
CSDx
DATA
D1
D2
Figure 19-14. Single Write Followed by On-Page Read Timing Diagram
MC9328MXS Reference Manual, Rev. 1.1
19-22
Freescale Semiconductor
Operating Modes
SDCLK
ADDR
COL1n
ROWn
COLb
COL2n COL3n COL4n
tRCD
RAS, CAS, SDWE
ACT
NOP WRIT WRIT WRIT WRIT NOP READ TBST
CAS Latency
CSDx
DATA
D1n
D2n
D3n
D4n
D1b
Figure 19-15. Burst Write Followed by On-Page Read Timing Diagram
SDCLK
ADDR
COLn
ROWn
COLb
tRCD
RAS,
CAS,
SDWE
ACT
NOP
READ
TBST
NOP
NOP
NOP
WRIT
NOP
CAS Latency
CSDx
DATA
D1n
D2b
Figure 19-16. Single Read Followed by On-Page Write Timing Diagram
SDCLK
ADDR
COLb
COL1n
ROWn
tRCD
RAS, CAS, SDWE
ACT
NOP READ NOP NOP NOP NOP NOP NOP NOP NOP NOP WRIT NOP
CAS Latency
CSDx
DATA
D1n
D2n
D3n
D4n
D1b
Figure 19-17. Burst Read Followed by On-Page Write Timing Diagram
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Freescale Semiconductor
19-23
Operating Modes
19.5.3 Precharge Command Mode (SMODE = 001)
The Precharge Command Mode (SMODE = 001) is used during SDRAM device initialization, and to manually
deactivate any and all active banks. While in this mode, an access (either read or write) to the SDRAM address
space will generate a precharge command cycle. SDRAM address bit A10 determines whether a single bank, or all
banks, are precharged by the command. (See Figure 19-18). Accessing an address with the SDRAM address A10
low will precharge only the bank selected by the bank address. Conversely, accesses with A10 high will precharge
all banks regardless of the bank address. Note that A10 is the SDRAM pin, not the ARM920T processor’s address.
Translation of the SDRAM A10 address bit to the corresponding ARM920T processor’s address is dependent on
the memory configuration. The precharge command access is two clocks in length on the AHB, and one cycle to
the SDRAM controller.
SDCLK
ADDR
SDRAMx,
SDRAMx
with A10-0
Row
tRP Min applies only to same bank.
RAS,
CAS,
SDWE
PRE
NOP
NOP
NOP
ACT
CSDx
DATA
Figure 19-18. Precharge Bank Timing Diagram
SDCLK
ADDR
SDRAMx
with A10 = 1
SDRAMx
Row
tRP Min
RAS,
CAS,
SDWE
PRE
NOP
NOP
NOP
ACT
CSDx
DATA
Figure 19-19. Precharge All Timing Diagram
MC9328MXS Reference Manual, Rev. 1.1
19-24
Freescale Semiconductor
Operating Modes
19.5.4 Auto-Refresh Mode (SMODE = 010)
The Auto-Refresh Mode (SMODE = 010) is used to manually request SDRAM refresh cycles. It is normally used
only during device initialization because the SDRAM Controller will automatically generate refresh cycles when
properly configured. The auto-refresh command refreshes all banks in the device, so the address supplied during
the refresh command only needs to specify the correct SDRAM device. The lower address lines are ignored. Either
a read or write cycle may be used. If a write is used, the data will be ignored and the external data bus will not be
driven. The cycle will be 2 clocks on the AHB and a single clock to the SDRAM device.
The SDRAM Controller guarantees that the SDRAM is in the idle state before the auto-refresh command is given.
If one or more rows are active, a precharge-all command will be issued prior to the auto-refresh command. The
precharge-all command adds one additional clock to the access time.
Figure 19-20 on page 19-25 provides the software initiated Auto-Refresh timing diagram.
SDCLK
SDRAMx
ADDR
SDRAMx
SDRAMx
tRC Minimum
RAS,
CAS,
SDWE
PALL
CBR
NOP
NOP
CBR
NOP
NOP
CSDx
DATA
Figure 19-20. Software Initiated Auto-Refresh Timing Diagram
NOTE:
SDRAM devices require a minimum delay of tRC between refresh cycles. The
SDRAM Controller incorporates a timer to guarantee this timing is met. The timer
is user configurable through the SRC field in the SDCTLx register.
19.5.5 Set Mode Register Mode (SMODE = 011)
The Set Mode Register mode (SMODE = 011) is used to program the SDRAM/SyncFlash mode register. This
mode differs from normal SDRAM write cycles because the data to be written is transferred across the address bus.
Reads of the mode register are not allowed.
Either a read or write cycle may be used for this transfer. In the case of a write, the AHB data will be ignored and
the external data bus will not be driven. The row and bank address signals are used to transfer the data. The cycle
will be 2 clocks on the AHB and a single clock to the SDRAM device.
Figure 19-21 and Figure 19-22 illustrate the bus sequence for a mode register set operation. Mode register set
commands must be issued while the SDRAM is idle.
The SDRAM Controller does not guarantee that the SDRAMs have returned to the idle state before issuing the
mode register set command. Therefore, software must generate a precharge all sequence before issuing the mode
register set command if there is any possibility that one or more banks could be active. Also keep in mind that the
row cycle time (tRC) must be met before the mode register set command is issued.
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Freescale Semiconductor
19-25
Operating Modes
Section 19.7.4, “Mode Register Programming,” provides a detailed example of the mode register data value
calculation and mapping to the ARM920T processor’s address.
(Read | Write) & SMODE = pre_cmd
Precharge
All
Active
Idle
(Read | Write) & SMODE = set_mode
ILLEGAL SDRAM TRANSITION
Set
Mode Reg
(Read | Write) & SMODE = set_mode
Figure 19-21. Set Mode Register State Diagram
SDCLK
ADDR
SDRAMx
MODE
tRC Minimum
RAS,
CAS,
SDWE
REFRESH
MRS
Self-Refresh and Auto-Refresh
CSDx
DATA
Figure 19-22. Set Mode Register Timing Diagram
19.5.6 SyncFlash Load Command Mode
SyncFlash memories extend the standard SDRAM command set to include device-specific program, erase, and
configure commands. These proprietary operations use a 3 command sequence: Load Command register, Activate,
and Read or Write. The Load Command Register serves as an “escape” code to provide special meaning to the read
or write commands which follow. The 3 command sequences must always occur in the correct order, however any
number of NOPs can be inserted between them. The Load Command Register command is mapped to the same
encoding as the SDRAM Auto-Refresh and Self-Refresh commands.
The SyncFlash Load Command mode provides the mechanism for software to generate the first command in the
sequence. By toggling between this mode and Normal Read/Write any of the command triplets can be generated.
An example of a configuration register read is shown in Figure 19-23. The first bus cycle places the SDRAM
Controller in the Load Command Register Mode. The following bus cycle begins the first command of the triplet
by loading the command register with the desired operation code. Because the operation code is transferred across
the address bus, either a read or write bus cycle could have been used for this cycle. The third bus cycle returns the
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19-26
Freescale Semiconductor
Operating Modes
SDRAM Controller to the normal read/write mode. Finally, the fourth cycle performs the actual read of the
configuration register. Although not shown in the diagram, the device configuration data would be returned across
the data bus after the CAS latency had been met. The activate and read comprise the final two commands in the
triplet and must refer to the same bank as the original command register load. Changes to the bank address within
the triplet will return indeterminate results. Details on command register encodings and operation are covered in
Section 19.8.4, “SyncFlash Configuration.”
SDCLK
ADDR
COMMAND
ROWx
Configx
RAS,
CAS,
SDWE
LCR
ACT
READ
CSDx
DATA
Figure 19-23. Load Command Register Timing Diagram
19.5.7 SyncFlash Program Mode
SyncFlash programming and status checking operations require the same 3 command sequence described in
Section 19.5.6. Because these operations are repeated many thousands of times to program the entire array, a
hardware programming mode is provided as an alternative to the software-intensive method previously described.
SyncFlash programming mode implements two command sequence triplets: a program sequence (write) and a
status check sequence (read). The state diagram for these two sequences is illustrated in Figure 19-24.
IDLE
Read
Write
NOP
LCR
Addr = 0x40
Bank = A
LCR
Addr = 0x70
Bank = *
ACT
Addr = RowA
Bank = A
ACT
Addr = *
Bank = *
WRITE
Addr = ColA
Bank = A
READ
Addr = *
Bank = *
* — Any address within memory region
Figure 19-24. SyncFlash Program Mode State Diagram
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-27
General Operation
A write to an address within the memory region initiates the program sequence. The first command issued to the
SyncFlash is Load Command register. A [7:0] determines which operation the command performs. For this write
setup operation, an address of 0x40 is hardware generated. The bank and other address lines are driven with the
address to be programmed. The second command, Active, registers the row address and confirms the bank address.
The third command supplies the column address, re-confirms the bank address, and supplies the data to be written.
SyncFlash does not support burst writes, therefore a Burst Terminate command is not required.
A read to the memory region initiates the status read sequence. The first command issued to the SyncFlash is the
Load Command Register with A [7:0] set to 0x70 which corresponds to the Read Status Register operation. The
bank and other address lines are driven to the selected address. The second command, Active, sets up the status
register read. The bank and row addresses are driven during this command. The third command of the triplet is
Read. Bank and column addresses are driven on the address bus during this command. Data is returned from
memory on the low-order 8 data bits following the CAS latency.
SDCLK
ADDR
BANKA, CMD BANK/ROWA
RAS, CAS, SDWE
LCR
COLUMNA
ACT
WRIT
CSDx
DATA
DATAA
Figure 19-25. SyncFlash Program Timing Diagram
SDCLK
ADDR
RAS,
CAS,
SDWE
BANKA, CMD BANK/ROWA
LCR
ACT
COLUMNA
READ
tCL = 2
CSDx
DATA
DATAA
Figure 19-26. SyncFlash Read Status Register Timing Diagram
19.6 General Operation
The general operation of the SDRAM controller is discussed in this section and includes address multiplexing,
refresh and self-refresh modes. The SDRAM Controller is designed to support a broad range of JEDEC standard
SDRAM configurations including devices of 64-, 128-, and 256-Mbit densities. Given the physical size constraints
of the target applications, the design was optimized for a memory device data width of 32 bits. Table 19-11
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Freescale Semiconductor
General Operation
summarizes the devices targeted by the design. The controller is capable of interfacing with devices of other widths
and densities, however, only devices with 4 banks are supported. A 100 MHz system bus operation is possible with
PC100 compliant single data rate memory devices.
Table 19-11. JEDEC Standard Single Data Rate SDRAMs
SDRAM Configuration
Item
64 Mbit
128 Mbit
256 Mbit
Bus Width
16
32
16
32
16
32
Depth
4 Mword
2 Mword
8 Mword
4 Mword
16 Mword
8 Mword
Refresh Rows
4096
(15.62 μs)
4096
(15.62 μs)
4096
(15.62 μs)
4096
(15.62 μs)
8192
(7.81 μs)
8192
(7.81 μs)
# Banks
4
4
4
4
4
4
Bank Address
2
2
2
2
2
2
Row Address
12
11
12
12
13
13
Column Address
8
8
9
8
9
8
Data Qualifiers
2
4
2
4
2
4
19.6.1 Address Multiplexing
The JEDEC standard SDRAMs for which the controller was optimized, use an asymmetrical array architecture
with more row than column address lines. The SDRAM Controller multiplexes only those pins which change
between the row and column addresses. The remaining (most significant) row addresses and the bank addresses are
not multiplexed.
19.6.1.1 Multiplexed Address Bus
The SDRAM Controller multiplexed address bus is aligned to the column addresses so that address line A1 always
appears on pin MA0. With this alignment, the “folding point” in the multiplexor is driven solely by the number of
column address bits, although interleave mode causes a two bit shift to account for the bank addresses. Column bus
widths of 8 to 11 bits are supported in non-interleave mode, although only 8 and 9 bit widths are allowed in
interleave mode. Table 19-12 summarizes the multiplex options supported by the controller. Column addresses
through A10 are driven regardless of the multiplexor configuration, although some of the lines will be unused for
the smaller page sizes.
Memory width does not affect the multiplexer; however, it does affect how the memories are connected to the
SDRAM Controller pins. The width of the multiplexed bus is one bit larger than in previous generations of the
SDRAMC so that 32-bit memory systems can be supported with a minimal impact on the multiplex hardware
because 32-bit memory systems are shifted left by one bit and use MA [n+1:1]. This is demonstrated in the last two
rows of Table 19-12 by the grayed-out boxes. Note that the AP signal is duplicated in two bit positions to permit
this signal to always appear on memory pin A10. Table 19-13 lists the SDRAM interface connections for different
configurations of JEDEC SDRAM.
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19-29
General Operation
Table 19-12. Address Multiplexing by Column Width
Column Bits
IAM=0
IAM=1
SDRAM Controller Pin
Memory
Width
MA1
1
MA1
0
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
ROW
8
-
32
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
9
-
32
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
10
8
32
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
11
9
32
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A5
A4
A3
A2
A1
COLUMN
ALL
32
AP
AP
A10
A9
A8
A7
A6
Indicates address lines not required for this memory width.
Table 19-13. MC9328MXS to SDRAM Interface Connections
Memory
Configuration
4M x16Bits
x 2 Chips
(16 Mbyte)
8Mx16Bits
x 2 Chips
(32 Mbyte)
i.MX Pins
16M x16Bits
x 2 Chips
(64 Mbyte)
2M x32Bits
x 1 Chip
(8 Mbyte)
4Mx32Bits
x 1 Chip
(16 Mbyte)
8M x32Bits
x 1 Chip
(32 Mbyte)
SDRAM Memory Address Pins
Rows
12
12
13
11
12
13
Columns
8
9
9
8
8
8
Data size
32
32
32
32
32
32
Refresh rows
4096
4096
8192
2048
4096
8192
IAM
0
1
0
1
0
1
0
1
0
1
0
1
SDRAM Memory Address Pins1
i.MX Pins
A19
A18
BA1
A17
BA0
BA1
BA1
BA0
BA0
BA1
BA1
BA1
BA0
BA0
BA0
A16
A15
BA1
A14
A13
BA1
A12
BA0
A11
A11
A11
A11
BA1
A12
BA0
A11
BA0
A12
A11
A11
BA1
A11
BA1
A12
BA0
A11
BA1
BA0
A12
BA0
A11
A11
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General Operation
Table 19-13. MC9328MXS to SDRAM Interface Connections (continued)
Memory
Configuration
4M x16Bits
x 2 Chips
(16 Mbyte)
8Mx16Bits
x 2 Chips
(32 Mbyte)
i.MX Pins
1.
16M x16Bits
x 2 Chips
(64 Mbyte)
2M x32Bits
x 1 Chip
(8 Mbyte)
4Mx32Bits
x 1 Chip
(16 Mbyte)
8M x32Bits
x 1 Chip
(32 Mbyte)
SDRAM Memory Address Pins
MA11
A10
A10
A10
A10
A10
A10
A10
A10
A10
A10
A10
A10
MA10
A9
A9
A9
A9
A9
A9
A9
A9
A9
A9
A9
A9
A10
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A9
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A8
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A7
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A6
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A5
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A4
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A3
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A2
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
Grayed-out boxes are unused.
19.6.1.2 Non-Multiplexed Address Bus
The most significant row address bits are not sampled when the column addresses are being driven, and therefore
do not need to be multiplexed. The SDRAM Controller implementation takes advantage of this fact and uses the
existing non-multiplexed address bus to provide these signals. Addresses A21 through A25 are needed across the
supported configurations. The specific connections which will need to be made are dependent on the memory
device type, density and bank interleave mode. These configuration-dependent connections are handled through
the design of the external hardware. Examples are provided in Section 19.7, “SDRAM Operation,” and
Section 19.8, “SyncFlash Operation.”
19.6.1.3 Bank Addresses
Which bank addresses of the SDRAM controller are multiplexed with which MC9328MXS address pins, depends
on whether or not the memory system is in interleaved mode. For non-interleaved mode, the SDRAM controller
bank addresses SDBA[4:0] are multiplexed with the address pins A[15:11]. For interleaved mode, the SDRAM
controller “interleaved” bank addresses SDIBA[3:0] are multiplexed with the MC9328MXS address pins
A[19:16]. Instead of detailing the complexity of how these bank addresses are multiplexed with the corresponding
MC9328MXS address pins with different memory configurations, the user is directed to Table 19-13. This table
explicitly shows which SDRAM memory bank address pin must be connected to which corresponding
MC9328MXS address pins given different the JEDEC standard memory configurations. Also, if the user wants to
derive how the density of the memory is calculated or how to derive the page size, they use the following
equations:
Page Size (Bytes) = 2#Column Address Bits × (Memory Width in Bits / 8)
Eqn. 19-1
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-31
General Operation
Density (Bytes) = 2(# Column Address Bits + # Row Address Bits)
× (Memory Width in Bits / 2)
Eqn. 19-2
19.6.2 Refresh
SDRAM Controller hardware satisfies all SDRAM refresh requirements after an initial configuration by the user
software. 0, 1, 2, or 4 refresh cycles are scheduled at 31.25 μS (nominal 32 kHz clock) intervals, providing 0, 2048,
4096, or 8192 refresh cycles every 64 ms. The refresh rate is programmed through the SREFR field in the SDCTLx
registers. Each array can have a different rate, allowing a mix of different density SDRAMs. Refresh is disabled by
hardware reset.
A refresh request is made pending at each rising edge on the 32 kHz clock. In response to this request, the hardware
gains control of the SDRAM as soon as any in-process bus cycle completes. Once it has gained control of the
memory, commands are issued to precharge all banks. Following a row precharge delay (tRP), an auto-refresh
command is issued. At tRC intervals, additional auto-refresh cycles are issued until the specified number of cycles
have been run. Figure 19-27 illustrates a 2 refresh sequence.
Burst transfers in progress when the refresh request arrives are allowed to complete prior to the refresh operation.
SDRAM bus accesses queued after the refresh request are held off until the refresh completes. In Figure 19-28, an
access is queued just as the refresh begins. This cycle is delayed until the precharge and single refresh (SREFR =
01) cycles are run. Bus cycles targeted to other memory or peripheral devices are allowed to progress normally
while the refresh is in progress. None of the pins shared between the SDRAM and other devices are required for the
refresh operation.
32KHz
SDCLK
ADDR
A10 = 1
>= tRP
RAS,
CAS,
SDWE
PRE-ALL
>= tRC
REF A
REF A
CSDx
DATA
DATAA
Figure 19-27. Hardware Refresh Timing Diagram
MC9328MXS Reference Manual, Rev. 1.1
19-32
Freescale Semiconductor
General Operation
32KHz
Internal
Address
Bus
SDRAMx
Internal R/W
SDCLK
ROWx
ADDR
>= tRC (Minimum)
tRP (Minimum)
RAS,
CAS,
SDWE
PRE-ALL
REF A
ACT
CSDx
DATA
Figure 19-28. Hardware Refresh With Pending Bus Cycle Timing Diagram
19.6.3 Self-Refresh
SDRAM data must be retained during assertion of system reset (RESET_IN) and power conservation modes if
refresh has been enabled. The SDRAM Controller detects these conditions and places the memory in self-refresh.
If refresh has not been enabled, the SDRAM Controller places the memories in a lower power consumption mode
known as Powerdown. This operation is described in Section 19.6.3.3, “Powerdown Operation During Reset and
Low-Power Modes.”
19.6.3.1 Self-Refresh During RESET_IN
The assertion of system reset (RESET_IN) triggers the SDRAM Controller to place the memory in self-refresh
provided refresh had been previously enabled. Refresh during system reset is disabled by an SDRAM Controller
reset. It remains disabled until the refresh rate is programmed to a non-zero value. Once enabled, self-refresh is
invoked anytime system reset is asserted without a corresponding SDRAM reset.
19.6.3.2 Self-Refresh During Low-Power Mode
If refresh is enabled, low-power mode also forces the SDRAM into self-refresh mode. When the SDRAM
Controller detects that the bus masters are entering a low-power condition it begins a self-refresh sequence once
any in-progress bus access has completed. A Precharge All command is issued to close any open memory pages,
the Self-Refresh command is issued, and the clock enable is brought low. Once the memories are safely in their
low-power state, the SDRAMC tells the system clock controller to enter sleep mode.
19.6.3.3 Powerdown Operation During Reset and Low-Power Modes
The powerdown mode is used instead of self-refresh whenever system reset or any of the low-power modes occur
and refresh has not been enabled. This memory operating mode does not remove power, as the name might imply.
It simply lowers power consumption by disabling the clock input buffer and halting all internal activity. Because
powerdown can only be entered if all banks are idle, a Precharge All command must be issued to the memories
prior to stopping the clock. Figure 19-31 illustrates the powerdown sequence following assertion of system reset.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-33
General Operation
Low-Power Mode
Signal from CPU
SDRAM Low-Power
Mode Acknowledge
Signal
SDCLK
SDCKEx
ADDR
A10 = 1
>= tRP
RAS,
CAS,
SDW
PRE-ALL
SLFRRSH
CSDx
DATA
DATAA
Figure 19-29. Self-Refresh Entry Due to Low-Power Mode Timing Diagram
Low-Power Mode
Signal from CPU
SDRAM Low-Power
Mode Acknowledge
Signal
SDCLK
SDCKEx
ADDR
RAS,
CAS,
SDWE
>= tRC + 1 Clock
NOP
NOP
NOP
REF A
CSDx
DATA
Figure 19-30. Low-Power Mode Self-Refresh Exit Timing Diagram
MC9328MXS Reference Manual, Rev. 1.1
19-34
Freescale Semiconductor
General Operation
m_rst
SDCLK
SDCKEx
ADDR
A10 = 1
RAS,
CAS,
SDWE
PRE-ALL
NOP
NOP
CSDx
DATA
DATAA
Figure 19-31. Powerdown Mode Resulting From Reset with Refresh Disabled
19.6.4 Clock Suspend Low-Power Mode
SDRAM and SyncFlash memories incorporate a command sequence to disable the clock input buffer and suspend
internal activity, lowering power consumption as much as an order of magnitude. The SDRAM Controller
implements a clock suspend time-out mechanism to take advantage of this feature. Several software selectable
time-outs are provided to accommodate for varying system conditions, with the time-out condition being specified
in the Clock Suspend Timeout (CLKST) field in the SDCTLx register. The feature is disabled out of reset.
SDRAM/SyncFlash clock suspend actually consists of two sub-modes: Clock Suspend and Powerdown. The
distinguishing factor between the two is whether banks remain active while the clock is stopped. Clock suspend
allows banks to remain activated, while Powerdown does not.
19.6.4.1 Powerdown (Precharge Powerdown)
Programming CLKST [1:0] = 01 causes the SDRAM Controller to place the memories in powerdown mode
anytime the controller detects that no banks are active. The Precharge Powerdown mode is useful in applications
where a memory array is accessed infrequently and the chances of another access to the same page are minimal.
Reading or writing to memory activates a page within the addressed bank. Reset, software generated precharge,
and hardware initiated refresh are three ways to close an active bank. The periodically occurring refresh will be the
normal means that invokes the powerdown mode. At each refresh interval, all banks will be closed by a
precharge-all command, followed by the refresh operation. The controller will then issue the powerdown command
to the memories. A few cycle delays are incurred with the first read or write cycle to restart the clocks, however
only on the first cycle. After that, the clocks will continue to run until the next refresh operation or until any active
banks are manually precharged.
Page misses on read and write cycles cause the addressed bank to be closed (precharged) and a new page opened
within the bank. This operation does not cause the clocks to stop, nor does manually precharging only a single bank
within the memory. All banks within the memory must be inactive before the powerdown mode is invoked.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-35
General Operation
19.6.4.2 Clock Suspend (Active Powerdown)
The second clock suspend mode is selected whenever CLKST [1:0] = 1x. In Active Powerdown mode the clocks
are stopped after a selectable delay from the last access to the array. Active banks are not closed prior to disabling
the SDRAM clock. Either 64 (CLKST [1:0] = 10) or 128 (CLKST [1:0] = 11) cycle delays are possible. SDRAM
clocks are counted from the end of the last read or write access. Subsequent read or write accesses, and self-refresh
modes reset the counter. Auto-refresh cycles do not affect the counter; however, if the counter expires during a
refresh operation the clock will be disabled immediately following the refresh.
19.6.4.3 Refresh During Powerdown or Clock Suspend
Refresh requests queued while the clock is suspended will restart the clock, run the appropriate number of refresh
cycles, and then disable the clock again.
32KHz
SDCLK
SDCKEx
ADDR
ROWx
tRP (Minimum)
RAS,
CAS,
SDWE
PRE-ALL
REF A
NOP
CSDx
DATA
Figure 19-32. Precharge Powerdown Mode Entry Timing Diagram
SDCLK
SDCKEx
ADDR
RAS,
CAS,
SDWE
ROWA
COLUMNA
tRCD Minimum
NOP
ACT
COLUMNA
COLUMN
SDRAMx B
tCL=2
READ
TBST
NOP
NOP
READ
CSDx
DATA
DATAA
Figure 19-33. Precharge Powerdown Exit Timing Diagram
MC9328MXS Reference Manual, Rev. 1.1
19-36
Freescale Semiconductor
SDRAM Operation
SDCLK
SDCKEx
64 Clocks
ADDR C0LUMNA
RAS,
CAS,
SDWE
C0LUMNA
C0LUMN
SDRAMx B
tCL = 2
READ
TBST
NOP
READ
CSDx
DATA
DATAA
Figure 19-34. Clock Suspend (Active Powerdown) Timing Diagram
NOTE:
For each of the previous Precharge and Active Powerdown figures, it is assumed
that only one chip-select has been enabled. If both chip-selects are enabled and one
of the two chip-selects is not currently in a powerdown mode, then the SDCLK will
continue to run even while the other chip-select is in powerdown mode since both
chip selects share the SDCLK.
19.7 SDRAM Operation
The following subsections provide details on selecting compatible SDRAM memories and configuring the
controller to work with the memory system.
19.7.1 SDRAM Selection
Table 19-11 on page 19-29 lists the memories around which the controller is optimized, however many other
memory types are also suitable for use. Important characteristics to consider when choosing a memory module are:
•
Page comparators expect 4 bank memories—2 bank devices are not supported. Their use results in the
memory and controller losing synchronization when crossing page boundaries.
•
Page (column) addressing must match one of the supported sizes.
•
Memory density can be larger or smaller than those directly supported, although some memory may be
inaccessible or redundantly mapped. In linear mode (IAM bit of the Control Register is 0), the bank
addresses are the most significant addresses and connecting a memory smaller than the selected density will
result in one or more banks being inaccessible.
•
Controller design is for memories meeting PC100 timing specifications at 100 MHz system operation. Use
of non-compliant memories or other system clock rates require a thorough analysis of all timing parameters.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-37
SDRAM Operation
19.7.2 Configuring Controller for SDRAM Memory Array
Configuration register programming options and controller-memory physical connections provide flexibility to
accommodate different memory types and system configurations. Options are broadly grouped into 3 categories:
•
Physical Characteristics: row and column address bus widths, data bus width, and interleave mode
•
Timing Parametrics: CAS latency, row precharge and cycle delays, and refresh rate
•
Functional Features: clock suspend timer and supervisor/user protection
Table 19-20 on page 19-46 and Table 19-21 on page 19-47 are provided to assist the designer with the selection of
the correct physical parameters for a number of preferred memory configurations. Timing parametrics are
addressed in the following subsections.
19.7.2.1 CAS Latency
CAS latency is determined by the operating frequency and access time of the memories. For a 100 MHz system
clock frequency and PC100 compliant memories, the CAS latency will generally be programmed to 3 clocks,
although the memory specifications must always be consulted to confirm this value. CAS latency must be
programmed in two places: the chip-select Control Register and the SDRAM Mode Register. See Table 19-6 on
page 19-9 for a description of the control register encoding and Section 19.7.4, “Mode Register Programming,” for
the details on programming the SDRAM mode register.
19.7.2.2 Row Precharge Delay
Row precharge delay is defined as the delay between a precharge command and the next row activate command to
the same bank. The SDRAM memory specification provides the minimum precharge delay as tRP, usually in terms
of ns. Therefore the user will have to calculate the number clocks needed for the row precharge delay and program
this value into the SRP bit in SDRAM Control register described in Table 19-6 on page 19-9. For example, a tRP
specification of 15 ns with a 100 MHz clock (10 ns period) results in 1.5 clocks, rounded to 2.
19.7.2.3 Row-to-Column Delay
The row-to-column delay is defined as the delay between a row activate command and a subsequent read or write
command. The SDRAM memory specification provides the minimum row-to-column (or ACTIVE to READ or
WRITE) delay as tRCD, usually in terms of ns. Given the system bus speed, the user must calculate the number of
clocks needed after an activate command is given before the subsequent read or write command and program this
value into the SRCD bit field in the SDRAM Control register, as described in Table 19-6 on page 19-9. For
example, a tRCD specification of 15 ns with a 100 MHz clock (10 ns period) results in 1.5 clocks, rounded to 2.
19.7.2.4 Row Cycle Delay
Row cycle delay is defined as the delay between a refresh and any subsequent refresh or read/write access. Because
the tRC timing for row activate to row activate with the same bank is implicitly guaranteed by the sum of tRCD + tCL
+ tRP, the value programmed into the SRC field in the SDRAM Control register must depend on the AUTO
REFRESH period, tRCF, specified in the SDRAM memory.
MC9328MXS Reference Manual, Rev. 1.1
19-38
Freescale Semiconductor
SDRAM Operation
19.7.2.5 Refresh Rate
The refresh rate is the rate by which the SDRAM controller is required to refresh each row in the SDRAM
memory. The SDRAM memory specification provides the total number of rows per bank, and the corresponding
refresh rate must be programmed into the SREFR field in the SDRAM control register (See Table 19-6 on
page 19-9). For example, if the SDRAM memory contains 8192 rows, or requires 8192 AUTO REFRESH cycles
every 64 ms, then the refresh rate can be calculated as 64 ms / 8192 rows = 7.81 μs per row. Therefore the user
programs the SREFR field with 11. Refer to Section 19.6.2, “Refresh,” on page 19-32 for more information.
19.7.2.6 Memory Configuration Examples
Twelve different examples of SDRAM configurations are provided in this section and shown in Figure 19-35 on
page 19-40 through Figure 19-56 on page 19-70. These examples are 64 Mbit, 128 Mbit, and 256 Mbit SDRAM
memories in single x16, dual x16, and single x32 configurations. All examples use bank and non-bank interleaving
for address configuration. Each figure is accompanied with the control register values in Table 19-14 on
page 19-40 through Table 19-49 on page 19-70.
NOTE:
The following examples assume that the number of rows and columns for each
given SDRAM density follow the JEDEC standard. The SDRAM Controller can
interface to SDRAMS which do not follow the JEDEC standards for row and
column sizes, however the user must take care to ensure that the SDRAM Control
Register bits ROW and COL are programmed to the appropriate number of rows
and columns given in the SDRAM data sheet. These examples do not cover
non-JEDEC standard SDRAMS.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-39
SDRAM Operation
Table 19-14. Single 4M x 16 Control Register Values
Control Field
Value
Density
8 Mbyte
Page Size
512
ROW
12
COL
8
DSIZ
16 (D[15:0])
IAM
Bank Interleaved
A17
A16
MA[11:10],A[10:1]:
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
DQ[15:0]
BA1
BA0
A[11:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
SDCLK
CLK
SDCKE
CKE
SDRAM
CONTROLLER
4M x 16
SDRAM
Figure 19-35. Single 64 Mbit (4M x 16) Connection Diagram (IAM = 1)
MC9328MXS Reference Manual, Rev. 1.1
19-40
Freescale Semiconductor
SDRAM Operation
Table 19-15. Single 4M x 16 Control Register Values
Control Field
Value
Density
8 Mbyte
Page Size
512
ROW
12
COL
8
DSIZ
16 (D[15:0])
IAM
Non-bank Interleaved
A12
A11
MA[11:10],A[10:1]:
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
DQ[15:0]
BA1
BA0
A[11:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
SDCLK
CLK
SDCKE
CKE
SDRAM
CONTROLLER
4M x 16
SDRAM
Figure 19-36. Single 64 Mbit (4M x 16 x 1) Connection Diagram (IAM = 0)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-41
SDRAM Operation
Table 19-16. Single 8M x 16 Control Register Values
Control Field
Value
Density
16 Mbyte
Page Size
1024 bytes
ROW
12
COL
9
DSIZ
16 (D[15:0])
IAM
Bank Interleaved
A18
A17
MA[11:10],A[10:1]:
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
DQ[15:0]
BA1
BA0
A[11:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
SDCLK
CLK
SDCKE
CKE
SDRAM
CONTROLLER
8M x 16
SDRAM
Figure 19-37. Single 128 Mbit (8M x 16) Connection Diagram (IAM = 1)
MC9328MXS Reference Manual, Rev. 1.1
19-42
Freescale Semiconductor
SDRAM Operation
Table 19-17. Single 8M x 16 Control Register Values
Control Field
Value
Density
16 Mbyte
Page Size
1024 bytes
ROW
12
COL
9
DSIZ
16 (D[15:0])
IAM
Non-bank Interleaved
A13
A12
MA[11:10],A[10:1]:
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
DQ[15:0]
BA1
BA0
A[11:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
SDCLK
CLK
SDCKE
CKE
SDRAM
CONTROLLER
8M x 16
SDRAM
Figure 19-38. Single 128 Mbit (8M x 16) Connection Diagram (IAM = 0)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-43
SDRAM Operation
Table 19-18. Single 16M x16 Control Register Values
Control Field
Value
Density
32 Mbyte
Page Size
1024
ROW
13
COL
9
DSIZ
16 (D[15:0])
IAM
Bank-Interleaved
A18
A17
A[14]
MA[11:10],A[10:1
RAS
CAS
CS2/CSD0
SDWE
BA1
BA0
A[12]
A[11:0]
RAS
CAS
CS
WE
DQM3
DQM2
DQMH
DQM1
DQM0
DQ[15:0]
DQML
DQ[15:0]
SDCLK
CLK
SDCKE
CKE
SDRAM
CONTROLLER
16M x 16
SDRAM
Figure 19-39. Single 256 Mbit (16M x 16) Connection Diagram (IAM = 1)
MC9328MXS Reference Manual, Rev. 1.1
19-44
Freescale Semiconductor
SDRAM Operation
Table 19-19. Single 16M x16 Control Register Values
Control Field
Value
Density
32 Mbyte
Page Size
1024
ROW
13
COL
9
DSIZ
16 (D[15:0])
IAM
Non-Bank-Interleaved
A14
A13
A[12]
MA[11:10],A[10:1
RAS
CAS
CS2/CSD0
SDWE
BA1
BA0
A[12]
A[11:0]
RAS
CAS
CS
WE
DQM3
DQM2
DQMH
DQM1
DQM0
DQ[15:0]
DQML
DQ[15:0]
SDCLK
CLK
SDCKE
CKE
SDRAM
CONTROLLER
16M x 16
SDRAM
Figure 19-40. Single 256 Mbit (16M x 16) Connection Diagram (IAM = 1)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-45
SDRAM Operation
Table 19-20. Dual 64 Mbit (4M x 16 x 2) Control Register Values (IAM = 1)
Control Field
Value
Density
16 Mbyte
Page size
1024 bytes
ROW
12
COL
8
DSIZ
32 (D [31:0])
IAM
Bank–interleaved
SDCLK
SDCKE
A18
A17
A13
MA[11:10], A[10:2]
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
D[31:16]
D[15:0]
MC9328MXS
CLK
CKE
BA1
BA0
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
4M x 16
SDRAM
CLK
CKE
BA1
BA0
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
4M x 16
SDRAM
Figure 19-41. Dual 64 Mbit (4M x 16 x 2) Connection Diagram (IAM = 1)
MC9328MXS Reference Manual, Rev. 1.1
19-46
Freescale Semiconductor
SDRAM Operation
Table 19-21. Dual 64 Mbit (4M x 16 x 2) Control Register Values (IAM = 0)
Control Field
Value
Density
16 Mbyte
Page size
1024 bytes
ROW
12
COL
8
DSIZ
32 (D [31:0])
IAM
Non-bank–interleaved
SDCLK
SDCKE
A13
A12
A11
MA[11:10], A[10:2]
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
D[31:16]
D[15:0]
MC9328MXS
CLK
CKE
BA1
BA0
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
4M x 16
SDRAM
CLK
CKE
BA1
BA0
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
4M x 16
SDRAM
Figure 19-42. Dual 64 Mbit (4M x 16 x 2) Connection Diagram (IAM = 0)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-47
SDRAM Operation
Table 19-22. Dual 128 Mbit (8M x 16 x 2) Control Register Values (IAM = 1)
Control Field
Value
Density
32 Mbyte
Page size
2048 bytes
ROW
12
COL
9
DSIZ
32 (D [31:0])
IAM
Bank–interleaved
SDCLK
SDCKE
A19
A18
A14
MA[11:10], A[10:2]
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
D[31:16]
D[15:0]
MC9328MXS
CLK
CKE
BA1
BA0
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
8M x 16
SDRAM
CLK
CKE
BA1
BA0
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
8M x 16
SDRAM
Figure 19-43. Dual 128 Mbit (8M x 16 x 2) Connection Diagram (IAM = 1)
MC9328MXS Reference Manual, Rev. 1.1
19-48
Freescale Semiconductor
SDRAM Operation
Table 19-23. Dual 128 Mbit (8M x 16 x 2) Control Register Values (IAM = 0)
Control Field
Value
Density
32 Mbyte
Page size
2048 bytes
ROW
12
COL
9
DSIZ
32 (D [31:0])
IAM
Non-bank–interleaved
SDCLK
SDCKE
A14
A13
A12
MA[11:10], A[10:2]
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
D[31:16]
D[15:0]
MC9328MXS
CLK
CKE
BA1
BA0
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
8M x 16
SDRAM
CLK
CKE
BA1
BA0
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
8M x 16
SDRAM
Figure 19-44. Dual 128 Mbit (8M x 16 x 2) Connection Diagram (IAM = 0)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-49
SDRAM Operation
Table 19-24. Dual 256 Mbit (16M x 16 x 2) Control Register Values (IAM = 1)
Control Field
Value
Density
64 Mbyte
Page size
2048 bytes
ROW
13
COL
9
DSIZ
32 (D [31:0])
IAM
Bank–interleaved
SDCLK
SDCKE
A19
A18
A15
A14
MA[11:10],A[10:2]
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
D[31:16]
CLK
CKE
BA1
BA0
A12
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
D[15:0]
16M x 16
SDRAM
MC9328MXS
CLK
CKE
BA1
BA0
A12
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
16M x 16
SDRAM
Figure 19-45. Dual 256 Mbit (16M x 16 x 2) Connection Diagram (IAM = 1)
MC9328MXS Reference Manual, Rev. 1.1
19-50
Freescale Semiconductor
SDRAM Operation
Table 19-25. Dual 256 Mbit (16M x 16 x 2) Control Register Values (IAM = 0)
Control Field
Value
Density
64 Mbyte
Page size
2048 bytes
ROW
13
COL
9
DSIZ
32 (D [31:0])
IAM
Non-bank–interleaved
SDCLK
SDCKE
A15
A14
A[13:12]
MA[11:10],A[10:2]
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
CLK
CKE
BA1
BA0
A[12:11]
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
D[31:16]
DQ[15:0]
D[15:0]
16M x 16
SDRAM
MC9328MXS
CLK
CKE
BA1
BA0
A12
A11
A[10:0]
RAS
CAS
CS
WE
DQMH
DQML
DQ[15:0]
16M x 16
SDRAM
Figure 19-46. Dual 256 Mbit (16M x 16 x 2) Connection Diagram (IAM = 0)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-51
SDRAM Operation
Table 19-26. Single 64 Mbit (2M x 32) Control Register Values (IAM = 1)
Control Field
Value
Density
8 Mbyte
Page size
1024 bytes
ROW
11
COL
8
DSIZ
32 (D [31:0])
IAM
Bank–interleaved
A18
A17
BA1
BA0
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
RAS
CAS
CS
WE
DQM3
DQM2
DQM1
DQM0
D[31:0]
DQ[31:0]
SDCLK
SDCKE
CLK
CKE
MC9328MXS
2M x 32
SDRAM
Figure 19-47. Single 64 Mbit (2M x 32) Connection Diagram (IAM = 1)
MC9328MXS Reference Manual, Rev. 1.1
19-52
Freescale Semiconductor
SDRAM Operation
Table 19-27. Single 64 Mbit (2M x 32) Control Register Values (IAM = 0)
Control Field
Value
Density
8 Mbyte
Page size
1024 bytes
ROW
11
COL
8
DSIZ
32 (D [31:0])
IAM
Non-bank–interleaved
SDCLK
SDCKE
A12
A11
MA[11:10], A[10:2]
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
D[31:0]
MC9328MXS
CLK
CKE
BA1
BA0
A[10:0]
RAS
CAS
CS
WE
DQM3
DQM2
DQM1
DQM0
DQ[31:0]
2M x 32
SDRAM
Figure 19-48. Single 64 Mbit (2M x 32) Connection Diagram (IAM = 0)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-53
SDRAM Operation
Table 19-28. Single 128 Mbit (4M x 32) Control Register Values (IAM = 1)
Control Field
Value
Density
16 Mbyte
Page size
1024 bytes
ROW
12
COL
8
DSIZ
32 (D [31:0])
IAM
Bank–interleaved
A18
A17
A13
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RAS
CAS
CS
WE
DQM3
DQM2
DQM1
DQM0
D[31:0]
DQ[31:0]
SDCLK
SDCKE
CLK
CKE
MC9328MXS
4M x 32
SDRAM
Figure 19-49. Single 128 Mbit (4M x 32) Connection Diagram (IAM = 1)
MC9328MXS Reference Manual, Rev. 1.1
19-54
Freescale Semiconductor
SDRAM Operation
Table 19-29. Single 128 Mbit (4M x 32) Control Register Values (IAM = 0)
Control Field
Value
Density
16 Mbyte
Page size
1024 bytes
ROW
12
COL
8
DSIZ
32 (D [31:0])
IAM
Non-bank–interleaved
SDCLK
SDCKE
A13
A12
A11
MA[11:10], A[10:2]
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
CLK
CKE
BA1
BA0
A11
A[10:0]
RAS
CAS
CS
WE
DQM3
DQM2
DQM1
DQM0
D[31:0]
DQ[31:0]
4M x 32
SDRAM
MC9328MXS
Figure 19-50. Single 128 Mbit (4M x 32) Connection Diagram (IAM = 0)
NOTE:
JEDEC has not issued a standard pinout and array configuration for the 128 Mbit
density memories in a x32 package option. This connection diagram is based on the
PC100 Standard.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-55
SDRAM Operation
Table 19-30. Single 256 Mbit (8M x 32) Control Register Values (IAM = 1)
Control Field
Value
Density
32 Mbyte
Page size
2048 bytes
ROW
12
COL
9
DSIZ
32 (D [31:0])
IAM
Bank-interleaved
A19
A18
BA1
BA0
A14
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
RAS
CAS
CS
WE
DQM3
DQM2
DQM1
DQM0
D[31:0]
DQ[31:0]
SDCLK
SDCKE
CLK
CKE
MC9328MXS
8M x 32
SDRAM
Figure 19-51. Single 256 Mbit (8M x 32) Connection Diagram (IAM = 1)
MC9328MXS Reference Manual, Rev. 1.1
19-56
Freescale Semiconductor
SDRAM Operation
Table 19-31. Single 256 Mbit (8M x 32) Control Register Values (IAM = 0)
Control Field
Value
Density
32 Mbyte
Page size
2048 bytes
ROW
12
COL
9
DSIZ
32 (D [31:0])
IAM
Non-bank–interleaved
SDCLK
SDCKE
A14
A13
A12
MA[11:10], A[10:2]
RAS
CAS
CS2/CSD0
SDWE
DQM3
DQM2
DQM1
DQM0
CLK
CKE
BA1
BA0
A11
A[10:0]
RAS
CAS
CS
WE
DQM3
DQM2
DQM1
DQM0
D[31:0]
DQ[31:0]
8M x 32
SDRAM
MC9328MXS
Figure 19-52. Single 256 Mbit (8M x 32) Connection Diagram (IAM = 0)
NOTE:
JEDEC has not issued a standard pinout and array configuration for the 256 Mbit
density memories in a x32 package option. This connection diagram is based on the
PC100 Standard.
19.7.3 SDRAM Reset Initialization
SDRAM initialization must follow a defined sequence following the power-on condition. The steps are as follows:
1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP conditions at the
command inputs.
2. Maintain stable power, clock, and NOP conditions for a minimum of 200 μs.
3. Issue precharge commands for all banks either with precharge all or precharge individual bank
commands.
4. After all banks are in the idle state for a minimum time of tRP, issue 8 or more auto-refresh
commands.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-57
SDRAM Operation
5. Issue a mode register set command to initialize the mode register.
6. SDRAM is now ready for normal operation.
The SDRAM Controller accomplishes steps 1 and 2 in hardware, however it relies on software assistance to
complete the remaining actions. The 200 μs stabilization period is guaranteed by the use of 2 reset signals whose
negations are separated by this amount. An SDRAM reset signal (SD_RST) is asserted to coincide with the system
reset used by the rest of the chip, however it negates 200 ms prior to the negation of system reset. The SDRAM
Controller leaves the SDRAM arrays in a NOP condition following the negation of the DRAM reset. Figure 19-53
shows the SDRAM Power-on initialization sequence.
VCC
SYSTEM
CLOCK
DRAM
RESET
200 μs Minimum
HARD_ASYN_
RESET
SDCLK
SDRAM
COMMAND
NOP
PRE
ALL
AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO MODE
NORMAL
REF
REF
REF
REF
REF
REF
REF
REF
SET
SDRAM Software Initialization Sequence
Figure 19-53. SDRAM Power-On Initialization Sequence
Following negation of system reset, initialization software must complete steps 3 through 5 using the special
operating modes enabled by the SMODE field in the SDRAM Control Register. To precharge the SDRAM array,
the SDRAM Controller operating mode is set to “precharge command” and an access is made to the SDRAM
address range with address bit A10 = 1. Instead of running a normal read or write cycle, the controller issues a
precharge all command to the addressed array. The operating mode is then switched to “auto-refresh” and 8
accesses are made to the SDRAM address space. Each of the accesses results in a refresh command to the
addressed array. A “mode register set” command is required to complete the initialization sequence. The value
written is system dependent. Consult Section 19.7.4, “Mode Register Programming,” for details. Finally, the
controller is placed back in the normal mode of operation so that subsequent accesses to the address space result in
normal read and write cycles to the SDRAM array.
Although the initialization sequence described in the previous paragraphs is only required at power-on, it may be
repeated at any time the programmer deems necessary.
Code Example 19-2 on page 19-59 provides the code necessary for the initialization sequence.
MC9328MXS Reference Manual, Rev. 1.1
19-58
Freescale Semiconductor
SDRAM Operation
Code Example 19-2. init_sdram
init_sdram:
ldr
ldr
st
st
ldr
ldr
ld
ld
ldr
st
st
movi
L1
ld
ld
decgt
bt
ldr
st
st
ldr
ld
ldr
ld
ldr
st
st
r2,CSD_REGS
r3,PRE_ALL_CMD
r3,(0,r2)
r3,(4,r2)
r4,SDRAM_ARRAY_0
r5,SDRAM_ARRAY_1
r3,(0,r4)
r3,(0,r5)
r3,AUTO_REF_CMD
r3,(0,r2)
r3,(4,r2)
r6,7
r3,(0,r4)
r3,(0,r5)
r6
L1
r3,SET_MODE_REG_CMD
r3,(0,r2)
r3,(4,r2)
r3,MODE_REG_VAL0
r3,(0,r3)
r3,MODE_REG_VAL1
r3,(0,r3)
r3,NORMAL_MODE
r3,(0,r2)
r3,(4,r2)
CSD_REGS
.long
SDRAM_ARRAY_0: .long
SDRAM ARRAY_1: .long
PRE_ALL_CMD
.long
AUTO_REF_CMD
.long
SET_MODE_REG_CMD.long
MODE_REG_VAL0
.long
MODE_REG_VAL1
.long
NORMAL_MODE
.long
// base address of registers
//
//
//
//
//
//
put array 0 in precharge command mode
put array 1 in precharge command mode
get address of first array
get address of second array
precharge array 0
precharge array 1
//
//
//
//
//
put array 0 in auto-refresh mode
put array 1 in auto-refresh mode
load loop counter
run auto-refresh cycle to array 0
run auto-refresh cycle to array 1
// 8 refresh cycles complete?
//
//
//
//
//
//
setup CSD0 for mode register write
setup CSD1 for mode register write
array 0 mode register value
New mode register value on address bus
array 1 mode register value
Write CSD1 mode register
// setup CSD0 for normal operation
// setup CSD1 for normal operation
0x00221000
0x08000000
0x0c000000
0xXXXXXXXX
0xXXXXXXXX
0xXXXXXXXX
0xXXXXXXXX
0xXXXXXXXX
0xXXXXXXXX
19.7.4 Mode Register Programming
This section describes how to program the SDRAM mode register using the MC9328MXS external address bus.
The mode register is used to set the SDRAM operating characteristics including CAS latency, burst length, burst
mode, and write data length. The settings depend on system characteristics including the operating frequency,
memory device type, burst buffer/cache line length, and bus width. Operating characteristics vary by device type,
so the data sheet must be consulted to determine the actual value to be written.
Table 19-32 through Table 19-37 provide examples of the SDRAM memory mode register configuration for
different SDRAM memory densities. These tables depict which mode register bit is connected to the SDRAM
memory address pin. Because the mode register is written via the MC9328MXS external address bus, and the
SDRAM data sheet specifies the SDRAM addresses on which to place the data, the next step is to then determine
the address translation from the MC9328MXS internal address bus to the MC9328MXS external address pins.
Table 19-38 on page 19-61 provides an example of which mode bits are mapped to which internal address bit for
each of the given memory densities.
Table 19-32. 4M x 16 Memory Configuration
SDRAM Address
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register Bit
M13
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
WB
Reserved
Content
Reserved
CAS latency
BT
Burst length
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-59
SDRAM Operation
Table 19-33. 8M x 16 Memory Configuration
SDRAM Address
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register Bit
M13
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
WB
Reserved
Reserved
Content
CAS latency
BT
Burst length
Table 19-34. 16M x 16 Memory Configuration
SDRAM Address
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register Bit
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
WB
Reserved
Reserved
Content
CAS latency
BT
Burst length
Table 19-35. 2M x 32 Memory Configuration
SDRAM Address
BA1
BA0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register Bit
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
WB
Reserved
Reserved
Content
CAS latency
BT
Burst length
Table 19-36. 4M x 32 Memory Configuration
SDRAM Address
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register Bit
M13
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
WB
Reserved
Reserved
Content
CAS latency
BT
Burst length
Table 19-37. 8M x 32 Memory Configuration
SDRAM Address
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register Bit
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
WB
Reserved
Content
Reserved
CAS latency
BT
Burst length
MC9328MXS Reference Manual, Rev. 1.1
19-60
Freescale Semiconductor
CSDx Base
A'10
A'9
A'8
A'7
A'6
A'5
A'4
A'3
A'2
A'1
A'0
M0
0
0
M12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
M12
M1
M13
M0
M2
M0
M1
0
M2
M0
0
M11
0
M0
0
M12
0
M0
0
0
A'11
M1
M13
M0
M12
M0
0
M1
0
A'12
M2
M0
M1
M13
M1
0
0
M2
0
M0
A'13
M3
M1
M2
M0
M2
M0
M3
M1
M3
M1
M3
M1
A'14
M4
M2
M3
M1
M3
M1
M4
M13
M11
M12
M10
M12
M13
M11
0
M11
M11
0
M12
M2
0
M4
X
M2
X
M4
0
M2
0
A'15
0
M5
0
M3
1
M4
0
M2
0
M4
X
M2
X
M5
0
M3
0
M5
0
M3
0
M5
0
M3
8Mx32Bit
x 1 Chip
(32 Mbyte)
A'16
0
M6
0
M4
X
M5
X
M3
0
M5
0
M3
0
M6
0
M4
1
M6
0
M4
0
M6
X
M4
X
A'17
0
M7
0
M5
0
M6
0
M4
0
M6
4Mx32Bit
x 1 Chip
(16 Mbyte)
M4
0
M7
0
M5
0
M7
X
M5
X
M7
0
M5
0
A'18
0
M8
0
M6
1
M7
0
M5
0
M7
0
M5
X
M8
X
M6
0
M8
0
M6
0
M8
M10
0
M6
M11
0
A'19
M12
2Mx32Bit
x 1 Chip
(8 Mbtye)
M9
X
M7
X
M8
0
M6
0
M8
0
M6
0
M9
1
M7
0
M9
X
M7
X
M9
0
M7
0
A'20
0
M10
0
M8
0
M9
16Mx16Bit
x 2 Chips
(64 Mbyte)
M7
0
M9
X
M7
X
M10
0
M8
0
M10
0
M8
0
M10
1
M8
0
A'21
X
M11
X
M9
0
M10
0
M8
0
M10
0
M8
0
M11
8Mx16Bit
x 2 Chips
(32 Mbyte)
M9
0
M11
0
M9
X
M11
X
M9
0
A'22
0
M12
0
M10
0
M11
1
M9
0
M11
0
M9
X
M12
A'24
X
M10
A'25
0
M12
A'26
0
M10
A'27
0
M12
A'28
0
M10
A'29
0
A'23
A'30
4Mx16Bit
x 2 Chips
(16Mbyte)
M13
Memory
Config.
A'31
MC9328MXS Internal Address Bus (internal address bits are differentiated using the nomenclature A’x)
IAM
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
Table 19-38. MC9328MXS SDRAM Memory Configuration
SDRAM Memory Mode Register Bits
SDRAM Operation
19-61
SDRAM Operation
19.7.5 Mode Register Programming Examples
To illustrate how these tables are used and as a demonstration of the programming procedure for the mode register,
two examples are provided. Refer to the SDRAM data sheet for up-to-date characteristics, as the values used in the
example may change from the date of this document’s publication.
19.7.5.1 Example 1—256 Mbit SDRAM Mode Register
For Example 1, the following system characteristics will be used:
•
2 Micron MT48LC16M16A2-7E SDRAMs configured as a x32 memory (16M × 16 bits × 2 chips)
•
100 MHz system clock frequency
•
Non-bank interleaved mode (IAM = 0)
•
Burst length of 8 (not optional as the MC9328MXS performs 8 word burst reads)
•
Single word writes (not optional as the MC9328MXS performs single writes only and does not provide a
burst terminate after each write)
Table 19-39 illustrates the Mode register bit assignments for the Micron 256 Mbit SDRAM.
Table 19-39. 256 Mbit SDRAM Mode Register
SDRAM
Address
Mode Register
Bit
Content
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
Reserved
WB
Reserved
CAS latency
BT
Burst length
Table 19-40. 256 Mbit SDRAM Mode Register Description
Name
Description
Settings
WB
Bit M9
Write Burst Mode—Needs to be programmed to 1 for single
location accesses.
0 = Burst writes (not supported by
MC9328MXS)
1 = Single word writes
CAS Latency
Bits M6–M4
CAS Latency—Sets latency between column address and data.
Note, the MC9328MXS does not support CAS Latencies of 1.
000 = Reserved
001 = Reserved
010 = 2 clocks
011 = 3 clocks
1xx = Reserved
BT
Bit M3
Burst Type—Selects sequential or interleaved bursts.
0 = Sequential
1 = Interleaved
MC9328MXS Reference Manual, Rev. 1.1
19-62
Freescale Semiconductor
SDRAM Operation
Table 19-40. 256 Mbit SDRAM Mode Register Description (continued)
Name
Description
Settings
Burst Length
Bits M2–M0
Burst Length—A burst length of 8 matches the ARM920T cache
line length.
000 = 1
001 = 2
010 = 4
011 = 8
111 = Full page (if BT = 0)
10x = Reserved
1x0 = Reserved
The values programmed into the SDRAM Mode register for example 1 are as follows:
•
Sequential burst (BT = 0)
•
Burst length of 8 (BL = 011), not optional
•
Single word writes (WB = 1), not optional
•
2 Clock latency (LTMODE = 010)
When the Mode register value has been determined, it must be converted to an address. The Mode register is
written via the address bus and the memory data sheet specifies the SDRAM address bits on which to place the
data. One final transformation is necessary to align the address to the multiplexed outputs of the SDRAM
controller. Memory density and bus width determine the alignment of the SDRAM to the controller pins and must
be considered during the calculation.
The first step is to determine the value of the 256 Mbit SDRAM Mode register and convert this into an SDRAM
address. Table 19-41 is the same as Table 19-39, however it includes the values for this 256 Mbit SDRAM
example. This table illustrates what value needs to be placed on the address bus to the SDRAM memory.
Table 19-41. 256 Mbit SDRAM Mode Register with Values
SDRAM Address
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register Bit
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
WB
Reserved
Content
Value
Reserved
0
0
0
1
0
0
CAS latency
0
1
BT
0
0
Burst length
0
1
1
The next step is to determine that the proper value is written to the MC9328MXS internal address bus to ensure
that the SDRAM controller’s ROW/COLUMN ADDRESS MUX writes these values to the correct address pins of
the MC9328MXS’s external address bus and then to the SDRAM memory. Table 19-38 simplifies this procedure
by allowing the user to simply plug in the Mode register bits into this table therefore generating the correct address
to write from the MC9328MXS. Referring to Table 19-38 and locating the proper SDRAM memory density (in this
case the 16M × 16 SDRAM), proceed by plugging in the Mode register bits into this table. Table 19-42 illustrates
this procedure.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-63
SDRAM Operation
0
0
0
1
1
A'0
1
A'1
0
A'2
0
A'3
0
A'4
1
A'5
0
A'6
0
A'7
0
A'8
0
A'9
A'10
M0
A'11
M1
A'12
M2
A'13
M3
A'14
M4
0
A'15
0
A'16
0
M5
1
M6
0
A'17
0
M7
0
A'18
0
A'19
Mode
Register
Bit
Value
M8
0
M9
0
A'20
A'24
X
A'21
A'25
X
M10
A'26
0
M11
A'27
0
A'22
A'28
0
M12
A'29
0
A'23
A'30
Mode
Register
Bit
M13
Internal
Address
A'31
Table 19-42. MC9328MXS Address Calculation for Given Mode Register Values
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 19-42 assumes CSD0 is being used as the chip-select for the SDRAM memory, therefore the chip-select base
address bits, A'31 through A'24, are set to 00001000 for the memory map region 0x08000000. As a result, for this
example, the final value (in hexadecimal format) written to the MC9328MXS internal address for proper
translation to the SDRAM memory mode register is 0x08111800. The procedure would then be to issue a Set Mode
Register Command to the SDRAM memory, followed by an access (either READ or WRITE) to the SDRAM
memory at address 0x08111800. This value is also written into the MODE_REG_VAL0 variable of
Code Example 19-2 on page 19-59. Refer to Section 19.5.5, “Set Mode Register Mode (SMODE = 011),” on page
19-25 for more information on the Set Mode Register Command.
19.7.5.2 Example 2—64 Mbit SDRAM Mode Register
For Example 2, the following system characteristics are used:
•
2 Mitsubishi M5M4V64S40ATP-8 64Mbit (4M × 16) SDRAMs configured as a x32 memory
(4M × 16 bits × 2 chips)
•
100 MHz system clock frequency
•
Bank-interleaved mode (IAM = 1)
•
Burst length of 8 (not optional as the MC9328MXS performs 8 word burst reads)
•
Single word writes (not optional as the MC9328MXS performs single writes only and does not provide a
burst terminate after each write)
Table 19-43 illustrates the Mode Register bit assignments for the Mitsubishi 64 Mbit SDRAM and Table 19-44.
provides the register descriptions.
Table 19-43. 64 Mbit SDRAM Mode Register
SDRAM Address
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register Bit
M13
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
WB
Reserved
Content
Reserved
CAS latency
BT
Burst length
Table 19-44. 64 Mbit SDRAM Mode Register Description
Name
WB
Bit M9
Description
Write Burst Mode—Needs to be programmed to 1 for
single location accesses.
Settings
0 = Burst writes (not supported by
MC9328MXS)
1 = Single word writes
MC9328MXS Reference Manual, Rev. 1.1
19-64
Freescale Semiconductor
SDRAM Operation
Table 19-44. 64 Mbit SDRAM Mode Register Description (continued)
CAS Latency
Bits M6–M4
CAS Latency—Sets latency between column
address and data. Note, the MC9328MXS does not
support CAS Latencies of 1.
000 = Reserved
001 = Reserved
010 = 2 clocks
011 = 3 clocks
1xx = Reserved
BT
Bit M3
Burst Type—Selects sequential or interleaved
bursts.
0 = Sequential
1 = Interleaved
Burst Length
Bits M2–M0
Burst Length—A burst length of 8 matches the
ARM920T cache line length.
000 = 1
001 = 2
010 = 4
011 = 8
111 = Full page (if BT = 0)
10x = Reserved
1x0 = Reserved
The values programmed into the SDRAM mode register for Example 2 are as follows:
•
Sequential burst (BT = 0)
•
Burst length of 8 (BL = 011), not optional
•
Single word writes (WB = 1), not optional
•
3 clock latency (LTMODE = 011)
In example 1, we saw that once the mode register value has been determined, it must be converted to an address.
The mode register is written via the address bus and the data sheet for the memory being used specifies the
SDRAM address bits on which to place the data. One final transformation is necessary to align the address to the
multiplexed outputs of the SDRAM controller. Memory density and bus width determine the alignment of the
SDRAM to the controller pins and must be defined during the calculation.
To defined memory density and bus width, the value of the 64 Mbit SDRAM mode register must be determined
and converted into a SDRAM address. Table 19-45 is the same as Table 19-43, however it includes the values
given in the 64 Mbit SDRAM mode register—example 2. Table 19-45 illustrates what value needs to be placed on
the address bus to the SDRAM memory.
Table 19-45. 64 Mbit SDRAM Mode Register with Values
SDRAM Address
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register Bit
M13
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
WB
Reserved
Content
Value
Reserved
0
0
0
1
0
0
CAS latency
0
1
1
BT
0
Burst length
0
1
1
The next step is to determine the proper value that is written to the MC9328MXS internal address bus so the
SDRAM controller ROW/COLUMN ADDRESS MUX may properly write these values to the correct address pins
of the MC9328MXS external address bus and then to the SDRAM memory. Table 19-38 on page 19-61 simplifies
this procedure by allowing the user to simply plug in the correct mode register bits into this table therefore
generating the correct address to write from the MC9328MXS. Referring to Table 19-38 and locating the proper
SDRAM memory density (in this case the 4M × 16 SDRAM), we can proceed by entering the mode register bits
into this table. Table 19-46 illustrates this procedure.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-65
SDRAM Operation
0
0
A'0
A'10
A'11
A'12
1
A'1
1
A'2
0
A'3
0
A'4
1
A'5
1
A'6
0
A'7
0
A'8
0
A'9
1
M12
0
M0
0
M13
A'13
A'14
M1
A'15
0
M2
0
M3
0
A'16
1
A'17
0
M4
0
A'18
0
M5
0
M6
Mode
Register
Bit
Value
A'19
0
A'20
0
M7
A'24
X
A'21
A'25
X
M8
A'26
0
M9
A'27
0
A'22
A'28
0
A'23
A'29
0
M10
A'30
Mode
Register
Bit
M11
Internal
Address
A'31
Table 19-46. MC9328MXS Address Calculation for Given Mode Register Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 19-42 assumes CSD0 is being used as the chip-select for the SDRAM memory, therefore the chip-select base
address bits, A’31 through A’24, are set to 00001000 for the memory map region 0x08000000. Therefore, for this
example, the final value (in hexadecimal format) that is written to the MC9328MXS internal address for proper
translation to the SDRAM memory mode register is 0x08233000. The procedure then must issue a Set Mode
Register Command to the SDRAM memory, followed by an access (either READ or WRITE) to the SDRAM
memory at address 0x08233000. This value will also be written into the “MODE_REG_VAL0” variable of
Code Example 19-2 on page 19-59. Refer to Section 19.5.5, “Set Mode Register Mode (SMODE = 011),” for
more information on the Set Mode Register Command.
MC9328MXS Reference Manual, Rev. 1.1
19-66
Freescale Semiconductor
SyncFlash Operation
19.7.6 SDRAM Memory Refresh
SDRAM memory specifications generally specify an interval during which all rows in the device must be
refreshed. The memory refresh requirements are outlined in Table 19-47. The SDRAM Controller refresh rate
(SREFR field of the Control Register) is programmable to meet these varying requirements. Refresh must be
enabled prior to storing data in the memory.
Table 19-47. SDRAM Memory Refresh
Device Size
Array Size
Refresh
Interval
Refresh Rate
Requirement
SREFR
Value
64 Mbit
4096 rows
64 ms
1 row every 15.6 µs
2 rows refreshed during each 32 kHz clock
10
128 Mbit
4096 rows
64 ms
1 row ever 15.6 µs
2 rows refreshed during each 32 kHz clock
10
256 Mbit
8192 rows
64 ms
1 row every 7.8 µs
4 rows refreshed during each 32 kHz clock
11
NOTE:
The memory data sheet must always be consulted to determine the correct refresh
interval and array architecture (number of rows). Refresh clock rates other the
nominal value require recalculation of the value to be programmed into REFR.
19.8 SyncFlash Operation
Micron SyncFlash memories are 3 V electrically sector-erasable, non-volatile memories architected to comply with
the SDRAM interface specifications. With few exceptions, they are capable of matching all SDRAM operating
modes.
19.8.1 SyncFlash Reset Initialization
SyncFlash initialization is considerably more straightforward than SDRAM. The SyncFlash sequence is:
1. Apply power to Vcc, VccQ, and VccP simultaneously.
2. Apply clock.
3. After clock is stable, transition RESET_SF from low to high.
4. Maintain power, stable clock, and RESET_SF high for minimum of 100 μs.
5. Initialization is now complete.
The SDRAM Controller asserts RESET_SF low anytime sd_rst is asserted. The 200 μs delay between the negation
of sd_rst and negation of m_rst easily meets the 100 μs stabilization requirement of the SyncFlash.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-67
SyncFlash Operation
VCC
SYSTEM
CLOCK
DRAM
RESET
100 μS Minimum
SYSTEM
RESET
RESET_SF
SDCLK
SYNCFLASH
COMMAND
NOP
ACT READ READ
Vector Fetch
Instruction Fetches
Figure 19-54. Sync Flash Reset Timing
19.8.2 SyncFlash Mode Register Programming
The mode register can be programmed following the initialization sequence, although generally it is not required.
A non-volatile mode register is initially programmed at the same time as the rest of the array. This non-volatile
register is copied into the mode register automatically during device initialization, and does not require reloading
prior to the first operational command. Software may overwrite the default value at any time the memory is idle
using the same sequence as an SDRAM mode register. Consult Section 19.7.4, “Mode Register Programming,” for
details.
Programming the SyncFlash non-volatile mode register requires a specialized sequence of load command register
triplets with VccP applied. Consult the SyncFlash data sheet for details.
19.8.3 Booting From SyncFlash
The SDRAM Controller is designed to permit booting from the SyncFlash device immediately out of reset. Default
values in the configuration register allow booting at frequencies up to 100 MHz. Complete initialization of the
controller is still required, however, and must be completed as quickly as possible.
19.8.4 SyncFlash Configuration
Hardware connections are similar to those for SDRAM of like density. One difference is that a SyncFlash boot
device is limited to using CSD1. SyncFlash can be connected to CSD0, however, it cannot be the boot device. The
second difference is the added connection to the reset/powerdown pin (RESET_SF). An example of a 32-bit
configuration is provided in Figure 19-56.
MC9328MXS Reference Manual, Rev. 1.1
19-68
Freescale Semiconductor
SyncFlash Operation
The only significant difference in the software configuration is that refresh must be disabled. SyncFlash maps the
control register access commands to the same basic commands as SDRAM refresh. Enabling hardware refresh
would most likely result in unexpected behavior.
Table 19-48. Single 4M x 16 SyncFlash Control Register Values
Control Field
Value
Density
8 Mbyte
Page Size
512
ROW
12
COL
8
DSIZ
16 (D[15:0])
IAM
Non-Interleaved
A12
A11
BA1
BA0
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RAS
CAS
CSD1
SDWE
DQM3
DQM2
DQM1
DQM0
RAS
CAS
CS
WE
DQM3
DQM2
DQMH
DQML
DQ[15:0]
DQ[15:0]
SDCLK
SDCKE0
CLK
CKE
RP
SDRAM
CONTROLLER
RP
4M x 16
SyncFlash
Figure 19-55. Single 64 Mbit SyncFlash Connection Diagram (IAM = 0)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-69
SyncFlash Operation
Table 19-49. Dual 4M x 16 SyncFlash Control Register Values (IAM = 0)
Control Field
Value
Density
16 Mbyte
Page size
1024
ROW
12
COL
8
DSIZ
32 (D [31:0])
IAM
Non-Interleaved
CLK
CKE
BA1
BA0
A11
A [10:0]
RAS
CAS
CS
WE
DQMH
DQML
SDCLK
SDCKE
A13
A12
A11
MA [11:10], A [10:2]
RAS
CAS
CSD1
SDWE
DQM3
DQM2
DQM1
DQM0
DQ [31:16]
DQ [15:0]
RESET_SF
RP
DQ [15:0]
MC9328MXS
4M x 16
SyncFlash
CLK
CKE
BA1
BA0
A12
A [10:0]
RAS
CAS
CS
WE
DQMH
DQML
RP
DQ [15:0]
4M x 16
SyncFlash
Figure 19-56. Dual 64 Mbit SyncFlash Connection Diagram (IAM = 0)
MC9328MXS Reference Manual, Rev. 1.1
19-70
Freescale Semiconductor
SyncFlash Operation
19.8.5 SyncFlash Programming
Table 19-50 provides a quick reference of the available commands for SyncFlash operation. The detailed command
encoding for SDRAM compatibility, is located in Table 19-10. All SyncFlash operations with LCR (LOAD
COMMAND REGISTER), LCR/ACTIVE/READ, or LCR/ACTIVE/WRITE commands and command sequences
are defined in Table 19-50 and Table 19-10.
Table 19-50. SyncFlash Command Sequences
1st Cycle
2nd Cycle
3rd Cycle
Operation
CMD
ADDR
ADDR
DQ
CMD
ADDR
ADDR
DQ
CMD
ADDR
ADDR
DQ
Read
Device
Configuration
LCR
90H
Bank
X
ACT
Row
Bank
X
READ
CA
Bank
X
Read
Status
Register
LCR
70H
X
X
ACT
X
X
X
READ
X
X
X
Clear
Status
Register
LCR
50H
X
X
—
—
—
—
—
—
—
—
Erase
Setup/
Confirm
LCR
20H
Bank
X
ACT
Row
Bank
X
WRITE
X
Bank
D0H
Write
Setup/
Confirm
LCR
40H
Bank
X
ACT
Row
Bank
X
WRITE
Col
Bank
D1H
Protect
Block/
Confirm
LCR
60H
Bank
X
ACT
Row
Bank
X
WRITE
X
Bank
01H
Protect
Device/
Confirm
LCR
60H
Bank
X
ACT
X
Bank
X
WRITE
X
Bank
F1H
Unprotect
Blocks/
Confirm
LCR
60H
Bank
X
ACT
X
Bank
X
WRITE
X
Bank
D0H
Erase
NVMODE
Register
LCR
30H
Bank
X
ACT
X
Bank
X
WRITE
X
Bank
C0H
Write
NVMODE
Register
LCR
A0H
Bank
X
ACT
X
Bank
X
WRITE
X
Bank
X
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-71
Deep Powerdown Operation with SyncFlash
19.8.6 Clock Suspend Timer Use with SyncFlash
The SyncFlash enters clock suspend mode when the CLKST[1:0] bits are set to 10 or 11 in the SDRAM control
register (SDCTL0/1). The clock to the SyncFlash memory will stop after a programmable delay following the last
access to the SyncFlash (64 clock cycles for CLKST=10 or 128 clock cycles for CLKST = 11). When CLKST is
set to 10 or 11, the active bank is not closed (no Precharge command is issued) before the entry into the clock
suspend mode. Figure 19-57 illustrates this timing relationship.
SDCLK
SDCKEx
64 (CLKST=10) or 128 (CLKST=11) clocks
ADDR COLUMNA COLUMN
B
tCL = 2
RAS,
READ
TBST
CAS,
COLUMNB
READ
SDWE
CSDx
DATA
DATAA
Figure 19-57. SyncFlash Clock Suspend Timer Operation Timing Diagram
19.8.7 Powerdown Operation with SyncFlash
The SyncFlash enters powerdown mode when the (CLKST [1:0] bits are set to 01 in the SDRAM control register
(SDCTL0/1) and only when no bank is active. In powerdown mode, the clock to the SyncFlash memory will stop.
Again, the powerdown mode can only entered when all banks within the memory area are inactive. Figure 19-58
illustrates the operation of SyncFlash powerdown mode.
SDCLK
SDCKEx
ROW
ADDR
RAS,
CAS,
SDWE
tRP (Minimum)
ACT
PRE-ALL
CSDx
DATA
Figure 19-58. SyncFlash Powerdown Operation Timing Diagram
19.9 Deep Powerdown Operation with SyncFlash
The SyncFlash enters deep powerdown mode when the MC9328MXS enters stop mode (both the MCU PLL and
System PLL are shut down). Upon entry of deep powerdown mode, all active memory banks are closed, the clock
input to the SyncFlash stops, and the RESET_SF signal is asserted. The SyncFlash exits deep powerdown mode
MC9328MXS Reference Manual, Rev. 1.1
19-72
Freescale Semiconductor
Deep Powerdown Operation with SyncFlash
after the MC9328MXS exits stop mode (when the MCU PLL and System PLL have waken up) and the clock to the
SyncFlash is stable. The RESET_SF signal is then deasserted. Figure 19-59 illustrates the operation of the
SyncFlash when entering deep powerdown mode.
Low-Power
Mode Signal normal
from CPU
MC9328MXS Stop Mode (PLLs shutdown)
normal
SDCLK
SDCKEx
ADDR
tRP (Minimum)
RAS,
CAS,
SDWE
PRE-ALL
CSDx
reset_sf
Figure 19-59. SyncFlash Deep Powerdown Operation Timing Diagram
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
19-73
Deep Powerdown Operation with SyncFlash
MC9328MXS Reference Manual, Rev. 1.1
19-74
Freescale Semiconductor
Chapter 20
General-Purpose Timers
The MC9328MXS contains two identical general-purpose 32-bit timers with programmable prescalers and
compare and capture registers. Each timer counter value can be captured using an external event and can be
configured to trigger a capture event on either the leading or trailing edges of an input pulse. The timer can also
generate an interrupt when the timer reaches a programmed value. Each timer has an 8-bit prescaler providing a
programmable clock frequency derived from PERCLK1. Figure 20-1 illustrates the general-purpose timers block
diagram.
1 Compare
PERCLK1
÷ 16
PERCLK1
Prescaler1
PCLK
CLK32
1 Capture
TIN
TIMER1_INT
1 Counter
Output
Logic
1 Control
Capture
Logic
1 Status
MPU Bus
2 Status
MPU Bus
TIN
Capture
Logic
2 Control
TIN
2 Capture
CLK32
Prescaler2
PCLK
TMR2OUT
Output
Logic
2 Counter
TIMER2_INT
PERCLK1
PERCLK1
÷ 16
2 Compare
Figure 20-1. General-Purpose Timers Block Diagram
The timers have the following features:
•
Maximum period of 512 × 65536 seconds at 32.768 kHz
•
10 ns resolution at 100 MHz
•
Programmable sources for the clock input, including external clock
•
Input capture capability with programmable trigger edge
•
Output compare with programmable mode
•
Free-run and restart modes
•
Software reset function
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
20-1
Operation
20.1 Operation
The clock that feeds the prescaler can be selected from the main clock (divided by 1 or by 16), from the timer input
pin (TIN), or from the 32 kHz clock (CLK32). The clock input source is determined by the clock source
(CLKSOURCE) field in the timer control registers (TCTL1 and TCTL2). The timer prescaler registers (TPRER1
and TPRER2) are used to select the divide ratio of the input clock that drives the main counter. The prescaler can
divide the input clock by a value between 1 and 256. When CLK32 is selected as the clock source, the timer
operates even while the PLL is in sleep mode (at that time, the PERCLK1 from the PLL is off).
Each timer can be configured for free-run or restart mode by programming the free-run/restart (FRR) bit in the
corresponding TCTLx register. In restart mode, after the compare value is reached, the counter resets to
0x00000000, the compare event (COMP) bit of the timer status register is set, an interrupt is issued if the interrupt
request enable (IRQEN) bit of the corresponding TCTLx register is set, and the counter resumes counting. This
mode is useful when you need to generate periodic events or audio tones when the free-running timer is used with
the timer output signals. In free-run mode, the compare function operates as it does in restart mode, however the
counter continues counting without resetting to 0x00000000. When 0xFFFFFFFF is reached, the counter rolls over
to 0x00000000 and keeps counting.
Each timer has a 32-bit capture register that takes a “snapshot” of the counter when a defined transition of the timer
input (TIN) is detected by the capture edge detector. The type of transition that triggers this capture is selected by
the capture edge (CAP) field of the corresponding TCTLx register. Pulses that produce the capture edge can be as
short as 20 ns. The minimum time between pulses is two PCLK periods.
When a capture or compare event occurs, the corresponding (CAPT or COMP) status bit is set in the timer status
register and an interrupt is posted if the capture function is enabled or if the IRQEN bit of the corresponding
TCTLx register is set. The free-running timer is disabled at reset.
When 1 is written to the software reset (SWR) bit in the TCTLx register, the module resets immediately. The reset
signal is asserted for three times the period of the 96 MHz SystemCLK cycle. For example, if the system clock
period is 10 ns, the reset signal is asserted for 30 ns and then is automatically released.
20.1.1 Pin Configuration for General-Purpose Timers
Figure 20-1 shows the pins used for the General-Purpose Timer module. These pins are multiplexed with other
functions on the device, and must be configured for General-Purpose Timer operation. Table 20-1 lists the pin
configuration for the General-Purpose Timers.
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 25.5.1, “Data Direction Registers,” on
page 25-8 for details.
Table 20-1. Pin Configuration
Pin
Setting
Configuration Procedure
TIN
Primary function of GPIO
Port A [1]
1. Clear bit 1 of Port A GPIO In Use Register (GIUS_A)
2. Clear bit 1 of Port A General Purpose Register (GPR_A)
TMR2OUT
Primary function of GPIO
Port D [31]
1. Clear bit 31 of Port D GPIO In Use Register (GIUS_D)
2. Clear bit 31 of Port D General Purpose Register (GPR_D)
MC9328MXS Reference Manual, Rev. 1.1
20-2
Freescale Semiconductor
Programming Model
20.2 Programming Model
The General-Purpose Timers module includes 6 user-accessible 32-bit registers for each timer. Table 20-2
summarizes these registers and their addresses.
Table 20-2. GP Timers Module Register Memory Map
Description
Name
Address
Timer Control Register 1
TCTL1
00202000
Timer Prescaler Register 1
TPRER1
00202004
Timer Compare Register 1
TCMP1
00202008
Timer Capture Register 1
TCR1
0020200C
Timer Counter Register 1
TCN1
00202010
Timer Status Register 1
TSTAT1
00202014
Timer Control Register 2
TCTL2
00203000
Timer Prescaler Register 2
TPRER2
00203004
Timer Compare Register 2
TCMP2
00203008
Timer Capture Register 2
TCR2
0020300C
Timer Counter Register 2
TCN2
00203010
Timer Status Register 2
TSTAT2
00203014
20.2.1 Timer Control Registers 1 and 2
Each timer control register (TCTL1 or TCTL2) controls the overall operation of the corresponding general-purpose
timer. Table 20-3 provides the register description. The TCTLx registers control the following:
•
Selecting the free-running or restart mode after a compare event
•
Selecting the capture trigger event
•
Controlling the output compare mode
•
Enabling the compare event interrupt
•
Selecting the prescaler clock source
•
Enabling and disabling the GP timer
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
20-3
Programming Model
TCTL1
TCTL2
Addr
00202000
00203000
Timer Control Register 1
Timer Control Register 2
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
OM
IRQEN
RESET
0x0000
BIT
15
14
13
12
11
10
9
SWR
TYPE
8
7
FRR
CAP
CLKSOURCE
TEN
rw
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 20-3. Timer 1 and 2 Control Registers Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
SWR
Bit 15
Software Reset—Controls the software reset function. When 1
is written to this bit, a reset signal is generated to the reset timer
module. The reset signal is active for 3 system clock cycles, and
then is automatically released. The software reset does not
reset the timer enable (TEN) bit.
Reserved
Bits 14–9
Reserved—These bits are reserved and should read 0.
FRR
Bit 8
Free-Run/Restart—Controls how the timer operates after a
compare event occurs. In free-run mode, the timer continues
running. In restart mode, the counter resets to 0x00000000 and
resumes counting.
0 = Restart mode
1 = Free-run mode
CAP
Bits 7–6
Capture Edge—Controls the operation of the capture function.
The direction (DIRx) bit in the corresponding port register must
be set to 0 for the capture function to operate correctly.
00 = Disable the capture function
01 = Capture on the rising edge and
generate an interrupt
10 = Capture on the falling edge and
generate an interrupt
11 = Capture on the rising and falling
edges and generate an interrupt
OM
Bit 5
Output Mode—Controls the output mode of the timer after a
reference-compare event occurs. This bit has no function unless
the CAP field is set to 0. When the counter value (COUNT)
period is less than 40 ns, timer out (TMR2OUT) is not valid.
0 = Active-low pulse for one IPG_CLK
period
1 = Toggle output
IRQEN
Bit 4
Interrupt Request Enable—Enables/Disables the generation of
an interrupt on a compare event.
0 = Disable the compare interrupt
1 = Enable the compare interrupt
0 = No software reset sent
1 = Software reset sent to timer module
MC9328MXS Reference Manual, Rev. 1.1
20-4
Freescale Semiconductor
Programming Model
Table 20-3. Timer 1 and 2 Control Registers Description (continued)
Name
Description
Settings
CLKSOURCE
Bits 3–1
Clock Source—Selects the source of the clock to the prescaler.
The stop-count setting freezes the timer at its current value.
000 = Stop count (clock disabled)
001 = PERCLK1 to prescaler
010 = PERCLK1 ÷16 to prescaler
011 = TIN to prescaler
1xx = 32 kHz clock to prescaler
TEN
Bit 0
Timer Enable—Enables/Disables the general-purpose timer.
The TEN bit can be reset only by a hardware asynchronous
reset, not by the SWR reset.
0 = Timer is disabled (counter reset to
0x00000000)
1 = Timer is enabled
Note: When configuring this control register, configure all
other bits before configuring the TEN bit.
20.2.2 Timer Prescaler Registers 1 and 2
Each timer prescaler register (TPRER1 and TPRER2) controls the divide ratio of the associated 8-bit prescaler.
The settings for the registers are described in Table 20-4.
TPRER1
TPRER2
Addr
00202004
00203004
Timer Prescaler Register 1
Timer Prescaler Register 2
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
PRESCALER
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 20-4. Timer 1 and 2 Prescaler Registers Description
Name
Description
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
PRESCALER
Bits 7–0
Prescaler—Determines the division value (1–256) of the prescaler.
Settings
0x00 = Divide by 1
0x01 = Divide by 2
...
0xFF = Divide by 256
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
20-5
Programming Model
20.2.3 Timer Compare Registers 1 and 2
Each timer compare register (TCMP1 and TCMP2) contains the value that is compared with the free-running
counter. A compare event is generated when the counter matches the value in this register. This register is set to
0xFFFFFFFF at system reset. Table 20-5 provides the register description.
TCMP1
TCMP2
BIT
Addr
00202008
00203008
Timer Compare Register 1
Timer Compare Register 2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
COMPARE VALUE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
6
5
4
3
2
1
0
RESET
0xFFFF
BIT
15
14
13
12
11
10
9
8
COMPARE VALUE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
RESET
0xFFFF
Table 20-5. Timer 1 and 2 Compare Registers Description
Name
COMPARE VALUE
Bits 31–0
Description
Compare Value—Holds the value at which a compare event will be triggered.
MC9328MXS Reference Manual, Rev. 1.1
20-6
Freescale Semiconductor
Programming Model
20.2.4 Timer Capture Registers 1 and 2
Each read-only timer capture register (TCR1 and TCR2) stores the counter value when a capture event occurs. This
register is read-only, and resets to 0x00000000. Table 20-6 provides the register description.
TCR1
TCR2
BIT
Addr
0020200C
0020300C
Timer Capture Register 1
Timer Capture Register 2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CAPTURE VALUE
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
CAPTURE VALUE
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 20-6. Timer 1 and 2 Capture Registers Description
Name
CAPTURE VALUE
Bits 31–0
Description
Capture Value—Stores the counter value that existed at the time of the capture event.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
20-7
Programming Model
20.2.5 Timer Counter Registers 1 and 2
Each read-only timer counter register (TCN1 and TCN2) contains the current count. The timer counter registers
can be read at any time without affecting the current count. Table 20-7 describes the register descriptions.
TCN1
TCN2
BIT
Addr
00202010
00203010
Timer Counter Register 1
Timer Counter Register 2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
COUNT
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
COUNT
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 20-7. Timer 1 and 2 Counter Registers Description
Name
COUNT
Bits 31–0
Description
Counter Value—Contains the current count value.
MC9328MXS Reference Manual, Rev. 1.1
20-8
Freescale Semiconductor
Programming Model
20.2.6 Timer Status Registers 1 and 2
Each read-only timer status register (TSTAT1 and TSTAT2) indicates the corresponding timer’s status. When a
capture event occurs, the CAPT bit is set. When a compare event occurs, the COMP bit is set. These bits must be
cleared to clear the interrupt, if it is enabled. These bits are cleared by writing 0x0, write 0 to clear—w0c, and will
clear only if they have been read while set. This ensures that an interrupt is not missed if it occurs between the
status read and the interrupt clear. The registers and settings are described Table 20-8.
TSTAT1
TSTAT2
Addr
00202014
00203014
Timer Status Register 1
Timer Status Register 2
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
CAPT
COMP
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r/w0c
r/w0c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 20-8. Timer 1 and 2 Status Registers Description
Name
Description
Settings
Reserved
Bits 31–2
Reserved—These bits are reserved and should read 0.
CAPT
Bit 1
Capture Event—Indicates when a capture event occurs.
0 = No capture event occurred
1 = A capture event occurred
COMP
Bit 0
Compare Event—Indicates when a compare event occurs.
0 = No compare event occurred
1 = A compare event occurred
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
20-9
Programming Model
MC9328MXS Reference Manual, Rev. 1.1
20-10
Freescale Semiconductor
Chapter 21
Universal Asynchronous Receiver/Transmitters (UART)
Modules
21.1 Introduction
This chapter describes the universal asynchronous receiver/transmitter (UART) modules in the MC9328MXS. The
UART modules are capable of standard RS-232 non-return-to-zero (NRZ) encoding format and IrDA-compatible
infrared modes. Each UART provides serial communication capability with external devices through an RS-232
cable or through use of external circuitry that converts infrared signals to electrical signals (for reception) or
transforms electrical signals to signals that drive an infrared LED (for transmission) to provide low speed IrDA
compatibility to the MC9328MXS.
UARTs transmit and receive characters that are either 7 or 8 bits in length (program selectable). To transmit, data
is written from the peripheral data bus to a 32-byte transmitter FIFO (TxFIFO). This data is passed to the shift
register and shifted serially out on the transmitter pin (TXD). To receive, data is received serially from the receiver
pin (RXD) and stored in a 32-half-words-deep receiver FIFO (RxFIFO). The received data is retrieved from the
RxFIFO on the peripheral data bus. The RxFIFO and TxFIFO generate maskable interrupts as well as DMA
Requests when the data level in each of the FIFO reaches a programmed threshold level.
The UARTs generate baud rates based on a configurable divisor and input clock. The UARTs also contain
configurable auto baud detection circuitry to receive 1 or 2 stop bits as well as odd, even, or no parity. The receiver
detects framing errors, idle conditions, BREAK characters, parity errors, and overrun errors.
The TXD pin is configurable for open-drain operation at the chip boundary. The UART modules use a software
interface for control of modem operations and have a serial infrared (IR) module that decodes and encodes
IrDA-compatible serial IR data.
21.2 Features
•
7 or 8 data bits
•
1 or 2 stop bits
•
Programmable parity (even, odd, and no parity)
•
Full 8-wire serial DCE interface1 for modem flow control on UART
•
Hardware flow control support for request to send (RTS) and clear to send (CTS) signals
•
Software flow control support for data set ready (DSR), data carrier detect (DCD), and ring indicator (RI)
signals on UART
•
Edge selectable RTS and data terminal ready (DTR) edge detect interrupts
•
Status flags for various flow control and FIFO states
•
Serial IR interface (low speed, IrDA-compatible) enable via UART Control Register 1
1. UART GPIO pins must be used for DTR, DSR, DCD, and RI functions.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-1
Features
•
Voting logic for improved noise immunity (16x oversampling)
•
Transmitter FIFO empty interrupt suppression
•
UART internal clocks enable/disable
•
Auto baud rate detection
•
Receiver and transmitter enable/disable
•
RTS, IrDA asynchronous wake (AIRINT), and receive asynchronous wake (AWAKE) interrupts wake the
ARM920T processor from STOP mode
•
Twenty maskable interrupts
•
Two DMA Requests (TxFIFO DMA Request and RxFIFO DMA Request)
•
Escape character sequence detection
•
Software reset (SRST)
21.2.1 Module Interface
The serial and modem control signals used by the UART module are identified and described in Table 21-1.
Table 21-1. UART Module Interface Signals
Signal Name
I/O
Active UART
Comments
Serial Signals
UART1_TXD
UART2_TXD
OUT
HIGH
Transmitter serial output (multiplexed IR or NRZ encoding format)
UART1_RXD
UART2_RXD
IN
HIGH
Receiver serial input (multiplexed IR or NRZ encoding format)
Modem Control Signals
UART1_RTS
UART2_RTS
IN
LOW
Controls the transmitter. By asserting RTS, the modem signals ready to receive to the
UART. Normally, the transmitter waits until UARTx_RTS is active (low) before
transmitting a character, however when the ignore UARTx_RTS pin (IRTS) bit is set,
the transmitter sends each character as it is ready to transmit. When this pin serves as
a general purpose input, its status is read in the RTSS bit. This pin can post an
interrupt on any transition of this pin and wake the ARM9 core from STOP mode on its
assertion. When RTS is negated during a transmission, the UART transmitter finishes
transmitting the current character and shuts off. The contents of the TxFIFO
(characters to be transmitted) remain undisturbed.
UART1_CTS
UART2_CTS
OUT
LOW
This output pin serves two purposes. Normally, the receiver indicates that it is ready to
receive data by asserting this pin (low). When the receiver detects a pending overrun,
it negates this pin. For other applications, this pin functions as a general purpose
output controlled by the CTS bit in UART Control Register 2.
UART2_DSR OUT
LOW
2
DSR signal for modem control
UART2_RI
OUT
LOW
2
RI signal for modem control
UART2_DCD OUT
LOW
2
DCD signal for modem control
MC9328MXS Reference Manual, Rev. 1.1
21-2
Freescale Semiconductor
Features
Table 21-1. UART Module Interface Signals (continued)
Signal Name
I/O
UART2_DTR
IN
Active UART
LOW
2
Comments
DTR signal for modem control
21.2.2 UART Pin Configuration
Table 21-2 lists the pins used for the UART 1 UART 2 modules. These pins are multiplexed with other functions
on the device, and must be configured for UART operation.
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 25.5.1, “Data Direction Registers,” on
page 25-8 for details.
Table 21-2. Pin Configuration
Pin
Setting
Configuration Procedure
UART1_RXD
Primary function of
GPIO Port C [12]
1.Clear bit 12 of Port C GPIO In Use Register (GIUS_C)
2.Clear bit 12 of Port C General Purpose Register (GPR_C)
UART1_TXD
Primary function of
GPIO Port C [11]
1.Clear bit 11 of Port C GPIO In Use Register (GIUS_C)
2.Clear bit 11 of Port C General Purpose Register (GPR_C)
UART1_RTS
Primary function of
GPIO Port C [10]
1.Clear bit 10 of Port C GPIO In Use Register (GIUS_C)
2.Clear bit 10 of Port C General Purpose Register (GPR_C)
UART1_CTS
Primary function of
GPIO Port C [9]
1.Clear bit 9 of Port C GPIO In Use Register (GIUS_C)
2.Clear bit 9 of Port C General Purpose Register (GPR_C)
UART2_RXD
Primary function of
GPIO Port B [31]
1.Clear bit 31 of Port B GPIO In Use Register (GIUS_B)
2.Clear bit 31 of Port B General Purpose Register (GPR_B)
UART2_TXD
Primary function of
GPIO Port B [30]
1.Clear bit 30 of Port B GPIO In Use Register (GIUS_B)
2.Clear bit 30 of Port B General Purpose Register (GPR_B)
UART2_RTS
Primary function of
GPIO Port B [29]
1.Clear bit 29 of Port B GPIO In Use Register (GIUS_B)
2.Clear bit 29 of Port B General Purpose Register (GPR_B)
UART2_CTS
Primary function of
GPIO Port B [28]
1.Clear bit 28 of Port B GPIO In Use Register (GIUS_B)
2.Clear bit 28 of Port B General Purpose Register (GPR_B)
UART2_DSR
Alternate function
of GPIO Port D [10]
1.Clear bit 10 of Port D GPIO In Use Register (GIUS_D)
2.Set bit 10 of Port D General Purpose Register (GPR_D)
UART2_RI
Alternate function
of GPIO Port D [9]
1.Clear bit 9 of Port D GPIO In Use Register (GIUS_D)
2.Set bit 9 of Port D General Purpose Register (GPR_D)
UART2_DCD
Alternate function
of GPIO Port D [8]
1.Clear bit 8 of Port D GPIO In Use Register (GIUS_D)
2.Set bit 8 of Port D General Purpose Register (GPR_D)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-3
Interrupts and DMA Requests
Table 21-2. Pin Configuration (continued)
Pin
UART2_DTR
Setting
Alternate function
of GPIO Port D [7]
Configuration Procedure
1.Set bit 7 of Port D GPIO In Use Register (GIUS_D)
2.Set bit 7 of Port D General Purpose Register (GPR_D)
21.3 Interrupts and DMA Requests
Table 21-3 lists all of the interrupts that are output on each interrupt output. See the individual register descriptions
for explanation of available enables and status flags.
Table 21-3. Interrupts and DMA
Interrupt
Output
Interrupt
Enable
Enable Register
Location
Interrupt
Flag
Flag Register
Location
UART_MINT_DTR
DTREN
UCR3_2 (bit 13)
DTRF
USR2_2 (bit 13)
UART_MINT_RTS
RTSDEN
RTSEN
UCR1_1/UCR1_2 (bit 5)
UCR2_1/UCR2_2 (bit 4)
RTSD
RTSF
USR1_1/USR1_2 (bit 12)
USR2_1/USR2_2 (bit 4)
UART_MINT_RX
RRDYEN
IDEN
DREN
RXDSEN
UCR1_1/UCR1_2 (bit 9)
UCR1_1/UCR1_2 (bit 12)
UCR4_1/UCR4_2 (bit 0)
UCR3_1/UCR3_2 (bit 6)
RRDY
IDLE
RDR
RXDS
USR1_1/USR1_2 (bit 9)
USR2_1/USR2_2 (bit 12)
USR2_1/USR2_2 (bit 0)
USR1_1/USR1_2 (bit 6)
UART_MINT_TX
TXMPTYEN
TRDYEN
TCEN
UCR1_1/UCR1_2 (bit 6)
UCR1_1/UCR1_2 (bit 13)
UCR4_1/UCR4_2 (bit 3)
TXFE
TRDY
TXDC
USR2_1/USR2_2 (bit 14)
USR1_1/USR1_2 (bit 13)
USR2_1/USR2_2 (bit 3)
UART_MINT_UARTC
OREN
BKEN
WKEN
ADEN
ESCI
ENIRI
AIRINTEN
AWAKEN
UCR4_1/UCR4_2 (bit 1)
UCR4_1/UCR4_2 (bit 2)
UCR4_1/UCR4_2 (bit 7)
UCR1_1/UCR1_2 (bit 15)
UCR2_1/UCR2_2 (bit 15)
UCR4_1/UCR4_2 (bit 8)
UCR3_1/UCR3_2 (bit 5)
UCR3_1/UCR3_2 (bit 4)
ORE
BRCD
WAKE
ADET
ESCF
IRINT
AIRINT
AWAKE
USR2_1/USR2_2 (bit 1)
USR2_1/USR2_2 (bit 2)
USR2_1/USR2_2 (bit 7)
USR2_1/USR2_2 (bit 15)
USR1_1/USR1_2 (bit 11)
USR2_1/USR2_2 (bit 8)
USR1_1/USR1_2 (bit 5)
USR1_1/USR1_2 (bit 4)
UART_MINT_PFRERR
FRAERREN
PARERREN
UCR3_1/UCR3_2 (bit 11)
UCR3_1/UCR3_2 (bit 12)
FRAERR
PARITYERR
USR1_1/USR1_2 (bit 10)
USR1_1/USR1_2 (bit 15)
UART_RX_DMAREQ
RDMAEN
UCR1_1/UCR1_2 (bit 8)
RRDY
USR1_1/USR1_2 (bit 9)
UART_TX_DMAREQ
TDMAEN
UCR1_1/UCR1_2 (bit 3)
TRDY
USR1_1/USR1_2 (bit 13)
21.4 General UART Definitions
Definitions of terms that occur the following discussions are given in this section.
•
Bit time—The period of time required to serially transmit or receive 1 bit of data (1 cycle of the baud rate
frequency).
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21-4
Freescale Semiconductor
General UART Definitions
•
Start bit—The bit time of a logic 0 that indicates the beginning of a data frame. A start bit begins with a
1-to-0 transition, and is preceded by at least 1 bit time of logic 1.
•
Stop bit—1 bit time of logic 1 that indicates the end of a data frame.
•
BREAK—A frame in which all of the data bits, including the stop bit, are logic 0. This type of frame is
usually sent to signal the end of a message or the beginning of a new message.
•
Frame—A start bit followed by a specified number of data or information bits and terminated by a stop bit.
The number of data or information bits depends on the format specified and must be the same for the
transmitting device and the receiving device. The most common frame format is 1 start bit followed by 8
data bits (least significant bit first) and terminated by 1 stop bit. An additional stop bit and a parity bit also
can be included.
•
Framing error—An error condition that occurs when the stop bit of a received frame is missing, usually
when the frame boundaries in the received bit stream are not synchronized with the receiver bit counter.
Framing errors can go undetected if a data bit in the expected stop bit time happens to be a logic 1. A framing
error is always present on the receiver side when the transmitter is sending BREAKs. However, when the
UART is programmed to expect 2 stop bits and only the first stop bit is received, this is not a framing error
by definition.
•
Parity error—An error condition that occurs when the calculated parity of the received data bits in a frame
does not match the parity bit received on the RXD input. Parity error is calculated only after an entire frame
is received.
•
Idle—One in NRZ encoding format and selectable polarity in IrDA mode.
•
Overrun error—An error condition that occurs when the latest character received is ignored to prevent
overwriting a character already present in the UART receive buffer (RxFIFO). An overrun error indicates
that the software reading the buffer (RxFIFO) is not keeping up with the actual reception of characters on
the RXD input.
Computer
UART
(DTE)
TXD
RXD
RXD
TXD
RTS
RTS
CTS
CTS
DTR
DTR
DSR
DSR
DCD
DCD
RI
MC9328MXS
UART
(DCE)
UART
(DCE)
RI
Figure 21-1. General Connections for a UART with a Modem
21.4.1 RTS—UART Request To Send
The UART request to send input controls the transmitter. The modem or other terminal equipment signals the
UART when it is ready to receive by asserting RTS on the UARTx_RTS pin. Normally, the transmitter waits until
this signal is active (low) before transmitting a character, however when the ignore UARTx_RTS pin (IRTS) bit is
set, the transmitter sends a character as soon as it is ready to transmit. This pin can post an interrupt on any
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-5
General UART Definitions
transition of this pin and wakes the ARM920T processor from STOP mode on its assertion. When RTS is negated
during a transmission, the UART transmitter finishes transmitting the current character and shuts off. The contents
of the TxFIFO (characters to be transmitted) remain undisturbed.
21.4.2 RTS Edge Triggered Interrupt
The input to the UARTx_RTS pin can be programmed to generate an interrupt on a selectable edge. The operation
of the RTS edge triggered interrupt (RTSF) is summarized in Table 21-4.
To enable the UARTx_RTS pin to generate an interrupt, set the request to send interrupt enable (RTSEN) bit in the
UART Control Register 2 (UCR2_x) to 1. Writing 1 to the RTS edge triggered interrupt flag (RTSF) bit in
UCR2_x clears the interrupt flag.The interrupt can occur on the rising edge, falling edge, or either edge of the RTS
input. The request to send edge control (RTEC) field in UCR2_x programs the edge that generates an interrupt.
When RTEC is set to 0x00 and RTSEN = 1, the interrupt occurs on the rising edge (default). When RTEC is set to
0x01 and RTSEN = 1, the interrupt occurs on the falling edge. When RTEC is set to 0x1X and RTSEN = 1, the
interrupt occurs on either edge.This is a synchronous interrupt. The RTSF bit is cleared by writing 1 to it. Writing 0
to RTSF has no effect.
Table 21-4. RTS Edge Triggered Interrupt Truth Table
RTS
RTSEN
RTEC [1]
RTEC [0]
RTSF
Interrupt Occurs On…
UART_MINT_RTS
X
0
X
X
0
Interrupt disabled
1
1–>0
1
0
0
0
Rising edge
1
0–>1
1
0
0
1
Rising edge
0
1–>0
1
0
1
1
Falling edge
0
0–>1
1
0
1
0
Falling edge
1
1–>0
1
1
X
1
Either edge
0
0–>1
1
1
X
1
Either edge
0
There is another RTS interrupt that is not programmable, however it asserts the RTS Delta (RTSD) bit when the
RTS pin changes state. The status bit RTSD asserts the UART_MINT_RTS interrupt when the RTS delta interrupt
enable = 1. This is an asynchronous interrupt. The RTSD bit is cleared by writing 1 to it. Writing 0 to the RTSD bit
has no effect.
21.4.3 DTR—Data Terminal Ready
The data terminal ready signal to the UART2_DTR indicates the general readiness of the data terminal equipment
(DTE). When the connection between the UART and the DTE is established, the DTR signal must remain active
throughout the whole connection time. The DTR signal is only available on UART2. In general, the DTR and DSR
signals establish the connection and the RTS and CTS signals control the data transfer and the transfer direction
(for half-duplex configurations). The DTR signal is like a main switch—when the DTR signal is inactive the RTS
and CTS signals have no effect and the modem does not respond to control signals. This functionality is not
implemented in the hardware and is the result of how the registers in the UART are programmed.
MC9328MXS Reference Manual, Rev. 1.1
21-6
Freescale Semiconductor
General UART Definitions
21.4.4 DTR Edge Triggered Interrupt
The DTR signal can be used to generate an interrupt on a selectable edge. To enable the DTR signal to
generate an interrupt, set the data terminal ready interrupt enable (DTREN) bit in UART Control
Register 3 (UCR3_x). Clear the DTRF bit by writing 1 to it. Writing 0 to the DTRF bit has no effect.
Write to the DTR interrupt edge control (DPEC) field in UCR3_x to select the edge that generates an
interrupt. When the DPEC field is set to 00b and DTREN = 1, the interrupt occurs on the rising edge
(default). When the bits are set to 01b and DTREN = 1, the interrupt occurs on the falling edge. When the
bits are set to 1Xb and DTREN = 1, the interrupt occurs on either edge. This is a synchronous interrupt.
Table 21-5. DTR Edge Triggered Interrupt Truth Table
DTR
DTREN
DPEC [1]
DPEC [0]
DTRF
Interrupt Occurs On…
UART_MINT_DTR
X
0
X
X
0
Interrupt disabled
1
1–>0
1
0
0
0
Rising edge
1
0–>1
1
0
0
1
Rising edge
0
1–>0
1
0
1
1
Falling edge
0
0–>1
1
0
1
0
Falling edge
1
1–>0
1
1
X
1
Either edge
0
0–>1
1
1
X
1
Either edge
0
21.4.5 DSR—Data Set Ready
The UART uses the DSR signal to inform the DTE that it is powered on, all preparations are complete, and
that it is ready to communicate with the DTE.
21.4.6 DCD—Data Carrier Detect
The UART uses this signal to inform the DTE that it detected the carrier signal and the connection is
established. This signal remains active as long as the connection remains established.
21.4.7 RI—Ring Indicator
The UART uses this signal to inform the DTE when a ring occurs.
21.4.8 CTS—Clear To Send
Normally, the receiver indicates that it is ready to receive data by asserting this pin (low). When the CTS
trigger level is programmed to trigger at 32 characters received and the receiver detects the valid start bit of
the 33rd character, it deasserts this pin.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-7
General UART Definitions
21.4.9 Programmable CTS Deassertion
The CTS output can also be programmed to deassert when the RxFIFO reaches a certain level. Setting the CTS
trigger level at any value less than 32 deasserts the CTS pin on detection of the valid start bit of the N + 1 character
(where N is the trigger level setting). The receiver continues to receive characters until the RxFIFO is full.
21.4.10 TXD—UART Transmit
This is the transmitter serial output. When operating in normal mode, NRZ encoded data is output. When operating
in infrared mode, a 3/16 bit-period pulse is output for each 0 bit transmitted, and no pulse is output for each 1 bit
transmitted. For RS-232 applications, this pin must be connected to an RS-232 transmitter.
21.4.11 RXD—UART Receive
This is the receiver serial input. When operating in normal mode, NRZ encoded data is expected. When operating
in infrared mode, a narrow pulse is expected for each 0 bit received and no pulse is expected for each 1 bit
received. External circuitry must convert the IR signal to an electrical signal. RS-232 applications require an
external RS-232 receiver to convert voltage levels.
MC9328MXS Reference Manual, Rev. 1.1
21-8
Freescale Semiconductor
Sub-Block Description
DTR
Transmitter
Data Path
RI
DCD
DSR
IF Interface
DCE Interface
PERCLK1
from PLL &
Clock Cont
Programmable
Divider
UFC:RFDIV[2:0]
CTS
Receiver
Data Path
TxFIFO
Peripheral Gasket Block
Module
Interface Gasket Block (AIPI)
RxFIFO
RTS
TX
RX
Binary Rate
Multiplier
(BRM)
UART
REF_CLK
Data
To Auto
Baud
Control
-15- -16- -1-
-2-
-3-
-4-
-5-
-6-
-7-
-8-
-9- -10- -11- -12- -13- -14- -15- -16- -1-
-2-
-3-
CKIH
BRM_CLK
Bit Stream
BIT 0
Bit 1
Bit 2
INC = 0, MOD = 1 –> Ratio = 0.05 = 1/2
Possible
Parity
Bit
8-Bit Data Format
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
RXD / TXD
STOP
BIT
Next
Start
Bit
Standard
Data
Figure 21-2. UART Block Diagram and Clock Generation Diagram
21.5 Sub-Block Description
The UART module is easy to use from both hardware and software perspectives. The working registers shown in
Table 21-6 provide all status (USR1_x, USR2_x) and control (UCR1_x through UCR4_x) functions. A separate
test register is provided for applications that require it. The binary rate multiplier (BRM) registers (UBIR_x,
UBMR_x, BMPR1_x, and BMPR4_x) control the UART bit rate and there is a transmitter register and a receiver
register all shown in Table 21-6.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-9
Sub-Block Description
Table 21-6. UART Register Summary
Status
Registers
Control
Registers
BRM
Registers
BRC
Registers
1
USR1_1
USR2_1
UCR1_1
UCR2_1
UCR3_1
UCR4_1
UBIR_1
UBMR_1
BMPR1_1
BMPR4_1
UBRC_1
2
USR1_2
USR2_2
UCR1_2
UCR2_2
UCR3_2
UCR4_2
UBIR_2
UBMR_2
BMPR1_2
BMPR4_2
UBRC_2
UART
Esc
Character
Registers
Transmitter
Registers
Receiver
Registers
UESC_1
UTIM_1
UTXD_1
URXD_1
UESC_2
UTIM_2
UTXD_2
URXD_2
The transmit and receive registers are optimized for a 32-bit bus. All status bits associated with the received data
are accessible along with the data in a single read. Except for the transmit data (TX_DATA) field in the UART
Transmitter Registers, all register bits are readable and most are read/write. The UART Baud Rate Count (BRC)
Register performs automatic baud rate detection. There are also two registers for the escape sequence detection, the
UART Escape Character Register (UESC_x) and the UART Escape Timer Register (UTIM_x). The following
sections describe the basic functionality of the major blocks in UART module.
The MC9328MXS only supports a 16 MHz reference frequency. The reference frequency is defined as the input
peripheral clock, PERCLK1, divided by the value of the RFDIV [2:0] bits in the UFCR. Also note that the
frequency of the system/CPU clock (HCLK/BCLK) must be greater than the UART reference frequency. For
example, if the UART reference frequency is 16 MHz, BCLK must be greater than 16 MHz. If the BCLK
frequency is not greater, some of the UART features may not operate properly. For more details on BLCK please
refer to Chapter 12, “Phase-Locked Loop and Clock Controller.”
It is recommended to use a reference frequency of 16 MHz. Since the default (a maximum) System PLL frequency
is 96 MHz, 16 MHz is an integer multiple of 96 MHz. The accuracy of the reference frequency is needed to
accurately determine auto baud frequencies and break detect. The System PLL default setting of 96 Mhz also
assumes the use of a 32 kHz crystal. If a different crystal frequency is used (such as a 32.768 kHz crystal), the PLL
would need to be re-programmed for 96 MHz in order for an accurate 16 MHz ref frequency to be produced.
Although reference frequencies of 25 MHz and 30 MHz can also be used to determine features such as auto baud
detection and break detect, these are not integer multiples of the default (and maximum) System PLL of 96 MHz.
21.5.1 Transmitter
The transmitter accepts a parallel character from the ARM920T processor and transmits it serially. The start, stop,
and parity (when enabled) bits are added to the character. When the ignore RTS bit (IRTS) is set, the transmitter
sends a character as soon as it is ready to transmit. RTS can be used to provide flow-control of the serial data.
When RTS is negated (high), the transmitter finishes sending the character in progress (if any), stops, and waits for
RTS to be asserted (low) again. Generation of BREAK characters and parity errors (for debugging purposes) is
supported. The transmitter operates from the 1x clock provided by the BRM. Normal NRZ encoded data is
transmitted when the IR interface is disabled.
The transmitter FIFO (TxFIFO) contains 32 bytes. The data is written to TxFIFO by writing to the appropriate
register (UTXnD_x) with the byte data to the [7:0] bits. The TxFIFO is addressed using UTXnD_x register
(depending on if you are using UART 12) with any one of the 16 addresses (0x00212040–0x0021207C) and the
MC9328MXS Reference Manual, Rev. 1.1
21-10
Freescale Semiconductor
Sub-Block Description
data is written consecutively if the TxFIFO is not full or is read consecutively if the TxFIFO is not empty. If the
TxFIFO is full and data is again attempted to be written to the FIFO, the overrun bit will be set and data cannot be
written unless a read is first performed.
21.5.2 Transmitter FIFO Empty Interrupt Suppression
The transmitter FIFO empty interrupt suppression logic suppresses the interrupt between writes to the TxFIFO.
When a character is written to the TxFIFO, it is immediately transferred to the transmitter shift register
(PISO_OUT) on the next transmit baud rate clock (when the transmitter is enabled). The suppression logic allows
the software to write another character to the TxFIFO before the interrupt is asserted. When the transmitter shift
register empties before another character is written to the TxFIFO, the interrupt is asserted. Writing data (even a
single character) to the TxFIFO releases the interrupt. The interrupt is asserted on the following conditions:
•
System reset
•
UART module reset
•
When a single character has been written to Transmitter FIFO and then the Transmitter FIFO and the
Transmitter Shift Register become empty until another character is written to the Transmitter FIFO.
•
The last character in the TxFIFO is transferred to the shift register, when TxFIFO contains two or more
characters. See Figure 21-3 on page 21-12.
To provide system bus bandwidth efficiency when filling the transmit FIFO, there is a threshold called Transmitter
Trigger Level control (TXTL) which allows a maskable interrupt to be generated whenever the data level in the
TxFIFO falls below the selected threshold. The following conditions are required to avoid the TxFIFO being
overwritten, thus affecting parity calculation and data pattern transmission.
1. Maximum 32 bytes can be written into TxFIFO when transmission is completed.
USR2 bit[3] TXDC = 1, requires the use of polling or interrupt service routine via source UART_MINT_TX
with UCR1/TXEMPTYEN = 0, UCR1/TRDYEN = 0 and UCR4/TCEN = 1
2. Maximum 31 bytes can be written into TxFIFO when the FIFO is empty.
USR2 bit[14] TXFE = 1, requires the use of polling or interrupt service routine via source
UART_MINT_TX with UCR1/TXEMPTYEN = 1, UCR1/TRDYEN = 0 and UCR4/TCEN = 0
3. Write 32-TXTL bytes into TxFIFO when data level in TxFIFO falls below the selected threshold
TXTL.
USR1 bit[13] TRDY = 1, scenario where DMA is used with UCR1/TDMAEN = 1
Table 21-7. Number of Characters Allowed to be Written into TxFIFO
USR2/TXDC
USR2/TXFE
USR1/TRDY
1
1
1
32
–
–
0
1
1
31
–
–
0
0
1
32–n
–
–
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-11
Sub-Block Description
Reset = Peripheral Reset OR Software Reset
Assert
Transmitter
FIFO Empty
Flag
Y
Transmitter
FIFO
Empty
Reset
N
Deassert
Transmitter
FIFO Empty
Flag
Deassert
Transmitter
FIFO Empty
Flag
Y
Transmitter
FIFO
Empty
N
Deassert
Transmitter
FIFO Empty
Flag
Reset
N
Deassert
Transmitter
FIFO Empty
Flag
Transmitter
Shift Register
Empty
Reset
Y
Y
Transmitter N
FIFO Contains > 2
Characters
Reset
N
Transmitter
FIFO
Empty
Reset
Y
Figure 21-3. Transmitter FIFO Empty Interrupt Suppression Flow Chart
21.5.3 Receiver
The receiver accepts a serial data stream and converts it into parallel characters. When enabled, it searches for a
start bit, qualifies it, and samples the following data bits at the bit-center. Jitter tolerance and noise immunity are
provided by sampling at a 16x rate and using voting techniques to clean up the samples. Once the start bit is found,
the data bits, parity bit (if enabled), and stop bits (either 1 or 2 depending on user selection) are shifted in. Parity is
checked and its status reported in the appropriate register (either URXDn_1 2) when parity is enabled. Frame errors
and BREAKs are also checked and reported. When a new character is ready to be received by the RxFIFO, the
receive data ready (RDR) bit in the UART Status Register 2 (USR2_x) is asserted and an interrupt is posted (if
MC9328MXS Reference Manual, Rev. 1.1
21-12
Freescale Semiconductor
Sub-Block Description
DREN = 1). If the receiver trigger level is set to 0, the receiver ready interrupt flag (RRDY) is asserted and an
interrupt is posted if the receiver ready interrupt enable bit is set (RRDYEN = 1). If any UART Receiver Register
(URXDn_x) is read as a word and there is only 1 character in the RxFIFO, the interrupt generated by the RRDY bit
is automatically cleared and the data along with 4 status bits are read by the ARM920T processor (see the bit
descriptions in Section 21.7.8, “UART Status Register 1,” on page 21-40 and Section 21.7.9, “UART Status
Register 2,” on page 21-42). The RRDY bit is cleared when the data in the RxFIFO falls below the programmed
trigger level.
Normal NRZ encoded data is expected when the IR interface is disabled.
The RxFIFO contains 32 half-words. The data is read from the RxFIFO by reading the half-word data in the [15:0]
bits in the appropriate register for the UART being used (URXDn_x). The RxFIFO is addressed using the
aforementioned register with any one of the 16 addresses and the data is written consecutively if the RxFIFO is not
full, or is read consecutively if the RxFIFO is not empty. When additional data is written to the RxFIFO while it is
full, the write operation cannot complete unless a read is performed. If a write is performed on the RxFIFO when it
is full, the ORE bit is set in the appropriate USR2_x register. The ORE bit is cleared by writing 1 to it.
21.5.4 Idle Line Detect
The receiver logic block includes the ability to detect an idle line. Idle lines indicate the end or the beginning of a
message. For an idle condition to occur, there must be at least 1 word in the RxFIFO and the RXD pin must be idle
for more than a configured number of frames.
When the idle condition detected interrupt enable (IDEN) bit in the UART Control Register 1 (UCR1_x) is set and
the line is idle for 4 (default), 8, 16, or 32 (maximum) frames, the detection of an idle condition flags an interrupt.
When an idle condition is detected, the IDLE bit in the appropriate register (USR2_x) is set. Clear the IDLE bit by
writing 1 to it. Writing 0 to the IDLE bit has no effect.
21.5.4.1 Idle Condition Detect Configuration
The idle condition detect (ICD [1:0]) field is located in the UART Control Register 1. If the bits are set to 00b,
RXD must be idle for more than 4 frames before the IDLE bit is asserted. If the bits are set to 01b, RXD must be
idle for more than 8 frames before the IDLE bit is asserted. If the bits are set to 10b, RXD must be idle for more
than 16 frames before the IDLE bit is asserted. If the bits are set to 11b, RXD must be idle for more than 32 frames
before the IDLE bit is asserted (see Table 21-8).
Table 21-8. IDLE Detection Truth Table
IDEN
ICD [1]
ICD [0]
IDLE
UART_MINT_RX
0
X
X
0
1
1
0
0
asserted after 4 idle frames
asserted after 4 idle frames
1
0
1
asserted after 8 idle frames
asserted after 8 idle frames
1
1
0
asserted after 16 idle frames
asserted after 16 idle frames
1
1
1
asserted after 32 idle frames
asserted after 32 idle frames
Note: This table assumes that no other interrupt is set at the same time this interrupt is set for
the MINT_RX signal. This table shows how this interrupt affects the MINT_RX signal.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-13
Sub-Block Description
During a normal message there is no idle time between frames. When all of the information bits in a frame
are logic 1s, the start bit ensures that at least one logic 0 bit time occurs for each frame so that the IDLE bit
is not asserted.
21.5.5 Receiver Wake
The receiver logic block includes the WAKE bit in the USR2_x register that is set when the receiver
detects the start bit. The WAKE bit is not set until the start bit is qualified. When the wake interrupt enable
(WKEN) bit is enabled, the receiver flags an interrupt (UART_MINT_UARTC) if the WAKE status bit is
set. The WAKE bit is cleared by writing 1 to it. Writing 0 to the WAKE bit has no effect.
When the asynchronous wake interrupt (AWAKE) is enabled (AWAKEN = 1) and the ARM920T
processor is in STOP mode, a falling edge detected on the receive pin asserts the AWAKE bit and the
UART_MINT_UARTC interrupt to wake the ARM920T processor from STOP mode. Clear the AWAKE
bit by writing 1 to it. Writing 0 to the AWAKE bit has no effect.
If the asynchronous IR WAKE interrupt is enabled (AIRINTEN = 1), the UART is configured for IR
mode, the ARM920T processor is in STOP mode, and a falling edge is detected on the receive pin, this
asserts the AIRINT bit and the UART_MINT_UARTC interrupt and wakes the ARM920T processor from
STOP mode. Clear the AIRINT bit by writing 1 to it. Writing 0 to the AIRINT bit has no effect.
The recommended procedure for programming the asynchronous interrupts is to first clear them by writing
1 to the appropriate bit in the UART Status Register 1 (USR1_x). Poll or enable the interrupt for the
Receiver IDLE Interrupt Flag (RXDS) in the appropriate register (USR1_x). When asserted, the RXDS bit
indicates to the software that the receiver state machine is in the idle state, the next state is idle, and the
RXD pin is idle (high). After following this procedure, enable the asynchronous interrupt and enter STOP
mode.
21.5.6 Receiving a BREAK Condition
A BREAK condition is received when the receiver detects all 0s (including a 0 during the bit time of the
stop bit) in a frame. The BREAK condition asserts the BRCD bit in the appropriate register (USR2_x) and
writes only the first BREAK character to the RxFIFO. Clear the BRCD bit by writing 1 to it. Writing 0 to
the BRCD bit has no effect. The BRCD bit remains asserted as long as a BREAK condition exists. The
BREAK condition ends when the receiver detects a 0-to-1 transition.
21.5.7 Vote Logic
The vote logic block provides jitter tolerance and noise immunity by sampling with respect to VOTE_CLK
and using voting techniques to clean up the samples. The voting is implemented by sampling the incoming
signal constantly on the rising edge of VOTE_CLK. The receiver is provided with the majority vote value,
which is 2 out of the 3 samples. Examples of the majority vote results of the vote logic are shown in
Table 21-9.
MC9328MXS Reference Manual, Rev. 1.1
21-14
Freescale Semiconductor
Sub-Block Description
Table 21-9. Majority Vote Results
Samples
Vote
000
0
101
1
001
0
111
1
The vote logic captures a sample on every rising edge of BRM_CLK, however the receiver uses 16x
oversampling to take its value in the middle of the sample frame. The idle character may be longer or
shorter than 16 counts, however the receiver looks for a 1-to-0 transition. The receiver starts to count when
the Start bit is set however it does not capture the contents of the RxFIFO at the time the Start bit is set. The
start bit is validated when 0s are received for 7 consecutive bit times following the 1-to-0 transition. Once
the counter reaches 0xF, it starts counting on the next bit and captures it in the middle of the sampling
frame (see Figure 21-4). All data bits are captured in the same manner. Once the stop bit is detected, the
receiver shift register (SIPO_OUT) data is parallel shifted to the RxFIFO.
There is a special case when the BRM_CLK period is longer than the period of the IR 0 pulse (when the
baud rate is configured for less than 31.25 Kbps). In this case, the software sets the IRSC bit so that the
MC9328MXS reference clock is the clock for the voting logic. The pulse is validated by counting the
length of the pulse. This logic only works with 16 MHz, 25 MHz, and 30 MHz reference clock
frequencies. Enabling this bit with any other reference frequency is undefined. When setting IRSC = 1,
either:
•
Ignore the first character received, clear the status flags after the RDR bit is set, and proceed,
•
OR enables the software reset of the UART module after the initial configuration of UART
including setting of the reference frequency bit (Ref16/Ref25/Ref30), however before setting IRSC
bit to high. Using this method, insures the first character received is correct.
21.5.8 Binary Rate Multiplier (BRM)
The BRM submodule generates all baud rates that required integer and non-integer division. The input and
output frequency ratio is programmed in the UART BRM Incremental Register (UBIR_x) and UART
BRM Modulator Register (UBMR_x). The output frequency is divided by the input frequency to produce
this ratio. For integer division, set the appropriate UBIR_x register to equal 0x000F and write the divisor to
the UBMR_x register. All values written to these registers must be one less than the actual value to
eliminate division by 0 (undefined), and to increase the maximum range of the registers.
Updating the BRM registers requires writing to both registers. The UBIR_x register must be written before
writing to the UBMR_x register. If only one register is written to by the software, the BRM continues to
use the previous values.
The following examples show how to determine what values are to be programmed into UBIR and UBMR
for a given reference frequency and desired baud rate. The following equation can be used to help
determine these values:
[(Desired Baud Rate)*16]/(reference frequency)=NUM/DENOM
Eqn. 21-1
UBIR = NUM - 1
Eqn. 21-2
UBMR = DENOM - 1
Eqn. 21-3
reference frequency = PERCLK1 / RFDIV [2:0]
Eqn. 21-4
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-15
Sub-Block Description
Example:
Integer Division ÷ 2
Reference Frequency = 19.44 MHz
NUM = 0x0000
DENOM = 0x0001
UBIR = NUM - 1
UBMR = DENOM - 1
NOTE:
Notice each value written to the registers is one less than the actual value.
Example:
Non-integer Division
Reference Frequency = 16 MHz
Output Frequency = 920 kbps × 16 (sampling) = 14.72 MHz
Ratio --> 14.72 ÷ 16 = 0.92
NUM = 92 (decimal) = 0x5C
DENOM = 100 (decimal) = 0x64
UBIR = NUM - 1
UBMR = DENOM - 1
NOTE:
The ratio is derived directly from the division with no factoring (easiest).
To derive the exact ratio, some factoring must be performed. Factoring the
above ratio produces:
Factored Ratio: 23 ÷ 25
NUM = 22 (decimal) = 0x0016
DENOM = 25 (decimal) = 0x0019
Example:
Non-integer Division
Reference Frequency = 25 MHz
Output Frequency = 920 kbps × 16 (sampling) = 14.72 MHz
Ratio --> 14.72 ÷ 25 = 0.5888
NUM = 5888 (decimal) = 0x1700
DENOM = 10000 (decimal) = 0x2710
UBIR = NUM - 1
UBMR = DENOM - 1
NOTE:
The ratio is derived directly from the division with no factoring (easiest).
To derive the exact ratio, some factoring must be performed. Factoring the
above ratio produces:
Factored Ratio = 184 ÷ 313
NUM = 183 (decimal) = 0x00B7
DENOM = 313 (decimal) = 0x0139
Example:
Non-integer Division:
Reference Frequency: 30 MHz
Output Frequency: 920 kbps × 16 (sampling) = 14.72 MHz
Ratio --> 14.72 ÷ 30 = 0.4907
NUM = 4907 (decimal) = 0x132B
DENOM = 10000 (decimal) = 0x2710
NOTE:
The ratio is derived directly from the division with no factoring (easiest).
To derive the exact ratio, some factoring must be perform. Factoring the
above ratio produces:
Factored Ratio: 184 ÷ 325
MC9328MXS Reference Manual, Rev. 1.1
21-16
Freescale Semiconductor
Sub-Block Description
NUM = 183 (decimal) = 0x00B7
DENOM = 325 (decimal) = 0x0144
Baud Rate = (CKIH) ÷ (16 × Divisor)
or
Divisor = (CKIH) ÷ (16 × Baud Rate)
Transmitter Clock = 16 × Baud Rate
Receiver Clock = CKIH ÷ Divisor = 16 × Baud Rate
21.5.9 Baud Rate Automatic Detection Logic
When the baud rate automatic detection logic is enabled, the UART locks onto the incoming baud rate. To
enable this feature, set the automatic detection of baud rate bit (ADBR = 1) in the UART Control Register
1 and write 1 to the ADET bit in the UART Status Register 2 to clear it. When ADET=0 and ADBR=1, the
UART automatically sets the INC=0x0 in the appropriate UBIR_x register and MOD =0x0 in the
UBMR_x register. The UART waits for the start bit (transition from 1-to-0) and tries to lock onto the
incoming baud rate. Once the start bit is detected, the length of the start bit is calculated by counting until
the 0-to-1 transition (see Figure 21-4 and Section 21.5.9.1). The new baud rate is determined using this
equation:
Eqn. 21-5
Count
BaudRate = 〈 ----------------〉
16
Table 21-10. Baud Rate Automatic Detection
ADBR
ADET
Baud Rate Detection
UART_MINT_UARTC
0
X
Manual Configuration
1
1
0
Auto Detection
1
1
1
Auto Detection
Complete
0
Note: This table assumes that no other interrupt is set at the
same time this interrupt is set for the UART_MINT_UARTC signal.
1
0
0
0
0
1
1
Idle
0
Stop
Bit
Start
Bit
Transition from 0-to-1
Note:
LSB transmitted first.
Figure 21-4. Baud Rate Detection Protocol Diagram
The BRM Incremental Preset registers (BIPR1_x through BIPR4_x) and BRM Modulator Preset registers
(BMPR1_x through BMPR4_x) are used when detecting the special baud rates (when BPEN = 1). These
registers are written by software before the start of automatic baud sequence detection. After the auto baud
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-17
Sub-Block Description
count value is divided by 16 and a remainder higher than 3 is detected, the appropriate BIPRn_x and
BMPRn_x registers are selected (if the BPEN bit is asserted). This feature is available for 16 MHz,
25 MHz, or 30 MHz reference frequencies only. Enabling this feature with any other reference frequency
is not supported and is undefined. The corresponding reference frequency bits in the control register (they
are in different registers) must also be set (REF16, REF25, or REF30).
When the BPEN bit is not asserted (BPEN = 0), non-integer division is performed for all detections. This
method works with any reference frequency. Based on the reference frequency, the UART computes the
baud rate on the fly.
If any of the UART BRM registers are written to simultaneously by the baud rate automatic detection logic
and peripheral data bus, the peripheral data bus has priority.
21.5.9.1 Baud Rate Automatic Detection Protocol
The receiver must receive an ASCII character “A” or “a” to verify proper detection of the incoming baud
rate. When an ASCII character “A” or “a” is received and no error occurs, the Automatic Detect baud rate
bit is set (ADET=1) and if the interrupt is enabled (ADEN=1),an interrupt UART_MINT_UARTC is
generated.
When an ASCII character “A” or “a” is not received (because of a bit error or the transmission of another
character), the value written into the associated UBIR_x and UBMR_x registers may not be accurate.
When the ADET bit is not asserted after the required time-out value (based on baud rate, word size, parity,
and number of stop bits), look out for the parity/frame error interrupt (UART_MINT_PFERR = 0) if
enabled. After the interrupt is asserted, re-send the character “A” or “a” and repeat the above procedure
until the ADET bit is set.
As long as ADET = 0 and ADBR = 1, the UART continues to try to lock onto the incoming baud rate.
Once the ASCII character “A” or “a” is detected and the ADET bit is set, the receiver ignores the ADBR
bit and continues normal operation with the calculated baud rate divisor.
The UART interrupt is active (UART_MINT_UARTC = 0) as long as ADET = 1 and ADBR = 1. This can
be disabled by clearing the automatic baud rate detection interrupt enable bit (ADEN = 0). Before starting
an automatic baud rate detection sequence, set ADET = 0 and ADBR = 1.
The RxFIFO must contain the ASCII character “A” or “a” following the automatic baud rate detection
interrupt, which can be cleared by reading it. Because this UART has standard reference frequencies of
16 MHz, 25 MHz, or 30 MHz, the highest achievable baud rate is determined by the value of the reference
frequency ÷ 16.
Table 21-11. Highest Baud Rates
Reference Frequency (MHz)
Highest Baud Rate (bps)
16 MHz
1 Mbps
25 MHz
1.5625 Mbps
30 MHz
1.875 Mbps
The 16-bit UART Baud Rate Count Register (UBRC_x) is reset to 8 and stays at 0xFFFF when an
overflow occurs. The appropriate UBRC_x register counts the start bit of the incoming baud rate. When the
start bit is detected and counted, the UART Baud Rate Count Register retains its value until the next
automatic baud rate detection sequence is initiated.
The read only Baud Rate Count Register counts only when auto detection is enabled.
MC9328MXS Reference Manual, Rev. 1.1
21-18
Freescale Semiconductor
Sub-Block Description
21.5.10 Escape Sequence Detection
An escape sequence typically consists of 3 characters entered in rapid succession (such as +++). Because
these are valid characters by themselves, the time between characters determines if it is a valid escape
sequence. Too much time between two of the + characters is interpreted as two + characters, and not part
of an escape sequence.
The software chooses the escape character and writes its value to the associated UART Escape Character
Register (UESC_x). The hardware compares this value to incoming characters in the RxFIFO. When an
escape character is detected, the internal escape timer starts to count. The software specifies a time-out
value for the maximum allowable time between escape characters. The escape timer is programmable in
intervals of 2 msec to a maximum interval of 8.192 seconds.
Table 21-12. Escape Timer Scaling
UTIM_1/
UTIM_2
Register
Maximum Time Between
Specified Escape Characters
0x000
2 msec
0x001
4 msec
0x002
6 msec
0x003
8 msec
0x004
10 msec
…
…
0F8
498 msec
0F9
500 msec
…
…
9C3
5 sec
…
…
FFD
8.188 sec
FFE
8.190 sec
FFF
8.192 sec
Note:
To calculate the time interval:
(UTIM_Value + 1) × 0.002 = Time_Interval
Example: (09C3 + 1) × 0.002 = 5 sec
The escape sequence detection feature is available for 16 MHz, 25 MHz, or 30 MHz reference frequencies
only. Enabling this feature with any other reference frequency is not supported and is undefined.Set the
corresponding reference frequency bits (REF16 in the UCR4_x register, REF25 or REF30 in UCR3_x
register).
The escape sequence detection feature asserts the escape sequence interrupt flag (ESCF) bit when the
escape sequence interrupt enable (ESCI) bit is set and an escape sequence is detected. Clear the ESCF bit
by writing 1 to it. Writing 0 to the ESCF bit has no effect.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-19
Infrared Interface
21.6 Infrared Interface
The IR interface converts data to be transmitted or received as specified in the IRDA Serial Infrared
Physical Layer Specification.
For each 0 to be transmitted, a narrow positive pulse (3/16 of a bit time) is generated. For each 1 to be
transmitted, no pulse is generated (output is low). The data is muxed out onto the TXD pin when the
infrared interface enable bit is set (IREN = 1). External circuitry must be provided to drive an infrared
LED.
When receiving, a narrow negative pulse is expected for each 1 transmitted and no pulse is expected for
each 0 transmitted (input is high). The data from the RXD pin is demuxed to the appropriate IR decoder
logic when the infrared interface enable bit is set (IREN = 1). Circuitry external to the MC9328MXS
transforms the IR signal into an electrical signal.
Serial infrared mode (SIR) uses an edge triggered interrupt flag (the serial infrared interrupt flag, IRINT, in
the associated USR2_x register) that validates 0 bits as they are received. When INVR =0, detection of a
falling edge on the UART_RXD pin assets the IRINT bit. When INVR=1, detection of a rising edge on the
UART_RXD pin assets the IRINT bit. When both the IRINT and ENIRI bits are asserted, the
UART_MINT_UARTC interrupt is asserted. Clear the IRINT bit by writing 1 to it. Writing 0 to the IRINT
bit has no effect.
In many applications, the ability to detect IrDA pulses < 2μs (micro-seconds) has caused data to be
misread or missed all together. The work around to this is to allow enough oversampling of the UART
clock when receiving narrow IR pulses < 2μs by configuring PerCLK1 greater than the selected reference
frequency of 16 MHZ, 25 MHz, or 30 MHz as selected in the UART registers UCR3 and UCR4. The
UART module will think that it is using a certain reference frequency, however, in fact it will be over
driven by a higher frequency PerCLK1. However, caution must be used when employing this method as
this will render features that are dependant on an accurate reference frequencies useless, such as the auto
baud detection and break detection. Also, baud rates will need to be re-calculated based on the PerCLK1
clock frequency. An example suggestion is to simply set PerCLK1 to 32 MHz, while setting the UART
reference frequency to 16 MHz (make sure that the RFDIV bits are set to divide by one in the UFCR
register and REF16 is set in the UCR4 register). This oversampling ensures that IR pulses < 2μs will be
detected. Also, make sure to remember to re-calculate the baud rates based on the value of 32 MHz and not
16 MHz when using this example.
MC9328MXS Reference Manual, Rev. 1.1
21-20
Freescale Semiconductor
Programming Model
21.7 Programming Model
The UART modules include user-accessible 32-bit registers and user-accessible 16-bit registers. All
registers use word, halfword, or byte access. The UART Receiver Registers and the UART Transmitter
Registers are each mapped to 16 word-length addresses to support the load multiple registers (LDM)
instruction and the store multiple registers (STM) instruction, respectively
Table 21-13 summarizes these registers and their addresses.
Table 21-13. UART Module Register Memory Map
Description
Name
Address
UART1 Receiver Register n
URXDn_1
0x00206000+4*n
UART1 Transmitter Register n
UTXnD_1
0x00206040+4*n
UART1 Control Register 1
UCR1_1
0x00206080
UART1 Control Register 2
UCR2_1
0x00206084
UART1 Control Register 3
UCR3_1
0x00206088
UART1 Control Register 4
UCR4_1
0x0020608C
UART1 FIFO Control Register
UFCR_1
0x00206090
UART1 Status Register 1
USR1_1
0x00206094
UART1 Status Register 2
USR2_1
0x00206098
UART1 Escape Character Register
UESC_1
0x0020609C
UART1 Escape Timer Register
UTIM_1
0x002060A0
UART1 BRM Incremental Register
UBIR_1
0x002060A4
UART1 BRM Modulator Register
UBMR_1
0x002060A8
UART1 Baud Rate Count Register
UBRC_1
0x002060AC
UART1 BRM Incremental Preset Register 1
BIPR1_1
0x002060B0
UART1 BRM Incremental Preset Register 2
BIPR2_1
0x002060B4
UART1 BRM Incremental Preset Register 3
BIPR3_1
0x002060B8
UART1 BRM Incremental Preset Register 4
BIPR4_1
0x002060BC
UART1 BRM Modulator Preset Register 1
BMPR1_1
0x002060C0
UART1 BRM Modulator Preset Register 2
BMPR2_1
0x002060C4
UART1 BRM Modulator Preset Register 3
BMPR3_1
0x002060C8
UART1 BRM Modulator Preset Register 4
BMPR4_1
0x002060CC
UART1 Test Register 1
UTS_1
0x002060D0
UART2 Receiver Register n
URXDn_2
0x00207000+4*n
UART2 Transmitter Register n
UTXnD_2
0x00207040+4*n
UART2 Control Register 1
UCR1_2
0x00207080
UART2 Control Register 2
UCR2_2
0x00207084
UART2 Control Register 3
UCR3_2
0x00207088
UART 1
UART 2
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-21
Programming Model
Table 21-13. UART Module Register Memory Map (continued)
Description
Name
Address
UART2 Control Register 4
UCR4_2
0x0020708C
UART2 FIFO Control Register
UFCR_2
0x00207090
UART2 Status Register 1
USR1_2
0x00207094
UART2 Status Register 2
USR2_2
0x00207098
UART2 Escape Character Register
UESC_2
0x0020709C
UART2 Escape Timer Register
UTIM_2
0x002070A0
UART2 BRM Incremental Register
UBIR_2
0x002070A4
UART2 BRM Modulator Register
UBMR_2
0x002070A8
UART2 Baud Rate Count Register
UBRC_2
0x002070AC
UART2 BRM Incremental Preset Register 1
BIPR1_2
0x002070B0
UART2 BRM Incremental Preset Register 2
BIPR2_2
0x002070B4
UART2 BRM Incremental Preset Register 3
BIPR3_2
0x002070B8
UART2 BRM Incremental Preset Register 4
BIPR4_2
0x002070BC
UART2 BRM Modulator Preset Register 1
BMPR1_2
0x002070C0
UART2 BRM Modulator Preset Register 2
BMPR2_2
0x002070C4
UART2 BRM Modulator Preset Register 3
BMPR3_2
0x002070C8
UART2 BRM Modulator Preset Register 4
BMPR4_2
0x002070CC
UART2 Test Register 1
UTS_2
0x002070D0
MC9328MXS Reference Manual, Rev. 1.1
21-22
Freescale Semiconductor
Programming Model
21.7.1 UART Receiver Registers
The read-only UART Receiver Registers contain the received character and its status. After reset, when the
receiver enable bit is set (RXEN = 1), these registers contain random data and the CHARRDY bit is 0 until
the first character is received. The URXDn_x registers are each mapped to 16 word-length addresses to
support the LDM instruction.
URXDn_1
URXDn_2
Addr
0x00206000+4*n
0x00207000+4*n
UART1 Receiver Register n
UART2 Receiver Register n
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
CHAR
RDY
ERR
OVR
RUN
FRM
ERR
BRK
PR
ERR
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
?
?
?
?
?
?
?
?
TYPE
9
8
RX_DATA
RESET
0x0000
Note:
n
= (0 through 15)
Table 21-14. UART 1 2 Receiver Register Descriptions
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
CHARRDY
Bit 15
Character Ready—Indicates an invalid read when the
RxFIFO is empty and the software attempts to read the
previously read data.
0 = The character in the RX_DATA
field and its associated flags
are invalid.
1 = The character in the RX_DATA
field and its associated flags
are valid and ready to read
ERR
Bit 14
Error Detect—Indicates whether the character present in the
RX_DATA field has an error (OVRRUN, FRMERR, BRK or
PRERR) status. The ERR bit is updated and valid for each
received character.
0 = No error status was detected
1 = An error status was detected
OVRRUN
Bit 13
Receiver Overrun—Indicates whether the receiver ignored
data to prevent overwriting the data in the RxFIFO. This error
indicates that the software is not keeping up with the incoming
data rate. OVRRUN is set for the last (32nd) character written
to the RxFIFO to indicate that all characters following this
character will be ignored if a read is not performed by the
software. OVRRUN is updated and valid for each received
character. Under normal circumstances, OVRRUN is never
set.
0 = No RxFIFO overrun was
detected
1 = A RxFIFO overrun was
detected
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-23
Programming Model
Table 21-14. UART 1 2 Receiver Register Descriptions (continued)
Name
Description
Settings
FRMERR
Bit 12
Frame Error—Indicates whether the current character had a
framing error (a missing stop bit) and is possibly corrupted.
FRMERR is updated for each character read from the RxFIFO.
0 = The current character has no
framing error
1 = The current character has a
framing error
BRK
Bit 11
BREAK Detect—Indicates whether the current character was
detected as a BREAK character. The data bits and the stop bit
are all 0. The FRMERR bit is set when BRK is set. When odd
parity is selected, PRERR is also set when BRK is set. BRK is
valid for each character read from the RxFIFO.
0 = The current character is not a
BREAK character
1 = The current character is a
BREAK character
PRERR
Bit 10
Parity Error—Indicates whether the current character was
detected with a parity error and is possibly corrupted. PRERR
is updated for each character read from the RxFIFO. When
parity is disabled, PRERR always reads as 0.
0 = No parity error was detected for
data in the RX_DATA field
1 = A parity error was detected for
data in the RX_DATA field
Reserved
Bits 9–8
Reserved—These bits are reserved and should read 0.
RX_DATA
Bits 7–0
Received Data—Holds the received character. In 7-bit mode, the most significant bit (MSB) is forced
to 0. In 8-bit mode, all bits are active.
MC9328MXS Reference Manual, Rev. 1.1
21-24
Freescale Semiconductor
Programming Model
21.7.2 UART Transmitter Registers
The write-only UART Transmitter Registers are where the ARM920T processor writes the data to be
transmitted. When these registers are read, the TX_DATA bits are always read as 0. The UTXnD_x
registers are each mapped to 16 word-length addresses to support the STM instruction.
UTXnD_1
UTXnD_2
Addr
0x00206040+4*n
0x00207040+4*n
UART1 Transmitter Register n
UART2 Transmitter Register n
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
TX_DATA
TYPE
r
r
r
r
r
r
r
r
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
?
?
?
?
?
?
?
?
RESET
0x0000
Note:
n
= (0 through 15)
Table 21-15. UART 1 2 Transmitter Register Descriptions
Name
Description
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
TX_DATA
Bits 7–0
Transmit Data—Holds the parallel transmit data inputs. In 7-bit mode, D7 is ignored. In 8-bit
mode, all bits are used. Data is transmitted least significant bit (LSB) first. A new character is
transmitted when the TX_DATA field is written. The TX_DATA field must be written only when the
TRDY bit is high to ensure that corrupted data is not sent.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-25
Programming Model
21.7.3 UART Control Register 1
UART Control Register 1 enables the respective UART features and controls the transmit and receive
blocks. This register also controls the TxFIFO and RxFIFO levels and enables the TRDY and RRDY
interrupts.
UCR1_1
UCR1_2
Addr
0x00206080
0x00207080
UART1 Control Register 1
UART2 Control Register 1
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
ADEN ADBR
TYPE
13
12
TRDY
IDEN
EN
11
10
ICD
9
8
7
UART
RRDY RDMA
TXMPTY RTSD SND TDMA UARTCLK
DOZE
IREN
EN
EN
EN
EN
EN
EN BRK EN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
RESET
0x0004
Table 21-16. UART 1 2 Control Register 1 Descriptions
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
ADEN
Bit 15
Automatic Baud Rate Detection Interrupt
Enable—Enables/Disables the automatic baud rate
detect complete (ADET) bit to generate an interrupt
(UART_MINT_UARTC = 0).
0 = Disable the automatic baud
rate detection interrupt
1 = Enable the automatic baud
rate detection interrupt
ADBR
Bit 14
Automatic Detection of Baud Rate—Enables/Disables
automatic baud rate detection. When the ADBR bit is set
and the ADET bit is cleared, the receiver detects the
incoming baud rate automatically. The ADET flag is set
when the receiver verifies that the incoming baud rate is
detected properly by detecting an ASCII character “A” or
“a” (0x61 or 0x41).
0 = Disable automatic detection of
baud rate
1 = Enable automatic detection of
baud rate
TRDYEN
Bit 13
Transmitter Ready Interrupt Enable—Enables/Disables
the transmitter Ready Interrupt (TRDY) when the
transmitter has one or more slots available in the TxFIFO.
The fill level in the TXFIFO at which an interrupt is
generated is controlled by TxTL bits. When TRDYEN is
negated, the transmitter ready interrupt is disabled.
0 = Disable the transmitter ready
interrupt
1 = Enable the transmitter ready
interrupt
IDEN
Bit 12
Idle Condition Detected Interrupt
Enable—Enables/Disables the IDLE bit to generate an
interrupt (UART_MINT_RX = 0).
0 = Disable the IDLE bit
1 = Enable the IDLE bit
MC9328MXS Reference Manual, Rev. 1.1
21-26
Freescale Semiconductor
Programming Model
Table 21-16. UART 1 2 Control Register 1 Descriptions (continued)
Name
Description
Settings
ICD
Bits 11–10
Idle Condition Detect—Controls the number of frames
RXD is allowed to be idle before an idle condition is
reported.
00 = Idle for more than 4 frames
01 = Idle for more than 8 frames
10 = Idle for more than 16 frames
11 = Idle for more than 32 frames
RRDYEN
Bit 9
Receiver Ready Interrupt Enable—Enables/Disables
the RRDY interrupt when the RxFIFO contains data. The
fill level in the RXFIFO at which an interrupt is generated
is controlled by the RXTL bits. When RRDYEN is
negated, the receiver ready interrupt is disabled.
0 = Disables the RRDY interrupt
1 = Enables the RRDY interrupt
RDMAEN
Bit 8
Receive Ready DMA Enable—Enables/Disables the
receive DMA request UART_RX_DMAREQ when the
receiver has data in the RxFIFO. The fill level in the
RxFIFO at which a DMA request is generated is
controlled by the RXFL bits. When negated, the receive
DMA request is disabled.
0 = Disable UART_RX_DMAREQ
DMA request
1 = Enable UART_RX_DMAREQ
DMA request
IREN
Bit 7
Infrared Interface Enable—Enables/Disables the IR
interface. See the IR interface description in Section 21.6
for more information.
0 = Disable the IR interface
1 = Enable the IR interface
TXMPTYEN
Bit 6
Transmitter Empty Interrupt Enable—Enables/Disables
the transmitter FIFO empty (TXFE) interrupt.
UART_MINT_TX. When negated, the TXFE interrupt is
disabled.
0 = Disable the transmitter FIFO
empty interrupt
1 = Enable the transmitter FIFO
empty interrupt
RTSDEN
Bit 5
RTS Delta Interrupt Enable—Enables/Disables the
RTSD interrupt. The current status of the UARTx_RTS
pin is read in the RTSS bit.
0 = Disable RTSD interrupt
1 = Enable RTSD interrupt
SNDBRK
Bit 4
Send BREAK—Forces the transmitter to send a BREAK
character. The transmitter finishes sending the character
in progress (if any) and sends BREAK characters until
SNDBRK is reset. Because the transmitter samples
SNDBRK after every bit is transmitted, it is important that
SNDBRK is asserted high for a sufficient period of time to
generate a valid BREAK. After the BREAK transmission
completes, the UART transmits 2 mark bits. The user can
continue to fill the TxFIFO and any characters remaining
are transmitted when the BREAK is terminated.
0 = Do not send a BREAK
character
1 = Send a BREAK character
(continuous 0s)
TDMAEN
Bit 3
Transmitter Ready DMA Enable—Enables/Disables the
transmit DMA request UART_TX_DMAREQ when the
transmitter has one or more slots available in the TxFIFO.
The fill level in the TxFIFO that generates the
UART_TX_DMAREQ is controlled by the TXTL bits.
0 = Disable transmit DMA request
1 = Enable transmit DMA request
UARTCLKEN
Bit 2
UART Clock Enable—Enables/Disables all of the
internal clocks of the UART module
0 = Disable UART clocks
1 = Enable UART clocks
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-27
Programming Model
Table 21-16. UART 1 2 Control Register 1 Descriptions (continued)
Name
Description
Settings
DOZE
Bit 1
DOZE—Determines the UART enable condition in the
DOZE state. When the ARM9 core executes a DOZE
instruction and the system is placed in the DOZE state,
the DOZE bit affects the operation of the UART. When
the system is in the DOZE state and the DOZE bit is
asserted, the UART is disabled. See Section 21.8, “UART
Operation in Low-Power System States,” on page 21-52
for more information.
0 = The UART is enabled when in
DOZE state
1 = The UART is disabled when in
DOZE state
UARTEN
Bit 0
UART Enable—Enables/Disables the UART. If UARTEN
is negated in the middle of a transmission, the transmitter
stops and pulls the TXD line to a logic 1.
0 = Disable the UART
1 = Enable the UART
MC9328MXS Reference Manual, Rev. 1.1
21-28
Freescale Semiconductor
Programming Model
21.7.4 UART Control Register 2
The UART Control Register 2 controls the overall operation of its respective UART. The bits in these
registers set the BITSEL and its source, specify the number of bits per character, enable or disable parity
generation and checking, and control the RTS and CTS pins.
UCR2_1
UCR2_2
Addr
0x00206084
0x00207084
UART1 Control Register 2
UART2 Control Register 2
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
PREN
PROE
TXEN
RXEN
SRST
RESET
0x0000
BIT
15
14
ESCI
IRTS
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
TYPE
13
12
CTSC CTS
11
ESC
EN
10
9
RTEC
STPB WS
RTS
EN
RESET
0x0001
Table 21-17. UART 1 2 Control Register 2 Descriptions
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
ESCI
Bit 15
Escape Sequence Interrupt Enable—Enables/Disables the
ESCF bit to generate an interrupt.
0 = Disable the escape sequence
interrupt
1 = Enable the escape sequence
interrupt
IRTS
Bit 14
Ignore UARTx_RTS Pin—Forces the UARTx_RTS input signal
presented to the transmitter to always be asserted, effectively
ignoring the external pin. When in this mode, the UARTx_RTS
pin serves as a general purpose input.
0 = Transmit only when the
UARTx_RTS pin is asserted
1 = Ignore the UARTx_RTS pin
CTSC
Bit 13
UARTx_CTS Pin Control—Controls the operation of the
UARTx_CTS output pin. When CTSC is asserted, the
UARTx_CTS output pin is controlled by the receiver. When the
RxFIFO is filled to the level of the programmed trigger level and
the start bit of the overflowing character (TRIGGER LEVEL + 1)
is validated, the UARTx_CTS output pin is negated to indicate to
the far-end transmitter to stop transmitting. When the trigger
level is programmed for less than 32, the receiver continues to
receive data until the RxFIFO is full. When the CTSC bit is
negated, the UARTx_CTS output pin is controlled by the CTS
bit. On reset, because CTSC is cleared to 0, the UARTx_CTS
pin is controlled by the CTS bit, which again is cleared to 0 on
reset. This means that on reset the UARTx_CTS signal is
negated.
0 = The UARTx_CTS pin is
controlled by the CTS bit
1 = The UARTx_CTS pin is
controlled by the receiver
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-29
Programming Model
Table 21-17. UART 1 2 Control Register 2 Descriptions (continued)
Name
Description
Settings
CTS
Bit 12
Clear to Send—Controls the UARTx_CTS pin when the CTSC
bit is negated. CTS has no function when CTSC is asserted.
0 = The UARTx_CTS pin is high
(inactive)
1 = The UARTx_CTS pin is low
(active)
ESCEN
Bit 11
Escape Enable—Enables/Disables the escape sequence
detection logic.
0 = Disable escape sequence
detection
1 = Enable escape sequence
detection
RTEC
Bits 10–9
Request to Send Edge Control—Selects the edge that triggers
the RTS interrupt. This has no effect on the RTS delta interrupt.
RTEC has an effect only when RTSEN = 1 (see Table 21-4).
00 = Trigger interrupt on a rising
edge
01 = Trigger interrupt on a falling
edge
1X = Trigger interrupt on any edge
PREN
Bit 8
Parity Enable—Enables/Disables the parity generator in the
transmitter and parity checker in the receiver. When PREN is
asserted, the parity generator and checker are enabled, and
disabled when PREN is negated.
0 = Disable parity generator and
checker
1 = Enable parity generator and
checker
PROE
Bit 7
Parity Odd/Even—Controls the sense of the parity generator
and checker. When PROE is high, odd parity is generated and
expected. When PROE is low, even parity is generated and
expected. PROE has no function if PREN is low.
0 = Even parity
1 = Odd parity
STPB
Bit 6
Stop—Controls the number of stop bits transmitted after a
character. When STPB is high, 2 stop bits are sent. When STPB
is low, 1 stop bit is sent. STPB has no effect on the receiver,
which expects 1 or more stop bits.
0 = 1 stop bit transmitted
1 = 2 stop bits transmitted
WS
Bit 5
Word Size—Controls the character length. When WS is high,
the transmitter and receiver are in 8-bit mode. When WS is low,
they are in 7-bit mode. The transmitter ignores bit 7 and the
receiver sets bit 7 to 0. WS can be changed in-between
transmission (reception) of characters, however not when a
transmission (reception) is in progress, in which case the length
of the current character being transmitted (received) is
unpredictable.
0 = 7-bit transmit and receive
character length (not
including START, STOP or
PARITY bits)
1 = 8-bit transmit and receive
character length (not
including START, STOP or
PARITY bits)
RTSEN
Bit 4
Request to Send Interrupt Enable—Controls the RTS edge
sensitive interrupt. When RTSEN is asserted and the
programmed edge is detected on the UARTx_RTS pin, the
RTSF bit is asserted (see Table 21-4).
0 = Disable request to send
interrupt
1 = Enable request to send
interrupt
Reserved
Bit 3
Reserved—This bit is reserved and should read 0.
TXEN
Bit 2
Transmitter Enable—Enables/Disables the transmitter. When
TXEN is negated the transmitter is disabled and idle. When the
UARTEN and TXEN bits are set the transmitter is enabled. If
TXEN is negated in the middle of a transmission, the UART
disables the transmitter immediately, and starts marking 1s.
0 = Disable the transmitter
1 = Enable the transmitter
MC9328MXS Reference Manual, Rev. 1.1
21-30
Freescale Semiconductor
Programming Model
Table 21-17. UART 1 2 Control Register 2 Descriptions (continued)
Name
Description
Settings
RXEN
Bit 1
Receiver Enable—Enables/Disables the receiver. When the
receiver is enabled, if the RXD input is already low, the receiver
does not recognize BREAK characters, because it requires a
valid 1-to-0 transition before it can accept any character.
0 = Disable the receiver
1 = Enable the receiver
SRST
Bit 0
Software Reset—Resets the transmitter and receiver state
machines, all FIFOs, and all status registers. Once the software
writes 0 to SRST, the software reset remains active for 4 clock
cycles of CKIH before the hardware deasserts SRST. The
software can only write 0 to SRST. Writing 1 to SRST is ignored.
0 = Reset the transmit and receive
state machines, all FIFOs and
all status registers
1 = No reset
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-31
Programming Model
21.7.5 UART Control Register 3
The UART Control Register 3 controls the features and operation of UART 1.
21.7.5.1 UART1 Control Register 3
UCR3_1
Addr
0x00206088
UART1 Control Register 3
BIT
31
30
29
28
27
26 25 24 23
TYPE
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
RXDS AIRINT AWAK
REF25 REF30 INVT BPEN
EN
EN
EN
PARERREN FRAERREN
TYPE
r
r
r
rw
rw
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 21-18. UART 1 Control Register 3 Descriptions
Name
Description
Settings
Reserved
Bits 31–13
Reserved—These bits are reserved and should read 0.
PARERREN
Bit 12
Parity Error Interrupt Enable—Enables/Disables
the interrupt. When asserted, PARERREN causes
the PARITYERR bit to generate an interrupt
(UART_MINT_PFERR = 0)
0 = Disable the parity error interrupt
1 = Enable the parity error interrupt
FRAERREN
Bit 11
Frame Error Interrupt Enable—Enables/Disables
the interrupt. When asserted, FRAERREN causes
the FRAMERR bit to generate an interrupt
(UART_MINT_PFERR = 0)
0 = Disable the frame error interrupt
1 = Enable the frame error interrupt
Reserved
Bits 10–7
Reserved—These bits are reserved and should read 0.For proper operation, ensure these bits
always read 0.
RXDSEN
Bit 6
Receive Status Interrupt Enable—Controls the
receive status interrupt (UART_MINT_RX). When
this bit is enabled and RXDS status bit is set, the
interrupt UART_MINT_RX will be generated.
0 = Disable the RXDS interrupt
1 = Enable the RXDS interrupt
AIRINTEN
Bit 5
Asynchronous IR WAKE Interrupt
Enable—Controls the asynchronous IR WAKE
interrupt. An interrupt is generated when AIRINTEN
is asserted and a pulse is detected on the UART_RX
pin.
0 = Disable the AIRINT interrupt
1 = Enable the AIRINT interrupt
MC9328MXS Reference Manual, Rev. 1.1
21-32
Freescale Semiconductor
Programming Model
Table 21-18. UART 1 Control Register 3 Descriptions
Name
Description
Settings
AWAKEN
Bit 4
Asynchronous WAKE Interrupt Enable—Controls
the asynchronous WAKE interrupt. An interrupt is
generated when AWAKEN is asserted and a falling
edge is detected on the RXD pin.
0 = Disable the AWAKE interrupt
1 = Enable the AWAKE interrupt
REF25
Bit 3
Reference Frequency 25 MHz—Indicates to the
hardware that a reference clock frequency of 25 MHz
is used. The reference clock is derived from the input
clock IPG_CLK via the programmable divider.
0 = 25 MHz reference clock not used
1 = 25 MHz reference clock used
REF30
Bit 2
Reference Frequency 30 MHz—Indicates to the
hardware that a reference clock frequency of 30 MHz
is used. The reference clock is derived from the input
clock IPG_CLK via the programmable divider.
0 = 30 MHz reference clock not used
1 = 30 MHz reference clock used
INVT
Bit 1
Inverted Infrared Transmission—Sets the active
level for the transmission. When INVT is cleared, the
infrared logic block transmits a positive IR 3/16 pulse
for all 0s and 0s are transmitted for 1s. When INVT is
set (INVT = 1), the infrared logic block transmits an
active low or negative infrared 3/16 pulse for all 0s
and 1s are transmitted for 1s.
0 = Active low transmission
1 = Active high transmission
BPEN
Bit 0
Preset Registers Enable—Activates the BRM
preset registers for use during automatic baud rate
detection mode. When BPEN is deasserted, the
remainder from the automatic baud count register
divided by 16 is ignored. When BPEN is asserted,
the remainder and the dividend chooses the
appropriate preset register on the detection of special
baud rates. If the criteria is not met for selecting one
of the preset registers, integer division is performed
by writing one less than the dividend to the
UBMR_1/UBMR_2 register.
0 = The BRM preset registers are not used
(normal operation)
1 = The BRM preset registers are used
(auto detect special baud rates)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-33
Programming Model
21.7.5.2 UART2 Control Register 3
UCR3_2
Addr
0x00207088
UART2 Control Register 3
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
12
11
10
9
8
7
AIR
RXDS
AWAK
INT
REF25 REF30 INVT BPEN
EN
EN
EN
DTR PARERR FRAERR
DSR DCD RI
EN
EN
EN
DPEC
TYPE
13
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 21-19. UART 2 Control Register 3 Descriptions
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
DPEC
Bits 15–14
DTR Interrupt Edge Control—Controls the edge
that generates an interrupt. An interrupt is generated
only if the DTREN bit is set.
00 = Interrupt generated on rising edge
01 = Interrupt generated on falling edge
1X = Interrupt generated on either edge
DTREN
Bit 13
Data Terminal Ready Interrupt Enable—Controls
the DTR edge sensitive interrupt. When DTREN is
asserted and the programmed edge is detected on
the UART2_DTR pin, the DTRF bit is asserted (see
Table 21-4).
0 = Disable the data terminal ready
interrupt
1 = Enable the data terminal ready interrupt
PARERREN
Bit 12
Parity Error Interrupt Enable—Enables/Disables
the interrupt. When asserted, PARERREN causes
the PARITYERR bit to generate an interrupt
(UART_MINT_PFERR = 0)
0 = Disable the parity error interrupt
1 = Enable the parity error interrupt
FRAERREN
Bit 11
Frame Error Interrupt Enable—Enables/Disables
the interrupt. When asserted, FRAERREN causes
the FRAMERR bit to generate an interrupt
(UART_MINT_PFERR = 0)
0 = Disable the frame error interrupt
1 = Enable the frame error interrupt
DSR
Bit 10
Data Set Ready—Selects the logic level for the
UART_DSR pin for the modem interface.
0 = The UART_DSR pin is logic 0
1 = The UART_DSR pin is logic 1
DCD
Bit 9
Data Carrier Detect—Selects the logic level for the
UART_DCD pin for the modem interface.
0 = The UART_DCD pin is logic 0
1 = The UART_DCD pin is logic 1
RI
Bit 8
Ring Indicator—Selects the logic level for the
UART_RI pin for the modem interface.
0 = The UART_RI pin is logic 0
1 = The UART_RI pin is logic 1
MC9328MXS Reference Manual, Rev. 1.1
21-34
Freescale Semiconductor
Programming Model
Table 21-19. UART 2 Control Register 3 Descriptions (continued)
Name
Description
Settings
Reserved
Bit 7
This bit is reserved and should read zero. For proper operation, ensure this bit always reads 0.
RXDSEN
Bit 6
Receive Status Interrupt Enable—Controls the
receive status interrupt (UART_MINT_RX). When
this bit is enabled and RXDS status bit is set, the
interrupt UART_MINT_RX will be generated.
0 = Disable the RXDS interrupt
1 = Enable the RXDS interrupt
AIRINTEN
Bit 5
Asynchronous IR WAKE Interrupt
Enable—Controls the asynchronous IR WAKE
interrupt. An interrupt is generated when AIRINTEN
is asserted and a pulse is detected on the UART_RX
pin.
0 = Disable the AIRINT interrupt
1 = Enable the AIRINT interrupt
AWAKEN
Bit 4
Asynchronous WAKE Interrupt Enable—Controls
the asynchronous WAKE interrupt. An interrupt is
generated when AWAKEN is asserted and a falling
edge is detected on the RXD pin.
0 = Disable the AWAKE interrupt
1 = Enable the AWAKE interrupt
REF25
Bit 3
Reference Frequency 25 MHz—Indicates to the
hardware that a reference clock frequency of 25 MHz
is used. The reference clock is derived from the input
clock IPG_CLK via the programmable divider.
0 = 25 MHz reference clock not used
1 = 25 MHz reference clock used
REF30
Bit 2
Reference Frequency 30 MHz—Indicates to the
hardware that a reference clock frequency of 30 MHz
is used. The reference clock is derived from the input
clock IPG_CLK via the programmable divider.
0 = 30 MHz reference clock not used
1 = 30 MHz reference clock used
INVT
Bit 1
Inverted Infrared Transmission—Sets the active
level for the transmission. When INVT is cleared, the
infrared logic block transmits a positive IR 3/16 pulse
for all 0s and 0s are transmitted for 1s. When INVT is
set (INVT = 1), the infrared logic block transmits an
active low or negative infrared 3/16 pulse for all 0s
and 1s are transmitted for 1s.
0 = Active low transmission
1 = Active high transmission
BPEN
Bit 0
Preset Registers Enable—Activates the BRM
preset registers for use during automatic baud rate
detection mode. When BPEN is deasserted, the
remainder from the automatic baud count register
divided by 16 is ignored. When BPEN is asserted,
the remainder and the dividend chooses the
appropriate preset register on the detection of special
baud rates. If the criteria is not met for selecting one
of the preset registers, integer division is performed
by writing one less than the dividend to the
UMBR_2/UMBR_3 register.
0 = The BRM preset registers are not used
(normal operation)
1 = The BRM preset registers are used
(auto detect special baud rates)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-35
Programming Model
21.7.6 UART Control Register 4
The UART Control Register 4 provides configuration control for the UARTs and is used to enable/disable
several UART interrupts.
UCR4_1
UCR4_2
Addr
0x0020608C
0x0020708C
UART1 Control Register 4
UART2 Control Register 4
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
3
2
1
0
TCEN
BKEN
OREN
DREN
RESET
0x0000
BIT
15
14
13
12
11
10
CTSTL
TYPE
9
8
7
6
5
INVR
ENIRI
WKEN
REF16
IRSC
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
rw
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
RESET
0x8040
Table 21-20. UART 1 2 Control Register 4 Descriptions
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
CTSTL
Bits 15–10
CTS Trigger Level—Controls the threshold at which the CTS
pin is deasserted by the RxFIFO. After the trigger level is
reached and the CTS pin is deasserted, the RxFIFO
continues to receive data until it is full. The CTSTL bits are
encoded as shown in the Settings column.
000000 = 0 characters received
000001 = 1 characters in the RxFIFO
...
100000 = 32 characters in the
RxFIFO (maximum)
All Other Settings Reserved
INVR
Bit 9
Inverted Infrared Reception—Determines the logic level for
the detection. When cleared, the infrared logic block expects
an active low or negative IR 3/16 pulse for 0s and 1s are
expected for 1s. When INVR is set (INVR = 1), the infrared
logic block expects an active high or positive IR 3/16 pulse
for 0s and 0s are expected for 1s.
0 = Active low detection
1 = Active high detection
ENIRI
Bit 8
Serial Infrared Interrupt Enable—Enables/Disables the
serial infrared interrupt.
0 = Serial infrared Interrupt disabled
1 = Serial infrared Interrupt enabled
WKEN
Bit 7
WAKE Interrupt Enable—Enables/Disables the WAKE bit to
generate an interrupt. The WAKE bit is set at the detection of
a start bit by the receiver.
0 = Disable the WAKE interrupt
1 = Enable the WAKE interrupt
REF16
Bit 6
Reference Frequency 16 MHz—Indicates to the hardware
that a reference clock of 16 MHz is used. The reference clock
is derived from input clock IPG_CLK via the programmable
divider.
0 = 16 MHz reference clock not used
1 = 16 MHz reference clock is used
MC9328MXS Reference Manual, Rev. 1.1
21-36
Freescale Semiconductor
Programming Model
Table 21-20. UART 1 2 Control Register 4 Descriptions (continued)
Name
Description
Settings
IRSC
Bit 5
IR Special Case—Selects the clock for the vote logic. When
set, IRSC switches the vote logic clock from the sampling
clock to the UART reference clock. The IR pulses are
counted a predetermined amount of time depending on the
reference frequency.
0 = The vote logic uses the sampling
clock (16x baud rate) for normal
operation
1 = The vote logic uses the UART
reference clock
Reserved
Bit 4
Reserved—This bit is reserved and should read 0.
TCEN
Bit 3
Transmit Complete Interrupt Enable—Enables/Disables
the TXDC bit to generate an interrupt (UART_MINT_TX = 0).
0 = Disable TXDC interrupt
1 = Enable TXDC interrupt
BKEN
Bit 2
BREAK Condition Detected Interrupt
Enable—Enables/Disables the BRCD bit to generate an
interrupt (UART_MINT_UARTC = 0).
0 = Disable the BRCD interrupt
1 = Enable the BRCD interrupt
OREN
Bit 1
Receiver Overrun Interrupt Enable—Enables/Disables the
ORE bit to generate an interrupt (UART_MINT_UARTC = 0).
0 = Disable ORE interrupt
1 = Enable ORE interrupt
DREN
Bit 0
Receive Data Ready Interrupt Enable—Enables/Disables
the RDR bit to generate an interrupt (MINT_RX = 0).
0 = Disable RDR interrupt
1 = Enable RDR interrupt
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-37
Programming Model
21.7.7 UART FIFO Control Registers
The UART FIFO Control Registers control the operation of the UART FIFO trigger levels and interrupts.
UFCR_1
UFCR_2
Addr
0x00206090
0x00207090
UART1 FIFO Control Register
UART2 FIFO Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
TXTL
TYPE
8
RFDIV
RXTL
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
RESET
0x0881
Table 21-21. UART 1 2 FIFO Control Register Descriptions
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
TXTL
Bits 15–10
Transmitter Trigger Level—Controls the
threshold at which a maskable interrupt is
generated by the TxFIFO. A maskable interrupt
is generated whenever the data level in the
TxFIFO falls below the selected threshold. The
bits are encoded as shown in the Settings
column. You must ensure the corresponding
Interrupt Service Routine (ISR) or DMA
configuration are correct in that every FIFO
update does not exceed the maximum 32 bytes
or size of 32 for TXTL. Exceeding limit can lead
to incorrect data or an invalid parity bit. For
details refer to Section 21.5.2, “Transmitter FIFO
Empty Interrupt Suppression.”
000000 = Reserved
000001 = Reserved
000010 = TxFIFO has 2 or fewer characters
...
011111 = TxFIFO has 31 or fewer characters
100000 = TxFIFO has 32 characters (maximum)
All Other Settings Reserved
RFDIV
Bits 9–7
Reference Frequency Divider—Controls the
divide ratio for the reference clock. The input
clock is IPG_CLK. The output from the divider
must be synchronous with the bus clock
IPB_CLK.
000 = Divide input clock by 6
001 = Divide input clock by 5
010 = Divide input clock by 4
011 = Divide input clock by 3
100 = Divide input clock by 2
101 = Divide input clock by 1
110 = Divide input clock by 7
MC9328MXS Reference Manual, Rev. 1.1
21-38
Freescale Semiconductor
Programming Model
Table 21-21. UART 1 2 FIFO Control Register Descriptions (continued)
Name
Description
Reserved
Bit 6
Reserved—This bit is reserved and should read 0.
RXTL
Bits 5–0
Receiver Trigger Level—Controls the threshold
at which a maskable interrupt is generated by
the RxFIFO. A maskable interrupt is generated
whenever the data level in the RxFIFO reaches
the selected threshold. The RXTL bits are
encoded as shown in the Settings column.
Settings
000000 = 0 characters received
000001 = RxFIFO has 1 character
...
011111 = RxFIFO has 31 characters
100000 = RxFIFO has 32 characters (maximum)
All Other Settings Reserved
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-39
Programming Model
21.7.8 UART Status Register 1
The UART Status Register 1 reports errors and status flags for both UARTs.
USR1_1
USR1_2
Addr
0x00206094
0x00207094
UART1 Status Register 1
UART2 Status Register 1
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
PARITY
FRAM
RTSS TRDY RTSD ESCF
RRDY
ERR
ERR
TYPE
RXDS
AIR
AWAKE
INT
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x2000
Table 21-22. UART 1 2 Status Register Descriptions
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
PARITYERR
Bit 15
Parity Error Interrupt Flag—Indicates a parity error is detected.
PARITYERR is cleared by writing 1 to it. Writing 0 to
PARITYERR has no effect. When parity is disabled, PARITYERR
always reads 0. At reset, PARITYERR is set to 0
0 = No parity error detected
1 = Parity error detected
RTSS
Bit 14
RTS Pin Status—Indicates the current status of the
UARTx_RTS pin. A “snapshot” of the pin is taken immediately
before RTSS is presented to the data bus. RTSS cannot be
cleared because all writes to RTSS are ignored. At reset, RTSS
is set to 0.
0 = The UARTx_RTS pin is
high (inactive)
1 = The UARTx_RTS pin is low
(active)
TRDY
Bit 13
Transmitter Ready Interrupt / DMA Flag—Indicates that the
TxFIFO emptied below its target threshold and requires data.
TRDY is automatically cleared when the data level in the TxFIFO
goes beyond above the set threshold level by TXFL bits.
At reset, TRDY is set to 1.
0 = The transmitter does not
require data
1 = The transmitter requires
data (interrupt posted)
RTSD
Bit 12
RTS Delta—Indicates whether the RTS pin changed state. It
(RTSD) generates a maskable interrupt. When in STOP mode,
only RTS assertion sets RTSD and wakes the ARM9 core. The
current state of the UARTx_RTS pin is available on the RTSS bit.
Clear RTSD by writing 1 to it. Writing 0 to RTSD has no effect. At
reset, RTSD is set to 0.
0 = UARTx_RTS pin did not
change state since last
cleared
1 = UARTx_RTS pin changed
state (write 1 to clear)
MC9328MXS Reference Manual, Rev. 1.1
21-40
Freescale Semiconductor
Programming Model
Table 21-22. UART 1 2 Status Register Descriptions (continued)
Name
Description
Settings
ESCF
Bit 11
Escape Sequence Interrupt Flag—Indicates if an escape
sequence was detected. ESCF is asserted when the ESCEN bit
is set and an escape sequence is detected in the RxFIFO. Clear
ESCF by writing 1 to it. Writing 0 to ESCF has no effect.
0 = No escape sequence
detected
1 = Escape sequence detected
(write 1 to clear)
FRAMERR
Bit 10
Frame Error Interrupt Flag—Indicates that a frame error is
detected. The UART_PFERR interrupt generated by this. Clear
FRAMERR by writing 1 to it. Writing 0 to FRAMERR has no
effect.
0 = No frame error detected
1 = Frame error detected
RRDY
Bit 9
Receiver Ready Interrupt / DMA Flag—Indicates that the
RxFIFO data level is above the threshold set by the RXFL bits.
(See the RXFL bits description for setting the interrupt threshold.)
When asserted, RRDY generates a maskable interrupt or DMA
request. In conjunction with the CHARRDY bit in the URXDn_1 or
URXDn_2 register, the software can continue to read the RxFIFO
in an interrupt service routine until the RxFIFO is empty. RRDY is
automatically cleared when data level in the RxFIFO goes below
the set threshold level. At reset, RRDY is set to 0.
0 = No character ready
1 = Character(s) ready
(interrupt posted)
Reserved
Bits 8-7
Reserved—This bit is reserved and should read 0.
RXDS
Bit 6
Receiver IDLE Interrupt Flag—Indicates that the receiver state
machine is in an IDLE state, the next state is IDLE, and the
receive pin is high. RXDS is automatically cleared when a
character is received. RXDS is active only when the receiver is
enabled.
0 = Receive in progress
1 = Receiver is IDLE
AIRINT
Bit 5
Asynchronous IR WAKE Interrupt Flag—Indicates that the IR
WAKE pulse was detected (on the RXD pin). Clear AIRINT by
writing 1 to it. Writing 0 to AIRINT has no effect.
0 = No pulse was detected on
the RXD pin
1 = A pulse was detected on
the RXD pin
AWAKE
Bit 4
Asynchronous WAKE Interrupt Flag—Indicates that a falling
edge was detected on the RXD pin. Clear AWAKE by writing 1 to
it. Writing 0 to AWAKE has no effect.
0 = No falling edge was
detected on the RXD pin
1 = A falling edge was detected
on the RXD pin
Reserved
Bits 3–0
Reserved—These bits are reserved and should read 0.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-41
Programming Model
21.7.9 UART Status Register 2
The read-only UART Status Register 2 is used to store data about errors and status flags. There is a status
register for each UART.
USR2_1
USR2_2
Addr
0x00206098
0x00207098
UART1 Status Register 2
UART2 Status Register 2
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
IRINT
WAKE
RESET
0x0000
BIT
15
14
13
12
ADET
TXFE
DTRF
IDLE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
TYPE
11
10
9
RTSF TXDC BRCD ORE RDR
RESET
0x4008
Table 21-23. UART 1 2 Status Register 2 Descriptions
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
ADET
Bit 15
Automatic Baud Rate Detect Complete—Indicates that an “A”
or “a” was received and that the receiver detected and verified the
incoming baud rate. Clear ADET by writing 1 to it. Writing 0 to
ADET has no effect.
0 = ASCII “A” or “a” was not
received
1 = ASCII “A” or “a” was received
(write 1 to clear)
TXFE
Bit 14
Transmit Buffer FIFO Empty—Indicates that the transmit buffer
(TxFIFO) is empty. TXFE is cleared automatically when data is
written to the TxFIFO. Even though TXFE is high, the
transmission might still be in progress.
0 = The transmit buffer (TxFIFO)
is not empty
1 = The transmit buffer (TxFIFO)
is empty
DTRF
(USR2_2
ONLY)
Bit 13
DTR Edge Triggered Interrupt Flag—Indicates if a programmed
edge was detected on the UART2_DTR pin. The DPEC bits
select the edge that generates an interrupt (see Table 21-4). The
DTRF assertion will cause an interrupt if the DTREN bit in the
UCR3 is set. The DTRF interrupt (UART_MINT_DTR) is cleared
by writing 1 to it. Writing 0 to DTRF has no effect.
0 = Programmed edge not
detected on UART2_DTR
1 = Programmed edge detected
on UART2_DTR (write 1 to
clear)
IDLE
Bit 12
Idle Condition—Indicates that an idle condition has existed for
more than a programmed amount frame (see Section 21.5.4.1).
The UART_MINT_RX interrupt generated by this IDLE bit is
cleared by writing 1 to IDLE. Writing 0 to IDLE has no effect.
0 = No idle condition detected
1 = Idle condition detected (write
1 to clear)
Reserved
Bits 11–9
Reserved—These bits are reserved and should read 0.
MC9328MXS Reference Manual, Rev. 1.1
21-42
Freescale Semiconductor
Programming Model
Table 21-23. UART 1 2 Status Register 2 Descriptions (continued)
Name
Description
Settings
Serial Infrared Interrupt Flag—Indicates if a valid edge was
detected on the RX pin during SIR mode. When ENIRI is asserted
and IRINT is asserted, this asserts the common interrupt,
UART_MINT_UARTC. Clear IRINT by writing 1 to it. Writing 0 to
IRINT has no effect.
0 = no edge detected
1 = valid edge detected (write 1
to clear)
WAKE
Bit 7
Wake—Indicates the start bit is detected. WAKE can generate an
interrupt on UART_MINT_UARTC that can be masked using the
WKEN bit. Clear WAKE by writing 1 to it. Writing 0 to WAKE has
no effect.
0 = start bit not detected
1 = start bit detected (write 1 to
clear)
Reserved
Bits 6–5
Reserved—These bits are reserved and should read 0.
RTSF
Bit 4
RTS Edge Triggered Interrupt Flag—Indicates if a programmed
edge is detected on the RTS pin. The RTEC bits select the edge
that generates an interrupt (see Table 21-4). RTSF can generate
an interrupt on UART_MINT_RTS that can be masked using the
RTSEN bit. Clear RTSF by writing 1 to it. Writing 0 to RTSF has
no effect.
0 = Programmed edge not
detected on RTS
1 = Programmed edge detected
on RTS (write 1 to clear)
TXDC
Bit 3
Transmitter Complete—Indicates that the transmit buffer
(TxFIFO) and Shift Register is empty; therefore the transmission
is complete. TXDC is cleared automatically when data is written to
the TxFIFO.
0 = Transmit is incomplete
1 = Transmit is complete
BRCD
Bit 2
BREAK Condition Detected—Indicates that a BREAK condition
was detected by the receiver. Clear BRCD by writing 1 to it.
Writing 0 to BRCD has no effect.
0 = No BREAK condition was
detected
1 = A BREAK condition was
detected (write 1 to clear)
ORE
Bit 1
Overrun Error—Indicates that the receive buffer (RxFIFO) was
full when data was being received. Clear ORE by writing 1 to it.
Writing 0 to ORE has no effect.
0 = No overrun error
1 = Overrun error (write 1 to
clear)
RDR
Bit 0
Receive Data Ready—Indicates that at least 1 character is
received and written to the RxFIFO. If the URXDn_1 or URXDn_2
register is read and there is only 1 character in the RxFIFO, RDR
is automatically cleared.
0 = No receive data ready
1 = Receive data ready
IRINT
Bit 8
When INVR = 1, valid edge is
0-to-1 transition edge
When INVR = 0, valid edge is
1-to-0 transition edge
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-43
Programming Model
21.7.10 UART Escape Character Registers
The UART Escape Character Registers establish the software-selected escape character.
UESC_1
UESC_2
Addr
0x0020609C
0x0020709C
UART1 Escape Character Register
UART2 Escape Character Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
ESC_CHAR
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
RESET
0x002B
Table 21-24. UART 1 2 Escape Character Register Descriptions
Name
Description
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
ESC_CHAR
Bits 7–0
UART Escape Character—Holds the selected escape character that all received characters
are compared against to detect an escape sequence.
MC9328MXS Reference Manual, Rev. 1.1
21-44
Freescale Semiconductor
Programming Model
21.7.11 UART Escape Timer Registers
The UART Escape Timer Registers establish the software-selected maximum interval between escape
characters. These registers are scalable in intervals of 2 msec to a maximum of 8.192 sec.
UTIM_1
UTIM_2
Addr
0x002060A0
0x002070A0
UART1 Escape Timer Register
UART2 Escape Timer Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
TIM
TYPE
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 21-25. UART 1 2 Escape Timer Register Descriptions
Name
Description
Reserved
Bits 31–12
Reserved—These bits are reserved and should read 0.
TIM
Bits 11–0
UART Escape Timer—Holds the maximum interval allowed between escape characters.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-45
Programming Model
21.7.12 UART BRM Incremental Registers
The BRM (Binary Rate Multiplier) Incremental registers hold the numerator value (minus one) of the
BRM ratio. These registers can be written to at any time. Hardware updates the value in the UART BRM
Modulator Registers (UBMR_x) at the appropriate time to avoid glitches on the BRM_CLK output
(sampling clock). The BRM is not updated until both the modulator of the respective UBMR_x register
and its incremental UBIR_x registers are written to by software. If only one register of the two registers is
written to by the software, the BRM ignores this data until the other register is also written.
UBIR_1
UBIR_2
Addr
0x002060A4
0x002070A4
UART1 BRM Incremental Register
UART2 BRM Incremental Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
INC
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 21-26. UART 1 2 BRM Incremental Register Descriptions
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
INC
Bits 15–0
Incremental Numerator—Holds the numerator value minus one of the BRM ratio (see Section
21.5.8). Updating this field using byte accesses is not recommended and is undefined. This register
cannot be written to by the user if ADBR=1.
MC9328MXS Reference Manual, Rev. 1.1
21-46
Freescale Semiconductor
Programming Model
21.7.13 UART BRM Modulator Registers
The UART BRM (Binary Rate Multiplier) Modulator Registers hold the denominator value (minus one) of
the BRM ratio. These registers can be written to at any time. Hardware updates the value in the UART
BRM Modulator Registers (UBMR_x) at the appropriate time to avoid glitches on the BRM_CLK output
(sampling clock). The BRM is not updated until both the modulator of the respective UBMR_x register
and its incremental UBIR_x registers are written to by software. If only one register of the two registers is
written to by the software, the BRM ignores this data until the other register is also written.
UBMR_1
UBMR_2
Addr
0x002060A8
0x002070A8
UART1 BRM Modulator Register
UART2 BRM Modulator Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
MOD
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 21-27. UART 1 2 BRM Modulator Register Descriptions
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
MOD
Bits 15–0
Modulator Denominator—Holds the value of the denominator minus one of the BRM ratio (see
Section 21.5.8). Updating this register using byte accesses is not recommended and undefined.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-47
Programming Model
21.7.14 UART Baud Rate Count Registers
The read-only UART Baud Rate Count Registers count the start bit of the incoming baud rate. When the
start bit is detected and counted, these registers retain their value until the next automatic baud rate
detection sequence is initiated. The registers are reset to 0x00000008, however they stay at 0x0000FFFF in
the case of an overflow.
UBRC_1
UBRC_2
Addr
0x002060AC
0x002070AC
UART1 Baud Rate Count Register
UART2 Baud Rate Count Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
BCNT
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
RESET
0x0008
Table 21-28. UART 1 2 Baud Rate Count Register Descriptions
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
BCNT
Bits 15–0
Baud Rate Count Register—Counts or measures the length of the incoming baud rate start bit
when in automatic baud rate detection mode. This register is clocked by the BRM_CLK.
MC9328MXS Reference Manual, Rev. 1.1
21-48
Freescale Semiconductor
Programming Model
21.7.15 UART BRM Incremental Preset Registers 1–4
The eight 32-bit UART BRM Incremental Preset Registers (BIPRn_x) are used in conjunction with the
automatic baud detection logic. These registers are assigned preset values for the special baud rates
920 Kbps, 460 Kbps, 230 Kbps, and 115.2 Kbps. When the BPEN bit is asserted, these registers are used
on the detection of a remainder. These registers must be written to prior to enabling the auto baud detection
logic. This feature supports 16 MHz, 25 MHz, and 30 MHz reference frequencies only. Enabling this
feature with other reference frequencies is not supported.
BIPR1_1
BIPR1_2
BIPR2_1
BIPR2_2
BIPR3_1
BIPR3_2
BIPR4_1
BIPR4_2
Addr
0x002060B0
0x002070B0
0x002060B4
0x002070B4
0x002060B8
0x002070B8
0x002060BC
0x002070BC
UART1 BRM Incremental Preset Register 1
UART2 BRM Incremental Preset Register 1
UART1 BRM Incremental Preset Register 2
UART2 BRM Incremental Preset Register 2
UART1 BRM Incremental Preset Register 3
UART2 BRM Incremental Preset Register 3
UART1 BRM Incremental Preset Register 4
UART2 BRM Incremental Preset Register 4
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
INCPI
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
RESET
0x????
B
Table 21-29. UART 1 2 Incremental Preset Registers 1–4 Descriptions
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
INCPI
Bits 15–0
BRM Incremental Preset Register—Holds the appropriate numerator for the special baud rates
when in automatic detect mode.
BIPR1_x register is for the 920 Kbps
BIPR2_x register is for the 460 Kbps
BIPR3_x register is for the 230 Kbps
BIPR4_x register is for the 115.2 Kbps
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-49
Programming Model
21.7.16 UART BRM Modulator Preset Registers 1–4
BMPR1_1
BMPR1_2
BMPR2_1
BMPR2_2
BMPR3_1
BMPR3_2
BMPR4_1
BMPR4_2
Addr
0x002060C0
0x002070C0
0x002060C4
0x002070C4
0x002060C8
0x002070C8
0x002060CC
0x002070CC
UART1 BRM Modulator Preset Register 1
UART2 BRM Modulator Preset Register 1
UART1 BRM Modulator Preset Register 2
UART2 BRM Modulator Preset Register 2
UART1 BRM Modulator Preset Register 3
UART2 BRM Modulator Preset Register 3
UART1 BRM Modulator Preset Register 4
UART2 BRM Modulator Preset Register 4
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
MODI
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
RESET
0x????
Table 21-30. UART 1 2 Modulator Preset Registers 1–4 Descriptions
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
MODI
Bits 15–0
BRM MOD Preset Registers—Holds the appropriate numerator for the special baud rates when in
automatic detect mode.
BMPR1_x register is for 920 Kbps
BMPR2_x register is for 460 Kbps
BMPR3_x register is for 230 Kbps
BMPR4_x register is for 115.2 Kbps
MC9328MXS Reference Manual, Rev. 1.1
21-50
Freescale Semiconductor
Programming Model
21.7.17 UART Test Register 1
The UART Test Register 1 controls the various test features of the UART module.
UTS_1
UTS_2
Addr
0x002060D0
0x002070D0
UART1 Test Register 1
UART2 Test Register 1
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
TX
EMPTY
RX
EMPTY
TX
FULL
RX
FULL
RESET
0x0000
BIT
TYPE
15
14
13
12
FRCP
ERR
LOOP
11
10
9
8
7
SOFT
RST
r
r
rw
rw
r
rw
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
RESET
0x0060
Table 21-31. UART 1 2 Test Register Descriptions
Name
Description
Settings
Reserved
Bits 31–14
Reserved—These bits are reserved and should read 0.
FRCPERR
Bit 13
Force Parity Error—Forces the transmitter to generate a parity
error if parity is enabled. FRCPERR is provided for system
debugging.
0 = Generate normal parity
1 = Generate inverted parity
(error)
LOOP
Bit 12
Loop TX and RX for Test—Controls loopback for test purposes.
When LOOP is high, the receiver input is internally connected to the
transmitter and ignores the RXD pin. The transmitter is unaffected
by LOOP.
0 = Normal receiver operation
1 = Internally connect the
transmitter output to the
receiver input
Reserved
Bits 11–7
Reserved—These bits are reserved and should read 0.
TXEMPTY
Bit 6
TxFIFO Empty—Indicates that the TxFIFO is empty.
0 = The TxFIFO is not empty
1 = The TxFIFO is empty
RXEMPTY
Bit 5
RxFIFO Empty—Indicates the RxFIFO is empty.
0 = The RxFIFO is not empty
1 = The RxFIFO is empty
TXFULL
Bit 4
TxFIFO FULL—Indicates the TxFIFO is full.
0 = The TxFIFO is not full
1 = The TxFIFO is full
RXFULL
Bit 3
RxFIFO FULL—Indicates the RxFIFO is full.
0 = The RxFIFO is not full
1 = The RxFIFO is full
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-51
UART Operation in Low-Power System States
Table 21-31. UART 1 2 Test Register Descriptions (continued)
Name
Description
Reserved
Bits 2–1
Reserved—These bits are reserved and should read 0.
SOFTRST
Bit 0
Software Reset—Indicates the status of the software reset (SRST).
Settings
0 = No software reset
1 = Generate software reset
21.8 UART Operation in Low-Power System States
The UART’s serial interface will operate as long as the 16x bit clock generator is provided with the
PerCLK1. The RXEN, TXEN and UARTEN bits are set by the user and provide software control of
low-power modes.
When in DOZE state, the UART’s behavior depends on the DOZE bit. If the DOZE bit is negated and the
system is in DOZE state, the UART serial interface is operational. If the system is in DOZE state and the
DOZE bit is asserted, the UART transmitter and receiver operations are halted.
If the DOZE state is entered with the DOZE bit asserted when the UART’s serial interface is receiving or
transmitting data, the reception/transmission of the current character is completed and signal to the far-end
transmitter/receiver to stop sending/receiving. The control/status/data registers do not change when
entering or exiting low-power modes.
The following UART interrupts wake the ARM920T processor from STOP mode:
•
RTS
•
IrDA Asynchronous WAKE (AIRINT)
•
Asynchronous WAKE (AWAKE)
The UART_CLK_EN bit (UCR1_x) enables the clock inputs to the UART module. If the control bit is set
to 0, it abruptly enables the clock inputs to the UART module. To get maximum power conservation when
the module is shut off, make sure that the above clock control bit is set to 0. Setting the UARTEN
(UCR1_x) bit to 0 only shuts off the receiver and transmitter logic and the associated clocks.
When an asynchronous WAKE interrupt exits the ARM920T processor from STOP mode, make sure that
a dummy character is sent first because the first character may not be received correctly. After the settling
time of the USB_PLL, actual characters can be sent to the UART. Even though the dummy character is
written to RxFIFO, just ignore it.
MC9328MXS Reference Manual, Rev. 1.1
21-52
Freescale Semiconductor
UART Operation in Low-Power System States
I1
I2
I3
I4
I5
I6
I7
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10
BRM_CLK
CD [11:0]
0x01
NOISE
RX_PIN
110 100 000
VOTE_SR [2:0]
VOTE
RECEIVE_SR [7:0]
110 101 011
111 111 111 111 111 111 110 100 000 000 000 000 000 000 000 000 000 000 000 000 000 001 011 111 110 101 011 111 111 111 111 111 111
Start Bit
00000000
10000000
Figure 21-5. Majority Vote Results
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
21-53
UART Operation in Low-Power System States
I1
I2
I3
I4
I5
I6
I7
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S1 S2 S3
BRM_CLK
CD [11:0]
0x01
RX_PIN
VOTE_SR [2:0]
111 111 111 111 111 111 110 100 000 000 000 000 000 000 000 000 000 000 000 000 000 001 011 111 110
VOTE
start bit
RECEIVE_SR [7:0]
UBRC
00000000
08
09 0A 0B 0C 0D 0E 0F 10 10 10 10
Figure 21-6. Baud Rate Detection of Divisor = 1
MC9328MXS Reference Manual, Rev. 1.1
21-54
Freescale Semiconductor
Chapter 22
USB Device Port
This chapter describes the USB device port of the MC9328MXS. It also provides configuration, interface
description and detailed programming information for designers to achieve the optimum performance from this
device.
22.1 Introduction
The Universal Serial Bus specification describes a USB system as having the following three parts:
•
A USB host—The bus master that periodically polls peripherals to initiate data transfers. There is only one
host on the bus.
•
A USB device—A bus slave that communicates only with a USB host. It does not generate bus traffic and
only responds to requests from the host.
•
A USB Interconnect—A special class of USB devices that add additional connection points to the bus for
more USB devices.
From the user’s perspective, the USB module hides all direct interaction with the USB protocol. The registers
allow the user to enable or disable the module, control the characteristics of individual endpoints, and monitor
traffic flow through the module without ever seeing the low level details of the USB protocol.
Even though this module hides all direct interaction with the protocol, some knowledge of the USB is required to
properly configure the device for operation on the bus. Programming requirements are covered in this chapter.
22.1.1 Features
The USB device module on the MC9328MXS provides the following USB features:
•
Complies with Universal Serial Bus Specification Revision 1.1.
•
Endpoint configurations are shown in Table 22-1. Six pipes are available for mapping. Endpoint 0 is
required by the USB specification, however all other endpoints are optional. While endpoints
1, 2, 3, 4, and 5 can be configured as Bulk, Interrupt or Isochronous pipes (IN or OUT).
•
Control, bulk and interrupt pipes are supported. The packet sizes are limited to 8, 16, 32, or 64 bytes, and
the maximum packet size depends on the endpoint’s FIFO size.
•
Isochronous communications pipes are also supported. A frame match interrupt feature that notifies the user
when a specific USB frame occurs is supported. For DMA access, the maximum packet size for the
isochronous endpoint is restricted by the endpoint’s FIFO size. For programmed I/O, isochronous data
packets can take any size from 0 to 1023 bytes.
•
Remote wake-up feature is supported through a register bit.
•
The USB module operation is operates in both bus-powered and self-powered mode.
•
Full speed (12 Mbps) operation.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
22-1
Module Components
l
Table 22-1. Endpoint Configurations
Endpoint
Type
Physical FIFO Size
Endpoint Configuration
Comments
0
IN and OUT
32 bytes
Control
Mandatory
1
IN or OUT
64 bytes
Ctrl, Int, Bulk, or Iso
Optional
2
IN or OUT
64 bytes
Ctrl, Int, Bulk, or Iso
Optional
3
IN or OUT
32 bytes
Ctrl, Int, Bulk, or Iso
Optional
4
IN or OUT
32 bytes
Ctrl, Int, Bulk, or Iso
Optional
5
IN or OUT
32 bytes
Ctrl, Int, Bulk, or Iso
Optional
Table 22-2. USB Specific Interrupts
Name of Interrupt
(from Interrupt
Assignment Table)
Description
Associated Status
Register
USBD_INT[0]
Endpoint 0 Interrupt
USB_EP0_INTR
USBD_INT[1]
Endpoint 1 Interrupt
USB_EP1_INTR
USBD_INT[2]
Endpoint 2 Interrupt
USB_EP2_INTR
USBD_INT[3]
Endpoint 3 Interrupt
USB_EP3_INTR
USBD_INT[4]
Endpoint 4 Interrupt
USB_EP4_INTR
USBD_INT[5]
Endpoint 5 Interrupt
USB_EP5_INTR
USBD_INT[6]
USBd Interrupt
USB_INTR
22.2 Module Components
A block diagram of the complete USB Device is shown in Figure 22-1. This section briefly describes each of the
components within the module.
MC9328MXS Reference Manual, Rev. 1.1
22-2
Freescale Semiconductor
Module Components
Peripheral Bus
USB Core
USB DMA
Control
Bus IP
(BlueLine)
Register Decodes
Internal Peripheral Bus
Control Logic
FIFO
Control
... x5...
FIFO
RAM
Muxing
Write Port
FIFO
Control
Read Port
FIFO 0
32bytes
FIFO1 & 2
64bytes
FIFO
RAM
Dual Port,
4 banks
x 9 bits
Interrupts
USB Configuration/Control
Endpoint Configuration
Module Specification Revision
Frame Count/Match
Endpoint Buffer Download
FIFO
Configuration
Application
Bus
Decode
FIFO 3–5
32bytes
Synchronization
Synchronization &
Transaction Decode
UDC Core
To/From USB Transceiver
Figure 22-1. USB Device Module Block Diagram
22.2.1 Universal Serial Bus Device Controller
The Universal Serial Bus Device Controller Core (UDC) interfaces the USB function device to the Universal Serial
Bus. The UDC handles all the USB protocol and provides a simple read/write protocol on the function interface
(application bus). The UDC handles all details of managing the USB protocol and presents a simple set of
handshakes to the application for managing data flow, vendor commands, and configuration information. It
provides the following features:
•
Complies with USB Specification revision 1.1
•
Supports USB protocol handling
•
Requires no microcontroller or firmware support
•
Provides USB device state handling
•
Enables clock and data recovery from USB
•
Supports bit stripping and bit stuffing functions
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
22-3
Module Components
•
Supports CRC5 checking and CRC16 generation and checking
•
Provides serial to parallel data conversion
•
Maintains data synchronization bits (DATA0/DATA1) toggle bits
•
Understands and decodes standard USB commands to endpoint 0
22.2.2 Synchronization and Transaction Decode
The synchronization and transaction decode block performs two functions:
•
It synchronizes the front-end logic timing to the UDC’s application bus timing. The front-end logic is
targeted for a maximum of 96 MHz operation, while the UDC’s application bus runs at 12 MHz for
full-speed devices.
•
The synchronization layer contains a transaction decoder. The application bus protocol is very simple and
makes no distinction between RAM, FIFO, and configuration access. The decoder examines the type of
transaction requested by the UDC and generates control signals appropriate to that transaction type (RAM,
FIFO, and so on).
The transaction decoder ensures that all packet transfers occur in units of the maximum packet size for the selected
endpoint. This block decodes the buffer address from the UDC’s application bus to determine the maximum packet
size for the current endpoint. It also looks at bytes free and end-of-frame (EOF) information from the FIFO module
to determine when a packet transfer occurs.
In general, all transfers are of the maximum packet size except when all of these conditions apply:
•
The endpoint is isochronous
•
The transmit FIFO has less than the maximum packet size worth of data available
•
There is an end-of-frame indicator in the FIFO
The transaction decoder also handles hardware retries of USB packets containing errors. The hardware is capable
of retransmitting an IN packet to the host or discarding an OUT packet from the host.
The synchronization and transaction decode section contains logic related to the UDC module’s clock enable. The
UDC module is designed with low-power operation in mind. It includes a gated clock and part of the enable logic
for that clock with low-power operation in mind.
22.2.3 Endpoint FIFO Architecture
The USB protocol has some specialized requirements that affect FIFO implementation and essentially require one
FIFO per USB endpoint. The USB host can access any endpoint on the function in any order, even the same
endpoint in back-to-back transactions, however there is a latency requirement that means the USB device must
respond to the USB host within a certain number of USB bit times or the device loses its time slice on the USB
until some point in the future. To achieve maximum USB bandwidth use, the USB device must provide full packets
of data to the USB host immediately on request and receive full packets from the host on request. This requirement
results in one FIFO per USB endpoint.
Depending on the traffic requirements, the FIFO sizes are adjustable to support double buffering. Typically, bulk
and isochronous endpoints are double buffered, while interrupt and control endpoints usually are single buffered.
Six endpoint FIFOs are available in the USB device module:
•
FIFO 0, 32 bytes
•
FIFO 1, 64 bytes
MC9328MXS Reference Manual, Rev. 1.1
22-4
Freescale Semiconductor
Module Components
•
FIFO 2, 64 bytes
•
FIFO 3, 32 bytes
•
FIFO 4, 32 bytes
•
FIFO 5, 32 bytes
22.2.4 Control Logic
The USB module’s control logic section implements the logic and registers that allow the user to control and
communicate with the USB module. The register functions include interrupt status/mask, USB configuration
download, FIFO control and access, and device request processing from the control endpoint.
22.2.5 USB Transceiver Interface
The MC9328MXS provides support for a low-cost external USB transceiver interface. Generic USB transceivers
that support 3.0 V I/O levels are supported. The transceiver interface signals are illustrated in Figure 22-2 and each
signal is described in the following section.
V Supply
USBD_AFE
USBD_ROE
USB Core
UDC
I/O Translators
MC9328MXS
SW
USBD_VMO
USBD_BPO
USBD_SUSPND
USBD_RCV
USBD_VP
USBD_VM
USB
Transceiver
VCC
OE
VMO/FSEO
VPO
SUSPND
RCV
D+
D–
VP
VM
Figure 22-2. USB Module Transceiver Interface
22.2.6 Signal Description
The USB module has seven signals that can be used to interface with the external USB driver.
• USBD_AFE—Analog Front-End Enable. This signal is used to enable the front-end transceiver (optional).
•
USBD_ROE—Reverse Output Enable. This active low signal is used to control the transceiver to drive its
D+/D- signal (to the host connection) according to the signal in USBD_VPO and USBD_VMO (output
signal), respectively.
•
USBD_VMO/USBD_VPO—USB Module Data Output. These signals provide single ended data to the
USB Transceiver Transmitter differential driver.
•
USBD_SUSPND—Transceiver Suspend Enable. This signal, when high, activates a low-power state in the
USB transceiver. Normally, when suspended, the transceiver drives USBD_RCV low and tri-state the USB
bus signals D+ and D-.
•
USBD_RCV—USB Module Receive Data. This signal is a CMOS level driven signal provided by the
external USB transceiver. The signal is derived from the D+ and D- differential input to the transceiver.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
22-5
Programming Model
•
USBD_VP—Input D+ signal connected directly to the D+.
•
USBD_VM—Input D- signal connected directly to the D-.
22.2.7 Pin Configuration for USB
Table 22-3 lists the pins used by the USB module. These pins are multiplexed with other functions on the device
and must be configured for USB operation.
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 25.5.1, “Data Direction Registers,” on
page 25-8 for details.
Table 22-3. Pin Configuration for USB Module
Pin
Setting
Configuration Procedure
USBD_AFE
Primary function of
GPIO Port B [20]
1.Clear bit 20 of Port B GPIO In Use Register (GIUS_B)
2.Clear bit 20 of Port B General Purpose Register (GPR_B)
USBD_SUSPND
Primary function of
GPIO Port B [23]
1.Clear bit 23 of Port B GPIO In Use Register (GIUS_B)
2.Clear bit 23 of Port B General Purpose Register (GPR_B)
USBD_VMO
Primary function of
GPIO Port B [27]
1.Clear bit 27 of Port B GPIO In Use Register (GIUS_B)
2.Clear bit 27 of Port B General Purpose Register (GPR_B)
USBD_VPO
Primary function of
GPIO Port B [26]
1.Clear bit 26 of Port B GPIO In Use Register (GIUS_B)
2.Clear bit 26 of Port B General Purpose Register (GPR_B)
USBD_ROE
Primary function of
GPIO Port B [21]
1.Clear bit 21 of Port B GPIO In Use Register (GIUS_B)
2.Clear bit 21 of Port B General Purpose Register (GPR_B)
USBD_VM
Primary function of
GPIO Port B [25]
1.Clear bit 25 of Port B GPIO In Use Register (GIUS_B)
2.Clear bit 25 of Port B General Purpose Register (GPR_B)
USBD_VP
Primary function of
GPIOP Port B [24]
1.Clear bit 24 of Port B GPIO In Use Register (GIUS_B)
2.Clear bit 24 of Port B General Purpose Register (GPR_B)
USBD_RCV
Primary function of
GPIO Port B [22]
1.Clear bit 22 of Port B GPIO In Use Register (GIUS_B)
2.Clear bit 22 of Port B General Purpose Register (GPR_B)
22.3 Programming Model
The USB module includes 20 required and 55 optional 32-bit registers. Table 22-4 summarizes these registers and
their addresses.
Table 22-4. USB Module Register Memory Map
Description
Name
Address
USB Frame
USB_FRAME
0x00212000
USB Specification
USB_SPEC
0x00212004
USB Status
USB_STAT
0x00212008
MC9328MXS Reference Manual, Rev. 1.1
22-6
Freescale Semiconductor
Programming Model
Table 22-4. USB Module Register Memory Map (continued)
Description
Name
Address
USB Control
USB_CTRL
0x0021200C
USB Descriptor RAM Address
USB_DADR
0x00212010
USB Descriptor RAM/Endpoint Buffer Data
USB_DDAT
0x00212014
USB Interrupt
USB_INTR
0x00212018
USB Interrupt Mask
USB_MASK
0x0021201C
USB Enable
USB_ENAB
0x00212024
Endpoint n Status/Control
USB_EPn_STAT
0x00212030+ (n*0x30)1
Endpoint n Interrupt Status
USB_EPn_INTR
0x00212034+ (n*0x30)1
Endpoint n Interrupt Mask
USB_EPn_MASK
0x00212038+ (n*0x30)1
Endpoint n FIFO Data
USB_EPn_FDAT
0x0021203C+ (n*0x30)1
Endpoint n FIFO Status
USB_EPn_FSTAT
0x00212040+ (n*0x30)1
Endpoint n FIFO Control
USB_EPn_FCTRL
0x00212044+ (n*0x30)1
USB Endpoint n Last Read Frame Pointer
USB_EPn_LRFP
0x00212048+ (n*0x30)1
USB Endpoint n Last Write Frame Pointer
USB_EPn_LWFP
0x0021204C+ (n*0x30)1
Endpoint n FIFO Alarm
USB_EPn_FALRM
0x00212050+ (n*0x30)1
Endpoint n FIFO Read Pointer
USB_EPn_FRDP
0x00212054+ (n*0x30)1
Endpoint n FIFO Write Pointer
USB_EPn_FWRP
0x00212058+ (n*0x30)1
1.
The parameter ‘n’ refers to the number of endpoints programmed into this device through
MPP software in RTL and ranges from 0 to 5.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
22-7
Programming Model
22.3.1 USB Frame Register
The USB Frame Number and Match register (USB_FRAME) is used to detect a specific frame.
USB_FRAME
BIT
31
Addr
0x00212000
USB Frame
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MATCH
TYPE
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
FRAME
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 22-5. USB Frame Register Description
Name
Description
Reserved
Bits 31–27
Reserved—These bits are reserved and should read 0.
MATCH
Bits 26–16
Match Field—Sets compare value for FRAME_MATCH interrupt. When the value in the FRAME field
equals the value in the MATCH field, a FRAME_MATCH interrupt is generated (if not masked).
Reserved
Bits 15–11
Reserved—These bits are reserved and should read 0.
FRAME
Bits 10–0
Frame Field—Holds the frame number decoded from the SOF (Start of Frame) packet that leads each
USB frame.
MC9328MXS Reference Manual, Rev. 1.1
22-8
Freescale Semiconductor
Programming Model
22.3.2 USB Specification Register
The read-only USB Specification and Release Number register (USB_SPEC) stores information about the version
of the USB specification with which the USB module complies.
USB_SPEC
Addr
0x00212004
USB Specification
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SPEC
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
RESET
0x0110
Table 22-6. USB Specification Register Description
Name
Description
Reserved
Bits 31–12
Reserved—These bits are reserved and should be set to 0.
SPEC
Bits 11–0
Specification Number—Contains the version of USB
specification with which the underlying USB core complies.
These 12 bits represent the version number of
the specification.
0x110 = version 1.1
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
22-9
Programming Model
22.3.3 USB Status Register
The read-only USB Status register (USB_STAT) reports the current state of various features of the USB module.
Certain bits are used only for hardware debug mode and always read 0 when debug mode is not enabled.
USB_STAT
Addr
0x00212008
USB Status
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
6
RST
SUSP
CFG
INTF
ALTSET
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 22-7. USB Status Register Description
Name
Description
Settings
Reserved
Bits 31–9
Reserved—These bits are reserved and should read 0.
RST
Bit 8
Reset Signaling—Indicates type of reset signaling.
0 = Normal signaling in
progress on USB
1 = Reset signaling in
progress on USB
SUSP
Bit 7
Suspend—Indicates USB suspend condition.
0 = USB is not suspended
1 = USB is suspended
CFG
Bits 6–5
Configuration—Represents the currently selected USB configuration. See Section 22.5.1,
“Configuration Download.”
INTF
Bits 4–3
Interface—Identifies the USB interface in the current configuration that is associated with the
Alternative Interface Indicator (AINTF).
ALTSET
Bits 2–0
Alternate Setting—Contains the currently selected USB alternate setting.
MC9328MXS Reference Manual, Rev. 1.1
22-10
Freescale Semiconductor
Programming Model
22.3.4 USB Control Register
The USB Control register (USB_CTRL) configures numerous features of the USB module.
USB_CTRL
Addr
0x0021200C
USB Control
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
CMD_
OVER
CMD_
ERROR
RESET
0x0000
BIT
15
TYPE
14
13
12
11
10
9
8
7
USB_ USB_ UDC_ AFE_
SPD
ENA
RST
ENA
RESUME
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
w
rw
w
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
RESET
0x0010
Table 22-8. USB Control Register Description
Name
Description
Settings
Reserved
Bits 31–7
Reserved—These bits are reserved and should read 0.
CMD_OVER
Bit 6
Command Over—Indicates status of command processing. See
Table 22-9 for more information. CMD_OVER clears automatically
after the UDC core has completed the status phase of a control
transfer.
0 = Command complete
1 = Command in process
CMD_ERROR
Bit 5
Command Error—Indicates if an error was encountered during
processing of a device request. See Table 22-9 for more
information. CMD_OVER and CMD_ERROR combine to create the
handshaking code for the status phase of a device request
transaction.
0 = If the command was processed,
there was no error
1 = If the command was processed,
an error occurred
USB_SPD
Bit 4
USB Speed—Sets the operating speed for the USB module.
0 = Low speed
1 = Full speed
Note: The USB module supports only full speed operation of the
device. Attempts to set to slow speed results in unpredictable
operation.
USB_ENA
Bit 3
USB Enable—Determines whether the USB module responds to
requests from the USB host. The USB module comes out of reset in
the disabled state. The user must ensure that the USB endpoint
configuration and USB registers are programmed appropriately
before enabling communications. USB_ENA does not affect the
underlying UDC core, only the front-end logic’s ability to
communicate with the core.
0 = USB module front-end logic is
disabled. All transactions to or
from the UDC are ignored.
1 = USB module front-end logic is
enabled and ready to
communicate with the host.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
22-11
Programming Model
Table 22-8. USB Control Register Description (continued)
Name
Description
Settings
UDC_RST
Bit 2
UDC Reset—Executes a hard reset sequence on the UDC module
in accordance with the UDC specification. It allows the system
software to force a reset of the UDC’s logic when the system is first
connected to the USB, or for debugging purposes.
0 = No effect
1 = Hard reset of the UDC
AFE_ENA
Bit 1
Analog Front-End Enable—Enables/Disables the analog
front-end to the USB. This can be either an external chip or an
on-chip transceiver module. Use AFE_ENA to power-down the
AFE.
0 = AFE disabled
1 = AFE enabled
RESUME
Bit 0
Resume—Initiates resume signaling on the USB. Automatically
resets to 0 after a write. Remote wake-up capability is controlled in
the UDC through the CLEAR_FEATURE request. Software must
have a time-out feature that aborts the remote wake-up attempt
when the RESUME interrupt does not occur after a specified time.
0 = No effect
1 = Initiate resume signaling on the
bus when the remote wake-up
capability is enabled for the
current USB configuration.
When the remote wake-up
capability is disabled, RESUME
has no effect.
Table 22-9. Device Request Status
Result of Transfer
CMD_OVER
CMD_ERROR
Application processed the device request successfully
0
0
Application encountered an error while processing the request
0
1
Application is busy completing the request
1
X
MC9328MXS Reference Manual, Rev. 1.1
22-12
Freescale Semiconductor
Programming Model
22.3.5 USB Descriptor RAM Address Register
This register allows user access to the USB descriptor RAM. The user programs a desired address into the 9-bit
desired RAM address (DADR) field and follows it with a read or write to the USB_DDAT register to complete the
access. On read/write access to the USB Descriptor RAM/Endpoint Buffer Data (USB_DDAT), the address in the
DADR field increments automatically. When the CFG bit is set to 1, the DADR address is ignored.
USB_DADR
BIT
TYPE
Addr
0x00212010
USB Descriptor RAM Address
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CFG
BSY
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x8000
BIT
15
14
13
12
11
10
9
8
DADR
TYPE
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 22-10. USB Descriptor RAM Address Register Description
Name
Description
Settings
CFG
Bit 31
Configuration—Determines the function of USB_DDAT
Register. The Configuration versus Descriptor access
indicator is set automatically at power-on or hard reset
and clears after the last byte of endpoint buffer
configuration data is downloaded into the UDC.
0 = The USB_DDAT register is set to access the
descriptor storage RAM. Configuration load has
completed. The USB_DDAT writes have no
effect.
1 = The USB_DDAT register is set to download
endpoint buffer configuration data to the UDC.
BSY
Bit 30
Busy—Indicates if a write is in progress to the endpoint
buffer. Because the front-end logic and the UDC module
operate on different clocks, the configuration download
interface busy signal is provided to ensure that writes
from the USB_DDAT register have sufficient time to
successfully enter the UDC’s clock domain.
0 = No write is in progress.
1 = A write is in progress to the UDC module’s
endpoint buffer. Attempt no other operations on
the USB Core module until BSY has cleared.
Reserved
Bits 29–9
Reserved—These bits are reserved and should read 0.
DADR
Bits 8–0
Desired RAM Address—Holds the desired RAM address. The user programs a desired descriptor RAM
address into the DADR field and follows it with a read or write to the USB_DDAT register to complete the access.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
22-13
Programming Model
22.3.6 USB Descriptor RAM/Endpoint Buffer Data Register
This register allows user access to the endpoint buffer download facility. For endpoint buffer access, when the CFG
bit in the USB_DADR register is set, writes to this register cause the data to be loaded into the UDC module’s
endpoint buffers, and reads are undefined. When the CFG bit in the USB_DADR register is cleared, writes have no
effect and reads are zero.
Access to this register is allowed only when the USB_ENA bit in the USB Control (USB_CTRL) is set to 0.
Access at other times is ignored and reads are undefined.
USB_DDAT
Addr
0x00212014
USB Descriptor RAM/Endpoint Buffer Data
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DDAT
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 22-11. USB Descriptor RAM/Endpoint Buffer Data Register Description
Name
Description
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
DDAT
Bits 7–0
DDAT—Allows user access to the endpoint buffer in the UDC module when the endpoint configuration is
happening. (When the CFG bit in the USB_DADR is set) Writing to this field loads the data written into the
UDC endpoint buffers.
MC9328MXS Reference Manual, Rev. 1.1
22-14
Freescale Semiconductor
Programming Model
22.3.7 USB Interrupt Register
The USB Interrupt register (USB_INTR) maintains the status of interrupt conditions that pertain to USB functions.
An interrupt, when set, remains set until 1 is written to the corresponding bit. Interrupts do not clear automatically
when the event that caused them goes away. For example, when reset signaling comes and goes with no
intervention from software, both RESET_START and RESET_STOP are set and stay set. Writing 0 to this register
has no effect.
If a register write occurs at the same time an interrupt is received, the interrupt takes precedence over the write.
USB_INTR
BIT
31
Addr
0x00212018
USB Interrupt
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
rw
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WAKEUP
TYPE
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MSOF
SOF
RESET
_STOP
RESET
_START
RES
SUSP
FRAME
_MATCH
CFG_
CHG
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 22-12. USB Interrupt Register Description
Name
WAKEUP
Bit 31
Description
Wakeup—Indicates a state change from suspend to
resume (wakeup) in the UDC module. Clearing the
interrupt has no effect on the actual state of the USB
module (WAKEUP can be written to even when the
module is disabled.)
Settings
0 = No state change since last interrupt
1 = USB has changed state from suspend
to resume (wakeup)
Note: Use the asynchronous WAKEUP interrupt to
power-down the module clocks and to power-up the USB
module.
Reserved
Bits 30–8
Reserved—These bits are reserved and should read 0.
MSOF
Bit 7
Missed Start-of-Frame Interrupt—Indicates if a
start-of-frame was missed.
0 = No missed start-of-frame
1 = A SOF interrupt was set, however not
cleared before the next one was
received
SOF
Bit 6
Start-of-Frame Interrupt—Indicates if a start-of-frame
was received.
0 = No start-of-frame received
1 = The UDE module received a
start-of-frame token (the USB frame
number is current)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
22-15
Programming Model
Table 22-12. USB Interrupt Register Description (continued)
Name
Description
Settings
RESET_STOP
Bit 5
Reset Signaling Stop—Indicates the end of reset
signaling on the USB.
0 = Reset signaling has not stopped (does
not imply that reset signaling is
occurring, just that no end-of-reset
event has occurred)
1 = Reset signaling has stopped
RESET_START
Bit 4
Reset Signaling Start—Indicates start of reset signaling
on the USB.
0 = Reset signaling has not started (does
not imply that reset signaling is
occurring, but only that no start of reset
event has occurred)
1 = Reset signaling in progress
RES
Bit 3
Suspend to Resume—Indicates a change of state from
suspend to resume in the UDC module (indicates only the
change from suspended to active mode). Clearing the
interrupt has no effect on the actual state of the USB.
0 = The USB has not left the suspended
state (does not imply that the bus is, or
ever was, suspended)
1 = USB has left the suspend state
SUSP
Bit 2
Active to Suspend—Indicates the suspend state of the
UDC module (indicates only the change from active to
suspended mode). Clearing the interrupt has no effect on
the actual state of the USB.
0 = USB is not suspended, or the interrupt
was cleared
1 = USB is suspended
FRAME_MATCH
Bit 1
Frame Match—Indicates whether there is a match
between the USB frame number and the value in the USB
Frame.
0 = No match occurred
1 = Match occurred
CFG_CHG
Bit 0
Configuration Change—Indicates if a change occurred
in the USB configuration (configuration, interface,
alternate) which requires the software to reread the USB
Status.
0 = No configuration change occurred
1 = Configuration change occurred
MC9328MXS Reference Manual, Rev. 1.1
22-16
Freescale Semiconductor
Programming Model
22.3.8 USB Interrupt Mask Register
The USB Interrupt Mask register (USB_MASK) is used to mask the corresponding interrupt in the USB_INTR
register.
USB_MASK
BIT
31
Addr
0x0021201C
USB Interrupt Mask
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
rw
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WAKEUP
TYPE
RESET
0x8000
BIT
15
TYPE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MSOF
SOF
RESET_
STOP
RESET_
START
RES
SUSP
FRAME_
MATCH
CFG_
CHG
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RESET
0x00FF
Table 22-13. USB Interrupt Mask Register Description
Name
Description
Settings
WAKEUP
Bit 31
Wakeup Mask—Enables/Disables the WAKEUP interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
Reserved
Bits 30–8
Reserved—These bits are reserved and should read 0.
MSOF
Bit 7
Missed Start-of-Frame Mask—Enables/Disables the MSOF
interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
SOF
Bit 6
Start-of-Frame Mask—Enables/Disables the SOF interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
RESET_STOP
Bit 5
Reset Signaling Stop Mask—Enables/Disables the
RESET_STOP interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
RESET_START
Bit 4
Reset Signaling Start Mask—Enables/Disables the
RESET_START interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
RES
Bit 3
Suspend to Resume Mask—Enables/Disables the RES
interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
SUSP
Bit 2
Suspend Mask—Enables/Disables the SUSP interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
FRAME_MATCH
Bit 1
Frame Match Mask—Enables/Disables the FRAME_MATCH
interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
CFG_CHG
Bit 0
Configuration Change Mask—Enables/Disables the
CFG_CHG interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
22-17
Programming Model
22.3.9 USB Enable Register
The USB Enable register (USB_ENAB) controls the operation of the USB functions.
USB_ENAB
BIT
31
30
29
28
RST
ENAB
SUSPEND
ENDIAN_
MODE
rw
rw
r
0
0
0
TYPE
Addr
0x00212024
USB Enable
27
26
25
24
23
22
21
20
19
18
17
16
r/w
r
r
r
r
r
r
r
r
r
r
r
r
1
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
RESET
0x1000
BIT
15
14
13
12
11
10
9
PWRMD
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
RESET
0x0001
Table 22-14. USB Enable Register Description
Name
RST
Bit 31
Description
Reset—Indicates the USB’s software reset state.
Automatically clears after the USB module is reset.
Note:
Settings
0 = No USB reset in progress
1 = USB reset in progress
Setting RST automatically sets the ENAB bit.
ENAB
Bit 30
Enable—Indicates the USB’s enable state.
When the USB is disabled, all write access to the USB
registers is ignored except for writes to ENAB and to the
WAKEUP bit in the USB_INTR register.
0 = Disable the USB
1 = Enable the USB
SUSPEND
Bit 29
Suspend—Indicates whether the UDC module is in the
suspend state.
0 = Module is in resume/active state
1 = Module is in suspend state
ENDIAN_MODE
Bit 28
Endian Mode Select—Selects whether the USB module is
in Big Endian mode or Little Endian mode.
1 = USBd module is in Little Endian mode
0 = USBd module is in Big Endian mode
Reserved
Bits 27–1
Reserved—These bits are reserved and should read 0.
PWRMD
Bit 0
Power Mode—Determines the power mode of USBD. The
default power mode is self powered.
0 = Bus powered mode
1 = Self-powered mode
MC9328MXS Reference Manual, Rev. 1.1
22-18
Freescale Semiconductor
Programming Model
22.3.10 Endpoint n Status/Control Registers
The Endpoint n Status/Control registers allow the user to configure the endpoints and contains a field for
maintaining a count of the FIFO contents.
The number of Endpoint n Status/Controls in the MC9328MXS depends on the number of endpoints configured.
USB_EP0_STAT
USB_EP1_STAT
USB_EP2_STAT
USB_EP3_STAT
USB_EP4_STAT
USB_EP5_STAT
BIT
31
30
Addr
0x00212030
0x00212060
0x00212090
0x002120C0
0x002120F0
0x00212120
Endpoint 0 Status/Control Register
Endpoint 1 Status/Control Register
Endpoint 2 Status/Control Register
Endpoint 3 Status/Control Register
Endpoint 4 Status/Control Register
Endpoint 5 Status/Control Register
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BYTE_COUNT
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
TYPE
14
13
12
11
10
9
8
7
SIP
DIR
MAX
TYP
ZLPS FLUSH
FORCE_
STALL
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
w
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 22-15. Endpoint n Status/Control Register Description
Name
Description
Settings
Reserved
Bits 31–23
Reserved—These bits are reserved and should read 0.
BYTE_COUNT
Bits 22–16
Byte Count—Represents the number of bytes currently stored in the associated FIFO.
Reserved
Bits 15–9
Reserved—These bits are reserved and should read 0.
SIP
Bit 8
Setup Packet In Progress—Indicates whether the setup packet
is being transferred from host to device.
0 = Setup data is not being
transferred from host to device
1 = Setup data is currently being
transferred from host to device
DIR
Bit 7
Transfer Direction—Sets the endpoint direction (DIR is ignored
for control endpoints).
0 = OUT endpoint
(from host to device)
1 = IN endpoint
(from device to host)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
22-19
Programming Model
Table 22-15. Endpoint n Status/Control Register Description (continued)
Name
MAX
Bits 6–5
Description
Maximum Packet Size—Sets the maximum packet size for the
endpoint (MAX is ignored for -ronous endpoints).
Note: The maximum packet size cannot be greater than the
endpoint’s FIFO size. See Table 22-1 for FIFO sizes.
Settings
00 = Packet is 8 Bytes
01 = Packet is 16 Bytes
10 = Packet is 32 Bytes
11 = Packet is 64 Bytes
TYP
Bits 4–3
Endpoint Type—Sets up the type of endpoint being used.
Endpoint 0 is defined as a control endpoint, however all other
endpoints can be any type.
00 = Control
01 = Isochronous
10 = Bulk
11 = Interrupt
ZLPS
Bit 2
Zero Length Packet Send—Determines if a zero length packet
will be sent to the host. If the FIFO is empty and the USB host
requests an IN transaction, the USB module can send a zero
length packet in response. ZLPS automatically clears after the
transaction completes successfully. ZLPS signifies to the USB
host that the end of data was reached in a data transmission
when the end of data lands on a packet boundary and there is no
short packet to signify the end of data.
0 = No zero length packet to send
1 = A zero length packet to send
FLUSH
Bit 1
Flush—Flushes the associated FIFO to its empty state.
0 = Do nothing
1 = Initiate flush operation
FORCE_STALL
Bit 0
Force a Stall Condition—Causes the endpoint to respond with a
STALL to the next poll, and automatically clears when the stall
takes effect.
0 = Do nothing
1 = Force a stall condition
Note: There is no endpoint stalled indicator because one is not
returned from the UDC. The USB host is expected to
communicate with the USB device through device requests to fix
the stall condition. The USB host sends a CLEAR_FEATURE
request to the UDC module to clear the stall and resume normal
operations.
22.3.11 Endpoint n Interrupt Status Registers
The Endpoint n Interrupt Status registers monitor the status of a specific endpoint and generates CPU interrupts
each time a monitored event occurs.
When an interrupt is set, it remains set until cleared by writing 1 to the corresponding bit. Interrupts do not clear
automatically when the event that caused them goes away (for example, when reset signaling comes and goes with
no intervention from software, both RESET_START and RESET_STOP are set). Writing 0 has no effect.
If a register write occurs at the same time an interrupt is received, the interrupt takes precedence over the write.
The number of Endpoint n Interrupt Statuss in the MC9328MXS depends on the number of endpoints configured.
MC9328MXS Reference Manual, Rev. 1.1
22-20
Freescale Semiconductor
Programming Model
USB_EP0_INTR
USB_EP1_INTR
USB_EP2_INTR
USB_EP3_INTR
USB_EP4_INTR
USB_EP5_INTR
Addr
0x00212034
0x00212064
0x00212094
0x002120C4
0x002120F4
0x00212124
Endpoint 0 Interrupt Status Register
Endpoint 1 Interrupt Status Register
Endpoint 2 Interrupt Status Register
Endpoint 3 Interrupt Status Register
Endpoint 4 Interrupt Status Register
Endpoint 5 Interrupt Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIFO_
FULL
FIFO_
EMPTY
FIFO_
ERROR
FIFO_
HIGH
FIFO_
LOW
MDEV
REQ
EOT
DEV
REQ
EOF
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
RESET
0x0080
Table 22-16. Endpoint n Interrupt Status Register Description
Name
Description
Settings
Reserved
Bits 31–9
Reserved—These bits are reserved and should read 0.
FIFO_FULL
Bit 8
FIFO Full—Indicates whether the FIFO is full or not.
0 = The FIFO is not full
1 = The FIFO is full
FIFO_EMPTY
Bit 7
FIFO Empty—Indicates whether the FIFO is empty or not.
0 = The FIFO is not empty
1 = The FIFO is empty
FIFO_ERROR
Bit 6
FIFO Error—Indicates an error condition in the FIFO
controller. The specific error condition can be checked by
reading the Endpoint n FIFO Status (USB_EPn_FSTAT).
0 = No error condition pending
1 = Error condition pending
FIFO_HIGH
Bit 5
FIFO High—Asserts when the FIFO has hit a high level
alarm. FIFO_HIGH applies only when the FIFO is in
receive mode (USB OUT).
0 = The number of data bytes in the FIFO is
less than GR value from the Endpoint n
FIFO Control
1 = The number of free bytes in the FIFO is
less than ALRM value from the Endpoint
n FIFO Alarm
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
22-21
Programming Model
Table 22-16. Endpoint n Interrupt Status Register Description (continued)
Name
Description
Settings
FIFO_LOW
Bit 4
FIFO Low—Asserts when the FIFO has hit a low level
alarm. FIFO_LOW applies only when the FIFO is in
transmit mode (USB IN).
0 = The number of free bytes in the FIFO is
less than 4xGR value from the Endpoint n
FIFO Control
1 = The number of data bytes in the FIFO is
less than ALRM value from the Endpoint
n FIFO Alarm
MDEVREQ
Bit 3
Multiple Device Requests—Asserts when a DEVREQ
interrupt is pending and another setup packet is received.
MDEVREQ asserts only for control endpoints.
0 = Multiple setup packets are not pending
1 = Multiple setup packets pending
EOT
Bit 2
End-of-Transfer—Asserts when the last packet of a USB
data transfer has crossed into, or out of, the UDC module.
The last packet is identified by its length. Any packet
shorter than the maximum packet size for the associated
endpoint is considered to be an end-of-transfer marker.
The EOT interrupt also asserts (for control endpoints only)
when the number of bytes specified in the wLength field of
the setup packet has been transferred.
0 = Last packet of data not sent/received
1 = Last packet of data sent/received
DEVREQ
Bit 1
Device Request—Indicates whether there is a device
request on the current endpoint. DEVREQ asserts only for
control endpoints.
0 = No request pending
1 = Request pending
EOF
Bit 0
End-of-Frame—Indicates whether there is end-of-frame
activity for this endpoint. EOF monitors the data flow
between the FIFO and the UDC and indicates when the
end of a USB packet is written into the FIFO or the UDC
as the end of a frame.
0 = End-of-frame (USB packet) not
sent/received
1 = End-of-frame (USB packet) sent/received
MC9328MXS Reference Manual, Rev. 1.1
22-22
Freescale Semiconductor
Programming Model
22.3.12 Endpoint n Interrupt Mask Register
The Endpoint n Interrupt Mask registers allow the user to mask individual interrupts for each endpoint. Writing 1
to a bit in this register masks the corresponding interrupt in the USB_EPn_STAT register. Writing 0 unmasks the
interrupt.
The number of Endpoint n Interrupt Masks in the MC9328MXS depends on the number of endpoints configured.
USB_EP0_MASK
USB_EP1_MASK
USB_EP2_MASK
USB_EP3_MASK
USB_EP4_MASK
USB_EP5_MASK
Addr
0x00212038
0x00212068
0x00212098
0x002120C8
0x002120F8
0x00212128
Endpoint 0 Interrupt Mask Register
Endpoint 1 Interrupt Mask Register
Endpoint 2 Interrupt Mask Register
Endpoint 3 Interrupt Mask Register
Endpoint 4 Interrupt Mask Register
Endpoint 5 Interrupt Mask Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIFO_
FULL
FIFO_
EMPTY
FIFO_
ERROR
FIFO_
HIGH
FIFO_
LOW
MDEV
REQ
EOT
DEV
REQ
EOF
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
RESET
0x01FF
Table 22-17. Endpoint n Interrupt Mask Register Description
Name
Description
Settings
Reserved
Bits 31–9
Reserved—These bits are reserved and should read 0.
FIFO_FULL
Bit 8
FIFO Full Mask—Enables/Disables the FIFO Full interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
FIFO_EMPTY
Bit 7
FIFO Empty Mask—Enables/Disables the FIFO Empty interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
FIFO_ERROR
Bit 6
FIFO Error Mask—Enables/Disables the FIFO Error interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
FIFO_HIGH
Bit 5
FIFO High Alarm Mask—Enables/Disables the FIFO High Alarm
interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
FIFO_LOW
Bit 4
FIFO Low Alarm Mask—Enables/Disables the FIFO Low Alarm
interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
22-23
Programming Model
Table 22-17. Endpoint n Interrupt Mask Register Description (continued)
Name
Description
Settings
MDEVREQ
Bit 3
Multiple Device Requests Mask—Enables/Disables the Multiple
Device Requests interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
EOT
Bit 2
End-of-Transfer Mask—Enables/Disables the End-of-Transfer
interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
DEVREQ
Bit 1
Device Request Mask—Enables/Disables the Device Request
interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
EOF
Bit 0
End-of-Frame Mask—Enables/Disables the end-of-frame
interrupt.
0 = Interrupt enabled (unmasked)
1 = Interrupt disabled (masked)
MC9328MXS Reference Manual, Rev. 1.1
22-24
Freescale Semiconductor
Programming Model
22.3.13 Endpoint n FIFO Data Registers
The Endpoint n FIFO Data registers are the main interface port for each FIFO. Data to be buffered in the FIFO, or
currently buffered in the FIFO, is accessed through this register. This register can access data from the FIFO
independent of the transmit or receive configuration in byte, word, or longword formats, however each access must
be aligned with the most significant byte (big endian) of the data port. Byte 0 is bits 31:24, byte 1 is bits 23:16, byte
2 is bits 15:8, and byte 3 is bits 7:0. Byte transfers must access byte 0. Word transfers must access bytes 0 and 1,
and longword transfers must access all four bytes. USB FIFO data write is in big-endian format.
The direction of the FIFO is determined by the value of the DIR field in the Endpoint n Status/Control.
The number of Endpoint n FIFO Datas in the MC9328MXS depends on the number of endpoints configured.
USB_EP0_FDAT
USB_EP1_FDAT
USB_EP2_FDAT
USB_EP3_FDAT
USB_EP4_FDAT
USB_EP5_FDAT
BIT
31
30
Addr
0x0021203C
0x0021206C
0x0021209C
0x002120CC
0x002120FC
0x0021212C
Endpoint 0 FIFO Data Register
Endpoint 1 FIFO Data Register
Endpoint 2 FIFO Data Register
Endpoint 3 FIFO Data Register
Endpoint 4 FIFO Data Register
Endpoint 5 FIFO Data Register
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RXDATA [31:16] (Read) or TXDATA [31:16] (Write)
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0X0000
BIT
15
14
13
12
11
10
9
8
RXDATA [15:0] (Read) or TXDATA [15:0] (Write)
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 22-18. Endpoint n FIFO Data Register Description
Name
Description
TXDATA [31:0]
Bits 31–0
Transmit Data—Contains the transmit FIFO write data.
RXDATA [31:0]
Bits 31–0
Read Data—Contains the receive FIFO read data.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
22-25
Programming Model
22.3.14 Endpoint n FIFO Status Registers
The Endpoint n FIFO Status registers are the main status registers for the FIFOs, and contain information about
frame status, underflow, overflow, alarm, and FIFO content.
The number of Endpoint n FIFO Status registers in the MC9328MXS depends on the number of endpoints
configured.
USB_EP0_FSTAT
USB_EP1_FSTAT
USB_EP2_FSTAT
USB_EP3_FSTAT
USB_EP4_FSTAT
USB_EP5_FSTAT
BIT
31
30
Endpoint 0 FIFO Status Register
Endpoint 1 FIFO Status Register
Endpoint 2 FIFO Status Register
Endpoint 3 FIFO Status Register
Endpoint 4 FIFO Status Register
Endpoint 5 FIFO Status Register
29
28
27
26
25
24
23
FRAME0 FRAME1 FRAME2 FRAME3
TYPE
Addr
0x00212040
0x00212070
0x002120A0
0x002120D0
0x00212100
0x00212130
22
21
20 19
18
17
16
ERROR OF UF FR FULL ALARM EMPTY
r
r
r
r
r
r
r
r
r
rw
rw
rw
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
RESET
0x0001
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 22-19. Endpoint n FIFO Status Register Description
Name
Description
Settings
Reserved
Bits 31–28
Reserved—These bits are reserved and should read 0.
FRAME0
Bit 27
Frame Status Bit 0—Indicates whether a frame boundary
exists in bus bits [31:24] for non-DMA applications.
0 = No frame boundary on the [31:24] byte
1 = A frame boundary has occurred on the
[31:24] byte of the bus
FRAME1
Bit 26
Frame Status Bit 1—Indicates whether a frame boundary
exists in bus bits [23:16] for non-DMA applications.
0 = No frame boundary on the [23:16] byte
1 = A frame boundary has occurred on the
[23:16] byte of the bus
FRAME2
Bit 25
Frame Status Bit 2—Indicates whether a frame boundary
exists in bus bits [15:8] for non-DMA applications.
0 = No frame boundary on the [15:8] byte
1 = A frame boundary has occurred on the
[15:8] byte of the bus
MC9328MXS Reference Manual, Rev. 1.1
22-26
Freescale Semiconductor
Programming Model
Table 22-19. Endpoint n FIFO Status Register Description (continued)
Name
Description
Settings
FRAME3
Bit 24
Frame Status Bit 3—Indicates whether a frame boundary
exists in bus bits [7:0] for non-DMA applications.
0 = No frame boundary on the [7:0] byte
1 = A frame boundary has occurred on the
[7:0] byte of the bus
Reserved
Bit 23
Reserved—This bit is reserved and should read 0.
ERROR
Bit 22
FIFO Error—Signifies that an error condition has happened in
the FIFO controller. Writing 1 to ERROR clears it. Writing 0
has no effect.
0 = No error
1 = Underflow, overflow, pointer out of
bounds, or other error condition
occurred
UF
Bit 21
FIFO Underflow—Indicates FIFO underflow status. Writing 1
to UF clears it. Writing 0 has no effect.
0 = No underflow
1 = Read pointer has passed the write
pointer
OF
Bit 20
FIFO Overflow—Indicates FIFO overflow status. Writing 1 to
OF clears it. Writing 0 has no effect.
0 = No overflow
1 = Write pointer has passed the read
pointer
FR
Bit 19
Frame Ready—Indicates frame ready status. FR is inactive
when the FIFO is not programmed for frame mode.
0 = No complete frames exist in the FIFO
1 = One or more complete frames exists in
the FIFO
FULL
Bit 18
FIFO Full—Indicates FIFO full status. Read FULL to clear it.
0 = The FIFO is not full
1 = The FIFO is full
ALARM
Bit 17
FIFO Alarm—Indicates FIFO alarm status. The specific alarm
condition detected depends on the FIFO direction. The signal
relies on the values of the alarm (ALRM) field of the Endpoint n
FIFO Alarm and the granularity (GR) field of the Endpoint n
FIFO Control.
0 = The alarm not set
1 = The alarm is set
For IN (transmit) FIFOs, the ALARM bit indicates a low level. It
asserts when there are less than ALRM bytes of data
remaining in the FIFO, and deasserts when there are less than
4 times GR free bytes remaining.
When the FIFO is configured to receive (OUT FIFOs), the
ALARM bit indicates a high level. It asserts when there are
less than ALRM bytes free in the FIFO, and deasserts when
there are less than GR bytes of data remaining.
This signal is cleared by reading or writing (as appropriate) the
FIFO, or by manipulating the FIFO pointers.
EMPTY
Bit 16
FIFO Empty—Indicates FIFO empty status. Write 1 to EMPTY
to clear it.
Reserved
Bits 15–0
Reserved—These bits are reserved and should read 0.
0 = The FIFO is not empty
1 = The FIFO is empty
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
22-27
Programming Model
22.3.15 Endpoint n FIFO Control Registers
The Endpoint n FIFO Control registers are the primary control registers regarding data in the FIFO. This includes
frame mode and low and high data service requests.
The number of Endpoint n FIFO Controls in the MC9328MXS depends on the number of endpoints configured.
USB_EP0_FCTRL
USB_EP1_FCTRL
USB_EP2_FCTRL
USB_EP3_FCTRL
USB_EP4_FCTRL
USB_EP5_FCTRL
BIT
31
30
Endpoint 0 FIFO Control Register
Endpoint 1 FIFO Control Register
Endpoint 2 FIFO Control Register
Endpoint 3 FIFO Control Register
Endpoint 4 FIFO Control Register
Endpoint 5 FIFO Control Register
29
28
WFR
TYPE
Addr
0x00212044
0x00212074
0x002120A4
0x002120D4
0x00212104
0x00212134
27
26
FRAME
25
24
23
22
21
20
19
18
17
16
GR
r
r
rw
r
rw
rw
rw
rw
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
RESET
0x0100
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 22-20. Endpoint n FIFO Control Register Description
Name
Description
Reserved
Bits 31–30
Reserved—These bits are reserved and should read 0.
WFR
Bit 29
Write Frame End—Determines the end of the current
data frame in the FIFO. Setting WFR means that the
next write is the end of the current data frame.
Reserved
Bit 28
Reserved—This bit is reserved and should read 0.
Settings
0 = Next write to FIFO data register is not the
end-of-frame
1 = Next write to FIFO data register is the
end-of-frame
MC9328MXS Reference Manual, Rev. 1.1
22-28
Freescale Semiconductor
Programming Model
Table 22-20. Endpoint n FIFO Control Register Description (continued)
Name
Description
Settings
FRAME
Bit 27
Frame Mode—Indicates whether the USB module is in
FRAME mode. In FRAME mode, the FIFO uses its
internal frame pointer and information from the
peripheral to transfer only full frames of data, as defined
by the peripheral. Because the controller only keeps a
pointer to the end of the last complete frame, a read
request can contain more than one frame of data. The
MC9328MXS supports only FRAME = 1.
0 = Frame mode disabled
1 = Frame mode enabled
GR
Bits 26–24
Granularity—Defines the deassertion point for the
“high level” and “low level” service requests. See the
ALARM field of the Endpoint n FIFO Status for more
information.
000 = FIFO has 1 data byte or 1 free location
001 = FIFO has 2 data bytes or 2 free locations
010 = FIFO has 3 data bytes or 3 free locations
011 = FIFO has 4 data bytes or 4 free locations
100 = FIFO has 5 data bytes or 5 free locations
101 = FIFO has 6 data bytes or 6 free locations
110 = FIFO has 7 data bytes or 7 free locations
111 = FIFO has 8 data bytes or 8 free locations
A “high level” service request is deasserted when there
are less than GR data bytes remaining in the FIFO. A
“low level” service request is deasserted when there are
less than four times GR free bytes remaining in the
FIFO.
The direction, type, and packet size are defined in the
Endpoint n Status/Control.
Reserved
Bits 23–0
Reserved—These bits are reserved and should read 0.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
22-29
Programming Model
22.3.16 USB Endpoint n Last Read Frame Pointer Registers
The USB Endpoint n Last Read Frame Pointer registers hold the location of the most recently read frame or the
start of the frame currently in transmission.
The number of USB Endpoint n Last Read Frame Pointers in the MC9328MXS depends on the number of
endpoints configured.
USB_EP0_LRFP
USB_EP1_LRFP
USB_EP2_LRFP
USB_EP3_LRFP
USB_EP4_LRFP
USB_EP5_LRFP
Endpoint 0 Last Read Frame Pointer Register
Endpoint 1 Last Read Frame Pointer Register
Endpoint 2 Last Read Frame Pointer Register
Endpoint 3 Last Read Frame Pointer Register
Endpoint 4 Last Read Frame Pointer Register
Endpoint 5 Last Read Frame Pointer Register
Addr
0x00212048
0x00212078
0x002120A8
0x002120D8
0x00212108
0x00212138
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
LRFP
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 22-21. USB Endpoint n Last Read Frame Pointer Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
LRFP
Bits 5–0
Last Read Frame Pointer—Indicates the start of the most recently read frame or the start of the frame
currently in transmission. The LRFP can be read and written for debugging purposes. For the frame
retransmit function, the LRFP indicates the point to begin retransmission of the data frame. There are no
safeguards to prevent retransmitting data that was overwritten. When the FRAME bit is not set, this pointer
has no meaning.
MC9328MXS Reference Manual, Rev. 1.1
22-30
Freescale Semiconductor
Programming Model
22.3.17 USB Endpoint n Last Write Frame Pointer Registers
The USB Endpoint n Last Write Frame Pointer registers hold the location of the most recently written frame.
The number of USB Endpoint n Last Write Frame Pointers in the MC9328MXS depends on the number of
endpoints configured.
USB_EP0_LWFP
USB_EP1_LWFP
USB_EP2_LWFP
USB_EP3_LWFP
USB_EP4_LWFP
USB_EP5_LWFP
Endpoint 0 Last Write Frame Pointer Register
Endpoint 1 Last Write Frame Pointer Register
Endpoint 2 Last Write Frame Pointer Register
Endpoint 3 Last Write Frame Pointer Register
Endpoint 4 Last Write Frame Pointer Register
Endpoint 5 Last Write Frame Pointer Register
Addr
0x0021204C
0x0021207C
0x002120AC
0x002120DC
0x0021210C
0x0021213C
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
LWFP
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 22-22. USB Endpoint n Last Write Frame Pointer Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
LWFP
Bits 5–0
Last Write Frame Pointer—Indicates the start of the last frame written into the FIFO. The LWFP can be read
and written for debugging purposes. For the frame retransmit function, the LRFP indicates the point to begin
retransmission of the data frame. For the frame discard function, the LWFP divides the valid data region of the
FIFO (the area in-between the read and write pointers) into framed and unframed data. Data between the
LRFP and write pointer is an incomplete frame, while data between the read pointer and the LWFP is received
as whole frames. When the FRAME bit is not set, this pointer has no meaning.
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Programming Model
22.3.18 Endpoint n FIFO Alarm Registers
The Endpoint n FIFO Alarm registers define the high/low level alarm setting. The number of Endpoint n FIFO
Alarms in the MC9328MXS depends on the number of endpoints configured.
USB_EP0_FALRM
USB_EP1_FALRM
USB_EP2_FALRM
USB_EP3_FALRM
USB_EP4_FALRM
USB_EP5_FALRM
Addr
0x00212050
0x00212080
0x002120B0
0x002120E0
0x00212110
0x00212140
Endpoint 0 FIFO Alarm Register
Endpoint 1 FIFO Alarm Register
Endpoint 2 FIFO Alarm Register
Endpoint 3 FIFO Alarm Register
Endpoint 4 FIFO Alarm Register
Endpoint 5 FIFO Alarm Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
ALRM
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 22-23. Endpoint n FIFO Alarm Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
ALRM
Bits 5–0
Alarm Information—Provides the assertion point for the “high level” and “low
level” service requests. See the ALARM field of the Endpoint n FIFO Status for
more information.
A low level alarm reports lack of data while a high level alarm reports lack of
space. The integrator must decide which alarm is necessary for each
application.
Settings
0x00 = 1 data byte left or 1
free byte available
0x01 = 2 data bytes left or 2
free bytes available
...
0x3F = 64 data bytes left or
64 free bytes
available
When the amount of data or space in the FIFO is above the indicated amount,
the alarm sets in non-frame mode. In frame mode, the alarm sets when the
amount of data or space in the FIFO is above the amount indicated by the ALRM
setting or when there are end-of-frame bytes in the FIFO (see frame mode
operation).
A “high level” service request is asserted when there are less than ALRM bytes
free in the FIFO. A “low level” service request asserts when there are less than
ALRM bytes of data in the FIFO.
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Programming Model
22.3.19 Endpoint n FIFO Read Pointer Registers
The Endpoint n FIFO Read Pointer registers hold the location of the next FIFO location to read.
The number of Endpoint n FIFO Read Pointers in the MC9328MXS depends on the number of endpoints
configured.
USB_EP0_FRDP
USB_EP1_FRDP
USB_EP2_FRDP
USB_EP3_FRDP
USB_EP4_FRDP
USB_EP5_FRDP
Addr
0x00212054
0x00212084
0x002120B4
0x002120E4
0x00212114
0x00212144
Endpoint 0 FIFO Read Pointer Register
Endpoint 1 FIFO Read Pointer Register
Endpoint 2 FIFO Read Pointer Register
Endpoint 3 FIFO Read Pointer Register
Endpoint 4 FIFO Read Pointer Register
Endpoint 5 FIFO Read Pointer Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
RP
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 22-24. Endpoint n FIFO Read Pointer Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
RP
Bits 5–0
Read Pointer—Points to the next FIFO location to read. The physical address of this FIFO location is actually
the sum of the read pointer and the FIFO base, provided through a port to the FIFO controller. This base
address can vary, however if chosen properly, the FIFO RAM address can be concatenated with the read
pointer instead of requiring hardware for addition. The read pointer can be both read and written. This ability
facilitates the debugging of the FIFO controller and peripheral drivers. The current maximum size of the write
pointer is twelve bits, however it can be reduced through parameterization.
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Programmer’s Reference
22.3.20 Endpoint n FIFO Write Pointer Registers
The Endpoint n FIFO Write Pointer registers hold the location of the next FIFO location to write.
The number of Endpoint n FIFO Write Pointers in the MC9328MXS depends on the number of endpoints
configured.
USB_EP0_FWRP
USB_EP1_FWRP
USB_EP2_FWRP
USB_EP3_FWRP
USB_EP4_FWRP
USB_EP5_FWRP
Addr
0x00212058
0x00212088
0x002120B8
0x002120E8
0x00212118
0x00212148
Endpoint 0 FIFO Write Pointer Register
Endpoint 1 FIFO Write Pointer Register
Endpoint 2 FIFO Write Pointer Register
Endpoint 3 FIFO Write Pointer Register
Endpoint 4 FIFO Write Pointer Register
Endpoint 5 FIFO Write Pointer Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WP
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 22-25. Endpoint n FIFO Write Pointer Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
WP
Bits 5–0
Write Pointer—Points to the next FIFO location to write. The physical address of this FIFO location is actually
the sum of the read pointer and the FIFO base, provided through a port to the FIFO controller. This base
address can vary, however if chosen properly, the FIFO RAM address can be concatenated with the read
pointer instead of requiring hardware for addition. The read pointer can be both read and written. This ability
facilitates the debugging of the FIFO controller and peripheral drivers.
22.4 Programmer’s Reference
The programmer’s reference guide gives details on how to program the USB module. This section covers device
initialization, processing vendor requests, normal datapath operations, interrupt services, and reset operation.
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Device Initialization
22.5 Device Initialization
During device initialization, user software downloads critical configuration information to the UDC module and
prepares the USB module datapath for processing. This process is performed at two different times: at reset (hard
reset or software reset via RST bit in the USB_DDAR register) and when the device is first connected to the USB.
At power-up, the USB module contains no configuration information—such as, how many endpoints are available
or how to locate the descriptors. Device initialization consists of downloading this information to the appropriate
memories and to configure the datapath to match the intended application. The following steps are involved in the
initialization process:
1. Perform a hard reset or a software reset (by setting the RST bit in USB Enable-USB_ENAB).
2. Wait for the device to be properly reset (after writing to RST bit, wait for it to clear) before accessing
the device registers.
3. Wait for the CFG bit in the USB_DDAR register to assert before attempting to communicate with
the UDC. Setting the RST bit forces the ENAB bit to set automatically.
4. Download configuration data (ENDPTBUFs, see Table 22-26 on page 22-36) to the device’s USB
Descriptor RAM/Endpoint Buffer Data-USB_DDAT).
5. Program the USB Interrupt Mask (USB_MASK) to enable interrupts not associated with a
particular endpoint.
6. Program each Endpoint n Status/Control (USB_EPn_STAT) and Endpoint n Interrupt Mask
(USB_EPn_MASK) to support the intended data transfer modes.
7. Program endpoint type, direction, and maximum packet size in the USB_EPn_STAT register for
each endpoint.
8. Program the FIFO control registers. For each enabled endpoint, program frame mode, granularity,
alarm level, and so on (USB_EPn_FCTRL and USB_EPn_FALRM). Normally, all endpoints
should be programmed with FRAME mode enabled. To ensure proper operation of the DMA
request lines for frame mode endpoints, program the alarm level to a value equal to or a multiple of
the packet size of the endpoint.
9. Enable the USB for processing (set the USB_ENA bit in the USB Control, USB_CTRL).
NOTE:
Initialization of the USB module is a time critical process. The USB host waits
about 100ms after power-on or a connection event to begin enumerating devices on
the bus. This device must have all of the configuration information available when
the host requests it.
After the device is enumerated, the USB host selects a specific configuration and set of interfaces on the device.
Software on the device must beware of USB configuration changes to maintain proper communication with the
USB host. The software retains sole responsibility for always knowing the current configuration and alternate
interface. The CFG_CHG interrupt in the USB_INTR register reports changes in device configuration and
alternate interface settings to the software. The software is required to respond to the CFG_CHG interrupt. To
prevent the state of the device from becoming out of sync with respect to the host, the device halts further traffic on
the USB while this interrupt is pending.
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Device Initialization
22.5.1 Configuration Download
The configuration download process initializes 6 endpoint buffers (ENDPTBUF-see Table 22-26 on page 22-36)
within the UDC module to define its personality on the USB. The first ENDPTBUF is reserved for the default pipe
(Control Endpoint) and must contain the value 0x0000080000. Endpoint buffers 1–5 can have a maximum of two
configurations. Because endpoint buffers 1–5 can have up to two configurations, both configurations are
downloaded to the device. A total of 55 bytes will transfer because endpoint buffer 0 is restricted to one
configuration.
The endpoint buffers are 40-bit data strings per physical endpoint (pipe) that are loaded directly into the UDC
module. They associate “logical” endpoint numbers in the USB software stack with hardware within the UDC.
Specifically, they attach each endpoint to a USB configuration, interface, and alternate setting, and they specify
transfer type, packet size, data direction, and hardware FIFO numbers.
Table 22-26. ENDPTBUF—UDC Endpoint Buffers Format
Bit/Field
Type
Description
[39:36]
EPNUM
Logical Endpoint Number
[35:34]
CONFIG
Configuration Number (maximum of 2 configurations: 1 and 2)
[33:32]
INTERFACE
Interface Number (maximum of 4 interfaces)
[31:29]
ALTSETTING
Alternate Setting Number (maximum of 8 alternate settings)
[28:27]
TYPE
[26]
DIR
Type of Endpoint:
00 = Control
01 = Isochronous
10 = Bulk
11 = Interrupt
Direction of the Endpoint:
0 = OUT endpoint
1 = IN endpoint
[25:16]
MAXPKTSIZE
Maximum packet size for the endpoint
0x08 = 8 bytes
0x10 = 16 bytes
0x20 = 32 bytes
0x40 = 64 bytes
[15:14]
TRXTYP
These bits must be set to 00 for endpoint 0, and 11 for all other endpoints.
[13:3]
Reserved
Reserved
[2:0]
FIFONUM
This field maps the endpoint to one of the <<BLOCK NAME>> module’s hardware FIFOs.
Multiple UDC endpoints can map to a single hardware FIFO. It is up to the software to monitor
and control any data hazards related to this type of operation in this way:
The hardware FIFOs that are available are:
FIFO0 (32 bytes)
FIFO1 (64 bytes)
FIFO2 (64 bytes)
FIFO3 (32 bytes)
FIFO4 (32 bytes)
FIFO5 (32 bytes)
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Device Initialization
To download the configuration data, perform the following steps:
1. Verify that the CFG bit (in the USB_DADR register) is set. This ensures that the UDC is fully reset
and is ready to take data.
2. Write the endpoint buffers (EnfPtBufs) to the USB_DDAT register. (the first byte written is
EPn[39:32] and the last byte written is EPn[7:0]). After writing each byte, and before performing
any other operation on the peripheral, verify that the BSY bit (in the USB_DADR register) is clear.
3. After writing all endpoint buffer configuration bytes, check the CFG bit of the USB_DADR to
verify that the configuration download is complete. CFG changes from 1 to 0 after the last byte is
loaded into the UDC.
22.5.1.1 USB Endpoint to FIFO Mapping
The USB protocol recognizes a maximum of 31 endpoints on a USB device. The endpoint numbers available on a
specific USB device are based on the functionality present in the device, and on the configuration and alternate
interfaces currently selected. Regardless of the logical endpoint number programmed in the interface descriptors,
some hardware must be associated with each endpoint.
The USB module supports a maximum of 6 endpoints, including endpoint 0. Each hardware endpoint consists of a
single FIFO that is independently programmable for direction, transfer type, frame mode, and low/high alarms. To
fit these hardware endpoints to the USB’s logical endpoints, mapping is established in the UDC module’s endpoint
buffer (EndPtBufs). Endpoint FIFO 0 is reserved for the default pipe (Control Endpoint).
Endpoint type, direction and packet size are defined in the USB_EPn_STAT register for each endpoint. FIFO
characteristics are programmed in the USB_EPn_FCTRL and USB_EPn_FALRM registers. At power-up, the USB
endpoints are mapped to specific hardware FIFOs when the UDC endpoint buffers are downloaded to the device
from the CPU. The endpoint buffer makes 16 bits available to identify each hardware endpoint. These bits are the
UDC_BufAdrPtr field [15:0] in the USB_SPEC register (see Table 22-26). Depending on the transaction selected
by the UDC, this bus includes the indicator for a setup packet, or endpoint specific encoding. The UDC_BufAdrPtr
[15:0] fields defined for the USB module are shown in Table 22-26 -EndPtBuf[15:0].
22.5.1.2 USB Interrupt
If the application uses the interrupt registers, the specific interrupts must be enabled. During reset, all interrupts
revert to the masked state. USB global interrupts (interrupts that affect the whole module) are programmed
separately from those affecting a single endpoint.
22.5.1.3 Endpoint Registers
The characteristics of the FIFO and a number of interrupt sources can be programmed for each endpoint. The
integrator must program the following registers:
•
USB Endpoint Interrupt Mask (USB_EPn_MASK)
Separate interrupt registers are provided for each hardware FIFO. Enable the interrupts pertaining to the
application by writing 0 to the mask bit for that interrupt.
•
Endpoint FIFO Controller Configuration (USB_EPn_FCTRL).
Each FIFOs programming is based on the type of data transmission used by the endpoint. Normally, all
endpoints are programmed with FRAME mode.
•
FIFO Alarm Register (USB_EPn_FALRM).
For bulk traffic (FRAME = 1), the alarm level is normally programmed to a multiple of the USB packet size
(for 8 byte packets and a 16 byte FIFO, the alarm is programmed to 8 bytes) to allow the DMA request lines
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Exception Handling
to request full packets. For single buffered endpoints (packet size = 8, FIFO depth = 8 bytes), the alarm is
normally programmed to 0. For isochronous traffic, the alarm is programmed to allow streaming operation
to occur on the isochronous endpoint.
22.5.1.4 Enable the Device
The last step in initializing the USB module is to enable it for processing in the USB_CTRL register. Most
applications set the USB_SPD bit, the AFE_ENA bit and the USB_ENA bit in the USB_CTRL register.
NOTE:
The USB_SPD bit must be set at 1 (high speed mode, default). The USB device
does not support low speed.
22.6 Exception Handling
Exception handling occurs in two situations:
•
When corrupted frames must be discarded
•
When an error occurs on the USB
The hardware automatically discards corrupted frames, so no software intervention is required.
If the device cannot respond to the host in the time allotted, the hardware automatically handles retries. No
software intervention is required.
There are four error situations that must be dealt with by the software:
•
Unable to Complete Device Request
•
Aborted Device Request
•
Unable to Fill or Empty FIFO Due to Temporary Problem
•
Catastrophic Error.
Explanations for each of the errors are described in the following sections.
22.6.1 Unable to Complete Device Request
In the event that the software receives a device request it cannot interpret, it asserts the CMD_ERROR and
CMD_OVER bits (in the USB_CTRL register) to the UDC. This results in a STALL to the endpoint in question
and requires intervention from the USB host to clear. When the CMD_OVER bit clears, it means that the USB host
has cleared the stall condition.
22.6.2 Aborted Device Request
When the host sends a setup packet to the device, the ACK handshake from the device can become corrupted and
lost on its way to the host. If this happens, the host retries the setup packet, and the device can wind up with two or
more setup packets in its FIFO. There are two ways to detect this condition:
•
The presence of a MDEVREQ interrupt (in the USB_EPn_INTR register)
•
The SIP bit in the Endpoint n Status/Control (USB_EPn_STAT) is active
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Data Transfer Operations
In either case, the presence of more than one setup packet invalidates the first one in the FIFO. When MDEVREQ
is active, software must discard the first one, and process the second one. When SIP is active, software must
discard the first one, clear the device request, and wait for it to reassert.
22.6.3 Unable to Fill or Empty FIFO Due to Temporary Problem
When the USB module is unable to fill or empty a FIFO due to a temporary problem (such as the OS did not
service the FIFO in time and it overflowed), the software stalls the endpoint through the FORCE_STALL bit in the
USB_EPn_STAT register. This aborts the transfer in progress and forces intervention from the USB host to clear
the stall condition. The FORCE_STALL register bit automatically clears after the stall takes effect. The application
software on the host must deal with the stall condition and notify the device on how to proceed.
22.6.4 Catastrophic Error
In the case of a catastrophic error, the software executes a hard reset, re-initializes the USB module, and waits for
the USB host to re-enumerate the bus.
22.7 Data Transfer Operations
Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous transfers
and interrupt transfer. From the perspective of the USB module, the interrupt transfer type is identical to the bulk
data transfer mode, and no additional hardware is supplied to support it. This section covers the transfer modes and
how they work.
Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same packet
transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved in the form of
packets, however, because isochronous pipes are given a fixed portion of the USB bandwidth at all times, there is
no end-of-transfer (EOT).
22.7.1 USB Packets
Packets range in size from 0 to 1023 bytes, depending on the transfer mode. For bulk, control, and interrupt traffic,
packet sizes are limited to 8-, 16-, 32-, or 64-bytes. Isochronous packets can range from 0 bytes to 1023 bytes. The
packet size is programmed within the UDC module on an endpoint by endpoint basis. For DMA access, the
maximum packet size for isochronous endpoints is restricted by the endpoint’s FIFO size.
The terms packet and frame are used interchangeably within this document. While USB traffic occurs in units
called packets, the FIFO mechanism uses the term frames for the same blocks of data. The only difference between
frames and packets from the user’s standpoint is that packets can be as little as zero bytes in length, while a frame
must be at least one byte in length.
22.7.1.1 Short Packets
Each endpoint has a maximum packet size associated with it. The packet size is set with the MAX field in the
Endpoint n Status/Control. In most cases, packets transferred across an endpoint are sent at the maximum size.
Because the USB does not indicate a data transfer size, or include an end-of-transfer token, short packets are used
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Data Transfer Operations
to mark the end of data. Software writes short packets into the FIFO to indicate the end of data. Incoming short
packets are identified by examining the length of a received packet or by looking at the end-of-transfer and
end-of-frame interrupts.
22.7.1.2 Sending Packets
To send a packet of data to the USB host using programmed I/O, use these steps:
1. For an N byte packet, write the first N-1 bytes to the Endpoint n FIFO Data (USB_EPn_FDAT). Data
can be written as bytes, words, or longwords.
2. For the Nth byte, set the WFR bit in the USB_EPn_FCTRL register before writing the last data byte
to the USB_EPn_FDAT register. Data is written in big-endian format. The most significant byte
(byte 3) is held in bits 7 through 0.
When using the DMA controller for a memory I/O transfer to send packets, the sequence is as follows:
1. Program the DMA controller to write data to the endpoint FIFO and enable the DMA channel for the
USB endpoint DMA.
2. When the FIFO byte count has dropped below the alarm level, a DMA request is generated. The
DMA writes data to the FIFO until the DMA request deasserts.
3. For an N byte packet, the first N-1 bytes are written to the FIFO data register (USB_EPn_FDAT)
as bytes, words, or long words.
4. On the Nth byte, to signal the end of a frame, the DMA controller signals to the USB that it is writing
the final byte of the USB_EPn_FDAT register. The last byte in the transfer gets the end-of-frame
tag (bits 31–24 for byte, bits 23–16 for word, and bits 7–0 for longword).
In a double-buffered system, the FIFO depth is twice the size of the USB packet size. Program the FIFO alarm
level to be the same as a single packet. This causes the DMA request to assert whenever there is the equivalent to
one packet of data or less in the FIFO. The system can write data until the DMA request deasserts, as long as the
last byte of each USB packet is tagged as the end-of-frame.
22.7.1.3 Receiving Packets
Perform the following steps to receive a packet of data from the USB host using programmed I/O.
1. Monitor the EOF interrupt for the endpoint.
2. On receiving the EOF interrupt, prepare to read a complete packet of data. Clear the EOF interrupt
so that software receives notification of the next frame.
3. Read the USB_EPn_FDAT register for the next piece of data.
4. Read the USB_EPn_FSTAT register to get the end-of-frame status bits (see note below). When the
end-of-frame bit is set for the current transfer, stop reading data.
5. Go to step 3.
NOTE:
When reading end-of-frame indicators from USB_EPn_FSTAT, the
USB_EPn_FSTAT (FRAME [3:0]) field contains valid frame byte lanes used on
the bus (31:24, 23:16, 15:8, 7:0). Currently, more than one bit can be set when there
are multiple end-of-frame bytes on word or longword transfers. Extra software
might be required to determine the first valid end-of-frame maker. The value of this
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Data Transfer Operations
field is computed directly from the frame boundary bits stored in the RAM. The
user must ensure that the RAM data is valid when accessing these bits. For
example, when there are only two bytes of data marked EOF in the RAM, and the
user does a longword access, bits 1:0 of this field are undefined.
22.7.1.4 Programming the FIFO Controller
The FIFO controller has two modes of operation, Frame and Non-Frame. Only Frame mode is normally used for
the USB application.
In Frame mode, the FIFO controller can handle automatic hardware retry of bad packets. During device
initialization, the user configures the FIFOs through the USB_EPn_FCTRL register for FRAME mode. Data flow
is controlled with the end-of-frame and end-of-transfer interrupts, or with the DMA request lines. For isochronous
endpoints, no data retries are performed.
22.7.2 USB Transfers
Data transfers on the USB are composed of one or more packets. Instead of maintaining a transfer count, the USB
host and device send groups of packets to each other in units called transfers. In a transfer, all packets are the same
size, except the last one. The last packet in a transfer is a short packet, as small as 0 bytes (when the last data byte
ends on a packet boundary).
This section describes how data transfers work from both the device to the host, and from the host to the device.
22.7.2.1 Data Transfers to the Host
The user starts by determining the number of packets in the data block, based on the maximum packet size of the
target endpoint.
When the number of packets is an integer, the transfer ends on a packet boundary. A zero length packet is required
to terminate the transfer. When the number of packets is not an integer, the last packet of the transfer is a short
packet and no zero length packet is required.
For each packet in the transfer, write the data to the USB_EPn_FDAT register. The last byte in each packet must be
tagged with the end-of-frame marker through the USB_EPn_FCTRL register (WFR bit) or DMA service request
lines. Monitor the FIFO_LOW interrupt, EOF interrupt, or DMA service requests to determine when the FIFO can
accept another packet.
When a zero length packet is required to terminate the transfer after the last byte is written to the FIFO, set the
ZLPS bit in the USB_EPn_STAT register for the endpoint.
Wait for the EOT interrupt to determine when the transfer is complete.
NOTE:
For DMA operation, a zero length frame is not defined so it is necessary to have
the user software monitor the EOT interrupts and use them as a basis for
delineating individual transfers. USB traffic flow is halted until the EOT interrupt
is serviced to ensure that data from different data transfers does not get mixed-up
in the FIFOs.
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Data Transfer Operations
22.7.2.2 Data Transfers to the Device
The length of data transfer from the host is generally not known in advance. The device receives a continuous
stream of packets and uses the EOT interrupt to determine when the transfer ended.
Software on the device monitors the EOF interrupt and/or the DMA transfer requests to manage packet traffic.
Each time a packet is received, the device must pull the data from the FIFO. When an end-of-frame is transferred
from the UDC module into the data FIFO, the EOF interrupt asserts. At the end of a complete transfer, the EOT
interrupt asserts. For a bulk endpoint, until the CPU has serviced the EOT interrupt, the device Negative
Acknowledges (NAKs) any further requests to that endpoint from the host. This guarantees that data from two
different transfers never get intermixed within the FIFO.
22.7.3 Control Transfers
The USB host sends commands to the device through control transfers. Control transfers can be addressed to any
control endpoint. Control transfers consist of three distinct phases: beginning with a setup phase, followed by an
optional data phase, and ending with a status phase. Command processing occurs in the following steps:
1. Receive the SETUP packet on a control endpoint. DEVREQ and EOF interrupts assert for that
endpoint.
2. Read 8 bytes of the setup packet from the appropriate FIFO data register and decode the command.
3. Clear EOF and DEVREQ interrupts.
4. Set up and perform the data transfer when a data transfer is implied by the command. Do not send
more bytes to the USB host than were requested in the wLength field of the SETUP packet.
Hardware does not check for incorrect data phase length. The EOT interrupt asserts on completion
of the data phase.
5. Assert the CMD_OVER and CMD_ERROR bits (in the USB_CTRL register) to indicate
processing or error status. The UDC module generates appropriate handshakes on the USB to
implement the status phase. CMD_OVER automatically clears at the end of the status phase.
6. Wait for CMD_OVER to clear, indicating that the device request has completed.
The USB module assumes that the UDC module handles most of the standard requests without software
intervention. User software does not need to be concerned with handling any of the so-called “Chapter 9" requests
listed in the USB specification, except for SYNCH_FRAME, GET_DESCRIPTOR and SET_DESCRIPTOR. The
requests are passed through endpoint 0 as a device request and must be processed by the device driver software.
22.7.4 Bulk Traffic
Bulk traffic guarantees the error-free delivery of data in the order that it was sent, however the rate of transfer is not
guaranteed. Bandwidth is allocated to bulk, interrupt, and control packets based on the bandwidth usage policy of
the USB host.
22.7.4.1 Bulk OUT
For OUT transfers (from host to device), internal logic marks the start of packet location in the FIFO. When a
transfer does not complete without errors, the logic forces the FIFO to return to the start of the current packet and
try again. No software intervention is required to handle packet retries.
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Data Transfer Operations
User software reads packets from the FIFOs as they appear and stops reading when an EOT interrupt is received.
To enable further data transfers, software services and clears the pending interrupts (EOF or EOT) and waits for the
next transfer to begin. For Bulk Out endpoint, until the CPU has serviced the EOT interrupt, the device NAKs any
further requests to that endpoint from the host. This guarantees that data from two different transfers never get
intermixed within the FIFO.
22.7.4.2 Bulk IN
For IN transfers (from device to host), software tags the last byte in a packet to mark the end-of-frame. When a
transfer does not complete without errors, the hardware automatically forces the FIFO to return to the start of the
current packet and re-send the data. User software is expected to write data to the FIFO data register in units of the
associated endpoint’s maximum packet size. The end-of-frame can be indicated through the WFR bit in the
Endpoint n FIFO Control (USB_EPn_FCTRL) or via the end-of-frame tag signal from the DMA controller.
In the USB protocol, the last packet in a transfer is allowed to be short (smaller than endpoint’s maximum packet
size) or even zero length. To indicate a zero length packet, the software sets the ZLPS bit in the associated
Endpoint n Status/Control. The ZLPS bit automatically clears after the zero length packet is successfully sent to the
host.
The EOT interrupt asserts to indicate that the last packet of the IN transfer has completed. Software clears any
pending interrupts (EOT and EOF) to begin the next data transfer.
22.7.5 Interrupt Traffic
Interrupt endpoints are a special case of bulk traffic. Interrupt endpoints are serviced on a periodic basis by the
USB host. Interrupt endpoints are guaranteed to transfer one packet per polling interval. Therefore, an endpoint
with an 8 byte packet size and serviced every 2 ms would move 16 Kb/sec across the USB.
The only difference between interrupt transfers and bulk transfers from the device standpoint is that every time an
interrupt packet is transferred, regardless of size, the EOT interrupt asserts. The device driver software must
service this interrupt packet before the next interrupt servicing interval to prevent the device from NAKing the poll.
Device driver software must ensure that the interrupt endpoint polling interval is longer than the device’s interrupt
service latency.
22.7.6 Isochronous Operations
Isochronous operations are a special case of USB traffic. Instead of guaranteeing delivery with unbounded latency,
isochronous traffic flows over the bus at a guaranteed rate with no error checking.
22.7.6.1 Isochronous Transfers in a Nutshell
The USB host guarantees an endpoint exactly one isochronous packet per frame. Isochronous packets can range
from 0 bytes to 1023 bytes. See the USB specification for more information on isochronous transfer.
Because isochronous packets can be as large as 1023 bytes, it is not practical to implement large FIFOs for each
endpoint. Instead, the software drivers are responsible for keeping the FIFOs serviced. When an IN or OUT request
is received on an isochronous endpoint, the software drivers must ensure that the correct amount of data can be
transferred without emptying the FIFO. When the FIFO empties during an isochronous packet transfer, the host
terminates the packet immediately and the device loses its time slot until the next USB frame.
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Interrupt Services
For DMA access, the maximum packet size for isochronous endpoints is restricted by the endpoint’s FIFO size. For
programmed I/O, isochronous data packets can take any size from 0 to 1023 bytes.
To allow the driver software to maintain synchronization with the USB host, the <<BLOCK NAME>> maintains a
register that holds the current USB frame number. An interrupt is asserted each time the frame number changes or
when a specific USB frame number is received. The interrupts are maskable.
The EOT interrupt asserts for isochronous packet transfers when the UDC module reports that the packet data is
error free. This can be used along with the EOF interrupt to determine when a transfer error of some sort occurs on
an isochronous endpoint.
22.7.6.2 The SYNCH_FRAME Standard Request
The SYNCH_FRAME standard request allows synchronization between the USB host and device during
isochronous operations. The command is passed through endpoint 0 as a device request and must be processed by
the device driver software.
22.8 Interrupt Services
The USB module generates a number of interrupts to indicate situations requiring attention from the host. The
types of interrupts are broken into two categories: USB general interrupts and Endpoint specific interrupts. These
interrupts are discussed in this section, as well as missed interrupts and their behaviors.
22.8.1 USB General Interrupts
The USB general interrupts indicate such things as global configuration and status changes pertaining to the USB.
All of these interrupts are maskable. When an event causes an interrupt condition to occur, and the corresponding
bit in the interrupt mask register is zero, an interrupt signal asserts on the module’s interface. Writing 1 to the
associated bit in the interrupt register clears the interrupt. After a hard reset, all interrupts are masked by default.
This section describes each of the USB General Interrupts.
22.8.1.1 MSOF—Missed Start-of-Frame
The MSOF interrupt is used to inform software that it did not service the SOF interrupt before another SOF
interrupt was received.
22.8.1.2 SOF—Start-of-Frame
The SOF interrupt means that a start-of-frame token was received by the device. The current USB frame number
can be read from the USB_FRAME register. The start-of-frame interrupt is usually used by isochronous devices to
provide a stable timebase.
22.8.1.3 RESET_STOP—End of USB Reset Signaling
The RESET_STOP interrupt means that reset signaling on the USB has stopped.
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Interrupt Services
22.8.1.4 RESET_START—Start of USB Reset Signaling
The RESET_START interrupt indicates that reset signaling on the USB has begun. When reset signaling is active
on the USB, the device does not expect to receive any transactions on the bus. This interrupt results in a reset of the
UDC into the powered state, however it does not cause any specific actions in the <<BLOCK NAME>> front-end
logic. User software must clear any pending interrupts and ensure that the module is configured properly after the
reset. This interrupt indicates the start of reset signaling. Status of the USB at any given moment can be verified by
examining the USB_STAT register.
Presence of USB reset signaling invalidates any transaction in progress. On detection of RESET_START, user
software reads any remaining valid data from the receive FIFOs and flushes all others. When reset signaling is
detected, user software must clear any pending interrupts and ensure that the module is configured properly after
the reset.
22.8.1.5 WAKEUP—Resume (Wakeup) Signaling Detected
This interrupt asserts when resume signaling is detected on the USB. The device uses this interrupt to wake up
from suspend mode and resume normal operations. This interrupt is independent of the clock to the USB module.
22.8.1.6 SUSP—USB Suspended
This interrupt asserts when the USB goes into suspend mode. Suspend mode occurs when the device fails to
receive any traffic from the USB for a period of 6 ms. When suspend mode is detected, the device puts itself into a
low power standby mode.
22.8.1.7 FRAME_MATCH—Match Detected in USB_FRAME Register
This interrupt asserts when the frame number programmed into the MATCH field of the USB_FRAME register is
the same as the FRAME field of the USB_FRAME register. Isochronous pipes can use this interrupt for
synchronization between the data source and sink.
22.8.1.8 CFG_CHG—Host Changed USB Device Configuration
This interrupt means that the USB host selected a different configuration or alternate interface. Software reads the
USB_STAT register to determine the current configuration and interfaces and reconfigures itself accordingly.
22.8.2 Endpoint Interrupts
The endpoint interrupts indicate requests for service by specific USB endpoints. All bits are maskable. Each
endpoint’s interrupt output is connected to a separate hardware interrupt line. When an event occurs that causes an
interrupt condition to occur, and the corresponding bit in the interrupt mask register is zero, an interrupt signal
asserts on the module’s interface. Writing 1 to the associated bit in the interrupt register clears the interrupt.
22.8.2.1 FIFO_FULL
This interrupt asserts when the FIFO is full.
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Interrupt Services
22.8.2.2 FIFO_EMPTY
This interrupt asserts when the FIFO is empty.
22.8.2.3 FIFO_ERROR
This interrupt means some abnormal condition occurred in the FIFO. The cause of the error can be verified by
reading the USB_EPn_FSTAT register associated with the FIFO that had the error.
22.8.2.4 FIFO_HIGH
Each FIFO has an alarm register. The FIFO_HIGH interrupt asserts when the number of free bytes in the FIFO is
below the level specified by the alarm register.
22.8.2.5 FIFO_LOW
Each FIFO has an alarm register. The FIFO_LOW interrupt asserts when the byte count in the FIFO is below the
level specified by the alarm register.
22.8.2.6 EOT—End of Transfer
This interrupt asserts after the last data byte of a USB transfer crosses from the <<BLOCK NAME>> into the UDC
module or vice versa. The end of a USB transfer is indicated by either a zero byte packet or by a data packet shorter
than the maximum packet size for the endpoint.
The EOT never asserts along with the DEVREQ interrupt for setup packets.The EOT interrupt asserts after every
interrupt packet transfer, every complete bulk data transfer and data phase of control transfer. The EOT interrupt
generally asserts along with an EOF interrupt, although an EOT interrupt can occur without an EOF interrupt when
a transfer terminates on a USB packet boundary. The EOT interrupt asserts for isochronous packet transfers when
the UDC module reports that the packet data is error free. This can be used along with the EOF interrupt to
determine when a transfer error of some sort occurs on an isochronous endpoint.
22.8.2.7 DEVREQ—Device Request
The Device Request (Setup Packet) interrupt means that the most recently received packet was a setup or device
request packet. Software on the USB device must decode and respond to the packet to complete a Vendor, Class, or
Standard request.
22.8.2.8 MDEVREQ—Multiple Device Request
The Multiple Device Requests indicator asserts when two or more setup packets have been received before the
DEVREQ interrupt was cleared. This interrupt is used to determine when the USB host has aborted a transfer in
progress. In this case, the device receives a setup packet, followed by a new setup packet before it has completed
processing of the original command.
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Reset Operation
22.8.2.9 EOF—End of Frame
This interrupt means that an end-of-frame marker was sent or received on the FIFO/UDC interface. This interrupt
asserts when a DEVREQ is received for bulk, control, isochronous, and interrupt data. While packet retries are not
supported for isochronous endpoints, the end-of-frame indicator is still valid and can be used along with the SOF
interrupt to control data flow.
22.8.3 Interrupts, Missed Interrupts, and the USB
Improper operation of the device can result when interrupts are not serviced in a timely manner. For example, a
CFG_CHG interrupt is received, the device does not service it, and another CFG_CHG interrupt is received. This
could leave the device in an incorrect operating mode. The interrupts of concern in this manner are SOF,
CFG_CHG, EOT, and DEVREQ. The missed-interrupt behaviors are discussed in the following subsections.
22.8.3.1 SOF
When the device misses a start-of-frame interrupt, the MSOF bit asserts in the USB_INTR register.
22.8.3.2 CFG_CHG
When the device receives a CFG_CHG interrupt, the module NAKs all traffic from the USB host until software
clears the interrupt bit. This prevents the device configuration from getting out of sync with what the host has
requested.
22.8.3.3 EOT
When an end-of-transfer is received on a BULK OUT endpoint, the device NAKs all traffic on that endpoint until
software clears the interrupt bit. This prevents data from two different transfers from becoming mixed up in a
FIFO.
22.8.3.4 DEVREQ
When a device request is received, the device NAKs all IN/OUT traffic on the affected endpoint until software
clears the interrupt bit. This ensures that the device correctly identifies the setup packet in the FIFO and can clear
the FIFO before the data phase is allowed to begin. When multiple setup packets are received, the MDEVREQ
interrupt asserts.
22.9 Reset Operation
The USB module includes four reset modes: Hard Reset, Software Reset, UDC reset and USB Reset signaling.
The UDC reset allows software to force a hard reset of the UDC module only, leaving all register bits in the
front-end logic intact. A UDC reset is normally used only as a debug option, however it can also be used in the
event of a connect/disconnect bus event. A hard reset requires that MCU PLL and System PLL be locked.
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Reset Operation
22.9.1 Hard Reset
A hard reset is generated from the USB module’s bus interface, and resets all storage elements in both the front-end
logic and in the UDC module. A hard reset also issues a UDC reset. Both the MCU PLL and System PLL must be
locked before issuing a Software Reset.
22.9.2 USB Software Reset
The USB device allows the reset of all the storage elements in both the front-end logic and in the UDC module
through the RST bit in the USB_ENAB register. On initial power-up, the user issues a Software reset. This causes
the module to be enabled and the internal logic to be reset. Both the MCU PLL and USB PLL must be locked
before issuing a Software Reset.
22.9.3 UDC Reset
A UDC reset is accomplished by setting the UDC_RST bit in the USB Control (USB_CTRL.) The UDC must be
reset any time a connect/disconnect occurs on the USB. Any time the device is plugged in or unplugged from the
USB, software must initiate either a hard reset or a UDC reset to ensure that the module can properly communicate
with the USB host. Reset signaling is discussed in chapter 7 of the USB Specification. UDC Reset can invalidate
data remaining in the data FIFOs. Depending on the application, software might need to flush the data FIFOs
before proceeding.
22.9.4 USB Reset Signaling
Reset signaling can occur on the USB for a number of reasons. When the device receives reset signaling, it means
that the host is preparing to re-enumerate the bus. All transactions in progress must be invalidated, and the device
software prepared to receive configuration changes.
Because the device can contain valid, but as-yet unread, data in the FIFOs when USB reset signaling occurs, the
hardware does not flush the FIFOs. When device software receives reset signaling, it completes reading any unread
data from the FIFOs and execute FIFO flush operations on all of the FIFOs. This guarantees that the datapath is
empty and ready for new data transfer operations when reset signaling and re-enumeration are complete.
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Chapter 23
I2C Module
23.1 Overview
I2C is a two-wire bidirectional serial bus that provides a simple and efficient method of data exchange while
minimizing the interconnection between devices. This bus is most suitable for applications requiring occasional
communication between many devices in close proximity. The flexible I2C bus allows additional devices to be
connected to the bus for expansion and system development.
The I2C system is a true multiple-master bus. It features collision and arbitration detection to prevent data
corruption when multiple devices attempt to control the bus simultaneously. This allows for complex applications
with multiprocessor control and can support rapid testing and alignment of end products through external
connections to an assembly-line computer.
23.2 Interface Features
The following are key features of the I2C module:
•
Compatible with the I2C bus standard
•
Supports 3.3V tolerant devices
•
Multiple-master operation
•
Software programmable clock frequencies (supports 64 different frequencies)
•
Software selectable acknowledge bit
•
Interrupt driven, byte-by-byte data transfer
•
Arbitration lost interrupt with automatic switching from master to slave mode
•
Calling address identification interrupt
•
START and STOP signal generation and detection
•
Repeated START signal generation
•
Acknowledge bit generation and detection
•
Bus-busy detection
Figure 23-1 on page 23-2 shows a block diagram of the I2C module.
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23-1
I2C System Configuration
Internal Bus
IRQ
Address
Data
Registers and MC9328MXS Interface
Address Decode
I2C Frequency
Divider Register
(IFDR)
I2C Control
Register
(I2CR)
I2C Status
Register
(I2SR)
Clock
Control
Input
Sync
I2C Data
I/O Register
(I2DR)
Data MUX
I2C Address
Register
(IADR)
In/Out
Data
Shift
Register
START, STOP,
and
Arbitration
Control
Address
Compare
Serial
Clock
Line
(SCL)
Serial
Data
Line
(SDA)
Figure 23-1. I2C Module Block Diagram
23.3 I2C System Configuration
The I2C module uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. For I2C compliance, all
devices connected to these two signals must have open drain or open collector outputs. (There is no such
requirement for inputs.) The logic AND function is exercised on both lines with external pull-up resistors.
The default state of the I2C is slave receiver. When not programmed to be a master or responding to a slave
transmit address, the I2C module always returns to the default state. Exceptions are described in Section 23.7.1,
“Initialization Sequence.”
NOTE:
The I2C module is designed to be compatible with The I2C Bus Specification,
Version 2.1 (Philips Semiconductor: 2000). For detailed information on system
configuration, protocol, and restrictions, see the Philips I2C standard.
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I2C Protocol
23.4 I2C Protocol
The I2C communication protocol consists of six components: START, Data Source/Recipient, Data Direction,
Slave Acknowledge, Data, Data Acknowledge and STOP. These are shown in Figure 23-2 and described in the text
following the figure.
SCL
MSB
1
LSB
2
3
4
5
6
7
8
MSB
9
LSB
1
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
9
SDA
AD7
START
Signal
AD6 AD5 AD4 AD3 AD2 AD1 R/W
Calling Address
B
A
XXX
R/W ACK
Bit
C
D
Data Byte
E
ACK STOP
/no ACK Signal
F
G
Figure 23-2. I2C Standard Communication Protocol
•
START (A)—When the bus is free (both the SCL and the SDA lines are at logic high), a device can initiate
communication by sending a START signal. This is defined as a high-to-low transition of SDA while SCL
is high. This signal denotes the beginning of a data transfer and awakens all the slave devices on the bus.
•
Data Source/Recipient (B)—The master sends out the 7-bit address of the slave that it intends to transfer
data to or receive data from. Each slave must have a unique address. An I2C master cannot transmit to its
own slave address—a device cannot be master and slave at the same time.
•
Data Direction (C)—This single bit sets the data transfer direction.
•
Acknowledge (D)—The addressed slave device responds to the master by returning an acknowledge bit.
This is defined as the SDA line pulled low on the ninth clock after the START signal. This acknowledge is
independent of the values of the Acknowledge Enable bit in the Control Register.
•
Data (E)—The data transfer is done on a byte-by-byte basis in the direction specified by the Data Direction
bit. Data can be changed only while the SCL is low and must be held stable while the SCL is high. The SCL
is pulsed once for each data bit and the most significant bit (MSB) is sent first.
•
Acknowledge (F)—The receiving device must acknowledge each byte by pulling the SDA low on the ninth
clock, so a data byte transfer takes nine clock pulses. For multi-byte data transactions, an end-of-data
condition is indicated when the receiver does not send an acknowledge.
When the master transmits data to the slave and the slave does not acknowledge the master, this indicates
an end-of-data condition to the master. The SDA line is left high and the master can generate a STOP signal
to abort the data transfer or generate a START signal (repeated START, shown in Figure 23-3 on page 23-4)
to restart the transfer.
When the master receives data from the slave and the master does not acknowledge the slave, this indicates
an end-of-data condition to the slave. The slave releases the SDA and the master generates a STOP or
START signal.
•
STOP (G)—A STOP signal is sent to free the bus after data is transmitted or when the master stops
communication. A STOP signal is defined as a low-to-high transition of the SDA while the SCL is at logical
high.
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I2C Protocol
NOTE:
A master can generate a STOP even when the slave sent an acknowledge. The slave
must release the bus.
•
Repeated START (H)—Instead of sending a STOP signal, the master can repeat the START signal and the
rest of the communication protocol. When a START signal is generated without a preceding STOP signal,
a repeated START occurs. This is shown in Figure 23-3. The master generates a repeated START to
communicate with another slave or with the same slave in a different mode (transmit/receive mode) without
releasing the bus.
SCL
MSB
1
LSB
2
3
4
5
6
7
8
MSB
9
1
LSB
2
3
4
5
6
7
8
9
SDA
AD7
AD6 AD5 AD4 AD3 AD2 AD1 R/W
XX
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Calling Address
START
Signal
New Calling Address
No STOP
ACK Signal
Bit
R/W ACK Repeated
START
Bit
Signal H
Figure 23-3. Repeated START
23.4.1 Clock Synchronization
When multiple devices simultaneously request the bus, the bus clock is determined by a synchronization procedure
in which the clock lines from the individual devices are compared. The system clock line (SCL) is the result of an
AND operation on all individual clock lines.
After the master drives the SCL low, the internal clocks begin counting their low periods. By performing an AND
operation, the system clock stays low until ALL of the individual device clocks on the bus have transitioned to the
high state. At this point, the individual clocks begin counting their high periods. The system clock remains high
until ANY of the device clocks on the bus transition to the low state.
As a result, the devices with the longest low periods and shortest high periods control the SCL.
Devices with shorter low periods transition to high before the SCL transitions. This wait is shown in Figure 23-4.
Wait
Begin Counting High Period
SCL1
SCL2
SCL
Internal Counter Reset
Figure 23-4. Synchronized Clock SCL
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Pin Configuration for I2C
23.4.2 Arbitration Procedure
The relative priority of competing devices is determined by a data arbitration procedure. A device loses arbitration
when it sends a logic high while another device sends a logic low. The device that loses arbitration immediately
switches to slave-receive mode, stops driving SDA, and sets the Arbitration Lost (IAL) bit in its I2C Status
Register (I2SR). In this case, the transition from master to slave mode does not generate a STOP condition.
23.4.3 Handshaking
Clock synchronization can function as a handshake in data transfers. When slave devices hold the SCL low after
completing a one byte transfer (9 bits), the clock synchronization feature halts the bus clock and forces the master
clock into a wait state until the slave releases the SCL.
23.4.4 Clock Stretching
Clock synchronization allows slaves to slow down the transfer bit rate. After the master drives the SCL low, the
slave can hold the SCL low. When the slave SCL low period is longer than the master SCL low period, the SCL
bus signal low period is stretched.
23.5 Pin Configuration for I2C
Two pins are available for the I2C module. These pins are multiplexed with other functions on the device and must
be configured for SPI operation.
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 25.5.1, “Data Direction Registers,” on
page 25-8 for details.
Table 23-1. Pin Configuration
Pin
Setting
Configuration Procedure
I2C_SCL
I2C CLOCK—This pin is open-drain when not in
GPIO. This is the primary function of
GPIO Port A [16].
1. Clear bit 16 of Port A GPIO In Use Register (GIUS_A)
2. Clear bit 16 of Port A General Purpose Register (GPR_A)
I2C_SDA
I2C Data—This pin is open-drain when not in
GPIO. This is the primary function of
GPIO Port A [15].
1. Clear bit 15 of Port A GPIO In Use Register (GIUS_A)
2. Clear bit 15 of Port A General Purpose Register (GPR_A)
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Programming Model
23.6 Programming Model
The I2C module includes five 32-bit registers. Table 23-2 summarizes these registers and their addresses.
Table 23-2. I2C Module Register Memory Map
Description
Name
Address
I2C Address Register
IADR
0x00217000
I2C Frequency Divider Register
IFDR
0x00217004
I2C Control Register
I2CR
0x00217008
I2C Status Register
I2SR
0x0021700C
I2C Data I/O Register
I2DR
0x00217010
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Programming Model
23.6.1 I2C Address Register
The I2C Address Register (IADR) holds the address to which the I2C responds when addressed as a slave.
NOTE:
2
As part of the I C communications protocol, the master sends out the 7-bit address
of the slave it intends to transfer data to or receive data from. When the
MC9328MXS is the bus master, the address it sends out is the address of its
intended slave device. It is NOT the address in this register. This value is only
referenced when another device is bus master and it intends to communicate with
the MC9328MXS.
Addr
0x00217000
I2C Address Register
IADR
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
ADR
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 23-3. I2C Address Register Description
Name
Description
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
ADR
Bits 7–1
Slave Address—Contains the specific slave address to be used by the I2C module. Slave mode is the
default I2C mode for an address match on the bus.
Reserved
Bit 0
Reserved—This bit is reserved and should read 0.
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23-7
Programming Model
23.6.2 I2C Frequency Divider Register
The I2C Frequency Divider Register (IFDR) holds the prescaler value that configures the clock for bit-rate
selection.
Addr
0x00217004
I2C Frequency Divider Register
IFDR
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
IC
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 23-4. IFDR Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
IC
Bits 5–0
I2C Clock Rate Divider—Prescales the clock for bit-rate selection. Due
to potentially slow rise and fall times of SCL and SDA, bus signals are
sampled at the prescaler frequency. The input clock from the PLL is
HCLK. The serial bit clock for the I2C module is HCLK divided by the
divider shown in Table 23-5.
Note:
Settings
See Table 23-5 on page 23-9.
The IC value can be changed at any point.
MC9328MXS Reference Manual, Rev. 1.1
23-8
Freescale Semiconductor
Programming Model
Table 23-5. HCLK Dividers
IC
Divider
IC
Divider
IC
Divider
IC
Divider
0x00
30
0x10
288
0x20
22
0x30
160
0x01
32
0x11
320
0x21
24
0x31
192
0x02
36
0x12
384
0x22
26
0x32
224
0x03
42
0x13
480
0x23
28
0x33
256
0x04
48
0x14
576
0x24
32
0x34
320
0x05
52
0x15
640
0x25
36
0x35
384
0x06
60
0x16
768
0x26
40
0x36
448
0x07
72
0x17
960
0x27
44
0x37
512
0x08
80
0x18
1152
0x28
48
0x38
640
0x09
88
0x19
1280
0x29
56
0x39
768
0x0A
104
0x1A
1536
0x2A
64
0x3A
896
0x0B
128
0x1B
1920
0x2B
72
0x3B
1024
0x0C
144
0x1C
2304
0x2C
80
0x3C
1280
0x0D
160
0x1D
2560
0x2D
96
0x3D
1536
0x0E
192
0x1E
3072
0x2E
112
0x3E
1792
0x0F
240
0x1F
3840
0x2F
128
0x3F
2048
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
23-9
Programming Model
23.6.3 I2C Control Register
The I2C Control Register (I2CR) enables the I2C module and the I2C interrupt. This register also contains bits that
select whether the device operates as a slave or a master.
Addr
0x00217008
I2C Control Register
I2CR
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
IEN
IIEN
MSTA
MTX
TXAK
RSTA
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 23-6. I2C Control Register Description
Name
Description
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
IEN
Bit 7
I2C Enable—Controls the software reset of the entire
I2C module. When the module is enabled in the middle
of a byte transfer, slave mode ignores the current bus
transfer and begins operating whenever a subsequent
START condition is detected.
Settings
0 = Disable the I2C module (registers can still be
accessed)
1 = Enable the I2C module (this bit must be set before
any other I2CR bits have any effect)
Master mode is not aware that the bus is busy, so when
a START cycle is initiated, the current bus cycle can
become corrupted and cause either the current bus
master or the I2C module to lose arbitration, after which
bus operation returns to normal.
IIEN
Bit 6
I2C Interrupt Enable—Enables the I2C interrupts.
0 = Disable the I2C module interrupts (currently
pending interrupt conditions are not cleared)
1 = Enable the I2C module interrupts (an I2C interrupt
occurs when the I2C interrupt (IIF) bit in the I2SR
Register is also set)
MSTA
Bit 5
Master/Slave Mode Select—Selects master or slave
mode operation. When the device loses arbitration
while running in master mode, MSTA is cleared without
generating a STOP signal.
0 = Slave mode (changing MSTA from 1 to 0
generates a STOP and selects slave mode)
1 = Master mode (changing MSTA from 0 to 1 signals
a START on the bus and selects master mode)
MC9328MXS Reference Manual, Rev. 1.1
23-10
Freescale Semiconductor
Programming Model
Table 23-6. I2C Control Register Description (continued)
Name
MTX
Bit 4
Description
Settings
Transmit/Receive Mode Select—Selects the direction
of master and slave transfers.
0 = Receive
1 = Transmit
Note: When a slave is addressed during transmit
mode, software sets MTX according to the Slave
Read/Write (SRW) bit in the I2SR Register. In master
mode, MTX is set according to the type of transfer
required. Therefore, for address cycles, MTX is always
set for master mode and cleared for slave mode.
TXAK
Bit 3
0 = Sends an acknowledge signal to the bus at the
ninth clock bit after receiving one byte of data
1 = No acknowledge signal response is sent (the data
acknowledge bit in the protocol = 1)
Transmit Acknowledge Enable—Specifies the value
driven onto SDA during data acknowledge cycles for
both master mode and slave mode receivers.
Note: TXAK applies only when the I2C bus is a
receiver.
RSTA
Bit 2
Repeated START—Generates a repeated START
condition. This bit always reads 0. Attempting a
repeated START without bus mastership causes loss of
arbitration.
Reserved
Bits 1–0
Reserved—These bits are reserved and should read 0.
0 = No repeated START
1 = Generates a repeated START
23.6.4 I2C Status Register
The I2C Status Register (I2SR) indicates transaction direction and status.
Addr
0x0021700C
I2C Status Register
I2SR
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
ICF
IAAS
IBB
IAL
SRW
IIF
RXAK
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
r
r
r
r
r
r
r
r
r
r
r
rw
r
r
rw
r
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
RESET
0x0081
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
23-11
Programming Model
Table 23-7. I2SR Register Description
Name
Description
Settings
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
ICF
Bit 7
Data Transfer—Indicates data transfer condition. ICF is cleared
while one byte of data is transferred.
0 = Transfer in progress
1 = Transfer complete (set at the falling
edge of the ninth clock of a byte
transfer)
IAAS
Bit 6
I2C Addressed As a Slave—Indicates that the device slave
address matches the address sent on the data line. When the I2C
Enable (IIEN) bit in the I2CR Register is set, an interrupt is
generated to the ARM9 core when this match occurs. The ARM9
core must check the Slave Read/Write (SRW) bit and set the
Transmit/Receive Mode Select (MTX) bit of the I2CR Register
accordingly. Writing to the I2CR Register clears this bit.
0 = Not addressed
1 = Addressed as a slave (set when the
MC9328MXS slave address in the
IADR Register matches the calling
address)
IBB
Bit 5
I2C Bus Busy—Indicates the status of the bus. When a STOP
signal is detected, IBB is cleared, and when a START signal is
detected, IBB is set.
0 = Bus is idle
1 = Bus is busy
IAL
Bit 4
Arbitration Lost—Indicates that this device will not operate as bus master. IAL cleared by writing 0 to it, and is
set by the hardware in the following circumstances:
• SDA samples low when the master drives high during an address or data-transmit cycle
• SDA samples low when the master drives high during the acknowledge bit of a data-receive cycle
• A START is attempted when the bus is busy
• A repeated START is requested in slave mode
• A STOP condition is detected when the master did not request it
Reserved
Bit 3
Reserved—This bit is reserved and should read 0.
SRW
Bit 2
Slave Read/Write—Indicates the value of the R/W command bit of
the I2C protocol when the device is the addressed as a slave (IAAS
bit is set). SRW is valid only when a complete transfer occurs, no
other transfers have been initiated, and the I2C module is a slave
with an address match.
0 = Slave receiver, master writing to slave
1 = Slave transmitter, master reading from
slave
IIF
Bit 1
I2C interrupt—Indicates an interrupt condition. Cleared by writing
0 in the interrupt routine. Set when one of the following occurs:
• Completion of one byte transfer (set at the falling edge of
the ninth clock)
• Calling address matches MC9328MXS slave address
• Arbitration is lost
0 = No I2C interrupt pending
1 = An interrupt is pending, which causes
a processor interrupt request
(when IIEN = 1).
RXAK
Bit 0
Received Acknowledge—Indicates whether an acknowledge
signal (to the data) was received on SDA.
0 = An acknowledge signal was received
after the completion of 8-bit data
transmission on the bus
1 = No acknowledge signal was detected
at the ninth clock
MC9328MXS Reference Manual, Rev. 1.1
23-12
Freescale Semiconductor
I2C Programming Examples
23.6.5 I2C Data I/O Register
The I2C Data I/O Register (I2DR) contains the data received or the data to be transmitted during I/O operations. In
transmission mode, this value is sent out after the receiving device sends an acknowledge signal. In master-receive
mode, the last byte received is held in this register. Reading this register initiates the transfer of the next byte of
receive data. In slave mode, the same function is available after the device is addressed.
Addr
0x00217010
I2C Data I/O Register
I2DR
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
D
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 23-8. I2DR Register Description
Name
Description
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
D
Bits 7–0
I2C Data—Holds last data byte received or next data byte to be transferred.
23.7 I2C Programming Examples
This section describes programming sequences for I2C, including initialization, START signalling, post-transfer
software response, STOP signalling, and repeated START generation. The flowchart in Figure 23-5 on page 23-16
illustrates an interrupt routine.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
23-13
I2C Programming Examples
23.7.1 Initialization Sequence
The registers must be initialized before the interface can transfer serial data. The procedure to initialize the
registers is as follows:
1. Set the Clock Rate Divider (IC field) in the I2C Frequency Divider Register (IFDR) for the
appropriate SCL frequency.
2. Write the device slave address in the I2C Address Register (IADR).
3. Enable the I2C module by setting the I2C Enable bit (IEN) in the I2C Control Register (I2CR).
4. Modify the bits in the I2C Control Register (I2CR) to select master/slave mode, transmit/receive
mode, and interrupt enable/disable.
NOTE:
Before enabling the I2C module, ensure that another communication is not in
progress by verifying that the I2C Bus Busy bit (IBB) of the I2C Status Register
(I2SR) is cleared. When it is not cleared, execute the following code sequence to
force the slave device into an idle condition by issuing a STOP command before
enabling the I2C module.
23.7.2 Generation of START
After the initialization procedure is complete and the serial bus is free, the MC9328MXS transmits serial data by
selecting the master transmitter mode. The IBB bit in the I2SR Register indicates the bus condition. When the bus
is free (IBB bit in the I2SR Register = 0), the START signal and the slave address can be sent. The address of the
appropriate slave is written to the I2C Data I/O Register (I2DR), where the least significant bit (LSB) indicates the
transfer direction.
The bus free time between a STOP signal and the next START signal is built into the hardware that generates the
START. Depending on the relative frequencies of the system clock and the SCL period, it is sometimes necessary
to wait after writing the calling address to the I2DR before proceeding with the following instructions.
23.7.3 Post-Transfer Software Response
When one byte is sent or received, the Data Transfer (ICF) and the I2C Interrupt (IIF) bits in the I2C Status Register
(I2SR) are set. An interrupt occurs when interrupts are enabled by the IIEN bit of the I2C Control Register (I2CR).
First, the software must clear IIF in the interrupt routine. ICF is cleared either by reading the data from the I2C Data
I/O Register (I2DR) in receive mode or by writing to the I2DR in transmit mode. Clearing ICF triggers the start of
the next communication byte.
The software can service the I2C I/O in the main program by disabling the interrupts (clear IIEN) and polling the
IIF bit.
When an interrupt occurs at the end of the address cycle, the master is still in transmit mode. When master receive
mode is required, toggle the MTX bit in the I2CR Register.
When the device is functioning as the addressed slave (the IAAS bit in the I2SR is set), the SRW bit in the I2SR
Register is read to determine the direction of the next transfer, and MTX is programmed accordingly. For
slave-mode data cycles (IAAS = 0), the SRW bit is invalid. The MTX bit is read to determine the current transfer
direction.
MC9328MXS Reference Manual, Rev. 1.1
23-14
Freescale Semiconductor
I2C Programming Examples
The following is an example of a software response by a master transmitter in the interrupt routine (see Figure 23-5
on page 23-16).
23.7.4 Generation of STOP
A data transfer ends when the master signals a STOP, which can occur after all data is sent. When the master
receiver intends to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last data
byte. This is done by setting the TXAK bit in the I2CR Register before reading the next-to-last byte. Before the last
byte is read, a STOP signal must be generated.
23.7.5 Generation of Repeated START
After the data transfer is complete, the master can retain control of the bus by issuing a repeated START. Instead of
sending a STOP signal, the master sends another START signal and sends out another slave calling address. See
Figure 23-3 on page 23-4 for more information.
23.7.6 Slave Mode
When another device initiates communication on the bus, the MC9328MXS I2C module must verify whether it is
addressed as the slave device by checking the I2C Addressed as a Slave bit (IAAS) in the I2SR Register. When
IAAS is set, the software reads the SRW bit in the I2SR Register and sets the Transmit/Receive Mode Select bit
(MTX) in the I2CR Register accordingly. Writing to the I2CR Register clears the IAAS bit automatically. The
IAAS bit is set only at the end of the address cycle, even when there are multiple data bytes transferred.
Initiate a data transfer by writing data to the I2DR Register for slave transmits, or by reading data from the I2DR
Register in slave receive mode. A dummy read of the I2DR Register in slave receive mode releases the SCL,
allowing the master to send data.
In the slave transmitter routine, the Receive Acknowledge bit (RXAK) in the I2SR Register must be tested before
sending the next byte of data. When RXAK is high, the master receiver intends to terminate the data transfer. The
software must switch the MC9328MXS from transmitter to receiver mode. Reading the I2DR Register releases the
SCL so the master can generate a STOP signal.
23.7.7 Arbitration Lost
When several devices try to engage the bus at the same time, one becomes the master and the hardware
immediately switches the other devices to slave receive mode. Data output to the SDA line stops, however the
serial clock continues to be generated until the end of the byte during which arbitration is lost. An interrupt occurs
at the falling edge of the ninth clock of this transfer.
When a device that is not a master tries to transmit or generate a START, hardware automatically clears the
Master/Slave Mode Select bit (MSTA) in the I2CR Register without signalling a STOP, generates an interrupt to
the ARM920T processor, and sets the Arbitration Lost bit (IAL) in the I2SR Register to indicate a failed attempt to
engage the bus. The slave service routine must first test the IAL bit and clear it when it is set.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
23-15
I2C Programming Examples
Clear IIF
Yes
Master Mode?
No
Yes
Tx
Rx
Tx/Rx?
Arbitration Lost?
No
Last Byte
Transmitted?
Yes
Clear IAL
No
No
Last Byte
to be Read?
RXAK=0?
End of
ADDR Cycle
(Master Rx)
?
Yes
IAAS=1?
Address
Cycle
No
Yes
Yes
No
Yes
(Read)
Yes
2nd Last
Byte to be
Read?
IAAS=1?
Yes
No
SRW=1?
Tx/Rx?
(Write)
No
No
No
Yes
Set Tx Mode
Data
Cycle
Rx
Tx
Yes
ACK from
Receiver?
No
Write Next
Byte to I2DR
Set TXAK=1
Generate
STOP Signal
Switch to
Rx Mode
Dummy Read
from I2DR
Generate
STOP Signal
Read Data
from I2DR
and Store
Write Data
to I2DR
Tx Next Byte
Read Data
from I2DR
and Store
Set Rx Mode
Switch to
Rx Mode
Dummy Read
from I2DR
Dummy Read
from I2DR
RTE
Figure 23-5. Flow Chart of Typical I2C Interrupt Routine
MC9328MXS Reference Manual, Rev. 1.1
23-16
Freescale Semiconductor
Chapter 24
Synchronous Serial Interface (SSI)
24.1 Introduction
This chapter describes the Synchronous Serial Interface (SSI) and provides descriptions of the architecture,
programming model, operating modes, and initialization procedures of SSI module. The SSI is a full-duplex serial
port that allows the MC9328MXS to communicate with a variety of serial devices. These serial devices include
standard codecs, digital signal processors (DSPs), microprocessors, peripherals that implement the Motorola Serial
Peripheral Interface (SPI), and popular industry audio codecs that implement the inter-IC sound bus standard (I2S).
The SSI typically transfers samples in a periodic manner. The SSI consists of independent transmitter and receiver
sections with independent clock generation and frame synchronization functions.
The capabilities of the SSI include:
•
Independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared
internal/external clocks and frame syncs, operating as master or slave
•
Normal mode operation using frame sync
•
Network mode operation allowing multiple devices to share the port with as many as 32 time slots
•
Gated clock mode operation requiring no frame sync
•
Programmable internal clock divider
•
Programmable data interface modes such as I2S, left-, and right-justified
•
Programmable word length (8, 10, 12, or 16 bits)
•
Program options for frame sync and clock generation
•
Programmable I2S mode (master, slave, or normal) selection
•
Completely separate clock and frame sync selections for the receive and transmit sections
•
Programmable oversampling output clock SYS_CLK (PerCLK3) of the sampling frequency in master mode
which is available at the SSI_RXCLK pin when operated in sync mode.
•
SSI power-down feature
•
SSI signals are connected to Port B or Port C I/O pins
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-1
SSI Architecture
24.2 SSI Architecture
Figure 24-1 shows that the SSI functions can use Port B or Port C pins. For SSI output signals, the signal appears
on both pins. However, SSI input or bidirectional signals require that the user configure one of the ports for the
signal. This is done by setting up the desired pin in the Function Muxing Control Register (FMCR) in the system
control module and then setting up the GPIO pins appropriately for Primary/Alternate and GPIO/Peripheral
functions.For more information, see Section 24.2.3, on page 24-5.
MC9328MXS
GPIO Port B
Alternate
Function
PTB[19]
SSI_TXCLK
PTB[18]
SSI_TXFS
PTB[17]
SSI_TXDAT
PTB[16]
SSI_RXDAT
Transmit Clock
PTB[15]
SSI_RXCLK
Transmit Frame Sync
PTB[14]
SSI_RXFS
SSI
Transmit Data
Receive Data
Receive Clock
Receive Frame Sync
Note: The user may
choose to use Port B
or Port C, but not both.
See Section 24.2.3,
“Pin Configuration for
SSI.”
FMCR
Register
GPIO Port C
Primary
Function
PTC[8]
SSI_TXCLK
PTC[7]
SSI_TXFS
PTC[6]
SSI_TXDAT
PTC[5]
SSI_RXDAT
PTC[4]
SSI_RXCLK
PTC[3]
SSI_RXFS
Figure 24-1. MC9328MXS SSI Input/Output Block Diagram
Figure 24-2 shows a block diagram of the SSI module. The SSI modules uses three control registers to configure
the port, one status register, separate transmit and receive circuits with FIFO registers, and separate serial clock and
frame sync generation for the transmit and receive sections.
MC9328MXS Reference Manual, Rev. 1.1
24-2
Freescale Semiconductor
SSI Architecture
IP Bus
32-bit
SSI Transmit Clock
Control Register
(STCCR)
Transmit Control
and
State Machines
SSI Receive Clock
Control Register
(SRCCR)
Operations
Update
Register
Values
SSI Transmit
Configuration
Register (STCR)
Receive Control
and
State Machines
SSI Receive
Configuration
Register (SRCR)
Operations
Update
Register
Values
SSI Control/Status
Register (SCSR)
Transmit Clock
Generator
SSI_
TXCLK
Transmit Sync
Generator
SSI_TXFS
Receive Clock
Generator
SSI_RXCLK /
SYS_CLK
Receive Sync
Generator
SSI_RXFS
SSI Time Slot
Register (STSR)
TXFIFO
(8x16)
SSI Transmit Data
Register (STX)
SSI Transmit Shift
Register (TXSR)
SSI_TXDAT
RXFIFO
(8x16)
SSI Receive Data
Register (SRX)
SSI Receive Shift
Register (RXSR)
SSI_RXDAT
Figure 24-2. SSI Block Diagram
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-3
SSI Architecture
24.2.1 SSI Clocking
The SSI uses the following clocks:
•
Serial bit clock—Serially clocks the data bits in and out of the SSI port
•
Word clock—Counts the number of data bits per word (8, 10, 12, or 16 bits)
•
Frame clock—Counts the number of words in a frame
•
SYS_CLK—Input Clock from the PLL Clock Controller Module (PerCLK3). Made available on an output
pin in synchronous master mode.
24.2.1.1 Normal Operating Mode
In normal operating mode, when the I2S Mode Select bits (I2S_MODE1 and I2S_MODE0) in the SSI
Control/Status Register (SCSR) are both clear, the serial bit clock is available on the serial transmit
clock (SSI_TXCLK) and serial receive clock (SSI_RXCLK) pins. The word clock is an internal clock that
determines when transmission of an 8-, 10-, 12-, or 16-bit word is complete. The word clock also clocks the frame
clock, which counts the number of words in the frame. The frame sync clock is available on the SSI_TXFS and
SSI_RXFS frame sync pins because a frame sync is generated after the correct number of words in the frame are
transmitted/received. See Section 24.5, “SSI Operating Modes,” on page 24-38 for a detail description about the
SSI operating modes.
24.2.1.2 Master / Synchronous Mode
In master mode and synchronous mode, the unused SSI_RXCLK pin outputs the serial system clock (SYS_CLK)
enabled by the SYS_CLK_EN bit in the SSI Control/Status Register (SCSR). The SYS_CLK (PerCLK3) is the
input clock into the SSI module. The SSI Clock Generator uses the word length (WL), prescaler range (PSR),
prescaler modulus select (PM), and frame rate divider control (DC) to generate the other clocks from SYS_CLK
(PerCLK3). The relationship between the clocks and the dividers is shown in Figure 24-3. A serial bit clock may be
received from a SSI clock pin or can be generated internally from the PerCLK3 clock by a series of dividers, as
shown in Figure 24-4.
Serial Bit Clock
Word Divider
(÷8, ÷10, ÷12, ÷16)
Word Clock
Frame Divider
(÷1, to ÷32)
Frame Clock
Figure 24-3. SSI Clocking
24.2.2 SSI Clock and Frame Sync Generation
Data clock and frame sync signals are generated internally by the MC9328MXS or can be obtained from external
sources. When generated internally, the SSI clock generator derives bit clock and frame sync signals from an input
clock signal. The SSI clock generator consists of a selectable, fixed prescaler and a programmable prescaler for bit
rate clock generation. In gated clock mode, the data clock is valid only when data is being transmitted. If the
pull-up is disabled for this pin in the GPIO Module’s Pull-Up Enable Register, then the clock pin is tri-stated when
data is not transmitting.
A programmable frame rate divider and a word length divider are used for frame rate sync signal generation.
MC9328MXS Reference Manual, Rev. 1.1
24-4
Freescale Semiconductor
SSI Architecture
Figure 24-4 on page 24-5 shows a block diagram of the clock generator for the transmit section. Whether the serial
bit clock is generated internally or derived from an external source depends on the transmit direction bit in the SSI
Transmit Configuration Register (STCR). The receive section contains a similar clock generator circuit. However,
for the receiver, because SSI_RXCLK is used for the receive clock, SYS_CLK (PerCLK3) is not made available
on any output pins.
PLL Clock Controller Module
PSR
System PLLCLK
PCLKDIV3
7-bit divider
PerCLK3
÷4
PM [7:0]
Prescaler (÷1 or ÷8)
Modulus Divider
(÷1 to ÷256)
Only in Synchronous Master Mode
TXDIR
SYS_CLK_EN
NET
SYN
SSI_RXCLK /
SYS_CLK
TXDIR (1=Output)
WL [1:0]
TXDIR (1=Output)
SSI_TXCLK
Word Divider
/8, /10, /12, or /16
TXDIR (0=Input)
Word Clock
Serial Bit Clock
Figure 24-4. SSI Transmit Clock Generator Block Diagram
Figure 24-5 shows the frame sync generator block for the transmit section. When generated internally, both receive
and transmit frame sync signals are generated from the word clock and are defined by the DC and WL bits of the
SSI Transmit Clock Control Register (STCCR). The receive section contains an equivalent circuit for the frame
sync generator.
DC [4:0]
Word Clock
TFSI
Frame Divider
Frame Clock Frame Sync
/1 to /32
Frame Clock
Tx Control
TFDIR (1=input)
SSI_TXFS
TFSL
Tx Frame Sync Out
TFSI
Tx Frame Sync In
TFDIR (0=output)
Figure 24-5. SSI Transmit Frame Sync Generator Block Diagram
24.2.3 Pin Configuration for SSI
Figure 24-1 illustrates the pins used for the SSI module. Table 24-1 on page 24-6 provides the pin configuration for
the SSI module. These pins are multiplexed with other functions on the device, and must be configured for SSI
operation.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-5
SSI Architecture
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 25.5.1, “Data Direction Registers,” on
page 25-8 for details.
Table 24-1. SSI Pin Configuration
Pin
SSI_TXCLK
SSI_TXFS
SSI_TXDAT
SSI_RXDAT
Setting1
Configuration Procedure
Primary function of
GPIO Port C [8]
1. Clear bit 8 of Port C GPIO In Use Register (GIUS_C)
2. Clear bit 8 of Port C General Purpose Register (GPR_C)
3. Clear bit 3 in the Function Muxing Control Register (FMCR) in the System Control
Module
Alternate function
of GPIO Port B [19]
1. Clear bit 19 of Port B GPIO In Use Register (GIUS_B)
2. Set bit 19 of Port B General Purpose Register (GPR_B)
3. Set bit 3 in the Function Muxing Control Register (FMCR) in the System Control
Module
Primary function of
GPIO Port C [7]
1. Clear bit 7 of Port C GPIO In Use Register (GIUS_C)
2. Clear bit 7 of Port C General Purpose Register (GPR_C)
3. Clear bit 4 in the Function Muxing Control Register (FMCR) in the System Control
Module
Alternate function
of GPIO Port B [18]
1. Clear bit 18 of Port B GPIO In Use Register (GIUS_B)
2. Set bit 18 of Port B General Purpose Register (GPR_B)
3. Set bit 4 in the Function Muxing Control Register (FMCR) in the System Control
Module
Primary function of
GPIO Port C [6]
1. Clear bit 6 of Port C GPIO In Use Register (GIUS_C)
2. Clear bit 6 of Port C General Purpose Register (GPR_C)
(This is an output-only pin and therefore does not require a control signal in the
Function Muxing Control Register (FMCR))
Alternate function
of GPIO Port B [17]
1. Clear bit 17 of Port B GPIO In Use Register (GIUS_B)
2. Set bit 17 of Port B General Purpose Register (GPR_B)
(This is an output-only pin and therefore does not require a control signal in the
Function Muxing Control Register (FMCR))
Primary function of
GPIO Port C [5]
1. Clear bit 5 of Port C GPIO In Use Register (GIUS_C)
2. Clear bit 5 of Port C General Purpose Register (GPR_C)
3. Clear bit 5 in the Function Muxing Control Register (FMCR) in the System Control
Module
Alternate function
of GPIO Port B [16]
1. Clear bit 16 of Port B GPIO In Use Register (GIUS_B)
2. Set bit 16 of Port B General Purpose Register (GPR_B)
3. Set bit 5 in the Function Muxing Control Register (FMCR) in the System Control
Module
MC9328MXS Reference Manual, Rev. 1.1
24-6
Freescale Semiconductor
Programming Model
Table 24-1. SSI Pin Configuration (continued)
Pin
SSI_RXCLK
SSI_RXFS
1.
Setting1
Configuration Procedure
Primary function of
GPIO Port C [4]
1. Clear bit 4 of Port C GPIO In Use Register (GIUS_C)
2. Clear bit 4 of Port C General Purpose Register (GPR_C)
3. Clear bit 6 in the Function Muxing Control Register (FMCR) in the System Control
Module
Alternate function
of GPIO Port B [15]
1. Clear bit 15 of Port B GPIO In Use Register (GIUS_B)
2. Set bit 15 of Port B General Purpose Register (GPR_B)
3. Set bit 6 in the Function Muxing Control Register (FMCR) in the System Control
Module
Primary function of
GPIO Port C [3]
1. Clear bit 3 of Port C GPIO In Use Register (GIUS_C)
2. Clear bit 3 of Port C General Purpose Register (GPR_C)
3. Clear bit 7 in the Function Muxing Control Register (FMCR) in the System Control
Module
Alternate function
of GPIO Port B [14]
1. Clear bit 14 of Port B GPIO In Use Register (GIUS_B)
2. Set bit 14 of Port B General Purpose Register (GPR_B)
3. Set bit 7 in the Function Muxing Control Register (FMCR) in the System Control
Module
Only one of the two pins should be set-up for each SSI signal.
24.2.3.1 Pin Configuration Example Software
Code Example 24-1 sets up the SSI pins as the alternate function of Port B by following the configuration
in Table 24-1 on page 24-6.
Code Example 24-1. SSI Pin Setup
// Configure Pad to Peripheral Function instead of GPIO
LDR r1,=GIUS_B
// GPIO PORT B GIUS register
LDR r2,=0xFFF03FFF
// Pins 14-19 should be cleared
STR r2,[r1]
// Configure Pad for Alternate Function instead of Primary
LDR r1,=GPR_B
// GPIO PORT B GPR register
LDR r2,=0x000FC000
// Pins 14-19 should be set
STR r2,[r1]
// Configure FMCR to Select SSI input from SSI/SIM Pads
LDR r1,=FMCR
// CRM FMCR register
LDR r2,=0x000000F8
// Pins 7-3 should be set
STR r2,[r1]
// The SSI default is in pull-up state. Disable the pull-up, making them tristate
LDR r1,=PUEN_B
// GPIO PORTB PUEN register
LDR r2,=0xFFF03FFF
// Disable pullup for SSI input pins
STR r2,[r1]
24.3 Programming Model
The SSI module includes ten user-accessible 32-bit registers. It also includes two 16-bit internal registers
and two 8×16 bit internal FIFOs. Table 24-2 summarizes these registers and their addresses.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-7
Programming Model
Table 24-2. SSI Module Register Summary
Description
Name
Address
SSI Transmit Data Register
STX
0x00218000
SSI Receive Data Register
SRX_1
0x00218004
SSI Control/Status Register
SCSR
0x00218008
SSI Transmit Configuration Register
STCR
0x0021800C
SSI Receive Configuration Register
SRCR
0x00218010
SSI Transmit Clock Control Register
STCCR
0x00218014
SSI Receive Clock Control Register
SRCCR
0x00218018
SSI Time Slot Register
STSR
0x0021801C
SSI FIFO Control/Status Register
SFCSR
0x00218020
SSI Option Register
SOR
0x00218028
SSI Transmit and Receive FIFO Registers
SSI Transmit Shift Register
TXSR
—
SSI Receive Shift Register
RXSR
—
NOTE:
To use SSI, the Port B General Purpose Register (GPR) and GPIO In Use (GIUS)
registers must be set correctly. See Section 24.2.3, “Pin Configuration for SSI,” for
more information.
24.3.1 SSI Transmit Data Register
The SSI Transmit Data Register (STX) holds the data to be transmitted. The data is transferred to the SSI Transmit
Shift Register (TXSR), and when that register is empty, the data is shifted out onto the serial transmit data
(SSI_TXDAT) pin.
The STXregister is implemented as the first word of the transmit FIFO. When the transmit FIFO enable (TFEN) bit
in STCR is set, 8 data values are written to the STX register and these values are held in the transmit FIFO. They
are then transmitted out one word at a time.
When the transmit interrupt enable (TIE) bit in the SSI Transmit Configuration Register (STCR1 is set, an interrupt
occurs if no data is waiting to be transferred to the shift register (the transmit data empty (TDE) bit in the SCSR
register is set) and the transmit register is empty.
When multiple writes to the STX register occur, data already in the register is not overwritten by incoming data.
Multiple writes are accomplished as shown in the following examples:
•
When the transmit FIFO is enabled and the user writes data1, data2, …, data9 to the STX register,
data1, data2, …, data8 are stored in the FIFO, and data9 is discarded.
•
When the transmit FIFO is disabled and user writes data1, data2 to the STX register, data2 is discarded.
NOTE:
Enable the SSI (SSI_EN = 1) in the SCSR before writing to the STX register.
MC9328MXS Reference Manual, Rev. 1.1
24-8
Freescale Semiconductor
Programming Model
STX
Addr
0x00218000
SSI Transmit Data Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
HIGH BYTE
TYPE
LOW BYTE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 24-3. SSI1 Transmit Data Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
HIGH BYTE
Bits15–8
Transmit Data High Byte—Holds the high byte of the data to be transmitted out of the SSI.
LOW BYTE
Bits 7–0
Transmit Data Low Byte—Holds the low byte of the data to be transmitted out of the SSI.
24.3.2 SSI Transmit FIFO Register
The SSI transmit FIFO is a 8×16-bit register that holds up to 8 words to be transmitted out by the SSI. The STX
register is the first word of this FIFO, and data is transmitted first-in–first-out. The transmit FIFO is enabled by
setting the Transmit FIFO Enable (TFEN) in the STCR register.
When the TIE bit in the STCR is enabled and the Transmit FIFO Empty (TFE) bit in the SCSR is set, an interrupt
occurs if the data level in the transmit FIFO falls below the threshold value.
When the transmit FIFO is full, all further writes are ignored until the data is transmitted.
24.3.3 SSI Transmit Shift Register
The SSI Transmit Shift Register (TXSR) is a 16-bit shift register containing the data ready to be transmitted.
When a continuous clock is used, data is shifted out to the SSI_TXDAT pin by the selected (internal/external) bit
clock when the associated (internal/external) frame sync is asserted. When a gated clock is used, data is shifted out
to the SSI_TXDAT pin by the selected (internal/external) gated clock.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-9
Programming Model
The WL bits in the STCCR register determine the number of bits that will be shifted out of the TXSR before it is
considered empty and can be written to again. This word length can be 8, 10, 12, or 16 bits.
The Transmit Shift Direction (TSHFD) bit and Transmit Bit Position(TXBIT0) in the STCR determines how the
data is transmitted. Table 24-4 displays the data bit shifting configuration and Figure 24-6 through Figure 24-9
visually the data path for each configuration.
Table 24-4. Data Bit Shifting Configuration
TXBIT0
TSHFD
WL[1:0]
Shifting from Bit
0
0
xx
Bit 15 (MSB) first
0
1
00
Bit 8 (LSB) first, bit 15 (MSB) last
0
1
01
Bit 6 (LSB) first, bit 15 (MSB) last
0
1
10
Bit 4 (LSB) first, bit 15 (MSB) last
0
1
11
Bit 0 (LSB) first, bit 15 (MSB) last
1
0
00
Bit 7 (MSB) first, bit 0 (LSB) last
1
0
01
Bit 9 (MSB) first, bit 0 (LSB) last
1
0
10
Bit 11 (MSB) first, bit 0 (LSB) last
1
0
11
Bit 15 (MSB) first, bit 0 (LSB) last
1
1
xx
Bit 0 (LSB) first
8-Bit Word
10-Bit Word
12-Bit Word
16-Bit Word
15 14 13 12 11 10 9 8 7 6
5
4
3
2
1
0
STX
SSI_TXDAT
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TXSR
Bit 15 is shifted out first.
The number of bits shifted is based on word length.
Figure 24-6. Transmit Data Path (TXBIT0 = 0, TSHFD = 0)
MC9328MXS Reference Manual, Rev. 1.1
24-10
Freescale Semiconductor
Programming Model
8-Bit Word
10-Bit Word
12-Bit Word
16-Bit Word
15 14 13 12 11 10 9 8 7 6
5
4
3
2
1
0
15 14 13 12 11 10 9
5
4
3
2
1
0
STX
8
7
6
TXSR
16-Bit Word
12-Bit Word
10-Bit Word
8-Bit Word
The first bit shifted out depends on word length.
Arrows indicate the first bit shifted out for each word length;
remaining higher bits are then shifted out.
Bit 15 is always shifted out last.
SSI_TXDAT
Figure 24-7. Transmit Data Path (TXBIT0 = 0, TSHFD = 1)
8-Bit Word
10-Bit Word
12-Bit Word
16-Bit Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2
1
0
15 14 13 12 11 10 9
1
0
STX
8
7
6
5
4
3
2
TXSR
8-Bit Word
10-Bit Word
12-Bit Word
16-Bit Word
SSI_TXDAT
The first bit shifted out depends on word length.
Arrows indicate the first bit shifted out for each word length;
remaining lower bits are then shifted out.
Bit 0 is always shifted out last
Figure 24-8. Transmit Data Path (TXBIT0 = 1, TSHFD = 0)
8-Bit Word
10-Bit Word
12-Bit Word
16-Bit Word
15 14 13 12 11 10 9 8 7 6 5 4 3 2
1
0
15 14 13 12 11 10 9
1
0
STX
8
7
6
5
4
SSI_TXDAT
3
2
TXSR
Bit 0 is shifted out first.
Number of bits shifted is based on word length.
Figure 24-9. Transmit Data Path (TXBIT0 = 1, TSHFD = 1)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-11
Programming Model
24.3.4 SSI Receive Data Register
The read-only SSI Receive Data Register (SRX) holds the most recently received data. Incoming data from the
serial receive data (SSI_RXDAT) pin is held in the SSI Receive Shift Register (RXSR) as it is received. When the
transmission is complete, the data is transferred to the SRX register.
The SRX register is implemented as the first word of the receive FIFO. When the receive FIFO is enabled in the
SSI Receive Configuration Register (SRCR), 8 data values are received into the SSI receive FIFO.
When the receive interrupt enable (RIE) bit in the SRCR is set, an interrupt occurs when a new value is loaded into
the SRX register from the RXSR.
SRX
Addr
0x00218004
SSI Receive Data Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
HIGH BYTE
TYPE
LOW BYTE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 24-5. SSI Receive Data Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
HIGH BYTE
Bits 15–8
Receive Data High Byte—Holds the high byte of the data received from the RXSR.
LOW BYTE
Bits 7–0
Receive Data Low Byte—Holds the low byte of the data received from the RXSR.
24.3.5 SSI Receive FIFO Register
SSI receive FIFO is an 8×16-bit register that holds the last 8 words received by the SSI. The SRX register is the
first word of this FIFO. The receive FIFO is enabled by setting the Receive FIFO Enable (RFEN) in the SRCR
When the RIE bit is enabled and the Receive FIFO Full (RFF) bit in the SCSR is set, an interrupt occurs if the data
level in the receive FIFO reaches the threshold value.
When the receive FIFO is full, all further received data is ignored until the data is read out.
MC9328MXS Reference Manual, Rev. 1.1
24-12
Freescale Semiconductor
Programming Model
24.3.6 SSI Receive Shift Register
The SSI Receive Shift Register (RXSR) is a 16-bit shift register that contains the data being received from the
SSI_RXDAT pin. When the register is full, received data fills the receive FIFO.
When a continuous clock is used, data is shifted in by the selected (internal/external) bit clock when the associated
(internal/external) frame sync is asserted. When a gated clock is used, data is shifted in from the SSI_TXDAT pin
by the selected (internal/external) gated clock.
The Receive shift direction (RSHFD) bit and Receive bit position(RXBIT0) in the SRCR determines how the data
is stored. Table 24-6 contains all of the information about data bit shifting configurations and Figure 24-10 through
Figure 24-13 visually the data path for each configuration.
The WL bits in the SSI Receive Clock Control Register (SRCCR) determine the number of bits to be shifted in
from the SSI_RXDAT pin. This word length can be 8, 10, 12, or 16 bits. When receiving 8, 10, or 12 bits of data,
0s are appended to the end of the data string to fill the 16-bit register.
Table 24-6. Data Bit Shifting Configuration
RXBIT0
RSHFD
WL[1:0]
0
0
00
Bit 15 (MSB) first, bit 8 (LSB) last
01
Bit 15 (MSB) first, bit 6 (LSB) last
10
Bit 15 (MSB) first, bit 4 (LSB) last
11
Bit 15 (MSB) first, bit 0 (LSB) last
00
Bit 8 (MSB) first, bit 15 (LSB) last
01
Bit 6 (MSB) first, bit 15 (LSB) last
10
Bit 4 (MSB) first, bit 15 (LSB) last
11
Bit 0 (MSB) first, bit 15 (LSB) last
00
Bit 0 (MSB) first, bit 7 (LSB) last
01
Bit 0 (MSB) first, bit 9 (LSB) last
10
Bit 0 (MSB) first, bit 11 (LSB) last
11
Bit 0 (MSB) first, bit 15 (LSB) last
00
Bit 7 (MSB) first, bit 0 (LSB) last
01
Bit 9 (MSB) first, bit 0 (LSB) last
10
Bit 11 (MSB) first, bit 0 (LSB) last
11
Bit 15 (MSB) first, bit 0 (LSB) last
0
1
1
1
0
1
Shifting to bit
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-13
Programming Model
8-Bit Word
10-Bit Word
12-Bit Word
16-Bit Word
15 14 13 12 11 10 9 8 7 6
5
4
3
2
1
0
15 14 13 12 11 10 9
5
4
3
2
1
0
SRX
8
7
6
SSI_RXDAT
RXSR
Bit 15 is shifted in first. The number of bits shifted is based on word length.
Zeros are added to end of data string for smaller words (8, 10 or 12 bits).
Figure 24-10. Receive Data Path (RXBIT0 = 0, RSHFD = 0)
8-Bit Word
10-Bit Word
12-Bit Word
16-Bit Word
15 14 13 12 11 10 9 8 7 6
5
4
3
2
1
0
15 14 13 12 11 10 9
5
4
3
2
1
0
SRX
8
7
6
SSI_RXDAT
RXSR
The first bit shifted in depends on word length.
Arrowheads indicate the bit shifted in first in each case; remaining higher bits are then
shifted in. Bit 15 is always shifted in last.
Figure 24-11. Receive Data Path (RXBIT0 = 0, RSHFD = 1)
8-Bit Word
10-Bit Word
12-Bit Word
16-Bit Word
15 14 13 12 11 10 9 8 7 6 5 4 3
2
1
0
SRX
SSI_RXDAT
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RXSR
Bit 0 is shifted in first. The number of bits shifted is based on word length.
Zeros are added to end of the data string for smaller words (8, 10 or 12 bits).
Figure 24-12. Receive Data Path (RXBIT0 = 1, RSHFD = 0)
MC9328MXS Reference Manual, Rev. 1.1
24-14
Freescale Semiconductor
Programming Model
8-Bit Word
10-Bit Word
12-Bit Word
16-Bit Word
15 14 13 12 11 10 9 8 7 6 5 4
3
2
1
0
15 14 13 12 11 10 9
3
2
1
0
SRX
8
7
6
5
4
SSI_RXDAT
RXSR
The first bit shifted in depends on word length.
Arrowheads indicate the bit shifted in first in each case; all lower bits are then shifted in.
Bit 0 is always shifted in last.
Figure 24-13. Receive Data Path (RXBIT0 = 1, RSHFD = 1)
24.3.7 SSI Control/Status Register
The SSI Control/Status Register sets up and monitors the SSI. The SSI status bits are updated when the SSI is
enabled, and then after the transmission or reception of the first bit of the next SSI word is complete. The Receive
Overrun Error (ROE) and Transmitter Underrun Error (TUE) bits are cleared by reading this register, followed by
a read of the SRX register (to clear ROE), or a write to the STX register (to clear TUE).
SCSR
Addr
0x00218008
SSI Control/Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
SYS_CLK_
EN
TYPE
13
I2S_MODE
12
11
10
9
8
SYN
NET
RE
TE
SSI_EN
RDR TDE ROE TUE TFS RFS RFF TFE
rw
rw
rw
rw
rw
rw
rw
rw
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
RESET
0x0041
Table 24-7. SSI Control/Status Register Description
Name
Reserved
Bits 31–16
Description
Settings
Reserved—These bits are reserved and should read 0.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-15
Programming Model
Table 24-7. SSI Control/Status Register Description (continued)
Name
Description
Settings
SYS_CLK_EN
Bit 15
System Clock Enable—Determines whether the input clock PerCLK3 is
output as SYS_CLK on the SSI_RXCLK pin. When SYS_CLK_EN is set,
PerCLK3 is output on the SRCK pin if the network mode, synchronous
mode, and transmit internal clock mode bits are also set. The timing
relationship between SYS_CLK and the internal serial bit clock is
controlled by the STCCR and/or SRCCR registers.
0 = SYS_CLK is not output
on the SSI_RXCLK pin
1 = SYS_CLK is output on
the SSI_RXCLK pin
I2S_MODE
Bits 14–13
I2S Mode Select—Determines whether the SSI operates in normal mode,
I2S master mode, or I2S slave mode.
See Section 24.3.7.1, “I2S
Mode Selection.”
SYN
Bit 12
Synchronous Mode—Enables/Disables the synchronous mode of
operation. In synchronous mode, the transmit and receive sections share
a common clock pin (SSI_TXCLK) and frame sync pin (SSI_TXFS).
0 = Disable synchronous
mode
1 = Enable synchronous
mode
NET
Bit 11
Network Mode—Selects the operational mode of the SSI. See
Section 24.5.2, “Network Mode,” for more information on Network Mode.
0 = Normal mode
1 = Network mode
RE
Bit 10
Receive Enable—Enables/Disables the receive portion of the SSI. When
disabled data transfers into the SRX register/receive FIFO are inhibited. If
data is being received when the RE bit is disabled, the rest of the word is
ignored. If the RE bit is re-enabled before the second-to-last bit of the
same word is received, the word is received.
0 = Disable SSI receive
1 = Enable SSI receive
TE
Bit 9
Transmit Enable—Enables/Disables the transfer of the contents of the
STX register to the TXSR. When the TE bit is set and a word boundary is
detected, the transmit portion of the SSI is enabled. When the TE bit is
cleared, the transmitter continues to send the data currently in the TXSR
and then disables the transmitter. The serial output is disabled and any
data present in the STX register is not transmitted.
0 = Disable SSI transmit
1 = Enable SSI transmit
Data can be written to the STX register with the TE bit cleared. The TDE
bit is cleared, however data is not transferred to the TXSR. When the TE
bit is cleared and then set again during the same transmitted word, the
data continues to be transmitted. When the TE bit is set again during a
different time slot, data is not transmitted until the next word boundary.
The normal transmit enable sequence is to write data to the STX register
or to the SSI Time Slot Register (STSR) before setting the TE bit. The
normal transmit disable sequence is to clear the TE bit and the TIE bit in
the STCR after the TDE bit is set.
When an internal gated clock is used, the gated clock runs during valid
time slots when the TE bit is set. When the TE bit is cleared, the
transmitter continues to send the data currently in the TXSR until the
TXSR register is empty, then the clock stops. When the TE bit is set again,
the gated clock starts immediately and runs during any valid time slots.
MC9328MXS Reference Manual, Rev. 1.1
24-16
Freescale Semiconductor
Programming Model
Table 24-7. SSI Control/Status Register Description (continued)
Name
SSI_EN
Bit 8
Description
SSI Enable—Enables/Disables the SSI. The SSI Enable bit must be set
prior to setting other bits.
Settings
0 = Disable the SSI
1 = Enable the SSI
When the SSI is set up for internal frame sync, enabling causes an output
frame sync to be generated. When the SSI is set up for external frame
sync, enabling causes the SSI to wait for the input frame sync. When the
SSI is disabled, the SSI_TXCLK, SSI_TXFS, and SSI_TXFS pins are
tri-stated, the status register bits hold their reset value, and all internal
clocks are disabled (other than clocking for register access).
Reset the SSI by clearing the SSI_EN bit. The contents of the transmit
FIFO and receive FIFO are cleared when the SSI_EN bit is reset.
RDR
Bit 7
Receive Data Ready—Indicates that the SRX register or the receive FIFO
contains a new value. It is automatically cleared when the CPU reads the
SRX register or when the receive FIFO (when enabled) is empty.
When the RIE bit in the SRCR is set, an interrupt occurs when the RDR bit
is set.
TDE
Bit 6
Transmit Data Register Empty—Indicates that no data is waiting to be
transferred to the TXSR. This occurs when the STX register is empty.
Because the STX register is the first word of the transmit FIFO, the TDE bit
is not set until the transmit FIFO is empty.
When the TDE bit is set and data is not written to the STX register or to the
SSI Time Slot Register (STSR) before the TXSR empties, an underrun
error occurs.
0 = SRX does not contain a
new value or the receive
FIFO is empty
1 = SRX or receive FIFO
contains a new value
0 = Data is waiting to be
transmitted (transferred
to the TXSR)
1 = No data is waiting to be
transmitted (transferred
to the TXSR)
To clear the TDE bit, write transmission data to the STX register or write
any data to the STSR register.
When the TIE bit in the STCR is set, an interrupt occurs when the TDE bit
is set.
ROE
Bit 5
Receive Overrun Error—Indicates when the RXSR is filled and ready to
transfer to the SRX register or the receive FIFO register (when enabled),
and these registers are already full. This is also indicated by the RFF and
Receive Data Ready (RDR) bits of this register.
When ROE is set, the contents of the RXSR are not transferred. However,
when the ROE bit is set, it causes a change in the interrupt vector used,
allowing the use of a different interrupt handler for a receive overrun
condition. When a receive interrupt occurs with the ROE bit set, the
Receive Data with Exception interrupt is generated. When a receive
interrupt occurs with the ROE bit cleared, the Receive Data interrupt is
generated.
0 = SRX and/or receive FIFO
can hold more data
1 = RXSR is ready to transfer
data, however SRX
and/or receive FIFO is
full
ROE is cleared by reading this register, and then reading the SRX register.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-17
Programming Model
Table 24-7. SSI Control/Status Register Description (continued)
Name
TUE
Bit 4
Description
Settings
Transmitter Underrun Error—Indicates that the TXSR is empty AND a
transmit time slot occurs. The TDE bit in this register indicates the first
condition. When a transmit underrun error occurs, the data that was in the
TXSR is retransmitted.
0 = TXSR is empty and no
transmit time slot has
occurred OR the TXSR
is not empty
1 = TXSR is empty and a
transmit time slot has
occurred
In normal mode, a transmit time slot occurs when the frame sync is
asserted. In network mode, each time slot requires data transmission and
is a transmit time slot (TE = 1).
When the TUE bit is set, there is no data transferred to the TXSR.
However, the TUE bit does cause a change in the interrupt vector used for
transmit interrupts so that a different interrupt handler can be used for a
transmit underrun condition. When a transmit interrupt occurs with the
TUE bit set, the Transmit Data with Exception interrupt is generated. When
a transmit interrupt occurs with the TUE bit cleared, the Transmit Data
interrupt is generated.
TUE is cleared by reading this register, and then writing to the STX
register or to the SSI Time Slot Register (STSR).
TFS
Bit 3
Transmit Frame Sync—Indicates that a frame sync occurred during
transmission of the last word written to the STX register.
Data written to the STX register during the time slot when the TFS bit is set
is sent during the second time slot (in network mode) or in the next first
time slot (in normal mode). In network mode, the TFS bit is set during
transmission of the first slot of the frame. It is then cleared when starting
transmission of the next slot.
RFS
Bit 2
Receive Frame Sync—Indicates that a frame sync occurred when
receiving a word into the SRX register.
In network mode, the RFS bit is set when the first slot of the frame is being
received. It is cleared when the next slot of the frame begins to be
received.
RFF
Bit 1
Receive FIFO Full—Indicates that the data level in the receive FIFO
reaches the Receive FIFO Full Water Mark. The Water Mark is defined in
the RFWM field of the SSI FIFO Control/Status Register (SFCSR). The
receive FIFO must be enabled or RFF is meaningless.
When RFF is set, data can be read from the receive FIFO via the SRX
register. When the RX FIFO has received 8 bytes of data, all further
received data is ignored until the data is read out of the receive FIFO.
0 = No frame sync occurred
during transmission
1 = A frame sync occurred
during transmission
0 = No frame sync occurred
when receiving
1 = A frame sync occurred
when receiving
0 = Data level in the receive
FIFO exceeds Water
Mark level
1 = Data level in receive
FIFO reaches Water
Mark
Note: An interrupt is generated only when both the RFF and RIE bits in
the SRCR are set and the receive FIFO (the RFEN bit in the SRCR) is
enabled.
MC9328MXS Reference Manual, Rev. 1.1
24-18
Freescale Semiconductor
Programming Model
Table 24-7. SSI Control/Status Register Description (continued)
Name
TFE
Bit 0
Description
Settings
Transmit FIFO Empty—Indicates that the data level in the transmit FIFO
reaches the Transmit FIFO Empty Water Mark. The Water Mark is defined
in the TFWM field of the SSI FIFO Control/Status Register (SFCSR). The
transmit FIFO must be enabled or TFE is meaningless.
0 = Data level in the transmit
FIFO exceeds Water
Mark
1 = Data level in the transmit
FIFO below Watermark
When TFE is set, data can be written to the transmit FIFO via the STX
register.
Note: An interrupt is generated only when both the TFE and TIE (of the
STCR) are set and the transmit FIFO is enabled (the TFEN bit in the
STCR is set).
24.3.7.1 I2S Mode Selection
The SSI is able to emulate certain features of the I2S standard. Both early frame sync and 1-word-wide frame sync
are supported. Data can be up to 16-bits per channel. However, dummy clocks are not supported. If the data is
16-bit and there are 2 channels per frame, the number of bit clock should be exactly 32. Use of dummy clocks is
forbidden.
The SCSRcontains two bits, the I2S Mode Select (I2S MODE1 and I2S MODE0) bits, that determine the mode of
the SSI module. This section explains how the mode of the module affects the bits in the other SSI registers.
Table 24-8 summarizes the mode settings.
Table 24-8. I2S Mode Selection
I2S_MODE [1]
I2S_MODE [0]
Remark
0
0
Normal mode
0
1
I2S master mode
1
0
I2S slave mode
1
1
Normal mode
In normal mode operation, no register bits are forced to any particular state internally and the SSI can be
programmed to work in any operating condition.
When entering I2S modes (I2S master or I2S slave), several control bits are fixed in the hardware. Attempts to write
to these bits when in I2S master or I2S slave mode are ignored. These bits are described in Table 24-9.
The user must configure the bit clock in the STCCR and the SRCCR.
Table 24-9. I2S Master or I2S Slave Mode Settings
I2S Mode
Bit
Name
Register
Location
Forced
Value
Master or slave
SYN
SCSR [12]
1
Synchronous mode enabled
Master or slave
NET
SCSR [11]
1
Network mode enabled
Function
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-19
Programming Model
Table 24-9. I2S Master or I2S Slave Mode Settings (continued)
I2S Mode
Bit
Name
Register
Location
Forced
Value
Master or slave
TSHFD
STCR [4]
0
Transmission direction is MSB first
Master or slave
RSHFD
SRCR [4]
0
Receive direction is MSB first
Master or slave
TSCKP
STCR [3]
1
Falling edge of bit clock clocks data out
Master or slave
RSCKP
SRCR [3]
1
Rising edge of bit clock clocks data in
Master or slave
TFSI
STCR [2]
1
Transmit frame sync is active low
Master or slave
RSFI
SRCR [2]
1
Receive frame sync is active low
Master or slave
TFSL
STCR [1]
0
Transmit frame sync length is 1 word
Master or slave
RFSL
SRCR [1]
0
Receive frame sync length is 1 word
Master or slave
TEFS
STCR [0]
1
Transmit frame sync initiated sync one bit-clock before transmission
Master or slave
REFS
SRCR [0]
1
Receive frame sync initiated one bit-clock before receive
Master
TXDIR
STCR [5]
1
Clock source is generated internally bit clock
Master
TFDIR
STCR [6]
1
Transmit frame sync is generated internally
Slave
TXDIR
STCR [5]
0
Clock source is externally generated bit clock
Slave
TFDIR
STCR [6]
0
Transmit frame sync is generated externally
Function
When the SSI is configured as an I2S master, the external codec may require an oversampling clock in addition to
the sampling rate frequency and bit clock. This oversampling clock is usually required to be 256 times the
sampling frequency.
As an example, if a sampling frequency of 44.1 kHz was required, and the word length was set to 16-bits. Then a
frame sync would be 2×16 = 32 bit clocks. This makes the bit clock frequency 1.4112 MHz.
The frequency ratios that must hold would be the following:
SYS_CLK (PerCLK3) = 256 × Frame Sync
Eqn. 24-1
Frame_Sync = Bit Clock / 32
Eqn. 24-2
SYS_CLK (PerCLK3) = 8 × Bit Clock
Eqn. 24-3
Therefore,
If the divide ratio is set to 8—that is, PM = 1 and PSR = 0, SYS_CLK_EN is set, the module is in I2S master mode
and the incoming frequency of PerCLK3 is 11.2896 MHz, then SYS_CLK will meet the requirements. The
external codec will not need a crystal oscillator for clocking.
MC9328MXS Reference Manual, Rev. 1.1
24-20
Freescale Semiconductor
Programming Model
24.3.8 SSI Transmit Configuration Register
The SSI Transmit Configuration Register (STCR) controls the transmit operation of the SSI. This register controls
the frame synchronization signal, clocking, and data direction. It also contains enables for the DMA, transmit
FIFO, and the transmit interrupt.
As with all on-chip peripheral interrupts for the MC9328MXS, the STCR must first be set to enable maskable
interrupts. Next, the AITC (ARM9 Interrupt Controller) is configured to handle the SSI interrupts. For example,
the SSI interrupt bits (bits 45 through 42) in the AITC’s Interrupt Enable High Register (INTENABLEH) must be
set to enable the interrupt. Also be sure to enable interrupts to the core (either the IRQ or FIQ interrupts). After all
of these steps are completed, an interrupt is generated when any of the desired transmit status bits of the SCSR
(TDE, TUE, TFS, or TFE) are set.
NOTE:
SSI reset does not affect the STCR bits. Power-on-reset clears all STCR bits.
STCR
BIT
TYPE
Addr
0x0021800C
SSI Transmit Configuration Register
31 30 29 28 27
26
25
24
23
22
21
20
19
18
17
16
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
TYPE
15 14 13 12 11
10
9
8
7
6
5
4
3
2
1
0
TXBIT0
TDMAE
TIE
TFEN
TFDIR
TXDIR
TSHFD
TSCKP
TFSI
TFSL
TEFS
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 24-10. SSI Transmit Configuration Register Description
Name
Description
Reserved
Bits 31–11
Reserved—These bits are reserved and should read 0.
TXBIT0
Bit 10
Transmit Bit0—This bit determines which bit in the Transmit Shift Register
(TXSR) triggers the TXSR to transmit its data word. By default, shifting of
data is triggered by bit position 15 of TXSR. The shifting data direction (MSB
or LSB bit transmitted first) is controlled by the TSHFD bit.
Settings
0 = Bit position 15 of TXSR
triggers transfer
1 = Bit position 0 of TXSR
triggers transfer
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-21
Programming Model
Table 24-10. SSI Transmit Configuration Register Description (continued)
Name
TDMAE
Bit 9
Description
Settings
Transmit DMA Enable—Enables DMA requests to be issued when certain
conditions are met.
0 = No DMA request issued
1 = DMA request issued
When the transmit FIFO is enabled and the TDMAE bit is set, a DMA request
is issued when the TFE bit in the SCSR is set.
When the transmit FIFO is disabled and the TDMAE bit is set, a DMA
request is issued when the TDE bit in the SCSR is set.
The TIE bit (in this register) has higher priority than the TDMA bit. When TIE
is set, an interrupt is generated to the CPU instead of the DMA.
TIE
Bit 8
Transmit Interrupt Enable—Enables/Disables the transmit interrupt when
certain conditions are met. TIE works with the Transmit Enable (TE) bit in the
SCSR.
0 = Transmit interrupt
disabled
1 = Transmit interrupt
enabled
When the transmit FIFO is enabled and the TIE and TE bits are both set, an
interrupt occurs when the TFE bit in the SCSR register is set.
When the transmit FIFO is disabled and the TIE and TE bits are both set, an
interrupt occurs when the TDE bit in the SCSR register is set.
Two transmit data interrupts with separate interrupt vectors are available:
transmit data with exception status and transmit data without exceptions.
Table 24-11 shows the conditions that generate these interrupts and lists the
interrupt vectors.
TFEN
Bit 7
Transmit FIFO Enable—Enables/Disables the transmit FIFO. When the
transmit FIFO is enabled, a maximum of 8 values are written to the STX
register at a time. These values are then transmitted out first-in–first-out.
When the transmit FIFO is disabled, only one value is written to the STX
register at a time.
0 = Transmit FIFO disabled
1 = Transmit FIFO enabled
TFDIR
Bit 6
Transmit Frame Direction—Selects the direction and source of the transmit
frame sync signal. When the TFDIR bit is set, the frame sync is generated
internally and output to the SSI_TXFS pin (if not configured as GPIO). When
the TFDIR bit is cleared, the transmit frame sync is supplied from an external
source. Table 24-14 shows the clock pin configuration.
0 = Frame sync generated
externally
1 = Frame sync generated
internally
TXDIR
Bit 5
Transmit Direction—Selects the direction and source of the clock signal
that clocks the TXSR. When the TXDIR bit is set, the clock is generated
internally and output to the SSI_TXCLK pin (if not configured as GPIO).
When the TXDIR bit is cleared, the clock source is external, the internal clock
generator is disconnected from the SSI_TXCLK pin, and an external clock
source can drive this pin to clock the TXSR.
0 = External source must
drive SSI_TXCLK pin
1 = Clock generated
internally and output to
SSI_TXCLK pin
TSHFD
Bit 4
Transmit Shift Direction—Controls whether the MSB or LSB is transmitted
first for the transmit section.
0 = MSB transmitted first
1 = LSB transmitted first
Note: The codec device labels the MSB as bit 0, however the
MC9328MXS labels the LSB as bit 0. When using a standard codec, the
MC9328MXS MSB (or codec bit 0) is shifted out first, and the TSHFD bit is
cleared.
MC9328MXS Reference Manual, Rev. 1.1
24-22
Freescale Semiconductor
Programming Model
Table 24-10. SSI Transmit Configuration Register Description (continued)
Name
Description
Settings
TSCKP
Bit 3
Transmit Clock Polarity—Controls the bit clock edge that clocks out data
for the transmit functions.
0 = Rising edge of clock
clocks data out
1 = Falling edge of clock
clocks data out
TFSI
Bit 2
Transmit Frame Sync Invert—Selects the logic of the transmit frame sync
I/O.
0 = Active high
1 = Active low
TFSL
Bit 1
Transmit Frame Sync Length—Selects the length of the frame sync signal
to be generated or recognized. When the word-long frame sync is selected,
this frame sync length is determined by the WL field of the STCCR.
0 = Frame sync is 1 word
long
1 = Frame sync is 1 bit-clock
long
TEFS
Bit 0
Transmit Early Frame Sync—Controls when the frame sync is initiated for
the transmit section. The frame sync is disabled after one bit for bit-length
frame sync and after one word for word-length frame sync (based on the
TFSL bit of this register).
0 = Frame sync is initiated
with first data bit
transmission
1 = Frame sync is initiated
one bit-clock before
transmission starts
Table 24-11. SSI Transmit Data Interrupts
Interrupt Source
Register High1
TIE
TUE
TFE/TDE
Transmit Data with Exception
Bit 11 (IN43)
1
1
1
Transmit Data Without Exception
Bit 10 (IN42)
1
0
1
Interrupt
1.
Refer to Chapter 10, “Interrupt Controller (AITC),” for more information about interrupts.
24.3.9 SSI Receive Configuration Register
The SSI Receive Configuration Register (SRCR) controls the receive operation of the SSI—which controls the
frame synchronization signal, clocking, and data direction configurations. It also contains enables for the DMA,
receive FIFO, and the receive interrupt settings.
As with all on-chip peripheral interrupts for the MC9328MXS, the SRCR must first be set to enable maskable
interrupts. Next, the AITC (ARM9 Interrupt Controller) is configured to handle the SSI interrupts. For example,
the SSI interrupt bits (bits 45 through 42) in the AITC’s Interrupt Enable High Register (INTENABLEH) must be
set to enable the interrupt. Also be sure to enable interrupts to the core (either the IRQ or FIQ interrupts). When all
of these steps are complete, then an interrupt is generated when any of the desired transmit status bits of the SCSR
(RDR, ROE, RFS, or RFF) are set.
NOTE:
An SSI reset does not affect the bits in the SRCR register. Power-on-reset clears all
SRCR register bits.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-23
Programming Model
SRCR
Addr
0x00218010
SSI Receive Configuration Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RFDIR
RXDIR
RSHFD
RSCKP
RESET
0x0000
BIT
15
TYPE
14
13
12
11
10
9
RXBIT0
RDMAE
8
7
RIE RFEN
RFSI RFSL
REFS
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 24-12.
Name
SSI Receive Configuration Register Description
Description
Settings
Reserved
Bits 31–11
Reserved—These bits are reserved and should read 0.
RXBIT0
Bit 10
Receive Bit 0—This bit determines which bit in the Receive Shift Register
(RXSR) triggers the RXSR to transmit its data word. By default, shifting of data
is triggered by bit position 15 of TXSR. The shifting data direction (MSB or LSB
bit transmitted first) is controlled by the RSHFD bit.
0 = Bit position 15 of RXSR
triggers transfer
1 = Bit position 0 of RXSR
triggers transfer
RDMAE
Bit 9
Receive DMA Enable—Enables DMA requests to be issued when certain
conditions are met.
0 = No DMA request issued
1 = DMA request issued
When the receive FIFO is enabled and the RDMAE bit is set, a DMA request is
issued when the RFF bit in the SCSR is set.
When the receive FIFO is disabled and the RDMAE bit is set, a DMA request is
issued when the RDR bit in the SCSR is set.
The RIE bit (in this register) has higher priority than the RDMAE bit. When the
RIE bit is set, an interrupt is generated to the CPU instead of the DMA.
MC9328MXS Reference Manual, Rev. 1.1
24-24
Freescale Semiconductor
Programming Model
Table 24-12.
Name
RIE
Bit 8
SSI Receive Configuration Register Description (continued)
Description
Receive Interrupt Enable—Enables/Disables the receive interrupt when
certain conditions are met. The RIE bit works with the RE bit in the SCSR.
Settings
0 = Disable transmit interrupt
1 = Enable transmit interrupt
When the receive FIFO is enabled and the RIE and RE bits are both set, an
interrupt occurs when the RFF bit in the SCSR is set.
When the receive FIFO is disabled and the RIE and RE bits are both set, an
interrupt occurs when the RDR bit in the SCSR is set.
Two receive data interrupts with separate interrupt vectors are available,
Receive Data with Exception and Receive Data Without Exception. Table 24-13
on page 24-26 shows the conditions that generate these interrupts and lists the
interrupt vectors.
RFEN
Bit 7
Receive FIFO Enable—Enables/Disables the receive FIFO. When the receive
FIFO is enabled, a maximum of 8 values can be received by the SSI without
losing data. A ninth value can be received into the RXSR, however it is not
transferred to the receive FIFO. When the receive FIFO is disabled, only one
value can be received into the SRX register (that value must be read out before
another value can be transferred in from the RXSR).
0 = Disable receive FIFO
1 = Enable transmit FIFO
RFDIR
Bit 6
Receive Frame Direction—Selects the direction and source of the receive
frame sync signal. When the RFDIR bit is set, the frame sync is generated
internally and output to the SSI_RXFS pin (if not configured as a GPIO). When
the RFDIR bit is cleared, the receive frame sync is supplied from an external
source.
0 = Receive frame sync
generated externally
1 = Receive frame sync
generated internally
RXDIR
Bit 5
Receive Direction—Selects the direction and source of the clock signal that
clocks the RXSR. When the RXDIR bit is set, the clock is generated internally
and output to the SSI_RXCLK pin (if not configured as a GPIO). When the
RXDIR bit is cleared, the internal clock generator is disconnected from the
SSI_RXCLK pin so an external clock source can drive this pin to clock the
RXSR. Table 24-14 on page 24-26 shows the clock pin configuration.
0 = External source drives
SSI_RXCLK pin
1 = Clock generated
internally and output to
SSI_RXCLK pin
RSHFD
Bit 4
Receive Shift Direction—Controls whether the MSB or LSB is received first.
0 = MSB received first
1 = LSB received first
RSCKP
Bit 3
Receive Clock Polarity—Controls the bit clock edge that latches in data.
0 = Falling edge of clock
latches data in
1 = Rising edge of clock
latches data in
RFSI
Bit 2
Receive Frame Sync Invert—Selects the logic of the receive frame sync I/O.
0 = Active high
1 = Active low
RFSL
Bit 1
Receive Frame Sync Length—Selects the length of the frame sync signal to
be generated or recognized. When the word-long frame sync is selected, this
frame sync length is determined by the WL field of the SRCCR.
0 = Frame sync is 1 word
long
1 = Frame sync is 1 bit-clock
long
Note: The codec device labels the MSB as bit 0, whereas the MC9328MXS
labels the LSB as bit 0. When using a standard codec, the MC9328MXS MSB
(or codec bit 0) is shifted in first, and the RSHFD bit is cleared.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-25
Programming Model
Table 24-12.
SSI Receive Configuration Register Description (continued)
Name
Description
REFS
Bit 0
Settings
Receive Early Frame Sync—Controls when the frame sync is initiated for the
receive section. The frame sync is disabled after one bit for bit-length frame
sync and after one word for word-length frame sync (based on the RFSL bit of
this register).
0 = Frame sync is initiated
with first data bit
received
1 = Frame sync is initiated
one bit-clock before
data received
Table 24-13. SSI Receive Data Interrupts
Interrupt Source
Register High1
RIE
ROE
RFF/RDR
Receive Data with Exception
Bit 13 (IN45)
1
1
1
Receive Data Without Exception
Bit 12 (IN44)
1
0
1
Interrupt
1.
Refer to Chapter 10, “Interrupt Controller (AITC),” for more information about interrupts.
Table 24-14. Clock Pin Configuration
SYN
RXDIR
TXDIR
RFDIR
TFDIR
SSI_RXFS
SSI_TXFS
SSI_RXCLK
SSI_TXCLK
Asynchronous Mode1
0
0
0
0
0
Receive
Frame Sync
(RFS) in
Transmit
Frame Sync
(TFS) in
Receive Clock
(RCK) in
Transmit Clock
(TCK) in
0
0
1
0
1
RFS in
TFS out
RCK in
TCK out
0
1
0
1
0
RFS out
TFS in
RCK out
TCK in
0
1
1
1
1
RFS out
TFS out
RCK out
TCK out
Synchronous Mode2
1
0
0
x
0
GPIO
TFS in
GPIO
TCK in
1
0
1
x
1
GPIO
TFS out
GPIO
TCK out
1
1
0
x
x
GPIO
GPIO
GPIO
Gated Clock in
1
1
1
x
x
GPIO
GPIO
GPIO
Gated Clock out
1.
2.
See Figure 24-14 on page 24-36.
See Figure 24-15 on page 24-37.
MC9328MXS Reference Manual, Rev. 1.1
24-26
Freescale Semiconductor
Programming Model
24.3.10 SSI Transmit Clock Control Register and SSI Receive Clock Control
Register
The SSI Transmit Clock Control Register (STCCR) and SSI Receive Clock Control Register (SRCCR) control the
clocks for the SSI. These registers control the prescaler, word length, and frame rate for the transmit and receive
clocks. The fields of this register control the dividers that generate the serial bit clock, the word clock and the frame
clock from the PerCLK3 input. See Section 24.3.10.1, “Calculating the SSI Bit Clock from the Input Clock Value,”
for detailed information on clock values.
The STCCR is dedicated to the transmit section, and the SRCCR register is dedicated to the receive section (except
in synchronous mode, when the STCCR controls both the receive and transmit sections). The bit structure for both
registers is identical, however they are two distinct registers and must be individually programmed.
NOTE:
SSI reset does not affect the STCCR and SRCCR bits. Power-on reset clears all
STCCR and SRCCR bits.
STCCR
SRCCR
Addr
0x00218014
0x00218018
SSI Transmit Clock Control Register
SSI Receive Clock Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
PSR
TYPE
13
12
11
WL
10
9
8
7
DC
PM
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 24-15. SSI Transmit Clock Control Register and SSI Receive Clock Control Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
PSR
Bit 15
Prescaler Range—Selects whether the fixed divide-by-eight prescaler will be
used to generate the serial bit clock. See Figure 24-4. Using this prescaler
allows a 128 kHz master clock to be generated for Motorola MC1440x series
codecs.
Settings
0 = Bypass divide-by-eight
prescaler
1 = Use divide-by-eight
prescaler
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-27
Programming Model
Table 24-15. SSI Transmit Clock Control Register and SSI Receive Clock Control Register Description
Name
Description
Settings
WL
Bits 14–13
Word Length—Selects the length (8, 10, 12, or 16 bits) of the data words
being transferred by the SSI. WL also controls the frame sync pulse length
when the length of the frame sync (SRCR:RFSL or STCR:TFSL) is set to 1
word. The value of this field is used as a divider value to convert serial bit clock
to word clock as shown in Figure 24-4.
00 = 8 Bits per word
01 = 10 Bits per word
10 = 12 Bits per word
11 = 16 Bits per word
DC
Bits 12–8
Frame Rate Divider Control—Specifies the divide ratio for the programmable
frame rate divider shown in Figure 24-5. The divider converts the word clock to
the frame clock. In normal mode, this ratio determines the word transfer rate. In
network mode, this ratio sets the number of words per frame.
00000 = Divide Ratio is 1
00001 = Divide Ratio is 2
…
11111 = Divide Ratio is 32
In network mode, a divide ratio of one (DC = 00000) is a special case
(on-demand mode).
In network mode,
DC = 00000 is a special
case.
In normal mode, a divide ratio of one (DC = 00000) provides continuous
periodic data word transfer (a bit-length sync must be used).
PM
Bits 7–0
Prescale Modulus Select—Specifies the divide ratio for the modulus divider
shown in Figure 24-4. This divider is one of three dividers that convert the
PerCLK3 signal to the serial bit clock.
0x00 = Divide ratio is 1
0x01 = Divide ratio is 2
...
0xFF = Divide ratio is 256
24.3.10.1 Calculating the SSI Bit Clock from the Input Clock Value
The serial bit clock is the result of the Clock Controller input PerCLK3 being divided by one fixed, one selectable,
and one programmable divider. Serial bit clock may range from the value (PerCLK3 / 4×1×1) to (PerCLK3 /
(4×8×256)). See Figure 24-4 on page 24-5. Note that WL has a value of 8, 10, 12, or 16.
fINT_BIT_CLK = fPerCLK3 ÷ [4 x (7 x PSR + 1) x (PM + 1)]
Eqn. 24-4
fFRAME_SYN_CLK = (fINT_BIT_CLK) ÷ [(DC + 1) x WL]
Eqn. 24-5
Example 1: When the 7-bit clock controller divider, PCLKDIV3 in the PLL and Clock Control module, is set to 5,
then PerCLK3 is 96 MHz ÷ 5 = 19.2 MHz.
The SSI is set up in normal mode with a word length of 8 (WL = 00), a frame rate divider control of 1 (DC = 0001),
a prescale modulus of 74 (decimal) (PM = 01001010), and the PSR bit cleared (PSR = 0).
In this case, the bit clock rate is 19.2 MHz ÷ (4 × 1 × 75) = 64 kHz.
That means that the frame sync clock (SSI_TXFS) is 64 kHz ÷ (2 × 8) = 4 kHz.
Example 2: When the 7-bit clock controller divider, PCLKDIV3, is set to 8, then PerCLK3 is 96 MHz ÷ 8 = 12
MHz.
The SSI is set up in network mode, with a word length of 16 (WL = 11), a frame rate divider control of 1 (DC =
0001), a prescale modulus of 1 (decimal) (PM = 00000001), and the PSR bit cleared (PSR = 0).
In this case, the bit clock rate is 12 MHz ÷ (4 × 1 × 2) = 1.5 MHz.
That means that the frame sync clock (SSI_TXFS) is 1.5 MHz ÷ (2 × 16) = 46.875 kHz.
Table 24-16 shows various combinations of the PSR and PM fields that achieve different bit clock frequencies.
MC9328MXS Reference Manual, Rev. 1.1
24-28
Freescale Semiconductor
Programming Model
Table 24-16. SSI Bit and Frame Clock as a Function of PSR and PM in Normal Mode
System PLL output
in the clock
Controller Module
(MHz)
System Clock
Divider
PCLKDIV3
(7 Bit)
PerCLK3
(MHz)
Input to
the SSI
Module
PSR
(0 or 1)
96
15
6.4
96
10
96
PM [7:0]
Actual Bit_Clk
Frequency (kHz)
SSI_TXCLK,
SSI_RXCLK
Ideal Bit_Clk
Frequency (kHz)
1
24(0x18)
8.0
8.0
9.6
1
24(0x18)
12.0
12.0
20
4.8
0
74(0x4A)
16.0
16.0
96
5
19.2
0
74(0x4A)
64.0
64.0
96
5
19.2
0
37(0x25)
126.3
128.0
96
2
48.0
0
46(0x2E)
255.3
256.0
96
1
96.0
0
46(0x2E)
510.6
512.0
96
1
96.0
0
23(0x0F)
1000.0
1024
96
1
96.0
0
11(0x0B)
2000.0
2048
96
1
96.0
0
5(0x05)
4000.0
4096
Table 24-17 shows the effect of changing the clock controller divider value to generate SYS_CLK and bit clock
frequencies close to the ideal. In these examples, master mode was selected by setting the I2S Mode Select
(I2S_MODE1 and I2S_MODE0) bits in the SCSR to 01, or individually programming the SSI into network,
synchronous, and transmit internal modes.
Table 24-17. SSI Sys, Bit and Frame Clock in Master Mode
Ideal
Sampling
Rate
(kHz)
Ideal
Bit Clock
Frequency
(kHz)
Ideal
SYS_CLK
Frequency
(MHz)
CRM Clock
Controller
Divider
Value
(with 96
MHz input)
8.0
256.0
2.048
11.025
352.8
16.00
PerCLK3
(MHz)
Actual
SYS_CLK
Frequency
(MHz)
SSI_RXCLK
Actual
Bit Clock
Frequency
(kHz)
SSI_TXCLK
Actual
Sampling
Rate
(kHz)
SSI_TXFS
47
2.043
2.043
255.32
7.98
2.822
32
3.000
3.000
375.00
11.72
512.0
4.096
23
4.173
4.173
510.64
15.96
22.05
705.6
5.644
17
5.647
5.647
705.88
22.06
32.00
1024.0
8.192
12
8.000
8.000
1000.0
31.25
44.10
1411.0
11.289
9
10.677
10.677
1334.63
41.71
48.00
1536.0
12.288
8
12.000
12.000
1500.00
48.88
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-29
Programming Model
24.3.11 SSI Time Slot Register
The write-only SSI Time Slot Register (STSR) is used when data should not be transmitted in an available transmit
time slot. For the purposes of timing, the time slot register behaves like an alternate transmit data register. Instead
of transmitting data, the SSI_TXDAT pin is either tri-stated or pulled high, depending on the setting for that pin in
the Pull-Up Enable Register in the GPIO Module. Using this register is important for avoiding overflow/underflow
during inactive time slots.
STSR
Addr
0x0021801C
SSI Time Slot Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DUMMY
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 24-18. SSI Time Slot Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
DUMMY
Bits 15–0
Dummy Bits—Holds data that is not intended for transmission. This register can be used during
inactive time slots.
MC9328MXS Reference Manual, Rev. 1.1
24-30
Freescale Semiconductor
Programming Model
24.3.12 SSI FIFO Control/Status Register
The SSI FIFO Control/Status Register (SFCSR) tracks the number of data words held in the transmit and receive
FIFOs and holds the Water Mark levels for each FIFO. The Water Mark is a user-defined value that determines
when the RFF and TFE bits in the SCSR are set.
SFCSR
Addr
0x00218020
SSI FIFO Control/Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
RFCNT
TYPE
9
8
TFCNT
RFWM
TFWM
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
RESET
0X0081
Table 24-19. SSIFIFO Control/Status Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
RFCNT
Bits 15–12
Receive FIFO
Counter—Indicates how many
data words are in the receive
FIFO. This count does not
include words that are being
received or were received into
the RXSR_1 yet not transferred
to the receive FIFO.
0000 = 0 data words in the receive FIFO
0001 = 1 data word in the receive FIFO
0010 = 2 data words in the receive FIFO
0011 = 3 data words in the receive FIFO
0100 = 4 data words in the receive FIFO
0101 = 5 data words in the receive FIFO
0110 = 6 data words in the receive FIFO
0111 = 7 data words in the receive FIFO
1000 = 8 data words in the receive FIFO
All other settings reserved
TFCNT
Bits 11–8
Transmit FIFO
Counter—Indicates how many
data words are in the transmit
FIFO. This count does not
include words that were
transferred to the TXSR.
0000 = 0 data words in the transmit FIFO
0001 = 1 data word in the transmit FIFO
0010 = 2 data words in the transmit FIFO
0011 = 3 data words in the transmit FIFO
0100 = 4 data words in the transmit FIFO
0101 = 5 data words in the transmit FIFO
0110 = 6 data words in the transmit FIFO
0111 = 7 data words in the transmit FIFO
1000 = 8 data words in the transmit FIFO
All other settings reserved
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-31
Programming Model
Table 24-19. SSIFIFO Control/Status Register Description (continued)
Name
Description
Settings
RFWM
Bits 7–4
Receive FIFO Full
Water Mark—
Specifies the Receive FIFO
Water Mark. When the data
level of the receive FIFO
reaches the Water Mark level,
the RFF bit in the SCSR register
is set.
0000 = Reserved
0001 = RFF sets when at least one data word is written to the receive FIFO
(RFCNT = 1, 2, 3, 4, 5, 6, 7, 8 data words)
0010 = RFF sets when 2 or more data words are written to the receive FIFO
(RFCNT = 2, 3, 4, 5, 6, 7, 8 data words)
0011 = RFF sets when 3 or more data words are written to the receive FIFO
(RFCNT = 3, 4, 5, 6, 7, 8 data words)
0100 = RFF sets when 4 or more data words are written to the receive FIFO
(RFCNT = 4, 5, 6, 7, 8 data words)
0101 = RFF sets when 5 or more data words are written to the receive FIFO
(RFCNT = 5, 6, 7, 8 data words)
0110 = RFF sets when 6 or more data words are written to the receive FIFO
(RFCNT = 6, 7, 8 data words)
0111 = RFF sets when 7 or more data words are written to the receive FIFO
(RFCNT = 7, 8 data words)
1000 = RFF sets when exactly 8 data words are written to the receive FIFO
(RFCNT = 8 data words)
All other settings reserved
TFWM
Bits 3–0
Transmit FIFO Empty
Water Mark—
Specifies the Transmit FIFO
Water Mark. When the data
level of the transmit FIFO falls
below the Water Mark level, the
TFE bit in the SCSR register is
set.
0000 = Reserved
0001 = TFE sets when there are 1 or more empty slots in the transmit FIFO
(TFCNT = 7, 6, 5, 4, 3, 2, 1, 0 data words)
0010 = TFE sets when there are 2 or more empty slots in the transmit FIFO
(TFCNT = 6, 5, 4, 3, 2, 1, 0 data words)
0011 = TFE sets when there are 3 or more empty slots in the transmit FIFO
(TFCNT = 5, 4, 3, 2, 1, 0 data words)
0100 = TFE sets when there are 4 or more empty slots in the transmit FIFO
(TFCN = 4, 3, 2, 1, 0 data words)
0101 = TFE sets when there are 5 or more empty slots in the transmit FIFO
(TFCNT = 3, 2, 1, 0 data words)
0110 = TFE sets when there are 6 or more empty slots in the transmit FIFO
(TFCNT = 2, 1, 0 data words)
0111 = TFE sets when there are 7 or more empty slots in the transmit FIFO
(TFCNT = 1, 0 data words)
1000 = TFE sets when there are 8 empty slots are in the transmit FIFO
(TFCNT = 0 data words)
All other settings reserved
MC9328MXS Reference Manual, Rev. 1.1
24-32
Freescale Semiconductor
Programming Model
Table 24-20. Value of Transmit FIFO Empty (TFE) and Receive FIFO Full (RFF)
Transmit FIFO
Water Mark (TFWM)
or
Receive FIFO
Water Mark (RFWM)
Number of Data Words in TXFIFO
Number of Data Words in RXFIFO
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
1 (0001)
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
2 (0010)
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
3 (0011)
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
4 (0100)
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
5 (0101)
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
6 (0110)
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
7 (0111)
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
8 (1000)
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-33
Programming Model
24.3.13 SSI Option Register
The SSI Option Register (SOR) allows the user to clear out the receive FIFO and/or the transmit FIFO, turn the
clock off when the SSI is disabled, and reset the frame synchronization and the state machine. This register also
includes a user-programmable field to set wait states.
SOR
Addr
0x00218028
SSI Option Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
CLK
OFF
TYPE
SYN
RST
RX_CLR TX_CLR
r
r
r
r
r
r
r
r
r
rw
rw
rw
r
r
r
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 24-21. SSI Option Register Description
Name
Description
Settings
Reserved
Bits 31–7
Reserved—These bits are reserved and should read 0.
CLKOFF
Bit 6
Clock Off—Turns off the clocks when the SSI is disabled to further
reduce power consumption.
0 = Clocks enabled when SSI
disabled
1 = Clocks disabled when SSI
disabled
RX_CLR
Bit 5
Receiver Clear—Controls whether the receive FIFO is flushed. The
transmit portion of the SSI is not affected. The software must clear
RX_CLR before the SSI transmitter can operate.
0 = No effect
1 = Clear receive FIFO
TX_CLR
Bit 4
Transmitter Clear—Controls whether the transmit FIFO is flushed. The
receiver portion of the SSI is not affected. The software must clear
TX_CLR before the SSI transmitter can operate.
0 = No effect
1 = Clear transmit FIFO
Reserved
Bits 3–1
Reserved—These bits are reserved and should read 0.
SYNRST
Bit 0
Frame Sync Reset—Resets the accumulation of data in the SRX register
and receive FIFO (RXFIFO) on frame synchronization.
0 = No effect
1 = Reset data accumulation
MC9328MXS Reference Manual, Rev. 1.1
24-34
Freescale Semiconductor
SSI Data and Control Pins
24.4 SSI Data and Control Pins
SSI has six I/O pins. The pins are shared with either Port B or Port C pins, depending on the configuration of the
ports. See Section 24.2.3, “Pin Configuration for SSI,” for more information. Each pin is described in detail in the
sections following Table 24-22.
Table 24-22. SSI Pin Description
Pin Description
Pin Name
Port C
Multiplexed Pin
Port B
Multiplexed Pin
Serial Transmit Data
SSI_TXDAT
PTC [6]
PTB [17]
Serial Receive Data
SSI_RXDAT
PTC [5]
PTB [16]
Serial Transmit Clock
SSI_TXCLK
PTC [8]
PTB [19]
Serial Receive Clock
SSI_RXCLK
PTC [4]
PTB [15]
Serial Transmit Frame Sync
SSI_TXFS
PTC [7]
PTB [18]
Serial Receive Frame Sync
SSI_RXFS
PTC [3]
PTB [14]
24.4.1 SSI_TXDAT, Serial Transmit Data
The SSI_TXDAT pin transmits data from the TXSR. While data is being transmitted, the SSI_TXDAT pin is an
output pin. This pin is disabled between data word transmissions and on the trailing edge of the bit clock after the
last bit of a word is transmitted. This pin has an internal pull-up controlled by the GPIO’s PUEN bit. For more
information, refer to the Chapter 25, “GPIO Module and I/O Multiplexer (IOMUX).”
24.4.2 SSI_RXDAT, Serial Receive Data
The SSI_RXDAT pin brings serial data into the SSI Receive Shift Register (RXSR).
24.4.3 SSI_TXCLK, Serial Transmit Clock
The SSI_TXCLK pin can be used as either an input or an output. This clock signal is used by the transmitter and
can be either continuous or gated. During gated clock mode, data on the SSI_TXCLK pin is valid only during the
transmission of data. If the pull-up is disabled for this pin in the GPIO Module’s Pull-Up Enable Register, then the
clock pin is tri-stated when data is not transmitting. In synchronous mode, this pin is used by both the transmit and
receive sections. When using gated clock mode, an external resistor is connected to this pin to prevent the signal
from floating when not being driven.
24.4.4 SSI_RXCLK, Serial Receive Clock
The SSI_RXCLK pin can be used as either an input or an output. This clock signal is used by the receiver and is
always continuous. During gated clock mode, the SSI_TXCLK pin is used instead for clocking in data. In I2S
master mode, this pin is used as an output pin for the oversampling clock, SYS_CLK (PerCLK3).
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-35
SSI Data and Control Pins
24.4.5 SSI_TXFS, Serial Transmit Frame Sync
The SSI_TXFS pin can be used as either an input or an output. The frame sync is used by the transmitter to
synchronize the transfer of data. The frame sync signal can be 1 bit-clock or 1 word in length and can occur one bit
before the transfer of data or with the transfer of data. (These configurations are set in the STCR.) In synchronous
mode, this pin is used by both the transmit and receive sections. In gated clock mode, frame sync signals are not
used. When SSI_TXFS is configured as input, the external device should drive SSI_TXFS at the rising or falling
edge of SSI_TXCLK, depending on the setting of the TSCKP bit of the SSI Transmit Configuration Register.
SSI_TXFS should sync with the rising edge of SSI_TXCLK if the data is clocking out at the rising edge of
SSI_TXCLK. SSI_TXFS should sync with the falling edge of SSI_TXCLK if the data is clocking out at the falling
edge of SSI_TXCLK.
24.4.6 SSI_RXFS, Serial Receive Frame Sync
The SSI_RXFS pin can be used as either an input or an output. The frame sync is used by the receiver to
synchronize the transfer of data. The frame sync signal can be 1 bit-clock or 1 word in length and can occur one bit
before the transfer of data or with the transfer of data. (These configurations are set in the SRCR.) When
SSI_RXFS is configured as an input, the external device can drive SSI_RXFS at the rising or falling edge of
SSI_RXCLK, depending on the setting of the RSCKP bit of the SRCR Register. SSI_RXFS should sync with the
rising edge of SSI_RXCLK if the data is clocking out at the rising edge of SSI_RXCLK. SSI_RXFS should sync
with the falling edge of SSI_RXCLK if the data is clocking out at the falling edge of SSI_RXCLK.
Figure 24-14 and Figure 24-15 on page 24-37 show the main SSI configurations. These pins support all transmit
and receive functions with continuous or gated clocks as shown. Note that gated clock implementations do not
require the use of the frame sync pins (SSI_TXFS and SSI_RXFS). In this case, these pins also can be used as
GPIO pins.
MC9328MXS
MC9328MXS
SSI_TXDAT
SSI_TXDAT
SSI_RXDAT
SSI_RXDAT
SSI_TXCLK
SSI_TXCLK
SSI_TXFS
SSI_TXFS
SSI_RXCLK
SSI_RXCLK
SSI_RXFS
SSI_RXFS
SSI TX/RX Internal Continuous Clock
(RXDIR=1, TXDIR=1, RFDIR=1, TFDIR=1, SYN=0)
MC9328MXS
SSI RX Internal Continuous Clock, SSI TX External
Continuous Clock
(RXDIR=1, TXDIR=0, RFDIR=1, TFDIR=0, SYN=0)
MC9328MXS
SSI_TXDAT
SSI_TXDAT
SSI_RXDAT
SSI_RXDAT
SSI_TXCLK
SSI_TXCLK
SSI_TXFS
SSI_TXFS
SSI_RXCLK
SSI_RXCLK
SSI_RXFS
SSI_RXFS
SSI TX/RX External Continuous Clock
(RXDIR=0, TXDIR=0, RFDIR=0, TFDIR=0, SYN=0)
SSI TX Internal Continuous Clock, SSI RX External
Continuous Clock
(RXDIR=0, TXDIR=1, RFDIR=0, TFDIR=1, SYN=0)
Figure 24-14. Asynchronous (SYN = 0) SSI Configurations—Continuous Clock
MC9328MXS Reference Manual, Rev. 1.1
24-36
Freescale Semiconductor
SSI Data and Control Pins
MC9328MXS
MC9328MXS
SSI_TXDAT
SSI_TXDAT
SSI_RXDAT
SSI_RXDAT
SSI_TXCLK
SSI_TXCLK
SSI TX/RX Internal Gated Clock
(RXDIR=1, TXDIR=1, SYN=1)
SSI_TXFS
SYS_CLK
MC9328MXS
SSI TX/RX Internal Continuous Clock
(RXDIR=0, TXDIR=1, RFDIR=X, TFDIR=1, SYN=1, SYS_CLK_EN=1)
SSI I2S Master Mode (I2S_Mode Select=01, SYS_CLK_EN)
SSI_TXDAT
SSI_RXDAT
MC9328MXS
SSI_TXCLK
SSI_TXDAT
SSI TX/RX External Gated Clock
(RXDIR=1, TXDIR=0, SYN=1)
SSI_RXDAT
SSI_TXCLK
SSI_TXFS
SSI TX/RX External Continuous Clock
(RXDIR=0, TXDIR=0, RFDIR=X, TFDIR=0, SYN=1)
SSI I2S Slave Mode (I2S_Mode Select=10)
Figure 24-15. Synchronous SSI Configurations—Continuous and Gated Clock
An example of the pin signals for an 8-bit data transfer is shown in Figure 24-16. Continuous and gated clock
signals are shown, as well as the bit-length frame sync signal and the word-length frame sync signal.
NOTE:
The shift direction can be defined as MSB first or LSB first.
Continuous SSI_TXCLK, SSI_RXCLK
Gated SSI_TXCLK, SSI_RXCLK
SSI_TXFS, SSI_RXFS
Early SSI_TXFS, SSI_RXFS
SSI_TXDAT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SSI_RXDAT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
8-Bit Data
Bit Length Frame Sync
Word Length Frame Sync
Figure 24-16. Serial Clock and Frame Sync Timing
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-37
SSI Operating Modes
24.5 SSI Operating Modes
SSI module three basic operating modes, with the option of asynchronous or synchronous protocol for most
modes.
•
Normal mode
— asynchronous protocol
— synchronous protocol
•
Network mode
— asynchronous protocol
— synchronous protocol
•
Gated clock mode
— synchronous protocol only
The mode of the SSI is determined by several bits in the SSI control registers. Table 24-23 lists these operating
modes and gives examples of applications that typically use each mode.
Table 24-23. SSI Operating Modes
TX, RX Sections
Serial Clock
Mode
Typical Application
Asynchronous
Continuous
Normal
Multiple synchronous codecs
Asynchronous
Continuous
Network
TDM codec or DSP networks
Synchronous
Continuous
Normal
Multiple synchronous codecs
Synchronous
Continuous
Network
TDM codec or DSP network
Synchronous
Gated
Normal
SPI-type devices; DSP to MCU
The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode, the
transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous mode, the
transmitter and receiver each have their own clock and frame synchronization signals. Continuous or Gated clock
mode can be selected. In continuous mode, the clock runs continuously. In gated clock mode, the clock is only
functioning during transmission.
Normal or network mode also can be selected. In normal mode, the SSI functions with one data word of I/O per
frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is typically used in star
or ring-time division multiplex networks with other processors or codecs, allowing interface to time division
multiplexed networks without additional logic. Use of the gated clock is not allowed in network mode. These
distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices.
The SSI supports both normal and network modes, and these can be selected regardless of whether the transmitter
and receiver are synchronous or asynchronous. Typically these protocols are used in a periodic manner, when data
is transferred at regular intervals, such as at the sampling rate of an external codec. Both modes use the concept of
a frame. The beginning of the frame is marked with a frame sync when programmed with continuous clock. The
frame sync occurs at a periodic interval. The length of the frame is determined by the DC field in either the SRCCR
or STCCR register, depending on whether data is being transferred or received. The number of words transferred
per frame depends on the mode of the SSI.
MC9328MXS Reference Manual, Rev. 1.1
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Freescale Semiconductor
SSI Operating Modes
In normal mode, one data word is transferred per frame. In network mode, the frame is divided into anywhere
between 2 and 32 time slots, when one data word can optionally be transferred in each time slot.
24.5.1 Normal Mode
Normal mode is the simplest mode of the SSI. It transfers one word per frame. In continuous clock mode, a frame
sync occurs at the beginning of each frame. The length of the frame is determined by the fields of the STCCR or
SRCCR registers:
•
The period of the serial bit clock. For external clocking, this is based on the frequency on the SSI_TXCLK
pin. For an internal clock, this is determined by the values of the PSR bit and the PM field.
•
The number of bits per sample (WL)
•
The number of time slots per frame (DC)
When normal mode is configured to provide more than one time slot per frame, data is transmitted only in the first
time slot. No data is transmitted in subsequent time slots.
24.5.1.1 Normal Mode Transmit
The conditions for data transmission from the SSI in normal mode are:
1. SSI enabled (SCSR:SSI_EN = 1)
2. Enable the FIFO (STCR:TFEN = 1) and configure the transmit (SFCSR:TFWM) and receive
(SFCSR:RFWM) Water Marks if the FIFO is used.
3. Write data to the STX register
4. Enable transmitter (SCSR:TE = 1)
5. Active frame sync (required for continuous clock)
6. Active bit clock (the bit clock is active when the transmitter is enabled; for a gated clock, see
Table 24-14)
When these conditions occur in normal mode, the next data word is transferred into the TXSR. When the transmit
FIFO is enabled, the data word is transferred from the transmit FIFO. When the transmit FIFO is disabled, the data
word is transferred from the STX register.
The new data word is transmitted immediately and the TDE bit is set.
When the transmit FIFO is disabled and the TIE bit in the STCR is set, the transmit interrupt occurs. When the
transmit FIFO is enabled, the FIFO waits until the Transmit Water Mark level has been reached. The transmit
interrupt then occurs if the TIE bit is set. In this case, an eighth data word is transferred and shifted out before the
MC9328MXS writes new data to the STX register.
The SSI_TXDAT pin is disabled except during the data transmission period. For a continuous clock, the optional
frame sync output and clock outputs are not tri-stated, even when both receiver and transmitter are disabled.
24.5.1.2 Normal Mode Receive
The conditions for data reception from the SSI are:
1. SSI enabled (SCSR:SSI_EN = 1)
2. Receiver enabled (SCSR:RE = 1)
3. Active frame sync (required for continuous clock)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-39
SSI Operating Modes
4. Active bit clock (the bit clock is active when the receiver is enabled; for a gated clock, see
Table 24-14)
With these conditions are met in normal mode with a continuous clock, each time the frame sync signal is
generated (or detected), a data word is clocked in. Also given these conditions and a gated clock, each time the
clock begins, a data word is clocked in.
When the receive FIFO is not enabled, after receiving a data word, the data is transferred from the RXSR to the
SRX register. The RDR bit is set, and the receive interrupt occurs if it is enabled (the RIE bit is set).
When the receive FIFO is enabled, after receiving the data word, it is transferred to the receive FIFO. The RFF bit
is set when the SRX register is full and receive FIFO register reaches the select threshold (Receive Water Mark),
and the receive interrupt occurs if the RIE bit is set.
The MC9328MXS program must read the data from the SRX register before a new data word is transferred from
the RXSR, otherwise the ROE bit is set. When the receive FIFO is enabled, the ROE bit is set when the SRX
register and the receive FIFO are full of data and a new data word is ready to be transferred to the receive FIFO.
Figure 24-17 shows transmitter and receiver timing for an 8-bit word with two words per time slot in normal mode,
with a continuous clock and a late word length frame sync.
Continuous Clock
Frame Sync
TX DATA
SSI_TXDAT
SSI_RXDAT
RX DATA
Figure 24-17. Normal Mode Timing—Continuous Clock
Figure 24-18 shows a similar case for a gated clock. A pull-down resistor is required in the gated clock example
because the clock pin is tri-stated between transmissions.
Gated CLK
TX DATA
SSI_TXDAT
SSI_RXDAT
RX DATA
Figure 24-18. Normal Mode Timing—Gated Clock
MC9328MXS Reference Manual, Rev. 1.1
24-40
Freescale Semiconductor
SSI Operating Modes
24.5.2 Network Mode
Network mode is used for creating a Time Division Multiplexed (TDM) network, such as a TDM codec network or
a network of DSPs. In continuous clock mode, a frame sync occurs at the beginning of each frame. In this mode,
the frame is divided into more than one time slot. During each time slot, one data word can be transferred. Each
time slot is then assigned to an appropriate codec or DSP on the network. The DSP can be a master device that
controls its own private network, or a slave device that is connected to an existing TDM network and occupies a
few time slots.
The frame sync signal indicates the beginning of a new data frame. Each data frame is divided into time slots and
transmission and/or reception of one data word can occur in each time slot (rather than in just the frame sync time
slot as in normal mode). The frame rate divider, controlled by the DC bits of the STCCR or SRCCR, selects 2 to 32
time slots per frame.
The length of the frame is determined by the fields of the STCCR or SRCCR registers:
•
The period of the serial bit clock
— for external clocking, this is based on the frequency on the SSI_TXCLK pin
— for internal clocking, this is based on the values of the PSR bit and the PM field
•
The number of bits per sample (WL)
•
The number of time slots per frame (DC)
In network mode, data can be transmitted in any time slot. The distinction of the network mode is that each time
slot is identified with respect to the frame sync (data word time). This time slot identification allows the option of
transmitting data during the time slot by writing to the STX register or ignoring the time slot by writing to SSI
Time Slot Register (STSR). The receiver is treated in the same manner, except that data is always being shifted into
the RXSR and transferred to the SRX register. The MC9328MXS reads the SRX register and either uses it or
discards it.
24.5.2.1 Network Mode Transmit
The transmit portion of the SSI is enabled when the SSI_EN and the TE bits in the SCSR are both set. However, for
a continuous clock, when the TE bit is set, the transmitter is enabled only after detection of a new time slot (if the
TE bit is set during a slot other than the first). The software must find the start of the next frame.
The normal start-up sequence for transmission is as follows:
1. Write the data to be transmitted to the STX register. This clears the TDE bit.
2. Set the TE bit to enable the transmitter on the next word boundary (for continuous clock).
3. Enable transmit interrupts.
If the programmer decides not to transmit in a time slot by writing to the SSI Time Slot Register (STSR), this clears
the TDE bit, however the SSI_TXDAT pin remains disabled during the time slot. When the frame sync is detected
or generated (continuous clock), the first enabled data word is transferred from the STX register to the TXSR and is
shifted out (transmitted). When the STX register is empty, the TDE bit is set. When the TIE bit in the STCR is set,
setting the TDE bit causes a transmitter interrupt to occur.
The software can poll the TDE bit or use interrupts to reload the STX register with new data for the next time slot,
or can write to the STSR to prevent transmitting in the next time slot. Failing to write to the STX register (or the
STSR) before the TXSR is finished shifting (empty) causes a transmitter underrun. This is detected by the TUE bit
of the SCSR. When this happens, the SSI_TXDAT pin continuously sends the last transmitted data.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-41
SSI Operating Modes
Clearing the TE bit disables the transmitter (and the SSI_TXDAT pin) after transmission of the current data word
is complete. Setting the TE bit enables transmission of the next word. The TE bit is cleared after the TDE bit is set
to ensure that all pending data is transmitted.
To summarize, in network mode, the transmitter can generate an interrupt during every enabled time slot or require
the DSP program to poll the TDE bit. When the TDE bit is set, the MC9328MXS responds with one of the
following actions:
•
Write data to the STX register—enables transmission in the next time slot.
•
Write to the SSI Time Slot Register (STSR)—disables transmission in the next time slot.
•
Do nothing—causes a transmit underrun to occur at the beginning of the next time slot (the previous data is
re-transmitted).
24.5.2.2 Network Mode Receive
The receiver portion of the SSI is enabled when both the SSI_EN and the RE bits in the SCSR are set. However,
the receive enable takes place during that time slot only if the RE bit is enabled before the second to last bit of the
word. When the RE bit is cleared, the receiver is disabled immediately. SSI is capable of finding the start of the
next frame automatically. The word is received into the RXSR and then transferred to the SRX register when the
whole word is received. The transfer to the SRX register sets the RDR bit. When the RIE bit is set, setting the RDR
bit causes a receive interrupt to occur.
After the received word is transferred to the SRX register, the second data word (second time slot in the frame),
begins shifting in immediately. The DSP program must read the data from the SRX register (this clears the RDR
bit) before the second data word is completely received into the RXSR or a receive overrun error occurs. This is
detected by the ROE bit of the SCSR.
To summarize, in network mode, the receiver can generate an interrupt during every enabled time slot or require
the DSP program to poll the RDR bit. When the TDE bit is set, the MC9328MXS responds with one of the
following actions:
•
Read the SRX register and use the data.
•
Read the SRX register and ignore the data.
•
Do nothing—a receiver overrun occurs at the end of the current time slot.
NOTE:
For a continuous clock, the optional frame sync output and clock output signals are
not affected even when the transmitter or receiver is disabled. The TE and RE bits
do not disable the bit clock or the frame sync generation. The only way to disable
the bit clock and the frame sync generation is to disable the SSI_EN bit in the
SCSRregister.
Figure 24-19 on page 24-43 shows the transmitter and receiver timing for an 8-bit word with continuous clock,
with the FIFO disabled, and with a frame size of three words per frame sync, operating in network mode.
MC9328MXS Reference Manual, Rev. 1.1
24-42
Freescale Semiconductor
Gated Clock Mode
CLK
Frame Sync
STSR
TX DATA 0x5E
0xD6
SSI_TXDAT
0x7B
0x5E
0x5E
0xD6
0x7B
0x5E
0x5E
0xD6
XX
XX
0x5E
0x5E
0xD6
XX
TDE
TUE
SSI_RXDAT
RX DATA
0x7B
RDR
ROE
NOTE: XX = “don’t care”
Figure 24-19. Network Mode Timing—Continuous Clock
24.6 Gated Clock Mode
The gated clock mode is often used to connect to SPI-type interfaces on Microcontroller Units (MCUs) or external
peripheral chips. In gated clock mode, the presence of the clock indicates that valid data is on the SSI_TXDAT or
SSI_RXDAT pins. For this reason, no frame sync is needed in this mode. When transmission of data is complete,
the clock pin is tri-stated. Gated clocks are allowed for both the transmit and receive sections with either internal or
external clock and in Normal mode. Gated clocks are not allowed in Network mode.
The clock runs when the TE bit or the RE bit in the SCSR are appropriately enabled. For clocks that are generated
internally, all internal bit clocks, word clocks, and frame clocks continue to operate. When a valid time slot occurs,
such as the first time slot in normal mode, the internal bit clock is enabled onto the appropriate clock pin. This
allows data to be transferred out in periodic intervals in gated clock mode. When an external clock is used, the SSI
waits for a clock signal to be received. When the clock begins, valid data is shifted in.
For gated clock operation in external clock mode, a proper clock signal must be applied to the SSI STCK for proper
function. If the SSI uses a rising edge transition to clock data (TSCKP=0) and a falling edge transition to latch
data(RSCKP=0), the clock must be in an active low state when idle. If the SSI uses a falling edge transition to
clock data (TSCKP=1) and a rising edge transition to latch data (RSCKP=1), the clock must be in an active high
state when idle. The following diagrams illustrate the different edge clocking and latching.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-43
External Frame and Clock Operation
STCK
STXD
SRXD
TSCKP=0, RSCKP=0
Figure 24-20. Rising Edge Clocking with Falling Edge Latching
STCK
STXD
SRXD
TSCKP=1, RSCKP=1
Figure 24-21. Falling Edge Clocking with Rising Edge Latching
For gated clock operation in internal clock mode, only the rising edge transition to clock data (TSCKP=0) and
falling edge transition to latch data (RSCKP=0) is supported. The clock will always be in an active low state when
idle. TSCKP=1 and RSCKP=1 are not supported in internal clock mode.
NOTE:
The bit clock pins must be kept free of timing glitches. A single glitch causes all
subsequent transfers to lose synchronization.
When there is new data to be transmitted after the idle state has been entered, the data written to the Transmit FIFO
will be transmitted immediately.
24.7 External Frame and Clock Operation
When applying external frame sync and clock signals to SSI, TE should not be set to 1 within 4 clock cycles before
the rising edge of the frame sync signal and 4 clock cycles after the rising edge of the frame sync signal. The
transition of SSI_TXFS or SSI_RXFS is synchronized with the rising edge of the external clock signal,
SSI_TXCLK or SSI_RXCLK.
24.8 SSI Reset and Initialization Procedure
The SSI is affected by three types of reset:
•
Power-on reset—The power-on reset is generated by asserting either the RESET pin or the Computer
Operating Properly (COP) timer reset. The power-on reset clears the SSI_EN bit in the SCSR and disables
the SSI.
MC9328MXS Reference Manual, Rev. 1.1
24-44
Freescale Semiconductor
SSI Reset and Initialization Procedure
•
SSI reset—The SSI reset is generated when the SSI_EN bit in the SCSR is cleared. The SSI status bits are
reset to the same state produced by the power-on reset. The SSI control bits are unaffected. The control bits
in the top half of the SCSR are also unaffected. The SSI reset is useful for selective reset of the SSI without
changing the present SSI control bits and without affecting the other peripherals.
The correct sequence to initialize the SSI is as follows:
1. Issue a power-on or SSI reset.
2. Set the SSI_EN bit in the SCSR.
3. Set all other control bits (such as TXDIR and RXDIR).
4. Set the TE and RE bits in the SCSR.
To ensure proper operation of the SSI, use the power-on or SSI reset before changing any of the control bits listed
in Table 24-24. These control bits should not be changed during SSI operation.
Table 24-24. SSI Control Bits Requiring Reset Before Change
Control Register
Bit
SRCCR and STCCR
[14:13] = WL [1:0]
STCR and SRCR
[9] = TDMAE / RDMAE
[6] = TFDIR / RFDIR
[5] = TXDIR / RXDIR
[4] = TSHFD / RSHFD
[3] = TSCKP / RSCKP
[2] = TFSI / RFSI
[1] = TFSL / RFSL
[0] = TEFS / REFS
SCSR
[15] = SYS_CLK_EN
[14:13] = I2S_MODE
[12] = SYN
[11] = NET
NOTE:
The SSI bit clock must go low for at least one complete period to ensure proper SSI
reset.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
24-45
SSI Reset and Initialization Procedure
MC9328MXS Reference Manual, Rev. 1.1
24-46
Freescale Semiconductor
Chapter 25
GPIO Module and I/O Multiplexer (IOMUX)
25.1 General Description
This chapter describes the four GPIO ports of the MC9328MXS. All of the GPIO port pins are multiplexed with
other signals.
NOTE:
See Chapter 2, “Signal Descriptions and Pin Assignments,” for detailed I/O
multiplexing information.
This section contains the description of the top level I/O multiplexing strategy in the MC9328MXS, which consists
of two modules:
•
Software controllable multiplexing performed in the GPIO module
•
Hardware multiplexing performed in the IOMUX module
The I/O multiplexing strategy is designed to configure the inputs and outputs of the MC9328MXS to allow the
same I/O pad to be used for peripheral functions and GPIO. The I/O multiplexing is designed to be as flexible as
possible and to allow the simple and quick reuse of this system in future derivatives of the MC9328MXS. In
addition to the I/O multiplexing, the IOMUX module contains the JTAG shift registers, which significantly
simplify the I/O design.
There are four GPIO ports on the MC9328MXS: Port A, Port B, Port C, and Port D. Each port consists of 32 pins,
however not all pins are used. The usable port pins are:
•
Port A—pins 0–31
•
Port B—pins 8–31
•
Port C—pins 3–17
•
Port D—pins 6–31
Figure 25-1 on page 25-2 depicts a top-level view of the IOMUX and GPIO modules for a single port pin. This
circuitry is duplicated for each of the 97 port pins.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
25-1
GPIO Module Overview
IOMUX Module
Pin Primary Function
0
Pin Alternate Function
1
GPIO Module
GPR_X
GPR_X [i]
0
GPIO functions
GIUS_X
GIUS_X [i]
Pad
i
1
Pin Port X [i]
PUEN_X [i]
PUEN_X
Figure 25-1. Top Level of Circuitry for Port X, Pin [i]
25.2 GPIO Module Overview
Most of this chapter focuses on the GPIO module, which provides general purpose I/O capability to the device. The
GPIO module communicates with the ARM920T processor through an IPBUS interface connected as an IP
peripheral. The complete module controls 97 bidirectional port pins. Software configurability allows each I/O to be
configured as general purpose input (optionally routed to two different destinations) or general purpose output
(from one out of four selectable sources).
25.2.1 GPIO Module Features
The GPIO module features include:
•
97 direction-configurable port pins
•
Software controllable input/output selection through four 32-bit direction registers
•
Software control for multiplexing one of four different sources (a data register and three peripheral modules
on the MC9328MXS) for every output pin
•
Software control for routing every input to other modules
•
Input data sampling on each clock
•
Software control of the IOMUX module through four 32-bit general purpose registers
•
Configurability of each input port pin interrupt as positive edge triggered, negative edge triggered, positive
level sensitive, negative level sensitive or as a masked interrupt
•
Ability to logically OR each port’s 32 interrupt lines to a single interrupt to the ARM920T processor
•
Software reset
MC9328MXS Reference Manual, Rev. 1.1
25-2
Freescale Semiconductor
GPIO Module Overview
25.2.2 Interrupts
The interrupt block inside the GPIO module controls all GPIO interrupt signals. Inside this block, interrupts are
defined as positive edge triggered, negative edge triggered, positive level sensitive, negative level sensitive, or
masked. For edge triggered interrupts, the edge is detected by the GPIO interrupt block and is converted to a low
level interrupt that is routed to other internal modules. When the interrupt is masked, a value of 1 is driven to the
interrupt controller regardless of the GPIO input value. The interrupts waiting for service are stored in the Interrupt
Status Register (ISR) for that port. Write a value of 1 to the ISR to clear the interrupt. The logical OR of all the
non-masked interrupt lines is available as an output from the port. Individual interrupts for each port pin may also
be output to other internal modules.
25.2.3 GPIO Signal Description
The circuitry for a single pin of the GPIO module is shown in Figure 25-2 on page 25-4. The signals shown in that
figure and the signals shown in Figure 25-1 on page 25-2 are described in Table 25-1.
Table 25-1. GPIO External Pins Description
Signal Name
Direction
Description
AIN
Input
A 32-bit input from MC9328MXS. Any signal may be connected. This input may be reflected to
GPIO output (GPIO-Out in Figure 25-2) by appropriate GPIO configuration.
BIN
Input
Same as AIN.
CIN
Input
Not Used.
AOUT
Output
A 32-bit output from the GPIO that connects external pins to internal signals in the
MC9328MXS, sends an interrupt signal to an internal module, or is connected high or low.
BOUT
Output
Not Used.
GIUS_X
Output
Represents one of four GPIO In-Use Registers (GIUS). Connects to the IOMUX module and
selects whether a pin is used for GPIO or a peripheral function.
GPR_X
Output
Represents one of the four General Purpose Registers (GPR). Connects to the IOMUX module
and selects whether a pin is used for its primary or alternate function.
PUEN_X
Output
Selects whether the port pin is pulled up to a logic high.
GPIO_INT
Output
The OR value of all 32 interrupt lines. Each pin [i] of the port corresponds to pin [i] of the ISR
register.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
25-3
GPIO Module Block Diagram
25.3 GPIO Module Block Diagram
OCR1_X
OCR2_X
DDIR_X
Bits [2i + 1] and [2i] or
Bits [2i – 32 + 1] and [2i – 32]
Bit[i]
SWR_X
AIN[i]
BIN[i]
CIN[i]
00
01
10
11
GPIO-Out
Bit[i]
To
Multiplexer
GPIO-In
Bit[i]
Bit[i]
SSR_X
DR_X
ICONFA2_X
ICONFA1_X
GPIO_INT
Interrupt Block
ISR_X
Bits [2i + 1] and [2i] or
Bits [2i – 32 + 1] and [2i–32]
Bit[i]
Bits [2i + 1] and [2i] or
Bits [2i – 32 + 1] and [2i – 32]
AOUT[i]
00
01
10
11
Bit[i]
ISR_X
ICR1_X
ICR2_X
0
1
IMR_X
Bit[i]
ICONFB1_X
ICONFB2_X
GPR_X
Bit[i]
Bits [2i + 1] and [2i] or
Bits [2i – 32 + 1] and [2i – 32]
BOUT[i]
00
01
10
11
GPR_X[i]
Bit[i]
GIUS_X[i]
GIUS_X
ISR_X
0
1
Figure 25-2. GPIO Module Block Diagram for Port X, Pin [i]
25.4 Pin Configuration for GPIO
The GPIO port pins on the MC9328MXS are multiplexed with signals from peripheral modules on the device.
These pins must be configured for GPIO operation. Table 25-2 on page 25-5 shows the pin configuration.
MC9328MXS Reference Manual, Rev. 1.1
25-4
Freescale Semiconductor
Pin Configuration for GPIO
To further expand the multiplexing features of the GPIO module, added functionality was incorporated to route the
input and output signals of selected peripherals. These signals are routed to the GPIO module via AIN[i], BIN[i],
CIN[i], AOUT[i], and BOUT[i], where “i” denotes any bit from bit 31 to bit 0. There are a set of these signals
available for each GPIO Port (Port A, Port B, Port C, and Port D). The “IN” signals denote inputs to the GPIO
module whereas the “OUT” signals are outputs from the GPIO module, as can be seen in Figure 25-2 on page 25-4.
In the case of the “IN” signals, these signals are passed through the GPIO module from the selected peripheral and
are output to the MC9328MXS pins. Therefore, the Data Direction Register for the desired “IN” signal must be set
as an output. On the other hand, in the case of the “OUT” signals, these signals are also passed through the GPIO
module, however their inputs come from the MC9328MXS pins and are output to the selected peripheral.
Therefore, the Data Direction register for the desired “OUT” signal must be set as an input. For example, if the user
wants to route the SPI2_RXD input via the PA1 pin, they must set GIUS_A bit 1 for GPIO function (set bit 1). The
next step would then be to clear the ICONFA1_A bits 2 and 3 (to 00) to select the GPIO-IN to allow PA1 to drive
AOUT[1]. Finally, the DDIR bit 1 must be set as an input (clear bit 1). Should the user need to route the SPI2_CLK
output via pin PD7, they must first set bit 7 of GIUS_D. The next step is to clear bits 15 and 14 of OCR1_D to
select AIN[7] as an input to the GPIO module. Finally, bit 7 of DDIR must be set to select this signal as an output
from the GPIO module to the external pin. Table 25-3 shows the signals that use this expanded functionality.
Table 25-2. Pin Configuration
Pin
Port A
Pins 31–0
Configuration Procedure
1.
For each pin [i] that is used as a GPIO, set bit [i] in the Port A GPIO In Use Register (GIUS_A).
2.
When pin [i] is used as an input:
3.
• Clear bit [i] in the Port A Data Direction Register (DDIR_A)
• Read the Port A Sample Status Register (SSR_A) as needed
When pin [i] is used as an output:
•
•
•
Port B
Pins 31–8
Set bits [2i + 1] and [2i] in the Port A Output Configuration Register 1 (OCR1_A)
or
Set bits [2i – 32 + 1] and [2i – 32] in the Port A Output Configuration Register 2 (OCR2_A)
Write desired output value to bit [i] of the Port A Data Register (DR_A)
Set bit [i] in the Port A Data Direction Register (DDIR_A)
1.
For each pin [i] that is used as a GPIO, set bit [i] in thePort B GPIO In Use Register (GIUS_B).
2.
When pin [i] is used as an input:
3.
• Clear bit [i] in the Port B Data Direction Register (DDIR_B)
• Read the Port B Sample Status Register (SSR_B) as needed
When pin [i] is used as an output:
•
•
•
Set bits [2i + 1] and [2i] in the Port B Output Configuration Register 1 (OCR1_B)
or
Set bits [2i – 32 + 1] and [2i – 32] in the Port B Output Configuration Register 2 (OCR2_B)
Write desired output value to bit [i] of the Port B Data Register (DR_B)
Set bit [i] in the Port B Data Direction Register (DDIR_B)
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
25-5
Programming Model
Table 25-2. Pin Configuration (continued)
Pin
Configuration Procedure
Port C
Pins 17–3
1.
For each pin [i] that is used as a GPIO, set bit [i] in the Port C GPIO In Use Register (GIUS_C).
2.
When pin [i] is used as an input:
3.
• Clear bit [i] in the Port C Data Direction Register (DDIR_C)
• Read the Port C Sample Status Register (SSR_C) as needed
When pin [i] is used as an output:
•
•
•
Port D
Pins 31–6
Set bits [2i + 1] and [2i] in the Port C Output Configuration Register 1 (OCR1_C)
or
Set bits [2i – 32 + 1] and [2i – 32] in the Port C Output Configuration Register 2 (OCR2_C)
Write desired output value to bit [i] of the Port C Data Register (DR_C)
Set bit [i] in the Port C Data Direction Register (DDIR_C)
1.
For each pin [i] that is used as a GPIO, set bit [i] in the Port D GPIO In Use Register (GIUS_D).
2.
When pin [i] is used as an input:
3.
• Clear bit [i] in the Port D Data Direction Register (DDIR_D)
• Read the Port D Sample Status Register (SSR_D) as needed
When pin [i] is used as an output:
•
•
•
Set bits [2i + 1] and [2i] in the Port D Output Configuration Register 1 (OCR1_D)
or
Set bits [2i – 32 + 1] and [2i – 32] in the Port D Output Configuration Register 2 (OCR2_D)
Write desired output value to bit [i] of the Port D Data Register (DR_D)
Set bit [i] in the Port D Data Direction Register (DDIR_D)
25.5 Programming Model
There are four sets of control registers corresponding to the four GPIO ports. Each port has 17 registers associated
with it, located at sequential addresses in the memory map. Table 25-3 summarizes these registers and their
addresses.
The starting address of each register set is known as the base address and is referred to by the term $BA. The base
addresses for the four GPIO ports are as follows:
•
GPIO Port A $BA = 0x0021C000
•
GPIO Port B $BA = 0x0021C100
•
GPIO Port C $BA = 0x0021C200
•
GPIO Port D $BA = 0x0021C300
Table 25-3. GPIO Module Register Memory Map
Description1
Name1
Address
Port X Data Direction Register
DDIR_X
$BA + $000
Port X Output Configuration Register 1
OCR1_X
$BA + $004
Port X Output Configuration Register 2
OCR2_X
$BA + $008
Port X Input Configuration Register A1
ICONFA1_X
$BA + $00C
MC9328MXS Reference Manual, Rev. 1.1
25-6
Freescale Semiconductor
Programming Model
Table 25-3. GPIO Module Register Memory Map (continued)
Description1
Name1
Address
Port X Input Configuration Register A2
ICONFA2_X
$BA + $010
Port X Input Configuration Register B1
ICONFB1_X
$BA + $014
Port X Input Configuration Register B2
ICONFB2_X
$BA + $018
Port X Data Register
DR_X
$BA + $01C
Port X GPIO In Use Register
GIUS_X
$BA + $020
Port X Sample Status Register
SSR_X
$BA + $024
Port X Interrupt Configuration Register 1
ICR1_X
$BA + $028
Port X Interrupt Configuration Register 2
ICR2_X
$BA + $02C
Port X Interrupt Mask Register
IMR_X
$BA + $030
Port X Interrupt Status Register
ISR_X
$BA + $034
Port X General Purpose Register
GPR_X
$BA + $038
Port X Software Reset Register
SWR_X
$BA + $03C
Port X Pull_Up Enable Register
PUEN_X
$BA + $040
1.
X is a variable representing A, B, C or D. The actual register
names include the port.
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
25-7
Programming Model
25.5.1 Data Direction Registers
The data direction registers specify whether each pin of the port is an input or an output pin.
There are four distinct Data Direction Registers; each holds the data for one of the four GPIO ports (Port A, Port B,
Port C, and Port D).
DDIR_A
DDIR_B
DDIR_C
DDIR_D
BIT
Addr
0x0021C000
0x0021C100
0x0021C200
0x0021C300
Port A Data Direction Register
Port B Data Direction Register
Port C Data Direction Register
Port D Data Direction Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DDIR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DDIR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 25-4. Data Direction Registers Description
Name
DDIR [i]
Bits 31–0
Description
Data Direction—Controls the direction of the pins.
Settings
0 = Pin [i] is an input
1 = Pin [i] is an output
MC9328MXS Reference Manual, Rev. 1.1
25-8
Freescale Semiconductor
Programming Model
25.5.2 Output Configuration Registers
The output configuration registers specify the output signal for each pin. There are two bits in the output
configuration registers for each port pin.
There are two output configuration registers for each port; each holds the data for one of the four GPIO ports (Port
A, Port B, Port C, and Port D).
25.5.2.1 Output Configuration Register 1
OCR1_A
OCR1_B
OCR1_C
OCR1_D
BIT
Addr
0x0021C004
0x0021C104
0x0021C204
0x0021C304
Port A Output Configuration Register 1
Port B Output Configuration Register 1
Port C Output Configuration Register 1
Port D Output Configuration Register 1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OCR1
pin 15
TYPE
pin 14
pin 13
pin 12
pin 11
pin 10
pin 9
pin 8
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
OCR1
pin 7
TYPE
pin 6
pin 5
pin 4
pin 3
pin 2
pin 1
pin 0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 25-5. Output Configuration Register 1 Description
Name
Description
OCR1 [i]
Bits 31–0
Output Configuration—Corresponds to pins 0–15 of the
port and defines which one of the four options is selected as
the output signal GPIO-Out. Each port pin [i] (i = 0 through
15) requires two OCR1 bits to determine the output signal.
Settings
OCR1
[2i + 1]
OCR1
[2i]
Output Selected
0
0
External input AIN [i]
0
1
External input BIN [i]
1
0
External input CIN [i]
1
1
Data Register [i]
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
25-9
Programming Model
25.5.2.2 Output Configuration Register 2
OCR2_A
OCR2_B
OCR2_C
OCR2_D
BIT
Addr
0x0021C008
0x0021C108
0x0021C208
0x0021C308
Port A Output Configuration Register 2
Port B Output Configuration Register 2
Port C Output Configuration Register 2
Port D Output Configuration Register 2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OCR2
pin 31
TYPE
pin 30
pin 29
pin 28
pin 27
pin 26
pin 25
pin 24
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
OCR2
pin 23
TYPE
pin 22
pin 21
pin 20
pin 19
pin 18
pin 17
pin 16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 25-6. Output Configuration Register 2 Description
Name
Description
OCR2 [i]
Bits 31–0
Output Configuration—Corresponds to pins 16–31 of
the port and defines which one of the four options is
selected as the output signal GPIO-Out. Each port pin [i] (i
= 16 through 31) requires two OCR2 bits to determine the
output signal.
Settings
OCR2
[2i–32 + 1]
OCR2
[2i–32]
Output Selected
0
0
External input AIN [i]
0
1
External input BIN [i]
1
0
External input CIN [i]
1
1
Data Register [i]
MC9328MXS Reference Manual, Rev. 1.1
25-10
Freescale Semiconductor
Programming Model
25.5.3 Input Configuration Registers
The input configuration registers ICONFA1 and ICONFA2 specify the signal or value driven to the AOUT bus.
The input configuration registers ICONFB1 and ICONFB2 specify the signal or value driven to the BOUT bus.
There are two bits in the input configuration registers for each port pin.
There are four distinct input configuration registers for each port; each holds the data for one of the four GPIO
ports (Port A, Port B, Port C, and Port D).
25.5.3.1 Input Configuration Register A1
ICONFA1_A
ICONFA1_B
ICONFA1_C
ICONFA1_D
BIT
31
Addr
0x0021C00C
0x0021C10C
0x0021C20C
0x0021C30C
Port A Input Configuration Register A1
Port B Input Configuration Register A1
Port C Input Configuration Register A1
Port D Input Configuration Register A1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ICONFA1
pin 15
TYPE
pin 14
pin 13
pin 12
pin 11
pin 10
pin 9
pin 8
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
RESET
0xFFFF
BIT
15
14
13
12
11
10
9
8
ICONFA1
pin 7
TYPE
pin 6
pin 5
pin 4
pin 3
pin 2
pin 1
pin 0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
0xFFFF
Table 25-7. Input Configuration Register A1 Description
Name
Description
ICONFA1 [i]
Bits 31–0
Input Configuration—Corresponds to pins 0–15
of the port and defines which one of the four
options is driven to AOUT [i]. Each port pin [i] (i = 0
through 15) requires two ICONFA1 bits to
determine the input value.
Settings
ICONFA1
[2i + 1]
ICONFA1
[2i]
Input Selected
0
0
GPIO-In [i]
0
1
Interrupt Status Register [i]
1
0
0
1
1
1
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
25-11
Programming Model
25.5.3.2 Input Configuration Register A2
ICONFA2_A
ICONFA2_B
ICONFA2_C
ICONFA2_D
BIT
31
Addr
0x0021C010
0x0021C110
0x0021C210
0x0021C310
Port A Input Configuration Register A2
Port B Input Configuration Register A2
Port C Input Configuration Register A2
Port D Input Configuration Register A2
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ICONFA2
pin 31
TYPE
pin 30
pin 29
pin 28
pin 27
pin 26
pin 25
pin 24
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
RESET
0xFFFF
BIT
15
14
13
12
11
10
9
8
ICONFA2
pin 23
TYPE
pin 22
pin 21
pin 20
pin 19
pin 18
pin 17
pin 16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
0xFFFF
Table 25-8. Input Configuration Register A2 Description
Name
Description
ICONFA2 [i]
Bits 31–0
Input Configuration—Corresponds to pins
16–31 of the port and defines which one of the
four options is driven to AOUT [i]. Each port pin [i]
(i = 16 through 31) requires two ICONFA2 bits to
determine the input value.
Settings
ICONFA2
[2i – 32 + 1]
ICONFA2
[2i – 32]
Input Selected
0
0
GPIO-In [i]
0
1
Interrupt Status Register [i]
1
0
0
1
1
1
MC9328MXS Reference Manual, Rev. 1.1
25-12
Freescale Semiconductor
Programming Model
25.5.3.3 Input Configuration Register B1
ICONFB1_A
ICONFB1_B
ICONFB1_C
ICONFB1_D
BIT
31
Addr
0x0021C014
0x0021C114
0x0021C214
0x0021C314
Port A Input Configuration Register B1
Port B Input Configuration Register B1
Port C Input Configuration Register B1
Port D Input Configuration Register B1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ICONFB1
pin 15
TYPE
pin 14
pin 13
pin 12
pin 11
pin 10
pin 9
pin 8
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
RESET
0xFFFF
BIT
15
14
13
12
11
10
9
8
ICONFB1
pin 7
TYPE
pin 6
pin 5
pin 4
pin 3
pin 2
pin 1
pin 0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
0xFFFF
Table 25-9. Input Configuration Register B1 Description
Name
Description
ICONFB1 [i]
Bits 31–0
Input Configuration—Corresponds to pins 0–15 of
the port and defines which one of the four options is
driven to BOUT [i]. Each port pin [i] (i = 0 through
15) requires two ICONFB1 bits to determine the
input value.
Settings
ICONFB1
[2i + 1]
ICONFB1
[2i]
Input Selected
0
0
GPIO-In [i]
0
1
Interrupt Status Register [i]
1
0
0
1
1
1
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
25-13
Programming Model
25.5.3.4 Input Configuration Register B2
ICONFB2_A
ICONFB2_B
ICONFB2_C
ICONFB2_D
BIT
31
Addr
0x0021C018
0x0021C118
0x0021C218
0x0021C318
Port A Input Configuration Register B2
Port B Input Configuration Register B2
Port C Input Configuration Register B2
Port D Input Configuration Register B2
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ICONFB2
pin 31
TYPE
pin 30
pin 29
pin 28
pin 27
pin 26
pin 25
pin 24
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
RESET
0xFFFF
BIT
15
14
13
12
11
10
9
8
ICONFB2
pin 23
TYPE
pin 22
pin 21
pin 20
pin 19
pin 18
pin 17
pin 16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
0xFFFF
Table 25-10. Input Configuration Register B2 Description
Name
Description
ICONFB2 [i]
Bits 31–0
Input Configuration—Corresponds to pins
16–31 of the port and defines which one of the
four options is driven to BOUT [i]. Each port
pin [i] (i = 16 through 31) requires two
ICONFB2 bits to determine the input value.
Settings
ICONFB2
[2i – 32 + 1]
ICONFB2
[2i – 32]
Input Selected
0
0
GPIO-In [i]
0
1
Interrupt Status Register [i]
1
0
0
1
1
1
MC9328MXS Reference Manual, Rev. 1.1
25-14
Freescale Semiconductor
Programming Model
25.5.4 Data Registers
The Port X Data Register holds the value to be output from port X when a pin is configured as an output and the
Data Register is chosen in the Output Configuration Register 1 and Output Configuration Register 2.
There are four distinct Data Registers; each holds the data for one of the four GPIO ports (Port A, Port B, Port C,
and Port D).
DR_A
DR_B
DR_C
DR_D
BIT
Addr
0x0021C01C
0x0021C11C
0x0021C21C
0x0021C31C
Port A Data Register
Port B Data Register
Port C Data Register
Port D Data Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 25-11. Data Register Description
Name
DR [i]
Bits 31–0
Description
Data—Contains the GPIO output values when the Output Configuration
Registers select the Data Register as the output for the pin (selection 11).
Settings
0 = Drives the output signal low
1 = Drives the output signal high
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
25-15
Programming Model
25.5.5 GPIO In Use Registers
The GPIO In Use Registers control a multiplexer in the IOMUX module. The settings in these registers choose
whether a pin is used for a peripheral function or for its GPIO function (see Figure 25-1 on page 25-2).
There are four distinct GPIO In Use Registers; each holds the data for one of the four GPIO ports (Port A, Port B,
Port C, and Port D).
GIUS_A
GIUS_B
GIUS_C
GIUS_D
BIT
Addr
0x0021C020
0x0021C120
0x0021C220
0x0021C320
Port A GPIO In Use Register
Port B GPIO In Use Register
Port C GPIO In Use Register
Port D GPIO In Use Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
GIUS
TYPE
rw
rw
rw
rw
rw
rw
rw
Reset Value A = INUSE_RESET_SEL [31:16] = 0x00C3
Reset Value B = INUSE_RESET_SEL [31:16] = 0xFFFF
Reset Value C = INUSE_RESET_SEL [31:16] = 0x0007
Reset Value D = INUSE_RESET_SEL [31:16] = 0xFFFF
RESET
BIT
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
GIUS
TYPE
RESET
rw
rw
rw
rw
rw
rw
rw
rw
Reset Value A = INUSE_RESET_SEL [15:0] = 0xFFFE
Reset Value B = INUSE_RESET_SEL [15:0] = 0xFFFF
Reset Value C = INUSE_RESET_SEL [15:0] = 0xFFFF
Reset Value D = INUSE_RESET_SEL [15:0] = 0xFFFF
Table 25-12. GPIO In Use Register Description
Name
Description
GIUS [i]
Bits 31–0
GPIO In Use—Informs the IOMUX module whether the port pin in used for
its GPIO function. When the pin is used for its GPIO function, the
multiplexed functions are not available. The reset value of this register is
determined by the input value of the signal INUSE_RESET_SEL [31:0].
Settings
0 = Pin used for multiplexed
function
1 = Pin used for GPIO function
MC9328MXS Reference Manual, Rev. 1.1
25-16
Freescale Semiconductor
Programming Model
25.5.6 Sample Status Registers
The read-only Sample Status Registers contain the value of the GPIO pins for the port. The register is updated on
every clock. The contents are used as a status value when the pins are configured as inputs.
There are four distinct Sample Status Registers; each holds the data for one of the four GPIO ports (Port A, Port B,
Port C, and Port D).
SSR_A
SSR_B
SSR_C
SSR_D
BIT
Addr
0x0021C024
0x0021C124
0x0021C224
0x0021C324
Port A Sample Status Register
Port B Sample Status Register
Port C Sample Status Register
Port D Sample Status Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SSR
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SSR
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 25-13. Sample Status Register Description
Name
SSR [i]
Bits 31–0
Description
Sample Status—Contains the value of the GPIO pin [i]. It is sampled on every
clock.
Settings
0 = Pin value is low
1 = Pin value is high
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
25-17
Programming Model
25.5.7 Interrupt Configuration Registers
These registers specify the external interrupt configuration for each of the 32 interrupts. There are two bits in the
interrupt configuration registers for each port pin.
There are two interrupt configuration registers for each port; each holds the data for one of the four GPIO ports
(Port A, Port B, Port C, and Port D).
25.5.7.1 Interrupt Configuration Register 1
ICR1_A
ICR1_B
ICR1_C
ICR1_D
BIT
Addr
0x0021C028
0x0021C128
0x0021C228
0x0021C328
Port A Interrupt Configuration Register 1
Port B Interrupt Configuration Register 1
Port C Interrupt Configuration Register 1
Port D Interrupt Configuration Register 1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ICR1
pin 15
TYPE
pin 14
pin 13
pin 12
pin 11
pin 10
pin 9
pin 8
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
ICR1
pin 7
TYPE
pin 6
pin 5
pin 4
pin 3
pin 2
pin 1
pin 0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 25-14. Interrupt Configuration Register 1 Description
Name
ICR1 [i]
Bits 31–0
Description
Interrupt Configuration—Corresponds to
interrupts 0–15 of the port and defines which one of
the four options is the sensitivity of the interrupt.
Each interrupt [i] (i = 0 through 15) requires two
ICR1 bits to determine the sensitivity.
Settings
ICR1
[2i + 1]
ICR1
[2i]
Sensitivity Selected
0
0
Positive edge sensitive
0
1
Negative edge sensitive
1
0
Positive level sensitive
1
1
Negative level sensitive
MC9328MXS Reference Manual, Rev. 1.1
25-18
Freescale Semiconductor
Programming Model
25.5.7.2 Interrupt Configuration Register 2
ICR2_A
ICR2_B
ICR2_C
ICR2_D
BIT
Addr
0x0021C02C
0x0021C12C
0x0021C22C
0x0021C32C
Port A Interrupt Configuration Register 2
Port B Interrupt Configuration Register 2
Port C Interrupt Configuration Register 2
Port D Interrupt Configuration Register 2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ICR2
pin 31
TYPE
pin 30
pin 29
pin 28
pin 27
pin 26
pin 25
pin 24
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
ICR2
pin 23
TYPE
pin 22
pin 21
pin 20
pin 19
pin 18
pin 17
pin 16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 25-15. Interrupt Configuration Register 2 Description
Name
Description
ICR2 [i]
Bits 31–0
Interrupt Configuration—Corresponds to interrupts
16–31of the port and defines which one of the four
options is the sensitivity of the interrupt. Each
interrupt [i] (i = 16 through 31) requires two ICR2 bits
to determine the sensitivity.
Settings
ICR2
[2i – 32 + 1]
ICR2
[2i – 32]
Sensitivity Selected
0
0
Positive edge sensitive
0
1
Negative edge sensitive
1
0
Positive level sensitive
1
1
Negative level sensitive
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
25-19
Programming Model
25.5.8 Interrupt Mask Registers
The Interrupt Mask Registers determine whether an interrupt is active. When an interrupt event occurs and the bit
in this register is set (active), then the corresponding bit in the Interrupt Status Register (ISR) is set.
There are four distinct Interrupt Mask Registers; each holds the data for one of the four GPIO ports (Port A, Port B,
Port C, and Port D).
IMR_A
IMR_B
IMR_C
IMR_D
BIT
Addr
0x0021C030
0x0021C130
0x0021C230
0x0021C330
Port A Interrupt Mask Register
Port B Interrupt Mask Register
Port C Interrupt Mask Register
Port D Interrupt Mask Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IMR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
IMR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 25-16. Interrupt Mask Register Description
Name
IMR [i]
Bits 31–0
Description
Interrupt Mask—Masks the interrupts for this module.
Settings
0 = Interrupt is masked
1 = Interrupt is not masked
MC9328MXS Reference Manual, Rev. 1.1
25-20
Freescale Semiconductor
Programming Model
25.5.9 Interrupt Status Registers
The Interrupt Status Registers indicate whether an interrupt has occurred. When an interrupt event occurs and the
corresponding bit in the Interrupt Mask Register (IMR) is set (interrupt is active), then the bit in this register is set.
There are four distinct Interrupt Status Registers; each holds the data for one of the four GPIO ports (Port A, Port
B, Port C, and Port D).
ISR_A
ISR_B
ISR_C
ISR_D
BIT
Addr
0x0021C034
0x0021C134
0x0021C234
0x0021C334
Port A Interrupt Status Register
Port B Interrupt Status Register
Port C Interrupt Status Register
Port D Interrupt Status Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ISR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
ISR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 25-17. Interrupt Status Register Description
Name
ISR [i]
Bits 31–0
Description
Interrupt Status—Indicates whether the interrupt [i] has occurred for this
module. Write 1 to clear.
Settings
0 = Interrupt has not occurred
1 = Interrupt has occurred
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
25-21
Programming Model
25.5.10 General Purpose Registers
The General Purpose Registers control a multiplexer in the IOMUX module. The settings in these registers choose
whether a pin is used for its primary peripheral function or for its alternate peripheral function (see Figure 25-1 on
page 25-2).
There are four distinct General Purpose Registers; each holds the data for one of the four GPIO ports (Port A, Port
B, Port C, and Port D).
GPR_A
GPR_B
GPR_C
GPR_D
BIT
Addr
0x0021C038
0x0021C138
0x0021C238
0x0021C338
Port A General Purpose Register
Port B General Purpose Register
Port C General Purpose Register
Port D General Purpose Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
GPR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
GPR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 25-18. General Purpose Register Description
Name
Description
GPR [i]
Bits 31–0
General Purpose—Selects between the primary and alternate functions
of the pin. When the associated bit in the GIUS register is set, this bit has
no meaning.
Settings
0 = Select primary pin function
1 = Select alternate pin function
Note: Ensure that this bit is cleared when there is no alternate function
for a particular pin.
MC9328MXS Reference Manual, Rev. 1.1
25-22
Freescale Semiconductor
Programming Model
25.5.11 Software Reset Registers
The Software Reset Registers control the reset of the GPIO module. When the SWR bit of the Port X Software
Reset Register is set, the GPIO circuitry for Port X resets immediately.
There are four distinct Software Reset Registers; each holds the data for one of the four GPIO ports (Port A, Port B,
Port C, and Port D).
SWR_A
SWR_B
SWR_C
SWR_D
Addr
0x0021C03C
0x0021C13C
0x0021C23C
0x0021C33C
Port A Software Reset Register
Port B Software Reset Register
Port C Software Reset Register
Port D Software Reset Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SWR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 25-19. Software Reset Register Description
Name
Description
Reserved
Bits 31–1
Reserved—These bits are reserved and should read 0.
SWR
Bit 0
Software Reset—Controls software reset of the port. The reset
signal is active for 3 system clock cycles and then it is released
automatically.
Settings
0 = No effect
1 = GPIO circuitry for Port X reset
MC9328MXS Reference Manual, Rev. 1.1
Freescale Semiconductor
25-23
Programming Model
25.5.12 Pull_Up Enable Registers
The Pull_Up Enable Registers enable or disable the pull-up on each port pin. When the pull-up is disabled, then the
pin is tri-stated when not driven.
There are four distinct Pull_Up Enable Registers; each holds the data for one of the four GPIO ports (Port A, Port
B, Port C, and Port D).
NOTE:
The Port C Pull_Up Enable Register has a different reset value than the other Port
A, B or D Pull_Up Enable Registers.
PUEN_A
PUEN_B
PUEN_C
PUEN_D
BIT
31
Addr
0x0021C040
0x0021C140
0x0021C240
0x0021C340
Port A Pull_Up Enable Register
Port B Pull_Up Enable Register
Port C Pull_Up Enable Register
Port D Pull_Up Enable Register
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
11
11
11
1
11
11
11
11
7
6
5
4
3
2
1
0
PUEN
TYPE
rw
1
rw
1
rw
1
rw
1
rw
rw
rw
1
11
11
RESET
0xFFFF/0xF9101
BIT
15
14
13
12
11
10
9
8
PUEN
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
0xFFFF
1.
The reset value for PUEN_C is 0xF910FFFF.
Table 25-20. Pull_Up Enable Register Description
Name
PUEN [i]
Bits 31–0
1.
Description
Settings
Pull_Up Enable—Determines whether the port pin [i] is pulled up1 to
a logic high. When the pin is configured as an input, clearing this bit
causes the signal to be tri-stated when not driven by an external
source. When the pin is configured as an output, clearing this bit
causes the signal to be tri-stated when it is not enabled.
0 = Pin [i] is tri-stated when not driven
internally or externally
1 = Pin [i] is pulled high1 when not
driven internally or externally
PUEN_B bit 11 is pulled down when the bit is set.
MC9328MXS Reference Manual, Rev. 1.1
25-24
Freescale Semiconductor
Index
Numerics
32 kHz Clock signal, see CLK32 signal
A
AIPI
data access to 16-bit peripherals, 7-16
data access to 32-bit peripherals, 7-17
data access to 8-bit peripherals, 7-15
features, 7-1
general information, 7-1
non-natural size access, 7-18
overview, 7-1
programming example, 7-15
programming model, 7-8
AIPI 1 & 2 peripheral size register 0, see PSR0_n,
AIPI 1 & 2 peripheral size register 1, see PSR1_n,
AIPI module register memory map, 7-8
AIPI peripheral address MODULE_EN numbers, 7-8
AIPI registers
PAR_n, 7-12
PCR_n, 7-13
PSR0_n, 7-10
PSR1_n, 7-11
TSR_n, 7-14
AITC
assigning interrupt sources, 10-33
enabling interrupt sources, 10-33
features, 10-1
input signals, 10-3
interrupt assignments, 10-3
introduction, 10-1
operation, 10-2-10-3
prioritization of interrupt sources, 10-33
programming model, 10-4
register field summary, 10-5
register memory map, 10-4
writing reentrant normal interrupt routines, 10-35
ALRM_HM register
HOURS field, 18-9
MINUTES field, 18-9
ALRM_HM register, 18-9
ALRM_SEC register
SECONDS field, 18-10
ALRM_SEC register, 18-10
ARM Thumb
instruction set, 4-7
ARM920T processor
ARMv4T Architecture, 4-4
cache lock-down, 4-3
caches, 4-3
conditional execution, 4-5
control coprocessor, 4-4
exception types, 4-5
instruction classes, 4-5-4-7
instruction set, 4-7
introduction, 4-1
macrocell, 4-2
MMUs, 4-3
modes and exception handling, 4-4
modes and registers, 4-9
PATAG RAM, 4-3
prioritization of exception sources, 10-33
Registers, 4-4
reset, 6-2
status registers, 4-5
system controller, 4-3
typical interrupt entry sequences, 10-34
write buffer, 4-3
Atomic read/modify/write sequence, 10-10
AUCR3_1 register
WAKEN bit, 21-33
B
BIPRx_x
INCPI field, 21-49
BIPRx_x, 21-49
BLRx register
BL bit, 13-26
BLRx register, 13-26
BMPRx_x register
MODI field, 21-50
BMPRx_x register, 21-50
Bootstrap mode
bootloader flowchart, 9-7
B-record examples, 9-3
changing communication speed, 9-3
entering, 9-1
instruction buffer, 9-3
operation of, 9-1
programming notes, 9-7
read/write examples, 9-5
record format, 9-2
register usage, 9-2
setting up RS-232 terminal, 9-3
BUCRx register
CCNT field, 13-29
BUCRx register, 13-29
C
CAP field, 20-4
CAPT bit, 20-9
Capture edge field, see CAP field
Capture edge, see CAP bit
MC9328MXS Reference Manual, Rev. 1
Freescale Semiconductor
Index-i
Capture event, see CAPT bit
CAPTURE VALUE field, 20-7
CCRx register
CEN bit, 13-24
DMOD field, 13-22
DSIZ field, 13-23
FRC bit, 13-23
MDIR bit, 13-23
MSEL bit, 13-23
REN bit, 13-23
RPT bit, 13-23
SMOD field, 13-23
SSIZ field, 13-23
CCRx register, 13-22
Channel x burst length register, see BLRx register 13-26
Channel x bus utilization control register, see BUCRx
register
Channel x control register, see CCRx register
Channel x count register, see CNTRx register
Channel x destination address register, see DARx register
Channel x request source select register, see RSSRx register
Channel x request time-out register, see RTORx register
Channel x source address register, see SARx register
Chip select 0 control registers see CSOU and CSOL registers
Chip select 1 - 5 control registers see CS1U - CS5U and
CS1L - CS5L registers
CLK32 signal, 6-3
CLKSOURCE field, 20-5
Clock source control register, see CSCR register
Clock source, see CLKSOURCE field
CNTRx register
CNT field, 13-21
CNTRx register, 13-21
COMP bit, 20-9
Compare event, see COMP bit
COMPARE VALUE field, 20-6
CONTROLREG1 register, 15-7
CONTROLREGx register
BIT_COUNT field, 15-8
DATARATE field, 15-7
DRCTL field, 15-7
MODE bit, 15-7
PHA bit, 15-8
POL bit, 15-8
SPIEN bit, 15-7
SSCTL bit, 15-8
SSPOL bit, 15-8
XCH bit, 15-8
Core test reset, see CORE_TRST signal
CORE_TRST signal, 6-3
COUNT field, 20-8
Counter value, see COUNT field
CP15, see ARM920T processor, control coprocessor,
CPOS register
CC field, 16-29
CXP field, 16-29
CYP field, 16-29
OP bit, 16-29
CPOS register, 16-29
CS0L register, 11-12
CS0U register, 11-11
CS1L register, 11-13
CS2L register, 11-13
CS3L register, 11-13
CS4L register, 11-13
CS5L register, 11-13
CSCR register
BCLK_DIV field, 12-7
CLKO_SEL field, 12-6
MPEN bit, 12-7
MPLL_RESTART bit, 12-7
OSC_EN bit, 12-7
PRESC bit, 12-7
SD_CNT field, 12-6
SPEN bit, 12-7
SPLL_RESTART bit, 12-7
System_SEL bit, 12-7
USB_DIV field, 12-6
CSCR register, 12-6
CTS
de-assertion, programmable, 21-8
D
DARx register
DA field, 13-20
DARx register, 13-20
DAYALARM register
DAYSAL field, 18-8
DAYALARM register, 18-8
DAYR register
DAYS field, 18-5
DAYR register, 18-5
DBOSR register
bits CH10 through CH0, 13-14
DBOSR register, 13-14
DBTOCR register
CNT field, 13-15
EN bit, 13-15
DBTOCR register, 13-15
DBTOSR register
bits CH10 through CH0, 13-11
DBTOSR register, 13-11
DCR register
DEN bit, 13-8
DRST bit, 13-8
DCR register, 13-8
DDIR_A register, 25-8
MC9328MXS Reference Manual, Rev. 1
Index-ii
Freescale Semiconductor
DDIR_B register, 25-8
DDIR_C register, 25-8
DDIR_D register, 25-8
DDIR_x
DDIR field, 25-8
DIMR register
bits CH10 through CH0, 13-10
DISNUM field, 10-10
DISR register, 13-9
DMA buffer overflow status register, see DBOSR register
DMA burst time-out control register, see DBTOCR register
DMA burst time-out status register, see DBTOSR register
DMA control register, see DCR register
DMA control register, see DMACR register
DMA interrupt mask register, see DIMR register
DMA interrupt status register, see DISR register
DMA request time-out status register, see DRTOSR register
DMA transfer error status register, see DSESR register
DMAC
2D memory registers (A & B), 13-16
big endian/little endian byte-ordering, 13-4
block diagram, 13-2
channel registers, 13-18
DMA request table, 13-29
features, 13-1
general registers, 13-8
programming model, 13-4
signal description, 13-3
DMACR register
BURST bit, 16-36
HM field, 16-36
TM field, 16-36
DMACR register, 16-36
DMAREG1 register, 15-13
DMAREGx register
RFDEN bit, 15-13
RHDEN bit, 15-13
RHDMA bit, 15-14
TEDEN bit, 15-13
TEDMA bit, 15-13
THDEN bit, 15-13
THDMA bit, 15-13
DR_A register, 25-15
DR_B register, 25-15
DR_C register, 25-15
DR_D register, 25-15
DR_x register
DR field, 25-15
DRAM reset, see RESET_DRAM signal
DRTOSR register
bits CH10 through CH0, 13-12
DRTOSR register, 13-12
DSESR register
bits CH10 through CH0, 13-13
DSESR register, 13-13
DTR edge triggered interrupt, 21-7
E
EIM
address bus, 11-1
burst mode signals, 11-3
chip select outputs, 11-2
control signals, 11-2
data bus, 11-1
I O signals, 11-1
overview, 11-1
pin configuration, 11-3
programming model, 11-10
read and write signals, 11-1
system connections, typical, 11-5
EIM configuration register see EIM register
EIM functionality
burst clock divisor, 11-8
burst clock start, 11-9
burst mode operation, 11-8
configurable bus sizing, 11-8
error conditions, 11-9
page mode emulation, 11-9
programmable output generation, 11-8
EIM register, 11-21
Embedded Trace Macrocell, see ETM
Endpointx data register, see USB_EPx_FDAT register
Endpointx FIFO alarm register, see USB_EPx_FALRM
register
Endpointx FIFO write pointer register, see
USB_EPx_FWRP register
Endpointx interrupt mask register, see USB_EPx_MASK
register
Endpointx interrupt status register, see USB_EPx_INTR
register
Endpointx last read frame pointer register, see
USB_EPx_LRFP register
Endpointx last write frame pointer register, see
USB_EPx_LWFP register
EndpointxFIFO read pointer register, see USB_EPx_FRDP
register,
EndpointxFIFO Status Register, see USB_EPx_FSTAT
register
ENNUM field, 10-9
ETM
block diagram, 5-1
introduction, 5-1
pin configuration, 5-2
registers, programming and reading, 5-2
EXR bit, 6-4
External Interface Module see EIM module
External reset bit, see EXR bit
MC9328MXS Reference Manual, Rev. 1
Freescale Semiconductor
Index-iii
F
Fast interrupt
arbiter disable, see FIAD bit
pending bit, see FIPEND field
pending register high, see FIPNDH register
pending register low, see FIPNDL register
vector and status register, see FIVECSR register
vector, see FIVECTOR field
Fast interrupt pending bit, see FIPEND field
FIPEND field, 10-31, 10-32
FIPNDH register, 10-31
FIPNDL register, 10-32
FIVECSR register, 10-24
FIVECTOR field, 10-24
FORCE field, 10-27, 10-28
Four bits/pixel grayscale mode
GPM field, 16-39
Free-run/restart, see FRR bit
FRR bit, 20-4
Function multiplexing control register, see FMCR register
G
General purpose timers
programming model, 20-3
GIUS_A register, 25-16
GIUS_B register, 25-16
GIUS_C register, 25-16
GIUS_D register, 25-16
GIUS_x register
GIUS field, 25-16
Global peripheral control register, see GPCR register
GPIO
data direction registers, 25-8
data registers, 25-15
general description, 25-1
general purpose registers, 25-22
in use registers, 25-16
Input configuration registers, 25-11
interrupt configuration registers, 25-18
interrupt mask registers, 25-20
interrupt status registers, 25-21
interrupts, 25-3
module block diagram, 25-4
module features, 25-2
module overview, 25-2
output configuration registers, 25-9
pin configuration, 25-4
programming model, 25-5
pull_up enable registers, 25-24
sample status registers, 25-17
signal description, 25-3
software reset registers, 25-23
GPR_A register, 25-22
GPR_B register, 25-22
GPR_C register, 25-22
GPR_D register, 25-22
GPR_x register
GPR field, 25-22
H
Hard asynchronous reset, see HARD_ASYN_RESET signal
Hard reset signal, see HARD_RESET signal
HARD_ASYN_RESET signal, 6-3
HCR register
H_WAIT_1 field, 16-26
H_WAIT_2 field, 16-26
H_WIDTH field, 16-26
HCR register, 16-26
Horizontal configuration register, see HCR register
HOURMIN register
HOURS field, 18-6
HOURMIN register, 18-6
HOURMIN register, MINUTES field, 18-6
HRESET signal, 6-3
I
I2C
Address Register, see IADR register
arbitration procedure, 23-4, 23-5
clock stretching, 23-5
clock synchronization, 23-4
handshaking, 23-5
initialization sequence, 23-14
interface features, 23-1
lost arbitration, 23-15
module, see I2C
overview, 23-1
pin configuration, 23-5
programming
examples, 23-13
model, 23-6
protocol, communication, 23-3
repeated START generation, 23-15
slave mode, 23-15
software response, post transfer, 23-14
START signal, generation, 23-14
STOP generation, 23-15
I2C control register, see I2CR register
I2C data I/O register, see I2DR register
I2C frequency divider register, see IFDR register
I2C status register, see I2CSR register
I2CR register
IEN bit, 23-10
IIEN bit, 23-10
MC9328MXS Reference Manual, Rev. 1
Index-iv
Freescale Semiconductor
MSTA bit, 23-10
MTX bit, 23-11
RSTA bit, 23-11
TXAK bit, 23-11
I2CR register, 23-10
I2CSR register
IAAS bit, 23-12
IAL bit, 23-12
IBB bit, 23-12
ICF bit, 23-12
IIF bit, 23-12
RXAK bit, 23-12
SRW bit, 23-12
I2CSR register, 23-11
I2DR register
D field, 23-13
I2DR register, 23-13
IADR register
ADR field, 23-7
IADR register, 23-7
ICONFA1_A register, 25-11
ICONFA1_C register, 25-11
ICONFA1_D register, 25-11
ICONFA1_x register
ICONFA1 field, 25-11
ICONFA2_A register, 25-12
ICONFA2_B register, 25-12
ICONFA2_C register, 25-12
ICONFA2_D register, 25-12
ICONFA2_x register
ICONFA2 field, 25-12
ICONFB1_A register, 25-13
ICONFB1_B register, 25-13
ICONFB1_C register, 25-13
ICONFB1_D register, 25-13
ICONFB1_x register
ICONFB1 field, 25-13
ICONFB2_A register, 25-14
ICONFB2_B register, 25-14
ICONFB2_C register, 25-14
ICONFB2_D register, 25-14
ICONFB2_x register
ICONFB2 field, 25-14
ICR1_A register, 25-18
ICR1_B register, 25-18
ICR1_C register, 25-18
ICR1_D register, 25-18
ICR1_x register
ICR1 field, 25-18
ICR2_A register, 25-19
ICR2_B register, 25-19
ICR2_C register, 25-19
ICR2_D register, 25-19
ICR2_x register
ICR2 field, 25-19
IFDR register
IC field, 23-8
IFDR register, 23-8
IMR_A register, 25-20
IMR_B register, 25-20
IMR_C register, 25-20
IMR_D register, 25-20
IMR_x register
IMR field, 25-20
INTCNTL register
FIAD bit, 10-7
NIAD bit, 10-7
INTCNTL register, 8-6, 10-6
INTDISNUM register, 10-10
INTENABLE field, 10-11, 10-12
INTENABLEH register, 10-11
INTENABLEL register, 10-12
INTENNUM register, 10-9
Interrupt configuration register, see LCDICR register
Interrupt control register, see INTCNTL register
Interrupt controller, see AITC
Interrupt disable number register, see INTDISNUM register
Interrupt disable number, see DISNUM field
Interrupt enable number register, see INTENNUM register
Interrupt enable number, see ENNUM field
Interrupt enable register high, see INTENABLEH register
Interrupt enable register low, see INTENABLEL register
Interrupt enable, see INTENABLE field
Interrupt Force Register High, see INTFRCH register
Interrupt force register low, see INTFRCL register
Interrupt request enable, see IRQEN bit
Interrupt source force request, see FORCE field
Interrupt source register high, see INTSRCH register
Interrupt source register low, see INTSRCL register
Interrupt source, see INTIN field
Interrupt source, see INTIN field
Interrupt status register, see LCDISR register
Interrupt type register high, see INTTYPEH register
Interrupt type register low, see INTTYPEL register
Interrupt type, see INTTYPE field
INTFRCH register, 10-27
INTFRCL register, 10-28
INTIN field, 10-25, 10-26
INTREG1 register, 15-9
INTREGx register
BO bit, 15-10
BOEN bit, 15-9
RF bit, 15-10
RFEN bit, 15-9
RH bit, 15-10
RHEN bit, 15-9
RO bit, 15-10
ROEN bit, 15-9
MC9328MXS Reference Manual, Rev. 1
Freescale Semiconductor
Index-v
RR bit, 15-10
RREN bit, 15-9
TE bit, 15-10
TEEN bit, 15-9
TF bit, 15-10
TFEN bit, 15-9
TH bit, 15-10
THEN bit, 15-9
INTSRCH register, 10-25
INTSRCL register, 10-26
INTTYPE field, 10-13, 10-14
INTTYPEH register, 10-13
INTTYPEL register, 10-14
IRQEN bit, 20-4
ISR_A register, 25-21
ISR_B register, 25-21
ISR_C register, 25-21
ISR_D register, 25-21
ISR_x register
ISR field, 25-21
L
LCD color cursor mapping register, see LCHCC register
LCD cursor position, see CPOS register
LCD cursor width height and blink register, see LCWHB
register
LCD gray palette mapping register, see LSCR1 register
LCDC
active matrix panel interface signals
"digital CRT", 16-14
active matrix panel interface signals, 16-14
active panel interface timing, 16-16
black-and-white operation, 16-7
color generation, 16-8
display data mapping, 16-3
features, 16-1
frame rate modulation control, 16-10
gray scale operation, 16-7
introduction, 16-1
mapping RAM registers, 16-39
operation, 16-2
panel interface signals, 16-11
panning
typical panning algorithm, 16-3
panning, 16-3
passive panel interface timing, 16-13
pin configuration
setting data direction, 16-11
pin configuration, 16-11
programming model, 16-18
screen format
maximum page width, 16-3
screen format, 16-2
using VPH for boundary checks, 16-3
LCDICR register
INTCON bit, 16-37
INTSYN bit, 16-37
LCDICR register, 16-37
LCDISR register
BOF bit, 16-38
EOF bit, 16-38
ERR_RES bit, 16-38
UDR_ERR bit, 16-38
LCDISR register, 16-38
LCHCC register
CUR_COL_B register, 16-31
CUR_COL_G register, 16-31
CUR_COL_R register, 16-31
LCHCC register, 16-31
LCWHB register
BD field, 16-30
BK_EN bit, 16-30
CH field, 16-30
CW field, 16-30
LCWHB register, 16-30
LGPMR register, see LSCR1 register
LSCR1 register
CLS_RISE_DELAY field, 16-32
GRAY 1 register, 16-32
GRAY 2 register, 16-32
PS_RISE_DELAY field, 16-32
REV_TOGGLE_DELAY field, 16-32
M
Mapping RAM registers
eight bits/pixel active matrix color mode register, 16-41
eight bits/pixel passive matrix color mode, 16-40
four bits/pixel active matrix color mode, 16-41
four bits/pixel gray-scale mode, 16-39
four bits/pixel passive matrix color mode, 16-40
one bit/pixel mono mode, 16-39
twelve bits/pixel active matrix color mode, 16-42
MC9328MXS
features of, 1-2-1-8
internal registers, 3-6
MCU PLL and system clock control register 1, see MPCTL1
register
MCU PLL control register 0, see MPCTL0 register
Memory space
double map image, 3-5
external memory, 3-5
internal register space, 3-4
memory map description, 3-1
Memory space, 3-1
MISCELLANEOUS register
OMA bit, 19-17
MC9328MXS Reference Manual, Rev. 1
Index-vi
Freescale Semiconductor
OCR2_A register, 25-10
OCR2_B register, 25-10
OCR2_C register, 25-10
OCR2_D register, 25-10
OCR2_x register
OCR2 field, 25-10
OM bit, 20-4
Output mo

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