NXP i.MX27 Multimedia Applications Processors - Robust Security Reference Manual

NXP i.MX27 Multimedia Applications Processors - Robust Security Reference Manual
An addendum, entitled Addendum to Rev. 0.3 of MCIMX27
Multimedia Applications Processor Reference Manual (Rev. 0.4)
has been added at the end of this document.
MCIMX27 Multimedia
Applications Processor
Reference Manual
MCIMX27RM
Rev. 0.4
06/2012
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Document Number: MCIMX27RM
Rev. 0.4
06/2012
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Contents
Paragraph
Number
Title
Page
Number
Contents
Chapter 1
Introduction to the i.MX27 Multimedia Applications Processor
1.1
1.2
1.2.1
1.2.2
1.2.2.1
1.2.2.2
1.2.3
1.2.3.1
1.2.3.2
1.2.3.3
1.2.3.4
1.2.3.5
1.2.3.6
1.2.4
1.2.4.1
1.2.4.2
1.2.4.3
1.2.5
1.2.5.1
1.2.5.2
1.2.5.3
1.2.5.4
1.2.6
1.2.6.1
1.2.6.2
1.2.6.3
1.2.6.4
1.2.6.4.1
1.2.6.4.2
1.2.6.4.3
1.2.6.4.4
1.2.7
1.2.7.1
1.2.7.2
1.2.7.3
1.2.7.4
1.2.7.5
i.MX27 Applications Processor Block Diagram ............................................................. 1-2
Summary of Core and Modules ....................................................................................... 1-2
ARM9™ Platform ....................................................................................................... 1-2
System Control ............................................................................................................ 1-4
Clock Controller Module (CCM) ............................................................................ 1-4
JTAG Controller (JTAGC) ....................................................................................... 1-4
Standard System Resources ......................................................................................... 1-4
General Purpose Timer (GPT) ................................................................................. 1-5
Pulse-Width Modulator (PWM) .............................................................................. 1-5
Real Time Clock (RTC) ........................................................................................... 1-5
Watchdog Timer Module (WDOG) ......................................................................... 1-5
General-Purpose I/O Ports (GPIO).......................................................................... 1-6
Direct Memory Access Controller (DMAC) ........................................................... 1-6
Power Management and Backup Modes...................................................................... 1-6
SCC, RTC, and Oscillator Power Supply ................................................................ 1-6
Enter/Exit Mode....................................................................................................... 1-7
Reset Strategy ..................................................................................................... 1-7
System Security ........................................................................................................... 1-7
Security Controller Module (SCC).......................................................................... 1-7
Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2) ............. 1-7
Run-Time Integrity Checkers (RTIC) ...................................................................... 1-8
IC Identification Module (IIM)................................................................................ 1-8
Connectivity................................................................................................................. 1-9
Configurable Serial Peripheral Interfaces (CSPI).................................................... 1-9
Inter-IC Connectivity (I2C) Bus Module ............................................................... 1-10
Synchronous Serial Interface (SSI) ....................................................................... 1-10
Bus Control ............................................................................................................ 1-10
AHB-Lite IP Interface Module (AIPI) .............................................................. 1-11
ARM926EJ-S Interrupt Controller (AITC) ....................................................... 1-11
Intellectual Property Bus Multiplexer (IPMUX) ............................................... 1-11
Multi-Layer AHB Crossbar Switch (MAX) ...................................................... 1-11
Wireline Connectivity ................................................................................................ 1-11
Universal Asynchronous Receiver/Transmitter (UART) ....................................... 1-11
High Speed USB 2.0 Interface (USB) ................................................................... 1-12
1-Wire Interface (1-Wire) ...................................................................................... 1-12
Advanced Technology Attachment (ATA)............................................................. 1-12
Fast Ethernet Controller (FEC).............................................................................. 1-12
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Paragraph
Number
1.2.8
1.2.8.1
1.2.8.2
1.2.8.3
1.2.8.4
1.2.8.5
1.2.9
1.2.9.1
1.2.9.2
1.2.10
1.2.10.1
1.2.10.2
1.2.10.2.1
1.2.10.2.2
1.2.10.3
1.2.11
1.2.11.1
1.2.12
1.2.12.1
1.2.12.2
1.2.12.3
1.2.13
Title
Page
Number
External Memory Interface........................................................................................ 1-13
Multi-Master Memory Interface (M3IF) ............................................................... 1-13
SDRAM Controller (SDRAMC) ........................................................................... 1-14
NAND Flash Controller (NFC) ............................................................................. 1-15
Personal Computer Memory Card International Association (PCMCIA)............. 1-15
External Interface Module (EIM) .......................................................................... 1-16
Memory Expansion.................................................................................................... 1-16
Memory Stick Host Controller (MSHC) ............................................................... 1-16
Secured Digital Host Controller (SDHC) .............................................................. 1-17
Video Codec and enhanced Multimedia Accelerator Lite (eMMA_lt) ..................... 1-17
Video Codec........................................................................................................... 1-17
enhanced Multimedia Accelerator Lite (eMMA_lt).............................................. 1-19
Image Pre-Processor (PrP)................................................................................. 1-20
Post-Processor (PP) ........................................................................................... 1-21
Digital Audio Multiplexer (AUDMUX) ................................................................ 1-22
MultiMedia Interface ................................................................................................. 1-23
CMOS Sensor Interface (CSI) ............................................................................... 1-23
Human Interface ........................................................................................................ 1-23
Liquid Crystal Display Controller (LCDC) ........................................................... 1-24
Smart Liquid Crystal Display Controller (SLCDC) .............................................. 1-24
Keypad Port (KPP) ................................................................................................ 1-25
Packaging Information............................................................................................... 1-25
Chapter 2
System Memory and Register Map
2.1
2.2
2.2.1
2.3
Introduction...................................................................................................................... 2-1
Memory Space ................................................................................................................. 2-1
Detailed Memory Map................................................................................................. 2-1
Register Map.................................................................................................................... 2-7
Chapter 3
Clocks, Power Management, and Reset Control
3.1
3.2
3.2.1
3.2.2
3.3
3.3.1
3.3.2
Introduction...................................................................................................................... 3-1
Clock Controller Architecture Block Diagram ................................................................ 3-1
High Frequency Clock Source and Distribution.......................................................... 3-4
Output Frequency Calculations ................................................................................... 3-5
Power Management ......................................................................................................... 3-5
PLL Operation at Power-Up ........................................................................................ 3-5
PLL Operation at Wake-Up ......................................................................................... 3-5
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Paragraph
Number
3.3.3
3.3.3.1
3.3.3.2
3.3.4
3.3.5
3.3.6
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.8.1
3.4.9
3.4.10
3.4.11
3.4.12
3.4.13
3.4.14
3.5
3.5.1
3.5.2
Title
Page
Number
i.MX27 Processor Low-Power Modes......................................................................... 3-5
Doze Mode............................................................................................................... 3-6
Sleep Mode .............................................................................................................. 3-6
SDRAM Power Modes ................................................................................................ 3-8
Power Management in the PLL Clock Controller ....................................................... 3-8
Power Management Using Frequency Control............................................................ 3-8
Memory Map and Register Definition ............................................................................. 3-9
Register Summary........................................................................................................ 3-9
Clock Source Control Register (CSCR) .................................................................... 3-10
MPLL Control Register 0 (MPCTL0) ....................................................................... 3-13
MCU and System PLL Control Register 1 (MPCTL1) ............................................. 3-15
Programming the Serial Peripheral PLL (SPLL)....................................................... 3-16
SPLL Control Register 0 (SPCTL0).......................................................................... 3-17
SPLL Control Register 1 (SPCTL1).......................................................................... 3-19
Oscillator 26M Register............................................................................................. 3-20
Adjusting the 26 MHz Oscillator Trim.................................................................. 3-20
Peripheral Clock Divider Register 0 (PCDR0) .......................................................... 3-21
Peripheral Clock Divider Register 1 (PCDR1) .......................................................... 3-23
Peripheral Clock Control Register 0 (PCCR0) .......................................................... 3-25
Peripheral Clock Control Register 1 (PCCR1) .......................................................... 3-28
Clock Control Status Register (CCSR)...................................................................... 3-31
Wakeup Guard Mode Control Register (WKGDCTL) .............................................. 3-33
Functional Description of the Reset Module ................................................................. 3-34
Global Reset............................................................................................................... 3-34
ARM9 Platform Reset ............................................................................................... 3-36
Chapter 4
System Control
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10
Introduction...................................................................................................................... 4-1
Memory Map and Register Definition ............................................................................. 4-1
Chip ID Register (CID)................................................................................................ 4-3
Function Multiplexing Control Register (FMCR) ....................................................... 4-4
Global Peripheral Control Register (GPCR) ............................................................... 4-7
Well Bias System ......................................................................................................... 4-8
Well Bias Control Register (WBCR) ........................................................................... 4-9
Drive Strength Control Register 1 (DSCR1) ............................................................. 4-11
Drive Strength Control Register 2 (DSCR2) ............................................................. 4-13
Drive Strength Control Register 3 ............................................................................. 4-15
Drive Strength Control Register 4 ............................................................................. 4-17
Drive Strength Control Register 5 ............................................................................. 4-19
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
4.2.11
4.2.12
4.2.13
4.2.14
4.2.15
4.2.16
4.2.17
4.2.18
4.2.19
4.2.20
4.2.21
4.2.22
4.2.23
4.2.24
4.2.25
4.2.26
4.3
Title
Page
Number
Drive Strength Control Register 6 ............................................................................. 4-21
Drive Strength Control Register 7 ............................................................................. 4-24
Drive Strength Control Register 8 ............................................................................. 4-26
Drive Strength Control Register 9 ............................................................................. 4-28
Drive Strength Control Register 10 ........................................................................... 4-31
Drive Strength Control Register 11 ........................................................................... 4-33
Drive Strength Control Register 12 ........................................................................... 4-35
Drive Strength Control Register 13 ........................................................................... 4-37
Pull Strength Control Register (PSCR) ..................................................................... 4-39
Priority Control and Select Register (PCSR)............................................................. 4-41
Power Management Control Register (PMCR) ......................................................... 4-42
DPTC Comparator Value Register 0 (DCVR0) ......................................................... 4-44
DPTC Comparator Value Register 1 (DCVR1) ......................................................... 4-44
DPTC Comparator Value Register 2.......................................................................... 4-45
DPTC Comparator Value Register 3.......................................................................... 4-46
PMIC Pad Control Register (PPCR).......................................................................... 4-46
System Boot Mode Selection......................................................................................... 4-47
Chapter 5
Signal Descriptions and Pin Assignments
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
Introduction...................................................................................................................... 5-1
Signal Descriptions .......................................................................................................... 5-1
I/O Power Supply and Signal Multiplexing Scheme ....................................................... 5-9
Pull/Pull Strength/Open Drain Descriptions.............................................................. 5-10
GPIO Default and Pull-Up Configuration ................................................................. 5-10
I/O Mode and Supply Level....................................................................................... 5-10
Chapter 6
General-Purpose I/O (GPIO)
6.1
6.2
6.3
6.4
6.5
6.6
6.6.1
6.6.2
6.6.3
6.6.4
Introduction...................................................................................................................... 6-1
Overview.......................................................................................................................... 6-3
GPIO Features.................................................................................................................. 6-3
External Signals Description ........................................................................................... 6-4
Interrupts .......................................................................................................................... 6-4
Memory Map and Register Definitions ........................................................................... 6-4
Register Summary........................................................................................................ 6-8
Data Direction Register (PTn_DDIR) ......................................................................... 6-9
Output Configuration Register 1 (OCR1).................................................................. 6-10
Output Configuration Register 2 (OCR2).................................................................. 6-11
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
6.6.5
6.6.6
6.6.7
6.6.8
6.6.9
6.6.10
6.6.11
6.6.11.1
6.6.11.2
6.6.11.3
6.6.11.4
6.6.11.5
6.6.11.6
6.6.12
6.6.13
6.6.14
6.6.15
6.6.16
6.6.17
6.6.18
6.6.19
6.6.20
Title
Page
Number
Input Configuration Register A1 (ICONFA1) ........................................................... 6-12
Input Configuration Register A2 (ICONFA2) ........................................................... 6-13
Input Configuration Register B1 (ICONFB1) ........................................................... 6-14
Input Configuration Register B2 (ICONFB2) ........................................................... 6-15
Data Register (DR) .................................................................................................... 6-16
GPIO IN USE Registers (GIUS) ............................................................................... 6-17
GPIO IN USE Register Reset Values ........................................................................ 6-17
GPIO IN USE Register A (PTA_GIUS)................................................................ 6-18
GPIO IN USE Register B (PTB_GIUS) ................................................................ 6-18
GPIO IN USE Register C (PTC_GIUS) ................................................................ 6-19
GPIO IN USE Register D (PTD_GIUS) ............................................................... 6-19
GPIO IN USE Register E (PTE_GIUS) ................................................................ 6-20
GPIO IN USE Register F (PTF_GIUS)................................................................. 6-20
Sample Status Register (SSR).................................................................................... 6-21
Interrupt Configuration Register 1 (ICR1) ................................................................ 6-22
Interrupt Configuration Register 2 (ICR2) ................................................................ 6-23
Interrupt Mask Register (IMR) .................................................................................. 6-24
Interrupt Status Register (ISR) .................................................................................. 6-25
General Purpose Register (GPR) ............................................................................... 6-26
Software Reset Register (SWR)................................................................................. 6-27
Pull-Up Enable Register (PUEN) .............................................................................. 6-28
Port Interrupt Mask Register (PMASK) .................................................................... 6-29
Chapter 7
JTAG Controller (JTAGC)
7.1
7.2
7.3
7.4
7.5
7.6
7.6.1
7.6.2
7.7
7.8
7.8.1
7.8.2
7.8.3
7.8.4
7.8.5
Introduction...................................................................................................................... 7-1
Features ............................................................................................................................ 7-1
Implementation ................................................................................................................ 7-1
JTAG Controller Pin List ................................................................................................. 7-2
JTAG Overview................................................................................................................ 7-3
JTAG Modes .................................................................................................................... 7-3
ARM926 Platform mode ............................................................................................ 7-3
i.MX27 JTAG Controller mode .................................................................................. 7-3
Boundary Scan Register................................................................................................... 7-3
Instruction Register.......................................................................................................... 7-4
EXTEST Instruction .................................................................................................... 7-4
SAMPLE/PRELOAD Instruction................................................................................ 7-4
IDCODE Instruction.................................................................................................... 7-5
ENABLE_ExtraDebug Instruction .............................................................................. 7-5
HIGHZ Instruction....................................................................................................... 7-5
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
7.8.6
7.8.7
7.9
7.9.1
7.9.2
7.9.3
7.10
Title
Page
Number
CLAMP Instruction ..................................................................................................... 7-6
BYPASS Instruction .................................................................................................... 7-6
TMS Sequences ............................................................................................................... 7-6
TMS Sequence to Check ID Code............................................................................... 7-6
TMS Sequence to Write to ExtraDebug Register ........................................................ 7-7
TMS Sequence to Read ExtraDebug Register ............................................................. 7-8
i.MX27 JTAG Restrictions............................................................................................... 7-8
Chapter 8
Bootstrap Mode Operation
8.1
8.2
8.3
8.4
8.4.1
8.4.1.1
8.4.1.2
8.4.1.3
8.4.1.4
Introduction...................................................................................................................... 8-1
UART/USB Configuration............................................................................................... 8-1
Enter Bootstrap Mode Configuration............................................................................... 8-1
Bootstrap Flow................................................................................................................. 8-2
Bootstrap Protocol and Definition ............................................................................... 8-3
Synchronization Operation ...................................................................................... 8-3
Write Register Operation ......................................................................................... 8-3
Download Operation................................................................................................ 8-4
Bootstrap End Indication Operation ........................................................................ 8-5
Chapter 9
ARM9 Platform
9.1
9.1.1
9.1.2
9.1.2.1
9.2
9.2.1
9.2.1.1
9.2.1.2
9.2.2
9.2.3
9.2.3.1
9.2.3.2
9.2.3.3
9.2.3.4
9.2.4
9.2.5
9.2.5.1
Introduction.................................................................................................................... 10-1
Design Methodology Summary ................................................................................. 10-2
Performance Characteristics ...................................................................................... 10-3
Performance Target................................................................................................ 10-3
ARM9 Platform Sub-Modules....................................................................................... 10-3
ARM926EJ-S Processor ............................................................................................ 10-3
ARM926EJ-S Co-Processor Interface ................................................................... 10-3
TCM Interfaces...................................................................................................... 10-4
ARM9 Embedded Trace Macrocell and Embedded Trace Buffer............................. 10-4
The 6 x 3 Multi-Layer AHB Crossbar Switch (MAX).............................................. 10-4
MAX Configuration Registers............................................................................... 10-4
Master Ports ........................................................................................................... 10-5
Slave Ports ............................................................................................................. 10-5
Debug Support ....................................................................................................... 10-5
ARM Interrupt Controller (AITC)............................................................................. 10-5
Memory Controller and BIST Engine (MCTL)......................................................... 10-6
RAM ...................................................................................................................... 10-6
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
9.2.5.2
9.2.6
9.2.7
9.2.8
9.2.8.1
9.2.9
9.2.10
9.2.11
9.3
9.4
9.5
9.5.1
9.5.2
9.5.3
9.5.4
9.6
9.6.1
9.6.2
9.6.2.1
9.6.3
9.6.4
9.7
9.7.1
9.7.2
9.8
9.8.1
9.8.2
9.8.3
9.8.4
9.9
9.9.1
9.9.2
9.9.3
9.9.4
9.9.5
9.9.5.1
9.9.5.2
9.9.5.3
9.9.5.4
9.9.5.5
9.9.5.6
Title
Page
Number
ROM ...................................................................................................................... 10-6
AHB IP Bus Interface (AIPI)..................................................................................... 10-7
PAHBMUX–Primary AHB Mux............................................................................... 10-7
ROMPATCH .............................................................................................................. 10-7
External Boot ......................................................................................................... 10-7
Clock Control Module (CLKCTL) ............................................................................ 10-8
JAM............................................................................................................................ 10-8
Test Wrapper.............................................................................................................. 10-9
ARM9 Platform Hierarchy ............................................................................................ 10-9
JTAG ID Register......................................................................................................... 10-10
System Memory Map................................................................................................... 10-10
ARM9 Platform Memory Map ................................................................................ 10-10
External Peripheral Space........................................................................................ 10-11
External Boot ........................................................................................................... 10-11
Memory Map Considerations .................................................................................. 10-12
Platform Clocking........................................................................................................ 10-12
ARM926EJ-S Clock Considerations ....................................................................... 10-12
ARM926EJ-S JTAG Port Clocking Considerations ................................................ 10-14
JTAG_TCK .......................................................................................................... 10-14
External Alternate Bus Master Interfaces................................................................ 10-14
External Secondary AHB Ports ............................................................................... 10-14
Platform Resets ............................................................................................................ 10-15
HRESET .................................................................................................................. 10-15
POR and JTAG_TRST............................................................................................. 10-15
Power Management ..................................................................................................... 10-16
Register Level Clock Gating.................................................................................... 10-16
Block Level Clock Gating ....................................................................................... 10-16
External Clock Gating ............................................................................................. 10-16
Well Biasing............................................................................................................. 10-17
Platform AHB Interfaces ............................................................................................. 10-18
Definition of AHB-Lite ........................................................................................... 10-18
Alternate Bus Master Ports ...................................................................................... 10-18
Single Master Seamless Connection to ABM Port.................................................. 10-19
Multiple External Masters Connection to ABM Port .............................................. 10-20
Alternate Bus Master Design Considerations.......................................................... 10-20
Edge Based Design .............................................................................................. 10-21
htrans [1:0]........................................................................................................... 10-21
hlock/hmastlock................................................................................................... 10-21
hmaster................................................................................................................. 10-21
hresp0—Bus Error ............................................................................................... 10-22
Unaligned Transfers............................................................................................. 10-22
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Paragraph
Number
9.9.5.7
9.9.5.8
9.9.6
9.9.6.1
9.9.6.2
9.9.7
9.9.7.1
9.9.7.2
9.9.7.3
9.9.7.4
9.9.7.5
9.9.7.6
9.10
9.11
9.12
9.13
9.13.1
9.13.2
9.13.2.1
9.13.3
9.13.4
9.13.5
9.13.6
9.13.7
Title
Page
Number
Alternate Bus Master Throttle Control ................................................................ 10-22
Halt Request (ccm_br) ......................................................................................... 10-22
MAX AHB Slave Ports............................................................................................ 10-23
Slave Port 0—Primary AHB (Internal) ............................................................... 10-23
Secondary AHB Slave Ports 1 and 2 ................................................................... 10-24
Endian Modes .......................................................................................................... 10-25
Affected Modules ................................................................................................ 10-26
Unaffected Modules............................................................................................. 10-26
Un-Aligned Transfers .......................................................................................... 10-26
Endian Mode and Alternate Bus Masters ............................................................ 10-26
Little Endian Operation ....................................................................................... 10-26
Big Endian Operation .......................................................................................... 10-27
Preliminary Size Estimate............................................................................................ 10-28
Power Consumption..................................................................................................... 10-29
ARM9 Platform I/O Signal List................................................................................... 10-30
Electrical Specifications............................................................................................... 10-38
Conditions................................................................................................................ 10-39
Well Bias Mode ....................................................................................................... 10-39
Functional Operation in Well Bias Mode ............................................................ 10-39
clk and jtag_tck Relationship................................................................................... 10-39
Clocks and Reset Timing ......................................................................................... 10-39
Alternate Bus Master (ABM) Interface Timing....................................................... 10-40
Secondary AHB Timing .......................................................................................... 10-42
RAM and ROM Interface Timing............................................................................ 10-44
Chapter 10
ARM926EJ-S Interrupt Controller (AITC)
10.1
10.1.1
10.1.2
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.7
10.2.8
10.2.9
Overview........................................................................................................................ 11-1
Features...................................................................................................................... 11-2
Modes of Operation ................................................................................................... 11-2
Memory Map and Register Definition ........................................................................... 11-3
Memory Map ............................................................................................................. 11-3
Register Summary...................................................................................................... 11-4
Interrupt Control Register (INTCNTL) ..................................................................... 11-8
Normal Interrupt Mask Register (NIMASK)........................................................... 11-10
Interrupt Enable Number Register (INTENNUM) .................................................. 11-11
Interrupt Disable Number Register (INTDISNUM)................................................ 11-12
Interrupt Enable Register High (INTENABLEH) and Low (INTENABLEL)........ 11-13
Interrupt Type Register High (INTTYPEH) and Low (INTTYPEL) ...................... 11-14
Normal Interrupt Priority Level Registers (NIPRIORITYn)................................... 11-15
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
10.2.10
10.2.11
10.2.12
10.2.12.1
10.2.12.2
10.2.13
10.2.14
10.2.15
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.3.7
Title
Page
Number
Normal Interrupt Vector and Status Register (NIVECSR) ...................................... 11-23
Fast Interrupt Vector and Status Register (FIVECSR) ............................................ 11-24
Interrupt Source Register High (INTSRCH) and Low (INTSRCL) ........................ 11-25
Interrupt Assignments High................................................................................. 11-26
Interrupt Assignments Low ................................................................................. 11-27
Interrupt Force Register High (INTFRCH) and Low (INTFRCL) .......................... 11-28
Normal Interrupt Pending Register High (NIPNDH) and Low (NIPNDL)............. 11-29
Fast Interrupt Pending Register High (FIPNDH) and Low (FIPNDL).................... 11-30
ARM926EJ-S Interrupt Controller Operation ............................................................. 11-31
ARM926EJ-S Prioritization of Exception Sources ................................................. 11-31
AITC Prioritization of Interrupt Sources ................................................................. 11-31
Assigning and Enabling Interrupt Sources .............................................................. 11-32
Enabling Interrupt Sources ...................................................................................... 11-32
Typical Interrupt Entry Sequences........................................................................... 11-32
Writing Reentrant Normal Interrupt Routines ......................................................... 11-33
AHB Interface of AITC ........................................................................................... 11-34
Chapter 11
Security Controller (SCC)
11.1
11.2
Overview........................................................................................................................ 12-2
External Signal Description ........................................................................................... 12-2
Chapter 12
Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2)
12.1
Features .......................................................................................................................... 13-1
Chapter 13
Run-Time Integrity Checker (RTIC)
13.1
13.1.1
13.2
13.2.1
Features .......................................................................................................................... 14-1
Modes of Operation ................................................................................................... 14-2
Initialization/Application Information ........................................................................... 14-2
System Application.................................................................................................... 14-2
Chapter 14
IC Identification (IIM)
14.1
14.1.1
Overview........................................................................................................................ 15-1
Features...................................................................................................................... 15-1
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Paragraph
Number
Title
Page
Number
Chapter 15
External Memory Interface (EMI)
15.1
15.2
15.3
15.3.1
15.3.2
15.3.3
15.4
15.4.1
15.4.1.1
15.4.1.2
15.5
15.6
15.6.1
15.7
15.7.1
15.7.2
15.8
Overview........................................................................................................................ 16-1
Features .......................................................................................................................... 16-3
PCMCIA Host Adapter.................................................................................................. 16-4
Interrupt Generation................................................................................................... 16-5
Card Extraction.......................................................................................................... 16-5
TrueIDE Support........................................................................................................ 16-5
NAND Flash Controller (NFC)...................................................................................... 16-5
Operation ................................................................................................................... 16-6
Internal and External Communications ................................................................. 16-6
Sharing of I/O Pins ................................................................................................ 16-7
Enhanced SDRAM Controller (ESDRAMC) ................................................................ 16-7
M3IF AHB MUX........................................................................................................... 16-7
Overview of EMI AHB MUX Operation .................................................................. 16-7
M3IF I/O MUX.............................................................................................................. 16-7
Overview of EMI I/O MUX Operation ..................................................................... 16-8
EMI Input/Output Signals........................................................................................ 16-22
Memory Map and Register Definitions ....................................................................... 16-29
Chapter 16
Multi-Master Memory Interface (M3IF)
16.1
16.1.1
16.1.2
16.2
16.2.1
16.3
16.3.1
16.3.2
16.3.3
16.3.3.1
16.3.3.2
16.3.3.3
16.3.3.4
16.3.3.5
16.4
16.4.1
16.4.1.1
Overview........................................................................................................................ 17-1
M3IF Interfaces.......................................................................................................... 17-1
Features...................................................................................................................... 17-3
External Signal Description ........................................................................................... 17-4
Overview.................................................................................................................... 17-4
Memory Map and Register Definition ........................................................................... 17-6
Memory Map ............................................................................................................. 17-6
Register Summary...................................................................................................... 17-7
Register Descriptions ............................................................................................... 17-10
M3IF Control Register (M3IFCTL) .................................................................... 17-10
M3IF Snooping Configuration Register 0 (M3IFSCFG0) .................................. 17-12
M3IF Snooping Configuration Register 1–2 (M3IFSCFG1–2) .......................... 17-13
M3IF Snooping Status Register 0–1 (M3IFSSR0–1) .......................................... 17-15
M3IF Master Lock WEIM CSx Register (M3IFMLWEx) .................................. 17-17
Functional Description................................................................................................. 17-18
Master Port Gasket (MPG) ...................................................................................... 17-18
Overview of MPG Operation............................................................................... 17-18
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
16.4.1.2
16.4.1.3
16.4.1.4
16.4.1.5
16.4.1.6
16.4.1.7
16.4.2
16.4.2.1
16.4.2.2
16.4.2.3
16.4.2.4
16.4.2.5
16.4.2.6
16.4.2.7
16.4.3
16.4.3.1
16.4.3.2
16.4.3.3
16.4.4
16.4.4.1
16.4.4.2
16.4.4.3
16.4.5
16.5
16.5.1
Title
Page
Number
MPG Basic Transfer ............................................................................................ 17-23
MPG Transfer Type ............................................................................................. 17-24
MPG Transfer Response...................................................................................... 17-25
MPG Burst Operation .......................................................................................... 17-26
MPG Early Burst Termination............................................................................. 17-27
Multi-Endianness................................................................................................. 17-28
Master Port Gasket 64 (MPG64) ............................................................................. 17-29
Overview.............................................................................................................. 17-29
MPG64 Basic Transfer ........................................................................................ 17-31
MPG64 Transfer Type ......................................................................................... 17-31
Mpg64 Transfer Response ................................................................................... 17-32
MPG64 Burst Operation ...................................................................................... 17-32
MPG64 Early Burst Termination......................................................................... 17-32
Multi Endianness ................................................................................................. 17-32
M3IF Arbitration (M3A) ......................................................................................... 17-33
Overview.............................................................................................................. 17-33
M3A–Find First 1 (FF1) Algorithm .................................................................... 17-35
Bus_free Signal Algorithm .................................................................................. 17-37
Master Arbitration and Buffering (MAB)................................................................ 17-37
Overview of MAB Operation .............................................................................. 17-37
M3B–Find First 1 (FF1) Algorithm..................................................................... 17-37
M3IF Operation During HMASTLOCK Accesses ............................................. 17-39
Snooping Logic........................................................................................................ 17-40
Initialization/Application Information ......................................................................... 17-41
M3IF in a System..................................................................................................... 17-41
Chapter 17
Wireless External Interface Module (WEIM)
17.1
17.2
17.3
17.4
17.5
17.5.1
17.5.2
17.5.3
17.5.3.1
17.5.3.2
17.5.3.3
17.5.3.4
Features .......................................................................................................................... 18-1
Overview........................................................................................................................ 18-1
External Signal Description ........................................................................................... 18-3
Detailed Signal Descriptions ......................................................................................... 18-4
Memory Map and Register Definition ........................................................................... 18-7
Memory Map ............................................................................................................. 18-8
Register Summary...................................................................................................... 18-9
Register Descriptions ............................................................................................... 18-10
Chip Select x Upper Control Register (CSCRxU) .............................................. 18-13
Chip Select x Lower Control Register (CSCRxL)............................................... 18-17
Chip Select x Additional Control Register (CSCRxA) ....................................... 18-20
WEIM Configuration Register (WCR)................................................................ 18-23
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
17.6
17.6.1
17.6.2
17.6.3
17.6.4
17.6.5
17.6.6
17.6.7
17.6.8
17.6.9
17.6.10
17.6.11
17.6.12
17.6.13
17.7
17.8
17.8.1
17.8.1.1
17.8.1.2
17.8.2
17.8.2.1
17.8.3
17.8.3.1
17.8.4
17.8.4.1
17.8.4.2
17.8.5
17.8.5.1
17.8.5.2
17.8.6
17.8.6.1
17.8.6.2
Title
Page
Number
Functional Description................................................................................................. 18-24
Configurable Bus Sizing.......................................................................................... 18-24
WEIM Operational Modes....................................................................................... 18-25
Burst Mode Memory Operation............................................................................... 18-25
Burst Clock Divisor ................................................................................................. 18-26
Burst Clock Start...................................................................................................... 18-26
Page Mode Emulation.............................................................................................. 18-26
PSRAM Mode Operation......................................................................................... 18-27
Multiplexed Address/Data mode ............................................................................. 18-27
Mixed AHB/Memory Burst Modes Support ........................................................... 18-27
AHB Bus Cycles Support ........................................................................................ 18-27
DTACK Mode.......................................................................................................... 18-29
Internal Input Data Capture ..................................................................................... 18-29
Error Conditions ...................................................................................................... 18-29
Initialization/Application Information ......................................................................... 18-30
External Bus Timing Diagrams.................................................................................... 18-30
Asynchronous Memory Accesses Timing Diagrams............................................... 18-32
AHB Halfword Access to Halfword Width Memory .......................................... 18-32
AHB Word Access to Halfword Width Memory................................................. 18-39
Page Mode Timing Diagrams .................................................................................. 18-50
AHB Word Accesses to Halfword Width Memory ............................................. 18-50
DTACK Mode Memory Accesses Timing Diagrams .............................................. 18-51
AHB Word Accesses to Word-Width Memory.................................................... 18-51
Burst Memory Accesses Timing Diagrams ............................................................. 18-54
AHB Word Accesses to Halfword Width Memory ............................................. 18-54
AHB Accesses to Word-Width Burst Memory.................................................... 18-57
Synchronous Accesses Timing Diagrams with PSRAM ......................................... 18-65
AHB Sequential Accesses to Halfword Width PSRAM Memory....................... 18-65
AHB Sequential Accesses to Word-Width PSRAM Memory ............................. 18-67
Multiplexed A/D Mode............................................................................................ 18-68
Asynchronous Word Accesses to Word-Width Memory ..................................... 18-68
Synchronous Accesses with Word-Width Memory ............................................. 18-70
Chapter 18
Enhanced SDRAM Controller (ESDRAMC)
18.1
18.1.1
18.1.2
18.1.3
18.1.4
Overview........................................................................................................................ 19-1
SDRAM Command Controller .................................................................................. 19-1
Bank Model................................................................................................................ 19-1
Decoder and Address MUX....................................................................................... 19-1
ESDRAMC Control and Configuration Registers ..................................................... 19-3
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Contents
Paragraph
Number
18.1.5
18.1.6
18.1.7
18.1.8
18.1.8.1
18.1.9
18.1.10
18.2
18.2.1
18.3
18.3.1
18.3.2
18.3.3
18.3.3.1
18.3.3.2
18.3.3.3
18.3.3.4
18.3.3.5
18.4
18.4.1
18.4.1.1
18.4.1.2
18.4.1.3
18.4.2
18.4.2.1
18.4.2.2
18.4.3
18.4.4
18.4.5
18.4.5.1
18.4.5.2
18.4.5.3
18.4.5.3.1
18.4.5.4
18.4.5.4.1
18.4.5.5
18.4.5.6
18.4.6
18.4.6.1
18.4.7
18.4.7.1
Title
Page
Number
Refresh Sequencer ..................................................................................................... 19-3
Command Sequencer ................................................................................................. 19-3
Size Logic .................................................................................................................. 19-3
Mobile/Low Power DDR (LPDDR) Interface ........................................................... 19-3
Power Down Timer................................................................................................ 19-4
Features...................................................................................................................... 19-4
Modes of Operation ................................................................................................... 19-5
External Signal Description ........................................................................................... 19-6
Detailed Signal Descriptions ..................................................................................... 19-7
Memory Map and Register Definition ........................................................................... 19-9
Memory Map ............................................................................................................. 19-9
Register Summary.................................................................................................... 19-10
Register Descriptions ............................................................................................... 19-13
ESDCTL0 and ESDCTL1 Control Registers ...................................................... 19-14
ESDRAMC Configuration Registers (ESDCFG0 /ESDCFG1) .......................... 19-18
ESDMISC Miscellaneous Register (ESDMISC)................................................. 19-31
MDDR Delay Line 1–5 Configuration Debug Register ...................................... 19-33
MDDR Delay Line Cycle Length Debug Register .............................................. 19-35
Functional Description................................................................................................. 19-36
Enhanced SDRAM Controller Optimization Strategy............................................. 19-37
MIF1—No optimization/Sequential Accesses .................................................... 19-41
MIF2—Medium Level Optimization/Command Anticipation............................ 19-42
Latency Hiding .................................................................................................... 19-42
Address Multiplexing .............................................................................................. 19-44
Multiplexed Address Bus..................................................................................... 19-44
Bank Addresses ................................................................................................... 19-47
Multiplexed Address Bus—During “Special” Mode (SMODE 1 or 3)................... 19-47
Refresh ..................................................................................................................... 19-47
Low Power Operating Modes .................................................................................. 19-49
Self Refresh Mode for SDRAM/LPDDR Devices .............................................. 19-49
Manual Self Refresh Mode for SDRAM/LPDDR Devices ................................. 19-51
Precharge Power Down Mode ............................................................................. 19-53
SDRAM Precharge Power Down Mode .......................................................... 19-53
Active Power Down Mode................................................................................... 19-57
SDRAM/LPDDR Active Power Down Mode ................................................. 19-57
Precharge Bank(s)—Low Power Mode ............................................................... 19-60
LPDDR Frequency Change ................................................................................. 19-60
SDRAM (SDR and LPDDR) Command Encoding................................................. 19-60
Reset .................................................................................................................... 19-61
Normal READ/WRITE Mode ................................................................................. 19-61
SDR Cycle Accurate Enhanced SDRAM Controller Accesses........................... 19-84
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Paragraph
Number
18.4.7.1.1
18.4.7.1.2
18.4.7.1.3
18.4.7.2
18.4.7.2.1
18.4.7.3
18.4.8
18.4.9
18.4.10
18.4.11
18.5
18.5.1
18.5.2
18.5.3
18.5.4
18.5.4.1
18.5.4.1.1
18.5.4.1.2
18.5.4.2
18.5.4.3
18.5.4.3.1
18.5.4.3.2
18.5.4.3.3
18.5.4.3.4
18.5.4.3.5
18.5.4.3.6
18.5.4.3.7
18.5.4.3.8
18.5.4.3.9
18.5.4.3.10
18.5.4.3.11
18.5.4.3.12
18.5.4.3.13
18.5.4.3.14
18.5.4.3.15
18.5.4.3.16
Title
Page
Number
Single Read Word Access to 16-Bit Memory.................................................. 19-84
Misaligned INCR4 Burst Read Access to 16-Bit Memory ............................. 19-85
Misaligned WRAP8 Burst Read Access to 32-Bit Memory ........................... 19-87
Single Write Word Access to 32-Bit Memory..................................................... 19-89
INCR4 Burst Write Word Access to 32-Bit Memory...................................... 19-90
SDRAM Command Sequence for Burst Accesses .............................................. 19-91
Precharge Command Mode ..................................................................................... 19-92
Auto-Refresh Mode ................................................................................................. 19-93
Manual Self Refresh Mode ...................................................................................... 19-94
Set Mode Register Mode ......................................................................................... 19-94
Initialization/Application Information ......................................................................... 19-96
Memory Device Selection........................................................................................ 19-96
Configuring Controller for SDRAM Memory Array .............................................. 19-96
CAS Latency............................................................................................................ 19-96
SDRAM/LPDDR Initialization Sequence ............................................................... 19-97
SDRAM Initialization.......................................................................................... 19-97
SDR SDRAM Initialization............................................................................. 19-97
LPDDR SDRAM Initialization ....................................................................... 19-98
SDR SDRAM Load Mode Register .................................................................. 19-100
SDRAM Memory Configuration Examples ...................................................... 19-101
Single 64Mb (4Mx16) SDRAM Configuration............................................. 19-102
Single 128 Mb (8MBx16) SDRAM Configuration ....................................... 19-103
Single 256 Mb (16MBx16) SDRAM Configuration ..................................... 19-104
Single 512 Mb (32MBx16) SDRAM Configuration ..................................... 19-105
Single 1-Gb (64MBx16) SDRAM Configuration ......................................... 19-106
Dual 64 Mb (4MBx16) SDRAM Configuration ........................................... 19-107
Dual 128 Mb (8MBx16) SDRAM Configuration ......................................... 19-108
Dual 256 Mb (16MBx16) SDRAM Configuration ....................................... 19-109
Single 64-Mbyte (2MBx32) SDRAM Configuration.................................... 19-110
Single 128-Mbyte (4MBx32) SDRAM Configuration.................................. 19-111
Single 256-Mb (8MBx32) SDRAM Configuration....................................... 19-112
Single 512-Mb (16MBx32) SDRAM Configuration..................................... 19-113
Single 1-Gb (32Mx32) SDRAM Configuration ............................................ 19-114
Single 2-Gb (64MBx32) SDRAM Configuration ......................................... 19-115
Single 512-Mb (16MBx32) Mobile DDR SDRAM Configuration............... 19-116
Single 512-Mb (32MBx16) Mobile DDR SDRAM Configuration............... 19-117
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Paragraph
Number
Title
Page
Number
Chapter 19
NAND Flash Controller (NFC)
19.1
19.2
19.3
19.4
19.4.1
19.4.2
19.5
19.5.1
19.6
19.6.1
19.6.2
19.7
19.7.1
19.7.2
19.7.3
19.7.4
19.7.5
19.7.6
19.7.7
19.7.8
19.7.9
19.7.10
19.7.11
19.7.12
19.7.13
19.7.14
19.7.15
19.7.16
19.8
19.8.1
19.8.2
19.8.3
Overview........................................................................................................................ 20-1
Operation ....................................................................................................................... 20-2
Features .......................................................................................................................... 20-2
External Signal Description ........................................................................................... 20-3
Overview.................................................................................................................... 20-3
Detailed Signal Descriptions ..................................................................................... 20-3
NFC Buffer Memory Space ........................................................................................... 20-5
Main and Spare Area Buffers .................................................................................... 20-5
Memory Map and Register Definition ........................................................................... 20-7
Memory Map ............................................................................................................. 20-7
Register Summary...................................................................................................... 20-8
Register Descriptions ..................................................................................................... 20-9
Internal SRAM SIZE (NFC_BUFSIZE).................................................................... 20-9
Buffer Number for Page Data Transfer (RAM_BUFFER_ADDRESS).................. 20-10
NAND Flash Address (NAND_FLASH_ADD)...................................................... 20-10
NAND Flash Command (NAND_FLASH_CMD).................................................. 20-11
NFC Internal Buffer Lock Control (NFC_CONFIGURATION)............................. 20-11
Controller Status and Result of Flash Operation (ECC_STATUS_RESULT)......... 20-12
ECC Error Position of Main Area Data Error x8
(ECC_RSLT_MAIN_AREA) .............................................................................. 20-12
ECC Error Position of Main Area Data Error x16
(ECC_RSLT_MAIN_AREA) .............................................................................. 20-13
ECC Error Position of Spare Area Data Error x8
(ECC_RSLT_SPARE_AREA) ............................................................................ 20-14
ECC Error Position of Spare Area Data Error x16
(ECC_RSLT_SPARE_AREA) ............................................................................ 20-14
NAND Flash Write Protection (NF_WR_PROT).................................................... 20-15
Address to Unlock in Write Protection Mode—Start
(UNLOCK_START_BLK_ADD) ....................................................................... 20-15
Address to Unlock in Write Protection Mode—End
(UNLOCK_END_BLK_ADD) ........................................................................... 20-16
NAND Flash Write Protection Status (NAND_FLASH_WR_PR_ST) .................. 20-16
NAND Flash Operation Configuration (NAND_FLASH_CONFIG1) ................... 20-17
NAND Flash Operation Configuration 2 (NAND_FLASH_CONFIG2) ................ 20-18
Functional Description................................................................................................. 20-19
Modes of Operation ................................................................................................. 20-19
Booting From a NAND Flash Device...................................................................... 20-20
NAND Flash Control ............................................................................................... 20-22
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
19.8.4
19.8.5
19.8.6
19.8.7
19.8.8
19.8.9
19.8.10
19.8.11
19.8.11.1
19.8.11.2
19.8.12
19.9
19.9.1
19.9.1.1
19.9.1.1.1
19.9.1.1.2
19.9.1.1.3
19.9.1.1.4
19.9.1.1.5
19.9.1.2
19.9.1.2.1
19.9.1.3
19.9.1.3.1
19.9.1.4
19.9.1.5
19.9.1.6
19.9.1.7
19.9.2
19.9.2.1
19.9.2.2
19.9.2.3
19.9.3
19.9.3.1
19.9.3.2
19.9.3.3
19.9.3.4
19.9.3.4.1
19.9.3.4.2
19.9.3.4.3
19.9.4
Title
Page
Number
Error Code Correction (ECC) Control..................................................................... 20-23
Address Control ....................................................................................................... 20-23
RAM Buffer (SRAM) .............................................................................................. 20-24
Registers (Command, Address, Status, and Others.) ............................................... 20-24
Read and Write Control ........................................................................................... 20-24
Data Output Control................................................................................................. 20-24
Host Control............................................................................................................. 20-24
AHB BUS INTERFACE.......................................................................................... 20-24
Big/Little Endian ................................................................................................. 20-24
Burst Access Support........................................................................................... 20-25
I/O Pins Sharing....................................................................................................... 20-25
Initialization/Application Information ......................................................................... 20-25
Normal Operation .................................................................................................... 20-26
Fundamental Building Block Operations ............................................................ 20-26
Preset Operation .............................................................................................. 20-26
NAND Flash Command Input Operation ........................................................ 20-27
NAND Flash Address Input Operation............................................................ 20-28
NAND Flash Data Input Operation ................................................................. 20-29
NAND Flash Data Output Operation .............................................................. 20-30
NAND Flash ID Read Operation......................................................................... 20-31
NAND Flash ID Data Formats ........................................................................ 20-31
NAND Flash Status Read Operation ................................................................... 20-32
NAND Flash Status Data Format .................................................................... 20-32
Read NAND Flash Data Operation ..................................................................... 20-33
Program NAND Flash Data Operation................................................................ 20-34
Erase NAND Flash Data Operation..................................................................... 20-35
Hot Reset (Controller and NAND Flash Reset)................................................... 20-35
ECC Operation......................................................................................................... 20-36
ECC Normal Operation ....................................................................................... 20-36
ECC Bypass Operation ........................................................................................ 20-36
How to Operate ECC ........................................................................................... 20-36
Write Protection Operation...................................................................................... 20-37
Write Protection for RAM Buffer (LSB 1 Kbyte) ............................................... 20-37
Write Protection Modes....................................................................................... 20-38
Write Protection Commands................................................................................ 20-38
Write Protection Status ........................................................................................ 20-39
Lock Sequence................................................................................................. 20-39
Unlock Sequence ............................................................................................. 20-40
Lock-tight Sequence ........................................................................................ 20-40
Memory Configuration Examples ........................................................................... 20-40
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
Title
Page
Number
Chapter 20
Personal Computer Memory Card International Association (PCMCIA) Controller
20.1
20.2
20.3
20.3.1
20.4
20.4.1
20.4.1.1
20.4.1.2
20.4.1.3
20.4.1.4
20.4.1.5
20.4.1.6
20.4.1.7
20.4.1.8
20.5
20.5.1
20.5.2
20.5.2.1
20.5.3
20.5.4
20.5.4.1
20.5.5
20.5.6
20.5.7
20.5.8
20.5.9
20.5.10
20.5.11
20.5.12
20.5.13
20.6
Overview........................................................................................................................ 21-1
Features .......................................................................................................................... 21-3
External Signal Description ........................................................................................... 21-3
Detailed Signal Descriptions ..................................................................................... 21-3
Memory Map and Register Definition ........................................................................... 21-6
Register Summary...................................................................................................... 21-7
PCMCIA Input Pins Register (PIPR) .................................................................... 21-9
PCMCIA Status Change Register (PSCR) .......................................................... 21-10
PCMCIA Enable Register (PER)......................................................................... 21-12
PCMCIA Base Registers 0–4 (PBR0–PBR4)...................................................... 21-14
PCMCIA Option Registers 0–4 (POR0–POR4).................................................. 21-15
PCMCIA Offset Registers 0–4 (POFR0–POFR4)............................................... 21-18
PCMCIA General Control Register (PGCR)....................................................... 21-19
PCMCIA General Status Register (PGSR).......................................................... 21-20
Functional Description................................................................................................. 21-21
Modes of Operation ................................................................................................. 21-21
Windowing Capabilities........................................................................................... 21-21
Window Overlapping........................................................................................... 21-21
WAIT Signal ............................................................................................................ 21-21
Interrupts.................................................................................................................. 21-22
Error Interrupt Conditions ................................................................................... 21-22
Power Control .......................................................................................................... 21-23
Reset and Three-Score Control................................................................................ 21-23
Write Protect ............................................................................................................ 21-23
16-Bit/8-Bit Support ................................................................................................ 21-24
Data and Control Signals Relations ......................................................................... 21-24
True IDE Mode Access............................................................................................ 21-25
Card Extraction ........................................................................................................ 21-26
TrueIDE Support...................................................................................................... 21-26
Endianness Support.................................................................................................. 21-27
Timing Diagrams ......................................................................................................... 21-28
Chapter 21
1-Wire Interface (1-Wire)
21.1
21.2
21.3
Overview........................................................................................................................ 22-1
Port Definitions .............................................................................................................. 22-2
Pin Configuration........................................................................................................... 22-2
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Paragraph
Number
21.4
21.5
21.5.1
21.5.2
21.5.3
21.5.4
21.5.5
21.6
21.6.1
21.6.1.1
21.6.2
21.6.3
Title
Page
Number
Clock Enable and AIPI Configuration........................................................................... 22-3
Functional Description................................................................................................... 22-3
Low-Power Modes..................................................................................................... 22-3
Reset Sequence with Reset Pulse Presence Pulse...................................................... 22-3
Write 0 ....................................................................................................................... 22-4
Write 1 and Read Data............................................................................................... 22-4
Program Pulse ............................................................................................................ 22-5
Memory Map and Register Definition ........................................................................... 22-5
Register Summary...................................................................................................... 22-5
Control Register (CONTROL) .............................................................................. 22-7
Time Divider Register (TIME_DIVIDER)................................................................ 22-9
Reset Register .......................................................................................................... 22-11
Chapter 22
Advanced Technology Attachment (ATA)
22.1
22.2
22.3
22.4
22.4.1
22.5
22.5.1
22.5.1.1
22.5.1.2
22.5.1.3
22.5.1.4
22.5.1.5
22.5.1.6
22.5.1.7
22.5.1.8
22.5.1.9
22.6
22.6.1
22.6.2
22.6.3
22.6.3.1
22.6.3.1.1
22.6.3.1.2
22.6.3.1.3
Overview........................................................................................................................ 23-1
Features .......................................................................................................................... 23-2
Operation ....................................................................................................................... 23-3
PIO Mode....................................................................................................................... 23-3
DMA Mode (Multi-Word DMA and Ultra DMA) .................................................... 23-3
External Signal Description ........................................................................................... 23-4
Detailed Signal Descriptions ..................................................................................... 23-5
ipp_do_ata_reset_b (out) ....................................................................................... 23-5
ipp_do_ata_dior (out) ............................................................................................ 23-5
ipp_do_ata_diow (out)........................................................................................... 23-5
ipp_do_ata_cs0, ipp_do_ata_cs1, ipp_do_ata_da2, ipp_do_ata_da1,
ipp_do_ata_da0 (out) ......................................................................................... 23-5
ipp_ind_ata_dmarq (in) ......................................................................................... 23-5
ipp_do_ata_dmack (out) ........................................................................................ 23-5
ipp_ind_ata_intrq (in) ............................................................................................ 23-5
ipp_ind_ata_iordy (in) ........................................................................................... 23-5
ipp_do_ata_data[15:0] (out) .................................................................................. 23-6
Memory Map and Register Definition ........................................................................... 23-6
Memory Map ............................................................................................................. 23-6
Register Summary...................................................................................................... 23-7
Register Descriptions ............................................................................................... 23-10
Timing Registers.................................................................................................. 23-10
TIME_CONFIG0............................................................................................. 23-11
TIME_CONFIG1............................................................................................. 23-12
TIME_CONFIG2............................................................................................. 23-13
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
22.6.3.1.4
22.6.3.1.5
22.6.3.1.6
22.6.3.2
22.6.3.2.1
22.6.3.2.2
22.6.3.3
22.6.3.4
22.6.3.5
22.6.3.6
22.6.3.7
22.7
22.8
22.8.1
22.8.2
22.8.3
22.8.4
Title
Page
Number
TIME_CONFIG3............................................................................................. 23-14
TIME_CONFIG4............................................................................................. 23-15
TIME_CONFIG5............................................................................................. 23-16
FIFO Data Registers ............................................................................................ 23-16
FIFO_DATA_32 Register in 32-bit Mode ....................................................... 23-17
FIFO_DATA_16 Register ................................................................................ 23-17
FIFO_FILL Register ............................................................................................ 23-18
ATA_CONTROL Register ................................................................................... 23-19
INT_PENDING, INT_ENABLE, INT_CLEAR Registers ................................. 23-20
FIFO Alarm Register ........................................................................................... 23-23
Drive Registers Mapped to Host Module ............................................................ 23-23
Functional Description................................................................................................. 23-24
Initialization/Application Information ......................................................................... 23-25
Resetting ATA Bus................................................................................................... 23-25
Access to ATA Bus in PIO Mode ............................................................................ 23-25
Using DMA Mode to Receive Data from ATA bus ................................................. 23-25
Using DMA Mode to Transmit Data to ATA bus .................................................... 23-26
Chapter 23
Configurable Serial Peripheral Interface (CSPI)
23.1
23.1.1
23.2
23.2.1
23.2.2
23.2.2.1
23.2.2.2
23.2.2.3
23.2.2.4
23.2.2.5
23.2.3
23.2.4
23.2.5
23.3
23.3.1
23.4
23.4.1
23.4.2
23.4.3
23.4.3.1
Features .......................................................................................................................... 24-1
External Signals Description ..................................................................................... 24-2
Operation ....................................................................................................................... 24-2
Phase and Polarity Configurations............................................................................. 24-3
Master Mode .............................................................................................................. 24-3
Master Mode with SPI_RDY................................................................................. 24-4
Master Mode with Wait States............................................................................... 24-5
Master Mode with Continuation............................................................................ 24-6
Master Mode with SSCTL Control........................................................................ 24-6
Master Mode with various configurations of WAIT, BURST and SSCTL ........... 24-7
Slave Mode ................................................................................................................ 24-7
Interrupt Control ........................................................................................................ 24-8
DMA Control............................................................................................................. 24-9
Initialization/Application Information ......................................................................... 24-10
Software Restrictions............................................................................................... 24-11
Memory Map and Register Definition ......................................................................... 24-11
Memory Map ........................................................................................................... 24-12
Register Summary.................................................................................................... 24-12
Register Descriptions ............................................................................................... 24-15
Receive Data Register (RXDATA) ...................................................................... 24-15
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Paragraph
Number
23.4.3.2
23.4.3.3
23.4.3.4
23.4.3.5
23.4.3.6
23.4.3.7
23.4.3.8
Title
Page
Number
Transmit Data Register (TXDATA) ..................................................................... 24-16
Control Register (CONREG)............................................................................... 24-17
Interrupt Control and Status Register (INTREG) ................................................ 24-20
Test Control Register (TESTREG) ...................................................................... 24-23
Sample Period Control Register (PERIODREG) ................................................ 24-24
DMA Control Register (DMAREG) ................................................................... 24-25
Soft Reset Register .............................................................................................. 24-27
Chapter 24
Inter-Integrated Circuit (I2C)
24.1
24.1.1
24.2
24.2.1
24.3
24.3.1
24.3.2
24.3.3
24.3.3.1
24.3.3.2
24.3.3.3
24.3.3.4
24.3.3.5
24.4
24.4.1
24.4.2
24.4.2.1
24.4.2.2
24.4.2.3
24.4.2.4
24.4.2.5
24.4.3
24.4.4
24.4.5
24.4.6
24.4.7
24.4.8
24.5
24.5.1
24.5.2
Overview........................................................................................................................ 25-2
Features...................................................................................................................... 25-2
External Signal Description ........................................................................................... 25-3
Detailed External Signal Descriptions....................................................................... 25-3
Memory Map and Register Definition ........................................................................... 25-4
I2C Memory Map....................................................................................................... 25-4
Register Summary...................................................................................................... 25-4
Register Descriptions ................................................................................................. 25-6
I2C Address Register (IADR)................................................................................ 25-6
I2C Frequency Register (IFDR)............................................................................. 25-6
I2C Control Register (I2CR).................................................................................. 25-8
I2C Status Register (I2SR)..................................................................................... 25-9
I2C Data Register (I2DR) .................................................................................... 25-10
Functional Description................................................................................................. 25-11
I2C System Configuration........................................................................................ 25-11
I2C Protocol ............................................................................................................. 25-11
START Signal ...................................................................................................... 25-12
Slave Address Transmission ................................................................................ 25-12
Data Transfer ....................................................................................................... 25-12
STOP Signal ........................................................................................................ 25-13
Repeat Start.......................................................................................................... 25-13
Arbitration Procedure .............................................................................................. 25-13
Clock Synchronization............................................................................................. 25-13
Handshaking ............................................................................................................ 25-14
Clock Stretching ...................................................................................................... 25-14
IP Bus Accesses ....................................................................................................... 25-14
Generation of Transfer Error on IP Bus................................................................... 25-14
Initialization/Application Information ......................................................................... 25-14
Initialization Sequence............................................................................................. 25-14
Generation of START .............................................................................................. 25-15
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Contents
Paragraph
Number
24.5.3
24.5.4
24.5.5
24.5.6
24.5.7
24.5.8
Title
Page
Number
Post-Transfer Software Response ............................................................................ 25-15
Generation of STOP................................................................................................. 25-15
Generation of Repeated START .............................................................................. 25-16
Slave Mode .............................................................................................................. 25-16
Arbitration Lost........................................................................................................ 25-16
Timing Section......................................................................................................... 25-18
Chapter 25
Keypad Port (KPP)
25.1
25.1.1
25.1.2
25.2
25.2.1
25.2.1.1
25.2.1.2
25.3
25.3.1
25.3.2
25.3.3
25.3.3.1
25.3.3.2
25.3.3.3
25.3.3.4
25.4
25.4.1
25.4.2
25.4.3
25.4.4
25.4.5
25.4.6
25.4.6.1
25.4.7
25.5
25.5.1
25.5.2
25.5.3
Overview........................................................................................................................ 26-1
Features...................................................................................................................... 26-2
Modes of Operation ................................................................................................... 26-2
External Signal Description ........................................................................................... 26-2
Overview.................................................................................................................... 26-2
Input Pins ............................................................................................................... 26-2
Output Pins ............................................................................................................ 26-2
Memory Map and Register Definition ........................................................................... 26-3
KPP Memory Map ..................................................................................................... 26-3
Register Summary...................................................................................................... 26-3
Register Descriptions ................................................................................................. 26-5
Keypad Control Register (KPCR) ......................................................................... 26-5
Keypad Status Register (KPSR) ............................................................................ 26-6
Keypad Data Direction Register (KDDR) ............................................................. 26-7
Keypad Data Register (KPDR).............................................................................. 26-8
Functional Description................................................................................................... 26-9
Keypad Matrix Construction...................................................................................... 26-9
Keypad Port Configuration ........................................................................................ 26-9
Keypad Matrix Scanning ........................................................................................... 26-9
Keypad Standby ...................................................................................................... 26-10
Glitch Suppression on Keypad Inputs...................................................................... 26-10
Multiple Key Closures ............................................................................................. 26-11
Ghost Key Problem and Correction..................................................................... 26-13
3-Point Contact Keys Support ................................................................................. 26-14
Initialization/Application Information ......................................................................... 26-15
Typical Keypad Configuration and Scanning Sequence.......................................... 26-15
Key Press Interrupt Scanning Sequence .................................................................. 26-15
Additional Comments .............................................................................................. 26-16
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
Title
Page
Number
Chapter 26
Memory Stick Host Controller (MSHC)
26.1
26.1.1
26.1.2
26.2
26.2.1
26.2.1.1
26.3
26.3.1
26.3.1.1
26.3.1.2
26.3.1.2.1
26.3.1.2.2
26.3.1.2.3
26.4
26.4.1
26.4.2
26.4.2.1
26.4.2.2
26.4.2.2.1
26.4.2.3
26.4.2.4
26.4.2.5
Overview........................................................................................................................ 27-2
Features...................................................................................................................... 27-2
Modes of Operation ................................................................................................... 27-2
External Signal Description ........................................................................................... 27-3
Overview.................................................................................................................... 27-3
Memory Stick Interface ......................................................................................... 27-3
Memory Map and Register Definition ........................................................................... 27-3
Register Descriptions ................................................................................................. 27-4
SMSC Registers..................................................................................................... 27-4
Gasket Register ...................................................................................................... 27-5
Gasket Timeout Register ................................................................................... 27-5
Gasket Interrupt Status/Clear Register .............................................................. 27-5
Gasket Interrupt Enable Register....................................................................... 27-6
Functional Description................................................................................................... 27-7
Sony Memory Stick Controller (SMSC) ................................................................... 27-7
MSHC Gasket ............................................................................................................ 27-7
Resetting and Clocking.......................................................................................... 27-7
Memory Stick Interface ......................................................................................... 27-9
Back-to-Back Transfer..................................................................................... 27-10
Transfer Error ...................................................................................................... 27-11
Transfer Wait Condition ...................................................................................... 27-12
Gasket Interrupt ................................................................................................... 27-12
Chapter 27
Secured Digital Host Controller (SDHC)
27.1
27.1.1
27.2
27.3
27.3.1
27.3.2
27.3.3
27.3.3.1
27.3.3.2
27.3.3.3
27.3.3.4
27.3.3.5
Overview........................................................................................................................ 28-2
Features...................................................................................................................... 28-2
External Signal Description ........................................................................................... 28-3
Memory Map and Register Definition ........................................................................... 28-3
Memory Map ............................................................................................................. 28-3
Register Summary...................................................................................................... 28-4
Register Descriptions ................................................................................................. 28-8
SDHC Clock Control Register (STR_STP_CLK)................................................. 28-8
SDHC Status Register (STATUS).......................................................................... 28-9
SDHC Clock Rate Register (CLK_RATE).......................................................... 28-14
SDHC Command and Data Control Register (CMD_DAT_CONT)................... 28-16
SDHC Response Time Out Register (RES_TO) ................................................. 28-17
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Contents
Paragraph
Number
27.3.3.6
27.3.3.7
27.3.3.8
27.3.3.9
27.3.3.10
27.3.3.11
27.3.3.12
27.3.3.13
27.3.3.14
27.4
27.4.1
27.4.1.1
27.4.1.2
27.4.1.3
27.4.1.4
27.4.1.5
27.4.2
27.4.2.1
27.4.3
27.4.4
27.4.4.1
27.4.4.2
27.4.4.3
27.4.5
27.4.6
27.4.6.1
27.4.6.2
27.4.7
27.4.8
27.4.9
27.5
27.5.1
27.5.2
27.5.2.1
27.5.2.2
27.5.2.3
27.5.2.4
27.5.3
27.5.3.1
27.5.3.1.1
27.5.3.1.2
Title
Page
Number
SDHC Read Time Out Register (READ_TO) ..................................................... 28-19
SDHC Block Length Register (BLK_LEN) ........................................................ 28-20
SDHC Number of Blocks Register (NOB).......................................................... 28-21
SDHC Revision Number Register (REV_NO).................................................... 28-23
SDHC Interrupt Control Register (INT_CNTR) ................................................. 28-24
SDHC Command Number Register (CMD)........................................................ 28-28
SDHC CMD Argument Register (ARG) ............................................................. 28-29
SDHC Response FIFO Access Register (RES_FIFO) ........................................ 28-30
SDHC Data Buffer Access Register (BUFFER_ACCESS) ................................ 28-31
Functional Description................................................................................................. 28-32
Data Buffers ............................................................................................................. 28-32
Data Buffer Access .............................................................................................. 28-32
Write Operation Sequence................................................................................... 28-33
Read Operation Sequence.................................................................................... 28-33
Data Buffer Size................................................................................................... 28-34
Dividing Large Data Transfer .............................................................................. 28-34
DMA Interface......................................................................................................... 28-36
DMA Request ...................................................................................................... 28-36
Memory Controller .................................................................................................. 28-37
SDIO Card Interrupt ................................................................................................ 28-37
Interrupts in 1-Bit Mode ...................................................................................... 28-37
Interrupt in 4-Bit Mode........................................................................................ 28-37
Card Interrupt Handling....................................................................................... 28-38
Card Insertion and Removal Detection.................................................................... 28-39
Power Management and Wake-Up Events............................................................... 28-40
Dynamic Voltage/Frequency Scaling (DVFS) Operation.................................... 28-41
Setting Wake-Up Events ...................................................................................... 28-41
Command/Data Interpreter ...................................................................................... 28-41
System Clock Controller.......................................................................................... 28-43
DAT/CMD Transceiver ............................................................................................ 28-44
Initialization/Application of SDHC ............................................................................. 28-44
Command Submit—Response Receive Basic Operation ........................................ 28-45
Card Identification Mode......................................................................................... 28-46
Card Detect .......................................................................................................... 28-47
Reset .................................................................................................................... 28-47
Voltage Validation................................................................................................ 28-48
Card Registry ....................................................................................................... 28-49
Card Access ............................................................................................................. 28-51
Block Access—Block Write and Block Read ..................................................... 28-51
Block Write...................................................................................................... 28-51
Block Read ...................................................................................................... 28-52
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Paragraph
Number
27.6
Page
Number
Title
Commands for MMC/SD/SDIO .................................................................................. 28-54
Chapter 28
Universal Asynchronous Receiver/Transmitters (UART)
28.1
28.1.1
28.1.2
28.2
28.2.1
28.3
28.3.1
28.3.2
28.3.3
28.3.4
28.3.4.1
28.3.4.2
28.3.4.3
28.3.4.4
28.3.4.5
28.3.4.6
28.3.4.7
28.3.4.8
28.3.4.9
28.3.4.10
28.3.4.11
28.3.4.12
28.3.4.13
28.3.4.14
28.3.4.15
28.3.4.16
28.4
28.4.1
28.4.2
28.4.2.1
28.4.2.2
28.4.3
28.4.3.1
28.4.3.2
28.4.3.3
28.4.3.4
Overview........................................................................................................................ 29-1
Features...................................................................................................................... 29-2
Modes of Operation ................................................................................................... 29-2
External Signal Description ........................................................................................... 29-3
Overview.................................................................................................................... 29-3
Memory Map and Register Definition ........................................................................... 29-3
Memory Map and Register Summary........................................................................ 29-3
Memory Map ............................................................................................................. 29-4
Register Summary...................................................................................................... 29-5
Register Descriptions ................................................................................................. 29-8
UART Receiver Register (URXD)......................................................................... 29-8
UART Transmitter Register (UTXD) .................................................................... 29-9
UART Control Register 1 (UCR1) ...................................................................... 29-10
UART Control Register 2 (UCR2) ...................................................................... 29-12
UART Control Register 3 (UCR3) ...................................................................... 29-14
UART Control Register 4 (UCR4) ...................................................................... 29-16
UART FIFO Control Register Summary (UFCR) ............................................... 29-18
UART Status Register 1 Summary (USR1)......................................................... 29-19
UART Status Register 2 (USR2) ......................................................................... 29-21
UART Escape Character Register Summary (UESC) ......................................... 29-23
UART Escape Timer Register Summary (UTIM) ............................................... 29-23
UART BRM Incremental Register (UBIR) ......................................................... 29-24
UART BRM Modulator Register Summary (UBMR)......................................... 29-24
UART Baud Rate Count Register Summary (UBRC) ......................................... 29-25
UART One Millisecond Register (ONEMS) ....................................................... 29-26
UART Test Register (UTS).................................................................................. 29-26
Functional Description................................................................................................. 29-28
Interrupts and DMA Requests ................................................................................. 29-28
Clocking Considerations.......................................................................................... 29-28
Minimum and Maximum Clock Frequencies...................................................... 29-28
Clocking in Low-Power Modes ........................................................................... 29-31
General UART Definitions ...................................................................................... 29-31
RTS—UART Request To Send............................................................................ 29-32
RTS Edge Triggered Interrupt ............................................................................. 29-32
Clear To Send (CTS)............................................................................................ 29-33
Programmable CTS Deassertion.......................................................................... 29-33
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
28.4.3.5
28.4.3.5.1
28.4.4
28.4.4.1
28.4.4.1.1
28.4.4.1.2
28.4.4.2
28.4.4.2.1
28.4.4.2.2
28.4.4.2.3
28.4.4.2.4
28.4.4.2.5
28.4.4.2.6
28.4.5
28.4.6
28.4.6.1
28.4.6.2
28.4.6.3
28.4.6.3.1
28.4.7
28.4.7.1
28.4.7.2
28.4.7.3
28.4.7.4
28.4.7.5
28.4.8
28.4.9
28.5
28.5.1
28.5.2
Title
Page
Number
TXD—UART Transmit ....................................................................................... 29-33
RXD—UART Receive..................................................................................... 29-33
Sub-Block Description............................................................................................. 29-34
Transmitter........................................................................................................... 29-35
Transmitter FIFO Empty Interrupt Suppression.............................................. 29-35
Transmitting a Break Condition ...................................................................... 29-36
Receiver ............................................................................................................... 29-37
Idle Line Detect ............................................................................................... 29-37
Idle Condition Detect Configuration ............................................................... 29-37
Aging Character Detect ................................................................................... 29-38
Receiver Wake ................................................................................................. 29-38
Receiving a BREAK Condition....................................................................... 29-39
Vote Logic........................................................................................................ 29-39
Binary Rate Multiplier (BRM) ................................................................................ 29-40
Baud Rate Automatic Detection Logic.................................................................... 29-42
Baud Rate Automatic Detection Protocol............................................................ 29-43
Baud Rate Automatic Detection Protocol Improved ........................................... 29-43
New Baudrate Determination .............................................................................. 29-44
New Autobaud Counter Stopped Bit and Interrupt ......................................... 29-44
Escape Sequence Detection ..................................................................................... 29-44
Generalities .......................................................................................................... 29-46
Inverted Transmission and Reception Bits (INVT and INVR)............................ 29-46
InfraRed Special Case (IRSC) Bit ....................................................................... 29-46
IrDA Interrupt ...................................................................................................... 29-47
Conclusion About IrDA....................................................................................... 29-48
UART Operation in Low-Power System States....................................................... 29-48
UART Operation in System Debug State ................................................................ 29-49
Programming IrDA Interface ....................................................................................... 29-50
High Speed............................................................................................................... 29-50
Low Speed ............................................................................................................... 29-51
Chapter 29
Fast Ethernet Controller (FEC)
29.1
29.2
29.2.1
29.3
29.3.1
29.3.2
29.3.2.1
Introduction.................................................................................................................... 30-1
Overview........................................................................................................................ 30-1
Features...................................................................................................................... 30-1
Modes of Operation ....................................................................................................... 30-2
Full and Half Duplex Operation ................................................................................ 30-2
Interface Options........................................................................................................ 30-2
10 Mbps and 100 Mbps MII Interface ................................................................... 30-2
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
29.3.2.2
29.3.3
29.3.4
29.4
29.5
29.5.1
29.5.1.1
29.5.2
29.5.3
29.5.4
29.5.5
29.5.6
29.5.7
29.5.8
29.5.9
29.5.10
29.5.11
29.5.12
29.5.13
29.5.14
29.5.14.1
29.5.14.1.1
29.5.14.1.2
29.5.14.1.3
29.5.14.1.4
29.5.14.2
29.5.14.2.1
29.5.14.2.2
29.5.14.2.3
29.5.14.2.4
29.5.14.2.5
29.6
29.6.1
29.6.2
29.6.3
29.6.4
29.6.4.1
29.6.4.2
29.6.4.3
29.6.4.4
29.6.4.5
Title
Page
Number
10 Mpbs 7-Wire Interface Operation..................................................................... 30-2
Address Recognition Options .................................................................................... 30-2
Internal Loopback...................................................................................................... 30-3
FEC Top-Level Functional Diagram.............................................................................. 30-3
Functional Description................................................................................................... 30-4
Initialization Sequence............................................................................................... 30-4
Hardware Controlled Initialization ........................................................................ 30-4
User Initialization (Prior to Asserting ECR[ETHER_EN])....................................... 30-5
Microcontroller Initialization..................................................................................... 30-6
User Initialization (After Asserting ECR[ETHER_EN]) .......................................... 30-6
Network Interface Options......................................................................................... 30-6
FEC Frame Transmission .......................................................................................... 30-7
FEC Frame Reception................................................................................................ 30-8
Ethernet Address Recognition ................................................................................... 30-9
Hash Algorithm........................................................................................................ 30-11
Full Duplex Flow Control........................................................................................ 30-14
Inter-Packet Gap (IPG) Time ................................................................................... 30-15
Collision Handling................................................................................................... 30-15
Internal and External Loopback............................................................................... 30-15
Ethernet Error-Handling Procedure ......................................................................... 30-15
Transmission Errors ............................................................................................. 30-16
Transmitter Underrun ...................................................................................... 30-16
Retransmission Attempts Limit Expired ......................................................... 30-16
Late Collision .................................................................................................. 30-16
Heartbeat.......................................................................................................... 30-16
Reception Errors .................................................................................................. 30-16
Overrun Error................................................................................................... 30-16
Non-Octet Error (Dribbling Bits) .................................................................... 30-17
CRC Error........................................................................................................ 30-17
Frame Length Violation................................................................................... 30-17
Truncation........................................................................................................ 30-17
Memory Map and Register Definition ......................................................................... 30-17
High-Level Module Memory Map........................................................................... 30-17
Detailed Memory Map (Control/Status Registers) .................................................. 30-18
MIB Block Counters Memory Map......................................................................... 30-18
Register Descriptions ............................................................................................... 30-20
Ethernet Interrupt Event Register (EIR) .............................................................. 30-21
Interrupt Mask Register (EIMR) ......................................................................... 30-23
Receive Descriptor Active Register (RDAR) ...................................................... 30-24
Transmit Descriptor Active Register (TDAR) ..................................................... 30-24
Ethernet Control Register (ECR)......................................................................... 30-25
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
29.6.4.6
29.6.4.7
29.6.4.8
29.6.4.9
29.6.4.10
29.6.4.11
29.6.4.12
29.6.4.13
29.6.4.14
29.6.4.15
29.6.4.16
29.6.4.17
29.6.4.18
29.6.4.19
29.6.4.20
29.6.4.21
29.6.4.22
29.6.4.23
29.6.5
29.6.5.1
29.6.5.1.1
29.6.5.1.2
29.6.5.2
29.6.5.3
Title
Page
Number
MII Management Frame Register (MMFR) ........................................................ 30-26
MII Speed Control Register (MSCR) .................................................................. 30-27
MIB Control Register (MIBC) ............................................................................ 30-28
Receive Control Register (RCR) ......................................................................... 30-29
Transmit Control Register (TCR) ........................................................................ 30-30
Physical Address Low Register (PALR).............................................................. 30-31
Physical Address High Register (PAUR)............................................................. 30-32
Opcode/Pause Duration Register (OPD) ............................................................. 30-32
Descriptor Individual Upper Address Register (IAUR) ...................................... 30-33
Descriptor Individual Lower Address Register (IALR) ...................................... 30-33
Descriptor Group Upper Address Register (GAUR) ........................................... 30-34
Descriptor Group Lower Address Register (GALR) ........................................... 30-34
Transmit FIFO Watermark Register (TFWR)...................................................... 30-35
FIFO Receive Bound Register (FRBR) ............................................................... 30-35
FIFO Receive Start Register (FRSR)................................................................... 30-36
Receive Buffer Descriptor Ring Start Register (ERDSR) ................................... 30-36
Transmit Buffer Descriptor Ring Start Register (ETDSR).................................. 30-37
Receive Buffer Size Register (EMRBR) ............................................................. 30-37
Buffer Descriptors.................................................................................................... 30-38
Driver/DMA Operation with Buffer Descriptors................................................. 30-38
Driver/DMA Operation with Transmit BDs .................................................... 30-39
Driver/DMA Operation with Receive BDs...................................................... 30-39
Ethernet Receive Buffer Descriptor (RxBD) ....................................................... 30-40
Ethernet Transmit Buffer Descriptor (TxBD)...................................................... 30-42
Chapter 30
High-Speed USB On-The-Go (HS USB-OTG)
30.1
30.2
30.3
30.3.1
30.3.1.1
30.3.1.2
30.3.1.3
30.4
30.4.1
30.4.2
30.5
30.5.1
30.5.1.1
Overview........................................................................................................................ 31-2
Features .......................................................................................................................... 31-2
Modes of Operation ....................................................................................................... 31-2
Operational Modes..................................................................................................... 31-3
Normal Mode......................................................................................................... 31-3
Bypass Mode ......................................................................................................... 31-3
Low Power Mode................................................................................................... 31-4
External Signal Description ........................................................................................... 31-4
Overview.................................................................................................................... 31-4
Detailed Signal Descriptions ..................................................................................... 31-4
Memory Map and Register Definitions ......................................................................... 31-4
Register Descriptions ................................................................................................. 31-7
USBCONTROL—USB Control Register (USB_CTRL)...................................... 31-7
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
30.5.1.2
30.5.1.3
30.6
30.6.1
30.6.1.1
30.6.2
30.6.2.1
30.6.3
30.6.3.1
30.6.3.2
30.6.3.3
30.6.3.4
30.6.4
30.6.4.1
30.6.4.2
30.6.4.2.1
30.6.4.2.2
30.6.5
30.6.5.1
30.6.5.2
30.6.5.3
30.6.6
30.6.6.1
30.6.6.2
30.6.7
30.6.8
30.6.8.1
30.6.8.2
30.7
30.7.1
30.7.1.1
30.7.1.2
30.7.2
30.7.2.1
30.8
30.8.1
30.8.1.1
30.8.1.2
30.8.1.2.1
30.8.1.2.2
30.8.1.2.3
Title
Page
Number
OTGMIRROR—OTG port Mirror Register ........................................................ 31-10
USB Core Register .............................................................................................. 31-11
Functional Description................................................................................................. 31-11
USB HOST Controller 1.......................................................................................... 31-11
Host Controller 1 to Host Port 1 Interface........................................................... 31-11
USB Host Controller 2............................................................................................. 31-12
Host Port 2 Signal Connections and Signal Muxing ........................................... 31-12
USB OTG Controller ............................................................................................... 31-13
Host Mode ........................................................................................................... 31-14
Peripheral (Device) Mode.................................................................................... 31-14
Special Considerations......................................................................................... 31-14
OTG Port Signal Connections and Signal Muxing.............................................. 31-14
USB Power Control Module.................................................................................... 31-15
Entering Suspend Mode....................................................................................... 31-16
Wake-up Events ................................................................................................... 31-16
Host Mode Events............................................................................................ 31-16
Device mode events ......................................................................................... 31-16
TLL Mode................................................................................................................ 31-17
TLL Functional Description ................................................................................ 31-17
Host Port 1 ........................................................................................................... 31-18
Host Port 2 ........................................................................................................... 31-18
USB Bypass Mode................................................................................................... 31-19
Bypass Mode operation ....................................................................................... 31-19
OTG and Host 1 pin functions ............................................................................. 31-20
ULPI/Serial MUX.................................................................................................... 31-20
Interrupts.................................................................................................................. 31-20
USB Core Interrupts ............................................................................................ 31-20
USB Wake-Up Interrupts..................................................................................... 31-20
Initialization/Application Information ......................................................................... 31-21
Software Model........................................................................................................ 31-21
Device Data Structure.......................................................................................... 31-22
Host Data Structure.............................................................................................. 31-22
Register Interface ..................................................................................................... 31-22
Configuration, Control and Status Register Set................................................... 31-23
Summary of Register Layouts ..................................................................................... 31-27
Identification Registers ............................................................................................ 31-30
ID ......................................................................................................................... 31-30
HWGENERAL .................................................................................................... 31-30
HWHOST ........................................................................................................ 31-31
HWDEVICE.................................................................................................... 31-32
HWTXBUF ..................................................................................................... 31-32
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
30.8.1.2.4
30.8.1.3
30.8.1.3.1
30.8.1.3.2
30.8.1.3.3
30.8.1.3.4
30.8.1.3.5
30.8.1.4
30.8.1.4.1
30.8.1.4.2
30.8.1.4.3
30.8.1.4.4
30.8.1.5
30.8.1.5.1
30.8.1.5.2
30.8.1.5.3
30.8.1.5.4
30.8.1.5.5
30.8.1.5.6
30.8.1.5.7
30.8.1.5.8
30.8.1.5.9
30.8.1.5.10
30.8.1.5.11
30.8.1.5.12
30.8.1.5.13
30.8.1.5.14
30.8.1.5.15
30.8.1.5.16
30.8.1.5.17
30.8.1.5.18
30.8.1.5.19
30.8.1.5.20
30.8.1.5.21
30.8.1.6
30.8.1.6.1
30.8.1.6.2
30.8.2
30.8.2.1
30.8.2.2
30.8.2.3
Title
Page
Number
HWRXBUF ..................................................................................................... 31-33
Device/Host Capability Registers ........................................................................ 31-34
CAPLENGTH—EHCI Compliant .................................................................. 31-34
HCIVERSION—EHCI Compliant.................................................................. 31-34
HCSPARAMS—EHCI Compliant with Extensions ....................................... 31-34
HCCPARAMS—EHCI Compliant.................................................................. 31-36
DCCPARAMS (Non-EHCI)............................................................................ 31-38
Device/Host Timer Registers (Non-EHCI).......................................................... 31-38
GPTIMER0LD (Non-EHCI) ........................................................................... 31-39
GPTIMER0CTRL (Non-EHCI) ...................................................................... 31-39
GPTIMER1LD (Non-EHCI) ........................................................................... 31-40
GPTIMER1CTRL (Non-EHCI) ...................................................................... 31-40
Device/Host Operational Registers...................................................................... 31-41
USBCMD ........................................................................................................ 31-41
USBSTS........................................................................................................... 31-43
USBINTR ........................................................................................................ 31-46
FRINDEX........................................................................................................ 31-48
CTRLDSSEGMENT ....................................................................................... 31-49
PERIODICLISTBASE; DEVICEADDR ........................................................ 31-49
ASYNCLISTADDR; ENDPOINTLISTADDR............................................... 31-51
BURSTSIZE .................................................................................................... 31-52
TXFILLTUNING ............................................................................................ 31-52
ULPI VIEWPORT (Optional) ......................................................................... 31-54
CONFIGFLAG ................................................................................................ 31-56
PORTSCx ........................................................................................................ 31-57
OTGSC ............................................................................................................ 31-63
USBMODE...................................................................................................... 31-65
ENDPTSETUPSTAT ....................................................................................... 31-66
ENDPTPRIME ................................................................................................ 31-67
ENDPTFLUSH................................................................................................ 31-68
ENDPTSTAT ................................................................................................... 31-69
ENDPTCOMPLETE ....................................................................................... 31-70
ENDPTCTRL0 ................................................................................................ 31-71
ENDPTCTRL1—ENDPTCTRL15 ................................................................. 31-72
OTG Operations................................................................................................... 31-74
Register Bits..................................................................................................... 31-74
Hardware Assist............................................................................................... 31-75
Host Data Structures ................................................................................................ 31-76
Periodic Frame List.............................................................................................. 31-77
Asynchronous List Queue Head Pointer.............................................................. 31-78
Isochronous (High-Speed) Transfer Descriptor (iTD)......................................... 31-79
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
30.8.2.3.1
30.8.2.3.2
30.8.2.3.3
30.8.2.4
30.8.2.4.1
30.8.2.4.2
30.8.2.4.3
30.8.2.4.4
30.8.2.4.5
30.8.2.5
30.8.2.5.1
30.8.2.5.2
30.8.2.5.3
30.8.2.5.4
30.8.2.6
30.8.2.6.1
30.8.2.6.2
30.8.2.7
30.8.2.7.1
30.8.2.7.2
30.8.3
30.8.3.1
30.8.3.2
30.8.3.2.1
30.8.3.2.2
30.8.3.2.3
30.8.3.2.4
30.8.3.2.5
30.8.3.3
30.8.3.3.1
30.8.3.4
30.8.3.4.1
30.8.3.5
30.8.3.6
30.8.3.7
30.8.3.7.1
30.8.3.7.2
30.8.3.8
30.8.3.8.1
30.8.3.8.2
30.8.3.8.3
Title
Page
Number
Next Link Pointer ............................................................................................ 31-80
iTD Transaction Status and Control List ......................................................... 31-80
iTD Buffer Page Pointer List (Plus) ................................................................ 31-81
Split Transaction Isochronous Transfer Descriptor (siTD).................................. 31-83
Next Link Pointer ............................................................................................ 31-84
siTD Endpoint Capabilities/Characteristics..................................................... 31-84
siTD Transfer State.......................................................................................... 31-85
siTD Buffer Pointer List (plus)........................................................................ 31-86
siTD Back Link Pointer ................................................................................... 31-87
Queue Element Transfer Descriptor (qTD) ......................................................... 31-88
Next qTD Pointer............................................................................................. 31-88
Alternate Next qTD Pointer............................................................................. 31-89
qTD Token ....................................................................................................... 31-89
qTD Buffer Page Pointer List .......................................................................... 31-93
Queue Head ......................................................................................................... 31-94
Endpoint Capabilities/Characteristics.............................................................. 31-95
Transfer Overlay .............................................................................................. 31-98
Periodic Frame Span Traversal Node (FSTN) .................................................... 31-99
FSTN Normal Path Pointer ........................................................................... 31-100
FSTN Back Path Link Pointer ...................................................................... 31-100
Host Operational Model ........................................................................................ 31-101
Host Controller Initialization ............................................................................ 31-101
Port Routing and Control .................................................................................. 31-102
Port Routing Control via EHCI Configured (CF) Bit ................................... 31-104
Port Routing Control via PortOwner and Disconnect Event ........................ 31-104
Example Port Routing State Machine .......................................................... 31-106
Port Power .................................................................................................... 31-107
Port Reporting Over-Current ........................................................................ 31-107
Suspend/Resume ............................................................................................... 31-108
Port Suspend/Resume ................................................................................... 31-109
[Schedule Traversal Rules ................................................................................ 31-110
Example—Preserving Micro-Frame Integrity .............................................. 31-112
Periodic Schedule Frame Boundaries vs Bus Frame Boundaries ..................... 31-115
Periodic Schedule ............................................................................................. 31-117
Managing Isochronous Transfers Using iTDs .................................................. 31-118
Host Controller Operational Model for iTDs ............................................... 31-118
Software Operational Model for iTDs .......................................................... 31-120
Asynchronous Schedule .................................................................................... 31-122
Adding Queue Heads to Asynchronous Schedule ......................................... 31-124
Removing Queue Heads from Asynchronous Schedule ............................... 31-124
Empty Asynchronous Schedule Detection ................................................... 31-127
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
30.8.3.8.4
30.8.3.8.5
30.8.3.8.6
30.8.3.9
30.8.3.9.1
30.8.3.10
30.8.3.10.1
30.8.3.10.2
30.8.3.10.3
30.8.3.10.4
30.8.3.10.5
30.8.3.10.6
30.8.3.10.7
30.8.3.10.8
30.8.3.11
30.8.3.12
30.8.3.12.1
30.8.3.12.2
30.8.3.12.3
30.8.3.13
30.8.3.14
30.8.3.15
30.8.3.15.1
30.8.3.15.2
30.8.4
30.8.4.1
30.8.4.1.1
30.8.4.1.2
30.8.4.1.3
30.8.4.1.4
30.8.4.1.5
30.8.4.2
30.8.4.3
30.8.4.3.1
30.8.4.3.2
30.8.4.4
30.8.4.4.1
30.8.4.5
30.8.4.5.1
30.8.4.5.2
30.8.4.5.3
Title
Page
Number
Restarting Asynchronous Schedule Before EOF .......................................... 31-127
Asynchronous Schedule Traversal : Start Event ........................................... 31-130
Reclamation Status Bit (USBSTS Register) ................................................. 31-130
Operational Model for Nak Counter.................................................................. 31-131
Nak Count Reload Control ........................................................................... 31-132
Managing Control/Bulk/Interrupt Transfers via Queue Heads.......................... 31-133
Fetch Queue Head ........................................................................................ 31-134
Advance Queue ............................................................................................. 31-135
Execute Transaction ...................................................................................... 31-136
Write Back qTD ............................................................................................ 31-141
Follow Queue Head Horizontal Pointer ........................................................ 31-141
Buffer Pointer List Use for Data Streaming with qTDs ............................... 31-141
Adding Interrupt Queue Heads to the Periodic Schedule ............................. 31-143
Managing Transfer Complete Interrupts from Queue Heads ....................... 31-143
Ping Control ...................................................................................................... 31-144
Split Transactions ............................................................................................. 31-145
Split Transactions for Asynchronous Transfers ............................................ 31-145
Split Transaction Interrupt ............................................................................ 31-147
Split Transaction Isochronous ...................................................................... 31-160
Host Controller Pause ....................................................................................... 31-173
Port Test Modes ................................................................................................ 31-174
Interrupts ........................................................................................................... 31-174
Transfer/Transaction Based Interrupts .......................................................... 31-175
Host Controller Event Interrupts .................................................................. 31-178
EHCI Deviation ..................................................................................................... 31-179
Embedded Transaction Translator Function...................................................... 31-180
Capability Registers....................................................................................... 31-180
Operational Registers..................................................................................... 31-180
Discovery....................................................................................................... 31-180
Data Structures .............................................................................................. 31-181
Operational Model ......................................................................................... 31-181
Device Operation ............................................................................................... 31-184
USBMODE Register ......................................................................................... 31-184
Non-Zero Fields the Register File. ................................................................ 31-184
SOF Interrupt ................................................................................................. 31-184
Embedded Design Interface............................................................................... 31-184
Frame Adjust Register ................................................................................... 31-184
Miscellaneous Variations from EHCI................................................................ 31-185
Programmable Physical Interface Behaviour ................................................ 31-185
Discovery....................................................................................................... 31-185
Port Test Mode............................................................................................... 31-186
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
30.8.5
30.8.5.1
30.8.5.1.1
30.8.5.1.2
30.8.5.1.3
30.8.5.1.4
30.8.5.2
30.8.6
30.8.6.1
30.8.6.2
30.8.6.2.1
30.8.6.2.2
30.8.6.2.3
30.8.6.2.4
30.8.6.2.5
30.8.6.2.6
30.8.6.3
30.8.6.3.1
30.8.6.3.2
30.8.6.3.3
30.8.6.4
30.8.6.4.1
30.8.6.4.2
30.8.6.5
30.8.6.5.1
30.8.6.5.2
30.8.6.5.3
30.8.6.5.4
30.8.6.5.5
30.8.6.5.6
30.8.6.6
30.8.6.6.1
30.8.6.6.2
30.8.6.6.3
Title
Page
Number
Device Data Structures .......................................................................................... 31-186
Endpoint Queue Head (dQH) ............................................................................ 31-187
Endpoint Capabilities/Characteristics............................................................ 31-187
Transfer Overlay ............................................................................................ 31-188
Current dTD Pointer ...................................................................................... 31-188
Set-up Buffer ................................................................................................. 31-189
Endpoint Transfer Descriptor (dTD) ................................................................. 31-189
Device Operational Model..................................................................................... 31-191
Device Controller Initialization ......................................................................... 31-191
Port State and Control........................................................................................ 31-192
Bus Reset ....................................................................................................... 31-193
Suspend/Resume............................................................................................ 31-194
Managing Endpoints...................................................................................... 31-195
Endpoint Initialization ................................................................................... 31-196
Stalling........................................................................................................... 31-196
Data Toggle ................................................................................................... 31-197
Operational Model For Packet Transfers ........................................................... 31-197
Interrupt/Bulk Endpoint Operational Model ................................................. 31-198
Control Endpoint Operation Model ............................................................... 31-200
Isochronous Endpoint Operational Model..................................................... 31-203
Managing Queue Heads..................................................................................... 31-205
Queue Head Initialization.............................................................................. 31-206
Operational Model For Setup Transfers ........................................................ 31-206
Managing Transfers with Transfer Descriptors ................................................. 31-207
Software Link Pointers .................................................................................. 31-207
Building a Transfer Descriptor ...................................................................... 31-207
Executing A Transfer Descriptor ................................................................... 31-207
Transfer Completion ...................................................................................... 31-208
Flushing/De-priming an Endpoint ................................................................. 31-209
Device Error Matrix....................................................................................... 31-209
Servicing Interrupts ........................................................................................... 31-210
High-Frequency Interrupts............................................................................. 31-210
Low-Frequency Interrupts ............................................................................. 31-210
Error Interrupts .............................................................................................. 31-210
Chapter 31
General Purpose Timer (GPT)
31.1
31.2
31.2.1
Introduction.................................................................................................................... 32-1
Operation ....................................................................................................................... 32-2
Clocks ........................................................................................................................ 32-3
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Paragraph
Number
31.2.2
31.2.3
31.2.4
31.2.5
31.3
31.3.1
31.3.2
31.3.3
31.3.4
31.3.5
31.3.6
Title
Page
Number
Operation During Low-Power Mode ......................................................................... 32-3
Capture Event ............................................................................................................ 32-3
Compare Event .......................................................................................................... 32-3
Modes of Operation ................................................................................................... 32-4
Programming Model ...................................................................................................... 32-4
GPT Control Registers............................................................................................... 32-7
GPT Prescaler Register .............................................................................................. 32-9
GPT Compare Register............................................................................................ 32-10
GPT Capture Register.............................................................................................. 32-11
GPT Counter Register.............................................................................................. 32-12
GPT Status Register................................................................................................. 32-13
Chapter 32
Pulse-Width Modulator (PWM)
32.1
32.2
32.2.1
32.2.1.1
32.3
32.3.1
32.3.2
32.3.2.1
32.3.2.2
32.3.2.3
32.3.2.4
32.3.2.5
32.3.2.6
32.4
32.4.1
32.4.1.1
32.4.1.2
32.4.1.3
32.4.1.4
32.4.1.5
32.5
32.5.1
32.5.2
Overview........................................................................................................................ 33-1
Signal Description.......................................................................................................... 33-2
External Signals ......................................................................................................... 33-3
PWMO Signal........................................................................................................ 33-4
Memory Map and Register Definition ........................................................................... 33-4
Register Summary...................................................................................................... 33-4
Register Descriptions ................................................................................................. 33-6
PWM Control Register (PWMCR)........................................................................ 33-6
PWM Status Register (PWMSR)........................................................................... 33-8
PWM Interrupt Register (PWMIR) ....................................................................... 33-9
PWM Sample Register (PWMSAR) ................................................................... 33-10
PWM Period Register (PWMPR) ........................................................................ 33-11
PWM Counter Register (PWMCNR) .................................................................. 33-12
Functional Description................................................................................................. 33-12
Operation ................................................................................................................. 33-12
Clocks .................................................................................................................. 33-13
FIFO..................................................................................................................... 33-13
Rollover and Compare Event............................................................................... 33-14
Low Power Mode Behavior ................................................................................. 33-14
Debug Mode Behavior......................................................................................... 33-14
PWM Clocking ............................................................................................................ 33-15
PWM Clock Inputs .................................................................................................. 33-16
ipg_enable_clk Generation ...................................................................................... 33-17
Chapter 33
Real Time Clock (RTC)
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
xxxv
Contents
Paragraph
Number
33.1
33.2
33.2.1
33.2.2
33.3
33.3.1
33.4
33.4.1
33.4.2
33.4.3
33.4.3.1
33.4.3.2
33.4.3.3
33.4.3.4
33.4.3.5
33.4.3.6
33.4.3.7
33.4.3.8
33.4.3.9
33.4.3.10
33.5
33.5.1
33.5.2
33.5.3
33.5.4
33.6
33.6.1
33.6.2
Title
Page
Number
Introduction.................................................................................................................... 34-1
Overview........................................................................................................................ 34-2
Features...................................................................................................................... 34-2
Modes of Operation ................................................................................................... 34-2
External Signal Description ........................................................................................... 34-3
Overview.................................................................................................................... 34-3
Memory Map and Register Definition ........................................................................... 34-3
Memory Map ............................................................................................................. 34-3
Register Summary...................................................................................................... 34-4
Register Descriptions ................................................................................................. 34-6
RTC Hours and Minutes Counter Register (HOURMIN) ..................................... 34-6
RTC Seconds Counter Register (SECONDS) ....................................................... 34-7
RTC Hours and Minutes Alarm Register (ALRM_HM) ....................................... 34-8
RTC Seconds Alarm Register (ALRM_SEC) ....................................................... 34-9
RTC Control Register (RTCCTL)........................................................................ 34-10
RTC Interrupt Status Register (RTCISR) ............................................................ 34-11
RTC Interrupt Enable Register (RTCIENR)........................................................ 34-13
RTC Stopwatch Minutes Register (STPWCH).................................................... 34-15
RTC Days Counter Register (DAYR) .................................................................. 34-16
RTC Day Alarm Register (DAYALARM) ........................................................... 34-17
Functional Description................................................................................................. 34-18
Prescaler and Counter .............................................................................................. 34-18
Alarm ....................................................................................................................... 34-18
Sampling Timer ....................................................................................................... 34-18
Minute Stopwatch .................................................................................................... 34-19
Initialization/Application Information ......................................................................... 34-20
Flowchart of RTC Operation ................................................................................... 34-20
Code Example of ARM Instruction ......................................................................... 34-20
Chapter 34
Watchdog Timer (WDOG)
34.1
34.1.1
34.2
34.2.1
34.2.1.1
34.2.2
34.3
34.3.1
34.3.2
Overview........................................................................................................................ 35-1
Features...................................................................................................................... 35-2
External Signal Description ........................................................................................... 35-2
Detailed External Signal Descriptions....................................................................... 35-2
IPP_WDOG, IPP_WDOG_OE.............................................................................. 35-2
Internal Port Signals................................................................................................... 35-3
Memory Map and Register Definitions ......................................................................... 35-4
Watchdog Timer Memory Map.................................................................................. 35-4
Register Summary...................................................................................................... 35-4
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
34.4
34.4.1
34.4.2
34.4.2.1
34.5
34.5.1
34.5.2
34.5.3
34.5.3.1
34.5.3.2
34.5.3.3
34.5.3.4
34.5.4
34.5.5
34.5.5.1
34.5.5.2
34.5.6
34.5.7
34.6
34.6.1
Title
Page
Number
Register Descriptions ..................................................................................................... 35-5
Watchdog Control Register (WCR) ........................................................................... 35-5
Watchdog Service Register (WSR)............................................................................ 35-6
Watchdog Reset Status Register (WRSR) ............................................................. 35-7
Functional Description................................................................................................... 35-8
Timing Specifications ................................................................................................ 35-8
Watchdog During Reset ............................................................................................. 35-8
Watchdog After Reset ................................................................................................ 35-8
Initial Load............................................................................................................. 35-8
Timer Countdown .................................................................................................. 35-8
Reloading the Counter ........................................................................................... 35-9
Time-Out................................................................................................................ 35-9
Generation of Transfer Error on the IP Bus............................................................... 35-9
Low-Power and DEBUG Modes ............................................................................... 35-9
Low-Power Mode (WAIT, STOP) ......................................................................... 35-9
DEBUG Mode ..................................................................................................... 35-10
Watchdog Reset Control .......................................................................................... 35-10
WDOG Operation.................................................................................................... 35-10
Initialization/Application Information ......................................................................... 35-11
State Machine .......................................................................................................... 35-11
Chapter 35
AHB-Lite IP Interface (AIPI) Module
35.1
35.1.1
35.1.2
35.2
35.3
35.3.1
35.3.2
35.3.3
Programming Model ...................................................................................................... 36-2
Peripheral Size Registers[1:0] ................................................................................... 36-3
Peripheral Access Register ........................................................................................ 36-4
AIPI1 and AIPI2 Peripheral Widths and PSR Setting ................................................... 36-4
Interface Timing............................................................................................................. 36-6
Read Cycles ............................................................................................................... 36-6
Write Cycles .............................................................................................................. 36-7
Aborted Cycles .......................................................................................................... 36-7
Chapter 36
Multi-Layer AHB Crossbar Switch (MAX)
36.1
36.2
36.3
36.4
36.4.1
Features .......................................................................................................................... 37-1
Overview........................................................................................................................ 37-1
General Operation.......................................................................................................... 37-2
Memory Map and Register Definition ........................................................................... 37-3
Register Summary...................................................................................................... 37-3
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
36.4.2
36.4.3
36.4.4
36.4.5
36.4.6
36.4.7
36.4.8
36.4.8.1
36.5
36.5.1
36.5.1.1
36.5.1.2
36.5.1.3
36.5.2
36.5.2.1
36.5.3
36.5.3.1
36.5.3.2
36.5.3.3
36.5.3.4
36.5.3.5
36.5.3.5.1
36.5.3.5.2
36.5.4
36.5.4.1
36.5.4.2
36.5.4.3
36.5.4.4
36.5.4.4.1
36.5.4.4.2
36.5.4.4.3
36.5.4.4.4
36.5.4.4.5
36.6
36.7
36.7.1
36.7.2
Title
Page
Number
Memory Map ............................................................................................................. 37-4
Register Summary...................................................................................................... 37-4
MAX Register Descriptions....................................................................................... 37-6
Master Priority Registers (MPR0–MPR2)................................................................. 37-6
Alternate Master Priority Register for Slave Port 0–2 (AMPR0–2).......................... 37-7
General Purpose Control Register for Slave Port 0–2 (SGPCR0–2) ......................... 37-9
Alternate SGPCR for Slave Port 0–2 (ASGPCR0–2).............................................. 37-11
General Purpose Control Register for Master Port 0–5 (MGPCR0–5) ............... 37-13
Function ....................................................................................................................... 37-14
Arbitration................................................................................................................ 37-14
Arbitration During Undefined Length Bursts...................................................... 37-14
Fixed Priority Operation ...................................................................................... 37-15
Round-Robin Priority Operation ......................................................................... 37-15
Priority Assignment ................................................................................................. 37-15
Context Switching ............................................................................................... 37-16
Master Port Functionality ........................................................................................ 37-16
General................................................................................................................. 37-16
Decoders .............................................................................................................. 37-17
Capture Unit......................................................................................................... 37-18
Registers .............................................................................................................. 37-18
State Machine ...................................................................................................... 37-18
States................................................................................................................ 37-18
Slave Swapping................................................................................................ 37-19
Slave Port Functionality........................................................................................... 37-19
General................................................................................................................. 37-19
Muxes .................................................................................................................. 37-19
Registers .............................................................................................................. 37-20
State Machine ...................................................................................................... 37-21
States................................................................................................................ 37-21
Arbitration ....................................................................................................... 37-21
Master Hand-Off.............................................................................................. 37-21
Parking............................................................................................................. 37-23
Halt Mode ........................................................................................................ 37-25
Initialization/Application Information ......................................................................... 37-25
Interface ....................................................................................................................... 37-26
Master Ports ............................................................................................................. 37-26
Slave Ports ............................................................................................................... 37-26
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Contents
Paragraph
Number
Title
Page
Number
Chapter 37
Direct Memory Access Controller (DMAC)
37.1
37.2
37.2.1
37.2.2
37.3
37.4
37.4.1
37.4.2
37.4.3
37.4.3.1
37.4.3.2
37.4.3.3
37.4.3.4
37.4.3.5
37.4.3.6
37.4.3.7
37.4.3.8
37.4.4
37.4.4.1
37.4.4.2
37.4.4.3
37.4.5
37.4.5.1
37.4.5.2
37.4.5.3
37.4.5.4
37.4.5.5
37.4.5.6
37.4.5.7
37.4.5.8
37.4.5.9
37.5
37.6
37.6.1
37.6.2
37.7
37.7.1
37.7.2
Features .......................................................................................................................... 38-1
DMA Request and Acknowledge .................................................................................. 38-2
DMA Request ............................................................................................................ 38-2
External DMA Request and Grant............................................................................. 38-2
DMA Request Mapping................................................................................................. 38-3
Memory Map and Register Definition ........................................................................... 38-5
DMAC Memory Map ................................................................................................ 38-5
Register Summary...................................................................................................... 38-6
General Registers ..................................................................................................... 38-11
DMA Control Register (DCR)............................................................................. 38-11
DMA Interrupt Status Register (DISR) ............................................................... 38-12
DMA Interrupt Mask Register (DIMR)............................................................... 38-13
DMA Burst Time-Out Status Register (DBTOSR) ............................................. 38-14
DMA Request Time-Out Status Register (DRTOSR) ......................................... 38-15
DMA Transfer Error Status Register (DSESR) ................................................... 38-16
DMA Buffer Overflow Status Register (DBOSR) .............................................. 38-17
DMA Burst Time-Out Control Register (DBTOCR) .......................................... 38-18
2D Memory Registers (A and B) ............................................................................. 38-19
W-Size Registers (WSRA, WSRB) ..................................................................... 38-20
X-Size Registers (XSRA, XSRB)........................................................................ 38-21
Y-Size Registers (YSRA, YSRB) ........................................................................ 38-22
Channel Registers .................................................................................................... 38-23
Channel Source Address Registers (SAR0–SAR15)........................................... 38-23
Destination Address Registers (DAR0–DAR15)................................................. 38-24
Channel Count Registers (CNTR0–CNTR15) .................................................... 38-25
Channel Control Registers (CCR0–CCR15) ....................................................... 38-26
Channel Request Source Select Registers (RSSR0–RSSR15) ............................ 38-28
Channel Burst Length Registers (BLR0–BLR15) ............................................... 38-29
Channel Request Time-Out Registers (RTOR0–RTOR15) ................................. 38-30
Channel Bus Utilization Control Registers (BUCR0–BUCR15) ........................ 38-31
Channel Counter Registers (CCNR0–CCNR15)................................................. 38-32
DMA Chaining ............................................................................................................ 38-32
Special Cases of Burst Length and Access Size Settings ............................................ 38-33
Memory Increment .................................................................................................. 38-33
Memory Decrement ................................................................................................. 38-34
Special Cases When CCNR and CNTR Values Differ ................................................ 38-34
CNTR Not A Multiple of Destination Access Size ................................................. 38-34
BL is Not a Multiple of Destination Access Size, CNTR Is.................................... 38-35
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
37.8
37.9
37.10
Title
Page
Number
Application Note.......................................................................................................... 38-35
DMA Burst Termination .............................................................................................. 38-36
Glossary of Terms Used............................................................................................... 38-36
Chapter 38
Digital Audio MUX (AUDMUX)
38.1
38.2
38.3
38.4
38.5
38.6
38.7
38.8
38.9
38.10
38.11
38.11.1
38.11.2
38.11.3
38.11.4
38.12
38.12.1
38.12.2
38.12.3
38.12.4
Features .......................................................................................................................... 39-1
Overview........................................................................................................................ 39-1
Internal Network Mode.................................................................................................. 39-4
Tx/Rx Switch and External Network Mode................................................................... 39-4
Frame Sync and Clocks ................................................................................................. 39-6
Synchronous Mode (4-Wire Interface) .......................................................................... 39-7
Asynchronous Mode (6-Wire Interface) ........................................................................ 39-7
SSI to Peripheral Connection......................................................................................... 39-8
SSI to SAP ................................................................................................................... 39-11
Peripheral Port to Peripheral Port ................................................................................ 39-11
Memory Map and Register Definition ......................................................................... 39-14
AUDMUX Memory Map......................................................................................... 39-14
Register Summary.................................................................................................... 39-14
Host Port Configuration Register (HPCR1–2) ........................................................ 39-16
Peripheral Port Configuration Registers (PPCR1–2)............................................... 39-18
Peripheral Connectivity Through AUDMUX Configuration....................................... 39-20
Generic Configuration ............................................................................................. 39-21
AUDMUX Configuration with SSI1 and SAP as Master........................................ 39-23
Tx-Rx Switch Enabled............................................................................................. 39-24
Internal/External Network Mode ............................................................................. 39-25
Chapter 39
CMOS Sensor Interface (CSI)
39.1
39.2
39.2.1
39.3
39.3.1
39.3.2
39.3.3
39.3.4
39.3.5
39.4
CSI Architecture ............................................................................................................ 40-1
CSI Interface Signal Description ................................................................................... 40-3
Signals from CSI to eMMA Pre-Processor Block (PrP)............................................ 40-3
Principles of Operation .................................................................................................. 40-3
Gated Clock Mode ..................................................................................................... 40-4
Non-Gated Clock Mode............................................................................................. 40-4
CCIR656 Interlace Mode........................................................................................... 40-4
CCIR656 Progressive Mode ...................................................................................... 40-6
Error Correction for CCIR656 Coding ...................................................................... 40-7
Interrupt Generation....................................................................................................... 40-7
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
39.4.1
39.4.2
39.4.3
39.4.4
39.4.5
39.4.6
39.4.6.1
39.4.6.2
39.4.7
39.5
39.5.1
39.5.2
39.5.3
39.5.4
39.5.5
39.5.6
39.5.7
39.5.8
39.5.9
Title
Page
Number
Start Of Frame Interrupt (SOF_INT)......................................................................... 40-7
End Of Frame Interrupt (EOF_INT).......................................................................... 40-8
Change Of Field Interrupt (COF_INT)...................................................................... 40-8
CCIR Error Interrupt (ECC_INT).............................................................................. 40-8
Data Packing Style..................................................................................................... 40-8
RX FIFO Path ............................................................................................................ 40-9
RGB565 Data......................................................................................................... 40-9
RGB888 Data....................................................................................................... 40-10
STAT FIFO Path ...................................................................................................... 40-10
Memory Map and Register Definition ......................................................................... 40-11
CSI Memory Map .................................................................................................... 40-11
Register Summary.................................................................................................... 40-11
CSI Control Register 1 (CSICR1) ........................................................................... 40-14
CSI Control Register 2 (CSICR2) ........................................................................... 40-17
CSI Control Register 3 (CSICR3) ........................................................................... 40-19
CSI Status Register (CSISR) ................................................................................... 40-20
CSI STATFIFO Register (CSISTATFIFO) .............................................................. 40-22
CSI RxFIFO Register (CSIRFIFO) ......................................................................... 40-23
CSI RX Count Register (CSIRXCNT) .................................................................... 40-23
Chapter 40
Video Codec (Video_Codec)
40.1
40.2
40.3
40.3.1
40.3.2
40.4
40.4.1
40.4.2
40.4.3
40.4.3.1
40.4.3.2
40.4.3.3
40.4.3.4
40.4.3.5
40.4.3.6
40.4.3.7
40.5
40.5.1
Features .......................................................................................................................... 41-1
Overview........................................................................................................................ 41-2
Clock Domain and Reset ............................................................................................... 41-3
Clocks ........................................................................................................................ 41-3
Reset........................................................................................................................... 41-3
Memory Map and Register Definition ........................................................................... 41-4
Memory Map ............................................................................................................. 41-4
Register Summary...................................................................................................... 41-5
Register Descriptions ................................................................................................. 41-7
Video Codec Code Run Register (CodeRun) ........................................................ 41-7
Video Codec BIT Boot Code Download Data Register (CodeDown)................... 41-8
Video Codec Host Interrupt Request Register (HostIntReq)................................. 41-9
Video Codec BIT Interrupt Clear Register (BitIntClear)....................................... 41-9
Video Codec BIT Interrupt Status Register (BitIntSts) ....................................... 41-10
Video Codec BIT Code Reset Register (BitCodeReset)...................................... 41-11
Video Codec BIT Current PC Register (BitCurPc) ............................................. 41-12
Functional Description................................................................................................. 41-12
Video Codec Architecture........................................................................................ 41-12
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Paragraph
Number
40.5.1.1
40.5.1.2
40.5.2
40.6
40.7
40.7.1
40.7.1.1
40.7.1.2
40.7.1.3
40.7.1.4
40.7.1.5
40.7.1.6
40.7.1.7
40.7.1.8
40.7.2
Title
Page
Number
Embedded BIT processor .................................................................................... 41-12
Codec Hardware Accelerator............................................................................... 41-13
Interrupts.................................................................................................................. 41-15
Initialization Information ............................................................................................. 41-15
Application Information .............................................................................................. 41-16
Video Codec Processing Control ............................................................................. 41-16
Video Codec Processing Flow ............................................................................. 41-16
Video Codec Processing Finish Detection........................................................... 41-18
Video Codec Processing Flow Example.............................................................. 41-19
Frame Buffer........................................................................................................ 41-20
BIT Processor Program Memory......................................................................... 41-24
Working Buffer .................................................................................................... 41-24
Bitstream Buffer .................................................................................................. 41-24
Buffer Requirement Summary............................................................................. 41-25
Application Using Cases.......................................................................................... 41-25
Chapter 41
enhanced Multimedia Accelerator Light (eMMA_lt)
41.1
41.1.1
41.2
41.2.1
41.2.2
41.2.3
41.3
41.3.1
41.3.2
41.3.3
41.3.4
41.3.5
41.3.6
41.4
41.4.1
41.4.2
41.4.3
41.4.4
41.4.5
41.4.6
41.4.7
41.4.8
Introduction.................................................................................................................... 42-1
Features...................................................................................................................... 42-1
eMMA_lt Architecture .................................................................................................. 42-2
Pre-Processor (PrP).................................................................................................... 42-3
Post-Processor (PP).................................................................................................... 42-3
64-Bit Gasket ............................................................................................................. 42-4
Post-Processor (PP)........................................................................................................ 42-5
Color Space Conversion (CSC) ................................................................................. 42-7
Input Interface............................................................................................................ 42-9
Output Interface ....................................................................................................... 42-10
Data Flow................................................................................................................. 42-11
Relationship of Register Fields Related to the Input Frame.................................... 42-11
Relationship of Register Fields Related to Output Frame ....................................... 42-12
Post Processor (PP) Programming Model ................................................................... 42-13
PP Control Register ................................................................................................. 42-14
PP Interrupt Control Register .................................................................................. 42-16
PP Interrupt Status Register..................................................................................... 42-17
PP Source Y Address Register................................................................................. 42-18
PP Source Cb Address Register............................................................................... 42-18
PP Source Cr Address Register ............................................................................... 42-19
PP Destination RGB Frame Start Address Register ................................................ 42-20
PP Quantizer Start Address Register ....................................................................... 42-20
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
41.4.9
41.4.10
41.4.11
41.4.12
41.4.13
41.4.14
41.4.15
41.4.16
41.4.17
41.5
41.5.1
41.5.2
41.5.2.1
41.5.2.2
41.5.2.3
41.5.2.4
41.5.2.5
41.5.3
41.5.3.1
41.5.3.2
41.5.3.3
41.5.3.4
41.5.3.5
41.5.3.6
41.5.4
41.5.5
41.5.5.1
41.5.5.2
41.5.6
41.5.7
41.5.8
41.5.9
41.5.10
41.5.11
41.5.12
41.5.13
41.5.14
41.6
41.6.1
41.6.2
41.6.3
Title
Page
Number
PP Process Frame Parameter Register ..................................................................... 42-21
PP Source Frame Width Register............................................................................. 42-22
PP Destination Display Width Register ................................................................... 42-23
PP Destination Image Size Register ........................................................................ 42-23
PP Destination Frame Format Control Register ...................................................... 42-24
PP Resize Table Index Register ............................................................................... 42-25
PP CSC COEF 123 Register.................................................................................... 42-27
PP CSC COEF_4 Register ....................................................................................... 42-28
PP Resize Coefficient Table..................................................................................... 42-29
Pre-Processor ............................................................................................................... 42-30
Features.................................................................................................................... 42-31
Input Data Formats .................................................................................................. 42-31
Input Size ............................................................................................................. 42-31
Resize Ratios ....................................................................................................... 42-31
Output Formats .................................................................................................... 42-32
Output Data.......................................................................................................... 42-32
Output Size .......................................................................................................... 42-32
Resize....................................................................................................................... 42-32
Bilinear Resize in PrP.......................................................................................... 42-32
Averaging Resize in PrP ...................................................................................... 42-33
Combined Bilinear and Averaging ...................................................................... 42-34
Resize Output Image Size.................................................................................... 42-34
Channel-1 Output................................................................................................. 42-34
Channel-2 Output................................................................................................. 42-35
Color Space Conversion (CSC) ............................................................................... 42-35
RGB to YUV ........................................................................................................... 42-35
YUV to RGB ....................................................................................................... 42-36
Clipping of RGB and YUV Outputs.................................................................... 42-36
Frame Skip............................................................................................................... 42-36
LOOP Mode (LEN) ................................................................................................. 42-37
Channel-1 and Channel-2 Enable ............................................................................ 42-37
Channel-2 Flow Control .......................................................................................... 42-38
Line Buffer Overflow............................................................................................... 42-38
Relationship of Register Fields Related to the Input Frame.................................... 42-39
Relationship of Register Fields Related to Channel-1 Output Frame ..................... 42-40
CSI Frame Cropping................................................................................................ 42-40
CSI-PrP Link............................................................................................................ 42-42
Pre-Processor (PrP) Programming Model ................................................................... 42-43
PrP Control Register ................................................................................................ 42-45
PrP Interrupt Control Register ................................................................................. 42-48
PrP Interrupt Status Register.................................................................................... 42-49
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
41.6.4
41.6.5
41.6.6
41.6.7
41.6.8
41.6.9
41.6.10
41.6.11
41.6.12
41.6.13
41.6.14
41.6.15
41.6.16
41.6.17
41.6.18
41.6.19
41.6.20
41.6.21
41.6.22
41.6.23
41.6.24
41.6.25
41.6.26
41.6.27
41.6.28
41.6.29
41.6.30
41.6.31
41.6.32
41.6.33
Title
Page
Number
PrP Source Y Address Register ............................................................................... 42-50
PrP Source Cb Address Register ............................................................................. 42-51
PrP Source Cr Address Register .............................................................................. 42-51
PrP Destination RGB1 Frame Start Address Register............................................. 42-52
PrP Destination RGB2 Frame Start Address Register............................................. 42-53
PrP Destination Y Address Register ........................................................................ 42-53
PrP Destination Cb Address Register ...................................................................... 42-54
PrP Destination Cr Address Register....................................................................... 42-55
PrP Source Frame Size Register .............................................................................. 42-55
PrP Destination Channel-1 Line Stride Register ..................................................... 42-56
PrP Source Pixel Format Control Register .............................................................. 42-57
PrP Channel-1 Pixel Format Control Register......................................................... 42-59
PrP Destination Channel-1 Output Image Size Register ......................................... 42-60
PrP Destination Channel-2 Output Image Size Register ......................................... 42-61
PrP Source Line Stride Register .............................................................................. 42-62
PrP CSC Coefficient 012 ......................................................................................... 42-63
PrP CSC Coefficient 345 ......................................................................................... 42-64
PrP CSC Coefficient 678 ......................................................................................... 42-65
PrP Channel 1 Horizontal Resize Coefficient-1 ...................................................... 42-66
PrP Channel1 Horizontal Resize Coefficient-2 ....................................................... 42-67
PrP Channel 1 Horizontal Resize Valid ................................................................... 42-69
PrP Channel1 Vertical Resize Coefficient-1 ............................................................ 42-70
PrP Channel 1 Vertical Resize Coefficient 2 ........................................................... 42-71
PrP Channel 1 Vertical Resize Valid........................................................................ 42-72
PrP Channel-2 Horizontal Resize Coefficient-1 ...................................................... 42-73
PrP Channel-2 Horizontal Resize Coefficient-2 ...................................................... 42-74
PrP Channel-2 Horizontal Resize Valid................................................................... 42-75
PrP Channel2 Vertical Resize Coefficient-1 ............................................................ 42-76
PrP Channel 2 Vertical Resize Coefficient 2 ........................................................... 42-77
PrP Channel 2 Vertical Resize Valid........................................................................ 42-78
Chapter 42
Synchronous Serial Interface (SSI)
42.1
42.1.1
42.1.2
42.1.2.1
42.1.2.1.1
42.1.2.1.2
42.1.2.2
Overview........................................................................................................................ 43-2
Features...................................................................................................................... 43-3
Modes of Operation ................................................................................................... 43-3
Normal Mode......................................................................................................... 43-5
Normal Mode Transmit ..................................................................................... 43-5
Normal Mode Receive ....................................................................................... 43-6
Network Mode ....................................................................................................... 43-8
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
42.1.2.2.1
42.1.2.2.2
42.1.2.3
42.1.2.4
42.1.2.5
42.1.2.5.1
42.1.2.5.2
42.1.2.6
42.1.2.7
42.2
42.2.1
42.2.2
42.2.2.1
42.2.2.2
42.2.2.3
42.2.2.4
42.2.2.5
42.2.2.6
42.2.3
42.3
42.3.1
42.3.2
42.3.3
42.3.3.1
42.3.3.2
42.3.3.3
42.3.3.4
42.3.3.5
42.3.3.6
42.3.3.7
42.3.3.8
42.3.3.9
42.3.3.10
42.3.3.11
42.3.3.12
42.3.3.13
42.3.3.14
42.3.3.15
42.3.3.16
42.3.3.17
Title
Page
Number
Network Mode Transmit.................................................................................... 43-9
Network Mode Receive ................................................................................... 43-10
Gated Clock Mode............................................................................................... 43-12
I2S Mode ............................................................................................................. 43-14
AC97 Mode.......................................................................................................... 43-16
AC97 Fixed Mode (SACNT[1]=0) .................................................................. 43-18
AC97 Variable Mode (SACNT[1]=1).............................................................. 43-18
External Frame and Clock Operation .................................................................. 43-18
Data Alignment Formats Supported .................................................................... 43-18
External Signal Description ......................................................................................... 43-20
Overview.................................................................................................................. 43-20
Detailed Signal Descriptions ................................................................................... 43-20
SRCK—Serial Receive Clock ............................................................................. 43-20
SRFS—Serial Receive Frame Sync..................................................................... 43-21
SRXD—Serial Receive Data ............................................................................... 43-21
STCK—Serial Transmit Clock............................................................................ 43-21
STFS—Serial Transmit Frame Sync ................................................................... 43-21
STXD—Serial Transmit Data.............................................................................. 43-21
Internal I/O Signal Description................................................................................ 43-25
Memory Map and Register Definition ......................................................................... 43-27
R/WSSI Memory Map ............................................................................................. 43-27
Register Summary.................................................................................................... 43-28
Register Descriptions ............................................................................................... 43-32
SSI Transmit Data Registers 0 and 1 (STX0/1)................................................... 43-33
SSI Transmit FIFO 0 and 1 Registers .................................................................. 43-33
SSI Transmit Shift Register (TXSR) ................................................................... 43-34
SSI Receive Data Registers 0 and 1 (SRX0/1) .................................................... 43-36
SSI Receive FIFO 0 and 1 Registers.................................................................... 43-36
SSI Receive Shift Register (RXSR)..................................................................... 43-37
SSI Control Register (SCR)................................................................................. 43-39
SSI Interrupt Status Register (SISR) ................................................................... 43-41
SSI Interrupt Enable Register (SIER).................................................................. 43-46
SSI Transmit Configuration Register (STCR) ..................................................... 43-47
SSI Receive Configuration Register (SRCR) ...................................................... 43-49
SSI Transmit and Receive Clock Control Registers (
STCCR and SRCCR)....................................................................................... 43-51
SSI FIFO Control/Status Register (SFCSR)........................................................ 43-53
SSI Test Register (STR)....................................................................................... 43-56
SSI Option Register (SOR).................................................................................. 43-57
SSI AC97 Control Register (SACNT) ................................................................. 43-58
SSI AC97 Command Address Register (SACADD) ........................................... 43-60
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
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Contents
Paragraph
Number
42.3.3.18
42.3.3.19
42.3.3.20
42.3.3.21
42.3.3.22
42.3.3.23
42.3.3.24
42.4
42.4.1
42.4.2
42.4.2.1
42.4.2.2
42.4.3
42.4.4
42.4.5
42.4.5.1
42.4.5.2
42.4.5.3
42.5
Title
Page
Number
SSI AC97 Command Data Register (SACDAT).................................................. 43-61
SSI AC97 Tag Register (SATAG) ........................................................................ 43-62
SSI Transmit Time Slot Mask Register (STMSK) .............................................. 43-63
SSI Receive Time Slot Mask Register (SRMSK)................................................ 43-64
SSI AC97 Channel Status Register (SACCST) ................................................... 43-65
SSI AC97 Channel Enable Register (SACCEN) ................................................. 43-66
SSI AC97 Channel Disable Register (SACCDIS) ............................................... 43-67
Functional Description................................................................................................. 43-67
SSI Architecture....................................................................................................... 43-67
SSI Clocking ............................................................................................................ 43-67
SSI Clock and Frame Sync Generation ............................................................... 43-68
DIV2, PSR and PM Bit Description .................................................................... 43-69
Receive Interrupt Enable Bit Description ................................................................ 43-72
Transmit Interrupt Enable Bit Description .............................................................. 43-72
IP Bus Interface ....................................................................................................... 43-73
Transfer Lengths Supported................................................................................. 43-73
Transfer Bus Errors.............................................................................................. 43-73
Clock Rate ........................................................................................................... 43-73
Initialization/Application Information ......................................................................... 43-73
Chapter 43
Liquid Crystal Display Controller (LCDC)
43.1
43.2
43.2.1
43.2.2
43.2.3
43.2.4
43.2.5
43.2.6
43.2.7
43.2.8
43.2.9
43.2.9.1
43.2.9.2
43.2.9.3
43.2.10
43.2.10.1
43.2.10.2
43.3
Features .......................................................................................................................... 44-1
Overview........................................................................................................................ 44-3
LCD Screen Format ................................................................................................... 44-3
Graphic Window on Screen ....................................................................................... 44-4
Panning ...................................................................................................................... 44-5
Display Data Mapping ............................................................................................... 44-5
Black-and-White Operation....................................................................................... 44-7
Gray-Scale Operation ................................................................................................ 44-7
Color Generation........................................................................................................ 44-8
Frame Rate Modulation Control (FRC)..................................................................... 44-9
Panel Interface Signals and Timing ......................................................................... 44-10
Pin Configuration for LCDC ............................................................................... 44-11
Passive Matrix Panel Interface Signals................................................................ 44-11
Passive Panel Interface Timing............................................................................ 44-13
8 bpp Mode Color STN Panel.................................................................................. 44-13
Active Matrix Panel Interface Signals ................................................................. 44-14
Active Panel Interface Timing ............................................................................. 44-17
Memory Map and Register Definitions ....................................................................... 44-18
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Contents
Paragraph
Number
43.3.1
43.3.2
43.3.3
43.3.4
43.3.5
43.3.6
43.3.7
43.3.8
43.3.9
43.3.10
43.3.11
43.3.12
43.3.13
43.3.14
43.3.15
43.3.16
43.3.17
43.3.18
43.3.19
43.3.20
43.3.21
43.3.22
43.3.23
43.3.24
43.3.25
43.3.26
43.3.27
43.3.28
43.3.28.1
43.3.28.2
43.3.28.3
43.3.28.4
43.3.28.5
Title
Page
Number
Register Summary.................................................................................................... 44-19
LCDC Screen Start Address Register (LSSAR)...................................................... 44-23
LCDC Size Register (LSR)...................................................................................... 44-24
LCDC Virtual Page Width Register (LVPWR)........................................................ 44-25
LCDC Cursor Position Register (LCPR)................................................................. 44-25
LCDC Cursor Width Height and Blink Register (LCWHB) ................................... 44-26
LCDC Color Cursor Mapping Register (LCCMR) ................................................. 44-27
LCDC Panel Configuration Register (LPCR).......................................................... 44-28
LCDC Horizontal Configuration Register (LHCR)................................................. 44-31
LCDC Vertical Configuration Register (LVCR)...................................................... 44-32
LCDC Panning Offset Register (LPOR).................................................................. 44-33
LCDC Sharp Configuration Register (LSCR) ........................................................ 44-34
LCDC PWM Contrast Control Register (LPCCR).................................................. 44-36
LCDC DMA Control Register (LDCR)................................................................... 44-37
LCDC Refresh Mode Control Register (LRMCR).................................................. 44-38
LCDC Interrupt Configuration Register (LICR) ..................................................... 44-39
LCDC Interrupt Enable Register (LIER)................................................................. 44-40
LCDC Interrupt Status Register (LISR) .................................................................. 44-41
LCDC Graphic Window Start Address Register (LGWSAR) ................................. 44-42
LCDC Graphic Window Size Register (LGWSR)................................................... 44-43
LCDC Graphic Window Virtual Page Width Register (LGWVPWR) .................... 44-44
LCDC Graphic Window Panning Offset Register (LGWPOR)............................... 44-44
LCDC Graphic Window Position Register (LGWPR) ............................................ 44-45
LCDC Graphic Window Control Register (LGWCR)............................................. 44-46
LCDC Graphic Window DMA Control Register (LGWDCR)............................... 44-47
LCDC AUS Mode Control Register (LAUSCR) ..................................................... 44-48
LCDC AUS Mode Cursor Control Register (LAUSCCR) ...................................... 44-49
BGLUT and GWLUT.............................................................................................. 44-49
Four Bits Per Pixel Gray-Scale Mode.................................................................. 44-50
Four Bits Per Pixel Passive Matrix Color Mode.................................................. 44-50
Eight Bits Per Pixel Passive Matrix Color Mode................................................. 44-51
Four Bits Per Pixel Active Matrix Color Mode ................................................... 44-51
Eight Bits Per Pixel Active Matrix Color Mode.................................................. 44-51
Chapter 44
Smart Liquid Crystal Display Controller (SLCDC)
44.1
44.2
44.2.1
44.2.2
SLCDC Module Pin List................................................................................................ 45-1
Functional Description................................................................................................... 45-2
Word Size Definition ................................................................................................. 45-3
Image Endianness ...................................................................................................... 45-3
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
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Contents
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Number
44.2.3
44.2.3.1
44.2.3.1.1
44.2.3.1.2
44.2.3.1.3
44.2.3.2
44.2.4
44.2.5
44.2.6
44.2.7
44.2.8
44.2.9
44.2.10
44.2.11
44.2.12
44.2.13
44.2.14
44.2.15
44.2.16
44.2.17
44.2.18
44.2.19
44.3
44.3.1
44.3.2
44.4
44.5
Title
Page
Number
Accessing the LCD Controller................................................................................... 45-3
Automatic SLCDC Transfers................................................................................. 45-4
Automatic Display Data Transfers (AUTOMODE[1:0]=10) ............................ 45-4
Automatic Command Data Transfers (AUTOMODE[1:0]=00)...................... 45-13
Automatic Command Data Transfers (AUTOMODE[1:0]=01)...................... 45-13
Direct Register Access......................................................................................... 45-14
Aborting SLCDC Transfers ..................................................................................... 45-14
Low-Power Mode Operation ................................................................................... 45-14
Memory Map ........................................................................................................... 45-14
Register Summary.................................................................................................... 45-15
SLDC Register Descriptions.................................................................................... 45-16
Data Buffer Base Address Register (DATABASEADR) ......................................... 45-18
Data Buffer Size Register (DATABUFSIZE) .......................................................... 45-18
Command Buffer Base Address Register (COMBASEADR) ................................. 45-19
Command Buffer Size Register (COMBUFSIZ)..................................................... 45-19
Command String Size Register (COMSTRINGSIZ)............................................... 45-20
FIFO Configuration Register (FIFOCONFIG)........................................................ 45-21
LCD Controller Configuration Register (LCDCONFIG)........................................ 45-21
LCD Transfer Configuration Register (LCDTRANSCONFIG).............................. 45-22
SLCDC Control/Status Register (SLCDCCONTROL/STATUS) ........................... 45-23
LCD Clock Configuration Register (LCDCLOCKCONFIG) ................................. 45-26
LCD Write Data Register (LCDWRITEDATA) ...................................................... 45-26
LCD Controller Interface............................................................................................. 45-27
Serial Interface......................................................................................................... 45-27
Parallel Interface ...................................................................................................... 45-29
LCD Clock Configuration............................................................................................ 45-30
R-AHB Interface and SLCDC FIFOs .......................................................................... 45-31
Appendix A
Revision History
A.1
Changes From Revision 02. to Revision 0.3................................................................... A-1
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Figures
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1-1
1-2
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1-7
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4-15
Title
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Number
Figures
i.MX27 Processor Functional Block Diagram ........................................................................ 1-2
i.MX27 Connectivity Example ............................................................................................... 1-9
Video Codec Architecture Diagram ...................................................................................... 1-18
eMMA_lt Architecture.......................................................................................................... 1-20
Pre-Processor Data Flow....................................................................................................... 1-20
Post-Processor ....................................................................................................................... 1-21
Typical AUDMUX Application ............................................................................................ 1-22
Detailed Block Diagram for the i.MX27 Processor ................................................................ 2-2
i.MX27 Processor’s Physical Memory Map (4 Gbytes) ......................................................... 2-5
i.MX27 Clock Distribution Block Diagram (1 of 2)............................................................... 3-2
i.MX27 Clock Distribution Block Diagram (2 of 2)............................................................... 3-3
Key to Register Fields ............................................................................................................. 3-9
Clock Source Control Register (CSCR)................................................................................ 3-10
MPLL Control Register 0 (MPCTL0)................................................................................... 3-13
MCU and System PLL Control Register 1 (MPCTL1) ........................................................ 3-15
SPLL Control Register 0 (SPCTL0) ..................................................................................... 3-17
SPLL Control Register 1 (SPCTL1) ..................................................................................... 3-19
Oscillator 26M Control Register (OSC26MCTL) ................................................................ 3-20
Peripheral Clock Divider Register 0 (PCDR0) ..................................................................... 3-21
Peripheral Clock Divider Register 1(PCDR1) ...................................................................... 3-23
Peripheral Clock Control Register 0 (PCCR0) ..................................................................... 3-25
Peripheral Clock Control Register 1(PCCR1) ...................................................................... 3-28
Clock Control Status Register (CCSR) ................................................................................. 3-31
Wakeup Guard Mode Control Register (WKGDCTL) ......................................................... 3-33
Reset Module Clock Diagram............................................................................................... 3-34
DRAM and Internal Reset Timing Diagram ......................................................................... 3-36
Key to Register Fields ............................................................................................................. 4-2
Chip ID Register (CID)........................................................................................................... 4-3
Function Multiplexing Control Register (FMCR) .................................................................. 4-4
Global Peripheral Control Register (GPCR)........................................................................... 4-7
Well Bias Control Register (WBCR) ...................................................................................... 4-9
Drive Strength Control Register (DSCR1)............................................................................ 4-11
Drive Strength Control Register 2 (DSCR2)......................................................................... 4-13
Drive Strength Control Register 3 (DSCR3)......................................................................... 4-15
Drive Strength Control Register 4 (DSCR4)......................................................................... 4-17
Drive Strength Control Register 5 (DSCR5)......................................................................... 4-19
Drive Strength Control Register 6 (DSCR6)......................................................................... 4-21
Drive Strength Control Register 7 (DSCR7)......................................................................... 4-24
Drive Strength Control Register 8 (DSCR8)......................................................................... 4-26
Drive Strength Control Register 9 (DSCR9)......................................................................... 4-28
Drive Strength Control Register 10 (DSCR10)..................................................................... 4-31
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
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Figures
Figure
Number
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
6-1
6-2
6-3
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6-27
7-1
7-2
7-3
Title
Page
Number
Drive Strength Control Register 11 (DSCR11)..................................................................... 4-33
Drive Strength Control Register 12 (DSCR12)..................................................................... 4-35
Drive Strength Control Register 13 (DSCR13)..................................................................... 4-37
Pull Strength Control Register (PSCR)................................................................................. 4-39
Priority Control and Select Register (PCSR) ........................................................................ 4-41
Power Management Control Register (PMCR) .................................................................... 4-42
DPTC Comparator Value Register 0 (DCVR0) .................................................................... 4-44
DPTC Comparator Value Register 1 (DCVR1) .................................................................... 4-44
DPTC Comparator Value Register 2 (DCVR2) .................................................................... 4-45
DPTC Comparator Value Register 3 (DCVR3) .................................................................... 4-46
PMIC Pad Control Register (PPCR) ..................................................................................... 4-46
Functional Block Diagram of GPIO ....................................................................................... 6-2
GPIO Block Diagram for an Individual Port .......................................................................... 6-3
Key to Register Fields ............................................................................................................. 6-8
Data Direction Register (PTn_DDIR)..................................................................................... 6-9
Output Configuration Register 1 (OCR1) ............................................................................. 6-10
Output Configuration Register 2 (OCR2) ............................................................................. 6-11
Input Configuration Register A1 (ICONFA1) ...................................................................... 6-12
Input Configuration Register A2 (ICONFA2) ...................................................................... 6-13
Input Configuration Register B1 (ICONFB1)....................................................................... 6-14
Input Configuration Register B1 (ICONFB2)....................................................................... 6-15
Data Register (DR)................................................................................................................ 6-16
GPIO IN USE Register (GIUS) ............................................................................................ 6-17
GPIO IN USE Register A Reset Values (PTA_GIUS).......................................................... 6-18
GPIO IN USE Register B Reset Values (PTB_GIUS).......................................................... 6-18
GPIO IN USE Register C Reset Values (PTC_GIUS).......................................................... 6-19
GPIO IN USE Register D Reset Values (PTD_GIUS) ......................................................... 6-19
GPIO IN USE Register E Reset Values (PTE_GIUS) .......................................................... 6-20
GPIO IN USE Register F Reset Values (PTF_GIUS)........................................................... 6-20
Sample Status Register (SSR)............................................................................................... 6-21
Interrupt Configuration Register 1 (ICR1)............................................................................ 6-22
Interrupt Configuration Register 2 (ICR2)............................................................................ 6-23
Interrupt Mask Register (IMR) ............................................................................................. 6-24
Interrupt Status Register (ISR).............................................................................................. 6-25
General Purpose Register...................................................................................................... 6-26
Software Reset Register (SWR)............................................................................................ 6-27
Pull-Up Enable Register (PUEN).......................................................................................... 6-28
Port Interrupt Mask Register (PMASK) ............................................................................... 6-29
JTAG Signals Timing Diagram ............................................................................................... 7-1
i.MX27 JTAG Block Diagram ................................................................................................ 7-3
ID Register Configuration....................................................................................................... 7-5
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Figures
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Number
8-1
8-2
8-3
8-4
8-5
9-1
9-2
9-3
9-4
9-5
9-6
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10-1
10-2
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10-16
10-17
10-18
10-19
10-20
10-21
10-22
10-23
Title
Page
Number
Flow Diagram for Bootstrap Mode ......................................................................................... 8-2
iROM Status Command .......................................................................................................... 8-3
Write Register Command........................................................................................................ 8-3
Download Command .............................................................................................................. 8-4
Bootstrap End Indication Operation Diagram ........................................................................ 8-5
ARM9 Platform Block Diagram ........................................................................................... 10-2
ARM9 Platform Hierarchy.................................................................................................... 10-9
AHB Clock Relationship .................................................................................................... 10-13
Example hclk to clk Synchronization when clk is Faster ................................................... 10-14
ARM9 Platform Resets ....................................................................................................... 10-15
ARM9 Platform Clocking Strategy..................................................................................... 10-17
Example of Two External Masters Connected to an ABM Port ......................................... 10-20
The Primary AHB ............................................................................................................... 10-23
Endian Configuration Routing ............................................................................................ 10-25
ARM9 Platform AHB Clock and Reset Timing Relationship ............................................ 10-40
Alternate Bus Master Timing Parameters ........................................................................... 10-41
Secondary AHB AC TIming Parameters ............................................................................ 10-43
RAM and ROM Interface AC Timing Parameters .............................................................. 10-45
AITC Block Diagram............................................................................................................ 11-1
Key to Register Fields ........................................................................................................... 11-4
Interrupt Control Register Format......................................................................................... 11-8
Normal Interrupt Mask Register Format............................................................................. 11-10
Interrupt Enable Number Register Format.......................................................................... 11-11
Interrupt Enable Number Register Format.......................................................................... 11-12
Interrupt Enable Register High Format............................................................................... 11-13
Interrupt Enable Register Low Format................................................................................ 11-13
Interrupt Type Register High Format .................................................................................. 11-14
Interrupt Type Register Low Format................................................................................... 11-14
Normal Interrupt Priority Level 7 Register Format............................................................. 11-15
Normal Interrupt Priority Level 6 Register Format............................................................. 11-16
Normal Interrupt Priority Level 5 Register Format............................................................. 11-17
Normal Interrupt Priority Level 4 Register Format............................................................. 11-18
Normal Interrupt Priority Level 3 Register Format............................................................. 11-19
Normal Interrupt Priority Level 2 Register Format............................................................. 11-20
Normal Interrupt Priority Level 1 Register Format............................................................. 11-21
Normal Interrupt Priority Level 1 Register Format............................................................. 11-22
Normal Interrupt Vector and Status Register Format.......................................................... 11-23
Fast Interrupt Vector and Status Register Format ............................................................... 11-24
Interrupt Source Register High Format............................................................................... 11-25
Interrupt Source Register High Format............................................................................... 11-25
Interrupt Force Register Format.......................................................................................... 11-29
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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10-24
11-1
13-1
13-2
15-1
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17-4
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Fast Interrupt Pending Register High and Low Format ...................................................... 11-31
Security Controller Block Diagram ...................................................................................... 12-1
RTIC Block Diagram ............................................................................................................ 14-1
System Diagram .................................................................................................................... 14-2
M3IF System Block Diagram ............................................................................................... 16-2
PCMCIA Host Adapter Simplified Block Diagram.............................................................. 16-4
NAND Flash Controller Simplified Block Diagram............................................................. 16-6
EMI AHB MUX Interface Diagram ..................................................................................... 16-9
EMI I/O MUX Interface Diagram....................................................................................... 16-10
M3IF Block Diagram—System Overview............................................................................ 17-2
Key to Register Fields ........................................................................................................... 17-7
M3IF Control Register ........................................................................................................ 17-10
M3IF Snooping Configuration Register 0 (M3IFSCFG0).................................................. 17-12
M3IF Snooping Configuration Register 1 (M3IFSCFG1).................................................. 17-13
M3IF Snooping Configuration Register 2 (M3IFSCFG2).................................................. 17-14
M3IF Snooping Status Register 0 (M3IFSSR0) ................................................................. 17-15
M3IF Snooping Status Register 1 (M3IFSSR1) ................................................................. 17-16
M3IF Lock General Register (M3IFMLGE) ...................................................................... 17-17
Master Port Gasket (MPG) Interface Diagram ................................................................... 17-20
MPG Simple Transfer ......................................................................................................... 17-23
MPG with Wait States......................................................................................................... 17-24
MPG Multiple Transfers ..................................................................................................... 17-24
MPG—Transfer Type Examples ......................................................................................... 17-25
MPG Four Beat Wrapping Burst......................................................................................... 17-27
MPG Four Beat Incrementing Burst ................................................................................... 17-27
MPG Undefined Length Bursts........................................................................................... 17-28
MPG64 Port Interface Diagram .......................................................................................... 17-30
MPG64 Simple Double Word Transfer............................................................................... 17-31
MPG64—8 Beat Incremental Burst of Double Words to 32-bit SDRAM.......................... 17-32
M3A Block Diagram........................................................................................................... 17-34
M3A Simple Transfer Timing Diagram.............................................................................. 17-35
M3A—Round Robin Token Chain—Equal Priority........................................................... 17-36
M3A—Round Robin Token Chain—Masters 1 and 4 has 50% Priority ............................ 17-36
MAB Overview Block Diagram ......................................................................................... 17-38
MAB Arbitration Process Timing Diagram ........................................................................ 17-39
MAB Multi-Master Request Time Diagram ....................................................................... 17-40
M3IF System Example........................................................................................................ 17-42
WEIM Block Diagram .......................................................................................................... 18-2
Key to Register Fields ........................................................................................................... 18-9
Chip Select x Upper Control Register................................................................................. 18-13
Chip Select x Lower Control Register ................................................................................ 18-17
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Title
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Chip Select x Addition Control Register ............................................................................ 18-20
WCR Register ..................................................................................................................... 18-23
Read Access, WSC=1 ......................................................................................................... 18-32
Write Access, WSC=1, EBWA=1, EBWN=1, LBN=1 ...................................................... 18-33
Read and Write Accesses, WSC=2, WWS=2, EBWA=1, EBWN=2 ................................. 18-34
Read and Write Accesses, WSC=2, WWS=1, EBWA=1, EBWN=2, EDC=1 ................... 18-35
Read and Write Accesses, WSC=3, CSA=1, CSN=1, LBA=1, LBN=1............................. 18-36
Read Accesses, WSC=2, OEA=2, CNC=2, BCM=1, EBRA=2......................................... 18-37
Read and Write Accesses, WSC=2, OEA=2, EBWA=1, EBWN=2,
CNC=2, EBRA=2 .......................................................................................................... 18-38
Read Access, WSC=1, OEA=1, EBRA=1.......................................................................... 18-39
Write Access, WSC=1, EBWA=1, EBWN=1..................................................................... 18-40
Read Access, WSC=3, OEA=2, EBRA=2.......................................................................... 18-41
Write Access, WSC=3, EBWA=1, EBWN=3..................................................................... 18-42
Read Access, WSC=3, OEA=4, EBRA=4.......................................................................... 18-43
Write Access, WSC=3, EBWA2, EBWN=3 ....................................................................... 18-44
Read Access, WSC=3, OEN=2, EBRN=2.......................................................................... 18-45
Read Access, WSC=3, OEA=2, OEN=2, EBRA=2, EBRN=2 .......................................... 18-46
Write Access, WSC=2, WWS=1, EBWA=1, EBWN=2..................................................... 18-47
Write Access, WSC=1, WWS=2, EBWA=1, EBWN=2..................................................... 18-48
Write Access, WSC=2, CSA=1, WWS=1, CSN=1 ............................................................ 18-49
Sequential Read Access, WSC=7, OEA=8, PME=1, SYNC=1, DOL=1,
EBRA=8 ......................................................................................................................... 18-50
Read Access, WSC=3F, OEA=8, OEN=5, EBRA=8, EBRN=5......................................... 18-51
Sequential Read Accesses, WSC=1, EW=1, DCT=1 ......................................................... 18-52
Sequential Write Accesses, WSC=1, EW=1, RWA=1, RWN=1 ........................................ 18-53
Non-sequential Read Accesses, WSC=2, SYNC=1, DOL=0 ............................................. 18-54
Sequential Read Access, WSC=7, OEA=8, SYNC=1, DOL=1, BCD=1, BCS=1,
EBRA=8 ......................................................................................................................... 18-55
Non-sequential Read Accesses, WSC=3, SYNC=1, DOL=1 ............................................. 18-56
Increment 4 AHB Read Access, WSC=2, SYNC=1, DOL=1, WRAP=0 .......................... 18-57
Increment 4 AHB Read Access, WSC=2, SYNC=1, DOL=1, WRAP=0 .......................... 18-58
Increment 4 AHB Read Access, WSC=3, SYNC=1, DOL=1, WRAP=0,
EW=0 ............................................................................................................................. 18-59
Increment 4 AHB Read Access, WSC=3, SYNC=1, DOL=1, WRAP=0,
EW=1 ............................................................................................................................. 18-60
Increment 4 AHB Read Access, WSC=3, SYNC=1, WRAP=0, EW=1 ............................ 18-61
Increment 4 AHB Read Access, WSC=2, SYNC=1, DOL=1, WRAP=1,
PSZ=0............................................................................................................................. 18-62
Wrap 4 AHB Read Access, WSC=2, SYNC=1, DOL=1, WRAP=0.................................. 18-63
Wrap 4 AHB Read Access, WSC=2, SYNC=1, DOL=1, WRAP=1, PSZ=0..................... 18-64
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
liii
Figures
Figure
Number
17-40
17-41
17-42
17-43
17-44
17-45
17-46
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
18-15
18-16
18-17
18-18
18-19
18-20
18-21
18-22
18-23
18-24
18-25
18-26
18-27
18-28
18-29
18-30
18-31
18-32
18-33
18-34
Title
Page
Number
Write Access, BCD=1, BCS=1, WSC=5, SYNC=1, DOL=1, EW=1, PSR=1................... 18-65
Read Access, BCD=1, BCS=1, WSC=5, SYNC=1, DOL=1, EW=1, PSR=1.................... 18-66
Write Access, BCS=1, WSC=4, SYNC=1, PSR=1 ............................................................ 18-67
Read Access, WSC=7, LBA=1, LBN=1, LAH=1, OEA=7................................................ 18-68
Write Access, WSC=7, LBA=1, LBN=1, LAH=1 ............................................................. 18-69
Read Access, BCD=1, SYNC=1, WCS=4, DOL=1, LBN=2, LAH=1, PSR=1 ................. 18-70
Write Access, BCD=1, SYNC=1, WCS=5, DOL=1, LBN=2, LAH=1, PSR=1 ................ 18-71
Enhanced SDR/LPDDR SDRAM Controller Block Diagram.............................................. 19-2
Key to Register Fields ......................................................................................................... 19-10
Data Organization in Memory ............................................................................................ 19-13
Enhanced SDRAM Control Register (ESDCTL0) ............................................................. 19-14
Enhanced SDRAM Control Register (ESDCTL1) ............................................................. 19-14
Enhanced SDRAM Configuration Register 0 (ESDCFG0) ................................................ 19-18
Enhanced SDRAM Configuration Register 1 (ESDCFG1) ................................................ 19-19
tRP—Precharge Delay Timing............................................................................................ 19-23
tWTRtRP Bit Field Encoding ............................................................................................. 19-24
tMRD—SDRAM Load Mode Register to Active Command Timing Diagram ................. 19-24
tWR—WRITE to PRECHARGE Timing Diagram ............................................................ 19-25
tRAS—SDRAM ACTIVE to PRECHARGE Command Timing Diagram ........................ 19-25
tRAS—SELF REFRESH Mode Minimum Time Period.................................................... 19-26
tRRD—Alternating Bank Read Access .............................................................................. 19-26
SDR CAS Latency Timing.................................................................................................. 19-27
Mobile LPDDR CAS Latency Timing................................................................................ 19-28
tRCD—Row to Column Delay Timing............................................................................... 19-29
tRC—Row Cycle Timing.................................................................................................... 19-30
tXP—New Command After Power Down Exit (4 Cycles) ................................................. 19-31
ESDRAMC Miscellaneous Register (ESDMISC) .............................................................. 19-31
MDDR Delay Line 1 Configuration Debug Register.......................................................... 19-33
MDDR Delay Line 2 Configuration Debug Register.......................................................... 19-33
MDDR Delay Line 3 Configuration Debug Register.......................................................... 19-34
MDDR Delay Line 4 Configuration Debug Register.......................................................... 19-34
MDDR Delay Line 5 Configuration Debug Register.......................................................... 19-35
MDDR Delay Line Cycle Length Debug Register ............................................................. 19-35
SDR SDRAM Read Burst Command Sequence Example.................................................. 19-37
LPDDR SDRAM Read Burst Command Sequence Example ............................................ 19-38
SDR SDRAM Optimization Strategies—MIF1 and MIF2 Examples ................................ 19-40
Mobile LPDDR SDRAM Optimization Strategies—MIF1 and MIF2 Examples .............. 19-41
SDR Simple Read after Read Latency Hiding Timing Diagram ........................................ 19-42
Mobile DDR Simple Read after Read Latency Hiding Timing Diagram ........................... 19-43
SDR Miss Write to CSD1 after Read from CSD0 .............................................................. 19-43
Mobile DDR Miss Write to CSD1 after Read from CSD0................................................. 19-44
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
liv
Freescale Semiconductor
Figures
Figure
Number
18-35
18-36
18-37
18-38
18-39
18-40
18-41
18-42
18-43
18-44
18-45
18-46
18-47
18-48
18-49
18-50
18-51
18-52
18-53
18-54
18-55
18-56
18-57
18-58
18-59
18-60
18-61
18-62
Title
Page
Number
Hardware Refresh Timing Diagram.................................................................................... 19-48
Hardware Refresh with Pending Bus Cycle Timing Diagram ............................................ 19-48
SDRAM/LPDDR Enter Self Refresh Mode During System Sleep Mode .......................... 19-50
SDRAM/LPDDR Exit Self Refresh Mode During System Sleep Mode ............................ 19-51
Manual Self Refresh Entry Timing Diagram ...................................................................... 19-52
Manual Self Refresh Exit Timing Diagram ........................................................................ 19-53
SDR SDRAM Precharge Power Down Mode Entry Timing Diagram ............................... 19-54
SDR SDRAM Precharge Power Down Mode Exit Timing Diagram ................................. 19-55
Mobile DDR SDRAM Precharge Power Down Mode Entry Timing Diagram .................. 19-56
Mobile DDR SDRAM Precharge Power Down Mode Exit Timing Diagram .................... 19-57
SDR SDRAM Active Power Down Mode Timing Diagram .............................................. 19-58
Mobile DDR SDRAM Active Power Down Mode Timing Diagram ................................. 19-59
Simplified Enhanced SDRAM Controller State Diagram .................................................. 19-62
SDR and LPDDR Off-Page Single Read Timing Diagram
(32-Bit Memory for SDR and 16-Bit for LPDDR) ........................................................ 19-64
SDR and LPDDR On-Page Single Read Timing Diagram
(32-Bit Memory for SDR, 16-Bit for LPDDR).............................................................. 19-65
SDR and LPDDR Off-Page Burst Read Timing Diagram
(32-Bit Memory for SDR or 16-Bit for LPDDR) .......................................................... 19-66
AHB 32-Bit read from a LPDDR: Off-Page Burst Read Timing Diagram
(32-Bit) ........................................................................................................................... 19-67
AHB 64-Bit read from a LPDDR: Off-Page Burst Read Timing Diagram
(32-Bit) ........................................................................................................................... 19-68
SDR and LPDDR On-Page Burst Read Timing Diagram
(32-Bit Memory for SDR and 16-Bit for LPDDR) ........................................................ 19-69
On-Page Burst Read Timing Diagram (16-Bit Memory for SDR, LPDDR 8-Bit Is Not
Supported) ...................................................................................................................... 19-70
Off-Page Burst Read Timing Diagram
(16-Bit Memory, LPDDR 8-Bit Is Not Supported)........................................................ 19-70
SDR Off-Page Write Followed by On-Page Write Timing Diagram.................................. 19-71
LPDDR Off-Page Write Followed by On-Page Write Timing Diagram ............................ 19-72
Off-Page Burst Write Timing Diagram (32-Bit Memory for SDR and
16-Bit for LPDDR)......................................................................................................... 19-73
AHB 64-Bit Write to LPDDR: Off-Page Burst Write Timing Diagram
(32-Bit Memory) ............................................................................................................ 19-74
AHB 32-Bit write to LPDDR: Off-Page Burst Write Timing Diagram
(32-Bit Memory) ............................................................................................................ 19-75
On-Page Burst Write Timing Diagram (32-Bit Memory for SDR and
16-Bit for LPDDR)......................................................................................................... 19-76
Off-Page Burst Write Timing Diagram (SDR 16-bit Memory, LPDDR
8-Bit is Not Supported) .................................................................................................. 19-77
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
lv
Figures
Figure
Number
18-63
18-64
18-65
18-66
18-67
18-68
18-69
18-70
18-71
18-72
18-73
18-74
18-75
18-76
18-77
18-78
18-79
18-80
18-81
18-82
18-83
18-84
18-85
18-86
18-87
18-88
18-89
18-90
18-91
18-92
18-93
18-94
18-95
18-96
18-97
18-98
19-1
19-2
19-3
19-4
Title
Page
Number
On-Page Burst Write Timing Diagram
(SDR 16-Bit Memory, LPDDR 8-Bit Memory is Not Supported) ................................ 19-78
SDR Single Write followed by On-Page Read Timing Diagram........................................ 19-79
LPDDR Single Write Followed by On-Page Read Timing Diagram.................................. 19-80
SDR Single Read Followed by On-Page Write Timing Diagram ....................................... 19-81
LPDDR Single Read Followed by On-Page Write Timing Diagram.................................. 19-82
SDR Burst Read Followed by On-Page Write Timing Diagram ........................................ 19-83
LPDDR Burst Read Followed by On-Page Write Timing Diagram ................................... 19-84
Single on Page Read—Word Access to 16-Bit Memory (Cycle Accurate)........................ 19-85
Misaligned on Page INCR4 Burst Read Access to 16-Bit Memory ................................... 19-86
Misaligned WRAP8 Burst Read Access to 32-Bit Memory............................................... 19-88
Single on Page Write—Word Access to 32-Bit Memory (Cycle Accurate) ....................... 19-89
INCR4 Burst on Page Write—Word Access to 32-Bit Memory (Cycle Accurate) ............ 19-90
Precharge Specific Bank Timing Diagram.......................................................................... 19-92
Precharge All Banks Timing Diagram ................................................................................ 19-93
Software Initiated Auto-Refresh Timing Diagram.............................................................. 19-94
Set Mode Register State Diagram ....................................................................................... 19-95
SDR and LPDDR Set Mode Register Timing Diagram...................................................... 19-95
SDR SDRAM Initialization and Load Mode Register Sequence ....................................... 19-97
Simplified LPDDR SDRAM Initialization and Load Mode Register Sequence ................ 19-99
128 Mbit SDR SDRAM Mode Register ........................................................................... 19-100
Single 64 Mb (4M x 16) SDRAM Connection Diagram .................................................. 19-102
Single 128 Mb (8M x 16) SDRAM Connection Diagram ................................................ 19-103
Single 256 Mb (16M x 16) Connection Diagram ............................................................. 19-104
Single 512 Mb (32M x 16) SDRAM Connection Diagram .............................................. 19-105
Single 1-Gb (64M x 16) SDRAM Connection Diagram .................................................. 19-106
Dual 64 Mb (4M x 16 x 2) SDRAM Connection Diagram .............................................. 19-107
Dual 128 Mb (8M x 16 x 2) SDRAM Connection Diagram ............................................ 19-108
Dual 256-Mbyte (16M x 16 x 2) SDRAM Connection Diagram ..................................... 19-109
Single 64-Mbyte (2MBx32) SDRAM Connection Diagram ............................................ 19-110
Single 128-Mb (4MBx32) SDRAM Connection Diagram ............................................... 19-111
Single 256-MB (8MBx32) SDRAM Connection Diagram .............................................. 19-112
Single 512-Mb (16MBx32) SDRAM Connection Diagram ............................................. 19-113
Single 1-Gb (32MBx32) SDRAM Connection Diagram.................................................. 19-114
Single 2-Gb (64MBx32) SDRAM Connection Diagram.................................................. 19-115
Single 512-Mb (16MBx32) LPDDR SDRAM Connection Diagram ............................... 19-116
Single 512-Mb (32MBx16) LPDDR SDRAM Connection Diagram ............................... 19-117
NAND FLASH Controller Block Diagram........................................................................... 20-1
Warm Reset Operation .......................................................................................................... 20-5
Key to Register Fields ........................................................................................................... 20-8
NFC_BUFSIZE Register ...................................................................................................... 20-9
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
lvi
Freescale Semiconductor
Figures
Figure
Number
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
19-15
19-16
19-17
19-18
19-19
19-20
19-21
19-22
19-23
19-24
19-25
19-26
19-27
19-28
19-29
19-30
19-31
19-32
19-33
19-34
19-35
19-36
19-37
19-38
19-39
19-40
19-41
20-1
20-2
20-3
20-4
Title
Page
Number
RAM Buffer Address Register............................................................................................ 20-10
NAND Flash Address Register ........................................................................................... 20-10
NAND_Flash_CMD Register ............................................................................................. 20-11
NFC_Configuration Register .............................................................................................. 20-11
ECC_Status_Result ............................................................................................................. 20-12
ECC_RSLT_MAIN_AREA Register.................................................................................. 20-12
ECC_RSLT_MAIN_AREA Register.................................................................................. 20-13
ECC_Rslt_Spare_Area Register ......................................................................................... 20-14
ECC_Rslt_Spare_Area Register ......................................................................................... 20-14
NAND Flash Write Protection Register.............................................................................. 20-15
Unlock_Start_Blk_Add Register ........................................................................................ 20-15
UNLOCK_END_BLK_ADD Register ............................................................................... 20-16
NAND_FLASH_WR_PR_ST Register .............................................................................. 20-16
NAND_FLASH_CONFIG1 Register ................................................................................. 20-17
NAND_FLASH_CONFIG2 Register ................................................................................. 20-18
Boot Mode Operation.......................................................................................................... 20-21
Read Operation ................................................................................................................... 20-22
Program Operation .............................................................................................................. 20-22
Erase Operation................................................................................................................... 20-23
Flowchart of Preset Operation ............................................................................................ 20-26
Flowchart of NAND Flash Command Input Operation ...................................................... 20-27
Flowchart of NAND Flash Address Input Operation.......................................................... 20-28
Flowchart of NAND Flash Data Input Operation ............................................................... 20-29
Flowchart of NAND Flash Data Output Operation ............................................................ 20-30
Flowchart of Read NAND Flash ID Operation................................................................... 20-31
NAND Flash ID Data Format (x8)...................................................................................... 20-31
NAND Flash ID Data Format (x16).................................................................................... 20-32
Flowchart of Read NAND Flash Status Operation ............................................................. 20-32
NAND Flash Status Data Format........................................................................................ 20-32
Flowchart of Read NAND Flash Data Operation ............................................................... 20-33
Flowchart of Program NAND Flash Data Operation.......................................................... 20-34
Flowchart of Erase NAND Flash Operation ....................................................................... 20-35
Flowchart of Hot Reset Operation ...................................................................................... 20-35
State Diagram of RAM Buffer Write Protection ................................................................ 20-37
State Diagram of NAND Flash Write Protection................................................................ 20-39
256-Mbit (32 Mbit x 8 Bit) NAND Flash Connection Diagram......................................... 20-41
256 Mbit (16 M x 16 Bit) NAND Flash Connection Diagram ........................................... 20-42
PCMCIA Controller Interface Block Diagram ..................................................................... 21-2
Key to Register Fields ........................................................................................................... 21-7
PCMCIA Input Pins Register (PIPR).................................................................................... 21-9
PCMCIA Status Change Register (PSCR).......................................................................... 21-11
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
lvii
Figures
Figure
Number
20-5
20-6
20-7
20-8
20-9
20-10
20-11
20-12
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
21-9
21-10
22-1
22-2
22-3
22-4
22-5
22-6
22-7
22-8
22-9
22-10
22-11
22-12
22-13
22-14
22-15
22-16
23-1
23-2
23-3
23-4
23-5
23-6
23-7
Title
Page
Number
PCMCIA Enable Register (PER) ........................................................................................ 21-12
PCMCIA Base Registers 0–4 (PBR0–PBR4) ..................................................................... 21-14
PCMCIA Option Registers 0–4 (POR0–POR4) ................................................................. 21-15
PCMCIA Offset Registers 0–4 (POFR0–POFR4) .............................................................. 21-18
PCMCIA General Control Register (PGCR) ...................................................................... 21-19
PCMCIA General Status Register (PGSR) ......................................................................... 21-20
Write Accesses PSHT=1, PSST =1..................................................................................... 21-28
Read Cycle PSHT=1, PSST =1........................................................................................... 21-29
1-Wire Connection ................................................................................................................ 22-1
1-Wire Block-Level Description ........................................................................................... 22-2
1-Wire Initialization .............................................................................................................. 22-3
Write 0 Timing ...................................................................................................................... 22-4
Write 1 Timing ...................................................................................................................... 22-4
Read Timing .......................................................................................................................... 22-5
Key to Register Fields ........................................................................................................... 22-5
Control Register .................................................................................................................... 22-7
Time Divider Register ........................................................................................................... 22-9
Reset Register...................................................................................................................... 22-11
ATA Host Controller Block Diagram.................................................................................... 23-1
Key to Register Fields ........................................................................................................... 23-7
ATA TIME_CONFIG0 Register ......................................................................................... 23-11
ATA TIME_CONFIG1 Register ......................................................................................... 23-12
ATA TIME_CONFIG2 Register ......................................................................................... 23-13
ATA TIME_CONFIG3 Register ......................................................................................... 23-14
ATA TIME_CONFIG4 Register ......................................................................................... 23-15
ATA TIME_CONFIG5 Register ......................................................................................... 23-16
ATA FIFO_DATA_32 Register ........................................................................................... 23-17
ATA FIFO_DATA_16 Register ........................................................................................... 23-17
ATA FIFO_FILL Register ................................................................................................... 23-18
ATA_CONTROL Register .................................................................................................. 23-19
ATA INT_PENDING Register............................................................................................ 23-20
ATA INT_ENABLE Register.............................................................................................. 23-21
ATA INT_CLEAR Register ................................................................................................ 23-21
ATA FIFO_ALARM Register ............................................................................................. 23-23
Configurable Serial Peripheral Interface Block Diagram ..................................................... 24-1
Generic CSPI Timing ............................................................................................................ 24-3
Typical SPI Transfer (8-Bit).................................................................................................. 24-4
Relationship between a SPI transfer and the Falling Edge of SPI_RDY.............................. 24-4
Relationship between a SPI Transfer and SPI_RDY ............................................................ 24-5
SPI Transfers with Wait States.............................................................................................. 24-5
SPI continuous transfer with BURST=1............................................................................... 24-6
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
lviii
Freescale Semiconductor
Figures
Figure
Number
23-8
23-9
23-10
23-11
23-12
23-13
23-14
23-15
23-16
23-17
23-18
23-19
23-20
23-21
23-22
24-1
24-2
24-3
24-6
24-7
24-8
24-9
24-10
24-11
24-12
24-13
24-14
24-15
25-1
25-2
25-3
25-4
25-5
25-6
25-7
25-8
25-9
25-10
25-11
25-12
26-1
Title
Page
Number
SPI Transfer while SSCTL is Clear ...................................................................................... 24-6
SPI Transfers while SSCTL is Set ........................................................................................ 24-7
Increment Data FIFO by SS Rising Edge ............................................................................. 24-8
Program Sequence of SPI Burst Using Interrupt .................................................................. 24-9
Program Sequence of SPI Burst Using DMA ....................................................................... 24-9
Flow Chart of CSPI Operation ............................................................................................ 24-10
Key to Register Fields ......................................................................................................... 24-12
RXDATA Register Diagram................................................................................................ 24-15
TXDATA Register Diagram ................................................................................................ 24-16
CSPI Control Register......................................................................................................... 24-17
Interrupt Control Register Diagram .................................................................................... 24-20
Test Control Register Diagram............................................................................................ 24-23
Sample Period Control Register Diagram........................................................................... 24-24
DMA Control Register Diagram ......................................................................................... 24-25
Reset Register Diagram....................................................................................................... 24-27
I2C Block Diagram................................................................................................................ 25-1
Connection of Devices to I2C Bus ........................................................................................ 25-2
Key to Register Fields ........................................................................................................... 25-4
I2C Address Register............................................................................................................. 25-6
I2C Frequency Register ......................................................................................................... 25-6
I2C Control Register.............................................................................................................. 25-8
I2C Status Register ................................................................................................................ 25-9
I2C Data Register ................................................................................................................ 25-10
I2C Standard Communication Protocol............................................................................... 25-12
Repeated START................................................................................................................. 25-13
Synchronized Clock SCL.................................................................................................... 25-14
Flowchart of Typical I2C Interrupt Routine ........................................................................ 25-17
Definition of Timing for Devices on I2C Bus ..................................................................... 25-18
KPP Peripheral Block Diagram ............................................................................................ 26-1
Key to Register Fields ........................................................................................................... 26-3
KPCR Register ...................................................................................................................... 26-5
KPSR Register ...................................................................................................................... 26-6
KDDR Register ..................................................................................................................... 26-8
KPDR Register...................................................................................................................... 26-8
Keypad Synchronizer Functional Diagram ......................................................................... 26-11
Multiple Key Presses on Same Column Line (Simplified View)........................................ 26-12
Multiple Key Presses on Same Row Line (Simplified View) ............................................. 26-12
Decoding Wrong Three-Key Presses .................................................................................. 26-13
Matrix with “Ghost” Key Protections ................................................................................. 26-14
KPP Interface with 3-Point Contact Key Matrix (Simplified View)................................... 26-15
Memory Stick Controller Block Diagram............................................................................. 27-1
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
lix
Figures
Figure
Number
26-2
26-3
26-4
26-5
26-6
27-1
27-2
27-3
27-4
27-5
27-6
27-7
27-8
27-9
27-10
27-11
27-12
27-13
27-14
27-15
27-16
27-17
27-18
27-19
27-20
27-21
27-22
27-23
27-24
27-25
27-26
27-27
27-28
28-1
28-2
28-3
28-4
28-5
28-6
28-7
28-8
Title
Page
Number
MSHC Clock Structure ......................................................................................................... 27-8
Gasket Memory Interface Logic ........................................................................................... 27-9
Basic Read/Write Timing Diagram..................................................................................... 27-10
Back-to-Back Write/Read Timing Diagram ....................................................................... 27-11
Gasket Interrupt Generation................................................................................................ 27-13
Secure Digital Host Controller Block Diagram .................................................................... 28-1
System Interconnection with the Secure Digital Host Controller......................................... 28-2
Key to Register Fields ........................................................................................................... 28-4
SDHC Clock Control Register .............................................................................................. 28-8
SDHC Status Register ......................................................................................................... 28-10
SDHC Clock Rate Register................................................................................................. 28-14
SDHC Command and Data Control Register...................................................................... 28-16
MMC/SD Response Time Out Register.............................................................................. 28-18
SDHC Read Time Out Register .......................................................................................... 28-19
SDHC Block Length Register............................................................................................. 28-20
SDHC Number of Blocks Register ..................................................................................... 28-22
SDHC Revision Number Register....................................................................................... 28-23
SDHC Interrupt Control Register........................................................................................ 28-24
SDHC Command Number Register .................................................................................... 28-28
SDHC Command Argument Register ................................................................................. 28-29
SDHC Response FIFO Register.......................................................................................... 28-30
SDHC Buffer Access Register ............................................................................................ 28-31
SDHC Buffer Scheme ......................................................................................................... 28-32
Byte Lanes Relationship Between System IP Bus and SD Card Bus ................................. 28-33
Example for Dividing Large Data Transfer ........................................................................ 28-35
DMA Interface Block.......................................................................................................... 28-36
Memory Controller Block Diagram .................................................................................... 28-37
a) Card Interrupt Scheme; b) Card Interrupt Detection and Handling Procedure .............. 28-39
Block Diagram for Command Interpreter ........................................................................... 28-42
Command CRC Shift Register (DATs Has Similar Structure) ........................................... 28-42
Clock Used in SDHC .......................................................................................................... 28-44
Flow Diagram for Card Detection....................................................................................... 28-47
Flow Chart for Reset of SDHC and SD I/O Card ............................................................... 28-48
UART Block Diagram........................................................................................................... 29-1
Key to Register Fields ........................................................................................................... 29-5
Key to Register Fields ........................................................................................................... 29-5
UART Receiver Register (URXD)........................................................................................ 29-8
UART Transmitter (UTXD) Register.................................................................................... 29-9
UART Control Register 1 (UCR1)...................................................................................... 29-10
UART Control Register 2 (UCR2) Summary ..................................................................... 29-12
UART Control Register 3 (UCR3) Summary ..................................................................... 29-14
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
lx
Freescale Semiconductor
Figures
Figure
Number
28-9
28-10
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Title
Page
Number
UART Control Register 4 (UCR4) Summary ..................................................................... 29-16
UART FIFO Control Register (UFCR) Summary .............................................................. 29-18
UART Status Register 1 (USR1) Summary ........................................................................ 29-19
UART Status Register 2 (USR2) Summary ........................................................................ 29-21
UART Escape Character Register Summary (UESC)......................................................... 29-23
UART Escape Timer Register Summary (UTIM)............................................................... 29-23
UART BRM Incremental Register Summary (UBIR) ........................................................ 29-24
UART BRM Modulator Register Summary (UBMR) ........................................................ 29-24
UART Baud Rate Count Register Summary (UBRC) ........................................................ 29-25
UART One Millisecond Register Summary (ONEMS) ...................................................... 29-26
UART Test Register Summary (UTS)................................................................................. 29-26
Examples of Working Relationships Between ipg_clk and ipg_perclk .............................. 29-30
UART Simplified Block and Clock Generation Diagrams ................................................. 29-34
Transmitter FIFO Empty Interrupt Suppression Flow Chart .............................................. 29-36
Majority Vote Results.......................................................................................................... 29-40
Baud Rate Detection Protocol Diagram.............................................................................. 29-43
FEC Block Diagram.............................................................................................................. 30-3
Ethernet Address Recognition—Receive Block Decisions ................................................ 30-10
Ethernet Address Recognition—Microcode Decisions ...................................................... 30-11
Ethernet Interrupt Event Register (EIR) ............................................................................. 30-21
EIMR Register .................................................................................................................... 30-23
RDAR Register ................................................................................................................... 30-24
TDAR Register.................................................................................................................... 30-24
ECR Register....................................................................................................................... 30-25
MMFR Register .................................................................................................................. 30-26
MSCR Register ................................................................................................................... 30-27
MIBC Register .................................................................................................................... 30-28
RCR Register ...................................................................................................................... 30-29
TCR Register....................................................................................................................... 30-30
PALR Register..................................................................................................................... 30-31
PAUR Register .................................................................................................................... 30-32
OPD Register ...................................................................................................................... 30-32
IAUR Register..................................................................................................................... 30-33
IALR Register ..................................................................................................................... 30-33
GAUR Register ................................................................................................................... 30-34
GALR Register.................................................................................................................... 30-34
TFWR Register ................................................................................................................... 30-35
FRBR Register .................................................................................................................... 30-35
FRSR Register..................................................................................................................... 30-36
ERDSR Register.................................................................................................................. 30-36
Transmit Buffer Descriptor Ring Start Register (ETDSR) ................................................. 30-37
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
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Figures
Figure
Number
29-26
29-27
29-28
30-1
30-2
30-3
30-4
30-5
30-6
30-7
30-8
30-9
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30-29
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30-31
30-32
30-33
30-34
30-35
30-36
30-37
30-38
Title
Page
Number
EMRBR Register ................................................................................................................ 30-37
Receive Buffer Descriptor (RxBD)..................................................................................... 30-40
Transmit Buffer Descriptor (TxBD) ................................................................................... 30-42
USB Block Diagram ............................................................................................................. 31-1
USB Control Register ........................................................................................................... 31-7
OTG Mirror Register (OTGMIRROR) ............................................................................... 31-10
TLL Mux Functional Diagram............................................................................................ 31-17
USB Bypass Mux Functional Diagram............................................................................... 31-19
End Point Queue Head Organization .................................................................................. 31-22
ID—Identification Register................................................................................................. 31-30
HWGENERAL—General Hardware Parameters ............................................................... 31-31
HWHOST—Host Hardware Parameters............................................................................. 31-31
HWDEVICE—Device Hardware Parameters..................................................................... 31-32
HWTXBUF—TX Buffer Hardware Parameters................................................................. 31-33
WRXBUF—RX Buffer Hardware Parameters ................................................................... 31-33
CAPLENGTH—Capability Register Length...................................................................... 31-34
HCIVERSION—Host Interface version number................................................................ 31-34
HCSPARAMS—Host Control Structural Parameters......................................................... 31-35
HCCPARAMS—Host Control Capability Parameters ....................................................... 31-36
DCIVERSION—Device Interface Version Number........................................................... 31-38
DCCPARAMS—Device Control Capability Parameters.................................................... 31-38
GPTIMER0LD—General Purpose Timer #0 Load Register .............................................. 31-39
GPTIMER0LD—General Purpose Timer #0 Controller .................................................... 31-40
USBCMD—USB Command Register ................................................................................ 31-41
USBSTS—USB Status ....................................................................................................... 31-44
USBINTR—USB Interrupt Enable..................................................................................... 31-46
FRINDEX—USB Frame Index .......................................................................................... 31-49
PERIODICLISTBASE—Host Controller Frame List Base Address ................................. 31-50
DEVICEADDR—Device Controller USB Device Address ............................................... 31-50
ASYNCLISTADDR—Host Controller Next Asynch. Address.......................................... 31-51
ENDPOINTLISTADDR—Device Controller Endpoint List Address................................ 31-51
BURSTSIZE—Host Controller Embedded TT Async. Buffer Status ................................ 31-52
TXFILLTUNING ................................................................................................................ 31-53
ULPI VIEWPORT .............................................................................................................. 31-56
PORTSCx—Port Status Control[1:8] ................................................................................. 31-57
OTGSC—OTG Status Control............................................................................................ 31-63
USBMODE -USB Device Mode ........................................................................................ 31-65
ENDPTSETUPSTAT—Endpoint Setup Status................................................................... 31-67
ENDPTPRIME—Endpoint Initialization ........................................................................... 31-67
ENDPTFLUSH—Endpoint De-Initialize ........................................................................... 31-68
ENDPTSTAT—Endpoint Status ......................................................................................... 31-69
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Freescale Semiconductor
Figures
Figure
Number
30-39
30-40
30-41
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31-1
31-2
Title
Page
Number
ENDPTCOMPLETE—Endpoint Compete......................................................................... 31-70
ENDPTCTRL0—Endpoint Control 0................................................................................. 31-71
......................................... ENDPTCTRL1—ENDPTCTRL15—Endpoint Control 1 to 1531-72
Controller Mode .................................................................................................................. 31-75
Periodic Schedule Organization.......................................................................................... 31-77
Format of Frame List Element Pointer................................................................................ 31-78
Asynchronous Schedule Organization ................................................................................ 31-79
Split-transaction Isochronous Transaction Descriptor (siTD) ............................................ 31-84
Queue Element Transfer Descriptor Block Diagram .......................................................... 31-88
Queue Head Structure Layout............................................................................................. 31-95
Frame Span Traversal Node Structure Layout .................................................................. 31-100
Example USB 2.0 Host Controller Port Routing Block Diagram..................................... 31-103
Port Owner Handoff State Machine.................................................................................. 31-106
Derivation of Pointer into Frame List Array..................................................................... 31-111
General Format of Asynchronous Schedule List .............................................................. 31-111
Best Fit Approximation..................................................................................................... 31-113
Frame Boundary Relationship between HS bus and FS/LS Bus ...................................... 31-115
Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries ............ 31-116
Example Periodic Schedule .............................................................................................. 31-118
Example Association of iTDs to Client Request Buffer ................................................... 31-121
Generic Queue Head Unlink Scenario .............................................................................. 31-126
Asynchronous Schedule List w/Annotation to Mark Head of List ................................... 31-127
Example State Machine for Managing Asynchronous Schedule Traversal ...................... 31-128
Example HC State Machine for Controlling Nak Counter Reloads ................................. 31-132
Host Controller Queue Head Traversal State Machine ..................................................... 31-134
Example Mapping of qTD Buffer Pointers to Buffer Pages ............................................. 31-142
Host Controller Asynchronous Schedule Split-Transaction State Machine ..................... 31-146
Split Transaction, Interrupt Scheduling Boundary Conditions ......................................... 31-148
General Structure of EHCI Periodic Schedule Utilizing Interrupt Spreading .................. 31-149
Example Host Controller Traversal of Recovery Path via FSTNs.................................... 31-151
Split Transaction State Machine for Interrupt................................................................... 31-154
Split Transaction, Isochronous Scheduling Boundary Conditions ................................... 31-161
siTD Scheduling Boundary Examples .............................................................................. 31-163
Split Transaction State Machine for Isochronous ............................................................. 31-166
End Point Queue Head Organization ................................................................................ 31-186
Endpoint Queue Head (dQH)............................................................................................ 31-187
Endpoint Transfer Descriptor (dTD)................................................................................. 31-189
End Point Queue Head Diagram ....................................................................................... 31-205
Software Link Pointers ..................................................................................................... 31-207
General-Purpose Timer Block Diagram................................................................................ 32-2
GPT Control Register............................................................................................................ 32-7
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
lxiii
Figures
Figure
Number
31-3
31-4
31-5
31-6
31-7
32-1
32-2
32-3
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32-5
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34-1
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34-5
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36-1
36-2
36-3
36-4
Title
Page
Number
GPT Control Register............................................................................................................ 32-9
GPT Compare Register ....................................................................................................... 32-10
GPT Capture Register ......................................................................................................... 32-11
GPT Counter Register ......................................................................................................... 32-12
GPT Status Register ............................................................................................................ 32-13
Pulse-Width Modulator Block Diagram ............................................................................... 33-1
PWM Module Signals ........................................................................................................... 33-3
Key to Register Fields ........................................................................................................... 33-4
PWM Control Register (PWMCR) ....................................................................................... 33-6
PWM Status Register (PWMSR) .......................................................................................... 33-8
PWM Interrupt Register (PWMIR)....................................................................................... 33-9
PWM Sample Register (PWMSAR)................................................................................... 33-10
PWM Period Register (PWMPR) ....................................................................................... 33-11
PWM Counter Register (PWMCNR).................................................................................. 33-12
PWM Clocking ................................................................................................................... 33-15
Clock Distribution Inside PWM.......................................................................................... 33-16
Clock Selection and Division Unit...................................................................................... 33-17
ipg_enable_clk Generation Logic ....................................................................................... 33-17
Real Time Clock Block Diagram .......................................................................................... 34-1
Key to Register Fields ........................................................................................................... 34-4
RTC Hours and Minutes Counter Register ........................................................................... 34-6
RTC Seconds Counter Register............................................................................................. 34-7
RTC Hours and Minutes Alarm Register .............................................................................. 34-8
RTC Seconds Alarm Register ............................................................................................... 34-9
RTC Control Register.......................................................................................................... 34-10
RTC Interrupt Status Register ............................................................................................. 34-11
RTC Interrupt Enable Register............................................................................................ 34-13
RTC Stopwatch Minutes Register ....................................................................................... 34-15
RTC Days Counter Register................................................................................................ 34-16
RTC Day Alarm Register .................................................................................................... 34-17
Flowchart of RTC Operation............................................................................................... 34-20
WDOG Block Diagram......................................................................................................... 35-1
Key to Register Fields ........................................................................................................... 35-4
Watchdog Control Register ................................................................................................... 35-5
Watchdog Service Register (WSR) ....................................................................................... 35-6
Watchdog Reset Status Register (WRSR)............................................................................. 35-7
Counter State Machine........................................................................................................ 35-13
MAX Block Diagram............................................................................................................ 37-2
Key to Register Fields ........................................................................................................... 37-4
Slave General Purpose Control Register (SGPCR0-2) ....................................................... 37-10
Alternate SGPCR for Slave Port0–2 (ASGPCR0-2) .......................................................... 37-12
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Freescale Semiconductor
Figures
Figure
Number
36-5
36-6
36-7
36-8
36-9
36-10
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38-2
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38-5
38-6
38-7
Title
Page
Number
Master General Purpose Control Registers (MGPCR0-5) .................................................. 37-13
MAX Master Port Block Diagram ...................................................................................... 37-17
MAX Slave Port Block Diagram ........................................................................................ 37-20
Low to High Priority Mastership Change ........................................................................... 37-22
High to Low Priority Mastership Change ........................................................................... 37-22
Round-Robin Mastership Change ....................................................................................... 37-23
Parking on Last Master ....................................................................................................... 37-24
Parking on a Specific Master .............................................................................................. 37-25
Block Diagram of DMAC ..................................................................................................... 38-1
Assertion of DMA External Grant Signal............................................................................. 38-3
Safe Maximum Timings for External Request De-Assertion ............................................... 38-3
Key to Register Fields ........................................................................................................... 38-6
DMA Control Register (DCR) ............................................................................................ 38-11
DMA Interrupt Status Register ........................................................................................... 38-12
DMA Interrupt Status Register (DIMR) ............................................................................. 38-13
DMA Burst Time-Out Status Register (DBTOSR)............................................................. 38-14
DMA Request Time-Out Status Register (DRTOSR)......................................................... 38-15
DMA Transfer Error Status Register (DSESR) .................................................................. 38-16
DMA Buffer Overflow Status Register (DBOSR).............................................................. 38-17
DMA Burst Time-Out Control Register (DBTOCR).......................................................... 38-18
2D Memory Increment Diagram......................................................................................... 38-19
2D Memory Decrement Diagram ....................................................................................... 38-19
W-Size Registers (WSRA, WSRB)..................................................................................... 38-20
X-Size Registers (XSRA, XSRB) ....................................................................................... 38-21
Y Size Registers (YSRA, YSRB) ....................................................................................... 38-22
Channel Source Address Register (SAR0–SAR15)............................................................ 38-23
Channel Destination Address Registers (DAR0–DAR15).................................................. 38-24
Channel Count Registers (CNTR0–CNTR15).................................................................... 38-25
Channel Control Registers (CCR0–CCR15)....................................................................... 38-26
Channel Request Source Select Registers (RSSR0–RSSR15)............................................ 38-28
Channel Burst Length Registers (BLR0–BLR15) .............................................................. 38-29
Channel Request Time-Out Registers (RTOR0–RTOR15)................................................. 38-30
Channel Bus Utilization Control Register (BUCR0–BUCR15) ......................................... 38-31
Channel Counter Register (CCNR0–CCNR15).................................................................. 38-32
AUDMUX Block Diagram ................................................................................................... 39-3
Internal Network Mode ......................................................................................................... 39-4
Tx/Rx Switch ........................................................................................................................ 39-5
Frame Sync and Clock Routing when Peripheral Port is 4-Wire.......................................... 39-6
Frame Sync Routing when Peripheral Port is 6-Wired ......................................................... 39-9
Clock Routing when Peripheral Port is 6-Wired................................................................. 39-10
SSI to Peripheral Port Interconnection................................................................................ 39-12
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
lxv
Figures
Figure
Number
38-8
38-9
38-10
38-11
38-12
38-13
38-14
38-15
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39-1
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40-13
40-14
40-15
40-16
Title
Page
Number
SSI to SAP Interconnection ................................................................................................ 39-13
Key to Register Fields ......................................................................................................... 39-14
Host Port Configuration Register (HPCR1–2).................................................................... 39-16
Peripheral Port Configuration Registers (PPCR1–2) .......................................................... 39-18
SAP as Master to SSI2 as Slave Interconnection................................................................ 39-21
Configuration Overview...................................................................................................... 39-22
SSI1 as Master in Internal Network Mode.......................................................................... 39-23
Tx-Rx Switch Restriction.................................................................................................... 39-24
Internal and External Mode Restriction .............................................................................. 39-25
CSI Block Diagram ............................................................................................................... 40-2
Non-Gated Clock Mode Timing Diagram ............................................................................ 40-4
CCIR656 Interlace Mode (PAL) ........................................................................................... 40-5
CCIR656 General Line Timing............................................................................................. 40-5
CCIR656 Progressive Mode (General Case) ........................................................................ 40-7
Sample Timing Diagram for RGB888 Data........................................................................ 40-10
Optional Dummy Byte Packing Scheme............................................................................. 40-10
Key to Register Fields ......................................................................................................... 40-11
CSPI Control Register 1 (CSICR1)..................................................................................... 40-14
CSI Control Register 2 (CSICR2)....................................................................................... 40-17
CSI Control Register 3 (CSICR3)....................................................................................... 40-19
CSI Status Register (CSISR)............................................................................................... 40-20
CSI STATFIFO Register (CSISTATFIFO).......................................................................... 40-22
CSI RxFIFO Register (CSIRFIFO)..................................................................................... 40-23
CSI RX Count Register (CSIRXCNT) ............................................................................... 40-23
Video Codec Block Architecture Diagram ........................................................................... 41-1
Key to Register Fields ........................................................................................................... 41-5
Video Codec Code Run Register........................................................................................... 41-7
Video Codec BIT Boot Code Download Data Register........................................................ 41-8
Video Codec Host Interrupt Request Register ...................................................................... 41-9
Video Codec BIT Interrupt Clear Register............................................................................ 41-9
Video Codec BIT Interrupt Status Register ........................................................................ 41-10
Video Codec BIT Code Reset Register ............................................................................... 41-11
Video Codec BIT Current PC Register ............................................................................... 41-12
Rotation and Mirroring Data Flow...................................................................................... 41-15
Video Codec Interface with Application Software Diagram .............................................. 41-16
Codec Process State Diagram ............................................................................................. 41-17
H.264 Codec Process Flow Example .................................................................................. 41-19
Frame Buffer Configuration................................................................................................ 41-21
Frame Buffer Address Map in Little Endian....................................................................... 41-22
One of Application Using Case: One Channel Encoding and
Three Channels Decoding .............................................................................................. 41-26
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
lxvi
Freescale Semiconductor
Figures
Figure
Number
41-1
41-2
41-3
41-4
41-5
41-6
41-7
41-8
41-9
41-10
41-11
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41-41
Title
Page
Number
eMMA_lt Block Diagram ..................................................................................................... 42-3
eMMA AHB 64-Bit Gasket with Bypass.............................................................................. 42-4
Post-Processor (PP) Block Diagram ..................................................................................... 42-5
PP Input Data Layout (QCIF) ............................................................................................. 42-10
Input Line Stride ................................................................................................................. 42-12
Output Line Stride............................................................................................................... 42-13
PP Control Register............................................................................................................. 42-14
PP Interrupt Control Register.............................................................................................. 42-16
PP Interrupt Status Register ................................................................................................ 42-17
PP Source Y Address Register............................................................................................ 42-18
PP Source Cb Address Register .......................................................................................... 42-18
PP Source Cr Address Register........................................................................................... 42-19
PP Destination RGB Frame Start Address Register ........................................................... 42-20
PP Quantizer Start Address Register................................................................................... 42-20
PP Process Parameter Register............................................................................................ 42-21
PP Source Frame Width Register........................................................................................ 42-22
PP Destination Display Width Register .............................................................................. 42-23
PP Destination Image Size Register.................................................................................... 42-23
PP Destination Frame Format Control Register.................................................................. 42-24
PP Resize Table Index Register .......................................................................................... 42-26
PP CSC Coefficient_123 Register....................................................................................... 42-27
PP CSC Coefficient_4 Register........................................................................................... 42-28
PP Resize Coefficient Table (Array of 32 Resize Coefficients).......................................... 42-29
Memory Image Size and Source Line Stride ...................................................................... 42-40
Memory Image and Output Stride ...................................................................................... 42-40
CSI Frame Cropping ........................................................................................................... 42-41
CSI-PrP Link....................................................................................................................... 42-42
PRP Control Register .......................................................................................................... 42-45
PRP Interrupt Control Register ........................................................................................... 42-48
PrP Interrupt Status Register............................................................................................... 42-49
PrP Source Y Address Register........................................................................................... 42-50
PrP Source Cb Address Register......................................................................................... 42-51
PrP Source Cr Address Register ......................................................................................... 42-51
PrP Destination RGB1 Start Address Register ................................................................... 42-52
PrP Destination RGB2 Start Address Register ................................................................... 42-53
PrP Destination Y Address Register ................................................................................... 42-53
PrP Destination Cb Address Register ................................................................................. 42-54
PrP Destination Cr Address Register .................................................................................. 42-55
PrP Source Frame Size Register ......................................................................................... 42-55
PrP Destination Channel-1 Line Stride Register................................................................. 42-56
PrP Source Pixel Format Control Register.......................................................................... 42-57
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
lxvii
Figures
Figure
Number
41-42
41-43
41-44
41-45
41-46
41-47
41-48
41-49
41-50
41-51
41-52
41-53
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41-60
42-1
42-2
42-3
42-4
42-5
42-6
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42-12
42-13
42-14
42-15
42-16
42-17
42-18
42-19
42-20
42-21
42-22
Title
Page
Number
PrP CH1 Pixel Format Control Register ............................................................................. 42-59
PrP Destination Channel-1 Output Image Size Register..................................................... 42-60
PrP Destination CH2 Output Image Size Register.............................................................. 42-61
PrP Source Line Stride Register.......................................................................................... 42-62
PrP CSC Coefficient 012..................................................................................................... 42-63
PrP CSC Coefficient 345..................................................................................................... 42-64
PrP CSC Coefficient 678..................................................................................................... 42-65
PrP Channel-1 Horizontal Resize Coefficient 1.................................................................. 42-66
PrP Channel-1 Horizontal Resize Coefficient 2.................................................................. 42-67
PrP Channel-1 Resize Horizontal Valid .............................................................................. 42-69
PrP Channel 1 Vertical Resize Coefficient 1....................................................................... 42-70
PrP Channel-1 Vertical Resize Coefficient 2 ...................................................................... 42-71
PrP Channel1 Vertical Resize Valid .................................................................................... 42-72
PrP Channel-2 Horizontal Resize Coefficient 1.................................................................. 42-73
PrP Channel-2 Horizontal Resize Coefficient 2.................................................................. 42-74
PrP Channel-2 Resize Horizontal Valid .............................................................................. 42-75
PrP Channel2 Vertical Resize Coefficient 1........................................................................ 42-76
PrP Channel-2 Vertical Resize Coefficient 2 ...................................................................... 42-77
PrP Channel2 Vertical Resize Valid .................................................................................... 42-79
SSI Block Diagram ............................................................................................................... 43-2
Normal Mode Timing—Continuous Clock .......................................................................... 43-7
Normal Mode Timing—Internal Gated Clock...................................................................... 43-8
Normal Mode Timing—External Gated Clock..................................................................... 43-8
Network Mode Timing—Continuous Clock....................................................................... 43-12
Internal Gated Mode Timing—Rising Edge Clocking/Falling Edge Latching................... 43-13
Internal Gated Mode Timing—Falling Edge Clocking/Rising Edge Latching................... 43-13
External Gated Mode Timing—Rising Edge Clocking/Falling Edge Latching ................. 43-14
External Gated Mode Timing—Falling Edge Clocking/Rising Edge Latching ................. 43-14
I2S Mode Timing—Serial Clock, Frame Sync, and Serial Data ........................................ 43-14
Asynchronous (SYN=0) SSI Configurations—Continuous Clock ..................................... 43-22
Synchronous SSI Configurations—Continuous and Gated Clock...................................... 43-23
Serial Clock and Frame Sync Timing ................................................................................. 43-24
Key to Register Fields ......................................................................................................... 43-28
SSI Transmit Data Registers ............................................................................................... 43-33
Transmit Data Path (TXBIT0=0, TSHFD=0) (MSB Alignment) ....................................... 43-34
Transmit Data Path (TXBIT0=0, TSHFD=1) (MSB Alignment) ....................................... 43-35
Transmit Data Path (TXBIT0=1, TSHFD=0) (LSB Alignment) ........................................ 43-35
Transmit Data Path (TXBIT0=1, TSHFD=1) (LSB Alignment) ........................................ 43-36
SSI Receive Data Registers................................................................................................. 43-36
Receive Data Path (RXBIT0=0, RSHFD=0) (MSB Alignment) ........................................ 43-37
Receive Data Path (RXBIT0=0, RSHFD=1) (MSB Alignment) ........................................ 43-38
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Figures
Figure
Number
42-23
42-24
42-25
42-26
42-27
42-28
42-29
42-30
42-31
42-32
42-33
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43-6
43-8
43-9
43-10
43-11
43-12
43-13
43-14
43-15
43-16
Title
Page
Number
Receive Data Path (RXBIT0=1, RSHFD=0) (LSB Alignment) ......................................... 43-38
Receive Data Path (RXBIT0=1, RSHFD=1) (LSB Alignment) ......................................... 43-39
SSI Control Register ........................................................................................................... 43-39
SSI Interrupts ...................................................................................................................... 43-41
SSI Interrupt Status Register............................................................................................... 43-42
SSI Interrupt Enable Register.............................................................................................. 43-46
SSI Transmit Configuration Register .................................................................................. 43-47
SSI Receive Configuration Register.................................................................................... 43-49
SSI Transmit and Receive Clock Control Registers ........................................................... 43-51
SSI FIFO Control/Status Register....................................................................................... 43-53
SSI Test Register ................................................................................................................. 43-56
SSI Option Register............................................................................................................. 43-57
SSI AC97 Control Register ................................................................................................. 43-58
SSI AC97 Command Address Register .............................................................................. 43-60
SSI AC97 Command Data Register .................................................................................... 43-61
SSI AC97 Tag Register ....................................................................................................... 43-62
SSI Transmit Time Slot Mask Register............................................................................... 43-63
SSI Receive Time Slot Mask Register ................................................................................ 43-64
SSI AC97 Channel Status Register ..................................................................................... 43-65
SSI AC97 Channel Enable Register.................................................................................... 43-66
SSI AC97 Channel Disable Register................................................................................... 43-67
SSI Clocking ....................................................................................................................... 43-68
SSI Transmit Clock Generator Block Diagram .................................................................. 43-69
SSI Transmit Frame Sync Generator Block Diagram ......................................................... 43-69
SSI Bit Clock Equation ....................................................................................................... 43-70
LCDC Block Diagram .......................................................................................................... 44-3
LCD Screen Format .............................................................................................................. 44-3
Graphic Window on Screen .................................................................................................. 44-4
Pixel Location on Display Screen ......................................................................................... 44-5
Display Data Mapping 1 bpp Through 16 bpp Mode ........................................................... 44-6
Display Data Mapping for 24 bpp Mode .............................................................................. 44-7
Display Data Mapping for 18 bpp Mode .............................................................................. 44-7
Gray-Scale Pixel Generation................................................................................................. 44-8
Active Matrix Color Pixel Generation .................................................................................. 44-8
Passive Matrix Color Pixel Generation ................................................................................. 44-9
LCDC Interface Signals ...................................................................................................... 44-10
LCDC Interface Timing for 4-Bit Data Width Gray-Scale Panels...................................... 44-12
LCDC Interface Timing for 8-Bit Data Passive Matrix Color Panels................................. 44-12
Horizontal Sync Pulse Timing in Passive Mode ................................................................. 44-13
Vertical Sync Pulse Timing in Passive Mode...................................................................... 44-13
LCDC Interface 16-Bit Timing for Active Matrix Color Panels ........................................ 44-14
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
lxix
Figures
Figure
Number
43-17
43-18
43-19
43-20
43-21
43-22
43-23
43-24
43-25
43-26
43-27
43-28
43-29
43-30
43-31
43-32
43-33
43-34
43-35
43-36
43-37
43-38
43-39
43-40
43-41
43-42
43-43
43-44
43-45
43-46
43-47
43-48
43-49
44-1
44-2
44-3
44-4
44-5
Title
Page
Number
LCDC Interface 18-Bit Timing for Active Matrix Color Panels ........................................ 44-15
LCDC Interface 24-bpp Timing For AUS Mode ................................................................ 44-16
LCDC Interface 16-bpp Timing For AUS Mode ................................................................ 44-17
Horizontal Sync Pulse Timing in TFT Mode...................................................................... 44-17
Vertical Sync Pulse Timing TFT Mode .............................................................................. 44-18
Key to Register Fields ......................................................................................................... 44-19
LCDC Screen Start Address Register (LSSAR) ................................................................. 44-23
LCDC Size Register (LSR)................................................................................................. 44-24
LCDC Virtual Page Width Register (LVPWR)................................................................... 44-25
LCDC Cursor Position Register (LCPR) ............................................................................ 44-25
LCDC Cursor Width Height and Blink Register (LCWHB) .............................................. 44-26
LCDC Color Cursor Mapping Register (LCCMR)............................................................. 44-27
LCDC Panel Configuration Register (LPCR) ..................................................................... 44-28
LCDC Horizontal Configuration Register (LHCR) ............................................................ 44-31
LCDC Vertical Configuration Register (LVCR) ................................................................. 44-32
LCDC Panning Offset Register (LPOR) ............................................................................. 44-33
LCDC Sharp Configuration Register (LSCR) .................................................................... 44-34
Horizontal Timing in Device_Number ............................................................................... 44-35
LCDC PWM Contrast Control Register (LPCCR) ............................................................. 44-36
LCDC DMA Control Register (LDCR).............................................................................. 44-37
LCDC Refresh Mode Control Register (LRMCR) ............................................................. 44-38
LCDC Interrupt Configuration Register (LICR)) ............................................................... 44-39
LCDC Interrupt Enable Register (LIER) ............................................................................ 44-40
LCDC Interrupt Status Register (LISR).............................................................................. 44-41
LCDC Graphic Window Start Address Register (LGWSAR) ............................................ 44-42
LCDC Graphic Window Start Address Register (LGWSAR) ............................................ 44-43
LCDC Graphic Window Virtual Page Width Register (LGWVPWR) ............................... 44-44
LCDC Graphic Window Panning Offset Register (LGWPOR).......................................... 44-44
LCDC Graphic Window Position Register (LGWPR)........................................................ 44-45
LCDC Graphic Window Control Register (LGWCR) ........................................................ 44-46
LCDC Graphic Window DMA Control Register (LGWDCR)........................................... 44-47
LCDC AUS Mode Control Register (LAUSCR) ................................................................ 44-48
LCDC AUS Mode Cursor Control Register (LAUSCCR).................................................. 44-49
SLCDC System Diagram ...................................................................................................... 45-2
Sample LCD Controller Memory Mapping (Monochrome)
(8-Bit Command/8-Bit Data) ........................................................................................... 45-5
SLCDC LCD Controller Memory Mapping (2-Bit Color/Gray Scale)
(8-Bit Command/8-Bit Data) ........................................................................................... 45-6
Automatic Display Data Transfer Memory Configuration
(8-Bit Command/8-Bit Data) ........................................................................................... 45-7
Command Buffer Tag Organization (8-Bit Words)............................................................... 45-8
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
lxx
Freescale Semiconductor
Figures
Figure
Number
44-6
44-7
44-8
44-9
44-10
44-11
44-12
44-13
44-14
44-15
44-16
44-17
44-18
44-19
44-20
44-21
44-22
44-23
44-24
Title
Page
Number
Sample LCD Controller Memory Map (16-Bit Color)
(16-Bit Command/16-Bit Data) ....................................................................................... 45-9
Command Buffer Tag Organization (16-bit Words) ........................................................... 45-10
Automatic Display Data Transfer Memory Configuration
(16-Bit Command/16-Bit Data) ..................................................................................... 45-11
SLCDC Automatic Mode Write Sequence (Monochrome Display) .................................. 45-12
SLCDC Automatic Mode Data Flow (AUTOMODE[1:0] = 10)........................................ 45-13
Key to Register Fields ......................................................................................................... 45-15
Data Buffer Base Address register ...................................................................................... 45-18
Data Buffer Size register ..................................................................................................... 45-18
Command Buffer Base Address Register............................................................................ 45-19
Command Buffer Size Register........................................................................................... 45-19
Command String Size Register ........................................................................................... 45-20
FIFO Configuration Register .............................................................................................. 45-21
LCD Controller Configuration Register.............................................................................. 45-21
LCD Transfer Configuration Register................................................................................. 45-22
SLCDC Control/Status Register ......................................................................................... 45-23
LCD Clock Configuration Register .................................................................................... 45-26
LCD Write Data Register.................................................................................................... 45-26
SLCDC Serial Transfers to LCD Device ............................................................................ 45-28
SLCDC Parallel Transfers to LCD Device ......................................................................... 45-30
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
lxxi
Figures
Figure
Number
Title
Page
Number
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
lxxii
Freescale Semiconductor
Tables
Table
Number
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
Title
Page
Number
Tables
4 Gbyte Memory Map Breakdown.......................................................................................... 2-1
Primary AHB Memory Map (Lower) ..................................................................................... 2-3
Secondary AHB Port 1 Memory Map..................................................................................... 2-3
Secondary AHB Port 2 Memory Map..................................................................................... 2-5
Primary AHB Memory Map (Upper)...................................................................................... 2-5
AIPI1 Memory Map................................................................................................................ 2-6
AIPI2 Memory Map................................................................................................................ 2-7
Register Map ........................................................................................................................... 2-7
PLL Clock Controller Signal Descriptions ............................................................................. 3-3
SDRAM Operation During Power Modes .............................................................................. 3-8
Power Management in the Clock Controller........................................................................... 3-8
PLL Clock Controller Memory Map ...................................................................................... 3-9
Register Conventions .............................................................................................................. 3-9
Clock Source Control Register Field Descriptions ............................................................... 3-11
MPLL Register 0 Field Descriptions .................................................................................... 3-13
Recommend Settings for Frequency Stability....................................................................... 3-14
MCU and System PLL Control Register 1 Field Descriptions ............................................. 3-15
Serial PLL Multiplier Factor................................................................................................. 3-16
SPLL Control Register 0 Field Descriptions ........................................................................ 3-17
Serial Peripheral PLL Control Register 1 Field Descriptions............................................... 3-19
Oscillator 26M Control Register Field Descriptions ............................................................ 3-20
Peripheral Clock Divider Register 0 Field Descriptions....................................................... 3-22
Peripheral Clock Divider Register 1 Field Descriptions....................................................... 3-23
Clock Sources for i.MX27 Peripherals ................................................................................. 3-24
Peripheral Clock Control Register 0 Field Descriptions....................................................... 3-25
Peripheral Clock Control Register 1 Field Descriptions....................................................... 3-28
Clock Control Status Register Field Descriptions ................................................................ 3-31
Wakeup Guard Mode Control Register Field Descriptions .................................................. 3-33
Reset Module Pin and Signal Descriptions........................................................................... 3-36
Block Memory Map ................................................................................................................ 4-1
Register Conventions .............................................................................................................. 4-2
Chip ID Register Field Descriptions ....................................................................................... 4-3
Function Multiplexing Control Register Description ............................................................. 4-4
Global Peripheral Control Register Descriptions.................................................................... 4-7
Well Bias Control Register Field Descriptions ....................................................................... 4-9
Drive Strength Control Register 1 Field Description............................................................ 4-11
Drive Strength Control Register 2 Field Descriptions .......................................................... 4-13
Drive Strength Control Register 3 Field Descriptions .......................................................... 4-15
Drive Strength Control Register 4 Field Descriptions .......................................................... 4-18
Drive Strength Control Register 5 Field Descriptions .......................................................... 4-19
Drive Strength Control Register 6 Field Descriptions .......................................................... 4-22
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
lxxiii
Tables
Table
Number
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
5-1
5-2
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
7-1
7-2
7-3
Title
Page
Number
Drive Strength Control Register 7 Field Descriptions .......................................................... 4-24
Drive Strength Control Register 8 Field Descriptions .......................................................... 4-26
Drive Strength Control Register 9 Field Descriptions .......................................................... 4-29
Drive Strength Control Register 10 Field Descriptions ........................................................ 4-31
Drive Strength Control Register 11 Field Descriptions ........................................................ 4-33
Drive Strength Control Register 12 Field Descriptions ........................................................ 4-36
Drive Strength Control Register 13 Field Descriptions ........................................................ 4-37
Pull Strength Control Register Field Descriptions................................................................ 4-39
Priority Control and Select Register Field Descriptions ....................................................... 4-41
Power Management Control Register Field Descriptions..................................................... 4-42
DPTC Comparator Value Register 0 Field Description ........................................................ 4-44
DPTC Comparator Value Register 1 Field Descriptions....................................................... 4-45
DPTC Comparator Value Register 2 Field Descriptions....................................................... 4-45
DPTC Comparator Value Register 3 Description ................................................................. 4-46
PMIC Pad Control Register Field Description...................................................................... 4-47
System Boot Mode Selection................................................................................................ 4-48
i.MX27 Signal Descriptions.................................................................................................... 5-1
i.MX27 Pin MUX Table........................................................................................................ 5-11
GPIO Memory Map ................................................................................................................ 6-5
Register Conventions .............................................................................................................. 6-8
Data Direction Register Field Descriptions ............................................................................ 6-9
Output Configuration Register 1 Field Descriptions ............................................................ 6-10
Output Configuration Register 2 Field Descriptions ............................................................ 6-11
Input Configuration Register A1 Field Descriptions ............................................................ 6-13
Input Configuration Register A2 Field Descriptions ............................................................ 6-13
Input Configuration Register B1 Field Descriptions ............................................................ 6-14
Input Configuration Register B2 Description ....................................................................... 6-15
Data Register Field Descriptions .......................................................................................... 6-16
GPIO In Use Register Field Descriptions ............................................................................. 6-17
Sample Status Register Field Descriptions ........................................................................... 6-21
Interrupt Configuration Register 1 Field Descriptions.......................................................... 6-22
Interrupt Configuration Register 2 Field Descriptions.......................................................... 6-23
Interrupt Mask Register Description ..................................................................................... 6-24
Interrupt Status Register Field Descriptions ......................................................................... 6-25
General Purpose Register Field Descriptions ....................................................................... 6-26
Software Reset Register Field Descriptions.......................................................................... 6-27
Pull-Up Enable Register Field Descriptions ......................................................................... 6-28
Port Interrupt Mask Register Field Descriptions .................................................................. 6-29
TMS Sequence To Check ID Code ......................................................................................... 7-6
TMS Sequence to Write to ExtraDebug Register ................................................................... 7-7
TMS Sequence to Read ExtraDebug Register ........................................................................ 7-8
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
lxxiv
Freescale Semiconductor
Tables
Table
Number
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
Title
Page
Number
Synch Command Response Definition ................................................................................... 8-3
Response A Definition ............................................................................................................ 8-3
Write Register Command Definition ...................................................................................... 8-4
Response B Definition ............................................................................................................ 8-4
Response C Definition ............................................................................................................ 8-4
Download Command Definition ............................................................................................. 8-5
Response B Silicon Type Definition ....................................................................................... 8-5
Bootstrap End Indication Operation Diagram ........................................................................ 8-6
AIPI ARM9 Platform IP Bus Support .................................................................................. 10-7
JAM IP Bus General Purpose Registers................................................................................ 10-8
ARM926EJ-S JTAG ID Register Definition ....................................................................... 10-10
Upper Address Bit Decode ................................................................................................. 10-10
ARM9 Platform Memory Map ........................................................................................... 10-10
Alternate Bus Master Interface Signal List ......................................................................... 10-18
Single External Master Connections to an Alternate Bus Master Interface........................ 10-19
hmaster Encodings .............................................................................................................. 10-21
Primary AHB Slave Device Latencies ................................................................................ 10-24
Secondary AHB Interface Signal List................................................................................. 10-24
ARM926EJ-S Endian Related Signals................................................................................ 10-25
Little Endian Byte Write Enable Decoding ........................................................................ 10-26
Big Endian Byte Write Enable Decoding ........................................................................... 10-27
ARM9 Platform Size Estimates .......................................................................................... 10-28
ARM9 Platform Power Estimates ....................................................................................... 10-29
ARM9 Platform Signal List ................................................................................................ 10-30
ARM9 Platform AHB Clock and Reset Timing Constraints .............................................. 10-39
Alternate Bus Master Constraints ....................................................................................... 10-40
Alternate Bus Master Interface AC Timing Parameters...................................................... 10-42
Secondary AHB Constraints ............................................................................................... 10-42
Secondary AHB AC Timing Parameters............................................................................. 10-43
RAM and ROM Interface Loading Constraints .................................................................. 10-44
RAM and ROM Interface AC Timing Parameters .............................................................. 10-45
AITC Memory Map .............................................................................................................. 11-3
Register Figure Conventions ................................................................................................. 11-4
AITC Register Summary....................................................................................................... 11-5
Interrupt Control Register Field Description ........................................................................ 11-9
Normal Interrupt Mask Register Field Description ............................................................ 11-10
Interrupt Enable Number Register Description................................................................... 11-11
Interrupt Disable Number Register Field Description ........................................................ 11-12
Interrupt Enable Register Low and High Field Descriptions.............................................. 11-14
Interrupt Type Register High and Low Register Description.............................................. 11-15
Normal Interrupt Priority Level Register 7 Field Description ............................................ 11-16
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
lxxv
Tables
Table
Number
10-11
10-12
10-13
10-14
10-15
10-16
10-17
10-18
10-19
10-21
10-20
10-22
10-23
10-24
10-25
10-26
10-27
15-1
15-2
15-3
15-4
15-5
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
16-9
16-10
16-11
16-12
16-13
16-14
16-15
16-16
17-1
17-2
17-3
Title
Page
Number
Normal Interrupt Priority Level Register 6 Field Description ............................................ 11-17
Normal Interrupt Priority Level Register 5 Field Description ............................................ 11-18
Normal Interrupt Priority Level Register 4 Field Description ............................................ 11-19
Normal Interrupt Priority Level Register 3 Field Description ............................................ 11-20
Normal Interrupt Priority Level Register 2 Field Description ............................................ 11-21
Normal Interrupt Priority Level Register 1 Field Description ............................................ 11-22
Normal Interrupt Priority Level Register 0 Field Description ............................................ 11-23
Normal Interrupt Vector and Status Register Field Description ......................................... 11-24
Fast Interrupt Vector and Status Register Description ........................................................ 11-25
Interrupt Source High (INTSRCH) Assignment................................................................. 11-26
Interrupt Source Register High and Low Description......................................................... 11-26
Interrupt Source Low (INTSRCL) Assignment .................................................................. 11-27
Interrupt Force Register High and Low Field Description ................................................. 11-29
Normal Interrupt Pending Register High and Low Description ......................................... 11-30
Fast Interrupt Pending Register High and Low Field Description...................................... 11-31
Typical Hardware Accelerated Normal Interrupt Entry Sequence...................................... 11-32
Typical Fast Interrupt Entry Sequence ................................................................................ 11-33
CHOOSEN_SLAVE Encoding ............................................................................................. 16-8
External Memory Interface I/O MUX Description............................................................. 16-11
EMI Signal Properties ......................................................................................................... 16-22
EMI Registers Definition .................................................................................................... 16-29
EMI Memory Map .............................................................................................................. 16-30
M3IF Signal Properties ......................................................................................................... 17-4
M3IF Memory Map .............................................................................................................. 17-6
M3IF Memory Space Summary............................................................................................ 17-6
Register Figure Conventions ................................................................................................. 17-7
M3IF Register Summary....................................................................................................... 17-8
M3IF Control Register Field Descriptions.......................................................................... 17-11
M3IF Snooping Configuration Register 0 Field Descriptions ............................................ 17-12
SWSZ Field Descriptions.................................................................................................... 17-12
M3IF Snooping Configuration Register 1–2 Field Descriptions ........................................ 17-14
M3IF Snooping Status Register 0 Field Descriptions......................................................... 17-15
M3IF Snooping Status Register 1 Field Descriptions......................................................... 17-16
M3IF Lock General Register Field Descriptions ................................................................ 17-17
MPG Supported Burst Accesses ......................................................................................... 17-19
MPG MAX Signals ............................................................................................................. 17-20
MPG64 Supported Burst Accesses ..................................................................................... 17-29
MPG64 Additional Signals ................................................................................................. 17-30
Signal Properties ................................................................................................................... 18-3
WEIM Detailed Signal Descriptions..................................................................................... 18-4
Boot Configuration Settings.................................................................................................. 18-6
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
lxxvi
Freescale Semiconductor
Tables
Table
Number
17-4
17-5
17-6
17-7
17-8
17-9
17-10
17-11
17-12
17-13
17-14
17-15
17-16
17-17
17-18
17-19
17-20
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
18-15
18-16
18-17
18-18
18-19
18-20
18-21
18-22
Title
Page
Number
WEIM Out/in Data in Case AHB Out/in Data is 0xB3B2B1B0 .......................................... 18-7
WEIM Memory Map ............................................................................................................ 18-8
WEIM Chip Selection Memory Map.................................................................................... 18-8
Register Figure Conventions ................................................................................................. 18-9
WEIM Register Summary................................................................................................... 18-10
Chip Select x Upper Control Register Field Descriptions .................................................. 18-13
PSZ Bit Field Values ........................................................................................................... 18-16
WSC Bit Field Values ......................................................................................................... 18-16
Chip Select x Lower Control Register Field Descriptions.................................................. 18-18
DSZ Bit Field Values .......................................................................................................... 18-19
Chip Select x Addition Control Register Field Descriptions .............................................. 18-21
LBN Bit Field Values .......................................................................................................... 18-23
CNC/CNC2 Bit Values........................................................................................................ 18-23
WEIM Control Register Field Descriptions........................................................................ 18-24
WEIM Operation Modes Field Settings.............................................................................. 18-25
AHB Burst Cycles Supported ............................................................................................. 18-28
External Memory Bursts Start Addresses for Some AHB Burst Accesses......................... 18-28
ESDRAMC Signal Properties ............................................................................................... 19-6
ESDRAMC Detailed Signal Description.............................................................................. 19-7
ESDRAMC Memory Map .................................................................................................. 19-10
ESDRAMC Memory Map .................................................................................................. 19-10
Register Figure Conventions ............................................................................................... 19-11
ESDRAMC Register Summary........................................................................................... 19-11
Enhanced SDRAM Control Register (ESDCTL0/1) Field Descriptions............................ 19-15
COL Bit Field Encoding ..................................................................................................... 19-16
SREFR Bit Field Encoding ................................................................................................. 19-17
PWDT Bit Field Encoding.................................................................................................. 19-17
Burst Length Bit Field Encoding ........................................................................................ 19-17
PRCT Bit Field Encoding ................................................................................................... 19-17
ESDCFG0/ESDCFG1 Field Descriptions .......................................................................... 19-19
tWR Bit Field Encoding...................................................................................................... 19-21
Configurable SDRAM/LPDDR Timing Parameters........................................................... 19-22
tRC Bit Field Encoding....................................................................................................... 19-30
Enhanced SDRAM Control Register (ESDCTL0/1) Field Descriptions............................ 19-32
Enhanced MDDR Delay Line 5 Control Register (ESDCDLY5)
Field Descriptions .......................................................................................................... 19-35
Enhanced MDDR Delay Line Cycle Length Debug Register (ESDCDLYL)
Field Descriptions .......................................................................................................... 19-36
JEDEC Standard Single/Double Data Rate SDRAMs........................................................ 19-36
Possibilities for Latency Hiding.......................................................................................... 19-41
CPU to SDRAM/LPDDR Translation ................................................................................ 19-44
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
lxxvii
Tables
Table
Number
18-23
18-24
18-25
18-26
18-27
18-28
18-29
18-30
18-31
18-32
18-33
18-34
18-35
18-36
18-37
18-38
18-39
18-40
18-41
18-42
18-43
18-44
18-45
18-46
18-47
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-12
19-13
19-11
19-14
19-15
19-16
Title
Page
Number
Address Multiplexing by Column/Row Width for 16-Bit Devices..................................... 19-45
Address Multiplexing by Column/Row Width for 32-bit Devices ..................................... 19-46
Bank Address Bit Assignment ............................................................................................ 19-47
ESDRAMC Low Power Operating Modes ......................................................................... 19-49
SDRAM (SDR and LPDDR) Command Encoding ............................................................ 19-60
SDRAM/LPDDR Burst Access Support............................................................................. 19-63
SDRAM Command Sequence for Burst Accesses ............................................................. 19-91
SDRAM Mode Register Description ................................................................................ 19-100
Example Address Calculation for Mode Register............................................................. 19-101
Single 4Mx16 Control Register Value .............................................................................. 19-102
Single 8MBx16 Control Register Value............................................................................ 19-103
Single 16MBx16 Control Register Value.......................................................................... 19-104
Single 32MBx16 Control Register Value.......................................................................... 19-105
Single 64MBx16 Control Register Value.......................................................................... 19-106
Dual 4MBx16 Control Register Value .............................................................................. 19-107
Dual 8MBx16 Control Register Value .............................................................................. 19-108
Dual 16MBx16 Control Register Value ............................................................................ 19-109
Single 2MBx32 Control Register Value............................................................................ 19-110
Single 4MBx32 Control Register Value............................................................................ 19-111
Single 8MBx32 Control Register Value............................................................................ 19-112
Single 16MBx32 Control Register Value.......................................................................... 19-113
Single 32MBx32 Control Register Value.......................................................................... 19-114
Single 64MBx32 Control Register Value.......................................................................... 19-115
Single 16MBx32 Control Register Value.......................................................................... 19-116
Single 32MBx16 Control Register Value.......................................................................... 19-117
NFC Signal Properties .......................................................................................................... 20-3
NFC Detailed Signal Descriptions........................................................................................ 20-3
Data (Buffer) Organization in Memory ................................................................................ 20-5
Spare Area Buffer (with X8 I/O bus) .................................................................................... 20-6
Spare Area Buffer (with X16 I/O bus) .................................................................................. 20-6
NFC Module Register Memory Map .................................................................................... 20-7
Register Figure Conventions ................................................................................................. 20-8
NFC Register Summary ........................................................................................................ 20-8
NFC_BUFSIZE Register Field Description........................................................................ 20-10
RAM Buffer Address Field Descriptions............................................................................ 20-10
NAND_Flash_CMD Register Field Description ................................................................ 20-11
NFC_Configuration Register Field Descriptions................................................................ 20-11
NAND Flash Address Register Field Description .............................................................. 20-11
ECC_STATUS_RESULT Register Field Description......................................................... 20-12
ECC_RSLT_MAIN_AREA Register Field Descriptions ................................................... 20-13
ECC_RSLT_MAIN_AREA Register Field Descriptions ................................................... 20-13
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
lxxviii
Freescale Semiconductor
Tables
Table
Number
19-17
19-18
19-19
19-20
19-21
19-22
19-23
19-24
19-25
19-26
19-27
19-28
19-29
19-30
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11
20-12
20-13
20-14
20-15
20-16
20-17
20-18
20-19
20-20
20-21
21-1
21-2
21-3
21-4
21-5
21-6
Title
Page
Number
ECC_Rslt_Spare_Area Descriptions .................................................................................. 20-14
ECC_Rslt_Spare_Area Descriptions .................................................................................. 20-15
NAND Flash Write Protection Register Field Descriptions ............................................... 20-15
Unlock_Start_Blk_Add Register Field Description............................................................ 20-16
UNLOCK_END_BLK_ADD Register Field Description .................................................. 20-16
NAND_FLASH_WR_PR_ST Register Field Descriptions................................................ 20-16
Write Protected States ......................................................................................................... 20-17
NAND_FLASH_CONFIG1 Register Field Descriptions ................................................... 20-17
NAND_FLASH_CONFIG2 Register Field Descriptions ................................................... 20-18
NAND FLASH Controller Operating Modes ..................................................................... 20-20
NAND Flash Burst Access Support .................................................................................... 20-25
ECC Code/Result Readability............................................................................................. 20-36
Write Protection for Main/Spare RAM Buffer ................................................................... 20-37
Examples for NFC Pin Configuration for Selected Memory Devices ................................ 20-40
PCMCIA Signal Descriptions ............................................................................................... 21-3
BVD1 and BVD2 Descriptions............................................................................................. 21-6
PCMCIA Controller Memory Map...................................................................................... 21-6
Register Figure Conventions ................................................................................................. 21-7
PCMCIA Controller Register Summary ............................................................................... 21-7
PIPR Field Descriptions...................................................................................................... 21-10
PSCR Field Descriptions .................................................................................................... 21-11
PER Field Descriptions ....................................................................................................... 21-12
PBR0–PBR4 Field Descriptions ......................................................................................... 21-14
POR0–POR4 Field Descriptions......................................................................................... 21-15
BSIZE Values ...................................................................................................................... 21-16
BSIZE Mask........................................................................................................................ 21-17
POFR0–POFR4 Field Descriptions .................................................................................... 21-18
PGCR Field Descriptions.................................................................................................... 21-19
PGSR Field Descriptions .................................................................................................... 21-20
PCMCIA I/F Interrupt Sources ........................................................................................... 21-22
Write Protect ....................................................................................................................... 21-23
IOIS16 and PPS Bit Relations ............................................................................................ 21-24
Data and Control Signal Relations...................................................................................... 21-24
Data, Control and Address Relations in TrueIDE Mode .................................................... 21-25
PCMCIA Card TrueIDE Signal Names and Assignments.................................................. 21-26
1-Wire Port Definitions: DS2502.......................................................................................... 22-2
1-Wire Pin Configuration...................................................................................................... 22-2
CRM and API Register Descriptions .................................................................................... 22-3
1-Wire Memory Map ............................................................................................................ 22-5
Register Figure Conventions Key to Register Fields ............................................................ 22-5
1-Wire Register Summary..................................................................................................... 22-6
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
lxxix
Tables
Table
Number
21-7
21-8
21-9
21-10
21-11
22-1
22-2
22-3
22-4
22-5
22-6
22-7
22-8
22-9
22-10
22-11
22-13
22-12
22-14
22-15
22-16
22-17
23-1
23-1
23-2
23-3
23-4
23-5
23-6
23-7
23-8
23-9
23-10
23-11
24-3
24-4
24-5
24-6
24-7
24-8
24-9
Title
Page
Number
Control Register Field Descriptions...................................................................................... 22-8
Time Divider Register Field Descriptions............................................................................. 22-9
System Timing Requirements ............................................................................................. 22-10
System Clock Requirements ............................................................................................... 22-10
Reset Register Field Descriptions ....................................................................................... 22-11
Signal Properties ................................................................................................................... 23-4
ATA Memory Map ................................................................................................................ 23-6
Register Figure Conventions ................................................................................................. 23-7
ATA Register Summary ........................................................................................................ 23-8
ATA TIME_CONFIG0 Register Field Descriptions ........................................................... 23-11
ATA TIME_CONFIG1 Register Field Descriptions ........................................................... 23-12
ATA TIME_CONFIG2 Register Field Descriptions ........................................................... 23-13
ATA TIME_CONFIG3 Register Field Descriptions ........................................................... 23-14
ATA TIME_CONFIG4 Register Field Descriptions ........................................................... 23-15
ATA TIME_CONFIG5 Register Field Descriptions ........................................................... 23-16
ATA FIFO_DATA_32 Register Field Descriptions............................................................. 23-17
FIFO_FILL Register Field Descriptions............................................................................. 23-18
FIFO_DATA_16 Register Field Descriptions ..................................................................... 23-18
ATA Control Register Field Descriptions ........................................................................... 23-19
INT_PENDING Register Field Description ....................................................................... 23-22
ATA FIFO_ALARM Register Field Descriptions .............................................................. 23-23
Drive Registers connected to ATA Bus ............................................................................... 23-23
CSPI Behavior In Master Mode In Various Configurations ................................................. 24-7
CSPI Memory Map ............................................................................................................. 24-12
Register Figure Conventions ............................................................................................... 24-13
CSPI Register Summary ..................................................................................................... 24-13
RXDATA Register Field Descriptions ................................................................................ 24-15
TXDATA Register Field Descriptions................................................................................. 24-16
CONREG Register Field Descriptions................................................................................ 24-17
Interrupt Control/Status Register Description..................................................................... 24-21
TESTREG Register Field Descriptions .............................................................................. 24-23
PERIODREG Register Field Descriptions.......................................................................... 24-25
DMA Register Description ................................................................................................. 24-25
Reset Register Field Description......................................................................................... 24-27
I2C Memory Map .................................................................................................................. 25-4
I2C Register Summary .......................................................................................................... 25-5
I2C Address Register Field Descriptions .............................................................................. 25-6
I2C Frequency Register Field Descriptions........................................................................... 25-7
IFDR Register Field Values .................................................................................................. 25-7
I2C Control Register Field Descriptions ............................................................................... 25-8
I2C Status Register Field Descriptions.................................................................................. 25-9
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
lxxx
Freescale Semiconductor
Tables
Table
Number
24-10
24-11
25-1
25-2
25-3
25-4
25-5
25-6
25-7
25-8
26-1
26-2
26-3
26-4
26-5
26-6
27-1
27-2
27-3
27-4
27-5
27-6
27-7
27-8
27-9
27-10
27-11
27-12
27-13
27-14
27-15
27-16
27-17
27-18
27-19
27-20
27-21
28-1
28-2
28-3
28-4
Title
Page
Number
I2C Data Register Field Descriptions.................................................................................. 25-11
I2C Bus Timing Parameters................................................................................................. 25-18
Keypad Port Column Modes ................................................................................................. 26-3
KPP Memory Map ................................................................................................................ 26-3
Register Figure Conventions ................................................................................................. 26-4
KPP Register Summary......................................................................................................... 26-4
Keypad Control Register Field Descriptions ........................................................................ 26-5
Keypad Status Register Field Descriptions ........................................................................... 26-6
Keypad Data Direction Register Field Descriptions ............................................................. 26-8
Keypad Data Register Field Descriptions ............................................................................. 26-9
MSHC I/O Signals ................................................................................................................ 27-3
MSHC Memory Map ............................................................................................................ 27-4
MSHC Data Endianism and Connection to IP Bus............................................................... 27-4
Timeout Register ................................................................................................................... 27-5
Interrupt Status/Clear Register.............................................................................................. 27-5
Interrupt enable register ........................................................................................................ 27-6
Signal Properties ................................................................................................................... 28-3
Signal Descriptions ............................................................................................................... 28-3
SDHC Memory Map............................................................................................................. 28-3
Register Figure Conventions ................................................................................................. 28-4
SDHC Register Summary ..................................................................................................... 28-5
SDHC Clock Control Register Field Descriptions................................................................ 28-9
SDHC Status Register Field Descriptions........................................................................... 28-10
SDHC Clock Rate Register Field Descriptions .................................................................. 28-15
SDHC Command and Data Control Register Field Description......................................... 28-16
MMC/SD Response Time Out Register Field Descriptions ............................................... 28-18
SDHC Read Time Out Register Field Descriptions............................................................ 28-19
SDHC Block Length Register Field Descriptions .............................................................. 28-21
SDHC Number of Blocks Register Field Descriptions....................................................... 28-22
SDHC Revision Number Register Field Descriptions ........................................................ 28-23
SDHC Interrupt Control Register Field Descriptions ......................................................... 28-24
Interrupt Mechanisms ......................................................................................................... 28-27
SDHC Command Number Register Field Descriptions...................................................... 28-28
SDHC Command Argument Register Field Descriptions .................................................. 28-29
SDHC Response FIFO Register Field Descriptions ........................................................... 28-30
SDHC Buffer Access Register Field Descriptions.............................................................. 28-31
Commands for MMC/SD/SDIO ......................................................................................... 28-54
Interface Signals.................................................................................................................... 29-3
UART Memory Map ............................................................................................................. 29-4
Register Conventions ............................................................................................................ 29-5
UART Register Summary ..................................................................................................... 29-6
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
lxxxi
Tables
Table
Number
28-5
28-6
28-7
28-8
28-9
28-10
28-11
28-12
28-13
28-14
28-15
28-16
28-17
28-18
28-19
28-20
28-21
28-22
28-23
28-24
28-25
28-26
28-27
29-1
29-2
29-3
29-4
29-5
29-6
29-7
29-8
29-9
29-10
29-11
29-12
29-13
29-14
29-15
29-16
29-17
29-18
Title
Page
Number
Receiver Register Field Descriptions.................................................................................... 29-8
UART Transmitter Register Field Descriptions .................................................................... 29-9
UART Control Register 1 (UCR1) Field Descriptions ....................................................... 29-10
UART Control Register 2 Field Descriptions ..................................................................... 29-12
UART Control Register 3 (UCR3) Field Descriptions ....................................................... 29-14
UART Control Register 4 (UCR4) Field Descriptions ....................................................... 29-16
UART FIFO Control Register Description ......................................................................... 29-18
UART Status Register 1 (USR1) Field Descriptions .......................................................... 29-19
UART Status Register 2 Field Descriptions........................................................................ 29-21
UART Escape Character Register Field Descriptions......................................................... 29-23
UART Escape Timer Register (UTIM) Field Descriptions................................................. 29-23
UART BRM Incremental Register Field Descriptions ....................................................... 29-24
UART BRM Modulator Register Field Descriptions.......................................................... 29-25
UART Baud Rate Count Register Field Descriptions ......................................................... 29-25
UART One Millisecond Register Field Descriptions.......................................................... 29-26
UART Test Register Description......................................................................................... 29-27
Interrupts and DMA ............................................................................................................ 29-28
RTS Edge Triggered Interrupt Truth Table ......................................................................... 29-32
Detection Truth Table.......................................................................................................... 29-38
Majority Vote Results.......................................................................................................... 29-39
Baud Rate Automatic Detection ......................................................................................... 29-42
Escape Timer Scaling.......................................................................................................... 29-45
UART Low Power State Operation..................................................................................... 29-49
ECR[ETHER_EN] De-Assertion Effect on FEC.................................................................. 30-5
User Initialization (Before ECR[ETHER_EN]) ................................................................... 30-5
FEC User Initialization (Before ECR[ETHER_EN]) ........................................................... 30-5
Microcontroller Initialization................................................................................................ 30-6
MII Mode .............................................................................................................................. 30-6
7-Wire Mode Configuration.................................................................................................. 30-7
Destination Address to 6-Bit Hash...................................................................................... 30-12
Module Memory Map ......................................................................................................... 30-17
FEC Register Memory Map ................................................................................................ 30-18
MIB Counters Memory Map............................................................................................... 30-19
EIR Field Descriptions........................................................................................................ 30-21
EIMR Field Descriptions .................................................................................................... 30-23
RDAR Field Descriptions ................................................................................................... 30-24
TDAR Field Descriptions.................................................................................................... 30-25
ECR Field Descriptions ...................................................................................................... 30-25
MMFR Field Descriptions .................................................................................................. 30-26
MSCR Field Descriptions ................................................................................................... 30-27
Programming Examples for MSCR .................................................................................... 30-28
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
lxxxii
Freescale Semiconductor
Tables
Table
Number
29-19
29-20
29-21
29-22
29-23
29-24
29-25
29-26
29-27
29-28
29-29
29-30
29-31
29-32
29-33
29-34
29-35
30-1
30-2
30-3
30-4
30-5
30-6
30-7
30-8
30-9
30-10
30-11
30-12
30-13
30-14
30-15
30-16
30-17
30-18
30-19
30-20
30-21
30-22
30-23
30-24
Title
Page
Number
MIBC Field Descriptions .................................................................................................... 30-28
RCR Field Descriptions ...................................................................................................... 30-29
TCR Field Descriptions ...................................................................................................... 30-31
PALR Field Descriptions .................................................................................................... 30-31
PAUR Field Descriptions .................................................................................................... 30-32
OPD Field Descriptions ...................................................................................................... 30-32
IAUR Field Descriptions..................................................................................................... 30-33
IALR Field Descriptions ..................................................................................................... 30-33
GAUR Field Descriptions ................................................................................................... 30-34
GALR Field Descriptions ................................................................................................... 30-34
TFWR Field Descriptions ................................................................................................... 30-35
FRBR Field Descriptions .................................................................................................... 30-35
FRSR Field Descriptions .................................................................................................... 30-36
ERDSR Field Descriptions ................................................................................................. 30-36
EMRBR Field Descriptions ................................................................................................ 30-38
Receive Buffer Descriptor Field Definitions....................................................................... 30-40
Transmit Buffer Descriptor Field Definitions ..................................................................... 30-42
USB Module Memory Map .................................................................................................. 31-4
USB Control Register Field Descriptions ............................................................................. 31-8
Host Port 1 Pin Functions ................................................................................................... 31-11
Host Port 2 Signal Connections .......................................................................................... 31-12
ULPI/ Serial Muxing........................................................................................................... 31-13
Signal Connections ............................................................................................................. 31-14
OTG ULPI/Serial Muxing................................................................................................... 31-15
Port 1 TLL and PHY Mode Pin Connections ..................................................................... 31-18
Port 2 TLL and PHY Mode Pin Connections ..................................................................... 31-18
HOST1 Bypass Mode Pin Functions .................................................................................. 31-20
Interface Register Sets......................................................................................................... 31-23
Configuration, Control, and Status Register Set ................................................................. 31-23
HS-USB Register Summary................................................................................................ 31-27
HWGENERAL ................................................................................................................... 31-31
HWHOST Field Descriptions ............................................................................................. 31-32
HCSPARAMS Field Descriptions ...................................................................................... 31-35
HCCPARAMS Field Descriptions ...................................................................................... 31-37
DCCPARAMS Field Descriptions ...................................................................................... 31-38
GPTIMER0LD Field Descriptions ..................................................................................... 31-39
GPTIMER0LD Field Descriptions ..................................................................................... 31-40
USBCMD—USB Command Register Field Descriptions.................................................. 31-41
USBSTS Field Descriptions................................................................................................ 31-44
USBINTR Field Descriptions ............................................................................................. 31-47
FRINDEX Register Field Descriptions............................................................................... 31-49
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
lxxxiii
Tables
Table
Number
30-25
30-26
30-27
30-28
30-29
30-30
30-31
30-32
30-33
30-34
30-35
30-36
30-37
30-38
30-39
30-40
30-41
30-42
30-43
30-44
30-45
30-46
30-47
30-48
30-49
30-50
30-51
30-52
30-53
30-54
30-55
30-56
30-57
30-58
30-59
30-60
30-61
30-62
30-63
30-64
30-65
Title
Page
Number
PERIODICLISTBASE Register Field Descriptions ........................................................... 31-50
DEVICEADDR Field Descriptions .................................................................................... 31-50
ASYNCLISTADDR Field Descriptions ............................................................................. 31-51
ENDPOINTLISTADDR Field Descriptions....................................................................... 31-52
BURSTSIZE Field Descriptions ......................................................................................... 31-52
TXFILLTUNING Field Descriptions.................................................................................. 31-54
ULPI VIEWPORT Field Descriptions ................................................................................ 31-56
PORTSCx Field Descriptions ............................................................................................. 31-58
OTGSC Field Descriptions ................................................................................................. 31-63
Typ Field Value Definitions ................................................................................................ 31-78
Isochronous Transfer Descriptor......................................................................................... 31-79
Next Schedule Element Pointer .......................................................................................... 31-80
iTD Transaction Status and Control.................................................................................... 31-81
it Buffer Pointer Page 0 (Plus) ............................................................................................ 31-82
iTD Buffer Pointer Page 1 (Plus) ........................................................................................ 31-82
iTD Buffer Pointer Page 2 (Plus) ........................................................................................ 31-82
iTD Buffer Pointer Page 3-6 ............................................................................................... 31-83
Next Link Pointer ................................................................................................................ 31-84
Endpoint and Transaction Translator Characteristics ......................................................... 31-84
Micro-frame Schedule Control ........................................................................................... 31-85
siTD Transfer Status and Control ....................................................................................... 31-85
Buffer Page Pointer List (plus)............................................................................................ 31-87
siTD Back Link Pointer ...................................................................................................... 31-87
D Next Element Transfer Pointer (DWord 0)...................................................................... 31-89
TD Alternate Next Element Transfer Pointer (DWord 1) ................................................... 31-89
qTD Token (DWord 2) ........................................................................................................ 31-90
qTD Buffer Pointer(s) (DWords 3-7) .................................................................................. 31-94
Queue Head DWord 0 ......................................................................................................... 31-95
Endpoint Characteristics: Queue Head DWord 1................................................................ 31-96
Endpoint Capabilities: Queue Head DWord 2 .................................................................... 31-97
Current qTD Link Pointer ................................................................................................... 31-98
Host-Controller Rules for Bits in Overlay (DWords 5, 6, 8 and 9)..................................... 31-99
Default Values of Operational Register Space .................................................................. 31-101
Default Port Routing Depending on EHCI HC CF Bit ..................................................... 31-104
Port Power Enable Control Rules ..................................................................................... 31-107
Behavior During Wake-up Events..................................................................................... 31-110
Example Worse-case Transaction Timing Components ................................................... 31-113
Operation of FRINDEX and SOFV (SOF Value Register)............................................... 31-116
Asynchronous Schedule SM Transition Actions .............................................................. 31-129
Typical Low-/Full-speed Transaction Times..................................................................... 31-130
NakCnt Field Adjustment Rules ....................................................................................... 31-131
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
lxxxiv
Freescale Semiconductor
Tables
Table
Number
30-66
30-67
30-68
30-69
30-70
30-71
30-72
30-73
30-74
30-75
30-76
30-77
30-78
30-79
30-80
30-81
30-82
30-83
30-84
30-85
30-86
30-87
30-88
30-89
30-90
30-91
30-92
30-93
30-94
30-95
30-96
31-1
31-2
31-3
31-4
31-5
31-6
31-7
31-8
32-1
Title
Page
Number
Actions for Park Mode, based on Endpoint Response
and Residual Transfer State.......................................................................................... 31-140
Example Periodic Reference Patterns for Interrupt Transfers with 2ms Poll Rate........... 31-143
Ping Control State Transition Table .................................................................................. 31-144
Interrupt IN/OUT Do Complete Split State Execution Criteria........................................ 31-158
Initial Conditions for OUT siTD's TP and T-count Fields................................................ 31-167
Transaction Position (TP)/Transaction Count (T-Count) Transition Table....................... 31-167
Summary siTD Split Transaction State............................................................................. 31-170
Example Case 2a—Software Scheduling siTDs for an IN Endpoint................................ 31-172
Summary of Transaction Error.......................................................................................... 31-176
Summary Behavior of EHCI Host Controller on Host System Errors.............................. 31-179
Summary of EHCI ............................................................................................................ 31-181
Summary of the conditons of handshakes......................................................................... 31-182
Endpoint Capabilities/Characteristics ............................................................................... 31-188
Next dTD Pointer .............................................................................................................. 31-188
Multiple Mode Control (HCCPARAMS) ......................................................................... 31-189
Next dTD Pointer .............................................................................................................. 31-189
dTD Token ........................................................................................................................ 31-190
dTD Buffer Page Pointer List............................................................................................ 31-190
Device State Diagram ....................................................................................................... 31-192
Device Controller State Information Bits ......................................................................... 31-193
Device Controller Endpoint Initialization ......................................................................... 31-196
Device Controller Stall Response Matrix ......................................................................... 31-196
Variable Length Transfer Protocol Example (ZLT = 0) .................................................... 31-199
Variable Length Transfer Protocol Example (ZLT = 1) .................................................... 31-199
Interrupt/Bulk Endpoint Bus Response Matrix................................................................. 31-200
Isochronous Endpoint Bus Response Matrix .................................................................... 31-205
Device Error Matrix .......................................................................................................... 31-209
Error Descriptions ............................................................................................................. 31-209
High Frequency Interrupt Events ...................................................................................... 31-210
Low Frequency Interrupt Events....................................................................................... 31-210
Error Interrupt Events ....................................................................................................... 31-211
GPT Register Summary ........................................................................................................ 32-4
General Purpose Timer Register Summary........................................................................... 32-5
GPT Control Registers Field Descriptions............................................................................ 32-7
GPT Prescaler Register Description...................................................................................... 32-9
GPT Compare Registers Descriptions ................................................................................ 32-10
GPT Capture Registers Description .................................................................................... 32-11
GPT Counter Register Field Descriptions........................................................................... 32-12
GPT Status Register Field Descriptions.............................................................................. 32-13
i.MX27 External Signals....................................................................................................... 33-3
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
lxxxv
Tables
Table
Number
32-2
32-3
32-4
32-5
32-6
32-7
32-8
32-9
32-10
33-1
33-2
33-3
33-4
33-5
33-6
33-7
33-8
33-9
33-10
33-11
33-12
33-13
33-14
33-15
34-1
34-2
34-3
34-4
34-5
34-6
34-7
34-8
35-1
35-2
35-3
35-4
35-5
36-1
36-2
36-3
36-4
Title
Page
Number
PWM Memory Map .............................................................................................................. 33-4
Register Figure Conventions ................................................................................................. 33-4
PWM Register Summary ...................................................................................................... 33-5
PWMCR Field Descriptions ................................................................................................. 33-6
PWMSR Field Descriptions.................................................................................................. 33-9
PWMIR Field Descriptions................................................................................................. 33-10
PWMSAR Field Descriptions ............................................................................................. 33-11
PWMPR Field Descriptions................................................................................................ 33-11
PWMCNR Field Descriptions ............................................................................................ 33-12
RTC Signal Names List......................................................................................................... 34-3
RTC Register Memory Map.................................................................................................. 34-3
Register Figure Conventions ................................................................................................. 34-4
RTC Register Summary ........................................................................................................ 34-4
RTC Hours and Minutes Counter Register Field Descriptions ............................................. 34-7
RTC Seconds Counter Register Field Descriptions .............................................................. 34-8
RTC Hours and Minutes Alarm Register Field Descriptions................................................ 34-8
RTC Seconds Alarm Register Field Descriptions ................................................................. 34-9
RTC Control Register Field Descriptions ........................................................................... 34-10
RTC Interrupt Status Register Field Descriptions............................................................... 34-11
RTC Interrupt Enable Register Field Descriptions ............................................................. 34-13
RTC Stopwatch Minutes Register Field Descriptions ........................................................ 34-16
RTC Days Counter Register Field Descriptions ................................................................. 34-17
RTC Day Alarm Register Field Descriptions...................................................................... 34-17
Sampling Timer Frequencies .............................................................................................. 34-19
Signal Properties ................................................................................................................... 35-2
WDOG Module Port List ...................................................................................................... 35-3
WDOG Memory Map ........................................................................................................... 35-4
Register Figure Conventions ................................................................................................. 35-4
WDOG Register Summary ................................................................................................... 35-5
WCR Register Descriptions .................................................................................................. 35-6
Watchdog Service Register Description................................................................................ 35-7
Watchdog Reset Status Register Field Descriptions ............................................................. 35-7
AHB-Lite To IP Bus V2.0 Interface Operation (Little Endian)............................................ 36-1
PSR 1–0 Data Bus Size Encoding......................................................................................... 36-3
AIPI1 PSR Setting ................................................................................................................ 36-4
AIPI2 PSR Setting ................................................................................................................ 36-4
i.MX27 AIPI Peripheral Access Sizes and IP Access Types ................................................ 36-5
MAX Memory Map .............................................................................................................. 37-4
Register Figure Conventions ................................................................................................. 37-4
MAX Detailed Register Summary ........................................................................................ 37-5
Master Priority Register (MPR0–MPR2).............................................................................. 37-6
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
lxxxvi
Freescale Semiconductor
Tables
Table
Number
36-5
36-6
36-7
36-8
36-9
36-10
37-1
37-2
37-3
37-4
37-5
37-6
37-7
37-8
37-9
37-10
37-11
37-12
37-13
37-14
37-15
37-16
37-17
37-18
37-19
37-20
37-21
37-22
37-23
37-24
37-25
37-26
38-1
38-2
38-3
38-4
38-5
39-1
39-2
39-3
39-4
Title
Page
Number
Master Priority Register Field Descriptions.......................................................................... 37-6
Alternate Priority Register (MPR0–MPR2).......................................................................... 37-8
Alternate Priority Register Field Descriptions...................................................................... 37-8
Slave General Purpose Control Register Field Descriptions .............................................. 37-10
Alternate Slave General Purpose Control Register Field Descriptions............................... 37-12
Master General Purpose Control Register Field Descriptions ............................................ 37-14
DMA Request Mapping ........................................................................................................ 38-3
DMAC Memory Map............................................................................................................ 38-5
Register Figure Conventions ................................................................................................. 38-7
DMAC Register Summary .................................................................................................... 38-7
DMA Control Register Field Descriptions ......................................................................... 38-11
DMA Interrupt Status Register Field Descriptions............................................................. 38-12
DMA Interrupt Mask Register Field Descriptions.............................................................. 38-13
DMA Burst Time-Out Status Register Description ............................................................ 38-14
DMA Request Time-Out Status Register Field Descriptions ............................................. 38-16
DMA Transfer Error Status Register Field Descriptions .................................................... 38-16
DMA Buffer Overflow Status Register Field Descriptions ................................................ 38-17
DMA Burst Time-Out Control Register Field Descriptions ............................................... 38-18
W-Size Registers Field Descriptions................................................................................... 38-20
X-Size Registers Field Descriptions ................................................................................... 38-21
Y-Size Registers Field Descriptions.................................................................................... 38-22
Channel Source Address Register Field Description .......................................................... 38-24
Channel Destination Address Registers Field Descriptions................................................ 38-24
Channel Count Registers Field Descriptions ...................................................................... 38-25
Channel Control Registers Field Descriptions.................................................................... 38-26
Channel Request Source Select Registers Field Descriptions ............................................ 38-28
Channel Burst Length Registers Field Descriptions ........................................................... 38-29
Channel Request Time-Out Registers Field Descriptions................................................... 38-30
Channel Bus Utilization Control Register Field Descriptions ............................................ 38-31
Channel Counter Register Field Descriptions..................................................................... 38-32
CNNR Value Combinations ................................................................................................ 38-35
CCNR Value Combinations ................................................................................................ 38-35
AUDMUX Memory Map.................................................................................................... 39-14
Register Figure Conventions ............................................................................................... 39-14
AUDMUX Register Summary ............................................................................................ 39-15
Host Port Configuration Register Field Descriptions ......................................................... 39-16
Peripheral Port Configuration Register Field Descriptions ................................................ 39-19
Signals Between CSI and Sensor .......................................................................................... 40-3
Integer Multiples of RxFIFO Full Levels ............................................................................. 40-3
Coding for SAV and EAV ..................................................................................................... 40-6
Coding for Protection Bits .................................................................................................... 40-6
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Tables
Table
Number
39-5
39-6
39-7
39-8
39-9
39-10
39-11
39-12
39-13
40-1
40-2
40-3
40-4
40-5
40-6
40-7
40-8
40-9
40-10
40-11
40-12
40-13
40-14
40-15
41-1
41-2
41-3
41-4
41-5
41-6
41-7
41-8
41-9
41-10
41-11
41-12
41-13
41-14
41-15
41-16
41-17
Title
Page
Number
Representations by F-Bit....................................................................................................... 40-6
CSI Memory Map ............................................................................................................... 40-11
Register Figure Conventions ............................................................................................... 40-11
CSI Register Summary........................................................................................................ 40-12
CSI Control Register 1 Field Descriptions.......................................................................... 40-14
CSI Control Register 2 Description .................................................................................... 40-17
CSI Control Register 3 Field Descriptions.......................................................................... 40-19
CSI Status Register Field Descriptions ............................................................................... 40-20
CSI RX Count Register Field Descriptions ........................................................................ 40-24
Video Codec Hardware Register Memory Map.................................................................... 41-5
Register Conventions ............................................................................................................ 41-5
Video Codec Hardware Register Summary .......................................................................... 41-6
Video Codec Code Run Register Field Descriptions ............................................................ 41-8
Video Codec BIT Boot Code Download Data Register Field Descriptions ......................... 41-8
Video Codec Host Interrupt Request Register Field Descriptions........................................ 41-9
Video Codec BIT Interrupt Clear Register Field Descriptions ........................................... 41-10
Video Codec BIT Interrupt Status Register Field Descriptions .......................................... 41-10
Video Codec BIT Code Reset Register Field Descriptions ................................................ 41-11
Video Codec BIT Current PC Register Field Descriptions................................................. 41-12
Rotation and Mirroring Mode ............................................................................................. 41-13
RunCodStd Register Value for Coding Standard ................................................................ 41-18
Frame Buffer Requirement ................................................................................................. 41-23
Working Buffer Organization.............................................................................................. 41-24
Summary of Buffer Requirement........................................................................................ 41-25
Resize Coefficients for 3:5.................................................................................................... 42-6
Resize Coefficients for 5:3.................................................................................................... 42-7
Resize Coefficients for 4:1.................................................................................................... 42-7
YUV to RGB CSC Equations ............................................................................................... 42-8
RGB Color Width and Offsets ............................................................................................ 42-11
PP Register Memory Map................................................................................................... 42-13
PP Control Register Field Descriptions .............................................................................. 42-14
PP Interrupt Control Register Description .......................................................................... 42-16
PP Interrupt Status Register Field Descriptions.................................................................. 42-17
PP Source Y Address Register Field Descriptions ............................................................. 42-18
PP Source Cb Address Register Field Descriptions............................................................ 42-19
PP Source Cr Address Register Field Descriptions ............................................................ 42-19
PP Destination RGB Frame Start Address Register Description........................................ 42-20
PP Quantizer Start Address Register Description............................................................... 42-21
PP Process Parameter Register Description........................................................................ 42-21
PP Source Frame Width Register Field Descriptions ......................................................... 42-22
PP Destination Display Width Register Description........................................................... 42-23
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
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Tables
Table
Number
41-18
41-19
41-20
41-21
41-22
41-23
41-24
41-25
41-26
41-27
41-28
41-29
41-30
41-31
41-32
41-33
41-34
41-35
41-36
41-37
41-38
41-39
41-40
41-41
41-42
41-43
41-44
41-45
41-46
41-47
41-48
41-49
41-50
41-51
41-52
41-53
41-54
41-55
41-56
41-57
41-58
Title
Page
Number
PP Destination Image Size Register Description ................................................................ 42-24
PP Destination Frame Format Control Register Description.............................................. 42-24
YUV 4:2:2 Configuration Settings...................................................................................... 42-25
PP Resize Table Index Register Field Descriptions ............................................................ 42-26
PP Lock Bit Register Field Descriptions ............................................................................ 42-27
PP CSC COEF_4 Register Field Descriptions.................................................................... 42-28
CSC Coefficient Usage ....................................................................................................... 42-28
PP Resize Coefficient Table Register Field Descriptions ................................................... 42-29
Pre-Processing Block Diagram ........................................................................................... 42-30
Input Data Formats.............................................................................................................. 42-31
Resize Ratios....................................................................................................................... 42-31
Output Formats.................................................................................................................... 42-32
Channel-1 Output Formats and Sizes.................................................................................. 42-34
Channel-2 Output Formats and Sizes.................................................................................. 42-35
YUV to RGB CSC Equations ............................................................................................. 42-36
Loop Mode Ping Pong Registers......................................................................................... 42-37
CSI-PrP Link Internal Signals............................................................................................. 42-42
PrP Register Memory Map.................................................................................................. 42-43
PRP Control Register Field Descriptions............................................................................ 42-45
PRP Interrupt Control Register Field Descriptions............................................................. 42-48
PrP Interrupt Status Register Field Descriptions ................................................................ 42-49
PrP Source Y Address Register Field Descriptions ............................................................ 42-50
PrP Source Cb Address Register Field Descriptions .......................................................... 42-51
PrP Source Cr Address Register Field Descriptions ........................................................... 42-52
PrP Destination RGB1 Start Address Register Field Descriptions..................................... 42-52
PrP Destination RGB2 Start Address Register Field Descriptions..................................... 42-53
PrP Destination Y Address Register Field Descriptions..................................................... 42-54
PrP Destination Cb Address Register Field Descriptions ................................................... 42-54
PrP Destination Cr Address Register Description .............................................................. 42-55
PrP Source Frame Size Register Field Descriptions ........................................................... 42-56
PrP Destination Channel-1 Line Stride Register Field Descriptions .................................. 42-56
PrP Source Pixel Format Control Register Field Descriptions ........................................... 42-57
Example Source Input Pixel Formats.................................................................................. 42-58
PrP CH1 Pixel Format Control Register Field Descriptions............................................... 42-59
Example Channel-1 RGB Output Pixel Format.................................................................. 42-60
PrP Destination Channel-1 Output Image Size Register Field Descriptions ...................... 42-61
PrP Destination CH2 Output Image Size Register Field Description................................. 42-61
PrP Source Line Stride Register Field Descriptions ........................................................... 42-62
YUV to RGB....................................................................................................................... 42-63
For RGB to YUV ................................................................................................................ 42-64
For YUV to RGB ................................................................................................................ 42-64
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Tables
Table
Number
41-59
41-60
41-61
41-62
41-63
41-64
41-65
41-66
41-67
41-68
41-69
41-70
41-71
41-72
41-73
42-1
42-2
42-3
42-4
42-5
42-6
42-7
42-8
42-9
42-10
42-11
42-12
42-13
42-14
42-15
42-16
42-18
42-17
42-19
42-20
42-21
42-22
42-23
42-24
42-25
42-26
Title
Page
Number
For RGB to YUV ................................................................................................................ 42-65
For RGB to YUV ................................................................................................................ 42-65
CSC Equations .................................................................................................................... 42-66
PrP Channel 1 Horizontal Resize Coefficient-1 Register Field Descriptions ..................... 42-67
PrP Channel1 Horizontal Resize Coefficient-2 Register Field Descriptions ...................... 42-68
PrP Channel 1 Horizontal Resize Valid Register Field Descriptions.................................. 42-69
PrP Channel1 Vertical Resize Coefficient-1 Register Field Descriptions........................... 42-70
PrP Channel 1 Vertical Resize Coefficient 2 Register Field Descriptions .......................... 42-71
PrP Channel 1 Vertical Resize Valid Register Field Descriptions ...................................... 42-72
PrP Channel-2 Horizontal Resize Coefficient-1 Register Field Descriptions..................... 42-73
PrP Channel-2 Horizontal Resize Coefficient-2 Field Descriptions ................................... 42-75
PrP Channel-2 Horizontal Resize Valid Register Field Descriptions ................................. 42-76
PrP Channel2 Vertical Resize Coefficient-1 Register Field Descriptions........................... 42-77
PrP Channel 2 Vertical Resize Coefficient 2 Register Field Descriptions .......................... 42-78
PrP Channel 2 Vertical Resize Valid Register Field Descriptions ...................................... 42-79
SSI Operating Modes ............................................................................................................ 43-4
I2S Mode Selection............................................................................................................. 43-15
Data Alignment ................................................................................................................... 43-19
Signal Properties ................................................................................................................. 43-20
Clock Pin Configuration ..................................................................................................... 43-25
Internal I/O Signal Description ........................................................................................... 43-25
SSI Memory Map................................................................................................................ 43-27
Register Figure Conventions ............................................................................................... 43-28
Register Summary ............................................................................................................... 43-29
SSI Transmit Data Register Field Descriptions .................................................................. 43-33
SSI Receive Data Register Field Descriptions.................................................................... 43-36
SSI Control Register Field Descriptions ............................................................................. 43-40
SSI Interrupt Status Register Field Descriptions ................................................................ 43-42
SSI Interrupt Enable Register Field Descriptions ............................................................... 43-46
SSI Transmit Configuration Register Field Descriptions.................................................... 43-48
SSI Receive Configuration Register Field Descriptions ..................................................... 43-49
SSI Data Length .................................................................................................................. 43-52
SSI Transmit and Receive Clock Control Register Field Descriptions............................... 43-52
SSI FIFO Control/Status Register Field Descriptions ........................................................ 43-54
Status of Transmit FIFO Empty Flag.................................................................................. 43-55
SSI Test Register Field Descriptions................................................................................... 43-56
SSI Option Register Field Descriptions .............................................................................. 43-57
SSI AC97 Control Register Field Descriptions................................................................... 43-59
SSI AC97 Command Address Register Field Descriptions ................................................ 43-60
SSI AC97 Command Data Register .................................................................................... 43-61
SSI AC97 Tag Register Field Descriptions ......................................................................... 43-62
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Tables
Table
Number
42-27
42-28
42-29
42-30
42-31
42-32
42-33
42-34
42-35
42-36
42-37
42-38
43-1
43-2
43-3
43-4
43-5
43-6
43-7
43-8
43-9
43-10
43-11
43-12
43-13
43-14
43-15
43-16
43-17
43-18
43-19
43-20
43-21
43-23
43-22
43-24
43-25
43-26
43-27
43-28
43-29
Title
Page
Number
SSI Transmit Time Slot Mask Register Field Descriptions ................................................ 43-63
SSI Receive Time Slot Mask Register Field Descriptions.................................................. 43-64
SSI AC97 Channel Status Register Field Descriptions....................................................... 43-65
SSI AC97 Channel Enable Register Field Descriptions ..................................................... 43-66
SSI AC97 Channel Disable Register Field Descriptions .................................................... 43-67
SSI Bit Clock and Frame Rate as a Function of PSR, PM and DIV2................................. 43-70
SSI System Clock, Bit Clock, Frame Clock in Master Mode............................................. 43-71
SSI Receive Data 1 Interrupts ............................................................................................. 43-72
SSI Receive Data 0 Interrupts ............................................................................................. 43-72
SSI Transmit Data 1 Interrupts ........................................................................................... 43-73
SSI Transmit Data 0 Interrupts ........................................................................................... 43-73
SSI Control Bits Requiring SSI to be Disabled Before Change ......................................... 43-74
Supported Panel Characteristics............................................................................................ 44-2
Gray Palette Density ........................................................................................................... 44-10
Pin Configuration ................................................................................................................ 44-11
TFT Color Channel Assignments ....................................................................................... 44-16
LCDC Memory Map........................................................................................................... 44-18
Register Figure Conventions ............................................................................................... 44-19
LCDC Register Summary ................................................................................................... 44-20
Screen Start Address Register Field Description ................................................................ 44-23
LCDC Size Register Field Descriptions ............................................................................. 44-24
LCDC Virtual Page Width Register Field Descriptions...................................................... 44-25
LCDC Cursor Position Register Field Descriptions ........................................................... 44-26
LCDC Cursor Width Height and Blink Register Field Descriptions .................................. 44-27
LCDC Color Cursor Mapping Register Field Descriptions................................................ 44-28
LCDC Panel Configuration Register Field Descriptions .................................................... 44-29
LCDC Horizontal Configuration Register Field Description ............................................. 44-31
LCDC Vertical Configuration Register Field Descriptions ................................................ 44-32
LCDC Panning Offset Register Field Descriptions ............................................................ 44-33
LCDC Sharp Configuration Register Field Descriptions.................................................... 44-34
LCDC PWM Contrast Control Register Field Description................................................. 44-36
LCDC DMA Control Register Field Descriptions............................................................. 44-37
LCDC Refresh Mode Control Register Field Descriptions ................................................ 44-38
INTSYN/INTCON Settings................................................................................................ 44-39
LCDC Interrupt Configuration Register Field Descriptions ............................................... 44-39
LCDC Interrupt Enable Register Field Description............................................................ 44-40
LCDC Interrupt Status Register Field Descriptions............................................................ 44-41
LCDC Graphic Window Start Address Register Field Descriptions .................................. 44-42
LCDC Graphic Window Size Register Field Descriptions ................................................. 44-43
LCDC Graphic Window Virtual Page Width Register Field Descriptions ......................... 44-44
LCDC Graphic Window Panning Offset Register Field Descriptions ................................ 44-45
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Tables
Table
Number
43-30
43-31
43-32
43-33
43-34
43-35
43-36
43-37
43-38
43-39
44-1
44-2
44-3
44-4
44-5
44-6
44-7
44-8
44-10
44-9
44-11
44-12
44-13
44-14
44-15
44-16
44-17
44-18
44-19
Title
Page
Number
LCDC Graphic Window Position Register Field Descriptions........................................... 44-45
LCDC Graphic Window Control Register Field Descriptions............................................ 44-46
LCDC DMA Control Register Field Descriptions............................................................. 44-47
LCDC AUS Mode Control Register Field Descriptions ..................................................... 44-48
LCDC AUS Mode Cursor Control Register Field Descriptions ......................................... 44-49
Four Bits Per Pixel Gray-Scale Mode ................................................................................. 44-50
Four Bits Per Pixel Passive Matrix Color Mode ................................................................. 44-50
Eight Bits Per Pixel Passive Matrix Color Mode ................................................................ 44-51
Four Bits Per Pixel Active Matrix Color Mode .................................................................. 44-51
Eight Bits Per Pixel Active Matrix Color Mode ................................................................. 44-51
SLCDC Module Pin List....................................................................................................... 45-1
Image Endianness ................................................................................................................. 45-3
SDLC Memory Map ........................................................................................................... 45-14
Register Conventions .......................................................................................................... 45-15
SLCDC Register Summary ................................................................................................. 45-16
Data Buffer Base Address Register Field Description........................................................ 45-18
Data Buffer Size Register Description ................................................................................ 45-18
Command Base Address Register Field Description .......................................................... 45-19
Command String Size Register Field Description .............................................................. 45-20
Command Buffer Size Register Field Description.............................................................. 45-20
FIFO Configuration Register Description........................................................................... 45-21
LCD Controller Configuration Register Field Description................................................. 45-21
LCD Transfer Configuration Register Field Description.................................................... 45-22
SLCDC Control/Status Register Field Description............................................................. 45-24
LCD Clock Configuration Register Field Description........................................................ 45-26
LCD Write Data Register Field Description....................................................................... 45-27
SLCDC Serial Interface Timing.......................................................................................... 45-29
SLCDC Parallel Interface Timing....................................................................................... 45-29
LCD_CLK Frequency Range.............................................................................................. 45-31
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An addendum, entitled Addendum to Rev. 0.3 of MCIMX27
Multimedia Applications Processor Reference Manual (Rev. 0.4)
has been added at the end of this document.
About This Book
The MCIMX27 Multimedia Applications Processor Reference Manual describes the features and operation
of the i.MX27 microprocessor, the seventh generation of the DragonBall family of products. It provides
the details of how to initialize, configure, and program the i.MX27 device. The manual presumes basic
knowledge of ARM926EJ-S™ architecture.
Audience
The MCIMX27 Multimedia Applications Processor Reference Manual is intended to provide a design
engineer with the necessary data to successfully integrate the i.MX27 processor into a wide variety of
applications. It is assumed that the reader has a good working knowledge of the ARM926EJ-S processor.
For programming information about the ARM926EJ-S processor, see the documents listed in the
Suggested Reading section of this preface.
Organization
This reference manual is organized into two books:
1. Book I contains chapters that detail integration information, including the signals, clocks, power
management, muxing tables, and JTAG/Boot operation of the IC.
2. Book II is divided into parts that consist of chapters that cover the operation and programming of
the i.MX27 device.
Suggested Reading
The following documents are recommended for a complete description of the i.MX27 Multimedia
Applications Processor, and enable proper design with the i.MX27 device. Especially for those not familiar
with the ARM926EJ-S processor or previous DragonBall products, the following documents will be
helpful when used in conjunction with this manual.
• AMBA AHB specifications, (ARM Ltd.)
• ARM926EJ-S Platform specifications (also named ARM926p Platform)
• Hip7a KiloBit Single Port HP SRAM Compiler, MEMCTC (May 8, 2002)
• Hip7A SAMI ROM Compiler, MEMCTC (November 16, 2001)
• Hip7A KiloBit HD VIA ROM Compiler, MEMCTC (June 28, 2002)
• ARM926EJ-S Platform Test Guide (ARM Ltd.)
• ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)
• ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)
• ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
xciii
•
•
MC9328MX1 i.MX Integrated Portable System Processor Reference Manual (order number
MC9328MX1RM)
MCIMX27 Multimedia Application Processor Data Sheet—(order number MCIMX27))
These manuals can be found at the ARM Ltd. World Wide Web site at http://www.arm.com and Freescale
Semiconductors World Wide Web site at http://www.freescale.com/imx. These documents can be
downloaded directly from the World Wide Web site, or printed versions may be ordered. The World Wide
Web site may also have useful application notes.
Conventions
This reference uses the following conventions:
• OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
• Logic level one is a voltage that corresponds to Boolean true (1) state.
• Logic level zero is a voltage that corresponds to Boolean false (0) state.
• To set a bit or bits means to establish logic level one.
• To clear a bit or bits means to establish logic level zero.
• A signal is an electronic construct whose state conveys or changes in state convey information.
• A pin is an external physical connection. The same pin can be used to connect a number of signals.
• Asserted means that a discrete signal is in active logic state.
— Active low signals change from logic level one to logic level zero.
— Active high signals change from logic level zero to logic level one.
• Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
• LSB means least significant bit or bits, and MSB means most significant bit or bits. References to
low and high bytes or words are spelled out.
• Numbers preceded by a percent sign (%) are binary. Numbers preceded by a 0x are hexadecimal.
Definitions, Acronyms, and Abbreviations
The following list defines acronyms and abbreviations used in this document.
ADC
analog-to-digital converter
AFE
analog front end
API
application programming interface
BCD
binary coded decimal
BER
bit error ratio
CGM
clock generation module
CMOS
complimentary metal-oxide semiconductor
CRC
cyclic redundancy check
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CSIC
DAC
DDR RAM
DMA
DRAM
DSP
FEC
FIFO
FIRI
GPIO
I/O
ICE
IrDa
JTAG
MAP
MAPBGA
MIPS
MMC
PLL
PWM
RTC
SD
SDRAM
SPI
SRAM
TQFP
UART
USB
USB OTG
XTAL
BE/LE
CCM
LV
LWB
MCTL
complex instruction set computer
digital-to-analog converter
double data rate RAM
direct memory access
dynamic random access memory
digital signal processor
forward error correction
first in first out
fast IR interface
general purpose input/output
Input/Output
in-circuit emulation
infrared data association
joint test action group
mold array process
mold array process ball grid array
million instructions per second
multimedia card
phase locked loop
pulse-width modulator
real-time clock
secure digital
synchronous dynamic random access memory
serial peripheral interface
static random access memory
thin quad flat pack
universal asynchronous receiver/transmitter
universal serial bus
USB On-The-Go
crystal
big endian/little endian
clock control module, also called “clkctl” module
low voltage
late-write buffer
memory controller
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RAM
ROM
R-AHB bus
SRAM
ARM
API
Fabrication Path
Flash Path
GPCR
HW
iRAM
iROM
NFC
NAND Flash
ROM Bootstrap
RAM Path
SIDR
Sync Flash
TBD
UART
USB
V-Sync Flash
Word
TYPE
UID
WTLS
random access memory
read only memory
reduced advanced high-performance bus (AHB), related to ARM bus architecture
static RAM
Advanced RISC Machines processor architecture
Application Programming Interface
Path within ROM Bootstrap for fabrication test execution
Path within ROM Bootstrap leading towards executing a Flash application.
Global Peripheral Control Registry of the i.MX27.
Hardware
Processor-internal RAM
Processor-internal ROM
NAND Flash Controller
A Flash ROM Technology
Internal boot code encompassing main boot flow as well as exception vectors,
USB/UART Bootloader blocks.
Path within ROM Bootstrap leading towards downloading and executing a RAM
application
Silicon ID Register of the i.MX27
A Flash ROM Technology
To Be Determined
Universal Asynchronous Receiver/Transmitter
Universal Serial Bus
A Flash ROM Technology
32 bits
Identifier that distinguishes a production or engineering device.
Unique ID; a field in the processor and CSF identifying a device or group of
devices
Wireless Transport layer Security, a part of the Wireless Application Protocol
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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Book I:
i.MX27 Applications Processor Integration and
Description
Introduction
Book I comprises detailed descriptions and information on the integration of the i.MX27 Multimedia
Applications Processor. Book I includes the following chapters.
Device Introduction and Memory Map
Chapter 1, “Introduction to the i.MX27 Multimedia Applications Processor,” on page 1-1
Chapter 2, “System Memory and Register Map,” on page 2-1
Clocks, Power Management and Reset
Chapter 3, “Clocks, Power Management, and Reset Control,” on page 3-1
Pins
Chapter 4, “System Control,” on page 4-1
Chapter 5, “Signal Descriptions and Pin Assignments,” on page 5-1
Chapter 6, “General-Purpose I/O (GPIO),” on page 6-1
Debug
Chapter 7, “JTAG Controller (JTAGC),” on page 7-1
Boot
Chapter 8, “Bootstrap Mode Operation,” on page 8-1
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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Chapter 1
Introduction to the i.MX27 Multimedia Applications
Processor
As part of the i.MX growing family of multimedia-focused products, the i.MX27 Multimedia Applications
Processor takes the Mobile Multimedia Experience to another level. Whether you are designing mobile
entertainment, a smartphone, wireless PDA, or any other portable device, the i.MX27 processor offers a
high degree of integration to significantly reduce your design time while providing low-power
consumption with performance to spare, and the flexibility necessary for today’s competitive marketplace.
The i.MX27 processor is packaged in a 404-pin MAPBGA.
Differentiating features of the i.MX27 device include:
• Advanced and power-efficient implementation of the ARM926EJ-S™ core, operating at speeds up
to 400 MHz
• enhanced Multimedia Accelerator Lite (eMMA_lt)—MPEG-4 and H.264 hardware encode or
decode up to D1 resolution at 30 fps or encode and decode up to VGA resolution at 24 fps.
• High-Speed USB On-The-Go controller, host or client
• Smart Speed Crossbar Switch—Multi-layer AMBA-compliant bus allows any one of the six bus
masters to talk to any of the three slaves without interfering with the other bus master/slave
transactions to provide system level parallelism.
• PCMCIA/Compact Flash Interface—Supports hot-insertion, card insert, and removal detection
• Security—Software and hardware combined security solution allows secure e-commerce, digital
rights management (DRM), information encryption, secure boot, and secure software downloads.
• Smart Power Management—Includes Run, Doze, and Sleep modes, frequency scaling, active well
biasing and clock gating
• LCD panels—Supports both smart and standard LCD panels
• Fast Ethernet—Supports 10/100 baseT Ethernet MAC
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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1-1
Introduction to the i.MX27 Multimedia Applications Processor
1.1
i.MX27 Applications Processor Block Diagram
Figure 1-1 is a simplified functional block diagram of the i.MX27 processor.
System Control
Connectivity
JTAG/ETM9
i.MX27
CSPI (3)
Bootstrap
SSI (2)
CRM
2
I C (2)
System Security
SCC
CPU Complex
Wireline
UART (6)
MAX
(Smart Speed Switch)
ARM926EJ-S
SAHARA2
RTIC
I-Cache
D-Cache
MMU
Internal Control
Bus Control
Memory Control
IIM
USB 2.0
1-WIRE
FEC
ATA
Multimedia Accelerator
External
Memory Interface
Std System Resource
Video Codec
GPT (6)
eMMA Lite
M3IF
PWM
Expansion
SDRAMC
WDOG
SDHC (3)
EIM
SRTC
NFC
GPIO
LCDC and SLCDC
PCMCIA/CF
SDMA
Keypad Control
MSHC
Multimedia Interface
CSI
Human Interface
Figure 1-1. i.MX27 Processor Functional Block Diagram
1.2
Summary of Core and Modules
This section describes the ARM926EJ-S as it applies to the i.MX27 processor and the function of the
modules within the i.MX27 device.
1.2.1
ARM9™ Platform
The ARM9™ Platform consists of the ARM926EJ-S core, operating at speeds up to 400 MHz at 1.6 V,
and 266 MHz at 1.2 V. The ARM926EJ-S core includes a 16-Kbyte level 1 (L1) cache system, a 6 × 3
multi-layer AHB crossbar switch, and a 16 channel DMA.
The ARM926EJ-S is a member of the ARM9 family of general-purpose microprocessors targeted at
multi-tasking applications. The ARM9 Platform provides the following features:
• ARM926EJ-S microprocessor core
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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Introduction to the i.MX27 Multimedia Applications Processor
—
—
—
—
—
—
—
•
•
•
•
•
•
•
16K instruction cache and 16K data cache
High-performance ARM® 32-bit RISC engine
Thumb® 16-bit compressed instruction set for a leading level of code density
Efficient execution of Java byte codes
EmbeddedICE™ JTAG software debug
100% user code binary compatibility with ARM7TDMI™
Advanced Microcontroller Bus Architecture (AMBA™) system-on-chip multi-master bus
interface
— Support for mixed loads of real-time and user applications via cache locking facilities
— Virtual Memory Management Unit (VMMU)
Support for Little Endian only
CPU and System speed
— ARM926EJ-S core: up to 400 MHz
— System Clock: up to 133 MHz
— External memory interface: same clock source as system, up to 133 MHz at 1.8 V supply
— System clock is derived from the CPU clock through an integer divider
ARM Interrupt Controller (AITC)
— The AITC is connected to the primary AHB as a slave device and provides support for up to
64 interrupt sources. It generates normal and fast interrupts to the processor core. The AITC
supports a hardware-assisted vectoring mode for automatic vectoring to reduce interrupt
latency.
Clock Control Module (CLKCTL)—The CLKCTL performs block level clock gating,
ARM926EJ-S JTAG synchronization requirements, as well as other miscellaneous clock control
for the platform.
AHB to IP bus interfaces (AIPIs)—Provide a communication interface between the high-speed
AHB to a lower-speed IP bus for slave peripherals
The Multi-Layer 6 × 3 AHB Crossbar Switch (MAX)—The crossbar switch allows for concurrent
transactions to proceed from any input port (bus master) to any output port (bus slave): That is, it
is possible for all three output ports to be active at the same time as a result of three independent
input or output requests.
Well Bias Charge Pump (WBCP)—With the exception of the memories, the entire ARM9 Platform
supports two active well biasing to reduce leakage current to minimum levels. The well bias enable
inputs (wt_en and wt_en_dnw) are driven by the external Well Bias Charge Pump (WBCP) to the
ARM9 Platform.
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1.2.2
System Control
To ensure optimum power use and clock signal stability, the i.MX27 processor uses the following modules
to generate, control, and distribute clock and control signals throughout the i.MX27 processor and to
external devices.
1.2.2.1
Clock Controller Module (CCM)
The CCM generates clock and reset signals used throughout the i.MX27 device and for external
peripherals. It also enables system software to control, customize, or read the status of the following
functions:
• Chip ID
• Multiplexing of I/O signals
• I/O driving strength
• I/O pull enable control
• Well bias control
• System boot mode selection
• DPTC control
1.2.2.2
JTAG Controller (JTAGC)
The JTAGC provides debug access to the ARM926EJ-S core and boundary scan test control. The i.MX27
processor offers designers and programers with full-debug capabilities through industry-standard JTAG
interface and the ability to bootload using either a serial or USB interface.
• UART Bootstrap mode function:
— Allows system initialization and program or data download to system memory via USB or
UART1
— Accepts execution command to run program stored in system memory
— Supports memory/register read/write operation of selectable data size of byte, half-word, or
word
— Provides a 16-byte instruction buffer for ARM instruction storage and execution
• USB Bootstrap mode function
— Supports bootstrapping through USB OTG port
• JTAG port to support generic ARM debug tools
1.2.3
Standard System Resources
The i.MX27 processor contains various timers and resource features to optimize the control and security
of both the internal modules and external devices.
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1.2.3.1
General Purpose Timer (GPT)
The six General-Purpose Timer (GPT) modules contain identical general-purpose 32-bit timers with
programmable prescalers and compare and capture registers with the following features:
• Automatic interrupt generation
• Programmable timer input/output pins
• Input capture channels capability with programmable trigger edge for each GPT
• Output compare channels with programmable mode for each GPT
1.2.3.2
Pulse-Width Modulator (PWM)
The Pulse-Width Modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored
sample audio images. It also generate tones.
The following features characterize the PWM module:
•
•
•
4 × 16 FIFO to minimize interrupt overhead
16-bit resolution
Sound and melody generation
1.2.3.3
Real Time Clock (RTC)
The Real-Time Clock (RTC) module maintains the system clock, provides stopwatch, alarm, and interrupt
functions, and supports the following features:
• 32.768 kHz and 32 kHz input operation
• Full clock features: seconds, minutes, hours, days
• Capable of counting up to 512 days
• Minute countdown timer with interrupt
• Programmable daily alarm with interrupt
• Sampling timer with interrupt
• Once-per-second, once-per-minute, once-per-hour, and once-per-day interrupts
• Interrupt generation for digitizer sampling or keyboard debouncing
• Independent power supply
1.2.3.4
Watchdog Timer Module (WDOG)
The Watchdog Timer module (WDOG Timer) module protects against system failures by providing a
method for the system to recover from unexpected events or programming errors. The WDOG timer
module also generates a system reset using a software write to the Watchdog Control Register (WCR), a
detection of a clock monitor event, an external reset, an external JTAG reset signal, or an occurrence of a
power-on reset.
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The WDOG Timer provides the following:
• Programmable time out of 0.5 s to 64 s
• Resolution of 0.5 s
1.2.3.5
General-Purpose I/O Ports (GPIO)
The GPIO module provides six general purpose I/O ports. Each single GPIO port is a 32-bit port that may
be multiplexed with one or more dedicated functions. The GPIO features are:
• Supports level or edge trigger interrupt and is system wake-up capable
• Most I/O signals are multiplexed with dedicated functions for pin efficiency.
1.2.3.6
Direct Memory Access Controller (DMAC)
The Direct Memory Access Controller (DMAC) provides 16 channels to support linear memory, 2D
memory, FIFO, and end-of-burst enable FIFO transfers to support a wide variety of DMA operations.
Features include the following:
• Supports 16 channels linear memory, 2D memory, and FIFO for both source and destination
• Supports 8-bit, 16-bit, or 32-bit FIFO port size and memory port size data transfer
• DMA burst length is configurable up to maximum of 16 words, 32 half-words, or 64 bytes for each
channel
• Bus utilization control for a channel that is not triggered by DMA request
• Interrupts that are provided to interrupt handler on bulk data transfer complete or transfer error
• DMA burst time-out error to terminate DMA cycle when the burst cannot be completed in a
programmed timing period
• Dedicated external DMA request and grant signal
• Supports increment, decrement, and no increment for source and destination addressing
• Supports DMA chaining
1.2.4
Power Management and Backup Modes
The i.MX27 processor’s power management features are as follows:
• SupportS 3 power modes of operation: Run, Doze, and Stop
• Aggressive clock gating within modules to minimize CMOS switching power
• Active well biasing technique to reduce standby mode current consumption
• Voltage/frequency scalable capability
• Dynamic process temperature compensation
1.2.4.1
SCC, RTC, and Oscillator Power Supply
The i.MX27 processor has a separate power domain from the main power domain for the SCC, RTC, and
the 32 kHz oscillator (OSC32K) power supply, so that when the main power domain shuts down, the SCC
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internal memory data and status is maintained. Also, the RTC and OSC32K works as normal using the
backup power supply that is provided by power management.
1.2.4.2
Enter/Exit Mode
Power management provides the power_cut to indicate the main power cut: 1—main power_cut; 0—main
power_on.
• Mode Enter—When power_cut is set to 1 by the power management chip, then the main power can
shut down.
• Mode Exit—power_cut must be set to 1 when the main power is not on; after main power_on is
restored (after the main power reset ends), power_cut should be set to 0.
• Power On Initial—In the initial process, power_cut must be set to 0, and POR must give a valid 0
slot for the SCC, RTC power_on reset.
1.2.4.3
Reset Strategy
The POR is active to the RTC and SCC. When power_cut is set to 1 (in the backed power mode), then the
reset from the chip system will be gated, preventing any chip reset sources from resetting SCC and RTC.
When power_cut is set to 0 (not in the backed power mode), then the reset from the chip system will be
active to SCC and RTC, which means all chip reset sources can reset the SCC and RTC.
1.2.5
System Security
To address the need for secure wireless communication, the i.MX27 processor provides confidentiality,
authentication, integrity, and legitimacy within its architecture. This section describes the modules that
provide these types of security—the Security Controller, SAHARA2, Run-Time Integrity Checker, and the
IC Identification Module—whose built-in features support a broad range of security-enabled products.
1.2.5.1
Security Controller Module (SCC)
The SCC is a hardware component composed of two blocks—the Secure RAM module and the Security
Monitor. The Secure RAM securely stores sensitive information. The Security Monitor implements the
security policy, checking algorithm sequencing, and controlling the Secure State. There is also a unique
encryption key accessible only to secure RAM.
1.2.5.2
Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2)
SAHARA2 is a security co-processor within the i.MX27 processor used to implement block encryption
algorithms, hashing algorithms, stream cipher algorithms, and hardware random number generation.
SAHARA2 accelerates the following security protocols and their features:
• AES encryption/decryption
— ECB, CBC, CTR, and CCM modes
— 128 bit key
• DES/3DES
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•
•
— EBC, CBC, and CTR modes
— 56 key with parity (DES)
— 112 bit or 168 bit key parity (3DES)
AR4 (RC4 compatible cipher)
— 5–16 byte key
— Host accessible S-box
MD5, SHA-1, SHA-224 and SHA-256 hashing algorithms
— Message lengths are multiples of bytes
— Auto padding supported
— HMAC (support for IPAD and OPAD via descriptors)
— Up to 4-Gbyte message length
Random number generator (NIST approved PRNG – FIPS 186-2)
— Entropy is generated via an independent free running ring oscillator
1.2.5.3
Run-Time Integrity Checkers (RTIC)
The RTIC ensures the integrity of the contents of the peripheral memory and assists with boot
authentication.
The RTIC offers the following features:
• SHA-1 message authentication
• Input DMA (AMBA-AHB Lite1 bus master) interface
• Segmented data gathering to support non-contiguous data blocks in memory (up to two segments
per block)
• Works with High Assurance Boot (HAB) process
• Secure-scan DFT security
• Support for up to four independent memory blocks
• Programmable DMA bus duty cycle timer and watchdog timer
• Power-saving clock gating logic
• Hardware configurable Big/Little-Endian data format
• Full word memory reads (word-aligned addresses, multiple of 32-bit lengths)
1.2.5.4
IC Identification Module (IIM)
The IC Identification Module (IIM) provides an interface for reading, and in some cases, programming,
and for overriding identification and control information stored in on-chip fuse elements.
1. AHB-Lite interface provides support for request/grant bus arbitration
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1.2.6
Connectivity
This section describes how the modules within the i.MX27 processor interface with each other, and
provides a high-level overview on how the architecture of the buses are configured and multiplexed.
GPS
UART3
Bluetooth
UART4
IrDA
UART5
IrDA
UART6
USB
OTG
USB
Host 1
USB
Host 2
Serial
EEPROM
EtherNet
1-Wire
FEC
INTERNAL CONNECTIVITY
i.MX27
ATA
CPU
ROMPATCH
ETM
CRM
MAX
RTIC
External
Memory
Interface
(EMI)
SD
Secure
Digital
MSHC
Memory
Stick Pro
ESDRAM
EIM
NFC
ETB
PCMCIA/CF
JTAGC
DMAC
MULTIMEDIA
Video Codec
ATAPI
IDE
Hard Drive
SCC
SECURITY
SSI2
M3IF
UART2
CSPI2 SAHARA2
MEMORY
EXPANSION
IrDA
SSI1
CSPI1
MEMORY
UART1
AUDMUX
EXTERNAL CONNECTIVITY
RS-232
IrDA
I2C
IIM
I2C
Audio SSI
Voice SSI
Bluetooth
MPEG-4
H.264
eMMA_lt
HUMAN INTERFACE
CSI
SLCDC
LCDC
KPP
CCIR656
Camera
Smart
Displays
Dumb
Display
KeyPad
Linear
FIFO
2D
Figure 1-2. i.MX27 Connectivity Example
1.2.6.1
Configurable Serial Peripheral Interfaces (CSPI)
The i.MX27 processor has three Configurable Serial Peripheral Interface (CSPI) modules that allow rapid
data communication with fewer software interrupts than conventional serial communications. Each CSPI
is equipped with data FIFO and is a master/slave configurable serial peripheral interface module, enabling
the i.MX27 processor to interface with external SPI master or slave devices.
• Master/slave configurable
• Two chip-selects each for master mode operation
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•
Up to 16-bit programmable data transfer
8 × 16 FIFO for both transmit and receive data
1.2.6.2
Inter-IC Connectivity (I2C) Bus Module
The two I2C modules are two-wire, bidirectional serial buses that provide a simple, efficient method of
data exchange, minimizing the interconnection between devices. These buses are suitable for applications
requiring occasional communications over a short distance between several devices. The flexible I2C
allows additional devices to be connected to the bus for expansion and system development. The I2C
features include:
• Multiple-master operation
• Software-programmable for 1 of 64 different serial clock frequencies
• Interrupt-driven, byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation and detection
• Repeated START signal generation
• Acknowledge bit generation and detection
• Bus-busy detection
1.2.6.3
Synchronous Serial Interface (SSI)
The two synchronous serial interfaces are full-duplex, serial ports that enable the i.MX27 device to
communicate with a variety of serial devices, such as standard codecs, digital signal processors (DSPs),
microprocessors, peripherals, and popular industry audio codecs that implement the inter-IC sound bus
standard (I2S) and Intel AC97 standard.
Features include the following:
• Supports generic SSI interface for timeslot based communication with synchronous voice codecs
• Timeslot mode supports up to four channels for communication among devices, Bluetooth™ voice
port, voice codecs, and baseband audio ports.
• Supports Philips standard Inter-IC Sound (I2S) bus for external digital audio chip interface at
44.1 kHz and 48 kHz
• AC97 Host Controller mode with support for two audio channels supporting fixed and variable rate
transfers
• Used together with the Digital Audio Mux (AUDMUX) module to provide flexible audio and voice
routing options
1.2.6.4
Bus Control
The six modules that control the bus in the MX27 are listed here. This section provides a brief description
for each.
• AHB-Lite IP Interface Module (AIPI)
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•
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ARM926EJ-S Interrupt Controller (AITC)
Intellectual Property Bus Multiplexer (IPMUX)
Multi-layer AHB Crossbar Switch (MAX)
1.2.6.4.1
AHB-Lite IP Interface Module (AIPI)
The AIPI acts as an interface between the ARM Advanced High-performance Bus Lite. (AHB-Lite) and
lower bandwidth peripherals that conform to the IP Bus Specification, Rev 2.0.
1.2.6.4.2
ARM926EJ-S Interrupt Controller (AITC)
AITC is connected to the primary AHB as a slave device. It generates the normal and fast interrupts to the
ARM926EJ-S processor.
1.2.6.4.3
Intellectual Property Bus Multiplexer (IPMUX)
The Intellectual Property Bus Multiplexer (IPMUX) is used to select the read data, transfer wait, and
transfer error signals from the various modules and pass it to the AIPI in the ARM9 Platform.
1.2.6.4.4
Multi-Layer AHB Crossbar Switch (MAX)
The ARM926EJ-S core’s instruction and data buses and all alternate bus master interfaces arbitrate for
resources via a 6 × 3 Multi-Layer AHB Crossbar Switch (MAX)—also known as a Smart Speed Switch.
There are six fully functional master ports (M0–M5) and three fully functional slave ports (S0–S2). The
MAX is uni-directional. All master and slave ports are AHB-Lite compliant.
1.2.7
Wireline Connectivity
The i.MX27 device provides a variety of external wireline connectivity. This section describes the modules
for this support.
1.2.7.1
Universal Asynchronous Receiver/Transmitter (UART)
The i.MX27 processor includes six Universal Asynchronous Receiver/Transmitter (UART) modules that
provide serial communication with external devices through either an RS-232 cable or by using
IrDA-compatible infrared.
Each of the six UARTs features the following:
• Supports serial data transmit/receive operation: 7 or 8 data bits, 1 or 2 stop bits, programmable
parity (even, odd, or none)
• Programmable baud rates up to 4.125 Mbps.
• Automatic baud rate detection
• 32-bytes FIFO for transmit and 32 half-words FIFO for receive data
• IrDA Serial Infra-Red (SIR) mode support
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1.2.7.2
High Speed USB 2.0 Interface (USB)
The i.MX27 processor supports three independent USB 2.0 ports, two of which support high speed (HS)
operation:
• OTG—High speed (480 Mbps)
• Host 1—Full speed (12 Mbps)
• Host 2—High speed (480 Mbps)
The USB connectivity of the i.MX27 processor provides extremely fast synchronization with a PC or
between two devices. Any of the USB ports may be used for transceiver-free connection or for external
transceiver-based connection.
The USB OTG port can connect to a PC as either a device or as a host to any of the following peripherals:
keyboard, printer, mouse, speakers, storage device, digital camera, and so on. It supports 16 endpoints for
each host and device.
USB Host 1 is typically connected to dedicated ICs that support WLAN, Bluetooth™ wireless technology,
and GPS. Host 1 supports 16 endpoints. USB Host 2 is typically used to connect to ICs for baseband or
WLAN, Bluetooth wireless technology, or GPS. Host 2 supports four endpoints.
1.2.7.3
1-Wire Interface (1-Wire)
The 1-Wire® module provides bi-directional communication between the ARM926EJ-S and the
Add-Only-Memory EPROM (DS2502). The 1-Kbit EPROM is used to hold information about the battery
and to communicate with the ARM9 Platform using the IP interface.
1.2.7.4
Advanced Technology Attachment (ATA)
The Advanced Technology Attachment (ATA) block of the i.MX27 processor is an AT attachment host
interface and is used to interface with IDE hard disk drives and ATAPI optical disk drives. This feature
allows designers to attach storage devices at low costs per unit, which is a critical selling point in the
portable digital player market. The ATA controller interfaces with ATA devices using the industry-standard
ATA-6 specification.
The ATA interface is compliant to the ATA-6 standard, and supports following protocols:
• PIO mode 0, 1, 2, 3, and 4
• Multiword DMA mode 0, 1, and 2
• Ultra DMA modes 0, 1, 2, 3, and 4 with bus clock of 50 MHz or higher
• Ultra DMA modes 5 with bus clock of 80 MHz or higher
1.2.7.5
Fast Ethernet Controller (FEC)
The Fast Ethernet Controller (FEC) performs the full set of IEEE 802.3/Ethernet CSMA/CD media access
control and channel interface functions. The FEC supports connection and functionality for the 10/100
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Mbps 802.3 Media Independent Interface (MII). It requires an external transceiver (PHY) to complete the
interface to the media. The FEC provides the following features:
• Supports three different Ethernet physical interfaces:
— 100 Mbps IEEE 802.3 MII
— 10 Mbps IEEE 802.3 MII
— 10 Mbps 7-wire interface (industry standard)
• IEEE 802.3 full-duplex flow control
• Programmable maximum frame length supports IEEE 802.1 VLAN tags and priority
• Supports full-duplex operation (200 Mbps throughput) with a minimum system clock rate of
50 MHz
• Supports half-duplex operation (100 Mbps throughput) with a minimum system clock rate of
25 MHz
• Retransmission from transmit FIFO following a collision (no processor bus utilization)
• Automatic internal flushing of the receive FIFO for runts (collision fragments) and address
recognition rejects (no processor bus utilization)
• Address recognition
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
1.2.8
External Memory Interface
The External Memory Interface (EMI) of the i.MX27 processor consists of the SDRAM controller
(SDRAMC), the PCMCIA controller, the NAND Flash controller (NFC), and the External Interface
module (EIM), using the Multi-Master Memory Interface (M3IF) as the controller through the external
memory ports. The individual features of these controllers are provided in this section.
To allow the maximum number of potential designs, the EMI supports the following memory types:
• SDRAM—133 MHz, 32/16-bit
• DDR—266 MHz, 32/16-bit
• NAND Flash—dedicated 8-bit, shared 16-bit
• PSRAM
1.2.8.1
Multi-Master Memory Interface (M3IF)
The Multi-Master Memory Interface (M3IF) controls memory accesses from one or more masters through
different port interfaces to the external memory controllers SDRAM, PCMCIA, NAND Flash, and EIM.
The M3IF includes these distinctive features:
• Supports multiple requests from masters through input port interfaces
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•
•
•
•
•
Arbitrates requests to the different memory controllers
Multiple requests capabilities to SDRAMC through a dedicated arbitration mechanism
Flexible round robin access arbitration, with a programmable priority scheme to selective masters
Programmable master that controls (locks) accesses to SDRAM/DDR, and a programmable master
that controls (locks) accesses to other memories (NFC, EIM)
Multi-endianness support for all memory controllers
Supports memory “snooping”—that is, monitors a region in external memory for write accesses
1.2.8.2
SDRAM Controller (SDRAMC)
The SDRAM Controller (SDRAMC) provides an interface and control for synchronous DRAM memories
for the system. The SDRAMC supports the following:
• Optimization of consecutive memory accesses using memory command anticipation (latency
hiding)
— Hiding latency (or “command anticipation”) by optimizing the commands to both connected
chip-selects
— Monitoring open memory pages
— Bank-wise memory address mapping
— SDRAM burst length configuration of 41 or 8 bursts or full-page mode
— MDDR burst length configuration of 8 bursts
— Support of different internal burst length (1/4/8 words) by using burst truncate commands
— ARM/AMBA/AHB-Lite compliant
— Shared address and command bus to SDRAM/MDDR
• Supports 64, 128, 256, 512 Mbit, 1 Gbit, and 2 Gbit, 4 bank, single data rate, synchronous
SDRAM, and MDDR
— Two independent chip-selects
— Up to 128 Mbytes per chip-select
— Up to four banks active simultaneously per chip-select
— JEDEC standard pinout/operation
• Supports mobile DDR266 devices (both 16-bit and 32-bit)
• PC133 compliant interface
— 133-MHz system clock achievable with “–7” option PC133 compliant memories
— Single fixed-length (4/8-word) burst or full page access
— Access time of 9-1-1-1-1-1-1-1 at 133 MHz (for read access when the memory bus is available,
the row is open and CAS latency configured to three cycles). The access time includes the
M3IF delay (assuming there is no arbitration penalty).
• Software configurable for different system and memory devices requirements
— 16-bit or 32-bit memory data bus width
1. For 16-bit memory burst length 4 is not supported.
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•
— Many row and column addresses
— Row cycle delay (tRC)
— Row precharge delay (tRP)
— Row-to-column delay (tRCD)
— Column-to-data delay (CAS latency)
— Load mode register to active command (tMRD)
— Write to precharge (tWR)
— Write to read (tWTR) for MDDR memories only
— MDDR exit power down to next valid command delay (tXS)
— Active to precharge (tRAS)
— Active to active (tRRD)
Built-in auto-refresh timer and state machine
Hardware and software supported self-refresh entry and exit
— Keeps data valid during system reset and low-power modes
— Auto Power Down timer (one per chip-select)
— Auto Precharge timer (one per bank in each chip-select)
1.2.8.3
NAND Flash Controller (NFC)
The NAND Flash controller (NFC) interfaces standard NAND Flash memory devices to the i.MX27
processor and hides the complexities of accessing NAND Flash. The NFC features include:
• Contains hardware boot loader for automatic boot up from NAND Flash devices
• Supports all 8-bit/16-bit NAND Flash devices regardless of density and organization
• Supports 512-byte and 2-Kbyte page sizes
• Internal 2 Kbytes of buffer RAM used as boot RAM during cold startup and as read/write page
buffers to relieve CPU intervention
• Automatic ECC detection and selectable correction
• Data protection for RAM buffer and NAND Flash pages
1.2.8.4
Personal Computer Memory Card International Association (PCMCIA)
The PCMCIA host adapter module provides the control logic for PCMCIA socket interfaces, and requires
some additional external analog power switching logic and buffering.
The PCMCIA controller provides the following features:
• A host adapter interface fully compliant with the PCMCIA standard release 2.1 (PC Card -16)
— Supports one PCMCIA socket
— Supports hot-insertion
— Supports card detection
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•
— Mappings to common memory space, attribute memory space, and I/O space. Each space is up
to 64 Mbytes in size.
— Supports five memory windows
— Generates a single interrupt to the CPU
— PC card access timing is fully programmable
— Handles interrupts from the card
The pcmcia_if signal is part of the EMI complex and shares pins with the EIM, SDRAMC, and
NFC controller.
Supports ATA disk emulation
1.2.8.5
External Interface Module (EIM)
The External Interface Module (EIM) interfaces to devices external to the chip, including generation of
chip-selects, clock and control for external peripherals, and memory. The EIM provides asynchronous and
synchronous access to devices with an SRAM-like interface.
The EIM includes the following features:
•
•
•
•
•
•
•
•
•
•
•
•
Six chip-selects for external devices, with CS [0] and CS [1] each covering a range of 128 Mbytes,
and CS [2] – CS [5], each covering a range of 32 Mbytes
CS [0] range can be increased to 256 Mbytes when collapsed with CS [1]
Selectable protection for each chip-select
Programmable data port size for each chip-select
Asynchronous accesses with programmable setup and hold times for control signals
Synchronous Memory Burst Read Mode support for AMD, Intel, and Micron burst flash memory
Synchronous Memory Burst Write Mode support for PSRAM (CellularRAMTM from Micron,
Infineon, and Cypress)
Support for multiplexed address/data bus operation
External cycle termination/postpone with DTACK signal
Programmable wait-state generator for each chip-select
Support for Big Endian and Little Endian modes of operation per access
ARM AHB slave interface
1.2.9
Memory Expansion
The i.MX27 processor offers memory expansion options for SD, Memory Stick Pro®, and ATA-6. Each
expansion port reflects the latest version of the respective specification for that interface. Brief
descriptions of each expansion port follow.
1.2.9.1
Memory Stick Host Controller (MSHC)
The i.MX27 processor’s Memory Stick Host Controller supports one Memory Stick Pro slot. The MSHC
conforms to Memory Stick Standard Format Specifications, ver.1.4-00 and Memory Stick Standard
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Memory Stick PRO Format Specification, ver.1.00-01. The MSHC communication is based on an
advanced 7-pin serial bus designed to operate in a low-voltage range. In addition to multimedia cards, the
module can be used to communicate to high-bit rate communication devices, such as WLAN 802.11 a/b,
and Bluetooth wireless technology, among others. The MSHC is placed between the AIPI and the customer
memory stick to support data transfer from the i.MX27 device to the customer memory stick.
1.2.9.2
Secured Digital Host Controller (SDHC)
The three Secured Digital Host Controllers (SDHC) in the i.MX27 device control the Secure Digital
memory cards and I/O functions by sending commands to the cards and performing data accesses to and
from the cards.
SDHC features include:
• Fully compatible with the SD Memory Card Specification 1.0 and SD I/O Specification 1.0 with
1 and 4 channel(s)
• Supports hot swappable operation
• Data rates from 25 Mbps to 100 Mbps
• Dedicated power pin
1.2.10
Video Codec and enhanced Multimedia Accelerator Lite (eMMA_lt)
The i.MX27 processor uses a Video Codec and an enhanced Multimedia Accelerator Lite (eMMA_lt) to
provide H.264, MPEG-4 and H.263 hardware acceleration with pre- and post-processing.
1.2.10.1
Video Codec
The Video Codec module supports full-duplex video codec with MPEG-4 and H.264 hardware encode or
decode up to D1 resolution at 30 fps or encode and decode up to VGA resolution at 24 fps, and integrates
multiple video processing standards, such as H.264 BP, MPEG-4 SP, and H.263 P3. The Video Codec
architecture is shown in the Figure 1-3.
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CRM
ahb64_sel
Clock and Reset
32bit
AXI
Video Processing IP
AXI to AHB bus
Read
Channel
1 and 2
Logic
Memories Block
64bit
32to64
Gasket
64bit
EMI
Write
Channel
Logic
Memory Bist
Engine
64bit
APB to IP Bus
32 bit
Test
Signal
Internal SRAM
AIPI
Interrupt
Signal
Figure 1-3. Video Codec Architecture Diagram
The Video Codec provides the following capabilities:
• Multi-standard video codec
— MPEG-4 part-II Simple Profile (SP) encoding/decoding
— H.264/AVC Baseline Profile (BP) encoding/decoding
— H.263 P3 encoding/decoding
— Multi-party call: One stream encoding and two streams decoding simultaneously
— Multi-format: Encodes MPEG-4 bitstream, and decodes H.264 bitstream simultaneously
• Coding tools
— High-performance motion estimation (single reference frame for both MPEG-4 and H.264
encoding)
– Quarter-pel and half-pel accuracy motion estimation
– [±16, ±16] search range
— All variable block sizes are supported. (In case of encoding, 8 × 4, 4 × 8, and 4 × 4 block sizes
are not supported.)
— Unrestricted motion vector
— MPEG-4 AC/DC prediction and intra-prediction (H.264)
— H.264/AVC intra-prediction
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•
•
•
— H.263 Annex I, J, K, and T are supported
— Error resilience tools
– MPEG-4 resync. marker and data-partitioning with RVLC (fixed number of
bits/macroblocks between macroblocks)
– H.264/AVC FMO and ASO
– H.263 slice structured mode
– Bit-rate control (CBR and VBR)
Pre/post rotation/mirroring
— 8 rotation/mirroring modes for image to be encoded
— 8 rotation/mirroring modes for image to be displayed
Programmability
— Embeds C and M proprietary 16-bit DSP processor that is dedicated to processing bitstream
and driving the codec hardware
— General purpose registers and interrupt for communication between internal host processor and
Video Codec IP
Performance
— Up to full-duplex VGA 24 fps encoding/decoding
— Up to half-duplex SD 30 fps encoding/decoding
1.2.10.2
enhanced Multimedia Accelerator Lite (eMMA_lt)
The i.MX27 processor comes with an enhanced Multimedia Accelerator Lite (eMMA_lt), which
comprises independent pre-processing and post-processing stages that provide exceptional image and
video quality. The eMMA_lt represents a major breakthrough to solve the problem of high MIPS required
for video encode and decode operations in mobile and wireless applications. Tight integration and memory
pipelining coupled with AHB master mode operation ensure minimal system loading. To further offload
the CPU, live video stream data enters the eMMA_lt module directly through an internal private data
interface.
The i.MX27 processor’s eMMA_lt features the following:
• Enables simultaneous MPEG-4 Simple Profile (SP) video encoding and decoding
• Supports real-time video decode in any of the following advanced formats:
— MPEG-4 Simple Profile (SP)
— H.264
• Provides video and image data pre/post-processing (resizing, color conversion, filtering) that is
fully hardware accelerated
The eMMA_lt architecture is shown in Figure 1-4.
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Introduction to the i.MX27 Multimedia Applications Processor
IP bus
IP bus Interface
Post
Pre-
Processing
Processing
Sensor data
From CSI
Bus Arbitration
AHB bus
Figure 1-4. eMMA_lt Architecture
1.2.10.2.1
Image Pre-Processor (PrP)
The image Pre-Processor block performs color space conversion and image resizing for the viewfinder
display, and data formatting for the video encoder. It also performs color space conversions of the still
image for input to either a hardware- or software-based video encoder or image compressor. The
Pre-Processor has two media input and output paths and can accept input from system memory or from a
private data bus connected to the CMOS Sensor Interface (CSI) module. The Pre-Processor can apply
frame rate control on the live video stream from the CSI module to adjust for different processing load
conditions. The Pre-Processor’s two output channels are used to output RGB data for display of the local
camera view and to output image data for compression by the hardware encoder or a software encoder (still
image or video encode). Figure 1-5 shows the image Pre-Processor.
System
Memory
CMOS
Sensor
Interface
Main
Color Space
Resize
Conversion
Second
Resize
Frame
Compression
4:2:2,4:2:0,
4:4:4
or video encode
RGB
Display
Viewfinder
Buffer
Buffer
(RGB/YUV)
YUV
Pre-Processor
Optional data paths using dumb CMOS sensors
Figure 1-5. Pre-Processor Data Flow
Pre-Processor features:
• Data input:
— System memory
— Private DMA between CMOS Sensor Interface module and Pre-Processor
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•
•
•
•
•
Data input formats:
— Arbitrarily unpacked RGB input
— YUV 4:2:2 (Interleaved)
— YUV 4:2:0 (Planar)
Input image size: 2044 × 2044
Image scaling:
— Main resize ratio: 8:1–1:1 in integral steps, Horizontal 9:8/vertical 6:5 and Horizontal
9:8/Vertical 1:1
— Secondary resize ratio for viewfinder: 8:1–1:1 in integral steps
Output data format:
— RGB565
— YUV 4:2:2 (Interleaved)
— YUV 4:2:0 (Planar)
RGB data and one YUV data format can be generated concurrently
1.2.10.2.2
Post-Processor (PP)
The Post-Processor performs Deblock, Dering, Image Resize, and Color Space Conversion (CSC)
functions on the input image data. These functions provide flexibility to meet various RGB formats and
YUV formats for display. In addition to working in tandem with the decoder sub-block in the eMMA_lt,
the Post-Processor can also be used by software decoders (other than MPEG-4) to touch up the final output
before display. The sub-blocks that perform Deblock, Dering, Resize, and CSC operations can be
selectively bypassed through software configuration. Figure 1-6 shows the flow for video postprocessing.
MPEG-4
Decoder
Current/
Ref
Post-Processor
Frame
Deblock
Dering
Image
Color
Resize
Conversion
RGB
Display
Buffer
Current/
Ref
Frame
Figure 1-6. Post-Processor
Post-Processor features:
• Input data:
— From system memory
• Input format:
— YUV 4:2:0 (Planar)
• Output format:
— YUV422
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•
•
— RGB444
— RGB565
— RGB666
— RGB888 (unpacked)
Input Size: Maximum size of 2044 × 2044
Image Resize:
— Upscaling ratios ranging from 1:1 to 1:4 in fractional steps
— Downscaling ratios ranging from 1:1 to 2:1 in fractional steps and a fixed 4:1
— Ratios provide scaling between QCIF, CIF, QVGA (320 × 240) and QVGA (240 × 320)
1.2.10.3
Digital Audio Multiplexer (AUDMUX)
The Digital Audio Multiplexer (AUDMUX) provides a programmable interconnect fabric for voice, audio,
and synchronous data routing between the i.MX27 processor’s SSI modules and external SSI, audio, and
voice codecs. The AUDMUX is designed so that resource configurations do not need to be hard-wired, but
instead, can be shared in many different configurations. The AUDMUX interconnections allow multiple
simultaneous separate audio/voice/data flows between the ports in a point-to-point or point-to-multipoint
configuration(s).
In a typical scenario, the AUDMUX and two SSI/I2S modules provide interfaces to the Serial Audio Port
of the cellular baseband (BB), narrowband (NB), and wideband (WB) audio ports of the external audio
AD/DA, and to the audio port of the Bluetooth wireless technology on-board peripheral. See Figure 1-7.
Power
Management
IC
Alert Tone
i.MX27
i.MX31/i.MX31L
Voice Notes NB
Voice Notes
Baseband
IC Voice
BB
SSI2
SAP
Port 2
Port44
Port
Port 4
(External)
(External)
(External)
Voice
Codec
BluetoothTM
IC Voice
Port55
Port
Port 5
(External)
(External)
(External)
Stereo
DAC
ADC/DAC
Audio
Blue
tooth
ADC/DAC
Voice
Port66
Port
Port 6
(External)
(External)
(External)
IO MUX
Port 1
AUDMUX
i.MX27
i.MX31/i.MX31L
WB SSI1
MP3
MP3
Port77
Port
Port 7
(External)
(External)
(External)
Port 3
Option
Voice Call
Figure 1-7. Typical AUDMUX Application
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Introduction to the i.MX27 Multimedia Applications Processor
1.2.11
MultiMedia Interface
The CMOS Sensor Interface (CSI) provides multimedia interfacing.
1.2.11.1
CMOS Sensor Interface (CSI)
The CMOS Sensor Interface (CSI) is a logic interface that enables the i.MX27 device to connect directly
to external CMOS sensors and a CCIR656 video source.
The sensor port provides a connection to either one or two image sensors, of which only one sensor can be
active at any given time. The sensor port supports a direct parallel interface to either CMOS or CCD sensor
controllers using a parallel interface with widths of 12 bits, 10 bits, 8 bits, or 4 bits at data bus rates up to
60 MHz. The sensor port may be configured to perform outputs of a still image to a non-contiguous
memory buffer, enabling efficient memory use under an open OS.
The capabilities of the CSI include:
• Configurable interface logic to support common available CMOS sensors in the market
• Support traditional sensor timing interface
• Support CCIR656 video interface, progressive mode for smart sensor, interlace mode for PAL and
NTSC input
• 8-bit input port for YCC, YUV, Bayer, or RGB data
• 32 × 32 FIFO storing image data supporting core data read and DMA data burst transfer to system
memory
• Full control of 8-bit and 16-bit data to 32-bit FIFO packing
• Direct interface to the eMMA_lt Pre-Processing block (PrP)
• Single interrupt source to the interrupt controller from maskable sensor interrupt sources: Start of
Frame, End of Frame, Change of Field, FIFO full
• Configurable master clock frequency output to sensor
• Asynchronous input logic design. Sensor master clock can be driven by either the i.MX27
processor or by an external clock source.
• Statistic data generation for Auto Exposure (AE) and Auto White Balance (AWB) control of the
camera (for Bayer data only)
1.2.12
Human Interface
The i.MX27 processor can connect to a wide variety of popular display devices, such as:
• RAM-less LCD panels—up to 40 Mpix/s (for example, SVGA @ 80 fps), 262k colors. Results are
dependent on end application.
• LCD panels with integrated frame buffer—up to 1024 × 1024, 14M colors. Results are dependent
on end application.
• Graphics accelerators
• TV encoders
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The i.MX27 processor’s display ports enable simultaneous connectivity of up to two displays—an LCD
without memory and a TV encoder—as well as provides connectivity to three interface types:
• Synchronous parallel (18-bit)
• Asynchronous parallel (18-bit)
• Asynchronous Serial (SPI-like) at a bus rate of up to 100 MHz
1.2.12.1
Liquid Crystal Display Controller (LCDC)
The Liquid Crystal Display Controller (LCDC) provides display data for external gray-scale or color LCD
panels. The LCDC features include the following:
• Software programmable screen size (up to 800 × 600) to support single (non-split) monochrome,
color STN panels, and color TFT panels
• Support for color depth for CSTN panels: 4- or 8-bit mapping from 256 × 18 table, 12-bit true color
• Support for color depth for TFT panels: 4- or 8-bit mapping from 256 × 18 table,
16-bit/18-bit/24-bit true color
• Up to 16 grey levels out of 16 palettes
• Capable of directly driving popular LCD drivers from manufacturers including Motorola, Sharp,
Hitachi, and Toshiba
• Support for data bus width of 16-bit or 18-bit TFT panels
• Support for the AUO panel in 16 bpp and 24 bpp pixel modes
• Support for data bus widths of 8-bit, 4-bit, 2-bit, and 1-bit monochrome LCD panels
• Direct interface to Sharp® 320 × 240 and 240 × 320 HR-TFT panels and other generic panels
• Support for logical operation between color hardware cursor and background
• LCD contrast control using 8-bit PWM
• Support for self-refresh LCD modules
• Hardware panning (soft horizontal scrolling)
• Windowing support for one graphic or text overlay
1.2.12.2
Smart Liquid Crystal Display Controller (SLCDC)
The Smart Liquid Crystal Display Controller (SLCDC) transparently and efficiently transfers image data
from system memory to an external LCD controller. The SLCDC module contains a DMA controller that
transfers image and control data from system memory to the SLCDC FIFO, where it is formatted and sent
out to the external LCD controller.
The SLCDC can be configured to write image data to an external LCD controller via a 4-line serial, 3-line
serial, or 8- or 16-bit parallel interface. The SLCDC has two FIFOs where command and display data are
loaded via DMA. The display data is tagged with commands that are used by the SLCDC to communicate
display information and data to the Smart LCD panel.
The command tagged data format of the SLCDC provides flexibility and ease of connection to existing
and new smart LCD panels.
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Introduction to the i.MX27 Multimedia Applications Processor
1.2.12.3
Keypad Port (KPP)
The Keypad Port (KPP) is used for key pad matrix scanning or as a general purpose I/O. This peripheral
simplifies the software task of scanning a keypad matrix. Features include:
• Up to 8 × 8 external key pad matrix support
• Open drain design
• Glitch suppression circuit prevents erroneous key detection
• Multiple keys detection
• Standby key press detection
1.2.13
Packaging Information
The i.MX27 processor is offered in the 404 MAPBGA package option. This package brings out all the new
interfaces, and supplies more flexible multiplexing.
•
•
•
Type: 0.65 mm pitch
Dimensions: 17 mm × 17 mm
Balls: 404
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Chapter 2
System Memory and Register Map
2.1
Introduction
This chapter provides the i.MX27 Multimedia Applications Processor’s memory maps and chip
configuration registers.
2.2
Memory Space
The i.MX27 Multimedia Applications Processor, with a 32-bit address bus, is capable of addressing a
4-Gbyte physical address space. This space is divided into sections of 512-Mbyte regions within which
various memories and peripherals are mapped.
Table 2-1 shows a simplified breakdown of the eight 512-Mbyte regions decoded within the 4-Gbyte
address space.
Table 2-1. 4 Gbyte Memory Map Breakdown
Address
2.2.1
Size
Usage
0x00000000
512 Mbyte
ROM, Primary AHB Slaves, and Peripherals
0x20000000
512 Mbyte
Reserved
0x40000000
512 Mbyte
Reserved
0x60000000
512 Mbyte
Reserved
0x80000000
512 Mbyte
Secondary AHB Slave Port 1
0xA0000000
1 Gbyte
Secondary AHB Slave Port 2
0xE0000000
512 Mbyte
Primary AHB (RAM)
Detailed Memory Map
Figure 2-2 shows the memory space breakout view for the i.MX27 processor. The left-most column shows
the eight 512-Mbyte regions. The middle column shows the breakout of primary and secondary AHB
slaves, and the right-most column shows the breakout of the AIPI1 and AIPI2 address spaces.
Table 2-2 through Table 2-5 show the detailed breakdown of the complete memory map according to the
512-Mbyte regions. Table 2-6 and Table 2-7 show the detailed breakdown of the AIPI1 and AIPI2 modules
and the different IP peripherals accessed over the AIPI1 and AIPI2.
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System Memory and Register Map
WB
Audio Voice
BT
CE
SSI 2
SSI 1
[16]
IIM SLID
RAM
[12,13]
SCC
MU
MU
MU
OWIRE
CSPI 1
CSPI 2
CSPI 3
[14]
[15]
[23]
[17]
[9]
IP Bus 2
[22]
WDOG
Interrupt
[2] WDOG
[21]
GPIO
GPIO
KPP
8x8 Keypad
MU
MPLL
MU
IPMUX
IP Bus 1
MU
OSC32K
MU
IPMUX
AUDMUX
2 1 0
Battery Ctl
Pulse Width
Mod. In/Out
[8]
OSC26M
SPLL
ARM926
PLATFORM
AITC
CLKCTL
CRM
Primary AHB
ETM9
RTC
IP bus
ETM
ARM926EJ-S
D-$
D-AHB
I-$
I-AHB
LCDC
SROUTER
[1]
FEC
TMAX
10/100baseT
PHY
MSHC
To CRM
[19]
[11]
TCU
[20]
[30]
JTAGC
64-bit TMAX
[3]
0
1
2
3
4
5
6
7
UART1
[4]
[10]
SCC, CRM, SAHARA2
[11]
IrDA
SDHC1
MMC/SD
Card
SDHC2
MMC/SD
Card
SDHC3
MMC/SD
Card
PCMCIA
PCMCIA/CF
NFC
NAND Flash
WEIM
NOR-Flash
SDRAM
ESDCTL
(SDR and DDR)
UART2
IIM
[29]
[8]
UART3
I2C2
MU
i.MX27
[12]
IrDA
M3IF
IrDA/WLAN
BB + RF
Memory Stick
MS/Pro
EMI
Video Codec
USB2.0
Hard Drive
MU
TMAX
LCD
Display 2
ATA
[24]
MU
TMAX
[2]
CSI
MCU M2
Internal 45 Kbyte 24 Kbyte
Memory RAM
ROM
[10]
RTIC
SLCDC
6x3 MAX
m0 S0
m1 S1
m2 S2
m3
m4
m5
ARM926EJ-S Platform
DMA
Camera
IP bus
I-AHB Patch
D-AHB Patch
[6]
I2C1
PAHBMUX
ROMPATCH
SAHARA2
LCD
Display 1
JAM
ABCD
[5]
[1]
PWM
[18]
IP bus
ETB
[7]
eMMA_lt
[6]
MCTL AIPI 1 AIPI 2
JTAG SYNC
[7]
USB ctl
[13]
MU
IrDA
UART4
[27]
[28]
[3]
[4]
[5]
[25]
[26]
[31]
UART 5
UART 6
GPT 1
GPT 2
GPT 3
GPT 4
GPT 5
GPT 6
MU
MU
IrDA
IPC
MU
MU
COLOR
LEGEND
MCU MemoryMapped Module
Other Modules like test, PLLs or
memories (all sizes in KByte)
DMA
LEGEND
Module
without DMA
Module with
internal DMA
MU
PAD-MUX
LEGEND
MU
MUX
MU
MU
Functional pad
muxing with other
peripherals in some
modes
Module with
DMA-req to DMA
Module with internal DMA
and DMA-req to DMA
Figure 2-1. Detailed Block Diagram for the i.MX27 Processor
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System Memory and Register Map
NOTE
Accesses to locations defined as Reserved (other than aliased RAM space)
result in an AHB error response. Accesses to unimplemented locations
within the AITC register spaces will be terminated, write accesses will have
no effect, and read accesses will return all zeros.
Table 2-2 shows the memory map of the Primary AHB address space in the first 512-Mbyte region.
Table 2-2. Primary AHB Memory Map (Lower)
Address
Secondary AHB Slave Port 1
Size
0x0000 0000–0x0000 3FFF
BROM
16 Kbyte
0x0000 4000–0x0040 3FFF
Reserved
4 Mbyte
0x0040 4000–0x0040 5FFF
BROM
8 Kbyte
0x0040 6000– 0x007F FFFF
BROM (Hole)
3 Mbyte + 1000 Kbyte
0x0080 0000–0x0FFF FFFF
Reserved
248 Mbyte
0x1000 0000–0x1001 FFFF
AIPI1
128 Kbyte
0x1002 0000–0x1003 FFFF
AIPI2
128 Kbyte
0x1004 0000–0x1004 0FFF
AITC
4 Kbyte
0x1004 1000– 0x1004 1FFF
ROM Patch
4 Kbyte
0x1004 2000–0x7FFF FFFF
Reserved
255 Mbyte + 752 Kbyte
Table 2-3 shows the memory map of the CSI and ATA modules when connected to the Secondary AHB
Ports 1 via the ABCD. The BROM (hole) is split into two sections of 16 Kbytes and 8 Kbytes. The BROM
(Hole) indicates that there is no BROM code present in this region. The AIPI1 and AIPI2 address space
contains AIPI control registers and the IP slave registers. The AIPI1 and AIPI2 maps are shown in
Table 2-6 and Table 2-7, respectively.
Table 2-3. Secondary AHB Port 1 Memory Map
Address
Secondary AHB Port 1
Size
0x8000 0000–0x8000 0FFF
CSI
4 Kbyte
0x8000 1000–0x8000 1FFF
ATA
4 Kbyte
0x8000 2000–0x9FFF FFFF
Reserved
512 Mbyte–8 Kbyte
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System Memory and Register Map
Figure 2-2 shows the i.MX27 processor’s physical memory map (4 Gbytes).
Base Address
0x1002 0000
0x1002 0FFF
16 Kbyte
0x0000 0000
0x1000 0000
BROM
0x0000 3FFF
128 Kbyte
0x1000 0000
0x1000 1000
AIPI1
4 Mbyte
0x1000 0FFF
0x1000 1FFF
0x0000 4000
0x1000 2000
Reserved
0x0040 3FFF
0x1001 FFFF
0x1002 0000
4 Mbyte 16 Kbyte
0x0040 4000
0x1003 1FFF
0x1004 0000
BROM
0x007F FFFF
248 Mbyte
0x0080 0000
Reserved
0x1004 0FFF
0x1004 1000
0x1004 1FFF
128 Kbyte
72 K byte
AIPI2
Reserved 36 K
20 K byte
AITC
0x1000 2FFF
0x1000 3000
0x1000 3FFF
0x1000 4000
4 Kbyte
0x1000 4FFF
0x1000 5000
4 Kbyte
0x1000 5FFF
0x1000 6000
ROM Patch
0x1000 6FFF
0x1000 7000
0x0FFF FFFF
0x1000 7FFF
264 Kbyte
0x1000 0000
0x1000 8000
Internal
Registers
0x1000 8FFF
0x1000 9000
0x1004 1FFF
0x1000 9FFF
0x1004 2000
0x1000 A000
256 Mbyte -
Reserved
280 Kbyte
256 Mbyte
0xA000 0000
0x1000 B000
CSD0
(SDRAM)
active low
0x1FFF FFFF
0xAFFF FFFF
0xB000 0000
0x2000 0000
0x1000 BFFF
0x1000 C000
256 Mbyte
0x1000 DFFF
0x1000 E000
128 Mbyte
Reserved
0xC7FF FFFF
0xC800 0000
0x1000 FFFF
0x1001 0000
128 Mbyte
CS1
(Flash)
active low
0x1001 1FFF
0x1001 2000
32 Mbyte
0xD1FF FFFF
0xD200 0000
0x8000 0000
0x9FFF FFFF
0xA000 0000
CSI (4KB)
ATA(4KB)
Reserved
External
Memory
(960 Mbyte)
0xDFFF FFFF
0x1001 4000
32 Mbyte
0x1001 5FFF
0x1001 6000
32 Mbyte
CS4
(Spare)
active low
0x1001 7FFF
0x1001 8000
32 Mbyte
511 Mbyte
0xE000 0000
0x1001 9FFF
0x1001 A000
64 Mbyte
979 Kbyte
0xFFFF 4BFF
0xFFFF 4C00
0xFFFF FFFF
Reserved
VRAM
(45 Kbyte)
0xDBFF FFFF
0xDC00 0000
0x1001 BFFF
0x1001 C000
Reserved
64 Mbyte
0x1001 CFFF
0x1001 D000
45 Kbyte
PCMCIA/CF
0xDFFF FFFF
0x1001 AFFF
0x1001 B000
EMI Modules
5X4 KByte
Reserved
0xFFEF FFFF
0xFFF0 0000
0x1001 8FFF
0x1001 9000
CS5
(Spare)
active low
0xD7FF FFFF
0xD800 0000
0x1001 6FFF
0x1001 7000
0xD5FF FFFF
0xD600 0000
Reserved
0x1001 4FFF
0x1001 5000
0xD3FF FFFF
0xD400 0000
Reserved
EMI (20 Kbyte)
0x1001 3FFF
CS3
(Spare)
active low
1 Gbyte
0x1001 2FFF
0x1001 3000
CS2
(Ext SRAM)
active low
512 Mbyte
0x1001 0FFF
0x1001 1000
0xCFFF FFFF
0xD000 0000
0x7FFF FFFF
0x1000 EFFF
0x1000 F000
CS0
(Flash)
active low
1536MB
0x1000 CFFF
0x1000 D000
CSD1
(SDRAM)
active low
0xBFFF FFFF
0xC000 0000
0x1000 AFFF
0x1001 DFFF
0x1001 E000
0x1001 EFFF
0x1001 F000
0x1001 FFFF
0x1002 1000
AIPI1
AIPI2
DMA
LCDC
WDOG
SLCDC
GPT1
H.264
GPT2
USB2.0
GPT3
SAHARA2
PWM
eMMA_lt
RTC
CRM
KPP
IIM
OWIRE
Reserved
UART1
RTIC
UART2
FEC
UART3
SCC
UART4
SCC
CSPI1
Reserved
CSPI2
Reserved
SSI1
Reserved
SSI2
Reserved
I2C1
Reserved
SDHC1
Reserved
SDHC2
Reserved
GPIO
Reserved
0x1002 1FFF
0x1002 2000
0x1002 2FFF
0x1002 3000
0x1002 3FFF
0x1002 4000
0x1002 4FFF
0x1002 5000
0x1002 5FFF
0x1002 6000
0x1002 6FFF
0x1002 7000
0x1002 7FFF
0x1002 8000
0x1002 8FFF
0x1002 9000
0x1002 9FFF
0x1002 A000
0x1002 AFFF
0x1002 B000
0x1002 BFFF
0x1002 C000
0x1002 CFFF
0x1002 D000
0x1002 DFFF
0x1002 E000
0x1002 EFFF
0x1002 F000
0x1002 FFFF
0x1003 0000
0x1003 0FFF
0x1003 1000
0x1003 1FFF
0x1003 2000
0x1003 2FFF
0x1003 3000
0x1003 3FFF
0x1003 4000
0x1003 4FFF
0x1003 5000
0x1003 5FFF
0x1003 6000
0x1003 6FFF
0x1003 7000
AUDMUX Reserved
0x1003 7FFF
0x1003 8000
CSPI3
Reserved
MSHC
Reserved
GPT4
Reserved
GPT5
Reserved
UART5
ETB Regs
UART6
ETB RAM
0x1003 8FFF
0x1003 9000
0x1003 9FFF
0x1003 A000
0x1003 AFFF
0x1003 B000
0x1003 BFFF
0x1003 C000
0x1003 CFFF
0x1003 D000
0x1003 DFFF
0x1003 E000
I2C2 CS5
ETB RAM
(Spare)
active
SDHC3 low
JAM
GPT6
0x1003 EFFF
0x1003 F000
0x1003 FFFF
MAX
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-4
Freescale Semiconductor
System Memory and Register Map
Figure 2-2. i.MX27 Processor’s Physical Memory Map (4 Gbytes)
Table 2-4 shows the memory map breakdown for the Secondary AHB Port 3. The SDRAMC, WEIM,
PCMCIA, and NFC module control registers and external memory are addressed via this region. The
external memory regions (memory or external peripherals) are accessed via the respective chip selects.
CSD1 and CSD0 are SDRAMC chip selects, and CS5 to CS0 are WEIM chip selects. CSD1 and CS0 chip
select spaces are available for external boot. 0xBC000 0000 to 0xDFFF_FFFF is allocated for PCMCIA
IO and memory space.
Table 2-4. Secondary AHB Port 2 Memory Map
Address
Secondary AHB Port 3
Size
0xA000 0000–0xAFFF FFFF
External SDRAM/MDDR (CSD0)
256 Mbyte
0xB000 0000–0xBFFF FFFF
External SDRAM/MDDR (CSD1)
256 Mbyte
0xC000 0000–0xC7FF FFFF
WEIM External Memory (CS0)
128 Mbyte
0xC800 0000–0xCFFF FFFF
WEIM External Memory (CS1)
128 Mbyte
0xD000 0000–0xD1FF FFFF
WEIM External Memory (CS2)
32 Mbyte
0xD200 0000–0xD3FF FFFF
WEIM External Memory (CS3)
32 Mbyte
0xD400 0000–0xD5FF FFFF
WEIM External Memory (CS4)
32 Mbyte
0xD600 0000–0xD7FF FFFF
WEIM External Memory (CS5)
32 Mbyte
0xD800 0000–0xD800 0FFF
NFC registers and internal RAM
4 Kbyte
0xD800 1000–0xD800 1FFF
SDRAMC registers
4 Kbyte
0xD800 2000–0xD800 2FFF
WEIM registers
4 Kbyte
0xD800 3000–0xD800 3FFF
M3IF registers
4 Kbyte
0xD800 4000–0xD800 4FFF
PCMCIA registers
4 Kbyte
0xD800 5000–0xDBFF FFFF
Reserved
64 Mbyte–20 Kbyte
0xDC00 0000–0xDFFF FFFF
PCMCIA Memory Space
64 Mbyte
Table 2-5 shows the last region of address space that is part of the Primary AHB Memory Map. The
Vector-RAM is mapped into this region and the i.MX27 device uses the high memory
(0xFFFF FF00–0xFFFF FFFF) to store the interrupt vector table (64 words). This region is aliased on a
128-Kbyte boundary.
Table 2-5. Primary AHB Memory Map (Upper)
Address
Primary AHB
Size
0xE000 0000–0xFFEF FFFF
Reserved (aliased)
511 Mbyte
0xFFF0 0000–0xFFFF 4BFF
VRAM Space Not Use
979 Kbyte
0xFFFF 4C00–0xFFFF FFFF
45 Kbyte VRAM
45 Kbyte
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-5
System Memory and Register Map
Table 2-6 and Table 2-7 show the detailed breakdown of the address space controlled by AIPI1 and AIPI2.
More details on the AIPI can be found in Chapter 35, “AHB-Lite IP Interface (AIPI) Module.”
Table 2-6. AIPI1 Memory Map
Address
AIPI1 Memory Map
Size
0
0x1000 0000–0x1000 0FFF
AIPI1 (slot 0)
4 Kbytes
1
0x1000 1000–0x1000 1FFF
DMA
4 Kbytes
2
0x1000 2000–0x1000 2FFF
WDOG
4 Kbytes
3
0x1000 3000–0x1000 3FFF
GPT1
4 Kbytes
4
0x1000 4000–0x1000 4FFF
GPT2
4 Kbytes
5
0x1000 5000–0x1000 5FFF
GPT3
4 Kbytes
6
0x1000 6000–0x1000 6FFF
PWM
4 Kbytes
7
0x1000 7000–0x1000 7FFF
RTC
4 Kbytes
8
0x1000 8000–0x1000 8FFF
KPP
4 Kbytes
9
0x1000 9000–0x1000 9FFF
OWIRE
4 Kbytes
10
0x1000 A000–0x1000 AFFF
UART1
4 Kbytes
11
0x1000 B000–0x1000 BFFF
UART2
4 Kbytes
12
0x1000 C000–0x1000 CFFF
UART3
4 Kbytes
13
0x1000 D000–0x1000 DFFF
UART4
4 Kbytes
14
0x1000 E000–0x1000 EFFF
CSPI1
4 Kbytes
15
0x1000 F000–0x1000 FFFF
CSPI2
4 Kbytes
16
0x1001 0000–0x1001 0FFF
SSI1
4 Kbytes
17
0x1001 1000–0x1001 1FFF
SSI2
4 Kbytes
18
0x1001 2000–0x1001 2FFF
I2C1
4 Kbytes
19
0x1001 3000–0x1001 3FFF
SDHC1
4 Kbytes
20
0x1001 4000–0x1001 4FFF
SDHC2
4 Kbytes
21
0x1001 5000–0x1001 5FFF
GPIO
4 Kbytes
22
0x1001 6000–0x1001 6FFF
AUDMUX
4 Kbytes
23
0x1001 7000–0x1001 7FFF
CSPI3
4 Kbytes
24
0x1001 8000–0x1001 8FFF
MSHC
4 Kbytes
25
0x1001 9000–0x1001 9FFF
GPT4
4 Kbytes
26
0x1001 A000–0x1001 AFFF
GPT5
4 Kbytes
27
0x1001 B000–0x1001 BFFF
UART5
4 Kbytes
28
0x1001 C000–0x1001 CFFF
UART6
4 Kbytes
29
0x1001 D000–0x1001 DFFF
I2C2
4 Kbytes
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-6
Freescale Semiconductor
System Memory and Register Map
Table 2-6. AIPI1 Memory Map (continued)
Address
AIPI1 Memory Map
Size
30
0x1001 E000–0x1001 EFFF
SDHC3
4 Kbytes
31
0x1001 F000–0x1001 FFFF
GPT6
4 Kbytes
Table 2-7. AIPI2 Memory Map
2.3
Address
AIPI2 Memory Map
Size
0
0x1002 0000–0x1002 0FFF
AIPI2 (Slot 0)
4 Kbytes
1
0x1002 1000–0x1002 1FFF
LCDC
4 Kbytes
2
0x1002 2000–0x1002 2FFF
SLCDC
4 Kbytes
3
0x1002 3000–0x1002 3FFF
Reserved
4 Kbytes
4
0x1002 4000–0x1002 4FFF
USB2.0
4 Kbytes
5
0x1002 5000–0x1002 5FFF
SAHARA2
4 Kbytes
6
0x1002 6000–0x1002 6FFF
eMMA_lt
4 Kbytes
7
0x1002 7000–0x1002 7FFF
CRM
4 Kbytes
8
0x1002 8000–0x1002 8FFF
IIM
4 Kbytes
9
0x1002 9000–0x1002 9FFF
Reserved
4 Kbytes
10
0x1002 A000–0x1002 AFFF
RTIC
4 Kbyte
11
0x1002 B000–0x1002 BFFF
FEC
4 Kbyte
12
0x1002 C000–0x1002 CFFF
SCC
4 Kbyte
13
0x1002 D000–0x1002 DFFF
SCC
4 Kbyte
14–26
0x1002 E000–0x1003 AFFF
Reserved (slots 14–26)
52 Kbytes
27
0x1003 B000–0x1003 BFFF
ETB Regs
4 Kbytes
28
0x1003 C000–0x1003 CFFF
ETB RAM
4 Kbytes
29
0x1003 D000–0x1003 DFFF
ETB RAM
4 Kbytes
30
0x1003 E000–0x1003 EFFF
JAM
4 Kbytes
31
0x1003 F000–0x1003 FFFF
MAX
4 Kbytes
Register Map
The internal registers in the i.MX27 processor are listed in Table 2-8.
Table 2-8. Register Map
Module Name
Address
Register Name
Description
AIPI1
0x1000 0000
PSR0
Peripheral Size Register 0
AIPI1
0x1000 0004
PSR1
Peripheral Size Register 1
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-7
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
AIPI1
0x1000 0008
PAR
AIPI1
0x1000 000C
AAOR
DMAC
0x1000 1000
DCR
DMA Control Register
DMAC
0x1000 1004
DISR
DMA Interrupt Status Register
DMAC
0x1000 1008
DIMR
DMA Interrupt Mask Register
DMAC
0x1000 100C
DBTOSR
DMA Burst Time-Out Status Register
DMAC
0x1000 1010
DRTOSR
DMA Request Time-Out Status Register
DMAC
0x1000 1014
DSESR
DMA Transfer Error Status Register
DMAC
0x1000 1018
DBOSR
DMA Buffer Overflow Status Register
DMAC
0x1000 101C
DBTOCR
DMA Burst Time-Out Control Register
DMAC
0x1000 1040
WSRA
W-Size Register A
DMAC
0x1000 1044
XSRA
X-Size Register A
DMAC
0x1000 1048
YSRA
Y-Size Register A
DMAC
0x1000 104C
WSRB
W-Size Register B
DMAC
0x1000 1050
XSRB
X-Size Register B
DMAC
0x1000 1054
YSRB
Y-Size Register B
DMAC
0x1000 1080
SAR0
Channel 0 Source Address Register
DMAC
0x1000 1084
DAR0
Channel 0 Destination Address Register
DMAC
0x1000 1088
CNTR0
Channel 0 Count Register
DMAC
0x1000 108C
CCR0
Channel 0 Control Register
DMAC
0x1000 1090
RSSR0
DMAC
0x1000 1094
BLR0
DMAC
0x1000 1098
RTOR0
BUCR0
Channel 0 Request Time-Out Register
Channel 0 Bus Utilization Control Register
DMAC
0x1000 109C
CCNR0
Channel 0 Channel Counter Register
DMAC
0x1000 10C0
SAR1
Channel 1 Source Address Register
DMAC
0x1000 10C4
DAR1
Channel 1 Destination Address Register
DMAC
0x1000 10C8
CNTR1
Channel 1 Count Register
DMAC
0x1000 10CC
CCR1
Channel 1 Control Register
DMAC
0x1000 10D0
RSSR1
DMAC
0x1000 10D4
BLR1
DMAC
0x1000 10D8
RTOR1
BUCR1
Peripheral Access Register
Atomic Access Only Register
Channel 0 Request Source Select Register
Channel 0 Burst Length Register
Channel 1 Request Source Select Register
Channel 1 Burst Length Register
Channel 1 Request Time-Out Register
Channel 1 Bus Utilization Control Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-8
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
DMAC
0x1000 10DC
CCNR1
Channel 1 Channel Counter Register
DMAC
0x1000 1100
SAR2
Channel 2 Source Address Register
DMAC
0x1000 1104
DAR2
Channel 2 Destination Address Register
DMAC
0x1000 1108
CNTR2
Channel 2 Count Register
DMAC
0x1000 110C
CCR2
Channel 2 Control Register
DMAC
0x1000 1110
RSSR2
DMAC
0x1000 1114
BLR2
DMAC
0x1000 1118
RTOR2
BUCR2
Channel 2 Request Time-Out Register
Channel 2 Bus Utilization Control Register
DMAC
0x1000 111C
CCNR2
Channel 2 Channel Counter Register
DMAC
0x1000 1140
SAR3
Channel 3 Source Address Register
DMAC
0x1000 1144
DAR3
Channel 3 Destination Address Register
DMAC
0x1000 1148
CNTR3
Channel 3 Count Register
DMAC
0x1000 114C
CCR3
Channel 3 Control Register
DMAC
0x1000 1150
RSSR3
DMAC
0x1000 1154
BLR3
DMAC
0x1000 1158
RTOR3
BUCR3
Channel 3 Request Time-Out Register
Channel 3 Bus Utilization Control Register
DMAC
0x1000 115C
CCNR3
Channel 3 Channel Counter Register
DMAC
0x1000 1180
SAR4
Channel 4 Source Address Register
DMAC
0x1000 1184
DAR4
Channel 4 Destination Address Register
DMAC
0x1000 1188
CNTR4
Channel 4 Count Register
DMAC
0x1000 118C
CCR4
Channel 4 Control Register
DMAC
0x1000 1190
RSSR4
DMAC
0x1000 1194
BLR4
DMAC
0x1000 1198
RTOR4
BUCR4
Channel 4 Request Time-Out Register
Channel 4 Bus Utilization Control Register
DMAC
0x1000 119C
CCNR 4
Channel 4 Channel Counter Register
DMAC
0x1000 11C0
SAR5
Channel 5 Source Address Register
DMAC
0x1000 11C4
DAR5
Channel 5 Destination Address Register
DMAC
0x1000 11C8
CNTR5
Channel 5 Count Register
DMAC
0x1000 11CC
CCR5
Channel 5 Control Register
DMAC
0x1000 11D0
RSSR5
DMAC
0x1000 11D4
BLR5
Channel 2 Request Source Select Register
Channel 2 Burst Length Register
Channel 3 Request Source Select Register
Channel 3 Burst Length Register
Channel 4 Request Source Select Register
Channel 4 Burst Length Register
Channel 5 Request Source Select Register
Channel 5 Burst Length Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-9
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
DMAC
0x1000 11D8
RTOR5
BUCR5
Channel 5 Request Time-Out Register
Channel 5 Bus Utilization Control Register
DMAC
0x1000 11DC
CCNR5
Channel 5 Channel Counter Register
DMAC
0x1000 1200
SAR6
Channel 6 Source Address Register
DMAC
0x1000 1204
DAR6
Channel 6 Destination Address Register
DMAC
0x1000 1208
CNTR6
Channel 6 Count Register
DMAC
0x1000 120C
CCR6
Channel 6 Control Register
DMAC
0x1000 1210
RSSR6
DMAC
0x1000 1214
BLR6
DMAC
0x1000 1218
RTOR6
BUCR6
Channel 6 Request Time-Out Register
Channel 6 Bus Utilization Control Register
DMAC
0x1000 121C
CCNR6
Channel 6 Channel Counter Register
DMAC
0x1000 1240
SAR7
Channel 7 Source Address Register
DMAC
0x1000 1244
DAR7
Channel 7 Destination Address Register
DMAC
0x1000 1248
CNTR7
Channel 7 Count Register
DMAC
0x1000 124C
CCR7
Channel 7 Control Register
DMAC
0x1000 1250
RSSR7
DMAC
0x1000 1254
BLR7
DMAC
0x1000 1258
RTOR7
BUCR7
Channel 7 Request Time-Out Register
Channel 7 Bus Utilization Control Register
DMAC
0x1000 125C
CCNR7
Channel 7 Channel Counter Register
DMAC
0x1000 1280
SAR8
Channel 8 Source Address Register
DMAC
0x1000 1284
DAR8
Channel 8 Destination Address Register
DMAC
0x1000 1288
CNTR8
Channel 8 Count Register
DMAC
0x1000 128C
CCR8
Channel 8 Control Register
DMAC
0x1000 1290
RSSR8
DMAC
0x1000 1294
BLR8
DMAC
0x1000 1298
RTOR8
BUCR8
Channel 8 Request Time-Out Register
Channel 8 Bus Utilization Control Register
DMAC
0x1000 129C
CCNR8
Channel 8 Channel Counter Register
DMAC
0x1000 12C0
SAR9
Channel 9 Source Address Register
DMAC
0x1000 12C4
DAR9
Channel 9 Destination Address Register
DMAC
0x1000 12C8
CNTR9
Channel 9 Count Register
DMAC
0x1000 12CC
CCR9
Channel 9 Control Register
Channel 6 Request Source Select Register
Channel 6 Burst Length Register
Channel 7 Request Source Select Register
Channel 7 Burst Length Register
Channel 8 Request Source Select Register
Channel 8 Burst Length Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-10
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
DMAC
0x1000 12D0
RSSR9
DMAC
0x1000 12D4
BLR9
DMAC
0x1000 12D8
RTOR9
BUCR9
Channel 9 Request Time-Out Register
Channel 9 Bus Utilization Control Register
DMAC
0x1000 12DC
CCNR9
Channel 9 Channel Counter Register
DMAC
0x1000 1300
SAR10
Channel 10 Source Address Register
DMAC
0x1000 1304
DAR10
Channel 10 Destination Address Register
DMAC
0x1000 1308
CNTR10
Channel 10 Count Register
DMAC
0x1000 130C
CCR10
Channel 10 Control Register
DMAC
0x1000 1310
RSSR10
DMAC
0x1000 1314
BLR10
DMAC
0x1000 1318
RTOR10
BUCR10
Channel 10 Request Time-Out Register
Channel 10 Bus Utilization Control Register
DMAC
0x1000 131C
CCNR10
Channel 10 Channel Counter Register
DMAC
0x1000 1340
SAR11
Channel 11 Source Address Register
DMAC
0x1000 1344
DAR11
Channel 11 Destination Address Register
DMAC
0x1000 1348
CNTR11
Channel 11 Count Register
DMAC
0x1000 134C
CCR11
Channel 11 Control Register
DMAC
0x1000 1350
RSSR11
Channel 11 Request Source Select Register
DMAC
0x1000 1354
BLR11
DMAC
0x1000 1358
RTOR11
BUCR11
Channel 11 Request Time-Out Register
Channel 11 Bus Utilization Control Register
DMAC
0x1000 135C
CCNR11
Channel 11 Channel Counter Register
DMAC
0x1000 1380
SAR12
Channel 12 Source Address Register
DMAC
0x1000 1384
DAR12
Channel 12 Destination Address Register
DMAC
0x1000 1388
CNTR12
Channel 12 Count Register
DMAC
0x1000 138C
CCR12
Channel 12 Control Register
DMAC
0x1000 1390
RSSR12
Channel 12 Request Source Select Register
DMAC
0x1000 1394
BLR12
DMAC
0x1000 1398
RTOR12
BUCR12
Channel 12 Request Time-Out Register
Channel 12 Bus Utilization Control Register
DMAC
0x1000 139C
CCNR12
Channel 14 Channel Counter Register
DMAC
0x1000 13C0
SAR13
Channel 13 Source Address Register
DMAC
0x1000 13C4
DAR13
Channel 13 Destination Address Register
Channel 9 Request Source Select Register
Channel 9 Burst Length Register
Channel 10 Request Source Select Register
Channel 10 Burst Length Register
Channel 11 Burst Length Register
Channel 12 Burst Length Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-11
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
DMAC
0x1000 13C8
CNTR13
Channel 13 Count Register
DMAC
0x1000 13CC
CCR13
Channel 13 Control Register
DMAC
0x1000 13D0
RSSR13
Channel 13 Request Source Select Register
DMAC
0x1000 13D4
BLR13
DMAC
0x1000 13D8
RTOR13
BUCR13
Channel 13 Request Time-Out Register
Channel 13 Bus Utilization Control Register
DMAC
0x1000 13DC
CCNR13
Channel 13 Channel Counter Register
DMAC
0x1000 1400
SAR14
Channel 14 Source Address Register
DMAC
0x1000 1404
DAR14
Channel 14 Destination Address Register
DMAC
0x1000 1408
CNTR14
Channel 14 Count Register
DMAC
0x1000 140C
CCR14
Channel 14 Control Register
DMAC
0x1000 1410
RSSR14
Channel 14 Request Source Select Register
DMAC
0x1000 1414
BLR14
DMAC
0x1000 1418
RTOR14
BUCR14
Channel 14 Request Time-Out Register
Channel 14 Bus Utilization Control Register
DMAC
0x1000 141C
CCNR14
Channel 14 Channel Counter Register
DMAC
0x1000 1440
SAR15
Channel 15 Source Address Register
DMAC
0x1000 1444
DAR15
Channel 15 Destination Address Register
DMAC
0x1000 1448
CNTR15
Channel 15 Count Register
DMAC
0x1000 144C
CCR15
Channel 15 Control Register
DMAC
0x1000 1450
RSSR15
Channel 15 Request Source Select Register
DMAC
0x1000 1454
BLR15
DMAC
0x1000 1458
RTOR15
BUCR15
Channel 15 Request Time-Out Register
Channel 15 Bus Utilization Control Register
DMAC
0x1000 145C
CCNR15
Channel 15 Channel Counter Register
DMAC
0x1000 1480
TCR
Test Control Register
DMAC
0x1000 1484
TFIFOAR
Test FIFO A Register
DMAC
0x1000 148C
TDIPR
DMAC
0x1000 1490
TFIFOBR
Test FIFO B Register
DMAC
0x1000 1498
TDRR_L
Low 32 DMA Request Register
DMAC
0x1000 149C
TDRR_H
High 32 DMA Request Register
WDOG
0x1000 2000
WCR
Watchdog Control Register
WDOG
0x1000 2002
WSR
Watchdog Service Register
WDOG
0x1000 2004
WRSR
Channel 13 Burst Length Register
Channel 14 Burst Length Register
Channel 15 Burst Length Register
Test DMA In Progress Register
Watchdog Reset Status Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-12
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
GPT1
0x1000 3000
TCTL1
GPT1
0x1000 3004
TPRER1
GPT Prescaler Register 1
GPT1
0x1000 3008
TCMP1
GPT Compare Register 1
GPT1
0x1000 300C
TCR1
GPT Capture Register 1
GPT1
0x1000 3010
TCN1
GPT Counter Register 1
GPT1
0x1000 3014
TSTAT1
GPT Status Register 1
GPT2
0x1000 4000
TCTL2
GPT Control Register 2
GPT2
0x1000 4004
TPRER2
GPT Prescaler Register 2
GPT2
0x1000 4008
TCMP2
GPT Compare Register 2
GPT2
0x1000 400C
TCR2
GPT Capture Register 2
GPT2
0x1000 4010
TCN2
GPT Counter Register 2
GPT2
0x1000 4014
TSTAT2
GPT Status Register 2
GPT3
0x1000 5000
TCTL3
GPT Control Register 3
GPT3
0x1000 5004
TPRER3
GPT Prescaler Register 3
GPT3
0x1000 5008
TCMP3
GPT Compare Register 3
GPT3
0x1000 500C
TCR3
GPT Capture Register 3
GPT3
0x1000 5010
TCN3
GPT Counter Register 3
GPT3
0x1000 5014
TSTAT3
GPT Status Register 3
PWM
0x1000 6000
PWMCR
PWM Control Register
PWM
0x1000 6004
PWMSR
PWM Status Register
PWM
0x1000 6008
PWMIR
PWM Interrupt Register
PWM
0x1000 600C
PWMSAR
PWM Sample Register
PWM
0x1000 6010
PWMPR
PWM Period Register
PWM
0x1000 6014
PWMCNR
PWM Counter Register
RTC
0x1000 7000
HOURMIN
RTC Hours and Minutes Counter Register
RTC
0x1000 7004
SECONDS
RTC Seconds Counter Register
RTC
0x1000 7008
ALRM_HM
RTC Hours and Minutes Alarm Register
RTC
0x1000 700C
ALRM_SEC
RTC Seconds Alarm Register
RTC
0x1000 7010
RCCTL
RTC Control Register
RTC
0x1000 7014
RTCISR
RTC Interrupt Status Register
RTC
0x1000 7018
RTCIENR
RTC Interrupt Enable Register
RTC
0x1000 701C
STPWCH
Stopwatch Minutes Register
RTC
0x1000 7020
DAYR
RTC Days Counter Register
GPT Control Register 1
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-13
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
RTC
0x1000 7024
DAYALARM
RTC Day Alarm Register
KPP
0x1000_8000
KPCR
Keypad Control Register
KPP
0x1000_8002
KPSR
Keypad Status Register
KPP
0x1000_8004
KDDR
Keypad Data Direction Register
KPP
0x1000_8006
KPDR
Keypad Data Register
O-Wire
0x1000 9000
CONTROL
O-Wire
0x1000 9002
TIME_DIVIDER
O-Wire
0x1000 9004
RESET
1-Wire Reset Register
UART1
0x1000_A000
UXRD_1
UART1 Receiver Register
UART1
0x1000_A040
UTXD_1
UART1 Transmitter Register
UART1
0x1000_A080
UCR1_1
UART1 Control Register
UART1
0x1000_A084
UCR2_1
UART1 Control Register 2
UART1
0x1000_A088
UCR3_1
UART1 Control Register 3
UART1
0x1000_A08C
UCR4_1
UART1 Control Register 4
UART1
0x1000_A090
UFCR_1
UART1 FIFO Control Register
UART1
0x1000_A094
USR1_1
UART1 Status Register 1
UART1
0x1000_A098
USR2_1
UART1 Status Register 2
UART1
0x1000_A09C
UESC_1
UART1 Escape Character Register
UART1
0x1000_A0A0
UTIM_1
UART1 Escape Timer Register
UART1
0x1000_A0A4
UBIR_1
UART1 BRM Incremental Register
UART1
0x1000_A0A8
UBMR_1
UART1 BRM Modulator Register
UART1
0x1000_A0AC
UBRC_1
UART1 Baud Rate Count Register
UART1
0x1000_A0B0
ONEMS_1
UART1 One Millisecond Register
UART1
0x1000_A0B4
UTS_1
UART2
0x1000_B000
UXRD_2
UART2 Receiver Register
UART2
0x1000_B040
UTXD_2
UART2 Transmitter Register
UART2
0x1000_B080
UCR1_2
UART2 Control Register
UART2
0x1000_B084
UCR2_2
UART2 Control Register 2
UART2
0x1000_B088
UCR3_2
UART2 Control Register 3
UART2
0x1000_B08C
UCR4_2
UART2 Control Register 4
UART2
0x1000_B090
UFCR_2
UART2 FIFO Control Register
UART2
0x1000_B094
USR1_2
UART2 Status Register 1
UART2
0x1000_B098
USR2_2
UART2 Status Register 2
1-Wire Control Register
1-Wire Time Divider Register
UART1 Test Register 1
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-14
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
UART2
0x1000_B09C
UESC_2
UART2 Escape Character Register
UART2
0x1000_B0A0
UTIM_2
UART2 Escape Timer Register
UART2
0x1000_B0A4
UBIR_2
UART2 BRM Incremental Register
UART2
0x1000_B0A8
UBMR_2
UART2 BRM Modulator Register
UART2
0x1000_B0AC
UBRC_2
UART2 Baud Rate Count Register
UART2
0x1000_B0B0
ONEMS_2
UART2 One Millisecond Register
UART2
0x1000_B0B4
UTS_2
UART3
0x1000_C000
UXRD_3
UART3 Receiver Register
UART3
0x1000_C040
UTXD_3
UART3 Transmitter Register
UART3
0x1000_C080
UCR1_3
UART3 Control Register
UART3
0x1000_C084
UCR2_3
UART3 Control Register 2
UART3
0x1000_C088
UCR3_3
UART3 Control Register 3
UART3
0x1000_C08C
UCR4_3
UART3 Control Register 4
UART3
0x1000_C090
UFCR_3
UART3 FIFO Control Register
UART3
0x1000_C094
USR1_3
UART3 Status Register 1
UART3
0x1000_C098
USR2_3
UART3 Status Register 2
UART3
0x1000_C09C
UESC_3
UART3 Escape Character Register
UART3
0x1000_C0A0
UTIM_3
UART3 Escape Timer Register
UART3
0x1000_C0A4
UBIR_3
UART3 BRM Incremental Register
UART3
0x1000_C0A8
UBMR_3
UART3 BRM Modulator Register
UART3
0x1000_C0AC
UBRC_3
UART3 Baud Rate Count Register
UART3
0x1000_C0B0
ONEMS_3
UART3 One Millisecond Register
UART3
0x1000_C0B4
UTS_3
UART4
0x1000_D000
UXRD_4
UART4 Receiver Register
UART4
0x1000_D040
UTXD_4
UART4 Transmitter Register
UART4
0x1000_D080
UCR1_4
UART4 Control Register
UART4
0x1000_D084
UCR2_4
UART4 Control Register 2
UART4
0x1000_D088
UCR3_4
UART4 Control Register 3
UART4
0x1000_D08C
UCR4_4
UART4 Control Register 4
UART4
0x1000_D090
UFCR_4
UART4 FIFO Control Register
UART4
0x1000_D094
USR1_4
UART4 Status Register 1
UART4
0x1000_D098
USR2_4
UART4 Status Register 2
UART4
0x1000_D09C
UESC_4
UART4 Escape Character Register
UART2 Test Register 1
UART3 Test Register 1
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-15
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
UART4
0x1000_D0A0
UTIM_4
UART4 Escape Timer Register
UART4
0x1000_D0A4
UBIR_4
UART4 BRM Incremental Register
UART4
0x1000_D0A8
UBMR_4
UART4 BRM Modulator Register
UART4
0x1000_D0AC
UBRC_4
UART4 Baud Rate Count Register
UART4
0x1000_D0B0
ONEMS_4
UART4 One Millisecond Register
UART4
0x1000_D0B4
UTS_4
CSPI1
0x1000 E000
RXDATA1
Receive Data Register 1
CSPI1
0x1000 E004
TXDATA1
Transmit Data Register 1
CSPI1
0x1000 E008
CONTROL_REG1
CSPI Control Register 1
CSPI1
0x1000 E00C
INT_REG1
Interrupt Control/Status Register 1
CSPI1
0x1000 E010
TEST_REG
CSPI Test Register 1
CSPI1
0x1000 E014
PERIOD1
CSPI1
0x1000 E018
CSPI_DMA1
CSPI1
0x1000 E01C
CSPI_RESET1
CSPI2
0x1000 F000
RXDATA2
Receive Data Register 2
CSPI2
0x1000 F004
TXDATA2
Transmit Data Register 2
CSPI2
0x1000 F008
CONTROL_REG2
CSPI Control Register 2
CSPI2
0x1000 F00C
INT_REG2
CSPI2
0x1000 F010
TEST_REG 2
CSPI2
0x1000 F014
PERIOD2
CSPI2
0x1000 F018
CSPI_DMA2
CSPI2
0x1000 F01C
CSPI_RESET2
SSI 1
0x1001 0000
STX0
SSI Transmit Data Register 0
SSI 1
0x1001 0004
STX1
SSI Transmit Data Register 1
SSI 1
0x1001 0008
SRX0
SSI Receive Data Register 0
SSI 1
0x1001 000C
SRX1
SSI Receive Data Register 1
SSI 1
0x1001 0010
SCR
SSI Control Register
SSI 1
0x1001 0014
SISR
SSI Interrupt Status Register
SSI 1
0x1001 0018
SIER
SSI Interrupt Enable Register
SSI 1
0x1001 001C
STCR
SSI Transmit Configuration Register
SSI 1
0x1001 0020
SRCR
SSI Receive Configuration Register
SSI 1
0x1001 0024
STCCR
SSI Transmit Clock Control Register
SSI 1
0x1001 0028
SRCCR
SSI Receive Clock Control Register
UART4 Test Register 1
CSPI Sample Period Control Register 1
CSPI DMA Register 1
CSPI 1 Soft Reset Register
Interrupt Control/Status Register 2
CSPI Test Register 2
CSPI Sample Period Control Register 2
CSPI DMA Register 2
CSPI 2 Soft Reset Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-16
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
SSI 1
0x1001 002C
SFCSR
SSI 1
0x1001 0030
STR
SSI Test Register
SSI 1
0x1001 0034
SOR
SSI Option Register
SSI 1
0x1001 0038
SACNT
SSI 1
0x1001 003C
SACADD
SSI AC97 Command Address Register
SSI 1
0x1001 0040
SACDAT
SSI AC97 Command Data Register
SSI 1
0x1001 0044
SATAG
SSI AC97 Tag Register
SSI 1
0x1001 0048
STMSK
SSI Transmit Time Slot Mask Register
SSI 1
0x1001 004C
SRMSK
SSI Receive Time Slot Mask Register
SSI 1
0x1001 0050
SACCST
SSI AC97 Channel Status Register
SSI 1
0x1001 0054
SACCEN
SSI AC97 Channel Enable Register
SSI 1
0x1001 0058
SACCDIS
SSI AC97 Channel Disable Register
SSI 2
0x1001 1000
STX0
SSI Transmit Data Register 0
SSI 2
0x1001 1004
STX1
SSI Transmit Data Register 1
SSI 2
0x1001 1008
SRX0
SSI Receive Data Register 0
SSI 2
0x1001 100C
SRX1
SSI Receive Data Register 1
SSI 2
0x1001 1010
SCR
SSI Control Register
SSI 2
0x1001 1014
SISR
SSI Interrupt Status Register
SSI 2
0x1001 1018
SIER
SSI Interrupt Enable Register
SSI 2
0x1001 101C
STCR
SSI Transmit Configuration Register
SSI 2
0x1001 1020
SRCR
SSI Receive Configuration Register
SSI 2
0x1001 1024
STCCR
SSI Transmit Clock Control Register
SSI 2
0x1001 1028
SRCCR
SSI Receive Clock Control Register
SSI 2
0x1001 102C
SFCSR
SSI FIFO Control/Status Register
SSI 2
0x1001 1030
STR
SSI Test Register
SSI 2
0x1001 1034
SOR
SSI Option Register
SSI 2
0x1001 1038
SACNT
SSI 2
0x1001 103C
SACADD
SSI AC97 Command Address Register
SSI 2
0x1001 1040
SACDAT
SSI AC97 Command Data Register
SSI 2
0x1001 1044
SATAG
SSI AC97 Tag Register
SSI 2
0x1001 1048
STMSK
SSI Transmit Time Slot Mask Register
SSI 2
0x1001 104C
SRMSK
SSI Receive Time Slot Mask Register
SSI 2
0x1001 1050
SACCST
SSI AC97 Channel Status Register
SSI FIFO Control/Status Register
SSI AC97 Control Register
SSI AC97 Control Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-17
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
SSI 2
0x1001 1054
SACCEN
SSI AC97 Channel Enable Register
SSI 2
0x1001 1058
SACCDIS
SSI AC97 Channel Disable Register
I2C 1
0x1001 2000
IADR
I2C Address Register
I2C 1
0x1001 2004
IFDR
I2C Frequency Divider Register
I2C 1
0x1001 2008
I2CR
I2C Control Register
I2C 1
0x1001 200C
I2SR
I2C Status Register
I2C 1
0x1001 2010
I2DR
I2C Data I/O Register
SDHC1
0x1001 3000
STR_STP_CLK
SDHC1
0x1001 3004
STATUS (Read Only)
SDHC1
0x1001 3008
CLK_RATE
SDHC1
0x1001 300C
CMD_DAT_CONT
MMC/SD1 Command and Data Control Register
SDHC1
0x1001 3010
RESPONSE_TO
MMC/SD1 Response Time Out Register
SDHC1
0x1001 3014
READ_TO
MMC/SD1 Read Time Out Register
SDHC1
0x1001 3018
BLK_LEN
MMC/SD1 Block Length Register
SDHC1
0x1001 301C
NOB
MMC/SD1 Number of Block Register
SDHC1
0x1001 3020
REV_NO
MMC/SD1 Revision Number Register
SDHC1
0x1001 3024
INT_CNTL
MMC/SD1 Interrupt Control Register
SDHC1
0x1001 3028
CMD
MMC/SD1 Command Number Register
SDHC1
0x1001 302C
ARGH
MMC/SD1 Higher Argument Register
SDHC1
0x1001 3030
ARGL
MMC/SD1 Lower Argument Register
SDHC1
0x1001 3034
RES_FIFO (Read Only)
MMC/SD1 Response FIFO Register
SDHC1
0x1001 3038
BUFFER_ACCESS
MMC/SD1 Buffer Access Register
SDHC2
0x1001 4000
STR_STP_CLK
MMC/SD2 Clock Control Register
SDHC2
0x1001 4004
STATUS (Read Only)
SDHC2
0x1001 4008
CLK_RATE
SDHC2
0x1001 400C
CMD_DAT_CONT
MMC/SD2 Command and Data Control Register
SDHC2
0x1001 4010
RESPONSE_TO
MMC/SD2 Response Time Out Register
SDHC2
0x1001 4014
READ_TO
MMC/SD2 Read Time Out Register
SDHC2
0x1001 4018
BLK_LEN
MMC/SD2 Block Length Register
SDHC2
0x1001 401C
NOB
MMC/SD2 Number of Block Register
SDHC2
0x1001 4020
REV_NO
MMC/SD2 Revision Number Register
SDHC2
0x1001 4024
INT_CNTL
MMC/SD2 Interrupt Control Register
SDHC2
0x1001 4028
CMD
MMC/SD1 Clock Control Register
MMC/SD1 Status Register
MMC/SD1 Clock Rate Register
MMC/SD2 Status Register
MMC/SD2 Clock Rate Register
MMC/SD2 Command Number Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-18
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
SDHC2
0x1001 402C
ARGH
MMC/SD2 Higher Argument Register
SDHC2
0x1001 4030
ARGL
MMC/SD2 Lower Argument Register
SDHC2
0x1001 4034
RES_FIFO (Read Only)
MMC/SD2 Response FIFO Register
SDHC2
0x1001 4038
BUFFER_ACCESS
GPIO
0x1001 5000
PTA_DDIR
Data Direction Register, Port A
GPIO
0x1001 5004
PTA_OCR1
Output Configuration Register 1 (OCR1), Port A
GPIO
0x1001 5008
PTA_OCR2
Output Configuration Register 2 (OCR2), Port A
GPIO
0x1001 500C
PTA_ICONFA1
Input Configuration Register A1 (ICONFA1), Port A
GPIO
0x1001 5010
PTA_ICONFA2
Input Configuration Register A1 (ICONFA2), Port A
GPIO
0x1001 5014
PTA_ICONFB1
Input Configuration Register B1 (ICONFB1), Port A
GPIO
0x1001 5018
PTA_ICONFB2
Input Configuration Register B2 (ICONFB2), Port A
GPIO
0x1001 501c
PTA_DR
GPIO
0x1001 5020
PTA_GIUS
GPIO In Use Register, Port A
GPIO
0x1001 5024
PTA_SSR
Sample Status Register, Port A
GPIO
0x1001 5028
PTA_ICR1
Interrupt Configuration Register 1, Port A
GPIO
0x1001 502C
PTA_ICR2
Interrupt Configuration Register 2, Port A
GPIO
0x1001 5030
PTA_IMR
Interrupt Mask Register, Port A
GPIO
0x1001 5034
PTA_ISR
Interrupt Status Register, Port A
GPIO
0x1001 5038
PTA_GPR
General Purpose Register, Port A
GPIO
0x1001 503c
PTA_SWR
Software Reset Register, Port A
GPIO
0x1001 5040
PTA_PUEN
Pull_up Enable Register, Port A
GPIO
0x1001_5100
PTB_DDIR
Data Direction Register, Port B
GPIO
0x1001 5104
PTB_OCR1
Output Configuration Register 1 (OCR1), Port B
GPIO
0x1001 5108
PTB_OCR2
Output Configuration Register 2 (OCR2), Port B
GPIO
0x1001 510c
PTB_ICONFA1
Input Configuration Register A1 (ICONFA1), Port B
GPIO
0x1001 5110
PTB_ICONFA2
Input Configuration Register A1 (ICONFA2), Port B
GPIO
0x1001 5114
PTB_ICONFB1
Input Configuration Register B1 (ICONFB1), Port B
GPIO
0x1001 5118
PTB_ICONFB2
Input Configuration Register B2 (ICONFB2), Port B
GPIO
0x1001 511c
PTB_DR
GPIO
0x1001 5120
PTB_GIUS
GPIO In Use Register, Port B
GPIO
0x1001 5124
PTB_SSR
Sample Status Register, Port B
GPIO
0x1001 5128
PTB_ICR1
Interrupt Configuration Register 1, Port B
GPIO
0x1001 512C
PTB_ICR2
Interrupt Configuration Register 2, Port B
MMC/SD2 Buffer Access Register
Data Register, Port A
Data Register, Port B
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-19
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
GPIO
0x1001 5130
PTB_IMR
Interrupt Mask Register, Port B
GPIO
0x1001 5134
PTB_ISR
Interrupt Status Register, Port B
GPIO
0x1001 5138
PTB_GPR
General Purpose Register, Port B
GPIO
0x1001 513c
PTB_SWR
Software Reset Register, Port B
GPIO
0x1001 5140
PTB_PUEN
Pull_up Enable Register, Port B
GPIO
0x1001_5200
PTC_DDIR
Data Direction Register, Port C
GPIO
0x1001 5204
PTC_OCR1
Output Configuration Register 1 (OCR1), Port C
GPIO
0x1001 5208
PTC_OCR2
Output Configuration Register 2 (OCR2), Port C
GPIO
0x1001 520c
PTC_ICONFA1
Input Configuration Register A1 (ICONFA1), Port C
GPIO
0x1001 5210
PTC_ICONFA2
Input Configuration Register A1 (ICONFA2), Port C
GPIO
0x1001 5214
PTC_ICONFB1
Input Configuration Register B1 (ICONFB1), Port C
GPIO
0x1001 5218
PTC_ICONFB2
Input Configuration Register B2 (ICONFB2), Port C
GPIO
0x1001 521C
PTC_DR
GPIO
0x1001 5220
PTC_GIUS
GPIO In Use Register, Port C
GPIO
0x1001 5224
PTC_SSR
Sample Status Register, Port C
GPIO
0x1001 5228
PTC_ICR1
Interrupt Configuration Register 1, Port C
GPIO
0x1001 522C
PTC_ICR2
Interrupt Configuration Register 2, Port C
GPIO
0x1001 5230
PTC_IMR
Interrupt Mask Register, Port C
GPIO
0x1001 5234
PTC_ISR
Interrupt Status Register, Port C
GPIO
0x1001 5238
PTC_GPR
General Purpose Register, Port C
GPIO
0x1001 523c
PTC_SWR
Software Reset Register, Port C
GPIO
0x1001 5240
PTC_PUEN
Pull_up Enable Register, Port C
GPIO
0x1001 5300
PTD_DDIR
Data Direction Register, Port D
GPIO
0x1001 5304
PTD_OCR1
Output Configuration Register 1 (OCR1), Port D
GPIO
0x1001 5308
PTD_OCR2
Output Configuration Register 2 (OCR2), Port D
GPIO
0x1001 530c
PTD_ICONFA1
Input Configuration Register A1 (ICONFA1), Port D
GPIO
0x1001 5310
PTD_ICONFA2
Input Configuration Register A1 (ICONFA2), Port D
GPIO
0x1001 5314
PTD_ICONFB1
Input Configuration Register B1 (ICONFB1), Port D
GPIO
0x1001 5318
PTD_ICONFB2
Input Configuration Register B2 (ICONFB2), Port D
GPIO
0x1001 531c
PTD_DR
GPIO
0x1001 5320
PTD_GIUS
GPIO In Use Register, Port D
GPIO
0x1001 5324
PTD_SSR
Sample Status Register, Port D
GPIO
0x1001 5328
PTD_ICR1
Interrupt Configuration Register 1, Port D
Data Register, Port C
Data Register, Port D
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-20
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
GPIO
0x1001 532C
PTD_ICR2
Interrupt Configuration Register 2, Port D
GPIO
0x1001 5330
PTD_IMR
Interrupt Mask Register, Port D
GPIO
0x1001 5334
PTD_ISR
Interrupt Status Register, Port D
GPIO
0x1001 5338
PTD_GPR
General Purpose Register, Port D
GPIO
0x1001 533c
PTD_SWR
Software Reset Register, Port D
GPIO
0x1001 5340
PTD_PUEN
Pull_up Enable Register, Port D
GPIO
0x1001 5400
PTE_DDIR
Data Direction Register, Port E
GPIO
0x1001 5404
PTE_OCR1
Output Configuration Register 1 (OCR1), Port E
GPIO
0x1001 5408
PTE_OCR2
Output Configuration Register 2 (OCR2), Port E
GPIO
0x1001 540c
PTE_ICONFA1
Input Configuration Register A1 (ICONFA1), Port E
GPIO
0x1001 5410
PTE_ICONFA2
Input Configuration Register A1 (ICONFA2), Port E
GPIO
0x1001 5414
PTE_ICONFB1
Input Configuration Register B1 (ICONFB1), Port E
GPIO
0x1001 5418
PTE_ICONFB2
Input Configuration Register B2 (ICONFB2), Port E
GPIO
0x1001 541c
PTE_DR
GPIO
0x1001 5420
PTE_GIUS
GPIO In Use Register, Port E
GPIO
0x1001 5424
PTE_SSR
Sample Status Register, Port E
GPIO
0x1001 5428
PTE_ICR1
Interrupt Configuration Register 1, Port E
GPIO
0x1001 542C
PTE_ICR2
Interrupt Configuration Register 2, Port E
GPIO
0x1001 5430
PTE_IMR
Interrupt Mask Register, Port E
GPIO
0x1001 5434
PTE_ISR
Interrupt Status Register, Port E
GPIO
0x1001 5438
PTE_GPR
General Purpose Register, Port E
GPIO
0x1001 543c
PTE_SWR
Software Reset Register, Port E
GPIO
0x1001 5440
PTE_PUEN
Pull_up Enable Register, Port E
GPIO
0x1001 5500
PTF_DDIR
Data Direction Register, Port F
GPIO
0x1001 5504
PTF_OCR1
Output Configuration Register 1 (OCR1), Port F
GPIO
0x1001 5508
PTF_OCR2
Output Configuration Register 2 (OCR2), Port F
GPIO
0x1001 550C
PTF_ICONFA1
Input Configuration Register A1 (ICONFA1), Port F
GPIO
0x1001 5510
PTF_ICONFA2
Input Configuration Register A1 (ICONFA2), Port F
GPIO
0x1001 5514
PTF_ICONFB1
Input Configuration Register B1 (ICONFB1), Port F
GPIO
0x1001 5518
PTF_ICONFB2
Input Configuration Register B2 (ICONFB2), Port F
GPIO
0x1001 551c
PTF_DR
GPIO
0x1001 5520
PTF_GIUS
GPIO In Use Register, Port F
GPIO
0x1001 5524
PTF_SSR
Sample Status Register, Port F
Data Register, Port E
Data Register, Port F
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-21
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
GPIO
0x1001 5528
PTF_ICR1
Interrupt Configuration Register 1, Port F
GPIO
0x1001 552C
PTF_ICR2
Interrupt Configuration Register 2, Port F
GPIO
0x1001 5530
PTF_IMR
Interrupt Mask Register, Port F
GPIO
0x1001 5534
PTF_ISR
Interrupt Status Register, Port F
GPIO
0x1001 5538
PTF_GPR
General Purpose Register, Port F
GPIO
0x1001 553c
PTF_SWR
Software Reset Register, Port F
GPIO
0x1001 5540
PTF_PUEN
Pull_up Enable Register, Port F
GPIO
0x1001 5600
PMASK
GPIO Port Interrupt Mask
AUDMUX
0x1001 6000
HPCR1
Host Port Configuration Register 1
AUDMUX
0x1001 6004
HPCR2
Host Port Configuration Register 2
AUDMUX
0x1001 6008
HPCR3
Host Port Configuration Register 3
AUDMUX
0x1001 6010
PPCR1
Peripheral Port Configuration Register 1
AUDMUX
0x1001 6014
PPCR2
Peripheral Port Configuration Register 2
AUDMUX
0x1001 601C
PPCR3
Peripheral Port Configuration Register 3
CSPI3
0x1001 7000
RXDATA3
Receive Data Register 3
CSPI3
0x1001 7004
TXDATA3
Transmit Data Register 3
CSPI3
0x1001 7008
CONTROL_REG3
CSPI Control Register 3
CSPI3
0x1001 700C
INT_REG3
CSPI3
0x1001 7010
TEST_REG3
CSPI3
0x1001 7014
PERIOD3
CSPI3
0x1001 7018
CSPI_DMA3
CSPI3
0x1001 701C
CSPI_RESET3
CSPI Soft Reset Register 3
MSHC
0x1001 8000
COMMAND_REG
MSHC Command Register
MSHC
0x1001 8008
DATA_REG
MSHC
0x1001 8010
STATUS_REG
MSHC Status Register
MSHC
0x1001 8018
SYSTEM_REG
MSHC System Register
GPT4
0x1001 9000
TCTL4
GPT Control Register 4
GPT4
0x1001 9004
TPRER4
GPT Prescaler Register 4
GPT4
0x1001 9008
TCMP4
GPT Compare Register 4
GPT4
0x1001 900C
TCR4
GPT Capture Register 4
GPT4
0x1001 9010
TCN4
GPT Counter Register 4
GPT4
0x1001 9014
TSTAT4
GPT Status Register 4
GPT5
0x1001 A000
TCTL5
GPT Control Register 5
Interrupt Control/Status Register 3
CSPI Test Register 3
CSPI Sample Period Control Register 3
CSPI DMA Register 3
MSHC Data Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-22
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
GPT5
0x1001 A004
TPRER5
GPT Prescaler Register 5
GPT5
0x1001 A008
TCMP5
GPT Compare Register 5
GPT5
0x1001 A00C
TCR5
GPT Capture Register 5
GPT5
0x1001 A010
TCN5
GPT Counter Register 5
GPT5
0x1001 A014
TSTAT5
GPT Status Register 5
UART5
0x1001_B000
UXRD_5
UART5 Receiver Register
UART5
0x1001_B040
UTXD_5
UART5 Transmitter Register
UART5
0x1001_B080
UCR1_5
UART5 Control Register
UART5
0x1001_B084
UCR2_5
UART5 Control Register 2
UART5
0x1001_B088
UCR3_5
UART5 Control Register 3
UART5
0x1001_B08C
UCR4_5
UART5 Control Register 4
UART5
0x1001_B090
UFCR_5
UART5 FIFO Control Register
UART5
0x1001_B094
USR1_5
UART5 Status Register 1
UART5
0x1001_B098
USR2_5
UART5 Status Register 2
UART5
0x1001_B09C
UESC_5
UART5 Escape Character Register
UART5
0x1001_B0A0
UTIM_5
UART5 Escape Timer Register
UART5
0x1001_B0A4
UBIR_5
UART5 BRM Incremental Register
UART5
0x1001_B0A8
UBMR_5
UART5 BRM Modulator Register
UART5
0x1001_B0AC
UBRC_5
UART5 Baud Rate Count Register
UART5
0x1001_B0B0
ONEMS_5
UART5 One Millisecond Register
UART5
0x1001_B0B4
UTS_5
UART6
0x1001_C000
UXRD_6
UART6 Receiver Register
UART6
0x1001_C040
UTXD_6
UART6 Transmitter Register
UART6
0x1001_C080
UCR1_6
UART6 Control Register
UART6
0x1001_C084
UCR2_6
UART6 Control Register 2
UART6
0x1001_C088
UCR3_6
UART6 Control Register 3
UART6
0x1001_C08C
UCR4_6
UART6 Control Register 4
UART6
0x1001_C090
UFCR_6
UART6 FIFO Control Register
UART6
0x1001_C094
USR1_6
UART6 Status Register 1
UART6
0x1001_C098
USR2_6
UART6 Status Register 2
UART6
0x1001_C09C
UESC_6
UART6 Escape Character Register
UART6
0x1001_C0A0
UTIM_6
UART6 Escape Timer Register
UART6
0x1001_C0A4
UBIR_6
UART6 BRM Incremental Register
UART5 Test Register 1
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-23
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
UART6
0x1001_C0A8
UBMR_6
UART6 BRM Modulator Register
UART6
0x1001_C0AC
UBRC_6
UART6 Baud Rate Count Register
UART6
0x1001_C0B0
ONEMS_6
UART6 One Millisecond Register
UART6
0x1001_C0B4
UTS_6
I2C 2
0x1001 D000
IADR
I2C Address Register
I2C 2
0x1001 D004
IFDR
I2C Frequency Divider Register
I2C 2
0x1001 D008
I2CR
I2C Control Register
I2C 2
0x1001 D00C
I2SR
I2C Status Register
I2C 2
0x1001 D010
I2DR
I2C Data I/O Register
SDHC3
0x1001 E000
STR_STP_CLK
SDHC3
0x1001 E004
STATUS (Read Only)
SDHC3
0x1001 E008
CLK_RATE
SDHC3
0x1001 E00C
CMD_DAT_CONT
MMC/SD2 Command and Data Control Register
SDHC3
0x1001 E010
RESPONSE_TO
MMC/SD2 Response Time Out Register
SDHC3
0x1001 E014
READ_TO
MMC/SD2 Read Time Out Register
SDHC3
0x1001 E018
BLK_LEN
MMC/SD2 Block Length Register
SDHC3
0x1001 E01C
NOB
MMC/SD2 Number of Block Register
SDHC3
0x1001 E020
REV_NO
MMC/SD2 Revision Number Register
SDHC3
0x1001 E024
INT_CNTL
MMC/SD2 Interrupt Control Register
SDHC3
0x1001 E028
CMD
MMC/SD2 Command Number Register
SDHC3
0x1001 E02C
ARGH
MMC/SD2 Higher Argument Register
SDHC3
0x1001 E030
ARGL
MMC/SD2 Lower Argument Register
SDHC3
0x1001 E034
RES_FIFO (Read Only)
MMC/SD2 Response FIFO Register
SDHC3
0x1001 E038
BUFFER_ACCESS
GPT6
0x1001 F000
TCTL6
GPT6
0x1001 F004
TPRER6
GPT Prescaler Register 6
GPT6
0x1001 F008
TCMP6
GPT Compare Register 6
GPT6
0x1001 F00C
TCR6
GPT Capture Register 6
GPT6
0x1001 F010
TCN6
GPT Counter Register 6
GPT6
0x1001 F014
TSTAT6
AIPI2
0x1002 0000
PSR0
Peripheral Size Register0
AIPI2
0x1002 0004
PSR1
Peripheral Size Register1
AIPI2
0x1002 0008
PAR
UART6 Test Register 1
MMC/SD2 Clock Control Register
MMC/SD2 Status Register
MMC/SD2 Clock Rate Register
MMC/SD2 Buffer Access Register
GPT Control Register 6
GPT Status Register 6
Peripheral Access Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-24
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
AIPI2
0x1002 000C
AAOR
Atomic Access Only Register
LCDC
0x1002 1000
LSSAR
LCDC Screen Start Address Register
LCDC
0x1002 1004
LSR
LCDC
0x1002 1008
LVPWR
LCDC
0x1002 100C
LCPR
LCDC
0x1002 1010
LCWHBR
LCDC
0x1002 1014
LCCMR
LCDC
0x1002 1018
LPCR
LCDC Panel Configuration Register
LCDC
0x1002 101C
LHCR
LCDC Horizontal Configuration Register
LCDC
0x1002 1020
LVCR
LCDC Vertical Configuration Register
LCDC
0x1002 1024
LPOR
LCDC Panning Offset Register
LCDC
0x1002 1028
LSCR
LCDC Sharp Configuration Register
LCDC
0x1002 102C
LPCCR
LCDC
0x1002 1030
LDCR
LCDC
0x1002 1034
LRMCR
LCDC Refresh Mode Control Register
LCDC
0x1002 1038
LICR
LCDC Interrupt Configuration Register
LCDC
0x1002 103C
LIER
LCDC Interrupt Enable Register
LCDC
0x1002 1040
LISR
LCDC Interrupt Status Register
LCDC
0x1002 1050
LGWSAR
LCDC
0x1002 1054
LGWSR
LCDC
0x1002 1058
LGWVPWR
LCDC
0x1002 105C
LGWPOR
LCDC
0x1002 1060
LGWPR
LCDC Graphic Window Position Register
LCDC
0x1002 1064
LGWCR
LCDC Graphic Window Control Register
LCDC
0x1002 1068
LGWDCR
LCDC Graphic Window DMA Control Register
LCDC
0x1002 1080
LAUSCR
LCDC Aus mode Control Register
LCDC
0x1002 1084
LAUSCCR
SLCDC
0x1002 2000
DATA_BASE_ADDR
SLCDC
0x1002 2004
DATA_BUFF_SIZE
SLCD Data Buffer Size Register
SLCDC
0x1002 2008
CMD_BASE_ADDR
SLCD Command Buffer Base Address Register
SLCDC
0x1002 200C
CMD_BUFF_SIZE
SLCD Command Buffer Size Register
SLCDC
0x1002 2010
CMD_STR_SIZE
SLCD Command String Size Register
SLCDC
0x1002 2014
FIFO_CONFIG
LCDC Size Register
LCDC Virtual Page Width Register
LCDC Cursor Position Register
LCDC Cursor Width Height and Blink Register
LCDC Color Cursor Mapping Register
LCDC PWM Contrast Control Register
LCDC DMA Control Register
LCDC Graphic Window Start Address Register
LCDC Graphic Window Size Register
LCDC Graphic Window Virtual Page Width Register
LCDC Graphic Window Panning Offset Register
LCDC Aus mode Cursor Control Register
SLCD Data Base Address Register
SLCD FIFO Configuration Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-25
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
SLCDC
0x1002 2018
LCD_CONFIG
SLCDC
0x1002 201C
LCD_XFER_CONFIG
SLCDC
0x1002 2020
DMA_CTRL_STAT
SLCD DMA Control/Status Register
SLCDC
0x1002 2024
LCD_CLK_CONFIG
SLCD Clock Configuration Register
SLCDC
0x1002 2028
LCD_WRITE_DATA
SLCD Write Data Register
Video Codec
0x1002 3000
CodeRun
Video Codec
0x1002 3004
CodeDownLoad
Video Codec
0x1002 3008
HostIntReq
Host Interrupt Request to BI
Video Codec
0x1002 300C
BitIntClear
BIT Interrupt Clear
Video Codec
0x1002 3010
BitIntSts
BIT Interrupt Status
Video Codec
0x1002 3100
WorkBufAddr
Working Buffer Address in External Memory
Video Codec
0x1002 3104
CodeBufAddr
Code Table Size in External Memory
Video Codec
0x1002 3108
BitStreamCtrl
Bit Stream Control
Video Codec
0x1002 310C
FrameMemCtrl
Video Codec
0x1002 3110
SramAddr
Internal SRAM Base Address
Video Codec
0x1002 3114
SramSize
Internal SRAM Size
Video Codec
0x1002 3140
BitStreamRdPtr
Bit Stream Buffer Read Address
Video Codec
0x1002 3144
BitStreamWrPtr
Bit Stream Buffer Write Address
Video Codec
0x1002 3148
FrameNum
Video Codec
0x1002 3160
BusyFlag
Video Codec
0x1002 3164
RunCommand
Video Codec
0x1002 3168
RunIndex
Video Codec
0x1002 316C
RunCodStd
Run Codec Standard
Video Codec
0x1002 3180
BitBufAddr
Parameter Registers in sequence initialization. Bitstream
Buffer Address
Video Codec
0x1002 3184
BitBufSize
Parameter Registers in sequence initialization. Bitstream
Buffer Size
Video Codec
0x1002 3188
FrameIntAddrY
Parameter Registers in sequence initialization. Temporal
Frame Y Address
Video Codec
0x1002 318C
FrameIntAddrCb
Parameter Registers in sequence initialization. Temporal
Frame Cb Address
Video Codec
0x1002 3190
FrameIntAddrCr
Parameter Registers in sequence initialization. Temporal
Frame Cr Address
Video Codec
0x1002 3194
EncCodStd
SLCD Configuration Register
SLCD Transfer Configuration Register
BIT run start
Code Download Data Register
Frame Memory Control
Encoded/Decoded Frame Number
Processing Busy Flag
Start/Stop Codec Run Command
Run Process Index
Parameter Registers in sequence initialization. Encode
Coding Standard
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-26
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
Video Codec
0x1002 3198
EncSrcFormat
Parameter Registers in sequence initialization. Encode
Source Frame Format
Video Codec
0x1002 319C
EncMp4Para
Parameter Registers in sequence initialization. Encode
MPEG4 Parameter
Video Codec
0x1002 31A0
Enc263Para
Parameter Registers in sequence initialization. Encode
H.263 Parameter
Video Codec
0x1002 31A4
Enc264Para
Parameter Registers in sequence initialization. Encode
H.264 Parameter
Video Codec
0x1002 31A8
EncSliceMode
Parameter Registers in sequence initialization. Encode
Slice Mode
Video Codec
0x1002 31AC
EncGopNum
Parameter Registers in sequence initialization. Encode
GOP Number
Video Codec
0x1002 31B0
EncPictureQs
Parameter Registers in sequence initialization. Encode
Picture Quantize Step
Video Codec
0x1002 31C0
RetStatus
Parameter Registers in sequence initialization. Command
Executing Result Status
Video Codec
0x1002 31C4
RetSrcFormat
Parameter Registers in sequence initialization. Decoded
Source Format
Video Codec
0x1002 31C8
RetMp4Info
Parameter Registers in sequence initialization. Decoded
MPEG4 Sequence Information
Video Codec
0x1002 31CC
Ret263Info
Parameter Registers in sequence initialization. Decoded
H.263 Sequence Information
Video Codec
0x1002 31D0
Ret264Info
Parameter Registers in sequence initialization. Decoded
H.264 Sequence Information
Video Codec
0x1002 3180
FrameSrcAddrY
Parameter Register in Processing Running.
Source Frame Y Address
Video Codec
0x1002 3184
FrameSrcAddrCb
Parameter Register in Processing Running.
Source Frame Cb Address
Video Codec
0x1002 3188
FrameSrcAddrCr
Parameter Register in Processing Running.
Source Frame Cr Address
Video Codec
0x1002 318C
FrameDecAddrY
Parameter Register in Processing Running.
Decode Frame Y Address
Video Codec
0x1002 3190
FrameDecAddrCb
Parameter Register in Processing Running.
Decode Frame Cb Address
Video Codec
0x1002 3194
FrameDecAddrCr
Parameter Register in Processing Running.
Decode Frame Cr Address
Video Codec
0x1002 31C0
RetStatus
Parameter Register in Processing Running. Command
Executing Result Status
USBOTG
0x1002 4000
UOG_ID
ID (UOG_ID)
USBOTG
0x1002 4004
UOG_HWGENERAL
Hardware General (UOG_HWGENERAL)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-27
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
USBOTG
0x1002 4008
UOG_HWHOST
USBOTG
0x1002 400C
UOG_HWDEVICE
Device Hardware Parameters (UOG_HWDEVICE)
USBOTG
0x1002 4010
UOG_HWTXBUF
TX Buffer Hardware Parameters (UOG_HWTXBUF)
USBOTG
0x1002 4014
UOG_HWRXBUF
RX Buffer Hardware Parameters (UOG_HWRXBUF)
USBOTG
0x1002 4080
GPTIMER0LD
USBOTG
0x1002 4084
GPTIMER0CTRL
USBOTG
0x1002 4088
GPTIMER0LD
USBOTG
0x1002 408C
GPTIMER0CTRL
USBOTG
0x1002 4100
UOG_CAPLENGTH
Capability Register Length (UOG_CAPLENGTH)
USBOTG
0x1002 4102
UOG_HCIVERSION
Host Interface Version (UOG_HCIVERSION)
USBOTG
0x1002 4104
UOG_HCSPARAMS
Host Control Structural Parameters (UOG_HCSPARAMS)
USBOTG
0x1002 4108
UOG_HCCPARAMS
Control Capability Parameters (UOG_HCCPARAMS)
USBOTG
0x1002 4120
UOG_DCIVERSION
Device Interface Version (UOG_DCIVERSION)
USBOTG
0x1002 4124
UOG_DCCPARAMS
Device Controller Capability Parameters
(UOG_DCCPARAMS)
USBOTG
0x1002 4140
UOG_USBCMD
USB Command Register (UOG_USBCMD)
USBOTG
0x1002 4144
UOG_USBSTS
USB Status Register (UOG_USBSTS)
USBOTG
0x1002 4148
UOG_USBINTR
Interrupt Enable Register (UOG_USBINTR)
USBOTG
0x1002 414C
UOG_FRINDEX
USB Frame Index (UOG_FRINDEX)
USBOTG
0x1002 4154
UOG_PERIODICLISTBASE
USBOTG
0x1002 4158
UOG_ASYNCLISTADDR
USBOTG
0x1002 4160
UOG_BURSTSIZE
USBOTG
0x1002 4164
UOG_TXFILLTUNING
USBOTG
0x1002 4170
ULPIVIEW
USBOTG
0x1002 4180
UOG_CFGFLAG
Config Flag (UOG_CFGFLAG)
USBOTG
0x1002 4184
UOG_PORTSC1
Port Status and Control (UOG_PORTSC1)
USBOTG
0x1002 41A4
UOG_OTGSC
USBOTG
0x1002 41A8
UOG_USBMODE
USBOTG
0x1002 41AC
UOG_ENDPTSETUPSTAT
USBOTG
0x1002 41B0
UOG_ENDPTPRIME
Endpoint Initialization (UOG_ENDPTPRIME)
USBOTG
0x1002 41B4
UOG_ENDPTFLUSH
Endpoint De-Initialize (UOG_ENDPTFLUSH)
Host Hardware Parameters (UOG_HWHOST)
General Purpose Timer #0 Load (GPTIMER0LD)
General Purpose Timer #0 Controller (GPTIMER0CTRL)
General Purpose Timer #1 Load (GPTIMER0LD)
General Purpose Timer #1 Controller (GPTIMER0CTRL)
Host Controller Frame List Base Address
(UOG_PERIODICLISTBASE)
Host Controller Next Asynch. Address
(UOG_ASYNCLISTADDR)
Host Controller Embedded TT Asynch. Buffer Status
(UOG_BURSTSIZE)
TX FIFO Fill Tuning (UOG_TXFILLTUNING)
ULPI Viewport (ULPIVIEW)
On-The-Go Status and control (UOG_OTGSC)
USB Device Mode (UOG_USBMODE)
Endpoint Setup Status (UOG_ENDPTSETUPSTAT)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-28
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
USBOTG
0x1002 41B8
UOG_ENDPTSTAT
USBOTG
0x1002 41BC
UOG_ENDPTCOMPLETE
USBOTG
0x1002 41C0
ENDPTCTRL0
Endpoint Control 0 (ENDPTCTRL0)
USBOTG
0x1002 41C4
ENDPTCTRL1
Endpoint Control 1 (ENDPTCTRL1)
USBOTG
0x1002 41C8
ENDPTCTRL2
Endpoint Control 2 (ENDPTCTRL2)
USBOTG
0x1002 41CC
ENDPTCTRL3
Endpoint Control 3 (ENDPTCTRL3)
USBOTG
0x1002 41D0
ENDPTCTRL4
Endpoint Control 4 (ENDPTCTRL4)
USB OTG
0x1002 41D4
ENDPTCTRL5
Endpoint Control 5 (ENDPTCTRL5)
USB OTG
0x1002 41D8
ENDPTCTRL6
Endpoint Control 6 (ENDPTCTRL6)
USBOTG
0x1002 41DC
ENDPTCTRL7
Endpoint Control 7 (ENDPTCTRL7)
USBOTG
0x1002 4200
UH1_ID
USBOTG
0x1002 4204
UH1_HWGENERAL
USBOTG
0x1002 4208
UH1_HWHOST
Host Hardware Parameters (UH1_HWHOST)
USBOTG
0x1002 4210
UH1_HWTXBUF
TX Buffer Hardware Parameters (UH1_HWTXBUF)
USBOTG
0x1002 4214
UH1_HWRXBUF
RX Buffer Hardware Parameters (UH1_HWRXBUF)
USBOTG
0x1002 4280
GPTIMER0LD
USBOTG
0x1002 4284
GPTIMER0CTRL
USBOTG
0x1002 4288
GPTIMER0LD
USBOTG
0x1002 428C
GPTIMER0CTRL
USBOTG
0x1002 4300
UH1_CAPLENGTH
Capability Register Length (UH1_CAPLENGTH)
USBOTG
0x1002 4302
UH1_HCIVERSION
Host Interface Version (UH1_HCIVERSION)
USBOTG
0x1002 4304
UH1_HCSPARAMS
Host Control Structural Parameters (UH1_HCSPARAMS)
USBOTG
0x1002 4308
UH1_HCCPARAMS
Control Capability Parameters (UH1_HCCPARAMS)
USBOTG
0x1002 4340
UH1_USBCMD
USB Command Register (UH1_USBCMD)
USBOTG
0x1002 4344
UH1_USBSTS
USB Status Register (UH1_USBSTS)
USBOTG
0x1002 4348
UH1_USBINTR
Interrupt Enable Register (UH1_USBINTR)
USBOTG
0x1002 434C
UH1_FRINDEX
USB Frame Index (UH1_FRINDEX)
USBOTG
0x1002 4354
UH1_PERIODICLISTBASE
USBOTG
0x1002 4358
UH1_ASYNCLISTADDR
USBOTG
0x1002 4360
UH1_BURSTSIZE
USBOTG
0x1002 4364
UH1_TXFILLTUNING
Endpoint Status (UOG_ENDPTSTAT)
Endpoint Complete (UOG_ENDPTCOMPLETE)
Host 1 ID (UH1_ID)
Hardware General (UH1_HWGENERAL)
General Purpose Timer #0 Load (GPTIMER0LD)
General Purpose Timer #0 Controller (GPTIMER0CTRL)
General Purpose Timer #1 Load (GPTIMER0LD)
General Purpose Timer #1 Controller (GPTIMER0CTRL)
Host Controller Frame List Base Address
(UH1_PERIODICLISTBASE)
Host Controller Next Asynch. Address
(UH1_ASYNCLISTADDR)
Host Controller Embedded TT Asynch. Buffer Status
(UH1_BURSTSIZE)
TX FIFO Fill Tuning (UH1_TXFILLTUNING)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-29
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
USBOTG
0x1002 4380
—
USBOTG
0x1002 4838
Reserved
Port Status and Control (UH1_PORTSC1)
USBOTG
0x1002 4384
UH1_PORTSC1
Port Status and Control (UH1_PORTSC1)
USBOTG
0x1002 483C
Reserved
USBOTG
0x1002 43A8
UH1_USBMODE
USBOTG
0x1002 4400
UH2_ID
USBOTG
0x1002 4404
UH2_HWGENERAL
USBOTG
0x1002 4408
UH2_HWHOST
Host Hardware Parameters (UH2_HWHOST)
USBOTG
0x1002 4410
UH2_HWTXBUF
TX Buffer Hardware Parameters (UH2_HWTXBUF)
USBOTG
0x1002 4414
UH2_HWRXBUF
RX Buffer Hardware Parameters (UH2_HWRXBUF)
USBOTG
0x1002 4480
GPTIMER0LD
USBOTG
0x1002 4484
GPTIMER0CTRL
USBOTG
0x1002 4488
GPTIMER0LD
USBOTG
0x1002 448C
GPTIMER0CTRL
USBOTG
0x1002 4500
UH2_CAPLENGTH
Capability Register Length (UH2_CAPLENGTH)
USBOTG
0x1002 4502
UH2_HCIVERSION
Host Interface Version (UH2_HCIVERSION)
USBOTG
0x1002 4504
UH2_HCSPARAMS
Host Control Structural Parameters (UH2_HCSPARAMS)
USBOTG
0x1002 4508
UH2_HCCPARAMS
Control Capability Parameters (UH2_HCCPARAMS)
USBOTG
0x1002 4540
UH2_USBCMD
USB Command Register (UH2_USBCMD)
USBOTG
0x1002 4544
UH2_USBSTS
USB Status Register (UH2_USBSTS)
USBOTG
0x1002 4548
UH2_USBINTR
Interrupt Enable Register (UH2_USBINTR)
USBOTG
0x1002 454C
UH2_FRINDEX
USB Frame Index (UH2_FRINDEX)
USBOTG
0x1002 4554
UH2_PERIODICLISTBASE
USBOTG
0x1002 4558
UH2_ASYNCLISTADDR
USBOTG
0x1002 4560
UH2_BURSTSIZE
USBOTG
0x1002 4564
UH2_TXFILLTUNING
USBOTG
0x1002 4570
ULPIVIEW
USBOTG
0x1002 4580
—
USBOTG
0x1002 4584
UH2_PORTSC1
Port Status and Control (UH2_PORTSC1)
USBOTG
0x1002 45A8
UH2_USBMODE
USB Device Mode (UH2_USBMODE)
USBOTG
0x1002 4600
USB_CTRL
Reserved
Reserved
USB Device Mode (UH1_USBMODE)
ID (UH2_ID)
Hardware General (UH2_HWGENERAL)
General Purpose Timer #0 Load (GPTIMER0LD)
General Purpose Timer #0 Controller (GPTIMER0CTRL)
General Purpose Timer #1 Load (GPTIMER0LD)
General Purpose Timer #1 Controller (GPTIMER0CTRL)
Host Controller Frame List Base Address
(UH2_PERIODICLISTBASE)
Host Controller Next Asynch. Address
(UH2_ASYNCLISTADDR)
Host Controller Embedded TT Asynch. Buffer Status
(UH2_BURSTSIZE)
TX FIFO Fill Tuning (UH2_TXFILLTUNING)
ULPI Viewport (ULPIVIEW)
Reserved
USB Control Register (USB_CTRL)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-30
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
USBOTG
0x1002 4604
USB_OTG_MIRROR
SAHARA2
0x1002 5000
VER_ID
SAHARA2
0x1002 5004
DSC_ADR
SAHARA2 Descriptor Address Register
SAHARA2
0x1002 5008
CONTROL
SAHARA2 Control Register
SAHARA2
0x1002 500C
COMMAND
SAHARA2 Command Register
SAHARA2
0x1002 5010
STAT
SAHARA2
0x1002 5014
ERR_STAT
SAHARA2 Error Status Register
SAHARA2
0x1002 5018
FAULT_ADR
SAHARA2 Fault Address Register
SAHARA2
0x1002 501C
C_DSC_ADR
SAHARA2 Current Descriptor Address Register
SAHARA2
0x1002 5020
I_DSC_ADR
SAHARA2 Initial Descriptor Address Register
SAHARA2
0x1002 5024
BUFF_LVL
SAHARA2
0x1002 5080
DSC_A
Location to Store Descriptor
SAHARA2
0x1002 5084
DSC_B
Location to Store Descriptor
SAHARA2
0x1002 5088
DSC_C
Location to Store Descriptor
SAHARA2
0x1002 508C
DSC_D
Location to Store Descriptor
SAHARA2
0x1002 5090
DSC_E
Location to Store Descriptor
SAHARA2
0x1002 5094
DSC_F
Location to Store Descriptor
SAHARA2
0x1002 50A0
LNK_1_A
Location to Store Link Data
SAHARA2
0x1002 50A4
LNK_1_B
Location to Store Link Data
SAHARA2
0x1002 50A8
LNK_1_C
Location to Store Link Data
SAHARA2
0x1002 50B0
LNK_2_A
Location to Store Link Data
SAHARA2
0x1002 50B4
LNK_2_B
Location to Store Link Data
SAHARA2
0x1002 50B8
LNK_2_C
Location to Store Link Data
SAHARA2
0x1002 50C0
FLOW_CTRL
SAHARA2 Internal Buffer and Data-Paths Control Register
SAHARA2
0x1002 5100
SKHA_MODE
SKHA Mode Register
SAHARA2
0x1002 5104
SKHA_KEY_SIZE
SKHA Key Size Register
SAHARA2
0x1002 5108
SKHA_DATA_SIZE
SKHA Data Size Register
SAHARA2
0x1002 510C
SKHA_STAT
SAHARA2
0x1002 5110
SKHA_ERR_STAT
SAHARA2
0x1002 5114
SKHA_End-of-Message
SAHARA2
0x1002 5140–
0x1002 517F
SKHA_CXT
USB OTG Mirror Register (USB_OTG_MIRROR)
SAHARA2 Version ID Register
SAHARA2 Status Register
SAHARA2 Buffer Level Register
SKHA Status Register
SKHA Error Status Register
SKHA End-of-Message Register
SKHA Context Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-31
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
SAHARA2
0x1002 5180–
0x1002 51FF
SKHA Key
SAHARA2
0x1002 5200
MDHA_MODE
SAHARA2
0x1002 5204
MDHA_KEY_SIZE
MDHA Key Size Register
SAHARA2
0x1002 5208
MDHA_DATA_SIZE
MDHA Data Size Register
SAHARA2
0x1002 520C
MDHA_STAT
SAHARA2
0x1002 5210
MDHA_ERR_STAT
SAHARA2
0x1002 5214
MDHA_End-of-Message
SAHARA2
0x1002 5240–
0x1002 5254
MDHA_Digest and Length
SAHARA2
0x1002 5280–
0x1002 52FF
MDHA_Key
MDHA Keys
SAHARA2
0x1002 5300
RNG_Mode
RNG Mode Register
SAHARA2
0x1002 5308
RNG_Data_SIZE
SAHARA2
0x1002 530C
RNG_STAT
SAHARA2
0x1002 5310
RNG_ERROR_STAT
SAHARA2
0x1002 5314
RNG_End-of-Message
RNG End-of-Message Register
SAHARA2
0x1002 5340–
0x1002 537F
RNG_VERIFICATION
RNG Verification Register
SAHARA2
0x1002 5380
RNG_ENTROPY
RNG Entropy Register
SAHARA2
0x1002 5400–
0x1002 54FF
Data Input Buffer
Data Input Buffers
SAHARA2
0x1002 5500–
0x1002 55FF
Data Output Buffer
Data Output Buffers
SAHARA2
0x1002 5600–
0x1002 57FF
SBOX CONTEXT
SBOX Context
eMMA_lt
0x1002 6000
PP_CNTL
eMMA_lt
0x1002 6004
PP_INTRCNTL
PP Interrupt Control Register
eMMA_lt
0x1002 6008
PP_INTRSTATUS
PP interrupt Status Register
eMMA_lt
0x1002 600C
PP_SOURCE_Y_PTR
eMMA_lt
0x1002 6010
PP_SOURCE_CB_PTR
PP Source “CB” Frame Data Pointer Register
eMMA_lt
0x1002 6014
PP_SOURCE_CR_PTR
PP Source “CR” Frame Data Pointer Register
eMMA_lt
0x1002 6018
PP_DEST_RGB_PTR
PP Destination “RGB” Frame Start Address Register
eMMA_lt
0x1002 601C
PP_QUANTIZER_PTR
PP Quantizer Start Address Register
eMMA_lt
0x1002 6020
PP_PROCESS_FRAME_PARA
SKHA Key Register
MDHA Mode Register
MDHA Status Register
MDHA Error Status Register
MDHA End-of-Message Register
MDHA Message Digest and Length Register
RNG Data Size Register
RNG Status Register
RNG Error Status Register
PP Control Register
PP Source “Y” FramE Data Pointer Register
PP Process Frame Parameter, Width And Height Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-32
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
eMMA_lt
0x1002 6024
eMMA_lt
0x1002 6028
PP_DEST_DISPLAY_WIDTH
eMMA_lt
0x1002 602C
PP_DEST_IMAGE_SIZE
eMMA_lt
0x1002 6030
eMMA_lt
0x1002 6034
PP Resize Table index Reg
eMMA_lt
0x1002 6038
PP_CSC_COEFF_012
PP CSC Coefficient 0, 1, and 2 Register
eMMA_lt
0x1002 603C
PP_CSC_COEFF_34
PP CSC Coefficient 3 and 4 Register
eMMA_lt
0x1002 6100–
0x1002 617C
PP_RESIZE_COEF_TBL
PP Resize Coefficient Table Register
eMMA_lt
0x1002 6400
PrP_CNTL
eMMA_lt
0x1002 6404
PrP_INTRCNTL
PrP Interrupt Control Register
eMMA_lt
0x1002 6408
PrP_INTRSTATUS
PrP interrupt Status Register
eMMA_lt
0x1002 640C
PrP_SOURCE_Y_PTR
eMMA_lt
0x1002 6410
PrP_SOURCE_CB_PTR
PrP Source “CB” Frame Start Address Register
eMMA_lt
0x1002 6414
PrP_SOURCE_CR_PTR
PrP Source “CR” Frame Start Address Register
eMMA_lt
0x1002 6418
PrP_DEST_RGB1_PTR
PrP Destination “RGB” Frame-1 Start Address Register
eMMA_lt
0x1002 641C
PrP_DEST_RGB2_PTR
PrP Destination “RGB” Frame-2 Start Address Register
eMMA_lt
0x1002 6420
PrP_DEST_Y_PTR
eMMA_lt
0x1002 6424
PrP_DEST_CB_PTR
PrP Destination “CB” Frame Start Address Register
eMMA_lt
0x1002 6428
PrP_DEST_CR_PTR
PrP Destination “CR” Frame Start Address Register
eMMA_lt
0x1002 642C
PrP_SOURCE_FRAME_SIZE
eMMA_lt
0x1002 6430
PrP_CH1_LINE_STRIDE
eMMA_lt
0x1002 6434
PrP_SRC_PIXEL_FORMAT_CN PrP Source Pixel Format Control Register
TL
eMMA_lt
0x1002 6438
PrP_CH1_PIXEL_FORMAT_CN PrP CH1 Pixel Format Control Register
TL
eMMA_lt
0x1002 643C
PrP_CH1_OUT_IMAGE_SIZE
PrP CH1 Output Image Size Register
eMMA_lt
0x1002 6440
PrP_CH2_OUT_IMAGE_SIZE
PrP CH2 Output Image Size Register
eMMA_lt
0x1002 6444
PrP_SOURCE_LINE_STRIDE
PrP Source Line Stride Register
eMMA_lt
0x1002 6448
PrP_CSC_COEFF_012
PrP CSC Coefficients 0, 1, and 2 Register
eMMA_lt
0x1002 644C
PrP_CSC_COEFF_345
PrP CSC Coefficients 3, 4, and 5 Register
eMMA_lt
0x1002 6450
PrP_CSC_COEFF_678
PrP CSC Coefficients 6, 7, and 8 Register
eMMA_lt
0x1002 6454
PrP_CH1_HRESIZE_COEFF1
PrP CH1 Horizontal Resize Coefficients Register
eMMA_lt
0x1002 6458
PrP_CH1_HRESIZE_COEFF2
PrP CH1 Horizontal Resize Coefficients Register
PP_SOURCE_FRAME_WIDTH PP Source Frame Width Register
PP Destination Display Width Register
PP Destination Image Size Register
PP_DEST_FRAME_FMT_CNTL PP Destination Frame Format Control Register
PP Resize Table Index Register
PrP Control Register
PrP Source “Y” Frame Start Address Register
PrP Destination “Y” Frame Start Address Register
PrP Source Frame Size Register
PrP Channel-1 Line stride Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-33
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
eMMA_lt
0x1002 645C
PrP_CH1_HRESIZE_VALID
eMMA_lt
0x1002 6460
PrP_CH1_VRESIZE_COEFF1
PrP CH1 Vertical Resize Coefficients Register
eMMA_lt
0x1002 6464
PrP_CH1_VRESIZE_COEFF2
PrP CH1 Vertical Resize Coefficients Register
eMMA_lt
0x1002 6468
PrP_CH1_VRESIZE_VALID
eMMA_lt
0x1002 646C
PrP_CH2_HRESIZE_COEFF1
PrP CH2 Horizontal Resize Coefficients Register
eMMA_lt
0x1002 6470
PrP_CH2_HRESIZE_COEFF2
PrP CH2 Horizontal Resize Coefficients Register
eMMA_lt
0x1002 6474
PrP_CH2_HRESIZE_VALID
eMMA_lt
0x1002 6478
PrP_CH2_VRESIZE_COEFF1
PrP CH2 Vertical Resize Coefficients Register
eMMA_lt
0x1002 647C
PrP_CH2_VRESIZE_COEFF2
PrP CH2 Vertical Resize Coefficients Register
eMMA_lt
0x1002 6480
PrP_CH2_VRESIZE_VALID
PLLCLK
0x1002 7000
CSCR
PLLCLK
0x1002 7004
MPCTL0
MPLL Control Register 0
PLLCLK
0x10027008
MPCTL1
MPLL Control Register 1
PLLCLK
0x1002700C
SPCTL0
SPLL Control Register 0
PLLCLK
0x10027010
SPCTL1
SPLL Control Register 1
PLLCLK
0x10027014
OSC26MCTL
Oscillator 26M Register
PLLCLK
0x10027018
PCDR0
Peripheral Clock Divider Register 0
PLLCLK
0x1002701C
PCDR1
Peripheral Clock Divider Register 1
PLLCLK
0x10027020
PCCR0
Peripheral Clock Control Register 0
PLLCLK
0x10027024
PCCR1
Peripheral Clock Control Register 1
PLLCLK
0x10027028
CCSR
Clock Control Status Register
PLLCLK
0x1002702C
PMCTL
PMOS Switch Control Register
PLLCLK
0x10027030
PMCOUNT
PMOS Switch Counter Register
PLLCLK
0x10027034
WKGDCTL
Wakeup Guard Mode Control Register
SYSCTRL
0x10027800
CID
SYSCTRL
0x10027814
FMCR
Function Multiplexing Control Register
SYSCTRL
0x10027818
GPCR
Global Peripheral Control Register
SYSCTRL
0x1002781C
WBCR
Well Bias Control Register
SYSCTRL
0x10027820
DSCR1
Driving Strength Control Register 1
SYSCTRL
0x10027824
DSCR2
Driving Strength Control Register 2
SYSCTRL
0x10027828
DSCR3
Driving Strength Control Register 3
SYSCTRL
0x1002782C
DSCR4
Driving Strength Control Register 4
SYSCTRL
0x10027830
DSCR5
Driving Strength Control Register 5
PrP CH1 Horizontal Resize Valid Register
PrP CH1 Vertical Resize Valid Register
PrP CH2 Horizontal Resize Valid Register
PrP CH2 Vertical Resize Valid Register
Clock Source Control Register
Chip ID Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-34
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
SYSCTRL
0x10027834
DSCR6
Driving Strength Control Register 6
SYSCTRL
0x10027838
DSCR7
Driving Strength Control Register 7
SYSCTRL
0x1002783C
DSCR8
Driving Strength Control Register 8
SYSCTRL
0x10027840
DSCR9
Driving Strength Control Register 9
SYSCTRL
0x1002 7844
DSCR10
Driving Strength Control Register 10
SYSCTRL
0x1002 7848
DSCR11
Driving Strength Control Register 11
SYSCTRL
0x1002 784C
DSCR12
Driving Strength Control Register 12
SYSCTRL
0x1002 7850
DSCR13
Driving Strength Control Register 13
SYSCTRL
0x1002 7854
PSCR
Pull Strength Control Register
SYSCTRL
0x1002 7858
PCSR
Priority Control and Select Register
SYSCTRL
0x1002 7860
PMCR
Power Management Control Register
SYSCTRL
0x1002 7864
DCVR0
DPTC Comparator Value Register 0
SYSCTRL
0x1002 7868
DCVR‘
DPTC Comparator Value Register 1
SYSCTRL
0x1002 786C
DCVR2
DPTC Comparator Value Register 2
SYSCTRL
0x1002 7870
DCVR3
DPTC Comparator Value Register 3
IIM
0x1002_8000
STAT
IIM
0x1002_8004
STATM
IIM
0x1002_8008
ERR
IIM
0x1002_800C
EMASK
IIM
0x1002_8010
FCTL
IIM
0x1002_8014
UA
Upper Address Register
IIM
0x1002_8018
LA
Lower Address Register
IIM
0x1002_801C
SDAT
Explicit Sense Data Register
IIM
0x1002_8020
PREV
Product Revision Register
IIM
0x1002_8024
SREV
Silicon Revision Register
IIM
0x1002_8028
PROG_P
IIM
0x1002_802C
SCS0
Software_Controllable Signals Register 0
IIM
0x1002_8030
SCS1
IIM
0x1002_8034
SCS2
Software_Controllable Volatile Hardware—Visible Signals
Register (1–3)
IIM
0x1002_8038
SCS3
IIM
0x1002_803C
FBAC0
IIM
0x1002_8804
WORD1_BANK0
Word 1 of Fusebank 0
IIM
0x1002_8808
WORD2_BANK0
Word 2 of Fusebank 0
Status Register
Status IRQ Mask Register
Module Errors Register
Error IRQ Mask Register
Fuse Control Register
Program Protection Register
Fuse Bank 0 Access Protection Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-35
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
IIM
0x1002_880C
WORD3_BANK0
Word 3 of Fusebank 0
IIM
0x1002_8810
WORD4_BANK0
Word 4 of Fusebank 0
IIM
0x1002_8814–
0x1002_8828
MAC_ADDR
IIM
0x1002_882C–
0x1002_887C
SCC_KEY
IIM
0x1002_8C00
FBAC1
IIM
0x1002_8C04–
0x1002_8C18
SUID
IIM
0x1002_8C1C–
0x1002_8C7C
RESERVED
RTIC
0x1002 A000
RTICSR
RTIC
0x1002 A004
RTICCMDR
RTIC Command Register
RTIC
0x1002 A008
RTICCNTLR
RTIC Control Register
RTIC
0x1002 A00C
RTICTR
RTIC Throttle Register
RTIC
0x1002 A010
RTICAMSAR1
RTIC
0x1002 A014
RTICAMLR1
RTIC
0x1002 A0018
RTICAMSAR2
RTIC
0x1002 A01C
RTICAMLR2
RTIC
0x1002 A030
RTICBMSAR1
RTIC
0x1002 A034
RTICBMLR1
RTIC
0x1002 A038
RTICBMSAR2
RTIC
0x1002 A003C
RTICBMLR2
RTIC
0x1002 A050
RTICCMSAR1
RTIC
0x1002 A054
RTICCMLR1
RTIC
0x1002 A058
RTICCMSAR2
RTIC
0x1002 A05C
RTICCMLR2
RTIC
0x1002 A070
RTICDMSAR1
RTIC
0x1002 A074
RTICDMLR1
RTIC
0x1002 A078
RTICDMSAR2
RTIC
0x1002 A07C
RTICDMLR2
RTIC
0x1002 A090
RTICFAR
RTIC Fault Address Register
RTIC
0x1002 A094
RTICWR
RTIC Watchdog Register
RTIC
0x1002 A0A0
RTICAMHR1
MAC Address of Ethernet
SCC_KEY[167:0]
Fuse Bank 0 Access Protection register
Silicon_Unique_ID[47:0]
Reserved for future use
RTIC Status Register
RTIC Memory A Start Address Register 1
RTIC Memory A Len Register 1
RTIC Memory A Start Address Register 2
RTIC Memory A Len Register 2
RTIC Memory B Start Address Register 1
RTIC Memory B Len Register 1
RTIC Memory B Start Address Register 2
RTIC Memory B Len Register 2
RTIC Memory C Start Address Register 1
RTIC Memory C Len Register 1
RTIC Memory C Start Address Register 2
RTIC Memory C Len Register 2
RTIC Memory D Start Address Register 1
RTIC Memory D Len Register 1
RTIC Memory D Start Address Register 2
RTIC Memory D Len Register 2
RTIC Memory A Hash Result [159:128]
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-36
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
RTIC
0x1002 A0A4
RTICAMHR2
RTIC Memory A Hash Result [127:96]
RTIC
0x1002 A0A8
RTICAMHR3
RTIC Memory A Hash Result [95:64]
RTIC
0x1002 A0AC
RTICAMHR4
RTIC Memory A Hash Result [63:32]
RTIC
0x1002 A0B0
RTICAMHR5
RTIC Memory A Hash Result [31:0]
RTIC
0x1002 A0C0
RTICBMHR1
RTIC Memory B Hash Result [159:128]
RTIC
0x1002 A0C4
RTICBMHR2
RTIC Memory B Hash Result [127:96]
RTIC
0x1002 A0C8
RTICBMHR3
RTIC Memory B Hash Result [95:64]
RTIC
0x1002 A0CC
RTICBMHR4
RTIC Memory B Hash Result [63:32
RTIC
0x1002 A0D0
RTICBMHR5
RTIC Memory B Hash Result [31:0]
RTIC
0x1002 A0E0
RTICCMHR1
RTIC Memory C Hash Result [159:128]
RTIC
0x1002 A0E4
RTICCMHR2
RTIC Memory C Hash Result [127:96]
RTIC
0x1002 A0E8
RTICCMHR3
RTIC Memory C Hash Result [95:64]
RTIC
0x1002 A0EC
RTICCMHR4
RTIC Memory C Hash Result [63:32]
RTIC
0x1002 A0F0
RTICCMHR5
RTIC Memory C Hash Result [31:0]
RTIC
0x1002 A100
RTICDMHR1
RTIC Memory D Hash Result [159:128]
RTIC
0x1002 A104
RTICDMHR2
RTIC Memory D Hash Result [127:96]
RTIC
0x1002 A108
RTICDMHR3
RTIC Memory D Hash Result [95:64]
RTIC
0x1002 A10C
RTICDMHR4
RTIC Memory D Hash Result [63:32]
RTIC
0x1002 A110
RTICDMHR5
RTIC Memory D Hash Result [31:0]
FEC
0x1002 B004
EIR
Interrupt Event Register
FEC
0x1002 B008
EIMR
Interrupt Mask Register
FEC
0x1002 B010
RDAR
Receive Descriptor Active Register
FEC
0x1002 B014
TDAR
Transmit Descriptor Active Register
FEC
0x1002 B024
ECR
Ethernet Control Register
FEC
0x1002 B040
MMFR
MII Management Frame Register
FEC
0x1002 B044
MSCR
MII Speed Control Register
FEC
0x1002 B064
MIBC
MIB Control/Status Register
FEC
0x1002 B084
RCR
Receive Control Register
FEC
0x1002 B0C4
TCR
Transmit Control Register
FEC
0x1002 B0E4
PALR
Physical Address Low Register
FEC
0x1002 B0E8
PAUR
Physical Address High+ Type Field
FEC
0x1002 B0EC
OPD
Opcode + Pause Duration
FEC
0x1002 B118
IAUR
Upper 32 bits of Individual Hash Table
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-37
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
FEC
0x1002 B11C
IALR
Lower 32 Bits of Individual Hash Table
FEC
0x1002 B120
GAUR
Upper 32 bits of Group Hash Table
FEC
0x1002 B124
GALR
Lower 32 bits of Group Hash Table
FEC
0x1002 B144
TFWR
Transmit FIFO Watermark
FEC
0x1002 B14C
FRBR
FIFO Receive Bound Register
FEC
0x1002 B150
FRSR
FIFO Receive FIFO Start Registers
FEC
0x1002 B180
ERDSR
Pointer to Receive Descriptor Ring
FEC
0x1002 B184
ETDSR
Pointer to Transmit Descriptor Ring
FEC
0x1002 B188
EMRBR
Maximum Receive Buffer Size
FEC
0x1002 B200
RMON_T_DROP
FEC
0x1002 B204
RMON_T_PACKETS
RMON Tx packet count
FEC
0x1002 B208
RMON_T_BC_PKT
RMON Tx Broadcast Packets
FEC
0x1002 B20C
RMON_T_MC_PKT
RMON Tx Multicast Packets
FEC
0x1002 B210
RMON_T_CRC_ALIGN
RMON Tx Packets w CRC/Align error
FEC
0x1002 B214
RMON_T_UNDERSIZE
RMON Tx Packets < 64 bytes, good crc
FEC
0x1002 B218
RMON_T_OVERSIZE
FEC
0x1002 B21C
RMON_T_FRAG
FEC
0x1002 B220
RMON_T_JAB
RMON Tx Packets > MAX_FL bytes, bad crc
FEC
0x1002 B224
RMON_T_COL
RMON Tx collision count
FEC
0x1002 B228
RMON_T_P64
RMON Tx 64 byte packets
FEC
0x1002 B22C
RMON_T_P65TO127
RMON Tx 65 to 127 byte packets
FEC
0x1002 B230
RMON_T_P128TO255
RMON Tx 128 to 255 byte packets
FEC
0x1002 B234
RMON_T_P256TO511
RMON Tx 256 to 511 byte packets
FEC
0x1002 B238
RMON_T_P512TO1023
RMON Tx 512 to 1023 byte packets
FEC
0x1002 B23C
RMON_T_P1024TO2047
RMON Tx 1024 to 2047 byte packets
FEC
0x1002 B240
RMON_T_P_GTE2048
FEC
0x1002 B244
RMON_T_OCTETS
FEC
0x1002 B248
IEEE_T_DROP
FEC
0x1002 B24C
IEEE_T_FRAME_OK
FEC
0x1002 B250
IEEE_T_1COL
Frames Transmitted with Single Collision
FEC
0x1002 B254
IEEE_T_MCOL
Frames Transmitted with Multiple Collisions
FEC
0x1002 B258
IEEE_T_DEF
Frames Transmitted after Deferral Delay
FEC
0x1002 B25C
IEEE_T_LCOL
Frames Transmitted with Late Collision
Count of frames not counted correctly
RMON Tx Packets > MAX_FL bytes, good crc
RMON Tx Packets < 64 bytes, bad crc
RMON Tx packets w > 2048 bytes
RMON Tx Octets
Count of frames not counted correctly
Frames Transmitted OK
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
FEC
0x1002 B260
IEEE_T_EXCOL
FEC
0x1002 B264
IEEE_T_MACERR
Frames Transmitted with Tx FIFO Underrun
FEC
0x1002 B268
IEEE_T_CSERR
Frames Transmitted with Carrier Sense Error
FEC
0x1002 B26C
IEEE_T_SQE
FEC
0x1002 B270
IEEE_T_FDXFC
FEC
0x1002 B274
IEEE_T_OCTETS_OK
FEC
0x1002 B284
RMON_R_PACKETS
RMON Rx packet count
FEC
0x1002 B288
RMON_R_BC_PKT
RMON Rx Broadcast Packets
FEC
0x1002 B28C
RMON_R_MC_PKT
RMON Rx Multicast Packets
FEC
0x1002 B290
RMON_R_CRC_ALIGN
RMON Rx Packets w CRC/Align error
FEC
0x1002 B294
RMON_R_UNDERSIZE
RMON Rx Packets < 64 bytes, good crc
FEC
0x1002 B298
RMON_R_OVERSIZE
FEC
0x1002 B29C
RMON_R_FRAG
FEC
0x1002 B2A0
RMON_R_JAB
FEC
0x1002 B2A4
RMON_R_RESVD_0
FEC
0x1002 B2A8
RMON_R_P64
FEC
0x1002 B2AC
RMON_R_P65TO127
RMON Rx 65 to 127 byte packets
FEC
0x1002 B2B0
RMON_R_P128TO255
RMON Rx 128 to 255 byte packets
FEC
0x1002 B2B4
RMON_R_P256TO511
RMON Rx 256 to 511 byte packets
FEC
0x1002 B2B8
RMON_R_P512TO1023
RMON Rx 512 to 1023 byte packets
FEC
0x1002 B2BC
RMON_R_P1024TO2047
RMON Rx 1024 to 2047 byte packets
FEC
0x1002 B2C0
RMON_R_P_GTE2048
FEC
0x1002 B2C4
RMON_R_OCTETS
FEC
0x1002 B2C8
IEEE_R_DROP
FEC
0x1002 B2CC
IEEE_R_FRAME_OK
FEC
0x1002 B2D0
IEEE_R_CRC
FEC
0x1002 B2D4
IEEE_R_ALIGN
FEC
0x1002 B2D8
IEEE_R_MACERR
FEC
0x1002 B2DC
IEEE_R_FDXFC
FEC
0x1002 B2E0
IEEE_R_OCTETS_OK
Octet count for Frames Rcvd w/o Error
SCC
0x1002 C000
RED_START
SCM Red Memory Start Addr Register
SCC
0x1002 C004
BLACK_START
SCM Black Memory Start Addr Register
SCC
0x1002 C008
LENGTH
Frames Transmitted with Excessive Collisions
Frames Transmitted with SQE Error
Flow Control Pause frames transmitted
Octet count for Frames Transmitted w/o Error
RMON Rx Packets > MAX_FL bytes, good crc
RMON Rx Packets < 64 bytes, bad crc
RMON Rx Packets > MAX_FL bytes, bad crc
Reserved
RMON Rx 64 byte packets
RMON Rx packets w > 2048 bytes
RMON Rx Octets
Count of frames not counted correctly
Frames Received OK
Frames Received with CRC Error
Frames Received with Alignment Error
Receive Fifo Overflow count
Flow Control Pause frames received
SCM Encrypt/Decrypt Data Length Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-39
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
SCC
0x1002 C010
SCM_STAT
SCC
0x1002 C014
SCM_ERROR
SCC
0x1002 C018
INTERRUPT_CONTROL
SCC
0x1002 C01C
CONFIGURATION
SCC
0x1002 C020
INIT_VECTOR 0
Initial Vector 0 Register
SCC
0x1002 C024
INIT_VECTOR1
Initial Vector 1 Register
SCC
0x1002 C400
–
0x1002 C7FF
SCM_RED_MEM
SCC
0x1002 C800
–
0x1002 CBFF
SCM_BLACK_MEM
SCM Black Memory
SCC
0x1002 D000
SMN_STAT
SMN Status Register
SCC
0x1002 D004
SMN_COMMAND
SCC
0x1002 D008
SEQ_START
Sequence Start Value Register
SCC
0x1002 D00C
SEQ_END
Sequence End Value Register
SCC
0x1002 D010
SEQ_CHECK
Sequence Check Register
SCC
0x1002 D014
BIT_COUNT
Bit Count Register
SCC
0x1002 D018
BIT_BANK_INC_SIZE
SCC
0x1002 D01C
BIT_BANK_DEC
SCC
0x1002 D020
CMP_SIZE
Compare Size Register
SCC
0x1002 D024
PLAINTEXT_CHECK
Plaintext Check Register
SCC
0x1002 D028
CIPHER CHECK
SCC
0x1002 D02C
TIMER IV
SCC
0x1002 D030
TIMER CONTROL
SCC
0x1002 D034
DEBUG DETECTOR STATUS
SCC
0x1002 D038
TIMER
Timer Register
ETB REG
0x1003 B000
ETB_ID
ETB Identify Register
ETB REG
0x1003 B004
ETB_RAM_DEPTH
ETB RAM depth Register
ETB REG
0x1003 B008
ETB_RAM_WIDTH
ETB RAM width Register
ETB REG
0x1003 B00C
ETB_STATUS
ETB REG
0x1003 B010
ETB_DATA
ETB REG
0x1003 B014
ETB_READ_POINTER
ETB Read Pointer Register
ETB REG
0x1003 B018
ETB_WRITE_POINTER
ETB Write Pointer Register
SCM Status Register
SCC Error Status Register
SCC Interrupt Control Register
SCC Configuration Register
SCM Red Memory
SMN Command Register
Bit Bank Increment Size Register
Bit Bank Decrement
Ciphertext Check Register
Timer Initial Vector Register
Timer Control Register
Debug Port Detection Status Register
ETB Status Register
ETB Data Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-40
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
ETB REG
0x1003 B01C
ETB_TRIGGER_COUNTER
ETB REG
0x1003 B020
ETB_CONTROL
JAM
0x1003 E000
JAM_ARM9P_GPR0
JAM ARM9P General Purpose Register 0
JAM
0x1003 E010
JAM_ARM9P_GPR4
JAM ARM9P General Purpose Register 4
MAX
0x1003 F000
MPR0
Master Priority Register for Slave Port 0
MAX
0x1003 F100
MPR1
Master Priority Register for Slave Port 1
MAX
0x1003 F200
MPR2
Master Priority Register for Slave Port 2
MAX
0x1003 F004
AMPR0
Alternate Master Priority Register for Slave Port 0
MAX
0x1003 F104
AMPR1
Alternate Master Priority Register for Slave Port 1
MAX
0x1003 F204
AMPR2
Alternate Master Priority Register for Slave Port 2
MAX
0x1003 F010
SGPCR0
General Purpose Control Register for Slave Port 0
MAX
0x1003 F110
SGPCR1
General Purpose Control Register for Slave Port 1
MAX
0x1003 F210
SGPCR2
General Purpose Control Register for Slave Port 2
MAX
0x1003 F014
ASGPCR0
Alternate SGPCR for Slave Port 0
MAX
0x1003 F114
ASGPCR1
Alternate SGPCR for Slave Port 1
MAX
0x1003 F214
ASGPCR2
Alternate SGPCR for Slave Port 2
MAX
0x1003 F800
MGPCR0
General Purpose Control Register for Master Port 0
MAX
0x1003 F900
MGPCR1
General Purpose Control Register for Master Port 1
MAX
0x1003 FA00
MGPCR2
General Purpose Control Register for Master Port 2
MAX
0x1003 FB00
MGPCR3
General Purpose Control Register for Master Port 3
MAX
0x1003 FC00
MGPCR4
General Purpose Control Register for Master Port 4
MAX
0x1003 FD00
MGPCR5
General Purpose Control Register for Master Port 5
AITC
0x1004 0000
INTCNTL
Interrupt Control Register
AITC
0x1004 0004
NIMASK
Normal Interrupt Mask Register
AITC
0x1004 0008
INTENNUM
Interrupt Enable Number Register
AITC
0x1004 000C
INTDISNUM
Interrupt Disable Number Register
AITC
0x1004 0010
INTENABLEH
Interrupt Enable Register High
AITC
0x1004 0014
INTENABLEL
Interrupt Enable Register Low
AITC
0x1004 0018
INTTYPEH
Interrupt Type Register High
AITC
0x1004 001C
INTTYPEL
Interrupt Type Register Low
AITC
0x1004 0020
NIPRIORITY7
Normal Interrupt Priority Level Register 7
AITC
0x1004 0024
NIPRIORITY6
Normal Interrupt Priority Level Register 6
AITC
0x1004 0028
NIPRIORITY5
Normal Interrupt Priority Level Register 5
ETB Trigger Counter Register
ETB Control Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-41
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
AITC
0x1004 002C
NIPRIORITY4
Normal Interrupt Priority Level Register 4
AITC
0x1004 0030
NIPRIORITY3
Normal Interrupt Priority Level Register 3
AITC
0x1004 0034
NIPRIORITY2
Normal Interrupt Priority Level Register 2
AITC
0x1004 0038
NIPRIORITY1
Normal Interrupt Priority Level Register 1
AITC
0x1004 003C
NIPRIORITY0
Normal Interrupt Priority Level Register 0
AITC
0x1004 0040
NIVECSR
Normal Interrupt Vector and Status Register
AITC
0x1004 0044
FIVECSR
Fast Interrupt Vector and Status Register
AITC
0x1004 0048
INTSRCH
Interrupt Source Register High
AITC
0x1004 004C
INTSRCL
Interrupt Source Register Low
AITC
0x1004 0050
INTFRCH
Interrupt Force Register High
AITC
0x1004 0054
INTFRCL
Interrupt Force Register Low
AITC
0x1004 0058
NIPNDH
Normal Interrupt Pending Register High
AITC
0x1004 005C
NIPNDL
Normal Interrupt Pending Register Low
AITC
0x1004 0060
FIPNDH
Fast Interrupt Pending Register High
AITC
0x1004 0064
FIPNDL
Fast Interrupt Pending Register Low
CSI
0x8000 0000
CSICR1
CSI Control Register 1
CSI
0x8000 0004
CSICR2
CSI Control Register 2
CSI
0x8000 0008
CSISR
CSI
0x8000 000C
CSISTATR
CSI
0x8000 0010
CSIRXR
CSI
0x8000 0014
CSIRXCNT
CSI RX Count Register
CSI
0x8000 0018
CSIDEBUG
CSI Debug Register
CSI
0x8000 001C
CSICR3
CSI Control Register 3
CSI Status Register
CSI Statistic FIFO Register
CSI RxFIFO Register
ATA
0x8000_1000
TIME_CONFIG0
ATA timing parameter 0.
ATA
0x8000_1004
TIME_CONFIG1
ATA timing parameter 1.
ATA
0x8000_1008
TIME_CONFIG2
ATA timing parameter 2.
ATA
0x8000_100C
TIME_CONFIG3
ATA timing parameter 3.
ATA
0x8000_1010
TIME_CONFIG4
ATA timing parameter 4.
ATA
0x8000_1014
TIME_CONFIG5
ATA timing parameter 5.
ATA
0x8000_1018
FIFO_DATA_32
32-bit wide data port to/from FIFO
ATA
0x8000_101C
FIFO_DATA_16
16-bit wide data port to/from FIFO
ATA
0x8000_1020
FIFO_FILL
ATA
0x8000_1024
ATA_CONTROL
FIFO Filling in Halfwords
ATA Interface Control Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-42
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
ATA
0x8000_1028
INT_PENDING
Interrupt Pending Register
ATA
0x8000_102c
INT_ENABLE
Interrupt Enable Register
ATA
0x8000_1030
INT_CLEAR
Interrupt Clear Register
ATA
0x8000_1034
FIFO_ALARM
FIFO Alarm Threshold
ATA
0x8000_10A0
DCTR
Drive Data Register
ATA
0x8000_10A4
DDTR
Drive Features Register
ATA
0x8000_10A8
DFTR
Drive Sector Count Register
ATA
0x8000_10AC
DSCR
Drive Sector Number Register
ATA
0x8000_10B0
DSNR
Drive Cylinder Low Register
ATA
0x8000_10B4
DCLR
Drive Cylinder High Register
ATA
0x8000_10B8
DCHR
Drive Device Head Register
ATA
0x8000_10BC
DDHR
Drive Command Register (W)/
Drive Status Register (R)
ATA
0x8000_10D8
DCDR
Drive Alternate Status Register (W)/
Drive Control Register (R)
NFC
0xD800 0E00
NFC_BUFSIZE
Internal SRAM Size
NFC
0xD800 0E02
BLOCK_ADD_LOCK
NFC
0xD800 0E04
RAM_BUFFER_ADDRESS
NFC
0xD800 0E06
NAND_FLASH_ADD
NAND Flash Address
NFC
0xD800 0E08
NAND_FLASH_CMD
NAND Flash Command
NFC
0xD800 0E0A
NFC_CONFIGURATION
NFC Internal Buffer Lock Control
NFC
0xD800 0E0C
ECC_STATUS_RESULT
Controller Status/Result of Flash Operation
NFC
0xD800 0E0E
ECC_RSLT_MAIN_AREA
ECC Error Position of Main Area Data Error
NFC
0xD800 0E10
ECC_RSLT_SPARE_AREA
ECC Error Position of Spare Area Data Error
NFC
0xD800 0E12
NF_WR_PROT
NFC
0xD800 0E14
UNLOCK_START_BLK_ADD
Start Address for Write Protection Unlock
NFC
0xD800 0E16
UNLOCK_END_BLK_ADD
End Address for Write Protection Unlock
NFC
0xD800 0E18
NAND_FLASH_WR_PR_ST
NFC
0xD800 0E1A
NAND_FLASH_CONFIG1
Nand Flash Operation Configuration 1
NFC
0xD800 0E1C
NAND_FLASH_CONFIG2
Nand Flash Operation Configuration 2
ESDCTL
0xD8001000
ESD_ESDCTL0
SDRAM/MDDR 0 Control Register
ESDCTL
0xD8001004
ESD_ESDCFG0
SDRAM/MDDR 0 Timing Config Register
ESDCTL
0xD8001008
ESD_ESDCTL1
SDRAM/MDDR 1 Control Register
NAND Flash Block Address for Lock Check
Buffer Number for Page Data Transfer To/
From Flash Memory
Nand Flash Write Protection
Current Nand Flash Write Protection Status
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-43
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
ESDCTL
0xD800100C
ESD_ESDCFG1
SDRAM/MDDR 1 Timing Config Register
ESDCTL
0xD8001010
ESD_ESDMISC
SDRAM/MDDR Miscellaneous Register
WEIM
0xD800 2000
CS0U
Chip Select 0 Upper Control Register
WEIM
0xD800 2004
CS0L
Chip Select 0 Lower Control Register
WEIM
0xD800 2008
CS0A
Chip Select 0 Addition Control Register
WEIM
0xD800 2010
CS1U
Chip Select 1 Upper Control Register
WEIM
0xD800 2014
CS1L
Chip Select 1 Lower Control Register
WEIM
0xD800 2018
CS1A
Chip Select 1 Addition Control Register
WEIM
0xD800 2020
CS2U
Chip Select 2 Upper Control Register
WEIM
0xD800 2024
CS2L
Chip Select 2 Lower Control Register
WEIM
0xD800 2028
CS2A
Chip Select 2 Addition Control Register
WEIM
0xD800 2030
CS3U
Chip Select 3 Upper Control Register
WEIM
0xD800 2034
CS3L
Chip Select 3 Lower Control Register
WEIM
0xD800 2038
CS3A
Chip Select 3 Addition Control Register
WEIM
0xD800 2040
CS4U
Chip Select 4 Upper Control Register
WEIM
0xD800 2044
CS4L
Chip Select 4 Lower Control Register
WEIM
0xD800 2048
CS4A
Chip Select 4 Addition Control Register
WEIM
0xD800 2050
CS5U
Chip Select 5 Upper Control Register
WEIM
0xD800 2054
CS5L
Chip Select 5 Lower Control Register
WEIM
0xD800 2058
CS5A
Chip Select 5 Addition Control Register
WEIM
0xD800 2060
EIM
M3IF
0xD8003000
M3IF_CTL
M3IF
0xD8003028
M3IF_SCFG0
M3IF Snooping Configuration Register 0
M3IF
0xD800302C
M3IF_SCFG1
M3IF Snooping Configuration Register 1
M3IF
0xD8003030
M3IF_SCFG2
M3IF Snooping Configuration Register 2
M3IF
0xD8003034
M3IF_SSR0
M3IF Snooping Status Register 0
M3IF
0xD8003038
M3IF_SSR1
M3IF Snooping Status Register 1
M3IF
0xD8003040
M3IFMLWE0
M3IF Master Lock WEIM CS0 Register
M3IF
0xD8003044
M3IFMLWE1
M3IF Master Lock WEIM CS1 Register
M3IF
0xD8003048
M3IFMLWE2
M3IF Master Lock WEIM CS2 Register
M3IF
0xD800304C
M3IFMLWE3
M3IF Master Lock WEIM CS3 Register
M3IF
0xD8003050
M3IFMLWE4
M3IF Master Lock WEIM CS4 Register
M3IF
0xD8003054
M3IFMLWE5
M3IF Master Lock WEIM CS5 Register
EIM Configuration Register
M3IF control register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-44
Freescale Semiconductor
System Memory and Register Map
Table 2-8. Register Map (continued)
Module Name
Address
Register Name
Description
PCMCIA
0xD8004000
PCMCIA_PIPR
PCMCIA Input Pins Register
PCMCIA
0xD8004004
PCMCIA_PSCR
PCMCIA Status Changed Register
PCMCIA
0xD8004008
PCMCIA_PER
PCMCIA Enable Register
PCMCIA
0xD800400C
PCMCIA_PBR0
PCMCIA Base Register 0
PCMCIA
0xD8004010
PCMCIA_PBR1
PCMCIA Base Register 1
PCMCIA
0xD8004014
PCMCIA_PBR2
PCMCIA Base Register 2
PCMCIA
0xD8004018
PCMCIA_PBR3
PCMCIA Base Register 3
PCMCIA
0xD800401C
PCMCIA_PBR4
PCMCIA Base Register 4
PCMCIA
0xD8004020
PCMCIA_PBR5
PCMCIA Base Register 5
PCMCIA
0xD8004024
PCMCIA_PBR6
PCMCIA Base Register 6
PCMCIA
0xD8004028
PCMCIA_POR0
PCMCIA Option Register 0
PCMCIA
0xD800402C
PCMCIA_POR1
PCMCIA Option Register 1
PCMCIA
0xD8004030
PCMCIA_POR2
PCMCIA Option Register 2
PCMCIA
0xD8004034
PCMCIA_POR3
PCMCIA Option Register 3
PCMCIA
0xD8004038
PCMCIA_POR4
PCMCIA Option Register 4
PCMCIA
0xD800403C
PCMCIA_POR5
PCMCIA Option Register 5
PCMCIA
0xD8004040
PCMCIA_POR6
PCMCIA Option Register 6
PCMCIA
0xD8004044
PCMCIA_POFR0
PCMCIA Offset Register 0
PCMCIA
0xD8004048
PCMCIA_POFR1
PCMCIA Offset Register 1
PCMCIA
0xD800404C
PCMCIA_POFR2
PCMCIA Offset Register 2
PCMCIA
0xD8004050
PCMCIA_POFR3
PCMCIA Offset Register 3
PCMCIA
0xD8004054
PCMCIA_POFR4
PCMCIA Offset Register 4
PCMCIA
0xD8004058
PCMCIA_POFR5
PCMCIA Offset Register 5
PCMCIA
0xD800405C
PCMCIA_POFR6
PCMCIA Offset Register 6
PCMCIA
0xD8004060
PCMCIA_PGCR
PCMCIA General Control Register
PCMCIA
0xD8004064
PCMCIA_PGSR
PCMCIA General Status Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
2-45
System Memory and Register Map
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
2-46
Freescale Semiconductor
Chapter 3
Clocks, Power Management, and Reset Control
3.1
Introduction
There are two clock controller modules in the i.MX27 Multimedia Applications Processor: The ARM9
Platform Clock Controller and the PLL Clock Controller module (CCM), which produces the clock signals
used and distributed by the ARM9 Platform Clock Controller.
• ARM9 Platform Clock Controller—The primary function of the ARM9 Platform Clock Controller
is to take the clock signals from the PLL Clock Controller and distribute them to various
peripherals on the ARM9 Platform. The clock control module contains the logic to turn clocks on
or off and to determine when the ARM9 Platform’s clock can be turned off. This module also
synchronizes the JTAG interface to the CLK domain.
• PLL Clock Controller—This module generates clock signals used throughout the i.MX27 chip and
external peripherals. The PLL Clock Controller also serves as the interface between the ARM9
Platform and the peripherals on the i.MX27 device.
The ARM9 Platform Clock Controller is not a user-programmable or accessible module, whereas the PLL
Clock Controller is accessible—therefore, only the PLL Clock Controller is described in this chapter.
3.2
Clock Controller Architecture Block Diagram
There are two DPLLs in the PLL Clock Controller—the MCU/System PLL (MPLL) and the Serial
Peripheral PLL (SPLL), which uses digital and mixed analog/digital circuits to provide clock frequencies
for wireless communication and other applications. The MPLL primarily generates the CLK signal to the
ARM9 and HCLK (also called System clock) for the system bus and for most of the on-chip peripherals,
including the LCDC pixel clock and the NAND Flash Controller clock. The SPLL produces the primary
clock to the clock dividers for USB OTG, SSI1, and SSI2.
Both MPLL and SPLL accept either the output of the FPM or the OSC26M as a source from which to
generate the required frequencies for the ARM9 Platform and/or peripherals using a fractional frequency
multiplication method. Detailed information about the calculation of the DPLL settings is shown in
Section 3.2.2, “Output Frequency Calculations.”
To produce the wide range of on-chip clock frequencies required by the i.MX27 processor, the core clock
generator uses a two-stage phase locked loop. The first stage is a Frequency Pre-Multiplier PLL (FPM),
which multiplies the input frequency by a factor of 1024. If the input crystal frequency is 32.768 kHz, the
premultiplier multiplies it by a factor of 1024 to 33.554 MHz (32.768 MHz for a 32.0 KHz crystal). The
output of the FPM is one of the clock sources for the MPLL and SPLL. Power management in the i.MX27
device is accomplished by controlling the clock output of the MPLL and SPLL units.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
3-1
Clocks, Power Management, and Reset Control
The distribution of clocks in the i.MX27 processor is shown in the general block diagram, Figure 3-1.
There are two external clock sources to the PLL Clock Controller:
• 32 kHz external crystal
• 26 MHz external source/crystal
Settings in the Clock Source Control Register (CSCR) are used to independently configure the external
clock sources applied to the MPLL and SPLL.
OSC 32K
CLK 32K
FPM
0
MPLL CLK
MPLL
1
FPM EN
BYPASS[1]
MPLLCLK SEL
BYPASS[1]
OSC26M DIS
BYPASS[0]
DIV 1P5
OSC 26M
1
0
UPLLCLK SEL
BYPASS[1]
0
EXT 60M
1
BYPASS[0]
OSC26M DIV1p5
0
UPLL
SPLL
0
SPLLCLK
CLK
UPLL
1
1
BYPASS[2]
Figure 3-1. i.MX27 Clock Distribution Block Diagram (1 of 2)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
3-2
Freescale Semiconductor
Clocks, Power Management, and Reset Control
B Y PA SS [2]
A RM SRC
1
1
D IV 2
A R M D IV :
E XT 26 6M
A RM C LK
A R M D IV
0
0
2X Cloc k Por t
MMPLL
CU DPLL
A HB D IV :
D IV 3
0
A H B CL K
A H B DIV
1
IP G CL K
IP G D IV
E XT 26 6M
N F C D IV :
B Y PA S S[2]
NF C D IV
NFC
PER 1 D IV :
U A R T/G P T/P W M
P E R 1D IV
P E R 2 D IV :
S D HC / C S P I
P E R 2D IV
P E R 3 D IV :
LC D C
P E R 3D IV
PER 4 D IV :
P E R 4D IV
CSI
SSI1 D IV :
1
S S I1D IV
Ref Clo c k
USSPLL
B DP L L
S S I1
0
S S I 2 D IV :
1
S S I2
S S I2D IV
0
M S HC D IV :
1
M S HC D IV
M S HC
0
H2 6 4 D IV :
1
H 26 4D IV
H 26 4
0
U S B D IV :
U S B D IV
US B
Figure 3-2. i.MX27 Clock Distribution Block Diagram (2 of 2)
Table 3-1. PLL Clock Controller Signal Descriptions
Signal Names
Description
CLK
Fast clock used only by ARM9 Platform for internal operations, such as executing instructions from the
cache. Can be gated during Doze and Sleep mode when all the criteria are met to enter a low power.
HCLK
System clock. Appears as the BCLK input to the CPU and the HCLK to the system. This is a continuous
clock (when the system is not in Sleep mode). It can be gated during Doze and Sleep mode when all
the criteria are met to enter a low power.
HCLKEN
Used to signify the rising edge of CLK that corresponds to the rising edge of HCLK. It is used by the
ARM9 Platform only.
CLK60M
60 MHz clock for the USB OTG module
SSI1CLK
Divided clock output for the SSI1 module
SSI2CLK
Divided clock output for the SSI2 module
NFCCLK
Divided clock output for the NAND Flash Controller module
H264CCLK
Divided clock output for the H264 module
MSHCCLK
Divided clock output for the MSHC module
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
3-3
Clocks, Power Management, and Reset Control
Table 3-1. PLL Clock Controller Signal Descriptions (continued)
Signal Names
Description
PERCLK1
Divided clock output for peripheral set 1 (UART, Timer, PWM)
PERCLK2
Divided clock output for peripheral set 2 (SDHC, CSPI)
PERCLK3
Divided clock output for the LCDC
PERCLK4
Divided clock output for the CSI
CLKO
Selected internal clock output to the CLKO pin
A9P_CLK_OFF Control signal from the ARM9 Platform Clock Controller
3.2.1
High Frequency Clock Source and Distribution
Two DPLLs—MPLL and SPLL—on the i.MX27 device are used to generate two separate clock
frequencies from either the Frequency Pre-Multiplier (FPM) or an external high frequency source
(CLK26M). The clock source for each DPLL is individually selected using bits in the Clock Source
Control Register (CSCR).
The MCU/System PLL (MPLL) is configured by the MPCTL registers (MPCTL0, MPCTL1) to produce
system clock signals that are divided down to output the FCLK (for example 266 MHz) and the HCLK
(for example, 133 MHz) clock signals. MPLL serves as the clock source for the PERCLK4, PERDIV3,
PERDIV2, and PERDIV1. FCLK serves as the clock source for the NFCDIV divider. These dividers
produce the clock signals for the following:
• NAND Flash Controller (NFC)
• Peripheral set 1 (PERCLK1): UART, Timer, and PWM
• Peripheral set 2 (PERCLK2): SDHC and CSPI
• LCDC Pixel Clock (PERCLK3)
• CSI (PERCLK4)
Serial Peripheral PLL (SPLL) is configured by SPCTL registers (SPCTL0, SPCTL1) and produces input
signals for the USBDIV, SSI1DIV, SSI2DIV, H264DIV, and MSHCDIV dividers, which generate clock
signals for serial peripherals that require special clock frequencies:
• CLK60M—for the USB OTG
• SSI1CLK—Clock signal for SSI1
• SSI2CLK—Clock signal for SSI2
• H264CCLK—Clock signal for H264
• MSHCCLK—Clock signal for MSHC
The clock source for the SSI1DIV and SSI2DIV dividers can be the MPLL or SPLL. Source selection is
controlled by the respective bits in the Clock Source Control register (CSCR).
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Freescale Semiconductor
Clocks, Power Management, and Reset Control
3.2.2
Output Frequency Calculations
Both DPLLs produce a high frequency clock that exhibits a low frequency jitter and a low phase jitter. The
DPLL output clock frequency (fdpll) is determined by the Equation 3-1:
fdpll = 2fref • MFI + MFN / (MFD+1)
PD+1
Eqn. 3-1
where:
• fref is the reference frequency (1024 × 32.768 kHz, 1024 × 32.0 kHz, or 26 MHz).
• MFI is an integer part of a multiplication factor (MF).
• MFN is the numerator and MFD is the denominator of the MF.
• PD is the predivider factor.
NOTE
In bootstrap mode, the PLL registers assume a source clock of 32.768 KHz.
If using bootstrap mode, use a 32.768 KHz crystal.
3.3
Power Management
The PLL Clock Controller module is designed with clock control at various stages of clock supply to
achieve optimum power savings. The operation of the PLL and clock controller at different stages of power
management is described in the following sections.
3.3.1
PLL Operation at Power-Up
The crystal oscillator begins oscillating within several hundred milliseconds of initial power-up. While
system reset remains asserted the PLL begins the lockup sequence and locks 1 ms after the crystal
oscillator becomes stable. Both DPLLs are enabled on power-up. The system reset is held asserted by the
PLL Clock Controller for 300 ms + 14 cycles of the 32 kHz, as shown in Figure 3-17.
3.3.2
PLL Operation at Wake-Up
When the device is awakened from Sleep mode by a wake-up event, the DPLL locks within 350 μs. The
crystal oscillator is always on after initial power-up, so crystal startup time is not a factor. The PLL output
clock starts operating as soon as it achieves lock.
3.3.3
i.MX27 Processor Low-Power Modes
The i.MX27 processor provides two power saving modes—Doze mode and Sleep mode:
• In Doze mode, the ARM9 executes a wait for interrupt (WFI) instruction. System clocks are still
active.
• In Sleep mode, the ARM9 executes a wait for interrupt (WFI) instruction. The output of the MPLL
and SPLL are shut down and only the 32 kHz clock is running.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
3-5
Clocks, Power Management, and Reset Control
These modes are controlled by the clock control logic and a sequence of CPU instructions. Most of the
peripheral modules can enable or disable the incoming clock signal through clock gating circuitry from the
peripheral bus. Each module has a module enable bit which, when disabled, disables the operational clock
to the module.
The i.MX27 PLL Clock Controller provides the Low-Power mode information to the Watchdog (WDOG)
module.
3.3.3.1
Doze Mode
Doze mode is defined as when the ARM9 executes a wait for an interrupt instruction, after which the
buffered clock supply to the MCU is turned off.
The sequence of operation to set the system to Doze mode is as follows:
1. Enable desired interrupts for wake-up from Doze mode.
2. Disable watchdog timer interrupt.
3. Execute wait-for-interrupt instruction.
The ARM9 executes a wait for interrupt instruction if all required conditions are met (no irq, fiq, or debug
requests pending), the ARM9 Platform generates an A9P_CLK_OFF signal to the PLL Clock Controller
module. The CLK signal to the MCU is immediately turned off when the A9P_CLK_OFF signal goes
active. CLK_ALWAYS and system bus (HCLK) remain running. HCLK is required by the Cross Bar
Switch within the ARM9 Platform for continuous operation of peripheral modules. When an unmasked
interrupt event occurs, the CLK signal to the ARM9 is re-enabled.
3.3.3.2
Sleep Mode
Sleep mode is defined as when all the DPLLs clock outputs are disabled. A sequence of operations and
criteria must be satisfied before the system turns off the MPLL and SPLL. The Sleep mode sequence is
initiated when the MPEN bit in the CSCR register is cleared disabling the MPLL. This action also
automatically turns off the SPLL.
The sequence to put the system into Sleep mode is as follows:
1. Disable AHB peripherals from bus accesses.
2. Enable desired interrupts to be used for system wake-up.
3. Disable watchdog timer interrupt.
4. Set the required value to the SD_CNT (CSCR register) for shutdown countdown.
5. Disable the MPLL by clearing the MPEN bit (CSCR register).
6. Execute wait-for-interrupt instruction.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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Clocks, Power Management, and Reset Control
The example of programming setup to enter Sleep mode is as follows:
Code Example 3-1. Programming Setup for Entering Sleep Mode
MRS
AND
MSR
LDR
LDRH
ORR
STRH
LDR
LDR
ORR
STR
BIC
STR
LDR
MCR
r0, CPSR
; Enable interrupts
r1, r0, #(ENABLE_IRQ+ENABLE_FIQ+MODE_BITS)
CPSR_c, r1
r3, =WDG_BASEADDR
; Disable WDG Timer
r4, [r3, #0x0]
r4, r4, #0x00000001
r4, [r3, #0x0]
r1, =CRM_BASEADDR
; Set SDCNT to ‘01’
r2, [r1, #0x0]
r2, r2, #0x0100_0000
r2, [r1, #0x0]
r2, r2, #0x00000001
; Disable MPEN
r2, [r1, #0x0]
r1, 0x00000000
p15, 0, r1, c7, c0, 4
; WFI
The MPLL and SPLL are turned off when the countdown value in SD_CNT is satisfied. For the MPLL,
there are a number of conditions that must be satisfied before the Clock Controller module turns off the
DPLL. The conditions to be satisfied before the PLL Clock Controller actually turns off the MPLL are as
follows:
1. Clock Controller module has successfully mastered the system bus.
2. The A9P_CLK_OFF signal from the ARM9 Platform is active.
3. SDRAM controller has successfully placed the external SDRAM into Self-Refresh mode.
4. After the above conditions are satisfied, the countdown based on the value in the SD_CNT field
will be initiated.
5. SD_CNT countdown completes.
When the conditions listed above are satisfied the MPLL and the SPLL will be turned off. The Frequency
Premultiplier (FPM) is also disabled in the Sleep mode. The FPM_EN bit (CSCR register) must not be
cleared if the FPM is providing the clock source to the DPLL.
When an unmasked interrupt event occurs, the FPM and then the MPLL are re-enabled and the MPLL
enable bit (MPEN) automatically restored to its enable setting. The SPLL is restored to its original state
based on the setting of the SPEN bit before Sleep mode. If the SPLL was not enabled before entering Sleep
mode the SPLL will not be enabled.
The total start-up time from Sleep mode is the sum of the FPM lock time and the DPLL lock time.
In Sleep mode, the i.MX27 device retains all RAM data and register configuration values. Data to output
terminals is also maintained and thus will continue to sink/source static current.
NOTE
System software must ensure that if there are any clocks being sourced by
the i.MX27 processor to external peripherals (for example, SSI MCLK),
then the corresponding PLL must not be turned off. In such cases, the
i.MX27 processor must remain in Doze mode.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
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Clocks, Power Management, and Reset Control
3.3.4
SDRAM Power Modes
When the SDRAM controller (SDRAMC) is enabled, the external SDRAM operates in
Distributed-Refresh mode or in Self-Refresh mode (as shown in Table 3-2). The SDRAM wake-up latency
is approximately 20 system clock cycles (HCLK). The SDRAMC can wake up from Self-Refresh mode
when it is in a SDRAM cycle.
In Doze and Run mode, the Power Down timers within the SDRAMC can be enabled to cause the SDRAM
to enter Power Down mode on detecting no activity. The SDRAMC still controls the refresh and it takes
the SDRAM out of the Power Down mode to perform refresh when needed and then put it back into the
Power Down mode. In Power Down mode the clock to the SDRAM is gated off and the CKE pin goes low.
In addition since the SDRAM will be in self refresh just when the system get into Sleep mode, no bus cycle
can access the SDRAM to cause it to exit the Self-Refresh mode. Exit from Self-Refresh mode will happen
when the chip will exit the Sleep mode and re-enable the MPEN.
Table 3-2. SDRAM Operation During Power Modes
SDRAM
Run
Doze
Stop
SDRAM
Distributed-refresh, Note 1
Distributed-refresh, Note 1
Self-refresh
3.3.5
Power Management in the PLL Clock Controller
The i.MX27 device has a very efficient clock control scheme that enables clocking control of the modules
and devices at various stages. Power management in the i.MX27 device is achieved by controlling the duty
cycles of the clock system efficiently. The clocking control scheme is shown in Table 3-3.
Table 3-3. Power Management in the Clock Controller
Device/Signal
Shut-Down Conditions
Wake-Up Conditions
MPLL
When 0 is written to the MPEN bit and the PLL shut-down count times
out (for details see the SD_CNT settings in Table 3-6).
When IRQ or FIQ is asserted
SPLL
When 0 is written to the SPEN bit.
When the SPEN bit is set to 1
FPM
When 0 is written to the FPMEN bit.
When the FPMEN bit is set to 1
CLK32
Continuously running.
Continuously running
Most modules in the i.MX27 processor have a module enable bit assigned which must be enabled before
the module is active. Enabling the module enables the clock source for the module to be provided for its
main operations. The clock input to the dividers from the SPLL is also controlled separately in the same
manner.
3.3.6
Power Management Using Frequency Control
The i.MX27 processor has DPTC, but does not support the DVFS feature. The i.MX27 device provides a
way for software to save power under different operating conditions.
• Software determines whether to change the operation frequency or not.
• Software uses DPTC to determine whether to reduce or increase the power supply.
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Clocks, Power Management, and Reset Control
•
•
After the power supply has been changed, software can update MPLL configuration.
It restarts the MPLL and operates with new frequency.
3.4
Memory Map and Register Definition
The PLL Clock Controller module includes six user-accessible 32-bit registers. Table 3-4 provides the
memory map for the PLL Clock Controller.
Table 3-4. PLL Clock Controller Memory Map
Address
Register
Access
Reset Value
Section/Page
General Registers
0x1002_7000 (CSCR)
Clock Source Control Register
R/W
0x33F0_1307
3.4.2/3-10
0x1002_7004 (MPCTL0)
MPLL Control Register 0
R/W
0x0021_1803
3.4.3/3-13
0x1002_7008 (MPCTL1)
MPLL Control Register 1
R/W
0x0000_8000
3.4.4/3-15
0x1002_700C (SPCTL0)
SPLL Control Register 0
R/W
0x8403_1C53
3.4.6/3-17
0x1002_7010 (SPCTL1)
SPLL Control Register 1
R/W
0x0000_8000
3.4.7/3-19
0x1002_7014 (OSC26MCTL)
Oscillator 26M Register
R/W
0x0000_3F00
3.4.8/3-20
0x1002_7018 (PCDR0)
Peripheral Clock Divider Register 0
R/W
0x2008_3403
3.4.9/3-21
0x1002_701C (PCDR1)
Peripheral Clock Divider Register 1
R/W
0x1204_1303
3.4.10/3-23
0x1002_7020 (PCCR0)
Peripheral Clock Control Register 0
R/W
0x0401_01C0
3.4.11/3-25
0x1002_7024 (PCCR1)
Peripheral Clock Control Register 1
R/W
0xFF4B_6848
3.4.12/3-28
0x1002_7028 (CCSR)
Clock Control Status Register
R/W
0x0000_0300
3.4.13/3-31
0x1002_7034 (WKGDCTL)
Wakeup Guard Mode Control Register
R/W
0x0000_0000
3.4.14/3-33
3.4.1
Register Summary
The conventions in Figure 3-3 and Table 3-5 serve as a key for the register summary and individual register
diagrams.
Always
reads 1
1
Always
reads 0
0
R/W BIT Read- BIT WriteWrite 1 BIT Self-clear 0
bit
only bit
only bit BIT to clear w1c
bit BIT
N/A
Figure 3-3. Key to Register Fields
Table 3-5 provides a key for register figures and tables and the register summary.
Table 3-5. Register Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writable.
FIELDNAME
Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
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Clocks, Power Management, and Reset Control
Table 3-5. Register Conventions (continued)
Convention
Description
R
Read only. Writing this bit has no effect.
W
Write only.
R/W
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by a hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
Self-clearing bit Writing a one has some effect on the module, but it always reads as zero. (Previously designated slfclr)
Reset Values
0
Resets to zero.
1
Resets to one.
—
Undefined at reset.
u
Unaffected by reset.
[signal_name]
3.4.2
Reset value is determined by polarity of indicated signal.
Clock Source Control Register (CSCR)
The Clock Source Control Register controls the various clock sources to the internal modules of the
i.MX27 processor. Figure 3-4 shows the register and Table 3-6 provides the field descriptions.
0x1002_7000 (CSCR)
31
R
30
27
26
0
0
USB_DIV
25
24
SD_CNT
23
22
21
20
19
18
17
16
SPLL MPLL
SSi2_ SSI1_ H264 MSHC
SP_S MCU
_RES _RES
SEL
SEL _SEL _SEL
EL _SEL
TART TART
0
0
1
1
0
0
1
1
1
1
1
1
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
ARM
W SRC
Reset
28
0
W
Reset
29
Access: User R/W
0
0
ARMDIV
0
0
1
AHBDIV
0
0
1
1
OSC2 OSC2
FPM_ SPE MPE
6M_DI 6M_D
EN
N
N
IS
V1P5
0
0
1
1
1
Figure 3-4. Clock Source Control Register (CSCR)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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Freescale Semiconductor
Clocks, Power Management, and Reset Control
Table 3-6. Clock Source Control Register Field Descriptions
Field
31
UPDATE_DIS
30–28
USB_DIV
27–26
25–24
SD_CNT
Description
Disable source selection and divider update until next MPLL lock. This bit is cleared automatically.
When reprogramming the PLL and corresponding CSCR settings, this bit must first be set before the
CSCR is updated and DPLL is reprogrammed to ensure that erratic clock behavior does not occur.
USB Clock Divider. Contains the 3-bit integer divider value for generation of CLK60M.
000 SPLL_CLK divided by 1
001 SPLL_CLK divided by 2
...
111 SPLL_CLK divided by 8
Reserved. These bits are reserved and should read 0.
Shut-Down Control. Contains the value that determines duration of DPLL clock output before it goes off
after a 0 is written to the MPEN or SPEN bit.
Note: Power controller requests the bus before SPLL shutdown. Any unmasked interrupt event will
enable MPLL.
00 DPLL shuts down after the next rising edge of CLK32 is detected and the current bus cycle is
completed. A minimum of 16 HCLK cycles is occurs after writing 0 to MPEN bit.
01 DPLL shuts down after second rising edge of CLK32 is detected and the current bus cycle is
completed.
10 DPLL shuts down after third rising edge of CLK32 is detected and the current bus cycle is
completed.
11 DPLL shuts down after forth rising edge of CLK32 is detected and the current bus cycle is
completed.
23
SSI2_SEL
SSI2 Baud Source Select. Selects the clock source to SSI2 fractional divider (SSI2_DIV).
0 Source clock to SSI2 fractional divider from SPLL
1 Source clock to SSI2 fractional divider from MPLL
22
SSI1_SEL
SSI1 Baud Source Select. Selects the clock source to SSI1 fractional divider (SSI1_DIV).
0 Source clock to SSI1 fractional divider from SPLL
1 Source clock to SSI1 fractional divider from MPLL
21
H264_SEL
H264 CCLK Source Select. Selects the clock source to H264 divider (H264_DIV).
0 Source clock to H264 divider is from SPLL
1 Source clock to H264 divider is from MPLL
20
MSHC_SEL
MSHC CCLK Source Select. Selects the clock source to MSHC divider (MSHC_DIV).
0 Source clock to MSHC divider is from SPLL
1 Source clock to MSHC divider is from MPLL
19
SPLL_RESTART
SPLL Restart. Restarts SPLL at the new assigned frequency. SPLL_RESTART self-clears after 1 (min)
or 2 (max) cycles of CLK32.
0 No Effect
1 Restarts SPLL at new frequency
18
MPLL Restart. Restarts MPLL at the new assigned frequency. MPLL_RESTART self-clears after 1 (min)
MPLL_RESTART or 2 (max) cycles of CLK32.
0 No Effect
1 Restarts MPLL at new frequency
17
SP_SEL
SPLL Select. Selects clock source of SPLL input. When set, the external high frequency clock input is
selected.
0 Clock source is the internal premultiplier. Register map shows this bit as reserved also conflicts with
1 Clock source is the external high frequency clock
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
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Clocks, Power Management, and Reset Control
Table 3-6. Clock Source Control Register Field Descriptions (continued)
Field
Description
16
MCU_SEL
MPLL Select. Selects clock source of MPLL input. When set, the external high frequency clock input is
selected.
0 Clock source is the internal premultiplier.
1 Clock source is the external high frequency clock.
15
ARM SRC
ARMSRC. It selects the ARM clock source.
0 MPLL CLK * 2 / 3
1 MPLL CLK
13–12
ARM_DIV
ARM_DIV. Divider value for arm clk.
00 divide by 1
01 divide by 2
10 divide by 3
11 divide by 4
11–10
Reserved
AHB_DIV. Divider value for AHB clk.
00 divide by 1
01 divide by 2
10 divide by 3
11 divide by 4
9-8
AHB_DIV
7–5
Reserved
4
Oscillator 26M Divide Enable. Divides osc26m output by 1 or 1.5.
OSC26M_DIV1P5 0 osc26m output divide by 1 (default)
1 osc26m output divide by 1.5
3
OSC26M_DIS
Oscillator Disable. Disables the internal (on-chip) 26 MHz oscillator circuit when this bit is set to 1.
0 Enable the internal 26 MHz oscillator circuit
1 Disable the internal 26 MHz oscillator circuit
2
FPM_EN
Frequency Premultiplier Enable. Enables/disables FPM when set/cleared. This bit is set automatically
on system reset. When the software writes a 0 to this bit, FPM is shut down immediately. This bit must
remain at 1 prior and during Sleep mode if FPM is providing the source to the DPLL.
0 Disable the frequency premultiplier circuit
1 Enable the frequency premultiplier circuit
1
SPEN
Serial Peripheral PLL Enable. Enables/disables the SPLL. When software writes 0 to SPEN, SPLL shuts
down after timeout determined by SD_CNT. SPEN sets automatically when SPLLEN asserts, and on
system reset.
0 Serial Peripheral PLL disabled
1 Serial Peripheral PLL enabled
0
MPEN
MPLL Enable. Enables/disables the MPLL. When software writes 0 to MPEN, MPLL shuts down after
SDCNT timeout. MPEN sets automatically when MPLLEN asserts, and on system reset.
0 MCU and Serial PLL disabled
1 MCU and Serial PLL enabled
NOTE
When PRESC and BCLKDIV are modified at the same time, it must be
performed in two programming steps: The first step is to change BCLKDIV,
and then to change PRESC.
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Clocks, Power Management, and Reset Control
3.4.3
MPLL Control Register 0 (MPCTL0)
The MCU and System PLL Control Register 0 (MPCTL0) is a 32-bit register that controls the operation
of the MPLL. The MPCTL0 control bits are described in the following sections.
Figure 3-5 shows the register and Table 3-7 provides the field descriptions.
The following is the recommended procedure for changing the MPLL settings:
1. Program the desired values of PD, MFD, MFI, and MFN into the MPCTL0.
2. Set the MPLL_RESTART bit in the CSCR (it will self-clear).
3. New MPLL settings will take effect.
4. The new PLL clock output is valid upon the assertion of the DPLL lock flag.
0x1002_7004 (MPCTL0)
31
R
30
29
Access: User R/W
28
27
26
25
24
23
22
21
20
19
18
17
16
0
CPLM
PD
MFD
W
Reset
R
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
MFI
MFN
W
Reset
0
0
0
1
1
0
0
0
0
0
0
Figure 3-5. MPLL Control Register 0 (MPCTL0)
Table 3-7. MPLL Register 0 Field Descriptions
Field
Description
31
CPLM
Phase Lock Mode. DPLL operates in the Frequency Only Lock mode (FOL) when CPLM bit is cleared, and in
Frequency and Phase Lock mode (FPL) when the bit is set. FPL mode can be used for both integer and fractional
multiplication factor, but phase skew elimination is accomplished only for integer MF.
0 FOL
1 FPL
30
29–26
PD
Reserved. This bit is reserved and should read 0.
Predivider Factor. Defines the predivider factor (PD) applied to MPLL input frequency. PD is an integer between 0
and 15 (inclusive). PD is chosen to ensure that the resulting output frequency remains within the specified range.
When a new value is written into PD, MPLL loses its lock; and after a time delay, MPLL re-locks. MPLL output is
determined by Equation 3-1.
0000 0
0001 1
…
1111 15
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
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Clocks, Power Management, and Reset Control
Table 3-7. MPLL Register 0 Field Descriptions (continued)
Field
Description
25–16
MFD
Multiplication Factor (Denominator Part). Defines the denominator part of BRM value for MF. When a new value is
written into the MFD bits, MPLL loses its lock; and after a time delay, MPLL re-locks.
000 Reserved
001 1
…
3FF 1023
15–14
Reserved. These bits are reserved and should read 0.
13–10
MFI
Multiplication Factor (Integer). Defines the integer part of BRM value for MF. MFI is encoded so that MFI < 5 results
in MFI = 5. When a new value is written into the MFI bits, PLL loses its lock: and after a time delay, PLL re-locks.
VCO oscillates at a frequency determined by Equation 3-1. Where PD is the division factor of the predivider, MFI
is the integer part of total MF, MFN is the numerator of the fractional part of MF, and MFD is its denominator part.
MF is chosen to ensure that the resulting VCO output frequency remains within the specified range.
0000–01015
0110 6
...
1111 15
9–0
MFN
Multiplication Factor (Numerator). Defines the numerator of BRM value for MF. The MFN is the only part in the
DPLL Configuration that can be changed after the DPLL was locked without resetting the DPLL (on the fly).The bit
9 is the sign bit. When MFN is zero, the circuitry for fractional division is disabled to save power.
000 0
001 1
...
1FE 510
1FF reserved
...
3FE –510
3FF Reservoir
The recommended settings for MPLL and SPLL that produce the least amount of signal jitter are shown
in Table 3-8.
Table 3-8. Recommend Settings for Frequency Stability
Ref Frequency
Target
Frequency
MFI
MFN
MFD
PD
MPCTL0
Setting
Actual Calculated
Frequency
32.768 kHz
399 MHz
5
469
495
0
0x01EF15D5
399.000
32.000 kHz
399 MHz
6
3
21
0
0x00211803
398.998
26 MHz
399 MHz
7
35
51
0
0x00331C23
399
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
3-14
Freescale Semiconductor
Clocks, Power Management, and Reset Control
3.4.4
MCU and System PLL Control Register 1 (MPCTL1)
The MCU and System PLL Control Register 1 (MPCTL1) is a 32-bit register that directs the operation of
the on-chip MCU PLL. Figure 3-6 shows the register and Table 3-9 provides the field descriptions.
0x1002_7008 (MPCTL1)
R
Access: User R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
LF
BRMO
W
Reset
1
0
0
0
0
0
0
0
0
0
0
Figure 3-6. MCU and System PLL Control Register 1 (MPCTL1)
Table 3-9. MCU and System PLL Control Register 1 Field Descriptions
Field
31–16
15
LF
14–7
6
BRMO
5–0
Description
Reserved. These bits are reserved and should read 0.
Lock Flag. Indicates whether MPLL is locked or not. When set, MPLL clock output is valid. When cleared, MPLL
clock output remains at logic high.
0 MPLL is not locked.
1 MPLL is locked.
Reserved. These bits are reserved and should read 0.
BRM Order. Controls the BRM order which affects jitter performance of MPLL. The first order BRM is used if a MF
fractional part is more than 1/10 and less than 9/10. In other cases, second order BRM is used. BRMO bit is cleared
by a hardware reset. A delay of reference cycles is required between two write accesses to BRMO.
0 BRM contains first order.
1 BRM contains second order.
Reserved. These bits are reserved and should read 0.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
3-15
Clocks, Power Management, and Reset Control
3.4.5
Programming the Serial Peripheral PLL (SPLL)
One of the clock frequencies that the SPLL generates is for the USB OTG module (CLK60M). Its
frequency is set to 60 MHz using the SPLL control registers assuming a default input clock frequency
32.768 MHz. This input clock frequency assumes a 32 kHz crystal input. The predivider/multiplier output
depends on the input clock frequency. Recommended settings are provided for the Serial Peripheral PLL
as shown in Table 3-10.
Table 3-10. Serial PLL Multiplier Factor
Ref Frequency
Target
Frequency
MFI
MFN
MFD
PD
SPCTL0 Setting
Actual Calculated
Frequency
32.768 kHz
300 MHz
8
111
117
1
0x0475206F
299.99937 MHz
32.768 kHz
240 MHz
7
9
58
1
0x043A1C09
239.99950 MHz
32 kHz
300 MHz
9
25
160
1
0x04A02419
300.00020 MHz
32 kHz
240 MHz
7
83
255
1
0x04FF1C53
240 MHz
26 MHz
300 MHz
11
7
12
1
0x040C2C07
300 MHz
26 MHz
240 MHz
9
3
12
1
0x040C2403
240 MHz
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
3-16
Freescale Semiconductor
Clocks, Power Management, and Reset Control
3.4.6
SPLL Control Register 0 (SPCTL0)
The Serial Peripheral PLL Control Register 0 (SPCTL0) is a 32-bit register that controls the operation of
the SPLL. The SPCTL0 control bits are described in the following sections.
Figure 3-7 shows the register and Table 3-11 provides the field descriptions.
The following is a procedure for changing the Serial Peripheral PLL settings:
1. Program the desired values of PD, MFD, MFI, and MFN into the SPCTL0.
2. Set the SPLL_RESTART bit in the CSCR (it will self-clear).
3. New PLL settings will take effect.
4. The new PLL clock output is valid upon the assertion of the DPLL lock flag.
0x1002_700C (SPCTL0)
31
R
30
29
Access: User R/W
28
27
26
25
24
23
22
21
20
19
18
17
16
0
CPLM
PD
MFD
W
Reset
R
1
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
1
1
MFI
MFN
W
Reset
0
0
0
1
1
1
0
0
0
1
0
Figure 3-7. SPLL Control Register 0 (SPCTL0)
Table 3-11. SPLL Control Register 0 Field Descriptions
Field
Description
31
CPLM
Phase Lock Mode. DPLL operates in the Frequency Only Lock mode (FOL) when CPLM bit is cleared, and in
Frequency and Phase Lock mode (FPL) when the bit is set. FPL mode can be used for both integer and fractional
multiplication factor, but phase skew elimination is accomplished only for integer MF.
0 FOL
1 FPL
30
29–26
PD
Reserved. These bit is reserved and should read 0.
Predivider Factor. Defines the predivider factor (PD) that is applied to the PLL input frequency. PD is an integer
between 0 and 15 (inclusive). SPLL oscillates at a frequency determined by Equation 3-1. PD is chosen to ensure
that the resulting VCO output frequency remains within the specified range. When a new value is written into the
PD bits, SPLL loses its lock: and after a time delay, SPLL re-locks.
0000 0
0001 1
…
111115
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
3-17
Clocks, Power Management, and Reset Control
Table 3-11. SPLL Control Register 0 Field Descriptions (continued)
Field
Description
25–16
MFD
Multiplication Factor (Denominator Part). Defines the denominator part of BRM value for the MF. When a new value
is written into the MFD9 to MFD0 bits, PLL loses its lock: and after a time delay, PLL re-locks.
000 Reserved
001 1
…
3FF 1023
15–14
Reserved. These bits are reserved and should read 0.
13–10
MFI
Multiplication Factor (Integer Part). Defines the integer part of BRM value for MF. MFI is decoded so that MFI < 5
results in MFI = 5. SPLL oscillates at a frequency determined by Equation 3-1. Where PD is the division factor of
the predivider, MFI is the integer part of total MF, MFN is the numerator of fractional part of MF, and MFD is the
denominator part of MF. MF is chosen to ensure that the resulting VCO output frequency remains within the
specified range. When a new value is written into the MFI bits, SPLL loses its lock; and after a time delay, SPLL
re-locks.
0000–01015
0110 6
...
1111 15
9–0
MFN
Multiplication Factor (Numerator). Defines the numerator of BRM value for MF. The MFN is the only part in the
DPLL Configuration that can be changed after the DPLL was locked without resetting the DPLL (on the fly).The bit
9 is the sign bit. When MFN is zero, the circuitry for fractional division is disabled to save power.
0x0000
0x0011
...
0x1FE 510
0x1FF Reserved
...
0x3FE-510
0x3FF Reserved
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
3-18
Freescale Semiconductor
Clocks, Power Management, and Reset Control
3.4.7
SPLL Control Register 1 (SPCTL1)
The Serial PLL Control Register 1 (SPCTL1) is a 32-bit read/write register that directs the operation of the
SPLL. The SPCTL1 control bits are described in this section. Figure 3-8 shows the register and Table 3-12
provides the field descriptions.
0x1002_7010 (SPCTL1)
R
Access: User R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
LF
BRMO
W
Reset
1
0
0
0
0
0
0
0
0
0
Figure 3-8. SPLL Control Register 1 (SPCTL1)
Table 3-12. Serial Peripheral PLL Control Register 1 Field Descriptions
Field
31–16
15
LF
14–7
6
BRMO
5–0
Description
Reserved. These bits are reserved and should read 0.
Lock Flag. Indicates whether SPLL is locked or not. When set, SPLL clock output is valid. When cleared, SPLL
clock output remains at logic high.
0 SPLL is not locked.
1 SPLL is locked.
Reserved. These bits are reserved and should read 0.
BRM Order. Controls the BRM order which affect SPLL jitter performance. The first order BRM is used if a MF
fractional part is more than 1/10 and less than 9/10. In other cases, second order BRM is used. BRMO bit is cleared
by a hardware reset. A delay of reference cycles is required between two write accesses to BRMO.
0 BRM contains first order.
1 BRM contains second order.
Reserved. These bits are reserved and should read 0.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
3-19
Clocks, Power Management, and Reset Control
3.4.8
Oscillator 26M Register
This register is use to program the 26 MHz oscillator test modes as well as the gain control. Trimming of
the oscillator is necessary only on initial power up; the trim may be stored in Flash for future reference.
Figure 3-9 shows the register and Table 3-13 provides the field descriptions.
0x1002_7014 (OSC26MCTL)
R
Access: User R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
17
16
OSC26M_
PEAK
AGC
W
Reset
0
0
1
1
1
1
1
1
Figure 3-9. Oscillator 26M Control Register (OSC26MCTL)
Table 3-13. Oscillator 26M Control Register Field Descriptions
Field
31–18
Description
Reserved. These bits are reserved and should read 0.
17–16
OSC26M_PEAK. These bits indicates the current amplitude status from the oscillator.
OSC26M_PEAK 00 Amplitude in desired operating range
01 Amplitude too low; trim higher
10 Amplitude too high; trim lower
11 Invalid state
13–8
AGC
Automatic Gain Control. These bits sets the magnitude of crystal oscillations based on OSC26M_PEAK
status. Optimum settings for these bits is determined using the algorithm in Section 3.4.8.1, “Adjusting the
26 MHz Oscillator Trim.”
7–0
Reserved. These bits are reserved and should read 0.
Reserved
Bits 7–0
3.4.8.1
Reserved—These bits are reserved and should read 0.
Adjusting the 26 MHz Oscillator Trim
To ensure a proper startup of the 26 MHz oscillator on power-up or system reset use the following steps
to determine the optimum trim of the oscillator AGC. To ensure proper startup of 26 MHz oscillator on
power-up or system reset, use Example 3-2 to determine optimum trim. This algorithm must be run to
determine optimum AGC setting. Once done, software must read the trim value from external memory and
write it to OSC26M_AGC[5:0].
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
3-20
Freescale Semiconductor
Clocks, Power Management, and Reset Control
Example 3-2. 26 MHz Oscillator Trim Programming Algorithm
1. At power up or system reset, OSC26M_AGC[5:0] bits in the OSC26MCTL register are reset to
logic 1 (done in hardware, no software interaction required).
2. Read the peak amplitude value in bits OSC26M_PEAK[1:0] in the OSC26MCTL register.
3. If the amplitude is not in the desired range, adjust by decrementing the OSC26M_AGC[5:0] by 1
count.
4. Wait at least 30.5 us (1 cycle of 32 kHz clock) for system to update OSC26M_PEAK bits.
5. Repeat steps 2 to 4 until trimmed in desired range.
6. Decrement 4 additional counts to provide a margin of error for temperature drift.
7. Store trim value in an external memory—that is, Flash, for future use.
It is suggested that the proceeding algorithm be run to determine the optimum AGC setting. Once this is
done on power-up or system reset the software must read the trim value from the external memory and
write it to the OSC26M_AGC[5:0].
3.4.9
Peripheral Clock Divider Register 0 (PCDR0)
The Peripheral Clock Divider Register 0 (PCDR0) contains the divider values for the peripheral clock
dividers in the PLL Clock Controller. Peripherals in the i.MX27 device require special clock frequency
which is divided down from the MPLL and the SPLL clock output. Each of these peripheral modules
receive their clock input from the respective clock divider. These modules will still have the clock gating
scheme as with other modules for power saving advantages.
Figure 3-10 shows the register and Table 3-14 provides the field descriptions.
Table 3-16 lists the clock sources associated with the i.MX27 peripherals given in the PCDR0.
0x1002_7018 (PCDR0)
31
30
29
Access: User R/W
28
27
26
R
24
CLKO
_EN
SSI2DIV
W
Reset
25
23
22
21
20
CLKO_DIV
19
18
17
16
SSI1DIV
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
R
H264DIV
NFCDIV
MSHCDIV
W
Reset
0
0
0
1
0
1
0
0
1
1
0
0
0
0
Figure 3-10. Peripheral Clock Divider Register 0 (PCDR0)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
3-21
Clocks, Power Management, and Reset Control
Table 3-14. Peripheral Clock Divider Register 0 Field Descriptions
Field
Description
31–26
SSI2DIV
SSI2 Baud Clock Divider. Contains 6-bit fractional divider that produces the clock for SSI2CLK clock signal for
the peripherals. The value of the divider starts from 0.
0 2
1 2.5
2 3
....
63 33.5
Note: Formula for all others: clkin / (2 + 0.5 * SSI2DIV)
25
Clock Out Enable. Enable bit for CLKO pin.
CLKO_EN 0 disable CLKO output
1 enable CLKO output
24–22
Clock Out Divider. Contains the 3-bit divider that divides output clocks to CLKO pin.
CLKO_DIV 000 Divide by 1
001 Divide by 2
…
111 Divide by 8
21–16
SSI1DIV
SSI1 Baud Clock Divider. Contains 6-bit fractional divider that produces the clock for SSI1CLK clock signal for
the peripherals. The value of the divider starts from 0.
0 2
1 2.5
2 3
....
63 33.5
Note: Formula for all others: clkin / (2 + 0.5 * SSI1DIV)
15–10
H264DIV
H264 Baud Clock Divider. Contains 6-bit fractional divider that produces the clock for H264CLK clock signal for
the peripherals. The value of the divider starts from 0.
0 2
1 2.5
2 3
....
63 33.5
Note: Formula for all others: clkin / (2 + 0.5 * H264DIV)
9–6
NFCDIV
NAND Flash Controller Clock Divider. Contains 4-bit divider that produces the clock for NFCCLK clock signal of
the NAND Flash Controller.
0000 Divide by 1
0001 Divide by 2
…
1111 Divide by 16
5–0
MSHC Clock Divider. Contains 6-bit divider that produces the clock for MSHCCLK clock signal of MSHC.
MSHCDIV 000000 Divide by 1
000001 Divide by 2
…
111111 Divide by 64
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
3-22
Freescale Semiconductor
Clocks, Power Management, and Reset Control
3.4.10
Peripheral Clock Divider Register 1 (PCDR1)
The Peripheral Clock Divider Register 1 (PCDR1) contains the divider values for the peripheral clock
dividers in the PLL Clock Controller. Peripherals in i.MX27 requires special clock frequency which is
divided down from the MPLL and the SPLL clock output. Each of these peripheral modules receive their
clock input from the respective clock divider. These modules will still have the clock gating scheme as
with other modules for power saving advantages. Figure 3-11 shows the register and Table 3-15 provides
the field descriptions.
Table 3-16 lists the clock sources associated with the i.MX27 peripherals given in the PCDR1.
0x1002_701C (PCDR1)
R
31
30
0
0
29
Access: User R/W
28
27
26
25
24
23
22
0
0
21
20
PERDIV4
19
18
17
16
PERDIV3
W
Reset
R
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
1
1
PERDIV2
PERDIV1
W
Reset
0
0
0
0
0
0
1
1
0
0
0
0
0
0
Figure 3-11. Peripheral Clock Divider Register 1(PCDR1)
Table 3-15. Peripheral Clock Divider Register 1 Field Descriptions
Field
31–30
29–24
PERDIV4
23–22
21–16
PERDIV3
15–14
Description
These are reserved bits and should read 0.
Peripheral Clock Divider 4. Contains 6-bit integer divider that produces PERCLK4 clock signal for CSI MCLK
Clock.
000000 Divide by 1
000001 Divide by 2
…
111111 Divide by 64
These are reserved bits and should read 0.
Peripheral Clock Divider 3. Contains 6-bit integer divider that produces PERCLK3 clock signal for LCDC Pixel
Clock.
000000 Divide by 1
000001 Divide by 2
…
111111 Divide by 64
These are reserved bits and should read 0.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
3-23
Clocks, Power Management, and Reset Control
Table 3-15. Peripheral Clock Divider Register 1 Field Descriptions (continued)
Field
Description
13–8
PERDIV2
Peripheral Clock Divider 2. Contains 6-bit integer divider that produces PERCLK2 clock signal for the peripheral
2set (CSPI and SDHC).
000000 Divide by 1
000001 Divide by 2
…
111111 Divide by 64
7–6
5–0
PERDIV1
These are reserved bits and should read 0.
Peripheral Clock Divider 1. Contains 6-bit integer divider that produces PERCLK1 clock signal for the peripheral
1 set (UART, GPT, PWM).
000000 Divide by 1
000001 Divide by 2
…
111111 Divide by 64
Table 3-16. Clock Sources for i.MX27 Peripherals
Clock Source
Peripherals
Clock Source
Peripherals
SSI1CLK
SSI1
NFCCLK
NFC
SSI2CLK
SSI2
MSHCCLK
MSHC
H264CCLC
H264
—
—
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
3-24
Freescale Semiconductor
Clocks, Power Management, and Reset Control
3.4.11
Peripheral Clock Control Register 0 (PCCR0)
The Peripheral Clock Control Register 0 (PCCR0) provides additional power saving capabilities by
controlling the clocks in the i.MX27 modules. It also controls the clock source for Bootstrap mode. The
PCCR0 allows for gating of HCLK to modules or peripherals that access the AHB bus and perform AHB
bus transfers and also allows for gating of the ipg clk (PERCLK) to specific peripherals.
Figure 3-12 shows the register and Table 3-17 provides the field descriptions.
27
26
25
24
23
22
21
20
19
18
17
16
W
CSPI3_EN
DMA_EN
EMMA_EN
FEC_EN
GPIO_EN
GPT1_EN
GPT2_EN
GPT3_EN
GPT4_EN
GPT5_EN
GPT6_EN
I2C1_EN
I2C2_EN
IIM_EN
Reset
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RTC_EN
RTIC_EN
SAHARA_EN
SCC_EN
SDHC1_EN
SDHC2_EN
SDHC3_EN
SLCDC_EN
SSI1_EN
SSI2_EN
0
1
1
1
0
0
0
0
0
0
R
W
KPP_EN
R
Reset
0
0
PWM_EN
28
OWIRE_EN
29
MSHC_EN
30
LCDC_EN
31
CSPI2_EN
Access: User R/W
CSPI1_EN
0x1002_7020 (PCCR0)
0
0
0
0
0
Figure 3-12. Peripheral Clock Control Register 0 (PCCR0)
Table 3-17. Peripheral Clock Control Register 0 Field Descriptions
Field
Description
31
CSPI1_EN
CSPI1 IPG Clock Enable. Enables/Disables IPG clock input to CSPI1 module.
0 CSPI1 IPG clock input is disabled.
1 CSPI1 IPG clock input is enabled.
30
CSPI2_EN
CSPI2 IPG Clock Enable. Enables/Disables IPG clock input to CSPI2 module.
0 CSPI2 IPG clock input is disabled.
1 CSPI2 IPG clock input is enabled.
29
CSPI3_EN
CSPI3 IPG Clock Enable. Enables/Disables IPG clock input to CSPI3 module.
0 CSPI3 IPG clock input is disabled.
1 CSPI3 IPG clock input is enabled.
28
DMA_EN
27
EMMA_EN
26
FEC_EN
DMA IPG Clock Enable. Enables/Disables IPG clock input to DMA module.
0 DMA IPG clock input is disabled.
1 DMA IPG clock input is enabled.
EMMA IPG Clock Enable. Enables/Disables IPG clock input to EMMA module.
0 EMMA IPG clock input is disabled.
1 EMMA IPG clock input is enabled.
FEC IPG Clock Enable. Enables/Disables IPG clock input to FEC module.
0 FEC IPG clock input is disabled.
1 FEC IPG clock input is enabled.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
3-25
Clocks, Power Management, and Reset Control
Table 3-17. Peripheral Clock Control Register 0 Field Descriptions (continued)
Field
Description
25
GPIO_EN
GPIO IPG Clock Enable. Enables/Disables IPG clock input to GPIO module.
0 GPIO IPG clock input is disabled.
1 GPIO IPG clock input is enabled.
24
GPT1_EN
GPT1 IPG Clock Enable. Enables/Disables IPG clock input to GPT1 module.
0 GPT1 IPG clock input is disabled.
1 GPT1 IPG clock input is enabled.
23
GPT2_EN
GPT2 IPG Clock Enable. Enables/Disables IPG clock input to GPT2 module.
0 GPT2 IPG clock input is disabled.
1 GPT2 IPG clock input is enabled.
22
GPT3_EN
GPT3 IPG Clock Enable. Enables/Disables IPG clock input to GPT3 module.
0 GPT3 IPG clock input is disabled.
1 GPT3 IPG clock input is enabled.
21
GPT4_EN
GPT4 IPG Clock Enable. Enables/Disables IPG clock input to GPT4 module.
0 GPT4 IPG clock input is disabled.
1 GPT4 IPG clock input is enabled.
20
GPT5_EN
GPT5 IPG Clock Enable. Enables/Disables IPG clock input to GPT5 module.
0 GPT5 IPG clock input is disabled.
1 GPT5 IPG clock input is enabled.
19
GPT6_EN
GPT6 IPG Clock Enable. Enables/Disables IPG clock input to GPT6 module.
0 GPT6 IPG clock input is disabled.
1 GPT6 IPG clock input is enabled.
18
I2C1_EN
I2C1 IPG Clock Enable. Enables/Disables IPG clock input to I2C1 module.
0 I2C1 IPG clock input is disabled.
1 I2C1 IPG clock input is enabled.
17
I2C2_EN
I2C2 IPG Clock Enable. Enables/Disables IPG clock input to I2C2 module.
0 I2C2 IPG clock input is disabled.
1 I2C2 IPG clock input is enabled.
16
IIM_EN
15
KPP_EN
IIM IPG Clock Enable. Enables/Disables IPG clock input to IIM module.
0 IIM IPG clock input is disabled.
1 IIM IPG clock input is enabled.
KPP IPG Clock Enable. Enables/Disables IPG clock input to KPP module.
0 KPP IPG clock input is disabled.
1 KPP IPG clock input is enabled.
14
LCDC_EN
LCDC IPG Clock Enable. Enables/Disables IPG clock input to LCDC module.
0 LCDC IPG clock input is disabled.
1 LCDC IPG clock input is enabled.
13
MSHC_EN
MSHC IPG Clock Enable. Enables/Disables IPG clock input to MSHC module.
0 MSHC IPG clock input is disabled.
1 MSHC IPG clock input is enabled.
12
OWIRE_EN
OWIRE IPG Clock Enable. Enables/Disables IPG clock input to OWIRE module.
0 OWIRE IPG clock input is disabled.
1 OWIRE IPG clock input is enabled.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
3-26
Freescale Semiconductor
Clocks, Power Management, and Reset Control
Table 3-17. Peripheral Clock Control Register 0 Field Descriptions (continued)
Field
11
PWM_EN
10
Description
PWM IPG Clock Enable. Enables/Disables IPG clock input to PWM module.
0 PWM IPG clock input is disabled.
1 PWM IPG clock input is enabled.
Reserved. This bit is reserved.
9
RTC_EN
RTC IPG Clock Enable. Enables/Disables IPG clock input to RTC module.
0 RTC IPG clock input is disabled.
1 RTC IPG clock input is enabled.
8
RTIC_EN
RTIC IPG Clock Enable. Enables/Disables IPG clock input to RTIC module.
0 RTIC IPG clock input is disabled.
1 RTIC IPG clock input is enabled.
7
SAHARA_EN
6
SCC_EN
SAHARA IPG Clock Enable. Enables/Disables IPG clock input to SAHARA module.
0 SAHARA IPG clock input is disabled.
1 SAHARA IPG clock input is enabled.
SCC IPG Clock Enable. Enables/Disables IPG clock input to SCC_EN module.
0 SCC_EN IPG clock input is disabled.
1 SCC_EN IPG clock input is enabled.
5
SDHC1_EN
SDHC1 IPG Clock Enable. Enables/Disables IPG clock input to SDHC1 module.
0 SDHC1 IPG clock input is disabled.
1 SDHC1 IPG clock input is enabled.
4
SDHC2_EN
SDHC2 IPG Clock Enable. Enables/Disables IPG clock input to SDHC2 module.
0 SDHC2 IPG clock input is disabled.
1 SDHC2 IPG clock input is enabled.
3
SDHC3_EN
SDHC3 IPG Clock Enable. Enables/Disables IPG clock input to SDHC3 module.
0 SDHC3 IPG clock input is disabled.
1 SDHC3 IPG clock input is enabled.
2
SLCDC_EN
SLCDC IPG Clock Enable. Enables/Disables IPG clock input to SLCDC module.
0 SLCDC IPG clock input is disabled.
1 SLCDC IPG clock input is enabled.
1
SSI1_EN
SSI1 IPG Clock Enable. Enables/Disables IPG clock input to SSI1 module.
0 SSI1 IPG clock input is disabled.
1 SSI1 IPG clock input is enabled.
0
SSI2_EN
SSI2 IPG Clock Enable. Enables/Disables IPG clock input to SSI2 module.
0 SSI2 IPG clock input is disabled.
1 SSI2 IPG clock input is enabled.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
3-27
Clocks, Power Management, and Reset Control
3.4.12
Peripheral Clock Control Register 1 (PCCR1)
The Peripheral Clock Control Register 1 (PCCR1) provides additional power saving capabilities by
controlling the clocks in the i.MX27 modules. It also controls the clock source for Bootstrap mode. The
PCCR1 allows for gating of the ipg clk (PERCLK) to specific peripherals. Figure 3-13 shows the register
and Table 3-18 provides the field descriptions.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
W
UART1_EN
UART2_EN
UART3_EN
UART4_EN
UART5_EN
UART6_EN
USB_EN
WDT_EN
HCLK_ATA
HCLK_BROM
HCLK_CSI
HCLK_DMA
HCLK_EMI
HCLK_EMMA
HCLK_FEC
HCLK_H264
Reset
1
1
1
1
1
1
1
1
0
1
0
0
1
0
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HCLK_RTIC
HCLK_SAHARA
HCLK_SLCDC
HCLK_USB
PERCLK1_EN
PERCLK2_EN
PERCLK3_EN
PERCLK4_EN
H264_BAUDEN
SSI1_BAUDEN
SSI2+BAUDEN
NFC_BAUDEN
MSHC_BAUDEN
Access: User R/W
HCLK_LCDC
0x1002_7024 (PCCR1)
0
0
0
1
1
0
1
0
0
0
0
1
0
0
1
0
0
0
R
R
W
Reset
Figure 3-13. Peripheral Clock Control Register 1(PCCR1)
Table 3-18. Peripheral Clock Control Register 1 Field Descriptions
Field
Description
31
UART1_EN
UART1 IPG Clock Enable. Enables/Disables IPG clock input to UART1 module.
0 UART1 IPG clock input is disabled.
1 UART1 IPG clock input is enabled.
30
UART2_EN
UART2 IPG Clock Enable. Enables/Disables IPG clock input to UART2 module.
0 UART2 IPG clock input is disabled.
1 UART2 IPG clock input is enabled.
29
UART3_EN
UART3 IPG Clock Enable. Enables/Disables IPG clock input to UART3 module.
0 UART3 IPG clock input is disabled.
1 UART3 IPG clock input is enabled.
28
UART4_EN
UART4 IPG Clock Enable. Enables/Disables IPG clock input to UART4 module.
0 UART4 IPG clock input is disabled.
1 UART4 IPG clock input is enabled.
27
UART5_EN
UART5 IPG Clock Enable. Enables/Disables IPG clock input to UART5 module.
0 UART5 IPG clock input is disabled.
1 UART5 IPG clock input is enabled.
26
UART6_EN
UART6 IPG Clock Enable. Enables/Disables IPG clock input to UART6 module.
0 UART6 IPG clock input is disabled.
1 UART6 IPG clock input is enabled.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
3-28
Freescale Semiconductor
Clocks, Power Management, and Reset Control
Table 3-18. Peripheral Clock Control Register 1 Field Descriptions (continued)
Field
Description
25
USB_EN
USB IPG Clock Enable. Enables/Disables IPG clock input to USB module.
0 USB IPG clock input is disabled.
1 USB IPG clock input is enabled.
24
WDT_EN
WDT IPG Clock Enable. Enables/Disables IPG clock input to WDT module.
0 WDT IPG clock input is disabled.
1 WDT IPG clock input is enabled.
23
HCLK_ATA
ATA AHB Clock Enable. Enables/Disables AHB clock input to ATA module.
0 ATA AHB clock input is disabled.
1 ATA AHB clock input is enabled.
22
HCLK_BROM
BROM AHB Clock Enable. Enables/Disables AHB clock input to BROM module.
0 BROM AHB clock input is disabled.
1 BROM AHB clock input is enabled.
21
HCLK_CSI
CSI AHB Clock Enable. Enables/Disables AHB clock input to CSI module.
0 CSI AHB clock input is disabled.
1 CSI AHB clock input is enabled.
20
HCLK_DMA
DMA AHB Clock Enable. Enables/Disables AHB clock input to DMA module.
0 DMA AHB clock input is disabled.
1 DMA AHB clock input is enabled.
19
HCLK_EMI
EMI AHB Clock Enable. Enables/Disables AHB clock input to EMI module.
0 EMI AHB clock input is disabled.
1 EMI AHB clock input is enabled.
18
HCLK_EMMA
EMMA AHB Clock Enable. Enables/Disables AHB clock input to EMMA module.
0 EMMA AHB clock input is disabled.
1 EMMA AHB clock input is enabled.
17
HCLK_FEC
FEC AHB Clock Enable. Enables/Disables AHB clock input to FEC module.
0 FEC AHB clock input is disabled.
1 FEC AHB clock input is enabled.
16
HCLK_H264
H264 AHB Clock Enable. Enables/Disables AHB clock input to H264 module.
0 H264 AHB clock input is disabled.
1 H264 AHB clock input is enabled.
15
HCLK_LCDC
LCDC AHB Clock Enable. Enables/Disables AHB clock input to LCDC module.
0 LCDC AHB clock input is disabled.
1 LCDC AHB clock input is enabled.
14
HCLK_RTIC
RTIC AHB Clock Enable. Enables/Disables AHB clock input to RTIC module.
0 RTIC AHB clock input is disabled.
1 RTIC AHB clock input is enabled.
13
HCLK_SAHARA
12
HCLK_SLCDC
SAHARA AHB Clock Enable. Enables/Disables AHB clock input to SAHARA module.
0 SAHARA AHB clock input is disabled.
1 SAHARA AHB clock input is enabled.
SLCDC AHB Clock Enable. Enables/Disables AHB clock input to SLCDC module.
0 SLCDC AHB clock input is disabled.
1 SLCDC AHB clock input is enabled.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
3-29
Clocks, Power Management, and Reset Control
Table 3-18. Peripheral Clock Control Register 1 Field Descriptions (continued)
Field
11
HCLK_USB
Description
USB AHB Clock Enable. Enables/Disables AHB clock input to USB module.
0 USB AHB clock input is disabled.
1 USB AHB clock input is enabled.
10
PERCLK1_EN
PERCLK1 Clock Enable. Enables/Disables Peripheral clock1.
0 Peripheral clock1 is disabled.
1 Peripheral clock1 is enabled.
9
PERCLK2_EN
PERCLK2 Clock Enable. Enables/Disables Peripheral clock2.
0 Peripheral clock2 is disabled.
1 Peripheral clock2 is enabled.
8
PERCLK3_EN
PERCLK3 Clock Enable. Enables/Disables Peripheral clock3.
0 Peripheral clock3 is disabled.
1 Peripheral clock3 is enabled.
7
PERCLK4_EN
PERCLK4 Clock Enable. Enables/Disables Peripheral clock4.
0 Peripheral clock4 is disabled.
1 Peripheral clock4 is enabled.
6
H264_BAUDEN
H264 BAUD Clock Enable. Enables/Disables BAUD clock input to H264 module.
0 H264 BAUD clock input is disabled.
1 H264 BAUD clock input is enabled.
5
SSI1_BAUDEN
SSI1 BAUD Clock Enable. Enables/Disables BAUD clock input to SSI1 module.
0 SSI1 BAUD clock input is disabled.
1 SSI1 BAUD clock input is enabled.
4
SSI2_BAUDEN
SSI2 BAUD Clock Enable. Enables/Disables BAUD clock input to SSI2 module.
0 SSI2 BAUD clock input is disabled.
1 SSI2 BAUD clock input is enabled.
3
NFC_BAUDEN
NFC BAUD Clock Enable. Enables/Disables BAUD clock input to NFC module.
0 NFC BAUD clock input is disabled.
1 NFC BAUD clock input is enabled.
2
MSHC_BAUDEN
1–0
MSHC BAUD Clock Enable. Enables/Disables BAUD clock input to MSHC module.
0 MSHC BAUD clock input is disabled.
1 MSHC BAUD clock input is enabled.
Reserved. These bits are reserved and should read 0.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
3-30
Freescale Semiconductor
Clocks, Power Management, and Reset Control
3.4.13
Clock Control Status Register (CCSR)
The Clock Control Status Register (CCSR) provides information on the configuration of the Analog and
Digital block. The clocks within the chip can also be monitored by the CLKO_SEL programming.
Figure 3-14 shows the register and Table 3-19 provides the field descriptions.
0x1002_7028 (CCSR)
R
Access: User R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R 32K
W _SR
Reset
0
CLKMODE
0
0
0
0
0
1
1
CLKO_SEL
0
0
0
0
0
0
Figure 3-14. Clock Control Status Register (CCSR)
Table 3-19. Clock Control Status Register Field Descriptions
Field
Description
31–16
Reserved. These bit are reserved and should read 0.
15
32K_SR
32K Status Register. It contains status information of 32 KHz clock. It is cleared to zero
during the assertion of HARD_ASYNC_RESET signal. The sampled 32KHz clock phase
is continuously registered into the bit upon the de-assertion of HARD_ASYNC_RESET
signal.
0 CLK32 in low phase
1 CLK32 in high phase
14–12
Reserved. These bits are reserved and should read 0.
9–8
CLKMODE
CLKMODE. Determines the configuration of FPM, OSC26M and DPLL on the chip. Its
reset value depends on CLKMODE input signals.
00 DPLL, FPM, OSC26M bypassed
01 FPM bypassed.
10 FPM and OSC26M bypassed
11 FPM and DPLL in use (Default)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
3-31
Clocks, Power Management, and Reset Control
Table 3-19. Clock Control Status Register Field Descriptions (continued)
Field
7–5
4–0
CLKO_SEL
Description
Reserved. These bits are reserved and should read 0.
CLKO Select. Selects which clock signal source is the output of CLKO pin.
00000 CLK32
00001 PREMCLK
00010 CLK26M
00011 MPLL Reference CLK
00100 SPLL Reference CLK
00101 HCLK Source (MPLL 2x clock output / 3)
00110 SPLL CLK
00111 FCLK
01000 HCLK
01001 IPG_CLK
01010 PERCLK1
01011 PERCLK2
01100 PERCLK3
01101 PERCLK4
01110 SSI 1 Baud
01111 SSI 2 Baud
10000 NFC Baud
10001 MSHC_Baud
10010 H264 Baud
10011 CLK60M Always
10100 CLK32K Always
10101 CLK60M
10110 DPTC Reference Clock
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
3-32
Freescale Semiconductor
Clocks, Power Management, and Reset Control
3.4.14
Wakeup Guard Mode Control Register (WKGDCTL)
The Wakeup Guard mode Control Register (WKGDCTL) provides the configuration of the Wakeup Guard
mode. This is a write once only bit in order to be compatible with the watchdog behavior. After
enable/disable, it will not be modifiable. When enabled, the battery detector external to the chip provides
a glitch free signal through the TIN pin. Battery must be intact for the chip to wakeup from sleep.
Figure 3-15 shows the register and Table 3-20 provides the field descriptions.
0x1002_7034 (WKGDCTL)
R
Access: User write-once
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
WKGD_EN
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-15. Wakeup Guard Mode Control Register (WKGDCTL)
Table 3-20. Wakeup Guard Mode Control Register Field Descriptions
Field
31–1
0
WKDG_EN
Description
Reserved. These bits are reserved and should read 0.
Wakeup Guard Mode Enable. Enables /disables the wakeup guard logic. Write- once-only bit and can only be
cleared through system reset. Once enabled, battery indicator through TIN will be used to qualify the wakeup
process. When battery is intact, that is, TIN=1, wakeup from sleep proceed as per normal. When WKGD_EN=1
and battery is removed, 32 kHz clock to watchdog module is gated off. Clock resumes when battery is back in
place.
0 Wakeup Guard mode is disabled.
1 Wakeup Guard mode is enabled.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
3-33
Clocks, Power Management, and Reset Control
3.5
Functional Description of the Reset Module
The reset module controls or distributes all of the system reset signals used by the i.MX27 processor. A
simplified block diagram of the reset module is shown in Figure 3-16. The reset module generates two
distinct events—a global reset and an ARM9 Platform reset.
RESET_POR
POR
RESET_POR
300 ms
Counter
RESET_DRAM
7-cycle
stretcher
CLK32
POR_TIMEOUT
(programmed values)
fuse_latch
CLK32
14-cycle
HRESET
syn logic
stretcher
CLK32
3-cycle
Rising edge
detector
4-cycle
qualifier
WDOG_RESET
syn logic
stretcher
CLK32
RESET
HARD_ASYNC_RESET
hclk
RSR
GLOBAL_RESET
IP bus
EXT_RESET
Figure 3-16. Reset Module Clock Diagram
3.5.1
Global Reset
A global reset is produced by the simultaneous assertion of the following resets:
• RESET_DRAM
• HRESET
• HARD_ASYNC_RESET
• RESET_POR
There is one source capable of generating a global reset: A low condition on the POR pin when the 32 kHz
crystal oscillator is running.
The HRESET and HARD_ASYNC_RESET are armed simultaneously; they remain in that state for 14
CLK32 cycles.
RESET_DRAM is deasserted seven CLK32 cycles before HRESET and HARD_ASYNC_RESET are
deasserted. The SDRAM executes the necessary self refresh operations during this time.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
3-34
Freescale Semiconductor
Clocks, Power Management, and Reset Control
The timing diagram in Figure 3-16 shows the relationship of the reset signal timings. See Table 3-21 for
reset module signal and pin definitions.
The following signal conditions are not capable of generating a global reset, however their assertion will
reset the ARM9 Platform:
• An external qualified low condition on the RESET_IN pin
• A low condition on WDOG_RESET
Furthermore, these reset conditions will not reset the SDRAMC, Real Time Clock, WatchDog module, or
allow a change in Boot mode—that is, changes made to BOOT[3:0] during these resets conditions will not
take effect. Only the global reset is capable of this.
The source of the last hardware reset can be determined in the watchdog status register.
NOTE
Due to the asynchronous nature of the RESET_IN signal, the time period
required to qualify the signal may vary, and the HRESET timing relative to
the rising edge of the RESET_IN is also affected. A RESET_IN signal
shorter than three CLK32 cycles will not be qualified, a RESET_IN signal
equal to or longer than four CLK32 cycles will always be qualified, and any
period length that is more than three and less than four CLK32 cycles is
undefined.
POR is the reset signal for all the reset module flip-flops. For this reason, an
external reset signal is qualified if it lasts more than four CLK32 cycles
when POR is deasserted.
During power on the user must ensure that POR stay asserted (low) long
enough for the 32kHz crystal to stabilize. The time it takes for the crystal to
stabilize depends upon on the crystal used. Consult the crystal’s
specification for details about its stabilization timing.
NOTE
Refer to the i.MX27 Multimedia Applications Processor Data Sheet for
power-up and power-down sequence requirements.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
3-35
Clocks, Power Management, and Reset Control
POR
RESET_POR
7 cycles @ clk32
300 ms
RESET_DRAM
u
RESET_CPU
RESET_SYS
14 cycles @ clk32
n
d
e
CLK32
f
i
HCLK
n
e
d
Figure 3-17. DRAM and Internal Reset Timing Diagram
3.5.2
ARM9 Platform Reset
Any qualified global reset signal resets the ARM9 Platform and all related peripherals to their default state.
After the internal reset is deasserted, the ARM9 processor begins fetching code from the internal bootstrap
ROM or CS0 space. The memory location of the fetch depends on the configuration of the BOOT pins and
the value of the TEST pin on the rising edge of the HRESET.
Table 3-21. Reset Module Pin and Signal Descriptions
Signal Name
Direction
Signal Description
CLK32
IN
32 kHz Clock—A 32 kHz clock signal derived from the 32.768 KHz or 32.0 KHz crystal
oscillator circuit in the PLL Clock Controller.
POR
IN
Power-On Reset—An internal active Schmitt trigger signal from the POR pin. The POR
signal is normally generated by an external RC circuit designed to detect a power-up
event.
RESET_IN
IN
Reset—An external active low Schmitt trigger signal from the RESET_IN pin. When this
signal goes active, all modules (except the SDRAMC, Real Time Clock, WatchDog, and
the BOOT[3:0] signals) are reset.
WDOG_RESET
IN
Watchdog Timer Reset—An active low signal generated by the watchdog timer when a
time-out period has expired. Resets the same modules as RESET_IN.
HARD_ASYN_RESET
OUT
Hard Asynchronous Reset—An active low signal that resets all peripheral modules
except the watchdog module’s status register. The rising edge of this signal is
synchronous with IPG_CLK.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
3-36
Freescale Semiconductor
Clocks, Power Management, and Reset Control
Table 3-21. Reset Module Pin and Signal Descriptions (continued)
Signal Name
Direction
Signal Description
HRESET
OUT
Hard Reset—An active low signal that resets the ARM9 Platform. This signal is
deasserted during the low phase of HCLK. This signal also appears on the RESET_OUT
pin of the i.MX27.
RESET_DRAM
OUT
DRAM Reset—An active low signal that resets the SDRAM controller.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
3-37
Clocks, Power Management, and Reset Control
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
3-38
Freescale Semiconductor
Chapter 4
System Control
4.1
Introduction
This chapter describes the system control module of the i.MX27 microprocessor. The system control
module enables system software to control, customize, or read the status of the following functions:
• Chip ID
• Multiplexing of I/O signals
• I/O Drive Strength
• I/O Pull Enable Control
• Well Bias Control
• System boot mode selection
• DPTC Control
4.2
Memory Map and Register Definition
The system control module includes one 32-bit Silicon ID and twenty-four user-accessible 32-bit registers.
Table 4-1 summarizes these registers and their addresses.
Table 4-1. Block Memory Map
Address
Register
Access
Reset Value
Section/Page
General Registers
0x1002_7800 (CID)
Chip ID Register
R/W
0x1882_181D
4.2.1/4-3
0x1002_7814 (FMCR)
Function Multiplexing Control Register
R/W
0xFFFF_FFCB
4.2.2/4-4
0x1002_7818 (GPCR)
Global Peripheral Control Register
R/W
0x0000_0808
4.2.3/4-7
0x1002_781C (WBCR)
Well Bias Control Register
R/W
0x0000_0000
4.2.5/4-9
0x1002_7820 (DSCR1)
Drive Strength Control Register 1
R/W
0x0000_0000
4.2.6/4-11
0x1002_7824 (DSCR2)
Drive Strength Control Register 2
R/W
0x0000_0000
4.2.7/4-13
0x1002_7828 (DSCR3)
Drive Strength Control Register 3
R/W
0x0000_0000
4.2.8/4-15
0x1002_782C (DSCR4)
Drive Strength Control Register 4
R/W
0x0000_0000
4.2.9/4-17
0x1002_7830 (DSCR5)
Drive Strength Control Register 5
R/W
0x0000_0000
4.2.10/4-19
0x1002_7834 (DSCR6)
Drive Strength Control Register 6
R/W
0x0000_0000
4.2.11/4-21
0x1002_7838 (DSCR7)
Drive Strength Control Register 7
R/W
0x0000_0000
4.2.12/4-24
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-1
System Control
Table 4-1. Block Memory Map (continued)
Address
Register
Access
Reset Value
Section/Page
0x1002_783C (DSCR8)
Drive Strength Control Register 8
R/W
0x0000_0000
4.2.13/4-26
0x1002_7840 (DSCR9)
Drive Strength Control Register 9
R/W
0x0000_0000
4.2.14/4-28
0x1002_7844 (DSCR10)
Drive Strength Control Register 10
R/W
0x0000_0000
4.2.15/4-31
0x1002_7848 (DSCR11)
Drive Strength Control Register 11
R/W
0x0000_0000
4.2.16/4-33
0x1002_784C (DSCR12)
Drive Strength Control Register 12
R/W
0x0000_0000
4.2.17/4-35
0x1002_7850 (DSCR13)
Drive Strength Control Register 13
R/W
0x0000_0000
4.2.18/4-37
0x1002_7854 (PSCR)
Pull Strength Control Register
R/W
0x0000_0000
4.2.19/4-39
0x1002_7858 (PCSR)
Priority Control and Select Register
R/W
0x0000_0003
4.2.20/4-41
0x1002_7860 (PMCR)
Power Management Control Register
R/W
0x0000_0000
4.2.21/4-42
0x1002_7864 (DCVR0)
DPTC Comparator Value Register 0
R/W
0x0000_0000
4.2.22/4-44
0x1002_7868 (DCVR1)
DPTC Comparator Value Register 1
R/W
0x0000_0000
4.2.23/4-44
0x1002_786C (DCVR2)
DPTC Comparator Value Register 2
R/W
0x0000_0000
4.2.24/4-45
0x1002_7870 (DCVR3)
DPTC Comparator Value Register 3
R/W
0x0000_0000
4.2.25/4-46
The conventions in Figure 4-1 and Table 4-2 serve as a key for the register summary and individual register
diagrams.
Always
reads 1
1
Always
reads 0
0
R/W BIT Read- BIT WriteWrite 1 BIT Self-clear 0
bit
only bit
only bit BIT to clear w1c
bit BIT
N/A
Figure 4-1. Key to Register Fields
Table 4-2 provides a key for register figures and tables and the register summary.
Table 4-2. Register Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writable.
FIELDNAME
Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
R
Read only. Writing this bit has no effect.
W
Write only.
R/W
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by a hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
Self-clearing bit Writing a one has some effect on the module, but it always reads as zero. (Previously designated slfclr)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
4-2
Freescale Semiconductor
System Control
Table 4-2. Register Conventions (continued)
Convention
Description
Reset Values
0
Resets to zero.
1
Resets to one.
—
Undefined at reset.
u
Unaffected by reset.
[signal_name]
4.2.1
Reset value is determined by polarity of indicated signal.
Chip ID Register (CID)
The Chip ID register contains the chip identification number. Figure 4-2 shows the register and Table 4-3
provides its field descriptions.
0x1002_7800 (CID)
31
R
28
27
26
25
24
23
22
21
20
19
18
17
16
PART NUMBER
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
1
R
PART NUMBER
W
Reset
29
VERSION ID
W
Reset
30
Access: User R/W
0
0
0
MANUFACTURER ID
1
0
0
0
0
0
0
0
1
Figure 4-2. Chip ID Register (CID)
Table 4-3. Chip ID Register Field Descriptions
Field
31–28
VERSION ID
27–12
PART NUMBER
Description
VERSION ID. This field contains the 4-bit version ID number.
PART NUMBER. This field contains the 16-bit part number of the chip.
11–0
MANUFACTURER ID. This field contains the 12-bit manufacturer ID
MANUFACTURER ID number of the chip.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-3
System Control
4.2.2
Function Multiplexing Control Register (FMCR)
The FMCR controls the multiplexing of the signal lines shared by the SLCDC module, UART module,
and Keypad module as well as the SDRAM chip select lines. The FMCR also allows control or indicates
the boot status of the NAND Flash page size and data port size. Figure 4-3 shows the register and Table 4-4
provides its field descriptions.
26
25
24
23
22
21
20
19
1
1
UART4_RXD_CTL
UART4_RTS_CTL
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
5
4
3
2
1
0
1
PC_VS2_CTL
PC_BVD1_CTL
PC_BVD2_CTL
IOIS16_CTL
SLCDC_SEL
SDCS1_SEL
SDCS0_SEL
R
1
1
1
1
1
1
1
1
0
1
1
W
Reset
7
6
1
1
1
1
1
0
0
1
16
KP_ROW6_CTL
27
1
PC_VS1_CTL
Reset
17
KP_ROW7_CTL
28
1
W
18
KP_COL6_CTL
29
1
NF_16BIT_SEL
30
1
NF_FMS
31
PC_READY_CTL
R
Access: User R/W
PC_WAIT_B_CTL
0x1002_7814 (FMCR)
1
1
1
Figure 4-3. Function Multiplexing Control Register (FMCR)
Table 4-4. Function Multiplexing Control Register Description
Field
Description
31–26
Reserved. These bits are reserved and should read 1.
25
UART4_RXD_CTL
UART4 RXD Control. When set, the alternate signal of USBH1_RXDP (PB31) is input
to RXD of UART4. When 0, the USBH1_TXDP (PB29) GPIO’s AOUT is input to RXD
of UART4. With either setting, the user must also ensure that the proper GPIO
registers have been programmed to select the desired multiplexing.
0 The USBH1_TXDP (PB29) GPIO’s AOUT is input to RXD of UART4.
1 The alternate signal of USBH1_RXDP (PB31) is input to RXD of UART4.
24
UART4_RTS_CTL
UART4 RTS Control. When set, the alternate signal of USBH1_FS (PB26) is input to
RTS of UART4. When 0, the USBH1_RXDP (PB31) GPIO’s AOUT is input to RTS of
UART4. With either setting, the user must also ensure that the proper GPIO registers
have been programmed to select the desired multiplexing.
0 The USBH1_RXDP (PB31) GPIO’s AOUT is input to RTS of UART4.
1 The alternate signal of USBH1_FS (PB26) is input to RTS of UART4.
23–19
Reserved. These bits are reserved and should read 1.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
4-4
Freescale Semiconductor
System Control
Table 4-4. Function Multiplexing Control Register Description (continued)
Field
Description
18
KP_COL6_CTL
Keypad Column 6 Control. When set, the alternate signal of UART2_TXD (PE6) is
input to column 6 of keypad. When 0, the alternate signal of TEST_WB2 (PE0) is input
to column 6 of keypad. With either setting, the user must also ensure that the proper
GPIO registers have been programmed to select the desired multiplexing.
0 The alternate signal of TEST_WB2 (PE0) is input to column 6 of keypad.
1 The alternate signal of UART2_TXD (PE6) is input to column 6 of keypad.
17
KP_ROW7_CTL
Keypad Row 7 Control. When set, the alternate signal of UART2_RTS (PE4) is input
to row 7of keypad. When 0, the alternate signal of TEST_WB0 (PE2) is input to row 7
of keypad. With either setting, the user must also ensure that the proper GPIO registers
have been programmed to select the desired multiplexing.
0 The alternate signal of TEST_WB0 (PE2) is input to row 7 of keypad.
1 The alternate signal of UART2_RTS (PE4) is input to row 7of keypad.
16
KP_ROW6_CTL
Keypad Row 6 Control. When set, the alternate signal of UART2_RXD (PE7) is input
to row 6 of keypad. When 0, the alternate signal of TEST_WB1 (PE1) is input to row 6
of keypad. With either setting, the user must also ensure that the proper GPIO registers
have been programmed to select the desired multiplexing.
0 The alternate signal of TEST_WB1 (PE1) is input to row 6 of keypad.
1 The alternate signal of UART2_RXD (PE7) is input to row 6 of keypad.
15
Reserved. These bits are reserved and should read 1.
14
PC_WAIT_B_CTL
PC_WAIT_B Control. When set, signal pc_wait_b of PCMCIA is input from
PC_WAIT_B. When 0, it is input from BOUT of GPIO PORT C[31].
0 The signal pc_wait_b of PCMCIA is input from BOUT of GPIO PORT C[31].
1 The signal pc_wait_b of PCMCIA is input from PC_WAIT_B.
13
PC_READY_CTL
PC_READY Control. When set, signal pc_ready of PCMCIA is input from PC_READY.
When 0, it is input from BOUT of GPIO PORT C[30].
0 The signal pc_ready of PCMCIA is input from BOUT of GPIO PORT C[30].
1 The signal pc_ready of PCMCIA is input from PC_READY.
12
PC_VS1_CTL
PC_VS1 Control. When set, signal pc_vs1 of PCMCIA is input from PC_VS1. When 0,
it is input from BOUT of GPIO PORT C[29].
0 The signal pc_vs1 of PCMCIA is input from BOUT of GPIO PORT C[29].
1 The signal pc_vs1 of PCMCIA is input from PC_VS1.
11
PC_VS2_CTL
PC_VS2 Control. When set, signal pc_vs2 of PCMCIA is input from PC_VS2. When 0,
it is input from BOUT of GPIO PORT C[28].
0 The signal pc_vs2 of PCMCIA is input from BOUT of GPIO PORT C[28].
1 The signal pc_vs2 of PCMCIA is input from PC_VS2.
10
PC_BVD1_CTL
PC_BVD1 Control. When set, signal pc_bvd1 of PCMCIA is input from PC_BVD1.
When 0, it is input from BOUT of GPIO PORT C[19].
0 The signal pc_bvd1 of PCMCIA is input from BOUT of GPIO PORT C[19].
1 The signal pc_bvd1 of PCMCIA is input from PC_BVD1.
9
PC_BVD2_CTL
PC_BVD2 Control. When set, signal PC_BVD2 of PCMCIA is input from PC_BVD2.
When 0, it is input from BOUT of GPIO PORT C[18].
0 The signal pc_bvd2 of PCMCIA is input from BOUT of GPIO PORT C[18].
1 The signal pc_bvd2 of PCMCIA is input from PC_BVD2.
8
IOIS16_CTL
IOIS16 Control. When set, signal iois16 of PCMCIA is input from IOIS16. When 0, it is
input from BOUT of GPIO PORT C[17].
0 The signal iois16 of PCMCIA is input from BOUT of GPIO PORT C[17].
1 The signal iois16 of PCMCIA is input from IOIS16.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-5
System Control
Table 4-4. Function Multiplexing Control Register Description (continued)
Field
Description
7–6
Reserved. These bits are reserved and should read 1.
5
NF_FMS
Flash Memory Select. When Boot[3:0] = 0010 or 0011, the NF_FMS will be set,
otherwise it will be 0. After boot up, this bit is user programmable.
0 NAND Flash with 512B page size (64Mb/128Mb/256Mb/512Mbyte/
1Gbyte DDP)
1 NAND Flash with 2 Kbyte page size
(1Gbyte/2Gbyte DDP/2Gbyte)
Note: DDP means Double Density Package.
4
NF_16BIT_SEL
3
NAND Flash 16-bit Select. Selects 16-bit NF operation. Setting this bit forces the
NAND Flash into 16-bit operation and the NAND Flash upper data is available to the
pins. Clearing this bit forces the NF to 8-bit operation and the A[25:21]signals become
the function pins. The muxing is done in the EMI module, not I/O MUX module. During
system boot up, if the BOOT[3:0] input pins are configured to select 16-bit mode, this
NF_16BIT_SEL bit is set.
0 NAND Flash 8-bit operation
1 NAND Flash 16-bit operation
Reserved. This bit is reserved and should read 0.
2
SLCDC_SEL
SLCDC Select. Selects whether a BaseBand chip (BB) or the i.MX27 processor drives
the SLCDC display port in serial mode.
0 On Chip SLCDC drives the SLCDC port.
1 BB can write directly to the SLCDC port.
1
SDCS1_SEL
SDRAM Chip Select. Selects the function of the CS3/CSD1 pin.
0 CS3 is selected.
1 CSD1 is selected.
0
SDCS0_SEL
SDRAM Chip Select. Selects the function of the CS2/CSD0 pin.
0 CS2 is selected.
1 CSD0 is selected.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
4-6
Freescale Semiconductor
System Control
4.2.3
Global Peripheral Control Register (GPCR)
The Global Peripheral Control Register (GPCR) displays the current boot mode of the i.MX27 device. The
clock gating to the processor’s modules is also controlled by this register. Figure 4-4 shows the register and
Table 4-5 provides its field descriptions.
0x1002_7818 (GPCR)
R
Access: User R/W
31
30
29
28
27
26
25
24
23
22
21
20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
19
18
R
W
Reset
USB_ PP_ DMA_
ETM9
Burst Burst Burst
_PAD
_Over _Over _Over
_EN
ride
ride
ride
1
0
0
0
7
6
5
4
0
0
0
0
0
0
0
0
16
BOOT
W
Reset
17
0
0
0
0
3
2
1
0
CLOC
CLK_
DDR_
K_GA DDR_
DDR_
INPUT
TING_ MODE
MODE
EN
1
0
0
0
Figure 4-4. Global Peripheral Control Register (GPCR)
Table 4-5. Global Peripheral Control Register Descriptions
Field
Description
31–20
Reserved. These bits are reserved and should read 0.
19–16
BOOT
Boot Mode. These are 4-bit system boot mode for the i.MX27 device.
0000 Bootstrap from UART/USB
0001 Reserved
0010 8-bit NAND Flash (2 Kbyte per page)
0011 16-bit Nand Flash (2 Kbyte per page)
0100 16-bit Nand Flash (512 bytes per page)
0101 16-bit CS0
0110 32-bit CS0
0111 8 bit Nand Flash (512 bytes per page)
1xxx Reserved
15–12
Reserved. These bits are reserved and should read 0.
11
ETM9_PAD_EN
ETM9 Pad Enable. When this bit is set, pads for ETM9 are enabled.
0 Disable ETM9 pads
1 Enable ETM9 pads
10
USB Burst Override Control. When this bit is set, the burst type of USB will be forced to INCR8.
USB_Burst_Override 0 Bypass. The burst type will not be forced.
1 Burst type of USB is INCR8
9
PP_Burst_Override
EMMA PP Burst Override Control. When this bit is set, the burst type of EMMA PP will be forced
to INCR4 or INCR8.
0 Bypass. The burst type will not be forced.
1 Burst type of EMMA PP is INCR4 or INCR8.
8
DMA Burst Override Control. When this bit is set, the burst type of DMA will be forced to INCR4
DMA_Burst_Override or INCR8.
0 Bypass. The burst type will not be forced.
1 Burst type of DMA is INCR4 or INCR8.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-7
System Control
Table 4-5. Global Peripheral Control Register Descriptions (continued)
Field
Description
7–4
Reserved. These bits are reserved and should read 0.
3
Clock Gating Enable. When set to 1, the peripheral register access clocks are gated by the AIPI
CLOCK_GATING_EN modules. For example, when there is a register read or write access to the peripherals of AIPI1,
the ipg_clk_s1 clock will be running, otherwise if no access is taking place the clock will shut off
and when there is a register read or write access to the peripherals of AIPI2. The clock is running,
otherwise if no access is taking place the clock shuts off.
When this bit is cleared to 0 then the AIPI clocks become a continuous clock, regardless of
peripheral accesses.
It is recommended for maximum power savings to ensure this bit is set to 1.
2
DDR_MODE
1
CLK_DDR_MODE
0
DDR_INPUT
4.2.4
DDR Drive Strength Control. used to select DDR drive strength of all DDR pads except the SDCLK
pad.
0 Drive strength is selected by associated fields in the DSCRx registers.
1 Drive strength of about 20 mA, as defined in SSTL_18
CLK DDR MODE. used to select DDR drive strength of SDCLK pad.
0 Drive strength is selected by associated fields in the DSCR8 registers.
1 Drive strength of about 20 mA, as defined in SSTL_18
DDR_INPUT. Used to force input mode of DDR pads to CMOS input mode.
0 No force on input mode of DDR pads
1 DDR pads will be forced to CMOS input mode.
Well Bias System
The i.MX27 processor employs an innovative system feature to help reduce leakage current called Well
Biasing. The Well Bias System reduces the leakage current of the QVDDx sub-system during low-power
mode by increasing the threshold voltage of the QVDDx sub-system transistors. The i.MX27 contains two
Well Biasing System, one for ARM core logic and one for EMI module. The following section describes
how to enable and take advantage of this power saving feature.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
4-8
Freescale Semiconductor
System Control
4.2.5
Well Bias Control Register (WBCR)
The Well Bias Control Register (WBCR) allows the user to enable the A926P Well Biasing System and
EMI Well Biasing System. The default setting is both Well Biasing Systems are disabled. A926P Well
Biasing System can operate under both Doze mode and Sleep mode, while EMI Well Biasing System can
operate under Sleep mode only. To enable Well Biasing Systems and take advantage of this power saving
feature, CRM_WBFA or CRM_WBFA_EMI bit must be set to 1.
Figure 4-5 shows the register and Table 4-6 provides its field descriptions.
0x1002_781C (WBCR)
R
Access: User R/W
31
30
29
28
0
0
0
0
27
R
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
24
0
0
0
0
CRM_SPA
W
Reset
25
CRM_SPA_EMI
W
Reset
26
0
0
0
0
23
22
21
20
0
0
0
0
0
0
0
0
0
0
0
0
3
2
1
0
7
6
5
4
0
0
0
0
0
0
0
0
19
18
17
16
CRM_WBFA CRM_WBM_
_EMI
EMI
CRM_WBFA
0
0
CRM_WBM
0
0
Figure 4-5. Well Bias Control Register (WBCR)
Table 4-6. Well Bias Control Register Field Descriptions
Field
31–28
Description
Reserved. These bits are reserved and should read 0.
27–26
CRM_SPA_EMI
EMI PWELL Set Point Adjust. Describe the configuration of the EMI PWELL bias circuit’s set point or
regulation level.
00 Minimum Back Bias applied to the Pwells.
01 Decreased Back Bias applied to the Pwells.
10 Moderate Back Bias applied to the Pwells.
11 Increased Back Bias applied to the Pwells.
25–24
CRM_SPA_EMI
EMI NWELL Set Point Adjust. Describe the configuration of the EMI NWELL bias circuit’s set point or
regulation level.
00 Minimum Back Bias applied to the Nwells.
01 Decreased Back Bias applied to the Nwells.
10 Moderate Back Bias applied to the Nwells.
11 Increased Back Bias applied to the Nwells.
23–20
19
CRM_WBFA_EMI
Reserved. These bits are reserved and should read 0.
Well Bias Frequency Adjust. For optimal power savings, the user should set this bit to 1 when EMI Well
Bias is enabled.
0 Standard
1 Adjusted Suggested setting for optimal power savings when Well Bias is enabled.
Note: This bit has no effect when Well Bias is disabled.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-9
System Control
Table 4-6. Well Bias Control Register Field Descriptions (continued)
Field
Description
18–16
CRM_WBM_EMI
CRM_WBM. Enables or disables EMI Well Bias System during Sleep mode. To enable Well Bias during
Sleep mode, these bits must be set to 001. To disable Well Bias, these bits must be set to 000. All other
bit settings are reserved.
000 Well Bias not applied
001 Well Bias @ Sleep
010–111Well Bias not applied
15–12
Reserved. These bits are reserved and should read 0.
11–10
CRM_SPA
A926P PWELL Set Point Adjust. Describes the configuration of the A926P PWELL bias circuit’s set point
or regulation level.
00 Minimum Back Bias applied to the Pwells.
01 Decreased Back Bias applied to the Pwells.
10 Moderate Back Bias applied to the Pwells.
11 Increased Back Bias applied to the Pwells.
9–8
CRM_SPA
A926P NWELL Set Point Adjust. Describe the configuration of the A926P Nwell bias circuit’s set point or
regulation level.
00 Minimum Back Bias applied to the Nwells.
01 Decreased Back Bias applied to the Nwells.
10 Moderate Back Bias applied to the Nwells.
11 Increased Back Bias applied to the Nwells.
7–4
Reserved. These bits are reserved and should read 0.
3
CRM_WBFA
Well Bias Frequency Adjust. For optimal power savings, the user should set this bit to 1 when A926P Well
Bias is enabled.
0 Standard.
1 Adjusted Suggested setting for optimal power savings when Well Bias is enabled
This bit has no effect when Well Bias is disabled.
2–0
CRM_WBM
CRM_WBM. Controls when the A926P well bias will be applied.Enables or disables Well Bias System
during Sleep mode. To enable Well Bias during Sleep mode, these bits must be set to 001. To disable
Well Bias, these bits must be set to 000. All other bit settings are reserved.
000 Well Bias not applied
001 Well Bias @ Sleep
010 Well Bias @ Sleep and DOZE
100–111Well Bias not applied
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
4-10
Freescale Semiconductor
System Control
4.2.6
Drive Strength Control Register 1 (DSCR1)
The Drive Strength Control Register 1 (DSCR1) controls the driving force parameters of all slow I/O
signals in the i.MX27 device. Figure 4-6 shows the register and Table 4-7 provides its field descriptions.
0x1002_7820 (DSCR1)
R
Access: User R/W
31
30
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
Reset
R
W
Reset
DS_SLOW8
0
DS_SLOW7
0
0
0
DS_SLOW6
0
0
DS_SLOW5
0
0
DS_SLOW4
0
0
21
20
DS_SLOW11
DS_SLOW3
0
19
18
DS_SLOW10
DS_SLOW2
0
0
0
17
16
DS_SLOW9
DS_SLOW1
0
0
Figure 4-6. Drive Strength Control Register (DSCR1)
Table 4-7. Drive Strength Control Register 1 Field Description
Field
Description
31–22
Reserved. These bits are reserved and should read 0.
21–20
DS_SLOW11
Drive Strength Slow I/O. Controls the driving strength of slow I/O group 11. (DVS_PMIC)
00 Normal
01 High
10 Max high
11 Max high
19–18
DS_SLOW10
Drive Strength Slow I/O. Controls the driving strength of slow I/O group 10. (SDHC1 and CSPI3)
00 Normal
01 High
10 Max high
11 Max high
17–16
DS_SLOW9
Drive Strength Slow I/O. Controls the driving strength of slow I/O group 9. (JTAG)
00 Normal
01 High
10 Max high
11 Max high
15–14
DS_SLOW8
Drive Strength Slow I/O. Controls the driving strength of slow I/O group 8. (PWM, KPP, UART1,
UART2, UART3, and RESET_OUT_B)
00 Normal
01 High
10 Max high
11 Max high
13–12
DS_SLOW7
Drive Strength Slow I/O. Controls the driving strength of slow I/O group 7. (CSPI1 and CSPI2)
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-11
System Control
Table 4-7. Drive Strength Control Register 1 Field Description (continued)
Field
Description
11–10
DS_SLOW6
Drive Strength Slow I/O. Controls the driving strength of slow I/O group 6. (SSI1, SSI2, SAP, SSI3,
GPT4, and GPT5)
00 Normal
01 High
10 Max high
11 Max high
9–8
DS_SLOW5
Drive Strength Slow I/O. Controls the driving strength of slow I/O group 5. (GPT1, I2C1, and I2C2)
00 Normal
01 High
10 Max high
11 Max high
7–6
DS_SLOW4
Drive Strength Slow I/O. Controls the driving strength of slow I/O group 4. (USBH1, UART4, and
USBG)
00 Normal
01 High
10 Max high
11 Max high
5–4
DS_SLOW3
Drive Strength Slow I/O. Controls the driving strength of slow I/O group 3. (CSI, UART5, and
UART6)
00 Normal
01 High
10 Max high
11 Max high
3–2
DS_SLOW2
Drive Strength Slow I/O. Controls the driving strength of slow I/O group 2.(SDHC2 and MSHC)
00 Normal
01 High
10 Max high
11 Max high
1–0
DS_SLOW1
Drive Strength Slow I/O. Controls the driving strength of slow I/O group 1. (LCDC)
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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System Control
4.2.7
Drive Strength Control Register 2 (DSCR2)
The Drive Strength Control Register 2 (DSCR2) controls the driving force parameters of the fast I/O
signals in the i.MX27 processor. Figure 4-7 shows the register and Table 4-8 provides its field descriptions.
0x1002_7824 (DSCR2)
31
R
W
Reset
R
W
Reset
30
29
Access: User R/W
28
27
26
25
24
23
22
21
20
19
18
DS_FAST16 DS_FAST15 DS_FAST14 DS_FAST13 DS_FAST12 DS_FAST11 DS_FAST10
17
16
DS_FAST9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DS_FAST8
0
DS_FAST7
0
0
0
DS_FAST6
0
0
DS_FAST5
0
0
DS_FAST4
0
0
DS_FAST3
0
DS_FAST2
0
0
0
DS_FAST1
0
0
Figure 4-7. Drive Strength Control Register 2 (DSCR2)
Table 4-8. Drive Strength Control Register 2 Field Descriptions
Field
Description
31–30
DS_FAST16
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 16 (D15).
00 Normal
01 High
10 Max high
11 Max high
29–28
DS_FAST15
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 15 (D14).
00 Normal
01 High
10 Max high
11 Max high
27–26
DS_FAST14
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 14 (D13).
00 Normal
01 High
10 Max high
11 Max high
25–24
DS_FAST13
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 13 (D12).
00 Normal
01 High
10 Max high
11 Max high
23–22
DS_FAST12
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 12 (D11).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-13
System Control
Table 4-8. Drive Strength Control Register 2 Field Descriptions (continued)
Field
Description
21–20
DS_FAST11
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 11(D10).
00 Normal
01 High
10 Max high
11 Max high
19–18
DS_FAST10
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 10 (D9).
00 Normal
01 High
10 Max high
11 Max high
17–16
DS_FAST9
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 9 (D8).
00 Normal
01 High
10 Max high
11 Max high
15–14
DS_FAST8
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 8 (D7).
00 Normal
01 High
10 Max high
11 Max high
13–12
DS_FAST7
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 7 (D6).
00 Normal
01 High
10 Max high
11 Max high
11–10
DS_FAST6
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 6 (D5).
00 Normal
01 High
10 Max high
11 Max high
9–8
DS_FAST5
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 5 (D4).
00 Normal
01 High
10 Max high
11 Max high
7–6
DS_FAST4
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 4 (D3).
00 Normal
01 High
10 Max high
11 Max high
5–4
DS_FAST3
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 3 (D2).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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Freescale Semiconductor
System Control
Table 4-8. Drive Strength Control Register 2 Field Descriptions (continued)
Field
4.2.8
Description
3–2
DS_FAST2
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 2 (D1).
00 Normal
01 High
10 Max high
11 Max high
1–0
DS_FAST1
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 1 (D0).
00 Normal
01 High
10 Max high
11 Max high
Drive Strength Control Register 3
The Drive Strength Control Register 3 (DSCR3) controls the driving force parameters of the fast I/O
signals in the i.MX27. Figure 4-8 shows the register and Table 4-9 provides its field descriptions.
0x1002_7828 (DSCR3)
31
R
W
W
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DS_FAST32 DS_FAST31 DS_FAST30 DS_FAST29 DS_FAST28 DS_FAST27 DS_FAST26 DS_FAST25
Reset
R
30
Access: User R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DS_FAST24 DS_FAST23 DS_FAST22 DS_FAST21 DS_FAST20 DS_FAST19 DS_FAST18 DS_FAST17
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-8. Drive Strength Control Register 3 (DSCR3)
Table 4-9. Drive Strength Control Register 3 Field Descriptions
Field
Description
31–30
DS_FAST32
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 32 (A15).
00 Normal
01 High
10 Max high
11 Max high
29–28
DS_FAST31
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 31 (A14).
00 Normal
01 High
10 Max high
11 Max high
27–26
DS_FAST30
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 30 (A13).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-15
System Control
Table 4-9. Drive Strength Control Register 3 Field Descriptions (continued)
Field
Description
25–24
DS_FAST29
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 29 (A12).
00 Normal
01 High
10 Max high
11 Max high
23–22
DS_FAST28
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 28 (A11).
00 Normal
01 High
10 Max high
11 Max high
21–20
DS_FAST27
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 27 (A10).
00 Normal
01 High
10 Max high
11 Max high
19–18
DS_FAST26
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 26 (A9).
00 Normal
01 High
10 Max high
11 Max high
17–16
DS_FAST25
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 25 (A8).
00 Normal
01 High
10 Max high
11 Max high
15–14
DS_FAST24
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 24 (A7).
00 Normal
01 High
10 Max high
11 Max high
13–12
DS_FAST23
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 23 (A6).
00 Normal
01 High
10 Max high
11 Max high
11–10
DS_FAST22
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 22 (A5).
00 Normal
01 High
10 Max high
11 Max high
9–8
DS_FAST21
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 21 (A4).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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Freescale Semiconductor
System Control
Table 4-9. Drive Strength Control Register 3 Field Descriptions (continued)
Field
Description
7–6
DS_FAST20
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 20 (A3).
00 Normal
01 High
10 Max high
11 Max high
5–4
DS_FAST19
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 19 (A2).
00 Normal
01 High
10 Max high
11 Max high
3–2
DS_FAST18
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 18 (A1).
00 Normal
01 High
10 Max high
11 Max high
1–0
DS_FAST17
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 17 (A0).
00 Normal
01 High
10 Max high
11 Max high
4.2.9
Drive Strength Control Register 4
The Drive Strength Control Register 4 (DSCR4) controls the driving force parameters of the fast I/O
signals in the i.MX27 device. Figure 4-9 shows the register and Table 4-10 provides its field descriptions.
0x1002_782C (DSCR4)
R
Access: User R/W
31
30
29
28
27
26
25
24
23
22
21
20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
Reset
R
W
Reset
19
18
17
16
DS_FAST42 DS_FAST41
DS_FAST40 DS_FAST39 DS_FAST38 DS_FAST37 DS_FAST36 DS_FAST35 DS_FAST34 DS_FAST33
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-9. Drive Strength Control Register 4 (DSCR4)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-17
System Control
Table 4-10. Drive Strength Control Register 4 Field Descriptions
Field
Description
31–20
Reserved. These bits are reserved and should read 0.
19–18
DS_FAST42
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 42 (A25).
00 Normal
01 High
10 Max high
11 Max high
17–16
DS_FAST41
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 41 (A24).
00 Normal
01 High
10 Max high
11 Max high
15–14
DS_FAST40
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 40 (A23).
00 Normal
01 High
10 Max high
11 Max high
13–12
DS_FAST39
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 39 (A22).
00 Normal
01 High
10 Max high
11 Max high
11–10
DS_FAST38
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 38 (A21).
00 Normal
01 High
10 Max high
11 Max high
9–8
DS_FAST37
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 37 (A20).
00 Normal
01 High
10 Max high
11 Max high
7–6
DS_FAST36
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 36 (A19).
00 Normal
01 High
10 Max high
11 Max high
5–4
DS_FAST35
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 35 (A18).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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Freescale Semiconductor
System Control
Table 4-10. Drive Strength Control Register 4 Field Descriptions (continued)
Field
Description
3–2
DS_FAST34
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 34 (A17).
00 Normal
01 High
10 Max high
11 Max high
1–0
DS_FAST33
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 33 (A16).
00 Normal
01 High
10 Max high
11 Max high
4.2.10
Drive Strength Control Register 5
The Drive Strength Control Register 5 (DSCR5) controls the driving force parameters of the fast I/O
signals in the i.MX27 processor. Figure 4-10 shows the register and Table 4-11 provides its field
descriptions.
0x1002_7830 (DSCR5)
31
R
W
Reset
R
W
Reset
30
29
Access: User read/write
28
27
26
25
24
23
22
21
20
19
18
17
16
DS_FAST64 DS_FAST63 DS_FAST62 DS_FAST61 DS_FAST60 DS_FAST59 DS_FAST58 DS_FAST57
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DS_FAST56 DS_FAST55 DS_FAST54 DS_FAST53 DS_FAST52 DS_FAST51 DS_FAST50 DS_FAST49
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-10. Drive Strength Control Register 5 (DSCR5)
Table 4-11. Drive Strength Control Register 5 Field Descriptions
Field
Description
31–30
DS_FAST64
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 64 (SD15).
00 Normal
01 High
10 Max high
11 Max high
29–28
DS_FAST63
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 63 (SD14).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-19
System Control
Table 4-11. Drive Strength Control Register 5 Field Descriptions (continued)
Field
Description
27–26
DS_FAST62
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 62 (SD13).
00 Normal
01 High
10 Max high
11 Max high
25–24
DS_FAST61
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 61 (SD12).
00 Normal
01 High
10 Max high
11 Max high
23–22
DS_FAST60
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 60 (SD11).
00 Normal
01 High
10 Max high
11 Max high
21–20
DS_FAST59
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 59 (SD10).
00 Normal
01 High
10 Max high
11 Max high
19–18
DS_FAST58
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 58 (SD9).
00 Normal
01 High
10 Max high
11 Max high
17–16
DS_FAST57
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 57 (SD8).
00 Normal
01 High
10 Max high
11 Max high
15–14
DS_FAST56
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 56 (SD7).
00 Normal
01 High
10 Max high
11 Max high
13–12
DS_FAST55
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 55 (SD6).
00 Normal
01 High
10 Max high
11 Max high
11–10
DS_FAST54
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 54 (SD5).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
4-20
Freescale Semiconductor
System Control
Table 4-11. Drive Strength Control Register 5 Field Descriptions (continued)
Field
Description
9–8
DS_FAST53
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 53 (SD4).
00 Normal
01 High
10 Max high
11 Max high
7–6
DS_FAST52
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 52 (SD3).
00 Normal
01 High
10 Max high
11 Max high
5–4
DS_FAST51
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 51 (SD2).
00 Normal
01 High
10 Max high
11 Max high
3–2
DS_FAST50
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 50 (SD1).
00 Normal
01 High
10 Max high
11 Max high
1–0
DS_FAST49
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 49 (SD0).
00 Normal
01 High
10 Max high
11 Max high
4.2.11
Drive Strength Control Register 6
The Drive Strength Control Register 6 (DSCR6) controls the driving force parameters of the fast I/O
signals in the i.MX27 device. Figure 4-11 shows the register and Table 4-12 provides its field descriptions.
0x1002_7834 (DSCR6)
31
R
W
Reset
R
W
Reset
30
29
Access: User R/W
28
27
26
25
24
23
22
21
20
19
18
17
16
DS_FAST80 DS_FAST79 DS_FAST78 DS_FAST77 DS_FAST76 DS_FAST75 DS_FAST74 DS_FAST73
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DS_FAST72 DS_FAST71 DS_FAST70 DS_FAST69 DS_FAST68 DS_FAST67 DS_FAST66 DS_FAST65
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-11. Drive Strength Control Register 6 (DSCR6)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-21
System Control
Table 4-12. Drive Strength Control Register 6 Field Descriptions
Field
Description
31–30
DS_FAST80
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 80 (SD31).
00 Normal
01 High
10 Max high
11 Max high
29–28
DS_FAST79
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 79 (SD30).
00 Normal
01 High
10 Max high
11 Max high
27–26
DS_FAST78
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 78 (SD29).
00 Normal
01 High
10 Max high
11 Max high
25–24
DS_FAST77
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 77 (SD28).
00 Normal
01 High
10 Max high
11 Max high
23–22
DS_FAST7
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 76 (SD27).
00 Normal
01 High
10 Max high
11 Max high
21–20
DS_FAST75
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 75 (SD26).
00 Normal
01 High
10 Max high
11 Max high
19–18
DS_FAST74
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 74 (SD25).
00 Normal
01 High
10 Max high
11 Max high
17–16
DS_FAST73
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 73 (SD24).
00 Normal
01 High
10 Max high
11 Max high
15–14
DS_FAST72
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 72 (SD23).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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Freescale Semiconductor
System Control
Table 4-12. Drive Strength Control Register 6 Field Descriptions (continued)
Field
Description
13–12
DS_FAST71
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 71 (SD22).
00 Normal
01 High
10 Max high
11 Max high
11–10
DS_FAST70
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 70 (SD21).
00 Normal
01 High
10 Max high
11 Max high
9–8
DS_FAST69
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 69 (SD20).
00 Normal
01 High
10 Max high
11 Max high
7–6
DS_FAST68
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 68 (SD19).
00 Normal
01 High
10 Max high
11 Max high
5–4
DS_FAST67
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 67 (SD18).
00 Normal
01 High
10 Max high
11 Max high
3–2
DS_FAST66
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 66 (SD17).
00 Normal
01 High
10 Max high
11 Max high
1–0
DS_FAST65
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 65 (SD16).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-23
System Control
4.2.12
Drive Strength Control Register 7
The Drive Strength Control Register 7 (DSCR7) controls the driving force parameters of the fast I/O
signals in the i.MX27 processor. Figure 4-12 shows the register and Table 4-13 provides its field
descriptions.
0x1002_7838 (DSCR7)
R
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
Reset
R
W
Reset
29
Access: User R/W
28
27
26
25
24
23
22
21
20
19
18
17
16
DS_FAST95 DS_FAST94 DS_FAST93 DS_FAST92 DS_FAST91 DS_FAST90 DS_FAST89
DS_FAST88 DS_FAST87 DS_FAST86 DS_FAST85 DS_FAST84 DS_FAST83 DS_FAST82 DS_FAST81
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-12. Drive Strength Control Register 7 (DSCR7)
Table 4-13. Drive Strength Control Register 7 Field Descriptions
Field
Description
31–30
Reserved. These bits are reserved and should read 0.
29–28
DS_FAST95
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 95 (RW_B).
00 Normal
01 High
10 Max high
11 Max high
27–26
DS_FAST94
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 94 (BCLK).
00 Normal
01 High
10 Max high
11 Max high
25–24
DS_FAST93
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 93 (LBA_B).
00 Normal
01 High
10 Max high
11 Max high
23–22
DS_FAST92
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 92 (OE_B).
00 Normal
01 High
10 Max high
11 Max high
21–20
DS_FAST91
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 91 (ECB_B).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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Freescale Semiconductor
System Control
Table 4-13. Drive Strength Control Register 7 Field Descriptions (continued)
Field
Description
19–18
DS_FAST90
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 90 (CS5_B).
00 Normal
01 High
10 Max high
11 Max high
17–16
DS_FAST89
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 89 (CS4_B).
00 Normal
01 High
10 Max high
11 Max high
15–14
DS_FAST88
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 88 (CS3_B).
00 Normal
01 High
10 Max high
11 Max high
13–12
DS_FAST87
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 87 (CS2_B).
00 Normal
01 High
10 Max high
11 Max high
11–10
DS_FAST86
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 86 (CS1_B).
00 Normal
01 High
10 Max high
11 Max high
9–8
DS_FAST85
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 85 (CS0_B).
00 Normal
01 High
10 Max high
11 Max high
7–6
DS_FAST84
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 84 (EB1_B).
00 Normal
01 High
10 Max high
11 Max high
5–4
DS_FAST83
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 83 (EB0_B).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-25
System Control
Table 4-13. Drive Strength Control Register 7 Field Descriptions (continued)
4.2.13
Field
Description
3–2
DS_FAST82
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 82 (SDBA1).
00 Normal
01 High
10 Max high
11 Max high
1–0
DS_FAST81
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 81 (SDBA0).
00 Normal
01 High
10 Max high
11 Max high
Drive Strength Control Register 8
The Drive Strength Control Register 8 (DSCR8) controls the driving force parameters of the fast I/O
signals in the i.MX27 device. Figure 4-13 shows the register and Table 4-14 provides its field descriptions.
0x1002_783C (DSCR8)
R
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
Reset
29
Access: User R/W
28
27
26
25
24
23
22
21
20
0
18
17
16
DS_FAST111 DS_FAST110 DS_FAST109 DS_FAST108 DS_FAST107 DS_FAST106 DS_FAST105
R DS_FAST10
DS_FAST103 DS_FAST102 DS_FAST101 DS_FAST100 DS_FAST99
4
W
Reset
19
0
0
0
0
0
0
0
0
0
0
DS_FAST98
0
0
DS_FAST97
0
0
0
Figure 4-13. Drive Strength Control Register 8 (DSCR8)
Table 4-14. Drive Strength Control Register 8 Field Descriptions
Field
Description
31–30
Reserved. These bits are reserved and should read 0.
29–28
DS_FAST111
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 111 (SDQS3).
00 Normal
01 High
10 Max high
11 Max high
27–26
DS_FAST110
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 110 (SDQS2).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
4-26
Freescale Semiconductor
System Control
Table 4-14. Drive Strength Control Register 8 Field Descriptions (continued)
Field
Description
25–24
DS_FAST109
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 109 (SDQS1).
00 Normal
01 High
10 Max high
11 Max high
23–22
DS_FAST108
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 108 (SDQS0).
00 Normal
01 High
10 Max high
11 Max high
21–20
DS_FAST107
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 107 (SDCLK).
00 Normal
01 High
10 Max high
11 Max high
19–18
DS_FAST106
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 106 (SDCKE1).
00 Normal
01 High
10 Max high
11 Max high
17–16
DS_FAST105
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 105 (SDCKE0).
00 Normal
01 High
10 Max high
11 Max high
15–14
DS_FAST104
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 104 (SDWE_B).
00 Normal
01 High
10 Max high
11 Max high
13–12
DS_FAST103
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 103 (CAS_B).
00 Normal
01 High
10 Max high
11 Max high
11–10
DS_FAST102
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 102 (RAS_B).
00 Normal
01 High
10 Max high
11 Max high
9–8
DS_FAST101
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 101 (MA10).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-27
System Control
Table 4-14. Drive Strength Control Register 8 Field Descriptions (continued)
Field
4.2.14
Description
7–6
DS_FAST100
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 100 (DQM3).
00 Normal
01 High
10 Max high
11 Max high
5–4
DS_FAST99
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 99 (DQM2).
00 Normal
01 High
10 Max high
11 Max high
3–2
DS_FAST98
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 98 (DQM1).
00 Normal
01 High
10 Max high
11 Max high
1–0
DS_FAST97
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 97 (DQM0).
00 Normal
01 High
10 Max high
11 Max high
Drive Strength Control Register 9
The Drive Strength Control Register 9 (DSCR9) controls the driving force parameters of the fast I/O
signals in the i.MX27 device. Figure 4-14 shows the register and Table 4-15 provides its field descriptions.
0x1002_7840 (DSCR9)
R
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
Reset
R
W
Reset
29
Access: User R/W
28
27
26
25
24
23
22
21
20
19
18
17
16
DS_FAST127 DS_FAST126 DS_FAST125 DS_FAST124 DS_FAST123 DS_FAST122 DS_FAST121
DS_FAST120 DS_FAST119 DS_FAST118 DS_FAST117 DS_FAST116 DS_FAST115 DS_FAST114 DS_FAST113
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-14. Drive Strength Control Register 9 (DSCR9)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
4-28
Freescale Semiconductor
System Control
Table 4-15. Drive Strength Control Register 9 Field Descriptions
Field
31–30
Description
Reserved. These bits are reserved and should read 0.
29–28
DS_FAST127
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 127 (M_REQUEST).
00 Normal
01 High
10 Max high
11 Max high
27–26
DS_FAST126
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 126 (M_GRANT).
00 Normal
01 High
10 Max high
11 Max high
25–24
DS_FAST125
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 125 (IOIS16).
00 Normal
01 High
10 Max high
11 Max high
23–22
DS_FAST124
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 124 (PC_POE).
00 Normal
01 High
10 Max high
11 Max high
21–20
DS_FAST123
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 123 (PC_RW_B).
00 Normal
01 High
10 Max high
11 Max high
19–18
DS_FAST122
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 122 (PC_RST).
00 Normal
01 High
10 Max high
11 Max high
17–16
DS_FAST121
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 121 (PC_BVD2).
00 Normal
01 High
10 Max high
11 Max high
15–14
DS_FAST120
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 120 (PC_BVD1).
00 Normal
01 High
10 Max high
11 Max high
13–12
DS_FAST119
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 119 (PC_VS2).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-29
System Control
Table 4-15. Drive Strength Control Register 9 Field Descriptions (continued)
Field
Description
11–10
DS_FAST118
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 118 (PC_VS1).
00 Normal
01 High
10 Max high
11 Max high
9–8
DS_FAST117
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 117 (PC_PWRON).
00 Normal
01 High
10 Max high
11 Max high
7–6
DS_FAST116
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 116 (PC_READY).
00 Normal
01 High
10 Max high
11 Max high
5–4
DS_FAST115
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 115 (PC_WAIT_B).
00 Normal
01 High
10 Max high
11 Max high
3–2
DS_FAST114
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 114 (PC_CD2_B).
00 Normal
01 High
10 Max high
11 Max high
1–0
DS_FAST113
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 113 (PC_CD1_B).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
4-30
Freescale Semiconductor
System Control
4.2.15
Drive Strength Control Register 10
The Drive Strength Control Register 10 (DSCR10) controls the driving force parameters of the fast I/O
signals in the i.MX27 device. Figure 4-15 shows the register and Table 4-16 provides its field descriptions.
0x1002_7844 (DSCR10)
R
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
Reset
R
W
Reset
29
Access: User R/W
28
27
26
25
24
23
22
21
20
19
18
17
16
DS_FAST143 DS_FAST142 DS_FAST141 DS_FAST140 DS_FAST139 DS_FAST138 DS_FAST137
DS_FAST136 DS_FAST135 DS_FAST134 DS_FAST133 DS_FAST132 DS_FAST131 DS_FAST130 DS_FAST129
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-15. Drive Strength Control Register 10 (DSCR10)
Table 4-16. Drive Strength Control Register 10 Field Descriptions
Field
Description
31–30
Reserved. These bits are reserved and should read 0.
29–28
DS_FAST143
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 143 (SD3_CMD).
00 Normal
01 High
10 Max high
11 Max high
27–26
DS_FAST142
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 142 (SD3_CLK).
00 Normal
01 High
10 Max high
11 Max high
25–24
DS_FAST141
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 141 (SD2_CLK).
00 Normal
01 High
10 Max high
11 Max high
23–22
DS_FAST140
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 140 (LSCLK).
00 Normal
01 High
10 Max high
11 Max high
21–20
DS_FAST139
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 139 (CSI_MCLK).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-31
System Control
Table 4-16. Drive Strength Control Register 10 Field Descriptions (continued)
Field
Description
19–18
DS_FAST138
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 138 (CSI_PIXCLK).
00 Normal
01 High
10 Max high
11 Max high
17–16
DS_FAST137
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 137 (CLKO).
00 Normal
01 High
10 Max high
11 Max high
15–14
DS_FAST136
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 136.
00 Normal
01 High
10 Max high
11 Max high
13–12
DS_FAST135
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 135 (NFWE_B).
00 Normal
01 High
10 Max high
11 Max high
11–10
DS_FAST134
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 134 (NFRE_B).
00 Normal
01 High
10 Max high
11 Max high
9–8
DS_FAST133
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 133 (NFALE).
00 Normal
01 High
10 Max high
11 Max high
7–6
DS_FAST132
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 132 (NFCLE).
00 Normal
01 High
10 Max high
11 Max high
5–4
DS_FAST131
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 131 (NFWP_B).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
4-32
Freescale Semiconductor
System Control
Table 4-16. Drive Strength Control Register 10 Field Descriptions (continued)
Field
4.2.16
Description
3–2
DS_FAST130
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 130 (NFCE_B).
00 Normal
01 High
10 Max high
11 Max high
1–0
DS_FAST129
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 129 (NFRB).
00 Normal
01 High
10 Max high
11 Max high
Drive Strength Control Register 11
The Drive Strength Control Register 11 (DSCR11) controls the driving force parameters of the fast I/O
signals in the i.MX27 device. Figure 4-16 shows the register and Table 4-17 provides its field descriptions.
0x1002_7848 (DSCR11)
31
R
W
Reset
R
W
Reset
30
29
Access: User R/W
28
27
26
25
24
23
22
21
20
19
18
17
16
DS_FAST160 DS_FAST159 DS_FAST158 DS_FAST157 DS_FAST156 DS_FAST155 DS_FAST154 DS_FAST153
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DS_FAST152 DS_FAST151 DS_FAST150 DS_FAST149 DS_FAST148 DS_FAST147 DS_FAST146 DS_FAST145
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-16. Drive Strength Control Register 11 (DSCR11)
Table 4-17. Drive Strength Control Register 11 Field Descriptions
Field
Description
31–30
DS_FAST160
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 160 (ATA_DATA15).
00 Normal
01 High
10 Max high
11 Max high
29–28
DS_FAST159
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 159 (ATA_DATA14).
00 Normal
01 High
10 Max high
11 Max high
27–26
DS_FAST158
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 158 (ATA_DATA13).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-33
System Control
Table 4-17. Drive Strength Control Register 11 Field Descriptions (continued)
Field
Description
25–24
DS_FAST157
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 157 (ATA_DATA12).
00 Normal
01 High
10 Max high
11 Max high
23–22
DS_FAST156
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 156 (ATA_DATA11).
00 Normal
01 High
10 Max high
11 Max high
21–20
DS_FAST155
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 155 (ATA_DATA10).
00 Normal
01 High
10 Max high
11 Max high
19–18
DS_FAST154
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 154 (ATA_DATA9).
00 Normal
01 High
10 Max high
11 Max high
17–16
DS_FAST153
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 153 (ATA_DATA8).
00 Normal
01 High
10 Max high
11 Max high
15–14
DS_FAST152
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 152 (ATA_DATA7).
00 Normal
01 High
10 Max high
11 Max high
13–12
DS_FAST151
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 151 (ATA_DATA6).
00 Normal
01 High
10 Max high
11 Max high
11–10
DS_FAST150
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 150 (ATA_DATA5).
00 Normal
01 High
10 Max high
11 Max high
9–8
DS_FAST149
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 149 (ATA_DATA4).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
4-34
Freescale Semiconductor
System Control
Table 4-17. Drive Strength Control Register 11 Field Descriptions (continued)
Field
Description
7–6
DS_FAST148
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 148 (ATA_DATA3).
00 Normal
01 High
10 Max high
11 Max high
5–4
DS_FAST147
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 147 (ATA_DATA2).
00 Normal
01 High
10 Max high
11 Max high
3–2
DS_FAST146
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 146 (ATA_DATA1).
00 Normal
01 High
10 Max high
11 Max high
1–0
DS_FAST145
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 145 (ATA_DATA0).
00 Normal
01 High
10 Max high
11 Max high
4.2.17
Drive Strength Control Register 12
The Drive Strength Control Register 12 (DSCR12) controls the driving force parameters of the fast I/O
signals in the i.MX27 device. Figure 4-17 shows the register and Table 4-18 provides its field descriptions.
0x1002_784C (DSCR12)
R
Access: User R/W
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
Reset
23
22
21
20
19
18
17
16
DS_FAST172 DS_FAST171 DS_FAST170 DS_FAST169
R DS_FAST DS_FAST DS_FAST DS_FAST
DS_FAST164 DS_FAST163 DS_FAST162 DS_FAST161
168
167
166
165
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-17. Drive Strength Control Register 12 (DSCR12)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-35
System Control
Table 4-18. Drive Strength Control Register 12 Field Descriptions
Field
31–24
Description
Reserved. These bits are reserved and should read 0.
23–22
DS_FAST172
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 172 (USBOTG_CLK).
00 Normal
01 High
10 Max high
11 Max high
21–20
DS_FAST171
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 171 (USBOTG_NXT).
00 Normal
01 High
10 Max high
11 Max high
19–18
DS_FAST170
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 170 (USBOTG_STP).
00 Normal
01 High
10 Max high
11 Max high
17–16
DS_FAST169
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 169 (USBOTG_DIR).
00 Normal
01 High
10 Max high
11 Max high
15–14
DS_FAST168
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 168 (USBOTG_DATA7).
00 Normal
01 High
10 Max high
11 Max high
13–12
DS_FAST167
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 167 (USBOTG_DATA6).
00 Normal
01 High
10 Max high
11 Max high
11–10
DS_FAST166
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 166 (USBOTG_DATA5).
00 Normal
01 High
10 Max high
11 Max high
9–8
DS_FAST165
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 165 (USBOTG_DATA4).
00 Normal
01 High
10 Max high
11 Max high
7–6
DS_FAST164
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 164 (USBOTG_DATA3).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
4-36
Freescale Semiconductor
System Control
Table 4-18. Drive Strength Control Register 12 Field Descriptions (continued)
Field
Description
5–4
DS_FAST163
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 163 (USBOTG_DATA2).
00 Normal
01 High
10 Max high
11 Max high
3–2
DS_FAST162
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 162 (USBOTG_DATA1).
00 Normal
01 High
10 Max high
11 Max high
1–0
DS_FAST161
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 161 (USBOTG_DATA0).
00 Normal
01 High
10 Max high
11 Max high
4.2.18
Drive Strength Control Register 13
The Drive Strength Control Register 13 (DSCR13) controls the driving force parameters of the fast I/O
signals in the i.MX27 device. Figure 4-18 shows the register and Table 4-19 provides its field descriptions.
0x1002_7850 (DSCR13)
R
Access: User R/W
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
Reset
R
W
Reset
23
22
21
20
19
18
17
16
DS_FAST188 DS_FAST187 DS_FAST186 DS_FAST185
DS_FAST184 DS_FAST183 DS_FAST182 DS_FAST181 DS_FAST180 DS_FAST179 DS_FAST178 DS_FAST177
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-18. Drive Strength Control Register 13 (DSCR13)
Table 4-19. Drive Strength Control Register 13 Field Descriptions
Field
Description
31–24
Reserved. These bits are reserved and should read 0.
23–22
DS_FAST188
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 188 (USBH2_CLK).
00 Normal
01 High
10 Max high
11 Max high
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-37
System Control
Table 4-19. Drive Strength Control Register 13 Field Descriptions (continued)
Field
Description
21–20
DS_FAST187
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 187 (USBH2_DIR).
00 Normal
01 High
10 Max high
11 Max high
19–18
DS_FAST186
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 186 (USBH2_NXT).
00 Normal
01 High
10 Max high
11 Max high
17–16
DS_FAST185
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 185 (USBH2_STP).
00 Normal
01 High
10 Max high
11 Max high
15–14
DS_FAST184
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 184 (USBH2_DATA7).
00 Normal
01 High
10 Max high
11 Max high
13–12
DS_FAST183
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 183 (USBH2_DATA6).
00 Normal
01 High
10 Max high
11 Max high
11–10
DS_FAST182
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 182 (USBH2_DATA5).
00 Normal
01 High
10 Max high
11 Max high
9–8
DS_FAST181
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 181 (USBH2_DATA4).
00 Normal
01 High
10 Max high
11 Max high
7–6
DS_FAST180
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 180.(USBH2_DATA3)
00 Normal
01 High
10 Max high
11 Max high
5–4
DS_FAST179
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 179 (USBH2_DATA2)
00 Normal
01 High
10 Max high
11 Max high
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System Control
Table 4-19. Drive Strength Control Register 13 Field Descriptions (continued)
Field
Description
3–2
DS_FAST178
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 178 (USBH2_DATA1)
00 Normal
01 High
10 Max high
11 Max high
1–0
DS_FAST177
Drive Strength Fast I/O. Controls the driving strength of fast I/O group 177 (USBH2_DATA0)
00 Normal
01 High
10 Max high
11 Max high
4.2.19
Pull Strength Control Register (PSCR)
The Pull Strength Control Register (PSCR) controls the pull strength value and direction for the chip.
Figure 4-19 shows the register and Table 4-20 provides its field descriptions.
0x1002_7854 (PSCR)
R
Access: User R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
Reset
R
W
Reset
PUENCR7
0
PUENCR6
0
0
0
PUENCR5
0
0
PUENCR4
0
0
PUENCR3
0
0
PUENCR2
0
0
PUENCR1
0
0
PUENCR0
0
0
Figure 4-19. Pull Strength Control Register (PSCR)
Table 4-20. Pull Strength Control Register Field Descriptions
Field
31–16
Description
Reserved. These bits are reserved and should read 0.
15–14
PUENCR
PUEN Strength Control 7. Bit selects direction (up or down) and strength.
(SD2_D0_MSHC_DATA0)
00 100k pull-down
01 100k pull-up
10 47k pull-up
11 22k pull-up
13–12
PUENCR6
PUEN Strength Control 6. Bit selects direction (up or down) and strength.
(SD2_D1_MSHC_DATA1)
00 100k pull-down
01 100k pull-up
10 47k pull-up
11 22k pull-up
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
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System Control
Table 4-20. Pull Strength Control Register Field Descriptions (continued)
Field
Description
11–10
PUENCR5
PUEN Strength Control 5. Bit selects direction (up or down) and strength.
(SD2_D2_MSHC_DATA2)
00 100k pull-down
01 100k pull-up
10 47k pull-up
11 22k pull-up
9–8
PUENCR4
PUEN Strength Control 4. Bit selects direction (up or down) and strength.
(SD2_D3_MSHC_DATA3)
00 100k pull-down
01 100k pull-up
10 47k pull-up
11 22k pull-up
7–6
PUENCR3
PUEN Strength Control 3. Bit selects direction (up or down) and strength.
(SD2_CMD_MSHC_BS)
00 100k pull-down
01 100k pull-up
10 47k pull-up
11 22k pull-up
5–4
PUENCR2
PUEN Strength Control 2. Bit selects direction (up or down) and strength.
(SD2_CLK_MSHC_SCLK)
00 100k pull-down
01 100k pull-up
10 47k pull-up
11 22k pull-up
3–2
PUENCR1
PUEN Strength Control 1. Bit selects direction (up or down) and strength.
(SD1_D3_CSPI3_SS)
00 100k pull-down
01 100k pull-up
10 47k pull-up
11 22k pull-up
1–0
PUENCR0
PUEN Strength Control 0. Bit selects direction (up or down) and strength.
(ATA_DATA3_SD3_D3S)
00 100k pull-down
01 100k pull-up
10 47k pull-up
11 22k pull-up
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System Control
4.2.20
Priority Control and Select Register (PCSR)
The Priority Control and Select Register (PCSR) consist of the master high priority and slave alternate
context priority select to the ARM9 Platform. Figure 4-20 shows the register and Table 4-21 provides its
field descriptions.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
S3_AMPR_SEL
S2_AMPR_SEL
S1_AMPR_SEL
S0_AMPR_SEL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
M4_HIGH_PRIORITY
M3_HIGH_PRIORITY
M2_HIGH_PRIORITY
M1_HIGH_PRIORITY
M0_HIGH_PRIORITY
R
Access: User R/W
M5_HIGH_PRIORITY
Address 0x1002_7858 (PCSR)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
W
Reset
R
W
Reset
Figure 4-20. Priority Control and Select Register (PCSR)
Table 4-21. Priority Control and Select Register Field Descriptions
Field
31–20
19–16
S3_AMPR_SEL
S2_AMPR_SEL
S1_AMPR_SEL
S0_AMPR_SEL
15–6
5–0
M5_HIGH_PRIORITY
M4_HIGH_PRIORITY
M3_HIGH_PRIORITY
M2_HIGH_PRIORITY
M1_HIGH_PRIORITY
M0_HIGH_PRIORITY
Description
Reserved. These bits are reserved and should read 0.
Slave Alternate Context Priority Select. Inputs to the ARM9 Platform to select the priority determination
and control source for the appropriate slave port. (Note s0 is the primary AHB and does not come out of
the ARM9 Platform.
0 Priority determination and control is made by regular registers.
1 Priority determination and control is made by alternate registers set in the Crossbar switch.
Reserved. These bits are reserved and should read 0.
Master High Priority. Inputs to the ARM9 Platform to elevate to highest appropriate master ports priority
level to each slave above all other master ports priority levels which do not have this input asserted. If
more than one master has its high priority input asserted, priority level is determined by the software
programmed priority assignments inside the Crossbar switch.
0 Master port low priority
1 Master port high priority
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-41
System Control
4.2.21
Power Management Control Register (PMCR)
The Power Management Control Register (PMCR) controls the DPTC function of the chip. Figure 4-21
shows the register and Table 4-22 provides its field descriptions.
0x1002_7860 (PMCR)
31
R
W
Reset
R
W
Reset
30
29
Access: User R/W
28
27
26
25
24
23
22
0
21
20
19
18
17
16
MC
EM
UP
LO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
DIE
DPTE
N
0
0
0
0
RVEN
0
0
0
VSTBY
0
0
REFCOUNTER
DCR
RCLK DRCE DRCE DRCE DRCE
ON
3
1
2
0
0
0
0
0
0
0
DIM
0
0
Figure 4-21. Power Management Control Register (PMCR)
Table 4-22. Power Management Control Register Field Descriptions
Field
Description
31
MC
MC. Measure complete status bit
0 On progress or idle
1 Measure completed
30
EM
EM. Emergency interrupt state bit
0 No Emergency interrupt
1 Emergency interrupt is detected.
29
UP
UP. Upper_limit interrupt state bit
0 No Upper_limit interrupt is detected.
1 Upper_limit interrupt is detected.
28
LO
LO. Lower_limit interrupt state bit.
0 No lower_limit interrupt.
1 Lower_limit interrupt is detected.
27
Reserved. These bits are reserved and should read 0.
26–16
REFCOUNTER
15
RVEN
14
Reference Counter Value. These bits contains the value of reference counter in
comparison stage.
Reduced Voltage Mode Enable. This bit controls whether enable RV mode when chip
is in sleep mode.
0 Disable RV mode is in sleep mode.
1 Enable RV mode is in sleep mode.
Reserved. These bits are reserved and should read 0.
13–12
VSTBY
Voltage Standby Control. These two bits will be put on Boot1 and Boot0 when chip is in
sleep mode. And used to inform PMIC to change the voltage to the chip.
11–10
Reserved. These bits are reserved and should read 0.
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System Control
Table 4-22. Power Management Control Register Field Descriptions (continued)
Field
Description
9
DCR
DPTC counting range. This bit sets how many times the system clock may increment
and the reference circuits remain active (and their output signals will be counted). Value
of ‘1’ causes a 256 system clock count. Value of ‘0’ causes a 128 system clock count.
0 128 system clock count
1 256 system clock count
8
RCLKON
DPTC Reference Clock Monitor On. Enable Reference clock for debug.
0 Normal operation
1 Reference clock always on
7
DRCE3
DPTC reference circuit3 enable. This bit defines if reference circuit3 is enabled during
DPTC operation.
0 DPTC reference circuit3 is disabled.
1 DPTC reference circuit3 is enabled.
6
DRCE2
DPTC reference circuit2 enable. This bit defines if reference circuit2 is enabled during
DPTC operation.
0 DPTC reference circuit2 is disabled.
1 DPTC reference circuit2 is enabled.
5
DRCE1
DPTC reference circuit1 enable. This bit defines if reference circuit1 is enabled during
DPTC operation.
0 DPTC reference circuit1 is disabled.
1 DPTC reference circuit1 is enabled.
4
DRCE0
DPTC reference circuit0 enable. This bit defines if reference circuit0 is enabled during
DPTC operation.
0 DPTC reference circuit0 is disabled.
1 DPTC reference circuit0 is enabled.
3–2
DIM
DPTC interrupt mask. these bits control how DPTC generate its interrupt.
00 DPTC will generate an interrupt in all cases.
01 DPTC will generate an interrupt only in lower_limit case.
10 DPTC will generate an interrupt only in upper_limit case.
11 DPTC will generate an interrupt only in emergency case.
1
DIE
DPTC Interrupt enable. This bit enables DPTC interrupt generation.
0 No interrupt will be generated.
1 Enable interrupt generation
0
DPTEN
DPTC enable. This bit enables the DPTC block and starts the reference circuit clock
counting and compares this to look-up table values.
0 DPTC is disabled.
1 DPTC is enabled.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-43
System Control
4.2.22
DPTC Comparator Value Register 0 (DCVR0)
The DPTC Comparator Value Register 0 (DCVR0) contains the DPTC comparator value for the DPTC in
the i.MX27 processor. Figure 4-22 shows the register and Table 4-23 provides its field descriptions.
0x1002_7864 (DCVR0)
31
30
29
Access: User R/W
28
27
R
26
25
24
23
22
21
20
19
ULV
W
Reset
17
16
LLV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
R
LLV
W
Reset
18
0
0
0
ELV
0
0
0
0
0
0
0
0
Figure 4-22. DPTC Comparator Value Register 0 (DCVR0)
Table 4-23. DPTC Comparator Value Register 0 Field Description
Field
Description
31–21
ULV
Upper Limit. Value for the upper performance limit of the reference circuit 0 clock counter.
20–10
LLV
Lower Limit. Value for the lower performance limit of the reference circuit 0 clock counter.
9–0
ELV
4.2.23
Emergency Limit. Value for the lower performance limit of the reference circuit 0 clock counter. This
serves as an “emergency” lower limit, which indicates a critical value.
DPTC Comparator Value Register 1 (DCVR1)
The DPTC Comparator Value Register 1 (DCVR1) contains the DPTC comparator value for the DPTC in
the i.MX27 processor. Figure 4-23 shows the register and Table 4-24 provides its field descriptions.
0x1002_7868 (DCVR1)
31
30
29
Access: User R/W
28
27
R
24
23
22
21
20
19
18
17
16
LLV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
R
LLV
W
Reset
25
ULV
W
Reset
26
0
0
0
ELV
0
0
0
0
0
0
0
0
Figure 4-23. DPTC Comparator Value Register 1 (DCVR1)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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System Control
Table 4-24. DPTC Comparator Value Register 1 Field Descriptions
Field
Description
31–21
ULV
Upper Limit. Value for the upper performance limit of the reference circuit 1 clock counter.
20–10
LLV
Lower Limit. Value for the lower performance limit of the reference circuit 1 clock counter.
9–0
ELV
4.2.24
Emergency Limit. Value for the lower performance limit of the reference circuit 1 clock counter. This
serves as an “emergency” lower limit, which indicates a critical value
DPTC Comparator Value Register 2
The DPTC Comparator Value Register 2 (DCVR2) contains the DPTC comparator value for the DPTC in
the i.MX27 processor. Figure 4-24 shows the register and Table 4-25 provides its field descriptions.
0x1002_786C (DCVR2)
31
30
29
Access: User R/W
28
27
R
26
25
24
23
22
21
20
19
ULV
W
Reset
17
16
LLV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
R
LLV
W
Reset
18
0
0
0
ELV
0
0
0
0
0
0
0
0
Figure 4-24. DPTC Comparator Value Register 2 (DCVR2)
Table 4-25. DPTC Comparator Value Register 2 Field Descriptions
Field
Description
31–21
ULV
Upper Limit. Value for the upper performance limit of the reference circuit 2 clock counter.
20–10
LLV
Lower Limit. Value for the lower performance limit of the reference circuit 2 clock counter.
9–0
ELV
Emergency Limit. Value for the lower performance limit of the reference circuit 2 clock counter. This
serves as an “emergency” lower limit, which indicates a critical value.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-45
System Control
4.2.25
DPTC Comparator Value Register 3
The DPTC Comparator Value Register 3 (DCVR3) contains the DPTC comparator value for the DPTC in
the i.MX27 processor. Figure 4-25 shows the register and Table 4-26 provides its field descriptions.
0x1002_7870 (DCVR3)
31
30
29
Access: User R/W
28
27
R
26
25
24
23
22
21
20
19
18
ULV
W
Reset
16
LLV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
R
LLV
W
Reset
17
0
0
0
ELV
0
0
0
0
0
0
0
0
Figure 4-25. DPTC Comparator Value Register 3 (DCVR3)
Table 4-26. DPTC Comparator Value Register 3 Description
Field
Description
31–21
ULV
Upper Limit. Value for the upper performance limit of the reference circuit 3 clock counter.
20–10
LLV
Lower Limit. Value for the lower performance limit of the reference circuit 3 clock counter.
9–0
ELV
4.2.26
Emergency Limit. Value for the lower performance limit of the reference circuit 3 clock counter. This
serves as an “emergency” lower limit, which indicates a critical value.
PMIC Pad Control Register (PPCR)
The PMIC Pad Control Register (PPCR) contains control bits of Boot0 and Boot1 pads which used for RV
function in low power mode. Figure 4-26 shows the register and Table 4-27 provides its field descriptions.
0x1002_7874 (PPCR)
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
5
4
3
2
1
0
0
0
0
0
W
Reset
R
PUS1
W
Reset
0
PUE1
1
0
DSE1
0
OE1
0
0
7
6
0
0
0
0
PUS0
0
PUE0
1
0
DSE0
0
OE0
1
1
Figure 4-26. PMIC Pad Control Register (PPCR)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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System Control
Table 4-27. PMIC Pad Control Register Field Description
Field
4.3
Description
31–14
Reserved. These bits are reserved and should read 0.
13–12
PUS1
PUS1. PUS control of BOOT1 pad. Only used when RVEN bit is set.
11
PUE1
PUE1. PUE control of BOOT1 pad. Only used when RVEN bit is set.
10–9
DSE1
DSE1. DSE control of BOOT1 pad. Only used when RVEN bit is set.
8
OE1
OE1. OE control of BOOT1 pad. Only used when RVEN bit is set.
7–16
Reserved. These bits are reserved and should read 0.
5–4
PUS0
PUS0. PUS control of BOOT0 pad. Only used when RVEN bit is set.
3
PUE0
PUE0. PUE control of BOOT0 pad. Only used when RVEN bit is set.
2–1
DSE0
DSE0. DSE control of BOOT0 pad. Only used when RVEN bit is set.
0
OE0
OE0. OE control of BOOT0 pad. Only used when RVEN bit is set.
System Boot Mode Selection
The operational system boot mode of the i.MX27 processor upon system reset is determined by the
configuration of the four external input pins, BOOT[3:0]. The settings of these pins control where the
system is boot from and the memory port size.
The i.MX27 processor always begins fetching instruction from the address 0x00000000 after reset. The
BOOT[3:0] pins control the memory region that is mapped to the address 0x0. Upon power up, if the
BOOT_INT is 1, the Boot Address will always be 0x00000000. If the fuse of the BOOT_INT is blown,
the BOOT Address will be generated based on the BOOT[3:0] information. The boot modes are defined
in Table 4-28. These boot modes information are registered during the system reset. When an external chip
select is enabled by the BOOT[3:0] pins, the reset vector 0x0 will jump to the corresponding boot address
space.
NOTE
The BOOT pins must not change once the i.MX27 device is out of reset. For
proper operation, BOOT[3] must always be tied to VSS.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
4-47
System Control
Table 4-28. System Boot Mode Selection
Inputs
BOOT[3:0]
Output Signals Active Device
(Boot Internal)
Output Signals Active Device
(Boot External)
Boot Address
0000
iROM (Bootstrap USB/UART)
iROM Bootstrap USB/UART
0x00000030
0010
iROM (8-bit 2 Kbyte NAND Flash)
8-bit 2 Kbyte NAND Flash
0xD8000000
0011
iROM (16-bit 2 Kbyte NAND Flash)
16-bit 2 Kbyte NAND Flash
0xD8000000
0100
iROM (16-bit 512 byte NAND Flash)
16-bit 512 Kbyte NAND Flash
0xD8000000
0101
iROM (16-bit CS0 at D[15:0] (NOR Flash))
16-bit CS0 at D[15:0] (NOR Flash)
0xC0000000
0110
Reserved
Reserved
0xC0000000
0111
iROM (8-bit 512 byte NAND Flash)
8-bit 512B NAND Flash
0xD8000000
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Freescale Semiconductor
Signal Descriptions and Pin Assignments
Chapter 5
Signal Descriptions and Pin Assignments
5.1
Introduction
This chapter identifies and describes the i.MX27 signals and their pin assignments.
5.2
Signal Descriptions
The i.MX27 signals are described in Table 5-1. Most of the signals shown in Table 5-1 are multiplexed
with other signals. For simplicity, only the primary signal names are shown. See Table 5-2 for complete
information on the signal multiplexing schemes of these signals.
Table 5-1. i.MX27 Signal Descriptions
Pad Name
Function/Notes
External Bus/Chip Select (EMI)
A [13:0]
Address bus signals, shared with SDRAM/MDDR, WEIM and PCMCIA, A[10] for
SDRAM/MDDR is not the address but the pre-charge bank select signal.
MA10
Address bus signals for SDRAM/MDDR
A [25:14]
Address bus signals, shared with WEIM and PCMCIA
SDBA[1:0]
SDRAM/MDDR bank address signals
SD[31:0]
Data bus signals for SDRAM, MDDR
SDQS[3:0]
MDDR data sample strobe signals
DQM0–DQM3
SDRAM data mask strobe signals
EB0
Active low external enable byte signal that controls D [15:8], shared with PCMCIA PC_REG.
EB1
Active low external enable byte signal that controls D [7:0], shared with PCMCIA PC_IORD.
OE
Memory Output Enable—Active low output enables external data bus, shared with PCMCIA
PC_IOWR.
CS [5:0]
Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected
by the Function Multiplexing Control Register (FMCR) in the System Control chapter. By default
CSD [1:0] is selected. DTACK is multiplexed with CS4.
CS[5:4] are multiplexed with ETMTRACECLK and ETMTRACESYNC; PF22, 21.
ECB
Active low input signal sent by flash device to the EIM whenever the flash device must terminate
an on-going burst sequence and initiate a new (long first access) burst sequence.
LBA
Active low signal sent by flash device causing external burst device to latch the starting burst
address.
BCLK
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW
RW signal—Indicates whether external access is a read (high) or write (low) cycle. This signal
is also shared with the PCMCIA PC_WE.
RAS
SDRAM/MDDR Row Address Select signal
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
5-1
Signal Descriptions and Pin Assignments
Table 5-1. i.MX27 Signal Descriptions (continued)
Pad Name
Function/Notes
CAS
SDRAM/MDDR Column Address Select signal
SDWE
SDRAM Write Enable signal
SDCKE0
SDRAM Clock Enable 0
SDCKE1
SDRAM Clock Enable 1
SDCLK
SDRAM Clock
SDCLK_B
SDRAM Clock_B
NFWE_B
NFC Write enable signal, multiplexed with ETMPIPESTAT2; PF6
NFRE_B
NFC Read enable signal, multiplexed with ETMPIPESTAT1; PF5
NFALE
NFC Address latch signal, multiplexed with ETMPIPESTAT0; PF4
NFCLE
NFC Command latch signal, multiplexed with ETMTRACEPKT0; PF1
NFWP_B
NFC Write Permit signal, multiplexed with ETMTRACEPKT1; PF2
NFCE_B
NFC Chip enable signal, multiplexed with ETMTRACEPKT2; PF3
NFRB
NFC read Busy signal, multiplexed with ETMTRACEPKT3; PF0
D[15:0]
Data Bus signal, shared with EMI, PCMCIA, and NFC
PC_CD1_B
PCMCIA card detect signal, multiplexed with ATA ATA_DIOR signal; PF20
PC_CD2_B
PCMCIA card detect signal, multiplexed with ATA ATA_DIOW signal; PF19
PC_WAIT_B
PCMCIA WAIT signal, multiplexed with ATA ATA_CS1 signal; PF18
PC_READY
PCMCIA READY/IRQ signal, multiplexed with ATA ATA_CS0 signal; PF17
PC_PWRON
PCMCIA signal, multiplexed with ATA ATA_DA2 signal; PF16
PC_VS1
PCMCIA voltage sense signal, multiplexed with ATA ATA_DA1 signal; PF14
PC_VS2
PCMCIA voltage sense signal, multiplexed with ATA ATA_DA0 signal; PF13
PC_BVD1
PCMCIA Battery voltage detect signal, multiplexed with ATA ATA_DMARQ signal; PF12
PC_BVD2
PCMCIA Battery voltage detect signal, multiplexed with ATA ATA_DMACK signalPF11
PC_RST
PCMCIA card reset signal, multiplexed with ATA ATA_RESET_B signal; PF10
IOIS16
PCMCIA mode signal, multiplexed with ATA ATA_INTRQ signal; PF9
PC_RW_B
PCMCIA read write signal, multiplexed with ATA ATA_IORDY signal; PF8
PC_POE
PCMCIA output enable signal, multiplexed with ATA ATA_BUFFER_EN signal; PF7
Clocks and Resets
CLKO
Clock Out signal selected from internal clock signals. Refer to the clock controller for internal
clock selection; PF15.
EXT_60M
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
EXT_266M
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
5-2
Freescale Semiconductor
Signal Descriptions and Pin Assignments
Table 5-1. i.MX27 Signal Descriptions (continued)
Pad Name
Function/Notes
OSC26M_TEST
This is a special factory test signal. To ensure proper operation, leave this signal as a no
connect.
RESET_IN
Master Reset—External active low Schmitt trigger input signal. When this signal goes active,
all modules (except the reset module, SDRAMC module, and the clock control module) are
reset.
RESET_OUT
Reset_Out—Output from the internal Hreset_b; and the Hreset can be caused by all reset
source: power on reset, system reset (RESET_IN), and watchdog reset.
POR
Power On Reset—Active low Schmitt trigger input signal. The POR signal is normally generated
by an external RC circuit designed to detect a power-up event.
XTAL26M
Oscillator output to external crystal
EXTAL26M
Crystal input (26 MHz), or a 16 MHz to 32 MHz oscillator (or square-wave) input when internal
oscillator circuit is shut down.
CLKMODE[1:0]
These are special factory test signals. To ensure proper operation, do not connect to these
signals.
EXTAL32K
32 kHz crystal input (Note: in the RTC power domain)
XTAL32K
Oscillator output to 32 kHz crystal (Note: in the RTC power domain)
Power_cut
(Note: in the RTC power domain)
Power_on_reset
(Note: in the RTC power domain)
osc32K_bypass
The signal for osc32k input bypass (Note: in the RTC power domain)
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode of the i.MX27 processor upon
system reset is determined by the settings of these pins. BOOT[1:0] are also used as
handshake signals to PMIC(VSTBY).
JTAG
JTAG_CTRL
JTAG Controller select signal—JTAG_CTRL is sampled during rising edge of TRST. Must be
pulled to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal
test purposes only.
TRST
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
TDO
Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK
Test Clock to synchronize test logic and control register access through the JTAG port.
TMS
Test Mode Select to sequence JTAG test controller’s state machine. Sampled on rising edge of
TCK.
RTCK
JTAG Return Clock used to enhance stability of JTAG debug interface devices. This signal is
multiplexed with 1-Wire; thus, utilizing 1-Wire will render RTCK unusable and vice versa; PE16.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
5-3
Signal Descriptions and Pin Assignments
Table 5-1. i.MX27 Signal Descriptions (continued)
Pad Name
Function/Notes
Secure Digital Interface (X2)
SD1_CMD
SD Command bidirectional signal—If the system designer does not want to make use of the
internal pull-up, via the Pull-up enable register, a 4. 7K–69 K external pull up resistor must be
added. This signal is multiplexed with CSPI3_MOSI; PE22.
SD1_CLK
SD Output Clock. This signal is multiplexed with CSPI3_SCLK; PE23.
SD1_D[3:0]
SD Data bidirectional signals—If the system designer does not want to make use of the internal
pull-up, via the Pull-up enable register, a 50 K–69 K external pull up resistor must be added.
SD1_D[3] is muxed with CSPI3_SS while SD1_D[0] is muxed with CSPI3_MISO PE21–18.
SD2_CMD
SD Command bidirectional signal. This signal is multiplexed with MSHC_BS; through GPIO
multiplexed with SLCDC1_CS; PB8.
SD2_CLK
SD Output Clock signal. This signal is multiplexed with MSHC_SCLK, through GPIO
multiplexed with SLCDC1_CLK; PB9.
SD2_D[3:0]
SD Data bidirectional signals. SD2_D[3:0] multiplexed with MSHC_DATA[0:3], also through
GPIO SD2_1:0] multiplexed with SLCDC1_RS and SLDCD1_D0; PB7–PB4.
SD3_CMD
SD Command bidirectional signal. This signal is through GPIO PD0 multiplexed with
FEC_TXD0.
SD3_CLK
SD Output Clock signal. This signal is multiplexed with ETMTRACEPKT15 and also through
GPIO PD1 multiplexed with FEC_TXD1.
Note: SD3_DATA is multiplexed with ATA_DATA3–0.
UARTs (X6)
UART1_RTS
Request to Send input signal; PE15
UART1_CTS
Clear to Send output signal; PE14
UART1_RXD
Receive Data input signal; PE13
UART1_TXD
Transmit Data output signal, PE12
UART2_RXD
Receive Data input signal. This signal is multiplexed with KP_ROW6 signal from KPP; PE7.
UART2_TXD
Transmit Data output signal. This signal is multiplexed with KP_COL6 signal from KPP; PE6.
UART2_RTS
Request to Send input signal. This signal is multiplexed with KP_ROW7 signal from KPP; PE4.
UART2_CTS
Clear to Send output signal. This signal is multiplexed with KP_COL7 signal from KPP; PE3.
UART3_RTS
Request to Send input signal, PE11
UART3_CTS
Clear to Send output signal; PE10
UART3_RXD
Receive Data input signal; PE9
UART3_TXD
Transmit Data output signal; PE8
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
5-4
Freescale Semiconductor
Signal Descriptions and Pin Assignments
Table 5-1. i.MX27 Signal Descriptions (continued)
Pad Name
Function/Notes
Note: UART 4, 5, and 6 are multiplexed with COMS Sensor Interface signals.
Keypad
KP_COL[5:0]
Keypad Column selection signals. KP_COL[7:6] are multiplexed with UART2_CTS and
UART2_TXD respectively. Alternatively, KP_COL6 is also available on the internal factory test
signal TEST_WB2. The Function Multiplexing Control Register in the System Control chapter
must be used in conjunction with programming the GPIO multiplexing (to select the alternate
signal multiplexing) to choose which signal KP_COL6 is available.
KP_ROW[5:0]
Keypad Row selection signals. KP_ROW[7:6] are multiplexed with UART2_RTS and
UART2_RXD signals respectively. The Function Multiplexing Control Register in the System
Control chapter must be used in conjunction with programming the GPIO multiplexing (to select
the alternate signal multiplexing) to choose which signals KP_ROW6 and KP_ROW7 are
available.
Note: KP_COL[7:6] and KP_ROW[7:6] are multiplexed with UART2 signals as show above, also see UARTs table.
PWM
PWMO
PWM Output. This signal is multiplexed with PC_SPKOUT of PCMCIA, as well as TOUT2 and
TOUT3 of the General Purpose Timer module; PE5.
CSPI (X3)
CSPI1_MOSI
Master Out/Slave In signal, PD31
CSPI1_MISO
Master In/Slave Out signal, PD30
CSPI1_SS[2:0]
Slave Select (Selectable polarity) signal, the CSPI1_SS2 is multiplexed with
USBH2_DATA5/RCV; and CSPI1_SS1 is multiplexed with EXT_DMAGRANT; PD26–28.
CSPI1_SCLK
Serial Clock signal, PD29
CSPI1_RDY
Serial Data Ready signal, shared with Ext_DMAReq_B signal; PD25
CSPI2_MOSI
Master Out/Slave In signal, multiplexed with USBH2_DATA1/TXDP; PD24
CSPI2_MISO
Master In/Slave Out signal, multiplexed with USBH2_DATA2/TXDm; PD23
CSPI2_SS[2:0]
Slave Select (Selectable polarity) signals, multiplexed with USBH2_DATA4/RXDM,
USBH2_DATA3/RXDP, USBH2_DATA6/SPEED; PD19–PD21
CSPI2_SCLK
Serial Clock signal, multiplexed with USBH2_DATA0/OEn; PD22
Note: CSPI3 CSPI3_MOSI, CSPI3_MISO, CSPI3_SS, andCSPI3_SCLK are multiplexed with SD1 signals.
I2C
I2C2_SCL
I2C2 Clock, through GPIO, multiplexed with SLCDC_data8; PC6
I2C2_SDA
I2C2 Data, through GPIO, multiplexed with SLCDC_data7; PC5
I2C_CLK
I2C1 Clock; PD18
I2C_DATA
I2C1 Data; PD17
CMOS Sensor Interface
CSI_HSYNC
Sensor port horizontal sync, multiplexed with UART5_RTSP; PB21
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
5-5
Signal Descriptions and Pin Assignments
Table 5-1. i.MX27 Signal Descriptions (continued)
Pad Name
Function/Notes
CSI_VSYNC
Sensor port vertical sync, multiplexed with UART5_CTS; PB20
CSI_D7
Sensor port data, multiplexed with UART5_RXD; PB19
CSI_D6
Sensor port data, multiplexed with UART5_TXD; PB18
CSI_D5
Sensor port data; PB17
CSI_PIXCLK
Sensor port data latch clock; PB16
CSI_MCLK
Sensor port master clock, PB15
CSI_D4
Sensor port data, PD14
CSI_D3
Sensor port data, multiplexed with UART6_RTS; PB13
CSI_D2
Sensor port data, multiplexed with UART6_CTS; PB12
CSI_D1
Sensor port data, multiplexed with UART6_RXD; PB11
CSI_D0
Sensor port data, multiplexed with UART6_TXD; PB10
Serial Audio Port—SSI (Configurable to I2S Protocol and AC97) (2 to 4)
SSI1_CLK
Serial clock signal that is output in master or input in slave; PC23
SSI1_TXD
Transmit serial data; PC22
SSI1_RXD
Receive serial data; PC21
SSI1_FS
Frame Sync signal that is output in master and input in slave; PC20
SSI2_CLK
Serial clock signal that is output in master or input in slave, multiplexed with GPT4_TIN. PC27
SSI2_TXD
Transmit serial data signal, multiplexed with GPT4_TOUT; PC26
SSI2_RXD
Receive serial data, multiplexed with GPT5_TIN; PC25
SSI2_FS
Frame Sync signal which is output in master and input in slave, multiplexed with GPT5_TOUT:
PC24
SSI3_CLK
Serial clock signal which is output in master or input in slave. This signal is multiplexed with
SLCDC2_CLK; through GPIO multiplexed with PC_WAIT_B; PC31.
SSI3_TXD
Transmit serial data signal which is multiplexed with SLCDC2_CS, through GPIO multiplexed
with PC_READY; PC30
SSI3_RXD
Receive serial data which is multiplexed with SLCDC2_RS; through GPIO multiplexed with
PC_VS1; PC29
SSI3_FS
Frame Sync signal which is output in master and input in slave. This signal is multiplexed with
SLCDC2_D0; through GPIO multiplexed with PC_VS1; PC28.
SSI4_CLK
Serial clock signal which is output in master or input in slave; through GPIO multiplexed with
PC_BVD1; PC19
SSI4_TXD
Transmit serial data; through GPIO multiplexed with PC_BVD2; PC18
SSI4_RXD
Receive serial data; through GPIO multiplexed with IOIS16; PC17
SSI4_FS
Frame Sync signal which is output in master and input in slave; PC16
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
5-6
Freescale Semiconductor
Signal Descriptions and Pin Assignments
Table 5-1. i.MX27 Signal Descriptions (continued)
Pad Name
Function/Notes
General Purpose Timers (X6)
TIN
Timer Input Capture or Timer Input Clock—The signal on this input is applied to GPT 1–3
simultaneously. This signal is muxed with the Walk-up Guard Mode WKGD signal in the PLL,
Clock, and Reset Controller module, and is also multiplexed with GPT6_TOUT; PC15.
TOUT1
Timer Output signal from General Purpose Timer1 (GPT1). This signal is multiplexed with
SSI1_MCLK and SSI2_MCLK signal of SSI1 and SSI2. The pin name of this signal is simply
TOUT, and is also multiplexed with GPT6_TIN; PC14.
Note: TOUT2, TOUT3 are multiplexed with PWMO pad; GPT4 and GPT5 signals are multiplexed with SSI2 pads.
USB2.0
USBOTG_DIR/TXDM
USB OTG direction/Transmit Data Minus signal, multiplexed with KP_ROW7A; PE2
USBOTG_STP/TXDM
USB OTG Stop signal/Transmit Data Minus signal, multiplexed with KP_ROW6A; PE1
USBOTG_NXT/TXDM
USB OTG NEXT/Transmit Data Minus signal, multiplexed with KP_COL6A; PE0
USBOTG_CLK/TXDM
USB OTG Clock/Transmit Data Minus signal, PE24
USBOTG_DATA7/SUSPEND
USB OTG Data7/Suspend signal, PE25
USBH2_STP/TXDM
USB Host2 Stop signal/Transmit Data Minus signal, PA4
USBH2_NXT/TXDM
USB Host2 NEXT/Transmit Data Minus signal, PA3
USBH2_DATA7/SUSPEND
USB Host2 Data7/Suspend signal, PA2
USBH2_DIR/TXDM
USB Host2 Direction/Transmit Data Minus signal, PA1
USBH2_CLK/TXDM
USB Host2 Clock/Transmit Data Minus signal; PA0
USBOTG_DATA3/RXDP
USB OTG data4/Receive Data Plus signal; multiplexed with SLCDC1_DAT15 through PC13
USBOTG_DATA4/RXDM
USB OTG data4/Receive Data Minus signal; multiplexed with SLCDC1_DAT14 through PC12
USBOTG_DATA1/TXDP
USB OTG data1/Transmit Data Plus signal; multiplexed with SLCDC1_DAT13 through PC11
USBOTG_DATA2/TXDm
USB OTG data2/Transmit Data Minus signal; multiplexed with SLCDC1_DAT12 through PC10
USBOTG_DATA0/Oen
USB OTG data0/Output Enable signal; multiplexed with SLCDC1_DAT11 through PC9
USBOTG_DATA6/SPEED
USB OTG data6/Suspend signal; multiplexed with SLCDC1_DAT10 and USBG_TXR_INT_B
through PC8
USBOTG_DATA5/RCV
USB OTG data5/RCV signal; multiplexed with SLCDC1_DAT9 through PC7
USBH1_RXDP
USB Host1 Receive Data Plus signal, multiplexed with UART4_RXD; multiplexed with
SLCDC1_DAT6 and UART4_RTS_ALT through PB31
USBH1_RXDM
USB Host1 Receive Data Minus signal; multiplexed with SLCDC1_DAT5 and UART4_CTS
through PB30
USBH1_TXDP
USB Host1 Transmit Data Plus signal; multiplexed with UART4_CTS, multiplexed with
SLCDC1_DAT4 and UART4_RXD_ALT through PB29
USBH1_TXDM
USB Host1 Transmit Data Minus signal; multiplexed with UART4_TXD, multiplexed with
SLCDC1_DAT3 through PB28
USBH1_OE_B
USB Host1 Output Enable signal; multiplexed with SLCDC1_DAT2 through PB27
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
5-7
Signal Descriptions and Pin Assignments
Table 5-1. i.MX27 Signal Descriptions (continued)
Pad Name
Function/Notes
USBH1_FS
USB Host1 Full Speed output signal, multiplexed with UART4_RTS, multiplexed with
SLCDC1_DAT1 through PB26
USBH1_RCV
USB Host1 RCV signal; multiplexed with SLCDC1_DAT0 through PB25
USB_OC_B
USB OC signal. PB24
USB_PWR
USB Power signal; PB23
USBH1_SUSP
USB Host1 Suspend signal; PB22
LCD Controller and Smart LCD Controller
OE_ACD
Alternate Crystal Direction/Output Enable; PA31
CONTRAST
This signal is used to control the LCD bias voltage as contrast control; PA30
VSYNC
Frame Sync or Vsync—This signal also serves as the clock signal output for gate;
driver (dedicated signal SPS for Sharp panel HR-TFT); PA29.
HSYNC
Line Pulse or HSync; PA28
SPL_SPR
Sampling start signal for left and right scanning. Through GPIO, this signal is multiplexed with
the SLCDC1_CLK; PA27.
PS
Control signal output for source driver (Sharp panel dedicated signal). This signal is multiplexed
with the SLCDC1_CS; PA26.
CLS
Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated
signal). This signal is multiplexed with the SLCDC1_RS; PA25.
REV
Signal for common electrode driving signal preparation (Sharp panel dedicated signal). This
signal is multiplexed with SLCDC1_D0; PA24.
LD [17:0]
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. Through GPIO,
LD[15:0] signals are multiplexed with SLCDC1_DAT[15:0], SLCDC. PA23–PA6.
LSCLK
Shift Clock; PA5
Note: SLCDC signals are multiplexed with LCDC signals.
ATA
ATA_DATA15–0
ATA Data Bus, [15:0] are multiplexed with
ETMTRACEPKT4–12,
FEC_MDIO,
ETMTRACEPKT13–14
SD3_D3–0;
Through GPIO also are multiplexed with SLCDC 15–0, and FEC signals; PF23, PD16–PD2.
Noisy I/O Supply Pins
NVDD1–15, AVDD
Noisy Supply for the I/O pins. There are 16 I/O voltage pads, N VDD1 through NVDD15 + AVDD.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
5-8
Freescale Semiconductor
Signal Descriptions and Pin Assignments
Table 5-1. i.MX27 Signal Descriptions (continued)
Pad Name
Function/Notes
Analog Supply Pins
FPMVDD
MPLLVDD
OSC26VDD
UPLLVDD
OSC32VDD
Supply for analog blocks
FPMVSS
MPLLVSS
OSC26VSS
OSC32VSS
UPLLVSS
Quiet GND for analog blocks
QVDD Internal Power Supply
QVDD
Power supply pins for silicon internal circuitry
QVSS
GND pins for silicon internal circuitry
FUSEVDD
For FuseVDD
RTCVDD
For RTC, SCC power supply
RTCVSS
For RTC, SCC GND
Note: Note: Both 1-Wire and Fast Ethernet Controller signals are multiplexed with other signals. As a result these signal names
do not appear in this list. The signals are listed below with the named signal that they are multiplexed.
1-Wire Signals:
The 1-Wire input and output signal is multiplexed with JTAG RTCK pad, PE16.
Fast Ethernet Controller (FEC) Signals:
FEC_TX_EN: Transmit enable signal, through GPIO multiplexed with ATA_DATA15 pad; PF23
FEC_TX_ER: Transmit Data Error; through GPIO multiplexed with ATA_DATA14 pad; PD16
FEC_COL: Collision signal; through GPIO multiplexed with ATA_DATA13 pad; PD15
FEC_RX_CLK: Receive Clock signal; through GPIO multiplexed with ATA_DATA12 pad; PD14
FEC_RX_DV: Receive data Valid signal; through GPIO multiplexed with ATA_DATA11 pad; PD13
FEC_RXD0: Receive Data0; through GPIO multiplexed with ATA_DATA10 pad; PD12
FEC_TX_CLK: Transmit Clock signal; through GPIO multiplexed with ATA_DATA9 pad; PD11
FEC_CRS: Carrier Sense enable; through GPIO multiplexed with ATA_DATA8 pad; PD10
FEC_MDC: Management Data Clock; through GPIO multiplexed with ATA_DATA7 pad; PD9
FEC_MDIO: Management Data Input/Output, multiplexed with ATA_DATA6 pad; PD8
FEC_RXD3–1: Receive Data; through GPIO multiplexed with ATA_DATA5–3 pad; PD7–5
FEC_RX_ER: Receive Data Error; through GPIO multiplexed with ATA_DATA2 pad; PD4
FEC_TXD3–2: Transmit Data; through GPIO multiplexed with ATA_DATA1–0; pad; PD3–2
FEC_TXD1: Transmit Data; through GPIO multiplexed with SD3_CLK pad; PD1
FEC_TXD0: Transmit Data; through GPIO multiplexed with SD3_CMD pad; PD0
Note: The Rest ATA signals are multiplexed with PCMCIA Pads.
5.3
I/O Power Supply and Signal Multiplexing Scheme
This section describes information about both the power supply for each I/O pin and its functional
multiplexing scheme. Section 5.3.3, “I/O Mode and Supply Level” provides information on how to
configure the power supply scheme for each device in the system (memory and external peripherals). The
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
5-9
Signal Descriptions and Pin Assignments
functional multiplexing information shown in Table 5-2 enables the user to select the function of each pin
by configuring the appropriate GPIO registers when those pins are multiplexed to provide different
functions. In some cases, the use of the Function Multiplexing Control Register (FMCR) in Chapter 4,
“System Control” may be required to select multiplex functionality.
5.3.1
Pull/Pull Strength/Open Drain Descriptions
For Table 5-2, the following notes describe the abbreviations used in the Pull/Pull Strength/Open Drain
section.
• KP—Keeper Circuit permanently On when in Primary/Alternate Mode
• PU—Pull Up permanently On when in Primary/Alternate Mode
• PD—Pull Down permanently On when in Primary/Alternate Mode
• PUEN—Pull Up controllable from Module when in Primary/Alternate Mode
• PDEN—Pull Down controllable from Module when in Primary/Alternate Mode
• OD—Open Drain permanently On when in Primary/Alternate Mode
• ODEN—Open Drain Enable controllable from Module when in Primary/Alternate Mode
5.3.2
•
•
•
5.3.3
GPIO Default and Pull-Up Configuration
The term Primary name is the package contact name.
The Default column contains the GPIO default configuration as it appears after chip reset.
Pull-up configuration and pull strength—Pin mux with GPIO means that Pull Up is controlled by
the GPIO PUEN register (in Primary, Alternate or GPIO Mode), and the default pull strength is
100 K for all GPIO use.
I/O Mode and Supply Level
The supply level shown in Table 5-2 relates to the power bank segment. The same bank pad can be supplied
same voltage. The voltage limitation relates to the I/O mode selected.
• I/O type of DDR mode—Voltage rating 1.75–1.9 V.
• I/O type of slow mode—Voltage rating 1.75–3.1 V.
• I/O type of fast mode—Voltage rating 1.75–2.8 V.
• For every analog pad a recommended supply voltage is shown.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
5-10
Freescale Semiconductor
GPIO
AVDD
Slow/Hyst
BOOT2
I
BOOT2
AVDD
Slow/Hyst
BOOT0
I
BOOT0
AVDD
Slow/Hyst
BOOT3
I
BOOT3
AVDD
Slow/Hyst
BOOT1
I
BOOT1
FPMVDD
Supply
FPMVDD
static
FPMVDD
FPMVDD
Supply
FPMVSS
static
FPMVSS
FUSEVDD
Supply
FUSEVDD
static
FUSEVDD
FUSEVDD
Supply
FUSEVSS
static
FUSEVSS
MPLLVDD
Supply
MPLLVSS
static
MPLLVSS
MPLLVDD
Supply
MPLLVDD
static
MPLLVDD
NVDD1
Supply
NVSS1
static
NVSS1
NVDD1
Fast
NFRB
I
ETMTRACE
PKT3
O
PF0
PUEN
NFRB
NVDD1
Fast
NFWP_B
O
ETMTRACE
PKT1
O
PF2
PUEN
NFWP_B
NVDD1
Fast
NFALE
O
ETMPIPEST
AT0
O
PF4
PUEN
NFALE
NVDD1
Fast
NFWE_B
O
ETMPIPEST
AT2
O
PF6
PDEN
NFWE_B
Default
AVDD
BOUT
static
AOUT
AVDD
CIN
Supply
BIN
AVDD
AIN
AVSS
PUEN/PDEN
static
Mux3
Direction1
AVSS
Direction2
Signal/Pad Name
Supply
Signal
I/O Type
AVDD
Signal Descriptions and Pin Assignments
5-11
Power
Bank
Pull-up /Pull Strength
/Open Drain
Alternate
Pull-up/Pull Strength/Open Drain2
Primary
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
Table 5-2. i.MX27 Pin MUX Table
GPIO
PUEN
NFCLE
NVDD1
Fast
NFRE_B
O
ETMPIPEST
AT1
O
PF5
PUEN
NFRE_B
NVDD1
Fast
NFCLE
O
ETMTRACE
PKT0
O
PF1
PUEN
NFCE_B
NVDD1
DDR
D14
B
KP
D14
NVDD1
DDR
D15
B
KP
D15
NVDD1
DDR
D11
B
KP
D11
NVDD1
DDR
D13
B
KP
D13
NVDD1
DDR
D9
B
KP
D9
NVDD1
DDR
D12
B
KP
D12
NVDD1
DDR
D7
B
KP
D7
NVDD1
DDR
D5
B
KP
D5
NVDD1
DDR
D3
B
KP
D3
NVDD1
DDR
D1
B
KP
D1
NVDD1
Supply
NVDD1
static
NVDD1
DDR
D10
B
KP
D10
NVDD1
DDR
D8
B
KP
D8
NVDD1
DDR
D6
B
KP
D6
Default
PF3
BOUT
O
AOUT
PUEN/PDEN
ETMTRACE
PKT2
CIN
Mux3
O
BIN
Direction1
NFCE_B
AIN
Signal/Pad Name
Fast
Direction2
I/O Type
NVDD1
Signal
Power
Bank
Freescale Semiconductor
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Pull-up /Pull Strength
/Open Drain
Alternate
Pull-up/Pull Strength/Open Drain2
Primary
NVDD1
Signal Descriptions and Pin Assignments
5-12
Table 5-2. i.MX27 Pin MUX Table (continued)
KP
D2
NVDD1
DDR
D0
B
KP
D0
NVDD10
Slow/Hyst
SSI2_RXDA
T
B
GPT5_TIN
I
PC25
PUEN
NVDD10
Slow/Hyst
SSI3_RXDA
T
B
SLCDC2_R
S
I
PC29
PUEN
NVDD10
Slow_/Hyst
KP_ROW1
B
PU/100k
KP_ROW
1
NVDD10
Slow1/Hyst
KP_ROW5
B
PU/100k
KP_ROW
5
NVDD10
Slow/Hyst
SSI4_RXDA
T
B
PC17
PUEN
NVDD10
Slow/Hyst
SSI1_RXDA
T
B
PC21
PUEN
PC21
NVDD10
Slow/Hyst
SSI2_CLK
B
GPT4_TIN
I
PC27
PUEN
PC27
NVDD10
Slow/Hyst
SSI3_CLK
B
SLCDC2_CL
K
I
PC31
PUEN
NVDD10
Slow/Hyst
KP_ROW3
B
NVDD10
Slow/Hyst
TIN
I
Default
B
BOUT
D2
AOUT
DDR
CIN
NVDD1
BIN
D4
AIN
KP
PUEN/PDEN
B
Mux3
D4
Pull-up /Pull Strength
/Open Drain
Pull-up/Pull Strength/Open Drain2
DDR
Direction2
Direction1
NVDD1
Signal
Signal/Pad Name
GPIO
I/O Type
Alternate
Power
Bank
Primary
PC25
PC_VS
1
IOIS16
PC_W
AIT_B
PU/100k
PC29
PC17
PC31
KP_ROW
3
PC15
PUEN
5-13
GPT6_
TOUT
WKGD
_B
PC15
Signal Descriptions and Pin Assignments
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
Table 5-2. i.MX27 Pin MUX Table (continued)
GPIO
Slow/Hyst
SSI1_CLK
B
PC23
PUEN
NVDD10
Slow/Hyst
KP_ROW2
B
NVDD10
Slow/Hyst
SSI3_TXDA
T
B
SLCDC2_C
S
I
PC30
PUEN
PC_RE
ADY
PC30
NVDD10
Slow/Hyst
SSI3_FS
B
SLCDC2_D0
I
PC28
PUEN
PC_VS
2
PC28
NVDD10
Slow/Hyst
KP_ROW4
B
NVDD10
Slow/Hyst
TOUT
O
PC14
PUEN
NVDD10
Slow/Hyst
SSI1_TXDA
T
B
PC22
PUEN
PC22
NVDD10
Slow/Hyst
SSI2_TXDA
T
B
PC26
PUEN
PC26
NVDD10
Slow/Hyst
KP_ROW0
B
NVDD10
Slow/Hyst
SSI4_FS
B
PC16
PUEN
PC16
NVDD10
Slow/Hyst
SSI1_FS
B
PC20
PUEN
PC20
NVDD10
Supply
NVDD10
static
Default
NVDD10
BOUT
PUEN
AOUT
PUEN/PDEN
PC19
CIN
Mux3
B
BIN
Direction1
SSI4_CLK
AIN
Signal/Pad Name
Slow/Hyst
Direction2
I/O Type
NVDD10
Signal
Power
Bank
Freescale Semiconductor
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Pull-up /Pull Strength
/Open Drain
Alternate
Pull-up/Pull Strength/Open Drain2
Primary
PC_BV
D1
PC19
PC23
PU/100k
KP_ROW
2
PU/100k
KP_ROW
4
GPT4_TOUT
O
PU/100k
SSI_M
CLK1
SSI_M
CLK2
GPT6_
TIN
PC14
KP_ROW
0
NVDD10
Signal Descriptions and Pin Assignments
5-14
Table 5-2. i.MX27 Pin MUX Table (continued)
NVDD11
Slow/Hyst
CSI_D3
I
NVDD11
Slow/Hyst
CSI_D5
I
NVDD11
Slow/Hyst
CSI_HSYN
C
I
UART5_RTS
NVDD11
Slow/Hyst
CSI_D1
I
UART6_RX
D
NVDD11
Fast/Hyst
CSI_MCLK
O
NVDD11
Slow/Hyst
CSI_D7
I
UART5_RX
D
NVDD11
Slow/Hyst
CSI_D0
I
NVDD11
Slow/Hyst
CSI_D2
I
NVDD11
Fast/Hyst
CSI_PIXCL
K
I
Default
static
PUEN
BOUT
NVSS10
PC24
AOUT
Supply
O
CIN
NVDD10
GPT5_TOUT
PUEN
BIN
B
PC18
AIN
SSI2_FS
PUEN/PDEN
Slow/Hyst
Mux3
NVDD10
Pull-up /Pull Strength
/Open Drain
B
Direction2
SSI4_TXDA
T
Signal
Slow/Hyst
Direction1
NVDD10
GPIO
PC_BV
D2
PC18
PC24
NVSS10
UART6_RTS
I
PB13
PUEN
LCDC_
TEST9
PB13
PB17
PUEN
LCDC_
TEST1
1
PB17
I
PB21
PUEN
LCDC_
TEST1
5
PB21
I
PB11
PUEN
LCDC_
TEST7
PB11
PB15
PUEN
I
PB19
PUEN
LCDC_
TEST1
3
PB19
UART6_TXD
O
PB10
PUEN
LCDC_
TEST6
PB10
UART6_CTS
O
PB12
PUEN
LCDC_
TEST8
PB12
PB16
PUEN
PB15
PB16
Signal Descriptions and Pin Assignments
5-15
I/O Type
Pull-up/Pull Strength/Open Drain2
Alternate
Power
Bank
Signal/Pad Name
Primary
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
Table 5-2. i.MX27 Pin MUX Table (continued)
GPIO
I
NVDD11
Slow/Hyst
CSI_D6
I
NVDD11
Supply
NVDD11
static
NVDD11
Slow/Hyst
CSI_VSYN
C
I
NVDD11
Supply
NVSS11
static
NVDD12
Slow/Hyst
SPL_SPR
O
PA27
PDEN
NVDD12
Slow/Hyst
CONTRAST
O
PA30
PUEN
PA30
NVDD12
Slow/Hyst
HSYNC
O
PA28
PUEN
PA28
NVDD12
Slow/Hyst
PS
O
PA26
PDEN
NVDD12
Slow/Hyst
OE_ACD
O
PA31
PUEN
NVDD12
Slow/Hyst
REV
O
PA24
PDEN
SLDCD
1_D0
PA24
NVDD12
Slow/Hyst
LD16
O
PA22
PUEN
Ext_D
MAGra
nt_B
PA22
UART5_TXD
O
PUEN
LCDC_
TEST1
2
PB18
Default
PB18
BOUT
PB14
AOUT
LCDC_
TEST1
0
CIN
PUEN
BIN
PB14
AIN
PUEN/PDEN
Direction1
CSI_D4
Mux3
Signal/Pad Name
Slow/Hyst
Direction2
I/O Type
NVDD11
Signal
Power
Bank
Freescale Semiconductor
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Pull-up /Pull Strength
/Open Drain
Alternate
Pull-up/Pull Strength/Open Drain2
Primary
NVDD11
UART5_CTS
O
PB20
PUEN
LCDC_
TEST1
4
PB20
NVSS11
SLCDC
1_CLK
SLCDC
1_CS
PA27
PA26
PA31
Signal Descriptions and Pin Assignments
5-16
Table 5-2. i.MX27 Pin MUX Table (continued)
GPIO
SLCDC
1_DAT
6
PA20
NVDD12
Slow/Hyst
LD10
O
PA16
PUEN
SLCDC
1_DAT
10
SLCDC
1_DAT
2
PA16
NVDD12
Slow/Hyst
VSYNC
O
PA29
PUEN
NVDD12
Slow/Hyst
LD8
O
PA14
PUEN
SLCDC
1_DAT
8
NVDD12
Slow/Hyst
LD6
O
PA12
PUEN
SLCDC
1_DAT
6
NVDD12
Slow/Hyst
LD17
O
PA23
PUEN
NVDD12
Slow/Hyst
CLS
O
PA25
PDEN
NVDD12
Supply
NVSS12
static
NVDD12
Slow/Hyst
LD4
O
PA10
PUEN
SLCDC
1_DAT
4
NVDD12
Slow/Hyst
LD12
O
PA18
PUEN
SLCDC
1_DAT
12
Default
SLCDC
1_DAT
14
BOUT
PUEN
AOUT
PUEN/PDEN
PA20
CIN
Mux3
O
BIN
Direction1
LD14
AIN
Signal/Pad Name
Slow/Hyst
Direction2
I/O Type
NVDD12
Signal
Power
Bank
Pull-up /Pull Strength
/Open Drain
Alternate
Pull-up/Pull Strength/Open Drain2
Primary
PA29
SLCDC
1_DAT
0
PA14
PA12
PA23
SLCDC
1_RS
PA25
NVSS12
PA10
SLCDC
1_DAT
4
PA18
5-17
Signal Descriptions and Pin Assignments
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
Table 5-2. i.MX27 Pin MUX Table (continued)
GPIO
SLCDC
1_DAT
5
PA19
NVDD12
Slow/Hyst
LD15
O
PA21
PUEN
SLCDC
1_DAT
15
SLCDC
1_DAT
7
PA21
NVDD12
Slow/Hyst
LD0
O
PA6
PUEN
SLCDC
1_DAT
0
PA6
NVDD12
Slow/Hyst
LD2
O
PA8
PUEN
SLCDC
1_DAT
2
PA8
NVDD12
Slow/Hyst
LD7
O
PA13
PUEN
SLCDC
1_DAT
7
PA13
NVDD12
Slow/Hyst
LD5
O
PA11
PUEN
SLCDC
1_DAT
5
PA11
NVDD12
Slow/Hyst
LD11
O
PA17
PUEN
SLCDC
1_DAT
11
NVDD12
Fast/Hyst
LSCLK
O
PA5
PUEN
NVDD12
Slow/Hyst
LD3
O
PA9
PUEN
SLCDC
1_DAT
3
Default
SLCDC
1_DAT
13
BOUT
PUEN
AOUT
PUEN/PDEN
PA19
CIN
Mux3
O
BIN
Direction1
LD13
AIN
Signal/Pad Name
Slow/Hyst
Direction2
I/O Type
NVDD12
Signal
Power
Bank
Freescale Semiconductor
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Pull-up /Pull Strength
/Open Drain
Alternate
Pull-up/Pull Strength/Open Drain2
Primary
PA17
PA5
SLCDC
1_DAT
3
PA9
Signal Descriptions and Pin Assignments
5-18
Table 5-2. i.MX27 Pin MUX Table (continued)
GPIO
NVDD12
Slow/Hyst
LD9
O
PA15
PUEN
SLCDC
1_DAT
9
NVDD12
Supply
NVDD12
static
NVDD12
NVDD13
Supply
NVSS13
static
NVSS13
NVDD13
Slow/Hyst
osc32k_byp
ass
I
osc32k_by
pass
NVDD13
Supply
NVDD13
static
NVDD13
NVDD13
Slow/Hyst
Power_on_r
eset
I
PU/100k
Power_on
_reset
NVDD13
Slow/Hyst
Power_cut
I
PD/100k
Power_cut
NVDD14
Fast/Hyst
CSPI2_SS1
B
NVDD14
Slow/Hyst
USBH1_OE
_B
B
NVDD14
Fast/Hyst
CSPI2_SS2
B
USBH2_DAT
A4/RXDM
NVDD14
Fast/Hyst
CSPI2_SCL
K
B
USBH2_DAT
A0/OEn
B
PA7
SLCDC
1_DAT
1
PA15
PD20
PUEN
PD20
PB27
PUEN
B
PD19
PUEN
PD19
B
PD22
PUEN
PD22
SLCDC
1_DAT
2
PB27
5-19
Signal Descriptions and Pin Assignments
USBH2_DAT
A3/RXDP
Default
SLCDC
1_DAT
1
BOUT
PUEN
AOUT
PUEN/PDEN
PA7
CIN
Mux3
O
BIN
Direction1
LD1
AIN
Signal/Pad Name
Slow/Hyst
Direction2
I/O Type
NVDD12
Signal
Power
Bank
Pull-up /Pull Strength
/Open Drain
Alternate
Pull-up/Pull Strength/Open Drain2
Primary
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
Table 5-2. i.MX27 Pin MUX Table (continued)
Freescale Semiconductor
PB29
PDEN
SLCDC
1_DAT
4
NVDD14
Slow/Hyst
USBH1_FS
B
UART4_RTS
I
PB26
PDEN
SLCDC
1_DAT
1
NVDD14
Fast/Hyst
CSPI1_SS2
B
USBH2_DAT
A5/RCV
B
PD26
PUEN
PD26
NVDD14
Fast/Hyst
CSPI2_MO
SI
B
B
PD24
PUEN
PD24
UART4
_RXD_
ALT
Default
O
BOUT
UART4_CTS
AOUT
O
CIN
PUEN/PDEN
USBH1_TX
DP
BIN
Mux3
Slow/Hyst
AIN
Direction2
NVDD14
Direction1
Signal
Pull-up /Pull Strength
/Open Drain
GPIO
I/O Type
Pull-up/Pull Strength/Open Drain2
Alternate
Power
Bank
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Signal/Pad Name
Primary
PB29
PB26
USBH2_DAT
A1/TXDP
NVDD14
Slow/Hyst
USBH1_RX
DP
B
UART4_RX
D
I
PB31
PDEN
SLCDC
1_DAT
6
NVDD14
Slow/Hyst
USBH1_TX
DM
O
UART4_TXD
O
PB28
PDEN
SLCDC
1_DAT
3
NVDD14
Fast/Hyst
CSPI2_SS0
B
USBH2_DAT
A6/SPEED
B
PD21
PUEN
PD21
NVDD14
Slow/Hyst
USB_PWR
O
PB23
PUEN
PB23
NVDD14
Slow/Hyst
I2C2_SCL
B
PC6
PUEN
NVDD14
Slow/Hyst
USBH1_SU
SP
B
PB22
PUEN
OD
SLCDC
1_DAT
8
UART4
_RTS_
ALT
PB31
PB28
PC6
USB_BYP
_B
Signal Descriptions and Pin Assignments
5-20
Table 5-2. i.MX27 Pin MUX Table (continued)
Default
BOUT
AOUT
CIN
PUEN
BIN
PD23
AIN
Pull-up /Pull Strength
/Open Drain
Direction2
Signal
B
PUEN/PDEN
B
GPIO
Mux3
CSPI2_MIS
O
Alternate
Pull-up/Pull Strength/Open Drain2
Fast/Hyst
Direction1
I/O Type
NVDD14
Signal/Pad Name
Power
Bank
Primary
PD23
USBH2_DAT
A2/TXDm
NVDD14
Supply
NVSS14
static
NVSS14
NVDD14
Supply
NVDD14
static
NVDD14
NVDD14
Slow/Hyst
USB_OC_B
I
PB24
PUEN
NVDD14
Slow/Hyst
USBH1_RC
V
B
PB25
PUEN
SLCDC
1_DAT
0
NVDD14
Slow/Hyst
USBH1_RX
DM
B
PB30
PDEN
SLCDC
1_DAT
5
NVDD14
Slow/Hyst
I2C2_SDA
B
OD
PC5
PUEN
SLCDC
1_DAT
7
NVDD15
Slow/Hyst
SD2_D3
B
PU/PD/1
00k
PB7
PDEN
SLCDC
1_RS
NVDD15
Fast/Hyst
SD2_CLK
O
PB9
NVDD15
Slow/Hyst
SD2_D0
B
NVDD15
Slow/Hyst
SD2_CMD
B
MSHC_DAT
A3
B
PU/PD/1
00k
MSHC_SCL
K
O
PU/100k
MSHC_DAT
A0
B
PD/100k
PU/100k
MSHC_BS
O
PD/100k
PB24
PB25
UART4
_CTS
PB30
PC5
LCDC_
TEST3
PB7
PDEN
LCDC_
TEST5
PB9
PB4
PDEN
LCDC_
TEST0
PB4
PB8
PDEN
LCDC_
TEST4
PB8
SLCDC
1_CS
5-21
Signal Descriptions and Pin Assignments
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
Table 5-2. i.MX27 Pin MUX Table (continued)
B
PD/100k
PB6
PDEN
SLDCD
1_D0
LCDC_
TEST2
PB6
NVDD15
Slow/Hyst
SD2_D1
B
PU/100k
MSHC_DAT
A1
B
PD/100k
PB5
PDEN
SLCDC
1_CLK
LCDC_
TEST1
PB5
NVDD15
Supply
NVSS15
static
NVSS15
NVDD15
Supply
NVDD15
static
NVDD15
NVDD2
DDR
SD30
B
KP
SD30
NVDD2
DDR
A24
O
KP
A24
NVDD2
DDR
SD27
B
KP
SD27
NVDD2
DDR
A23
O
KP
A23
NVDD2
DDR
SD24
B
KP
SD24
NVDD2
DDR
A21
O
KP
A21
NVDD2
DDR
SD21
B
KP
SD21
NVDD2
DDR
SD10
B
KP
SD10
NVDD2
DDR
A22
O
KP
A22
NVDD2
DDR
SD20
B
KP
SD20
NVDD2
DDR
SD17
B
KP
SD17
NVDD2
DDR
A18
O
KP
A18
NVDD2
DDR
A17
O
KP
A17
NVDD2
DDR
SD22
B
KP
SD22
Default
MSHC_DAT
A2
BOUT
PUEN/PDEN
PU/100k
AOUT
Mux3
B
CIN
Pull-up /Pull Strength
/Open Drain
SD2_D2
BIN
Direction2
Slow/Hyst
AIN
Pull-up/Pull Strength/Open Drain2
NVDD15
Signal
Direction1
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
Signal/Pad Name
GPIO
I/O Type
Alternate
Power
Bank
Primary
Signal Descriptions and Pin Assignments
5-22
Table 5-2. i.MX27 Pin MUX Table (continued)
SD16
NVDD2
DDR
SD14
B
KP
SD14
NVDD2
DDR
SD11
B
KP
SD11
NVDD2
Supply
NVSS2
static
NVSS2
NVDD2
Supply
NVDD2
static
NVDD2
NVDD2
DDR
A9
B
KP
A9
NVDD2
DDR
A12
B
KP
A12
NVDD2
DDR
A5
B
KP
A5
NVDD2
DDR
A7
B
KP
A7
NVDD2
DDR
MA10
O
NVDD2
DDR
SDBA1
O
KP
SDBA1
NVDD2
DDR
A1
B
KP
A1
NVDD2
DDR
A13
B
KP
A13
NVDD2
DDR
A11
B
KP
A11
NVDD2
DDR
A3
B
KP
A3
NVDD2
DDR
SD31
B
KP
SD31
NVDD2
DDR
A25
O
KP
A25
NVDD2
DDR
A8
B
KP
A8
Default
KP
BOUT
B
AOUT
SD16
CIN
DDR
BIN
NVDD2
AIN
SD19
PUEN/PDEN
KP
Mux3
B
Pull-up /Pull Strength
/Open Drain
SD19
Direction2
Pull-up/Pull Strength/Open Drain2
DDR
Signal
Direction1
NVDD2
MA10
Signal Descriptions and Pin Assignments
5-23
Signal/Pad Name
GPIO
I/O Type
Alternate
Power
Bank
Primary
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
Table 5-2. i.MX27 Pin MUX Table (continued)
KP
SD26
NVDD2
DDR
SD28
B
KP
SD28
NVDD2
DDR
SD29
B
KP
SD29
NVDD2
DDR
A19
O
KP
A19
NVDD2
DDR
A4
B
KP
A4
NVDD2
DDR
A2
B
KP
A2
NVDD2
DDR
SD23
B
KP
SD23
NVDD2
DDR
SDQS2
B
KP
SDQS2
NVDD2
DDR
SD25
B
KP
SD25
NVDD2
DDR
SDQS1
B
KP
SDQS1
NVDD2
DDR
SD13
B
KP
SD13
NVDD2
DDR
A0
B
KP
A0
NVDD2
DDR
SDBA0
O
KP
SDBA0
NVDD2
DDR
SDQS3
B
KP
SDQS3
NVDD2
DDR
A20
O
KP
A20
NVDD2
DDR
SD18
B
KP
SD18
NVDD2
DDR
SD15
B
KP
SD15
NVDD2
DDR
SD12
B
KP
SD12
Default
B
BOUT
SD26
AOUT
DDR
CIN
NVDD2
BIN
A6
AIN
KP
PUEN/PDEN
B
Mux3
A6
Pull-up /Pull Strength
/Open Drain
DDR
Direction2
Pull-up/Pull Strength/Open Drain2
NVDD2
Signal
Direction1
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
Signal/Pad Name
GPIO
I/O Type
Alternate
Power
Bank
Primary
Signal Descriptions and Pin Assignments
5-24
Table 5-2. i.MX27 Pin MUX Table (continued)
A14
NVDD3
DDR
SD4
B
KP
SD4
NVDD3
DDR
SD1
B
KP
SD1
NVDD3
DDR
SD9
B
KP
SD9
NVDD3
DDR
SD5
B
KP
SD5
NVDD3
DDR
SD3
B
KP
SD3
NVDD3
DDR
DQM3
O
KP
DQM3
NVDD3
DDR
SD7
B
KP
SD7
NVDD3
DDR
SDQS0
B
KP
SDQS0
NVDD3
Supply
NVSS3
static
NVSS3
NVDD3
Supply
NVDD3
static
NVDD3
NVDD3
DDR
SD6
B
KP
SD6
NVDD3
DDR
A16
O
KP
A16
NVDD3
DDR
SD8
B
KP
SD8
NVDD3
DDR
A15
B
KP
A15
NVDD3
DDR
SD2
B
KP
SD2
NVDD4
DDR
RAS_B
O
KP
RAS_B
NVDD4
DDR
CS1_B
O
Default
KP
BOUT
B
AOUT
A14
CIN
DDR
BIN
NVDD3
AIN
SD0
PUEN/PDEN
KP
Mux3
B
Pull-up /Pull Strength
/Open Drain
SD0
Direction2
Pull-up/Pull Strength/Open Drain2
DDR
Signal
Direction1
NVDD3
CS1_B
Signal Descriptions and Pin Assignments
5-25
Signal/Pad Name
GPIO
I/O Type
Alternate
Power
Bank
Primary
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
Table 5-2. i.MX27 Pin MUX Table (continued)
GPIO
A10
NVDD4
DDR
CAS_B
O
KP
CAS_B
NVDD4
DDR
SDCKE0
O
KP
SDCKE0
NVDD4
DDR
RW_B
O
NVDD4
Fast
ECB_B
I
NVDD4
DDR
EB1_B
O
NVDD4
Fast
JTAG_CTRL
I
PU/100k
JTAG_CT
RL
NVDD4
DDR
DQM0
O
KP
DQM0
NVDD4
DDR_CLK
SDCLK
B
SDCLK
NVDD4
DDR_CLK
SDCLK_B
B
SDCLK_B
NVDD4
Fast
CS4_B
O
NVDD4
DDR
CS0_B
O
NVDD4
Fast
CLKO
O
NVDD4
Fast
EXT_266M
I
EXT_266
M
NVDD4
Supply
NVSS4
static
NVSS4
NVDD4
Supply
NVDD4
static
NVDD4
Default
KP
BOUT
B
AOUT
A10
CIN
DDR
BIN
NVDD4
AIN
O
PUEN/PDEN
Direction1
BCLK
Mux3
Signal/Pad Name
DDR
Direction2
I/O Type
NVDD4
Signal
Power
Bank
Freescale Semiconductor
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Pull-up /Pull Strength
/Open Drain
Alternate
Pull-up/Pull Strength/Open Drain2
Primary
BCLK
RW_B
PU/100k
ECB_B
EB1_B
ETMTRACE
SYNC
O
PF21
PUEN
CS5_D
TACK
CS4_B
CS0_B
PF15
PUEN
CLKO
Signal Descriptions and Pin Assignments
5-26
Table 5-2. i.MX27 Pin MUX Table (continued)
SDWE_B
NVDD4
DDR
CS3_B
O
KP
CS3_B
NVDD4
Fast
CS5_B
O
NVDD4
DDR
EB0_B
O
EB0_B
NVDD4
Fast
EXT_60M
I
EXT_60M
NVDD4
DDR
DQM2
O
KP
DQM2
NVDD4
DDR
SDCKE1
O
KP
SDCKE1
NVDD4
DDR
CS2_B
O
KP
CS2_B
NVDD4
DDR
LBA_B
O
LBA_B
NVDD4
DDR
OE_B
O
OE_B
NVDD5
Slow/Hyst
RESET_OU
T_B
O
NVDD5
Slow/Hyst
CLKMODE0
I
PU/100k
CLKMOD
E0
NVDD5
Slow/Hyst
CLKMODE1
I
PU/100k
CLKMOD
E1
NVDD5
Slow
PC_CD2_B
I
ATA_DIOW
O
PF19
PUEN
PC_CD2_
B
NVDD5
Slow
PC_VS1
I
ATA_DA1
O
PF14
PUEN
PC_VS1
ETMTRACE
CLK
O
PF22
PE17
PUEN
PUEN
Default
KP
BOUT
O
AOUT
SDWE_B
CIN
DDR
BIN
NVDD4
AIN
DQM1
PUEN/PDEN
KP
Mux3
O
Pull-up /Pull Strength
/Open Drain
DQM1
Direction2
Pull-up/Pull Strength/Open Drain2
DDR
Signal
Direction1
NVDD4
CS5_B
PC_TE
ST_AH
BST0
RESET_O
UT_B
Signal Descriptions and Pin Assignments
5-27
Signal/Pad Name
GPIO
I/O Type
Alternate
Power
Bank
Primary
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
Table 5-2. i.MX27 Pin MUX Table (continued)
GPIO
Slow
PC_READY
I
ATA_CS0
O
PF17
PUEN
PC_READ
Y
NVDD5
Slow
PC_BVD1
I
ATA_DMAR
Q
I
PF12
PUEN
PC_BVD1
NVDD5
Slow
PC_RW_B
O
ATA_IORDY
I
PF8
PUEN
PC_RW_
B
NVDD5
Slow/Hyst
POR_B
I
POR_B
NVDD5
Supply
NVSS5
static
NVSS5
NVDD5
Supply
NVDD5
static
NVDD5
NVDD5
Slow
IOIS16
I
ATA_INTRQ
I
PF9
PUEN
IOIS16
NVDD5
Slow
PC_POE
O
ATA_BUFFE
R_EN
O
PF7
PUEN
PC_POE
NVDD5
Slow
PC_CD1_B
I
ATA_DIOR
O
PF20
PUEN
PC_CD1_
B
NVDD5
Slow
PC_VS2
I
ATA_DA0
O
PF13
PUEN
PC_VS2
NVDD5
Slow
PC_BVD2
I
ATA_DMACK
O
PF11
PUEN
PC_BVD2
NVDD5
Slow
PC_WAIT_
B
I
ATA_CS1
O
PF18
PUEN
PC_WAIT
_B
Default
NVDD5
PU/100k
BOUT
I
PUEN
AOUT
RESET_IN_
B
PF10
CIN
Slow/Hyst
O
BIN
NVDD5
ATA_RESET
_B
AIN
O
PUEN/PDEN
Direction1
PC_RST
Mux3
Signal/Pad Name
Slow
Direction2
I/O Type
NVDD5
Signal
Power
Bank
Freescale Semiconductor
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Pull-up /Pull Strength
/Open Drain
Alternate
Pull-up/Pull Strength/Open Drain2
Primary
PC_RST
RESET_I
N_B
Signal Descriptions and Pin Assignments
5-28
Table 5-2. i.MX27 Pin MUX Table (continued)
Pull-up /Pull Strength
/Open Drain
GPIO
Supply
NVDD6
static
NVDD6
NVDD6
Slow/Hyst
ATA_DATA6
B
FEC_MDIO
B
PD8
PUEN
SLCDC
1_DAT
6
ATA_DATA
6
NVDD6
Slow/Hyst
ATA_DATA2
B
SD3_D2
B
PD4
PUEN
SLCDC FEC_R
1_DAT X_ER
2
ATA_DATA
2
NVDD6
Slow/Hyst
SD3_CMD
B
PD0
PUEN
FEC_T
XD0
SD3_CMD
NVDD6
Slow/Hyst
SD3_CLK
O
ETMTRACE
PKT15
O
PD1
PUEN
FEC_T
XD1
SD3_CLK
NVDD6
Slow/Hyst
ATA_DATA1
0
B
ETMTRACE
PKT9
O
PD12
PUEN
NVDD6
Slow/Hyst
ATA_DATA0
B
SD3_D0
B
PD2
PUEN
NVDD6
Slow/Hyst
ATA_DATA1
B
SD3_D1
B
PD3
PUEN
Default
NVDD6
BOUT
NVSS6
AOUT
static
PDEN
CIN
NVSS6
PF16
BIN
Supply
O
AIN
NVDD6
ATA_DA2
PUEN/PDEN
I
Mux3
PC_PWRO
N
Direction2
Slow
Signal
NVDD5
Direction1
I/O Type
Pull-up/Pull Strength/Open Drain2
Alternate
Power
Bank
Signal/Pad Name
Primary
PC_PWR
ON
SLCDC FEC_R
1_DAT
XD0
10
ATA_DATA
10
FEC_T
XD2
SLCDC
1_DAT
0
ATA_DATA
0
FEC_T
XD3
SLCDC
1_DAT
1
ATA_DATA
1
5-29
Signal Descriptions and Pin Assignments
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
Table 5-2. i.MX27 Pin MUX Table (continued)
NVDD6
Slow/Hyst
ATA_DATA4
B
ETMTRACE
PKT14
O
PD6
NVDD6
Slow/Hyst
ATA_DATA5
B
ETMTRACE
PKT13
O
NVDD6
Slow/Hyst
ATA_DATA3
B
SD3_D3
B
NVDD6
Slow/Hyst
ATA_DATA8
B
ETMTRACE
PKT11
NVDD6
Slow/Hyst
ATA_DATA1
2
B
NVDD6
Slow/Hyst
ATA_DATA7
NVDD6
Slow/Hyst
NVDD6
Slow/Hyst
SLCDC
1_DAT
14
ATA_DATA
14
PUEN
SLCDC FEC_R
1_DAT
XD2
4
ATA_DATA
4
PD7
PUEN
SLCDC FEC_R
1_DAT
XD3
5
ATA_DATA
5
PD5
PDEN
SLCDC FEC_R
1_DAT
XD1
3
ATA_DATA
3
O
PD10
PUEN
SLCDC FEC_C
1_DAT
RS
8
ATA_DATA
8
ETMTRACE
PKT7
O
PD14
PUEN
SLCDC FEC_R
1_DAT X_CLK
12
ATA_DATA
12
B
ETMTRACE
PKT12
O
PD9
PUEN
SLCDC
1_DAT
7
ATA_DATA
7
ATA_DATA9
B
ETMTRACE
PKT10
O
PD11
PUEN
SLCDC FEC_T
1_DAT X_CLK
9
ATA_DATA
9
ATA_DATA1
1
B
ETMTRACE
PKT8
O
PD13
PUEN
SLCDC FEC_R
1_DAT X_DV
11
ATA_DATA
11
PU/PD/1
00k
FEC_T
X_ER
Default
PDEN
BOUT
PD16
AOUT
O
CIN
ETMTRACE
PKT5
BIN
B
AIN
PUEN/PDEN
ATA_DATA1
4
Direction2
Slow/Hyst
Signal
NVDD6
Direction1
Mux3
Pull-up /Pull Strength
/Open Drain
GPIO
I/O Type
Pull-up/Pull Strength/Open Drain2
Alternate
Power
Bank
Freescale Semiconductor
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Signal/Pad Name
Primary
FEC_M
DC
Signal Descriptions and Pin Assignments
5-30
Table 5-2. i.MX27 Pin MUX Table (continued)
NVDD6
Slow/Hyst
ATA_DATA1
5
B
ETMTRACE
PKT4
O
PF23
PDEN
FEC_T
X_EN
NVDD7
Fast/Hyst
B
PC11
PUEN
SLCDC
1_DAT
13
PC11
B
PC10
PUEN
SLCDC
1_DAT
12
PC10
B
PC8
PUEN
SLCDC
1_DAT
10
USBOTG_D
ATA1/TXDP
NVDD7
Fast/Hyst
USBOTG_D
ATA2/TXDm
NVDD7
Fast/Hyst
NVDD7
Supply
NVDD7
Fast/Hyst
NVSS7
static
Fast/Hyst
NVDD7
Fast/Hyst
USBH2_CL
K/TXDM
USBOTG_D
ATA4/RXDM
ATA_DATA
13
SLCDC
1_DAT
15
ATA_DATA
15
USBG_
TXR_I
NT_B
PC8
NVSS7
B
PC7
PUEN
I
PA0
PUEN
B
PC12
PUEN
USBOTG_D
ATA5/RCV
NVDD7
SLCDC FEC_C
1_DAT
OL
13
SLCDC
1_DAT
9
PC7
PA0
SLCDC
1_DAT
14
PC12
5-31
Signal Descriptions and Pin Assignments
USBOTG_D
ATA6/SPEE
D
Default
PUEN
BOUT
PD15
AOUT
O
CIN
ETMTRACE
PKT6
BIN
B
AIN
PUEN/PDEN
ATA_DATA1
3
Direction2
Slow/Hyst
Signal
NVDD6
Direction1
Mux3
Pull-up /Pull Strength
/Open Drain
GPIO
I/O Type
Pull-up/Pull Strength/Open Drain2
Alternate
Power
Bank
Signal/Pad Name
Primary
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
Table 5-2. i.MX27 Pin MUX Table (continued)
Freescale Semiconductor
Default
BOUT
AOUT
CIN
PUEN/PDEN
SLCDC
1_DAT
11
BIN
Mux3
PUEN
Direction2
PC9
Signal
B
USBOTG_D
ATA0/Oen
AIN
GPIO
Pull-up /Pull Strength
/Open Drain
Alternate
Pull-up/Pull Strength/Open Drain2
Fast/Hyst
Direction1
NVDD7
Signal/Pad Name
I/O Type
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Power
Bank
Primary
PC9
NVDD7
Fast/Hyst
USBH2_ST
P/TXDM
O
PA4
PUEN
PA4
NVDD7
Fast/Hyst
USBH2_DA
TA7/SUSPE
ND
B
PA2
PUEN
PA2
NVDD7
Fast/Hyst
B
PC13
PUEN
I
PA1
PUEN
PA1
I
PE24
PUEN
PE24
I
PA3
PUEN
PA3
PE1
PUEN
PE1
PE0
PUEN
PE0
USBOTG_D
ATA3/RXDP
NVDD7
Fast/Hyst
NVDD7
Fast/Hyst
USBH2_DI
R/TXDM
SLCDC
1_DAT
15
PC13
USBOTG_C
LK/TXDM
NVDD7
Fast/Hyst
NVDD7
Fast/Hyst
USBH2_NX
T/TXDM
O
KP_ROW6A
B
I
KP_COL6A
B
USBOTG_S
TP/TXDM
NVDD7
Fast/Hyst
USBOTG_N
XT/TXDM
ODEN
Signal Descriptions and Pin Assignments
5-32
Table 5-2. i.MX27 Pin MUX Table (continued)
PE2
Default
PUEN
BOUT
PE2
AOUT
PE25
CIN
PUEN
BIN
PE25
AIN
PUEN/PDEN
B
Mux3
GPIO
Pull-up /Pull Strength
/Open Drain
Direction2
Signal
Alternate
Pull-up/Pull Strength/Open Drain2
Fast/Hyst
Direction1
I/O Type
NVDD7
Signal/Pad Name
Power
Bank
Primary
USBOTG_D
ATA7/SUSP
END
NVDD7
Fast/Hyst
USBOTG_D
IR/TXDM
I
KP_ROW7A
B
NVDD7
Supply
NVDD7
static
NVDD8
Slow/Hyst
RTCK
O
OWIRE
B
NVDD8
Slow/Hyst
SD1_D0
B
CSPI3_MIS
O
NVDD8
Slow/Hyst
SD1_CMD
B
CSPI3_MOS
I
NVDD8
Slow/Hyst
CSPI1_MIS
O
B
NVDD8
Slow/Hyst
TDI
I
PU/100k
TDI
NVDD8
Slow/Hyst
TMS
I
PU/100k
TMS
NVDD8
Slow/Hyst
SD1_D2
B
PE20
PUEN
NVDD8
Slow/Hyst
CSPI1_RDY
/Ext_DMAR
EQ_B
I
PD25
PUEN
NVDD7
OD
PE16
PUEN
RTCK
I
PE18
PUEN
PC_TE
ST_AH
BST1
PE18
O
PE22
PUEN
PC_TE
ST_INT
_ERR
PE22
PD30
PUEN
PD30
PC_TE
ST_CA
RDST1
PE20
PD25
5-33
Signal Descriptions and Pin Assignments
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
Table 5-2. i.MX27 Pin MUX Table (continued)
Slow/Hyst
CSPI1_SS1
B
PD27
PUEN
NVDD8
Slow/Hyst
CSPI1_MO
SI
B
PD31
PUEN
NVDD8
Slow/Hyst
TDO
O
NVDD8
Slow/Hyst
SD1_D1
B
NVDD8
Slow/Hyst
SD1_D3
B
PU/PD/1
00k
NVDD8
Slow/Hyst
TCK
I
PU/100k
NVDD8
Slow/Hyst
CSPI1_SCL
K
B
NVDD8
Supply
NVDD8
static
NVDD8
Slow/Hyst
SD1_CLK
O
NVDD8
Supply
NVSS8
static
NVDD9
Slow2/Hyst
UART2_RT
S
I
Default
NVDD8
BOUT
I
AOUT
TRST_B
PUEN
CIN
Slow/Hyst
PD28
BIN
NVDD8
PUEN/PDEN
Direction1
B
Mux3
Signal/Pad Name
CSPI1_SS0
Direction2
I/O Type
Slow/Hyst
Signal
Power
Bank
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
NVDD8
AIN
GPIO
Pull-up /Pull Strength
/Open Drain
Alternate
Pull-up/Pull Strength/Open Drain2
Primary
PD28
PU/100k
TRST_B
Ext_D
MAGra
nt_B
Ext_D
MAGra
nt_B
PD27
PD31
TDO
CSPI3_SS
O
PU/PD
PE19
PUEN
PC_TE
ST_CA
RDST0
PE19
PE21
PDEN
PC_TE
ST_CA
RDST2
PE21
TCK
PD29
PUEN
PD29
NVDD8
CSPI3_SCL
K
O
PE23
PUEN
PC_TE
ST_INT
_ALL
PE23
NVSS8
KP_ROW7
B
PE4
PUEN
UART2_R
TS
Signal Descriptions and Pin Assignments
5-34
Table 5-2. i.MX27 Pin MUX Table (continued)
NVDD9
Slow/Hyst
NVDD9
Default
UART3_CT
S
BOUT
Slow/Hyst
PU/100k/
ODEN
AOUT
NVDD9
CIN
O
BIN
UART2_TX
D
AIN
Slow/Hyst
PUEN/PDEN
NVDD9
Mux3
B
GPIO
Pull-up /Pull Strength
/Open Drain
Direction1
KP_COL2
Direction2
Signal/Pad Name
Slow/Hyst
Signal
I/O Type
NVDD9
Alternate
Pull-up/Pull Strength/Open Drain2
Power
Bank
Primary
KP_COL2
KP_COL6
PE6
PUEN
UART2_T
XD
O
PE10
PUEN
PE10
UART1_CT
S
O
PE14
PUEN
UART1_C
TS
Slow/Hyst
I2C_CLK
B
OD
PD18
PUEN
PD18
NVDD9
Slow/Hyst
KP_COL0
B
PU/100k/
ODEN
KP_COL0
NVDD9
Slow/Hyst
KP_COL4
B
PU/100k/
ODEN
KP_COL4
NVDD9
Slow/Hyst
UART3_TX
D
O
PE8
PUEN
PE8
NVDD9
Slow/Hyst
UART1_TX
D
O
PE12
PUEN
UART1_T
XD
NVDD9
Slow/Hyst
PWMO
O
PE5
PUEN
NVDD9
Slow/Hyst
UART1_RT
S
I
PE15
PUEN
UART1_R
TS
NVDD9
Slow/Hyst
UART2_CT
S
O
PE3
PUEN
UART2_C
TS
KP_COL7
B
B
ODEN
ODEN
PC_SP TOUT2 TOUT3
KOUT
PE5
5-35
Signal Descriptions and Pin Assignments
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
Table 5-2. i.MX27 Pin MUX Table (continued)
GPIO
Slow/Hyst
UART3_RT
S
I
NVDD9
Slow/Hyst
I2C_DATA
B
OD
NVDD9
Slow/Hyst
KP_COL1
B
PU/100k/
ODEN
KP_COL1
NVDD9
Slow/Hyst
KP_COL5
B
PU/100k/
ODEN
KP_COL5
NVDD9
Slow/Hyst
UART3_RX
D
I
PE9
PUEN
PE9
NVDD9
Slow/Hyst
UART1_RX
D
I
PE13
PUEN
UART1_R
XD
NVDD9
Supply
NVDD9
static
NVDD9
NVDD9
Supply
NVSS9
static
NVSS9
OSC26VDD
Supply
OSC26VDD
static
OSC26VD
D
OSC26VDD
Analog_By
p
XTAL26M
static
XTAL26M
OSC26VDD
Supply
OSC26VSS
static
OSC26VS
S
Default
NVDD9
BOUT
I
AOUT
UART2_RX
D
CIN
Slow/Hyst
BIN
NVDD9
PU/100k/
ODEN
AIN
B
PUEN/PDEN
Direction1
KP_COL3
Mux3
Signal/Pad Name
Slow/Hyst
Direction2
I/O Type
NVDD9
Signal
Power
Bank
Freescale Semiconductor
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Pull-up /Pull Strength
/Open Drain
Alternate
Pull-up/Pull Strength/Open Drain2
Primary
KP_COL3
KP_ROW6
B
PE7
PUEN
UART2_R
XD
PE11
PUEN
PE11
PD17
PUEN
PD17
Signal Descriptions and Pin Assignments
5-36
Table 5-2. i.MX27 Pin MUX Table (continued)
GPIO
OSC32VDD
Supply
OSC32VDD
static
OSC32VD
D
OSC32VDD
Analog
EXTAL32K
I
EXTAL32
K
OSC32VDD
Supply
OSC32VSS
static
OSC32VS
S
OSC32VDD
Analog
XTAL32K
I
XTAL32K
QVDD10
Supply
QVSS10
static
QVSS10
QVDD10
Supply
QVDD10
static
QVDD10
QVDD12
Supply
QVSS12
static
QVSS12
QVDD12
Supply
QVDD12
static
QVDD12
QVDD2
Supply
QVSS2
static
QVSS2
QVDD2
Supply
QVDD2
static
QVDD2
QVDD3
Supply
QVSS3
static
QVSS3
QVDD3
Supply
QVDD3
static
QVDD3
QVDD5
Supply
QVSS5
static
QVSS5
QVDD5
Supply
QVDD5
static
QVDD5
Default
OSC26M_
TEST
BOUT
I
AOUT
OSC26M_T
EST
CIN
Analog
BIN
OSC26VDD
AIN
EXTAL26
M
PUEN/PDEN
static
Mux3
Direction1
EXTAL26M
Direction2
Signal/Pad Name
Analog_By
p
Signal
I/O Type
OSC26VDD
Signal Descriptions and Pin Assignments
5-37
Power
Bank
Pull-up /Pull Strength
/Open Drain
Alternate
Pull-up/Pull Strength/Open Drain2
Primary
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
Table 5-2. i.MX27 Pin MUX Table (continued)
Freescale Semiconductor
QVDD6
QVDD7
Supply
QVSS7
static
QVSS7
QVDD7
Supply
QVDD7
static
QVDD7
QVDD8
Supply
QVSS8
static
QVSS8
QVDD8
Supply
QVDD8
static
QVDD8
RTCVDD
Supply
RTCVSS
static
RTCVSS
RTCVDD
Supply
RTCVDD
static
RTCVDD
UPLLVDD
Supply
UPLLVDD
static
UPLLVDD
UPLLVDD
Supply
UPLLVSS
static
UPLLVSS
Indicates direction of primary signal. It may not indicate the direction of the pin as it may be dependent on other functions.
KP = Keeper Circuit permanently On when in Primary/Alternate Mode; PU = Pull Up permanently On when in Primary/Alternate Mode; PUEN = Pull
Up controllable from Module when in Primary/Alternate Mode; OD = Open Drain permanently On when in Primary/Alternate Mode; ODEN = Open
Drain controllable from Module when in Primary/Alternate Mode.
3 Pin mux with GPIO has its Pull Up controlled by the GPIO PUEN register (in Primary, Alternate, or GPIO Mode)
2
Default
static
BOUT
QVDD6
AOUT
Supply
CIN
QVDD6
BIN
QVSS6
AIN
static
PUEN/PDEN
QVSS6
Mux3
Direction1
Supply
Direction2
Signal/Pad Name
QVDD6
Signal
I/O Type
Pull-up /Pull Strength
/Open Drain
GPIO
Power
Bank
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
1
Alternate
Pull-up/Pull Strength/Open Drain2
Primary
Signal Descriptions and Pin Assignments
5-38
Table 5-2. i.MX27 Pin MUX Table (continued)
Chapter 6
General-Purpose I/O (GPIO)
6.1
Introduction
The GPIO module in i.MX27 processor provides six general purpose I/O (GPIO) ports (PA, PB, PC, PD,
PE, and PF). Each GPIO port is a 32-bit port that may be multiplexed with one or more dedicated
functions.
This chapter contains the description of the top level i.MX27 I/O multiplexing strategy that consists of two
parts:
• Software controllable multiplexing done in the GPIO module
• Hardware multiplexing done by the IOMUX module
The I/O multiplexing strategy is designed to configure the inputs and outputs of the BONO Device chip in
different modes. It allows a user to use the same I/O pad for alternative purposes of the chip. The design
of I/O multiplexer is targeted to be as flexible as possible. Refer to Chapter 5, “Signal Descriptions and
Pin Assignments,” for detailed I/O multiplexing information.
Figure 6-1 shows the block diagram of the GPIO and IOMUX modules’ partition at the top level of the
BONO processor. Figure 6-2 shows a block diagram of an individual port of the GPIO module.
NOTE
A_IN, B_IN, C_IN, A_OUT, and B_OUT are internal signals and do not
represent individual port signals.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
6-1
General-Purpose I/O (GPIO)
IOMUX (Part of GPIO)
Primary Function
1
GP
GOUT
A_IN
B_IN
0
1
MUX
Alternate Function
MUX
0
GPIO
INUSE
Pin
I/O
0
GDIR
1
MUX
C_IN
A_OUT
B_OUT
PUEN
GIN
Figure 6-1. Functional Block Diagram of GPIO
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
6-2
Freescale Semiconductor
General-Purpose I/O (GPIO)
OCR1
OCR2
DDIR[i]
G_DIR[31:0]
A_IN[i]
G_DIR[i]
G_OUT[i]
MUX
B_IN[i]
C_IN[i]
PAD
i
G_IN[i]
DR
ICONFA1
SSR
MUX
ICONFA2
A_OUT[i]
ISR[i]
1’b0
1’b1
Interrupt
Module
ISR
MUX
ICONFB1
ICONFB2
B_OUT[i]
ISR[i]
1’b0
1’b1
ICR1
ICR2
IMR
GP
IN_USE_RESET_SEL [31:0]
GPR[31:0]
GIUS
IN_USE[31:0]
PUEN
PUEN[31:0]
Figure 6-2. GPIO Block Diagram for an Individual Port
6.2
Overview
The GPIO module provides General Purpose I/O capability to the device. Each I/O port can be
programmed as either a general purpose input or general purpose output. In addition to GPIO functionality,
pins can be changed from their default dedicated functions to alternate functions. Input and output signals
of peripherals are connected to the IOMUX module at the dedicated (primary) or alternate inputs. In the
output direction, one out of three alternate sources (originating from peripherals) can be selected. From the
input direction, one out of two alternate destinations (input to a peripheral) can be selected.
6.3
GPIO Features
The following list contains the GPIO features:
• Six 32-bit ports, each with direction-configurable pins
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
6-3
General-Purpose I/O (GPIO)
•
•
•
•
•
•
•
•
•
•
6.4
Software control for input/output pin configuration through 32-bit direction register
Software control for multiplexing one out of four different sources for every output. Three of them
are functional pins from internal modules while the fourth is from the data register of the module.
Software control for routing of every input to two different destinations
Input data can be sampled to the data register.
Inputs can be internally tied to a logic 1 or 0 to ensure any transitions attempted to be processed
are ignored.
One 32-bit general purpose register is dedicated to each GPIO port. These registers may be used
for software control of IOMUX block of the GPIO.
Every input is configurable as an interrupt and each interrupt can be defined as either:
— Rising-edge triggered
— Falling-edge triggered
— Level sensitive
The interrupts can be masked using a 32-bit mask register.
Two levels of interrupt masking are provided. Interrupts can be individually masked at the bit level
or at the port level.
Software reset function: when the SWR bit (SWR register, 0 bit) is written as a 1, the entire GPIO
module is reset immediately, and this reset signal is asserted for three system cycles. After this, the
reset signal will be released automatically.
External Signals Description
Refer to Chapter 5, “Signal Descriptions and Pin Assignments” for details on the I/O multiplexing scheme
and external connection to the GPIO module.
6.5
Interrupts
Every external input passes through the interrupt module in the GPIO module. Inside this module, the
interrupts may be defined as rising-edge triggered, or falling-edge triggered. Each interrupt can be masked
and also be designated as a high-level interrupt, or a low-level sensitive interrupt. The interrupt status
register bits corresponding to the interrupts waiting for service are stored as a value of 1. The interrupt
status register is Write 1 to Clear (w1c). The user is responsible for clearing the interrupt status register bit
after it has been serviced.
6.6
Memory Map and Register Definitions
The GPIO module has six ports and each port has 17 registers. In total, the GPIO has 102 registers. The
registers, other than the Sample Status Register (SSR) and the Interrupt Status Register (ISR), have both
read and write capability. The Sample Status Register is a read only register, while the Interrupt Status
Register is a w1c register; the register can be read, but writing a 1 to any register bit clears the bit. Writing
a value of 0 to the bit has no effect.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
6-4
Freescale Semiconductor
General-Purpose I/O (GPIO)
While there are six GPIO ports, each capable of representing 32 GPIO configurable pins as inputs or
outputs, not all bits are mapped to a pin and hence these bits do not have any effect and are marked as
reserved. These reserved bits are indicated in Section 6.6.10, “GPIO IN USE Registers (GIUS).”
Table 6-1 shows the GPIO memory map.
Table 6-1. GPIO Memory Map
Address
Register
Access
Reset Value
Section/Page
General Registers
0x1001_5000 (PTA_DDIR)
Data Direction Register
R/W
0x0000_0000
6.6.2/6-9
0x1001_5100 (PTB_DDIR)
Data Direction Register
R/W
0x0000_0000
6.6.2/6-9
0x1001_5200 (PTC_DDIR)
Data Direction Register
R/W
0x0000_0000
6.6.2/6-9
0x1001_5300 (PTD_DDIR)
Data Direction Register
R/W
0x0000_0000
6.6.2/6-9
0x1001_5400 (PTE_DDIR)
Data Direction Register
R/W
0x0000_0000
6.6.2/6-9
0x1001_5500 (PTF_DDIR)
Data Direction Register
R/W
0x0000_0000
6.6.2/6-9
0x1001_5004 (PTA_OCR1)
Output Configuration Register 1)
R/W
0x0000_0000
6.6.3/6-10
0x1001_5104 (PTB_OCR1)
Output Configuration Register 1
R/W
0x0000_0000
6.6.3/6-10
0x1001_5204 (PTC_OCR1)
Output Configuration Register 1)
R/W
0x0000_0000
6.6.3/6-10
0x1001_5304 (PTD_OCR1)
Output Configuration Register 1
R/W
0x0000_0000
6.6.3/6-10
0x1001_5404 (PTE_OCR1)
Output Configuration Register 1
R/W
0x0000_0000
6.6.3/6-10
0x1001_5504 (PTF_OCR1)
Output Configuration Register 1
R/W
0x0000_0000
6.6.3/6-10
0x1001_5008 (PTA_OCR2)
Output Configuration Register 2
R/W
0x0000_0000
6.6.4/6-11
0x1001_5108 (PTB_OCR2)
Output Configuration Register 2
R/W
0x0000_0000
6.6.4/6-11
0x1001_5208 (PTC_OCR2)
Output Configuration Register 2
R/W
0x0000_0000
6.6.4/6-11
0x1001_5308 (PTD_OCR2)
Output Configuration Register 2
R/W
0x0000_0000
6.6.4/6-11
0x1001_5408 (PTE_OCR2)
Output Configuration Register 2
R/W
0x0000_0000
6.6.4/6-11
0x1001_5508 (PTF_OCR2)
Output Configuration Register 2
R/W
0x0000_0000
6.6.4/6-11
0x1001_500C (PTA_ICONFA1)
Input Configuration Register A1
R/W
0xFFFF_FFFF
6.6.5/6-12
0x1001_510C (PTB_ICONFA1)
Input Configuration Register A1
R/W
0xFFFF_FFFF
6.6.5/6-12
0x1001_520C (PTC_ICONFA1)
Input Configuration Register A1
R/W
0xFFFF_FFFF
6.6.5/6-12
0x1001_530C (PTD_ICONFA1)
Input Configuration Register A1
R/W
0xFFFF_FFFF
6.6.5/6-12
0x1001_540C (PTE_ICONFA1)
Input Configuration Register A1
R/W
0xFFFF_FFFF
6.6.5/6-12
0x1001_550C (PTF_ICONFA1)
Input Configuration Register A1
R/W
0xFFFF_FFFF
6.6.5/6-12
0x1001_5010 (PTA_ICONFA2)
Input Configuration Register A2
R/W
0xFFFF_FFFF
6.6.6/6-13
0x1001_5110 (PTB_ICONFA2)
Input Configuration Register A2
R/W
0xFFFF_FFFF
6.6.6/6-13
0x1001_5210 (PTC_ICONFA2)
Input Configuration Register A2
R/W
0xFFFF_FFFF
6.6.6/6-13
0x1001_5310 (PTD_ICONFA2)
Input Configuration Register A2
R/W
0xFFFF_FFFF
6.6.6/6-13
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
6-5
General-Purpose I/O (GPIO)
Table 6-1. GPIO Memory Map (continued)
Address
Register
Access
Reset Value
Section/Page
0x1001_5410 (PTE_ICONFA2)
Input Configuration Register A2
R/W
0xFFFF_FFFF
6.6.6/6-13
0x1001_5510 (PTF_ICONFA2)
Input Configuration Register A2
R/W
0xFFFF_FFFF
6.6.6/6-13
0x1001_5014 (PTA_ICONFB1)
Input Configuration Register B1
R/W
0xFFFF_FFFF
6.6.7/6-14
0x1001_5114 (PTB_ICONFB1)
Input Configuration Register B1
R/W
0xFFFF_FFFF
6.6.7/6-14
0x1001_5214 (PTC_ICONFB1)
Input Configuration Register B1
R/W
0xFFFF_FFFF
6.6.7/6-14
0x1001_5314 (PTD_ICONFB1)
Input Configuration Register B1
R/W
0xFFFF_FFFF
6.6.7/6-14
0x1001_5414 (PTE_ICONFB1)
Input Configuration Register B1
R/W
0xFFFF_FFFF
6.6.7/6-14
0x1001_5514 (PTF_ICONFB1)
Input Configuration Register B1
R/W
0xFFFF_FFFF
6.6.7/6-14
0x1001_5018 (PTA_ICONFB2)
Input Configuration Register B2
R/W
0xFFFF_FFFF
6.6.8/6-15
0x1001_5118 (PTB_ICONFB2)
Input Configuration Register B2
R/W
0xFFFF_FFFF
6.6.8/6-15
0x1001_5218 (PTC_ICONFB2)
Input Configuration Register B2
R/W
0xFFFF_FFFF
6.6.8/6-15
0x1001_5318 (PTD_ICONFB2)
Input Configuration Register B2
R/W
0xFFFF_FFFF
6.6.8/6-15
0x1001_5418 (PTE_ICONFB2)
Input Configuration Register B2
R/W
0xFFFF_FFFF
6.6.8/6-15
0x1001_5518 (PTF_ICONFB2)
Input Configuration Register B2
R/W
0xFFFF_FFFF
6.6.8/6-15
0x1001_501C (PTA_DR)
Data Register
R/W
0x0000_0000
6.6.9/6-16
0x1001_511C (PTB_DR)
Data Register
R/W
0x0000_0000
6.6.9/6-16
0x1001_521C (PTC_DR)
Data Register
R/W
0x0000_0000
6.6.9/6-16
0x1001_531C (PTD_DR)
Data Register
R/W
0x0000_0000
6.6.9/6-16
0x1001_541C (PTE_DR)
Data Register
R/W
0x0000_0000
6.6.9/6-16
0x1001_551C (PTF_DR)
Data Register
R/W
0x0000_0000
6.6.9/6-16
0x1001_5020 (PTA_GIUS)
GPIO In Use Register A
R/W
0xFFFF_FFFF
6.6.11/6-17
0x1001_5120 (PTB_GIUS)
GPIO In Use Register B
R/W
0xFF3F_FFF3
6.6.11/6-17
0x1001_5220 (PTC_GIUS)
GPIO In Use Register C
R/W
0xFFFF_FFFF
6.6.11/6-17
0x1001_5320 (PTD_GIUS)
GPIO In Use Register D
R/W
0xFFFE_0000
6.6.11/6-17
0x1001_5420 (PTE_GIUS)
GPIO In Use Register E
R/W
0xFFFC_0F27
6.6.11/6-17
0x1001_5520 (PTF_GIUS)
GPIO In Use Register F
R/W
0xFF00_0000
6.6.11/6-17
0x1001_5024 (PTA_SSR)
Sample Status Register
R
0x0000_0000
6.6.12/6-21
0x1001_5124 (PTB_SSR)
Sample Status Register
R
0x0000_0000
6.6.12/6-21
0x1001_5224 (PTC_SSR)
Sample Status Register
R
0x0000_0000
6.6.12/6-21
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
6-6
Freescale Semiconductor
General-Purpose I/O (GPIO)
Table 6-1. GPIO Memory Map (continued)
Address
Register
Access
Reset Value
Section/Page
0x1001_5324 (PTD_SSR)
Sample Status Register
R
0x0000_0000
6.6.12/6-21
0x1001_5424 (PTE_SSR)
Sample Status Register
R
0x0000_0000
6.6.12/6-21
0x1001_5524 (PTF_SSR)
Sample Status Register
R
0x0000_0000
6.6.12/6-21
0x1001_5028 (PTA_ICR1)
Interrupt Configuration Register 1
R/W
0x0000_0000
6.6.13/6-22
0x1001_5128 (PTB_ICR1)
Interrupt Configuration Register 1
R/W
0x0000_0000
6.6.13/6-22
0x1001_5228 (PTC_ICR1)
Interrupt Configuration Register 1
R/W
0x0000_0000
6.6.13/6-22
0x1001_5328 (PTD_ICR1)
Interrupt Configuration Register 1
R/W
0x0000_0000
6.6.13/6-22
0x1001_5428 (PTE_ICR1)
Interrupt Configuration Register 1
R/W
0x0000_0000
6.6.13/6-22
0x1001_5528 (PTF_ICR1)
Interrupt Configuration Register 1
R/W
0x0000_0000
6.6.13/6-22
0x1001_502C (PTA_ICR2)
Interrupt Configuration Register 2
R/W
0x0000_0000
6.6.14/6-23
0x1001_512C (PTB_ICR2)
Interrupt Configuration Register 2
R/W
0x0000_0000
6.6.14/6-23
0x1001_522C (PTC_ICR2)
Interrupt Configuration Register 2
R/W
0x0000_0000
6.6.14/6-23
0x1001_532C (PTD_ICR2)
Interrupt Configuration Register 2
R/W
0x0000_0000
6.6.14/6-23
0x1001_542C (PTE_ICR2)
Interrupt Configuration Register 2
R/W
0x0000_0000
6.6.14/6-23
0x1001_552C (PTF_ICR2)
Interrupt Configuration Register 2
R/W
0x0000_0000
6.6.14/6-23
0x1001_5030 (PTA_IMR)
Interrupt Mask Register
R/W
0x0000_0000
6.6.15/6-24
0x1001_5130 (PTB_IMR)
Interrupt Mask Register
R/W
0x0000_0000
6.6.15/6-24
0x1001_5230 (PTC_IMR)
Interrupt Mask Register
R/W
0x0000_0000
6.6.15/6-24
0x1001_5330 (PTD_IMR)
Interrupt Mask Register
R/W
0x0000_0000
6.6.15/6-24
0x1001_5430 (PTE_IMR)
Interrupt Mask Register
R/W
0x0000_0000
6.6.15/6-24
0x1001_5530 (PTF_IMR)
Interrupt Mask Register
R/W
0x0000_0000
6.6.15/6-24
0x1001_5034 (PTA_ISR)
Interrupt Status Register
R/W
0x0000_0000
6.6.16/6-25
0x1001_5134 (PTB_ISR)
Interrupt Status Register
R/W
0x0000_0000
6.6.16/6-25
0x1001_5234 (PTC_ISR)
Interrupt Status Register
R/W
0x0000_0000
6.6.16/6-25
0x1001_5334 (PTD_ISR)
Interrupt Status Register
R/W
0x0000_0000
6.6.16/6-25
0x1001_5434 (PTE_ISR)
Interrupt Status Register
R/W
0x0000_0000
6.6.16/6-25
0x1001_5534 (PTF_ISR)
Interrupt Status Register
R/W
0x0000_0000
6.6.16/6-25
0x1001_5038 (PTA_GPR)
General Purpose Register
R/W
0x0000_0000
6.6.17/6-26
0x1001_5138 (PTB_GPR)
General Purpose Register
R/W
0x0000_0000
6.6.17/6-26
0x1001_5238 (PTC_GPR)
General Purpose Register
R/W
0x0000_0000
6.6.17/6-26
0x1001_5338 (PTD_GPR)
General Purpose Register
R/W
0x0000_0000
6.6.17/6-26
0x1001_5438 (PTE_GPR)
General Purpose Register
R/W
0x0000_0000
6.6.17/6-26
0x1001_5538 (PTF_GPR)
General Purpose Register
R/W
0x0000_0000
6.6.17/6-26
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
6-7
General-Purpose I/O (GPIO)
Table 6-1. GPIO Memory Map (continued)
Address
Register
Access
Reset Value
Section/Page
0x1001_503C (PTA_SWR)
Software Reset Register
R
0x0000_0000
6.6.18/6-27
0x1001_513C (PTB_SWR)
Software Reset Register
R
0x0000_0000
6.6.18/6-27
0x1001_513C (PTB_SWR)
Software Reset Register
R
0x0000_0000
6.6.18/6-27
0x1001_533C (PTD_SWR)
Software Reset Register
R
0x0000_0000
6.6.18/6-27
0x1001_543C (PTE_SWR)
Software Reset Register
R
0x0000_0000
6.6.18/6-27
0x1001_553C (PTF_SWR)
Software Reset Register
R
0x0000_0000
6.6.18/6-27
0x1001_5040 (PTA_PUEN)
Pull-Up Enable Register
R/W
0xFFFF_FFFF
6.6.19/6-28
0x1001_5140 (PTB_PUEN)
Pull-Up Enable Register
R/W
0xFFFF_FFFF
6.6.19/6-28
0x1001_5240 (PTC_PUEN)
Pull-Up Enable Register
R/W
0xFFFF_FFFF
6.6.19/6-28
0x1001_5340 (PTD_PUEN)
Pull-Up Enable Register
R/W
0xFFFF_FFFF
6.6.19/6-28
0x1001_5440 (PTE_PUEN)
Pull-Up Enable Register
R/W
0xFFFF_FFFF
6.6.19/6-28
0x1001_5540 (PTF_PUEN)
Pull-Up Enable Register
R/W
0xFFFF_FFFF
6.6.19/6-28
0x1001_5600 (PMASK)
Port Interrupt Mask Register
R/W
0x0000_003F
6.6.20/6-29
6.6.1
Register Summary
The conventions in Figure 6-3 and Table 6-2 serve as a key for the register summary and individual register
diagrams.
Always
reads 1
1
Always
reads 0
0
R/W BIT Read- BIT WriteWrite 1 BIT Self-clear 0
bit
only bit
only bit BIT to clear w1c
bit BIT
N/A
Figure 6-3. Key to Register Fields
Table 6-2 provides a key for register figures and tables and the register summary.
Table 6-2. Register Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writable.
FIELDNAME
Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
R
Read only. Writing this bit has no effect.
W
Write only.
R/W
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by a hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
Self-clearing bit Writing a one has some effect on the module, but it always reads as zero. (Previously designated slfclr)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
6-8
Freescale Semiconductor
General-Purpose I/O (GPIO)
Table 6-2. Register Conventions (continued)
Convention
Description
Reset Values
0
Resets to zero.
1
Resets to one.
—
Undefined at reset.
u
Unaffected by reset.
[signal_name]
6.6.2
Reset value is determined by polarity of indicated signal.
Data Direction Register (PTn_DDIR)
The Data Direction registers determine whether each port pin operates as an input or an output pin.
Figure 6-4 shows the register and Table 6-3 provides its field descriptions.
Access: User R/W
0x1001_5000 (PTA_DDIR)
0x1001_5100 (PTB_DDIR)
0x1001_5200 (PTC_DDIR)
0x1001_5300 (PTD_DDIR)
0x1001_5400 (PTE_DDIR)
0x1001_5500 (PTF_DDIR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
DDIR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
DDIR
W
Reset
0
0
0
0
0
0
0
0
0
Figure 6-4. Data Direction Register (PTn_DDIR)
Table 6-3. Data Direction Register Field Descriptions
Field
Description
31–0
DDIR
Data Direction. This is a read/write register that defines the current direction of the 32 pins of a port in the GPIO
module.
0 Pin operates as an input.
1 Pin operates as an output.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
6-9
General-Purpose I/O (GPIO)
6.6.3
Output Configuration Register 1 (OCR1)
Each port consists of 32-pins. Because the output configuration for each pin is described using a two-bit
combination the output configuration of the pins is controlled by two identical 32-bit registers (OCR1 and
OCR2). The Output Configuration register 1 (OCR1) configures the output signal for lower 16 pins (0–15)
of the associated port. Figure 6-5 shows the register and Table 6-4 provides its field descriptions.
Access: User R/W
0x1001_5004 (PTA_OCR1)
0x1001_5104 (PTB_OCR1)
0x1001_5204 (PTC_OCR1)
0x1001_5304 (PTD_OCR1)
0x1001_5404 (PTE_OCR1)
0x1001_5504 (PTF_OCR1)
31
30
29
28
27
26
25
24
R
PIN 15
PIN 14
PIN 13
PIN 12
21
20
19
18
17
16
PIN 11
PIN 10
PIN 9
PIN 8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
OCR1
W
Reset
22
OCR1
W
Reset
23
PIN 7
0
PIN 6
0
0
PIN 5
0
0
0
PIN 4
0
PIN 3
0
0
PIN 2
0
0
PIN 1
0
0
PIN 0
0
0
0
Figure 6-5. Output Configuration Register 1 (OCR1)
Table 6-4. Output Configuration Register 1 Field Descriptions
Field
Description
31–0
OCR1
Output Configuration Register 1. Each field selects how each pin (0–15) is used as an output by the GPIO.
00 Input A_IN output selected.
01 Input B_IN output selected.
10 Input C_IN output selected.
11 Data Register output selected.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
6-10
Freescale Semiconductor
General-Purpose I/O (GPIO)
6.6.4
Output Configuration Register 2 (OCR2)
The Output Configuration register 2 (OCR2) specifies the output signal for upper 16 pins (16–31) of the
associated port. The output configuration for each pin is described with a two-bit combination. Figure 6-6
shows the register and Table 6-5 provides its field descriptions.
Access: User R/W
0x1001_5008 (PTA_OCR2)
0x1001_5108 (PTB_OCR2)
0x1001_5208 (PTC_OCR2)
0x1001_5308 (PTD_OCR2)
0x1001_5408 (PTE_OCR2)
0x1001_5508 (PTF_OCR2)
31
30
29
28
27
26
25
24
R
PIN 31
PIN 30
PIN 29
PIN 28
21
20
19
18
17
16
PIN 27
PIN 26
PIN 25
PIN 24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
OCR2
W
Reset
22
OCR2
W
Reset
23
PIN 23
0
PIN 22
0
0
0
PIN 21
0
0
PIN 20
0
0
PIN 19
0
0
PIN 18
0
0
PIN 17
0
0
PIN 16
0
0
Figure 6-6. Output Configuration Register 2 (OCR2)
Table 6-5. Output Configuration Register 2 Field Descriptions
Field
Description
31–0
OCR2
Output Configuration Register 2. Each field selects how each pin (16–31) is used as an output by the GPIO.
00 Input A_IN output selected.
01 Input B_IN output selected.
10 Input C_IN output selected.
11 Data Register output selected.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
6-11
General-Purpose I/O (GPIO)
6.6.5
Input Configuration Register A1 (ICONFA1)
The input configuration registers (ICONFA1) specify the signal or value driven to the A_OUT signals that
is connected to internal modules of the BONO Device processor. Each port pin is defined by two bits in
the input configuration registers. Figure 6-7 shows the register and Table 6-6 provides its field
descriptions.
Access: User R/W
0x1001_500C (PTA_ICONFA1)
0x1001_510C (PTB_ICONFA1)
0x1001_520C (PTC_ICONFA1)
0x1001_530C (PTD_ICONFA1)
0x1001_540C (PTE_ICONFA1)
0x1001_550C (PTF_ICONFA1)
31
30
29
28
27
26
25
24
R
W
Reset
22
21
20
19
18
17
16
ICONFA1
PIN 15
PIN 14
PIN 13
PIN 12
PIN 11
PIN 10
PIN 9
PIN 8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
ICONFA1
W
Reset
23
PIN 7
1
PIN 6
1
1
PIN 5
1
1
1
PIN 4
1
PIN 3
1
1
PIN 2
1
1
PIN 1
1
1
PIN 0
1
1
1
Figure 6-7. Input Configuration Register A1 (ICONFA1)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
6-12
Freescale Semiconductor
General-Purpose I/O (GPIO)
Table 6-6. Input Configuration Register A1 Field Descriptions
Field
Description
31–0
ICONFA1
6.6.6
Input Configuration. Corresponds to port pins 0–15 and defines which one of the four options is driven to
A_OUT. Each port pin requires two ICONFA1 bits to determine the input value.
00 GPIO_In
01 Interrupt Status Register
10 0
11 1
Input Configuration Register A2 (ICONFA2)
The input configuration registers (ICONFA2) specify the signal or value driven to the A_OUT signals
connected to internal modules. There are two bits in the input configuration registers for each port pin.
Figure 6-8 shows the register and Table 6-7 provides its field descriptions.
Access: User R/W
0x1001_5010 (PTA_ICONFA2)
0x1001_5110 (PTB_ICONFA2)
0x1001_5210 (PTC_ICONFA2)
0x1001_5310 (PTD_ICONFA2)
0x1001_5410 (PTE_ICONFA2)
0x1001_5510 (PTF_ICONFA2)
31
30
29
28
27
26
25
24
R
W
Reset
Reset
22
21
20
19
18
17
16
ICONFA2
PIN 31
PIN 30
PIN 29
PIN 28
PIN 27
PIN 26
PIN 25
PIN 24
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
23
ICONFA2
PIN 23
1
PIN 22
1
1
1
PIN 21
1
1
PIN 20
1
1
PIN 19
1
1
PIN 18
1
1
PIN 17
1
1
PIN 16
1
1
Figure 6-8. Input Configuration Register A2 (ICONFA2)
Table 6-7. Input Configuration Register A2 Field Descriptions
Field
31–0
ICONFA2
Description
Input Configuration. Corresponds to port pins 16–31 and defines which one of the four options is driven to
A_OUT. Each port pin requires two ICONFA2 bits to determine the input value.
00 GPIO_In
01 Interrupt Status Register
10 0
11 1
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
6-13
General-Purpose I/O (GPIO)
6.6.7
Input Configuration Register B1 (ICONFB1)
The input configuration registers ICONFB1 specify the signal or value driven to the B_OUT signals
connected to internal modules. There are two bits in the input configuration registers for each port pin.
Figure 6-9 shows the register and Table 6-8 provides its field descriptions.
Access: User R/W
0x1001_5014 (PTA_ICONFB1)
0x1001_5114 (PTB_ICONFB1)
0x1001_5214 (PTC_ICONFB1)
0x1001_5314 (PTD_ICONFB1)
0x1001_5414 (PTE_ICONFB1)
0x1001_5514 (PTF_ICONFB1)
31
30
29
28
27
26
25
24
R
W
Reset
22
21
20
19
18
17
16
ICONFB1
PIN 15
PIN 14
PIN 13
PIN 12
PIN 11
PIN 10
PIN 9
PIN 8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
ICONFB1
W
Reset
23
PIN 7
1
PIN 6
1
1
PIN 5
1
1
1
PIN 4
1
PIN 3
1
1
PIN 2
1
1
PIN 1
1
1
PIN 0
1
1
1
Figure 6-9. Input Configuration Register B1 (ICONFB1)
Table 6-8. Input Configuration Register B1 Field Descriptions
Name
Description
31–0
ICONFB1
Input Configuration. Corresponds to pins 0–15 of the port and defines which one of the four options is
driven to b_OUT. Each port pin requires two ICONFB1 bits to determine the input value.
00 GPIO_IN
01 Interrupt Status register
10 0
11 1
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
6-14
Freescale Semiconductor
General-Purpose I/O (GPIO)
6.6.8
Input Configuration Register B2 (ICONFB2)
The input configuration registers ICONFB2 specify the signal or value driven to the B_OUT signals
connected to internal modules. There are two bits in the input configuration registers for each port pin.
Figure 6-10 shows the register and Table 6-9 provides its field descriptions.
Access: User R/W
0x1001_5018 (PTA_ICONFB2)
0x1001_5118 (PTB_ICONFB2)
0x1001_5218 (PTC_ICONFB2)
0x1001_5318 (PTD_ICONFB2)
0x1001_5418 (PTE_ICONFB2)
0x1001_5518 (PTF_ICONFB2)
31
30
29
28
27
26
25
24
R
W
Reset
Reset
22
21
20
19
18
17
16
ICONFB2
PIN 31
PIN 30
PIN 29
PIN 28
PIN 27
PIN 26
PIN 25
PIN 24
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
23
ICONFB2
PIN 23
1
PIN 22
1
1
1
PIN 21
1
1
PIN 20
1
1
PIN 19
1
1
PIN 18
1
1
PIN 17
1
1
PIN 16
1
1
Figure 6-10. Input Configuration Register B1 (ICONFB2)
Table 6-9. Input Configuration Register B2 Description
Name
Description
31–0
ICONFB2
Input Configuration. Corresponds to pins 16–31 of the port and defines which one of the four options
is driven to b_OUT. Each port pin requires two ICONFB2 bits to determine the input value.
00 GPIO_IN
01 Interrupt Status register
10 0
11 1
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
6-15
General-Purpose I/O (GPIO)
6.6.9
Data Register (DR)
The Data Register holds data for output from an associated port when a pin is configured as an output and
the Data Register is chosen using Output Configuration Register 1 and Output Configuration Register 2.
Figure 6-11 shows the register and Table 6-10 provides its field descriptions.
Access: User R/W
0x1001_501C (PTA_DR)
0x1001_511C (PTB_DR)
0x1001_521C (PTC_DR)
0x1001_531C (PTD_DR)
0x1001_541C (PTE_DR)
0x1001_551C (PTF_DR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
DR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
DR
W
Reset
0
0
0
0
0
0
0
0
Figure 6-11. Data Register (DR)
Table 6-10. Data Register Field Descriptions
Field
31–0
DR
Description
Data Register. Contains the GPIO output values when the Output Configuration Registers select the Data
Register as the output for the pin (selection 11).
0 Drives the output signal is low.
1 Drives the output signal is high.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
6-16
Freescale Semiconductor
General-Purpose I/O (GPIO)
6.6.10
GPIO IN USE Registers (GIUS)
The GPIO In Use Registers control a multiplexer in the IOMUX module. The settings in these registers
choose whether a pin is utilized for a peripheral function or for its GPIO function. If the register is set to
a zero for a corresponding pin, then this register is used in conjunction with the GPR register to control the
peripheral functionality. Figure 6-12 shows a GIUS overview register and Table 6-11 provides field
descriptions of the GIUS registers. Reset values for individual registers are shown in the following
sections.
Access: User R/W
0x1001_5020 (PTA_GIUS)
0x1001_5120 (PTB_GIUS)
0x1001_5220 (PTC_GIUS)
0x1001_5320 (PTD_GIUS)
0x1001_5420 (PTE_GIUS)
0x1001_5520 (PTF_GIUS)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
GIUS
W
Reset1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
GIUS
W
Reset1
—
—
—
—
—
—
—
—
—
1 The reset value of this register is determined by the input value of the signal INUSE_RESET_SEL [31:0].
Figure 6-12. GPIO IN USE Register (GIUS)
Table 6-11. GPIO In Use Register Field Descriptions
Field
Description
31–0
GIUS
GPIO In Use. Informs the IOMUX module whether the port pin is utilized for its GPIO function. When the pin
is utilized for its GPIO function, the multiplexed functions are not available.
The reset value of this register is determined by the input value of the signal INUSE_RESET_SEL [31:0].
0 Pin utilized for multiplexed function
1 Pin utilized for GPIO function
6.6.11
GPIO IN USE Register Reset Values
The following sections describe the GPIO In Use (GIUS) reset values for the various ports. Additionally,
the registers also indicate the reserved bits (unimplemented GPIO bits) of the GPIO ports.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
6-17
General-Purpose I/O (GPIO)
6.6.11.1
GPIO IN USE Register A (PTA_GIUS)
The reset value of the PTA_GIUS register is (0xFFFF_FFFF). Figure 6-13 shows the register.
0x1001_5020 (PTA_GIUS)
31
30
29
28
Access: User R/W
27
26
25
24
23
22
21
20
19
18
17
16
R
GIUS
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
R
GIUS
W
Reset
1
1
1
1
1
1
1
1
1
Figure 6-13. GPIO IN USE Register A Reset Values (PTA_GIUS)
6.6.11.2
GPIO IN USE Register B (PTB_GIUS)
The reset value of the PTB_GIUS register is (0xFF3F_FFF3). Figure 6-14 shows the register.
0x1001_5120 (PTB_GIUS)
31
30
29
28
Access: User R/W
27
26
25
24
23
22
21
20
19
18
17
16
R
GIUS
W
Reset
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
R
GIUS
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
0
0
Figure 6-14. GPIO IN USE Register B Reset Values (PTB_GIUS)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
6-18
Freescale Semiconductor
General-Purpose I/O (GPIO)
6.6.11.3
GPIO IN USE Register C (PTC_GIUS)
The reset value of the PTC_GIUS register is (0xFFFF_FFFF). Figure 6-15 shows the register.
0x1001_5220 (PTC_GIUS)
31
30
29
28
Access: User R/W
27
26
25
24
23
22
21
20
19
18
17
16
R
GIUS
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
R GIUS
W
Reset
1
1
1
1
1
1
1
1
1
1
1
Figure 6-15. GPIO IN USE Register C Reset Values (PTC_GIUS)
6.6.11.4
GPIO IN USE Register D (PTD_GIUS)
The reset value of the PTD_GIUS register is (0xFFFE_0000). Figure 6-16 shows the register.
0x1001_5320 (PTD_GIUS)
31
30
29
28
Access: User R/W
27
26
25
24
23
22
21
20
19
18
17
16
R
GIUS
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
GIUS
W
Reset
0
0
0
0
0
0
0
0
0
Figure 6-16. GPIO IN USE Register D Reset Values (PTD_GIUS)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
6-19
General-Purpose I/O (GPIO)
6.6.11.5
GPIO IN USE Register E (PTE_GIUS)
The reset value of the PTE_GIUS register is (0xFFFC_0F27). Figure 6-17 shows the register.
0x1001_5420 (PTE_GIUS)
31
30
29
28
Access: User R/W
27
26
R
25
24
1
1
23
22
21
GIUS
20
19
18
17
16
GIUS
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
GIUS
W
Reset
0
0
0
0
0
0
0
0
0
Figure 6-17. GPIO IN USE Register E Reset Values (PTE_GIUS)
6.6.11.6
GPIO IN USE Register F (PTF_GIUS)
The reset value of the PTF_GIUS register is (0xFF00_0000). Figure 6-17 shows the register.
0x1001_5520 (PTF_GIUS)
R
Access: User R/W
31
30
29
28
27
26
25
24
23
1
1
1
1
1
1
1
1
0
22
21
20
19
18
17
16
GIUS
W
Reset
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
GIUS
W
Reset
0
0
0
0
0
0
0
0
0
Figure 6-18. GPIO IN USE Register F Reset Values (PTF_GIUS)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
6-20
Freescale Semiconductor
General-Purpose I/O (GPIO)
6.6.12
Sample Status Register (SSR)
The read-only Sample Status Registers contain the value of the GPIO pins for each associated port. The
register is updated on every clock tick. The contents are used as a status indicator when the pins are
configured as inputs. Figure 6-19 shows the register and Table 6-12 provides its field descriptions.
Access: User read-only
0x1001_5024 (PTA_SSR)
0x1001_5124 (PTB_SSR)
0x1001_5224 (PTC_SSR)
0x1001_5324 (PTD_SSR)
0x1001_5424 (PTE_SSR)
0x1001_5524 (PTF_SSR)
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
SSR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
SSR
W
Reset
0
0
0
0
0
0
0
0
Figure 6-19. Sample Status Register (SSR)
Table 6-12. Sample Status Register Field Descriptions
Field
31–0
SSR
Description
Sample Status. Contains the value of the GPIO pin [i]. It is sampled on every clock.
0 Pin value is low.
1 Pin value is high.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
6-21
General-Purpose I/O (GPIO)
6.6.13
Interrupt Configuration Register 1 (ICR1)
This register specifies the external interrupt configuration for each of the lower 16 interrupts of a port.
There are two bits in the register for each port pin. Figure 6-20 shows the register and Table 6-13 provides
its field descriptions.
Access: User R/W
0x1001_5028 (PTA_ICR1)
0x1001_5128 (PTB_ICR1)
0x1001_5228 (PTC_ICR1)
0x1001_5328 (PTD_ICR1)
0x1001_5428 (PTE_ICR1)
0x1001_5528 (PTF_ICR1)
31
30
29
28
27
26
25
24
R
W
Reset
22
21
20
19
18
17
16
ICR1
PIN 15
PIN 14
PIN 13
PIN 12
PIN 11
PIN 10
PIN 9
PIN 8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
ICR1
W
Reset
23
PIN 7
0
PIN 6
0
0
PIN 5
0
0
0
PIN 4
0
PIN 3
0
0
PIN 2
0
0
PIN 1
0
0
PIN 0
0
0
0
Figure 6-20. Interrupt Configuration Register 1 (ICR1)
Table 6-13. Interrupt Configuration Register 1 Field Descriptions
Field
31–0
ICR1
Description
Interrupt Configuration. Corresponds to interrupts 0–15 of the port and defines which one of the four
options is the sensitivity of the interrupt. Each interrupt [i] (i= 0 through 15) requires two ICR1 bits to
determine the sensitivity.
00 Rising edge sensitive
01 Falling edge sensitive
10 High level sensitive
11 Low level sensitive
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
6-22
Freescale Semiconductor
General-Purpose I/O (GPIO)
6.6.14
Interrupt Configuration Register 2 (ICR2)
This register specify the external interrupt configuration for each of the upper 16 interrupts of the port.
There are two bits in the register for each port pin. Figure 6-21 shows the register and Table 6-14 provides
its field descriptions.
Access: User R/W
0x1001_502C (PTA_ICR2)
0x1001_512C (PTB_ICR2)
0x1001_522C (PTC_ICR2)
0x1001_532C (PTD_ICR2)
0x1001_542C (PTE_ICR2)
0x1001_552C (PTF_ICR2)
31
30
29
28
27
26
25
24
R
W
Reset
Reset
22
21
20
19
18
17
16
ICR2
PIN 31
PIN 30
PIN 29
PIN 28
PIN 27
PIN 26
PIN 25
PIN 24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
23
ICR2
PIN 23
0
PIN 22
0
0
0
PIN 21
0
0
PIN 20
0
0
PIN 19
0
0
PIN 18
0
0
PIN 17
0
0
PIN 16
0
0
Figure 6-21. Interrupt Configuration Register 2 (ICR2)
Table 6-14. Interrupt Configuration Register 2 Field Descriptions
Field
Description
31–0
ICR2
Interrupt Configuration. Corresponds to interrupts 16–31 of the port and defines which one of the four
options is the sensitivity of the interrupt. Each interrupt requires two ICR2 bits to determine the sensitivity.
00 Rising edge sensitive
01 Falling edge sensitive
10 High level sensitive
11 Low level sensitive
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
6-23
General-Purpose I/O (GPIO)
6.6.15
Interrupt Mask Register (IMR)
The Interrupt Mask Registers (IMR) determine if an interrupt will be asserted when an interrupt event
occurs and when the pin and corresponding bit is configured in an interrupt mode. An interrupt is asserted
when corresponding bits in the IMR and ISR are set. Figure 6-22 shows the register and Table 6-15
provides its field descriptions.
Access: User R/W
0x1001_5030 (PTA_IMR)
0x1001_5130 (PTB_IMR)
0x1001_5230 (PTC_IMR)
0x1001_5330 (PTD_IMR)
0x1001_5430 (PTE_IMR)
0x1001_5530 (PTF_IMR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
IMR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
IMR
W
Reset
0
0
0
0
0
0
0
0
Figure 6-22. Interrupt Mask Register (IMR)
Table 6-15. Interrupt Mask Register Description
Name
31–0
IMR
Description
Interrupt Mask. Masks the interrupts for this module.
0 Interrupt is masked.
1 Interrupt is not masked.
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6-24
Freescale Semiconductor
General-Purpose I/O (GPIO)
6.6.16
Interrupt Status Register (ISR)
The Interrupt Status Registers (ISR) indicate if an interrupt has occurred. When an interrupt event occurs,
the bit in this register is set. The condition necessary to set the bit is determined by the Interrupt
Configuration Registers (ICR) and the inputs satisfying the interrupt condition. Figure 6-23 shows the
register and Table 6-16 provides its field descriptions.
Access: User R/W
0x1001_5034 (PTA_ISR)
0x1001_5134 (PTB_ISR)
0x1001_5234 (PTC_ISR)
0x1001_5334 (PTD_ISR)
0x1001_5434 (PTE_ISR)
0x1001_5534 (PTF_ISR)
31
30
29
28
27
26
25
24
R
W
22
21
20
19
18
17
16
ISR
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
R
W
23
ISR
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Figure 6-23. Interrupt Status Register (ISR)
Table 6-16. Interrupt Status Register Field Descriptions
Field
Description
31–0
ISR
Interrupt Status. Indicates whether the interrupt [i] has occurred for in the GPIO module. The bits of this register
are write 1 to clear. The w1c bit is cleared when a value of 1 is written to the associated bit.
0 Interrupt has not occurred.
1 Interrupt has occurred.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
6-25
General-Purpose I/O (GPIO)
6.6.17
General Purpose Register (GPR)
The General Purpose Registers (GPR) control a multiplexer in the IOMUX module. When the
corresponding bit in the associated GIUS register is set to zero, the settings in these registers determine
whether a pin is utilized for its primary peripheral function or for its alternate peripheral function. When
the corresponding bit in the GIUS is set, the settings of this register have no effect. Figure 6-24 shows the
register and Table 6-17 provides its field descriptions.
Access: User R/W
0x1001_5038 (PTA_GPR)
0x1001_5138 (PTB_GPR)
0x1001_5238 (PTC_GPR)
0x1001_5338 (PTD_GPR)
0x1001_5438 (PTE_GPR)
0x1001_5538 (PTF_GPR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
GPR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
GPR
W
Reset
0
0
0
0
0
0
0
0
Figure 6-24. General Purpose Register
Table 6-17. General Purpose Register Field Descriptions
Field
31–0
GPR
Description
General Purpose Register. Selects between the primary and alternate functions of the pin. When the
associated bit in the GIUS register is set, this bit has no meaning.
Note: Ensure that this bit is cleared when there is not an alternate function for the associated pin.
0 Select primary pin function
1 Select alternate pin function
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6-26
Freescale Semiconductor
General-Purpose I/O (GPIO)
6.6.18
Software Reset Register (SWR)
The Software Reset Register (SWR) controls the reset of the individual ports in the GPIO module. When
the SWR bit of the Software Reset Register is set, the GPIO circuitry for the individual port resets
immediately.
The total time of the software reset sequence will take six clock cycles. The reset will be asserted from the
third cycle and remains asserted for three clocks.
Figure 6-25 shows the register and Table 6-18 provides its field descriptions.
Access: User R/W
0x1001_503C (PTA_SWR)
0x1001_513C (PTB_SWR)
0x1001_523C (PTC_SWR)
0x1001_533C (PTD_SWR)
0x1001_543C (PTE_SWR)
0x1001_553C (PTF_SWR)
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
SWR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-25. Software Reset Register (SWR)
Table 6-18. Software Reset Register Field Descriptions
Field
Description
31–1
Reserved. These bits are reserved and should read 0
0
SWR
Software Reset. Controls software reset of the port. The reset signal is active for 3 system clock
cycles and then it is released automatically. It is a self-clearing bit.
0 No effect
1 GPIO circuitry for Port X reset
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Freescale Semiconductor
6-27
General-Purpose I/O (GPIO)
6.6.19
Pull-Up Enable Register (PUEN)
The Pull-Up Enable (PUEN) Registers enable or disable a 69 kΩ pull-up resistor on the associated pin.
The pull-up can be applied to any GPIO pin regardless of whether it is configured as primary, alternate or
GPIO function. The pin is tri-stated when the pull-up is disabled and the pin is not driven. Figure 6-26
shows the register and Table 6-19 provides its field descriptions.
NOTE
Bits 27–24 on Port A (PTA_PUEN) enables or disables a 69 kΩ pull-down
resistor on the associated pin.
Bits 31–28, 26, and 9 on Port B (PTB_PUEN) enables or disables a 69 kΩ
pull-down resistor on the associated pin.
Access: User R/W
0x1001_5040 (PTA_PUEN)
0x1001_5140 (PTB_PUEN)
0x1001_5240 (PTC_PUEN)
0x1001_5340 (PTD_PUEN)
0x1001_5440 (PTE_PUEN)
0x1001_5540 (PTF_PUEN)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
PUEN
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
R
PUEN
W
Reset
1
1
1
1
1
1
1
1
1
Figure 6-26. Pull-Up Enable Register (PUEN)
Table 6-19. Pull-Up Enable Register Field Descriptions
Field
Description
31–0
PUEN
Pull-Up Enable. Determines whether the corresponding pad is pulled up to a logic-high or tri-stated. When the
pin is configured as an input, clearing this bit causes the signal to be tri-stated when not driven by an external
source. When the pin is configured as an output, clearing this bit causes the signal to be tri-stated when it is
not enabled.
0 Pin [i] is tri-stated when not driven internally or externally.
1 Pin [i] is pulled high1 when not driven internally or externally.
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6-28
Freescale Semiconductor
General-Purpose I/O (GPIO)
6.6.20
Port Interrupt Mask Register (PMASK)
The GPIO has six ports, each with interrupt generation capability. The PMASK register provides interrupt
masking capability at the port level while the Interrupt Mask Register provides control over individual
interrupts. If a bit is zero, then all interrupts for that port are masked. A software reset on a port (SWR is
set) will clear the corresponding mask bit of the port in this register. Figure 6-27 shows the register and
Table 6-20 provides its field descriptions.
0x1001_5600 (PMASK)
R
Access: User R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
PTF
PTE
PTD
PTC
PTB
PTA
1
1
1
1
1
1
W
Reset
R
W
Reset
0
0
0
0
0
0
0
0
0
0
Figure 6-27. Port Interrupt Mask Register (PMASK)
Table 6-20. Port Interrupt Mask Register Field Descriptions
Field
Description
31–6
Reserved. These bits are reserved and should read 0.
5
PTF
Port F. The bit helps in masking the Port F interrupt. The bit clears during software reset of Port F.
0 Interrupt is masked.
1 Interrupt is not masked.
4
PTE
Port E. The bit helps in masking the Port E interrupt. The bit clears during software reset of Port E.
0 Interrupt is masked.
1 Interrupt is not masked.
3
PTD
Port D. The bit helps in masking the Port D interrupt. The bit clears during software reset of Port D.
0 Interrupt is masked.
1 Interrupt is not masked.
2
PTC
Port C. The bit helps in masking the Port C interrupt. The bit clears during software reset of Port C.
0 Interrupt is masked.
1 Interrupt is not masked.
1
PTB
Port B. The bit helps in masking the Port B interrupt. The bit clears during software reset of Port B.
0 Interrupt is masked.
1 Interrupt is not masked.
0
PTA
Port A. The bit helps in masking the Port A interrupt. The bit clears during software reset of Port A.
0 Interrupt is masked.
1 Interrupt is not masked.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
6-29
General-Purpose I/O (GPIO)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
6-30
Freescale Semiconductor
Chapter 7
JTAG Controller (JTAGC)
7.1
Introduction
The JTAG Controller (JTAGC) module supports Debug access to ARM926 core and tri-state enabling of
the I/O pads. The JTAGC is compatible with 1EEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture.
7.2
Features
The Test and debug features of JTAG provide the following capabilities:
• Provide debug access to ARM926 core and execute its specific JTAG instructions independently
• Controls tri-state enable of I/O pads
7.3
Implementation
The JTAG Controller consists of the JTAG Controller state machine, Instruction Register (IR), Bypass
Register, Boundary Scan Register, Instruction decode, and various user specific data registers collectively
reside inside the ExtraDebug register.
The TDO output from the JTAG Controller is the muxed output based on whether i.MX27 JTAG
Controller or ARM926 Platform JTAG mode is active. It changes on falling edge of TCK. The TDO output
enable is selected based on whether i.MX27 JTAG Controller or ARM926 Platform JTAG mode is active.
TCK
TRST_N
TMS
Reset
TAP_STATE
RTI
DR
IR
Capture
Shift IR
EIR
Update
RTI
TDI
TDO
TDO_EN
Figure 7-1. JTAG Signals Timing Diagram
The Test Mode Select (TMS) input from external pin by default connects to the ARM926 Platform after
gating with the laser fuse output. At the rising edge of TRST_B, the JTAG_control input controls whether
the TMS pin should be connected to ARM926 Platform or to i.MX27 JTAG Controller.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
7-1
JTAG Controller (JTAGC)
When JTAG_control input is HIGH (by default), the TMS pin will be connected to ARM926 Platform after
gating with the laser fuse output. The TMS input of i.MX27 JTAG Controller will be held HIGH in this
case. When JTAG_control input is LOW, the TMS pin will be connected to i.MX27 JTAG Controller. The
TMS input of ARM926 Platform will be held HIGH.
• The Test Reset (TRST_B) input from external pin will be connected to both ARM926 Platform and
i.MX27 JTAG Controller.
• The Test Data Input (TDI) input from external pin will be connected to both ARM926 Platform
and i.MX27 JTAG Controller.
• The Test Clock (TCK) input from external pin will be connected to both ARM926 Platform and
i.MX27 JTAG Controller.
7.4
JTAG Controller Pin List
Table 7-1 provides a list of the JTAGC pins.
Table 7-1. JTAGC Pin List
Pin Name
Direction
Description
tdo
Output
tck
Input
Test Clock
Test Clock input is used to synchronize the Test Logic. This
includes an internal pull-up resistor.
tdi
Input
Test Data Input
TDI is captured during rising edge of TCK. TDI includes an
internal pull-up resistor.
tms
Input
Test Mode Select
TMS is captured during rising edge of TCK. TMS includes an
internal pull-up resistor. TMS input for the ARM926 Platform
and JTAG Controller is gated by the system logic.
trst_b
Input
Test Reset
TRST_B includes an internal pull-up resistor
Test Data Output
TDO is asserted during rising edge of TCK
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
7-2
Freescale Semiconductor
JTAG Controller (JTAGC)
7.5
JTAG Overview
Figure 7-2 shows the i.MX27 JTAG block diagram.
ARM926EJS
+ ICE
TCK
ARM
JTAG
CNTLR
TRST_B
TDI
JTAG_tms
JTAG_tdo
i.MX27
JTAG
Controller
TMS
TDO
Figure 7-2. i.MX27 JTAG Block Diagram
7.6
JTAG Modes
Two JTAG modes are created based on the I/O pin JTAG_control. These modes are used to maintain
compatibility to ARM MCU Multi-ICETM products as well as maintain IEEE JTAG standards.
7.6.1
ARM926 Platform mode
This mode connects the processed TMS input to the ARM926 Platform. TRST_B must be asserted to exit
this mode.
7.6.2
i.MX27 JTAG Controller mode
This mode will connect the processed TMS input to the i.MX27 JTAG Controller. This will provide a
dedicated user-accessible test access port that uses the same communication style as the IEEE1149.1
Standard. TRST_B or POR_B must be asserted to leave this mode.
In this mode, i.MX27 JTAG Controller supports the following capabilities:
• Query identification information (manufacturer, part number and version) of i.MX27 (IDCODE)
• Tri-state I/O pads for iddq test (HIGHZ)
• BYPASS instruction
7.7
Boundary Scan Register
The boundary scan register (BSR) in the i.MX27 JTAG implementation contains bits for all device signals
and clock pins and associated control signals. All i.MX27 bidirectional pins have a single register bit in
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
7-3
JTAG Controller (JTAGC)
the boundary scan register for pin data, and are controlled by an associated control bit in the boundary scan
register.
7.8
Instruction Register
The JTAG Instruction register is 3 bits wide. The settings of the IR is shown in Table 7-2.
Table 7-2. JTAG Instruction Register
Bit2
Bit1
Bit0
Instruction
0
0
0
IDCODE
0
0
1
SAMPLE/PRELOAD
0
1
0
EXTEST
0
1
1
ENABLE_ExtraDebug
1
0
0
HIGHZ
1
0
1
ACCESS_GENERIC_MBIST
1
1
0
CLAMP
1
1
1
BYPASS
The instruction register is reset to 3’b000 which is equivalent to the IDCODE instruction.
During the capture-IR state, the parallel inputs to the instruction register are loaded with the code 01 in the
least significant bits as required by the IEEE standard, the most significant bits are loaded with the values
0, leading to a capture value of 3’b001.
7.8.1
EXTEST Instruction
The EXTEST instruction selects the boundary scan register, and the 1149.1 test logic has control of the I/O
pins. EXTEST also asserts internal reset for the Core to force a predictable internal state while performing
external boundary scan operations.
By using the TAP Controller, the register is capable of:
• Scanning user-defined values into the output buffers
• Capturing values presented to input pins controlling the direction of bidirectional pins
• Controlling the output drive of tri-statable output pins
For more details on the function and use of EXTEST, refer to the IEEE 1149.1 document.
7.8.2
SAMPLE/PRELOAD Instruction
This selects the boundary scan register and the system logic controls the I/O pins. The
SAMPLE/PRELOAD instruction provides two separate functions. First, it provides a means to obtain a
snapshot of system data and control signals. The snapshot occurs on the rising edge of TCK in the
capture-DR Controller state. The data can be observed by shifting it transparently through the boundary
scan register.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
7-4
Freescale Semiconductor
JTAG Controller (JTAGC)
NOTE
Since there is no internal synchronization between the JTAG clock (TCK)
and the system clock (CLK), the user must provide some form of external
synchronization to achieve meaningful results.
The second function of SAMPLE/PRELOAD is to initialize the boundary scan register output cells prior
to selection of EXTEST. This initialization ensures that known data will appear on the outputs when
entering the EXTEST instruction.
7.8.3
IDCODE Instruction
This selects the ID register and the system logic controls the I/O pins. This instruction is a public
instruction to allow the manufacturer, part number and the version of the IC to be available through TAP.
Figure 7-3 shows the ID register configuration.
0x0000_7000 (IDCODE)
31
R
30
29
Access: User R/W
28
27
Version Information
26
25
24
23
22
21
Design Center Part Number
20
19
18
17
16
Device Number [21:12]
W
Reset
R
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Device Number [21:12]
MFG
1
W
Reset
0
0
0
0
1
0
1
1
0
0
0
1
1
1
0
1
Figure 7-3. ID Register Configuration
7.8.4
ENABLE_ExtraDebug Instruction
The ExtraDebug register consists of 44 bits comprising a 40-bits register (maximum), a 3-bit address field
and one read/write bit. The register data field does not need to be filled in during register read. The
particular ExtraDebug register connected between TDI and TDO is selected by the ExtraDebug Controller
based on the currently decoded address during Update_DR state. All communication with the ExtraDebug
Controller is done through the Select-DR-Scan path of the i.MX27 JTAG Controller.
7.8.5
HIGHZ Instruction
All output drivers, including the two-state drivers, are turned off (that is, high impedance). The instruction
selects the bypass register. The HIGHZ instruction also asserts internal reset for the Core to force a
predictable internal state while performing external boundary scan operations. In this mode, all internal
pull-up resistors on all the pins (except for the TMS TDI TCK TRST COLD_START MUXCTL pins) will
be disabled.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
7-5
JTAG Controller (JTAGC)
7.8.6
CLAMP Instruction
Selects the 1-bit bypass register as the serial path between TDI and TDO while allowing signals driven
from the component pins to be determined from the boundary scan register. During testing of ICs on PCB,
it may be necessary to place static guarding values on signals that control operation of logic not involved
in the test. The EXTEST instruction could be used for this purpose, but since it selects the boundary-scan
register the required guarding signals would be loaded as part of the complete serial data stream shifted in,
both at the start of the test and each time a new test pattern is entered. Since the CLAMP instruction allows
guarding values to be applied using the boundary-scan register of the appropriate ICs while selecting their
bypass registers, it allows much faster testing than does the EXTEST instruction. Data in the boundary
scan cell remains unchanged until a new instruction is shifted in or the JTAG state machine is set to its
reset state. The CLAMP instruction also asserts internal reset for the Core to force a predictable internal
state while performing external boundary scan operations.
7.8.7
BYPASS Instruction
Selects the single bit Bypass register and the system logic controls the I/O pins. This creates a shift register
path from TDI to the bypass register and finally to TDO.
When the bypass register is selected by the current instruction, the shift-register stage is set to a logic zero
on the rising edge of TCK in the capture-DR controller state. The first bit to be shifted out after selecting
the bypass register will always be a logic zero.
7.9
TMS Sequences
7.9.1
TMS Sequence to Check ID Code
Table 7-1 shows the TMS sequence to check the ID Code value, starting from any point in the state
machine.
Table 7-1. TMS Sequence To Check ID Code
Step
TCK
TMS
State
Comment
0
x5
1
Test Logic Reset
1
x1
0
Run-Test/Idle
—
2
x1
1
Select DR
—
3
x1
1
Select IR
4
x1
0
Capture IR
5
x1
0
Shift IR
6
x2
0
Shift
—
7
x1
1
Exit1
—
8
x1
1
Update
9
x1
0
Run-Test/Idle
SEQUENCE IS : IDCODE READ
IR Path : Loading ’Idcode’ instr.
—
Shift ’Idcode’ inst.= 3'b010 thru TDI
Select Idcode register
—
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JTAG Controller (JTAGC)
Table 7-1. TMS Sequence To Check ID Code (continued)
Step
TCK
TMS
10
x1
1
Select DR
DR Path:
11
x1
0
Capture DR
Capture Idcode value
12
x1
0
Shift DR
Shift out Idcode on 32bits
13
x31
0
Shift
—
14
x1
1
Exit1
—
15
x1
1
Update
—
16
x1
0
Run-Test/Idle
—
7.9.2
State
Comment
Reading Idcode reg.
TMS Sequence to Write to ExtraDebug Register
Table 7-2 shows the TMS sequence to Write to any of the ExtraDebug registers, starting from any point in
the state machine.
Table 7-2. TMS Sequence to Write to ExtraDebug Register
Step
TCK
TMS
State
Comment
0
x5
1
Test Logic Reset
1
x1
0
Run-Test/Idle
—
2
x1
1
Select DR
—
3
x1
1
Select IR
4
x1
0
Capture IR
5
x1
0
Shift IR
6
x2
0
Shift
—
7
x1
1
Exit1
—
8
x1
1
Update
9
x1
0
Run-Test/Idle
10
x1
1
Select DR
11
x1
0
Capture DR
12
x1
0
Shift DR
13
x43
0
Shift
—
14
x1
1
Exit1
—
15
x1
1
Update
16
x1
0
Run-Test/Idle
SEQUENCE IS : WRITE ExtraDebug Register
IR Path : Select ExtraDebug register.
—
Shift ‘Enable ExtraDebug’ inst.= 3'b011 thru TDI
Select ExtraDebug register
—
DR Path: Select Extradebug register to write data
—
Shift In Writ bit(1’b0) + Register Address + Data
Write to the ExtraDebug register
—
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JTAG Controller (JTAGC)
7.9.3
TMS Sequence to Read ExtraDebug Register
Table 7-3 shows the TMS sequence to READ any of the ExtraDebug registers, starting from any any point
in the state machine.
Table 7-3. TMS Sequence to Read ExtraDebug Register
7.10
Step
TCK
TMS
State
Comment
0
x5
1
Test Logic Reset
1
x1
0
Run-Test/Idle
—
2
x1
1
Select DR
—
3
x1
1
Select IR
4
x1
0
Capture IR
5
x1
0
Shift IR
6
x2
0
Shift
—
7
x1
1
Exit1
—
8
x1
1
Update
9
x1
0
Run-Test/Idle
10
x1
1
Select DR
11
x1
0
Capture DR
12
x1
0
Shift DR
13
x3
0
Shift
—
14
x1
1
Exit1
—
15
x1
1
Update
16
x1
0
Run-Test/Idle
17
x1
1
Select DR
2nd DR Path: ExtraDebug Read access
18
x1
0
Capture DR
Read the ExtraDebug register
19
x1
0
Shift DR
Shift out the captured value
20
x39
0
Shift
—
21
x1
1
Exit1
—
22
x1
1
Update
—
23
x1
0
Run-Test/Idle
—
SEQUENCE IS : READ ExtraDebug Register
IR Path : Select ExtraDebug register.
—
Shift ’Enable ExtraDebug’ inst.= 3'b011 thru TDI
Select ExtraDebug register
—
DR Path: Select Extradebug register to Read
—
Shift In Read bit(1’b1) + Register Address
Decode the 4 bits shifted in
—
i.MX27 JTAG Restrictions
TRST_b must be externally asserted to force the selection of ARM926 Platform TAP or i.MX27 JTAG
Controller. During POR_B assertion, ARM926 Platform TAP is selected.
If TMS either remains unconnected or connected to VDD, then the TAP controller cannot leave the
Test-Logic-Reset state regardless of TCK.
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Chapter 8
Bootstrap Mode Operation
8.1
Introduction
The bootstrap program is a small program that resides in the internal ROM of the i.MX27 processor. It is
activated when the BOOT[3:0] selection pins are set to 4’b0000 or if there is any exception during the
HAB checking during boot-up. The bootstrap operation handles the commands from either USB or
UART1 to establish a channel to interface the i.MX27 processor’s hardware and the external machine such
as PC. It provides the following functions.
1. For HAB Enable-type silicon, it downloads authenticated binary image code to memory so as to
execute in run time or perform Flash update.
2. For HAB Disable-type silicon, it downloads binary image code to memory as to execute in run time
or perform Flash update.
For HAB Enable-type silicon, a shell provides essential information such as the signatures, optimized
commands, and the authenticated binary image to the iROM to validate before the core to execute.
8.2
UART/USB Configuration
The configuration for RS 232 is using baud rate 115200, 8 Data bits, No Parity, 1 Stop bits, and No Flow
Control. The Configuration for USB is for Control Endpoint 0 with Max Packet Size equal 8 byte. Bulk
IN at Endpoint 2 with Max Packet Size equal 64 bytes, Bulk OUT at Endpoint 1 with Max Packet Size
equal 64 bytes.
NOTE
Current ROM code only supports Full Speed transmission over Full Speed
transceiver(ISP1301 and Atlas) and High Speed USB transceiver (ISP 1504
or the like). The ROM code does not support high-speed transmission over
high-speed USB transceiver (ISP 1504 or the like).
8.3
Enter Bootstrap Mode Configuration
The i.MX27 processor enters bootstrap mode under the following conditions:
1. BOOT[3:0] is selected bootstrap mode
or
2. For HAB Enabled type of silicon: HAB authentication fails when booting from Flash (for example
NAND Flash, NOR Flash)
Refer to Chapter 4, “System Control,” for the details of bootstrap mode configuration and operation.
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Bootstrap Mode Operation
8.4
Bootstrap Flow
The overall flow of the bootstrap program is shown in Figure 8-1.
Call USB/UART
bootloader to
download RAM
Application.
CSF Address
Execute
Address
Hardware
Configuration
Address
Valid
Execute
Address?
YES
YE
HAB
Enabled?
NO
YES
YE
Hardware
Configuration
Vector
Hardware
Configuration
CSF Data for
downloaded code
HAB Process
CSF
Execute Address
HAB Assert
Verification
Return
Status
NO
Return status =
HAB PASSED?
HAB SU Type =
Engg?
NO
YES
YE
YES
YE
Jump to
Application code
Figure 8-1. Flow Diagram for Bootstrap Mode
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Bootstrap Mode Operation
8.4.1
Bootstrap Protocol and Definition
In this section, bootstrap protocol and the command, response definition is defined. For the i.MX27
processor’s boot-up sequence, refer to System Boot. For the CSF, HW Configuration, Image definition,
refer to the High Assurance Boot (HAB).
8.4.1.1
Synchronization Operation
When bootstrap is firstly entered, the status of the iROM can be obtained by issuing the command shown
in Figure 8-2.
PC to i.MX27:
SYNCH COMMAND
i.MX27 to PC:
RESPONSE A
Figure 8-2. iROM Status Command
The SYNC COMMAND consists of 16 bytes using the format shown in Table 8-1.
:
Table 8-1. Synch Command Response Definition
Header
(2 bytes)
Address
(4 bytes)
Format
(1 byte)
Bytecount
(4 bytes)
Data
(4 bytes)
End
(1 byte)
0505
00000000
00
00000000
00000000
00
RESPONSE A is 4 bytes long using the format shown in Table 8-2.
Table 8-2. Response A Definition
8.4.1.2
Byte 0
Byte 1
Byte 2
Byte 3
STATUS CODE
STATUS CODE
STATUS CODE
STATUS CODe
Write Register Operation
To write to a register through bootstrap, requires a specific protocol. After the command is sent from PC
to MX27 processor, two responses are returned from MX27. One is used to indicate the type of silicon
(either HAB enable or disable), the other is used to indicate whether the write operation is successful.
PC to i.MX27:
i.MX27 to PC:
WRITE COMMAND
RESPONSE B
RESPONSE C
Figure 8-3. Write Register Command
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8-3
Bootstrap Mode Operation
WRITE COMMAND is 16 bytes long using the format shown in Table 8-3.
Table 8-3. Write Register Command Definition
Header
(2 bytes)
Address
(4 bytes)
Format
(1 byte)
Bytecount
(4 bytes)
Data
(4 bytes)
End
(1 byte)
0202
Address to be written
Format to be written
(08: byte access
10: halfword access
20: word access)
00
Data to be written to
the register
00
RESPONSE B indicates type of silicon. It is composed of 8 bytes using the format shown in Table 8-4.
Table 8-4. Response B Definition
Byte 0
Byte 1
Byte 2
Byte 3
HAB Disable/ Development
56
78
78
56
HAB Enable
12
34
34
12
RESPONSE C indicates the success of a write operation as shown in Table 8-5.
Table 8-5. Response C Definition
Byte 0
Byte 1
Byte 2
Byte 3
12
8A
8A
12
Remarks: For HAB enabled silicon, users can only write the following range of registers:
1. System Control registers (address: 0x10027800-0x10027870)
2. Phase-Locked Loop, Clock and Reset Controller registers
(address: 0x10027000–0x10027034)
3. NFC registers (address: 0xD8000000–0xD8000FFF)
4. SDRAMC registers (address: 0xD8001000–0xD8001FFF)
5. WEIM registers (address: 0xD8002000–0xD8002FFF)
6. Memory area of CS0, CS1, CS2, CS3, CS4, CS5, CSD0, and CSD1
(address: 0xA0000000–0xD7FFFFFF)
8.4.1.3
Download Operation
Memory is initialized before downloading a binary file to it. The following command can be used:
PC to i.MX27:
i.MX27 to PC:
DOWNLOAD COMMAND
BINARY DATA
RESPONSE B
Figure 8-4. Download Command
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Bootstrap Mode Operation
The DOWNLOAD COMMAND is 16 bytes long using the formats shown in Table 8-6.
Table 8-6. Download Command Definition
Header
(2 bytes)
Address
(4 Bytes)
Format
(1 byte)
CSF
0404
Start address where the binary
data is to be downloaded
00
HWC
0404
Start address where the binary
data is to be downloaded
Image file
0404
Image file
0404
Bytecount
(4 bytes)
Data
(4 bytes)
End
(1 byte)
Number of byte to
be written in Hex
Start address in
memory where data is
to be written
CC
00
Number of byte to
be written in Hex
Start address in
memory where data is
to be written
EE
Start address where the binary
data is to be downloaded
00
Number of byte to
be written in Hex
(max 0x1F0000)
Start address in
memory where data is
to be written
00
Start address where the binary
data is to be downloaded
00
Number of byte to
be written in Hex
Start address in
memory where data is
to be written
AA
RESPONSE B indicates the type of silicon. It is 8 bytes long using the format shown in Table 8-7.
Table 8-7. Response B Silicon Type Definition
BYTE 0
BYTE 1
BYTE 2
BYTE 3
HAB Disable/ Development
56
78
78
56
HAB Enable
12
34
34
12
After the RESPONSE B is received by the MX27 processor, the attached PC can start to download the
binary data to MX27 until all the BYTECOUNT is downloaded. Each time the Image File is downloaded
through HEADER (0404), the maximum data to be download is 0x1F0000. Thus, if the Image File size is
greater then 0x1F0000, it will send the command repeatedly with END (0x00). After all the data is
downloaded, PC must send a DOWNLOAD command with END (AA) to the target execution address.
8.4.1.4
Bootstrap End Indication Operation
After all the bootstrap operations are completed, the i.MX27 processor will send RESPONSE D to PC
after the Application Pointer was sent to indicate bootstrap was completed. After RESPONSE D, it will
enter iROM to perform the authentication check for HAB enable silicon or to execute the image for HAB
disable/development silicon.
i.MX27 to PC:
RESPONSE D
Figure 8-5. Bootstrap End Indication Operation Diagram
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8-5
Bootstrap Mode Operation
RESPONSE D is indicates the success of the write operation as shown in Table 8-8.
Table 8-8. Bootstrap End Indication Operation Diagram
BYTE 0
BYTE 1
BYTE 2
BYTE 3
88
88
88
88
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Book II:
Applications Processors’ Core and Peripherals
Introduction
Book II comprises detailed information on the applications processors’ core and peripherals. Book II
includes the following chapters.
Book II, Part 1: ARM9 Core and Interrupts
Chapter 9, “ARM9 Platform,” on page 9-1
Chapter 10, “ARM926EJ-S Interrupt Controller (AITC),” on page 10-1
Book II, Part 2: Security
Chapter 11, “Security Controller (SCC),” on page 11-1
Chapter 12, “Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2),” on page 12-1
Chapter 13, “Run-Time Integrity Checker (RTIC),” on page 13-1
Chapter 14, “IC Identification (IIM),” on page 14-1
Book II, Part 3: External Interfaces
Chapter 15, “External Memory Interface (EMI),” on page 15-1
Chapter 16, “Multi-Master Memory Interface (M3IF),on page 16-1
Chapter 17, “Wireless External Interface Module (WEIM),” on page 17-1
Chapter 18, “Enhanced SDRAM Controller (ESDRAMC),” on page 18-1
Chapter 19, “NAND Flash Controller (NFC),” on page 19-1
Chapter 20, “Personal Computer Memory Card International Association (PCMCIA) Controller,” on page 20-1
Book II, Part 4: Connectivity Peripherals
Chapter 21, “1-Wire Interface (1-Wire),” on page 21-1
Chapter 22, “Advanced Technology Attachment (ATA)”, on page 22-1
Chapter 23, “Configurable Serial Peripheral Interface (CSPI),” on page 23-1
Chapter 24, “Inter-Integrated Circuit (I2C),” on page 24-1
Chapter 25, “Keypad Port (KPP),” on page 25-1
Chapter 26, “Memory Stick Host Controller (MSHC),” on page 26-1
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II-1
Chapter 27, “Secured Digital Host Controller (SDHC),” on page 27-1
Chapter 28, “Universal Asynchronous Receiver/Transmitters (UART),” on page 28-1
Chapter 29, “Fast Ethernet Controller (FEC),” on page 29-1
Chapter 30, “High-Speed USB On-The-Go (HS USB-OTG),” on page 30-1
Book II, Part 5: Timer Peripherals
Chapter 31, “General Purpose Timer (GPT),” on page 31-1
Chapter 32, “Pulse-Width Modulator (PWM),” on page 32-1
Chapter 33, “Real Time Clock (RTC),” on page 33-1
Chapter 34, “Watchdog Timer (WDOG),” on page 34-1
Book II, Part 6: System Control Peripherals
Chapter 35, “AHB-Lite IP Interface (AIPI) Module,” on page 35-1
Chapter 36, “Multi-Layer AHB Crossbar Switch (MAX),” on page 36-1
Chapter 37, “Direct Memory Access Controller (DMAC),” on page 37-1
Book II, Part 7: Multimedia Peripherals
Chapter 38, “Digital Audio MUX (AUDMUX),” on page 38-1
Chapter 39, “CMOS Sensor Interface (CSI),” on page 39-1
Chapter 40, “Video Codec (Video_Codec),” on page 40-1
Chapter 41, “enhanced Multimedia Accelerator Light (eMMA_lt),” on page 41-1
Chapter 42, “Synchronous Serial Interface (SSI),” on page 42-1
Chapter 43, “Liquid Crystal Display Controller (LCDC),” on page 43-1
Chapter 44, “Smart Liquid Crystal Display Controller (SLCDC),” on page 44-1
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Book II, Part 1:
ARM9 Core and Interrupts
Introduction
This part provides an overview of the modules that make up the ARM9 core and interrupts.
Chapter 9, “ARM9 Platform,” on page 9-1
Chapter 10, “ARM926EJ-S Interrupt Controller (AITC),” on page 10-1
ARM9 Platform
The ARM9 Platform consists of the ARM926EJ-S processor, ETM9, ETB9, a 6 x 3 Multi-Layer AHB
crossbar switch (MAX), and a “primary AHB” complex. The instruction bus of the ARM926EJ-S
processor (I-AHB) is connected directly to MAX Master Port 0. The data bus of the ARM926EJ-S
processor (D-AHB) is connected directly to MAX Master Port 1. All four alternate bus master interfaces
are connected to MAX Master Ports 2-5. The three slave ports of the MAX are AHB-Lite compliant buses.
Slave Port 0 is designated as the “primary” AHB. The primary AHB is internal to the platform and has six
slaves connected to it: the AITC interrupt module, the MCTL memory controller, two AIPI peripheral
interface gaskets, and a ROMPATCH module. Slave ports 1 and 2 of the MAX are referred to as
“secondary” AHBs. Each of the secondary AHB interfaces is only accessible off platform.
ARM936EJ-S Interrupt Controller (AITC)
The ARM926EJ-S Interrupt Controller (AITC) is a 32-bit peripheral which collects interrupt requests from
up to 64 sources and provides an interface to the ARM926EJ-S core. The AITC includes software
controlled priority levels for normal interrupts.
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II.1-2
Freescale Semiconductor
Chapter 9
ARM9 Platform
9.1
Introduction
The ARM9 Platform consists of the ARM926EJ-S processor, ETM9, ETB9, a 6 x 3 Multi-Layer AHB
crossbar switch (MAX), and a “primary AHB” complex. The instruction bus of the ARM926EJ-S
processor (I-AHB) is connected directly to MAX Master Port 0. The data bus of the ARM926EJ-S
processor (D-AHB) is connected directly to MAX Master Port 1. All four alternate bus master interfaces
are connected to MAX Master Ports 2–5. The three slave ports of the MAX are AHB-Lite compliant buses.
Slave Port 0 is designated as the “primary” AHB. The primary AHB is internal to the platform and has six
slaves connected to it: the AITC interrupt module, the MCTL memory controller, two AIPI peripheral
interface gaskets, and a ROMPATCH module. Slave ports 1 and 2 of the MAX are referred to as
“secondary” AHBs. Each of the secondary AHB interfaces is only accessible off platform.
The four alternate bus master ports on the ARM9 Platform, which are connected directly to master ports
of the Multi-Layer Crossbar Switch (MAX), are designed to support connections to multiple AHB masters
external to the platform. An external arbitration and AHB control module is needed if multiple external
masters are desired to share an ARM9 Platform alternate bus master port. However, the alternate bus
master ports on the platform support seamless connection to a single master with no external interface
logic required.
A PAHBMUX module (primary AHBMUX) performs address decoding, read data muxing, bus watchdog,
and other miscellaneous functions for the primary AHB within the platform. A clock control module
(CLKCTL) is provided to support a power conscious design methodology as well as implementation of
several clock synchronization circuits.
The JAM (Just Another Module) implements the platform’s general purpose registers and also contains
miscellaneous platform logic.
A block diagram of the ARM9 Platform can be seen in Figure 9-1.
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9-1
ARM9 Platform
External
RAM/ROM
Interrupts
RT Debug
Two IP-bus
Peripheral Ports
JTAG
ARM926
PLATFORM
AITC
CLKCTL
MCTL
AIPI1
AIPI2
JTAG SYNC
Primary AHB
ETM9
IP Bus
ETB
IP Bus
ETM
PAHBMUX
JAM
ARM926EJ-S
IP Bus
D-AHB
ROMPATCH
I-AHB
6x3 MAX
I-AHB Patch
M0
S0
D-AHB Patch
M1
S1
M2
S2
M3
M4
M5
Four AHB-Lite Alternate
Bus Master Ports (ABM)
CCM
Clock Control “Bus Request”
Two AHB-Lite “Secondary”
Slave Ports
Figure 9-1. ARM9 Platform Block Diagram
9.1.1
Design Methodology Summary
Other than the CPU and ETB memories, this platform is a fully synthesizable, mux-D, rising edge clock
based design. DFT goals are for 95% fault coverage and the design includes BIST engines for all memories
implemented on the ARM926EJ-S, the ETB module and RAM or ROM controlled by the MCTL module.
The platform will be designed with a DFT friendly scan wrapper to allow for deeply embedded
integrations.
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ARM9 Platform
9.1.2
Performance Characteristics
The ARM9 Platform will support two main clocks—clk and hclk. clk will be connected to the
ARM926EJ-S processor, ETM9, ETB and the Clock Control Module only. The remainder of the platform
will be connected to hclk. The I-AHB and D-AHB from the ARM926EJ-S BIU module will run at the hclk
frequency and will be controlled by a single hclken input—that is, the two buses cannot be decoupled.
Refer to Section 9.6, “Platform Clocking” for more information on ARM926EJ-S clock control.
9.1.2.1
Performance Target
The ARM9 Platform team has committed to making an operating frequency of 266MHz characterized at
the 1.1V, 105C WCS 3 sigma cmos90lp standard Vt library and 400MHz characterized at the 1.45V, 105C
WCS 3 sigma cmos90lp standard Vt library. This is the level of performance required to meet functional
requirements. Due to the increased leakage of the cmos90lp library, well back-biasing will be employed
along with other standard low power clocking methodologies.
9.2
ARM9 Platform Sub-Modules
The sub-modules of the platform are listed below along with short functional descriptions.
9.2.1
ARM926EJ-S Processor
The ARM926EJ-S (ARM926) is a member of the ARM9 family of general-purpose microprocessors
targeted at multi-tasking applications. The ARM926 supports the 32-bit ARM and 16-bit THUMB
instructions sets. The ARM926 includes features for efficient execution of Java byte codes. A JTAG port
is provided to support the ARM Debug Architecture, along with associated signals to support the ETM9
real-time trace module. The ARM926EJ-S is a Harvard cached architecture including an ARM9EJ-S
integer core, a Memory Management Unit (MMU), separate instruction and data AMBA AHB interfaces,
separate instruction and data caches, and separate instruction and data tightly coupled memory (TCM)
interfaces. The ARM926 co-processor, instruction TCM, and data TCM interfaces will be tied off within
the ARM9 Platform and will not be available for external connection.
The ARM926EJ-S processor is a fully synthesizable macrocell with a configurable memory system. Both
instruction and data caches will be 16 Kbytes on the platform. The cache is virtually accessed and virtually
tagged. The data cached has physical tags as well. The MMU provides virtual memory facilities which are
required to support various platform operating systems such as Symbian OS, Windows CE, and Linux. The
MMU contains eight fully associative TLB entries for lockdown and 64 set associative entries. Refer to
the ARM926EJ-S Technical Reference Manual for more information.
9.2.1.1
ARM926EJ-S Co-Processor Interface
The co-processor interface will not exit the ARM9 platform and will be tied off internally and synthesized
away to improve routing congestion and timing.
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ARM9 Platform
9.2.1.2
TCM Interfaces
Both instruction and data tightly-coupled memory (TCM) interfaces will not exit the ARM9 platform and
will be tied off internally and synthesized away to improve routing congestion and timing.
9.2.2
ARM9 Embedded Trace Macrocell and Embedded Trace Buffer
The ARM9 platform will include an ARM9 Embedded Trace Macrocell (ETM9) and Embedded Trace
Buffer (ETB) supporting real-time instruction and data tracing. The ETM9/ETB external interface may run
at the ARM926EJ-S clock frequency or at half the ARM926EJ-S clock frequency. The Embedded Trace
Buffer is sized at 2048x 32 and can be used as general scratch pad memory when not being used for
real-time tracing. This scratch pad memory is accessible via AIPI2 slots 27 and 28. The ETB registers can
be accessed via AIPI2 slot 29. Refer to the ETM9 and ETB technical reference manuals for more
information.
9.2.3
The 6 x 3 Multi-Layer AHB Crossbar Switch (MAX)
The ARM926EJ-S processor’s instruction and data buses and all alternate bus master interfaces arbitrate
for resources via a 6 X 3 Multi-Layer AHB Crossbar Switch (MAX). There are six (M0–M5) fully
functional master ports and three (S0–S2) fully functional slave ports. The MAX is uni-directional. All
master and slave ports are AHB-Lite compliant. See Section 9.9.1, “Definition of AHB-Lite,” for an
explanation of AHB-Lite.
The design of the crossbar switch allows for concurrent transactions to proceed from any master port to
any slave port. That is, it is possible for all three slave ports to be active at the same time as a result of three
independent master requests. If a particular slave port is simultaneously requested by more than one master
port, arbitration logic exists inside the crossbar to allow the higher priority master port to be granted the
bus, while stalling the other requestor(s) until that transaction has completed. The slave port arbitration
schemes supported are fixed, programmable fixed, programmable default input port parking, and a round
robin arbitration scheme.
The Crossbar Switch also monitors the ccm_br input (clock control module bus request) which request a
bus grant from all four slave ports. The priority of ccm_br is programmable and defaults to the highest.
Upon receiving bus grants for all four output ports, the ccm_bg output will assert. At this point, the clock
control module can turn off hclk and be assured there are no outstanding AHB transactions in progress.
Once the CCM is granted a port, no other master will receive a grant on that port until the CCM bus request
(ccm_br) negates.
Brief descriptions below provide more detail on the MAX. For complete functionality, refer to the ARM9
Platform “Multi-Layer AHB Crossbar Switch” Module (MAX) specification.
9.2.3.1
MAX Configuration Registers
The Crossbar Switch has configuration and control registers accessible via the IP Bus (slot 31 of AIPI2).
Programmable registers exist to control arbitration schemes, bus parking, as well as other crossbar bus
switch functionality. Alternate master priority registers exists within the MAX module for each slave
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output port. The alternate priority register can be selected for use by the internal arbitration logic by driving
the sx_ampr_sel (x=0-2) input high.
A write-block sticky bit is implemented for those applications where it is desirable to prevent changes to
the MAX registers after boot. Refer to the MAX module design specification for more details.
9.2.3.2
Master Ports
Master Port 0 of the MAX is connected directly to the ARM926EJ-S I-AHB. Master Port 1 of the MAX
is connected directly to the ARM926EJ-S D-AHB. The other four master ports exit the platform and will
be connected to external alternate bus masters. Multiple external masters may be attached to a single
alternate bus master port via use of an external arbiter. See Section 9.9.3, “Single Master Seamless
Connection to ABM Port,” and Section 9.9.4, “Multiple External Masters Connection to ABM Port,” for
more information on how to connect either a single master or multiple masters to a single alternate master
port.
Master Port priorities are determined by the MAX priority register bit settings. Refer to the MAX module
design specification for more details.
9.2.3.3
Slave Ports
Slave port 0 through 2 are identical AHB-Lite buses. Slave Port 0 is designated as the “Primary AHB” bus,
and is internal to the platform. Slave port 1 and 2 are identical “Secondary AHB” buses and are available
external to the platform. See Section 9.9.6, “MAX AHB Slave Ports,” for more details.
9.2.3.4
Debug Support
In addition to the JTAG, ETM9 and ETB9 interfaces, several internal ARM926EJ-S signals, several
internal primary AHB signals as well as some internal signals from Master Ports 0 and 1, have been
brought out of the platform. These signals, along with alternate bus master and secondary AHB signals
already available on the top-level of the platform, enable the user to gain insight into the operation of the
processor and the MAX. Specifically, it is possible to monitor these signals and determine which master
currently owns each slave port. In addition, it is possible to determine which slave each master is targeting
for its next request.
9.2.4
ARM Interrupt Controller (AITC)
The ARM9 platform’s interrupt controller is called the AITC and is connected to the primary AHB as a
slave device. It will generate the normal and fast interrupts to the ARM926EJ-S processor. The AITC also
supports hardware assisted vectoring.
NOTE
If hardware assisted vectoring is used, the vector space must be marked
non-cacheable. Since the vector is dynamically “jammed” in by the AITC
during a vector fetch, there would be no way to do this if cached.
Refer to the AITC specification for more details.
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9.2.5
Memory Controller and BIST Engine (MCTL)
The MCTL module interfaces the primary AHB to RAM and ROM. BIST engines are provided for both
RAM and ROM.
9.2.5.1
RAM
The ram_connect input on the ARM9 Platform must be tied high if RAM exists on the MCTL RAM
interface. The MCTL module supports a minimum of 1 Kbyte of RAM and a maximum of 1 Mbyte. Non
power-of-two sizes between 1 Kbyte and 1 Mbyte are supported by strapping the ram_max_addr[9:0]
inputs, which correspond to the primary AHB’s haddr[19:10]. The ram_wait input should be tied high at
integration time if a wait state is required to make read data timing on RAM accesses (writes will still be
zero wait state). The RAM interface will support single clock edge non late-write style compiled
memories, and will implement an internal write buffer to mimic the late-write capability for improved
performance. A configurable BIST engine is provided.
Refer to the ARM9 Platform MCU Memory Controller specification for more detail on the RAM
controller design. Refer to Table 9-4 for the RAM’s location within the platform’s memory map.
9.2.5.2
ROM
The rom_connect input on the ARM9 Platform must be tied high if ROM exists on the MCTL ROM
interface. The MCTL module supports a minimum of 1 Kbyte of ROM and a maximum of 4 Mbyte. Non
power-of-two sizes between 1 Kbyte and 4 Mbyte are supported by strapping the rom_max_addr[11:0]
inputs, which correspond to the primary AHB’s haddr[21:10]. The rom_wait input should be tied high at
integration time if a wait state is required to make read data timing on ROM accesses. A configurable BIST
engine is provided.
9.2.5.2.1 ROM Addressing
The first 16 Kbytes of ROM will always be mapped starting at haddr[31:0]=32’h0000_0000. Any ROM
larger than 16Kbyte will have the remainder of its space mapped starting at haddr[31:0]=32’h0040_4000.
Any ROM size smaller than 16 Kbyte, will be aliased throughout the 16 Kbyte region. Accesses to the
“hole” between these two regions will be terminated with an ERROR response by the MCTL.
Refer to the ARM9 Platform MCU Memory Controller specification for more detail on the ROM
controller design.
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9.2.6
AHB IP Bus Interface (AIPI)
There are two AHB IP Bus Interface (AIPI) modules that interface the primary AHB to two external IP
Bus interfaces. The IP Bus interfaces and their peripherals will conform to the IP Bus Rev 2.0/3.0
specification. Each AIPI module supports up to 31 peripherals (the AIPI configuration registers consume
the slot 0), however the ARM9 Platform will only support 48 external peripherals as shown in Table 9-1.
Table 9-1. AIPI ARM9 Platform IP Bus Support
AIPI #
Module Slot(s)
Use
1
0
1
1–31
2
0
2
1–17
Off platform IP Bus module support
2
18–26
Reserved
2
27
On platform ETB Register Interface
2
28
On platform ETB RAM Interface
2
29
On platform ETB RAM Interface
2
30
On platform JAM Interface
2
31
On platform MAX Interface
AIPI1 Configuration Registers
Off platform IP Bus module support
AIPI2 Configuration Registers
Refer to the ARM9 Platform AIPI specification for more details on the operation of the AIPI.
9.2.7
PAHBMUX–Primary AHB Mux
The PAHBMUX module is responsible for address decoding for the primary AHB module selects. In
addition, the PAHBMUX module will perform the primary AHB read data muxing, the primary AHB
watchdog, and other miscellaneous functions.
Refer to the ARM9 Platform AHBMUX design specification for more detail.
9.2.8
ROMPATCH
The ROMPATCH will sit on the ARM926EJ-S I-AHB and D-AHB interfaces which are connected to
MAX Master Ports 0 and 1. This location will allow for patching of both internal and external memory
addresses on both ARM926EJ-S processor buses. The registers of the ROMPATCH will be programmed
via the Primary AHB. The ROMPATCH can be used to patch source code or data tables. The ROMPATCH
supports 32 patches.
9.2.8.1
External Boot
An external boot feature exists in the ROMPATCH module which allows patching of the reset vector fetch
(address = 32’h0000_0000) if the boot_int signal is negated. This mechanism will cause the ARM926EJ-S
to, in effect, fetch the reset vector from the address indicated by the ext_boot_addr[31:2] inputs.
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Refer to the ARM9 Platform ROMPATCH design specification for more details.
9.2.9
Clock Control Module (CLKCTL)
The CLKCTL module performs block level clock gating, ARM926EJ-S JTAG synchronization
requirements, as well as other miscellaneous clock control for the platform. Refer to the ARM9 Platform
CLKCTL design specification for more detail on design implementation.
9.2.10
JAM
The JAM (“Just Another Module”) implements miscellaneous logic with the platform. Functionality
within the JAM includes IP Bus #2 read data muxing, gating of the AHB debug signals in order to save
power, and an IP Bus interface for accessing ARM9 Platform general purpose registers. The IP Bus
interface on the JAM populates AIPI2, slot 30. The IP bus registers implemented in the JAM are shown in
Table 9-2.
Table 9-2. JAM IP Bus General Purpose Registers
Primary haddr
Register Name
Type
Implementation
32’h1003_E000
ARM9P_GPR0
Write/Read
{30’h0, etb_reg_clken, ahb_dbg_en}
32’h1003_E010
ARM9P_GPR4
Read Only
tapid[31:0]
The registers may be aliased throughout the AIPI2 slot 30 location; however, the registers should only be
accessed at the above listed addresses. Attempts to access the registers at aliased locations may result in
an error response. Additionally, attempts to access the registers in user mode or in non-word sizes will
result in an error response. Writes to the read only ARM9P_GPR4 register are ignored and will not cause
an AHB transfer error.
ARM9P_GPR0 bit [1], etb_reg_clken, is reset to zero on power-up and disables the clocks to the ETB for
non debug purposes. When set to one, etb_reg_clken will enable clocks to the ETB such that the memory
in the ETB can be used as general scratch-pad memory.
ARM9P_GPR0 bit [0], ahb_dbg_en, is reset to zero on power-up and disables the AHB debug related
signals from toggling in order to save power. When set to a one, ahb_dbg_en enables the following
top-level platform AHB related signals to toggle for platform debug:
• I-AHB: dbg_iahb_hready, dbg_iahb_htrans1, dbg_iahb_haddr[31:29]
• D-AHB: dbg_dahb_hready, dbg_dahb_htrans1, dbg_dahb_haddr[31:29]
• P-AHB: dbg_dahb_hready, dbg_dahb_htrans1, dbg_dahb_hmaster
These signals, along with signals available on the alternate bus master and secondary AHB ports, can be
used to gain insight into the functionality of the MAX.
ARM9P_GPR4 is provided for software to determine the version of the platform. These bits correspond
to the static state of the tapid[31:0] signals which include the tapid_ver[3:0] platform inputs. See
Section 9.4, “JTAG ID Register,” for more details.
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9.2.11
Test Wrapper
The ARM9 Platform’s test architecture is composed primarily of two functions: scan and BIST. The test
module (ARM926P_TEST) includes a test control unit which decodes primary test mode input signals and
places the platform into various test modes including scan, ac path testing, BIST, and safe state. These test
modes support the ability to test a deeply embedded platform.
Refer to the ARM9 Platform DFT specification for more information.
9.3
ARM9 Platform Hierarchy
The first two levels of the ARM9 Platform design hierarchy are shown in Figure 9-2.
ARM9P PLATFORM
ARM926P_CORE
ARM926P_TEST
ARM926P_DEBUG
ARM926P_WRAPPER
ETM9
ARM926P_TCU
ARM926EJ-S
ETB9
ARM926P_ROUTER
CLKCTL
MAX
(CROSSBAR SWITCH)
ARM926P_TSECURE
ARM926P_TCLOCKS
JAM
PAHBMUX
MCTL
ROMPATCH
AIPI1
JAM
AIPI2
AITC
Figure 9-2. ARM9 Platform Hierarchy
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9.4
JTAG ID Register
The ARM926EJ-S processor has a 32-bit input bus which corresponds to the JTAG ID register. This 32-bit
register is defined fields as shown in Table 9-3. ARM requires bits [31:12] be set in accordance with their
general rules such that Multi-ICE can auto-detect the device type.
Table 9-3. ARM926EJ-S JTAG ID Register Definition
tapid[31:28]
tapid[27:12]
Version
Part Number
4’b0
16’h7926
9.5
tapid[11:8]
tapid[7:1]
tapid[0]
Manufacturing ID
tapid_ver[3:0]
1’b1
7’b001_0000
1’b1
System Memory Map
haddr[31:29] on the MAX master ports are decoded determine which slave port has been selected. Only
three bits are used in order to keep output port decode time to a minimum. Table 9-4 shows a simplified
breakdown of the eight 512 Mbyte regions decoded within the 4 Gbyte address space.
Table 9-4. Upper Address Bit Decode
haddr[31:29]
Size
Use
3’b000
512 Mbyte
Primary AHB—AIPI1, AIPI2, AITC, MCTL (ROM), ROMPATCH
3’b001
512 Mbyte
Reserved
3’b010
512 Mbyte
Reserved
3’b011
512 Mbyte
Reserved
3’b100
512 Mbyte
Secondary AHB Slave Port 1
3’b101
1 Gbyte
Secondary AHB Slave Port 2
512 Mbyte
Primary AHB–MCTL (RAM)
3’b110
3’b111
9.5.1
ARM9 Platform Memory Map
Table 9-5 shows the complete ARM9 Platform memory map.
Table 9-5. ARM9 Platform Memory Map
Address Range
Size
Use
0000_0000–0000_3FFF
16 Kbytes
ROM: First 16 Kbytes (Primary AHB)
0000_4000–0040_3FFF
4 Mbytes
Reserved
0040_4000–007F_FFFF
4 Mbytes–16 Kbytes
0080_0000–0FFF_FFFF
256 Mbytes–8 Mbytes
1000_0000–1000_0FFF
4 Kbytes
AIPI1 Control Registers (Primary AHB)
1000_1000–1001_FFFF
124 Kbytes
AIPI1 Peripheral Space (Primary AHB)
ROM: Exceeding 16 Kbytes (Primary AHB)
Reserved
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Table 9-5. ARM9 Platform Memory Map (continued)
9.5.2
Address Range
Size
Use
1002_0000–1002_0FFF
4 Kbytes
AIPI2 Control Registers (Primary AHB)
1002_1000–1003_1FFF
68 Kbytes
AIPI2 Peripheral Space (Primary AHB)
1003_2000–1003_AFFF
36 Kbytes
Reserved
1003_B000–1003_BFFF
4 Kbytes
AIPI2—ETB Registers (Primary AHB)
1003_C000–1003_CFFF
4 Kbytes
AIPI2—ETB RAM (Primary AHB)
1003_D000–1003_DFFF
4 Kbytes
AIPI2—ETB RAM (Primary AHB)
1003_E000–1003_EFFF
4 Kbytes
AIPI2—JAM (Primary AHB)
1003_F000–1003_FFFF
4 Kbytes
AIPI2—MAX (Primary AHB)
1004_000–1004_0FFF
4 Kbytes
AITC (Primary AHB)
1004_1000–1004_1FFF
4 Kbytes
ROMPATCH (Primary AHB)
1004_2000–1FFF_FFFF
256 Mbytes–280 Kbytes
Reserved
2000_0000–7FFF_FFFF
1.5 Gbytes
Reserved
8000_0000–9FFF_FFFF
512 Mbytes
Secondary AHB Slave Port 1
A000_0000–DFFF_FFFF
1 Gbyte
Secondary AHB Slave Port 2
E000_0000–FFEF_FFFF
511 Mbytes
FFF0_0000–FFFF_FFFF
1 Mbyte
Reserved (Aliased RAM Space)
RAM (Primary AHB)
External Peripheral Space
AIPI1 supports 31 external peripherals starting at 32’h1000_1000. AIPI2 has three slots used internal to
the ARM9 Platform and supports 17 external peripherals from 1002_1000–1003_EFFF.
NOTE
Care should be taken when programming the PSR of AIPI2 since slot 31
(MAX), slot 30 (JAM), slot 29 (ETB Registers), slot 28 (ETB RAM) and
slot 27 (ETB RAM) will always be occupied and slots 26:18 will always be
unoccupied.
9.5.3
External Boot
When the boot_int input signal is asserted, the ARM926EJ-S will boot internal from ROM on the Primary
AHB. When boot_int is negated, the ARM926EJ-S reset vector fetch will essentially be routed to an
address indicated by the ext_boot_addr[31:2] input pins. This vectoring is done by the ROMPATCH
module, which monitors the I-AHB of the ARM926EJ-S and over-rides the reset vector fetch.
Refer to the ROMPATCH design specification for more detail on the external boot mechanism.
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NOTE
When boot_int is negated and the ARM926EJ-S boots externally the ARM9
Platform is placed in an insecure state.
9.5.4
•
•
•
•
9.6
Memory Map Considerations
Accesses to “Reserved” locations in Table 9-5 other than aliased RAM space will result in an AHB
error response.
Accesses to unsupported address locations through the MAX will result in an AHB error response
and the access will not pass through the MAX.
Accesses to address locations on the Primary AHB bus which do not map to a specific module will
time-out in accordance with the bmon_timeout[2:0] inputs.
Accesses to unimplemented locations within the AITC and ROMPATCH register space will be
terminated without a bus-error. Writes will have no effect and reads will return all zeros.
Platform Clocking
This section will describe some of the clocking considerations within the ARM9 Platform. The circuits
contained in the ARM9 Platform to address most of these issues will be implemented within the Clock
Control Module (CLKCTL). However, there are some external clock control issues that will be discussed.
Refer to the ARM9 Platform CLKCTL Module design specification for more detail.
9.6.1
ARM926EJ-S Clock Considerations
The ARM926EJ-S processor design uses a single clock, clk. In many systems, it will be desirable for the
ARM926EJ-S processor to run at a higher frequency than the AHB system bus (which runs on hclk). To
support this, ARM926EJ-S requires a separate AHB clock enable for each of the two bus masters. dhclken
is used to signify the rising edge of hclk for the system in which the data BIU is the bus master. ihclken is
used to signify the rising edge of hclk for the system in which the instruction BIU is the bus master.
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Figure 9-3 shows the relationship between clk, hclk and dhclken/ihclken. The ARM9 Platform will
provide a single hclken input pin that will be fed to both the dhclken and ihclken inputs on the
ARM926EJ-S. If hclk and clk are the same frequency, the hclken input to the platform must be tied HIGH.
(hclken)
Figure 9-3. AHB Clock Relationship
clk and hclk must be synchronous and the skew between clk and hclk to the ARM9 Platform should be
minimized. This will require some synchronization inside the chip clock control module. An example of
this is provided in Figure 9-4. In the example, clk and hclk are completely asynchronous and clk must be
much faster to sample the slower clock, otherwise a different scheme will be needed. Also, if clk and hclk
are synchronous to each other by design, then a synchronizer may not be needed, but care must still be
taken in aligning the rising edges of both clocks to the ARM9 Platform.
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hclken
BUS CLOCK
(Slow Clock)
D
Q
CLK
D
Q
CLK
D
Q
Insertion
Delay
HCLK
CLK
CLK
CPU CLOCK
(Fast Clock)
Insertion Delay
+ F/F Clk->Q
>Q
CLK_ALWAYS
Insertion Delay
+ F/F Clk->Q
CLK
GATE_HCLK
GATE_CLK
ARM9 Platform
CCM Boundary
Boundary
Figure 9-4. Example hclk to clk Synchronization when clk is Faster
9.6.2
ARM926EJ-S JTAG Port Clocking Considerations
The ARM926EJ-S does not support direct connection to the JTAG interface. The JTAG interface must be
synchronized to the clk domain. This synchronization will take place within the platform’s CLKCTL
module. Refer to the ARM9 Platform CLKCTL design specification for more detail.
9.6.2.1
JTAG_TCK
The jtag_tck clock must be less than 1/8 the frequency of the clk input in order for the JTAG port and
synchronizer to function properly. Note that the frequency of clk can vary when executing low-power
code. Therefore, care must be taken such that jtag_tck is less than 1/8 the lowest possible frequency of clk.
9.6.3
External Alternate Bus Master Interfaces
All four alternate bus master ports on the ARM9 Platform MUST have the AHB synchronized to hclk
external to the platform. All alternate bus master AHB inputs and outputs to/from the ARM9 Platform will
be synchronous to hclk.
9.6.4
External Secondary AHB Ports
Both secondary AHB ports inputs and outputs to and from the ARM9 Platform must be synchronous to
the hclk and will run at the hclk frequency.
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9.7
Platform Resets
This section will describe the various ARM9 Platform reset inputs. Figure 9-5 shows the reset paths within
the ARM9 Platform.
ARM9 Platform
ARM926P_CORE
ARM926P_TEST
hreset_b
tcu_hreset_b
hreset_b
ARM926EJ-S
HRESETn
ctbuf
DBGnTRST
ETM9
nRESET
CLKCTL
nTRST
por
OR
and
sync
jtag_trst_b
dbg_clear_b
ETB9
ctbuf
HRESETn
nTRST
clk_always
nRESET
hreset_b
(to all other platform modules)
Figure 9-5. ARM9 Platform Resets
9.7.1
HRESET
The hreset_b input is the asynchronous system reset for both the clk and hclk domains. It is gated with a
test mode signal in the scan wrapper, and is then buffered for distribution throughout the platform. The
hreset_b signal must satisfy the setup and hold time requirements relative to both clk and hclk rising edges.
9.7.2
POR and JTAG_TRST
The power-on-reset (POR) and the JTAG reset (jtag_trst_b) will be combined in the CLKCTL module to
drive the dbg_clear_b signal to the ARM926EJ-S and ETM9 modules. The dbg_clear_b output of the
CLKCTL module can be considered as the JTAG or debug reset of the platform. The dbg_clear_b signal
will assert asynchronously when either POR or jtag_trst_b asserts, and will negate synchronously to clk
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(through a synchronizer). Refer to the CLKCTL module design specification for more detailed
information.
9.8
9.8.1
Power Management
Register Level Clock Gating
A Synopsys power compiler will be used to implement clock-gating on all components of the ARM9
Platform. That is, under normal operating conditions, clocks internal to the platform will only be issued to
registers or banks of flops that need a rising edge for proper functionality. Otherwise, the clocks will be
held low.
9.8.2
Block Level Clock Gating
Clocks to individual modules within the platform will be enabled only when necessary. On the Primary
AHB for example, the CLKCTL module will only enable hclk to a slave module when the current AHB
access is addressed to that module. Slaves can also drive a signal to the CLKCTL if it requires its hclk to
run for any other reason. See the CLKCTL module design specification for more detail.
9.8.3
External Clock Gating
The ARM926EJ-S processor may be put into a low-power state by the wait-for-interrupt instruction. This
instruction switches the ARM926EJ-S into a low-power state until either an interrupt (nIRQ/nFIQ) or a
debug request occurs. The switch into the low-power state is indicated by the assertion of the
arm_standbywfi output signal. If arm_standbywfi is asserted then it is guaranteed that all ARM926EJ-S
external interfaces will be in an IDLE state. The arm_standbywfi signal is intended to be used to shut down
clocks to the other parts of the system, such as external coprocessors, which do not need to be clocked if
the ARM926EJ-S is idle. NOTE: The ARM926EJ-S clk must NOT be stopped during wait-for-interrupt
mode if an external debugger is connected to the JTAG port. An active clk is required to be able to write
values into the ARM9EJ-S debug control register, which is required for a debugger to be able to force
wait-for-interrupt mode to be exited. It should also be noted that the ARM926EJ-S needs clk to run in order
for an interrupt to cause the negation of arm_standbywfi.
The JTAG synchronizer in the CLKCTL module needs to have an “always” clock running to it in order to,
at any time, detect JTAG activity and thereby determine that a debugger is connected to the JTAG port.
The presence of an active JTAG debugger will be detected by monitoring the JTAG TMS signal. After
POR (or trst_b) assertion, a low state on TMS coincident with a rising-edge on TCK will transition the
JTAG tap-controller from the test-logic-reset state to the run-test-idle state. The dbgen signal will be
asserted, and held asserted, whenever the tap-controller is not in the test-logic-reset state. Once dbgen
asserts, an active trst_b or POR is required to clear it (that is, once a debugger is detected to be connected,
it is assumed to stay connected).
When asserted, the a9p_clk_off output of the platform will indicate to an external clock control module
that clk and hclken should be turned off at the earliest opportunity. However, in order to assure that no
alternate bus masters are in the middle of a transaction, the external clock control module must assert the
ccm_br input (bus request) of the crossbar switch. This will request ownership of all AHB Output Ports.
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Once the bus grant is asserted (ccm_bg), the external clock control module is then free to gate off hclk as
all transactions on both the primary and secondary AHBs will have completed.
Figure 9-6 shows a block diagram of how the clocks to the platform might be handled in a typical
implementation.
ARM9 PLATFORM
CLK
CLK
ARM926EJ-S
CLK
IHCLKEN
HCLKEN
HCLKEN
STANDBYWFI
DHCLKEN
RESET
FLOP
ETB9
HCLK
HCLK
Module
Clk
Gating
CLK_ALWAYS
ETM CG
Individual
Module
Enables
ETM9
CLK
DBGTCKEN
“ARM” JTAG
JTAG
SYNC
JTAG
CCM_BR
IRQ_B
AITC
CLKCTL
CCM_BG
DBGEN
FIRQ_B
irq[63:0]
A9P_CLK_OFF
EXTERNAL
CLOCK CONTROL MODULE
IP Bus
Figure 9-6. ARM9 Platform Clocking Strategy
9.8.4
Well Biasing
A well bias clamp enable input, wt_en, will be driven by an external clock control module to the ARM9
Platform. When asserted, VBB+ will be shorted to VDD and VBB- will be shorted to GND.
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9.9
Platform AHB Interfaces
This section will describe the major bus interfaces of the ARM9 Platform and the crossbar switch. A
simple block diagram of the bus connections to the platform is shown in Table 9-1. A definition of
AHB-Lite, a functional description of the alternate bus master ports, and finally a description of the
multi-layer crossbar switch slave ports follows.
9.9.1
Definition of AHB-Lite
All master and slave ports of the Multi-Layer AHB Crossbar switch are AHB-Lite compliant. Therefore,
all AHBs connected externally to the ARM9 Platform must be AHB-Lite compliant.
The definition of “AHB-Lite” for the ARM9 Platform is as follows:
• AHB split and retry protocols are not supported within the ARM9 Platform. This means that all
slaves connected to AHB-Lite ports (input or output) are prohibited from requesting a split or a
retry. This also means there is only one response signal, hresp0.
• AMBA bus request and bus grant are not supported on the AHB-Lite interfaces.
• Bursts are supported. The default configuration of the Crossbar Switch (MAX) insures no early
fixed length burst terminations due to the switch arbiter.
9.9.2
Alternate Bus Master Ports
There are four alternate bus master ports (ABM) on the ARM9 Platform which are connected directly to
the Multi-Layer AHB Crossbar Switch. These four ABM interfaces are AHB-Lite compliant. Table 9-6
lists the ABM interface signals (“x” is equal to 2 through 5). All signals function as documented in the
AMBA Specification, Rev 2.0, AMBA AHB chapter. It is assumed that the alternate bus masters are using
the same hclk and hreset_b as the ARM9 Platform.
Table 9-6. Alternate Bus Master Interface Signal List
Pin List
Direction1
mx_haddr[31:0]
Input
AHB Address Bus
mx_hmaster[3:0]
Input
AHB Master ID
mx_htrans[1:0]
Input
AHB Transfer Type
mx_hprot[3:0]
Input
AHB Access Protection Indicator
mx_hlock
Input
AHB Master Lock Indicator
mx_hmastlock
Input
AHB-Lite Master Lock Indicator
mx_hwrite
Input
AHB Access Write Indicator
mx_hsize[1:0]
Input
AHB Transfer Size
mx_hburst[2:0]
Input
AHB Access Burst Type
mx_hwdata[31:0]
Input
AHB Write Data
mx_hready_out
Output
Description
AHB Termination/Take Indicator
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ARM9 Platform
Table 9-6. Alternate Bus Master Interface Signal List (continued)
1
9.9.3
Pin List
Direction1
mx_hrdata[31:0]
Output
AHB Read Data
mx_hresp0
Output
AHB Error Indicator
Description
Direction is relative to the ARM9 Platform.
Single Master Seamless Connection to ABM Port
A single external master can connect seamlessly (no logic) to any of the four alternate bus master interfaces
(all four ABM interfaces are identical). In this configuration, Table 9-7 lists the AHB signals which
deserve special consideration.
Table 9-7. Single External Master Connections to an Alternate Bus Master Interface
AHB Signal
Master’s hbusreq Output
If present leave unconnected
Master’s hgrant Input
If present tie asserted (high)
Master’s hready Input
Connect to ABM hready_out Output
Master’s hlock Output
If present connect to ABM hlock Input1
Master’s hmastlock Output
1
2
Connection
If present connect to ABM hmastlock Input2
If the Master does not have an hlock output, tie the ABM hlock input negated (low).
If the Master does not have an hmastlock output, tie the ABM hmastlock input negated (low).
NOTE
The alternate bus master must drive htrans = IDLE when not requesting the
bus as the arbiter may be parked on that input port.
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ARM9 Platform
9.9.4
Multiple External Masters Connection to ABM Port
The four alternate bus master interfaces of the ARM9 Platform have been designed to support connection
of multiple external AHB-Lite masters and slaves directly to the interface. Figure 9-7 shows the
connection of two external masters to a ARM9 Platform alternate bus master interface. Note the location
of the ARM9 Platform in the figure below and that only one of four ABM ports is shown.
EXTERNAL
ARBITER
DATA_SELECT
ADR_SELECT
(Only one of four alternate Bus
Master Interfaces Shown)
M1_HBUSREQ
M1_HBGRANT
BUS
MASTER
#1
HREADY
M1_HADDR/CTRL
ARM9
PLATFORM
HADDR/CTRL
M2_HADDR/CTRL
HWDATA
HRDATA
HWDATA
A9P_HRDATA
M2_HWDATA
M2_HRDATA
M2_HBUSREQ
M2_HGRANT
A9P_HREADY
HREADY
BUS
MASTER
#2
M2_HREADY_OUT
M2_HADDR/CTRL
HWDATA
HRDATA
Figure 9-7. Example of Two External Masters Connected to an ABM Port
In the figure, two external masters, #1 and #2, arbitrate for control of the ABM interface on the ARM9
Platform. An external arbiter is required. The arbiter accepts the bus master’s hbusreq signals, and
responds to the masters with hgrants. The arbiter also controls the address/control and data muxing in the
external AHBMUX module.
9.9.5
Alternate Bus Master Design Considerations
This section will discuss various issues which should be taken into account by engineers designing AHB
masters to connect to the ARM9 Platform’s alternate bus master interfaces.
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ARM9 Platform
9.9.5.1
Edge Based Design
All alternate bus masters should be edge-based designs in order to meet the stringent timing imposed.
Specifically, an AHB master’s address and control information should be driven directly from the output
of a flip-flop. Similarly, an AHB master’s read data should go directly to a D-input of a flip-flop.
9.9.5.2
htrans [1:0]
Some important issues to remember about the AHB htrans signals:
• It is important that alternate bus masters drive htrans = IDLE when not requesting the bus. This is
critical because the arbiter can grant the bus to a master even when the master is not requesting it
(for example, a “parked” condition).
• Although the AMBA AHB specification does not require it, it is suggested that alternate bus
masters assert htrans = NSEQ with the initial assertion of hbusreq. In those systems where only a
single master is connected to an input port, the hgrant signal will tied high, and improved
performance may result.
• It is highly recommended that alternate bus masters insert an IDLE cycle after any locked sequence
to provide an opportunity for the arbitration to change before commencing further transfers.
9.9.5.3
hlock/hmastlock
The mx_hlock and mx_hmastlock ABM interface signal connections are dependent on whether there is a
single external master or connection to an external arbiter. The following notes specify the connections:
• For single masters only, the mx_hlock input should be connected directly to the master’s hlock
output. In this case, the mx_hmastlock input should be tied LOW. If the single master produces an
hmastlock instead the mx_hmastlock input should be connected directly to the master’s hmastlock
output. In this case, the mx_hlock input should be tied LOW.
• For multiple master connections on an ABM port, the mx_hmastlock input signal should be
connected to the external arbiter’s hmastlock output. In this case, mx_hlock should be tied LOW.
In either case above, logic within the crossbar switch will insure the locked cycles’ functionality.
9.9.5.4
hmaster
Alternate bus masters external to the ARM9 Platform should be aware that four values of the hmaster field
are used by bus masters internal to the platform. The reserved and available hmaster encodings are shown
in Table 9-8.
Table 9-8. hmaster Encodings
hmaster
Use
4’h0
Reserved: MAX default
4’h1
Reserved
4’h2
Reserved: ARM926EJ-S I-AHB
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ARM9 Platform
Table 9-8. hmaster Encodings (continued)
hmaster
4’h3
4’h4–4’hF
9.9.5.5
Use
Reserved: ARM926EJ-S D-AHB
Available to External Bus Masters
hresp0—Bus Error
A slave two cycle ERROR response (hresp0 = HIGH) allows for a bus master to cancel the remaining
transfers in a burst. However, this is not an AHB requirement, and it is acceptable for the master to
continue the remaining transfers of the burst.
AHB error responses generated on accesses to cacheable or bufferable memory address on the I-AHB and
D-AHB interfaces of the ARM926EJ-S are normally ignored by the processor. In the ROMPATCH
module, a feature can be enabled which will, on the above described accesses, gate 0’s onto hrdata[31:0]
on data reads, and SWI opcodes onto hrdata[31:0] for instruction prefetches. At the same time, the
ROMPATCH module will generate an abort which will guarantee entry into the ARM926EJ-S platform’s
abort exception handler. See the ARM9 Platform ROMPATCH design specification for more detail.
9.9.5.6
Unaligned Transfers
Alternate bus masters should not request unaligned transfers. That is, a word access to a non-word aligned
address; and, a halfword access to a non-halfword aligned address should not be requested as neither
transactions are supported by this platform. The transfers will complete as normal, however the lower
order address bits will be ignored according to Figure 9-4 and Figure 9-5.
9.9.5.7
Alternate Bus Master Throttle Control
Alternate bus masters should be designed with programmable maximum burst lengths as well as
programmable bus request interval timers. This will allow software to effectively “tune” the overall system
for maximum throughput and efficiency.
9.9.5.8
Halt Request (ccm_br)
Care must be taken to ensure that the Halt Low Priority bit is not changing as the Clock Control Module’s
Halt request is asserted. This will result in unpredictable behavior. This can be avoided by not modifying
this bit in the Slave General Purpose Control Register or in the Alternate Slave General Purpose Control
register in software where Halt could be requested. Also, the Halt Low Priority bit should be programmed
the same in both the Slave General Purpose Control Register and the Alternate Slave General Purpose
Control Register, if it is likely the MAX can change between the General Purpose and Alternate registers
during the time Halt could be requested.
Care should also be taken to ensure that the Clock Control Module’s Halt request is not asserted until at
least two clock cycles after the last locked access performed by any master connected to the MAX.
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ARM9 Platform
9.9.6
MAX AHB Slave Ports
Each slave port of the Multi-Layer Crossbar Switch is an AHB-Lite compliant bus. Brief functional
descriptions and attributes of each output port are provided.
9.9.6.1
Slave Port 0—Primary AHB (Internal)
Slave Port 0 of the MAX is connected to the “Primary” AHB of the ARM9 Platform. The primary AHB
is completely contained within the ARM9 Platform. A simplified block diagram of the Primary AHB
components is shown in Figure 9-8.
MCTL
AITC
AIPI1
ROM
PATCH
REGS
AIPI2
hsel_x
haddr
hcontrol
hwdata
aipi2_rdata
aitc_rdata
AHB
MULTI-LAYER
CROSSBAR
SWITCH
(MAX)
haddr
aipi1_rdata
mctl_rdata
addr
decode
select
hrdata[31:0]
hrdata
hready
hready
rompatch_rdata
hresp0
hresp0
gnd
(ONLY PRIMARY AHB
SLAVE PORT 0
SIGNALS ARE SHOWN)
combine
aitc_rdata_ovr
hready_out, hresp0 from slaves
bus monitor
PAHBMUX
Figure 9-8. The Primary AHB
The primary AHB will have the AITC, AIPI (2), MCTL and ROMPATCH modules connected as slave
devices. The PAHBMUX (Primary AHB mux) module is the glue that pulls the primary AHB and its
components together. It will decode the primary AHB haddr lines and issue module selects to the slaves,
combine the slave hready and hresp0 signals from the slaves into the single bus hready and hresp0, and
mux the read data from the currently selected slave onto the bus hrdata lines. A bus monitor module inside
of PAHBMUX will terminate timed-out bus transactions. In addition, the PAHBMUX will contain logic
to terminate any IDLE cycles and issue the required assertion of hready following negation of the hreset_b.
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ARM9 Platform
9.9.6.1.1 Primary AHB Device Latencies
The latency of each slave device on the primary AHB can be found in Table 9-1. The clock latency number
does not take into account the possible one clock arbitration delay of the MAX.
Table 9-1. Primary AHB Slave Device Latencies
Slave Device
Transaction Type
Latency
AITC
Register Access
1 clock
AIPI1
Writes
Reads
3 clocks
2 clocks
MCTL
Memory Access
1 clock2
ROMPATCH
Register Access
1 clock
1
The latency listed for the AIPIs are best case and based on a zero wait state
response from the IP bus target device. Each wait state the IP Bus target device
adds will add one extra clock to the listed latency value.
2
Assumes ram_wait and rom_wait are negated.
9.9.6.2
Secondary AHB Slave Ports 1 and 2
Each of the secondary AHB slave ports are identical AHB-Lite compliant buses. It is envisioned that these
ports will interface predominately to internal and external memory. However, it is possible to connect an
external AIPI interface along with associated peripherals to these ports. The secondary port slave signals
are list in Table 9-2 where “x” is equal to 1 or 2.
Table 9-2. Secondary AHB Interface Signal List
1
Pin List
Direction1
sx_haddr[31:0]
Output
AHB Address Bus
sx_hmaster[3:0]
Output
AHB Master ID
sx_htrans[1:0]
Output
AHB Transfer Type
sx_hprot[3:0]
Output
AHB Access Protection Indicator
sx_hmastlock
Output
AHB-Lite Master Lock Indicator
sx_hwrite
Output
AHB Access Write Indicator
sx_hsize[1:0]
Output
AHB Transfer Size
sx_hburst[2:0]
Output
AHB Access Burst Type
sx_hwdata[31:0]
Output
AHB Write Data
sx_hready
Input
AHB Termination/Take Indicator
sx_hrdata[31:0]
Input
AHB Read Data
sx_hresp0
Input
AHB Error Indicator
Description
Direction is relative to the ARM9 Platform.
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ARM9 Platform
9.9.7
Endian Modes
The ARM9 Platform will support both Big and Little Endian modes. The relevant signals to/from the
ARM926EJ-S processor are shown in Table 9-3 below along with brief descriptions.
Table 9-3. ARM926EJ-S Endian Related Signals
Signal
Direction
BIGENDINIT
Input
CFGBIGEND
Output
Description
Determines the setting of the BIGEND bit held in the CP15 control register after system reset.
When HIGH, the reset state of the BIGEND bit will be 1 (Big Endian).
When LOW, the reset state of the BIGEND bit will be 0 (Little Endian).
ARM926EJ-S BIGEND configuration indicator.
This signal reflects the value of the BIGEND bit held in the CP15 control register, which is used to
determine the behavior of the ARM926EJ-S WRT endianness. When HIGH, the ARM926EJ-S
treats bytes in memory as being in Big Endian format. When LOW, memory is treated as Little
Endian.
The bigendinit platform input is connected directly to the BIGENDINIT input of the ARM926EJ-S and
determines the processor and platform Endian mode of operation upon exiting system reset. However, the
endian mode of operation of the processor (and therefore the platform and associated memory systems)
may be changed according to the BIGEND bit in the CP15 control register. This output, cfg_bigend,
reflects the BIGEND bit and is used to indicate the current Endian mode of operation for the platform as
well as all external bus masters and slaves. The relevant Endian signals are shown in Figure 9-9.
ARM9 PLATFORM
ETM/ETB
etm_bigend
ARM926EJ-S
ROMPATCH
AIPI(2)
bigendinit
BIGENDINIT
MCTL
cfg_bigend
CFGBIGEND
(to external AHB
masters and slaves)
Figure 9-9. Endian Configuration Routing
The DHBL signals of the ARM926EJ-S will not be used within the platform. Instead, all modules affected
by the Endian mode will use the cfg_bigend signal in conjunction with hsize and haddr[1:0] in order to
handle non-word transfers correctly.
It is not envisioned that applications will need to dynamically change Endianness. However, this is still
under investigation, and should be possible since the platform will support both Endian modes in
hardware. It then becomes a software issue to insure a graceful mode change. For example, the write
buffers should be drained prior to changing Endian modes.
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ARM9 Platform
9.9.7.1
Affected Modules
Only the AIPI (2), MCTL (RAM and ROM) and ROMPATCH modules are affected by the cfg_bigend
signal within the platform. ETM9/ETB is affected by the Endian mode, and instead is connected to the
etm_bigend signal internally.
9.9.7.2
Unaffected Modules
The AITC module is 32-bit write only. The registers within the MAX are also 32-bit access only, and the
Endian mode is transparent from the AHB switch perspective. The PAHBMUX module has no registers
associated with it and the Endian mode is transparent to its data muxing.
9.9.7.3
Un-Aligned Transfers
Unaligned transfers are not supported by the ARM9 Platform and therefore should not be attempted by
alternate bus masters connected to it. That is, alternate bus masters should not attempt a 32-bit access to a
non-word aligned address, nor a 16-bit access to a non half-word aligned address. The transfers will
complete as normal, however the lower order address bits will be ignored according to Figure 9-4 and
Figure 9-5.
9.9.7.4
Endian Mode and Alternate Bus Masters
Alternate bus masters must be cognizant of the Endian mode if they are capable of performing non-word
accesses. Non-word register and memory transactions will be performed according to the state of the
cfg_bigend output signal. The manner in which memory is accessed in the two Endian modes is described
in the following two sections.
9.9.7.5
Little Endian Operation
A Little Endian configured ARM9 Platform (cfg_bigend = 0) should have memory connected to its
secondary AHB ports as follows:
• Byte 0 of the memory connected to D[7:0]
• Byte 1 of the memory connected to D[15:8]
• Byte 2 of the memory connected to D[23:16]
• Byte 3 of the memory connected to D[31:24]
The byte write enables should be decoded by the AHB slaves as in Table 9-4.
Table 9-4. Little Endian Byte Write Enable Decoding
hwrite
hsize[1:0]
haddr[1:0]
we[31:24]
we[23:16]
we[15:8]
we[7:0]
0
x
x
0
0
0
0
1
00
00
0
0
0
1
1
00
01
0
0
1
0
1
00
10
0
1
0
0
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ARM9 Platform
Table 9-4. Little Endian Byte Write Enable Decoding (continued)
9.9.7.6
hwrite
hsize[1:0]
haddr[1:0]
we[31:24]
we[23:16]
we[15:8]
we[7:0]
1
00
11
1
0
0
0
1
01
0x
0
0
1
1
1
01
1x
1
1
0
0
1
10
xx
1
1
1
1
1
11
Reserved
Big Endian Operation
A Big Endian configured ARM9 Platform (cfg_bigend=1) should have memory connected to its secondary
AHB ports as follows:
• Byte 0 of the memory connected to D[31:24]
• Byte 0 of the memory connected to D[23:16]
• Byte 0 of the memory connected to D[15:8]
• Byte 0 of the memory connected to D[7:0]
The byte write enables should be decoded by the slaves as in Table 9-5.
Table 9-5. Big Endian Byte Write Enable Decoding
hwrite
hsize[1:0]
haddr[1:0]
we[31:24]
we[23:16]
we[15:8]
we[7:0]
0
x
x
0
0
0
0
1
00
00
1
0
0
0
1
00
01
0
1
0
0
1
00
10
0
0
1
0
1
00
11
0
0
0
1
1
01
0x
1
1
0
0
1
01
1x
0
0
1
1
1
10
xx
1
1
1
1
1
11
Reserved
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ARM9 Platform
9.10
Preliminary Size Estimate
Table 9-6 show preliminary size estimates for the ARM9 Platform. Note that the area estimates correspond
to C90LP, WCS, 1.1V, 105C. clk = 266MHz, hclk = 133 MHz. Gate equivalents are scaled to the area of
the C90LP NAND2_2 cell.
Table 9-6. ARM9 Platform Size Estimates
Block
Number Included
in Platform
Area in μm2
Gate Count Total
(NAND2_2)
I-Cache Data Memory (1024x32)
4
259,512
—
I-Cache Tag Memory (128x22)
4
74,990
—
I-Cache Valid Memory (32x24)
1
16,122*
—
D-Cache Data Memory (1024x32)
4
259,512
—
D-Cache Tag Memory (256x22)
4
149,980*
—
D-Cache Valid Memory (32x24)
1
16,122*
—
D-Cache Dirty Memory (128x8)
1
8,242
—
MMU RAM (32x64)
2
73,286
—
ETB RAM (1024x32)
2
129,756
—
Memories Total
23
987,522
350K
ARM926 Core
1
—
TBD
ETM9 (Medium +)
1
—
TBD
ETB11
1
—
TBD
AITC
1
—
TBD
MCTL + ROM BIST
1
—
TBD
AIPI
2
—
TBD
AHBMUX
1
—
TBD
MAX
1
—
TBD
Scan Wrapper
1
—
TBD
ROMPATCH
1
—
TBD
BIST for Memories
4
—
TBD
IP to AHB (for ETB11)
1
—
TBD
Clock and Sync Control
1
—
TBD
JAM
1
—
TBD
Secure ROM monitor
1
—
TBD
Clock Tree
2
—
TBD
Logic Total
—
TBD
TBD
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ARM9 Platform
Table 9-6. ARM9 Platform Size Estimates (continued)
9.11
Block
Number Included
in Platform
Area in μm2
Gate Count Total
(NAND2_2)
55% routing efficiency (logic only)
—
TBD
TBD
Platform Total
—
TBD
TBD
Power Consumption
Table 9-7 summarizes preliminary power estimates for the various ARM9 Platform operating modes.
Power numbers will be measured off of the final freeze post-route netlist. There is no padding or margin
included in these numbers.
Table 9-7. ARM9 Platform Power Estimates
Mode of Operation
BCS Corner
(1.3 V –20C)
TYP Corner
(1.2 V 25C)
WCS Corner
(1.1 V, 105C)
Run Mode
TBD
TBD
TBD
Doze Mode
TBD
TBD
TBD
Sleep Mode without Well Bias Active
TBD
TBD
TBD
Sleep Mode with Well Bias Active
TBD
TBD
TBD
The operating modes are described below:
• Run Mode
clk, clk_always = 266MHz, hclk = 133MHz. Code running out of cache, once instructions loaded into
cache. Exercising cache/MMU memories. Core busy with arithmetic operations. Activity on all alternate
master ports and all slave ports concurrently. Compiled memory models pessimistic when memories not
being accessed. Estimated loads on all platform outputs ranging from 0.5pf to 1.5pf.
• Doze Mode
clk, clk_always, and hclken stopped. hclk = 117MHz. No alternate bus master activity. Estimated loads on
all platform outputs ranging from 0.5pf to 1.5pf.
• Sleep Mode
All clocks stopped. Includes: clk, clk_always, hclken, and hclk. Basically represents platform leakage
current. No Dynamic or Static power in Sleep Mode. Well bias active power TYP very crude estimate of
10x reduction + compiled memories. Power due to charge pump not included since charge pump is
external to the platform. WCS measured with well bias standard cell library.
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ARM9 Platform
9.12
ARM9 Platform I/O Signal List
The complete list of inputs and outputs for the ARM9 Platform are listed in Table 9-8.
Table 9-8. ARM9 Platform Signal List
Signal
Type
Description
Clocks and Resets
clk
Input
Processor and Nexus reference clock
clk_always
Input
CLK that always runs
hclk
Input
AHB domain reference clock
hclken
Input
Controls ARM926EJ-S sampling of HCLK domain
a9p_clk_off
Output
por
Input
Power-On Reset
hreset_b
Input
System reset (ARM926EJ-S and AHB reset)
To External Clock Control Module: The ARM9 Platform CLK may
be turned off
Platform Configuration
bigendinit
Input
1 = Big Endian, 0 = Little Endian
Determines initial Endian mode out of reset
cfg_bigend
Output
boot_int
Input
Internal Boot Indicator
ext_boot_adr[31:2]
Input
External Boot Address
bmon_timeout[2:0]
Input
Bus monitor timeout
1 = Big Endian, 0 = Little Endian
Reflects the value of BIGEND bit in ARM926EJ-S CP15 register.
Determines endianness of platform slaves and external AHBs.
JTAG Interface and Related I/O
jtag_tck
Input
JTAG Test Clock
jtag_trst_b
Input
JTAG Test Reset
jtag_tms
Input
JTAG Test Mode Select
jtag_tdi
Input
JTAG Test Data Input
jtag_tdo
Output
JTAG Test Data Output
jtag_tdoen_b
Output
JTAG Test Data Output Tri-state Control
tapid_ver[3:0]
Input
dbgrtck
Output
Platform Version Number
(JTAG ID register bits [11:8])
TCK “return clock” from JTAG synchronization
ARM926 Debug Related Signals
dbgrq
Input
dbgack
Output
To ARM926: Debug request (connected to EDBGRQ)
From ARM926: Debug Acknowledge
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ARM9 Platform
Table 9-8. ARM9 Platform Signal List (continued)
Signal
Type
Description
dbgext[1:0]
Input
To ICE: External breakpoints/watchpoints
dbgiebkpt
Input
To ARM926: Instruction breakpoint
dbgdewpt
Input
To ARM926: Data watchpoint
arm_dbgrng[1:0]
Output
From ARM926: Embedded ICE-RT range out
arm_standbywfi
Output
From ARM926: Processor is in wait for interrupt mode
arm_java_mode
Output
From ARM926: Processor is in JAVA mode
arm_thumb_mode
Output
From ARM926: Processor is in THUMB mode
arm_fiq_b
Output
From AITC: Fast interrupt request to processor
arm_irq_b
Output
From AITC: Interrupt request to processor
arm_fiq_disable
Output
From ARM926: Processor has disabled FIQ interrupts
arm_irq_disable
Output
From ARM926: Processor has disabled IRQ interrupts
arm_cpsr_mode[4:0]
Output
From ARM926: Processor CPSR mode bits
Platform Debug Related Signals
dbg_iahb_hready
Output
ARM926EJ-S I-AHB hready
dbg_iahb_htrans1
Output
ARM926EJ-S I-AHB htrans[1]
dbg_iahb_haddr[31:29]
Output
ARM926EJ-S I-AHB requested address (top 3 bits)
dbg_dahb_hready
Output
ARM926EJ-S D-AHB hready
dbg_dahb_htrans1
Output
ARM926EJ-S D-AHB htrans[1]
dbg_dahb_haddr[31:29]
Output
ARM926EJ-S D-AHB requested address (top 3 bits)
dbg_pahb_hready
Output
Primary AHB hready
dbg_pahb_htrans1
Output
Primary AHB htrans[1]
dbg_pahb_hmaster[3:0]
Output
Primary AHB hmaster ownership
dbg_a9p_ahb_en
Output
Enable output used for GPIO muxing of these debug signals
MCTL ROM Memory Interface
rom_connect
Input
Indicates ROM exists on the MCTL interface.
rom_max_addr[11:0]
Input
Indicates ROM size. Corresponds to HADDR[21:10].
Smallest size supported is 1Kbyte, largest 4 Mbyte.
rom_wait
Input
ROM wait-state indicator
0 = No wait-state required
1 = One wait-state required
mctl_ce_rom_b
Output
MCU ROM chip enable
mctl_addr_rom[19:0]
Output
MCU ROM address.
mem_q_rom[31:0]
Input
ROM read data
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ARM9 Platform
Table 9-8. ARM9 Platform Signal List (continued)
Signal
Type
Description
MCTL RAM Memory Interface
ram_connect
Input
Indicates RAM exists on the MCTL interface.
ram_max_addr[9:0]
Input
Indicates RAM size. Corresponds to HADDR[19:10].
Smallest size supported is 1Kbyte, largest 1 Mbyte.
ram_wait
Input
RAM read cycle wait-state indicator
0 = No wait-state required
1 = One wait-state required
mctl_mbist_sddtm
Output
MCU RAM mbist SDD test mode output
extram_oe
Output
Testmode control of external memories’ output enable. This
output should be connected to the OEN ports of all memories
external to the ARM9 Platform (SRAM and TCM).
mctl_ce_ram_b
Output
MCU RAM chip enable
mctl_wr_ram_b
Output
MCU RAM access type: read=0, write=1
mctl_addr_ram[17:0]
Output
MCU RAM address
mctl_ben_ram_7_0
Output
MCU RAM byte enables
mctl_ben_ram_15_8
Output
MCU RAM byte enables
mctl_ben_ram_23_16
Output
MCU RAM byte enables
mctl_ben_ram_31_24
Output
MCU RAM byte enables
mctl_d_ram[31:0]
Output
RAM write data
mem_q_ram[31:0]
Input
RAM read data
Multi-Layer AHB Master Port 2
m2_hlock
Input
AHB Locked Cycle Indicator (bus request timing)
m2_hmastlock
Input
AHB Locked Cycle Indicator (address timing)
m2_hmaster[3:0]
Input
AHB Master
m2_htrans[1:0]
Input
AHB Transfer Type
m2_hprot[3:0]
Input
AHB Protection Control
m2_hwrite
Input
AHB Write/Read Indicator
m2_hsize[1:0]
Input
AHB Transfer Size
m2_hburst[2:0]
Input
AHB Burst Length
m2_haddr[31:0]
Input
AHB Address
m2_hwdata[31:0]
Input
AHB Write Data
m2_hready_out
Output
AHB Transfer Done Out
m2_hrdata[31:0]
Output
AHB Read Data
m2_hresp0
Output
AHB Transfer Response
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ARM9 Platform
Table 9-8. ARM9 Platform Signal List (continued)
Signal
Type
Description
Multi-Layer AHB—Master Port 3
m3_hlock
Input
AHB Locked Cycle Indicator (bus request timing)
m3_hmastlock
Input
AHB Locked Cycle Indicator (address timing)
m3_hmaster[3:0]
Input
AHB Master
m3_htrans[1:0]
Input
AHB Transfer Type
m3_hprot[3:0]
Input
AHB Protection Control
m3_hwrite
Input
AHB Write/Read Indicator
m3_hsize[1:0]
Input
AHB Transfer Size
m3_hburst[2:0]
Input
AHB Burst Length
m3_haddr[31:0]
Input
AHB Address
m3_hwdata[31:0]
Input
AHB Write Data
m3_hready_out
Output
AHB Transfer Done Out
m3_hrdata[31:0]
Output
AHB Read Data
m3_hresp0
Output
AHB Transfer Response
Multi-Layer AHB Master Port 4
m4_hlock
Input
AHB Locked Cycle Indicator (bus request timing)
m4_hmastlock
Input
AHB Locked Cycle Indicator (address timing)
m4_hmaster[3:0]
Input
AHB Master
m4_htrans[1:0]
Input
AHB Transfer Type
m4_hprot[3:0]
Input
AHB Protection Control
m4_hwrite
Input
AHB Write/Read Indicator
m4_hsize[1:0]
Input
AHB Transfer Size
m4_hburst[2:0]
Input
AHB Burst Length
m4_haddr[31:0]
Input
AHB Address
m4_hwdata[31:0]
Input
AHB Write Data
m4_hready_out
Output
AHB Transfer Done Out
m4_hrdata[31:0]
Output
AHB Read Data
m4_hresp0
Output
AHB Transfer Response
Multi-Layer AHB Master Port 5
m5_hlock
Input
AHB Locked Cycle Indicator (bus request timing)
m5_hmastlock
Input
AHB Locked Cycle Indicator (address timing)
m5_hmaster[3:0]
Input
AHB Master
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ARM9 Platform
Table 9-8. ARM9 Platform Signal List (continued)
Signal
Type
Description
m5_htrans[1:0]
Input
AHB Transfer Type
m5_hprot[3:0]
Input
AHB Protection Control
m5_hwrite
Input
AHB Write/Read Indicator
m5_hsize[1:0]
Input
AHB Transfer Size
m5_hburst[2:0]
Input
AHB Burst Length
m5_haddr[31:0]
Input
AHB Address
m5_hwdata[31:0]
Input
AHB Write Data
m5_hready_out
Output
AHB Transfer Done Out
m5_hrdata[31:0]
Output
AHB Read Data
m5_hresp0
Output
AHB Transfer Response
Multi-Layer AHB Slave Port 1
s1_hmastlock
Output
AHB Locked Transfer
s1_hmaster[3:0]
Output
AHB Master
s1_htrans[1:0]
Output
AHB Transfer Type
s1_hprot[3:0]
Output
AHB Protection Control
s1_hwrite
Output
AHB Write/Read Indicator
s1_hsize[1:0]
Output
AHB Transfer Size
s1_hburst[2:0]
Output
AHB Burst Length
s1_haddr[31:0]
Output
AHB Address
s1_hwdata[31:0]
Output
AHB Write Data
s1_hrdata[31:0]
Input
AHB Read Data
s1_hready
Input
Transfer Done
s1_hresp0
Input
Transfer Response
Multi-Layer AHB Slave Port 2
s2_hmastlock
Output
AHB Locked Transfer
s2_hmaster[3:0]
Output
AHB Master
s2_htrans[1:0]
Output
AHB Transfer Type
s2_hprot[3:0]
Output
AHB Protection Control
s2_hwrite
Output
AHB Write/Read Indicator
s2_hsize[1:0]
Output
AHB Transfer Size
s2_hburst[2:0]
Output
AHB Burst Length
s2_haddr[31:0]
Output
AHB Address
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ARM9 Platform
Table 9-8. ARM9 Platform Signal List (continued)
Signal
Type
Description
s2_hwdata[31:0]
Output
AHB Write Data
s2_hrdata[31:0]
Input
AHB Read Data
s2_hready
Input
Transfer Done
s2_hresp0
Input
Transfer Response
MAX Specific (Crossbar Switch)
ccm_hbusreq
Input
External Clock Control Module Low-power Bus Request
ccm_hgrant
Output
s0_ampr_sel
Input
Slave port 0 alternate master priority register select.
s1_ampr_sel
Input
Slave port 1 alternate master priority register select.
s2_ampr_sel
Input
Slave port 2 alternate master priority register select.
Low-power Mode Bus Grant
IP Bus #1 (A)
ipsa_module_en[31:1]
Output
IP Bus “A” Module Select
ipsa_addr[11:0]
Output
IP Bus “A” Address
ipsa_wdata[31:0]
Output
IP Bus “A” Write Data
ipsa_byte_31_24
Output
IP Bus “A” Byte Select
ipsa_byte_23_16
Output
IP Bus “A” Byte Select
ipsa_byte_15:8
Output
IP Bus “A” Byte Select
ipsa_byte_7_0
Output
IP Bus “A” Byte Select
ipsa_rwb
Output
IP Bus “A” Read/Write Indicator
ipsa_supervisor_access
Output
IP Bus “A” Supervisor Mode Access Control
ipsa_rdata[31:0]
Input
IP Bus “A” Read Data
ipsa_xfr_wait
Input
IP Bus “A” Transfer Wait State Indicator
ipsa_xfr_err
Input
IP Bus “A” Transfer Error Indicator
IP Bus #2 (B)
ipsb_module_en[17:1]
Output
IP Bus “B” Module Select
ipsb_addr[11:0]
Output
IP Bus “B” Address
ipsb_wdata[31:0]
Output
IP Bus “B” Write Data
ipsb_byte_31_24
Output
IP Bus “B” Byte Select
ipsb_byte_23_16
Output
IP Bus “B” Byte Select
ipsb_byte_15:8
Output
IP Bus “B” Byte Select
ipsb_byte_7_0
Output
IP Bus “B” Byte Select
ipsb_rwb
Output
IP Bus “B” Read/Write Indicator
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ARM9 Platform
Table 9-8. ARM9 Platform Signal List (continued)
Signal
Type
Description
ipsb_supervisor_access
Output
ipsb_rdata[31:0]
Input
IP Bus “B” Read Data
ipsb_xfr_wait
Input
IP Bus “B” Transfer Wait State Indicator
ipsb_xfr_err
Input
IP Bus “B” Transfer Error Indicator
IP Bus “B” Supervisor Mode Access Control
ETM/ETB
etm_traceclk
Output
ETM Trace Clock
etm_clkdivtwoen
Output
ETM half rate clocking mode
etm_dbgrq
Output
Debug Request.
etm_etmen
Output
ETM Enabled
etm_pipestat[2:0]
Output
Pipeline Status
etm_tracepkt[15:0]
Output
ETM Trace Packet
etm_tracesync
Output
Trace synchronization.
etm_portsize[2:0]
Output
ETM Port Size.
etm_portmode[1:0]
Output
Normal, Multiplexed, or Demultiplexed mode of operation
etb_full
Output
ETB Overflow Indicator
etb_acqcomp
Output
ETB Trace Acquisition Complete
etm_extout
Output
External ETM Outputs
ect_dbgrq
Input
Debug Request.
etm_extin[3:0]
Input
External ETM Inputs.
Miscellaneous
aitc_rise_arb
Output
Interrupt pending, raise arbitration priority if desired
a9p_mem_on
Input
Used with a9p_mem_pwr_dn to power off ARM926 ICACHE,
DCACHE, and MMU memories
a9p_mem_pwr_dn
Input
Used with a9p_mem_on to power off ARM926 ICACHE,
DCACHE, and MMU memories
a9p_int_b[63:0]
Input
External Interrupts
a9p_dsm_int_holdoff
Input
Deep Sleep Module Interrupt Disable
wt_en
Input
Well Tie Input (Physical connection only)
wt_en_dnw
Input
Well Tie Input for deep n-wells (Physical connection only)
Platform Scan Test Interface
ipt_mode[3:0]
Input
Test Mode Control
ipt_clk_se
Input
Clock Gating Cell Scan Enable
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ARM9 Platform
Table 9-8. ARM9 Platform Signal List (continued)
Signal
Type
Description
ipt_memory_read_inhibit_int
Input
Disables memory read operations from internal memories
(caches, ETB) during scan testing. Read data is forced to zeros
when asserted. When negated, memories function normally.
ipt_scan_size[1:0]
Input
Scan Chain Length Control
ipt_scan_enable
Input
Scan Shift Enable
ipt_scan_in[66:0]
Input
Platform Test Serial In
ipt_scan_out[66:0]
Output
Platform Test Serial Out
Scan Wrapper Test Interface
ipt_wrapper_clk_in[1:0]
Input
Platform Wrapper Clocks
[0] = CLK Domain
[1] = HCLK Domain
ipt_wrapper_se
Input
Scan Shift Enable
ipt_wrapper_scan_size[1:0]
Input
Scan Wrapper Chain Length
ipt_wrapper_scan_in[23:0]
Input
Scan Wrapper Test Serial In
[2:0] = CLK
[11:3] = HCLK
ipt_wrapper_scan_out[23:0]
Output
Scan Wrapper Test Serial Out
[2:0] = CLK
[11:3] = HCLK
Memory BIST Interface
ipt_bist_fail
Output
Aggregate Memory BIST Fail Status
ipt_bist_done
Output
Aggregate Memory BIST Execution Status
ipt_bist_bitmap[15:0]
Output
Memory BIST Bitmap Data Out
ipt_bist_sdo
Output
Memory BIST Bitmap Serial Data Out
ipt_bist_addr_out[17:0]
Output
Memory BIST Address Out
ipt_bist_bmdata_avail
Output
Memory BIST Bitmap Data Strobe
ipt_bist_done_dcache
Output
Data Cache Memory BIST Done
ipt_bist_done_etb
Output
ETB Memory BIST Done
ipt_bist_done_icache
Output
Instruction Cache Memory BIST Done
ipt_bist_done_mmu
Output
MMU Memory BIST Done
ipt_bist_done_mram
Output
MCTL RAM Memory BIST Done
ipt_bist_done_mrom
Output
MCTL ROM Memory BIST Done
ipt_bist_fail_dcache
Output
Data Cache Memory BIST Fail
ipt_bist_fail_etb
Output
ETB Memory BIST Fail
ipt_bist_fail_icache
Output
Instruction Cache Memory BIST Fail
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ARM9 Platform
Table 9-8. ARM9 Platform Signal List (continued)
Signal
Type
ipt_bist_fail_mmu
Output
MMU Memory BIST Fail
ipt_bist_fail_mram
Output
MCTL RAM Memory BIST Fail
ipt_bist_config_addr_mode[2:0]
Input
Memory BIST Address Mode Selection
ipt_bist_config_alt_al_en
Input
Memory BIST Alternate Algorithm Enable
ipt_bist_config_aftest_en
Input
Memory BIST Address Fault Test Enable
ipt_bist_config_dpat_en[7:0]
Input
Memory BIST Data Pattern Enable
ipt_bist_config_dret_en
Input
Memory BIST Data Retention Test Enable
ipt_bist_config_dsof
Input
Memory BIST Disable “Stop on Fail”
ipt_bist_config_marchc_en
Input
Memory BIST Marching Pattern Test Enable
ipt_bist_config_sdd_en
Input
Memory BIST SDD Test Enable
ipt_bist_config_sel_dcache
Input
Memory BIST Data Cache Engine Select
ipt_bist_config_sel_etb
Input
Memory BIST ETB Engine Select
ipt_bist_config_sel_icache
Input
Memory BIST Instruction Cache Engine Select
ipt_bist_config_sel_mmu
Input
Memory BIST MMU Engine Select
ipt_bist_config_sel_mram
Input
Memory BIST MCTL RAM Engine Select
ipt_bist_config_sel_mrom
Input
Memory BIST MCTL ROM Engine Select
ipt_bist_config_usrctrl_bm
Input
Memory BIST User Controlled Parallel Bitmap Output Rate
ipt_bist_invoke
Input
Memory BIST Invoke
ipt_bist_mode[2:0]
Input
Memory BIST Mode Select
ipt_bist_release
Input
Memory BIST Pause State Release
ipt_bist_repdata_out_en
Input
Memory BIST Repair Data Output Enable
ipt_bist_reset
Input
Memory BIST Reset
ipt_bist_retention_en
Input
Memory BIST Retention Enable
ipt_bist_sdi
Input
Memory BIST Serial Data In
ipt_bist_serial_data_en
Input
Memory BIST Serial Data Enable
ipt_bist_shift_clk
Input
Memory BIST Shift Clock
9.13
Description
Electrical Specifications
This section will present timing information for all major AHBs (both internal and external) to the
platform. Timing information on all other signals on the platform periphery will be grouped by
functionality and presented after the AHB timings.
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ARM9 Platform
9.13.1
Conditions
The timing presented in this section were derived from an ARM926EJ-S synthesis run using the C90LP
library, worst case process, 105oC, 1.10V with clk running at 266 MHz. In this case, the hclk domain (all
AHBs) will run at half the clk speed or 133 MHz.
9.13.2
Well Bias Mode
The timing specifications in this section do not cover the well bias mode of operation. At the present time,
well bias mode is planned to be used in Sleep Mode only. That is, clk and hclk will be stopped and the
platform buses will be inactive. However, the negation of the a9p_clock_off output when an interrupt is
asserted is still required in order for the external clock control module to exit Sleep Mode and turn on the
clocks. The delay for the a9p_int_b[61:0] to a9p_clock_off path will be affected by well bias mode, but
not significantly so.
9.13.2.1
Functional Operation in Well Bias Mode
Programmable options should be used to support laboratory testing of the platform in well bias mode. The
platform’s AC performance will be impacted (slower) when well biasing is enabled and is TBD. Care
should be taken to identify external interfaces which may not be running in well bias mode as clock
insertion and clock skew differences may prevent proper operation.
9.13.3
clk and jtag_tck Relationship
The jtag_tck clock input must always be less than 1/8 the frequency of the clk clock input. This constraint
is due to the JTAG synchronization logic in the CLKCTL module. During the execution of low-power
code, the frequency of clk is dynamic, and therefore care should be taken that jtag_tck is always less than
1/8 the frequency of clk at any given instant.
To maximize throughput via the JTAG port when uploading/downloading code or memory images, it is
suggested the debugger enter debug mode directly out of reset with clk and jtag_tck running as fast as
possible. However, once normal mode low-power code execution begins, the jtag_tck frequency should be
set to be 1/8 the frequency of the lowest possible clk frequency.
9.13.4
Clocks and Reset Timing
Table 9-9 and Figure 9-10 are valid for all AHB interfaces on the ARM9 Platform. The same clock
insertion delay and hreset_b negation timing will be used for all modules on the ARM9 Platform.
Table 9-9. ARM9 Platform AHB Clock and Reset Timing Constraints
Description
CLK_ROOT Period
CLK_ROOT jitter (3% rounded up)
HCLK_ROOT Period
HCLK_ROOT jitter (3% rounded up)
Delay
3.75 ns (266 MHz)
115.0 ps
7.5 ns (133 MHz)
230.0 ps
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ARM9 Platform
Table 9-9. ARM9 Platform AHB Clock and Reset Timing Constraints (continued)
Description
Delay
CLK_ROOT to CLK and HCLK_ROOT to HCLK Insertion Delay (Tinsert)
1.60 +/– 0.100 ns
CLK and HCLK Uncertainty
200 ps
HRESET_B hold time to HCLK_LEAF (Tihrst)
1.80 ns
HRESET_B setup time to HCLK_LEAF (Tisrst)
1.60 ns
HCLKEN setup time to CLK_LEAF (Tisclken)
2.00 ns
HCLKEN hold time to CLK_LEAF (Tihclken)
0.00 ns
CLK_ROOT
CLK_LEAF
HCLK_ROOT
HCLK_LEAF
HRESET_B
Tihrst
Tisrst
Tinsert
HCLKEN
Tisclken
Figure 9-10. ARM9 Platform AHB Clock and Reset Timing Relationship
9.13.5
Alternate Bus Master (ABM) Interface Timing
Table 9-10 shows the loading constraints used on all ARM9 Platform Alternate Bus Master bus interfaces.
The timing parameters in Figure 9-11 reflect these constraints. The Alternate Bus Master signals are
designated by the “MX_” prefix attached to the normal AHB naming convention.
Table 9-10. Alternate Bus Master Constraints
Description
All Output Loading
Input Transition Time (platform boundary)
Value
0.50 pf
0.750 ns (20/80)
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ARM9 Platform
HCLK_ROOT
Tinsert
HCLK_LEAF
MX_HTRANS[1:0]
MX_HPROT[3:0]
MX_HLOCK
MX_HMASTLOCK
MX_HMASTER
Transfer Type
Tihtr
Tistr
MX_HADDR[31:0]
Address
Tiha
Tisa
MX_HBURST[3:0]
Transfer Control
MX_HWRITE
Tihctl
Tisctl
MX_HWDATA[31:0]
Write Data (A)
MX_HSIZE[2:0]
Tihwd
Tiswd
MX_HREADY_OUT
Tovrdyo
MX_HRDATA[31:0]
Tohrdyo
Read Data (A)
Tovrd
Tohrd
OK
MX_HRESP[1:0]
Tovrsp
Tohrsp
Figure 9-11. Alternate Bus Master Timing Parameters
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ARM9 Platform
Table 9-11. Alternate Bus Master Interface AC Timing Parameters
Description
Parameter
Timing (ns)
HCLK_LEAF minimum clock period including jitter
Tclk
7.27
MX_HMASTER/MX_HTRANS/MX_HPROT/MX_HLOCK/MX_HMASTLOCK/MX_HMAS
TER Transfer Type setup time before HCLK_LEAF
Tistr
6.23
MX_HMASTER/MX_HTRANS/MX_HPROT/MX_HLOCK/MX_HMASTLOCK/
MX_HMASTER Transfer Type hold time after HCLK_LEAF
Tihtr
>0
MX_HADDR[31:0] Address setup time before HCLK_LEAF
Tisa
6.23
MX_HADDR[31:0] Address hold time after HCLK_LEAF
Tiha
>0
MX_HWRITE/MX_HSIZE/MX_HBURST control signal setup time before HCLK_LEAF
Tisctl
6.23
MX_HWRITE/MX_HSIZE/MX_HBURST control signal hold time after HCLK_LEAF
Tihctl
>0
MX_HWDATA Write Data setup time before HCLK_LEAF
Tiswd
6.00
MX_HWDATA Write Data hold time after HCLK_LEAF
Tihwd
>0
MX_HREADY_OUT Ready Out valid time after HCLK_LEAF
Tovrdyo
4.80
MX_HREADY_OUT Ready Out hold time after HCLK_LEAF
Tohrdyo
>0
MX_HRDATA Read Data valid time after HCLK_LEAF
Tovrd
6.00
MX_HRDATA Read Data hold time after HCLK_LEAF
Tohrd
>0
MX_HRESP0 valid time after HCLK_LEAF
Tovrsp
6.00
MX_HRESP0 hold time after HCLK_LEAF
Tohrsp
>0
9.13.6
Secondary AHB Timing
Table 9-12 shows the loading constraints used on all ARM9 Platform Secondary AHB interfaces. The
timing parameters in Figure 9-13 reflect these constraints. The constraints and AC parameters are valid for
all 3 of the platform’s secondary AHBs. The Secondary AHB signals are designated by the “SX_” prefix
attached to the normal AHB naming convention.
Table 9-12. Secondary AHB Constraints
Description
Value
SX_HADDR, SX_HWDATA Loading
0.50 pf
All Other Output Loading
0.50 pf
Input Transition Time (at platform boundary)
0.75 ns (20/80)
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ARM9 Platform
HCLK_ROOT
Tinsert
HCLK_LEAF
SX_HTRANS[1:0]
SX_HPROT[3:0]
SX_HMASTLOCK
SX_HMASTER[3:0]
Transfer Type
Tohtr
Tovtr
Address
SX_HADDR[31:0]
Toha
Tova
SX_HWRITE
SX_HSIZE[1:0]
Transfer Control
Tohctl
SX_HBURST[3:0]
Tovctl
Write Data (A)
SX_HWDATA[31:0]
Tohwd
Tovwd
SX_HREADY
Tisrdy
Tihrdy
SX_HRDATA[31:0]
Read Data (A)
Tisrd
Tihrd
OK
SX_HRESP0
Tisrsp
Tihrsp
Figure 9-12. Secondary AHB AC TIming Parameters
Table 9-13. Secondary AHB AC Timing Parameters
Description
Parameter
Timing (ns)
HCLK_LEAF minimum clock period including jitter
Tclk
7.27
SX_HTRANS/SX_HPROT/SX_HMASTLOCK/SX_HMASTER Transfer Type valid time after
HCLK_LEAF
Tovtr
5.00
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ARM9 Platform
Table 9-13. Secondary AHB AC Timing Parameters (continued)
Description
Parameter
Timing (ns)
SX_HTRANS/SX_HPROT/SX_HMASTLOCK/SX_HMASTER Transfer Type hold time after
HCLK_LEAF
Tohtr
>0
SX_HADDR[31:0] Address valid time after HCLK_LEAF
Tova
4.30
SX_HADDR[31:0] Address hold time after HCLK_LEAF
Toha
>0
SX_HWRITE/SX_HSIZE/SX_HBURST control signal valid time after HCLK_LEAF
Tovctl
5.70
SX_HWRITE/SX_HSIZE/SX_HBURST control signal hold time after HCLK_LEAF
Tohctl
>0
SX_HWDATA Write Data valid time after HCLK_LEAF
Tovwd
5.70
SX_HWDATA Write Data hold time after HCLK_LEAF
Tohwd
>0
SX_HREADY setup time before HCLK_LEAF
(input to slaves)
Tisrdy
5.60
SX_HREADY hold time after HCLK_LEAF
Tihrdy
>0
SX_HRDATA setup time before HCLK_LEAF
Tisrd
4.10
SX_HRDATA hold time after HCLK_LEAF
Tihrd
>0
SX_HRESP0 setup time before HCLK_LEAF
Tisrsp
4.10
SX_HRESP0 hold time after HCLK_LEAF
Tihrsp
>0
9.13.7
RAM and ROM Interface Timing
Table 9-14 shows the loading constraints used when generating timing parameters on the ARM9
Platform’s RAM and ROM interfaces. External RAM and ROM interface signals not shown in the table
below are either static or test related.
Table 9-14. RAM and ROM Interface Loading Constraints
Signal
Type
Constraint
MCTL_OEN_RAM
Output
0.50 pf
MCTL_CE_RAM_B
Output
0.25 pf
MCTL_WR_RAM_B
Output
0.50 pf
MCTL_ADDR_RAM[17:0]
Output
0.50 pf
MCTL_BEN_RAM_*_*
Output
0.50 pf
MCTL_D_RAM[31:0]
Output
0.50 pf
MEM_Q_RAM[31:0]
Input
0.75 ns
(Input Transition Time)
Output
0.25 pf
RAM
ROM
MCTL_CE_ROM_B
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
9-44
Freescale Semiconductor
ARM9 Platform
Table 9-14. RAM and ROM Interface Loading Constraints (continued)
Signal
Type
Constraint
MCTL_ADDR_ROM[19:0]
Output
0.50 pf
MEM_Q_ROM[31:0]
Input
0.75 ns
(Input Transition Time)
hclk
hclk_leaf
Tovaram
mctl_addr_ram[17:0]
Tovdram
mctl_d_ram[31:0]
Tovcram
mctl_ce_ram_b
Tovwram
mctl_wr_ram_b
Tovbram
mctl_ben_ram
Tisqram
mem_q_ram[31:0]
Tovarom
mctl_addr_rom[19:0]
Tovcrom
mctl_ce_rom_b
Tisqrom
mem_q_rom[31:0]
Figure 9-13. RAM and ROM Interface AC Timing Parameters
Table 9-15. RAM and ROM Interface AC Timing Parameters
Description
Parameter
Timing (ns)
HCLK_LEAF minimum clock period
Tclk
8.40
Tovaram
6.65
RAM
MCTL_ADDR_RAM valid time after HCLK_LEAF
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Freescale Semiconductor
9-45
ARM9 Platform
Table 9-15. RAM and ROM Interface AC Timing Parameters (continued)
Description
Parameter
Timing (ns)
MCTL_D_RAM valid time after HCLK_LEAF
Tovdram
6.60
MCTL_CE_RAM_B valid time after HCLK_LEAF
Tovcram
6.70
MCTL_WR_RAM_B valid time after HCLK_LEAF
Tovwram
6.55
MCTL_BEN_RAM_*_* valid time after HCLK_LEAF
Tovbram
6.6
MEM_Q_RAM setup time before HCLK_LEAF
Tisqram
4.65
MEM_Q_RAM hold time after HCLK_LEAF
Tihqram
>0
MCTL_ADDR_ROM valid time after HCLK_LEAF
Tovarom
6.55
MCTL_CE_ROM_B valid time after HCLK_LEAF
Tovcrom
6.80
MEM_Q_ROM setup time before HCLK_LEAF
Tisqrom
3.85
MEM_Q_ROM hold time after HCLK_LEAF
Tihqrom
>0
ROM
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Freescale Semiconductor
Chapter 10
ARM926EJ-S Interrupt Controller (AITC)
The ARM926EJ-S Interrupt Controller (AITC) is a 32-bit peripheral that collects interrupt requests from
up to 64 sources, and provides an interface to the ARM926EJ-S core. The AITC includes
software-controlled priority levels for normal interrupts. Figure 10-1 shows the simplified block diagram
of the AITC.
aitc_fiq
64
INTENABLE
fipend
64
64
intin
FORCE
64
64
64
64
nipend
INTTYPE
6
Priority
Encoder
Software
Priority
Encoder
fivector
nivector
6
aitc_irq
aitc_rdata_ovr
NM
32
Equals to
0x0000_0018?
haddr
Equals to
0x0000_001C?
FM
Opcode
Generator
32
aitc_rdata
hready
Figure 10-1. AITC Block Diagram
10.1
Overview
The AITC consists of a set of control registers and associated logic to perform interrupt masking, and
priority support of normal interrupts. Interrupt source registers (INTSRCH/INTSRCL) are a pair of 32-bit
status registers with a single interrupt source associated with each of the 64 bits. An interrupt line or set of
interrupt lines are routed from each interrupt source to the INTSRCH or INTSRCL register. This allows
up to 64 distinct interrupt sources in an implementation.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
10-1
ARM926EJ-S Interrupt Controller (AITC)
10.1.1
Features
10.1.2
Modes of Operation
Interrupt requests may be forced to be asserted by way of the interrupt force registers
(INTFRCH/INTFRCL). Each bit in this register is logically “OR-ed” with the corresponding hardware
request line prior to feeding the INTSRCH or INTSRCL register inputs. There is a corresponding set of
interrupt enable registers (INTENABLEH/INTENABLEL), also 32-bits wide which allow individual bit
masking of the INTSRCH/INTSRCL registers. There is also a corresponding set of interrupt type register
(INTTYPEH/INTTYPEL), which selects whether an interrupt source will generate a normal or fast
interrupt to the ARM926EJ-S core.
There is a corresponding set of normal interrupt pending registers (NIPNDH/NIPNDL) which indicate
pending normal interrupt requests. These registers are equivalent to the logical AND of the interrupt source
registers (INTSRCH/INTSRCL), the interrupt enable registers (INTENABLEH/INTENABLEL), and the
NOT of the interrupt type registers (INTTYPEH/INTTYPEL). (Refer to Figure 10-1) The
NIPNDH/NIPNDL register bits are bit-wise “NOR-ed” together to form the nIRQ signal routed to the
ARM926EJ-S core. This core input signal is maskable by the normal interrupt disable bit (I bit) in the
processor status register (CPSR). The normal interrupt vector register (NIVECSR) indicates the vector
index of highest priority pending normal interrupt.
There is a corresponding set of fast interrupt pending registers (FIPNDH/FIPNDL) which indicate pending
fast interrupt requests. These registers are equivalent to logical AND of interrupt source registers
(INTSRCH/INTSRCL), interrupt enable registers (INTENABLEH/INTENABLEL), and interrupt type
registers (INTTYPEH/INTTYPEL). (Refer to Figure 10-1) FIPNDH/FIPNDL register bits are bit-wise
“NOR-ed” together to form the nFIQ signal routed to the ARM926EJ-S core. This core input signal is
maskable by the fast interrupt disable bit (F bit) in the CPSR. The fast interrupt vector register (FIVECSR)
indicates the vector index of highest priority pending fast interrupt.
AITC supports two vector table modes: high memory and low memory. If AITC is in high memory vector
table mode, opcode is “LDR PC, [PC,#-(288-4*(vector index)]”. This causes ARM926-ES core to load the
Program Counter (PC) with a vector from a table of 64 vectors located at 0xFFFF_FF00 to 0xFFFF_FFFF;
more specifically the PC is loaded with the vector located at 0xFFFF_FF00 + 4*(vector index). If AITC
is in low memory vector table mode, this opcode is “LDR PC, [PC, #((table pointer)+4*(vector index)
–32]”. This causes the ARM926-EJS core to load the PC with a vector from a table of 64 vectors beginning
at (table pointer) and ending at (table pointer)+0xFF; more specifically the PC is loaded with the vector
located at (table pointer) + 4*(vector index). This hardware mechanism alleviates the need for software to
determine which interrupt source caused the interrupt to be asserted. All interrupt controller registers can
be read and written during privileged mode only. Writes attempted to read-only registers will be ignored.
These registers can be only modified using 32-bit writes. INTFRCH/INTFRCL registers are provided for
software generation of interrupts. By enabling interrupts for these bit positions, software can force an
interrupt request. This register can also be used to debug hardware interrupt service routines by providing
an alternate method of interrupt assertion. The interrupt requests are prioritized in the following sequence:
1. Fast interrupt requests, in order of highest number
2. Normal interrupt requests, in order of highest priority level, then highest source number with the
same priority
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
AITC provides 16 software controlled priority levels for normal interrupts. Every interrupt can be placed
in any priority level. The AITC also provides a normal interrupt priority level mask (NIMASK) which
disables any interrupt with a priority level lower than or equal to the mask. If a level 0 normal interrupt
and a level 1 normal interrupt are asserted at the same time, the level 1 normal interrupt will be selected
assuming that NIMASK has not disabled level 1 normal interrupts. If two level 1 normal interrupts are
asserted at the same time, the level 1 normal interrupt with the highest source number will be selected, also
assuming that NIMASK has not disabled level 1 normal interrupts.
10.2
Memory Map and Register Definition
AITC module has 26 registers. All of these registers are single cycle access as the AITC sits on the native
bus of the ARM926EJ-S core. This section provides the detailed descriptions for all of the AITC registers.
10.2.1
Memory Map
Table 10-1 shows the AITC memory map.
Table 10-1. AITC Memory Map
Address
Register
Access
Reset Value
Section/Page
General Registers
0x1004_0000 (INTCNTL)
Interrupt Control Register
R/W
0x0000_0000
10.2.3/10-8
0x1004_0004 (NIMASK)
Normal Interrupt Mask Register
R/W
0x0000_001F
10.2.4/10-10
0x1004_0008 (INTENNUM)
Interrupt Enable Number Register
R/W
0x0000_0000
10.2.5/10-11
0x1004_000C (INTDISNUM)
Interrupt Disable Number Register
R/W
0x0000_0000
10.2.6/10-12
0x1004_0010 (INTENABLEH)
Interrupt Enable Register High
R/W
0x0000_0000
10.2.7/10-13
0x1004_0014 (INTENABLEL)
Interrupt Enable Register Low
R/W
0x0000_0000
10.2.7/10-13
0x1004_0018 (INTTYPEH)
Interrupt Type Register High
R/W
0x0000_0000
10.2.8/10-14
0x1004_001C (INTTYPEL)
Interrupt Type Register Low
R/W
0x0000_0000
10.2.8/10-14
0x1004_0020 (NIPRIORITY7)
Normal Interrupt Priority Level Register 7
R/W
0x0000_0000
10.2.9/10-15
0x1004_0024 (NIPRIORITY6)
Normal Interrupt Priority Level Register 6
R/W
0x0000_0000
10.2.9/10-15
0x1004_0028 (NIPRIORITY5)
Normal Interrupt Priority Level Register 5
R/W
0x0000_0000
10.2.9/10-15
0x1004_002C (NIPRIORITY4) Normal Interrupt Priority Level Register 4
R/W
0x0000_0000
10.2.9/10-15
0x1004_0030 (NIPRIORITY3)
Normal Interrupt Priority Level Register 3
R/W
0x0000_0000
10.2.9/10-15
0x1004_0034 (NIPRIORITY2)
Normal Interrupt Priority Level Register 2
R/W
0x0000_0000
10.2.9/10-15
0x1004_0038 (NIPRIORITY1)
Normal Interrupt Priority Level Register 1
R/W
0x0000_0000
10.2.9/10-15
0x1004_003C (NIPRIORITY0) Normal Interrupt Priority Level Register 0
R/W
0x0000_0000
10.2.9/10-15
0x1004_0040 (NIVECSR)
Normal Interrupt Vector and Status Register
R
0xFFFF_FFFF
10.2.10/10-23
0x1004_0044 (FIVECSR)
Fast Interrupt Vector and Status Register
R
0xFFFF_FFFF
10.2.11/10-24
0x1004_0048 (INTSRCH)
Interrupt Source Register High
R
0x0000_0000
10.2.12/10-25
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
10-3
ARM926EJ-S Interrupt Controller (AITC)
Table 10-1. AITC Memory Map (continued)
Address
Register
Access
Reset Value
Section/Page
0x1004_004C (INTSRCL)
Interrupt Source Register Low
R
0x0000_0000
10.2.12/10-25
0x1004_0050 (INTFRCH)
Interrupt Force Register High
R/W
0x0000_0000
10.2.13/10-28
0x1004_0054 (INTFRCL)
Interrupt Force Register Low
R/W
0x0000_0000
10.2.13/10-28
0x1004_0058 (NIPNDH)
Normal Interrupt Pending Register High
R
0x0000_0000
10.2.14/10-29
0x1004_005C (NIPNDL)
Normal Interrupt Pending Register High
R
0x0000_0000
10.2.14/10-29
0x1004_0060 (FIPNDH)
Fast Interrupt Pending Register High
R
0x0000_0000
10.2.15/10-30
0x1004_0064 (FIPNDL)
Fast Interrupt Pending Register Low
R
0x0000_0000
10.2.15/10-30
10.2.2
Register Summary
Figure 10-2 shows the key to the register fields and Table 10-2 shows the register figure conventions.
Always
reads 1
1
Always
reads 0
0
R/W BIT Read- BIT Write-only
bit
only bit
bit
BIT
Write 1 BIT Self-clear 0
to clear
bit
w1c
BIT
N/A
Figure 10-2. Key to Register Fields
Table 10-2. Register Figure Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writable.
FIELDNAME
Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
r
Read only. Writing this bit has no effect.
w
Write only.
rw
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by a hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
Self-clearing
bit
Writing a one has some effect on the module, but it always reads as zero.
Reset Values
0
Resets to zero.
1
Resets to one.
—
Undefined at reset.
u
Unaffected by reset.
[signal_name] Reset value is determined by polarity of indicated signal.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
10-4
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
Table 10-3 shows the AITC register summary.
Table 10-3. AITC Register Summary
Name
R
0x1004_0000
(INTCNTL)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
NIA
D
FIA
D
0
0
W
R
0
0
0
NIDI FIDI
S
S
MD
0
0
0
0
0
POINTER
W
R
0x1004_0004
(NIMASK)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
NIMASK
W
R
0x1004_0008
(INTENNUM)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
R
0x1004_000C
(INTDISNUM)
ENNUM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
DISNUM
R
INTENABLE[63:48]
0x1004_0010 W
(INTENABLEH) R
INTENABLE[47:32]
W
R
INTENABLE[31:16]
0x1004_0014
(INTENABLEL)
W
R
INTENABLE[15:0]]
W
R
INTTYPE[63:48]
0x1004_0018
(INTTYPEH)
W
R
INTTYPE[47:32]
W
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
10-5
ARM926EJ-S Interrupt Controller (AITC)
Table 10-3. AITC Register Summary (continued)
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
INTTYPE[31:16]
0x1004_001C
(INTTYPEL)
W
R
INTTYPE[16:0]
W
R
NIPR63
NIPR62
NIPR61
NIPR60
NIPR59
NIPR58
NIPR57
NIPR56
NIPR55
NIPR54
NIPR53
NIPR52
NIPR51
NIPR50
NIPR49
NIPR48
NIPR47
NIPR46
NIPR45
NIPR44
NIPR43
NIPR42
NIPR41
NIPR40
NIPR39
NIPR38
NIPR37
NIPR36
NIPR35
NIPR34
NIPR33
NIPR32
NIPR31
NIPR30
NIPR29
NIPR28
NIPR27
NIPR26
NIPR25
NIPR24
NIPR23
NIPR22
NIPR21
NIPR20
NIPR19
NIPR18
NIPR17
NIPR16
NIPR15
NIPR14
NIPR13
NIPR12
NIPR11
NIPR10
NIPR9
NIPR8
0x1004_0020 W
(NIPRIORITY7) R
W
R
0x1004_0024 W
(NIPRIORITY6) R
W
R
0x1004_0028 W
(NIPRIORITY5) R
W
R
0x1004_002C W
(NIPRIORITY4) R
W
R
0x1004_0030 W
(NIPRIORITY3) R
W
R
0x1004_0034 W
(NIPRIORITY2) R
W
R
0x1004_0038 W
(NIPRIORITY1) R
W
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
10-6
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
Table 10-3. AITC Register Summary (continued)
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
NIPR7
NIPR6
NIPR5
NIPR4
NIPR3
NIPR2
NIPR1
NIPR0
0x1004_003C W
(NIPRIORITY0) R
W
R
0x1004_0040
(NIVECSR)
NIVECTOR
W
R
NIPRILVL
W
R
0x1004_0044
(FIVECSR)
FIVECTOR
W
R
FIVECTOR
W
R
0x1004_0048
(INTSRCH)
INTIN[63:48]
W
R
INTIN[48:32]
W
R
0x1004_004C
(INTSRCL)
INTIN[31:16]
W
R
INTIN[15:0]
W
R
0x1004_0050
(INTFRCH)
FORCE[63:48]
W
R
FORCE[47:32]
W
R
0x1004_0054
(INTFRCL)
FORCE[31:16]
W
R
FORCE[15:0]
W
R
0x1004_0058
(NIPNDH)
NIPEND[63:48]
W
R
NIPEND[47:32]
W
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
10-7
ARM926EJ-S Interrupt Controller (AITC)
Table 10-3. AITC Register Summary (continued)
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0x1004_005C
(NIPNDL)
NIPEND[31:16]
W
R
NIPEND[15:0]
W
R
0x1004_0060
(FIPNDH)
FIPEND[63:48]
W
R
FIPEND[47:32]
W
R
0x1004_0064
(FIPNDL)
FIPEND[31:16]
W
R
FIPEND[15:0]
W
10.2.3
Interrupt Control Register (INTCNTL)
INTCNTL controls the interrupts in AITC. Both normal and fast interrupts can be enabled to jump directly
to the interrupt service routine. For fast interrupts, it may be faster to begin to fast interrupt routine at
0x0000_001C instead of jumping to a service routine. The vector table can be sourced in high memory,
0xFFFF_FF00 to 0xFFFF_FFFF, or in low memory. If the vector table is located in low memory (MD=1),
a register has been provided to control where the vector table is located. This register is located on the
ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed to in privileged mode. This
register can be only modified using 32-bit writes.
0x1004_0000 (INTCNTL)
R
Access: Supervisor read/write
31
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
0
0
0
0
0
W
Reset
R
21
20
19
18
17
0
0
0
0
0
3
2
NIDIS FIDIS NIAD FIAD
POINTER
W
Reset
22
0
0
0
0
0
0
0
0
0
0
16
MD
0
1
0
0
0
0
0
Figure 10-3. Interrupt Control Register Format
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
10-8
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
Table 10-4. Interrupt Control Register Field Description
Field
Description
31–23
Reserved. These bits are reserved and should read 0.
22
NIDIS
Normal Interrupt Disable. This bit, when set, disables the generation of the normal interrupt signal. This bit is similar
to the I bit of the ARM926EJ-S core. This bit along with the FIDIS bit is used to enable secure operations.
0 Does not affect the normal interrupt generation
1 Disable all normal interrupts
21
FIDIS
Fast Interrupt Disable. This bit, when set, disables the generation of the fast interrupt signal. This bit is similar to
the F bit of the ARM926EJ-S core. This bit along with the NIDIS bit is used to enable secure operations.
0 Does not affect the fast interrupt generation
1 Disable all fast interrupts
20
NIAD
Normal Interrupt Arbiter Rise ARM Level. This bit, when asserted, increases bus arbitration priority of ARM core
when normal interrupt signal (nIRQ) is asserted. If an alternate master has ownership of the bus when a normal
interrupt occurs, bus will be given back to the processor core after the DMA device has completed its accesses.
NIAD bit does not affect alternate master accesses that are in progress. To prevent an alternate master from
accessing the bus during an interrupt service routine, the interrupt flag must not be cleared until the end of the
service routine. Another option is to use the ABFEN and ABFLAG bits.
0 Disregard the normal interrupt flag when evaluating bus requests
1 Normal interrupt flag increases bus arbitration priority of the ARM core to decrease the latency of Interrupt
service routine
19
FIAD
Fast Interrupt Arbiter Rise ARM Level. This bit functions same as NIAD bit except for the fast interrupts (nFIQ).
0 Disregard the fast interrupt flag when evaluating bus requests
1 Fast interrupt flag increases bus arbitration priority of the ARM core to decrease the latency of interrupt service
routine.
18–17
Reserved. These bits are reserved and should read 0.
16
MD
15–12
Interrupt Vector Table Mode. Indicates whether the interrupt vector is located in high memory or low memory.
0 Interrupt vector table located in high memory from 0xFFFF_FF00 to 0xFFFF_FFFF
1 Interrupt vector table located in low memory from POINTER to POINTER+0xFF
Reserved. These bits are reserved and should read 0.
11–2
Interrupt Vector Table Pointer. Indicates start of vector table when in low memory (MD =1). Only word-aligned tables
POINTER are allowed, and 2 zeros are added in the LSBs when this value is used by AITC. The value stored here is left
shifted by 2 bits, so the actual table vector can be directly written into the appropriate bits. The value stored in 10
bits, times 4, must be set greater than or equal to 0x0000_0024 and less than or equal to 0x0000_0F00.
1–0
Reserved. These bits are reserved and should read 0.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
10-9
ARM926EJ-S Interrupt Controller (AITC)
10.2.4
Normal Interrupt Mask Register (NIMASK)
NIMASK controls the normal interrupt mask level. All normal interrupts with a priority level lower than
or equal to NIMASK are disabled. The priority level of normal interrupts are determined by the normal
interrupt priority level registers (NIPRIORITY7–0). Reset state of this register does not disable any
normal interrupts. Writing all 1’s, or –1, to NIMASK sets normal interrupt mask to –1 which does not
disable any normal interrupt priority levels. This hardware mechanism can be used to create reentrant
normal interrupt routines by disabling lower priority normal interrupts. Refer Section 10.3.6 for more
details on use of NIMASK register. This register is located on the ARM926EJ-S native bus, accessible in
1 cycle, and can only be accessed to in privileged mode. This register can be only modified using 32-bit
writes.
Address 0x1004_0004 (NIMASK)
R
Access: Supervisor
read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
W
Reset
R
NIMASK
W
Reset
1
1
1
Figure 10-4. Normal Interrupt Mask Register Format
Table 10-5. Normal Interrupt Mask Register Field Description
Field
31–5
4–0
NIMASK
Description
Reserved. These bits are reserved and should read 0.
Normal Interrupt Mask. Controls normal interrupt mask level. All normal interrupts of priority level lower than or
equal to the NIMASK will be disabled.
0 Disable priority level 0 normal interrupts
1 Disable priority level 1 and lower normal interrupts
...
0xE (14)Disable priority level 14 and lower normal interrupts
0xF (15)Disable all normal interrupts
0x10–0x1FDo not disable any normal interrupts
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
10-10
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
10.2.5
Interrupt Enable Number Register (INTENNUM)
The Interrupt Enable Number Register provides hardware accelerated enabling of interrupts. Any write to
this register enables an interrupt source. If 6 LSBs are 000000, then interrupt source 0 is enabled. If 6 LSBs
are 000001, then interrupt source 1 is enabled. And so forth. This register is decoded into a one hot mask
that is logically OR-ed with INTENABLEH/INTENABLEL register. This hardware mechanism alleviates
the need for an atomic read/modify/write sequence to enable an interrupt source. To enable interrupts 10
and 20, software only preforms two writes to AITC: first write 10 to INTENNUM register, then write 20
to INTENNUM register (order of writes is irrelevant). This register is located on the ARM926EJ-S native
bus, accessible in 1 cycle, and can only be accessed to in privileged mode. This register can be only
modified using 32-bit writes. This register always reads back all 0s.
Address 0x1004_0008 (INTENNUM)
R
Access: Supervisor
read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
ENNUM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-5. Interrupt Enable Number Register Format
Table 10-6. Interrupt Enable Number Register Description
Field
31–6
5–0
ENNUM
Description
Reserved. These bits are reserved and should read 0.
Interrupt Enable Number. Writing to this register will enable the interrupt source associated with this value.
0 Enable interrupt source 0
1 Enable interrupt source 1
...
63 Enable interrupt source 63
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
10-11
ARM926EJ-S Interrupt Controller (AITC)
10.2.6
Interrupt Disable Number Register (INTDISNUM)
The Interrupt Disable Number Register provides hardware accelerated disabling of interrupts. Any write
to this register disables one interrupt source. If the 6 LSBs are equal 000000, then interrupt source 0 is
disabled. If the 6 LSBs equal 000001, then interrupt source 1 is disabled, and so on. This register is
decoded into a one hot mask which is inverted and logically AND-ed with the
INTENABLEH/INTENABLEL register. The hardware mechanism alleviates the need for an atomic
read/modify/write sequence to disable an interrupt source. To disable interrupts 10 and 20, the software
need only preform two writes to the AITC: first write 10 to INTDISNUM register, then write 20 to
INTDISNUM register (the order of the writes is irrelevant). This register is located on the ARM926EJ-S
native bus, accessible in 1 cycle, and can only be accessed to in privileged mode. This register can be only
modified using 32-bit writes. This register always reads back all 0s.
Address 0x1004_000C (INTDISNUM)
R
Access: Supervisor
read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
DISNUM
0
0
Figure 10-6. Interrupt Enable Number Register Format
Table 10-7. Interrupt Disable Number Register Field Description
Field
31–6
5–0
DISNUM
Description
Reserved. These bits are reserved and should read 0.
Interrupt Disable Number. Writing to this register will disable the interrupt source associated with this value.
0 Disable interrupt source 0
1 Disable interrupt source 1
...
63 Disable interrupt source 63
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
10-12
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
10.2.7
Interrupt Enable Register High (INTENABLEH) and Low
(INTENABLEL)
The INTENABLEH and INTENABLEL registers are used to enable pending interrupt requests to the
ARM9 core. Each bit in these registers corresponds to an interrupt source available in the system. The reset
state of these registers are to have all interrupts masked. These registers can be updated by various
methods: writing directly to INTENABLEH/INTENABLEL registers, setting bits in the INTENNUM
register, or clearing bits in the INTDISNUM register. These registers are located on the ARM926EJ-S
native bus, accessible in 1 cycle, and can only be accessed to in privileged mode. These registers can be
only modified using 32-bit writes.
Address 0x1004_0010 (INTENABLEH)
31
30
29
28
Access: Supervisor
read
27
26
25
R
W rwm
Reset
23
22
21
20
19
18
17
16
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
INTENABLE[47:32]
W rwm
Reset
24
INTENABLE[63:48]
0
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-7. Interrupt Enable Register High Format
Address 0x1004_0014 (INTENABLEL)
31
30
29
28
Access: Supervisor
read
27
26
25
R
W rwm
Reset
23
22
21
20
19
18
17
16
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
INTENABLE[15:0]
W rwm
Reset
24
INTENABLE[31:16]
0
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
rwm
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-8. Interrupt Enable Register Low Format
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
10-13
ARM926EJ-S Interrupt Controller (AITC)
Table 10-8. Interrupt Enable Register Low and High Field Descriptions
Field
Description
31–0
Interrupt Enable. This bit enables the corresponding interrupt source to request a normal interrupt or a fast
INTENABLE interrupt. A reset operation clears this bit. If an enable bit is set and the corresponding interrupt source is
asserted, the interrupt controller will assert a normal or a fast interrupt request depending on associated
INTTYPEH/INTTYPEL setting.
0 Interrupt disabled
1 Interrupt enabled and will generate a normal or fast interrupt upon assertion
10.2.8
Interrupt Type Register High (INTTYPEH) and Low (INTTYPEL)
The INTTYPEH and INTTYPEL registers are used to select whether a pending interrupt source, when
enabled with the INTENABLEH/INTENABLEL, will create a normal interrupt or a fast interrupt to the
ARM9 core. Each bit in these registers corresponds to an interrupt source available in the system. The reset
state of these registers will cause all enabled interrupt sources to generate a normal interrupt. These
registers are located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed to in
privileged mode. These registers can be only modified using 32-bit writes.
Address 0x1004_0018 (INTTYPEH)
31
30
29
28
Access: Supervisor
read/write
27
26
25
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
INTTYPE[47:32]
W
Reset
23
INTTYPE[63:48]
W
Reset
24
0
0
0
0
0
0
0
0
0
Figure 10-9. Interrupt Type Register High Format
Address 0x1004_001C (INTTYPEL)
31
30
29
28
Access: Supervisor
read/write
27
26
25
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
INTTYPE[15:0]
W
Reset
23
INTTYPE[31:16]
W
Reset
24
0
0
0
0
0
0
0
0
0
Figure 10-10. Interrupt Type Register Low Format
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
10-14
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
Table 10-9. Interrupt Type Register High and Low Register Description
Field
Description
31–0
INTTYPE
Interrupt Type. This bit indicates whether the corresponding interrupt source will request a normal interrupt or a
fast interrupt. If INTTYPE bit is set and the corresponding interrupt source is asserted, the interrupt controller will
assert a fast interrupt request.
0 Interrupt source will generate a normal interrupt (nIRQ).
1 Interrupt source will generate a fast interrupt (nFIQ).
Normal Interrupt Priority Level Registers (NIPRIORITYn)
10.2.9
The Normal Interrupt Priority Level Registers (NIPRIORITY7–0) provide a software controllable
prioritization of normal interrupts. Normal interrupts with a higher priority level will preempt normal
interrupts with a lower priority. The reset state of these registers forces all normal interrupts to the lowest
priority level. If a level 0 normal interrupt and a level 1 normal interrupt are asserted at the same time, the
level 1 normal interrupt will be selected assuming that NIMASK has not disabled level 1 normal interrupts.
If two level 1 normal interrupts are asserted at the same time, the level 1 normal interrupt with the highest
source number will be selected, also assuming that NIMASK has not disabled level 1 normal interrupts.
These registers can only be accessed to in privileged mode using 32-bit writes.
Address 0x1004_0020 (NIPRIORITY7)
31
R
28
27
26
25
24
23
NIPR62
22
21
20
19
NIPR61
18
17
16
NIPR60
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
NIPR59
W
Reset
29
NIPR63
W
Reset
30
Access: Supervisor
read/write
0
0
0
NIPR58
0
0
0
0
NIPR57
0
0
0
0
NIPR56
0
0
0
0
0
Figure 10-11. Normal Interrupt Priority Level 7 Register Format
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
10-15
ARM926EJ-S Interrupt Controller (AITC)
Table 10-10. Normal Interrupt Priority Level Register 7 Field Description
Bits
Field
Description
31–28
NIPR63
Normal Interrupt Priority Level. Selects the software controlled priority level for the associated normal
interrupt source. These registers do not affect the prioritization of fast interrupt priorities.
27–24
NIPR62
0 Lowest priority normal interrupt
...
15 Highest priority normal interrupt
23–20
NIPR61
19–16
NIPR60
15–12
NIPR59
11–8
NIPR58
7–4
NIPR57
3–0
NIPR56
Address 0x1004_0024 (NIPRIORITY6)
31
R
28
27
26
25
24
23
NIPR54
22
21
20
19
NIPR53
18
17
16
NIPR52
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
NIPR51
W
Reset
29
NIPR55
W
Reset
30
Access: Supervisor
read/write
0
0
0
NIPR50
0
0
0
0
NIPR49
0
0
0
0
NIPR48
0
0
0
0
0
Figure 10-12. Normal Interrupt Priority Level 6 Register Format
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
10-16
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
Table 10-11. Normal Interrupt Priority Level Register 6 Field Description
Field
Description
31–28
NIPR55
Normal Interrupt Priority Level. Selects the software controlled priority level for the associated normal
interrupt source. These registers do not affect the prioritization of fast interrupt priorities.
27–24
NIPR54
0 Lowest priority normal interrupt
...
15 Highest priority normal interrupt
23–20
NIPR53
19–16
NIPR52
15–12
NIPR51
11–8
NIPR50
7–4
NIPR49
3–0
NIPR48
Address 0x1004_0028 (NIPRIORITY5)
31
R
28
27
26
25
24
23
NIPR46
22
21
20
19
NIPR45
18
17
16
NIPR44
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
NIPR43
W
Reset
29
NIPR47
W
Reset
30
Access: Supervisor
read/write
0
0
0
NIPR42
0
0
0
0
NIPR41
0
0
0
0
NIPR40
0
0
0
0
0
Figure 10-13. Normal Interrupt Priority Level 5 Register Format
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
10-17
ARM926EJ-S Interrupt Controller (AITC)
Table 10-12. Normal Interrupt Priority Level Register 5 Field Description
Field
Description
31–28
NIPR47
27–24
NIPR46
23–20
NIPR45
19–16
NIPR44
15–12
NIPR43
11–8
NIPR42
7–4
NIPR41
3–0
NIPR40
Normal Interrupt Priority Level. Selects the software controlled priority level for the associated normal
interrupt source. These registers do not affect the prioritization of fast interrupt priorities.
0 Lowest priority normal interrupt
...
15 Highest priority normal interrupt
Address 0x1004_002C (NIPRIORITY4)
31
R
28
27
26
25
24
23
NIPR38
22
21
20
19
NIPR37
18
17
16
NIPR36
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
NIPR35
W
Reset
29
NIPR39
W
Reset
30
Access: Supervisor
read/write
0
0
0
NIPR34
0
0
0
0
NIPR33
0
0
0
0
NIPR32
0
0
0
0
0
Figure 10-14. Normal Interrupt Priority Level 4 Register Format
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
10-18
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
Table 10-13. Normal Interrupt Priority Level Register 4 Field Description
Field
Description
31–28
NIPR39
Normal Interrupt Priority Level. Selects the software controlled priority level for the associated normal
interrupt source. These registers do not affect the prioritization of fast interrupt priorities.
27–24
NIPR38
0 Lowest priority normal interrupt
...
15 Highest priority normal interrupt
23–20
NIPR37
19–16
NIPR36
15–12
NIPR35
11–8
NIPR34
7–4
NIPR33
3–0
NIPR32
Address 0x1004_0030 (NIPRIORITY3)
31
R
28
27
26
25
24
23
NIPR30
22
21
20
19
NIPR29
18
17
16
NIPR28
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
NIPR27
W
Reset
29
NIPR31
W
Reset
30
Access: Supervisor
read/write
0
0
0
NIPR26
0
0
0
0
NIPR25
0
0
0
0
NIPR24
0
0
0
0
0
Figure 10-15. Normal Interrupt Priority Level 3 Register Format
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
10-19
ARM926EJ-S Interrupt Controller (AITC)
Table 10-14. Normal Interrupt Priority Level Register 3 Field Description
Field
Description
31–28
NIPR31
Normal Interrupt Priority Level. Selects the software controlled priority level for the associated normal
interrupt source. These registers do not affect the prioritization of fast interrupt priorities.
27–24
NIPR30
0 Lowest priority normal interrupt
...
15 Highest priority normal interrupt
23–20
NIPR29
19–16
NIPR28
15–12
NIPR27
11–8
NIPR26
7–4
NIPR25
3–0
NIPR24
Address 0x1004_0034 (NIPRIORITY2)
31
R
28
27
26
25
24
23
NIPR22
22
21
20
19
NIPR21
18
17
16
NIPR20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
NIPR19
W
Reset
29
NIPR23
W
Reset
30
Access: Supervisor
read/write
0
0
0
NIPR18
0
0
0
0
NIPR17
0
0
0
0
NIPR16
0
0
0
0
0
Figure 10-16. Normal Interrupt Priority Level 2 Register Format
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
10-20
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
Table 10-15. Normal Interrupt Priority Level Register 2 Field Description
Bits
Field
Description
31–28
NIPR23
27–24
NIPR22
Normal Interrupt Priority Level. Selects the software controlled priority level for the associated normal
interrupt source. These registers do not affect the prioritization of fast interrupt priorities.
23–20
NIPR21
19–16
NIPR20
15–12
NIPR19
11–8
NIPR18
7–4
NIPR17
3–0
NIPR16
0 Lowest priority normal interrupt
...
15 Highest priority normal interrupt
Address 0x1004_0038 (NIPRIORITY1)
31
R
28
27
26
25
24
23
NIPR14
22
21
20
19
NIPR13
18
17
16
NIPR12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
NIPR11
W
Reset
29
NIPR15
W
Reset
30
Access: Supervisor
read/write
0
0
0
NIPR10
0
0
0
0
NIPR9
0
0
0
0
NIPR8
0
0
0
0
0
Figure 10-17. Normal Interrupt Priority Level 1 Register Format
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
10-21
ARM926EJ-S Interrupt Controller (AITC)
Table 10-16. Normal Interrupt Priority Level Register 1 Field Description
Field
Description
31–28
NIPR15
Normal Interrupt Priority Level. Selects the software controlled priority level for the associated normal
interrupt source. These registers do not affect the prioritization of fast interrupt priorities.
27–24
NIPR14
0 Lowest priority normal interrupt
...
15 Highest priority normal interrupt
23–20
NIPR13
19–16
NIPR12
15–12
NIPR11
11–8
NIPR10
7–4
NIPR9
3–0
NIPR8
Address 0x1004_003C (NIPRIORITY0)
31
R
28
27
26
25
24
23
NIPR6
22
21
20
19
NIPR5
18
17
16
NIPR4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
NIPR3
W
Reset
29
NIPR7
W
Reset
30
Access: Supervisor
read/write
0
0
0
NIPR2
0
0
0
0
NIPR1
0
0
0
0
NIPR0
0
0
0
0
0
Figure 10-18. Normal Interrupt Priority Level 1 Register Format
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
10-22
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
Table 10-17. Normal Interrupt Priority Level Register 0 Field Description
Bits
Field
Description
31–28
NIPR7
27–24
NIPR6
Normal Interrupt Priority Level. Selects the software controlled priority level for the associated normal
interrupt source. These registers do not affect the prioritization of fast interrupt priorities.
23–20
NIPR5
19–16
NIPR4
15–12
NIPR3
11–8
NIPR2
7–4
NIPR1
3–0
NIPR0
0 Lowest priority normal interrupt
...
15 Highest priority normal interrupt
10.2.10 Normal Interrupt Vector and Status Register (NIVECSR)
The NIVECSR register displays the priority of the highest pending normal interrupt and also provides
vector index of the interrupt’s service routine. This number can be used directly as an index into a vector
table to select the highest pending normal interrupt source. This read-only register can only be accessed to
in privileged mode.
Address 0x1004_0040 (NIVECSR)
31
30
29
28
Access: Supervisor
read
27
26
25
R
24
23
22
21
20
19
18
17
16
NIVECTOR
W
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
R
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
NIPRILVL
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-19. Normal Interrupt Vector and Status Register Format
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
10-23
ARM926EJ-S Interrupt Controller (AITC)
Table 10-18. Normal Interrupt Vector and Status Register Field Description
Field
Description
31–16
Normal Interrupt Vector. Indicates vector index for the highest pending normal interrupt.
NIVECTOR –1 No normal interrupt request pending
0 Interrupt 0 highest priority pending normal interrupt
1 Interrupt 1 highest priority pending normal interrupt
...
63 Interrupt 63 highest priority pending normal interrupt
64+ (not –1)unused, will not occur
15–0
NIPRILVL
Normal Interrupt Priority Level. Indicates priority level of highest priority normal interrupt. This number can be
written to NIMASK to disable current priority normal interrupts to build a reentrant normal interrupt system.
–1 No normal interrupt request pending
0 Highest priority normal interrupt is level 0
1 Highest priority normal interrupt is level 1
...
15 Highest priority normal interrupt is level 15
16+ (not –1)unused, will not occur
10.2.11 Fast Interrupt Vector and Status Register (FIVECSR)
FIVECSR provides the vector index for highest priority active fast interrupt’s service routine (higher the
source number of fast interrupt, higher will be the priority level). This hardware mechanism replaces the
previous necessity for core support of the FF1 command. This number can be directly used as an index
into a vector table to select the highest pending fast interrupt source. This read-only register is located on
the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed to in privileged mode.
Address 0x1004_0044 (FIVECSR)
31
30
29
28
Access: Supervisor
read
27
26
25
R
24
23
22
21
20
19
18
17
16
FIVECTOR[31:16]
W
Reset
1
1
1
1
1
1
1
15
14
13
12
11
10
9
R
1
1
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
FIVECTOR[15:0]
W
Reset
1
1
1
1
1
1
1
1
1
Figure 10-20. Fast Interrupt Vector and Status Register Format
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
10-24
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
Table 10-19. Fast Interrupt Vector and Status Register Description
Field
Description
31–0
FIVECTOR
Fast Interrupt Vector. Indicates vector index for the highest pending fast interrupt.
–1 No fast interrupt request pending (–1 is defined as all bits in the field are set to 1.)
0 Interrupt 0 highest pending fast interrupt
1 Interrupt 1 highest pending fast interrupt
...
63 Interrupt 63 highest pending fast interrupt
64+ (not –1)unused, will not occur
10.2.12 Interrupt Source Register High (INTSRCH) and Low (INTSRCL)
INTSRCH and INTSRCL are both 32-bits wide. INTSRCH and INTSRCL reflect the status of all interrupt
request inputs into the interrupt controller. Unused bit positions always read zero (no request pending). The
state of this register out of reset is determined by the peripheral circuits generating the requests; normally,
the requests would be inactive. These read-only registers can only be accessed in privileged mode and can
only accessed with 32-bit reads.
Address 0x1004_0048 (INTSRCH)
31
30
29
28
Access: Supervisor
read
27
26
25
R
24
23
22
21
20
19
18
17
16
INTIN[63:48]
W
Reset1
0
0
0
0
0
0
0
15
14
13
12
11
10
9
R
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
INTIN[47:32]
W
Reset1
0
0
0
0
0
0
0
0
0
Figure 10-21. Interrupt Source Register High Format
1
The state of this register out of reset is determined by the peripheral circuits generating the requests; normally, the requests
would be inactive.
Address 0x1004_004C (INTSRCL)
31
30
29
28
Access: Supervisor
read
27
26
25
R
24
23
22
21
20
19
18
17
16
INTIN[31:16]
W
Reset1
0
0
0
0
0
0
0
15
14
13
12
11
10
9
R
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
INTIN[15:0]
W
Reset1
0
0
0
0
0
0
0
0
0
Figure 10-22. Interrupt Source Register High Format
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
10-25
ARM926EJ-S Interrupt Controller (AITC)
1
The state of this register out of reset is determined by the peripheral circuits generating the requests; normally, the requests
would be inactive.
Table 10-20. Interrupt Source Register High and Low Description
Field
31–0
INTIN
Description
Interrupt Source. Indicates the state of the corresponding hardware interrupt source.
0 Interrupt source negated
1 Interrupt source asserted
10.2.12.1 Interrupt Assignments High
Table 10-21. Interrupt Source High (INTSRCH) Assignment
Name
Bit
INT_DPTC
Bit 31
Dynamic Process Temperature Compensate (DPTC)
—
INT_IIM
Bit 30
IC Identify Module (IIM)
—
INT_LCDC
Bit 29
LCD Controller (LCDC)
—
INT_SLCDC
Bit 28
Smart LCD Controller (SLCDC)
—
INT_SAHARA
Bit 27
Symmetric/Asymmetric Hashing and Random Accelerator
—
INT_SCM
Bit 26
SCC SCM
—
INT_SMN
Bit 25
SCC SMN
—
INT_USBOTG
Bit 24
USB OTG
—
INT_USBHS2
Bit 23
USB HOST2
—
INT_USBHS1
Bit 22
USB HOST1
—
INT_H264
Bit 21
H264
—
INT_EMMAPP
Bit 20
eMMA Post Processor
—
INT_EMMAPRP
Bit 19
eMMA Pre Processor
—
INT_FEC
Bit 18
Fast Ethernet Controller
—
INT_UART5
Bit 17
UART5
—
INT_UART6
Bit 16
UART6
—
INT_DMACH15
Bit 15
DMA Channel 15
—
INT_DMACH14
Bit 14
DMA Channel 14
—
INT_DMACH13
Bit 13
DMA Channel 13
—
INT_DMACH12
Bit 12
DMA Channel 12
—
INT_DMACH11
Bit 11
DMA Channel 11
—
INT_DMACH10
Bit 10
DMA Channel 10
—
INT_DMACH9
Bit 9
DMA Channel 9
—
INT_DMACH8
Bit 8
DMA Channel 8
—
Interrupt Source Module
Notes
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
10-26
Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
Table 10-21. Interrupt Source High (INTSRCH) Assignment (continued)
Name
Bit
INT_DMACH7
Bit 7
DMA Channel 7
—
INT_DMACH6
Bit 6
DMA Channel 6
—
INT_DMACH5
Bit 5
DMA Channel 5
—
INT_DMACH4
Bit 4
DMA Channel 4
—
INT_DMACH3
Bit 3
DMA Channel 3
—
INT_DMACH2
Bit 2
DMA Channel 2
—
INT_DMACH1
Bit 1
DMA Channel 1
—
INT_DMACH0
Bit 0
DMA Channel 0
—
Interrupt Source Module
Notes
10.2.12.2 Interrupt Assignments Low
Table 10-22. Interrupt Source Low (INTSRCL) Assignment
Name
Bit
INT_CSI
Bit 31
CMOS Sensor Interface (CSI)
INT_ATA
Bit 30
Advanced Technology Attachment (ATA)
INT_NFC
Bit 29
NAND Flash Controller (NFC)
—
INT_PCMCIA
Bit 28
PCMCIA/CF Host Controller (PCMCIA)
—
INT_WDOG
Bit 27
Watchdog (WDOG)
—
INT_GPT1
Bit 26
General Purpose Timer (GPT1)
—
INT_GPT2
Bit 25
General Purpose Timer (GPT2)
—
INT_GPT3
Bit 24
General Purpose Timer (GPT3)
—
INT_PWM
Bit 23
Pulse Width Modulator (PWM)
—
INT_RTC
Bit 22
Real-Time Clock (RTC)
—
INT_KPP
Bit 21
Key Pad Port (KPP)
—
INT_UART1
Bit 20
UART1
—
INT_UART2
Bit 19
UART2
—
INT_UART3
Bit 18
UART3
—
INT_UART4
Bit 17
UART4
—
INT_CSPI1
Bit 16
Configurable SPI (CSPI1)
—
INT_CSPI2
Bit 15
Configurable SPI (CSPI2)
—
INT_SSI1
Bit 14
Synchronous Serial Interface (SSI1)
—
INT_SSI2
Bit 13
Synchronous Serial Interface (SSI2)
—
Bit 12
I2C
—
INT_I2C1
Interrupt Source Module
Bus Controller
(I2C1)
Notes
—
Hard Disk
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
10-27
ARM926EJ-S Interrupt Controller (AITC)
Table 10-22. Interrupt Source Low (INTSRCL) Assignment (continued)
Name
Bit
Interrupt Source Module
Notes
INT_SDHC1
Bit 11
Secure Digital Host Controller (SDHC1)
—
INT_SDHC2
Bit 10
Secure Digital Host Controller (SDHC2)
—
INT_SDHC3
Bit 9
Secure Digital Host Controller (SDHC3)
—
INT_GPIO
Bit 8
General Purpose Input/Output (GPIO)
—
INT_MSHC
Bit 7
Memory Stick Host Controller (MSHC)
—
INT_CSPI3
Bit 6
Configurable SPI (CSPI3)
—
INT_RTIC
Bit 5
Real Time Integrity Checker (RTIC)
—
INT_GPT4
Bit 4
General Purpose Timer (GPT4)
—
INT_GPT5
Bit 3
General Purpose Timer (GPT5)
—
INT_GPT6
Bit 2
General Purpose Timer (GPT6)
—
INT_I2C2
Bit 1
I2C Bus Controller (I2C2)
—
Reserved
Bit 0
Reserved
—
10.2.13 Interrupt Force Register High (INTFRCH) and Low (INTFRCL)
INTFRCH and INTFRCL are both 32-bits wide. They allow software generation of interrupts for each of
the possible interrupt sources for functional or debug purposes. System level design may reserve one or
more sources for software purposes to allow software to self-schedule interrupts by forcing one or more
of these “sources” in appropriate interrupt force register(s). These registers can only be accessed to in
privileged mode. These registers can be only modified using 32-bit writes.
Address 0x1004_0050 (INTFRCH)
31
30
29
28
Access: Supervisor
read/write
27
26
25
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
FORCE[47:32]
W
Reset
23
FORCE[63:48]
W
Reset
24
0
0
0
0
0
0
0
0
0
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Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
Address 0x1004_0054 (INTFRCL)
31
30
29
Access: Supervisor
read/write
28
27
26
25
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
FORCE[15:0]
W
Reset
23
FORCE[31:16]
W
Reset
24
0
0
0
0
0
0
0
0
0
Figure 10-23. Interrupt Force Register Format
Table 10-23. Interrupt Force Register High and Low Field Description
Field
31–0
FORCE
Description
Interrupt Source Force Request. Used to force a request for the corresponding interrupt source.
0 Standard interrupt operation
1 Interrupt forced asserted
10.2.14 Normal Interrupt Pending Register High (NIPNDH) and Low
(NIPNDL)
NIPNDH and NIPNDL are both 32-bits wide registers used to monitor the outputs of the enable and
masking operations. These registers are actually a set of buffers; therefore, reset state of these registers are
determined by normal interrupt enable registers, interrupt mask register and interrupt source registers. The
value reflected in these registers is unaffected by the value of NIMASK register. These read-only registers
are located on ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed in privileged mode
Address 0x1004_0058 (NIPNDH)
31
30
29
28
Access: Supervisor
read
27
26
25
R
24
23
22
21
20
19
18
17
16
NIPEND[63:48]
W
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
R
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
NIPEND [47:32]
W
Reset
0
0
0
0
0
0
0
0
0
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Freescale Semiconductor
10-29
ARM926EJ-S Interrupt Controller (AITC)
Address 0x1004_005C (NIPNDL)
31
30
29
28
Access: Supervisor
read
27
26
25
R
24
23
22
21
20
19
18
17
16
NIPEND[31:16]
W
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
R
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
NIPEND[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Table 10-24. Normal Interrupt Pending Register High and Low Description
Field
Description
31–0
NIPEND
Normal Interrupt Pending Bit. If a normal interrupt enable bit is set and the corresponding interrupt source is
asserted, the interrupt controller will assert a normal interrupt request. The normal interrupt pending bits reflect
the interrupt input lines which are asserted and are currently enabled to generate a normal interrupt.
0 No normal interrupt request
1 Normal interrupt request pending
10.2.15 Fast Interrupt Pending Register High (FIPNDH) and Low (FIPNDL)
FIPNDH and FIPNDL are both 32-bits wide registers used to monitor the outputs of enable and masking
operations. These registers are actually a set of buffers; therefore, reset state of these registers are
determined by fast interrupt enable registers, interrupt mask register and interrupt source registers. These
read-only registers are located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be
accessed to in privileged mode.
Address 0x1004_0060 (FIPNDH)
31
30
29
Access: Supervisor
read
28
27
26
25
R
24
23
22
21
20
19
18
17
16
FIPEND[63:48]
W
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
R
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
FIPEND[47:32]
W
Reset
0
0
0
0
0
0
0
0
0
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Freescale Semiconductor
ARM926EJ-S Interrupt Controller (AITC)
Address 0x1004_0064 (FIPNDL)
31
30
29
Access: Supervisor
read
28
27
26
25
R
24
23
22
21
20
19
18
17
16
FIPEND[31:16]
W
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
R
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
FIPEND[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-24. Fast Interrupt Pending Register High and Low Format
Table 10-25. Fast Interrupt Pending Register High and Low Field Description
Field
Description
31–0
FIPEND
Fast Interrupt Pending Bit. If fast interrupt enable bit is set and the corresponding interrupt source is asserted,
interrupt controller will assert fast interrupt request. Fast interrupt pending bits reflect interrupt input lines which
are asserted and are currently enabled to generate a fast interrupt.
0 No fast interrupt request
1 Fast interrupt request pending
10.3
10.3.1
ARM926EJ-S Interrupt Controller Operation
ARM926EJ-S Prioritization of Exception Sources
The ARM926EJ-S core imposes the following priority among the various exceptions:
• Reset (highest priority)
• Data Abort
• Fast Interrupt
• Normal Interrupt
• Prefetch Abort
• Undefined Instruction and SWI (lowest priority)
10.3.2
AITC Prioritization of Interrupt Sources
AITC module prioritizes various interrupt sources by source number where higher source numbers have
higher priority. Fast interrupt always have higher priority over normal interrupts. Interrupt requests are
prioritized in the following sequence:
1. Fast interrupt requests, in order of highest source number
2. Normal interrupt requests, in order of highest priority level, then in order of highest source number
with the same priority level
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor
10-31
ARM926EJ-S Interrupt Controller (AITC)
10.3.3
Assigning and Enabling Interrupt Sources
Interrupt controller provides for flexible assignment of any interrupt source to one of the two core interrupt
request inputs. This is done by setting the appropriate bits in INTENABLEH/INTENABLEL registers and
INTTYPEH/INTTYPEL registers. Usually, interrupt assignment is done once during system initialization
and does not affect interrupt latency. Interrupt assignment is the first of three steps required to enable an
interrupt source, and this is done at chip integration. The second step is to program the source to generate
interrupt requests. The final step is to enable the interrupt inputs in the core by clearing the normal interrupt
disable (I) and/or the fast interrupt disable (F) bits in the program status register (CPSR).
10.3.4
Enabling Interrupt Sources
There are two methods of enabling or disabling interrupts in the AITC. The first method is directly reading
INTENABLEH/INTENABLEL registers, logically OR or BIT CLEAR these registers with a generated
masks, then writing back to INTENABLEH/INTENABLEL registers. The second method is performing
an atomic write to source number in INTENNUM register. AITC will decode this 6-bit register and enable
one of the 64 interrupt sources. AITC will automatically generate a “one hot” enable mask and logically
OR this mask to the correct INTENABLEH or INTENABLEL register. To disable interrupts is the same
except the source number is written to the INTDISNUM register.
10.3.5
Typical Interrupt Entry Sequences
Table 10-26 shows a typical pipeline sequence for ARM926EJ-S core when a normal interrupt occurs,
assuming single cycle memories, it approximately takes 6 clocks from normal interrupt acknowledgment
within ARM926EJ-S to fetch first opcode of interrupt routine. Table 10-27 shows a typical pipeline
sequence for ARM926EJ-S core when a fast interrupt occurs, assuming that FIQ service routine begins at
0x0000_001C and single cycle memories.
Table 10-26. Typical Hardware Accelerated Normal Interrupt Entry Sequence
TIME
ADDR
–2
–1
nIRQ assert
Last ADDR
before nIRQ
+4 / +2
+8 / +4
0x0000_0018
+4
+8
Vector Table
Fetch
0
1
2
3
4
5
Link
Adjust
Fetch
Dec
Exec
Data
Wrbk
Fetch
Dec
6
7
8
Fetch
Dec
Exec
nIRQ ack.
Dec
Exec
Fetch
Dec
Fetch
Fetch
Vector
n/a
nIRQ Routine
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4
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ARM926EJ-S Interrupt Controller (AITC)
Table 10-26. Typical Hardware Accelerated Normal Interrupt Entry Sequence (continued)
TIME
ADDR
–2
–1
0
1
2
3
4
5
6
+4
7
8
Fetch
Dec
+8
Fetch
Table 10-27. Typical Fast Interrupt Entry Sequence
TIME
ADDR
–2
–1
nFIQ assert
Last ADDR before nFIQ
+4 / +2
+8 / +4
Fetch
0
1
2
Link
Adjust
Fetch
Dec
Exec
Fetch
Dec
nFIQ ack.
Dec
Exec
Fetch
Dec
Fetch
0x0000_001c
+4
+8
10.3.6
3
Fetch
Writing Reentrant Normal Interrupt Routines
AITC can be used to create a reentrant normal interrupt system. This enables preempting of lower priority
level interrupts by higher priority level interrupts. This requires a small amount of software support and
overhead.
1. Push the link register (LR_irq) on to the stack (SP_irq)
2. Push the saved status register (SPSR_irq) on to the stack
3. Read the current value of NIMASK and push this value on to the stack
4. Read current priority level via NIVECSR
5. Interrupts of the equal or lesser priority than the current priority level must be masked via the
NIMASK register by writing value from NIVECSR
6. Clear I bit in ARM926EJ-S core by a MSR or MRS command sequence (now a higher priority
normal interrupt can preempt a lower priority one). Also change operating mode of the core to
System Mode from IRQ mode
7. Push System Mode link register (LR) on to the stack (SP_user)
8. The traditional interrupt service routine is now included
9. Pop System Mode link register (LR) from the stack (SP_user)
10. Set I bit in ARM926EJ-S core by MSR or MRS command sequence (disables all normal interrupts)
11. Also change the operating mode of the core to IRQ Mode from System mode
12. Pop the original value of normal interrupt mask and write to the NIMASK register
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ARM926EJ-S Interrupt Controller (AITC)
13. The saved status register must be popped from the stack (SP_irq)
14. The link register must be popped from the stack into the PC
15. Return from nIRQ
NOTE
Steps 1, 2, 13, and 14 are automatically done by most C compilers and are
included for completeness.
10.3.7
AHB Interface of AITC
AITC is AHB compliant. This means, IDLE or BUSY cycles which are presented to AITC will receive an
aitc_hready (as required by specification).
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Book II, Part 2:
Security
Introduction
This part provides an overview of the modules that make up the i.MX27 security systems.
Chapter 11, “Security Controller (SCC),” on page 11-1
Chapter 12, “Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2),” on page 12-1
Chapter 13, “Run-Time Integrity Checker (RTIC),” on page 13-1
Chapter 14, “IC Identification (IIM),” on page 14-1
Security Controller (SCC)
The Security Controller (SCC) is a hardware component of the Platform Independent Security
Architecture (PISA) baseline, and is itself composed of two sub-blocks, the Secure RAM and the Security
Monitor.
The primary functionality of the SCC is associated with establishing the following:
• A centralized security state controller and hardware security state with a hardware configured,
unalterable security policy
• An uninterruptable hardware mechanism to detect and respond to threat detection signals
(specifically platform test access signals)
• A device-unique data protection/encryption resource to enable off chip storage of security sensitive
data
• An internal storage resource that automatically and irrevocably destroys plain text security
sensitive data upon threat detection
Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2)
Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2) is a security co-processor that
forms part of the Platform Independent Security Architecture (PISA), and can be used on cell phone
baseband processors or wireless PDAs. It implements block encryption algorithms, (AES, DES, and
3DES), hashing algorithms (MD5, SHA-1, SHA-224, and SHA-256), stream cipher algorithm (ARC4),
and a hardware random number generator. It has a slave IP bus interface for the host to write configuration
and command information, and to read status information. It also has a DMA controller, with an AHB bus
interface, to reduce the burden on the host to move the required data to and from memory.
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Run Time Integrity Checker (RTIC)
The Run Time Integrity Checker (RTIC) is part of the Platform Independent Security Architecture (PISA)
family of platform security components. Its function is to ensure the integrity of the peripheral memory
contents and assist with boot authentication. The RTIC has the ability to verify the memory contents during
system boot and during run time execution. If the memory contents at runtime fail to match the hash
signature, an error in the security monitor is triggered.
IC Identification (IIM)
The IC Identification Module (IIM) provides an interface for reading and in some cases programming
and/or overriding identification and control information stored in on-chip fuse elements. The module
supports electrically-programmable poly fuses (e-Fuses).
The IIM also provides a set of volatile software-accessible signals which can be used for software control
of hardware elements, not requiring non-volatility.
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Chapter 11
Security Controller (SCC)
The Security Controller (SCC) is composed of two sub-blocks, the Secure RAM and the Security Monitor
(see Figure 11-1).
The primary functionality of the SCC is associated with establishing the following:
• A centralized security state controller and a hardware security state with a hardware configured,
unalterable security policy
• An uninterruptible hardware mechanism that detects and responds to threat detection signals
(specifically, platform test access signals)
• A device-unique data protection/encryption resource that enables off-chip storage of
security-sensitive data
An internal storage resource that automatically and irrevocably destroys plain text security-sensitive data
upon threat detection.
Debug Ports (indicating JTAG or Test modes)
Security Key (SLID)
Debug Detector
Secure State
Controller
Timer
Key Encryption
Module
Red Memory
Status
Security
Policy
State
Algorithm Sequence
Checker
Black Memory
Memory Controller
Security Monitor
Secure RAM
Bus Interface
Security Controller (SCC)
IP Bus
Figure 11-1. Security Controller Block Diagram
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Security Controller (SCC)
11.1
Overview
Security and security services, in an embedded or data processing platform, refer to the platform’s ability
to provide mandatory and optional information protection services. Information in this context refers to all
embedded data, both to program store and data load. Therefore, a secure platform is intended to protect
information and data from unauthorized access in the form of inspection (read), modification (write), or
execution (use).
11.2
External Signal Description
The SCC has no external signals.
NOTE
Contact your Freescale Semiconductor sales office or distributor for
additional information on SCC.
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Chapter 12
Symmetric/Asymmetric Hashing and Random Accelerator
(SAHARA2)
The Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2) is a security co-processor
that forms part of Platform Independent Security Architecture (PISA), and can be used on cell phone
baseband processors or wireless PDAs. It implements block encryption algorithms, (AES, DES, and
3DES), hashing algorithms (MD5, SHA-1, SHA-224, and SHA-256), stream cipher algorithm (ARC4),
and a hardware random number generator. It has a slave IP bus interface for the host to write configuration
and command information, and to read status information. It also has a DMA controller, with an AHB bus
interface, to reduce the burden on the host to move the required data to and from memory.
12.1
Features
SAHARA2 accelerates the following security functions:
• AES encryption/decryption
— ECB, CBC, CTR, and CCM modes
— 128 bit key
• DES/3DES
— EBC, CBC and CTR modes
— 56-bit key with parity (DES)
— 112-bit or 168-bit key with parity (3DES)
• ARC4 (RC4-compatible cipher)
— 5-16 byte key
— Host accessible S-box
• MD5, SHA-1, SHA-224 and SHA-256 hashing algorithms.
— Messages lengths which are multiples of bytes.
— Autopadding supported.
— HMAC (support for IPAD and OPAD via descriptors).
— Up to 232 byte message length.
• Random number generator (based NIST Approved PRNG - FIPS 186-2).
— Entropy is generated via an independent free running ring oscillators
SAHARA2 also provides the following enhanced features:
• Descriptor based processing to reduce communication between host processor and SAHARA2
• Low power design
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Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2)
•
•
— Automatic power down of individual blocks when not in use
— Clock gating on registers
— RNG sleep mode
Restricted access to potentially sensitive information
— Internal registers are cleared after descriptor chain has completed processing in BATCH mode
— Security Monitor can cause data to be cleared.
— Scan reset and scan exit signals prevent data being scanned out.
Mixed Endianness support.
NOTE
Contact your Freescale Semiconductor sales office or distributor for
additional information on SAHARA2.
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Chapter 13
Run-Time Integrity Checker (RTIC)
The Run-Time Integrity Checker (RTIC) function is to ensure the integrity of the peripheral memory
contents, and assist with boot authentication. The RTIC has the ability to verify the memory contents
during system boot and during run-time execution. If the memory contents at run-time fail to match the
hash signature, an error in the security monitor is triggered. Figure 13-1 is a block diagram of the RTIC.
AHB
SAM
hclk_gated
DMAC
en
IP-Bus
hclk
Clock
IP-Bus
Controller
Controller
Run-time
IP-Bus
T-Secure
Timer
Hash
Once
Timer
Module
Hash
hclk_gated
scc_rtic_err
Register
File
ckil (32 kHz)
Figure 13-1. RTIC Block Diagram
13.1
Features
The RTIC offers the following features:
• SHA-1 message authentication
• Input DMA interface
• Segmented data gathering to support non-contiguous data blocks in memory (up to two segments
per block)
• Works with high assurance boot process
• Support for up to four independent memory blocks
• Programmable DMA bus duty cycle timer and watchdog timer
• Power-saving clock gating logic
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Run-Time Integrity Checker (RTIC)
•
•
Hardware configurable Big/Little-Endian data format
Full word memory reads (word-aligned addresses, multiple of 32-bit lengths)
13.1.1
Modes of Operation
The RTIC operates in two primary modes:
• One-time hash mode
— Is used during high assurance boot for code authentication or one time integrity checking
— Stores hash result internally and signals interrupt to host
• Continuous hash mode
— Is used at run-time to continuously to verify integrity of memory contents
— Checks re-generated hash against internally stored values and interrupts host only if error
occurs
13.2
Initialization/Application Information
13.2.1
System Application
The RTIC is intended to serve as a single-use hash accelerator to assist with code authentication and other
services at boot time, and as an autonomous/passive memory integrity checker during run-time. It is
programmed through the IP-slave interface, and scans the peripheral memory contents over the AHB
interface using direct memory access. A typical system configuration using the RTIC is shown in
Figure 13-2.
Memory A
Memory B
Memory C
Memory D
ARM Host
Processor
AHB
ipi_err_int
SCC
Run-Time Integrity Checker
IP Interface
Figure 13-2. System Diagram
In this example, there are four independent memory blocks that can be checked by the RTIC. Memories
A,B, and C have their contents partitioned over non-contiguous spaces. Memory D does not contain any
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Run-Time Integrity Checker (RTIC)
physical partitioning. The host would program the RTIC with the starting address and length of each
partition inside memory A, B, and C. For memory D, only one starting address and length would be
specified, wi