NXP MPC850 PowerQUICC® Processor Reference Manual

NXP MPC850 PowerQUICC®  Processor Reference Manual

Freescale Semiconductor Addendum

Document Number: MPC850UMAD Rev. 1.7, 06/2010

Errata to the MPC850 Family User’s Manual, Rev. 1

This errata document describes corrections to the MPC850 Family User’s Manual, Revision 1. For convenience, the section number and page number of the errata item in the reference manual are provided. Items with section and page numbers in bold are new since the last revision of this document. To locate any published updates for this document, refer to the world-wide web located on the last page of this document.

Section/Page

1, 1-2

Changes

For the MPC850DSL part in Table 1-1, change ‘Time-slot assigner, SMC2, and I 2 C are not supported.’ to the following: Time-slot assigner and I 2 C are not supported.

11.1.3.1, 11-3 Add the following note:

NOTE

The PLL loss of lock detection does not have a specification for the detection threshold. Therefore, it should be used solely as a debug tool and not in production systems. Characterization of the threshold value over temperature and operating voltages has shown that the threshold can be triggered when clock out to clock in phase differences are 1.8 ns or more.

11.3.1.1, 11-9 In Figure 11-8, change the field description for bit 2 to BBE (boot burst enable) and the field description for bit 15 to CLES (core little-endian swap). Add the following description to Table 11-3: © 2010 Freescale Semiconductor, Inc. All rights reserved.

Section, Page No.

Changes Table 11-3. Hard Reset Configuration Word Field Descriptions Bits

2 15

Name

BBE CLES

Description

Boot burst enable 0 The boot device does not support bursting.

1 The boot device does support bursting.

Core little-endian swap. Defines core access operation following reset.

0 Big endian 1 Little endian 14.2.2.3, 14-8 Replace Table 14-2 with the following:

Table 14-2. XFC Capacitor Values Based on PLPRCR[MF] MF Range Minimum Capacitance

1 ≤ (MF + 1) ≤ 4 XFC = [(MF + 1) × 425] – 125 (MF + 1) > 4 XFC = (MF + 1) × 520

Maximum Capacitance

XFC = [(MF + 1) × 590] – 175 XFC = (MF + 1) × 920 15.4.1,15-9 15.4.2, 15-11 15.8.4, 15-55 18.6.3, 18-13 21.2.1, 21-9 21.2.1, 21-9

Unit

pF pF In Figure 16-6, BR0, add the following footnote: Since the base address value is unknown at reset, program BR0 before programming OR0 to ensure proper operation.

Replace the text after Figure 16-7 with the following: At reset, OR0 has specific default values and is read-only, as shown in Figure 15-8. After reset, OR0 becomes R/W.

Remove Section 15.8.4.1, “Address Incrementing for External Synchronous Bursting Masters.” Remove Table 18-10 as well as the sentence before and the sentence after.

In the MODE field (bits 28–31) of Table 21-2, V.14 RAM microcode is not supported. Thereby, mode 0111 should be reserved.

In the MODE field (bits 28-31) of Table 21-2, DDCMP RAM microcode is not supported. Thereby, mode 1001 should be reserved.

2

Errata to the MPC850 Family User’s Manual, Rev. 1

Freescale Semiconductor

Section, Page No.

21.2.4, 21-10 21.3, 21-11

22, 22-1 22.16, 22-14 27.7, 27-9 27.21, 27-23

28.8, 28-7

31.4.1.2, 31-9 34.1, 34-2 34.3, 34-8 34.5.1.2, 34-18 35.2.1, 35-4

Changes

In Figure 21-5, change the TODR register access from R/W to W (write only).

Also, in Table 21-3, revise the second sentence of bit setting 1 in the TODR[TOD] description to read “TOD is cleared automatically after one system clock cycle, but...” In addition, in Table 21-3, “TODR Field Descriptions,” in TOD field description, change “TOD is cleared automatically after one serial clock...” to say “TOD is cleared automatically after 1 system clock...” Under third bullet point, change “For an RxBD, the value must be even,” to say, “For an RxBD, the value must be mod 4 aligned.” The last sentence in the last paragraph should be removed.

In the RZS field (bit 7) of Table 22-9, for selection 1, the second sentence in the paragraph (making reference to V.14 applications) should be removed.

Add superscript number 2 after PADDR1_H, PADDR1_M, PADDR1_L, TADDR_H, TADDR_M, and TADDR_L. Add the corresponding footnote 2 at the end of Table 27-1 with the following statement: The address should be written in little endian, not Motorola’s big-endian format, that is, physical address 112233445566 should be written PADDR_L = 6655, PADDR_M = 4433, and PADDR_H = 2211. The TADDR should be written in the same way as the PADDR.

In step 26, change the last sentence to read, “Then write 0x000E to TxBD[Data... .” In Table 28-5, change the third sentence in the Transmitter Underrun description to read as follows: Underrun in transparent mode occurs when the CPM or SDMA is experiencing a latency issue and cannot keep up with the transmission rate.

In the last sentence of Example 1, change the order of the string for REV = 1 to the following: first j_klmn_r_stuv last In the last sentence of Example 3, change the order of the string for REV = 1 to the following: first r_stuv_ghij_klmn last Inside the second bullet, add a footnote at the end of the sentence that states: At power on reset, port pins are not defined in any particular state until CLKOUT is present for two clocks.

In Table 34-6, add RTS2 to PB18, PBPAR[DDn] = 1, and PBDIR[DRn] = 1.

In Table 34-19, in the description of bits 3–15, add the following footnote to the definition of setting to 1 (The corresponding signal is an output): PD8 and PD10 will function as open drain.

The first bullet should reflect SPS = 0, and the second bullet should reference SPS = 1.

Freescale Semiconductor

Errata to the MPC850 Family User’s Manual, Rev. 1

3

Section, Page No.

B.3.1, B-4 Appendix B, B-4 Appendix F, F-2 Global Legend:

Register

SDCR PBR0 POR0 PBR1 POR1 PBR2 POR2 PBR3 SIUMCR SYPCR SWSR SIPEND SIMASK SIEL SIVEC TESR POR3 PBR4 POR4 PBR5 POR5

Changes

In Table B-1, the row making reference to SCC in Profibus (seventeenth row) should be removed.

In Table B-1, add a column showing that USB is 24 Mbps at 25 MHz.

In Figure F-1, add a line over the block for SMC2 to show that it is supported.

The following table is provided to clarify/correct the power-on reset value of many of the MPC850 registers and lists whether each register is affected by HRESET and/or SRESET.

x or X = ‘don’t care’ in either bits, nibbles, or the entire register.

0 = a single zero indicates the entire register is reset to zeros.

( ) = isolates bits of a nibble of the register.

? = a don’t care for POR, but if this register is affected by HRESET or SRESET, indicates that the value will remain the same as what it was before the reset occurred.

NA = not applicable, indicates that this register has no POR value.

POR Value

01200000 FFFFFF07 0 0000xxxx 0000xxxx 0000xxxx (xx11)(11xx)xxxxxx XXXX0000 x x x x x 0 x x x x x x x

Affected by HRESET

Yes Yes Yes Yes Yes Yes Yes Yes No No No No No Yes No No No No No No No

Affected by SRESET

No No Yes Yes Yes No Yes Yes No No No No No No No No No No No No No 4

Errata to the MPC850 Family User’s Manual, Rev. 1

Freescale Semiconductor

Section, Page No.

Changes Register

PER BR0 OR0 BR1 OR1 BR2 OR2 BR3 PBR6 POR6 PBR7 POR7 PGCRA PGCRBf PSCR PIPR OR3 BR4 OR4 BR5 OR5 BR6 OR6 BR7 OR7 MAR MCR MAMR MBMR MSTAT MPTPR MDR TBSCR

POR Value

x x x x 0 0 x ??00??00

0 XXXXX(??00)0(000?) 00000FF4 XXXXXX(xx00)0 XXXXXXX(xxx0) XXXXXX(xx00)0 XXXXXXX(xxx0) XXXXXX(xx00)0 XXXXXXX(xxx0) XXXXXX(xx00)0 XXXXXXX(xxx0) XXXXXX(xx00)0 XXXXXXX(xxx0) XXXXXX(xx00)0 XXXXXXX(xxx0) XXXXXX(xx00)0 XXXXXXX(xxx0) x (xx00)0(x000)0(xxx0)X(00xx)X xx001000 xx001000 0 0200 x 0

Affected by HRESET

No No No No Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes No Yes Freescale Semiconductor

Errata to the MPC850 Family User’s Manual, Rev. 1 Affected by SRESET

No No No No No No No Yes Yes No No No No No No No No No No No No No No No No No No No No No No No No 5

Section, Page No.

Register

TBREFA TBREFB RTCSC RTC RTSEC RTCAL PISCR PITC PITR SCCR PLPRCR RSR TBSCRK TBREFAK TBREFBK TBK RTCSCK RTCK RTSECK RTCALK PISCRK PITCK SCCRK PLPRCRK RSRK I2MOD I2ADD I2BRG I2COM I2CER I2CMR SDAR SDSR 6

Changes POR Value

x x 00(000x)(000x) x 0 x x x x 0(000?)(?000)(0??0)0000 ???0(0100)000 0 x x x x x x x x x x x x x 0 x FFFF 0 0 0 x 0

Affected by HRESET

No No Yes No No No Yes No N/A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes No Yes

Errata to the MPC850 Family User’s Manual, Rev. 1 Affected by SRESET

No No Yes Yes Yes No No No N/A No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes No Yes Freescale Semiconductor

Section, Page No.

Register

SDMR IDSR1 IDMR1 IDSR2 IDMR2 CIVR CICR CIPR CIMR CISR PADIR PAPAR PAODR PADAT PCDIR PCPAR TMR2 TRR1 TRR2 TCR1 TCR2 TCN1 TCN2 TMR3 TMR4 PCSO PCDAT PCINT PDDIR PDPAR PDDAT TGCR TMR1 Freescale Semiconductor

Changes POR Value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 0 0 0 x 0 0 0 x 0 FFFF FFFF 0 0 0 0 0 0

Affected by HRESET

Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes No Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

Errata to the MPC850 Family User’s Manual, Rev. 1 Affected by SRESET

Yes Yes Yes Yes Yes Yes No Yes Yes Yes No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 7

Section, Page No.

Register

TRR3 TRR4 TCR3 TCR4 TCN3 TCN4 TER1 TER2 TER3 TER4 CPCR RCCR RCTR1 RCTR2 RCTR3 RCTR4 RTER RTMR BRGC1 BRGC2 BRGC3 BRGC4 GSMR_L1 GSMR_H1 PSMR1 TODR1 DSR1 SCCE1 SCCM1 SCCS1 GSMR_L2 GSMR_H2 PSMR2 8

Changes POR Value

FFFF FFFF 0 0 0 0 0 0 0 0 0 0 NA NA NA NA 0 0 0 0 0 0 0 0 0 0 7E7E 0 0 0 0 0 0

Affected by HRESET

Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

Errata to the MPC850 Family User’s Manual, Rev. 1 Affected by SRESET

Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Freescale Semiconductor

Section, Page No.

Register

TODR2 DSR2 SCCE2 SCCM2 SCCS2 GSMR_L3 GSMR_H3 PSMR3 TODR3 DSR3 SCCE3 SCCM3 SCCS3 GSMR_L4 GSMR_H4 PSMR4 TODR4 DSR4 SCCE4 SCCM4 SCCS4 SMCMR1 SMCE1 SMCM1 SMCMR2 SMCE2 SMCM2 SPMODE SPIE SPIM SPCOM PIPC PTPR Freescale Semiconductor

Changes POR Value

0 7E7E 0 0 0 0 0 0 0 7E7E 0 0 0 0 0 0 0 7E7E 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Affected by HRESET

Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

Errata to the MPC850 Family User’s Manual, Rev. 1 Affected by SRESET

Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No 9

Section, Page No.

Register

PBDIR PBPAR PBODR PBDAT SIMODE SIGMR SISTR SICMR SICR SIRP

POR Value

xxx(xx00)0000 xxx(xx00)0000 0 x 0 0 0 0 0 0

Changes Affected by HRESET

Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

Affected by SRESET

No No No Yes Yes No No Yes No Yes 10

Errata to the MPC850 Family User’s Manual, Rev. 1

Freescale Semiconductor

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Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.

Freescale, the Freescale logo, and PowerQUICC, are trademarks of Freescale Semiconductor, Inc. Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © 2010 Freescale Semiconductor, Inc.

Document Number: MPC850UMAD Rev. 1.7

06/2010

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