NXP M-5 M-5™ Channel Adapter Data Sheet

Data Sheet

M-5 CHANNEL ADAPTER

SILICON REVISION A0

M5CAA0-DS

Rev 02 PRODUCTION

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com





Data Sheet

M-5 CHANNEL ADAPTER

SILICON REVISION A0

M5CAA0-DS

Rev 02






C

HAPTER

1

C

HAPTER

2

C

HAPTER

3


M5CAA0-DS

Rev 02

CONTENTS

About This Guide

Guide Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Data Sheet Classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Using C-Port Electronic Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Guide Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Related Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Functional Description

Chapter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

M-5 Channel Adapter (CA) Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

General M-5 CA Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

M-5 CA System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Possible Framer Configurations for C-5e NP (CPs) and (FP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

C-5e NP CPs to Framer Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

C-5e NP FP to Framer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Signal Descriptions

Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

M-5 CA I/O Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Serial Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

M-5 CA to C-5e NP Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Signals Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Electrical Specifications

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

M-5 CA Reference Clock Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

UTOPIA Level 3, SATURN POS-PHY Level 3 and UTOPIA Level 3-Like (PL3/UL3/UL3L) . . . . . . . . 39

V 02




6 CONTENTS

C

HAPTER

4

Gigabit Ethernet Media Independent Interface (GMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Management Data Input/Output (MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Low Speed Serial Bus (LSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Mechanical Specifications

Package Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Package Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Marking Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Index

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

M5CAA0




M5CAA0-DS

Rev 02

LIST OF FIGURES

3

4

1

2

5

6

7

8

9

10

11

M-5 CA Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

M-5 CA System Overview Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

M-5 CA Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

M-5 CA Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

PL3/UL3/UL3L Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Gigabit Ethernet Media Independent Interface (GMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

MDIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

LSP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

JTAG Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

M-5 CA TBGA Package Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

M-5 CA TBGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48



V 02

8 LIST OF FIGURES


M5CAA0




M5CAA0-DS

Rev 02

LIST OF TABLES

27

28

29

30

23

24

25

26

16

17

18

19

20

21

22

12

13

14

15

8

9

10

11

3

4

1

2

5

6

7

Data Sheet Classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Navigating Within a PDF Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

C-Port Silicon Documentation Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

M-5 CA Data Sheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Summary of Interfaces Supported by the M-5 CA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Framer to C-5e NP (CP) Configurations Supported by the M-5 CA . . . . . . . . . . . . . . . . . . . . 13

Some of the Various Mix Configurations Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

M-5 CA to C-5e NP CP Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Framer to C-5e NP (FP) Configuration Supported by the M-5 CA . . . . . . . . . . . . . . . . . . . . . . 14

M-5 CA Framer I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

M-5 CA C-5e NP I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Serial Interface Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Serial Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Clocks Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Phase Lock Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Scan Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

No Connection Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

M-5 CA to C-5e NP Channel Processor s (CPs) (Front Port) Connections . . . . . . . . . . . . . . . 27

M-5 CA to C-5e NP Fabric Processor (Back Port) Connections . . . . . . . . . . . . . . . . . . . . . . . . 29

M-5 CA Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

M-5 CA Reference Clock AC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

PL3/UL3/UL3L AC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

GMII AC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

V 02




10 LIST OF TABLES

31

32

33

34

35

MDIO AC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Low Speed Serial Bus AC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

JTAG AC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

M-5 CA Package Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

M-5 CA Marking Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

M5CAA0




M5CAA0-DS

Rev 02

ABOUT THIS GUIDE

Guide Overview

The M-5 TM Channel Adapter (CA) Data Sheet describes hardware layout specifications including pinouts, memory configuration guidelines, timing diagrams, power and power sequencing guidelines, thermal design guidelines and mechanical specifications.

Motorola reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Motorola reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

The guide covers the following topics:

•

Functional Description

•

Signal Descriptions

•

Electrical Specifications

•

Mechanical Specifications



V 02


2

Data Sheet Classifications

Table 1 describes the Data Sheet classifications of Advance, Preliminary, and Production.

Table 1 Data Sheet Classifications

CLASSIFICATION DESCRIPTION

Advance

Information

Used to advise customers of the proposed addition to the product line. This document will typically contain some useful information including interfacing with the user’s system and some specifications. The goal of this document is to allow customers to begin designs but with expectation of changes. Specification details may be changed later without notice.

Preliminary

Information

Describes pre-production or first production devices and is usually indicative of production stage performance. Minor changes should be expected as characteristic spreads become better controlled. Specification details may be changed slightly without notice, but the customer can design their product based on this data sheet.

Production Data Defines the long-term specified production limits based on fully characterized data. It includes a disclaimer to allow improvements in specifications and modifications that do not affect form, fit or function in original applications; if absolute maximum ratings are changed, they should improve rather than downgrade.

Using C-Port Electronic

Documents

C-Port electronic documents are provided as PDF files. Open and view them using the

Adobe® Acrobat® Reader application, version 3.0 or later. If necessary, download the

Acrobat Reader from the Adobe Systems, Inc. web site: http://www.adobe.com/prodindex/acrobat/readstep.html

Each provided PDF file offers several ways for moving among the document’s pages, as follows:

To move quickly from section to section within the document, use the Acrobat bookmarks that appear on the left side of the Acrobat Reader window. The bookmarks provide an expandable outline view of the document’s contents. To display the document’s Acrobat bookmarks, press the “Display both bookmarks and page” button on the Acrobat Reader tool bar.

To move to the referenced page of an entry in the document’s Contents or Index, click on the entry itself, each of which is hyperlinked.

To follow a cross-reference to a heading, figure, or table, click the blue text.

M5CAA0




Using C-Port Electronic Documents 3

To move to the beginning or end of the document, to move page by page within the document, or to navigate among the pages you displayed by clicking on hyperlinks, use the Acrobat Reader navigation buttons shown in this figure:

Beginning of document End of document

Previous or next hyperlink

Previous page

Next page

Table 2 summarizes how to navigate within a C-Port electronic document.

Table 2 Navigating Within a PDF Document

TO NAVIGATE THIS WAY

Move from section to section within the document.

CLICK THIS

A bookmark on the left side of the Acrobat Reader window

Move to an entry in the Table of Contents. The entry itself

Move to an entry in the Index. The page number

Move to an entry in the List of Figures or List of Tables.

Follow a cross-reference (highlighted in blue text).

Move page by page.

The Figure or Table number

The cross-reference text

Move to the beginning or end of the document.

The appropriate Acrobat Reader navigation buttons


Move backward or forward among a series of hyperlinks you have selected.


V 02




4

Guide Conventions

The following visual elements are used throughout this guide, where applicable:

This icon and text designates information of special note.

Warning: This icon and text indicate a potentially dangerous procedure. Instructions contained in the warnings must be followed.

Warning: This icon and text indicate a procedure where the reader must take precautions regarding laser light.

This icon and text indicate the possibility of electro-static discharge (ESD) in a procedure that requires the reader to take the proper ESD precautions.

Related Product

Documentation

Table 3 C-Port Silicon Documentation Set

DOCUMENT NAME

C-5e/C-3e Network Processor Architecture Guide

C-5e Network Processor Data Sheet

C-3e Network Processor Data Sheet

Table 3 lists the C-Port Family silicon documentation. These documents can be found

either on the Motorola web site (motorola.com/networkprocessors) or on the password-protected C-Port Family Support site (motorola.cportcorp.com/support).

C-5 Network Processor to C-5e Network Processor

Comparison

M-5 Channel Adapter Architecture Guide

M-5 Channel Adapter Data Sheet

PURPOSE

Describes the full architecture of the C-5e and C-3e network processors.

DOCUMENT ID

C5EC3EARCH-RM

C5ENPB0-DS Describes hardware design specifications for the C-5e network processor.

Describes hardware design specifications for the C-3e network processor.

C3ENPB0-DS

Describes key architectural features of the C-5e, and highlights main differences between C-5 and C-5e.

C5C5EDELTA-RM

Describes the full architecture of the M-5 channel adapter. M5CAARCH-RM

Describes hardware design specifications for the M-5 channel adapter.

M5CAA0-DS

M5CAA0




Revision History

Revision History 5

Table 4 shows the revision history for this data sheet, providing a description of the

changes.

Table 4 M-5 CA Data Sheet Revision History

REVISION CHANGE

02 Chapter 1, restructured and enhanced.

Chapter 2, added details for eight signal types.

Chapter 2, condensed the signals listed by pin number table.

Chapter 3, added description and specifications for Low Speed Serial Bus t sp characteristics.

Chapter 4, added more detail information about Reflow.

01 New document - no changes



V 02

6


M5CAA0



Chapter 1


M5CAA0-DS

Rev 02

FUNCTIONAL DESCRIPTION

Chapter Overview

This chapter covers the following topic:

•

M-5 Channel Adapter (CA) Overview



V 02


8 CHAPTER 1: FUNCTIONAL DESCRIPTION

M-5 Channel Adapter (CA)

Overview

In general, the M-5 CA accepts a mix of PDU rates (OC-1, OC-3c, OC-12c, OC-48 and

OC-48c) for both packet and cell applications. Basically, the M-5 CA is a multiplexor. It can be used with the C-5e’s CPs and/or with the C-5e’s FP based upon your application needs.

In more detail, the M-5 Channel Adapter (CA), is used with the C-5e NP to provide the required PDU ordering for both packet and cells for both the front ports (CPs) and back port (FPTx only under certain configurations). In addition, it provides bus translation from multi-physical layer (MPHY), 32bit UTOPIA Level 3 (UTOPIA-L3) to the C-5e front ports

(CPs) and back port (FP), as well as, bus translation from Saturn POS-PHY Level 3

(POS-PHY-L3) to the C-5e front ports (CPs) and back port (FP), thus allowing OC-48c bandwidths. Additionally, the front ports (CPs) use a Gigabit Media Independent Interface

(GMII) that can be modified to provide flow control that interfaces with the SDPs.

The method that the M-5 uses to provide PDU ordering is called Sequence Numbers .

Sequencer numbers are 13bits long and are included as part of the enqueue and dequeue operations. Sequence Numbers are used whenever a flow is spread across more than one cluster in the case of the front ports (CPs). The FPRx does not need sequence numbers since it maintains strict ordering internally. However, the FPTx does require sequence numbers only when virtual queueing is used in the configuration.

For a detailed description of potential M-5 CA configurations, refer to the C-5e/C-3e

Network Processor Architecture Guide (part number C5EC3EARCH-RM), section entitled

“C-5e NP System Configuration Overview”.

Throughout this manual Channel Processors (CPs) are referred to as “Front Port” and

Fabric Processor (FP) is referred to as “Back Port”. This simply refers to the location of theses ports on the C-5e NP.

M5CAA0




M-5 Channel Adapter (CA) Overview 9

General M-5 CA Features

The M-5 CA coprocessor provides the following features.

•

Supports ATM 52Byte cells

•

Supports packets from 5Bytes to 9216Bytes

•

Provides buffering of cells or packets between the framer and the C-5e NP

•

Provides two (2) low pin count Serial Bus Interface (SBI) protocols:

– High-speed protocol Management Data input/output (MDIO) or

– Low-Speed Protocol (LSP) slave

Both provide configuration, control and status monitoring functions. The M-5 CA

MDIO is compatible with the C-5e NP MDIO. And the M-5 CA LSP is compatible with the C-5e NP’s Level3 master serial interface.

•

Provides a standard five signal IEEE 1149.1 JTAG interface

•

BIST (Built In Self Test) provided for all internal RAMs.

•

Low power 1.8 V CMOS device with 3.3V TTL compatible digital inputs and 3.3 V

CMOS/TTL compatible outputs

• 324-pin TBGA

• Industrial Temperature Range (-40

°

to 85

°

C) ambient



V 02



Block Diagram

The block diagram of the M-5 CA is shown in Figure 1 on page 10.

Figure 1 M-5 CA Functional Block Diagram

Ingress

Scheduler

M-5 CA

From Framer

PL3 or UL3

Single Phy Or

Multi Phy interface

To Framer

PL3 or UL3

Single Phy Or

Multi Phy interface

Rx

Ingress

Interface

Tx

Egress

Interface

JTAG

Ingress

FIFOs

Egress

FIFOs

Config

Registers

UL3-Like Ingress

Interface for

Back Port

4x GMII

Ingress

Interfaces for

Front Port

4x GMII

Egress

Interfaces for

Front Port

UL3-like Egress

Interface for

Back Port

Config

Register

Interface

Egress

Scheduler

To C-5e NP

GMII Interfaces to Channel Processors

(front port) or

UL3 Like Interfaces to Fabric Port (back port)

From C-5e NP

GMII Interfaces to Channel Processors

(front port) or

UL3 Like Interfaces to Fabric Port (back port)

SBI:

MDIO/LSP or

Level 3

Interface

M5CAA0





M-5 CA System Overview

Based on the particular application, a framer to M-5 CA set may be used in three (3) possible configurations: on the front of the C-5e NP that feeds into its Channel Processors

(CP0 to CP15), on the back of the C-5e NP that feeds into its Fabric Processor (FP), or on both the front and back of the C-5e NP.

Figure 2 on page 11 and show the two (2) bridging configurations of the M-5 CA. Also

shown in

Figure 2 on page 11 are the four (4) allowed interfaces of the C-5 CA system. The

M-5 CA may have two (2) framer interfaces (noted as 1 & 2) and two (2) NP interfaces

(noted as 3 & 4). In addition, Table 5 on page 12 provides a list of each interface and its

description.

Figure 2 M-5 CA System Overview Block Diagram

Front Port of C-5eNP Back Port of C-5eNP

OC-48c

Framer

OC-48

(c)

SPHY/

MPHY 1

M-5 CA

Framer Interfaces:

PoS-PHYL3 (PL3) or

UTOPIA Level-3 (UL3)

Cluster0

Cluster1

Cluster2

Cluster3

CP0

CP1

CP2

CP3

CP4

CP5

CP6

CP7

CP8

CP9

CP10

CP11

CP12

CP13

CP14

CP15

C-5e NP

FP

M-5 CA

2

Framer

OC-48c

SPHY

Framer Interfaces:

PoS-PHYL3 (PL3) or

UTOPIA Level-3 (UL3)

OC-48c

3

NP Interface for CPs:

4 GMII signals map to C-5eNPs 4 CP

Clusters

4

NP Interface for FP:

1 UTOPIA

Level-3-Like

V 02





Table 5 Summary of Interfaces Supported by the M-5 CA

ITEM

Framer Interface

C-5e NP Channel

Processors (CPs) Front

Port Interface

C-5e NP Fabric Processor

(FP) Back Port Interface

DESCRIPTION

In general, the framer interface supports a variety of framers with an aggregate data rate of OC-48c.

Specifically, it provides bridging function from Framer to C-5e NPs Channel Processors (CPs) on the Front

Ports and on the C-5e NPs Fabric Port (FP) on the Back Port. Two (2) framer protocols are supported:

• Provides a 32bit UL3 (UTOPIA Level 3) framer interface operating from 66 to 104MHz with optional parity for ATM (Asynchronous Transfer Mode) applications. The M-5 CA is the UL3 master, or

• Provides a 32bit PL3 (SATURN PoS-PHY Level 3) framer interface operating from 66 to 104MHz with optional parity and packet level transfer control for Packet Over SONET (PoS), HDLC or ATM applications.

Word level transfer control (PL3 specification refers to this as Byte level transfer control) is not supported.

The M-5 CA is the PL3 master.

Both direct status (single Phy only, OC-48c) and polling (single Phy (OC-48c) or multi Phy (OC-1, OC-3,

OC-12)) modes are supported for both UTOPIA Level3 and PoS Level3.

Provides bridging function from the framer to the C-5e NP’s Channel Processor (CP) interface. One type of protocol is supported:

• Provides four (4) 8bit Gigabit Media Independent Interfaces (GMII) to the C-5e’s front port operating from approximately 66 to 104MHz with optional Cyclic Redundancy Check (CRC)-16. GMII protocol maps from the M-5 CA to the C-5e NP CP Clusters , of which their are four (4), and not to the C-5e NP individual sixteen (16) CP ports.

Provides a bridging function from an OC-48c Framer to the C-5e NP’s Fabric Processor (FP) interface. One type of protocol is supported:

• Provides a 32bit UL3-like (UTOPIA Level 3) interface to the C-5e’s back port operating from 66 to 104

MHz. Only direct status mode is supported. The M-5 CA is the UL3-Like master.

M5CAA0





Possible Framer

Configurations for C-5e NP

(CPs) and (FP)

Framer configurations for the C-5e NP CPs and the C-5e NP FP. In addition, the M-5 CA to

C-5e NP CP mapping is provided.

C-5e NP CPs to Framer Configurations

Table 6 on page 13 gives some of the possible framer configurations that are supported

by the M-5 CA when bridging the framer to the C-5e NP’s Channel Processor (CPs). The various mix configurations are made up of legal mixtures of OC-1, OC-3 and OC-12 channels with a combination data rate less than or equal to OC-48c.

Table 6 Framer to C-5e NP (CP) Configurations Supported by the M-5 CA

FRAMER PORT

CONFIGURATION

16 ports x OC-3c

4 ports x OC-12c

1 port x OC-48c

Various Mix of OC-1,

OC-3c and OC-12c

AGGREGATED

DATA RATE

NUMBER OF

FRAMER CHANNELS

OC-48

OC-48

OC-48

OC-48

16

4

1

Configurable. See

Table 7 on page 13

for details

Table 7 Some of the Various Mix Configurations Supported

0

3

12

# OF OC-1

CHANNELS

48

0

0

3

12

# OF OC-3C

CHANNELS

0

16

4

3

0

0

0

# OF OC-12C

CHANNELS

TOTAL

AGGREGATED

DATA RATE

OC-48

OC-48

OC-48

OC-48

OC-48

Table 7 on page 13 provides some of the possible OC-48 channel configurations

supported. Not all supported channel configurations are listed.

V 02





M-5 CA to C-5e NP CP Mapping

The M-5 CA provides the mapping function between the framer that has from 1 to 48 channels to the 16 channel processors of the C-5e NP.

Table 8 on page 14 describes this

mapping.

Table 8 M-5 CA to C-5e NP CP Mapping

DATA RATE FRAMER CHANNEL TO C-5e NP CHANNEL PROCESSOR MAPPINGS

OC-1 Three OC-1 channels map to a single C-5e NP channel processor

OC-3c

OC-12c

OC-48c

One OC-3c channel maps to a single C-5e NP channel processor

One OC-12c channel maps to one C-5e NP cluster, a cluster is comprises four

(4) channel processors.

Note: Clusters mapping is only required when using GMII protocol.

One OC-48c channel maps to all 16 C-5e NP channel processors

C-5e NP FP to Framer Configuration

Table 9 on page 14 gives the framer channel configuration supported by the M-5 CA

when bridging the framer to the C-5e NP’s back port.

Table 9 Framer to C-5e NP (FP) Configuration Supported by the M-5 CA

FRAMER PORT

CONFIGURATION

AGGREGATED

DATA RATE

1 port x OC-48c OC-48

NUMBER OF

FRAMER CHANNELS

1

M5CAA0



Chapter 2


SIGNAL DESCRIPTIONS

M5CAA0-DS

Rev 02

Signal Summary

The M-5 CA contains 324 pins that are organized into ten (10) signal groups as listed below:

•

Framer Interface — 94 pins (see Table 10 on page 17)

• C-5e NP Interface — 76 pins (see

Table 11 on page 19)

• Serial Bus Interface — 2 pins (see


• Clock Interface — 9 pins (see


•

Phase Lock Loop (PLL) — 3 pins (see Table 15 on page 24)

•

Test Access Port (TAP) — 5 pins (see Table 16 on page 25)

• Scan Mode — 1 pin (see


• Reset — 1 pin (see


• Power and Ground — 109 pins (see


• No Connection — 24 pins (see


For proper clock configurations, refer to the M-5 Channel Adapter Architecture Guide (part number M5CAARCH-RM).

All pins are LVTTL type.

V 02




16 CHAPTER 2: SIGNAL DESCRIPTIONS

Pinout Diagram

Figure 3 on page 16 and

Table 23 on page 31 describe the M-5 CA Pin Assignments. These

pin numbers are referenced throughout the remaining chapter.

Figure 3 M-5 CA Pinout Diagram

D

1

N b e

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

AC

AD

AE

AF

AG

AH

AJ

AK

U

V

W

Y

AA

AB

M

N

P

R

T

A

B

C

D

E

F

G

H

J

K

L

E

1

N

M5CAA0




M-5 CA I/O Interface Signals 17

M-5 CA I/O Interface

Signals

Table 10

describes the M-5 CA’s I/O interfaces to UTOPIA and POS-PHY framers. Table 11

describes the M-5 CA’s I/O interfaces to the C-5e NP’s front and back ports.

Table 10 M-5 CA Framer I/O

FRAMER INTERFACES

M-5 SIGNAL PL3 SIGNAL PL3 FUNCTION UL3 SIGNAL UL3 FUNCTION TOTAL I/O PIN # (MSB - LSB)

TADR[5:0] TADR[5:0] PL3 Framer

Interface

Transmit

Address

TxAddr[5:0] UL3 Framer

Interface

Transmit

Address

6 O A13, B13, A12, B12, A11, A10

TPA_TCA

TENB

PTPA or DTPA PL3 Framer

TENB

TSOP_TSOC TSOP

Interface

Polled-PHY

Transmit

Packet

Available

(MPHY) or

Direct-PHY

Transmit

Packet

Available

(SPHY)

PL3 Framer

Interface

Transmit

Enable

PL3 Framer

Interface

Transmit Start of Packet

TxClav

TxEnb

TxSOC

UL3 Framer

Interface

Polled-PHY

Transmit Cell

Available

(MPHY) or

Direct-PHY

Transmit Cell

Available

(SPHY)

UL3 Framer

Interface

Transmit

Enable

1

1

UL3 Framer

Interface

Transmit Start of Cell

1

I

O

O

A15

B14

A17

TDAT[31:0] TDAT[31:0] PL3 Framer

Interface

Transmit Data

TxData[31:0] UL3 Framer

Interface

Transmit Data

32

TPRTY TPRTY 1

O L30, K30, J30, J29, H30, H29, G30, F30, F29,

E30, D30, D29, B30, A29, B28, A28, A27, B27,

A26, A25, B25, A24, B24, A23, B23, A22, B22,

A21, B21, A20, B20, A19

O B18

TSX TSX

PL3 Framer

Interface

Transmit

Parity

TxPrty

PL3 Framer

Interface

Transmit Start of Transfer unused

UL3 Framer

Interface

Transmit

Parity

1 O B17

V 02





Table 10 M-5 CA Framer I/O (continued)



TEOP TEOP PL3 Framer

Interface

Transmit End of Packet unused 1 O B16

2 O B15, A14 TMOD[1:0] TMOD[1:0] PL3 Framer

Interface

Transmit

Modulo

TERR TERR PL3 Framer

Interface

Transmit Error unused unused 1 O A18

RADDR[5:0] unused 6 O T1,U1,W1,W2,Y1,Y2

RVAL_RCA

RENB

RVAL

RENB

PL3 Framer

Interface

Receive Data

Valid

PL3 Framer

Interface

Receive

Enable

RSOP_RSOC RSOP PL3 Framer

Interface

Receive Start of Packet

RDAT[31:0] RDAT[31:0] PL3 Framer

Interface

Receive Data

RPRTY RPRTY PL3 Framer

Interface

Receive Parity

RSX RSX PL3 Framer

Interface

Receive Start of Transfer

RxAddr[5:0] UL3 Framer

Interface

Receive

Address

RxClav UL3 Framer

Interface

Receive Cell

Available

RxEnb

RxSOC

UL3 Framer

Interface

Receive

Enable

UL3 Framer

Interface

Receive Start of Cell

RxData[31:0] UL3 Framer

Interface

Receive Data

RxPrty unused

UL3 Framer

Interface

Receive Parity

1

1

1

32

1

1 I

I

I

I

I

O

R1

R2

M1

A9, B9, A8, B8, A7, B7, A6, B6, A5, B5, A4, B4,

A3, A2, B3, B1, C1, C2, D2, D1, E1, E2, F2, F1,

G1, H2, H1, J1, J2, K2, K1, L1,

L2

N2

M5CAA0





Table 10 M-5 CA Framer I/O (continued)



REOP REOP PL3 Framer

Interface

Receive End of Packet unused 1 I M2 unused 2 I P2, P1 RMOD[1:0] RMOD[1:0] PL3 Framer

Interface

Receive

Modulo

RERR RERR PL3 Framer

Interface

Receive Error unused 1 I N1

TOTAL PINS 94

Table 11 M-5 CA C-5e NP I/O

C-5e INTERFACES

M-5 SIGNAL

FRONT PORT

MODE (GMII) GMII FUNCTION

FPI_TDATA[31:24] GMII3_RXD[7:0] C5 Channel

Processor

Cluster3

Interface

(GMII3) Receive

Data [7:0]


Processor

Cluster2

Interface

(GMII2) Receive

Data [7:0]


Processor

Cluster1

Interface

(GMII1) Receive

Data [7:0]

BACK PORT MODE

(UL3)

UL3 LIKE

FUNCTION

FPI_TDATA[31:24] C5 Fabric

Processor

Interface

Transmit Data

[31:24]

8

TOTAL I/O PIN # (MSB - LSB)

O R29, R30, T30, T29, U30, V30,

W29, W30


Processor

Interface

Transmit Data

[23:16]

8


Processor

Interface

Transmit Data

[15:8]

8

O

O

AA29, AB30, AC30, AC29,

AD30, AD29, AE30, AE29

AH29, AJ30, AK29, AJ28,

AK28, AJ27, AK27, AJ26

V 02





Table 11 M-5 CA C-5e NP I/O (continued)

M-5 SIGNAL

FPI_TDATA[7:0]

FPI_TPRTY

FPI_TENB

FPI_TCA

GMII0_RXDV

C-5e INTERFACES

FRONT PORT

MODE (GMII) GMII FUNCTION

GMII0_RXD[7:0] Output - C5

Channel

Processor

Cluster0

Interface

(GMII0) Receive

Data [7:0] Input

- Serial bus configuration sampled on

POR

GMII0_COL

GMII1_COL

C5 Channel

Processor

Cluster0

Interface

(GMII0)

Transmit Flow

Control

C5 Channel

Processor

Cluster1

Interface

(GMII1)

Transmit Flow

Control

GMII1_TXEN

GMII0_RXDV

C5 Channel

Processor

Cluster1

Interface

(GMII1)

Transmit Enable

C5 Channel

Processor

Cluster0

Interface

(GMII0) Receive

Data Valid

BACK PORT MODE

(UL3)

FPI_TDATA[7:0]

FPI_TPRTY

FPI_TENB

FPI_TCA unused

UL3 LIKE

FUNCTION

Output - C5

Fabric

Processor

Interface

Transmit Data

[7:0] Input -

Serial bus configuration sampled on

POR

8


I/O AJ24, AK24, AJ23, AK23,

AJ22, AK22, AJ21, AK21

C5 Fabric

Processor

Interface

Transmit

Parity

C5 Fabric

Processor

Interface

Transmit

Enable

C5 Fabric

Processor

Interface

Transmit

Segment

Available

1

1

1

1

I

O

O

O

AK20

AJ25

AF1

AJ19

M5CAA0






C-5e INTERFACES

M-5 SIGNAL

GMII1_RXDV

GMII2_RXDV

FPI_TSOC

FRONT PORT

MODE (GMII)

GMII1_RXDV

GMII2_RXDV

GMII3_RXDV

FPI_RDATA[31:24] GMII3_TXD[7:0] C5 Channel

Processor

Cluster3

Interface

(GMII3)

Transmit

Data[7:0]


Processor

Cluster2

Interface

(GMII2)

Transmit

Data[7:0]


Processor

Cluster1

Interface

(GMII1)

Transmit

Data[7:0]

GMII FUNCTION

C5 Channel

Processor

Cluster1

Interface

(GMII0) Receive

Data Valid

C5 Channel

Processor

Cluster2

Interface

(GMII0) Receive

Data Valid

C5 Channel

Processor

Cluster3

Interface

(GMII3) Receive

Data Valid

BACK PORT MODE

(UL3) unused unused

FPI_TSOC

UL3 LIKE

FUNCTION

C5 Fabric

Processor

Interface

Transmit Start of Segment

FPI_RDATA[31:24] C5 Fabric

Processor

Interface

Receive Data

[31:24]


Processor

Interface

Receive Data

[23:16]


Processor

Interface

Receive Data

[15:8]

1

1

8

8

8


1 O AK25

I

I

I

O

O

AH30

AA30

AJ14, AK13, AJ13, AK12,

AJ12, AK11, AJ11, AK10

AJ9, AK8, AJ8, AK7, AJ7, AJ6,

AK6, AK5

AJ4, AK3, AJ3, AK2, AJ1,

AH2, AG1, AG2

V 02






C-5e INTERFACES

M-5 SIGNAL

FRONT PORT

MODE (GMII)


Processor

Cluster0

Interface

(GMII0)

Transmit

Data[7:0]

FPI_RENB GMII2_COL

GMII FUNCTION

C5 Channel

Processor

Cluster2

Interface

(GMII2)

Transmit Flow

Control

GMII3_COL GMII3_COL

FPI_RPRTY GMII0_TXEN

C5 Channel

Processor

Cluster3

Interface

(GMII3)

Transmit Flow

Control

C5 Channel

Processor

Cluster0

Interface

(GMII0)

Transmit Enable

GMII2_TXEN

FPI_RSOC

GMII2_TXEN

GMII3_TXEN

C5 Channel

Processor

Cluster2

Interface

(GMII2)

Transmit Enable

C5 Channel

Processor

Cluster3

Interface

(GMII3)

Transmit Enable

BACK PORT MODE

(UL3)

FPI_RDATA[7:0]

FPI_RENB unused

FPI_RPRTY unused

FPI_RSOC

TOTAL PINS

UL3 LIKE

FUNCTION

C5 Fabric

Processor

Interface

Receive Data

[7:0]

C5 Fabric

Processor

Interface

Receive

Enable

1

1

C5 Fabric

Processor

Interface

Receive Parity

1

1

C5 Fabric

Processor

Interface

Receive Start of Segment

1


8 I AE1, AE2, AD2, AD1, AC1,

AC2, AB2, AB1

76

I

I

I

O

O

AG29

Y29

AA2

AK4

AK9

M5CAA0





Serial Interface Signals

The Serial Bus interface is a general purpose bi-directional, two-wire serial bus and I/O port. The serial bus allows a master (C-5e NP or other) to modify and read registers in the

M-5 CA. It allows the M-5 CA to support two (2) standard protocols.

•

The high-speed protocol (MDIO) uses a 16bit data format (though the M-5 CA only uses the lower 8bits; the upper 8bits are ignored) with 10bits of addressing, and supports transfers at up to 25 MHz (the M5CLK must run more than 3 times faster than the SICL).

• The low-speed protocol (LSP) uses an 8bit data format followed by an acknowledge bit and supports transfers at up to 400kbps. The serial bus interface is configured by pulling up or pulling down a set of pins that the M-5 CA samples during power on reset.

Refer to

Table 12

on page 23 for the SBI configuration pins and Table 13 on page 24 for the

SBI signals.

Table 12 Serial Interface Configuration Pins

PIN NAME CONFIGURATION NAME

FPI_TDATA[0] MDIO mode

PULLED LOW

LSP Used

FPI_TDATA[6:1] Slave Address[5:0] Serial Bus Slave Address

FPI_TDATA[7] MDIO Preamble Suppression Full Preamble Required

(32 cycle)

FPI_TDATA[8] MDIO Two Bit Turnaround MDIO uses 1 TA cycle during reads

PULLED HIGH

MDIO Protocol Used

Two Cycle Preamble

Required

MDIO always uses 2 TA cycles

The protocol to be used is selected by pulling up or pulling down the FPI_TDATA[0] pin, which the M-5 CA samples during power on reset. The M-5 CA is always a slave in both protocols.

Both SIDA and SICL are bi-directional lines that are connected (via an external pull-up resistor) to the positive supply voltage. The M-5 CA never drives the SICL line when in

MDIO mode. When the bus is free, both lines are HIGH. In Low Speed Protocol (LSP) mode, the output stages of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-AND function required for its arbitration mechanism. The bus supports collision detection and arbitration in LSP mode.

V 02





Table 13 Serial Interface Signals

SIGNAL

NAME

SICL

SIDA

TOTAL PINS

FUNCTION

Serial Clock line

Serial Data line

TOTAL I/O

1

1

I

PD

PIN # (MSB - LSB)

/O Y5

I

PD

/O Y6

2

Table 14 Clocks Interfaces

M5 SIGNAL

M5CLK

GTX_CLK[0:3]

RXCLK{0:3]

TOTAL PINS

FUNCTION

M-5 Clock

C-5e NP Forwarded

GMII Transmit Clock

M-5 Forwarded GMII

Receive Clock

4

4


1 I AK15

I AA1, AF2, AJ5, AJ10

9

O AJ20, AK26, AG30, Y30

Table 15 Phase Lock Loop

M5 SIGNAL

TPA_ANA

VDDANA_1

GNDANA_1

TOTAL PINS

FUNCTION

Analog PLL Test Pin 1

Analog VDD

Ground

TOTAL I/O

1

1

3

O


AK17

Power

Pad

AK16

Gnd AK18

M5CAA0





Table 16 Test Access Port

M5 SIGNAL FUNCTION

TCK Test Logic Clock

TMS

TDI

Tap mode control input

Serial test instruction/data input

TRSTB

TDO

Asynchronous test controller reset. In normal system operation, this should be connected to

RESETB.

Serial test instruction/data output

TOTAL PINS

TOTAL I/O

1 I

1 I

PD

1

1

1

5

I

I

PD

PD

O

N29

P30


N30

L29

M30

Table 17 Scan Mode


SCAN Scan enable

TOTAL PINS

TOTAL I/O

1 I

1


AJ15

Table 18 Reset


RESETB Reset

TOTAL PINS

TOTAL I/O

1

1

I


AK14

V 02





Table 19 Power and Ground Signals


VDDCORE Core Supply Voltage

(1.8V Input)

TOTAL I/O

31 P

VDDPAD I/O Supply Voltage

GND

(3.3V Input)

Ground

20

58

P

P


C3, AB3, AD3, AF3, AH6, AH15, AH26,

AE28, AC28, AB28, AA28, E3, W28, T28,

P28, N28, K28, J28, G28, F28, C27, C19, G3,

C13, C6, J3, L3, N3, R3, V2, Y3

AH27, P29, C11, AH24, H28, B26, AH21,

E28, B19, AH18, C30, B11, AH3, C24, AF28,

C23, V28, C18, U3, C15

AK30, AH19, AC3, U29, M28, F3, C17, A30,

AK1, AH17, AB29, U28, M3, E29, C14, A1,

AJ29, AH7, AA3, U2, L28, D28, C12, AJ17,

AG3, Y28, T3, K29, D3, C10, AJ2, AF30, W3,

T2, K3, C29, C4, AH28, AF29, V29, R28, H3,

C26, B29, AH25, AE3, V3,P3, G29, C22, B10,

AH22, AD28, V1, M29, G2, C20, B2

TOTAL PINS

109

Table 20 No Connection Pins


NC[0:23] Reserved for future functionality

TOTAL I/O

24 N/A


A16, AH10, AH23 C21, AG28, AH11, AJ16,

C25, AH1, AH12, C5, C28, AH4, AH13, C7,

AH5, AH14, C8, AH8, AH16, C9, AH9, AH20,

C16

TOTAL PINS

24

M5CAA0




M-5 CA to C-5e NP Signal Connections 27

M-5 CA to C-5e NP Signal

Connections

Table 21 and

Table 22 show the mapping of M-5 CA signals to C-5e NP signals.

Table 21 M-5 CA to C-5e NP Channel Processor s (CPs) (Front Port) Connections

M-5 CA PIN FUNCTION C-5e NP PIN FUNCTION

FPI_TDATA [31:24]

FPI_TSOC

RX_CLK3

FPI_TDATA [23:16]

CPF_5, CPF_4, CPF_3, CPF_2,

CPE_5, CPE_4, CPE_3, CPE_2

CPE_6

CPE_1

CPB_5, CPB_4, CPB_3,CPB_2,

CPA_5, CPA_4, CPA_3, CPA_2

GMII SIGNAL

NAME

GMII3 RXD

[7:0]

GMII2 RXD

[7:0]


R29, R30, T30, T29, U30,

V30, W29, W30

GMII3 RX_DV AA30

GMII3

RX_CLK

Y30

AA29, AB30, AC30,

AC29, AD30, AD29,

AE30, AE29

GMII2_RXDV

RX_CLK2

FPI_TDATA [15:8]

GMII1_RXDV

RX_CLK1

FPI_TDATA [7:0]

GMII0_RXDV

RX_CLK0

FPI_RDATA [31:24]

CPA_6

CPA_1

CP7_5, CP7_4, CP7_3, CP7_2,

CP6_5, CP6_4, CP6_3, CP6_2

CP6_6

CP6_1

CP3_5, CP3_4, CP3_3, CP3_2,

CP2_5, CP2_4, CP2_3, CP2_2

CP2_6

CP2_1

GMII2 RX_DV

GMII2

RX_CLK

GMII1 RXD

[7:0]

GMII1 RX_DV

GMII1

RX_CLK

GMII0 RXD

[7:0]

GMII0 RX_DV

GMII0

RX_CLK

GMII3 TXD

[7:0]

AH30

AG30

AH29, AJ30, AK29, AJ28,

AK28, AJ27, AK27, AJ26

AK25

AK26

AJ24, AK24, AJ23, AK23,

AJ22, AK22, AJ21, AK21

AJ19

AJ20

AJ14, AK13, AJ13, AK12,

AJ12, AK11, AJ11, AK10

GMII3_COL

FPI_RSOC

GTX_CLK3

CPD_5, CPD_4, CPD_3,

CPD_2,

CPC_5, CPC_4, CPC_3, CPC_2

CPD_1

CPC_6

CPC_0

GMII3 COL

GMII3 TX_EN

GMII3

GTX_CLK

Y29

AK9

AJ10

V 02





Table 21 M-5 CA to C-5e NP Channel Processor s (CPs) (Front Port) Connections (continued)

M-5 CA PIN FUNCTION C-5e NP PIN FUNCTION

FPI_RDATA [23:16] CP9_5, CP9_4, CP9_3, CP9_2,

CP8_5, CP8_4, CP8_3, CP8_2

FPI_RENB

GMII2_TXEN

GTX_CLK2

CP9_1

CP8_6

CP8_0

FPI_RDATA [15:8]

FPI_TENB

FPI_TCA

GTX_CLK1

FPI_RDATA [7:0]

FPI_TPRTY

FPI_RPRTY

GTX_CLK0

CP5_5, CP5_4, CP5_3, CP5_2,

CP4_5, CP4_4, CP4_3, CP4_2

CP5_1

CP4_6

CP4_0

CP1_5, CP1_4, CP1_3, CP1_2,

CP0_5, CP0_4, CP0_3, CP0_2

CP1_1

CP0_6

CP0_0

GMII SIGNAL

NAME

GMII2 TXD

[7:0]



AJ6, AK6, AK5

GMII2 COL AG29

GMII2 TX_EN AK4

AJ5 GMII2

GTX_CLK

GMII1 TXD

[7:0]


AH2, AG1, AG2

GMII1 COL AJ25

GMII1 TX_EN AF1

AF2 GMII1

GTX_CLK

GMII0 TXD

[7:0]

AE1, AE2, AD2, AD1,

AC1, AC2, AB2, AB1

GMII0 COL AK20

GMII0 TX_EN AA2

GMII0

GTX_CLK

AA1

M5CAA0




M-5 CA to C-5e NP Signal Connections 29

Table 22 M-5 CA to C-5e NP Fabric Processor (Back Port) Connections

M-5 CA PIN

FUNCTION

C-5e NP PIN

FUNCTION

FPI_TDATA [31:0] FIN[31:0]

FPI_TSOC

FPI_TENB

FPI_TCA

FPI_TPRTY

FPI_RDATA [31:0] FOUT[31:0]

FPI_RSOC

FPI_RENB

FPI_RPRTY

FRXCTL2

FRXCTL0

FRXCTL1

FRXCTL6

FTXCTL2

FTXCTL0

FTXCTL6

UL3-LIKE

SIGNAL

NAME

UL3L

RxData[31:0]


R29, R30, T30, T29, U30, V30, W29, W30,

AA29, AB30, AC30, AC29, AD30, AD29,

AE30, AE29, AH29, AJ30, AK29, AJ28, AK28,

AJ27, AK27, AJ26, AJ24, AK24, AJ23, AK23,

AJ22, AK22, AJ21, AK21

UL3L RxSOC AA30

UL3L RxEnb AJ25

UL3L RxClav AF1

UL3L RxPrty AK20

UL3L

TxData[31:0]

AJ14, AK13, AJ13, AK12, AJ12, AK11, AJ11,

AK10, AJ9, AK8, AJ8, AK7, AJ7, AJ6, AK6,

AK5, AJ4, AK3, AJ3, AK2, AJ1, AH2, AG1,

AG2, AE1, AE2, AD2, AD1, AC1, AC2, AB2,

AB1

UL3L TxSOC AK9

UL3L TxEnb AG29

UL3L TxPrty AA2



V 02



Signals Listed by Pin

Number

Table 23 lists M-5 CA signals organized by their corresponding pin number by row.

M5CAA0




Signals Listed by Pin Number 31

Table 23 M-5 CA Pin Assignments

ROW PIN # FUNCTION

A A1 GND

A2

A3

RDAT_18

RDAT_19

A4

A5

A6

A7

RDAT_21

RDAT_23

RDAT_25

RDAT_27

A8

A9

RDAT_29

RDAT_31

A10 TADR_0

A11 TADR_1

A12 TADR_3

A13 TADR_5

A14 TMOD_0

A15 TPA_TCA

A16 No Connect

A17 TSOP_TSOC

A18 TERR

A19 TDAT_0

A20 TDAT_2

A21 TDAT_4

A22 TDAT_6

A23 TDAT_8

A24 TDAT_10

A25 TDAT_12

A26 TDAT_13

A27 TDAT_15

A28 TDAT_16

A29 TDAT_18

A30 GND


B B1 RDAT_16

B2

B3

GND

RDAT_17

B4

B5

B6

B7

RDAT_20

RDAT_22

RDAT_24

RDAT_26

B8

B9

RDAT_28

RDAT_30

B10 GND

B11 VDDPAD

B12 TADR_2

B13 TADR_4

B14 TENB

B15 TMOD_1

B16 TEOP

B17 TSX

B18 TPRTY

B19 VDDPAD

B20 TDAT_1

B21 TDAT_3

B22 TDAT_5

B23 TDAT_7

B24 TDAT_9

B25 TDAT_11

B26 VDDPAD

B27 TDAT_14

B28 TDAT_17

B29 GND

B30 TDAT_19


C C1 RDAT_15

C2

C3

RDAT_14

VDDCORE

C4

C5

C6

C7

GND

No Connect

VDDCORE

No Connect

C8

C9

No Connect

No Connect

C10 GND

C11 VDDPAD

C12 GND

C13 VDDCORE

C14 GND

C15 VDDPAD

C16 No Connect

C17 GND

C18 VDDPAD

C19 VDDCORE

C20 GND

C21 No Connect

C22 GND

C23 VDDPAD

C24 VDDPAD

C25 No Connect

C26 GND

C27 VDDCORE

C28 No Connect

C29 GND

C30 VDDPAD

V 02





Table 23 M-5 CA Pin Assignments (continued)


D D1

D2

RDAT_12

RDAT_13

D3 GND

D28 GND

D29 TDAT_20

D30 TDAT_21

E

F

E1

E2

RDAT_11

RDAT_10

E3 VDDCORE

E28 VDDPAD

E29 GND

E30 TDAT_22

F1

F2

RDAT_8

RDAT_9

G

H

F3 GND

F28 VDDCORE

F29 TDAT_23

F30 TDAT_24

G1

G2

RDAT_7

GND

G3 VDDCORE

G28 VDDCORE

G29 GND

G30 TDAT_25

H1

H2

RDAT_5

RDAT_6

H3 GND

H28 VDDPAD

H29 TDAT_26

H30 TDAT_27


J J1

J2

RDAT_4

RDAT_3

J3

J28

J29

J30

VDDCORE

VDDCORE

TDAT_28

TDAT_29

K

L

K1

K2

RDAT_1

RDAT_2

K3 GND

K28 VDDCORE

K29 GND

K30 TDAT_30

L1

L2

RDAT_0

RPRTY

M

N

L3

L28

L29

L30

VDDCORE

GND

TMS

TDAT_31

M1

M2

RSOP_RSOC U

REOP

M3 GND

M28 GND

M29 GND

M30 TDI

N1

N2

RERR

RSX

N3 VDDCORE

N28 VDDCORE

N29 TRSTB

N30 TCK

V


P P1

P2

RMOD_0

RMOD_1

P3 GND

P28 VDDCORE

P29 VDDPAD

P30 TDO

R

T

R1

R2

RVAL_RCA

RENB

R3 VDDCORE

R28 GND

R29 FPI_TDATA_31

R30 FPI_TDATA_30

T1

T2

RADDR_5

GND

T3

U1

U2

U3

V1

V2

GND

T28 VDDCORE

T29 FPI_TDATA_28

T30 FPI_TDATA_29

RADDR_4

GND

VDDPAD

U28 GND

U29 GND

U30 FPI_TDATA_27

GND

VDDCORE

V3 GND

V28 VDDPAD

V29 GND

V30 FPI_TDATA_26

M5CAA0




Signals Listed by Pin Number 33



W W1

W2

RADDR_3

RADDR_2

W3 GND

W28 VDDCORE

W29 FPI_TDATA_25

W30 FPI_TDATA_24

Y Y1

Y2

RADDR_1

RADDR_0

Y3 VDDCORE

Y28 GND

Y29 GMII3_COL

Y30 RXCLK3

AA AA1 GTX_CLK0

AA2 FPI_RPRTY

AB

AA3 GND

AA28 VDDCORE

AA29 FPI_TDATA_23

AA30 FPI_TSOC

AB1 FPI_RDATA_0 AF

AB2 FPI_RDATA_1

AB3 VDDCORE

AB28 VDDCORE

AB29 GND

AB30 FPI_TDATA_22


AC AC1 FPI_RDATA_3

AC2 FPI_RDATA_2


AG AG1

AG2

FPI_RDATA_9

FPI_RDATA_8

AC3 GND

AC28 VDDCORE

AG3 GND

AG28 No Connect

AC29 FPI_TDATA_20 AG29 FPI_RENB

AC30 FPI_TDATA_21 AH AH1 No Connect

AD AD1 FPI_RDATA_4

AD2 FPI_RDATA_5

AD3 VDDCORE

AD28 GND

AE

AD29 FPI_TDATA_18

AD30 FPI_TDATA_19

AE1 FPI_RDATA_7

AE2 FPI_RDATA_6

AH2

AH3

AH4

AH5

AH6

AH7

AH8

AH9

FPI_RDATA_10

VDDPAD

No Connect

No Connect

VDDCORE

GND

No Connect

No Connect

AE3

AE28

AE29

AE30

AF1

AF2

AF3

AF28

AF29

AF30

GND

VDDCORE

FPI_TDATA_16

FPI_TDATA_17

FPI_TCA

GTX_CLK1

VDDCORE

VDDPAD

GND

GND

AH10

AH11

AH12

AH13

AH14

AH15

AH16

AH17

AH18

AH19

No Connect

No Connect

No Connect

No Connect

No Connect

VDDCORE

No Connect

GND

VDDPAD

GND

V 02







AH AH20 No Connect

AH21 VDDPAD

AH22 GND

AH23 No Connect

AH24 VDDPAD

AH25 GND

AJ

AH26 VDDCORE

AH27 VDDPAD

AH28 GND

AH29 FPI_TDATA_15

AH30 GMII2_RXDV

AJ1 FPI_RDATA_11 AK

AJ2 GND

AJ3 FPI_RDATA_13


AJ AJ20 RXCLK0

AJ21 FPI_TDATA_1

AJ22 FPI_TDATA_3

AJ23 FPI_TDATA_5

AJ24 FPI_TDATA_7

AJ25 FPI_TENB

AJ26

AJ27

AJ28

AJ29

AJ30

AK1

AK2

AK3

FPI_TDATA_8

FPI_TDATA_10

FPI_TDATA_12

GND

FPI_TDATA_14

GND

FPI_RDATA_12

FPI_RDATA_14

AJ4 FPI_RDATA_15

AJ5 GTX_CLK2

AJ6 FPI_RDATA_18

AJ7 FPI_RDATA_19

AJ8 FPI_RDATA_21

AJ9 FPI_RDATA_23

AJ10 GTX_CLK3

AJ11 FPI_RDATA_25

AJ12 FPI_RDATA_27

AJ13 FPI_RDATA_29

AJ14 FPI_RDATA_31

AJ15 SCAN

AJ16 No Connect

AJ17 GND

AJ18 SICL

AJ19 GMII0_RXDV

AK4

AK5

AK6

AK7

AK8

AK9

AK10

AK11

AK12

AK13

AK14

AK15

AK16

AK17

AK18

AK19

GMII2_TXEN

FPI_RDATA_16

FPI_RDATA_17

FPI_RDATA_20

FPI_RDATA_22

FPI_RSOC

FPI_RDATA_24

FPI_RDATA_26

FPI_RDATA_28

FPI_RDATA_30

RESETB

M5CLK

VDDANA

TPA_ANA

GNDANA

SIDA


AK AK20 FPI_TPRTY

AK21 FPI_TDATA_0

AK22 FPI_TDATA_2

AK23 FPI_TDATA_4

AK24 FPI_TDATA_6

AK25 GMII1_RXDV

AK26 RXCLK1

AK27 FPI_TDATA_9

AK28 FPI_TDATA_11

AK29 FPI_TDATA_13

AK30 GND

M5CAA0



Chapter 3


M5CAA0-DS

Rev 02

ELECTRICAL SPECIFICATIONS

DC Electrical

Characteristics

The figures and tables in this section describe the DC electrical characteristics of the M-5

CA.

Table 24 Absolute Maximum Ratings

SYMBOL

V

DD

AV

DD

OV

DD

V in

T stg

ESD tol

CHARACTERISTIC 1

Core Supply Voltage

PLL Supply Voltage

LVTTL I/O Supply Voltage

LVTTL Input Voltage 2,

ESD Tolerance 4

3

Storage Temperature Range

MIN

-0.3

-0.3

-0.3

-0.3

-55

2,000 -

MAX

2.2

2.2

4.0

4.3

150

UNIT

V

V

V

V o

V

C

1 Functional and tested operating conditions are given in Table 25 . Absolute maximum ratings are

stress ratings only, and functional operation at the maximums are not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.

2 Caution: LVTTL V in

must not exceed OV

DD

by more than 0.3V at any time, including during power-up.

3 Caution: OV

DD

must not exceed V

DD

/AV

DD

by more than 2.2V at any time, including during power-up.

4 ESD tolerance is stated for Human Body Model, all pins.

V 02




36 CHAPTER 3: ELECTRICAL SPECIFICATIONS

Table 25 Recommended Operating Conditions

SYMBOL

V

DD

AV

DD

OV

DD

V in

T

J


Core Supply Voltage 2

PLL Supply Voltage

LVTTL I/O Supply Voltage

LVTTL Input Voltage

Junction Temperature

MIN

1.65

1.65

3.0

0

-40

MAX

1.95

1.95

3.6

3.6

105

UNIT

V

V

V

V o C

1 These are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed.

2 Recommended supply power-up order is V

DD

, AV

DD

,, OV long as Absolute Maximum Ratings are not exceeded.

DD

, however, any order is acceptable as

Table 26 DC Electrical Specifications

SYMBOL CHARACTERISTIC 1

V

IH

V

IL

I

IH

I

IL

C in

V hys

V

OH

V

OL

P

DCore

P

DPLL

P

DIO

LVTTL Input High Voltage

LVTTL Input Low Voltage

LVTTL Input Leakage Current, V in

= V

DD

LVTTL Input Leakage Current, V in

=GND

LVTTL Input Capacitance

Schmitt Trigger Hysteresis

LVTTL Output High Voltage, I

OH

= -8 mA

LVTTL Output Low Voltage, I

OL

= 8 mA

Core Supply Power Dissipation

PLL Supply Power Dissipation

LVTTL I/O Supply Power Dissipation

-

-

-

-

-

-

-

-

MIN

2.0

500

2.4

-

-

-

MAX

0.8

5

5

10

0.4

2.7

0.2

0.7

1 V

DD

= AV

DD

= 1.8 + 0.15V dc, OV

DD

= 3.3 + 0.3V dc, GND = 0V dc, -40 < T J < 105 o C.

V

W

W

W

µA pF mV

V

UNIT

V

V

µA

M5CAA0




DC Electrical Characteristics 37

Table 27 Thermal Specifications

SYMBOL CHARACTERISTIC

R

θ

JA

Junction to Ambient

Natural Convection 1,2

R

θ

JMA

Junction to Ambient

Natural Convection 1,3

R

θ

JMA

R

θ

JMA

Four layer board

(2s2p)

Junction to Ambient (@200 ft/min) 1,3 Single layer board

(1s)

Junction to Ambient (@200 ft/min) 1,3 Four layer board

(2s2p)

R

θ

JB

R

θ

JC

Ψ

JT

Junction to Board 4

Junction to Case 5

Junction to Package Top 6

VALUE UNIT

18.4

°C/W

13.0

13.0

9.7

6.2

1.1

Natural Convection 1.1

°C/W

°C/W

°C/W

°C/W

°C/W

°C/W

1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3 Per JEDEC JESD51-6 with the board horizontal.

4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate used for case temperature.

6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.



V 02



AC Electrical

Characteristics

The figures and tables in this section describe the AC electrical characteristics of the M-5

CA. All of the input and outputs of the M-5 CA are 3.3V LVTTL compatible. The MDIO/low speed serial interface signals have Schmitt triggered inputs. Specifications are stated for T j

= -40 o C to 105 o C , V

DD

= AV

DD

=1.8 + 0.15V dc, OV

DD

= 3.3+0.3V dc, and rise and fall time of

1.5 ns of all input signals; except where explicitly counter indicated.

M-5 CA Reference Clock

Timing Specification

See Figure 4 . The M-5 CA Reference Clock is the master clock of the device and is used to

drive the M-5 CA PLL. The UL3 (UTOPIA Level 3), PL3 (SATURN POS-PHY Level 3 and a UL3L

(UTOPIA Level 3 - Like) (UL3/PL3/UL3L) interface timing is specified relative to this clock input.

Figure 4 M-5 CA Reference Clock

Cycle 1 Cycle 2 Cycle 3

M-5 Adapter

CLK t f

, t r t pwh t pwl

1/f clk

Table 28 M-5 CA Reference Clock AC Specification

SYMBOL f clk t pwh

/t pwl t r

/t f t lock

CHARACTERISTIC

Clock Frequency

MIN

66 MHz

Clock Pulse Width High/Low 1 3.85 ns

Clock Rise/Fall Time 2

PLL Lock Time 3 -

-

1 Measured between 50-50% points.


3 Lock time after compliant M5CLK signal applied.

MAX

104 MHz

-

2.0 ns

2048 clocks

+ 50 µs

M5CAA0




AC Electrical Characteristics 39

UTOPIA Level 3, SATURN

POS-PHY Level 3 and

UTOPIA Level 3-Like

(PL3/UL3/UL3L)

See Figure 5 . The M-5 CA supports UL3 (UTOPIA Level 3) and PL3 (SATURN POS-PHY Level

3) framer interfaces and a UL3L (UTOPIA Level 3-Like) C-5e NP system interface. These interfaces have identical timing attributes with the only exception being the output load at which timing is specified. The more demanding load of 30pF is used for specification.

Figure 5 PL3/UL3/UL3L Interface

Cycle 1 Cycle 2 Cycle 3

M-5 Adapter

CLK

Inputs t s t h

Outputs t valid

Table 29 PL3/UL3/UL3L AC Specification

SYMBOL CHARACTERISTIC t s t h t valid

Input setup time to rising edge of M5CLK 1

Input hold time to rising edge of M5CLK 1

Output valid time after rising edge of M5CLK 1,2,3

MIN

2.0

0.5

1.5

-

-

MAX UNIT

6.0

ns ns ns


2 UL3 specification is 0 ns minimum, PL3 specification is 1.5 ns minimum which is used for M-5 CA.

3 Timing specified for 30pF output load.

V 02





Gigabit Ethernet Media

Independent Interface

(GMII)

See Figure 6 . The M-5 CA supports a GMII C-5e NP interface. The GMII interface AC

specifications do not meet the IEEE 802.3 specifications, but are rather designed to interoperate as a point-to-point interface with the C-5e NP. The RXDV, RXD and COL M-5

CA output signals are synchronous to the falling edge of the receiver interface clock,

RXCLK, to meet the C-5e NP input hold time requirements. The GMII source-synchronous interfaces operate at the same frequency as the M-5 CA master clock, but have an arbitrary bounded phase relationship.

Figure 6 Gigabit Ethernet Media Independent Interface (GMII)

Cycle 1 Cycle 2

GTX_CLK

RXCLK t pwh/pwl

TXxx

Inputs t s t h

RXxx, COL

Outputs t valid

Table 30 GMII AC Specification

SYMBOL t pwh

/t pwl t s t h

CHARACTERISTIC

Clock pulse width high/low 1

Input setup time to rising edge of

GTX_CLK 1

Input hold time to rising edge of

GTX_CLK 1

MIN

3.85

2.0

0.0

-

-

-

MAX UNIT ns ns ns

M5CAA0





Table 30 GMII AC Specification (continued) t valid

Φ drift

Output valid time after falling edge of

RXCLK 1,2,3

Phase drift tolerance between

GTX_CLK and M5CLK 4, 5

-1.0

-360

1.0

360 ns degrees


2 Provides an equivalent output valid time of 3.8 ns min, 5.8 ns max relative to the rising edge of

RXCLK at 104 MHz.


4 After compliant M5CLK signal applied and reset deasserted.

5 Not tested but guaranteed by design.

Management Data

Input/Output (MDIO)

See Figure 7 on page 42. The MDIO interface follows the IEEE 802.3 Standard protocol but

does not have the same AC characteristics. IEEE 802.3 specifies an interface that operates at a minimum period of 400 ns and utilizes an open-drain driver with passive pull-up. The

M-5 CA MDIO must work with the C-5e NP MDIO that operates at a minimum period of 40 ns and utilizes a LVTTL three state driver. Although, the interface is compliant with IEEE

802.3 Standard AC characteristics with the exception of an external pull-up resistor and reduction of the cycle time to 40ns.



V 02



Figure 7 MDIO Interface

Cycle 1

MDC

Cycle 2 Cycle 3 t cycle t pwl t pwh

MDIO into

M-5 Adapter t s t h

MDIO out of

M-5 Adapter t valid t r

/ t f

Table 31 MDIO AC Specification

SYMBOL t cycle t pwh

/t pwl t s t h t r

/t f t valid t valid


MDC cycle time

MDC pulse width high/low

Input setup time to rising edge of MDC

Input hold time to rising edge of MDC

MDIO rise and fall time 2

Output valid time after rising edge of MDC

Output valid time after rising edge of MDC

2

3 -

-

MIN MAX UNIT

40

16

10

0.0

0

-

-

-

-

15.5

20

75 ns ns ns ns ns ns ns

1 All timing measured relative to V

IL

and V

IH

points.

2 Timing for minimum cycle time operation with 10pF to 100pF load.

3 Timing for IEEE 802.3 compliant load of 470pF; minimum cycle time operation is not possible.

Not tested but guaranteed by design.

M5CAA0





Low Speed Serial Bus

(LSP)

Figure 8 on page 43. The M-5 CA Low Speed Serial Bus (LSB) slave interface works with the

C-5e NP low speed serial bus master interface and other slave devices on the bus.

Operation to 400kHz is supported.

Figure 8 LSP Interface

Cycle 1 Cycle 2

SICL t pwh t pwl t cycle

SIDA into

M-5 Adapter t s:s t f

SIDA out of

M-5 Adapter t h:s t s:d t sp t h:d t s:stop t buf t r t of t valid

Table 32 Low Speed Serial Bus AC Specification

SYMBOL t cycle t pwh t pwl t r

/t f t of t s:s t h:s t s:d t sp

CHARACTERISTIC 1, 2

SICL cycle time

SICL pulse width high

SICL pulse width low

Input rise and fall time

Output fall time 3

Input setup time for repeated START condition

Input hold time for repeated START condition

Input setup time for data

Pulse width of spike that must be suppressed by the input filter

MIN

2500

600

1300

2

2

600

600

100

0

-

-

-

-

MAX UNIT ns ns ns

-

300

60 ns ns ns ns

-

50 ns ns

V 02





Table 32 Low Speed Serial Bus AC Specification (continued)

SYMBOL t h:d t s:stop t buf

CHARACTERISTIC 1, 2

Input hold time for data

Input setup time for STOP condition

Bus free time between a STOP and START condition

MIN

0

600

1250 t valid

Output valid time 0

1 All timing measured relative to V

IL

and V

IH

points.

2 Timing with 10pF to 400pF output load (C

L

).

3 M-5 CA does not meet the slew-controlled Min fall time equal to 20+0.1*C

L

.

350

-

-

-

MAX UNIT ns ns ns ns

M5CAA0





JTAG

See Figure 9 . The M-5 CA has an IEEE 1149.1 Standard Test Access Port and Boundary-Scan

Architecture compliant implementation.

Figure 9 JTAG Interface

Cycle 1 Cycle 2

TCK

1/f

TCK

TDI

TMS t s t h

TDO t valid

Table 33 JTAG AC Specification

SYMBOL CHARACTERISTIC t t s valid t h f

TCK f

D

R

PU

Output valid time after falling edge of TCK 1,2

Setup time to rising edge of

Hold time to rising edge of

TCK frequency

TCK duty cycle

Pull-up impedance to OV

TCK

TCK

DD

3

1

1



3 Internal pull-ups on TDI, TMS and TRSTB.

-

35

74

MIN

1.0

15.0

15.0

-

-

MAX

8.0

20

65

135

UNIT ns ns ns

MHz

% k

Ω

V 02





M5CAA0



Chapter 4


M5CAA0-DS

Rev 02

MECHANICAL SPECIFICATIONS

Package Views

The M-5 CA is an adapter ISA 324 pin Tape Ball Grid Array (TBGA). Figure 10 and

Figure 11

and

Table 34 show the package measurements.

Figure 10 M-5 CA TBGA Package Side View

A A

2 d

A

1

Seating Plane



V 02


48 CHAPTER 4: MECHANICAL SPECIFICATIONS

Figure 11 M-5 CA TBGA Package (Bottom View)

D

1

N b e

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

AG

A

B

F

G

H

J

C

D

E

K

L

AH

AJ

AK

E

1

N

M5CAA0




Package Measurements 49

Package Measurements

Table 34 defines the M-5 CA package measurements, providing nominal, minimum, and

maximum sizes where appropriate. See

Figure 10 and

Figure 11 for Symbols.

Table 34 M-5 CA Package Measurements

E

1

N

D

1 e

E

SYMBOL

A

A

1

A

2 b

D

DEFINITION

Overall

Ball height

Body thickness

Ball diameter

Body size

Ball footprint (X)

Ball pitch

Body size

Ball footprint (Y)

Ball Matrix

0.63

31

29

1.00

NOM. (MM)

1.65

0.60

1.05

31

29

30 x 30

MIN. (MM) MAX. (MM)

1.20

0.40

0.80

0.50

0.70

Marking Codes

Table 35 explains the marking on the M-5 CA.

Table 35 M-5 CA Marking Codes

MARKING (EXPLANATION OF CODES)

Top Logo/Part#/Country of Origin/Date Code

Bottom

Pin 1 Marking

N/A

Pin 1 has a solid dot in the A1 ball location marked on the package.

V 02




50 CHAPTER 4: MECHANICAL SPECIFICATIONS

Reflow

Typical Reflow Profile for the M-5 CA is described below.

• No minimum solder paste volume is required since the solder ball melts during reflow.

• TBGA has a high thermal mass and should be carefully profiled.

• Suggested profile (somewhat flux-dependent):

– Qualified to a maximum reflow temperature of 220°C -0/+5.

– Raise temperature of the joints to 100°C in 50 secs or less.

– Peak component temperature typically between 205 and 220°C.

– Desirable dwell time above 183°C between 50 and 80 secs.

This is a general guideline and should be modified as needed by the reflow vendor.

M5CAA0




M5CAA0-DS

Rev 02

INDEX

A

About This Guide

1

Absolute Maximum Ratings

35

AC Electrical Characteristics

38

C

CP Cluster Configuration Options for OC-48

13

CP Cluster to Framer Configurations Supported by the M-5 CA

13

D

DC Electrical Characteristics

35

E

Electrical Specifications

35

F

Fabric Processor Port Framer Configuration Supported by the M-5

Channel Adapter

14

Framer Configuration

13

Framer connections to C-5e NP Channel Processors and Fabric

Processor via the M-5 CA

11

Framer to C-5e Channel Processor Mapping

14

Functional Description

7

G

Gigabit Ethernet Media Independent Interface (GMII)

40 , 40

GMII

12

GMII AC Specification

40

Guide Conventions

4

J

JTAG

45

JTAG AC Specification

45

JTAG Interface

45

L

Low Speed Serial Bus (LSP)

43

Low Speed Serial Bus AC Specification

43

LSP Interface

43

M

M-5 CA BGA Package, Bottom View

16 ,

48

M-5 CA Chip I/O (1 of 2)

17

M-5 CA Chip I/O (2 of 2)

19

M-5 CA Functional Block Diagram

10

M-5 CA Marking Codes

49

M-5 CA on the Fabric Processor Port

14

M-5 CA Reference Clock

38

M-5 CA Reference Clock AC Specification

38

M-5 CA Reference Clock Timing Specification

38

M-5 CA System Overview Block Diagram

11

M-5 Channel Adapter (CA) Features

9

M-5 TMC BGA Package, Side View

47

Management Data Input/output (MDIO)

41

MDIO AC Specification

42

MDIO Interface

42

Measurements

M-5 CA

49

Mechanical Specifications

47

V 02




52 INDEX

P

Package Measurements

49

Package Views

47

Pinouts

16

PL3/UL3/UL3L AC Specification

39

PL3/UL3/UL3L Interface

39

Possible Framer Configurations

13

R

Recommended Operating Conditions

36

Reflow

50

Related Product Documentation

4

revision history, for this guide

5

S

SATURN POS-PHY Level 3

12

Serial Interface Configuration Pins

23

Serial Interface Signals

23

Serial Port Signals

24

Signal Decriptions

15

Signal Descriptions

M-5 CA to C-5e NP Channel Processors (CPs) Connections

27

Signals

Serial Interface

23

Serial Interface Configuration Pins

23

Serial Port

24

T

Thermal Specifications

37

Typical Reflow Profile for the M-5 CA

50

U

UL3 (UTOPIA Level 3), PL3 (SATURN POS-PHY Level 3 and a UL3L

(UTOPIA Level 3 - Like) (PL3/UL3/UL3L)

39

Using C-Port Electronic Documents

2

UTOPIA Level 3

12

M5CAA0







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