NXP MAC7124 32-bit Automotive Microcontrollers Reference Manual

NXP MAC7124 32-bit Automotive Microcontrollers Reference Manual
MAC7100EVB Users Manual
Revision 1.1
November 2004
Note – This users manual is for RE11505F Rev O PCBs
MAC7100EVB Users Manual Rev 1.1
November 2004
Revision History:
Revision
0.2
1.0
1.1
Date
27 June 2003
18 Sept 2003
12 Nov 2004
Author
A. Robertson
A. Robertson
A. Robertson
Comment
Initial Release – Prototype PCB Only
Changes for RE11505F Rev O Production PCB
Changed to Freescale. Updated MAC family table
Information in this document is provided solely to enable system and software implementers to use Freescale
Semiconductor products. There are no express or implied copyright licenses granted hereunder to design
or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale
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© Freescale Semiconductor, Inc., 2004; All Rights Reserved
MAC7100EVBUM/D
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INDEX
1.
INTRODUCTION..................................................................................................................................................... 1
1.1
2.
EVB FEATURE LIST............................................................................................................................................ 2
CONFIGURATION .................................................................................................................................................. 3
2.1
POWER SUPPLY CONFIGURATION ....................................................................................................................... 4
2.1.1
Power Supply Input Connectors ................................................................................................................... 4
2.1.2
Power Supply Configuration Jumpers (J41, J42 and J43) ........................................................................... 5
2.1.3
Power Switch (SW4) ..................................................................................................................................... 6
2.1.4
Power Status LED’s and Fuse ...................................................................................................................... 7
2.2
MCU POWER SUPPLY JUMPERS (J15, J19, J21, J22 AND J27)............................................................................. 7
2.3
ADC REFERENCE VOLTAGE SELECT (J7, J8)...................................................................................................... 8
2.4
MCU CLOCK CONTROL (JUMPERS J23, J29, J30 AND J32) ................................................................................. 9
2.4.1
Clock Selection ............................................................................................................................................. 9
2.4.2
PLL Control (J45)....................................................................................................................................... 10
2.5
ABORT SWITCH AND CONTROL (J1, SW3)........................................................................................................ 11
2.6
RESET SWITCH, LEDS AND LVI CONTROL (JUMPERS J10, J11, J12, SW2) ...................................................... 11
2.6.1
Reset LEDs.................................................................................................................................................. 12
2.7
RESET BUFFERING SCHEME .............................................................................................................................. 12
2.8
RESET MODE CONFIGURATION (SW1) ............................................................................................................. 13
2.9
JTAG AND NEXUS CONFIGURATION (J13, J18) ................................................................................................ 14
2.9.1
JTAG Configuration.................................................................................................................................... 15
2.9.2
Nexus Configuration (J14, J20) .................................................................................................................. 15
2.10
EXTERNAL MEMORY CONFIGURATION............................................................................................................. 17
2.10.1
Buffer Control (J26)............................................................................................................................... 17
2.10.2
Chip Select Control (J24)....................................................................................................................... 18
2.10.3
External SRAM Configuration (J35)...................................................................................................... 19
2.10.4
External FLASH Configuration (J31, J33, J34)..................................................................................... 20
2.11
ETHERNET CONTROLLER CONFIGURATION (JUMPERS J36, J37, J38, J39, J40) ................................................. 21
2.12
CAN CONFIGURATION (J2, J3, J4).................................................................................................................... 23
2.13
RS232 CONFIGURATION (J5, J6, J9) ................................................................................................................. 24
2.14
TERMINATION RESISTOR CONTROL (J28) ......................................................................................................... 25
2.15
MCU TA JUMPER (J25).................................................................................................................................... 25
3.
DEFAULT JUMPER SUMMARY TABLE ......................................................................................................... 26
4.
JUMPER CONFIGURATIONS FOR EVB OPERATING MODE ................................................................... 27
5.
USER CONNECTOR DESCRIPTIONS .............................................................................................................. 28
5.1
5.2
5.3
5.4
5.4.1
5.5
5.6
5.7
6.
EXPANSION CONNECTORS .............................................................................................................................. 33
6.1
7.
PORT A / DATABUS (P12) ................................................................................................................................ 28
PORT B / I2C / SPI (P10) .................................................................................................................................. 28
PORT C / ADDRESS [0..15] (P13)...................................................................................................................... 29
PORT D / ADDRESS [16..21] / CONTROL (P14 AND J44) ................................................................................... 29
PD2 / CLKOUT impedance matching control (J44)................................................................................... 30
PORT E / ADC AND ANALOGUE REFERENCE (P11 AND J17) ............................................................................ 30
PORT F / EMIOS AND USER LED’S (P9, J16).................................................................................................. 31
PORT G / CAN / SCI (P8) ................................................................................................................................. 32
USE OF MCU ADAPTER BOARDS ....................................................................................................................... 34
PROTOTYPE AREA.............................................................................................................................................. 35
APPENDIX A - BILL OF MATERIALS
APPENDIX B - SCHEMATICS
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Index of Figures and Tables
FIGURE 2-1 EVB FUNCTIONAL BLOCKS ........................................................................................................................... 3
FIGURE 2-2 2.1MM POWER CONNECTOR .............................................................................................................................. 4
FIGURE 2-3 2-LEVER POWER CONNECTOR ........................................................................................................................... 4
FIGURE 2-4 PC POWER CONNECTOR .................................................................................................................................... 5
FIGURE 2-5 VDDIO REGULATOR VARIABLE OUTPUT ......................................................................................................... 6
FIGURE 2-6 ADC REFERENCE VOLTAGE SELECTION ........................................................................................................... 8
FIGURE 2-7 EVB CLOCK SELECTION ................................................................................................................................... 9
FIGURE 2-8 PIERCE OSCILLATOR CONFIGURATION ........................................................................................................... 10
FIGURE 2-9 EVB RESET BUFFERING SCHEME .................................................................................................................... 12
FIGURE 2-10 RESET CONFIGURATION (MODE) SWITCH ..................................................................................................... 13
FIGURE 2-11 JTAG CONNECTORS...................................................................................................................................... 15
FIGURE 2-12 EXTERNAL MEMORY SCHEME....................................................................................................................... 17
FIGURE 2-13 CHIP SELECT ROUTING ................................................................................................................................. 18
FIGURE 2-14 ETHERNET CONTROLLER BLOCK DIAGRAM .................................................................................................. 21
FIGURE 2-15 CAN PHYSICAL INTERFACE CONNECTOR ..................................................................................................... 23
FIGURE 2-16 RS232 PHYSICAL INTERFACE CONNECTOR ................................................................................................... 24
FIGURE 5-1 J16 AND USER LED CONTROL ......................................................................................................................... 31
TABLE 1-1 MAC7100 PRODUCT FAMILY ............................................................................................................................ 1
TABLE 1-2 MAC7100 PACKAGE OPTIONS ........................................................................................................................... 1
TABLE 2-1 REGULATOR CONFIGURATION JUMPERS ............................................................................................................. 5
TABLE 2-2 POWER SUPPLY DISTRIBUTION ........................................................................................................................... 6
TABLE 2-3 MCU POWER SUPPLY JUMPERS ......................................................................................................................... 7
TABLE 2-4 CLOCK SOURCE JUMPER SELECTION .................................................................................................................. 9
TABLE 2-5 PLL DISABLE JUMPER ...................................................................................................................................... 10
TABLE 2-6 ABORT ENABLE JUMPER................................................................................................................................... 11
TABLE 2-7 LVI RESISTOR LADDER VALUES ...................................................................................................................... 11
TABLE 2-8 LVI CONTROL JUMPERS ................................................................................................................................... 11
TABLE 2-9 MAC7100 RESET CONFIGURATION ................................................................................................................. 13
TABLE 2-10 JTAG / NEXUS TARGET RESET ROUTING JUMPER J13 ................................................................................. 14
TABLE 2-11 JTAG / NEXUS TCLK TERMINATION J18..................................................................................................... 14
TABLE 2-12 NEXUS CONNECTORS ..................................................................................................................................... 15
TABLE 2-13 EVTI TERMINATION ENABLE JUMPERS J14, J20 ............................................................................................ 16
TABLE 2-14. NEXUS DEBUG CONNECTOR PINOUT ........................................................................................................... 16
TABLE 2-15 EBI BUFFER CONTROL JUMPER J26 ............................................................................................................... 17
TABLE 2-16 CHIP SELECT JUMPER J24............................................................................................................................... 18
TABLE 2-17 SRAM POWER SUPPLY JUMPER J35............................................................................................................... 19
TABLE 2-18 SRAM PIN COMPATIBLE DEVICES ................................................................................................................. 19
TABLE 2-19 FLASH CONTROL JUMPERS ........................................................................................................................... 20
TABLE 2-20 AMD FLASH PIN COMPATIBLE DEVICES ........................................................................................................ 20
TABLE 2-21 ETHERNET CIRCUIT CONTROL JUMPERS ......................................................................................................... 22
TABLE 2-22 CAN CONTROL JUMPERS ............................................................................................................................... 23
TABLE 2-23 RS232 CONTROL JUMPERS ............................................................................................................................. 24
TABLE 2-24 EBI PULLUP RESISTOR CONTROL (J29).......................................................................................................... 25
TABLE 2-25 JUMPER J25 .................................................................................................................................................... 25
TABLE 3-1 DEFAULT JUMPER POSITIONS ........................................................................................................................... 26
TABLE 4-1 CRITICAL JUMPER POSITIONS ........................................................................................................................... 27
TABLE 5-1 CONNECTOR P12 – PORTA / DATABUS ............................................................................................................. 28
TABLE 5-2 CONNECTOR P10 – PORTB / I2C / SPI............................................................................................................... 28
TABLE 5-3 CONNECTOR P13 – PORT C / ADDRESS ............................................................................................................. 29
TABLE 5-4 CONNECTOR P14 – PORT D / ADDRESS / CONTROL .......................................................................................... 29
TABLE 5-5 PD2 / CLKOUT TERMINATION BYPASS JUMPER ............................................................................................. 30
TABLE 5-6 CONNECTOR P11 – PORT E / ADC.................................................................................................................... 30
TABLE 5-7 RV1 CONNECTION JUMPER J17........................................................................................................................ 30
TABLE 5-8 CONNECTOR P9 – PORT F / EMIOS.................................................................................................................. 31
TABLE 5-9 CONNECTOR P8 – PORT G / CAN / SCI ............................................................................................................ 32
TABLE 6-1 EXPANSION CONNECTOR PART NUMBERS ........................................................................................................ 33
TABLE 6-2 EXPANSION CONNECTOR 1 (P5) ....................................................................................................................... 33
TABLE 6-3 EXPANSION CONNECTOR 2 (P19) ..................................................................................................................... 34
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MAC7100EVB Users Manual Rev 1.1
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1. Introduction
This document details the setup and configuration of the Freescale MAC7100 evaluation board (hereafter referred to as
the EVB). The EVB is intended to provide a mechanism for easy customer evaluation of the MAC7100 family of
microprocessors and to facilitate hardware and software development.
The table below shows the MAC7100 family portfolio (correct at time of writing this document).
Table 1-1 MAC7100 Product Family
Part Number
Flash Size
RAM Size
Expanded Bus
MAC71x6
1MB
48KB
Optional
MAC71x5
768KB
40KB
Optional
MAC71x1
512KB
32KB
Optional
MAC71x4
384KB
20KB
Contact Freescale
MAC71x2
256KB
16KB
Contact Freescale
The “x” in the part number field defines the package type and pinout options of the MCU. For information purposes, the
package types are detailed below.
Table 1-2 MAC7100 Package Options
Package Designator
0
1
2
3
4
Package Type
144 LQFP
144 LQFP
112 LQFP
208 MAP BGA
100 LQFP
ADC Channels
32
16
16
32
16
External Bus
No
Yes
No
Yes
No
Note that not all packages are available for all devices. The information detailed in the tables above is subject to change.
For the latest product information, please consult the MAC7100 website at www.freescale.com/mac7100, or speak to
your Freescale representative.
The MAC7100 EVB is populated with the MAC7111 MCU. As can be seen from the tables above, this is a 144QFP
device with 512Kbytes of Flash and 32Kbytes of SRAM. Should you wish to develop using any of the lower
specification devices, this can be achieved by emulating the feature set with the MAC7111 on the EVB. If you are
developing with a higher specification device, EVB adapter boards are available for this purpose. For important
information on the use of adapter board, please see section 6.1.
All of the MAC7100 family members in the same package are pin compatible (eg the MAC7111 is pin compatible to the
MAC7115).
The EVB is intended for bench / laboratory use and has been designed using normal temperature specified components
(+70°C).
Throughout this document, active low MCU signals are denoted with an “x” added onto the signal name, eg XCLKSx.
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1.1 EVB Feature List
The EVB provides the following features:
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
MAC7111 MCU device soldered directly onto the EVB with sufficient room to fit a surface mount Yamaichi
IC149-144 series socket if required (solder tabs and polarisation pins are supported).
Single external power supply input (7-14V), regulated on board to provide all the necessary EVB voltages.
Power may be supplied via a 2.1mm barrel power jack, 2-way Lever style connector or standard PC (Molex
style) power supply connector.
Flexible on board power supply selection, including the ability to bypass the internal 2.5V MCU regulator if
desired.
Master power switch.
User Reset and Abort pushbutton switches.
Configurable Low Voltage Inhibit (LVI) control circuitry to monitor all of the voltages from the EVB
regulators.
Full reset mode configuration switches.
Flexible MCU clock source options allowing clock to be selected from on board crystal circuit, on board
oscillator module or external clock source (via BNC connector). Both traditional and loop controlled (amplitude
limited) Pierce oscillator configurations are supported for the local crystal circuit.
14 and 20-way JTAG connectors.
38 pin MICTOR (Matched Impedance Connector) NEXUS connectors.
Two 120-way expansion connectors to allow connection of a daughter card supporting different MCU variants
or additional application specific circuitry.
Array of 0.1 inch pitch user connectors, providing direct access to all of the MCU port signals.
Up to 128K Bytes of asynchronous SRAM supported on the EVB. Can be configured for use with any MCU
chip select.
Up to 2M Bytes of asynchronous FLASH supported on the EVB with hardware write protection jumpers. As
with the SRAM, this can also be configured for use with any MCU chip select.
Two SCI (RS232) physical interface circuits connected to standard PC style DB9 female connectors allowing
direct connection to a PC serial port using a standard serial cable.
Two Philips PCA82C250T high-speed CAN interface transceivers connected to the MCU CAN channels A and
B.
Memory mapped full duplex 10/100 Megabit Ethernet controller and RJ45 connector.
Small prototyping area consisting of a grid of 0.1 inch spaced through holes with easy access to ground and
power supply points.
IMPORTANT
Before the EVB is used or power is applied, please fully read the following sections on
how to correctly configure the board.
Failure to correctly configure the board may cause device or EVB damage.
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2. Configuration
This section details the configuration of each of the EVB functional blocks.
Throughout this document, all default jumper and switch settings are clearly marked with “(D)” and are shown in blue
text. This should allow a more rapid return to the default state of the EVB if required. Note that the default configuration
for all 3-pin jumpers is a header fitted between pins 1 and 2.
The EVB has been designed with ease of use in mind and, where possible, has been segmented into functional blocks as
shown below. Detailed silkscreen legend has been used throughout the board on all switches, jumpers and user
connectors.
Figure 2-1 EVB Functional Blocks
Reset and Abort
Serial (SCI)
CAN
Prototype
Area
JTAG and
NEXUS
User
Connectors
SRAM
and
FLASH
External
Clock
Power
Connectors
Power
Switch
MCU and Expansion
Connectors
MAC7100EVBUM/D
Ethernet Controller
Voltage Regulators
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MAC7100EVB Users Manual Rev 1.1
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The Power supply
section is located in
the bottom left area of
the EVB
2.1 Power Supply Configuration
The EVB requires an external supply voltage of 7-14V DC, minimum 1Amp. This is regulated on board using three
switching voltage regulators to provide the necessary EVB voltages of 5V, 3.3V and 2.5V. There are three different
power supply input connectors on the EVB as described in the following section.
2.1.1
Power Supply Input Connectors
2.1mm Barrel Connector – P23:
This connector should be used to connect the supplied wall-plug mains adapter. Note – if a replacement or alternative
adapter is used, care must be taken to ensure the 2.1mm plug uses the correct polarisation as shown below:
V+ (7-14V)
GND
Figure 2-2 2.1mm Power Connector
2-Way Lever Connector – P21:
This can be used to connect a bare wire lead to the EVB, typically from a laboratory power supply. The polarisation of
the connectors is clearly marked on the EVB and care must be taken to ensure this is connected correctly.
V+ (7-14V)
GND
Figure 2-3 2-Lever Power Connector
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PC Style Power Connector – P20:
PC Power supplies offer an in-expensive source of stable, high current DC power. The EVB is designed to support direct
connection of a PC power supply 4-way connector (Molex Style plug that would normally be connected to a PC hard
disk or other internal PC hardware). Only the +12V line is used on the EVB and the +5V line is not connected to any
EVB circuitry. Typically, the +12V line will be coloured yellow (as shown in the figure below), however the connectors
are polarised and can therefore only be connected in the correct orientation.
+5V (N/C on EVB)
GND
GND
+12V
PC Power Connector
PCB Socket P20
Figure 2-4 PC Power Connector
Notes:
- PC power supplies are designed to be used with a load connected to both the 5V and 12V lines. Without this, the
power supply may shut down or not regulate correctly. The load of the EVB is generally sufficient for the +12V
line but supplemental loading may be required on the +5V line in order for the 12V line to regulate correctly or
indeed for the power supply to power on.
- If an ATX style power supply is used, there is an additional requirement in that the “PS_ON” line on the
motherboard connector must be grounded in order for the power supply to start. Please see the associated
power supply documentation for details.
2.1.2
Power Supply Configuration Jumpers (J41, J42 and J43)
The Power supply control jumpers are located adjacent to the respective regulators.
As mentioned above, the EVB has three voltage regulators on board:
-
2.5V regulator (U18) to supply the MCU Core voltage when the MCU on-chip regulator is disabled.
3.3V regulator (U19) for the EVB peripherals (For example Ethernet Controller).
VDDIO regulator (U20) for the MCU I/O supply and EVB peripherals.
The 2.5V and 3.3V regulators can be disabled if they are not required. The VDDIO regulator has the option of being used
in either a fixed 5V mode configuration or in a variable 3-5V mode. This is intended to support the MAC7100
specification where the peripheral voltage can be varied.
Table 2-1 Regulator Configuration Jumpers
Jumper
J41 (2.5V)
J42 (3.3V)
J43 (VDDIO)
Position
1-2 (D)
2-3
1-2 (D)
2-3
1-2 (D)
2-3
PCB Legend
ENABLE
DISABLE
ENABLE
DISABLE
5V
VAR
Description
2.5V regulator output is Enabled
2.5V regulator output is Disabled
3.3V regulator output is Enabled
3.3V regulator output is Disabled
VDDIO regulator is configured as 5.0V fixed mode.
VDDIO regulator is configured as 3-5V variable
mode controlled by RV2
When the VDDIO regulator is set to variable mode, the output can be varied from approximately 3V to 5V by moving
trimming resistor RV2. The following graph gives an indication of the expected VDDIO regulator output voltage against
resistor value when used in variable mode.
MAC7100EVBUM/D
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November 2004
960
900
840
780
720
660
600
540
480
420
360
300
180
120
60
240
LM2596 Regulator Output
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
0
Volts
MAC7100EVB Users Manual Rev 1.1
Resistance (Var)
Figure 2-5 VDDIO Regulator Variable Output
Before changing any of the regulator configurations, it is worthwhile carefully considering if any of the EVB components
you require will be affected. Table 2-2 details a list of the various EVB components and peripherals affected by each
regulator.
Table 2-2 Power Supply Distribution
Regulator
VDDIO
(3-5V)
Used On
Comments
MCU VDDA, VDDX and VDDR pins
External FLASH and SRAM
5V mode only. Disable if VDDIO < 4.75V *
CAN / RS232 physical interface drivers
5V mode only. Disable if VDDIO < 4.75V *
Expansion and prototype area connectors
Reset control and Abort switch circuits
Nexus and JTAG connectors
Pullup resistors
LED’s and variable resistor on user connectors
MCU 2.5V and VDDPLL pins (When VDDR = 0V)
Only when MCU on-chip regulator disabled
2.5V
External Oscillator Module
LVI circuit main power and reset switch
Expansion and prototype area connectors
Address Data-Bus and control buffers
3.3V
Ethernet Controller
Ethernet circuit PLD (also controls TGT-TA signal)
Expansion and prototype area connectors
* If the VDDIO regulator is set to variable mode, these blocks must be disabled if VDDIO < 4.75V
2.1.3
Power Switch (SW4)
Slide switch SW4 can be used to isolate the power supply input from the EVB voltage regulators if required.
Moving the slide switch to the right (away from connector P21) will turn the EVB on.
Moving the slide switch to the left (towards connector P21) will turn the EVB off.
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2.1.4
November 2004
Power Status LED’s and Fuse
When power is applied to the EVB, green power LED’s adjacent to the voltage regulators show the presence of the
supply voltages as follows:
LED DS10 – Indicates that the 2.5V regulator is enabled and working correctly
LED DS11 – Indicates that the 3.3V regulator is enabled and working correctly
LED DS12 – Indicates that the VDDIO (3-5V) regulator is working correctly
If no LED’s are illuminated when power is applied to the EVB and the Regulator jumpers are set to “enable”, it is
possible that either power switch SW4 is in the “OFF” position or that the fuse F1 has blown. This can occur if power is
applied to the EVB in reverse-bias where a protection diode ensures that the fuse blows rather than causing damage to the
EVB. Replace F1 with a 20mm 1A fast blow fuse.
The MCU Power supply
jumpers are located to the
right of the MCU in a box
titled “MCU Supply”
2.2 MCU Power Supply Jumpers
(J15, J19, J21, J22 and J27)
The MCU power supply lines are grouped together according to function (eg VDDX, VDDA). Each grouping is
jumpered to allow isolation from the power supply in order to facilitate current measurement. In addition, these jumpers
are used to disable the MCU on-chip 2.5V regulator if required and allow the EVB 2.5V regulator to be used to power
the MCU core and PLL circuitry.
Table 2-3 MCU Power Supply Jumpers
Jumper
J19 (ADC)
J15 (I/O)
J21 (REG) *
J22 (2.5V) *
J27 (PLL) *
Position
FITTED (D)
REMOVED
FITTED (D)
REMOVED
1-2 (D)
2-3
FITTED
REMOVED (D)
FITTED
REMOVED (D)
Description
Connects EVB VDDIO regulator output to MCU VDDA pins
MCU VDDA logic is not powered
Connects EVB VDDIO regulator output to MCU VDDX pins
MCU VDDX logic is not powered
Connects EVB VDDIO regulator output to MCU VDDR pins
Connects MCU VDDR to GND (required if J22 / J27 fitted)
Connects EVB 2.5V regulator output to MCU VDD2.5 pins
MCU On Chip regulator powers VDD2.5
Connects EVB 2.5V regulator output to MCU VDDPLL pins
MCU On Chip regulator powers VDDPLL
CAUTION: * When jumper J21 (REG) is set to position 1-2 (ON), enabling the built in 2.5V MCU regulator, jumpers
J22 (2.5V) and J27 (PLL) MUST be removed.
The jumper configuration shown in Table 2-3 shows the default state of the EVB where the EVB is configured to use the
MCU on-chip 2.5V regulator. In this case, jumpers J22 and J27 are removed and no external 2.5V power is supplied to
the MCU. The EVB can be re-configured with the EVB 2.5V regulator powering the MCU core and PLL circuitry in
preference to the MCU on-chip regulator. In this configuration, jumper J21 (REG) is moved to position 2-3 (OFF) and
jumpers J22 (2.5V) and J27 (PLL) are fitted.
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2.3 ADC Reference Voltage Select (J7, J8)
The ADC reference voltage
jumpers are located at the
top of the EVB in a box
titled “ADC REF”.
The Analogue to digital converter reference voltages, VRH and VRL can be connected directly to the EVB supply lines
(where VRH is connected to VDDIO and VRL to GND) or can be routed to user connector P11, allowing user defined
reference voltages to be supplied.
Figure 2-6 ADC Reference Voltage Selection
Jumper
J8 (VRH)
J7 (VRL)
MAC7100EVBUM/D
Position
1-2 (D)
2-3
1-2 (D)
2-3
PCB Legend
EVB
TGT
EVB
TGT
Description
MCU VRH is connected to EVB VDDIO
MCU VRH is connected to user connector P11
MCU VRL is connected to EVB analogue GND
MCU VRL is connected to user connector P11
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MAC7100EVB Users Manual Rev 1.1
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The MCU clock control jumpers are
located around the MCU (J29, J30, J45)
and above and in the area adjacent to
the BNC connector P17 (J32 and J23)
2.4 MCU Clock Control (Jumpers
J23, J29, J30 and J32)
2.4.1
Clock Selection
The EVB supports three possible MCU clock sources:
(1) The local Pierce clock oscillator circuit Y1 (which can be configured in traditional or low power modes).
(2) An oscillator module Y2, driving the MCU EXTAL signal.
(3) An external clock input to the EVB via BNC connector P17, again driving the MCU EXTAL signal.
The selection between these options is controlled using jumpers as shown below:
Figure 2-7 EVB Clock Selection
2.5V
J23
Oscillator
Module
(Y2)
Y2 PWR
1
J32
1
BNC
P17
J29
Y1
Y2
EXTAL
From J32
XTAL
BNC
EXTAL
J30
OSC SEL
MCU
Y1
Local
Crystal
Circuit (Y1)
Jumper
J23 (Y2 PWR)
J32 (OSC SEL)
J29 (EXTAL)
J30 (XTAL)
Position
FITTED
REMOVED (D)
1-2 (D)
2-3
1-2 (D)
2-3
FITTED (D)
REMOVED
PCB Legend
Y2
BNC
Y1
From J32
XTAL
Description
Oscillator Module Y2 is powered (enabled)
Oscillator Module Y2 is not powered (disabled)
External EXTAL routed from Oscillator Module Y2
External EXTAL routed from BNC Connector P17
MCU EXTAL connected to local oscillator circuit
MCU EXTAL routed to source defined by J32
MCU XTAL connected to local oscillator circuit
XTAL disconnected (External Oscillator configuration)
Table 2-4 Clock Source Jumper Selection
The default configuration connects the MCU EXTAL and XTAL pins to the local clock oscillator circuit containing Y1.
This can be configured as either loop controlled (ALC) Pierce (default) or full swing Pierce, as detailed in Figure 2-8.
The reset state of the XCLKSx (External Clock Source) pin determines the type of local oscillator circuit that will be
used (see section 2.8).
In order to configure the EVB to use an external oscillator source, jumper J29 (EXTAL) is moved to position 2-3 and
jumper J30 (XTAL) must be removed. Jumper J32 (OSC SEL) is then used to select the external clock source from either
the oscillator module Y2 (J32 in position 1-2) or BNC connector P17 (J32 in position 2-3). If the oscillator module Y2 is
to be used, jumper J23 (Y2 PWR) must be fitted.
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MAC7100EVB Users Manual Rev 1.1
November 2004
Caution - When an external oscillator source is used, XCLKSx must be set LOW (as configured for normal Pierce
configuration) - see section 2.8.
Notes:
- The power for oscillator module Y2 is sourced from the EVB 2.5V regulator so this regulator must be enabled if
oscillator module Y2 is used. See section 2.1.2 for details
- When an external oscillator source is used (Y2 or BNC), only the MCU EXTAL pin is driven. The MCU XTAL
pin must be left open circuit by removing jumper J30. When using the BNC connector, care must be taken to
ensure the signal amplitude does not exceed 2.5V.
To Clock Oscillator
/ External Clock
EXTAL
1
J29
R32
Y1
C74
Rbias
R31
XTAL
Rs
C73
J30
Default Configuration = Loop Controlled Pierce (Rs = 0Ω, RBias = αΩ)
For full swing Pierce configuration, please change Rs and RBias according
to operating conditions.
VSSPLL
Figure 2-8 Pierce Oscillator Configuration
2.4.2
PLL Control (J45)
If the PLL circuitry is not required, this can be disabled by tying the MCU XFC pin to VDDPLL. Jumper J45 provides
this functionality. The table below shows the default configuration with jumper J45 removed, thus enabling the PLL.
Table 2-5 PLL Disable Jumper
Jumper
J45 (PLL-DIS)
Position
FITTED
REMOVED (D)
Description
MCU PLL Circuitry is disabled (XFC = VDDPLL)
MCU PLL Circuitry is enabled
Note – If the PLL is disabled, the clock circuitry should be configured to use either the full swing Pierce oscillator
configuration or an external clock source.
MAC7100EVBUM/D
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MAC7100EVB Users Manual Rev 1.1
November 2004
2.5 Abort Switch and Control (J1, SW3)
The Abort Switch is located at
the top left of the EVB in a box
titled “ABORT”.
An active low, push button ABORT switch (SW3) is provided on the EVB. This is connected to the MCU XIRQx pin via
jumper J1 and when pressed, drives the MCU XIRQx signal low, causing an interrupt. Active de-bounce circuitry ensures
that a press of the switch issues a clean signal to the MCU, avoiding multiple interrupts.
Table 2-6 Abort Enable Jumper
Jumper
J1 (ABORT)
Position
FITTED (D)
REMOVED
Description
ABORT switch is connected to MCU XIRQx line (abort switch enabled)
ABORT switch is disconnected from MCU XIRQx line (disabled)
2.6 Reset Switch, LEDs and LVI Control
(Jumpers J10, J11, J12, SW2)
The Reset and LVI circuitry is
located at the top left corner of
the EVB in areas titled
“RESET” and “LVI
The EVB incorporates an LVI (Low Voltage Inhibit) device to provide under-voltage protection for all of the EVB
voltage regulators. When the regulator voltage(s) drop below a certain threshold level, the LVI will automatically assert
the MCU reset line in order to prevent incorrect operation of the MCU or EVB circuitry.
The table below shows the LVI reset threshold levels for each power supply line on the EVB.
Table 2-7 LVI Resistor Ladder Values
Regulator
2.5V
3.3V
VDDIO
Minimum Voltage Before MCU reset
2.33V
2.9V
4.75V
The LVI device is powered from the 2.5V regulator output with additional monitor inputs providing the protection for the
3.3V and VDDIO regulator outputs. Jumpers provide the possibility to disable the LVI protection for the 3.3V or VDDIO
regulators if desired. In addition, a jumper is provided to disconnect the LVI reset output so it will NOT assert the MCU
reset line. This allows the 2.5V regulator to be disabled without causing an MCU reset.
The LVI device also provides a de-bounced input for the EVB reset switch, SW2.
Table 2-8 LVI Control Jumpers
Jumper
J10 (LVI Reset)
J11 (VDDIO)
J12 (3.3V)
Position
FITTED (D)
REMOVED
1-2 (D)
2-3
1-2 (D)
2-3
PCB Legend
ENABLE
DISABLE
ENABLE
DISABLE
Description
RESET signal from LVI drives the MCU RESETx line
LVI is disconnected from MCU RESETx line (disabled)
VDDIO regulator output is monitored by LVI
VDDIO regulator output is NOT monitored by LVI
3.3V regulator output is monitored by LVI
VDDIO regulator output is NOT monitored by LVI
Notes:
- Failing to set jumper J11 to disabled when using the VDDIO regulator in variable voltage mode will cause the
LVI to issue a reset when VDDIO drops below approximately 4.75V
- If it is required to disable the 2.5V regulator on the EVB, jumper J10 must be removed to disconnect the LVI
and MCU reset lines or the LVI will continually drive the MCU reset line. Note that if the LVI device is depowered or jumper J10 is removed, the reset switch will no longer function.
MAC7100EVBUM/D
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MAC7100EVB Users Manual Rev 1.1
2.6.1
November 2004
Reset LEDs
There are two reset LED’s, DS1 (AMBER) and DS13 (RED), placed adjacent to the EVB RESET switch to indicate the
RESET status of the EVB and MCU.
LED DS13, titled “MCU”, will illuminate if the MCU itself issues a reset. In this condition, LED DS1 will NOT
illuminate.
LED DS1, titled “USR”, will illuminate when one of the following external hardware devices issues a reset to the MCU:
- LVI circuitry (either an under-voltage detection or the reset switch is being pressed)
- There is a reset being asserted from the user connectors or from the daughter card (if fitted)
- There is a reset being driven from the Nexus or JTAG debug probe.
- Note that LED DS13 (MCU) will also illuminate during an external (user) reset!
2.7 Reset Buffering Scheme
The MAC7100 family has a single RESETx pin. This pin functions as a dual purpose input / output MCU reset signal.
To reduce loading on the MCU reset pin and also allow direct connection of non open-drain reset signals (for example
connected to the user or daughter card connectors), a reset-in and reset-out buffering scheme was created as shown in
Figure 2-9. There are three possible external sources of reset:
-
JTAG / NEXUS MCU Reset
Daughter card connector or user connector
LVI Reset circuitry (including reset switch)
These are gated together independently of each other and then converted into an open-drain reset output which is directly
connected to the MCU reset pin.
Similarly, the MCU Reset pin is buffered to provide a Reset-Out signal which is used to control all devices on the EVB
that require a reset input.
JTAG/
NEXUS
MCU-RSTx
TRSTx
MCU
1
RESETx
J13
TPV13
TGT Resetx
LVI / Reset Switch
TPV14
Open-Drain Output
Reset-In Buffering
Buffered Reset-Out
Figure 2-9 EVB Reset Buffering Scheme
Notes
-
As can be seen from the figure, there is a jumper J13 on the MCU-Resetx line from the JTAG / NEXUS
connectors. For more information on this jumper, please refer to section 2.9.
The MCU TRSTx signal cannot be asserted via the external MCU Reset pin so the debug interface TRSTx signal
is not routed to the MCU reset circuitry.
MAC7100EVBUM/D
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MAC7100EVB Users Manual Rev 1.1
November 2004
The Reset Mode Switch is
located on the top edge of the
EVB in an area titled “RESET
CONFIGURATION”.
2.8 Reset Mode Configuration (SW1)
The MAC7100 has 7 external mode pins that are used to configure the operating mode of the device based on their state
at MCU reset.
The EVB uses a DIP switch (SW1) to set the value of these mode pins which is then actively driven onto the respective
MCU pins whilst the MCU reset signal is low. Table 2-9 shows the reset function and MCU pin related to each DIP
switch position
Table 2-9 MAC7100 Reset Configuration
Switch
Position
1
Switch
Legend
MODA
MCU
Pin
PD1
2
MODB
PD0
3
XCLKSx
PD2
4
PSIZ
PA14
5
AUTO-TA
PA15
6
NEX_LOC
PF0
7
NEX-EN
PF1
8
-----
Value
Setting
0 (D)
1
ON
OFF
0
1 (D)
0
1 (D)
0
1 (D)
0
1 (D)
0
1 (D)
0
1 (D)
0
1
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
Function
Boot Vector taken from normal reset vector (Only if ModeB=0)
PBL mode (Data Flash re-mapped to 0x0 and boot vector becomes
1st address of data flash. (Only if ModeB=0)
Single Chip Mode
Expanded Mode (EIM relocated to 0x0, Boot From EIM)
Standard Pierce Oscillator Mode / External Clock Mode
Low Power (ALC) Pierce Oscillator Mode (ALC Circuit rqd)
EBI is configured with 8-bit Port Size out of reset
EBI is configured with 16-bit Port Size out of reset
AutoACK is disabled – TA signal MUST be supplied externally
AutoACK is enabled – EBI will supply TA signal automatically
The Nexus port is mapped to the primary port (PA0..PA6)
The Nexus port is mapped to the secondary port (PE0..PE6) *
The Nexus module is not present and cannot be enabled
The Nexus module is present and debug interface can enable it
Spare
Spare
* See notes in section 2.9 if using this connector.
Note – It is important that the MCU pins shown in Table 2-9 are NOT directly tied to ground or VCC at the user
connectors as this will conflict with and invalidate the reset configuration data.
Switch SW1 is clearly labeled on the EVB with the switch function and also with the position of the switch required to
drive logic 1 or 0. When the switches are in the ON position, this corresponds to logic 0.
ON
1
1
1
1
1
1
1
1
2
3
4
5
6
7
8
MODB
XCLKS
PSIZ
AUTO-TA
NEX-LOC
NEX-EN
0
MODA
1-MODE-0
The figure below shows the default configuration of the switch.
Switch Position for Logic 1
(Turned OFF)
Figure 2-10 Reset Configuration (Mode) Switch
ON
MAC7100EVBUM/D
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MAC7100EVB Users Manual Rev 1.1
November 2004
2.9 JTAG and Nexus Configuration (J13, J18)
The JTAG and NEXUS
connectors are located on the
left hand edge of the EVB.
The EVB has two JTAG connectors supporting both the 14 and 20 pin configurations. There are also two Nexus “mictor”
connector footprints, allowing a Nexus probe to be connected to either of the possible multiplexed pin locations for
Nexus on the MAC7100 family.
There are two generic jumpers associated with both JTAG and Nexus as shown in the tables below.
Table 2-10 JTAG / NEXUS Target Reset Routing Jumper J13
Jumper
J13 (TRST)
Position
1-2 (D)
2-3
PCB Legend
BUFFER
DIRECT
Description
TARGET reset signal is buffered to MCU RESET pin
TARGET reset signal is connected directly to MCU RESET pin
Some JTAG and NEXUS probes have the ability to assert and also monitor the state of the MCU Resetx line. This is not
possible when the reset lines are buffered so jumper J13 is included to route the JTAG / NEXUS target reset signal
directly to the MCU bi-directional reset pin. In order to use this feature, jumper J13 should be moved to position 2-3.
Table 2-11 JTAG / NEXUS TCLK Termination J18
Jumper
J18 (TCLK Term)
Position
1-2 (D)
2-3
PCB Legend
VDDIO
GND
Description
JTAG / NEXUS TCLK signal is pulled to VDDIO via 10KΩ
JTAG / NEXUS TCLK signal is pulled to GND via 10KΩ
Some JTAG / NEXUS debug manufacturers require that the TCLK signal is pulled high and other require it is pulled
low. Jumper J18 allows the user to select between the TCLK signal being pulled high (J18 position 1-2) or Low (J18
position 2-3). Please consult your debug probe manufacturer for details on the correct configuration.
MAC7100EVBUM/D
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MAC7100EVB Users Manual Rev 1.1
2.9.1
November 2004
JTAG Configuration
As mentioned above, the EVB supports both 14 and 20-way JTAG connectors. Either connector can be used without
having to make any EVB jumper configuration changes.
When connecting or removing the JTAG debug interface, power must be removed from both the EVB and the
JTAG debug interface.
P7
2
4
6
8
10
12
14
SPU 1
TRSTx 3
TDI 5
TM 7
TCLK 9
TDO 11
SPU 13
SPU
TRSTx
ICERSTx / SRSTx
VTref
Vsupply
P15
VSS
VSS
VSS
VSS
VSS
ICERSTx
VSS
VTref
TRSTx
TDI
TM
TCLK
1
3
5
7
9
11
TDO 13
SRSTx 15
17
19
2
4
6
8
10
12
14
16
18
20
Vsupply
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
- System Powered UP. Connected to VDDIO via 33Ω Resistor.
- Test Reset. Connected to test pin only, NOT to the MCU reset circuitry
- Target System Reset. Connected to MCU Reset via Buffer (Jumper J13 Selectable)
- Target Reference Voltage. Connected directly to VDDIO
- Power Supply for ARM Embedded ICE probe. Connected to VDDIO
Figure 2-11 JTAG Connectors
2.9.2
Nexus Configuration (J14, J20)
The MAC7100 has a single Nexus 2+ debug module that is multiplexed between two physical locations, PortA and
PortE. The EVB also has a connector fitted in both of these port positions. This allows the user to select which port pins
may be used in order to support Nexus. Whatever port is configured for Nexus, it is important that you do NOT attempt
to use the respective pins for any other purpose!
The following table shows the pins used for each Nexus configuration and details the EVB setup.
Table 2-12 Nexus Connectors
Nexus Port
PortA
PortE
Pins Used by Nexus
PA[0..6]
PE[0..6]
Functionality Lost
PortA / Databus [0..6]
PortE / ADC [0..6]
SW1 “NEX-LOC”
LOW (Switch = ON)
HIGH (Switch = OFF)
EVB Connector Used
P6 – “NEXUS1(PA)”
P16 – “NEXUS2(PE)”
The Nexus module must be made available for use by ensuring that the reset configuration switch (SW7), position 7
“NEX-EN” is high (switch is in OFF position). See section 2.8 for details.
Important Configuration Notes:
PortA Config
When the EVB / MCU is configured to use the primary Nexus port (PortA), the upper byte of the Data
bus, Data[8..15], is available for use. On the EVB however, all of the external memories are configured
for 16-bit port width and will not function correctly when accessed by an 8-bit port. Therefore, the
external memory must be disabled if Nexus is used in the PortA configuration (see section 2.10 for
details). PortA[0..6] should not be connected to any other hardware whilst using this port for Nexus.
PortE Config
When the MCU is configured to use the secondary Nexus port (PortE / ADC), jumper J17 (RV1)
must be removed in order to prevent any contention between resistor RV1 and PortE[0]. PortE[0..6]
should NOT be connected to any other hardware whilst using this port for Nexus.
MAC7100EVBUM/D
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MAC7100EVB Users Manual Rev 1.1
November 2004
When the NEXUS port is enabled, the EVTIx signal must be pulled high to prevent Nexus mode being inadvertently
entered. As the Nexus pins are shared with other MCU port functions, these pull-ups must be selectable so they can be
disabled when the respective port is not being used for Nexus. Jumpers are provided to enable the EVTIx pullup resistor
for each port.
Table 2-13 EVTI Termination Enable Jumpers J14, J20
Jumper
J14 (EVTI Term Nexus 1)
J20 (EVTI Term Nexus 2)
Position
FITTED
REMOVED (D)
FITTED
REMOVED (D)
Description
EVTIx Signal for Primary Nexus port (PA) is pulled high
EVTIx Signal for Primary Nexus port is not terminated
EVTIx Signal for Secondary Nexus port (PA) is pulled high
EVTIx Signal for Secondary Nexus port is not terminated
The default configuration is NO pullup resistor is enabled. It is up to the user to determine what Nexus port will be used.
Note – whenever a Nexus port is not going to be used, the respective EVTIx pullup resistor should be disabled by
removing the relevant jumper.
The following table details the pinout of the Nexus connector. (UBatt is connected to the main EVB power supply line
via a resistor).
Table 2-14. NEXUS Debug Connector Pinout
Pin No
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
MAC7100EVBUM/D
Function
Reserved
Reserved
Vendor I/O-0
Vendor I/O-2
MCU Resetx
TDO
Vendor I/O-4
TCLK
TMS
TDI
MCU TRSTx
Vendor I/O-1
N/C (MDI[3])
N/C (MDI[2])
N/C (MDI[1])
UBATT (VDD IN, 7-12V)
UBATT (VDD IN, 7-12V)
Tool I/O-0
VSTBY (VDD Core)
Pin No
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
Page 16 of 35
Function
Reserved
Reserved
CLKOUT
Vendor I/O-3
EVTIx
VREF (VDD Core)
RDY
N/C (MD0[7])
N/C (MDO[6])
N/C (MDO[5])
N/C (MDO[4])
N/C (MDO[3])
N/C (MDO[2])
MDO[1]
MDO[0]
EVTOx
MCK0
N/C (MSEO1)
MSEO
MAC7100EVB Users Manual Rev 1.1
November 2004
2.10 External Memory Configuration
The External Memory section
is located in the lower right
quarter of the EVB, below the
bank of user connectors.
The following diagram shows the external memory implementation on the EVB.
BUFFERS
MCU
Data
SRAM
(64Kx16)
5V VDD
FLASH
(1Mx16)
5V VDD
Address
Control
Chip
Select
Jumpers
Expansion/
User
Connectors
Write
Protect
Jumpers
Figure 2-12 External Memory Scheme
2.10.1 Buffer Control (J26)
The MAC7111 MCU has a maximum output load capacitance of between 25 and 30pF on the external bus interface
signals. In order not to exceed this loading specification on the EVB, all of the EBI signals to the external SRAM and
FLASH (and Ethernet controller) are buffered. Note that the signals to the expansion connectors and user connectors
remain un-buffered for two reasons:
(1) The EBI signals are multiplexed with bi-directional single chip mode peripherals
(2) The un-buffered interface provides a “true” MCU interface to the user.
Note – If you are interfacing to the EBI via the expansion or user connectors, you must ensure that the loading
capacitance on each of the EBI signals does not exceed the specification, bearing in mind that the EVB buffers used on
the EBI signals already have an input capacitance of approximately 8pF.
When the EVB is used in Single chip mode, the buffers must be disabled otherwise conflicts will occur between
single chip functionality and the buffers. This can be achieved by REMOVING jumper J26 as shown in the table below.
The default configuration enables the buffers, assuming the board will be used in expanded mode.
Table 2-15 EBI Buffer Control Jumper J26
Jumper
J26 (VDD-BUFF)
MAC7100EVBUM/D
Position
FITTED (D)
REMOVED
Description
EBI External Memory Buffers are ENABLED
EBI Buffers are DISABLED (Required in Single Chip Mode)
Page 17 of 35
MAC7100EVB Users Manual Rev 1.1
November 2004
2.10.2 Chip Select Control (J24)
The EVB incorporates a flexible chip select routing scheme as shown below, allowing any of the three MAC7111 chip
selects to be routed to either the RAM or the FLASH. The way the jumper is configured automatically prevents the same
MCU chip select, inadvertently being assigned to both memories. The default configuration is shown. Chip select CS0x
is routed to the external EVB FLASH and Chip select CS1x is routed to the external EVB SRAM. To re-configure the
chip select mapping, please refer to the table below.
CS-ROUTE
1
CS0
4
CS1
CS2
7
FLSH
RAM
Figure 2-13 Chip Select Routing
Table 2-16 Chip Select Jumper J24
Jumper
J24 (CS-Route)
Position
1-2 (D)
2-3
4-5
5-6 (D)
7-8
8-9
Chip Select
CS0x
CS1x
CS2x
Routing
FLASH
RAM
FLASH
RAM
FLASH
RAM
Description
Chip Select CS0x is routed to the EVB FLASH
Chip Select CS0x is routed to the EVB SRAM
Chip Select CS1x is routed to the EVB FLASH
Chip Select CS1x is routed to the EVB SRAM
Chip Select CS2x is routed to the EVB FLASH
Chip Select CS2x is routed to the EVB SRAM
Note – Care should be taken that the MCU Chip selects chosen for FLASH and RAM are not used elsewhere on any
external hardware. The Ethernet controller uses CS2x if enabled (see section 2.11)
MAC7100EVBUM/D
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MAC7100EVB Users Manual Rev 1.1
November 2004
2.10.3 External SRAM Configuration (J35)
The EVB is fitted with a single 64Kx16 asynchronous SRAM giving a total memory space of 128Kbytes. This is
configured as a 16-bit port and as such, the MCU chip select being used for the SRAM must also be configured as a
16-bit port. The SRAM circuitry supports both 8-bit and 16-bit accesses within the 16-bit port. See section 2.10.2 for
details on how to select the desired chip select for SRAM on the EVB.
As this EVB provides a reference design platform, 5V SRAM devices were chosen which, in a standalone design, could
directly interface to the MCU without the requirement for any buffering. In practice, a 3.3V SRAM device could have
been used on the EVB as the buffers provide sufficient drive levels.
If the VDDIO regulator voltage drops below 5V when used in variable voltage mode, the SRAM devices MUST be
disabled or unpredictable operation will occur. Similarly the SRAM must be disabled when the EVB is used in single
chip mode. Jumper J35 provides a mechanism for disabling the SRAM.
Table 2-17 SRAM Power Supply Jumper J35
Jumper
J35 (VDD-SRAM)
Position
FITTED (D)
REMOVED
Description
EVB External SRAM is powered (enabled)
SRAM is disabled. Requirement if S/C mode or VDDIO Variable Mode
Note- The SRAM MUST be disabled if VDDIO is less than 5V or the EVB is used in single chip mode.
Table 2-20 details pin compatible 5V asynchronous SRAM devices that may be used on the EVB.
Table 2-18 SRAM Pin Compatible Devices
Manufacturer
Cypress
IDT
MAC7100EVBUM/D
32K x 16
CYC1020B
N/A
Page 19 of 35
64K x 16
CYC1021B
IDT71016
MAC7100EVB Users Manual Rev 1.1
November 2004
2.10.4 External FLASH Configuration (J31, J33, J34)
The EVB is fitted with a single 1Mx16 asynchronous FLASH memory giving a total memory space of 2Mbytes. This is
configured as a 16-bit port and, like the SRAM, the MCU chip select assigned for the FLASH must also be
configured as a 16-bit port. The FLASH circuitry is only designed to support 16-bit aligned accesses. Any other
access types must be avoided as these will result in incorrect data being read or written to the FLASH memory.
As with the SRAM, a 5V FLASH device has been chosen for use on the EVB. If the VDDIO regulator voltage drops
below 5V when used in variable mode, the FLASH devices MUST be disabled or unpredictable operation will occur. The
FLASH must also be disabled when the EVB is used in single chip mode using jumper J33.
Two additional jumpers provide a hardware mechanism for write protection. J34 controls read / write for the complete
FLASH and J31 provides additional boot block protection (AM29F400B Flash only). By default, the complete FLASH
memory block is un-protected.
Table 2-19 FLASH Control Jumpers
Jumper
J33 (VDD-FLASH)
Flash Write Enable
J31 (BOOT)
J34 (ALL)
Position
FITTED (D)
REMOVED
Description
EVB External FLASH is powered (enabled)
FLASH is disabled. Requirement if S/C mode or VDDIO Variable Mode
FITTED (D)
REMOVED
FITTED (D)
REMOVED
FLASH Boot Block (AM29F400B) is set to read / write
FLASH Boot Block (AM29F400B) can only be read
Complete FLASH is set to read / write (Boot Block Controlled By J31)
Complete FLASH is set to read only
Note – In order for the flash boot block to be written on the AM28F400B device, BOTH jumpers J31 and J34 must be
fitted.
Table 2-20 details pin compatible AMD 5V asynchronous FLASH devices that may be used on the EVB.
Table 2-20 AMD Flash Pin Compatible Devices
Part Number
AM29F160D*
AM29F800B
AM29F400B
Flash Size
16MBit (2M Bytes)
8M Bit (1M Bytes)
4M Bit (512K Bytes)
* Fitted by default
The AMD flash devices provide an easy in-system programming mechanism allowing the flash to be programmed and
erased using commands sent to the flash via the MAC7100 external bus. Many debugger manufacturers provide
automated external flash programming functionality, allowing the user to program the flash without having to manually
control the programming command sequence. Please consult your debugger manufacturer for details.
No additional programming voltage is require to program the external flash however the write enable jumpers J34 (and
if applicable J31) must be fitted before programming can take place.
MAC7100EVBUM/D
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MAC7100EVB Users Manual Rev 1.1
November 2004
2.11 Ethernet Controller Configuration
(Jumpers J36, J37, J38, J39, J40)
The Ethernet controller circuitry is
located in the bottom right area of the
EVB. The Control jumpers are located
in a box titled “ETHERNET”
There is a memory mapped Ethernet controller on the EVB, configured as shown in the block diagram below.
MAC7111
MCU
Control
Address
BUFFERS
GAL22V10
SMSC
ETHERNET
RJ45
ISOLATION
TRANSFORMER
Data
Figure 2-14 Ethernet Controller Block Diagram
The Ethernet controller used on the EVB is an SMSC LAN91C111-NE (Full Duplex, 10/100Mbit) device, configured for
asynchronous bus mode in order to be compatible with the MAC7111 external bus. The MAC7111 cannot interface
directly to the Ethernet controller as the control signals are generally active high on the Ethernet controller but active low
on the MCU. In addition, some of the Ethernet controller signals are generated from multiple MCU signals. The
GAL22V10 PLD (programmable logic device) is used to provide this MCU / Ethernet controller interface. The PLD also
provides an input from the Target TAx signal, asserting the MCU TAx line whenever the Target TA or Ethernet TA
signals are asserted.
Note - the Address / Data and Control signals to the Ethernet controller (and PLD) are buffered using the same set of
buffers used for the external SRAM and FLASH detailed in section 2.10.1. These buffers must therefore be enabled (and
the MCU running in expanded mode) before the Ethernet controller can be used.
The Ethernet controller and PLD are powered from the 3.3V EVB supply and as such, the 3.3V regulator must be
enabled for the Ethernet controller circuitry to work.
There are 5 jumpers associated with the Ethernet circuitry as shown in Table 2-21 below. Jumper J36 is used to apply
power to the Ethernet controller. When the MCU is used in single chip mode, or the Ethernet controller is not required,
this jumper should be removed. Jumper J37 and J38 are used to connect the MCU IRQx and MCU TAx signals to the
PLD. Again, if the Ethernet controller is required, these jumpers must be fitted. Note that the PLD has these pins
configured as open-drain output. Jumper J39 is used to apply power to the PLD and jumper J40 is used to connect the
MCU chip select CS2 to the PLD which in turn is used to control the Ethernet Controller (as before, both these jumpers
must be fitted for the Ethernet controller to function).
MAC7100EVBUM/D
Page 21 of 35
MAC7100EVB Users Manual Rev 1.1
November 2004
Table 2-21 Ethernet Circuit Control Jumpers
Jumper
J36 (VDD-ENET)
J37 (IRQx)
J38 (TAx)
J39 (VDD-PLD)
J40 (CS2x)
Position
FITTED (D)
REMOVED
FITTED (D)
REMOVED
FITTED (D)
REMOVED
FITTED (D)
REMOVED
FITTED (D)
REMOVED
Description
Ethernet Controller is powered (enabled)
Ethernet Controller is disabled – Requirement in Single Chip mode
Ethernet Controller IRQ signal is connected to MCU IRQx line
Ethernet Controller IRQ signal is NOT connected to MCU IRQx line
Ethernet Controller and Target TA signals connected to MCU TAx line
Ethernet Controller and Target TA signals NOT connected to MCU TAx line
GAL22V10 is enabled (required if Ethernet controller or target TA required)
GAL22V10 is disabled (Target TA or Ethernet controller will not function)
MCU Chip Select CS2x is routed to the Ethernet Controller via the GAL22V10
MCU Chip Select CS2x is NOT connected to the Ethernet controller.
By default, the Ethernet controller circuit is fully enabled with all the jumpers shown in Table 2-21 fitted.
Notes:
- Care should be taken to ensure that MCU Chip Select CS2x is not used for any other purpose if the Ethernet
controller is used.
- The EVB buffers must be enabled in order to use the Ethernet controller.
- If the MCU is used in single chip mode, the Ethernet controller should be disabled.
MAC7100EVBUM/D
Page 22 of 35
MAC7100EVB Users Manual Rev 1.1
November 2004
2.12 CAN Configuration (J2, J3, J4)
The CAN section is located at the top
right hand edge of the EVB in an area
marked “CAN”.
The EVB has a Philips PCA82C250T high speed physical CAN interface driver on the MCU CAN-A and CAN-B
channels. These are pre-configured for high speed operation by tying Pin8 of each CAN transceiver to ground via a zero
ohm resistor. If required, these resistors can be changed to provide slope control mode of operation. See the EVB
schematics for details.
Each CAN transceiver circuit has its CAN bus signals routed to a standard 0.1” connector at the top edge of the EVB.
Connector P1 provides the CAN bus level signal interface for CAN-A and connector P2 for CAN-B. The pinout of these
connectors is detailed below. Care should be taken NOT to confuse these connectors with jumper headers!
1
HI
LOW GND
Figure 2-15 CAN Physical Interface Connector
Each of the MCU signals to the CAN transceivers is jumpered, allowing the CAN transceiver to be isolated if that MCU
port is not configured or used for CAN operation. There is a 2x2 jumper for each CAN channel as shown in the table
below. In addition, there is a global CAN power jumper (J3) which is used to completely remove power from both CAN
transceivers.
Table 2-22 CAN Control Jumpers
Jumper
J2 (CAN-A) Posn 1-2
Legend
TX
J2 (CAN-A) Posn 3-4
RX
J4 (CAN-B) Posn 1-2
TX
J4 (CAN-B) Posn 3-4
RX
J3 (VDD-CAN)
Position
FITTED (D)
REMOVED
FITTED (D)
REMOVED
FITTED (D)
REMOVED
FITTED (D)
REMOVED
FITTED (D)
REMOVED
Description
MCU CNTX-A is connected to CAN controller A
MCU CNTX-A is NOT routed to CAN controller .
MCU CNRX-A is connected to CAN controller A
MCU CNRX-A is NOT routed to CAN controller.
MCU CNTX-B is connected to CAN controller B
MCU CNTX-B is NOT routed to CAN controller .
MCU CNRX-B is connected to CAN controller B
MCU CNRX-B is NOT routed to CAN controller.
Power is applied to both CAN transceivers
No power is applied to CAN transceivers
The default position is all jumpers fitted, connecting the MCU CAN A and CAN B signals to the CAN physical interface.
If the MCU is configured such that a CAN channel is configured as a normal I/O port (eg PortG 4,5 for CAN-A), the
respective jumpers must be removed or conflicts will occur. If neither CAN channel is being used, Jumper J3 should be
removed to disable both CAN transceivers.
Notes:
− The Philips CAN devices fitted to the EVB will only function with VDDIO connected to 5V. If the EVB is used in
variable VDDIO mode, the CAN devices MUST be disabled using jumper J3.
− Care should be taken when fitting jumpers to the 2x2 headers as they can easily be fitted in the incorrect
orientation. Jumper headers on J2 and J4 are fitted vertically.
MAC7100EVBUM/D
Page 23 of 35
MAC7100EVB Users Manual Rev 1.1
November 2004
2.13 RS232 Configuration (J5, J6, J9)
The RS232 circuitry is located in the
top centre edge of the EVB in an area
titled “SCI”.
The EVB has a single MAX232CSE RS232 transceiver device, providing RS232 signal translation for the MCU SCI
channels A and B.
Each of the two RS232 outputs from the MAX232 device is connected to a 9-way female D-Type connector, allowing a
direct RS232 connection to a PC or terminal. Connector P3 provides the RS232 level interface for MCU SCI-A and P4
for MCU SCI-B. The pinout of these connectors is detailed below. Note that hardware flow control is not supported on
this implementation.
Figure 2-16 RS232 Physical Interface Connector
As with the CAN circuitry, each of the MCU signals to the RS232 transceiver is jumpered to allow individual isolation if
required. There is also a global power jumper J5 controlling the power supply to the RS232 transceiver. This is shown in
Table 2-23 below.
Table 2-23 RS232 Control Jumpers
Jumper
J6 (SCI-A) Posn 1-2
Legend
TX
J6 (SCI-A) Posn 3-4
RX
J9 (SCI-B) Posn 1-2
TX
J9 (SCI-B) Posn 3-4
RX
J5 (VDD-SCI)
Position
FITTED (D)
REMOVED
FITTED (D)
REMOVED
FITTED (D)
REMOVED
FITTED (D)
REMOVED
FITTED (D)
REMOVED
Description
MCU TXD-A is routed via MAX232 to P3
MCU TXD-A signal is not connected to MAX232
MCU RXD-A is routed via MAX232 to P3
MCU RXD-A signal is not connected to MAX232
MCU TXD-B is routed via MAX232 to P4
MCU TXD-B signal is not connected to MAX232
MCU RXD-B is routed via MAX232 to P4
MCU RXD-B signal is not connected to MAX232
Power is applied to the MAX232 transceiver
No power is applied to the MAX232 transceiver
The default configuration is all jumpers fitted, connecting the MCU SCI- A and SCI-B signals to the physical RS232
connectors via the MAX232 device. If the MCU is configured such that SCI channel A or B is set as a normal I/O port,
the respective jumpers must be removed from J6 or J9 or conflicts will occur. If neither channel is being used as an SCI,
jumper J5 should be removed to disable the MAX232 transceiver device.
Notes:
− The MAC232 device fitted to the EVB will only function with VDDIO connected to 5V. If the EVB is used in
variable VDDIO mode, the MAX232 device MUST be disabled using jumper J5.
− Care should be taken when fitting jumpers to the 2x2 headers as they can easily be fitted in the incorrect
orientation. Jumper headers on J6 and J9 are fitted vertically.
MAC7100EVBUM/D
Page 24 of 35
MAC7100EVB Users Manual Rev 1.1
November 2004
2.14 Termination Resistor Control (J28)
The Termination control jumper is
located to the bottom right of the
MCU and MCU SUPPLY jumpers.
In expanded mode, the MCU EBI control signals must be pulled high. When the EVB is used in single chip mode
however, you may require the respective port pins to be left floating with the external pullup resistors disabled. Jumper
J28 controls the power to these pullup resistors. When the jumper is removed, the pullup resistors are no longer activated.
Table 2-24 EBI Pullup Resistor Control (J29)
Jumper
J28 (Exp-Mode Term)
Position
FITTED (D)
REMOVED
Description
EVB EBI signals are pulled high (Expanded Mode)
EBI signals are not pulled high (single Chip Mode)
The MCU TA jumper is
located close to the
bottom right hand
corner of the MCU.
2.15 MCU TA Jumper (J25)
Jumper J25 is used for test purposes only and should remain in position 1-2 for normal operation. Moving this jumper
will cause operational issues with the MCU in expanded mode.
Table 2-25 Jumper J25
Jumper
J25 (TAx)
MAC7100EVBUM/D
Position
1-2 (D)
2-3
PCB Legend
MAC 711
Description
MCU TAx signal is connected
TEST PURPOSES ONLY – DO NOT USE
Page 25 of 35
MAC7100EVB Users Manual Rev 1.1
November 2004
3. Default Jumper Summary Table
The following table details the DEFAULT jumper configuration of the EVB as explained in detail in section 2.
Table 3-1 Default Jumper Positions
Jumper
J1 (ABORT)
J2 (CAN-A) Posn 1-2
Posn 3-4
J3 (VDD-CAN)
J4 (CAN-B) Posn 1-2
Posn 3-4
J5 (VDD-SCI)
J6 (SCI-A) Posn 1-2
Posn 3-4
J7 (VRL)
J8 (VRH)
J9 (SCI-B) Posn 1-2
Posn 3-4
J10 (LVI Reset)
J11 (VDDIO)
J12 (3.3V)
J13 (TRST)
J14 (EVTI Term Nex1)
J15 (I/O)
J16 (PF-LED)
J17 (RV1)
J18 (TCLK Term)
J19 (ADC)
J20 (EVTI Term Nex2)
J21 (REG)
J22 (2.5V)
J23 (Y2 PWR)
J24 (CS-Route)
J25 (TAx)
J26 (VDD-BUFF)
J27 (PLL)
J28 (Exp-Mode Term)
J29 (EXTAL)
J30 (XTAL)
J31 (BOOT)
J32 (OSC SEL)
J33 (VDD-FLASH)
J34 (ALL)
J35 (VDD-SRAM)
J36 (VDD-ENET)
J37 (IRQx)
J38 (TAx)
J39 (VDD-PLD)
J40 (CS2x)
J41 (2.5V)
J42 (3.3V)
J43 (VDDIO)
J44 (PD2-EN)
J45 (PLL-DIS)
MAC7100EVBUM/D
Position
FITTED (D)
FITTED (D)
FITTED (D)
FITTED (D)
FITTED (D)
FITTED (D)
FITTED (D)
FITTED (D)
FITTED (D)
1-2 (D)
1-2 (D)
FITTED (D)
FITTED (D)
FITTED (D)
1-2 (D)
1-2 (D)
1-2 (D)
REMOVED (D)
FITTED (D)
ALL FITTED (D)
FITTED (D)
1-2 (D)
FITTED (D)
REMOVED (D)
1-2 (D)
REMOVED (D)
REMOVED (D)
1-2 (D)
5-6 (D)
1-2 (D)
FITTED (D)
REMOVED (D)
FITTED (D)
1-2 (D)
FITTED (D)
FITTED (D)
1-2 (D)
FITTED (D)
FITTED (D)
FITTED (D)
FITTED (D)
FITTED (D)
FITTED (D)
FITTED (D)
FITTED (D)
1-2 (D)
1-2 (D)
1-2 (D)
REMOVED (D)
REMOVED (D)
PCB Legend
TX
RX
TX
RX
TX
RX
EVB
EVB
TX
RX
ENABLE
ENABLE
BUFFER
VDDIO
CS0 / FLSH
CS1 / RAM
MAC 711
Y1
Y2
ENABLE
ENABLE
5V
Description
ABORT switch is connected to MCU XIRQ line
MCU CNTX-A is connected to CAN controller A
MCU CNRX-A is connected to CAN controller A
Power is applied to both CAN transceivers
MCU CNTX-B is connected to CAN controller B
MCU CNRX-B is connected to CAN controller B
Power is applied to the MAX232 transceiver
MCU TXD-A is routed via MAX232 to P3
MCU RXD-A is routed via MAX232 to P3
MCU VRL is connected to EVB analogue GND
MCU VRH is connected to EVB VDDIO
MCU TXD-B is routed via MAX232 to P4
MCU RXD-B is routed via MAX232 to P4
RESET signal from LVI drives the MCU RESET line
VDDIO regulator output is monitored by LVI
3.3V regulator output is monitored by LVI
JTAG Target Reset signal is buffered to MCU RESET pin
EVTI Signal for Primary Nexus port is not terminated
Connects EVB VDDIO regulator output to MCU VDDX pins
Connects PF[8..15] to LED’s DS[2..9]
Output from RV1 is applied to MCU PE0 / AN00 pin
JTAG / NEXUS TCLK signal is pulled to VDDIO via 10KΩ
Connects EVB VDDIO regulator output to MCU VDDA pins
EVTI Signal for Secondary Nexus port is not terminated
Connects EVB VDDIO regulator output to MCU VDDR pins
MCU On Chip regulator powers VDD2.5
Oscillator Module Y1 is not powered (disabled)
Chip Select CS0x is routed to the EVB FLASH
Chip Select CS1x is routed to the EVB SRAM
MCU TAx signal is connected (Do not move this jumper)
EBI External Memory Buffers are ENABLED
MCU On Chip regulator powers VDDPLL
EVB EBI signals are pulled high (Expanded Mode)
MCU EXTAL connected to local oscillator circuit
MCU XTAL connected to local oscillator circuit
External FLASH Boot Block (AM29F400B) set to read / write
External EXTAL routed from Oscillator Module
EVB External FLASH is powered (enabled)
Complete External FLASH is set to read / write
EVB External SRAM is powered (enabled)
Ethernet Controller is powered (enabled)
Ethernet Controller IRQ signal is connected to MCU IRQx line
Ethernet Controller and Target TA signals connected to MCU TAx
GAL22V10 PLD is enabled
MCU Chip Select CS2x is connected to the Ethernet Controller
2.5V regulator output is Enabled
3.3V regulator output is Enabled
VDDIO regulator is configured as 5.0V fixed mode.
CLKOUT Impedance matching resistor is active
MCU PLL Circuitry is enabled
Page 26 of 35
MAC7100EVB Users Manual Rev 1.1
November 2004
4. Jumper Configurations for EVB Operating Mode
This table details specific jumper positioning requirements for various EVB operating configurations / modes.
Note - Where “Any” is written in the table, this means the jumper can be configured as required by the user. It does NOT
infer that the EVB will function correctly with the jumper in any position.
Table 4-1 Critical Jumper Positions
Jumper
J1 (ABORT)
J2 (CAN-A)
J3 (VDD-CAN)
J4 (CAN-B)
J5 (VDD-SCI)
J6 (SCI-A)
J7 (VRL)
J8 (VRH)
J9 (SCI-B)
J10 (LVI Reset)
J11 (VDDIO)
J12 (3.3V)
J13 (TRST)
J14 (EVTI Term Nex1)
J15 (I/O)
J16 (PF-LED)
J17 (RV1)
J18 (TCLK Term)
J19 (ADC)
J20 (EVTI Term Nex2)
J21 (REG)
J22 (2.5V)
J23 (Y2 PWR)
J24 (CS-Route)
J25 (TAx)
J26 (VDD-BUFF)
J27 (PLL)
J28 (Exp-Mode Term)
J29 (EXTAL)
J30 (XTAL)
J31 (BOOT)
J32 (OSC SEL)
J33 (VDD-FLASH)
J34 (ALL)
J35 (VDD-SRAM)
J36 (VDD-ENET)
J37 (IRQx)
J38 (TAx)
J39 (VDD-PLD)
J40 (CS2x)
J41 (2.5V)
J42 (3.3V)
J43 (VDDIO)
J44 (PD2-EN)
J45 (PLL-DIS)
MAC7100EVBUM/D
Single Chip
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
REMOVED
1-2
REMOVED
Any
REMOVED
Any
Any
Any
Any
REMOVED
Any
REMOVED
REMOVED
REMOVED
REMOVED
REMOVED
REMOVED
Any
Any
Any
Any
Any
Expanded
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
1-2
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Page 27 of 35
VDDIO=5v
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
1-2
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
VDDIO<5v
Any
REMOVED
REMOVED
REMOVED
REMOVED
REMOVED
Any
Any
REMOVED
Any
2-3
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
REMOVED
1-2
Any
Any
Any
Any
Any
Any
Any
REMOVED
Any
REMOVED
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
MAC7100EVB Users Manual Rev 1.1
November 2004
5. User Connector Descriptions
The User connectors are grouped
together in the right hand middle
section of the EVB.
.
This section details the pinout for the user connectors on the EVB. All of the user connectors are located to the right of
the MCU and are all 0.1 inch pitch headers. Pins are grouped by Port functionality and the PCB legend clearly shows the
single chip port number adjacent to each header pin.
5.1 Port A / DataBus (P12)
Table 5-1 Connector P12 – PortA / Databus
Pin No
1*
3*
5*
7*
9
11
13
15
17
PCB
Legend
0
2
4
6
8
10
12
14
GND
Pin Function
Pin No
PA0 / DATA0 *
PA2 / DATA2 *
PA4 / DATA4 *
PA6 / DATA6 *
PA8 / DATA8
PA10 / DATA10
PA12 / DATA12
PA14 / DATA14 / EIMPS
GND
2*
4*
6*
8
10
12
14
16
18
PCB
Legend
1
3
5
7
9
11
13
15
GND
Pin Function
PA1 / DATA1 *
PA3 / DATA3 *
PA5 / DATA5 *
PA7 / DATA7
PA9 / DATA9
PA11 / DATA11
PA13 / DATA13
PA15 / DATA15 / EIMACK
GND
Notes:
- If the EVB is used in expanded mode, the only connection to these pins should be for test / measurement
equipment or for external bus interface purposes.
- * Indicates pin shared with Primary Nexus location. If this Nexus option is used, this pin must NOT be loaded.
Nexus tools should ONLY be connected at the appropriate NEXUS Mictor connector, not at this header.
- Pins 14 and 15 (MCU Pins PA14, PA15) are used by the EVB reset configuration logic to determine the MCU
EIM reset configuration. These pins must NOT be tied to power or ground OR pulled high or low using
aggressive pullup / pulldown resistors.
5.2 Port B / I2C / SPI (P10)
Table 5-2 Connector P10 – PortB / I2C / SPI
Pin No
1
3
5
7
9
11
13
15
17
MAC7100EVBUM/D
PCB
Legend
0
2
4
6
8
10
12
14
GND
Pin Function
PB0 / SDA
PB2 / SIN-A
PB4 / SCK-A
PB6 / PCS1-A
PB8 / PCSS-A
PB10 / PCSS-B
PB12 / PCS1-B
PB14 / SOUT-B
GND
Pin No
2
4
6
8
10
12
14
16
18
Page 28 of 35
PCB
Legend
1
3
5
7
9
11
13
15
GND
Pin Function
PB1 / SCK
PB3 / SOUT-A
PB5 / SS-A
PB7 / PCS2-A
PB9 / SS-B
PB11 / PCS2-B
PB13 / SCK-B
PB15 / SIN-B
GND
MAC7100EVB Users Manual Rev 1.1
November 2004
5.3 Port C / Address [0..15] (P13)
Table 5-3 Connector P13 – Port C / Address
Pin No
1
3
5
7
9
11
13
15
17
PCB
Legend
0
2
4
6
8
10
12
14
GND
Pin Function
PC0 / ADDR0
PC2 / ADDR2
PC4 / ADDR4
PC6 / ADDR6
PC8 / ADDR8
PC10 / ADDR10
PC12 / ADDR12
PC14 / ADDR14
GND
Pin No
2
4
6
8
10
12
14
16
18
PCB
Legend
1
3
5
7
9
11
13
15
GND
Pin Function
PC1 / ADDR1
PC3 / ADDR3
PC5 / ADDR5
PC7 / ADDR7
PC9 / ADDR9
PC11 / ADDR11
PC13 / ADDR13
PC15 / ADDR15
GND
Note – If the EVB is used in expanded mode, the only connection to these pins should be for test / measurement
equipment or for external bus interface purposes
5.4 Port D / Address [16..21] / Control (P14 and J44)
Table 5-4 Connector P14 – Port D / Address / Control
Pin No
1
3
5
7
9
11
13
15
17
19
21
PCB
Legend
0
CLKOUT
4
6
8
10
12
14
RST-IN
MCU-TA
GND
Pin Function
Pin No
PD0 / BS0x / MODB
CLKOUT / XCLKSx
PD4 / IRQx
PD6 / ADDR17
PD8 / ADDR19
PD10 / ADDR21
PD12 / CS2x
PD14 / CS0x
Target RESET-INx *
MCU TAx **
GND
2
4
6
8
10
12
14
16
18
20
22
PCB
Legend
1
3
5
7
9
11
13
15
RST-OUT
TGT-TA
GND
Pin Function
PD1 / BS1x / MODA
PD3 / XIRQx
PD5 / ADDR16
PD7 / ADDR18
PD9 / ADDR20
PD11 / OEx
PD13 / CS1x
PD15 / RWx
MCU Reset-OUTx *2
Target TAx **
GND
Notes:
-
If the EVB is used in expanded mode, the only connection to the ADDRESS / Control pins should be for test /
measurement equipment or for external bus interface purposes.
Pins 1,2 and 3 (MCU Pins PD0, PD1 and PD2) are used by the EVB reset configuration logic to determine the
operating mode of the MCU. These pins must NOT be tied to power or ground OR pulled high or low using
aggressive pullup / pulldown resistors.
* RST-INx (pin 17) is connected to the Reset Buffering Input. RST-OUTx (Pin 18) is the buffered MCU reset
signal. See section 2.7 for details.
** MCU-TAx (Pin 19) is connected directly to the MCU TAx pin. This must be driven with an open-drain output
only. TGT-TAx (Pin 20) is connected to the GAL22V10 and provides a non-open drain TA input. For TGT-TAx
to function, the GAL22V10 must be configured as described in section 2.11.
MAC7100EVBUM/D
Page 29 of 35
MAC7100EVB Users Manual Rev 1.1
5.4.1
November 2004
PD2 / CLKOUT impedance matching control (J44)
The MCU PD2/CLKOUT line has a series 33Ω resistor close to the MCU for CLKOUT impedance matching. If
required, this resistor can be bypassed using jumper J44. The default position of this jumper is shown in the table below,
with the jumper removed allowing impedance matching.
Table 5-5 PD2 / CLKOUT Termination Bypass Jumper
Jumper
J44 (PD2-EN)
Position
FITTED
REMOVED (D)
Description
CLKOUT Impedance matching resistor is bypassed
CLKOUT Impedance matching resistor is active
5.5 Port E / ADC and Analogue Reference (P11 and J17)
Table 5-6 Connector P11 – Port E / ADC
Pin No
1
3
5
7
9
11
13
15
17
19
Notes
-
PCB
Legend
0
2
4
6
8
10
12
14
VRH
GND
Pin Function
PE0 / AN000 *
PE2 / AN002 *
PE4 / AN004 *
PE6 /AN006 *
PE8 /AN008
PE10 / AN010
PE12 / AN012
PE14 / AN014
USR-VRH **
GND
Pin No
2
4
6
8
10
12
14
16
18
20
PCB
Legend
1
3
5
7
9
11
13
15
VRL
GND
Pin Function
PE1 / AN001 *
PE3 / AN003 *
PE5 / AN005 *
PE7 / AN007
PE9 / AN009
PE11 / AN011
PE13 / AN013
PE15 / AN015
USR-VRL **
GND
* Pin shared with Secondary Nexus Location. If this Nexus option is used, this pin must NOT be loaded. Nexus
tools should ONLY be connected at the appropriate NEXUS Mictor connector, not at this header.
** Pin 17 (VRH) and Pin 18 (VRL) provide a convenient point for the user to input high and low reference
voltages for the ADC assuming that the ADC control jumpers are configured appropriately. See section 2.3
for details.
To allow easy user evaluation of the ADC and to perform some simple tests, a 2K Ohm variable resistor (RV1) is
provided which provides a voltage of between 0V and VDDIO onto ADC channel 0 (PE0). Jumper J17 can be used to
disconnect this variable resistor if it is not required (or if PortE is to be used as a normal I/O Port). J11 and RV1 are
located adjacent to connector P11.
Table 5-7 RV1 Connection Jumper J17
Jumper
J17 (RV1)
MAC7100EVBUM/D
Position
FITTED (D)
REMOVED
Description
Output from variable resistor RV1 is applied to MCU PE0 / AN00 pin
Output from RV1 is not connected to MCU (disabled)
Page 30 of 35
MAC7100EVB Users Manual Rev 1.1
November 2004
5.6 Port F / EMIOS And User LED’S (P9, J16)
Table 5-8 Connector P9 – Port F / EMIOS
Pin No
1
3
5
7
9
11
13
15
17
PCB
Legend
0
2
4
6
8
10
12
14
GND
Pin Function
Pin No
PF0 / EMIOS0 / NEX-PS
PF2 / EMIOS 2
PF4 / EMIOS 4
PF6 / EMIOS 6
PF8 / EMIOS 8
PF10 / EMIOS 10
PF12 / EMIOS 12
PF14 / EMIOS 14
GND
2
4
6
8
10
12
14
16
18
PCB
Legend
1
3
5
7
9
11
13
15
GND
Pin Function
PF1 / EMIOS 1 / NEX-EN
PF3 / EMIOS 3
PF5 / EMIOS 5
PF7 / EMIOS 7
PF9 / EMIOS 9
PF11 / EMIOS 11
PF13 / EMIOS 13
PF15 / EMIOS 15
GND
Note - Pins 1 and 2 (MCU Pins PF0 and PF1) are used by the EVB reset configuration logic to determine the operating
mode of the MCU. These pins must NOT be tied to power or ground OR pulled high or low using aggressive pullup /
pulldown resistors.
8 LED’s are provided to allow test and evaluation. These are connected to the upper byte of Port F (bits [8..15]). A
jumper header (J16) is supplied to allow disconnection of these LED’s if not required as shown in the diagram below. By
default, all the jumpers are fitted.
J16
PF8
DS2
PF9
DS3
PF10
DS4
PF11
DS5
PF12
DS6
PF13
DS7
PF14
DS8
PF15
DS9
PF-LED
LED’S
Figure 5-1 J16 and User LED control
Note – These LED’s are ACTIVE low. A logic 0 must be driven out of the relevant port in order to illuminate the LED.
They are connected via a resistor to VDDIO so if VDDIO is lowered (in variable voltage mode), the LED’s will also get
correspondingly dimmer.
MAC7100EVBUM/D
Page 31 of 35
MAC7100EVB Users Manual Rev 1.1
November 2004
5.7 Port G / CAN / SCI (P8)
Table 5-9 Connector P8 – Port G / CAN / SCI
Pin No
1
3
5
7
9
11
13
15
17
PCB
Legend
0
2
4
6
8
10
12
14
GND
Pin Function
PG0 / RXD-B
PG2 / RXD-A
PG4 / CNTX-A
PG6 / CNTX-B
PG8 / CNTX-C
PG10 / CNTX-D
PG12 / RXD-D
PG14 / RXD-C
GND
Pin No
2
4
6
8
10
12
14
16
18
PCB
Legend
1
3
5
7
9
11
13
15
GND
Pin Function
PG1 / TXD-B
PG3 / TXD-A
PG5 / CNRX-A
PG7 / CNRX-B
PG9 / CNRX-C
PG11 / CNRX-D
PG13 / TXD-D
PG15 / TXD-C
GND
Notes:
- The signals at connector P8 are MCU-LEVEL. For physical interface for SCI or CAN, please see sections 2.12
and 2.13
- When the Can or SCI physical interfaces are being used, the corresponding MCU level signal on connector P8
MUST be left unconnected or conflicts will occur.
MAC7100EVBUM/D
Page 32 of 35
MAC7100EVB Users Manual Rev 1.1
November 2004
6. Expansion Connectors
The Expansion
connectors are
located above and
below the MCU.
Two 120-way expansion connectors are fitted to the EVB, allowing connection of an MCU daughter-card or other board
providing functionality enhancement. The pinout of these connectors is detailed below for reference.
All of the MCU power signals are routed to the expansion connectors after they have passed through the MCU supply
isolation jumpers, thus allowing isolation of power supply lines to the daughter-card if required. Note the output from the
3.3V regulator is not jumpered.
The part numbers of possible connectors are detailed in Table 6-1 below.
Table 6-1 Expansion Connector Part Numbers
Connector Location
EVB
Daughter Card
Height
8mm
9mm
13mm
Pitch
0.8mm
0.8mm
0.8mm
AMP Part Number
179031-5
5-179009-5
5-179010-5
Table 6-2 Expansion Connector 1 (P5)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
VDD3.3
PC3 / ADDR3
PC2 / ADDR2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
VDDI/O
GND
PC1 / ADDR1
PC0 / ADDR0
VDDI/O
PG6 / CNTX-B
PG11 / CNRX-D
GND
PG9 / CNRX-C
PG8 / CNTX-C
VDDI/O
PG4 / CNTX-A
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
PD7 / ADD18
PE15 / AN15
PE14 / AN14
PE13 / AN13
GND
PE11 / AN11
MCU-VRL
USR-VRH
USR-VRL
VDDA
GND
PE9 / AN09
PE7 / AN07
VDD3.3
PE5 / AN05
PE3 / AN03
GND
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
PD6 / ADD17
GND
GND
PG7 / CNRX-B
VDD3.3
PG10 / CNTX-D
GND
PG5 / CNRX-A
PG3 / TXD-A
PG2 / RXD-A
PG1 / TXD-B
GND
PG14 / RXD-C
VDD3.3
PA2 / DATA2
PA4 / DATA4
GND
TM
TDO
PD10 / ADD21
GND
PD8 / ADD19
GND
PG0 / RXD-B
PG15 / TXD-C
VDDI/O
PA0 / DATA0
PA1 / DATA1
GND
PA3 / DATA3
PA5 / DATA5
VDDI/O
PA6 / DATA6
TCLK
GND
TDI
PD9 / ADD20
VDD2.5
PE0 / AN00
PA8 / DATA8
PA10 / DATA10
GND
PD5 / ADDR16
VDD3.3
PC13 / ADDR13
GND
GND
PE12 / AN12
VDD2.5
PE10 / AN10
MCU-VRH
GND
VDDA
VDDA
VDD2.5
PE8 / AN08
PE6 / AN06
GND
PE4 / AN04
PE2 / AN02
VDD2.5
PE1 / AN01
PA7 / DATA7
GND
PA9 / DATA9
PA11 / DATA11
VDD2.5
PA12 / DATA12
PC15 / ADDR15
GND
PC14 / ADDR14
PC12 / ADDR12
GND
GND
Note: MCU-VRH and MCU-VRL are connected directly to the respective MCU pins. USR-VRH and USR-VRL are routed
to pin 3 of the ADC selection jumpers J7 and J8.
MAC7100EVBUM/D
Page 33 of 35
MAC7100EVB Users Manual Rev 1.1
November 2004
Table 6-3 Expansion Connector 2 (P19)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
VDD3.3
PB0 / SDA
PB1 / SCL
PB3 / SOUT-A
GND
PB4 / SCK-A
PB6 / PCS1-A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
VDD2.5
GND
PB2 / SIN-A
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
PG12 / RXD-D
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
PG13 / TXD-D
GND
VDDR
VDDR
VDDI/O
RESET-OUTx
VDDPLL
GND
PB8 / PCS5-A
PF14 / EMIOS14
GND
PC4 / ADDR4
VDD3.3
PC6 / ADDR6
PC7 / ADDR7
GND
PF10 / EMIOS10
PF7 / EMIOS7
PF6 / EMIOS6
GND
PF3 / EMIOS3
PF1 / EMIOS1
VDD3.3
PC8 / ADDR8
PC10 / ADDR10
GND
PC11 / ADDR11
VDD2.5
PB5 / PCS0-A
PB7 / PCS2-A
GND
PF15 / EMIOS15
PF13 / EMIOS13
VDD2.5
MTS12/PF12
PC5 / ADDR5
GND
PF11 / EMIOS11
VDD2.5
PF9 / EMIOS9
PF8 / EMIOS8
GND
PF5 / EMIOS5
PF4 / EMIOS4
VDD2.5
PF2 / EMIOS2
PF0 / EMIOS0
GND
PC9 / ADDR9
TGT-RESETx
VDDI/O
MCU-RESETx
VDDR
VDDR
GND
VDDPLL
VDDPLL
EXT-EXTAL
PA15 / DATA15
GND
PA14 / DATA14
PD11 / OEx
PD1 / BS1x
GND
PB10 / PCS5-B
PB11 / PCS2-B
VDD3.3
PB13 / SCK-B
GND
TA
PD3 / XIRQx
VDD3.3
PD4 / IRQx
PD14 / CS0x
GND
GND
VDDI/O
PA13 / DATA13
PD12 / CS2x
GND
PD0 / BS0x
PB9 / PCS0-B
VDDI/O
PB12 / PCS1-B
GND
PB14 / SOUT-B
PB15 / SIN-B
VDDI/O
CLKOUT
TGT-TAx
GND
PD13 / CS1x
PD15 / RW
GND
GND
6.1 Use of MCU adapter boards
If the EVB is to be used with an MCU adapter board, in order to provide support for packages other than 144QFP, there
are a few points that you need to bear in mind when using the EVB in this configuration.
(1) The 144 QFP MCU on the EVB must not be fitted if an MCU adapter board is to be used. Otherwise, both
MCU’s will be addressing the same peripherals and external bus (if used). This will result in probable damage to
the EVB and MCUs.
(2) The local clock circuitry on the EVB will not be used by the MCU adapter board (Pierce crystal oscillator circuit
and PLL loop filter) as this will be implemented on the adapter board. Therefore, EVB jumpers J2, J3 and J4
will have no function.
(3) Jumper J44 on the EVB is unused as Clkout impedance matching must be carried out as close to the MCU pin as
possible.
All other jumpers and EVB configuration / features remain unchanged.
Note – The exact functionality of the EVB when used with an MCU adapter board will also depend on the functionality
available on the MCU fitted to the adapter board. Many of these devices will not have an external bus for example.
MAC7100EVBUM/D
Page 34 of 35
MAC7100EVB Users Manual Rev 1.1
November 2004
7. Prototype Area
The prototype area
is located in the top
right section of the
EVB.
A small prototyping area is included on the EVB, consisting of a 0.1” grid array. Power from all three regulators and
ground pins are available at the bottom of the prototype area and are clearly marked.
Note the power supply lines to the prototype area are connected directly to the regulator outputs and not connected to
the jumpered MCU supply.
MAC7100EVBUM/D
Page 35 of 35
MAC7100EVB Users Manual Rev 1.1
November 2004
Appendix A - Bill Of Materials
Part Number
Item
Qty
Ref Des
Value
Function
0
1
N/A
PCB RE11505F Rev O
Bare Printed Circuit Board, Revision O
RE11505F Rev O
1
1
C33
1000uF
Aluminium electrolytic Capacitor, 50V
Panasonic ECA-1VM102
AVX CM316X7R105K16AT
2
5
C8 C11 C34 C35 C36
1.0uF
SMD Capacitor, 10V 1206 X7R
3
3
C44 C58 C60
0.22uF X7R
SMD Capacitor, 16V 0805 X7R
C0805X7R160-224KNE
4
1
C19
68uF TANT
SMD Capacitor, 25V
AVX TAJE686K025R
5
1
C32
0.01uF
SMD Capacitor, 25V 0805
BC 0805B103K500BT
6
40
0.1uF / 0.1uF X7R
SMD Capacitor, 25V 0805 X7R
AVX 08055C104KAT2A
7
1
C1 C4 C5 C7 C9 C10 C15 C17 C22 C25 C27 C28 C29 C30 C31 C37
C38 C78 C79 C89 C40 C42 C45 C50 C67 C68 C71C55 C56 C62 C65
C66 C69 C70 C82 C84 C86 C88 C91 C92
C73 C74
10pf
SMD Capacitor, 25V COG 0805
C0805COG500-100JNE
8
6
C39 C41 C46 C47 C61 C49
470pF
SMD Capacitor, 50V 0805 COG
C0805COG500-471KNE
9
1
C48
4.7nF
SMD Capacitor, 50V 0805 COG
C0805X7R160-472KNE
10
24
1nF
SMD Capacitor, 50V COG 0805
AVX 08051C102KAT2A
11
1
C2 C3 C6 C18 C26 C43 C57 C72 C75 C76 C77 C23 C51 C52 C53 C54
C63 C64 C80 C81 C83 C85 C87 C90
C59
1nF X7R
SMD Capacitor, 50V X7R 0805
12
3
C20 C21 C24
SMD Capacitor, AVX Tant, Low ESR
AVX TPSE337K010R0100
13
4
C12 C13 C14 C16
330uF AVX SMD
47pF - NO_FIT
14
4
D1 D2 D3 D4
MBRS340T3
SMD Diode, Schottky Power
On Semi MBRS340T3
15
1
DS1
SMD YELLOW LED
SMD LED
Kingbright AA3528SYC
DO NOT INSTALL
16
1
DS13
SMD RED LED
SMD LED
Kingbright AA3528EC
17
8
DS2 DS3 DS4 DS5 DS6 DS7 DS8 DS9
SMD YELLOW LED
SMD LED
Infineon HSMY-C650
18
3
DS10 DS11 DS12
SMD GREEN LED
SMD LED
Kingbright AA3528SGC
19
1
F1
Fuse, 1a, 250v,
Fuse, 5 x 20 mm, glass
Little Fuse 0216005.H
20
1
F1
Bussmann HTC-15M
Through Hole Fusemount (5mm Fuse)
Keystone 4527
21
1
FB1
FERRITE BEAD
SMD Ferrite Bead
Murata BLM31AJ601SN1L
22
19
J1 J3 J5 J10 J15 J17 J19 J26 J28 J30 J31 J33 J34 J35 J36 J37 J38 J39 J40
JUMPER 2 (Default FITTED)
Through Hole, 0.1 inch header (1x2)
Sullins PZC02SAAN
23
7
J14 J20 J22 J23 J27 J44 J45
JUMPER 2 (Default REMOVED)
Through Hole, 0.1 inch header (1x2)
Sullins PZC02SAAN
24
13
J7 J8 J11 J12 J13 J18 J21 J25 J29 J32 J41 J42 J43
JUMPER 3
Through Hole, 0.1 inch header (1x3)
Sullins PZC03SAAN
25
4
J2 J4 J6 J9
JUMPER 2x2
Through Hole, 0.1 inch header (2x2)
Sullins PZC02DAAN
MAC7100EVBUM/D
Page A-1
MAC7100EVB Users Manual Rev 1.1
November 2004
26
1
J24
JUMPER 3x3
Through Hole, 0.1 inch header (3x3)
Sullins PZC0 Series
27
1
J16
JUMPER 8x2
Through Hole, 0.1 inch header (8x2)
Sullins PZC08DAAN
28
29
4
1
L1 L2 L3 L4
P11
25uH
HEADER 10x2
Through hole Inductor, 500V ferrite core
Through Hole, 0.1 inch header (10x2)
Seimens EPCOS B82111-B-C024
Sullins PZC10DAAN
30
1
P14
HEADER 11x2
Through Hole, 0.1 inch header (11x2)
Sullins PZC11DAAN
31
1
P15
Walled HEADER 10x2
Through Hole walled, 0.1 inch header (10x2)
3M 2520-6002UB
32
1
P17
CONNECTOR BNC-RA
Through Hole Pwr Connector, BNC 50 OHM
AMP 415046-1
33
1
P20
AMP PC PWR Connector
Through Hole Pwr Connector, PC Style
AMP 350211-1
34
1
P21
PWR 2SV-02
Through Hole Pwr Connector, 2-way Lever
Buchanan 2SV-02
35
1
P22
RJ45_LED
Through Hole, RJ45 Ethernet Connector
Amphenol RJHS-5381
36
1
P23
PWR Switchcraft RAPC722
Through Hole Pwr Connector, 2.1mm Jack
Switchcraft RAPC722
37
2
P3 P4
CONNECTOR DB9
Through Hole Connector, DB9 RS232 female
AMP 788796-1
38
2
P5 P19
AMP 120-way SMT Connector
SMD Connector, 120-way 0.8mm pitch plug
AMP 179031-5
39
2
P6 P16
HEADER 19x2 MICTOR
SMT Connector, MICTOR Style (M38C)
AMP 767054-1
40
1
P7
Walled HEADER 7x2
Through Hole walled, 0.1 inch header (7x2)
3M 2514-6002UB
41
5
P8 P9 P10 P12 P13
HEADER 9x2
Through Hole, 0.1 inch header (9x2)
Sullins PZC09DAAN
42
2
P1 P2
HEADER 3x1
Through Hole, 0.1 inch header (3x1)
Sullins PZC03SAAN
43
1
P18
HEADER 8x1
Through Hole, 0.1 inch header (8x1)
Sullins PZC08SAAN
44
1
R22
1K2
SMD Resistor, 0805 5%
Panasonic, Philips or AVX
45
1
R25
150R
SMD Resistor, 0805 5%
Panasonic, Philips or AVX
46
1
R26
270R
SMD Resistor, 0805 5%
Panasonic, Philips or AVX
47
1
R28
5K
SMD Resistor, 0805 5%
Panasonic, Philips or AVX
48
3
R3 R27 R35
560R
SMD Resistor, 0805 5%
Panasonic, Philips or AVX
49
4
R4 R6 R8 R12
33R
SMD Resistor, 0805 5%
Panasonic, Philips or AVX
50
14
R5 R7 R10 R11 R14 R15 R18 R34 R9 R13 R17 R23 R30 R33
10K
SMD Resistor, 0805 5%
Panasonic, Philips or AVX
51
3
R1 R2 R29 R31
0R
SMD Resistor, 0805 5%
Panasonic, Philips or AVX
52
2
R16 R20
100R
SMD Resistor, 0805 5%
Panasonic, Philips or AVX
53
3
R21 R19 R24
1K
SMD Resistor, 0805 5%
Panasonic, Philips or AVX
54
1
R32
NO Fit
SMD Resistor, 0805 5%
55
56
8
1
RN1 RN2 RN3 RN6 RN7 RN8 RN10 RN12
RN11
10K Net
75R Net
SMD Resistor Network (x4), 1206 5%
SMD Resistor Network (x4), 1206 5%
Panasonic, Philips or AVX
Panasonic, Philips or AVX
57
2
RN4 RN5
560R Net
SMD Resistor Network (x4), 1206 5%
Panasonic, Philips or AVX
58
1
RN9
4K7 Net
SMD Resistor Network (x4), 1206 5%
Panasonic, Philips or AVX
59
1
RP1
330R 1%
SMD Precision Resistor, 0805 1%
Panasonic, Philips or AVX
MAC7100EVBUM/D
Page A-2
MAC7100EVB Users Manual Rev 1.1
60
1
November 2004
RP10
11K 1%
SMD Precision Resistor, 0805 1%
Panasonic, Philips or AVX
61
2
RP16 RP17
49.9R 1%
SMD Precision Resistor, 0805 1%
Panasonic, Philips or AVX
62
3
RP2 RP3 RP15
1K2 1%
SMD Precision Resistor, 0805 1%
Panasonic, Philips or AVX
63
1
RP4
180R 1%
SMD Precision Resistor, 0805 1%
Panasonic, Philips or AVX
64
1
RP5
15R 1%
SMD Precision Resistor, 0805 1%
Panasonic, Philips or AVX
65
3
RP6 RP13 RP14
470R 1%
SMD Precision Resistor, 0805 1%
Panasonic, Philips or AVX
66
1
RP7
270R 1%
SMD Precision Resistor, 0805 1%
Panasonic, Philips or AVX
67
4
RP8 RP9 RP11 RP12
24.9R 1%
SMD Precision Resistor, 0805 1%
Panasonic, Philips or AVX
68
1
RV1
2K Var
Through Hole trimmer, XICON 9mm snap-in
Alpha/Xicon 317-2090-2K
69
1
RV2
1K Var Trimmer SMD
SMD Trimmer, 3mm cermet type
CTS 303UC102E
70
1
SW1
SWITCH SPST, 8 Posn
SMD Switch, SPST Series 219 DIP
CTS Corp 219-8LPST
71
1
SW2
SWITCH C&K PUSH RED
SMD Switch, Momentary push button RED
C&K KS11R23CQD
72
1
SW3
SWITCH C&K PUSH BLK
SMD Switch, Momentary push button BLACK
C&K KS11R22CQD
73
1
SW4
SWITCH SPDT SLIDE
Through Hole Switch, SPDT Slide
CW Industries G107-0513
74
1
T1
HALO TG110-S050N5
SMD Filter, Ethernet isolation transformer
Halo TG110-S050N2
75
11
TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11
HEADER 1-TP
SMD Test point
Keystone 5015
76
2
U1 U2
PCA82C250T
SMD IC, Can Transceiver, S08 Package
Philips PCA82C250TD
77
2
U12 U13
MC74LCX16244
SMD IC, 16 bit buffer driver
On Semi MC74LCX16244DT
78
2
U18 U20
LM2596S-ADJ
National Semi LM2596S-ADJ
79
1
U19
LM2596S-3.3
SMD Switching Voltage Regulator (Variable
Output)
SMD Switching Voltage Regulator (3.3V Output)
80
1
U4
MAX232CSE
SMD IC, Maxim RS232 Level Shifter
Maxim MAX232CSE
81
1
U10
MC74LCX16245
SMD IC, 16 bit bi-directional buffer
On Semi MC74LCX16245DT
82
1
U11
NC7SZ57
Fairchild NC7SZ57P6X
83
1
U14
AM29F160D FLASH
SMD IC, TinyLogic Configurable 2-Input Logic
Gate
SMD FLASH, 2MByte Standard pinout, 5V
84
1
U15
(64Kx16) SRAM
SMD SRAM, 128KByte 5V
Cypress CY7C1021B-12ZC
85
1
U16
ispGAL22V10AV-5LJC
PLCC IC, PAL22V10 3.3V GAL, ISP
Lattice ispGAL22V10AV-5LJC
86
1
XU16-1
940-99-028-17-400000
SMD Socket, 28-ld PLCC
Mil-Max 940-99-028-17-400000
87
1
U17
SMSC LAN91C111-NE
SMD IC, Ethernet transceiver, 10/100
SMSC LAN91C111-NE
88
1
U9
MAC7111 144QFP
Freescale MAC7111 QFP MCU
89
1
U3
MAX6343-S
Maxim MAX6343SUT-T
Micrel MC74AC08-D
90
1
U5
MAX6703-Z
SMD IC,Low Voltage Monitor (Active Sw
Debounce)
SMD IC,Low Voltage Monitor Device
91
1
U6
MC74AC08-D
SMD IC, Quad 2-Input AND gates
MAC7100EVBUM/D
Page A-3
National Semi LM2596S-3.3
AMD Am29F160D B75EC
Maxim MAX6703ZKA-T
MAC7100EVB Users Manual Rev 1.1
November 2004
92
1
U7, U8
MC74AC125-D
SMD IC, Quad Buffer with 3-State Outputs
Micrel MC74AC125-D
93
1
Y1
8MHz XTAL, HC-49S
Fox FOXS080-20
94
1
Y2
8MHZ OSC Module
Through Hole Crystal Oscillator, HC-49 Low
Profile
Through Hole Oscillator Module, DIP14
Epson SG-8002DC-PCB-ND
95
1
Y3
25MHz OSC Module
Through Hole Oscillator Module, DIP14
Pletronics P1145-HCV-25MHZ
SJ-5518
Black self adhesive rubber feet
3M SJ5518-9-ND
STC02SYAN
Jumper Shunts, 2 pin
Sullins STC02SYAN
Misc Items
96
8
97
50
All default jumper headers fitted
MAC7100EVBUM/D
Page A-4
MAC7100EVB Users Manual Rev 1.1
November 2004
Appendix B - EVB Schematics
MAC7100EVBUM/D
Page B-1
MAC7100 Evaluation Board
Table Of Contents:
POWER SUPPLY
MAC7111 144 PIN MCU
CLOCK AND PLL CIRCUITRY
RESET GENERATION, CONTROL AND MODE SELECTION
JTAG AND NEXUS CONNECTORS
EBI BUFFERS 1 - DATABUS
EBI BUFFERS 2 - ADDRESS AND CONTROL
EXTERNAL MEMORY
ETHERNET 1 - SMSC ETHERNET CONTROLLER
ETHERNET 2 - MCU / ETHERNET INTERFACE AND RJ45
CAN AND SCI PHYSICAL INTERFACE
EXPANSION CONNECTORS (DAUGHTERCARD)
USER CONNECTORS
TERMINATION RESISTORS
SHEET 2
SHEET 3
SHEET 4
SHEET 5
SHEET 6
SHEET 7
SHEET 8
SHEET 9
SHEET 10
SHEET 11
SHEET 12
SHEET 13
SHEET 14
SHEET 15
Revision Information
Rev
Date
0.1
28 March 03
0.2
04 April 03
0.3
22 April 03
0.4
30 April 03
1.0
1.1
1.2
25 July 03
12 Sept 03
12 Nov 04
Designer
A. Robertson
A. Robertson
A. Robertson
A. Robertson
Comments
Provisional release
Incorporates review changes - Release to PCB layout
Mod's to incorporate changes to MCU reset config
Remove PD2 Jumper and pull VSSTest to ground
A. Robertson
A. Robertson
A. Robertson
Changes for PCB RevB
Changes to Productionise EVB (PCB RevO)
Name Change to Freescale Semiconductor
Notes:
- Resistor networks are donated RNx. All resistor networks are SMD 1206 style package.
Note:
- High precision resistors (1%) are denoted RPx and are SMD 0805
- Variable resistors are denoted RVx
- All other resistors are SMD 0805 style unless otherwise stated
- All decoupling caps less than 0.1uF are COG SMD 0805 unless otherwise stated
- All decoupling caps greater than 0.1uF are X7R SMD 0805 unless otherwise stated
- All connectors are denoted Px
- All jumpers are denoted Jx
- Jumper default positions are shown in the schematics. For 3 way jumpers, default is always posn 1-2
- All Switches are denoted SWx
- All test points are denoted TPx
These schematics are provided for reference purposes only.
As such, Freescale (Launched by Motorola) does not make
any warranty, implied or otherwise, as to the suitability of
circuit design or component selection (type or value) used in
these schematics for hardware design using the Freescale
MAC7xxx family of Microprocessors. Customers using any
part of these schematics as a basis for hardware design, do
so at their own risk and Freescale does not assume any
liability for such a hardware design.
- All unpopulated test points (vias) are denoted as TPVx
User notes are given throughtout the schematics.
Specific PCB LAYOUT notes are detailed in ITALICS
Freescale TECD Applications - East Kilbride
Title
Size
B
Date:
MAC7100 Evaluation Board
Document Number
Drawing 63A11505S
Rev
1.2
(MAC7100 EVB)
Friday, November 12, 2004
Sheet
1
of
15
POWER SUPPLY
7 to 14 Volt Power
Supply Input
POWER SWITCH
SW4
P23
2.1mm Barrel
Connector
POWER-IN
3
2
1
Switchcraft RAPC712
R20
100R
(Nexus Connector Power Monitor)
1
4
2
3
RP5
RP13
Augat 25V-02
GND
GND
GND
~ON/OFF
0.1uF
GND
4
FB
L2
2
C20
D2
RP14
470R 1%
1
+
MBRS340T3
2
+12V
1
GND#2
2
GND#3
3
+5V
4
1
3,13
2
VDDIO
(Peripherals ETC)
VDDIO
3,13
VDDR
(On Chip Regulator)
VDDR
3,13
1
0.1uF
2
GND
P3_3V
R27
560R
VDDR jumper MUST be
in posn 2-3 when
VDDCORE or VDDPLL
jumpers are fitted.
GND
P2_5V
R26
270R
R25
150R
P2_5V
LM2596S-3.3
P3_3V
J22
J42
TP6
TP7
4
3
D4
C21
+
1
2
0.1uF
TP11
POWER LED's
2
VDDCore
(When NOT using Reg)
VDDCore
3,13
2
VDDPLL
(Clock and PLL)
VDDPLL
3,4,13
MCU-VRH
3,13
USR-VRH
13,14
MCU-VRL
3,13
USR-VRL
13,14
J27
1
FB
1
25uH
MBRS340T3
1
GND
2
TP5
1
1
C30
TP4
~ON/OFF
L3
2
330uF AVX SMD
5
3
VOUT
TAB
DS10
VIN
6
DS11
1
GND
DS12
2
2
2
3.3V
TP3
VDDA
J21
C25
Note - 2.5V regulator output required
for reset switch to operate
GND
PVDDIO
U19
TP2
VDDA
(ADC Supply)
3
AMP 350210-1
TP1
2
25uH
J15
P20
PC PSU
Connector
1
1
C28
GND
5
3
VOUT
TAB
J41
1000uF
GND
68uF TANT
VIN
2
J19
P2_5V
15R 1%
470R 1%
6
1nF
+ C33
1
3
1
0.1uF
+
C19
LM2596S-ADJ
2.5V
2
C26
D1
U18
VMain-In
25uH
330uF AVX SMD
C27
L1
VFused
MBRS340T3
2
6
MCU Supply Jumpers
VSwitched
1
VDD-UNREG
PVDDIO
F1
P21
2 Lever
Connector
VDD-UNREG
5
1
C29
0.1uF
GND Reference Points
ADC Control
Current approx 5mA
1
1
1
1
1
1
1
1
ALL LED's GREEN SMD
GND
PVDDIO
J8
GND
1
2
3.0V to 5.0V
FERRITE BEAD
1
GND
AGND
5
Voltage Regulator
Reference Points
~ON/OFF
2
4
FB
RV2
J43
1
0.1uF
R22
1K2
2
3
PVDDIO
PT6
PT11
PT16
PT1
PT7
PT12
PT17
PT2
PT8
PT13
PT18
PT3
PT9
PT14
PT19
PT4
PT10
PT15
PT20
PT5
D3
3
PVDDIO
C24
+
J7
C22
1
MBRS340T3
0.1uF
AGND
3
MCU-VRL
2
(MCU And Expansion
Connectors)
USR-VRL
(From User Connectors)
RP6
470R 1%
Freescale TECD Applications - East Kilbride
Title
Protoype Area Reference Points
MCU-VRH
(MCU And Expansion
Connectors)
USR-VRH
(From User Connectors)
25uH
3
P3_3V
270R 1%
L4
2
P2_5V
1K2 1%
1
C31
VOUT
RP7
1K Var Trimmer SMD
GROUND Links
TP10
VIN
3
TP9
1
RP15
330uF AVX SMD
TP8
LM2596S-ADJ
1
2
1
1
1
U20
2
FB1
TAB
P3_3V
GND
P2_5V
6
PVDDIO
GND
GND
Jumper Posn 1-2 for 5.0V Fixed, Posn
2-3 for Variable
Size
B
Date:
MAC7100 Evaluation Board
Document Number
Drawing 63A11505S
Rev
1.2
(MAC7100 EVB)
Friday, November 12, 2004
Sheet
2
of
15
VDDCore
(2.5V)
VDDR
(5V)
NEXUS Port
EXTAL
XTAL
MCU-XFC
58
XFC
J-MCU-TAx
79
TA
Jumper Posn 1-2 for
normal operation.
2
3
TEST
R29
62
TEST
59
1
VSSPLL
J25
MCU-TAx
0R
57
50
64
87
124
14
55_VSSR
60
61
112 112_VSSA
4 MCU-XFC
MCU-EXTAL
MCU-XTAL
55
4 MCU-EXTAL
4 MCU-XTAL
TM
TCLK
TDO
TDI
13_VSSX
49_VSSX
63_VSSX
86_VSSX
125_VSSX
TM
TCLK
TDO
TDI
131
130
129
128
141
142
143
144
1
2
7
8
3
4
5
6
51
52
139
140
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PF[0..15]
15
16
17
18
19
20
21
22
23
72
73
74
75
76
77
78
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PG[0..15]
110
111
MCU-VRH
MCU-VRL
PB0 / SDA
PB1 / SCL
PB2 / SIN-A
PB3 / SOUT-A
PB4 / SCK-A
PB5 / PCS0-A / SS-A
PB6 / PCS1-A
PB7 / PCS2-A
PB8 / PCS5-A / PCSS-A
PB9 / PCS0-B / SS-B / MODC
PB10 / PCS5-B / PCSS-B
PB11 / PCS2-B
PB12 / PCS1-B
PB13 / SCK-B
PB14 / SOUT-B
PB15 / SIN-B
13
49
63
86
125
TM
TCLK
TDO
TDI
54 54_VSS2.5
126 126_VSS2.5
MCU-RSTx
5,6,13 MCU-RSTx
11,13,14,15 MCU-TAx
50_VDDX
64_VDDX
87_VDDX
124_VDDX
14_VDDX
RESET
VDDA
48
56_VDDR
PD0 / MODB / BWE0x
PD1 / MODA / BWE1x
PD2 / CLKOUT
PD3 / XIRQx
PD4 / IRQx
PD11 / OEx
PD12 / CS2x
PD13 / CS1x
PD14 / CS0x
PD15 / RWx
MCU-BWE0x
MCU-BWE1x
MCU-CLK
MCU-XIRQx
MCU-IRQx
MCU-OEx
MCU-CS2x
MCU-CS1x
MCU-CS0x
MCU-RWx
MCU-BWE0x
MCU-BWE1x
MCU-CLK
MCU-XIRQx
MCU-IRQx
MCU-OEx
MCU-CS2x
MCU-CS1x
MCU-CS0x
MCU-RWx
PG0 / RXD-B
PG1 / TXD-B
PG2 / RXD-A
PG3 / TXD-A
PG4 / CNTX-A
PG5 / CNRX-A
PG6 / CNTX-B
PG7 / CNRX-B
PG8 / CNTX-C
PG9 / CNRX-C
PG10 / CNTX-D
PG11 / CNRX-D
PG12 / RXD-D
PG13 / TXD-D
PG14 / RXD-C
PG15 / TXD-C
GND
GND
C47
C41
C72
C57
6,13,14,15
PF[0..15]
5,13,14
PG[0..15]
12,13,14
GND
C37
C38
0.1uF
0.1uF
AGND
SMD socket can be fitted by user if required - YAMAICHI IC149-144
PE[0..15]
Local Decoupling
PB[0..15]
VRH
VRL
GND
TPV2
C46
1nF
70
71
80
81
82
68
69
83
84
85
MAC7111
2,13
0.1uF X7R
PA0 / DATA0 / MCK0
PA1 / DATA1 / EVTO
PA2 / DATA2 / EVTI
PA3 / DATA3 / MDO_0
PA4 / DATA4 / MDO_1
PA5 / DATA5 / MSEO
PA6 / DATA6 / RDY
PA7 / DATA7
PA8 / DATA8
PA9 / DATA9
PA10 / DATA10
PA11 / DATA11
PA12 / DATA12
PA13 / DATA13
PA14 / DATA14
PA15 / DATA15
PE[0..15]
VDDIO
C71
1nF
138
137
136
135
134
133
132
98
97
96
95
94
93
67
66
65
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
C42
0.1uF X7R
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
PF0 / EMIOS0
PF1 / EMIOS1
PF2 / EMIOS2
PF3 / EMIOS3
PF4 / EMIOS4
PF5 / EMIOS5
PF6 / EMIOS6
PF7 / EMIOS7
PF8 / EMIOS8
PF9 / EMIOS9
PF10 / EMIOS10
PF11 / EMIOS11
PF12 / EMIOS12
PF13 / EMIOS13
PF14 / EMIOS14
PF15 / EMIOS15
43
42
41
40
39
38
37
36
35
34
33
32
27
26
25
24
C67
470pF
PD5 / ADDR16
PD6 / ADDR17
PD7 / ADDR18
PD8 / ADDR19
PD9 / ADDR20
PD10 / ADDR21
DATA[0..15]
5,6,7,13,14,15 DATA[0..15]
6,13,15
6,13,15
6,13,15
6,13,15
92
119
120
121
122
123
ADDR[0..21]
8,13,14 ADDR[0..21]
5,8,13,14,15
5,8,13,14,15
4
5,13,14,15
11,13,14,15
7,8,13,14,15
8,13,14,15
8,13,14,15
8,13,14,15
7,8,13,14,15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR20
ADDR21
C45
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
0.1uF X7R
Local Decoupling
C50
99
100
101
102
103
104
105
106
107
108
113
114
115
116
117
118
PE0 / AN00 / MCK0
PE1 / AN01 / EVTO
PE2 / AN02 / EVTI
PE3 / AN03 / MDO_0
PE4 / AN04 / MDO_1
PE5 / AN05 / MSEO
PE6 / AN06 / RDY
PE7 / AN07
PE8 / AN08
PE9 / AN09
PE10 / AN10
PE11 / AN11
PE12 / AN12
PE13 / AN13
PE14 / AN14
PE15 / AN15
470pF
GND
PC0 / ADDR0
PC1 / ADDR1
PC2 / ADDR2
PC3 / ADDR3
PC4 / ADDR4
PC5 / ADDR5
PC6 / ADDR6
PC7 / ADDR7
PC8 / ADDR8
PC9 / ADDR9
PC10 / ADDR10
PC11 / ADDR11
PC12 / ADDR12
PC13 / ADDR13
PC14 / ADDR14
PC15 / ADDR15
470pF
470pF
GND
9
10
11
12
28
29
30
31
44
45
46
47
88
89
90
91
NEXUS Port
1nF
GND
C75
1nF
C61
0.1uF X7R
C43
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
0.1uF X7R
C68
0.22uF X7R
0.22uF X7R
C39
C60
470pF
1nF X7R
GND
0.1uF X7R
0.22uF X7R
C59
C44
(5V)
0.1uF X7R
C40
109
VDDIO
U9
C58
MAC7111 144 PIN MCU
ENSURE there is suffient room around 144QFP
footprint for SMD socket to be fitted.
VDDPLL
2,13 VDDR
(5V)
53
127
2,13 VDDCore
(2.5V)
VDDA
56
2,13 VDDA
VDDPLL
53_VDD2.5
127_VDD2.5
2,4,13 VDDPLL
AGND
PB[0..15]
13,14
MCU-VRH
MCU-VRL
2,13
2,13
Freescale TECD Applications - East Kilbride
Title
Size
B
Date:
MAC7100 Evaluation Board
Document Number
Drawing 63A11505S
Rev
1.2
(MAC7100 EVB)
Friday, November 12, 2004
Sheet
3
of
15
CLOCK AND PLL CIRCUITRY
R8
33R
MCU-CLK
(FROM MCU)
Place resistor as close as
possible to MCU CLKOUT pin
MCU-CLK
1
2
MCU-CLKOUT
J23
R9
10K
Y2
1
OE
4
7
VCC
14
GND
OUT2
11
GND2
OUT1
8
MCU-CLKOUT 5,6,8,13,14
MCU-XFC
3
VDDPLL
2,3,13
EXT-EXTAL
13
MCU-EXTAL
(MCU Crystal Input)
MCU-EXTAL
3
MCU-XTAL
(MCU Crystal Output)
MCU-XTAL
3
R28
5K
J45
2
Note - External 2.5V
regulator MUST be
enabled when using
oscillator module
C49
470pF
1
FIT Jumper to
DISABLE PLL
(Cs)
Oscillator Module
(14 Pin DIL socket)
0.1uF
1
(Cp)
C15
(Ro)
2
MCU-XFC
P2_5V
3
J44
C48
4.7nF
VDDPLL
PLL Loop Filter
Place as close as possible
to device XFC pin
8MHZ OSC MODULE
EXT-EXTAL
(To Expansion Connectors)
GND
J32
OSC-MOD
1
J29
2
EXT-EXTAL
3
EXTAL_BNC 3
2
C74
R16
10pF
1
100R
2
1
GND
Y1
8MHz XTAL
RB
R32
NO FIT
1
BNC style
Connector
P17
CONNECTOR BNC-RA
2
R31
C73
J30
0R
10pF
1
2
RS
GND
Loop Controlled Pierce
Oscillator Circuit (Default)
For Full Swing Pierce change RB
and RS according to desired
operating conditions.
REMOVE jumper when
driving EXTAL from
Oscilaltor Module or
External Source
Crystal circuit ground must NOT be directly connected
to ground plane but routed via VSSPLL pin to VSSR and
then connected to ground
Freescale TECD Applications - East Kilbride
Title
Size
B
Date:
MAC7100 Evaluation Board
Document Number
Drawing 63A11505S
Rev
1.2
(MAC7100 EVB)
Friday, November 12, 2004
Sheet
4
of
15
RESET GENERATION, CONTROL AND MODE SELECTION
PVDDIO
Tri-State Buffered RESET signal to MCU (Reset-IN)
PVDDIO
USR RESET LED
R3
2
U6A
JTAG-RSTx
TPV14
JTAG-RSTx
1
SPARE-RSTx
2
560R
3
VDD = PVDDIO
VSS = GND
TGT-RSTx
9
LVI-RSTx
10
0.1uF
0.1uF
AC08 / AC125
Decoupling
Caps
U6B
GND
VDD = PVDDIO
VSS = GND
5
U6C
(From Expansion Conn
/ User Connectors)
TGT-RSTx
1
4
MC74AC08-D
13,14
C9
SMD AMBER LED
6
1
6
(From JTAG / NEXUS)
C10
DS1
MCU-RSTx
U7A
MCU-RSTx
3,6,13
RST-OUTx
9,11,13,14
MCU-BWE1x
3,8,13,14,15
MCU-BWE0x
3,8,13,14,15
MC74AC08-D
8
VDD = PVDDIO
VSS = GND
2
VDD=PVDDIO
VSS=GND
PVDDIO
3
MCU RESET LED
R35
GND
MC74AC08-D
DS13
MC74AC125-D
2
2
560R
1
SMD RED LED
PVDDIO
J10
RN3
U6D
JTAG-RSTx 1
SPARE-RSTx 3
TGT-RSTx
5
LVI-RSTx
7
MCU-RSTx
2
4
6
8
12
VDD = PVDDIO
VSS = GND
13
RST-OUTx
11
Buffered
RESET-OUT
MC74AC08-D
1
10K Net
RST-OUTx
4
PVDDIO
RN1
P2_5V
1
3
5
7
0.1uF
U5
RSTOUTx
7
RESET_SW
1
WDO
WDI
8
6
VCC
J12
3
2
J11
4
RST_IN1
GND
5
16
15
14
13
12
11
10
9
MODEA
MODEB
XCLKS
EBI-PSZ
AUTO-TA
NEXUS-LOC
NEXUS-EN
SWITCH CTS 219-8
3
GND
2
(PD1/MODA/BWE1x)
MCU-BWE1x
9
(PD0/MODB/BWE0x)
MCU-BWE0x
U7C
VDD=PVDDIO
VSS=GND
8
MC74AC125-D
XCLKS
GND
12
U7D
VDD=PVDDIO
VSS=GND
11
MCU-CLKOUT
MCU-CLKOUT 4,6,8,13,14
(PD2/CLKOUT/XCLKS)
TPV1
RST_IN2
GND
MC74AC125-D
MAX6703-Z
1
(Note - VDDIO LVI
monitoring must be
disabled when
VDDIO is set to
less than 5.0V)
2.33V Threshold LVI
IF RST-INX < 0.62V, Reset Asserted
Voltage
Vout (RST_IN)
RP1
330R 1%
6
MC74AC125-D
SW1
1
2
3
4
5
6
7
8
SW2
SWITCH C&K PUSH RED
Jumper Posn
2-3, Monitor
disabled
3
RP4
180R 1%
U7B
VDD=PVDDIO
VSS=GND
3.3V
5.0V
0.71V
0.65V
GND
PVDDIO
RN2
1
3
5
7
2
4
6
8
EBI-PSZ
AUTO-TA
NEXUS-LOC
NEXUS-EN
EBI-PSZ
2
DATA[0..15]
U8A
VDD=PVDDIO
VSS=GND
3
MC74AC125-D
LVI Circuit
AUTO-TA
5
U8B
VDD=PVDDIO
VSS=GND
6
DATA[0..15]
3,6,7,13,14,15
DATA14
10K Net
4
1
5
10
2
RP2
1K2 1%
MODEA
10K Net
GND
RP3
1K2 1%
MCU-RSTx
MODEA
MODEB
XCLKS
2
4
6
8
13
C7
1
PVDDIO P3_3V
DATA15
Note - AC08 / AC125
Devices operate from 2V
to 6V VCC so are
suitable for use with
variable VDDIO
PVDDIO
MC74AC125-D
VCC
C1
3
PFI
2
GND
J1
RSTOUTx
6
PFO
4
RESET_SW
5
1
2
NEXUS-LOC
9
SW3
SWITCH C&K PUSH BLK
GND
8
PF[0..15]
3,13,14
PF0
MC74AC125-D
GND
De-Bounced ABORT Switch
RESET Configuration
(Mode Selection)
3,13,14,15 MCU-XIRQx
PF[0..15]
U8C
VDD=PVDDIO
VSS=GND
13
0.1uF
MAX6343-S
10
U3
1
MCU-XIRQx
XIRQ (Highest Priority Interrupt)
NEXUS-EN
12
Freescale TECD Applications - East Kilbride
U8D
VDD=PVDDIO
VSS=GND
11
MC74AC125-D
PF1
Title
Size
B
Date:
MAC7100 Evaluation Board
Document Number
Drawing 63A11505S
Rev
1.2
(MAC7100 EVB)
Friday, November 12, 2004
Sheet
5
of
15
Layout Note - Place CAPS
as close as possible to
each connector.
Do NOT fit caps at board
assembly.
C13
C14
C12
C16
PVDDIO
(VTref)
JTAG-TRSTx
TDI
TM
TCLK
(RTCLK)
TDO
JTAG-JRSTx
(DBGRQ)
(DBGACK)
(All Caps 47pF)
GND
JTAG TRST Signal NOT
connected to MCU reset as
there is NO external
control of TRST on
MAC7100
TPV13
3,13,15
3,13,15
3,13,15
3,13,15
1
3
5
7
9
11
13
15
17
19
(Vsupply)
2
4
6
8
10
12
14
16
18
20
GND
Multi-ICE JTAG
Connector
GND
P7
SPU1
JTAG-TRSTx
TDI
TM
TCLK
TDO
JTAG-TRSTx
TDI
TM
TCLK
TDO
PVDDIO
2 VDD-UNREG
JTAG AND NEXUS CONNECTORS
PVDDIO
P15
VDD-UNREG
(Filtered main power supply line, 7-12V)
R6
33R
R4
33R
1
3
5
7
9
11
SPU13 13
2
4
6
8
10
12
14
JTAG-JRSTx
Embedded-ICE JTAG
Connector
GND
VDD-UNREG
J13
5 JTAG-RSTx
JTAG-RSTx
(To RESET-IN Buffer)
PVDDIO
1
2
3,5,13 MCU-RSTx
MCU-RSTx
(Direct to MCU-Reset pin)
JTAG-JRSTx
3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
MCU-CLKOUT
(Vendor IO-3)
(EVTI)
DATA2
VREF
(RDY)
DATA6
(MDO[7])
(MDO[6])
(MDO[5])
(MDO[4])
(MDO[3])
(MDO[2])
(MDO[1]) DATA4
(MDO[0]) DATA3
(EVTO)
DATA1
(MCK0)
DATA0
(MSEO[1])
(MSEO[0]) DATA5
MCU-CLKOUT 4,5,8,13,14
Nexus Option 1 (Shared
With PortA / DataBus)
DATA[0..15]
C1
C2
C3
C4
C5
(Vendor I/O 0)
(Vendor I/O 2)
JTAG-JRSTx
TDO
(Vendor I/O 4)
TCLK
TM
TDI
JTAG-TRSTx
(Vendor I/O 1)
(Tool I/O 3)
(Tool I/O 2)
(Tool I/O 1)
UBATT
UBATT
(Tool I/O 0)
VALTREF
NEXUS Conenctor (MICTOR)
Jumper allows JTAG RESET to
be routed via buffers or to
be directly connected to the
MCU RESETx bi-directional
pin (for debug hardware that
can monitor the state of the
target reset).
VREF
P6
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
DATA[0..15]
3,5,7,13,14,15
PE[0..15]
3,13,14,15
GND
P16
- Windsor Nexus implementation only uses two MDO channels.
NEXUS Conenctor (MICTOR)
Notes:
(Vendor I/O 0)
(Vendor I/O 2)
JTAG-JRSTx
TDO
(Vendor I/O 4)
TCLK
TM
TDI
JTAG-TRSTx
(Vendor I/O 1)
(Tool I/O 3)
(Tool I/O 2)
(Tool I/O 1)
UBATT
UBATT
(Tool I/O 0)
VALTREF
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
- For Speed, JTAG and NEXUS use UNBUFFERED MCU signals
PE[0..15]
MCU-CLKOUT
(Vendor IO-3)
(EVTI)
PE2
VREF
(RDY)
PE6
(MDO[7])
(MDO[6])
(MDO[5])
(MDO[4])
(MDO[3])
(MDO[2])
(MDO[1]) PE4
(MDO[0]) PE3
(EVTO)
PE1
(MCK0)
PE0
(MSEO[1])
(MSEO[0]) PE5
Nexus Option 2 (Shared
With PortE / ADC0..6)
Freescale TECD Applications - East Kilbride
C1
C2
C3
C4
C5
Title
GND
Size
B
Date:
MAC7100 Evaluation Board
Document Number
Drawing 63A11505S
Rev
1.2
(MAC7100 EVB)
Friday, November 12, 2004
Sheet
6
of
15
EBI BUFFERS 1 - DATABUS
2
P3_3V
J26
1
Global Buffer Power Jumper. Buffers MUST be
disabled when EVB is used in Single Chip Mode
8 VDD-BUFFER
VDD-BUFFER
(To Address Bus Buffers)
C70
C69
C52
C51
0.1uF
0.1uF
1nF
1nF
GND
U10
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
A0
B0
A1
B1
A2
B2
A3
B3
T/nRx=0
B4
B-------->A A4
A5
B5
A6
B6
A7
B7
T/nRx=1
B8
B<--------A A8
B9
A9
A10
B10
B11
A11
A12
B12
B13
A13
B14
A14
B15
A15
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
MCU-RWx
1
24
T/nR1
T/nR2
OE1x
OE2x
48
25
BDATA[0..15]
9,10
BDATA0
BDATA1
BDATA2
BDATA3
BDATA4
BDATA5
BDATA6
BDATA7
BDATA8
BDATA9
BDATA10
BDATA11
BDATA12
BDATA13
BDATA14
BDATA15
4
10
15
21
28
34
39
45
GND-4
GND-10
GND-15
GND-21
GND-28
GND-34
GND-39
GND-45
MC74LCX16245
3,8,13,14,15 MCU-RWx
BDATA[0..15]
(To / From Buffers)
7
18
31
42
DATA[0..15]
(To / From MCU)
7-VCC
18-VCC
31-VCC
42-VCC
3,5,6,13,14,15 DATA[0..15]
GND
(XNOR Input B)
U11
3,8,13,14,15 MCU-OEx
MCU-OEx
(XNOR Input A)
1
I1
2
GND
3
I0
I2
6
VCC
5
VDD-BUFFER
Y
4
XNOR-OUT
Fairchild NC7SZ57
C62
0.1uF
GND
GND
MCU-RWx
0 (Write)
0 (Write)
1 (Read)
1 (Read)
0
1
0
1
MCU-OEx
(Data In)
(Data Out)
(Data In)
(Data Out)
1
0
0
1
BUFFER-OEx
(INVALID State)
(Outputs Active)
(Outputs Active)
(INVALID State)
Fairchild NC7SZ57 Configurable Logic
Confgured as XNOR Gate. Tpd approx 3ns
Freescale TECD Applications - East Kilbride
Title
Note - Signal Naming Convention. All Buffered signals start with B (eg BDATA for Buffered Data)
Size
B
Date:
MAC7100 Evaluation Board
Document Number
Drawing 63A11505S
Rev
1.2
(MAC7100 EVB)
Friday, November 12, 2004
Sheet
7
of
15
EBI BUFFERS 2 - ADDRESS AND CONTROL
7 VDD-BUFFER
VDD-BUFFER
C65
C66
C56
C55
C63
C64
C53
C54
0.1uF
0.1uF
0.1uF
0.1uF
1nF
1nF
1nF
1nF
VDD-BUFFER
U12
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
48
25
OE2x
OE3x
42-VCC
31-VCC
18-VCC
7-VCC
ADDR[0..21]
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
OE1x
OE4x
1
24
BADDR[0..21]
9,10
BMCU-RWx
BMCU-BWE0x
BMCU-BWE1x
BMCU-OEx
BMCU-CS0x
BMCU-CS1x
BMCU-CS2x
9,11
9
9
9
9
9
9,11
BADDR0
BADDR1
BADDR2
BADDR3
BADDR4
BADDR5
BADDR6
BADDR7
BADDR8
BADDR9
BADDR10
BADDR11
BADDR12
BADDR13
BADDR14
BADDR15
BADDR0 and BADDR21 not used in Memory
but pinned out for debug purposes.
BADDR0
R10
10K
GND
BADDR21
45
39
34
28
21
15
10
4
GND
BADDR[0..21]
MC74LCX16244
GND-45
GND-39
GND-34
GND-28
GND-21
GND-15
GND-10
GND-4
3,13,14 ADDR[0..21]
42
31
18
7
GND
R11
10K
GND
GND
U13
MCU-RWx
MCU-BWE0x
MCU-BWE1x
MCU-OEx
MCU-CS0x
MCU-CS1x
MCU-CS2x
4,5,6,13,14 MCU-CLKOUT
MCU-RWx
MCU-BWE0x
MCU-BWE1x
MCU-OEx
MCU-CS0x
MCU-CS1x
MCU-CS2x
MCU-CLKOUT
48
25
GND
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
OE2x
OE3x
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
OE1x
OE4x
1
24
BADDR16
BADDR17
BADDR18
BADDR19
BADDR20
BADDR21
BMCU-RWx
BMCU-BWE0x
BMCU-BWE1x
BMCU-OEx
BMCU-CS0x
BMCU-CS1x
BMCU-CS2x
B-CLKOUT
BMCU-CLKOUT
R12
GND
BMCU-CLKOUT 11
33R
Place resistor as close as
possible to Buffer
45
39
34
28
21
15
10
4
3,7,13,14,15
3,5,13,14,15
3,5,13,14,15
3,7,13,14,15
3,13,14,15
3,13,14,15
3,13,14,15
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
MC74LCX16244
GND-45
GND-39
GND-34
GND-28
GND-21
GND-15
GND-10
GND-4
ADDR16
ADDR17
ADDR18
ADDR19
ADDR20
ADDR21
42-VCC
31-VCC
18-VCC
7-VCC
42
31
18
7
VDD-BUFFER
Freescale TECD Applications - East Kilbride
GND
Buffer OEx=0, Drive Input Dx to output Ox
Title
Size
B
Date:
MAC7100 Evaluation Board
Document Number
Drawing 63A11505S
Rev
1.2
(MAC7100 EVB)
Friday, November 12, 2004
Sheet
8
of
15
EXTERNAL MEMORY
BDATA[0..15]
7,10 BDATA[0..15]
BADDR[0..21]
8,10 BADDR[0..21]
PVDDIO
J33
U14
2 FLASH-VCC
1
C17
0.1uF
C18
1nF
BOOT Block
Write Enable
WP=0, Boot sector
protected
(AM29F400B ONLY)
1
2
J31
R13
10K
GND
General
WRITE Enable
R17
5,11,13,14 RST-OUTx
8 BMCU-OEx
BMCU_RWx
VCC
BADDR1
BADDR2
BADDR3
BADDR4
BADDR5
BADDR6
BADDR7
BADDR8
BADDR9
BADDR10
BADDR11
BADDR12
BADDR13
BADDR14
BADDR15
BADDR16
BADDR17
BADDR18
BADDR19
BADDR20
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
FLASH-WPx
FLASH-RWx
47
14
11
BYTE
WP
WE
RST-OUTx
BMCU_OEx
12
28
RST
OE
FLASH-CSx
26
CE
10K
J34
8,11 BMCU-RWx
R30
10K
(BYTE=1 FOR 16-BIT MODE)
GND
37
1
2
RST-OUTx
BMCU-OEx
BMCU_RWx
FLASH
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15 / A-1
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
RY/BY
15
GND_27
GND_46
27
46
BDATA0
BDATA1
BDATA2
BDATA3
BDATA4
BDATA5
BDATA6
BDATA7
BDATA8
BDATA9
BDATA10
BDATA11
BDATA12
BDATA13
BDATA14
BDATA15
PIN COMPATIBLE FLASH
AMD AM29F400B (512K Bytes)
AMD AM29F800B (1M Byte)
AMD AM29F160D (2M Bytes)
AM29F160D FLASH
GND
U15
1
SRAM-VCC
2
C78
C79
0.1uF
0.1uF
C76
1nF
1nF
GND
R33
10K
J24
8 BMCU-CS0x
8 BMCU-CS1x
8,11 BMCU-CS2x
BMCU-CS0x
2
BMCU-CS1x
5
BMCU-CS2x
8
1
3
4
6
7
9
11
33
VCC
VCC
BADDR1
BADDR2
BADDR3
BADDR4
BADDR5
BADDR6
BADDR7
BADDR8
BADDR9
BADDR10
BADDR11
BADDR12
BADDR13
BADDR14
BADDR15
BADDR16
5
4
3
2
1
44
43
42
27
26
25
24
21
20
19
18
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
BMCU-OEx
BMCU_RWx
41
17
SRAM-CSx
6
C77
FLASH-CSx
SRAM-CSx
SRAM
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
BDATA0
BDATA1
BDATA2
BDATA3
BDATA4
BDATA5
BDATA6
BDATA7
BDATA8
BDATA9
BDATA10
BDATA11
BDATA12
BDATA13
BDATA14
BDATA15
OE*
WE*
BLE*
BHE*
39
40
BMCU-BWE0x
BMCU-BWE1x
CS*
GND
GND
34
12
BLE
J35
BHE
PVDDIO
CY7C10211B (64Kx16) SRAM GND
8 BMCU-BWE1x
8 BMCU-BWE0x
PIN COMPATIBLE SRAM's
Cypress CYC1020B (32K * 16)
Cypress CYC1021B (64K * 16)
IDT71016 (64K * 16)
BWEx Encoding
BWE0x = D[0..7]
BWE1x = D[8..15]
BMCU-BWE1x
BMCU-BWE0x
Freescale TECD Applications - East Kilbride
Title
Size
B
Date:
MAC7100 Evaluation Board
Document Number
Drawing 63A11505S
Rev
1.2
(MAC7100 EVB)
Friday, November 12, 2004
Sheet
9
of
15
ETHERNET 1 - SMSC ETHERNET CONTROLLER
C91
C90
C88
C87
C84
C81
0.1uF
1nF
0.1uF
1nF
0.1uF
1nF
0.1uF
1nF
0.1uF
1nF
GND
U17
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
BDATA8
BDATA9
BDATA10
BDATA11
BDATA12
BDATA13
BDATA14
BDATA15
107
106
105
104
102
101
100
99
D0
D1
D2
D3
D4
D5
D6
D7
MCU - D8..D15
Ethernet Controller - D0..D7
BDATA0
BDATA1
BDATA2
BDATA3
BDATA4
BDATA5
BDATA6
BDATA7
76
75
74
73
71
70
69
68
D8
D9
D10
D11
D12
D13
D14
D15
66
65
64
63
61
60
59
58
D16
D17
D18
D19
D20
D21
D22
D23
56
55
54
53
51
50
49
48
D24
D25
D26
D27
D28
D29
D30
D31
94
95
96
97
nBE0
nBE1
nBE2
nBE3
BDATA[0..15]
7,9 BDATA[0..15]
P_ENET
C89
0.1uF
R23
10K
Y3
1
OE
VCC
14
4
GND
OUT2
11
7
GND2
OUT1
8
P_ENET
25MHz SMD OSC MODULE
(Pull Low)
SMSC-RESET
30
RESET
(Pull
(Pull
(Pull
(Pull
SMSC-nRD
SMSC-nWR
SMSC-ARDY
SMSC-INTR0
31
32
38
29
nRD
nWR
ARDY
INTR0
SMSC-RBIAS 12
RBIAS
High)
High)
High)
Low)
P_ENET
RN12
1
3
5
7
2
4
6
8
R21
1K
(NC)
RP10
11K 1%
41
XTAL2
XTAL1
AEN
ENEEP
6
EESK
EECS
EEDO
EEDI
IOS0
IOS1
IOS2
9
10
7
8
3
4
5
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
X25OUT
TXEN100
CRS100
RX_DV
RX_ER
COL100
47
111
119
125
126
112
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
TXD0
TXD1
TXD2
TXD3
116
115
114
113
(NC)
(NC)
(NC)
(NC)
TX25
RX25
109
118
(NC)
(NC)
RXD0
RXD1
RXD2
RXD3
124
123
122
121
(NC)
(NC)
(NC)
(NC)
MDI
MDO
MCLK
25
26
27
(NC)
(NC)
(NC)
2
(NC)
LBK
21
(NC)
nRDYRTN
nLEDV
46
45
SMSC-nRDYRTN(PULL HIGH)
(NC)
11
11
SMSC-TPOSMSC-TPO+
11
11
SMSC-nLEDB
SMSC-nLEDA
11
11
(Serial EEPROM
Disabled)
GND
P_ENET
nSRDY
LCLK
43
42
(NC)
SMSC-LCLK
nVLBUS
nLNK
40
20
(NC)
(NC)
nADS
W/nR
nCYCLE
nDATACS
37
36
35
34
(PULL LOW)
SMSC-nADS
(PULL HIGH)
SMSC-WnR
SMSC-nCYCLE (PULL HIGH)
(NC)
nCNTRL
28
(NC)
1
3
5
7
(PULL HIGH)
2
4
6
8
10K Net
R18
10K
GND
P_ENET
Freescale TECD Applications - East Kilbride
10K Net
Title
GND
GND
23
22
SMSC-TPISMSC-TPI+
RN10
GND-24
GND-39
GND-52
GND-57
GND-67
GND-72
GND-93
GND-103
GND-108
GND-117
SMSC-nRD
SMSC-nWR
SMSC-ARDY
SMSC-INTR0
SMSC-XTAL1
128
127
nLEDB
nLEDA
SMSC-nLEDB
SMSC-nLEDA
nCSOUT
GND
11 SMSC-RESET
11
11
11
11
SMSC LAN91C111-NE
24
39
52
57
67
72
93
103
108
117
GND
15
14
SMSC-TPOSMSC-TPO+
MSB
Most Signficant Bytes:
SMSC-TPISMSC-TPI+
TPOTPO+
BADDR[0..21]
8,9 BADDR[0..21]
18
17
TPITPI+
Serial EEPROM
BADDR1
BADDR2
BADDR3
BADDR4
BADDR5
BADDR6
BADDR7
BADDR8
BADDR9
BADDR10
BADDR11
BADDR12
BADDR13
BADDR14
BADDR15
1-VDD
33-VDD
44-VDD
62-VDD
77-VDD
98-VDD
110-VDD
120-VDD
C85
11
16
C86
11-AVDD
16-AVDD
2
C83
AGND-13
AGND-19
1
C92
1
33
44
62
77
98
110
120
P_ENET
J36
13
19
P3_3V
GND
Size
B
Date:
MAC7100 Evaluation Board
Document Number
Drawing 63A11505S
Rev
1.2
(MAC7100 EVB)
Friday, November 12, 2004
Sheet
10
of
15
ETHERNET 2 - MCU / ETHERNET INTERFACE AND RJ45
J37
3,13,14,15 MCU-IRQx
MCU-IRQx
1
MCU-TAx
1
2 MCU-JIRQx
IRQx and TAx outputs from PLD are Open Drain
J38
3,13,14,15 MCU-TAx
P3_3V
2 MCU-JTAx
J39
2 VDD-22V10
1
C80
8,9 BMCU-CS2x
8,9 BMCU-RWx
13,14 TGT-TAx
BMCU-CS2x
1
BMCU-RWx
TGT-TAx
2
(From Expansion Connectors)
RN9
PVDDIO
P18
1
3
5
7
2
4
6
8
4K7 Net
1
2
3
4
5
6
7
8
28
U16
GND
J40
2
3
4
5
6
MAC-I5
7
TPV11
MAC-I6
9
TPV12
SMSC-INTR0
10
SMSC-ARDY
11
MAC-I9 12
TPV10
MAC-I10 13
TPV9
MAC-I11 16
TPV8
ISP-TDO
ISP-TDI
22
15
8
1
ISP-MODE
CP/I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
TDO
TDI
MODE
TCLK
VCC
(Reset From MCU)
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
27
26
25
24
23
21
20
19
18
17
MCU-TAx
MCU-JIRQx
SMSC-RESET
MAC-IO3
MAC-IO4
MAC-IO5
SMSC-nRD
SMSC-nWR
MAC-IO8
MAC-IO9
ISP-TCLK
SMSC-RESET
10
SMSC-nRD
SMSC-nWR
10
10
SMSC-ARDY
SMSC-INTR0
10
10
TPV3
TPV4
TPV5
TPV6
TPV7
ispGAL22LV10-5LJ
Note - 22v10 has
INTERNAL pullups so
unused signals do not
require termination.
VSS
BMCU-CLKOUT
RST-OUTx
14
8 BMCU-CLKOUT
5,9,13,14 RST-OUTx
C82
0.1uF
1nF
R34
10K
GND
SMSC-ARDY
SMSC-INTR0
GND
MACH ISP Header
(Pin5 Removed for Polorisation)
P_ENET
P_ENET
Ethernet / MCU Signal Translation
P_ENET
P_ENET
R19
SMSC-TPOSMSC-TPO+
10
RP9 24.9R 1%
RP12
24.9R 1%
14
3
15
2
16
1
HALO TG110-S050N5
RN11
C23
1nF
1
3
5
7
2
4
6
8
8
7
6
5
4
3
2
1
R24 1K
P22
RJ45_LED
8
7
6
5
4
3
2
1
11
11 SMSC-nLEDA
9
9 SMSC-nLEDB
14
10 SMSC-TPO10 SMSC-TPO+
RP11
24.9R 1%
13
10 SMSC-TPI10 SMSC-TPI+
SMSC-TPISMSC-TPI+
6
14
RP8
24.9R 1%
7
11
10
RP17
49.9R 1%
8
13
RP16
49.9R 1%
9
10
1K
12
C32
0.01uF
12
T1
75R Net
NGND
NGND
10 SMSC-nLEDB
10 SMSC-nLEDA
SMSC-nLEDB
SMSC-nLEDA
Freescale TECD Applications - East Kilbride
Title
Isolation Transformer and RJ45 connector
Size
B
Date:
MAC7100 Evaluation Board
Document Number
Drawing 63A11505S
Rev
1.2
(MAC7100 EVB)
Friday, November 12, 2004
Sheet
11
of
15
CAN AND SCI PHYSICAL INTERFACE
PVDDIO
J5
2 RS232-VCC
1
C6
1nF
+
C34
1.0uF
+
C1+
V+
2
C2+
4
1
6
2
7
3
8
4
9
5
RS232_JTXD-A
RS232_4
RS232_JRXD-A
PG[0..15]
C35
+
+
C36
1.0uF
1.0uF
RS232_3
3
C1-
C2-
5
RS232_5
CONNECTOR DB9
J6
PG3
PG2
(TXD-A)
(RXD-A)
GND
1
3
MCU-JTXD-A
MCU-JRXD-A
2
4
11
12
T1IN
R1OUT
T1OUT
R1IN
14
13
T2IN
R2OUT
T2OUT
R2IN
7
8
V-
6
P4
1
3
MCU-JTXD-B
MCU-JRXD-B
2
4
10
9
GND
(TXD-B)
(RXD-B)
1
6
2
7
3
8
4
9
5
RS232_JTXD-B
J9
PG1
PG0
Default State = Jumpers FITTED
15
MAX232CSE
RS232_JRXD-B
C11
+
3,13,14 PG[0..15]
VCC
GND
1
P3
16
U4
RS232_1
C8
1.0uF
Note - If a MAX232A device is
used, the 5 polorised 1uF caps
can be reduced to 0.1uF
TERMINAL PORT
9-WAY D-TYPE
(Female)
CONNECTOR DB9
GND
1.0uF
GND
PVDDIO
J3
2 CAN-VCC
1
C2
C3
C4
C5
1nF
1nF
0.1uF
0.1uF
(Note - Can and RS232 Transceivers MUST
be powered down if VDDIO < 5.0V)
GND
U1
3
VCC
MCU-JCNTX-A
MCU-JCNRX-A
1
4
TXD
RXD
CANA-RS
8
2
J2
PG4
PG5
(CNTX-A)
(CNRX-A)
1
3
2
4
R1
0R
Rs
GND
VREF
5
CANH
CANL
7
6
P1
CANA-CANH
CANA-CANL
1
2
3
PCA82C250T
GND
GND
GND
Default State = Jumpers FITTED
U2
3
VCC
MCU-JCNTX-B
MCU-JCNRX-B
1
4
TXD
RXD
CANB-RS
8
2
J4
PG6
PG7
(CNTX-B)
(CNRX-B)
1
3
2
4
R2
0R
Rs
GND
VREF
5
CANH
CANL
7
6
P2
CANB-CANH
CANB-CANL
1
2
3
PCA82C250T
GND
GND
Freescale TECD Applications - East Kilbride
GND
Title
Rs = 0 Ohms for High Speed Operation. Replace
with non zero resistor to enable slope control.
Size
B
Date:
MAC7100 Evaluation Board
Document Number
Drawing 63A11505S
Rev
1.2
(MAC7100 EVB)
Friday, November 12, 2004
Sheet
12
of
15
3,12,14 PG[0..15]
2,3 VDDIO
2,3 VDDCore
PE[0..15]
PB[0..15]
PG[0..15]
VDDIO
VDDCore
P3_3V
ADDR3
ADDR2
(PC3)
(PC2)
(NC)
GND
PG7
(CNRX-B)
(NC)
3.3
PG10
(CNTX-D)
(NC)
GND
PG5
PG3
PG2
PG1
(CNRX-A)
(TXD-A)
(RXD-A)
(TXD-B)
(NC)
GND
PG14
(RXD-C)
(NC)
3.3
DATA2
DATA4
(PA2)
(PA4)
GND
(NC)
TM
TDO
(NC)
ADDR21 (PD10)
GND
ADDR19
ADDR18
PE15
PE14
PE13
(PD8)
(PD7)
(AN15)
(AN14)
(AN13)
PE11
(AN11)
GND
2,3
2,14
2,14
2,3
MCU-VRL
USR-VRH
USR-VRL
VDDA
MCU-VRL
USR-VRH
USR-VRL
VDDA
(AN09)
PE9
(AN07)
PE7
GND
3.3
Address / Data
and Control
signals to
Expansion
Connectors are
NOT buffered as
these are mux'd
with ports for
single chip
operation
PE5
PE3
(AN05)
(AN03)
GND
(NC)
(AN00)
PE0
(NC)
DATA8 (PA8)
DATA10 (PA10)
GND
(NC)
ADDR16 (PD5)
3.3
(NC)
ADDR13 (PC13)
GND
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
3,5,6,7,14,15 DATA[0..15]
2,3 MCU-VRH
3,6,15 TDI
3,6,15 TCLK
TGT-RSTx
MCU-RSTx
5,14
3,5,6
VDDR
2,3
RST-OUTx
VDDPLL
5,9,11,14
2,3,4
MCU-CS2x
MCU-BWE0x
3,8,14,15
3,5,8,14,15
ADDR[0..21]
GND
(5V)
(2.5V)
P19
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
3.3
I/O
GND
(PC1)
(PC0)
ADDR1
ADDR0
(SDA)
(SCL)
(SOUT-A)
PB0
PB1
PB3
GND
I/O
(CNTX-B)
(CNRX-D)
PG6
PG11
PB4
PB6
GND
(CNRX-C)
(CNTX-C)
PG9
PG8
PB8
PF14
(SCK-A)
(PCS1-A)
(NC)
(PCS5-A)
(EMIOS14)
GND
I/O
(CNTX-A)
(NC)
(NC)
(PC4)
PG4
ADDR4
3.3
GND
(RXD-B)
(TXD-C)
PG0
PG15
(PC6)
(PC7)
ADDR6
ADDR7
GND
I/O
(PA0)
(PA1)
DATA0
DATA1
GND
(PA3)
(PA5)
DATA3
DATA5
PF10
PF7
PF6
(EMIOS10)
(NC)
(EMIOS7)
(EMIOS6)
(NC)
GND
I/O
(PA6)
DATA6
(PD9)
TCLK
TDI
ADDR20
GND
PF3
PF1
(EMIOS3)
(EMIOS1)
3.3
ADDR8
ADDR10
(PC8)
(PC10)
GND
2.5
(NC)
(PD6)
ADDR17
ADDR11
PG12
(NC)
(AN12)
PE12
VDDR
GND
(PC11)
(RXD-D)
(NC)
GND
2.5
(AN10)
(NC)
PE10
MCU-VRH
GND
VDDA (Connected to net
VDDA , Pin 79)
VDDPLL
EXT-EXTAL
(PA15)
DATA15
GND
2.5
(AN08)
(AN06)
PE8
PE6
(AN04)
(AN02)
PE4
PE2
(PA14)
(PD11)
(NC)
(NC)
MCU-BWE1x (PD1)
(AN01)
(PA7)
PE1
DATA7
PB10
PB11
(PCS5-B)
(PCS2-B)
(PA9)
(PA11)
DATA9
DATA11
PB13
(SCK-B)
(NC)
GND
DATA14
MCU-OEx
GND
2.5
3.3
GND
GND
2.5
(PA12)
(PC15)
DATA12
ADDR15
MCU-TAx
MCU-XIRQx (PD3)
3.3
GND
(PC14)
(PC12)
ADDR14
ADDR12
MCU-IRQx (PD4)
MCU-CS0x (PD14)
GND
GND
GND
GND
AMP 120way SMT Connector
3,8,14 ADDR[0..21]
3,14
P3_3V
P5
3,6,15 TM
3,6,15 TDO
3,5,14
PB[0..15]
PG[0..15]
(5V)
(2.5V)
VDDIO
VDDCore
3.3
Expansion
Connector POWER
lines are
connected to
JUMPERED power
supply lines to
allow current
measurement /
supply isolation
on daughtercard
PF[0..15]
Conenctor 1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
2.5
GND
(SIN-A)
(NC)
PB2
(PCS0-A)
(PCS2-A)
PB5
PB7
2.5
GND
(EMIOS15) PF15
(EMIOS13) PF13
2.5
(EMIOS12) PF12
(PC5)
ADDR5
GND
(NC)
(EMIOS11) PF11
2.5
(EMIOS9)
(EMIOS8)
PF9
PF8
(EMIOS5)
(EMIOS4)
PF5
PF4
(EMIOS2)
(EMIOS0)
PF2
PF0
ADDR9
GND
2.5
GND
(PC9)
TGT-RSTx
MCU-RSTx
I/O
(TXD-D)
PG13
GND
VDDR
I/O
RST-OUTx
VDDPLL
GND
I/O
(NC)
(NC)
(PA13)
DATA13
GND
(PD12)
(PD0)
MCU-CS2x
MCU-BWE0x
(PCS0-B)
PB9
(NC)
(PCS1-B)
PB12
(SOUT-B)
(SIN-B)
PB14
PB15
(PD2)
MCU-CLKOUT
TGT-TAx
(PD13)
(PD15)
MCU-CS1x
MCU-RWx
EXPANSION CONNECTORS (DAUGHTERCARD)
PF[0..15]
3,6,14,15 PE[0..15]
I/O
GND
I/O
MCU-CLKOUT 4,5,6,8,14
TGT-TAx
11,14
GND
GND
GND
MCU-CS1x
MCU-RWx
3,8,14,15
3,7,8,14,15
MCU-CS0x
MCU-IRQx
MCU-XIRQx
MCU-TAx
MCU-BWE1x
MCU-OEx
EXT-EXTAL
3,8,14,15
3,11,14,15
3,5,14,15
3,11,14,15
3,5,8,14,15
3,7,8,14,15
4
AMP 120way SMT Connector
GND
DATA[0..15]
GND
ADDR[0..21]
Conenctor 2
GND
DATA[0..15]
MCU-CS0x
MCU-IRQx
MCU-XIRQx
MCU-TAx
MCU-BWE1x
MCU-OEx
EXT-EXTAL
MCU-VRH
TDI
TCLK
CONNECTORS MUST BE PLACED IN
ACCORDANCE WITH PCB SPECIFICATION
Freescale TECD Applications - East Kilbride
Title
AMP Connector Part number 179031-5 (8mm high, 0.8mm pitch 120way)
Suitable Mating connector - AMP 5-179009-5 (9mm high) or 5-179010-5 (13mm high)
Size
B
Date:
MAC7100 Evaluation Board
Document Number
Drawing 63A11505S
Rev
1.2
(MAC7100 EVB)
Friday, November 12, 2004
Sheet
13
of
15
USER CONNECTORS
DATA[0..15]
3,5,6,7,13,15 DATA[0..15]
PE[0..15]
PE[0..15]
3,6,13,15
USR-VRL
2,13
USR-VRH
2,13
PF[0..15]
3,5,13
P12
DATA0
DATA2
DATA4
DATA6
DATA8
DATA10
DATA12
DATA14
(PA0)
(PA2)
(PA4)
(PA6)
(PA8)
(PA10)
(PA12)
(PA14)
1
3
5
7
9
11
13
15
17
2
4
6
8
10
12
14
16
18
GND
(PA1)
(PA3)
(PA5)
(PA7)
(PA9)
(PA11)
(PA13)
(PA15)
DATA1
DATA3
DATA5
DATA7
DATA9
DATA11
DATA13
DATA15
P11
PE0 (AN00)
PE2 (AN02)
PE4 (AN04)
PE6 (AN06)
PE8 (AN08)
PE10 (AN10)
PE12 (AN12)
PE14 (AN14)
USR-VRH
1
3
5
7
9
11
13
15
17
19
GND
(AN01)
(AN03)
(AN05)
(AN07)
(AN09)
(AN11)
(AN13)
(AN15)
2
4
6
8
10
12
14
16
18
20
GND
PE1
PE3
PE5
PE7
PE9
PE11
PE13
PE15
USR-VRL
GND
PB[0..15]
3,13 PB[0..15]
P10
(SDA)
(SIN-A)
(SCK-A)
(PCS1-A)
(PCS5-A)
(PCS5-B)
(PCS1-B)
(SOUT-B)
1
3
5
7
9
11
13
15
17
2
4
6
8
10
12
14
16
18
GND
(SCL)
(SOUT-A)
(PCSO-A)
(PCS2-A)
(PCS0-B)
(PCS2-B)
(SCK-B)
(SIN-B)
PB1
PB3
PB5
PB7
PB9
PB11
PB13
PB15
PVDDIO
Simple POT to allow easy
evaluation of ADC
Mouser 317-2090-2K
RV1
2K Var
3
1
J17
PE0
1
GND
2
PB0
PB2
PB4
PB6
PB8
PB10
PB12
PB14
2
GND
PF[0..15]
ADDR[0..21]
3,8,13 ADDR[0..21]
P13
ADDR0
ADDR2
ADDR4
ADDR6
ADDR8
ADDR10
ADDR12
ADDR14
(PC0)
(PC2)
(PC4)
(PC6)
(PC8)
(PC10)
(PC12)
(PC14)
1
3
5
7
9
11
13
15
17
2
4
6
8
10
12
14
16
18
GND
3,5,13,15
3,5,8,13,15
3,5,8,13,15
4,5,6,8,13
3,11,13,15
MCU-XIRQx
MCU-BWE1x
MCU-BWE0x
MCU-CLKOUT
MCU-IRQx
MCU-CS2x
MCU-CS0x
TGT-RSTx
MCU-TAx
MCU-CS2x
MCU-CS0x
TGT-RSTx
MCU-TAx
TGT-TAx
RST-OUTx
MCU-RWx
MCU-CS1x
MCU-OEx
TGT-TAx
RST-OUTx
MCU-RWx
MCU-CS1x
MCU-OEx
P9
PF0
PF2
PF4
PF6
PF8
PF10
PF12
PF14
(EMIOS0)
1
(EMIOS2)
3
(EMIOS4)
5
(EMIOS6)
7
(EMIOS8)
9
(EMIOS10) 11
(EMIOS12) 13
(EMIOS14) 15
17
2
4
6
8
10
12
14
16
18
(EMIOS1)
(EMIOS3)
(EMIOS5)
(EMIOS7)
(EMIOS9)
(EMIOS11)
(EMIOS13)
(EMIOS15)
PF1
PF3
PF5
PF7
PF9
PF11
PF13
PF15
LEDs ACTIVE LOW
DS2
1
DS3
2
DS4
1
GND
2
DS5
GND
1
(PD0)
(PD4)
(PD6)
(PD8)
(PD10)
(PD12)
(PD14)
(Target RESET-IN)
1
3
5
7
9
11
13
15
17
19
21
PVDDIO
2
1
RN4
RPF8
RPF9
RPF10
RPF11
1
3
5
7
2
2
4
6
8
10
12
14
16
18
20
22
(PD1)
(PD3)
(PD5)
(PD7)
(PD9)
(PD11)
(PD13)
(PD15)
MCU-BWE1x
MCU-XIRQx
ADDR16
ADDR18
ADDR20
MCU-OEx
MCU-CS1x
MCU-RWx
RST-OUTx
TGT-TAx
1
J16
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
LPF8
LPF9
LPF10
LPF11
LPF12
LPF13
LPF14
LPF15
2
DS7
1
2
DS8
1
2
2
4
6
8
560R Net
DS6
P14
GND
11,13
5,9,11,13
3,7,8,13,15
3,8,13,15
3,7,8,13,15
ADDR1
ADDR3
ADDR5
ADDR7
ADDR9
ADDR11
ADDR13
ADDR15
GND
MCU-XIRQx
MCU-BWE1x
MCU-BWE0x
MCU-CLKOUT
MCU-IRQx
ADDR17
ADDR19
ADDR21
3,8,13,15
3,8,13,15
5,13
3,11,13,15
(PC1)
(PC3)
(PC5)
(PC7)
(PC9)
(PC11)
(PC13)
(PC15)
RN5
RPF12
RPF13
RPF14
RPF15
1
3
5
7
2
4
6
8
560R Net
DS9
1
2
ALL LEDS SMD YELLOW
Default State = Jumpers FITTED
GND
PG[0..15]
PG[0..15]
(Buffered MCU Reset-OUT)
3,12,13
P8
PG0
PG2
PG4
PG6
PG8
PG10
PG12
PG14
(RXD-B)
(RXD-A)
(CNTX-A)
(CNTX-B)
(CNTX-C)
(CNTX-D)
(RXD-D)
(RXD-C)
GND
1
3
5
7
9
11
13
15
17
2
4
6
8
10
12
14
16
18
(TXD-B)
(TXD-A)
(CNRX-A)
(CNRX-B)
(CNRX-C)
(CNRX-D)
(TXD-D)
(TXD-C)
PG1
PG3
PG5
PG7
PG9
PG11
PG13
PG15
Freescale TECD Applications - East Kilbride
GND
NOTE: All Connectors are 0.1" through-hole headers
Title
Size
B
Date:
MAC7100 Evaluation Board
Document Number
Drawing 63A11505S
Rev
1.2
(MAC7100 EVB)
Friday, November 12, 2004
Sheet
14
of
15
TERMINATION RESISTORS
2
PVDDIO
For Single Chip mode
operation, need to isolate
pullup resistors from pins
that are mux'd with single
chip functions (eg Port D)
J28
FM4
1
1
Fiducial Mark
FM3
RN7
3,5,8,13,14
3,5,8,13,14
3,5,13,14
3,11,13,14
MCU-BWE0x
MCU-BWE1x
MCU-XIRQx
MCU-IRQx
MCU-BWE0x
MCU-BWE1x
MCU-XIRQx
MCU-IRQx
1
3
5
7
FM7
FM8
1
FM1
2
4
6
8
1
1
Fiducial Mark
FM2
1
1
Fiducial Mark
1
1
Fiducial Mark
1
Fiducial Mark
FM5
1
1
Fiducial Mark
1
FM6
1
1
Fiducial Mark
1
1
Fiducial Mark
10K Net
RN8
3,7,8,13,14
3,8,13,14
3,8,13,14
3,8,13,14
MCU-OEx
MCU-CS0x
MCU-CS1x
MCU-CS2x
MCU-OEx
MCU-CS0x
MCU-CS1x
MCU-CS2x
1
3
5
7
MCU-RWx
R15
10K
MCU-TAx
R14
10K
TDI
TM
TCLK
TDO
1
3
5
7
2
4
6
8
10K Net
3,7,8,13,14 MCU-RWx
3,11,13,14 MCU-TAx
RN6
3,6,13
3,6,13
3,6,13
3,6,13
TDI
TM
TCLK
TDO
J18
10K Net
2
4
6
8
1
2
3
JTAG PORT
GND
Pullups always active
3,5,6,7,13,14 DATA[0..15]
DATA[0..15]
DATA2
3,6,13,14 PE[0..15]
R5
J14
10K
1
Nexus EVTI
Pullup
Enable
PE[0..15]
PE2
R7
10K
2
J20
1
2
Freescale TECD Applications - East Kilbride
All RESET Pullup Resistors are shown on Reset Circuitry page
Title
Size
B
Date:
MAC7100 Evaluation Board
Document Number
Drawing 63A11505S
Rev
1.2
(MAC7100 EVB)
Friday, November 12, 2004
Sheet
15
of
15
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