NXP i.MX1 Reference guide

NXP i.MX1 Reference guide
MC9328MX1
i.MX Integrated Portable
System Processor
Reference Manual
Document Number: MC9328MX1RM
Rev. 6.1
06/2007
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
[email protected]
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
[email protected]
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
[email protected]
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064, Japan
0120 191014 or +81 3 5437 9125
[email protected]
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
[email protected]
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-521-6274 or 303-675-2140
Fax: 303-675-2150
[email protected]
Information in this document is provided solely to enable system and software implementers to use
Freescale Semiconductor products. There are no express or implied copyright licenses granted
hereunder to design or fabricate any integrated circuits or integrated circuits based on the information
in this document.
Freescale Semiconductor reserves the right to make changes without further notice to any products
herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages. “Typical” parameters
that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating parameters,
including “Typicals”, must be validated for each customer application by customer’s technical experts.
Freescale Semiconductor does not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized for use as components
in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer purchase or use
Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was
negligent regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. ARM and the
ARM POWERED logo are the registered trademarks of ARM Limited. ARM9, ARM920T,
ARM9TDMI, ARMv4T, ARM7, ARM7TDMI, Thumb, and StrongARM are trademarks of ARM Limited.
All other product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc. 2003, 2004, 2005, 2006, 2007. All rights reserved.
Contents
About This Book
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxi
Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxi
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxiii
Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxiv
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxiv
Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxiv
Chapter 1
Introduction
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
ARM920T Microprocessor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
AHB to IP Bus Interfaces (AIPIs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
External Interface Module (EIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
SDRAM Controller (SDRAMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Clock Generation Module (CGM) and Power Control Module . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Three Universal Asynchronous Receiver/Transmitters
(UART 1, UART 2, and UART 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Two Serial Peripheral Interfaces (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Two General-Purpose 32-Bit Counters/Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Real-Time Clock/Sampling Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
LCD Controller (LCDC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Pulse-Width Modulation (PWM) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Universal Serial Bus (USB) Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Multimedia Card and Secure Digital (MMC/SD) Host Controller. . . . . . . . . . . . . . . . . . . . . . . 1-7
Memory Stick® Host Controller (MSHC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
SmartCard Interface Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Direct Memory Access Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Synchronous Serial Interface and Inter-IC Sound (SSI/I2S) Module . . . . . . . . . . . . . . . . . . . . . 1-8
Inter-IC (I2C) Bus Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Video Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
General-Purpose I/O (GPIO) Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Bootstrap Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Analog Signal Processing (ASP) Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Multimedia Accelerator (MMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Chapter 2
Signal Descriptions and Pin Assignments
2.1
Signal and Pin Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
iii
Chapter 3
Memory Map
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.2
Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip MCU Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Double Map Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-1
3-4
3-4
3-5
3-5
3-6
Chapter 4
ARM920T Processor
4.1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
ARM920T Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1
Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2
Cache Lock-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3
Write Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4
PATAG RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.5
MMUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.6
System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.7
Control Coprocessor (CP15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
ARMv4T Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2
Modes and Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3
Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.4
Exception Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.5
Conditional Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Four Classes of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1
Data Processing Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2
Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2.1
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2.2
Block Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.3
Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.3.1
Branch with Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.4
Coprocessor Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
The ARM9 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6
The ARM Thumb Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.1
ARM920T Modes and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
4-2
4-3
4-3
4-3
4-3
4-3
4-3
4-4
4-4
4-4
4-4
4-5
4-5
4-5
4-5
4-5
4-6
4-6
4-6
4-7
4-7
4-7
4-7
4-8
4-9
Chapter 5
Embedded Trace Macrocell (ETM)
5.1
5.2
Introduction to the ETM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Programming and Reading ETM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
MC9328MX1 Reference Manual, Rev. 6.1
iv
Freescale Semiconductor
5.3
Pin Configuration for ETM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Chapter 6
Reset Module
6.1
6.1.1
6.1.2
6.2
6.2.1
Functional Description of the Reset Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ARM920T Processor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Source Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1
6-1
6-2
6-3
6-3
Chapter 7
AHB to IP Bus Interface (AIPI)
7.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.2
General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.2.1
Peripheral Size Registers[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.2.1.1
AIPI1 Peripheral Size Register 0 and AIPI2 Peripheral Size Register 0 . . . . . . . . . . . 7-10
7.2.1.2
AIPI1 Peripheral Size Register 1 and AIPI2 Peripheral Size Register 1 . . . . . . . . . . . 7-11
7.2.2
Peripheral Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
7.2.3
Peripheral Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.2.4
Time-Out Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.3
Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
7.3.1
Data Access to 8-Bit Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
7.3.2
Data Access to 16-Bit Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
7.3.3
Data Access to 32-Bit Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
7.3.4
Special Consideration for Non-Natural Size Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
Chapter 8
System Control
8.1
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.1
Silicon ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.2
Function Multiplexing Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.3
Global Peripheral Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.4
Global Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2
System Boot Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-1
8-2
8-3
8-4
8-6
8-7
Chapter 9
Bootstrap Mode Operation
9.1
9.1.1
9.1.2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Entering Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Bootstrap Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
v
9.1.3
9.1.4
9.1.5
9.2
9.3
9.4
9.5
9.6
Registers Used in Bootloader Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Up the RS-232 Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing the Speed of Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-Record Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Buffer Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simple Read/Write Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootloader Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-3
9-3
9-3
9-3
9-3
9-5
9-7
9-7
Chapter 10
Interrupt Controller (AITC)
10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.3 AITC Interrupt Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.4 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.4.1
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.4.2
Normal Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10.4.3
Interrupt Enable Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.4
Interrupt Disable Number Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.4.5
Interrupt Enable Register High and Interrupt Enable Register Low. . . . . . . . . . . . . . . . . 10-11
10.4.5.1
Interrupt Enable Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.4.5.2
Interrupt Enable Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.4.6
Interrupt Type Register High and Interrupt Type Register Low . . . . . . . . . . . . . . . . . . . 10-13
10.4.6.1
Interrupt Type Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.4.6.2
Interrupt Type Register Low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.4.7
Normal Interrupt Priority Level Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.4.7.1
Normal Interrupt Priority Level Register 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.4.7.2
Normal Interrupt Priority Level Register 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.4.7.3
Normal Interrupt Priority Level Register 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.4.7.4
Normal Interrupt Priority Level Register 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10.4.7.5
Normal Interrupt Priority Level Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
10.4.7.6
Normal Interrupt Priority Level Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
10.4.7.7
Normal Interrupt Priority Level Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21
10.4.7.8
Normal Interrupt Priority Level Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
10.4.8
Normal Interrupt Vector and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
10.4.9
Fast Interrupt Vector and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
10.4.10
Interrupt Source Register High and Interrupt Source Register Low. . . . . . . . . . . . . . . . . 10-25
10.4.10.1
Interrupt Source Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
10.4.10.2
Interrupt Source Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26
10.4.11
Interrupt Force Register High and Interrupt Force Register Low. . . . . . . . . . . . . . . . . . . 10-27
10.4.11.1
Interrupt Force Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27
10.4.11.2
Interrupt Force Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28
10.4.12
Normal Interrupt Pending Register High and Normal Interrupt Pending Register Low . 10-29
10.4.12.1
Normal Interrupt Pending Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29
MC9328MX1 Reference Manual, Rev. 6.1
vi
Freescale Semiconductor
10.4.12.2
Normal Interrupt Pending Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.13 Fast Interrupt Pending Register High and Fast Interrupt Pending Register Low . . . . . . .
10.4.13.1
Fast Interrupt Pending Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.13.2
Fast Interrupt Pending Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5 ARM920T Processor Interrupt Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5.1
ARM920T Processor Prioritization of Exception Sources . . . . . . . . . . . . . . . . . . . . . . . .
10.5.2
AITC Prioritization of Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5.3
Assigning and Enabling Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5.4
Enabling Interrupts Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5.5
Typical Interrupt Entry Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5.6
Writing Reentrant Normal Interrupt Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-30
10-31
10-31
10-32
10-33
10-33
10-33
10-33
10-33
10-34
10-35
Chapter 11
External Interface Module (EIM)
11.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2 EIM I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2.1
Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2.2
Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2.3
Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2.4
Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.4.1
OE—Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.4.2
EB [3:0]—Enable Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.4.3
DTACK—Data Transfer Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.5
Chip Select Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.5.1
Chip Select 0 (CS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.5.2
Chip Select 1–Chip Select 5 (CS1–CS5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.6
Burst Mode Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.6.1
BCLK—Burst Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.6.2
LBA—Load Burst Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.6.3
ECB—End Current Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.3 Pin Configuration for EIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.4 Typical EIM System Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.5 EIM Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.5.1
Configurable Bus Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.5.2
Programmable Output Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.5.3
Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.5.4
Burst Clock Divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.5.5
Burst Clock Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.5.6
Page Mode Emulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.5.7
Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.6 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
11.6.1
Chip Select 0 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.6.1.1
Chip Select 0 Upper Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.6.1.2
Chip Select 0 Lower Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
vii
11.6.2
11.6.2.1
11.6.2.2
11.6.3
Chip Select 1–Chip Select 5 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Select 1–Chip Select 5 Upper Control Registers . . . . . . . . . . . . . . . . . . . . . . . .
Chip Select 1–Chip Select 5 Lower Control Registers. . . . . . . . . . . . . . . . . . . . . . . .
EIM Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-12
11-12
11-14
11-20
Chapter 12
Phase-Locked Loop and Clock Controller
12.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2.1
Low Frequency Clock Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2.2
High Frequency Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.3 DPLL Output Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3.1
DPLL Phase and Frequency Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.4 MC9328MX1 Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.4.1
PLL Operation at Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.4.2
PLL Operation at Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.4.3
ARM920T Processor Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.4.4
SDRAM Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.4.5
Power Management in the Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.5 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.5.1
Clock Source Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.5.2
Peripheral Clock Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.5.3
Programming Digital Phase Locked Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.5.3.1
MCU PLL Control Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.5.3.2
MCU PLL and System Clock Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.5.4
Generation of 48 MHz Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.5.4.1
System PLL Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.5.4.2
System PLL Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
Chapter 13
DMA Controller
13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.3 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.3.1
Big Endian and Little Endian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.4 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.4.1
General Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.4.1.1
DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.4.1.2
DMA Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
13.4.1.3
DMA Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.4.1.4
DMA Burst Time-Out Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.4.1.5
DMA Request Time-Out Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13.4.1.6
DMA Transfer Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
13.4.1.7
DMA Buffer Overflow Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
MC9328MX1 Reference Manual, Rev. 6.1
viii
Freescale Semiconductor
13.4.1.8
DMA Burst Time-Out Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2
2D Memory Registers (A and B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2.1
W-Size Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2.2
X-Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2.3
Y-Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3
Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3.1
Channel Source Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3.2
Destination Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3.3
Channel Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3.4
Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3.5
Channel Request Source Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3.6
Channel Burst Length Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3.7
Channel Request Time-Out Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3.8
Channel 0 Bus Utilization Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.5 DMA Request Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-15
13-16
13-16
13-17
13-18
13-18
13-19
13-20
13-21
13-22
13-25
13-26
13-27
13-28
13-30
Chapter 14
Watchdog Timer Module
14.1 General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.1
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.2
Watchdog During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.2.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.2.2
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3 Watchdog After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.1
Initial Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.2
Countdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.3
Reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.4
Time-Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.5
Halting the Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4 Watchdog Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.1
Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.2
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.6 Watchdog Timer I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.7 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.7.1
Watchdog Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.7.2
Watchdog Service Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.7.3
Watchdog Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14-1
14-1
14-1
14-2
14-2
14-2
14-2
14-2
14-2
14-2
14-3
14-3
14-3
14-3
14-3
14-4
14-5
14-6
14-6
14-7
14-8
Chapter 15
Analog Signal Processor (ASP)
15.1
15.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
ASP Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
ix
15.3 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.4 Pen ADC (PADC) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.4.1
Current-Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.4.2
Sample Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
15.4.3
Auto Zero Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.4.4
Pen-Down Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.4.5
Pen-Up Detection (Method 1 - Compare Value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.4.6
Pen Up Detection (Method 2 - Detect Rising Edge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.4.7
Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.5 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.5.1
ASP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.5.2
Pen A/D Sample Rate Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
15.5.3
Compare Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
15.5.4
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
15.5.5
Interrupt/Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
15.5.6
Pen Sample FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
15.5.7
Clock Divide Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17
15.5.8
ASP FIFO Pointer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18
Chapter 16
Bluetooth Accelerator (BTA)
16.1 Bluetooth Primer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.2 BTA Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.3 Module Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.3.1
Bluetooth Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.3.1.1
IP Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.3.1.2
Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.3.1.2.1
Bluetooth Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.3.1.2.2
Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16.3.1.3
Bluetooth Pipeline Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
16.3.1.3.1
HEC/CRC Generator and Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
16.3.1.3.2
Encryption and Decryption Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
16.3.1.3.3
Whitening/De-Whitening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
16.3.1.3.4
FEC Coding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
16.3.1.4
Bit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
16.3.1.5
Correlator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12
16.3.1.6
Bluetooth Application Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.3.1.7
Hop Selection Co-Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.3.1.8
Radio Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.3.1.8.1
Frequency Synthesizer and Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14
16.3.1.8.2
Pulse Width Modulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14
16.3.1.8.3
Radio Module Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
16.3.2
Wake-Up Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18
16.4 Pin Configuration for BTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20
MC9328MX1 Reference Manual, Rev. 6.1
x
Freescale Semiconductor
16.5 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.1
Sequencer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.1.1
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.1.2
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.1.3
Packet Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.1.4
Payload Header Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.2
Bluetooth Clocks Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.2.1
Native Count Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.2.2
Estimated Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.2.3
Offset Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.2.4
Native Clock Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.2.5
Native Clock High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.2.6
Estimated Clock Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.2.7
Estimated Clock High Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.2.8
Offset Clock Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.2.9
Offset Clock High Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.3
Bluetooth Pipeline Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.3.1
HECCRC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.3.2
White Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.3.3
Encryption Control X13 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.4
Radio Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.4.1
Correlation Time Setup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.4.2
Correlation Time Stamp Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.4.3
RF GPO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.4.4
PWM Received Signal Strength Indicator Register . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.4.5
Time A & B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.4.6
Time C & D Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.4.7
PWM TX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.4.8
RF Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.4.9
RF Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.4.10
RX Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.4.11
TX Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.5
Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.5.1
Bluetooth Application Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.6
Correlator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.6.1
Threshold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.6.2
Correlation Max Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.6.3
Synch Word 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.6.4
Synch Word 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.6.5
Synch Word 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.6.6
Synch Word 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.7
Bit Buffer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.7.1
Buffer Word Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.8
Wake-Up Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.8.1
Wake-Up 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-21
16-27
16-27
16-28
16-31
16-32
16-33
16-33
16-34
16-35
16-36
16-37
16-38
16-39
16-40
16-41
16-42
16-42
16-43
16-44
16-45
16-45
16-46
16-47
16-48
16-49
16-50
16-51
16-52
16-54
16-56
16-57
16-58
16-58
16-59
16-59
16-61
16-62
16-63
16-64
16-65
16-66
16-66
16-68
16-68
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
xi
16.5.8.2
16.5.8.3
16.5.8.4
16.5.8.5
16.5.8.6
16.5.8.7
16.5.9
16.5.9.1
16.5.10
16.5.10.1
16.5.10.2
16.5.10.3
16.5.10.4
16.5.10.5
16.5.10.6
16.5.10.7
16.5.10.8
16.5.11
16.5.11.1
16.5.11.2
16.5.11.3
16.5.11.4
16.5.11.5
16.5.11.6
16.5.12
16.5.12.1
16.5.13
16.5.13.1
16.5.13.2
16.5.14
16.5.14.1
16.5.14.2
Wake-Up 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-Up Delta4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-Up 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-Up Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-Up Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-Up Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Word0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Word1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Word2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Word3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Write Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Read Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Hopping Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hop 0 (Frequency In) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hop 1 (Frequency In) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hop 2 (Frequency In) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hop 3 (Frequency In) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hop 4 (Frequency In) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hop Frequency Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Joint Detect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronization Metric Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronize Frequency Carrier Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Reverse Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Word Reverse Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Byte Reverse Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-69
16-70
16-71
16-72
16-73
16-74
16-75
16-75
16-76
16-76
16-77
16-78
16-79
16-80
16-81
16-83
16-85
16-85
16-86
16-86
16-87
16-88
16-88
16-89
16-90
16-90
16-91
16-91
16-92
16-93
16-93
16-94
Chapter 17
Multimedia Accelerator (MMA)
17.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.2 MMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.2.1
Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.2.2
MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.2.2.1
Basic MAC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.2.2.2
Data Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.2.2.3
Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.2.3
DCT/iDCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17-1
17-1
17-1
17-2
17-2
17-2
17-3
17-4
17-5
MC9328MX1 Reference Manual, Rev. 6.1
xii
Freescale Semiconductor
17.3.1
17.3.1.1
17.3.1.2
17.3.1.3
17.3.1.4
17.3.1.5
17.3.1.6
17.3.1.7
17.3.1.8
17.3.1.9
17.3.1.10
17.3.2
17.3.3
17.3.3.1
17.3.3.2
17.3.3.3
17.3.3.4
17.3.3.5
17.3.3.6
17.3.4
17.3.4.1
17.3.4.2
17.3.4.3
17.3.4.4
17.3.4.5
17.3.4.6
17.3.5
17.3.5.1
17.3.5.2
17.3.5.3
17.3.5.4
17.3.5.5
17.3.5.6
17.3.5.7
17.3.5.8
17.3.5.9
17.3.5.10
17.3.5.11
MMA MAC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
MMA MAC Module Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
MMA MAC Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
MMA MAC Multiply Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
MMA MAC Accumulate Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
MMA MAC Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
MMA MAC Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
MMA MAC FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
MMA MAC FIFO Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
MMA MAC Burst Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14
MMA MAC Bit Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15
MMA MAC XY Count Accumulate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
MMA MAC X Register Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
MMA MAC X Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
MMA MAC X Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18
MMA MAC X Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18
MMA MAC X Modify Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
MMA MAC X Increment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20
MMA MAC X Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20
MMA MAC Y Register Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22
MMA MAC Y Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22
MMA MAC Y Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22
MMA MAC Y Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23
MMA MAC Y Modify Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24
MMA MAC Y Increment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24
MMA MAC Y Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25
MMA DCT/iDCT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26
DCT/iDCT Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26
DCT/iDCT Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27
DCT/iDCT IRQ Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-28
DCT/iDCT IRQ Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29
DCT/iDCT Source Data Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30
DCT/iDCT Destination Data Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30
DCT/iDCT X-Offset Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-31
DCT/iDCT Y-Offset Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-31
DCT/iDCT XY Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32
DCT/iDCT Skip Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-33
DCT/iDCT Data FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-34
Chapter 18
Serial Peripheral Interface Modules (SPI 1 and SPI 2)
18.1 SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.2.1
Phase and Polarity Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
xiii
18.2.2
Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.2.3
Pin Configuration for SPI 1 and SPI 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.3.1
Receive (RX) Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
18.3.2
Transmit (TX) Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7
18.3.3
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8
18.3.4
Interrupt Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10
18.3.5
Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12
18.3.6
Sample Period Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13
18.3.7
DMA Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14
18.3.8
Soft Reset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15
Chapter 19
LCD Controller
19.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.3 LCDC Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.3.1
LCD Screen Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.3.2
Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.3.3
Display Data Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.3.4
Black-and-White Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7
19.3.5
Gray-Scale Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7
19.3.6
Color Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8
19.3.7
Frame Rate Modulation Control (FRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10
19.3.8
Panel Interface Signals and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11
19.3.8.1
Pin Configuration for LCDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11
19.3.8.2
Passive Matrix Panel Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12
19.3.8.3
Passive Panel Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13
19.3.9
8 bpp Mode Color STN Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14
19.3.9.1
Active Matrix Panel Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14
19.3.9.2
Active Panel Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16
19.4 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18
19.4.1
Screen Start Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20
19.4.2
Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21
19.4.3
Virtual Page Width Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22
19.4.4
Panel Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23
19.4.5
Horizontal Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26
19.4.6
Vertical Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27
19.4.7
Panning Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28
19.4.8
LCD Cursor Position Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-29
19.4.9
LCD Cursor Width Height and Blink Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-30
19.4.10
LCD Color Cursor Mapping Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31
19.4.11 Sharp Configuration 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-32
19.4.12
PWM Contrast Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-34
MC9328MX1 Reference Manual, Rev. 6.1
xiv
Freescale Semiconductor
19.4.13
19.4.14
19.4.15
19.4.16
19.4.17
19.4.17.1
19.4.17.2
19.4.17.3
19.4.17.4
19.4.17.5
19.4.17.6
19.4.17.7
Refresh Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mapping RAM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
One Bit/Pixel Monochrome Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Four Bits/Pixel Gray-Scale Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Four Bits/Pixel Passive Matrix Color Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Eight Bits/Pixel Passive Matrix Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Four Bits/Pixel Active Matrix Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Eight Bits/Pixel Active Matrix Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twelve Bits/Pixel and Sixteen Bits/Pixel Active Matrix Color Mode . . . . . . . . . . . .
19-35
19-36
19-37
19-38
19-39
19-39
19-39
19-40
19-40
19-41
19-41
19-42
Chapter 20
Multimedia Card/Secure Digital Host Controller Module (MMC/SD)
20.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.2 Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.3 MMC/SD Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
20.4 MMC/SD Module and Card Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
20.4.1
MMC and SD Card Pin Assignments and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
20.4.2
Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
20.4.3
Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
20.4.4
Pin Configuration for the MMC/SD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
20.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
20.5.1
DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
20.5.1.1
DMA Burst Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
20.5.1.2
Write-Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
20.5.2
Memory Controller (Register Handler) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
20.5.2.1
SD I/O—IRQ and ReadWait Service Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
20.5.2.2
Card Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
20.5.2.3
MMC/SD Module Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9
20.5.3
Logic and Command Interpreters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9
20.5.4
System Clock Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11
20.5.4.1
Card Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12
20.6 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12
20.6.1
MMC/SD Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13
20.6.2
MMC/SD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-15
20.6.3
MMC/SD Clock Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18
20.6.4
MMC/SD Command and Data Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19
20.6.5
MMC/SD Response Time-Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21
20.6.6
MMC/SD Read Time-Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22
20.6.7
MMC/SD Block Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-23
20.6.8
MMC/SD Number of Blocks Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24
20.6.9
MMC/SD Revision Number Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-25
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
xv
20.6.10
MMC/SD Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.6.11
Commands and Arguments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.6.11.1
MMC/SD Command Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.6.11.2
MMC/SD Higher Argument Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.6.11.3
MMC/SD Lower Argument Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.6.12
MMC/SD Response FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.6.13
MMC/SD Buffer Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7 Functional Example for the MMC/SD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.1
Basic Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.2
Card Identification State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.2.1
Card Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.2.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.2.3
Voltage Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.2.4
Card Registry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.3
Card Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.3.1
Block Access: Block Write and Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.3.1.1
Block Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.3.1.2
Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.3.2
Stream Access—Stream Write and Stream Read (MMC Only). . . . . . . . . . . . . . . . .
20.7.3.2.1
Stream Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.3.2.2
Stream Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.3.3
Erase—Group Erase (MMC Only) and Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.3.4
Wide Bus Selection or Deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.4
Protection Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.4.1
Card Internal Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.4.2
Mechanical Write Protect Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.4.3
Password Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.4.3.1
Setting the Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.4.3.2
Resetting the Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.4.3.3
Locking a Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.4.3.4
Unlocking the Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.4.3.5
Forcing Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.5
Card Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.6
SD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.7
SD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.7.1
SD I/O Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.7.2
SD I/O Suspend and Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.7.3
SD I/O ReadWait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.8
Commands and Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.8.1
Application-Specific and General Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.8.2
Command Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.8.3
Command Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.8.4
Commands for the MMC/SD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.8.5
Response Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.7.8.5.1
R1—Normal Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-26
20-28
20-29
20-29
20-30
20-31
20-32
20-32
20-33
20-33
20-33
20-34
20-34
20-37
20-38
20-38
20-38
20-41
20-44
20-44
20-45
20-46
20-47
20-47
20-48
20-48
20-48
20-49
20-49
20-50
20-50
20-51
20-51
20-53
20-54
20-54
20-55
20-55
20-56
20-57
20-57
20-58
20-58
20-62
20-62
MC9328MX1 Reference Manual, Rev. 6.1
xvi
Freescale Semiconductor
20.7.8.5.2
20.7.8.5.3
20.7.8.5.4
20.7.8.5.5
20.7.8.5.6
20.7.8.5.7
20.7.8.5.8
R1b—Normal Response with Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R2—CID, CSD Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R3—OCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R4—Fast I/O for MMC Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R4b—SD I/O Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R5—Interrupt Request (for MMC Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R6—SD I/O Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-63
20-63
20-63
20-64
20-64
20-64
20-64
Chapter 21
Memory Stick Host Controller (MSHC) Module
21.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.3 Block Diagram and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.4 Memory Stick Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
21.4.1
Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.4.2
Pin Configuration for the MSHC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.5 Memory Stick Host Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
21.5.1
Data FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
21.5.2
Bus State Control Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
21.5.3
MSHC Module Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
21.5.3.1
Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
21.5.3.2
SDIO Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.5.4
Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.5.5
Power Save Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
21.5.5.1
Register Access During Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
21.5.5.2
Register Access while MSHC Module is Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
21.5.6
Auto Command Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
21.5.7
Serial Clock Divider Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11
21.5.8
System-Level DMA Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11
21.6 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12
21.7 Memory Stick Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13
21.7.1
Memory Stick Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14
21.7.2
Memory Stick Transmit FIFO Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15
21.7.3
Memory Stick Receive FIFO Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16
21.7.4
Memory Stick Interrupt Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16
21.7.5
Memory Stick Parallel Port Control/Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-18
21.7.6
Memory Stick Control 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-19
21.7.7
Memory Stick Auto Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-20
21.7.8
Memory Stick FIFO Access Error Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . 21-21
21.7.9
Memory Stick Serial Clock Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22
21.7.10
Memory Stick DMA Request Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23
21.8 Programmer’s Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-24
21.8.1
Memory Stick Serial Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-24
21.8.2
Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
xvii
21.8.2.1
21.8.2.2
21.8.3
21.8.4
21.8.4.1
21.8.4.2
21.8.5
21.8.5.1
21.8.5.2
21.8.5.3
Write Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transfer Protocol Command (TPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protocol Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two State Access Mode Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus State Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transfer Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21-26
21-27
21-27
21-28
21-28
21-30
21-31
21-31
21-31
21-32
Chapter 22
Pulse-Width Modulator (PWM)
22.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.2 PWM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.2.1
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.2.2
Pin Configuration for PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.3 PWM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.3.1
Playback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.3.2
Tone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.3.3
Digital-to-Analog Converter (D/A) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.4 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.4.1
PWM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.4.1.1
HCTR and BCTR Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.4.2
PWM Sample Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.4.3
PWM Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.4.4
PWM Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22-1
22-1
22-1
22-2
22-2
22-2
22-3
22-3
22-3
22-3
22-6
22-6
22-7
22-8
Chapter 23
Real-Time Clock (RTC)
23.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
23.1.1
Prescaler and Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
23.1.2
Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.1.3
Sampling Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.1.4
Minute Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
23.2.1
RTC Days Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
23.2.2
RTC Hours and Minutes Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.2.3
RTC Seconds Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7
23.2.4
RTC Day Alarm Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8
23.2.5
RTC Hours and Minutes Alarm Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9
23.2.6
RTC Seconds Alarm Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10
23.2.7
RTC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11
23.2.8
RTC Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12
MC9328MX1 Reference Manual, Rev. 6.1
xviii
Freescale Semiconductor
23.2.9
23.2.10
RTC Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14
Stopwatch Minutes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-15
Chapter 24
SDRAM Memory Controller
24.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
24.3 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.3.1
SDRAM Command Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.3.2
Page and Bank Address Comparators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.3.3
Row and Column Address Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.3.4
Data Aligner and Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.3.5
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.3.6
Refresh Request Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.3.7
Powerdown Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4
24.3.8
DMA Operation with the SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4
24.3.9
SDCLK—SDRAM Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
24.3.10
SDCKE0, SDCKE1—SDRAM Clock Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
24.3.11
CSD0, CSD1—SDRAM Chip-Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
24.3.12
DQ [31:0]—Data Bus (Internal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
24.3.13
MA [11:0]—Multiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
24.3.14
SDBA [4:0], SDIBA [3:0]—Non-Multiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . 24-6
24.3.15
DQM3, DQM2, DQM1, DQM0—Data Qualifier Mask . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
24.3.16
SDWE—Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
24.3.17 RAS—Row Address Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
24.3.18 CAS—Column Address Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
24.3.19
RESET_SF—Reset or Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
24.3.20
Pin Configuration for SDRAMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7
24.4 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
24.4.1
SDRAM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
24.4.2
SDRAM Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16
24.4.3
Miscellaneous Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-17
24.5 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18
24.5.1
SDRAM and SyncFlash Command Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18
24.5.2
Normal Read/Write Mode (SMODE = 000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19
24.5.3
Precharge Command Mode (SMODE = 001). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24
24.5.4
Auto-Refresh Mode (SMODE = 010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-25
24.5.5
Set Mode Register Mode (SMODE = 011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-25
24.5.6
SyncFlash Load Command Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26
24.5.7
SyncFlash Program Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27
24.6 General Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28
24.6.1
Address Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-29
24.6.1.1
Multiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-29
24.6.1.2
Non-Multiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-31
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
xix
24.6.1.3
Bank Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.6.2
Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.6.3
Self-Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.6.3.1
Self-Refresh During RESET_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.6.3.2
Self-Refresh During Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.6.3.3
Powerdown Operation During Reset and Low-Power Modes . . . . . . . . . . . . . . . . . .
24.6.4
Clock Suspend Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.6.4.1
Powerdown (Precharge Powerdown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.6.4.2
Clock Suspend (Active Powerdown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.6.4.3
Refresh During Powerdown or Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7 SDRAM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.1
SDRAM Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.2
Configuring Controller for SDRAM Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.2.1
CAS Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.2.2
Row Precharge Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.2.3
Row-to-Column Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.2.4
Row Cycle Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.2.5
Refresh Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.2.6
Memory Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.3
SDRAM Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.4
Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.5
Mode Register Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.5.1
Example 1—256 Mbit SDRAM Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.5.2
Example 2—64 Mbit SDRAM Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.7.6
SDRAM Memory Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.8 SyncFlash Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.8.1
SyncFlash Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.8.2
SyncFlash Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.8.3
Booting From SyncFlash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.8.4
SyncFlash Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.8.5
SyncFlash Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.8.6
Clock Suspend Timer Use with SyncFlash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.8.7
Powerdown Operation with SyncFlash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.9 Deep Powerdown Operation with SyncFlash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24-31
24-32
24-33
24-33
24-33
24-33
24-35
24-35
24-36
24-36
24-37
24-37
24-38
24-38
24-38
24-38
24-38
24-39
24-39
24-57
24-59
24-62
24-62
24-64
24-67
24-67
24-67
24-68
24-68
24-68
24-71
24-72
24-72
24-72
Chapter 25
SmartCard Interface Module (SIM)
25.1 Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.2 IP Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.2.1
SIM Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.2.2
SIM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.2.3
SIM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.2.4
SIM Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.2.5
SIM General Purpose Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25-1
25-1
25-2
25-2
25-2
25-3
25-3
MC9328MX1 Reference Manual, Rev. 6.1
xx
Freescale Semiconductor
25.2.6
SIM LRC and CRC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
25.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
25.3.1
SIM Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
25.3.1.1
Baud Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5
25.3.1.2
Transmitter Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5
25.3.1.3
Receiver Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5
25.3.1.4
Port Controller Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5
25.3.2
SIM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5
25.3.2.1
Transmit State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6
25.3.2.2
Transmit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7
25.3.2.3
Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7
25.3.2.4
Transmit Guard Time Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8
25.3.2.5
Transmit NACK Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8
25.3.2.6
Transmit Data Convention Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9
25.3.3
SIM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10
25.3.3.1
Receive State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10
25.3.3.2
Data Sampling / Voting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11
25.3.3.3
Start Bit Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12
25.3.3.4
Parity Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12
25.3.3.5
Framing Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12
25.3.3.6
NACK Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
25.3.3.7
Initial Character Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
25.3.4
Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14
25.3.4.1
Overrun Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14
25.3.5
Character Wait Time Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
25.4 SIM Port Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
25.4.1
SmartCard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
25.4.2
SmartCard Presence Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16
25.4.3
SmartCard Automatic Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16
25.4.4
SIM General Purpose Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16
25.4.5
SIM LRC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17
25.4.6
SIM CRC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17
25.4.7
SIM Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19
25.5 Pin Configuration for SIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19
25.6 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20
25.6.1
Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23
25.6.2
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-24
25.6.3
Receive Threshold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-26
25.6.4
Transmit/Receive Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27
25.6.5
Transmit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-28
25.6.6
Receive Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-30
25.6.7
Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-32
25.6.8
Port Transmit Buffer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-33
25.6.9
Receive Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-34
25.6.10
Port Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-35
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
xxi
25.6.11
Transmit Threshold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.6.12
Transmit Guard Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.6.13
Open-Drain Configuration Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.6.14
Reset Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.6.15
Character Wait Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.6.16
General Purpose Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.6.17
Divisor Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.7 Functional Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.7.1
Configuring the SIM for Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.7.2
Configuring the SIM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.7.3
Configuring the SIM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.7.4
Configuring the SIM General Purpose Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.7.5
Configuring the SIM Linear Redundancy Check Block. . . . . . . . . . . . . . . . . . . . . . . . . .
25.7.6
Configuring the SIM Cyclic Redundancy Check Block. . . . . . . . . . . . . . . . . . . . . . . . . .
25.8 Using the SIM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.8.1
Receive Parity Errors and Parity NACK Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.8.2
Receive Frame Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.8.3
Receive Overrun Errors and Overrun NACK Generation . . . . . . . . . . . . . . . . . . . . . . . .
25.8.4
Using Initial Character Mode and Resulting Receive Data Formats . . . . . . . . . . . . . . . .
25.8.5
Initial Character Mode Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.8.6
Automatic Receiver Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.8.7
Using the SIM Receiver with T = 1 SmartCards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.9 Using the SIM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.9.1
Transmit Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.9.2
Transmit NACKs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.9.3
Transmit Guard Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.9.4
Using the SIM Transmit with T = 1 SmartCards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.10 Suggested Programming Models for Specific SmartCards . . . . . . . . . . . . . . . . . . . . . . . . . .
25.10.1
Answer To Reset (ATR) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.10.2
Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.10.2.1
Geldkate Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.10.2.2
T = 0 SmartCards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.10.2.3
T = 1 SmartCards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25-36
25-37
25-38
25-39
25-40
25-41
25-42
25-42
25-42
25-43
25-44
25-44
25-45
25-45
25-45
25-46
25-47
25-47
25-47
25-48
25-48
25-48
25-49
25-50
25-50
25-50
25-50
25-51
25-51
25-53
25-53
25-54
25-55
Chapter 26
General-Purpose Timers
26.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.1.1
Pin Configuration for General-Purpose Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.2.1
Timer Control Registers 1 and 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.2.2
Timer Prescaler Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.2.3
Timer Compare Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.2.4
Timer Capture Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.2.5
Timer Counter Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26-2
26-2
26-3
26-3
26-5
26-6
26-7
26-8
MC9328MX1 Reference Manual, Rev. 6.1
xxii
Freescale Semiconductor
26.2.6
Timer Status Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9
Chapter 27
Universal Asynchronous Receiver/Transmitters (UART) Modules
27.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1
27.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1
27.2.1
Module Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2
27.2.2
UART Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3
27.3 Interrupts and DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4
27.4 General UART Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5
27.4.1
RTS—UART Request To Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
27.4.2
RTS Edge Triggered Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
27.4.3
DTR—Data Terminal Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7
27.4.4
DTR Edge Triggered Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7
27.4.5
DSR—Data Set Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8
27.4.6
DCD—Data Carrier Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8
27.4.7
RI—Ring Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8
27.4.8
CTS—Clear To Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8
27.4.9
Programmable CTS Deassertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8
27.4.10
TXD—UART Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8
27.4.11
RXD—UART Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8
27.5 Sub-Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9
27.5.1
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10
27.5.2
Transmitter FIFO Empty Interrupt Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-11
27.5.3
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12
27.5.4
Idle Line Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13
27.5.4.1
Idle Condition Detect Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13
27.5.5
Receiver Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-14
27.5.6
Receiving a BREAK Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-14
27.5.7
Vote Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-14
27.5.8
Binary Rate Multiplier (BRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-15
27.5.9
Baud Rate Automatic Detection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-17
27.5.9.1
Baud Rate Automatic Detection Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-18
27.5.10
Escape Sequence Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-19
27.6 Infrared Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-20
27.7 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-21
27.7.1
UART Receiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-24
27.7.2
UART Transmitter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-26
27.7.3
UART Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-27
27.7.4
UART Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-30
27.7.5
UART Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-33
27.7.5.1
UART1 Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-33
27.7.5.2
UART2 and UART3 Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-35
27.7.6
UART Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-37
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
xxiii
27.7.7
UART FIFO Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.7.8
UART Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.7.9
UART Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.7.10
UART Escape Character Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.7.11
UART Escape Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.7.12
UART BRM Incremental Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.7.13
UART BRM Modulator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.7.14
UART Baud Rate Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.7.15
UART BRM Incremental Preset Registers 1–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.7.16 UART BRM Modulator Preset Registers 1–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.7.17
UART Test Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.8 UART Operation in Low-Power System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27-39
27-41
27-43
27-45
27-46
27-47
27-48
27-49
27-50
27-51
27-53
27-54
Chapter 28
USB Device Port
28.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1
28.1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1
28.2 Module Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2
28.2.1
Universal Serial Bus Device Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3
28.2.2
Synchronization and Transaction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4
28.2.3
Endpoint FIFO Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4
28.2.4
Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5
28.2.5
USB Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5
28.2.6
Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5
28.2.7
Pin Configuration for USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6
28.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6
28.3.1
USB Frame Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8
28.3.2
USB Specification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-9
28.3.3
USB Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10
28.3.4
USB Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-11
28.3.5
USB Descriptor RAM Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-13
28.3.6
USB Descriptor RAM/Endpoint Buffer Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 28-14
28.3.7
USB Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-15
28.3.8
USB Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-17
28.3.9
USB Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-18
28.3.10
Endpoint n Status/Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-19
28.3.11
Endpoint n Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-20
28.3.12
Endpoint n Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-23
28.3.13
Endpoint n FIFO Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-25
28.3.14
Endpoint n FIFO Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-26
28.3.15
Endpoint n FIFO Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-28
28.3.16
USB Endpoint n Last Read Frame Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-30
28.3.17
USB Endpoint n Last Write Frame Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-31
28.3.18
Endpoint n FIFO Alarm Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-32
MC9328MX1 Reference Manual, Rev. 6.1
xxiv
Freescale Semiconductor
28.3.19
Endpoint n FIFO Read Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3.20
Endpoint n FIFO Write Pointer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.4 Programmer’s Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5 Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.1
Configuration Download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.1.1
USB Endpoint to FIFO Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.1.2
USB Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.1.3
Endpoint Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.1.4
Enable the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.6 Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.6.1
Unable to Complete Device Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.6.2
Aborted Device Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.6.3
Unable to Fill or Empty FIFO Due to Temporary Problem . . . . . . . . . . . . . . . . . . . . . . .
28.6.4
Catastrophic Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7 Data Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.1
USB Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.1.1
Short Packets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.1.2
Sending Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.1.3
Receiving Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.1.4
Programming the FIFO Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.2
USB Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.2.1
Data Transfers to the Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.2.2
Data Transfers to the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.3
Control Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.4
Bulk Traffic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.4.1
Bulk OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.4.2
Bulk IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.5
Interrupt Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.6
Isochronous Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.6.1
Isochronous Transfers in a Nutshell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.6.2
The SYNCH_FRAME Standard Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8 Interrupt Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.1
USB General Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.1.1
MSOF—Missed Start-of-Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.1.2
SOF—Start-of-Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.1.3
RESET_STOP—End of USB Reset Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.1.4
RESET_START—Start of USB Reset Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.1.5
WAKEUP—Resume (Wakeup) Signaling Detected . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.1.6
SUSP—USB Suspended. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.1.7
FRAME_MATCH—Match Detected in USB_FRAME Register . . . . . . . . . . . . . . .
28.8.1.8
CFG_CHG—Host Changed USB Device Configuration . . . . . . . . . . . . . . . . . . . . . .
28.8.2
Endpoint Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.2.1
FIFO_FULL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.2.2
FIFO_EMPTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.2.3
FIFO_ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-33
28-34
28-34
28-35
28-36
28-37
28-37
28-37
28-38
28-38
28-38
28-38
28-39
28-39
28-39
28-39
28-39
28-40
28-40
28-41
28-41
28-41
28-42
28-42
28-42
28-42
28-43
28-43
28-43
28-43
28-44
28-44
28-44
28-44
28-44
28-44
28-45
28-45
28-45
28-45
28-45
28-45
28-45
28-46
28-46
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
xxv
28.8.2.4
FIFO_HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.2.5
FIFO_LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.2.6
EOT—End of Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.2.7
DEVREQ—Device Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.2.8
MDEVREQ—Multiple Device Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.2.9
EOF—End of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.3
Interrupts, Missed Interrupts, and the USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.3.1
SOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.3.2
CFG_CHG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.3.3
EOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.8.3.4
DEVREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.9 Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.9.1
Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.9.2
USB Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.9.3
UDC Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.9.4
USB Reset Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-46
28-46
28-46
28-46
28-46
28-47
28-47
28-47
28-47
28-47
28-47
28-47
28-48
28-48
28-48
28-48
Chapter 29
I2C Module
29.1
29.2
29.3
29.4
29.4.1
29.4.2
29.4.3
29.4.4
29.5
29.6
29.6.1
29.6.2
29.6.3
29.6.4
29.6.5
29.7
29.7.1
29.7.2
29.7.3
29.7.4
29.7.5
29.7.6
29.7.7
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1
Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1
I2C System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
I2C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4
Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
Pin Configuration for I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6
I2C Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7
I2C Frequency Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8
I2C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10
I2C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11
I2C Data I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13
2
I C Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13
Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14
Generation of START. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14
Post-Transfer Software Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14
Generation of STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-15
Generation of Repeated START. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-15
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-15
Arbitration Lost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-15
MC9328MX1 Reference Manual, Rev. 6.1
xxvi
Freescale Semiconductor
Chapter 30
Synchronous Serial Interface (SSI)
30.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1
30.2 SSI Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1
30.2.1
SSI Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5
30.2.1.1
Normal Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5
30.2.1.2
Master / Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5
30.2.2
SSI Clock and Frame Sync Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5
30.2.3
Pin Configuration for SSI1 and SSI2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6
30.2.3.1
Pin Configuration Example Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8
30.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9
30.3.1
SSI Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-10
30.3.2
SSI1/SSI2 Transmit FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11
30.3.3
SSI1/SSI2 Transmit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11
30.3.4
SSI1/SSI2 Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-14
30.3.5
SSI Receive FIFO Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-14
30.3.6
SSI Receive Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-15
30.3.7
SSI1/SSI2 Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-17
30.3.7.1
I2S Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-21
30.3.8
SSI Transmit Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-23
30.3.9
SSI1/SSI2 Receive Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-25
30.3.10
SSI Transmit Clock Control Register and SSI Receive Clock Control Register . . . . . . . 30-29
30.3.10.1
Calculating the SSI Bit Clock from the Input Clock Value . . . . . . . . . . . . . . . . . . . . 30-30
30.3.11
SSI1/SSI2 Time Slot Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-32
30.3.12
SSI1/SSI2 FIFO Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-33
30.3.13
SSI1/SSI2 Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-36
30.4 SSI Data and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-37
30.4.1
SSI_TXDAT, Serial Transmit Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-37
30.4.2
SSI_RXDAT, Serial Receive Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-37
30.4.3
SSI_TXCLK, Serial Transmit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-37
30.4.4
SSI_RXCLK, Serial Receive Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-37
30.4.5
SSI_TXFS, Serial Transmit Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-38
30.4.6
SSI_RXFS, Serial Receive Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-38
30.5 SSI Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-40
30.5.1
Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-41
30.5.1.1
Normal Mode Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-41
30.5.1.2
Normal Mode Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-41
30.5.2
Network Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-43
30.5.2.1
Network Mode Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-43
30.5.2.2
Network Mode Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-44
30.6 Gated Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-45
30.7 External Frame and Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-46
30.8 SSI Reset and Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-46
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
xxvii
Chapter 31
CMOS Sensor Interface Module
31.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1
31.2 CSI Module Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1
31.3 CSI Module Interface Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2
31.3.1
Pin Configuration for CSI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3
31.4 CSI Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3
31.4.1
Data FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3
31.4.2
CSI Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4
31.4.3
Register Access While CSI Module is Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4
31.5 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4
31.5.1
CSI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5
31.5.2
CSI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8
31.5.3
CSI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-10
31.5.4
CSI Statistic FIFO Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-11
31.5.5
CSI RxFIFO Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12
31.6 Statistic Data Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-13
31.6.1
Statistic Block Diagram and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-13
31.6.2
Auto Exposure and Auto White Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-13
31.6.3
Auto Focus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-15
31.6.4
Packing of Statistic Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-15
31.6.5
Sensor Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16
31.6.6
Statistic Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16
31.6.6.1
Start of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16
31.6.6.2
Auto Focus Spread . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16
31.6.7
Statistic Output and DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16
31.6.7.1
Statistic Data Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16
31.6.7.2
Statistic FIFO Full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16
31.6.7.3
Statistic Data Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-17
Chapter 32
GPIO Module and I/O Multiplexer (IOMUX)
32.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1
32.2 GPIO Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2
32.2.1
GPIO Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2
32.2.2
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3
32.2.3
GPIO Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3
32.3 GPIO Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4
32.4 Pin Configuration for GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4
32.5 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-6
32.5.1
Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-8
32.5.2
Output Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9
32.5.2.1
Output Configuration Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9
32.5.2.2
Output Configuration Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-10
MC9328MX1 Reference Manual, Rev. 6.1
xxviii
Freescale Semiconductor
32.5.3
32.5.3.1
32.5.3.2
32.5.3.3
32.5.3.4
32.5.4
32.5.5
32.5.6
32.5.7
32.5.7.1
32.5.7.2
32.5.8
32.5.9
32.5.10
32.5.11
32.5.12
Input Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Configuration Register A1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Configuration Register A2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Configuration Register B1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Configuration Register B2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO In Use Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Mask Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Reset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pull_Up Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-11
32-11
32-12
32-13
32-14
32-15
32-16
32-17
32-18
32-18
32-19
32-20
32-21
32-22
32-23
32-24
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
xxix
MC9328MX1 Reference Manual, Rev. 6.1
xxx
Freescale Semiconductor
About This Book
This reference manual describes the features and operation of the MC9328MX1 (i.MX1) microprocessor, It
provides the details of how to initialize, configure, and program the MC9328MX1. The manual presumes basic
knowledge of ARM920T™ architecture.
Audience
The MC9328MX1 Reference Manual is intended to provide a design engineer with the necessary data to
successfully integrate the MC9328MX1 into a wide variety of applications. It is assumed that the reader has a good
working knowledge of the ARM920T processor. For programming information about the ARM920T processor,
see the documents listed in the Suggested Reading section of this preface.
Organization
The MC9328MX1 Reference Manual is organized into 32 chapters that cover the operation and programming of
the i.MX1 device. Summaries of the chapters follow.
Chapter 1
Introduction: This chapter contains a device feature list, overview of system modules,
and system block diagrams.
Chapter 2
Signal Descriptions and Pin Assignments: This chapter’s content has been moved to the
MC9328MX1 Data Sheet.
Chapter 3
Memory Map: This chapter summarizes the memory organization, programming
information and a listing of all of the registers in the MC9328MX1.
Chapter 4
ARM920T Processor: This chapter provides a high-level overview of the ARM920T
processor including the ARM9 Thumb® instruction set.
Chapter 5
Embedded Trace Macrocell (ETM): This chapter provides a summary of the operation
and features of the ARM Embedded Trace Macrocell™.
Chapter 6
Reset Module: The reset module processes of all of the system reset signals required by
the MC9328MX1. This chapter gives a detailed description of the reset module and
associated timing and signals.
Chapter 7
AHB to IP Bus Interface (AIPI): This chapter provides an overview of the R-AHB to
IP bus interface. The AIPI module in the MC9328MX1 acts as an interface between the
R-AHB (Reduced ARM Advanced High-performance Bus) and lower bandwidth
peripherals.
Chapter 8
System Control: This chapter describes the operation of and programming models for
the system multiplex control, peripheral control, ID register, and I/O drive control
registers.
Chapter 9
Bootstrap Mode Operation: The operation of bootstrap models is described in detail in
this chapter. This chapter describes programming information necessary to allow a system
to initialize a target system and download a program or data to the target system’s RAM
using the UART controller.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
xxxi
Chapter 10
Interrupt Controller (AITC): This chapter provides a description and operational
considerations for interrupt controller operation to perform interrupt masking, priority
support, and hardware acceleration of normal interrupts.
Chapter 11
External Interface Module (EIM): This chapter describes the external interface module
and shows how the module handles the interface to devices external to the MC9328MX1,
including generation of chip selects for external peripherals and memory.
Chapter 12
Phase-Locked Loop and Clock Controller: This chapter provides detailed information
about the operation and programming of the clock generation module as well as the
recommended circuit schematics for external clock circuits. It also describes and provides
programming information about the operation of the power control module and the
system power states.
Chapter 13
DMA Controller (DMAC): This chapter describes the operation of the direct memory
access controller contained in the MC9328MX1. The DMA controller provides two
memory channels and four I/O channels to support a wide variety of DMA operations.
Chapter 14
Watchdog Timer Module: The operation of the watchdog timer module is described in
this chapter. It includes information of how the watchdog timer protects against system
failures by providing a method of escaping from unexpected events or programming
errors.
Chapter 15
Analog Signal Processor (ASP): This chapter describes the analog signal processing
module of the MC9328MX1 which provides support and conversion capabilities for a
variety of analog devices, including analog-to-digital controllers (ADC) for voice
processing and pen input. The ASP also includes embedded circuity to support a touch
panel.
Chapter 16
Bluetooth Accelerator (BTA): This chapter describes the Bluetooth accelerator which,
controlled by software running on the ARM920T processor, implements baseband
protocols and other low-level link routines of the Bluetooth baseband.
Chapter 17
Multimedia Accelerator (MMA): This chapter describes the operation of the MMA
which is used in conjunction with the ARM920T processor to perform the iterative
operations of a digital signal processor for applications such as MPEG or MP3
encoding/decoding and speech compression/decompression.
Chapter 18
Serial Peripheral Interface Modules (SPI 1 and SPI 2): The programming and
operation of the two identical serial peripheral interface modules (SPI 1 and SPI 2) is
described in this chapter.
Chapter 19
LCD Controller (LCDC): This chapter describes the operation and programming of the
liquid crystal display controller, which provides display data for external LCD drivers or
for an LCD panel.
Chapter 20
Multimedia Card/Secure Digital Host Controller (MMC/SD): This chapter describes
the Multimedia Card (MMC) host controller which controls Flash-based mass storage
products. This chapter also describes the Secure Digital feature of the MMC, its operation
and programming information.
Chapter 21
Memory Stick Host Controller (MSHC): This chapter describes how data is transferred
to a Memory Stick device. It also discusses how to configure and program the Memory
Stick Host Controller.
Chapter 22
Pulse-Width Modulator (PWM): This chapter describes the operation and
configuration of the pulse-width modulator. Programming information is also provided.
MC9328MX1 Reference Manual, Rev. 6.1
xxxii
Freescale Semiconductor
Chapter 23
Real-Time Clock (RTC): This chapter describes the operation of the real-time clock
module, which is composed of a prescaler, time-of-day (TOD) clock, TOD alarm,
programmable real-time interrupt, watchdog timer, and minute stopwatch as well as
control registers and bus interface hardware.
Chapter 24
SDRAM Memory Controller (SDRAMC): The operation and programming of the
SDRAM controller is described in this chapter. This module provides a glueless interface
to 16-bit or 32-bit synchronous DRAM.
Chapter 25
SmartCard Interface Module: This chapter details the features, operation, and
programming interface of the SmartCard Interface Module (SIM).
Chapter 26
General-Purpose Timers: This chapter describes the two 16-bit timers that can be used
as both watchdogs and alarms.
Chapter 27
Universal Asynchronous Receiver/Transmitters (UART): This chapter describes the
capabilities and operation of the three UARTs. It also discusses how to configure and
program the UART modules.
Chapter 28
USB Device Port: This chapter provides configuration, interface description and detailed
programming information for designers to achieve the optimum performance from the
USB device.
Chapter 29
I2C Module: This chapter describes the I2C module of the MC9328MX1 including I2C
protocol, clock synchronization, and the registers in the I2C programming mode.
Chapter 30
Synchronous Serial Interface (SSI): This chapter presents the two Synchronous Serial
Interface modules and discusses the architecture, programming model, operating modes,
and initialization of the SSI.
Chapter 31
CMOS Sensor Interface (CSI): The CSI module is a logic interface that enables the
i.MX to connect directly to external CMOS image sensors. This chapter describes the CSI
module, and discusses the architecture, the programming model, and the software
initialization sequence.
Chapter 32
GPIO and I/O Multiplexer (IOMUX): This chapter covers all GPIO lines found in the
MC9328MX1. Because each pin is individually configurable, a detailed description of the
operation is provided.
Document Revision History
Table 0-1 includes technical content changes made for this revision.
Table 0-1. Revision History
Location
Description of Change
Chapter 13, “DMA Controller,” Table 13-23 on
page 13-30
DMA Request table: DMA_REQ [12] change from “Reserved”
to “Ext_DMA”.
Chapter 30, “Synchronous Serial Interface (SSI),”
Section 30.7, “External Frame and Clock Operation.”
Clarification to first paragraph.
Chapter 18, “Serial Peripheral Interface Modules (SPI 1
and SPI 2),” Section 18.3.3, “Control Registers.”
BIT_COUNT field description change.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
xxxiii
Suggested Reading
The following documents are required for a complete description of the MC9328MX1 and are necessary to design
properly with the device. Especially for those not familiar with the ARM920T processor or previous DragonBall
products, the following documents will be helpful when used in conjunction with this manual.
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)
ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)
ARM Technical Refines Manual (ARM Ltd., order number ARM DDI 0151C)
EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)
MC9328MX1 Product Brief (order number MC9328MX1P/D)
MC9328MX1 Data Sheet (order number MC9328MX1/D)
The manuals may be found at the Motorola Semiconductors World Wide Web site at
http://www.motorola.com/semiconductors. These documents may be downloaded directly from the World Wide
Web site, or printed versions may be ordered. The World Wide Web site also may have useful application notes.
Conventions
This reference manual uses the following conventions:
•
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
•
Logic level one is a voltage that corresponds to Boolean true (1) state.
•
Logic level zero is a voltage that corresponds to Boolean false (0) state.
•
To set a bit or bits means to establish logic level one.
•
To clear a bit or bits means to establish logic level zero.
•
A signal is an electronic construct whose state conveys or changes in state convey information.
•
A pin is an external physical connection. The same pin can be used to connect a number of signals.
•
Asserted means that a discrete signal is in active logic state.
— Active low signals change from logic level one to logic level zero.
— Active high signals change from logic level zero to logic level one.
•
Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
•
LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and
high bytes or words are spelled out.
•
Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are
hexadecimal.
Definitions, Acronyms, and Abbreviations
The following list defines acronyms and abbreviations used in this document.
ADC
analog-to-digital converter
AFE
analog front end
MC9328MX1 Reference Manual, Rev. 6.1
xxxiv
Freescale Semiconductor
API
application programming interface
BCD
binary coded decimal
BER
bit error ratio
CGM
clock generation module
CMOS
complimentary metal-oxide semiconductor
CRC
cyclic redundancy check
CSIC
complex instruction set computer
DAC
digital-to-analog converter
DDR RAM
double data rate RAM
DMA
direct memory access
DRAM
dynamic random access memory
FEC
forward error correction
FIFO
first in first out
GPIO
general purpose input/output
IAC
inquiry access code: A predefined Bluetooth ID
I/O
Input/Output
ICE
in-circuit emulation
IrDa
infrared
JTAG
joint test action group
MAP
mold array process
MAPBGA
mold array process ball grid array
MIPS
million instructions per second
MMC
multimedia card
PLL
phase locked loop
PWM
pulse-width modulator
RTC
real-time clock
SIM
system integration module
SD
secure digital
SDRAM
synchronous dynamic random access memory
SPI
serial peripheral interface
SRAM
static random access memory
TQFP
thin quad flat pack
UART
universal asynchronous receiver/transmitter
USB
universal serial bus
XTAL
crystal
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
xxxv
MC9328MX1 Reference Manual, Rev. 6.1
xxxvi
Freescale Semiconductor
Chapter 1
Introduction
The i.MX (Media Extensions) series provides a leap in performance with an ARM9™ microprocessor core
and highly integrated system functions. i.MX products specifically address the requirements of the
personal portable product market by providing intelligent integrated peripherals, an advanced processor
core, and power management capabilities.
The MC9328MX1 features the advanced and power-efficient ARM920T™ core that operates at speeds up to
200 MHz. Integrated modules such as an LCD controller, static RAM, USB support, an A/D converter (with touch
panel control), and an MMC/SD host controller offer a suite of peripherals to enhance any product seeking to
provide a rich multimedia experience. It is packaged in a 256-pin Mold Array Process-Ball Grid Array
(MAPBGA).
The MC9328MX1 provides the following benefits:
• Features a high level of on-chip integration
• Provides uncompromising performance in a very low-power system design
• Optimized for multimedia applications
• Connectivity features include SPI, UART, USB, and SSI/I2S
• Supports a wide variety of applications including the most popular PDA designs, smart phones, and
next-generation wireless communicators
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
1-1
System Control
JTAG/ICE
Bootstrap
Power
Control
DPLL x2
Standard
System I/O
GPIO
Connectivity
MC9328MX1
PWM
MMC/SD
Timer 1 & 2
Memory Stick®
Host Controller
CPU Complex
SPI 1 and
SPI 2
ARM9TDMI™
UART 1
RTC
I Cache
Watchdog
D Cache
UART 2 & 3
SSI / I2S
AIPI 1
Interrupt
Controller
VMMU
I2 C
USB Device
AIPI 2
DMAC
(11 Chnl)
Bus
Control
SmartCard I/F
Bluetooth
Accelerator
EIM &
SDRAMC
eSRAM
eSRAM
(128K)
(128K)
Multimedia
Multimedia
Accelerator
Video Port
Human Interface
Analog Signal
Processor
LCD Controller
Figure 1-1. MC9328MX1 Functional Block Diagram
To support a wide variety of applications, the MC9328MX1 boasts a robust array of features, including the
following:
• ARM920T Microprocessor Core
• AHB to IP Bus Interfaces (AIPIs)
• External Interface Module (EIM)
• SDRAM Controller (SDRAMC)
• DPLL Clock and Power Control Module
• Three Universal Asynchronous Receiver/Transmitters (UART 1, UART 2, and UART 3)
• Two Serial Peripheral Interfaces (SPI1 and SPI2)
• Two General-Purpose 32-bit Counters/Timers
• Watchdog Timer
• Real-Time Clock/Sampling Timer (RTC)
• LCD Controller (LCDC)
• Pulse-Width Modulation (PWM) Module
• Universal Serial Bus (USB) Device
• Multimedia Card and Secure Digital (MMC/SD) Host Controller
• Memory Stick® Host Controller (MSHC)
• SmartCard Interface Module (SIM)
MC9328MX1 Reference Manual, Rev. 6.1
1-2
Freescale Semiconductor
ARM920T Microprocessor Core
•
•
•
•
•
•
•
•
•
Direct Memory Access Controller (DMAC)
Two Synchronous Serial Interfaces (SSI1/2) and Inter-IC Sound (I2S) Module
Inter-IC (I2C) Bus Module
Video Port
General-Purpose I/O (GPIO) Ports
Bootstrap Mode
Analog Signal Processing (ASP) Module
Multimedia Accelerator (MMA)
256-pin PBGA Package
The following sections detail the features of the MC9328MX1’s functional blocks.
1.1 ARM920T Microprocessor Core
The MC9328MX1 uses the ARM920T microprocessor core which has the following features:
• 200 MHz maximum processing speed
• 16 Kbyte instruction cache and 16 Kbyte data cache
• ARM9 high performance 32-bit RISC engine
• Thumb® 16-bit compressed instruction set for a leading level of code density
• EmbeddedICE™ JTAG software debug
• 100-percent user code binary compatibility with ARM7TDMI® processors
• ARM9TDMI® core, including integrated caches, write buffers, and bus interface units, provides
CPU-cache transparency
• Advanced Microcontroller Bus Architecture (AMBA™) system-on-chip multi-master bus
interface
• Flexible CPU and bus clocking relationships including asynchronous, synchronous, and
single-clock configurations
• Cache locking to support mixed loads of real-time and user applications
• Virtual Memory Management Unit (VMMU)
1.2 AHB to IP Bus Interfaces (AIPIs)
The MC9328MX1 AIPIs provide a communication interface between the high-speed AHB bus and a
lower-speed IP bus for slow slave peripherals.
1.3 External Interface Module (EIM)
The MC9328MX1 EIM features:
• Up to six chip selects for external devices, each with 16 Mbyte of address space (chip selects for
ROM support a maximum of 32 Mbyte of address space)
• Programmable protection, port size, and wait states for each chip select
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
1-3
SDRAM Controller (SDRAMC)
•
•
•
•
•
Internal/external boot ROM selection
Selectable bus watchdog counter
Burst support for external AMD™ or Intel® flash with 32-bit data path
Interrupt controller to handle a maximum of 63 interrupt sources
Vectored interrupt capability with prioritization for 16 sources
1.4 SDRAM Controller (SDRAMC)
The MC9328MX1 SDRAMC features:
• Supports 4 banks of 64-, 128-, or 256-Mbit synchronous DRAMs
• Includes 2 independent chip-selects
— Up to 64 Mbyte per chip-select
— Up to four banks simultaneously active per chip-select
— JEDEC standard pinout and operation
• Supports burst reads of word (32-bit) data types
• PC100 compliant interface
— 100 MHz system clock achievable with “-8” option PC100 compliant memories
— single and fixed-length (8-word) word access
— Typical access time of 8-1-1-1 at 100 MHz
• Software configurable bus width, row and column sizes, and delays for differing system
requirements
• Built in auto-refresh timer and state machine
• Hardware supported self-refresh entry and exit which keeps data valid during system reset and
low-power modes
• Auto-powerdown (clock suspend) timer
1.5 Clock Generation Module (CGM) and Power Control Module
The MC9328MX1 CGM and Power Control Module features:
• Digital phase-locked loops (PLLs) and clock controller for all internal clocks generation
• MCUPLL generates FCLK to the CPU from either a 32 kHz or 32.768 kHz
• System PLL generates the system clock and the 48 MHz clock for the USB from a 16 MHz or
either a 32 kHz or 32.768 kHz
• Support for three power modes for different power consumption needs: run, doze, and stop
1.6 Three Universal Asynchronous Receiver/Transmitters
(UART 1, UART 2, and UART 3)
The MC9328MX1 UARTs features:
MC9328MX1 Reference Manual, Rev. 6.1
1-4
Freescale Semiconductor
Two Serial Peripheral Interfaces (SPI)
•
•
•
•
Support for serial data transmit/receive operation: 7 or 8 data bits, 1 or 2 stop bits, and
programmable parity (even, odd, or none)
Programmable baud rates up to 1.00 MHz
32-byte FIFO on Tx and 32 half-word FIFO on Rx that support autobaud
IrDA 1.0 support
1.7 Two Serial Peripheral Interfaces (SPI)
The MC9328MX1 SPIs feature:
• SPI 1 is master/slave configurable, SPI 2 is master only
• Up to 16-bit programmable data transfer
• 8 × 16 FIFO for both Tx and Rx data
1.8 Two General-Purpose 32-Bit Counters/Timers
The MC9328MX1 General-Purpose Counters/Timers features:
• Automatic interrupt generation
• Programmable timer input/output pins
• Input capture capability with programmable trigger edge
• Output compare with programmable mode
1.9 Watchdog Timer
The MC9328MX1 Watchdog Timer features:
• Programmable time out of 0.5 s to 64 s
• Resolution of 0.5 s
1.10 Real-Time Clock/Sampling Timer (RTC)
The MC9328MX1 RTC features:
• 32.768 kHz or 32 kHz
• Full clock features: seconds, minutes, hours, and days
• Capable of counting up to 512 days
• Minute countdown timer with interrupt
• Programmable daily alarm with interrupt
• Sampling timer with interrupt
• Once-per-second, once-per-minute, once-per-hour, and once-per-day interrupts
• Interrupt generation for digitizer sampling or keyboard debouncing
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
1-5
LCD Controller (LCDC)
1.11 LCD Controller (LCDC)
The MC9328MX1 LCDC features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Software programmable screen size (a maximum of 640 × 512 pixels) to support single (non-split)
monochrome, color STN panels, and color TFT panels
Support for 4 bpp (bits per pixel), 8 bpp, and 12 bpp for passive color panels
Support for 4 bpp, 8 bpp, 12 bpp, and 16 bpp for TFT panels
— Up to 256 colors out of a palette of 4096 for 8 bpp
— True 64K color for 16 bpp
In color STN mode, the maximum bit depth is 12 bpp
In BW mode, the maximum bit depth is 4 bpp
Up to 16 grey levels out of 16 palettes
Capable of directly driving popular LCD drivers from manufacturers including Motorola, Sharp,
Hitachi, and Toshiba
Support for data bus width for 12- or 16-bit TFT panels
Panel interface of 8-, 4-, and 2-bits, and a 1-bit wide LCD panel data bus for monochrome panels
Direct interface to Sharp® 320 × 240 HR-TFT panel
Support for logical operation between color hardware cursor and background
Uses system memory as display memory
LCD contrast control using 8-bit PWM
Support for self-refresh LCD modules
Hardware panning (soft horizontal scrolling)
1.12 Pulse-Width Modulation (PWM) Module
The MC9328MX1 PWM Module features:
• 4 × 16 FIFO to minimize interrupt overhead
• 16-bit resolution
• Sound and melody generation
1.13 Universal Serial Bus (USB) Device
The MC9328MX1 USB Device features:
•
•
•
Compliant with Universal Serial Bus Specification, revision 1.1
Up to six logical endpoints—see Table 1-1 on page 1-7
Support for isochronous communications pipes
— Frame match interrupt feature notifies the user when a specific USB frame occurs
— For DMA access, the maximum packet size for the isochronous endpoint is restricted by the
FIFO size of the endpoint
— For programmed I/O, isochronous data packets range from 0 bytes to 1023 bytes
MC9328MX1 Reference Manual, Rev. 6.1
1-6
Freescale Semiconductor
Multimedia Card and Secure Digital (MMC/SD) Host Controller
•
•
•
Support for control, bulk, and interrupt pipes
— Packet sizes are limited to 8, 16, 32, or 64 bytes
— Maximum packet size depends on the FIFO size of the endpoint
Support (via a register bit) for a remote wake-up feature
Full-speed (12 MHz) operation
•
Operation can be programmed for both bus-powered and self-powered mode
Table 1-1. Endpoint Configurations
Endpoint
Direction
Physical FIFO Size (Bytes)
Endpoint
Configuration
Maximum Packet Size (Bytes)
0
IN and OUT
32
Control
32
1–5
IN or OUT
32 or 641
Control, interrupt, bulk,
or isochronous
User configurable: 8, 16, 32, or 64
(depending on FIFO size)
1.FIFO1 and FIFO2 are 64 bytes each; FIFO3, FIFO4, and FIFO5 are 32 bytes each.
1.14
Multimedia Card and Secure Digital (MMC/SD) Host Controller
The MMC/SD Host Controller features:
• Compatible with the MultiMediaCard System Specification (SPI mode excluded), version 3.1
• Compatible to 1/4 bit with the SD Memory Card Specification (SPI mode excluded), version 1.0
and SD I/O Specification (SPI mode excluded), version 1.0 with 1 or 4 channel(s)
• Up to ten MMC cards and one SD are supported by standard (maximum data rate with a maximum
of ten cards)
• Support for hot swappable operation
• Support for data rates from 20 Mbps to 80 Mbps
1.15
Memory Stick® Host Controller (MSHC)
The MSHC features:
• Integrated 8-byte (4-word) FIFO buffer for transmit and receive
• Integrated CRC circuit
• Support for internal or external serial clock source
• Integrated Serial Clock Divider
• DMA support; DMA request condition is selectable based on FIFO status
• Automatic command execution when an interrupt from the Memory Stick is detected (can be
toggled on/off)
• RDY time-out period set by the number of serial clock cycles
• Interrupt output to the ARM920T core when a time-out occurs
• Two integrated general-purpose input pins for detecting Memory Stick insertion/extraction
• 16-bit host bus access (byte access not supported)
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
1-7
SmartCard Interface Module (SIM)
1.16
SmartCard Interface Module (SIM)
The MC9328MX1 SIM features:
• ISO7816 smartcard interface
• 32-word deep receive FIFO
• SIM card presence detect with interrupt capability
1.17 Direct Memory Access Controller (DMAC)
The MC9328MX1 DMAC features:
• 11 channels to support linear memory, 2D memory, FIFO, and End-of-Burst Enable FIFO for both
source and destination
• Support for 8-, 16-, or 32-bit FIFO port size and memory port size data transfer
• Support for big-endian and little-endian
• Configurable DMA burst length for each channel up to 16 words, 32 half-words, or 64 bytes
• Bus utilization control for a channel that is not triggered by DMA requests
• Bulk data transfer complete or transfer error interrupts provided to interrupt handler (and then to
the core)
• DMA burst time-out error terminates the DMA cycle when the burst cannot be completed within
a programmed timing period
• Acknowledge signal provided to peripheral after DMA burst is complete
1.18 Synchronous Serial Interface and Inter-IC Sound (SSI/I2S)
Module
The MC9328MX1 SSI/I2S Modules features:
• Supports generic SSI interface for external audio chip or interprocessor communication
• Supports Philips standard Inter-IC Sound (I2S) bus for external digital audio chip interface
1.19 Inter-IC (I2C) Bus Module
The MC9328MX1 I2C Bus Module features:
• Support for Philips I2C-bus standard for external digital control
• Support for 3.3 V tolerant devices
• Multiple-master operation
• Software-programmable for 1 of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven, byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
MC9328MX1 Reference Manual, Rev. 6.1
1-8
Freescale Semiconductor
Video Port
•
•
•
•
1.20
Start and stop signal generation and detection
Repeated START signal generation
Acknowledge bit generation and detection
Bus-busy detection
Video Port
The video port supports external CMOS sensor video data input.
1.21 General-Purpose I/O (GPIO) Ports
The MC9328MX1 GPIO ports feature:
• Interrupt capability
• 110 total I/O pins multiplexed with most dedicated functions for pin efficiency
1.22 Bootstrap Mode
The MC9328MX1 Bootstrap Mode features:
• Allows user to initialize system and download program or data to system memory through UART
• Accepts execution command to run program stored in system memory
• Supports memory/register read/write operation of selectable data size of byte, half-word, or word
• Provides a 32-byte instruction buffer for ARM920T core vector table storage, instruction storage
and execution
1.23
Analog Signal Processing (ASP) Module
The MC9328MX1 ASP Module features:
• Pen ADC
— 9-bit Pen ADC (PADC) for touch panel and low voltage detection
— 12 × 16-bit FIFO for PADC sample
— Embedded touch panel circuitry
— Supports auto and manual sampling mode
— Programmable pen down and pen-up interrupt to interrupt handler
— Provides data-ready and FIFO-full interrupt to interrupt handler
— True differential input
1.24
Multimedia Accelerator (MMA)
The Multimedia Accelerator features:
• MAC for FIR and FFT operation—MP3 applications save 10% to 15% CPU MIPS
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
1-9
Power Management Features
•
DCT/iDCT hardware accelerator—MPEG4 decode applications save approximately 10% CPU
MIPS
1.25 Power Management Features
The MC9328MX1 provides the following power management features:
• Programmable clock synthesizer using either a 32 kHz or 32.768 kHz crystal for full frequency
control
• Low-power stop capabilities
• Modules that can be individually shut down
• Lowest power mode control
1.26 Operating Voltage Range
The MC9328MX1 operating voltages are as follows:
• I/O voltage—1.7 V to 2.0 V or 2.7 V to 3.3 V
• Internal logic voltage—150 MHz: 1.7 V to 1.9 V; 200 MHz: 1.8 to 2.0V
1.27 Packaging
The MC9328MX1 features the package:
• 256-pin MAPBGA 14 mm × 14 mm × 1.3 mm package, with 0.8 mm ball pitch
MC9328MX1 Reference Manual, Rev. 6.1
1-10
Freescale Semiconductor
Chapter 2
Signal Descriptions and Pin Assignments
2.1 Signal and Pin Information
For information about the MC9328MX1 signals and their pin assignments refer to the MC9328MX1 data sheet
(document order number: MC9328MX1).
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
2-1
Signal and Pin Information
MC9328MX1 Reference Manual, Rev. 6.1
2-2
Freescale Semiconductor
Chapter 3
Memory Map
This chapter describes the memory maps and the chip configuration registers of the MC9328MX1.
3.1 Memory Space
The ARM920T microprocessor implements a virtual addressing mechanism. Refer to the ARM920T Memory
Management Unit in the ARM9 technical reference manual for more information on this topic.
The ARM920T processor physical memory map can be divided according to the addresses shown in Figure 3-1 on
page 3-2.
3.1.1 Memory Map
The base address referred to in each peripheral register address is the address from this table. The exact address
description of each of the peripherals is described in each peripheral section.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
3-1
Memory Space
Base Address
4 KB
64 KB
$0000 0000
1 MB
$0020 0000
AIPI1
Double Map
Image
$0020 FFFF
$0021 0000
$000F FFFF
$0010 0000
64 KB
AIPI2
1 MB
Bootstrap
ROM
$001F FFFF
$0020 0000
156 KB
Internal
Registers
$0022 6FFF
$0022 7000
868 KB
Reserved
$002F FFFF
$0030 0000
1 MB
$0021 FFFF
$0022 0000
$0022 0FFF
$0022 1000
$0022 1FFF
$0022 2000
$0022 2FFF
$0022 3000
$0022 3FFF
$0022 4000
$0022 4FFF
$0022 5000
$0022 5FFF
$0022 6000
$0022 6FFF
4 KB
EIM
4 KB
SDRAMC
4 KB
MMA
4 KB
AITC
4 KB
CSI
4 KB
Reserved
4 KB
Reserved
Embedded
SRAM
$003F FFFF (128 KB Used)
$0040 0000
$0800 0000
64 MB
CSD0
(SDRAM)
active low
124 MB
$0BFF FFFF
$0C00 0000
64 MB
CSD1
(SDRAM)
active low
Reserved
$0FFF FFFF
$1000 0000
32 MB
CS0
(Flash)
active low
$07FF FFFF
$0800 0000
$0FFF FFFF
$1000 0000
$16FF FFFF
$1700 0000
128 MB
External
(2x64 MB)
112 MB
External
(1x32 MB +
5x16 MB)
912 MB
$11FF FFFF
$1200 0000
$12FF FFFF
$1300 0000
$13FF FFFF
$1400 0000
Reserved
$4FFF FFFF
$5000 0000
4 KB
ARM9 Test
Registers
$5000 0FFF
$5000 1000
2815 MB
+
1020 KB
$14FF FFFF
$1500 0000
$15FF FFFF
$1600 0000
Reserved
$FFFF FFFF
$16FF FFFF
16 MB
CS1
(Flash)
active low
16 MB
CS2
(Ext SRAM)
active low
16 MB
CS3
(Spare)
active low
16 MB
CS4
(Spare)
active low
16 MB
CS5
(Spare)
active low
$0020 0000
$0020 0FFF AIPI1
$0020 1000
$0020 1FFF Watchdog
$0020 2000
$0020 2FFF Timer1
$0020 3000
$0020 3FFF Timer2
$0020 4000
RTC
$0020 4FFF
$0020 5000
$0020 5FFF LCDC
$0020 6000
$0020 6FFF UART1
$0020 7000
$0020 7FFF UART 2
$0020 8000
$0020 8FFF PWM
$0020 9000
$0020 9FFF DMAC
$0020 A000
$0020 AFFF UART 3
$0020 B000
$0020 BFFF Reserved
$0020 C000
$0020 CFFF Reserved
$0020 D000
$0020 DFFF Reserved
$0020 E000
$0020 EFFF Reserved
$0020 F000
$0020 FFFF Reserved
$0021 0000
$0021 0FFF AIPI2
$0021 1000
SIM
$0021 1FFF
$0021 2000
$0021 2FFF USBD
$0021 3000
$0021 3FFF SPI 1
$0021 4000
$0021 4FFF MMC/SDHC
$0021 5000
ASP
$0021 5FFF
$0021 6000
BTA
$0021 6FFF
$0021 7000
I2 C
$0021 7FFF
$0021 8000
$0021 8FFF SSI 1
$0021 9000 SPI 2
$0021 9FFF
$0021 A000 MSHC
$0021 AFFF
$0021 B000
RESET/
$0021 BFFF CLOCK/CTRL
$0021 C000
$0021 CFFF GPIO
$0021 D000
$0021 DFFF SSI 2
$0021 E000
$0021 EFFF Reserved
$0021 F000
$0021 FFFF Reserved
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
Figure 3-1. MC9328MX1 MCU Physical Memory Map (4 Gbyte)
MC9328MX1 Reference Manual, Rev. 6.1
3-2
Freescale Semiconductor
Memory Space
Table 3-1. MC9328MX1 MCU Memory Space (Physical Addresses)
Address
Description
Size
$0000 0000 - $000F FFFF
Bootstrap ROM
1 Mbyte
$0010 0000 - $001F FFFF
Reserved
1 Mbyte
$0020 0000 - $0020 0FFF
AIPI1
4 kbyte
$0020 1000 - $0020 1FFF
WatchDog
4 kbyte
$0020 2000 - $0020 2FFF
TIMER1
4 kbyte
$0020 3000 - $0020 3FFF
TIMER2
4 kbyte
$0020 4000 - $0020 4FFF
RTC
4 kbyte
$0020 5000 - $0020 5FFF
LCDC
4 kbyte
$0020 6000 - $0020 6FFF
UART1
4 kbyte
$0020 7000 - $0020 7FFF
UART2
4 kbyte
$0020 8000 - $0020 8FFF
PWM
4 kbyte
$0020 9000 - $0020 9FFF
DMAC
4 kbyte
$0020 A000 - $0020 AFFF
UART 3
4 kbyte
$0020 B000 - $0020 BFFF
Reserved
4 kbyte
$0020 C000 - $0020 CFFF
Reserved
4 kbyte
$0020 D000 - $0020 DFFF
Reserved
4 kbyte
$0020 E000 - $0020 EFFF
Reserved
4 kbyte
$0020 F000 - $0020 FFFF
Reserved
4 kbyte
$0021 0000 - $0021 0FFF
AIPI2
4 kbyte
$0021 1000 - $0021 1FFF
SIM
4 kbyte
$0021 2000 - $0021 2FFF
USBD
4 kbyte
$0021 3000 - $0021 3FFF
SPI 1
4 kbyte
$0021 4000 - $0021 4FFF
MMC/SDHC
4 kbyte
$0021 5000 - $0021 5FFF
ASP
4 kbyte
$0021 6000 - $0021 6FFF
BTA
4 kbyte
$0021 7000 - $0021 7FFF
I2C
4 kbyte
$0021 8000 - $0021 8FFF
SSI 1
4 kbyte
$0021 9000 - $0021 9FFF
SPI 2
4 kbyte
$0021 A000 - $0021 AFFF
MSHC
4 kbyte
$0021 B000 - $0021 BFFF
RESET/CLOCK/CTRL
4 kbyte
$0021 C000 - $0021 CFFF
GPIO
4 kbyte
$0021 D000 - $0021 DFFF
SSI 2
4 kbyte
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
3-3
Memory Space
Table 3-1. MC9328MX1 MCU Memory Space (Physical Addresses)
Address
Description
Size
$0021 E000 - $0021 EFFF
Reserved
4 kbyte
$0021 F000 - $0021 FFFF
Reserved
4 kbyte
$0022 0000 - $0022 0FFF
EIM
4 kbyte
$0022 1000 - $0022 1FFF
SDRAMC
4 kbyte
$0022 2000 - $0022 2FFF
MMA
4 kbyte
$0022 3000 - $0022 3FFF
AITC
4 kbyte
$0022 4000 - $0022 4FFF
CSI
4 kbyte
$0022 5000 - $0022 5FFF
Reserved
4 kbyte
$0022 6000 - $0022 6FFF
Reserved
4 kbyte
$0022 7000 - $002F FFFF
Reserved
868 kbyte
$0030 0000 - $003F FFFF
Internal SRAM (128 Kbyte used)
1 Mbyte
$0040 0000 - $07FF FFFF
Reserved
124 Mbyte
$0800 0000 - $0BFF FFFF
External memory (CSD0)
64 Mbyte
$0C00 0000 - $0FFF FFFF
External memory (CSD1)
64 Mbyte
$1000 0000 - $11FF FFFF
External memory (CS0)
32 Mbyte
$1200 0000 - $12FF FFFF
External memory (CS1)
16 Mbyte
$1300 0000 - $13FF FFFF
External Memory (CS2)
16 Mbyte
$1400 0000 - $14FF FFFF
External Memory (CS3)
16 Mbyte
$1500 0000 - $15FF FFFF
External Memory (CS4)
16 Mbyte
$1600 0000 - $16FF FFFF
External Memory (CS5)
16 Mbyte
$1700 0000 - $4FFF FFFF
Reserved
912 Mbyte
$5000 0000 - $5000 0FFF
ARM920T Test Registers
4 kbyte
$5000 1000 - $FFFF FFFF
Reserved
2815 Mbyte + 1020 kbyte
3.1.2 On-Chip MCU Memory
One megabyte of address space is assigned to embedded SRAM, however only the first 128 Kbyte is physically
populated, from address 0x00300000 to 0x0031FFFF. The last 32-bit word at 0x0031FFFC is an extending word.
Reading a word at the rest of the 1 Mbyte (0x00320000–0x003FFFFC) boundary returns the same value as at the
extending word.
3.1.3 Internal Register Space
Internal registers are located from 0x00200000 to 0x00224FFF. Some of the MC9328MX1 peripherals are each
allocated 4 Kbyte starting at address $00200000 and they are connected to the AIPI1 (AHB IP Interface). Any
ARM920T core write access to these modules will experience two wait states—that is, any write access will be a
MC9328MX1 Reference Manual, Rev. 6.1
3-4
Freescale Semiconductor
Memory Space
three cycle long access, and any ARM920T core read access from these modules will have one wait state—that is,
any read access will be two cycle long access. The other MC9328MX1 peripherals are each allocated 4 Kbyte
starting at address $00210000 and they are connected to the AIPI2. Any ARM920T core write access to these
modules will have two wait states—that is, any write access will be a three cycle long access, and any ARM920T
core read access from these modules will have one wait state—any read access will be two cycle long access.
4 kbyte address space beginning at 0x00220000 to 0x00220FFF is assigned for EIM internal registers.
4 kbyte address space beginning at 0x00221000 to 0x00221FFF is assigned for SDRAMC internal registers.
4 kbyte address space beginning at 0x00222000 to 0x00222FFF is assigned for MMA internal registers.
4 kbyte address space beginning at 0x00223000 to 0x00223FFF is assigned for AITC internal registers.
4 kbyte address space beginning at 0x00224000 to 0x00224FFF is assigned for CSI internal registers.
Within each 4 kbyte peripheral space, any number of architected registers may be defined (as outlined in the
chapter for each peripheral), and software must explicitly address them making no assumptions regarding multiple
mapping.
3.1.4 External Memory
There are 240 Mbytes of the memory map allocated for external chip access, beginning at address $08000000.
There are 8 external chip selects which are allocated 64 Mbyte each for CSD1–CSD0, 16 Mbyte each for
CS5Q–CS1, and 32 Mbyte for CS0.
3.1.5 Double Map Image
The first 1 Mbyte system address space (starting at address $0) is defined as double map image space. This address
space is mapped to the first 1 Mbyte of boot ROM upon power up. In MC9328MX1 the boot ROM can be either
SyncFlash, CS0, or Bootstrap ROM. After system power up, reading or writing to the double map space
($0000,0000 to $000F,FFFF) is the same as reading or writing to the first 1 Mbyte of the selected boot ROM which
is controlled by the configuration of BOOT [3:0] input pins.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
3-5
Internal Registers
3.2 Internal Registers
The internal registers in the MC9328MX1 are listed in Table 3-2.
Table 3-2. MC9328MX1 Internal Registers Sorted by Address
Module Name
Address
Name
Description
Watchdog
0x00201000
WCR
Watchdog Control Register
Watchdog
0x00201004
WSR
Watchdog Service Register
Watchdog
0x00201008
WSTR
Watchdog Status Register
Timer 1
0x00202000
TCTL1
Timer 1 Control Register
Timer 1
0x00202004
TPRER1
Timer 1 Prescaler Register
Timer 1
0x00202008
TCMP1
Timer 1 Compare Register
Timer 1
0x0020200C
TCR1
Timer 1 Capture Register
Timer 1
0x00202010
TCN1
Timer 1 Counter Register
Timer 1
0x00202014
TSTAT1
Timer 1 Status Register
Timer 2
0x00203000
TCTL2
Timer 2 Control Register
Timer 2
0x00203004
TPRER2
Timer 2 Prescaler Register
Timer 2
0x00203008
TCMP2
Timer 2 Compare Register
Timer 2
0x0020300C
TCR2
Timer 2 Capture Register
Timer 2
0x00203010
TCN2
Timer 2 Counter Register
Timer 2
0x00203014
TSTAT2
RTC
0x00204000
HOURMIN
RTC Hours and Minutes Counter Register
RTC
0x00204004
SECONDS
RTC Seconds Counter Register
RTC
0x00204008
ALRM_HM
RTC Hours and Minutes Alarm Register
RTC
0x0020400C
ALRM_SEC
RTC Seconds Alarm Register
RTC
0x00204010
RCCTL
RTC Control Register
RTC
0x00204014
RTCISR
RTC Interrupt Status Register
RTC
0x00204018
RTCIENR
RTC Interrupt Enable Register
RTC
0x0020401C
STPWCH
Stopwatch Minutes Register
RTC
0x00204020
DAYR
RTC Days Counter Register
RTC
0x00204024
DAYALARM
Timer 2 Status Register
RTC Day Alarm Register
MC9328MX1 Reference Manual, Rev. 6.1
3-6
Freescale Semiconductor
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
LCDC
0x00205000
SSA
Screen Start Address Register
LCDC
0x00205004
SIZE
Size Register
LCDC
0x00205008
VPW
Virtual Page Width Register
LCDC
0x0020500C
CPOS
LCD Cursor Position Register
LCDC
0x00205010
LCWHB
LCD Cursor Width Height and Blink Register
LCDC
0x00205014
LCHCC
LCD Color Cursor Mapping Register
LCDC
0x00205018
PCR
Panel Configuration Register
LCDC
0x0020501C
HCR
Horizontal Configuration Register
LCDC
0x00205020
VCR
Vertical Configuration Register
LCDC
0x00205024
POS
Panning Offset Register
LCDC
0x00205028
LGPMR
LCD Gray Palette Mapping Register
LCDC
0x0020502C
PWMR
PWM Contrast Control Register
LCDC
0x00205030
DMACR
DMA Control Register
LCDC
0x00205034
RMCR
Refresh Mode Control Register
LCDC
0x00205038
LCDICR
Interrupt Configuration Register
LCDC
0x00205040
LCDISR
Interrupt Status Register
UART 1
0x00206000
URX0D_1
UART1 Receiver Register 0
UART 1
0x00206004
URX1D_1
UART1 Receiver Register 1
UART 1
0x00206008
URX2D_1
UART1 Receiver Register 2
UART 1
0x0020600C
URX3D_1
UART1 Receiver Register 3
UART 1
0x00206010
URX4D_1
UART1 Receiver Register 4
UART 1
0x00206014
URX5D_1
UART1 Receiver Register 5
UART 1
0x00206018
URX6D_1
UART1 Receiver Register 6
UART 1
0x0020601C
URX7D_1
UART1 Receiver Register 7
UART 1
0x00206020
URX8D_1
UART1 Receiver Register 8
UART 1
0x00206024
URX9D_1
UART1 Receiver Register 9
UART 1
0x00206028
URX10D_1
UART1 Receiver Register 10
UART 1
0x0020602C
URX11D_1
UART1 Receiver Register 11
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
3-7
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
UART 1
0x00206030
URX12D_1
UART1 Receiver Register 12
UART 1
0x00206034
URX13D_1
UART1 Receiver Register 13
UART 1
0x00206038
URX14D_1
UART1 Receiver Register 14
UART 1
0x0020603C
URX15D_1
UART1 Receiver Register 15
UART 1
0x00206040
UTX0D_1
UART1 Transmitter Register 0
UART 1
0x00206044
UTX1D_1
UART1 Transmitter Register 1
UART 1
0x00206048
UTX2D_1
UART1 Transmitter Register 2
UART 1
0x0020604C
UTX3D_1
UART1 Transmitter Register 3
UART 1
0x00206050
UTX4D_1
UART1 Transmitter Register 4
UART 1
0x00206054
UTX5D_1
UART1 Transmitter Register 5
UART 1
0x00206058
UTX6D_1
UART1 Transmitter Register 6
UART 1
0x0020605C
UTX7D_1
UART1 Transmitter Register 7
UART 1
0x00206060
UTX8D_1
UART1 Transmitter Register 8
UART 1
0x00206064
UTX9D_1
UART1 Transmitter Register 9
UART 1
0x00206068
UTX10D_1
UART1 Transmitter Register 10
UART 1
0x0020606C
UTX11D_1
UART1 Transmitter Register 11
UART 1
0x00206070
UTX12D_1
UART1 Transmitter Register 12
UART 1
0x00206074
UTX13D_1
UART1 Transmitter Register 13
UART 1
0x00206078
UTX14D_1
UART1 Transmitter Register 14
UART 1
0x0020607C
UTX15D_1
UART1 Transmitter Register 15
UART 1
0x00206080
UCR1_1
UART1 Control Register 1
UART 1
0x00206084
UCR2_1
UART1 Control Register 2
UART 1
0x00206088
UCR3_1
UART1 Control Register 3
UART 1
0x0020608C
UCR4_1
UART1 Control Register 4
UART 1
0x00206090
UFCR_1
UART1 FIFO Control Register
UART 1
0x00206094
USR1_1
UART1 Status Register 1
UART 1
0x00206098
USR2_1
UART1 Status Register 2
UART 1
0x0020609C
UESC_1
UART1 Escape Character Register
MC9328MX1 Reference Manual, Rev. 6.1
3-8
Freescale Semiconductor
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
UART 1
0x002060A0
UTIM_1
UART1 Escape Timer Register
UART 1
0x002060A4
UBIR_1
UART1 BRM Incremental Register
UART 1
0x002060A8
UBMR_1
UART1 BRM Modulator Register
UART 1
0x002060AC
UBRC_1
UART1 Baud Rate Count Register
UART 1
0x002060B0
BIPR1_1
UART1 BRM Incremental Preset Register 1
UART 1
0x002060B4
BIPR2_1
UART1 BRM Incremental Preset Register 2
UART 1
0x002060B8
BIPR3_1
UART1 BRM Incremental Preset Register 3
UART 1
0x002060BC
BIPR4_1
UART1 BRM Incremental Preset Register 4
UART 1
0x002060C0
BMPR1_1
UART1 BRM Modulator Preset Register 1
UART 1
0x002060C4
BMPR2_1
UART1 BRM Modulator Preset Register 2
UART 1
0x002060C8
BMPR3_1
UART1 BRM Modulator Preset Register 3
UART 1
0x002060CC
BMPR4_1
UART1 BRM Modulator Preset Register 4
UART 1
0x002060D0
UTS_1
UART 2
0x00207000
URX0D_2
UART2 Receiver Register 0
UART 2
0x00207004
URX1D_2
UART2 Receiver Register 1
UART 2
0x00207008
URX2D_2
UART2 Receiver Register 2
UART 2
0x0020700C
URX3D_2
UART2 Receiver Register 3
UART 2
0x00207010
URX4D_2
UART2 Receiver Register 4
UART 2
0x00207014
URX5D_2
UART2 Receiver Register 5
UART 2
0x00207018
URX6D_2
UART2 Receiver Register 6
UART 2
0x0020701C
URX7D_2
UART2 Receiver Register 7
UART 2
0x00207020
URX8D_2
UART2 Receiver Register 8
UART 2
0x00207024
URX9D_2
UART2 Receiver Register 9
UART 2
0x00207028
URX10D_2
UART2 Receiver Register 10
UART 2
0x0020702C
URX11D_2
UART2 Receiver Register 11
UART 2
0x00207030
URX12D_2
UART2 Receiver Register 12
UART 2
0x00207034
URX13D_2
UART2 Receiver Register 13
UART 2
0x00207038
URX14D_2
UART2 Receiver Register 14
UART1 Test Register 1
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
3-9
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
UART 2
0x0020703C
URX15D_2
UART2 Receiver Register 15
UART 2
0X00207040
UTX0D_2
UART2 Transmitter Register 0
UART 2
0X00207044
UTX1D_2
UART2 Transmitter Register 1
UART 2
0X00207048
UTX2D_2
UART2 Transmitter Register 2
UART 2
0X0020704C
UTX3D_2
UART2 Transmitter Register 3
UART 2
0X00207050
UTX4D_2
UART2 Transmitter Register 4
UART 2
0X00207054
UTX5D_2
UART2 Transmitter Register 5
UART 2
0X00207058
UTX6D_2
UART2 Transmitter Register 6
UART 2
0X0020705C
UTX7D_2
UART2 Transmitter Register 7
UART 2
0X00207060
UTX8D_2
UART2 Transmitter Register 8
UART 2
0X00207064
UTX9D_2
UART2 Transmitter Register 9
UART 2
0X00207068
UTX10D_2
UART2 Transmitter Register 10
UART 2
0X0020706C
UTX11D_2
UART2 Transmitter Register 11
UART 2
0X00207070
UTX12D_2
UART2 Transmitter Register 12
UART 2
0X00207074
UTX13D_2
UART2 Transmitter Register 13
UART 2
0X00207078
UTX14D_2
UART2 Transmitter Register 14
UART 2
0X0020707C
UTX15D_2
UART2 Transmitter Register 15
UART 2
0x00207080
UCR1_2
UART2 Control Register 1
UART 2
0x00207084
UCR2_2
UART2 Control Register 2
UART 2
0x00207088
UCR3_2
UART2 Control Register 3
UART 2
0x0020708C
UCR4_2
UART2 Control Register 4
UART 2
0x00207090
UFCR_2
UART2 FIFO Control Register
UART 2
0x00207094
USR1_2
UART2 Status Register 1
UART 2
0x00207098
USR2_2
UART2 Status Register 2
UART 2
0x0020709C
UESC_2
UART2 Escape Character Register
UART 2
0x002070A0
UTIM_2
UART2 Escape Timer Register
UART 2
0x002070A4
UBIR_2
UART2 BRM Incremental Register
UART 2
0x002070A8
UBMR_2
UART2 BRM Modulator Register
MC9328MX1 Reference Manual, Rev. 6.1
3-10
Freescale Semiconductor
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
UART 2
0x002070AC
UBRC_2
UART2 Baud Rate Count Register
UART 2
0x002070B0
BIPR1_2
UART2 BRM Incremental Preset Register 1
UART 2
0x002070B4
BIPR2_2
UART2 BRM Incremental Preset Register 2
UART 2
0x002070B8
BIPR3_2
UART2 BRM Incremental Preset Register 3
UART 2
0x002070BC
BIPR4_2
UART2 BRM Incremental Preset Register 4
UART 2
0x002070C0
BMPR1_2
UART2 BRM Modulator Preset Register 1
UART 2
0x002070C4
BMPR2_2
UART2 BRM Modulator Preset Register 2
UART 2
0x002070C8
BMPR3_2
UART2 BRM Modulator Preset Register 3
UART 2
0x002070CC
BMPR4_2
UART2 BRM Modulator Preset Register 4
UART 2
0x002070D0
UTS_2
UART2 Test Register 1
PWM
0x00208000
PWMC
PWM Control Register
PWM
0x00208004
PWMS
PWM Sample Register
PWM
0x00208008
PWMP
PWM Period Register
PWM
0x0020800C
PWMCNT
PWM Counter Register
DMAC
0x00209000
DCR
DMA Control Register
DMAC
0x00209004
DISR
DMA Interrupt Status Register
DMAC
0x00209008
DIMR
DMA Interrupt Mask Register
DMAC
0x0020900C
DBTOSR
DMA Burst Time-Out Status Register
DMAC
0x00209010
DRTOSR
DMA Request Time-Out Status Register
DMAC
0x00209014
DSESR
DMA Transfer Error Status Register
DMAC
0x00209018
DBOSR
DMA Buffer Overflow Status Register
DMAC
0x0020901C
DBTOCR
DMA Burst Time-Out Control Register
DMAC
0x00209040
WSRA
W-Size Register A
DMAC
0x00209044
XSRA
X-Size Register A
DMAC
0x00209048
YSRA
Y-Size Register A
DMAC
0x0020904C
WSRB
W-Size Register B
DMAC
0x00209050
XSRB
X-Size Register B
DMAC
0x00209054
YSRB
Y-Size Register B
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
3-11
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
DMAC
0x00209080
SAR0
Channel 0 Source Address Register
DMAC
0x00209084
DAR0
Channel 0 Destination Address Register
DMAC
0x00209088
CNTR0
Channel 0 Count Register
DMAC
0x0020908C
CCR0
Channel 0 Control Register
DMAC
0x00209090
RSSR0
DMAC
0x00209094
BLR0
DMAC
0x00209098
RTOR0
BUCR0
DMAC
0x002090C0
SAR1
Channel 1 Source Address Register
DMAC
0x002090C4
DAR1
Channel 1 Destination Address Register
DMAC
0x002090C8
CNTR1
Channel 1 Count Register
DMAC
0x002090CC
CCR1
Channel 1 Control Register
DMAC
0x002090D0
RSSR1
DMAC
0x002090D4
BLR1
DMAC
0x002090D8
RTOR1
BUCR1
DMAC
0x00209100
SAR2
Channel 2 Source Address Register
DMAC
0x00209104
DAR2
Channel 2 Destination Address Register
DMAC
0x00209108
CNTR2
Channel 2 Count Register
DMAC
0x0020910C
CCR2
Channel 2 Control Register
DMAC
0x00209110
RSSR2
DMAC
0x00209114
BLR2
DMAC
0x00209118
RTOR2
BUCR2
DMAC
0x00209140
SAR3
Channel 3 Source Address Register
DMAC
0x00209144
DAR3
Channel 3 Destination Address Register
DMAC
0x00209148
CNTR3
Channel 3 Count Register
DMAC
0x0020914C
CCR3
Channel 3 Control Register
DMAC
0x00209150
RSSR3
Channel 0 Request Source Select Register
Channel 0 Burst Length Register
Channel 0 Request Time-Out Register
Channel 0 Bus Utilization Control Register
Channel 1 Request Source Select Register
Channel 1 Burst Length Register
Channel 1 Request Time-Out Register
Channel 1 Bus Utilization Control Register
Channel 2 Request Source Select Register
Channel 2 Burst Length Register
Channel 2 Request Time-Out Register
Channel 2 Bus Utilization Control Register
Channel 3 Request Source Select Register
MC9328MX1 Reference Manual, Rev. 6.1
3-12
Freescale Semiconductor
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
DMAC
0x00209154
BLR3
Channel 3 Burst Length Register
DMAC
0x00209158
RTOR3
BUCR3
DMAC
0x00209180
SAR4
Channel 4 Source Address Register
DMAC
0x00209184
DAR4
Channel 4 Destination Address Register
DMAC
0x00209188
CNTR4
Channel 4 Count Register
DMAC
0x0020918C
CCR4
Channel 4 Control Register
DMAC
0x00209190
RSSR4
DMAC
0x00209194
BLR4
DMAC
0x00209198
RTOR4
BUCR4
DMAC
0x002091C0
SAR5
Channel 5 Source Address Register
DMAC
0x002091C4
DAR5
Channel 5 Destination Address Register
DMAC
0x002091C8
CNTR5
Channel 5 Count Register
DMAC
0x002091CC
CCR5
Channel 5 Control Register
DMAC
0x002091D0
RSSR5
DMAC
0x002091D4
BLR5
DMAC
0x002091D8
RTOR5
BUCR5
DMAC
0x00209200
SAR6
Channel 6 Source Address Register
DMAC
0x00209204
DAR6
Channel 6 Destination Address Register
DMAC
0x00209208
CNTR6
Channel 6 Count Register
DMAC
0x0020920C
CCR6
Channel 6 Control Register
DMAC
0x00209210
RSSR6
DMAC
0x00209214
BLR6
DMAC
0x00209218
RTOR6
BUCR6
DMAC
0x00209240
SAR7
Channel 7 Source Address Register
DMAC
0x00209244
DAR7
Channel 7 Destination Address Register
DMAC
0x00209248
CNTR7
Channel 3 Request Time-Out Register
Channel 3 Bus Utilization Control Register
Channel 4 Request Source Select Register
Channel 4 Burst Length Register
Channel 4 Request Time-Out Register
Channel 4 Bus Utilization Control Register
Channel 5 Request Source Select Register
Channel 5 Burst Length Register
Channel 5 Request Time-Out Register
Channel 5 Bus Utilization Control Register
Channel 6 Request Source Select Register
Channel 6 Burst Length Register
Channel 6 Request Time-Out Register
Channel 6 Bus Utilization Control Register
Channel 7 Count Register
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
3-13
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
DMAC
0x0020924C
CCR7
DMAC
0x00209250
RSSR7
DMAC
0x00209254
BLR7
DMAC
0x00209258
RTOR7
BUCR7
DMAC
0x00209280
SAR8
Channel 8 Source Address Register
DMAC
0x00209284
DAR8
Channel 8 Destination Address Register
DMAC
0x00209288
CNTR8
Channel 8 Count Register
DMAC
0x0020928C
CCR8
Channel 8 Control Register
DMAC
0x00209290
RSSR8
DMAC
0x00209294
BLR8
DMAC
0x00209298
RTOR8
BUCR8
DMAC
0x002092C0
SAR9
Channel 9 Source Address Register
DMAC
0x002092C4
DAR9
Channel 9 Destination Address Register
DMAC
0x002092C8
CNTR9
Channel 9 Count Register
DMAC
0x002092CC
CCR9
Channel 9 Control Register
DMAC
0x002092D0
RSSR9
DMAC
0x002092D4
BLR9
DMAC
0x002092D8
RTOR9
BUCR9
Channel 9 Request Time-Out Register
Channel 9 Bus Utilization Control Register
DMAC
0x00209300
SAR10
Channel 10 Source Address Register
DMAC
0x00209304
DAR10
Channel 10 Destination Address Register
DMAC
0x00209308
CNTR10
Channel 10 Count Register
DMAC
0x0020930C
CCR10
Channel 10 Control Register
DMAC
0x00209310
RSSR10
DMAC
0x00209314
BLR10
DMAC
0x00209318
RTOR10
BUCR10
DMAC
0x00209340
TCR
Channel 7 Control Register
Channel 7 Request Source Select Register
Channel 7 Burst Length Register
Channel 7 Request Time-Out Register
Channel 7 Bus Utilization Control Register
Channel 8 Request Source Select Register
Channel 8 Burst Length Register
Channel 8 Request Time-Out Register
Channel 8 Bus Utilization Control Register
Channel 9 Request Source Select Register
Channel 9 Burst Length Register
Channel 10 Request Source Select Register
Channel 10 Burst Length Register
Channel 10 Request Time-Out Register
Channel 10 Bus Utilization Control Register
Test Control Register
MC9328MX1 Reference Manual, Rev. 6.1
3-14
Freescale Semiconductor
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
DMAC
0x00209344
TFIFOAR
DMAC
0x00209348
TDRR
Test DMA Request Register
DMAC
0x0020934C
TDIPR
Test DMA In Progress Register
DMAC
0x00209350
TFIFOBR
Test FIFO B Register
UART 3
0x0020A000
URX0D_3
UART3 Receiver Register 0
UART 3
0x0020A004
URX1D_3
UART3 Receiver Register 1
UART 3
0x0020A008
URX2D_3
UART3 Receiver Register 2
UART 3
0x0020A00C
URX3D_3
UART3 Receiver Register 3
UART 3
0x0020A010
URX4D_3
UART3 Receiver Register 4
UART 3
0x0020A014
URX5D_3
UART3 Receiver Register 5
UART 3
0x0020A018
URX6D_3
UART3 Receiver Register 6
UART 3
0x0020A01C
URX7D_3
UART3 Receiver Register 7
UART 3
0x0020A020
URX8D_3
UART3 Receiver Register 8
UART 3
0x0020A024
URX9D_3
UART3 Receiver Register 9
UART 3
0x0020A028
URX10D_3
UART3 Receiver Register 10
UART 3
0x0020A02C
URX11D_3
UART3 Receiver Register 11
UART 3
0x0020A030
URX12D_3
UART3 Receiver Register 12
UART 3
0x0020A034
URX13D_3
UART3 Receiver Register 13
UART 3
0x0020A038
URX14D_3
UART3 Receiver Register 14
UART 3
0x0020A03C
URX15D_3
UART3 Receiver Register 15
UART 3
0X0020A040
UTX0D_3
UART3 Transmitter Register 0
UART 3
0X0020A044
UTX1D_3
UART3 Transmitter Register 1
UART 3
0X0020A048
UTX2D_3
UART3 Transmitter Register 2
UART 3
0X0020A04C
UTX3D_3
UART3 Transmitter Register 3
UART 3
0X0020A050
UTX4D_3
UART3 Transmitter Register 4
UART 3
0X0020A054
UTX5D_3
UART3 Transmitter Register 5
UART 3
0X0020A058
UTX6D_3
UART3 Transmitter Register 6
UART 3
0X0020A05C
UTX7D_3
UART3 Transmitter Register 7
Test FIFO A Register
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
3-15
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
UART 3
0X0020A060
UTX8D_3
UART3 Transmitter Register 8
UART 3
0X0020A064
UTX9D_3
UART3 Transmitter Register 9
UART 3
0X0020A068
UTX10D_3
UART3 Transmitter Register 10
UART 3
0X0020A06C
UTX11D_3
UART3 Transmitter Register 11
UART 3
0X0020A070
UTX12D_3
UART3 Transmitter Register 12
UART 3
0X0020A074
UTX13D_3
UART3 Transmitter Register 13
UART 3
0X0020A078
UTX14D_3
UART3 Transmitter Register 14
UART 3
0X0020A07C
UTX15D_3
UART3 Transmitter Register 15
UART 3
0x0020A080
UCR1_3
UART3 Control Register 1
UART 3
0x0020A088
UCR2_3
UART3 Control Register 2
UART 3
0x0020A088
UCR3_3
UART3 Control Register 3
UART 3
0x0020A08C
UCR4_3
UART3 Control Register 4
UART 3
0x0020A090
UFCR_3
UART3 FIFO Control Register
UART 3
0x0020A094
USR1_3
UART3 Status Register 1
UART 3
0x0020A098
USR2_3
UART3 Status Register 2
UART 3
0x0020A09C
UESC_3
UART3 Escape Character Register
UART 3
0x0020A0A0
UTIM_3
UART3 Escape Timer Register
UART 3
0x0020A0A4
UBIR_3
UART3 BRM Incremental Register
UART 3
0x0020A0A8
UBMR_3
UART3 BRM Modulator Register
UART 3
0x0020A0AC
UBRC_3
UART3 Baud Rate Count Register
UART 3
0x0020A0B0
BIPR1_3
UART3 BRM Incremental Preset Register 1
UART 3
0x0020A0B4
BIPR2_3
UART3 BRM Incremental Preset Register 2
UART 3
0x0020A0B8
BIPR3_3
UART3 BRM Incremental Preset Register 3
UART 3
0x0020A0BC
BIPR4_3
UART3 BRM Incremental Preset Register 4
UART 3
0x0020A0C0
BMPR1_3
UART3 BRM Modulator Preset Register 1
UART 3
0x0020A0C4
BMPR2_3
UART3 BRM Modulator Preset Register 2
UART 3
0x0020A0C8
BMPR3_3
UART3 BRM Modulator Preset Register 3
UART 3
0x0020A0CC
BMPR4_3
UART3 BRM Modulator Preset Register 4
MC9328MX1 Reference Manual, Rev. 6.1
3-16
Freescale Semiconductor
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
UART 3
0x0020A0D0
UTS_3
SIM
0x00211000
PORT_CNTL
SIM
0x00211004
CNTL
SIM
0x00211008
RCV_THRESHOLD
SIM
0x0021100C
ENABLE
SIM
0x00211010
XMT_STATUS
Transmit Status Register
SIM
0x00211014
RCV_STATUS
Receive Status Register
SIM
0x00211018
INT_MASK
Interrupt Mask Register
SIM
0x0021101C
XMT_BUF
Port Transmit Buffer Register
SIM
0x00211020
RCV_BUF
Receive Buffer Register
SIM
0x00211024
PORT_DETECT
SIM
0x00211028
XMT_THRESHOLD
SIM
0x0021102C
GUARD_CNTL
SIM
0x00211030
OD_CONFIG
Open-Drain Configuration Control Register
SIM
0x00211034
RESET_CNTL
Reset Control Register
SIM
0x00211038
CHAR_WAIT
SIM
0x0021103C
GPCNT
SIM
0x00211040
DIVISOR
USBD
0x00212000
USB_FRAME
USBD
0x00212004
USB_SPEC
USB Specification and Release Number Register
USBD
0x00212008
USB_STAT
USB Status Register
USBD
0x0021200C
USB_CTRL
USB Control Register
USBD
0x00212010
USB_DADR
USB Descriptor RAM Address Register
USBD
0x00212014
USB_DDAT
USB Descriptor RAM/Endpoint Buffer Data Register
USBD
0x00212018
USB_INTR
USB Interrupt Status Register
USBD
0x0021201C
USB_MASK
USB Interrupt Mask Register
USBD
0x00212024
USB_ENAB
USB Enable Register
USBD
0x00212030
USB_EP0_STAT
UART3 Test Register 1
Port Control Register
Control Register
Receive Threshold Register
Transmit/Receive Enable Register
Detect Register
Transmit Threshold Register
Transmit Guard Control Register
Character Wait Timer Register
General Purpose Counter Register
Divisor Register
USB Frame Number and Match Register
Endpoint 0 Status/Control Register
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
3-17
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
USBD
0x00212034
USB_EP0_INTR
Endpoint 0 Interrupt Status Register
USBD
0x00212038
USB_EP0_MASK
Endpoint 0 Interrupt Mask Register
USBD
0x0021203C
USB_EP0_FDAT
Endpoint 0 FIFO Data Register
USBD
0x00212040
USB_EP0_FSTAT
Endpoint 0 FIFO Status Register
USBD
0x00212044
USB_EP0_FCTRL
Endpoint 0 FIFO Control Register
USBD
0x00212048
USB_EP0_LRFP
Endpoint 0 Last Read Frame Pointer Register
USBD
0x0021204C
USB_EP0_LWFP
Endpoint 0 Last Write Frame Pointer Register
USBD
0x00212050
USB_EP0_FALRM
Endpoint 0 FIFO Alarm Register
USBD
0x00212054
USB_EP0_FRDP
Endpoint 0 FIFO Read Pointer Register
USBD
0x00212058
USB_EP0_FWRP
Endpoint 0 FIFO Write Pointer Register
USBD
0x00212060
USB_EP1_STAT
Endpoint 1 Status/Control Register
USBD
0x00212064
USB_EP1_INTR
Endpoint 1 Interrupt Status Register
USBD
0x00212068
USB_EP1_MASK
Endpoint 1 Interrupt Mask Register
USBD
0x0021206C
USB_EP1_FDAT
Endpoint 1 FIFO Data Register
USBD
0x00212070
USB_EP1_FSTAT
Endpoint 1 FIFO Status Register
USBD
0x00212074
USB_EP1_FCTRL
Endpoint 1 FIFO Control Register
USBD
0x00212078
USB_EP1_LRFP
Endpoint 1 Last Read Frame Pointer Register
USBD
0x0021207C
USB_EP1_LWFP
Endpoint 1 Last Write Frame Pointer Register
USBD
0x00212080
USB_EP1_FALRM
Endpoint 1 FIFO Alarm Register
USBD
0x00212084
USB_EP1_FRDP
Endpoint 1 FIFO Read Pointer Register
USBD
0x00212088
USB_EP1_FWRP
Endpoint 1 FIFO Write Pointer Register
USBD
0x00212090
USB_EP2_STAT
Endpoint 2 Status/Control Register
USBD
0x00212094
USB_EP2_INTR
Endpoint 2 Interrupt Status Register
USBD
0x00212098
USB_EP2_MASK
Endpoint 2 Interrupt Mask Register
USBD
0x0021209C
USB_EP2_FDAT
Endpoint 2 FIFO Data Register
USBD
0x002120A0
USB_EP2_FSTAT
Endpoint 2 FIFO Status Register
USBD
0x002120A4
USB_EP2_FCTRL
Endpoint 2 FIFO Control Register
USBD
0x002120A8
USB_EP2_LRFP
Endpoint 2 Last Read Frame Pointer Register
MC9328MX1 Reference Manual, Rev. 6.1
3-18
Freescale Semiconductor
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
USBD
0x002120AC
USB_EP2_LWFP
Endpoint 2 Last Write Frame Pointer Register
USBD
0x002120B0
USB_EP2_FALRM
Endpoint 2 FIFO Alarm Register
USBD
0x002120B4
USB_EP2_FRDP
Endpoint 2 FIFO Read Pointer Register
USBD
0x002120B8
USB_EP2_FWRP
Endpoint 2 FIFO Write Pointer Register
USBD
0x002120C0
USB_EP3_STAT
Endpoint 3 Status/Control Register
USBD
0x002120C4
USB_EP3_INTR
Endpoint 3 Interrupt Status Register
USBD
0x002120C8
USB_EP3_MASK
Endpoint 3 Interrupt Mask Register
USBD
0x002120CC
USB_EP3_FDAT
Endpoint 3 FIFO Data Register
USBD
0x002120D0
USB_EP3_FSTAT
Endpoint 3 FIFO Status Register
USBD
0x002120D4
USB_EP3_FCTRL
Endpoint 3 FIFO Control Register
USBD
0x002120D8
USB_EP3_LRFP
Endpoint 3 Last Read Frame Pointer Register
USBD
0x002120DC
USB_EP3_LWFP
Endpoint 3 Last Write Frame Pointer Register
USBD
0x002120E0
USB_EP3_FALRM
Endpoint 3 FIFO Alarm Register
USBD
0x002120E4
USB_EP3_FRDP
Endpoint 3 FIFO Read Pointer Register
USBD
0x002120E8
USB_EP3_FWRP
Endpoint 3 FIFO Write Pointer Register
USBD
0x002120F0
USB_EP4_STAT
Endpoint 4 Status/Control Register
USBD
0x002120F4
USB_EP4_INTR
Endpoint 4 Interrupt Status Register
USBD
0x002120F8
USB_EP4_MASK
Endpoint 4 Interrupt Mask Register
USBD
0x002120FC
USB_EP4_FDAT
Endpoint 4 FIFO Data Register
USBD
0x00212100
USB_EP4_FSTAT
Endpoint 4 FIFO Status Register
USBD
0x00212104
USB_EP4_FCTRL
Endpoint 4 FIFO Control Register
USBD
0x00212108
USB_EP4_LRFP
Endpoint 4 Last Read Frame Pointer Register
USBD
0x0021210C
USB_EP4_LWFP
Endpoint 4 Last Write Frame Pointer Register
USBD
0x00212110
USB_EP4_FALRM
Endpoint 4 FIFO Alarm Register
USBD
0x00212114
USB_EP4_FRDP
Endpoint 4 FIFO Read Pointer Register
USBD
0x00212118
USB_EP4_FWRP
Endpoint 4 FIFO Write Pointer Register
USBD
0x00212120
USB_EP5_STAT
Endpoint 5 Status/Control Register
USBD
0x00212124
USB_EP5_INTR
Endpoint 5 Interrupt Status Register
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
3-19
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
USBD
0x00212128
USB_EP5_MASK
Endpoint 5 Interrupt Mask Register
USBD
0x0021212C
USB_EP5_FDAT
Endpoint 5 FIFO Data Register
USBD
0x00212130
USB_EP5_FSTAT
Endpoint 5 FIFO Status Register
USBD
0x00212134
USB_EP5_FCTRL
Endpoint 5 FIFO Control Register
USBD
0x00212138
USB_EP5_LRFP
Endpoint 5 Last Read Frame Pointer Register
USBD
0x0021213C
USB_EP5_LWFP
Endpoint 5 Last Write Frame Pointer Register
USBD
0x00212140
USB_EP5_FALRM
Endpoint 5 FIFO Alarm Register
USBD
0x00212144
USB_EP5_FRDP
Endpoint 5 FIFO Read Pointer Register
USBD
0x00212148
USB_EP5_FWRP
Endpoint 5 FIFO Write Pointer Register
SPI 1
0x00213000
RXDATAREG1
SPI 1 Rx Data Register
SPI 1
0x00213004
TXDATAREG1
SPI 1 Tx Data Register
SPI 1
0x00213008
CONTROLREG1
SPI 1 Control Register
SPI 1
0x0021300C
INTREG1
SPI 1
0x00213010
TESTREG1
SPI 1
0x00213014
PERIODREG1
SPI 1
0x00213018
DMAREG1
SPI 1
0x0021301C
RESETREG1
MMC/SDHC
0x00214000
STR_STP_CLK
MMC/SDHC
0x00214004
STATUS
MMC/SDHC
0x00214008
CLK_RATE
MMC/SDHC
0x0021400C
CMD_DAT_CONT
MMC/SDHC
0x00214010
RES_TO
MMC/SDHC
0x00214014
READ_TO
MMC/SD Read Time Out Register
MMC/SDHC
0x00214018
BLK_LEN
MMC/SD Block Length Register
MMC/SDHC
0x0021401C
NOB
MMC/SD Number of Blocks Register
MMC/SDHC
0x00214020
REV_NO
MMC/SD Revision Number Register
MMC/SDHC
0x00214024
INT_MASK
MMC/SDHC
0x00214028
CMD
SPI 1 Interrupt Control/Status Register
SPI 1 Test Register
SPI 1 Sample Period Control Register
SPI 1 DMA Control Register
SPI 1 Soft Reset Register
MMC/SD Clock Control Register
MMC/SD Status Register
MMC/SD Clock Rate Register
MMC/SD Command and Data Control Register
MMC/SD Response Time Out Register
MMC/SD Interrupt Mask Register
MMC/SD Command Number Register
MC9328MX1 Reference Manual, Rev. 6.1
3-20
Freescale Semiconductor
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
MMC/SDHC
0x0021402C
ARGH
MMC/SD Higher Argument Register
MMC/SDHC
0x00214030
ARGL
MMC/SD Lower Argument Register
MMC/SDHC
0x00214034
RES_FIFO
MMC/SD Response FIFO Register
MMC/SDHC
0x00214038
BUFFER_ACCESS
ASP
0x00215000
ASP_PADFIFO
Pen Sample FIFO
ASP
0x00215010
ASP_ACNTLCR
Control Register
ASP
0x00215014
ASP_PSMPLRG
Pen A/D Sample Rate Control Register
ASP
0x00215018
ASP_ICNTLR
Interrupt Control Register
ASP
0x0021501C
ASP_ISTATR
Interrupt/Error Status Register
ASP
0x0021502C
ASP_CLKDIV
Clock Divide Register
ASP
0x00215030
ASP_CMPCNTL
Compare Control Register
ASP
0x00215034
ASP_FIFO_PTR
ASP FIFO Pointer Register
BTA
0x00216000
COMMAND
STATUS
BTA
0x00216004
PACKET_HEADER
Packet Header Register
BTA
0x00216008
PAYLOAD_HEADER
Payload Header Register
BTA
0x0021600C
NATIVE_COUNT
BTA
0x00216010
ESTIMATED_COUNT
BTA
0x00216014
OFFSET_COUNT
Offset Count Register
BTA
0x00216018
NATIVECLK_LOW
Native Clock Low Register
BTA
0x0021601C
NATIVECLK_HIGH
Native Clock High Register
BTA
0x00216020
ESTIMATED_CLK_LOW
Estimated Clock Low Register
BTA
0x00216024
ESTIMATED_CLK_HIGH
Estimated Clock High Register
BTA
0x00216028
OFFSET_CLK_LOW
Offset Clock Low Register
BTA
0x0021602C
OFFSET_CLK_HIGH
Offset Clock High Register
BTA
0x00216030
HECCRC_CONTROL
HECCRC Control Register
BTA
0x00216034
WHITE_CONTROL
BTA
0x00216038
ENCRYPTION_CONTROL_X13
MMC/SD Buffer Access Register
Command Register
Status Register
Native Count Register
Estimated Count Register
White Control Register
Encryption Control X13 Register
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
3-21
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
BTA
0x00216040
CORRELATION_TIME_SETUP
CORRELATION_TIME_STAMP
BTA
0x00216048
RF_GPO
BTA
0x0021604C
PWM_RSSI
PWM Received Signal Strength Indicator Register
BTA
0x00216050
TIME_A_B
Time A & B Register
BTA
0x00216054
TIME_C_D
Time C & D Register
BTA
0x00216058
PWM_TX
BTA
0x0021605C
RF_CONTROL
RF_STATUS
BTA
0x00216060
RX_TIME
RX Time Register
BTA
0x00216064
TX_TIME
TX Time Register
BTA
0x00216068
BAT
BTA
0x0021606C
THRESHOLD
CORRELATION_MAX
BTA
0x00216070
SYNCH_WORD_0
Synch Word 0 Register
BTA
0x00216074
SYNCH_WORD_1
Synch Word 1 Register
BTA
0x00216078
SYNCH_WORD_2
Synch Word 2 Register
BTA
0x0021607C
SYNCH_WORD_3
Synch Word 3 Register
BTA
0x00216080
BUF_WORD_0 (LW0)
Buf Word 0 (LW0) Register
BTA
0x00216084
BUF_WORD_1 (LW0)
Buf Word 1 (LW0) Register
BTA
0x00216088
BUF_WORD_2 (LW0)
Buf Word 2 (LW0) Register
BTA
0x0021608C
BUF_WORD_3 (LW0)
Buf Word 3 (LW0) Register
BTA
0x00216090
BUF_WORD_4 (LW0)
Buf Word 4 (LW0) Register
BTA
0x00216094
BUF_WORD_5 (LW0)
Buf Word 5 (LW0) Register
BTA
0x00216098
BUF_WORD_6 (LW0)
Buf Word 6 (LW0) Register
BTA
0x0021609C
BUF_WORD_7 (LW0)
Buf Word 7 (LW0) Register
BTA
0x002160A0
BUF_WORD_8 (LW0)
Buf Word 8 (LW0) Register
BTA
0x002160A4
BUF_WORD_9 (LW0)
Buf Word 9 (LW0) Register
BTA
0x002160A8
BUF_WORD_10 (LW0)
Buf Word 10 (LW0) Register
Correlation Time Setup Register
Correlation Time Stamp Register
RF GPO Register
PWM TX Register
RF Control Register
RF Status Register
Bluetooth Application Timer Register
Threshold Register
Correlation Max Register
MC9328MX1 Reference Manual, Rev. 6.1
3-22
Freescale Semiconductor
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
BTA
0x002160AC
BUF_WORD_11 (LW0)
Buf Word 11 (LW0) Register
BTA
0x002160B0
BUF_WORD_12 (LW0)
Buf Word 12 (LW0) Register
BTA
0x002160B4
BUF_WORD_13 (LW0)
Buf Word 13 (LW0) Register
BTA
0x002160B8
BUF_WORD_14 (LW0)
Buf Word 14 (LW0) Register
BTA
0x002160BC
BUF_WORD_15 (LW0)
Buf Word 15 (LW0) Register
BTA
0x002160C0
BUF_WORD_16 (LW0)
Buf Word 16 (LW0) Register
BTA
0x002160C4
BUF_WORD_17 (LW0)
Buf Word 17 (LW0) Register
BTA
0x002160C8
BUF_WORD_18 (LW0)
Buf Word 18 (LW0) Register
BTA
0x002160CC
BUF_WORD_19 (LW0)
Buf Word 19 (LW0) Register
BTA
0x002160D0
BUF_WORD_20 (LW0)
Buf Word 20 (LW0) Register
BTA
0x002160D4
BUF_WORD_21 (LW0)
Buf Word 21 (LW0) Register
BTA
0x002160D8
BUF_WORD_22 (LW0)
Buf Word 22 (LW0) Register
BTA
0x002160DC
BUF_WORD_23 (LW0)
Buf Word 23 (LW0) Register
BTA
0x002160E0
BUF_WORD_24 (LW0)
Buf Word 24 (LW0) Register
BTA
0x002160E4
BUF_WORD_25 (LW0)
Buf Word 25 (LW0) Register
BTA
0x002160E8
BUF_WORD_26 (LW0)
Buf Word 26 (LW0) Register
BTA
0x002160EC
BUF_WORD_27 (LW0)
Buf Word 27 (LW0) Register
BTA
0x002160F0
BUF_WORD_28 (LW0)
Buf Word 28 (LW0) Register
BTA
0x002160F4
BUF_WORD_29 (LW7)
Buf Word 29 (LW7) Register
BTA
0x002160F8
BUF_WORD_30 (LW7)
Buf Word 30 (LW7) Register
BTA
0x002160FC
BUF_WORD_31 (LW7)
Buf Word 31 (LW7) Register
BTA
0x00216100
WAKEUP_1
WakeUp 1 Register
BTA
0x00216104
WAKEUP_2
WakeUp 2 Register
BTA
0x0021610C
WAKEUP_DELTA4
WAKEUP_4
WakeUp Delta4 Register
WakeUp 4 Register
BTA
0x00216110
WU_CONTROL
WU_STATUS
WakeUp Control Register
WakeUp Status Register
BTA
0x00216114
WU_COUNT
WakeUp Count Register
BTA
0x00216118
CLK_CONTROL
Clock Control Register
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
3-23
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
BTA
0x00216120
SPI_WORD0
SPI Word0 Register
BTA
0x00216124
SPI_WORD1
SPI Word1 Register
BTA
0x00216128
SPI_WORD2
SPI Word2 Register
BTA
0x0021612C
SPI_WORD3
SPI Word3 Register
BTA
0x00216130
SPI_WRITE_ADDR
SPI Write Address Register
BTA
0x00216134
SPI_READ_ADDR
SPI Read Address Register
BTA
0x00216138
SPI_CONTROL
SPI_STATUS
BTA
0x00216140
HOP0
HOP_FREQ_OUT
Hop 0 (Frequency In) Register
Hop Frequency Out Register
BTA
0x00216144
HOP1
Hop 1 (Frequency In) Register
BTA
0x00216148
HOP2
Hop 2 (Frequency In) Register
BTA
0x0021614C
HOP3
Hop 3 (Frequency In) Register
BTA
0x00216150
HOP4
Hop 4 (Frequency In) Register
BTA
0x00216160
INTERRUPT_VECTOR
BTA
0x00216170
SYNC_METRIC
BTA
0x00216174
SYNC_FC
BTA
0x00216178
WORD_REVERSE
Word Reverse Register
BTA
0x0021617C
BYTE_REVERSE
Byte Reverse Register
I2C
0x00217000
IADR
I2C Address Register
I2C
0x00217004
IFDR
I2C Frequency Divider Register
I2C
0x00217008
I2CR
I2C Control Register
I2C
0x0021700C
I2CSR
I2C Status Register
I2C
0x00217010
I2DR
I2C Data I/O Register
SSI 1
0x00218000
STX
SSI1 Transmit Data Register
SSI 1
0x00218004
SRX
SSI1 Receive Data Register
SSI 1
0x00218008
SCSR
SSI1 Control/Status Register
SSI 1
0x0021800C
STCR
SSI1 Transmit Configuration Register
SSI 1
0x00218010
SRCR
SSI1 Receive Configuration Register
SPI Control Register
SPI Status Register
Interrupt Vector Register
Synchronization Metric Register
Synchronize Frequency Carrier Register
MC9328MX1 Reference Manual, Rev. 6.1
3-24
Freescale Semiconductor
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
SSI 1
0x00218014
STCCR
SSI1 Transmit Clock Control Register
SSI 1
0x00218018
SRCCR
SSI1 Receive Clock Control Register
SSI 1
0x0021801C
STSR
SSI 1
0x00218020
SFCSR
SSI 1
0x00218028
SOR
SPI 2
0x00219000
RXDATAREG2
SPI 2 Rx Data Register
SPI 2
0x00219004
TXDATAREG2
SPI 2 Tx Data Register
SPI 2
0x00219008
CONTROLREG2
SPI 2 Control Register
SPI 2
0x0021900C
INTREG2
SPI 2
0x00219010
TESTREG2
SPI 2
0x00219014
PERIODREG2
SPI 2
0x00219018
DMAREG2
SPI 2
0x0021901C
RESETREG2
MSHC
0x0021A000
MSCMD
MSHC
0x0021A002
MSCS
MSHC
0x0021A004
MSTDATA
Memory Stick Transmit FIFO Data Register
MSHC
0x0021A004
MSRDATA
Memory Stick Receive FIFO Data Register
MSHC
0x0021A006
MSICS
MSHC
0x0021A008
MSPPCD
MSHC
0x0021A00A
MSC2
MSHC
0x0021A00C
MSACD
MSHC
0x0021A00E
MSFAECS
MSHC
0x0021A010
MSCLKD
Memory Stick Serial Clock Divider Register
MSHC
0x0021A012
MSDRQC
Memory Stick DMA Request Control Register
PLLCLK
0x0021B000
CSCR
PLLCLK
0x0021B004
MPCTL0
MCU PLL Control Register 0
PLLCLK
0x0021B0008
MPCTL1
MCU PLL and System Clock Control Register 1
SSI1 Time Slot Register
SSI1 FIFO Control/Status Register
SSI Option Register
SPI 2 Interrupt Control/Status Register
SPI 2 Test Register
SPI 2 Sample Period Control Register
SPI 2 DMA Control Register
SPI 2 Soft Reset Register
Memory Stick Command Register
Memory Stick Control/Status Register
Memory Stick Interrupt Control/Status Register
Memory Stick Parallel Port Control/Data Register
Memory Stick Control 2 Register
Memory Stick Auto Command Register
Memory Stick FIFO Access Error Control/Status
Register
Clock Source Control Register
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
3-25
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
PLLCLK
0x0021B00C
UPCTL0
USB PLL Control Register 0
PLLCLK
0x0021B010
UPCTL1
USB PLL Control Register 1
PLLCLK
0x0021B020
PCDR
RESET
0x0021B800
RSR
Reset Source Register
SYS CTRL
0x0021B804
SIDR
Silicon ID Register
SYS CTRL
0x0021B808
FMCR
Function Multiplexing Control Register
SYS CTRL
0x0021B80C
GPCR
Global Peripheral Control Register
GPIO A
0x0021C000
DDIR_A
Port A Data Direction Register
GPIO A
0x0021C004
OCR1_A
Port A Output Configuration Register 1
GPIO A
0x0021C008
OCR2_A
Port A Output Configuration Register 2
GPIO A
0x0021C00C
ICONFA1_A
Port A Input Configuration Register A1
GPIO A
0x0021C010
ICONFA2_A
Port A Input Configuration Register A2
GPIO A
0x0021C014
ICONFB1_A
Port A Input Configuration Register B1
GPIO A
0x0021C018
ICONFB2_A
Port A Input Configuration Register B2
GPIO A
0x0021C01C
DR_A
GPIO A
0x0021C020
GIUS_A
Port A GPIO In Use Register
GPIO A
0x0021C024
SSR_A
Port A Sample Status Register
GPIO A
0x0021C028
ICR1_A
Port A Interrupt Configuration Register 1
GPIO A
0x0021C02C
ICR2_A
Port A Interrupt Configuration Register 2
GPIO A
0x0021C030
IMR_A
Port A Interrupt Mask Register
GPIO A
0x0021C034
ISR_A
Port A Interrupt Status Register
GPIO A
0x0021C038
GPR_A
Port A General Purpose Register
GPIO A
0x0021C03C
SWR_A
Port A Software Reset Register
GPIO A
0x0021C040
PUEN_A
Port A Pull_Up Enable Register
GPIO B
0x0021C100
DDIR_B
Port B Data Direction Register
GPIO B
0x0021C104
OCR1_B
Port B Output Configuration Register 1
GPIO B
0x0021C108
OCR2_B
Port B Output Configuration Register 2
GPIO B
0x0021C10C
ICONFA1_B
Port B Input Configuration Register A1
Peripheral Clock Divider Register
Port A Data Register
MC9328MX1 Reference Manual, Rev. 6.1
3-26
Freescale Semiconductor
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
GPIO B
0x0021C110
ICONFA2_B
Port B Input Configuration Register A2
GPIO B
0x0021C114
ICONFB1_B
Port B Input Configuration Register B1
GPIO B
0x0021C118
ICONFB2_B
Port B Input Configuration Register B2
GPIO B
0x0021C11C
DR_B
GPIO B
0x0021C120
GIUS_B
Port B GPIO In Use Register
GPIO B
0x0021C124
SSR_B
Port B Sample Status Register
GPIO B
0x0021C128
ICR1_B
Port B Interrupt Configuration Register 1
GPIO B
0x0021C12C
ICR2_B
Port B Interrupt Configuration Register 2
GPIO B
0x0021C130
IMR_B
Port B Interrupt Mask Register
GPIO B
0x0021C134
ISR_B
Port B Interrupt Status Register
GPIO B
0x0021C138
GPR_B
Port B General Purpose Register
GPIO B
0x0021C13C
SWR_B
Port B Software Reset Register
GPIO B
0x0021C140
PUEN_B
Port B Pull_Up Enable Register
GPIO C
0x0021C200
DDIR_C
Port C Data Direction Register
GPIO C
0x0021C204
OCR1_C
Port C Output Configuration Register 1
GPIO C
0x0021C208
OCR2_C
Port C Output Configuration Register 2
GPIO C
0x0021C20C
ICONFA1_C
Port C Input Configuration Register A1
GPIO C
0x0021C210
ICONFA2_C
Port C Input Configuration Register A2
GPIO C
0x0021C214
ICONFB1_C
Port C Input Configuration Register B1
GPIO C
0x0021C218
ICONFB2_C
Port C Input Configuration Register B2
GPIO C
0x0021C21C
DR_C
GPIO C
0x0021C220
GIUS_C
Port C GPIO In Use Register
GPIO C
0x0021C224
SSR_C
Port C Sample Status Register
GPIO C
0x0021C228
ICR1_C
Port C Interrupt Configuration Register 1
GPIO C
0x0021C22C
ICR2_C
Port C Interrupt Configuration Register 2
GPIO C
0x0021C230
IMR_C
Port C Interrupt Mask Register
GPIO C
0x0021C234
ISR_C
Port C Interrupt Status Register
GPIO C
0x0021C238
GPR_C
Port C General Purpose Register
Port B Data Register
Port C Data Register
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
3-27
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
GPIO C
0x0021C23C
SWR_C
Port C Software Reset Register
GPIO C
0x0021C240
PUEN_C
Port C Pull_Up Enable Register
GPIO D
0x0021C300
DDIR_D
Port D Data Direction Register
GPIO D
0x0021C304
OCR1_D
Port D Output Configuration Register 1
GPIO D
0x0021C308
OCR2_D
Port D Output Configuration Register 2
GPIO D
0x0021C30C
ICONFA1_D
Port D Input Configuration Register A1
GPIO D
0x0021C310
ICONFA2_D
Port D Input Configuration Register A2
GPIO D
0x0021C314
ICONFB1_D
Port D Input Configuration Register B1
GPIO D
0x0021C318
ICONFB2_D
Port D Input Configuration Register B2
GPIO D
0x0021C31C
DR_D
GPIO D
0x0021C320
GIUS_D
Port D GPIO In Use Register
GPIO D
0x0021C324
SSR_D
Port D Sample Status Register
GPIO D
0x0021C328
ICR1_D
Port D Interrupt Configuration Register 1
GPIO D
0x0021C32C
ICR2_D
Port D Interrupt Configuration Register 2
GPIO D
0x0021C330
IMR_D
Port D Interrupt Mask Register
GPIO D
0x0021C334
ISR_D
Port D Interrupt Status Register
GPIO D
0x0021C338
GPR_D
Port D General Purpose Register
GPIO D
0x0021C33C
SWR_D
Port D Software Reset Register
GPIO D
0x0021C340
PUEN_D
Port D Pull_Up Enable Register
SSI 2
0x0021D000
STX_2
SSI2 Transmit Data Register
SSI 2
0x0021D004
SRX_2
SSI2 Receive Data Register
SSI 2
0x0021D008
SCSR_2
SSI2 Control/Status Register
SSI 2
0x0021D00C
STCR_2
SSI2 Transmit Configuration Register
SSI 2
0x0021D010
SRCR_2
SSI2 Receive Configuration Register
SSI 2
0x0021D014
STCCR_2
SSI2 Transmit Clock Control Register
SSI 2
0x0021D018
SRCCR_2
SSI2 Receive Clock Control Register
SSI 2
0x0021D01C
STSR_2
SSI 2
0x0021D020
SFCSR_2
Port D Data Register
SSI2 Time Slot Register
SSI2 FIFO Control/Status Register
MC9328MX1 Reference Manual, Rev. 6.1
3-28
Freescale Semiconductor
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
SSI 2
0x0021D028
SOR_2
EIM
0x00220000
CS0U
Chip Select 0 Upper Control Register
EIM
0x00220004
CS0L
Chip Select 0 Lower Control Register
EIM
0x00220008
CS1U
Chip Select 1 Upper Control Register
EIM
0x0022000C
CS1L
Chip Select 1 Lower Control Register
EIM
0x00220010
CS2U
Chip Select 2 Upper Control Register
EIM
0x00220014
CS2L
Chip Select 2 Lower Control Register
EIM
0x00220018
CS3U
Chip Select 3 Upper Control Register
EIM
0x0022001C
CS3L
Chip Select 3 Lower Control Register
EIM
0x00220020
CS4U
Chip Select 4 Upper Control Register
EIM
0x00220024
CS4L
Chip Select 4 Lower Control Register
EIM
0x00220028
CS5U
Chip Select 5 Upper Control Register
EIM
0x0022002C
CS5L
Chip Select 5 Lower Control Register
EIM
0x00220030
WEIM
WEIM Configuration Register
SDRAMC
0x00221000
SDCTL0
SDRAM 0 Control Register
SDRAMC
0x00221004
SDCTL1
SDRAM 1 Control Register
SDRAMC
0x00221014
MISCELLANEOUS
Miscellaneous Register
SDRAMC
0x00221018
SDRST
SDRAM Reset Register
MMA
0x00222000
MMA_MAC_MOD
MMA MAC Module Register
MMA
0x00222004
MMA_MAC_CTRL
MMA MAC Control Register
MMA
0x00222008
MMA_MAC_MULT
MMA MAC Multiply Counter Register
MMA
0x0022200C
MMA_MAC_ACCU
MMA MAC Accumulate Counter Register
MMA
0x00222010
MMA_MAC_INTR
MMA MAC Interrupt Register
MMA
0x00222014
MMA_MAC_INTR_MASK
MMA
0x00222018
MMA_MAC_FIFO
MMA
0x0022201C
MMA_MAC_FIFO_STAT
MMA MAC FIFO Status Register
MMA
0x00222020
MMA_MAC_BURST
MMA MAC Burst Count Register
MMA
0x00222024
MMA_MAC_BITSEL
MMA MAC Bit Select Register
SSI2 Option Register
MMA MAC Interrupt Mask Register
MMA MAC FIFO Register
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
3-29
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
MMA
0x00222200
MMA_MAC_XBASE
MMA MAC X Base Address Register
MMA
0x00222204
MMA_MAC_XINDEX
MMA MAC X Index Register
MMA
0x00222208
MMA_MAC_XLENGTH
MMA MAC X Length Register
MMA
0x0022220C
MMA_MAC_XMODIFY
MMA MAC X Modify Register
MMA
0x00222210
MMA_MAC_XINCR
MMA
0x00222214
MMA_MAC_XCOUNT
MMA
0x00222300
MMA_MAC_YBASE
MMA MAC Y Base Address Register
MMA
0x00222304
MMA_MAC_YINDEX
MMA MAC Y Index Register
MMA
0x00222308
MMA_MAC_YLENGTH
MMA MAC Y Length Register
MMA
0x0022230C
MMA_MAC_YMODIFY
MMA MAC Y Modify Register
MMA
0x00222310
MMA_MAC_YINCR
MMA
0x00222314
MMA_MAC_YCOUNT
MMA
0x00222400
MMA_DCTCTRL
DCT/iDCT Control Register
MMA
0x00222404
MMA_DCTVERSION
DCT/iDCT Version Register
MMA
0x00222408
MMA_DCTIRQENA
DCT/iDCT IRQ Enable Register
MMA
0x0022240C
MMA_DCTIRQSTAT
DCT/iDCT IRQ Status Register
MMA
0x00222410
DSA_DCTSRCDATA
DCT/iDCT Source Data Address
MMA
0x00222414
MMA_DCTDESDATA
DCT/iDCT Destination Data Address
MMA
0x00222418
MMA_DCTXOFF
DCT/iDCT X-Offset Address
MMA
0x0022241C
MMA_DCTYOFF
DCT/iDCT Y-Offset Address
MMA
0x00222420
MMA_DCTXYCNT
MMA
0x00222424
MMA_DCTSKIP
DCT/iDCT Skip Address
MMA
0x00222500
MMA_DCTFIFO
DCT/iDCT Data FIFO
AITC
0x00223000
INTCNTL
Interrupt Control Register
AITC
0x00223004
NIMASK
Normal Interrupt Mask Register
AITC
0x00223008
INTENNUM
Interrupt Enable Number Register
AITC
0x0022300C
INTDISNUM
Interrupt Disable Number Register
AITC
0x00223010
INTENABLEH
MMA MAC X Increment Register
MMA MAC X Count Register
MMA MAC Y Increment Register
MMA MAC Y Count Register
DCT/iDCT XY Count
Interrupt Enable Register High
MC9328MX1 Reference Manual, Rev. 6.1
3-30
Freescale Semiconductor
Internal Registers
Table 3-2. MC9328MX1 Internal Registers Sorted by Address (continued)
Module Name
Address
Name
Description
AITC
0x00223014
INTENABLEL
AITC
0x00223018
INTTYPEH
Interrupt Type Register High
AITC
0x0022301C
INTTYPEL
Interrupt Type Register Low
AITC
0x00223020
NIPRIORITY7
Normal Interrupt Priority Level Register 7
AITC
0x00223024
NIPRIORITY6
Normal Interrupt Priority Level Register 6
AITC
0x00223028
NIPRIORITY5
Normal Interrupt Priority Level Register 5
AITC
0x0022302C
NIPRIORITY4
Normal Interrupt Priority Level Register 4
AITC
0x00223030
NIPRIORITY3
Normal Interrupt Priority Level Register 3
AITC
0x00223034
NIPRIORITY2
Normal Interrupt Priority Level Register 2
AITC
0x00223038
NIPRIORITY1
Normal Interrupt Priority Level Register 1
AITC
0x0022303C
NIPRIORITY0
Normal Interrupt Priority Level Register 0
AITC
0x00223040
NIVECSR
Normal Interrupt Vector and Status Register
AITC
0x00223044
FIVECSR
Fast Interrupt Vector and Status Register
AITC
0x00223048
INTSRCH
Interrupt Source Register High
AITC
0x0022304C
INTSRCL
Interrupt Source Register Low
AITC
0x00223050
INTFRCH
Interrupt Force Register High
AITC
0x00223054
INTFRCL
Interrupt Force Register Low
AITC
0x00223058
NIPNDH
Normal Interrupt Pending Register High
AITC
0x0022305C
NIPNDL
Normal Interrupt Pending Register Low
AITC
0x00223060
FIPNDH
Fast Interrupt Pending Register High
AITC
0x00223064
FIPNDL
Fast Interrupt Pending Register Low
CSI
0x00224000
CSICR1
CSI Control Register 1
CSI
0x00224004
CSICR2
CSI Control Register 2
CSI
0x00224008
CSISR
CSI Status Register 1
CSI
0x0022400C
CSISTATR
CSI
0x00224010
CSIRXR
Interrupt Enable Register Low
CSI Statistic FIFO Register 1
CSI RxFIFO Register 1
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
3-31
Internal Registers
MC9328MX1 Reference Manual, Rev. 6.1
3-32
Freescale Semiconductor
Chapter 4
ARM920T Processor
This chapter describes the operational features of the ARM920T™ high-performance processor that includes an
overall summary of both the ARM920T processor core and the Thumb® instruction set as well as the operational
modes. For detailed technical and programming information about the ARM920T processor refer to the ARM920T
Technical Reference Manual (ARM Limited: 2001, order number DDI 0151C).
4.1 Introduction
The ARM920T processor is a high-performance 32-bit RISC integer processor macrocell combining an
ARM9TDMI™ core with:
•
16 kbyte instruction and 16 kbyte data caches
•
Instruction and data Memory Management Units (MMUs)
•
Write buffer
•
AMBA™ (Advanced Microprocessor Bus Architecture) bus interface
•
Embedded Trace Macrocell (ETM) interface
An enhanced ARM® architecture v4 MMU implementation provides translation and access permission checks for
instruction and data addresses. The ARM920T high-performance processor solution gives considerable savings in
chip complexity and area, chip system design, and power consumption. The ARM920T processor is 100% user
code binary compatible with ARM7TDMI®, and backwards compatible with the ARM7™ Thumb® Family and
the StrongARM® processor families, giving designers software-compatible processors with a range of
price/performance points from 60 MIPS to 200+ MIPS.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
4-1
ARM920T Macrocell
Figure 4-1. ARM920T Core Functional Block Diagram
4.2 ARM920T Macrocell
The ARM920T macrocell is based on the ARM9TDMI™ Harvard architecture processor core, with an efficient
5-stage pipeline. The architecture of the processor core or integer unit is described in more detail later in this
chapter.
To reduce the effect of main memory bandwidth and latency on performance, the ARM920T processor includes:
•
Instruction cache
•
Data cache
•
MMU
•
TLBs
•
Write buffer
•
Physical address TAG RAM
MC9328MX1 Reference Manual, Rev. 6.1
4-2
Freescale Semiconductor
ARM920T Macrocell
4.2.1 Caches
Two 16 kbyte caches are implemented, one for instructions, the other for data, both with an 8-word line size. A
32-bit data bus connects each cache to the ARM9TDMI core allowing a 32-bit instruction to be fetched and fed
into the instruction Decode stage of the pipeline at the same time as a 32-bit data access for the Memory stage of
the pipeline.
4.2.2 Cache Lock-Down
Cache lock-down is provided to allow critical code sequences to be locked into the cache to ensure predictability
for real-time code. The cache replacement algorithm can be selected by the operating system as either pseudo
random or round-robin. Both caches are 64-way set associative. Lock-down operates on a per-set basis.
4.2.3 Write Buffer
The ARM920T processor also incorporates a 16-entry write buffer, to avoid stalling the processor when writes to
external memory are performed.
4.2.4 PATAG RAM
The ARM920T processor implements PATAG RAM to perform write-backs from the data cache. The physical
address of all the lines held in the data cache is stored by the PATAG memory, removing the need for address
translation when evicting a line from the cache.
4.2.5 MMUs
The standard ARM920T processor implements an enhanced ARM v4 memory management unit (MMU) to
provide translation and access permission checks for the instruction and data address ports of the ARM9TDMI
core.
The MMU features are:
•
Standard ARM9™ v4 MMU mapping sizes, domains, and access protection scheme
•
Mapping sizes are 1 Mbyte sections, 64 kbyte large pages, 4 kbyte small pages, and new 1 kbyte tiny pages
•
Access permissions for sections
•
Access permissions for large pages and small pages can be specified separately for each quarter of the page
(these quarters are called subpages)
•
16 domains implemented in hardware
•
64-entry instruction TLB and 64-entry data TLB
•
Hardware page table walks
•
Round-robin replacement algorithm (also called cyclic)
4.2.6 System Controller
The system controller oversees the interaction between the instruction and data caches and the Bus Interface Unit.
It controls internal arbitration between the blocks and stalls appropriate blocks when required.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
4-3
ARMv4T Architecture
The system controller arbitrates between instruction and data access to schedule single or simultaneous requests to
the MMUs and the Bus Interface Unit. The system controller receives acknowledgement from each resource to
allow execution to continue.
The physical address of all the lines held in the data cache is stored by the PATAG memory, removing the need for
address translation when evicting a line from the cache.
4.2.7 Control Coprocessor (CP15)
The CP15 allows configuration of the caches, the write buffer, and other ARM920T processor options.
Several registers within CP15 are available for program control, providing access to features such as:
•
Invalidate whole TLB using CP15
•
Invalidate TLB entry, selected by modified virtual address, using CP15
•
Independent lock-down of instruction TLB and data TLB using CP15 register 10
•
Big or little-endian operation
•
Low-power state
•
Memory partitioning and protection
•
Page table address
•
Cache and TLB maintenance operations
4.3 ARMv4T Architecture
The following sections summarize the registers and instruction sets of the ARMv4T architecture.
4.3.1 Registers
The ARM920T processor core consists of a 32-bit data path and associated control logic. This data path contains
31 general purpose registers, coupled to a full shifter, Arithmetic Logic Unit, and multiplier. At any one time 16
registers are visible to the user. The remainder are synonyms used to speed up exception processing. Register 15 is
the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction.
R14 holds the return address after a subroutine call. R13 is used (by software convention) as a stack pointer.
4.3.2 Modes and Exception Handling
All exceptions have banked registers for R14 and R13. After an exception, R14 holds the return address for
exception processing. This address is used both to return after the exception is processed and to address the
instruction that caused the exception.
R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast
interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without the need to save or restore
these registers.
A seventh processing mode, System mode, does not have any banked registers. It uses the User mode registers.
System mode runs tasks that require a privileged processor mode and allows them to invoke all classes of
exceptions.
MC9328MX1 Reference Manual, Rev. 6.1
4-4
Freescale Semiconductor
Four Classes of Instructions
4.3.3 Status Registers
All other processor states are held in status registers. The current operating processor status is in the Current
Program Status Register (CPSR). The CPSR holds:
•
Four ALU flags (Negative, Zero, Carry, and Overflow)
•
Two interrupt disable bits (one for each type of interrupt)
•
A bit to indicate ARM9 or Thumb execution
•
Five bits to encode the current processor mode
All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task
immediately before the exception occurred.
4.3.4 Exception Types
ARM9TDMI core supports five types of exception, and a privileged processing mode for each type. The types of
exceptions are:
•
Fast interrupt (FIQ)
•
Normal interrupt (IRQ)
•
Memory aborts (used to implement memory protection or virtual memory)
•
Attempted execution of an undefined instruction
•
Software interrupts (SWIs)
4.3.5 Conditional Execution
All ARM9 instructions (with the exception of BLX) are conditionally executed. Instructions optionally update the
four condition code flags (Negative, Zero, Carry, and Overflow) according to their result. Subsequent instructions
are conditionally executed according to the status of flags. Fifteen conditions are implemented.
4.4 Four Classes of Instructions
The ARM9 and Thumb instruction sets can be divided into four broad classes of instruction:
•
Data processing instructions
•
Load and store instructions
•
Branch instructions
•
Coprocessor instructions
4.4.1 Data Processing Instructions
The data processing instructions operate on data held in general purpose registers. Of the two source operands, one
is always a register. The other has two basic forms:
•
An immediate value
•
A register value optionally shifted
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
4-5
Four Classes of Instructions
If the operand is a shifted register, the shift amount might have an immediate value or the value of another register.
Four types of shift can be specified. Most data processing instructions can perform a shift followed by a logical or
arithmetic operation. Multiply instructions come in two classes:
•
Normal, 32-bit result
•
Long, 32-bit result variants
Both types of multiply instruction can optionally perform an accumulate operation.
4.4.2 Load and Store Instructions
The second class of instruction is load and store instructions. These instructions come in two main types:
•
Load or store the value of a single register
•
Load and store multiple register values
Load and store single register instructions can transfer a 32-bit word, a 16-bit halfword and an 8-bit byte between
memory and a register. Byte and halfword loads might be automatically zero extended or sign extended as they are
loaded. Swap instructions perform an atomic load and store as a synchronization primitive.
4.4.2.1 Addressing Modes
Load and store instructions have three primary addressing modes:
•
Offset
•
Pre-indexed
•
Post-indexed
They are formed by adding or subtracting an immediate or register based offset to or from a base register.
Register-based offsets can also be scaled with shift operations. Pre-indexed and post-indexed addressing modes
update the base register with the base plus offset calculation. As the PC is a general purpose register, a 32-bit value
can be loaded directly into the PC to perform a jump to any address in the 4 Gbyte memory space.
4.4.2.2 Block Transfers
Load and store multiple instructions perform a block transfer of any number of the general purpose registers to or
from memory. Four addressing modes are provided:
•
Pre-increment addressing
•
Post-increment addressing
•
Pre-decrement addressing
•
Post-decrement addressing
The base address is specified by a register value (that can be optionally updated after the transfer). As the
subroutine return address and the PC values are in general-purpose registers, very efficient subroutine calls can be
constructed.
MC9328MX1 Reference Manual, Rev. 6.1
4-6
Freescale Semiconductor
The ARM9 Instruction Set
4.4.3 Branch Instructions
As well as allowing any data processing or load instruction to change control flow (by writing the PC) a standard
branch instruction is provided with 24-bit signed offset, allowing forward and backward branches of up to 32
Mbyte.
4.4.3.1 Branch with Link
There is a Branch with Link (BL) that allows efficient subroutine calls. BL preserves the address of the instruction
after the branch in R14 (the Link Register, or LR). This allows a move instruction to put the LR in to the PC and
return to the instruction after the branch.
The third type of branch (BX and BLX) switches between ARM9 and Thumb instruction sets optionally with the
return address preserving link option.
4.4.4 Coprocessor Instructions
There are three types of coprocessor instructions:
•
Coprocessor data processing instructions invoke a coprocessor-specific internal operation
•
Coprocessor register transfer instructions allow a coprocessor value to be transferred to or from an
ARM920T processor register
•
Coprocessor data transfer instructions transfer coprocessor data to or from memory, where the ARM920T
calculates the address of the transfer
4.5 The ARM9 Instruction Set
The instruction set used by the ARM920T processor is summarized in Table 4-1.
Table 4-1. ARM920T Instruction Set
Mnemonic
Operation
Mnemonic
Operation
MOV
Move
MVN
Move Not
ADD
Add
ADC
Add with Carry
SUB
Subtract
SBC
Subtract with Carry
RSB
Reverse Subtract
RSC
Reverse Subtract with Carry
CMP
Compare
CMN
Compare Negated
TST
Test
TEQ
Test Equivalence
AND
Logical AND
BIC
Bit Clear
FOR
Logical Exclusive OR
ORR
Logical (inclusive) OR
MUL
Multiply
MLA
Multiply Accumulate
SMULL
Sign Long Multiply
SMLAL
Signed Long Multiply Accumulate
UMULL
Unsigned Long Multiply
UMLAL
Unsigned Long Multiply Accumulate
CLZ
Count Leading Zeroes
BKPT
Breakpoint
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
4-7
The ARM Thumb Instruction Set
Table 4-1. ARM920T Instruction Set (continued)
Mnemonic
Operation
Mnemonic
Operation
MRS
Move From Status Register
MSR
Move to Status Register
B
Branch
–
–
BL
Branch and Link
BLX
Branch and Link and Exchange
BX
Branch and Exchange
SWI
Software Interrupt
LDR
Load Word
STR
Store Word
LDRH
Load Halfword
STRH
Store Halfword
LDRB
Load Byte
STRB
Store Byte
LDRSH
Load Signed Halfword
LDRSB
Load Signed Byte
LDMIA
Load Multiple
STMIA
Store Multiple
SWP
Swap Word
SWPB
Swap Byte
CDP
Coprocessor Data Processing
–
–
MRC
Move From Coprocessor
MCR
Move to Coprocessor
LDC
Load To Coprocessor
STC
Store From Coprocessor
4.6 The ARM Thumb Instruction Set
The ARM Thumb instruction set is summarized in Table 4-2.
Table 4-2. ARM Thumb Instruction Set
Mnemonic
Operation
Mnemonic
Operation
MOV
Move
MVN
Move Not
ADD
Add
ADC
Add with Carry
SUB
Subtract
SBC
Subtract with Carry
RSB
Reverse Subtract
RSC
Reverse Subtract with Carry
CMP
Compare
CMN
Compare Negated
TST
Test
NEG
Negate
AND
Logical AND
BIC
Bit Clear
FOR
Logical Exclusive OR
ORR
Logical (inclusive) OR
LSL
Logical Shift Left
LSR
Logical Shift Right
ASR
Arithmetic Shift Right
ROR
Rotate Right
MUL
Multiply
BKPT
Breakpoint
B
Unconditional Branch
Bcc
Conditional Branch
BL
Branch and Link
BLX
Branch and Link and Exchange
MC9328MX1 Reference Manual, Rev. 6.1
4-8
Freescale Semiconductor
The ARM Thumb Instruction Set
Table 4-2. ARM Thumb Instruction Set (continued)
Mnemonic
Operation
Mnemonic
Operation
BX
Branch and Exchange
SWI
Software Interrupt
LDR
Load Word
STR
Store Word
LDRH
Load Halfword
STRH
Store Halfword
LDRB
Load Byte
STRB
Store Byte
LDRSH
Load Signed Halfword
LDRSB
Load Signed Byte
LDMIA
Load Multiple
STMIA
Store Multiple
PUSH
Push Registers to stack
POP
Pop Registers from stack
4.6.1 ARM920T Modes and Registers
The modes and registers of the ARM920T processor are shown in Table 4-3.
Table 4-3. Register Availability by Mode
User and
System Modes
Supervisor
Mode
Abort Mode
Undefined
Mode
Interrupt Mode
Fast Interrupt
Mode
R0
R0
R0
R0
R0
R0
R1
R1
R1
R1
R1
R1
R2
R2
R2
R2
R2
R2
R3
R3
R3
R3
R3
R3
R4
R4
R4
R4
R4
R4
R5
R5
R5
R5
R5
R5
R6
R6
R6
R6
R6
R6
R7
R7
R7
R7
R7
R7
R8
R8
R8
R8
R8
R8_FIQ
R9
R9
R9
R9
R9
R9_FIQ
R10
R10
R10
R10
R10
R10_FIQ
R11
R11
R11
R11
R11
R11_FIQ
R12
R12
R12
R12
R12
R12_FIQ
R13
R13_SVC
R13_ABORT
R13_UNDEF
R13_IRQ
R13_FIQ
R14
R14_SVC
R14_ABORT
R14_UNDEF
R14_IRQ
R14_FIQ
PC
PC
PC
PC
PC
PC
CPSR
CPSR
CPSR
CPSR
CPSR
CPSR
SPSR_SVC
SPSR_ABORT
SPSR_UNDEF
SPSR_IRQ
SPSR_FIQ
= Mode-specific banked registers
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
4-9
The ARM Thumb Instruction Set
MC9328MX1 Reference Manual, Rev. 6.1
4-10
Freescale Semiconductor
Chapter 5
Embedded Trace Macrocell (ETM)
The MC9328MX1 is equipped with an ARM9 Embedded Trace Macrocell™ (ETM9) module for real time
debugging which is a great help to a system designer because the MC9328MX1 is a highly integrated processor, a
very limited number of pins are available for debug purposes. ETM signals in MC9328MX1 are multiplexed with
other function pins. This chapter contains a brief summary of the ETM features, for details of ETM operation,
please refer to the ETM9 Technical Reference Manual Rev.2a (ARM Limited: 2001, order number DDI0157E).
5.1 Introduction to the ETM
The ETM provides instruction and data trace for the ARM9™ family of microprocessors. This document describes
the interface between an ARM Thumb® family processor and the ETM. For details of the interface between an
ARM7™ processor and ETM7, refer to the ETM7 Technical Reference Manual Rev.1 (ARM Limited: 2001, order
number DDI0158D). The block diagram of the ETM is shown in Figure 5-1.
Figure 5-1. ETM Block Diagram
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
5-1
Programming and Reading ETM Registers
5.2 Programming and Reading ETM Registers
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit shift
register comprising:
•
32-bit data field
•
7-bit address field
•
A read/write bit
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field,
and 1 into the read/write bit.
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field
is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.
For further details of ETM registers, see the Embedded Trace Macrocell specification.
5.3 Pin Configuration for ETM
The ETM module uses 13 pins on the MC9328MX1. These pins are multiplexed with other functions on the
device, and must be configured for ETM operation. Table 5-1 identifies the pin configuration, however, only the 5
pins of the 13 that are multiplexed are shown.
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 32.5.1, “Data Direction Registers,” on
page 32-8 for details.
Table 5-1. ETM Pin Configuration
Pin
Setting
Configuration Procedure
ETMTRACESYNC
Alternate function of
GPIO Port A [0]
Clear bit 0 of Port A GPIO In Use Register (GIUS_A)
Set bit 0 of Port A General Purpose Register (GPR_A)
ETMTRACECLK
Alternate function of
GPIO Port A [31]
Clear bit 31 of Port A GPIO In Use Register (GIUS_A)
Set bit 31 of Port A General Purpose Register (GPR_A)
ETMPIPESTAT [2:0]
Alternate function of
GPIO Port A [30:28]
Clear bits [30:28] of Port A GPIO In Use Register (GIUS_A)
Set bits [30:28] of Port A General Purpose Register (GPR_A)
ETMTRACEPKT [7:4]
Alternate function of
GPIO Port A [20:17]
Clear bits [20:17] of Port A GPIO In Use Register (GIUS_A)
Set bits [20:17] of Port A General Purpose Register (GPR_A)
ETMTRACEPKT [3:0]
Alternate function of
GPIO Port A [27:24]
Clear bits [27:24] of Port A GPIO In Use Register (GIUS_A)
Set bits [27:24] of Port A General Purpose Register (GPR_A)
MC9328MX1 Reference Manual, Rev. 6.1
5-2
Freescale Semiconductor
Chapter 6
Reset Module
The reset module controls or distributes all of the system reset signals used by the MC9328MX1. This chapter
provides a detailed description of the operation of this module.
6.1 Functional Description of the Reset Module
A simplified block diagram of the reset module is shown in Figure 6-1. The reset module generates two distinct
events—a global reset and an ARM920T processor reset.
CORE_TRST
TRST
RESET_POR
300 ms
Counter
POR
7-Cycle
Stretcher
RESET_DRAM
CLK32
CLK32
14-Cycle
Stretcher
Sync
Logic
HARD_ASYN_RESET
CLK32
HCLK
RESET_IN
Watchdog
Timer
4-Cycle
Qualifier
Rising
Edge
Detector
DRAM
Controller
ARM9/
Watchdog
Timer
RESET_OUT
HRESET
CLK32
JTAG/ETM
All Modules
Except
Watchdog
Timer
IP Bus
RSR
WAT_RESET
Figure 6-1. Reset Module Block Diagram
6.1.1 Global Reset
A global reset simultaneously asserts three reset signals: HRESET, RESET_DRAM, and CORE_TRST. These
signals remain asserted for 14 CLK32 cycles. The RESET_DRAM signal is deasserted 7 CLK32 cycles before
HRESET and HARD_ASYN_RESET. This 7-cycle period provides the DRAM with time to execute any
necessary self-refresh operations. The timing diagram in Figure 6-2 on page 6-2 shows the relationship of the reset
signal timings. See Table 6-1 for reset module signal and pin definitions.
There is one source capable of generating a global reset: A high condition on the POR pin for at least 4 × 32 kHz
clocks when the 32 kHz crystal oscillator is running.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
6-1
Functional Description of the Reset Module
The following signal conditions are not capable of generating a global reset, however they reset the ARM920T
core:
•
An external qualified low condition on the RESET_IN pin
•
A low condition on WAT_RESET
NOTE:
Due to the asynchronous nature of the RESET signal, the time period required to
qualify the signal may vary, and the HRESET timing relative to the rising edge of
RESET is also affected. A RESET signal shorter than 3 CLK32 cycles will not be
qualified, a RESET signal equal to or longer than 4 CLK32 cycles will always be
qualified, and any period length that is more than 3 and less than 4 CLK32 cycles
is undefined.
IMPORTANT:
POR is the reset signal for all the reset module flip-flops. For this reason, an
external reset signal is qualified if it lasts more than 4 CLK32 cycles when POR is
deasserted.
POR
RESET_POR
300 ms
7 cycles @ CLK32
RESET_DRAM
14 cycles @ CLK32
HRESET
(RESET_OUT)
CLK32
HCLK
Figure 6-2. DRAM and Internal Reset Timing Diagram
6.1.2 ARM920T Processor Reset
Any qualified global reset signal resets the ARM920T processor and all related peripherals to their default state.
After the internal reset is deasserted, the ARM920T processor begins fetching code from the internal bootstrap
ROM, sync flash, or CS0 space. The memory location of the fetch depends on the configuration of the BOOT pins
on the rising edge of HRESET (see Section 8.2, “System Boot Mode Selection,” on page 8-7).
MC9328MX1 Reference Manual, Rev. 6.1
6-2
Freescale Semiconductor
Programming Model
Table 6-1. Reset Module Pin and Signal Descriptions
Signal Name
Direction
Signal Description
CLK32
IN
32 kHz Clock—A 32 kHz clock signal derived from the input crystal oscillator circuit in the
PLL.
POR
IN
Power-On Reset—An internal active high Schmitt trigger signal from the POR pin. The
POR signal is normally generated by an external RC circuit designed to detect a power-up
event.
RESET
IN
Reset—An external active low Schmitt trigger signal from the RESET_IN pin. When
this signal goes active, all modules (except the reset module and the clock control
module) are reset.
TRST
IN
Test Reset Pin—An external active low signal from the TRST pin. The Test Reset Pin is
used to asynchronously initialize the JTAG controller.
WAT_RESET
IN
Watchdog Timer Reset—An active low signal generated by the watchdog timer when a
time-out period has expired.
CORE_TRST
OUT
Core Test Reset—An active low signal that resets the JTAG module and the ETM.
HARD_ASYN_RESET
OUT
Hard Asynchronous Reset—An active low signal that resets all peripheral modules
except the watchdog timer module. The rising edge of this signal is synchronous with
HCLK.
HRESET
OUT
Hard Reset—An active low signal that resets the ARM920T processor and the watchdog
timer module.This signal is deasserted during the low phase of HCLK. This signal also
appears on the RESET_OUT pin of the MC9328MX1.
RESET_DRAM
OUT
DRAM Reset—An active low signal that resets the DRAM controller.
6.2 Programming Model
The Reset Source Register (RSR), the only register in the reset module, can be written to or read by the ARM920T
processor through the IP bus interface.
6.2.1 Reset Source Register (RSR)
The Reset Source Register is a 16-bit read-only register used by the ARM920T processor to determine the source
of the last MC9328MX1. hardware reset. The source of the last hardware reset is defined in Table 6-2 and
Table 6-3 on page 6-4.
If several sources’ signals overlap and if the signals are released during the same CLK32 cycle (which also causes
the assertion of the RESET_OUT signal), only the highest-priority event is registered by the RSR using the
following priority order:
1. POR signal
2. Qualified external reset signal
3. Watchdog signal
Otherwise, the last signal that is released is honored.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
6-3
Programming Model
RSR
Addr
0x0021B800
Reset Source Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
WDR
EXR
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 6-2. RSR Register Description
Name
Description
Settings
Reserved
Bits 31–2
Reserved—These bits are reserved and should read 0.
WDR
Bit 1
Watchdog Reset—Indicates whether the last reset
was caused by a Watchdog count expiration.
0 = Reset was NOT a Watchdog count expiration
1 = Reset WAS a Watchdog count expiration
EXR
Bit 0
External Reset—Indicates whether the last reset was
caused by a RESET_IN pin assertion.
0 = Reset was NOT a RESET_IN pin assertion
1 = Reset WAS a RESET_IN pin assertion
Table 6-3. Hardware Reset Source Matrix
Source
WDR
EXR
POR
0
0
Qualified external reset
0
1
Watchdog time-out
1
0
MC9328MX1 Reference Manual, Rev. 6.1
6-4
Freescale Semiconductor
Chapter 7
AHB to IP Bus Interface (AIPI)
7.1 Overview
This chapter provides an overview of the R-AHB to IP bus interface (AIPI). The AIPI module in the MC9328MX1
acts as an interface between the R-AHB (Reduced ARM Advanced High-performance Bus) and lower bandwidth
peripherals.
7.1.1 Features
The AIPI provides the following features:
•
All peripheral read transactions require a minimum of two system clocks (R-AHB side) and all write
transactions require a minimum of three system clocks (R-AHB side).
•
Support of 8-bit, 16-bit, and 32-bit IP bus peripherals.
•
Byte, half word, and word read and write are supported to and from each peripheral in both big and little
endian mode.
•
Support of multi-cycle accesses (16-bit operations to 8-bit peripherals, and 32-bit operations to 16-bit and
8-bit peripherals).
•
Ability to restrict user to limit access to peripherals in their natural size only.
•
Support of 15 external IP bus peripherals. Muxiplexers are incorporated to support the 15 separate read data
buses, and the transfer wait and transfer error from peripherals.
•
A watchdog timer is provided to time-out peripheral access if operation does not terminate with 512 clock
cycles.
•
Use of a single asynchronous reset and one global clock with both edges.
•
The AIPI module is implemented using MUX-D scan methodology for testability.
7.1.2 General Information
The AIPI is the interface between the R-AHB and on-chip IP bus peripherals as shown in Figure 7-1 on page 7-2.
IP bus peripherals are modules that contain readable/writable control and status registers. The R-AHB master reads
and writes these registers through the AIPI. The AIPI generates module enables, the module address, transfer
attributes, byte enables and write data as inputs to the IP bus peripherals. The AIPI captures read data (qualified by
IPS_XFR_WAIT) from the IP bus interface and drives it on the R-AHB. The AIPI module terminates the transfer
by asserting AIPI_HREADY_OUT.
The register maps of all IP bus peripherals are located on 4096 byte boundaries. Each IP bus peripheral is allocated
one 4-kbyte block (minimum block size) of the memory map, configured as 1024 32-bit internal registers (or 2048
16-bit internal registers, or 4096 8-bit internal registers), activated by one of 15 module enables from the AIPI. Up
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
7-1
Overview
to 15 IP bus peripherals may be implemented, occupying contiguous blocks of 4 kbytes, for a total of 60 kbytes.
The exact address assignment for the IP bus peripherals is system dependent, and is defined in the system
specification. Each IP bus peripheral will select its internal registers based on the address driven on the IPS_ADDR
signals.
The AIPI is responsible for telling the IP bus peripherals if the access is in supervisor or user mode. The AIPI may
block user mode accesses to certain IP bus peripherals or it may allow the individual IP bus peripherals to
determine if user mode accesses are allowed. Please see Section 7.2, “Programming Model,” for more
information.
The AIPI supports multi-cycle accesses to IP bus peripherals when the R-AHB master requests data transfers that
are larger than the targeted IP bus peripheral’s data bus width. Table 7-1 through Table 7-4 provides more
information on both single-cycle and multi-cycle accesses. For data access that are larger than the target IP bus
peripheral, the AIPI will duplicated the data across all the byte lanes on the AHB, i.e. for a word read from 8 bit
peripheral, the same data read will appear on byte lanes [31:24, [23:16], [15:8] and [7:0]. Similarly for a byte write
to the peripheral, the core will duplicate the same byte over the byte lanes of the AHB for the write operation.
haddr[16:0]
HWDATA[31:0]
IPS_WDATA[31:0]
HWDATA[31:0]
IPS_RDATA[15:1][31:
AIPI_HRDATA[31:0]
IPS_MODULE_EN[15:
HPROTL
IPS_ADDR1[11:1]
HTRANSL
IPS_BYTE_15_8
HSIZE[1:0]
AIPI
IPS_BYTE_23_16
HREADY_IN
IPS_BYTE_31_24
AIPI_HRESP[1:0]
IPS_RWB
IP BUS SIGNALS
IPS_BYTE_7_0
HWRITE
AIPI_HREADY_OUT
IPS_XFR_WAIT[15:1]
HCLK
IPS_XFR_ERR[15:1]
HCLK
IPS_SUPERVISOR_A
HSEL_AIPI
IPS_GATED_CLK_EN[1
HRESET
BIGEND_IN
Figure 7-1. AIPI Interface
MC9328MX1 Reference Manual, Rev. 6.1
7-2
Freescale Semiconductor
Overview
dbmx_aipi_16
aipi
aipi_core
hwdata[31:0]
ips_wdata[31:0]
aipi_write_data_path
aipi_current_state
ips_rwb
haddr[16:0]
hsize[1:0]
ips_supervisor_access
hready_in
ips_addr[11:0]
ips_module_en[15:1]
htransl
ips_byte_31_24
hprot
aipi_control
ips_byte_23_16
hsel
ips_byte_15_8
hclk
ips_byte_7_0
hclk
ips_gated_clk_en[15:1]
aipi_hresp[1:0]
hreset
aipi_hready_out
bigend_in
aipi_hrdata
[31:0]
hwrite
aipi_read_data_path
aipi_register_data
aipi_par_en
aipi_psr_err
aipi_register_err
aipi_registers
aipi_register_wait
IP
IP bus_peripheral_size
ips_xfr_wait
aipi_timeout
ips_xfr_err
ips_rdata[31:0]
ips_rdata[15:1][31:0]
aipi_watchdog
aipi_start_transfer
aipi_data_mux
aipi_ip_decode
aipi_xfr_mux
mux_select
[3:0]
ips_xfr_wait[15:1]
ips_xfr_err[15:1]
Figure 7-2. Block Diagram of the AIPI Module
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
7-3
Overview
Table 7-1. R-AHB to IP Bus Interface Operation (Big Endian—Read Operation)
Transfer
Size
Byte
Half Word
haddr
[1]
[0]
IP
Bus
Size
0
0
8-bit
0
Active Bus Section (IP Bus to R-AHB)
[1]
[0]
R-AHB [31:24]
R-AHB [23:16]
R-AHB [15:8]
R-AHB [7:0]
0
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
0
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
0
1
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
1
1
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
0
0
X
ips_rdata[15:8]
ips_rdata[7:0]
–
–
0
1
ips_rdata[15:8]
ips_rdata[7:0]
–
–
1
0
–
–
ips_rdata[15:8]
ips_rdata[7:0]
1
1
–
–
ips_rdata[15:8]
ips_rdata[7:0]
0
0
ips_rdata[31:24]
–
–
–
0
1
–
ips_rdata[23:16]
–
–
1
0
–
–
ips_rdata[15:8]
–
1
1
–
–
–
ips_rdata[7:0]
0
NA
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
X
ips_rdata[15:8]
ips_rdata[7:0]
ips_rdata[15:8]
ips_rdata[7:0]
1
X
ips_rdata[15:8]
ips_rdata[7:0]
ips_rdata[15:8]
ips_rdata[7:0]
X
X
ips_rdata[31:24]
ips_rdata[23:16]
–
–
X
X
–
–
ips_rdata[15:8]
ips_rdata[7:0]
0
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
X
ips_rdata[15:8]
ips_rdata[7:0]
ips_rdata[15:8]
ips_rdata[7:0]
1
X
ips_rdata[15:8]
ips_rdata[7:0]
ips_rdata[15:8]
ips_rdata[7:0]
X
X
ips_rdata[31:24]
ips_rdata[23:16]
ips_rdata[15:8]
ips_rdata[7:0]
16-bit
1
32-bit
8-bit
0
1
0
16-bit
1
0
32-bit
1
NA
X
X
1
Word
ips_addr
NA
8-bit
1
16-bit
32-bit
X
X
X
MC9328MX1 Reference Manual, Rev. 6.1
7-4
Freescale Semiconductor
Overview
Table 7-2. R-AHB to IP Bus Interface Operation (Big Endian—Write Operation)
Transfer
Size
Byte
Half
Word
haddr
[1]
[0]
IP
Bus
Size
0
0
8-bit
0
Active Bus Section (R-AHB to IP Bus)
[1]
[0]
R-AHB [31:24]
R-AHB [23:16]
R-AHB [15:8]
R-AHB [7:0]
0
0
ips_wdata[7:0]
–
–
–
1
0
1
–
ips_wdata[7:0]
–
–
1
0
1
0
–
–
ips_wdata[7:0]
–
1
1
1
1
–
–
–
ips_wdata[7:0]
0
0
0
X
ips_wdata[15:8]
–
–
–
0
1
–
ips_wdata[7:0]
–
–
1
0
–
–
ips_wdata[15:8]
–
1
1
–
–
–
ips_wdata[7:0]
0
0
ips_wdata[31:24]
–
–
–
0
1
–
ips_wdata[23:16]
–
–
1
0
–
–
ips_wdata[15:8]
–
1
1
–
–
–
ips_wdata[7:0]
0
NA
0
ips_wdata[7:0]
–
–
–
1
–
ips_wdata[7:0]
–
–
0
–
–
ips_wdata[7:0]
–
1
–
–
–
ips_wdata[7:0]
0
X
ips_wdata[15:8]
ips_wdata[7:0]
–
–
1
X
–
–
ips_wdata[15:8]
ips_wdata[7:0]
X
X
ips_wdata[31:24]
ips_wdata[23:16]
–
–
X
X
–
–
ips_wdata[15:8]
ips_wdata[7:0]
0
0
ips_wdata[7:0]
–
–
–
1
–
ips_wdata[7:0]
–
–
0
–
–
ips_wdata[7:0]
–
1
–
–
–
ips_wdata[7:0]
0
X
ips_wdata[15:8]
ips_wdata[7:0]
–
–
1
X
–
–
ips_wdata[15:8]
ips_wdata[7:0]
X
X
ips_wdata[31:24]
ips_wdata[23:16]
ips_wdata[15:8]
ips_wdata[7:0]
16-bit
1
32-bit
8-bit
0
1
0
16-bit
1
0
32-bit
1
NA
X
X
1
Word
ips_addr
NA
8-bit
1
16-bit
32-bit
X
X
X
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
7-5
Overview
Table 7-3. R-AHB to IP Bus Interface Operation (Little Endian—Read Operation)
Transfer
Size
Byte
Half
Word
haddr
[1]
[0]
IP
Bus
Size
0
0
8-bit
0
Active Bus Section (IP Bus to R-AHB)
[1]
[0]
R-AHB [31:24]
R-AHB [23:16]
R-AHB [15:8]
R-AHB [7:0]
0
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
0
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
0
1
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
1
1
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
0
0
X
–
–
ips_rdata[15:8]
ips_rdata[7:0]
0
1
–
–
ips_rdata[15:8]
ips_rdata[7:0]
1
0
ips_rdata[15:8]
ips_rdata[7:0]
–
–
1
1
ips_rdata[15:8]
ips_rdata[7:0]
–
–
0
0
–
–
–
ips_rdata[7:0]
0
1
–
–
ips_rdata[15:8]
–
1
0
–
ips_rdata[23:16]
–
–
1
1
ips_rdata[31:24]
–
–
–
0
NA
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
X
ips_rdata[15:8]
ips_rdata[7:0]
ips_rdata[15:8]
ips_rdata[7:0]
1
X
ips_rdata[15:8]
ips_rdata[7:0]
ips_rdata[15:8]
ips_rdata[7:0]
X
X
–
–
ips_rdata[15:8]
ips_rdata[7:0]
X
X
ips_rdata[31:24]
ips_rdata[23:16]
–
–
0
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
1
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
ips_rdata[7:0]
0
X
ips_rdata[15:8]
ips_rdata[7:0]
ips_rdata[15:8]
ips_rdata[7:0]
1
X
ips_rdata[15:8]
ips_rdata[7:0]
ips_rdata[15:8]
ips_rdata[7:0]
X
X
ips_rdata[31:24]
ips_rdata[23:16]
ips_rdata[15:8]
ips_rdata[7:0]
16-bit
1
32-bit
8-bit
0
1
0
16-bit
1
0
32-bit
1
NA
X
X
1
Word
ips_addr
NA
8-bit
1
16-bit
32-bit
X
X
X
MC9328MX1 Reference Manual, Rev. 6.1
7-6
Freescale Semiconductor
Overview
Table 7-4. R-AHB to IP Bus Interface Operation (Little Endian—Write Operation)
Transfer
Size
Byte
Half
Word
haddr
[1]
[0]
0
0
0
IP Bus
Size
Active Bus Section (R-AHB to IP Bus)
[1]
[0]
R-AHB [31:24]
R-AHB [23:16]
R-AHB [15:8]
R-AHB [7:0]
0
0
–
–
–
ips_wdata[7:0]
1
0
1
–
–
ips_wdata[7:0]
–
1
0
1
0
–
ips_wdata[7:0]
–
–
1
1
1
1
ips_wdata[7:0]
–
–
–
0
0
0
X
–
–
–
ips_wdata[7:0]
0
1
–
–
ips_wdata[15:8]
–
1
0
–
ips_wdata[7:0]
–
–
1
1
ips_wdata[15:8]
–
–
–
0
0
–
–
–
ips_wdata[7:0]
0
1
–
–
ips_wdata[15:8]
–
1
0
–
ips_wdata[23:16]
–
–
1
1
ips_wdata[31:24]
–
–
–
0
NA
0
–
–
–
ips_wdata[7:0]
1
–
–
ips_wdata[7:0]
–
0
–
ips_wdata[7:0]
–
–
1
ips_wdata[7:0]
–
–
–
0
X
–
–
ips_wdata[15:8]
ips_wdata[7:0]
1
X
ips_wdata[15:8]
ips_wdata[7:0]
–
–
X
X
–
–
ips_wdata[15:8]
ips_wdata[7:0]
X
X
ips_wdata[31:24]
ips_wdata[23:16]
–
–
0
0
–
–
–
ips_wdata[7:0]
1
–
–
ips_wdata[7:0]
–
0
–
ips_wdata[7:0]
–
–
1
ips_wdata[7:0]
–
–
–
0
X
–
–
ips_wdata[15:8]
ips_wdata[7:0]
1
X
ips_wdata[15:8]
ips_wdata[7:0]
–
–
X
X
ips_wdata[31:24]
ips_wdata[23:16]
ips_wdata[15:8]
ips_wdata[7:0]
8-bit
16-bit
1
32-bit
8-bit
0
1
0
16-bit
1
0
32-bit
1
NA
X
X
1
Word
ips_addr
NA
8-bit
1
16-bit
32-bit
X
X
X
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
7-7
Programming Model
7.2 Programming Model
There are six registers that reside inside the AIPI module. Two system clocks are required for read accesses and
three system clocks are required for write accesses to the AIPI registers. Table 7-5 is a summary of these registers
and their addresses.
Table 7-5. AIPI Module Register Memory Map
Description
Name
Address
AIPI1 Peripheral Size Register 0
PSR0_1
0x00200000
AIPI1 Peripheral Size Register 1
PSR1_1
0x00200004
AIPI1 Peripheral Access Register
PAR_1
0x00200008
AIPI1 Peripheral Control Register
PCR_1
0x0020000C
AIPI1 Time-Out Status Register
TSR_1
0x00200010
AIPI2 Peripheral Size Register 0
PSR0_2
0x00210000
AIPI2 Peripheral Size Register 1
PSR1_2
0x00210004
AIPI2 Peripheral Access Register
PAR_2
0x00210008
AIPI2 Peripheral Control Register
PCR_2
0x0021000C
AIPI2Time-Out Status Register
TSR_2
0x00210010
AIPI1
AIPI2
Table 7-6 illustrates the peripheral address associated with the corresponding module_en number. Refer to
Chapter 3, “Memory Map,” to see the corresponding address assigned to each peripheral.
Table 7-6. Peripheral Address MODULE_EN Numbers
AIPI 1
AIPI 2
Address
MODULE_EN
Address
MODULE_EN
0x0020 1000 – 0x0020 1FFF
1
0x0021 1000 – 0x0021 1FFF
1
0x0020 2000 – 0x0020 2FFF
2
0x0021 2000 – 0x0021 2FFF
2
0x0020 3000 – 0x0020 3FFF
3
0x0021 3000 – 0x0021 3FFF
3
0x0020 4000 – 0x0020 4FFF
4
0x0021 4000 – 0x0021 4FFF
4
0x0020 5000 – 0x0020 5FFF
5
0x0021 5000 – 0x0021 5FFF
5
0x0020 6000 – 0x0020 6FFF
6
0x0021 6000 – 0x0021 6FFF
6
0x0020 7000 – 0x0020 7FFF
7
0x0021 7000 – 0x0021 7FFF
7
0x0020 8000 – 0x0020 8FFF
8
0x0021 8000 – 0x0021 8FFF
8
0x0020 9000 – 0x0020 9FFF
9
0x0021 9000 – 0x0021 9FFF
9
0x0020 A000 – 0x0020 AFFF
10
0x0021 A000 – 0x0021 AFFF
10
0x0020 B000 – 0x0020 BFFF
11
0x0021 B000 – 0x0021 BFFF
11
MC9328MX1 Reference Manual, Rev. 6.1
7-8
Freescale Semiconductor
Programming Model
Table 7-6. Peripheral Address MODULE_EN Numbers (continued)
AIPI 1
AIPI 2
Address
MODULE_EN
Address
MODULE_EN
0x0020 C000 – 0x0020 CFFF
12
0x0021 C000 – 0x0021 CFFF
12
0x0020 D000 – 0x0020 DFFF
13
0x0021 D000 – 0x0021 DFFF
13
0x0020 E000 – 0x0020 EFFF
14
0x0021 E000 – 0x0021 EFFF
14
0x0020 F000 – 0x0020 FFFF
15
0x0021 F000 – 0x0021 FFFF
15
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
7-9
Programming Model
7.2.1 Peripheral Size Registers[1:0]
These registers control the size of the IP bus peripheral in each IP bus peripheral location. Peripheral locations that
are not occupied must have their corresponding bits in the PSRs (Peripheral Size Registers) programmed to 1 in
each register.
The least significant bit in the PSRs is a read only bit as it governs the AIPI registers themselves. They are set and
cleared appropriately to indicate the registers are 32 bits. Bits 31 through 16 in both registers are preset to 1 and the
fields are reserved and can only be read.
7.2.1.1 AIPI1 Peripheral Size Register 0 and AIPI2 Peripheral Size Register 0
PSR0_1
PSR0_2
BIT
Addr
0x00200000
0x00210000
AIPI1 Peripheral Size Register 0
AIPI2 Peripheral Size Register 0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PSR0_1
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PSR0_2
RESET
1
1
1
1
1
1
1
1
1
BIT
15
7
6
5
4
3
2
1
0
TYPE
0xFFFF
1
1
1
1
1
1
1
0xFFFF
14
13
12
11
10
9
8
MOD_EN_L
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
PSR0_1
RESET
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
PSR0_2
RESET
1
0
0
0
1
0
0
0
0
0xF800
1
0
0
0
1
0
0
0xC410
Table 7-7. AIPI1 Peripheral Size Register 0 and AIPI2 Peripheral Size Register 0 Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 1.
MOD_EN_L
Bits 15–1
Module_En (lower)—Each bit represents the lower bit of the
2-bit field (PSR1 + PSR0) that represents the Module_En
number.
Reserved
Bit 0
Reserved—This bit is reserved and should read 0.
Settings
See Table 7-9 for bit settings
MC9328MX1 Reference Manual, Rev. 6.1
7-10
Freescale Semiconductor
Programming Model
7.2.1.2 AIPI1 Peripheral Size Register 1 and AIPI2 Peripheral Size Register 1
PSR1_1
PSR1_2
BIT
Addr
0x00200004
0x00210004
AIPI1 Peripheral Size Register 1
AIPI2 Peripheral Size Register 1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PSR_1
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PSR_2
RESET
1
1
1
1
1
1
1
1
1
BIT
15
7
6
5
4
3
2
1
0
TYPE
0xFFFF
1
1
1
1
1
1
1
0xFFFF
14
13
12
11
10
9
8
MOD_EN_U
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
PSR_1
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PSR_2
RESET
1
1
1
1
0
1
1
1
1
0xFFFF
1
1
1
1
0
1
1
0xFBEF
Table 7-8. AIPI1 Peripheral Size Register 1 and AIPI2 Peripheral Size Register 1 Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 1.
MOD_EN_U
Bits 15–1
Module_En (upper)—Each bit represents the upper bit of the 2-bit
field (PSR1 + PSR0) that represents the Module_En number.
Reserved
Bit 0
Reserved—This bit is reserved and should read 0.
Settings
See Table 7-9 for bit settings
The PSRs work together to indicate the size of the IP bus peripheral occupying the corresponding ips_module_en
location, or to indicate there is no IP bus peripheral occupying the corresponding ips_module_en location. A good
example of how the PSRs work is the AIPI registers themselves. When haddr[16:12] is decoded to select the AIPI
registers, {PSR1[bit0], PSR0[bit0]} returns a value of 10, indicating that the AIPI registers are word width
registers. Table 7-9 shows how to program the PSR registers based on the size or availability of an IP bus
peripheral.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
7-11
Programming Model
Table 7-9. PSR Data Bus Size Encoding
PSR[1:0] Bits
IP Bus Peripheral Size [x]
(module_en [x])
PSR1[x]
PSR0[x]
0
0
8-bit
0
1
16-bit
1
0
32-bit
1
1
Unoccupied
7.2.2 Peripheral Access Registers
These registers are used to tell the AIPI whether or not the IP bus peripheral corresponding to the bit location in the
register may be accessed in user mode. If the peripheral may be accessed in supervisor mode only and a user mode
access is attempted an abort will be generated and no IP bus activity occurs. If the peripheral can be accessed in
user mode, then the IPS_SUPERVISOR_ACCESS bit reflects whether the attempted access is in supervisor or user
mode and the peripheral itself can decide whether to accept a user access (if one is attempted) or issue an error
response.
The least significant bit in the PAR is a read only bit as it governs the AIPI registers themselves. It is set to indicate
supervisor access only. Bits 31 through 16 in both registers are preset to 1 and the fields are reserved and can only
be read.
PAR_1
PAR_2
BIT
Addr
0x00200008
0x00210008
AIPI1 Peripheral Access Register
AIPI2 Peripheral Access Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PAR_1
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PAR_2
RESET
1
1
1
1
1
1
1
1
1
BIT
15
7
6
5
4
3
2
1
0
TYPE
0xFFFF
1
1
1
1
1
1
1
0xFFFF
14
13
12
11
10
9
8
ACCESS
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
PAR_1
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PAR_2
RESET
1
1
1
1
1
1
1
1
1
0xFFFF
1
1
1
1
1
1
1
0xFFFF
MC9328MX1 Reference Manual, Rev. 6.1
7-12
Freescale Semiconductor
Programming Model
Table 7-10. Peripheral Access Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 1.
ACCESS
Bits 15–1
Access Control—Each bit controls the access mode of
the corresponding peripheral.
Reserved
Bit 0
Reserved—This bit is reserved and should read 1.
0 = Assigned peripheral determines access
mode.
1 = the corresponding peripheral is a supervisor
access only peripheral.
7.2.3 Peripheral Control Register
These registers are to tell the AIPI whether or not the IP bus peripheral corresponding to the bit location in the
register can be accessed in their natural size only. When set to 1, only byte access is allowed on an 8-bit peripheral,
only halfword access is allowed on a 16-bit peripheral, and only word access is allowed on a 32-bit peripheral.
When set to 1, any access other than natural size that is attempted on the peripheral results in an error response and
no IP bus activity occurs.
The least significant bit in the PCR is a read-only bit and the AIPI registers are not governed by this bit. Bits 31
through 16 in both registers are preset to 0 and the fields are reserved and can only be read.
PCR_1
PCR_2
BIT
Addr
0x0020000C
0x0021000C
AIPI1 Peripheral Control Register
AIPI2 Peripheral Control Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PCR_1
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PCR_2
RESET
0
0
0
0
0
0
0
0
0
BIT
15
7
6
5
4
3
2
1
0
TYPE
0x0000
0
0
0
0
0
0
0
0x0000
14
13
12
11
10
9
8
ACCESS_MODE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
PCR_1
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PCR_2
RESET
0
0
0
0
0
0
0
0
0
0x0000
0
0
0
0
0
0
0
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
7-13
Programming Model
Table 7-11. Peripheral Control Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read
zero.
ACCESS_MODE
Bits 15–1
Module Access Mode—Each bit controls the method
of access used by the corresponding peripheral
assigned to the Module_en.
Reserved
Bit 0
Reserved—This bit is reserved and should read 1.
0 = sub-word and word access is allowed on
the peripheral
1 = corresponding peripheral can only be
accessed in the natural size. i.e. byte
accesses on 8-bit peripherals, half-word
accesses on 16-bit peripherals and word
accesses on 32-bit peripherals.
7.2.4 Time-Out Status Register
These registers contain status of the AIPI module prior to the occurrence of the time-out event. The Time-Out
registers are read-only and status is updated due to time-out operation and module_en must be active. The register
is clear during initial reset.
TSR_1
TSR_2
BIT
Addr
0x00200010
0x00210010
AIPI1 Time-Out Status Register
AIPI2 Time-Out Status Register
31
30
29
28
27
26
25
24
23
22
21
TO
RW
TYPE
rw
r
r
r
r
r
r
r
r
r
r
TSR_1
RESET
0
0
0
0
0
0
0
0
0
0
TSR_2
RESET
0
0
BIT
15
20
19
18
17
16
BE4
BE3
BE2
BE1
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
ADDR
0x0000
0
0
0
0
0
0
0
0x0000
14
13
12
11
10
9
8
MODULE_EN
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
TSR_1
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TSR_2
RESET
0
0
0
0
0
0
0
0
0
0x0000
0
0
0
0
0
0
0
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
7-14
Freescale Semiconductor
Programming Example
Table 7-12. Time-Out Status Register Description
Name
Description
Settings
TO
Bit 31
Time-Out—This bit when set to 1 indicates a time-out event and may be
cleared by the user.
0 = No time-out event
1 = time-out event
RW
Bit 30
This bit contains the ips_rwb status prior to time-out event.
–
ADDR
Bits 29–20
Address—These bits contains the ips_addr[11:2] status prior to time-out
event.
–
BE4
Bit 19
This bit contains the ips_byte_31_24 status prior to time-out event.
–
BE3
Bit 18
This bit contains the ips_byte_23_16 status prior to time-out event.
–
BE2
Bit 17
This bit contains the ips_byte_15_8 status prior to time-out event.
–
BE1
Bit 16
This bit contains the ips_byte_7_0 status prior to time-out event.
–
MODULE_EN
Bits 15–1
Module Enable Status—These bits contains the module_en[15:1] status
prior to time-out event. Refer to Table 7-6 to determine which peripheral
is assigned to which module_en number.
Reserved
Bit 0
Reserved—This bit is reserved and should read 0.
0= Corresponding module has
not timed out
1 = Corresponding module has
timed out
7.3 Programming Example
This section covers programming examples written in assembly code to illustrate the data access through the AIPI
module.
7.3.1 Data Access to 8-Bit Peripherals
The followings codes are executed with the ARM920T core set to big and little endian modes:
LDR
LDR
LDR
STRB
STRB
STRH
STR
LDRB
LDRB
LDRH
LDR
r0,
r1,
r2,
r0,
r1,
r0,
r1,
r3,
r4,
r5,
r6,
=0x11223344
=0x55667788
=8BIT_PERIPHERAL_ADDRESS
[r2, #0x0]
[r2, #0x1]
[r2, #0x2]
[r2, #0x4]
[r2, #0x0]
[r2, #0x1]
[r2, #0x2]
[r2, #0x4]
The Table 7-13 on page 7-16 illustrates the difference in the 8-bit peripheral register content.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
7-15
Programming Example
Table 7-13. Core and 8-Bit Peripheral Register Content After Code Execution
Address
Peripheral Registers
0
44
–
1
88
–
2
44
–
3
33
–
4
88
–
5
77
–
6
66
–
7
55
–
Address
Core Registers
r3
00
00
00
44
r4
00
00
00
88
r5
00
00
33
44
r6
55
66
77
88
7.3.2 Data Access to 16-Bit Peripherals
The followings codes are executed with the ARM core set to big and little endian modes.
LDR
LDR
LDR
STRB
STRB
STRH
STR
LDRB
LDRB
LDRH
LDR
r0,
r1,
r2,
r0,
r1,
r0,
r1,
r3,
r4,
r5,
r6,
=0x11223344
=0x55667788
=16BIT_PERIPHERAL_ADDRESS
[r2, #0x0]
[r2, #0x1]
[r2, #0x2]
[r2, #0x4]
[r2, #0x0]
[r2, #0x1]
[r2, #0x2]
[r2, #0x4]
The Table 7-14 and Table 7-15 illustrate the difference in the 16-bit peripheral register content.
Table 7-14. Core and 16-Bit Peripheral Register Content (Little Endian)
Address
Peripheral Registers
0
88
44
–
2
33
44
–
4
77
88
–
MC9328MX1 Reference Manual, Rev. 6.1
7-16
Freescale Semiconductor
Programming Example
Table 7-14. Core and 16-Bit Peripheral Register Content (Little Endian) (continued)
Address
6
Peripheral Registers
55
Address
66
–
Core Registers
r3
00
00
00
44
r4
00
00
00
88
r5
00
00
33
44
r6
55
66
77
88
Table 7-15. Core and 16-Bit Peripheral Register Content (Big Endian)
Address
Peripheral Registers
0
44
88
–
2
33
44
–
4
55
66
–
6
77
88
–
Address
Core Registers
r3
00
00
00
44
r4
00
00
00
88
r5
00
00
33
44
r6
55
66
77
88
7.3.3 Data Access to 32-Bit Peripherals
The followings codes are executed with the ARM core set to big and little endian modes.
LDR
LDR
LDR
STRB
STRB
STRH
STR
LDRB
LDRB
LDRH
LDR
r0,
r1,
r2,
r0,
r1,
r0,
r1,
r3,
r4,
r5,
r6,
=0x11223344
=0x55667788
=32BIT_PERIPHERAL_ADDRESS
[r2, #0x0]
[r2, #0x1]
[r2, #0x2]
[r2, #0x4]
[r2, #0x0]
[r2, #0x1]
[r2, #0x2]
[r2, #0x4]
The Table 7-16 and Table 7-17 on page 7-18 illustrate the difference in the 32-bit peripheral register content.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
7-17
Programming Example
Table 7-16. Core and 32-bit Peripheral Register Content (Little Endian)
Address
Peripheral Registers
0
33
44
88
44
4
55
66
77
88
Address
Core Registers
r3
00
00
00
44
r4
00
00
00
88
r5
00
00
33
44
r6
55
66
77
88
Table 7-17. Core and 32-bit Peripheral Register Content (Big Endian)
Address
Peripheral Registers
0
44
88
33
44
4
55
66
77
88
Address
Core Registers
r3
00
00
00
44
r4
00
00
00
88
r5
00
00
33
44
r6
55
66
77
88
7.3.4 Special Consideration for Non-Natural Size Access
A programmer must exercise care when accessing peripherals using access other than their natural size. An
example of such access includes byte access to a 32-bits peripheral and word access to 8-bit peripheral. The
examples in the previous section clearly illustrate the difference in byte accessing a 32-bits peripheral in both big
and little endian modes. An instruction such as:
STRB
r1,
[r2, #0x1]
is accessing using byte lane[15:8] in little endian, while byte lane[23:16] is accessed using big endian mode.
Therefore, if a programmer is using byte access to set up control information in 32-bit register, extreme care must
be taken to ensure the desired byte is written during the desired endian mode.
MC9328MX1 Reference Manual, Rev. 6.1
7-18
Freescale Semiconductor
Chapter 8
System Control
This chapter describes the system control module of the MC9328MX1 microprocessor. The system control module
enables system software to control, customize, or read the status of the following functions:
•
Multiplexing of SSI and SIM signals
•
Multiplexing of the SDRAM/SyncFlash chip select signal
•
Chip ID
•
System boot mode selection
8.1 Programming Model
The system control module includes four user-accessible 32-bit registers. Table 8-1 summarizes these registers and
their addresses.
Table 8-1. System Control Module Register Memory Map
Description
Name
Address
Silicon ID Register
SIDR
0x0021B804
Function Multiplexing Control Register
FMCR
0x0021B808
Global Peripheral Control Register
GPCR
0x0021B80C
Global Clock Control Register
GCCR
0x0021B810
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
8-1
Programming Model
8.1.1 Silicon ID Register
This 32-bit read-only register shows the chip identification. The bit assignments for the register are shown in the
following register display. The settings for the bits in the register are listed in Table 8-2.
SIDR
BIT
Addr
0x0021B804
Silicon ID Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SID
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
7
6
5
4
3
2
1
0
RESET
0x0005
BIT
15
14
13
12
11
10
9
8
SID
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
1
0
0
1
0
0
0
0
0
0
0
1
1
1
0
1
RESET
0x901D
Table 8-2. Silicon ID Register Description
Name
SID
Bits 31–0
Description
Silicon ID—Contains the chip identification number of the MC9328MX1.
Settings
Silicon ID:
Mask 1L = 0x04D4 C01D
Mask 2L = 0x00D4 C01D
MC9328MX1 Reference Manual, Rev. 6.1
8-2
Freescale Semiconductor
Programming Model
8.1.2 Function Multiplexing Control Register
The Function Multiplexing Control Register (FMCR) controls the multiplexing of the signal lines shared by the
SSI and SIM modules. It also controls the SDRAM/SyncFlash chip select lines and masking of the external bus
request. See Table 8-3 for detailed description of bit settings.
FMCR
Addr
0x0021B808
Function Multiplexing Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
BIT
15
14
13
12
11
10
9
8
SPI2_RXD_SEL
SSI_RXFS_SEL
SSI_RXCLK_SEL
SSI_RXDAT_SEL
SSI_TXFS_SEL
SSI_TXCLK_SEL
EXT_BR_EN
SDCS1_SEL
SDCS0_SEL
0x0000
TYPE
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
7
RESET
0x0003
Table 8-3. Function Multiplexing Control Register Description
Name
Description
Settings
Reserved
Bits 31–9
Reserved—These bits are reserved and should read 0.
SPI2_RXD_SEL
Bit 8
SPI2 Receive Data Input Select—Selects the SPI2
receive data input source.
0 = Input from SPI2_RXD-0 pin (AOUT of
GPIO port A[1])
1 = Input from SPI2_RXD_1 pin (AOUT of
Port D[9])
SSI_RXFS_SEL
Bit 7
SSI Receive Frame Sync Input Select—Selects the
receive frame sync input source.
0 = Input from Port C[3] SSI_RXFS pin
1 = Input from Port B[14] SIM_SVEN pin
SSI_RXCLK_SEL
Bit 6
SSI Receive Clock Select—Selects the receive clock
input source.
0 = Input from Port C[4] SSI_RXCLK pin
1 = Input from Port B[15] SIM_PD pin
SSI_RXDAT_SEL
Bit 5
SSI Receive Data Select—Selects the receive data input
source.
0 = Input from Port C[5] SSI_RXDAT pin
1 = Input from Port B[16] SIM_TX pin
SSI_TXFS_SEL
Bit 4
SSI Transmit Frame Sync Select—Selects the transmit
frame sync input source.
0 = Input from Port C[7] SSI_TXFS pin
1 = Input from Port B[18] SIM_RST pin
SSI_TXCLK_SEL
Bit 3
SSI Transmit Clock Select—Selects the transmit clock
input source.
0 = Input from Port C[8] SSI_TXCLK pin
1 = Input from Port B[19] SIM_CLK pin
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
8-3
Programming Model
Table 8-3. Function Multiplexing Control Register Description (continued)
Name
Description
EXT_BR_EN
Bit 2
Settings
External Bus Request Control—Chooses whether the
external bus request function is masked or enabled.
0 = External bus request masked
1 = External bus request enabled
Note: The external bus request is a test signal and the
EXT_BR_EN bit must be clear during normal operation.
SDCS1_SEL
Bit 1
SDRAM/SyncFlash Chip Select—Selects the function of
the CS3/CSD1 pin.
0 = CS3 selected
1 = CSD1 selected
SDCS0_SEL
Bit 0
SDRAM/SyncFlash Chip Select—Selects the function of
the CS2/CSD0 pin.
0 = CS2 selected
1 = CSD0 selected
8.1.3 Global Peripheral Control Register
The Global Peripheral Control Register (GPCR) controls the driving force parameters of the bus and several other
functions in the MC9328MX1. Descriptions of the register settings appear in Table 8-6.
GPCR
Addr
0x0021B80C
Global Peripheral Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
RESET
r
r
rw
0
0
0
0
10
9
CSI_PROT_EN
rw
11
rw
rw
rw
rw
rw
rw
rw
rw
r
r
rw
rw
0
0
1
1
1
1
1
1
1
0
1
1
BTAEN
DS_DATA
12
TEST_EN-REG
13
DS_ADDR
TYPE
14
DS_CNTL
15
DS_SLOW
BIT
MMA_PROT_EN
0x0000
RESET
0x03FB
Table 8-4. Global Peripheral Control Register Description
Name
Reserved
Bits 31–16
Description
Settings
Reserved—These bits are reserved and should read 0.
MC9328MX1 Reference Manual, Rev. 6.1
8-4
Freescale Semiconductor
Programming Model
Table 8-4. Global Peripheral Control Register Description (continued)
Name
Description
Settings
TEST_EN_REG
Bit 15
Test Enable Register—Active high of this bit switches the
internal test signals from MEMC to GPIO for debug purposes.
0 = Normal
1 = Switches MEMC inner test signals
to GPIO for debug purposes.
Reserved
Bits 14–13
Reserved—These bits are reserved and should read 0.
BTAEN
Bit 12
BTA Clock Input Control—Controls the clock input signals to
the BTA module. When the bit is clear, clock inputs to the BTA
are stopped for power saving. When this bit is set, clock inputs
to the BTA are enabled.
0 = Clock inputs to BTA disabled
1 = Clock inputs to BTA enabled
DS_SLOW
Bits 11–10
Driving Strength Slow I/O—Controls the driving strength of
all slow I/O signals.
00 = 26 MHz/15 pF
01 = 26 MHz/30 pF
10 = 26 MHz/45 pF
11 = 26 MHz/greater than 45 pF
DS_CNTL
Bits 9–8
Driving Strength Bus Control Signal—Controls the driving
strength of bus control signals.
00 = 50 MHz/15 pF
01 = 50 MHz/30 pF
10 = 100 MHz/15 pF
11 = 100 MHz/30 pF
DS_ADDR
Bits 7–6
Driving Strength Address Bus—Controls the driving
strength of the address bus.
00 = 50 MHz/15 pF
01 = 50 MHz/30 pF
10 = 100 MHz/15 pF
11 = 100 MHz/30 pF
DS_DATA
Bits 5–4
Driving Strength Data Bus—Controls the driving strength of
the data bus.
00 = 50 MHz/15 pF
01 = 50 MHz/30 pF
10 = 100 MHz/15 pF
11 = 100 MHz/30 pF
Reserved
Bit 3
Reserved—This bit must be set to 1 at all times for normal operation.
Reserved
Bit 2
Reserved—This bit is reserved and should read 0.
MMA_PROT_EN
Bit 1
MMA Privileged Mode Access—Selects whether the MMA
can only be accessed in privileged mode or if it can be
accessed in all modes.
0 = All access modes available
1 = Privileged mode access only
CSI_PROT_EN
Bit 0
CMOS Sensor Interface Privileged Mode Access—Selects
whether the CSI can only be accessed in privileged mode or if
it can be accessed in all modes.
0 = All access modes available
1 = Privileged mode access only
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
8-5
Programming Model
8.1.4 Global Clock Control Register
The Global Clock Control Register (GCCR) provides additional power saving capabilities by controlling the clocks
in the following MC9328MX1 modules: DMA, CSI, MMA and USB. It also controls the clock source for
Bootstrap mode.
GCCR
Addr
0x0021B810
Global Clock Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
3
2
1
0
RESET
BIT
15
14
13
12
11
10
9
8
7
6
UART3_CLK_EN
SSI2_CLK_EN
BROM_CLK_EN
DMA_CLK_EN
CSI_CLK_EN
MMA_CLK_EN
USBD_CLK_EN
0x0000
5
TYPE
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
RESET
0x002F
Table 8-5. Global Clock Control Register Description
Name
Description
Settings
Reserved
Bits 31–7
Reserved—These bits are reserved and should read 0.
UART3_CLK_E
N
Bit 6
UART 3 Clock Enable— Enables/Disables clock input to the
UART 3 module.
0 = UART 3 clock input is disabled.
1 = UART 3 clock input is enabled
(default).
SSI2_CLK_EN
Bit 5
SSI 2 Clock Enable—Enables/Disables clock input to the
SSI2 module.
0 = SSI 2 clock input is disabled.
1 = SSI 2 clock input is enabled
(default).
BROM_CLK_EN
Bit 4
BROM Clock Enable—Only available in Bootstrap mode.
This bit enables/disables the operational system boot mode of
the MC9328MX1 upon system reset. The boot mode is
determined by the settings of these pins.
0 = Clock gating is controlled by setting
of BOOT[3:0] pins.
1 = Overrides the setting of the
BOOT[3:0] pins and forces the
HCLK to be used as clock.
DMA_CLK_EN
Bit 3
DMA Clock Enable—Enables/Disables clock input to the
DMA module.
0 = DMA clock input is disabled.
1 = DMA clock input is enabled
(default).
MC9328MX1 Reference Manual, Rev. 6.1
8-6
Freescale Semiconductor
System Boot Mode Selection
Table 8-5. Global Clock Control Register Description (continued)
Name
Description
Settings
CSI_CLK_EN
Bit 2
CMOS Sensor Interface Clock Enable— Enables/Disables
clock input to the CSI module.
0 = CSI clock input is disabled.
1 = CSI clock input is enabled (default).
MMA_CLK_EN
Bit 1
Multimedia Accelerator Clock Enable— Enables/Disables
clock input to the MMA module.
0 = CSI clock input is disabled.
1 = CSI clock input is enabled (default).
USBD_CLK_EN
Bit 0
USBD Clock Enable—Enables/Disables clock input to the
USB module.
0 = USB clock input is disabled.
1 = USB clock input is enabled (default).
8.2 System Boot Mode Selection
The operational system boot mode of the MC9328MX1 upon system reset is determined by the configuration of
the four external input pins BOOT[3:0]. The settings of these pins control the following functions:
•
CS0 boot function of the EIM module
•
Control of the SyncFlash chip select (CSD1) boot function of the SDRAM controller
The settings of the system control module for the system boot mode selection are displayed in Table 8-6.
The MC9328MX1 always begins fetching instructions from address 0x00000000 after reset. The BOOT[3:0] pins
control the memory region that is mapped to address 0x0. The boot modes are defined in Table 8-6. The
BOOT[3:0] pins also control the initial configuration (for example bus width) for the external memory regions.
When an external chip select is enabled by the BOOT[3:0] pins, the first 1 Mbyte range (0x0000000–0x000FFFFF)
of the chip select's memory space is also mapped to address 0x0.
For example, by setting BOOT[3:0] to 0110, the MC9328MX1 will boot from the CS0 memory region using a
32-bit data bus width. The first 1 Mbyte of the CS0 memory space (0x10000000–0x100FFFFF) will be mapped to
addresses 0x00000000–0x000FFFFF.
NOTE:
The BOOT pins must not change once the MC9328MX1 is out of reset. To achieve
logic 0, a BOOT input must be tied to GND through a 1 kohm resistor. Otherwise,
excessive current may occur at power up. BOOT[3] must always be terminated with a
1 kohm resistor to GND.
NOTE:
If Bootstrap ROM is not selected for the boot mode, the internal ROM is not accessible.
Table 8-6. System Boot Mode Selection
Inputs
BOOT[3:0]
Output Signals
Active Device
0000
Bootstrap ROM
0001
16-bit SyncFlash D[15:0]
0010
32-bit SyncFlash
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
8-7
System Boot Mode Selection
Table 8-6. System Boot Mode Selection (continued)
Inputs
BOOT[3:0]
Output Signals
Active Device
0011
8-bit CS0 at D[7:0]
0100
16-bit CS0 at D[31:16]
0101
16-bit CS0 at D[15:0]
0110
32-bit CS0 at D[31:0]
0111
Reserved
MC9328MX1 Reference Manual, Rev. 6.1
8-8
Freescale Semiconductor
Chapter 9
Bootstrap Mode Operation
Bootstrap mode is designed to allow you to initialize a target system and download programs or data to the target
system’s RAM using the UART 1 or UART 2 controller. After a program is downloaded, it can be executed, which
gives you a simple debugging environment for failure analysis and a channel to update programs stored in flash
memory. Bootstrap mode has the following capabilities:
•
Allows you to initialize your system and download programs and data to system memory using UART 1 or
UART 2.
•
Accepts execution commands to run programs stored in system memory
•
Supports memory and register read and write operations of selectable data size (byte, half-word, or word)
•
Provides an 8-word instruction buffer for ARM920T vector table storage, instruction storage and execution
9.1 Operation
In bootstrap mode, only MC9328MX1’s UART 1 and UART 2 controllers are initialized. They are configured to
auto-baud detection mode, ignore RTS, keep CTS always active, no parity, 8-bit character length, and one stop bit.
Then they are ready to accept bootstrap data download. UART 3 does not support bootstrap loading. The first
character received must be a or A. This character determines the baud rate to be used and which UART port is
being used for bootstrapping. The first character is not part of a program or data being downloaded. To download
the data or program, the code must be converted to a bootstrap format file, which is a text file that contains
bootstrap records. A DOS-executable program, STOB.EXE, can be downloaded from the i.MX Web site to convert
an S-record file to a bootstrap format file.
The MC9328MX1’s internal registers must be initialized as the target system before a program can be downloaded
to system memory. Because these internal registers can be treated as a type of memory, each of them can be
initialized by issuing a bootstrap record.
The bootstrap design provides an 8-word instruction buffer to which ARM920T core instructions can be
downloaded. The buffers are word-access only. This feature enables the ARM920T core instructions to be run even
if the memory systems are disabled or in a core stand-alone system. The instruction buffer starts at 0x00000004.
Regardless of the operation (initializing internal registers, downloading a program to system RAM, or issuing a
core instruction), bootstrap mode will only accept bootstrap record transfers that are made with the UART. The
record type determines what action will occur.
The instruction buffer allows users to download the vector table onto the buffer without the use of external ROM or
Flash, the feature provides a fast and easy environment to users when using IRQ during program debug.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
9-1
Operation
9.1.1 Entering Bootstrap Mode
Bootstrap mode is the debug mode of the MC9328MX1. To enter bootstrap mode, the BOOT pins must be
properly configured during system reset. After reset, the bootstrap ROM is selected for reset vector fetch cycles.
Please refer to Section 8.2, “System Boot Mode Selection,” on page 8-7 for details about configuring bootstrap
mode.
9.1.2 Bootstrap Record Format
Only bootstrap records (b-records) are accepted for data transfers in bootstrap mode. The b-record format is shown
in Table 9-1, and Table 9-2 further defines the COUNT/MODE byte. All b-records are in uppercase. Each byte is
represented by two ASCII characters during transfer (for example, a byte of value 0x12 will be represented by the
characters 12).
Table 9-1. Bootstrap Record Format
4 Bytes
1 Byte
N (Count) Bytes
Address
Count/mode
Data
Table 9-2. Definition of COUNT/MODE Byte
Bit(s)
Definition
7–6
Data size
5
Read/write flag
4–0
Data count in number of bytes
Settings
00 = Byte
01 = Half-word
10 = Reserved
11 = Word
0 = Write
1 = Read
Value from 0 to 31
NOTE:
1. A half-word is defined as 16 bits, while a word is defined as 32 bits.
2. The address specified must fall on a data size boundary: for word access, the last 2 bits of the
address must be 0, while for half-word access, the last bit of the address must be 0. The data count
in the COUNT/MODE byte must be a multiple of the data size: for word access, the data count must
be a multiple of four, while for half-word access, the data count must be in multiple of two. If either
the address or the data count is not on an appropriate data size boundary, the bootloader program
will return a * character (asterisk) to indicate that an error has occurred, and the bootloader will then
start waiting for a new b-record.
3. During a read operation, a / character (forward slash) is returned after the last data has been returned.
4. A data count of zero (disregard the value of data size and the status of the mode flag) has a special
meaning: execute from the address specified. In this case, no data will follow the COUNT/MODE
byte.
Comments can be added to files of b-records. As described above, the shortest b-record consists of 10 ASCII
characters (when the data count is 0) of 0 to 9 or A to F (hexadecimal digits). Comments included must not contain
patterns to prevent the comments from being considered a b-record.
MC9328MX1 Reference Manual, Rev. 6.1
9-2
Freescale Semiconductor
B-Record Example
9.1.3 Registers Used in Bootloader Program
The bootloader program uses general-purpose registers r5 to r12 as well as r13 as the return register and r14 as the
link register. All the other registers can be used by target programs.
9.1.4 Setting Up the RS-232 Terminal
To set up communication between your target system and the PC, set the communication specifications to the baud
rate desired, no parity, 8-bit character length, and 1 stop bit. You may pause after each line (b-record) is transferred
to make sure each transferred ASCII character is echoed.
After setting up the hardware, powering up the system, and entering bootstrap mode, send an a or A character to the
target system to initiate the link. Once the bootloader receives this character, it adjusts the baud rate. If the link is
successful, the bootloader will return the special character : (colon) as an acknowledgment.
9.1.5 Changing the Speed of Communication
You can change the communication baud rate after communication is set up in the RS-232 terminal. Simply issue a
b-record to re-initialize the baud control register of the UART controller. After the last character of this b-record is
sent, the echo of this last character will be transmitted at the new speed. The maximum speed recommended for
Bootstrap is 57600 baud.
9.2 B-Record Example
Before you can download a program to system memory, the target system may need to be initialized using the
internal registers. An init file can be built using a text editor. Code Example 9-1 initializes the SRAM memory
location 0x00310000 to 0x12345678 in word access mode, the location 0x00310006 to 0x7788 in half-word access
mode, and the location 0x00310009 to 0x55 in byte access mode.
Code Example 9-1. init.b Example
// init.b -- Initialization Example
00310000C412345678
initialize 0x00310000 to 0x12345678
00310006427788
initialize 0x00310006 to 0x7788
003100090155
initialize 0x00310009 to 0x55
With b-records similar to those stated above, a target program can be downloaded to memory and executed from
the address chosen with the following b-record:
1122334400
execute from 11223344
The target program may exit and return to the bootloader program by jumping to address 0x00000100, where the
bootloader program starts.
9.3 Instruction Buffer Usage
A 8-word instruction buffer is provided for ARM920T core vector table storage, instruction and data storage. The
buffer starts at 0x00000004. Up to eight instructions can be loaded to the instruction buffer for execution.Usually,
the last instruction is an unconditional jump instruction (jmp) that jumps to the start of the bootloader program
(0x00000100).
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
9-3
Instruction Buffer Usage
Code Example 9-2 fills memory locations starting from 0x00310000 to 0x003100FF (the length of 0x100) with
0x12345678.
loop:
ldr
ldr
ldr
ldr
r1,=0x00310000
r2,=0x100
r3,=0x12345678
r4,=0x00000100
str
subs
bne
mov
r3,[r1, r2]
r2,r2, #4
loop
pc, r4
Code Example 9-2. Instruction Buffer Sample
// starting address is 0x003100FF
// length is 0x100
// data to fill is 0x12345678
// bootloader program
// store data
// decrement address
// loop back till r2 down to 0x0
// return to bootloader program
Because the instruction buffer is of limited size, the programmer cannot do everything at the same time. The
program can be broken into five parts, as shown in Table 9-3.
Table 9-3. Program Breakdown
Part
Code
1
ldr
mov
r4,=0x00000100
pc, r4
// bootloader address 0x00000100
// return to bootloader program
2
ldr
mov
r1,=0x00310000
pc, r4
// starting address is 0x00310000
// return to bootloader program
3
ldr
mov
r2,=0x00000100
pc, r4
// length is 0x100
// return to bootloader program
4
ldr
mov
r3,=0x12345678
pc, r4
// data to fill is 0x12345678
// return to bootloader program
str
subs
bne
mov
r3,[r1, r2]
r2,r2, #4
loop
pc, r4
//
//
//
//
5
loop
store data
decrement address
loop back till r2 down to 0x0
return to bootloader program
Breaking down the register initialization into three parts is not mandatory, however it produces similar b-records
and therefore is easier to manage.
The resulting b-records appear in Table 9-4.
Table 9-4. Resulting B-Records
B-Record Number
B-Record
1
00000004 08E3A04F40E1A0F004
0000000400
2
00000004 08E3A019C4E1A0F004
0000000400
3
00000004 08E3A02F40E1A0F004
0000000400
4
00000004 0CE59F3000E1A0F00412345678
0000000400
MC9328MX1 Reference Manual, Rev. 6.1
9-4
Freescale Semiconductor
Simple Read/Write Examples
Table 9-4. Resulting B-Records (continued)
B-Record Number
B-Record
00000004 0FE7813002E25220041AFFFFFCE1A0F004
0000000400
5
Note that all b-records start at the same address, 0x00000004, which is the starting address of the instruction buffer.
B-records 1, 2, and 3 are very similar and can be used as prototype b-records for general-purpose register
initialization.
Therefore, the resulting b-record file will be as follows:
Code Example 9-3. Bootloader B-Record
00000004 08E3A04F40E1A0F004initialize r4 to 0x00000100 (bootloader start)
0000000400
execute and return to bootloader
00000004 08E3A019C4E1A0F004initialize r1 to 0x00310000 (start)
0000000400
execute and return to bootloader
00000004 08E3A02F40E1A0F004initialize r2 to 0x100 (length)
0000000400
execute and return to bootloader
00000004 0CE59F3000E1A0F00412345678initialize r3 to 0x12345678 (content)
0000000400
execute and return to bootloader
00000004 0FE7813002E25220041AFFFFFCE1A0F004memory fill
0000000400
execute and return to bootloader
9.4 Simple Read/Write Examples
Table 9-5 provides examples demonstrating how to perform memory and register reads/writes of various data
sizes. Code Example 9-4 shows an example of the code used for Vector Tables
Code Example 9-4.
NOP
IRQ_Addr
FIQ_Addr
NOP
NOP
DCD
DCD
NOP
LDR
LDR
DCD
; 0x00
C_IRQ_Handler
C_FIQ_Handler
PC, IRQ_Addr
PC, FIQ_Addr
0
;
;
;
;
;
;
;
;
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
(programmable
(programmable
(programmable
(programmable
(programmable
(programmable
(programmable
(programmable
buffer)
buffer)
buffer)
buffer)
buffer)
buffer)
buffer)
buffer)
Table 9-5. Read/Write Examples
Example Type
B-Record
Read 3 bytes starting
from location 0x00310000
0031000023
Read 3 half-words
starting from location
0x00310000
Read 3 words starting
from location 0x00310000
Return Value
0031000003XXYYZZ/
(where XX, YY, and ZZ are data in byte)
0031000066
0031000066XXXXYYYYZZZZ/
(6 bytes = 3 half-words)
(where XXXX, YYYY, and ZZZZ are data in half-word)
00310000EC
00310000ECXXXXXXXXYYYYYYYYZZZZZZZZ/
(12 bytes = 3 words)
(where XXXXXXXX, YYYYYYYY, and ZZZZZZZZ are data
in word)
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
9-5
Simple Read/Write Examples
Table 9-5. Read/Write Examples (continued)
Example Type
B-Record
Return Value
Write 3 bytes starting from
location 0x00310000
0031000003112233
0031000003112233/
Write 3 half-words starting
from location 0x00310000
0031000046111122223333
0031000046111122223333/
Write 3 words starting
from location 0x00310000
00310000CC1111111122222222
33333333
(6 bytes = 3 half-words)
00310000CC111111112222222233333333/
(12 bytes = 3 words)
MC9328MX1 Reference Manual, Rev. 6.1
9-6
Freescale Semiconductor
Bootloader Flowchart
9.5 Bootloader Flowchart
Figure 9-1 on page 9-7 illustrates how the bootloader program operates inside the MC9328MX1. The bootloader
starts when the MC9328MX1 enters bootstrap mode.
START
Initialize
UART
Receive a Bootstrap
Record
Data COUNT = 0?
YES
Run Program
Starting
at ADDR
NO
Data COUNT &
Data SIZE
Valid?
NO
ECHO *
YES
ECHO /
NO
Read?
Store Data to
ADDR
YES
Read Data From
ADDR
ECHO Data
Figure 9-1. Bootloader Program Operation
9.6 Special Notes
The following summary items may be helpful when working in bootstrap mode.
•
A b-record is a string of uppercase hex characters with optional comments that follow.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
9-7
Special Notes
•
Comments in a b-record or b-record file must not contain any word or symbol that is longer than nine
characters. However, the following characters can be used in a string of any length (all of these have an
ASCII code value that is less than 0x30):
— space
— ! (exclamation point)
— “ (quotation mark)
— # (number sign)
— $ (dollar sign)
— % (percentage symbol)
— & (ampersand)
— ( (opening parenthesis)
— ) (closing parenthesis)
— * (asterisk)
— + (plus sign)
— - (minus sign)
— . (period)
— / (forward slash)
— , (comma)
•
The bootloader program echoes all characters being received, however only those having an ASCII code
value greater than or equal to 0x30 are kept for b-record assembling. Sending a character that is not a
b-record (ASCII code value less than 0x30) will force the bootloader to start a new b-record.
•
General-purpose registers r7–r14 and supervisor scratch registerss3 are used by the bootloader program.
Writing to these registers may corrupt the bootloader program.
•
Please visit the DragonBall Web site for bootstrap utility programs.
MC9328MX1 Reference Manual, Rev. 6.1
9-8
Freescale Semiconductor
Chapter 10
Interrupt Controller (AITC)
This chapter describes the ARM9 Interrupt Controller (AITC) that is used to control and prioritize up to 64
interrupts in the MC9328MX1. This chapter describes the registers and bit settings plus all other information
necessary to write the software necessary to write interrupt service routines.
10.1 Introduction
The MC9328MX1 interrupt controller (AITC) is a 32-bit peripheral that collects interrupt requests from a
maximum of 64 sources and provides an interface to the ARM920T processor.
AITC_FIQ
64
FIVECTOR
FIPEND
64
64
64
INTIN
64
FIAD
6
FORCE
64
AITC_BLOCK_ARB
Priority
Encoder
NIPEND
INTTYPE
64
Software
Priority
Encoder
NIVECTOR
INTENABLE
6
NIAD
AITC_IRQ
AITC_RDATA_OVR
NM
32
HADDR
Equals
0x00000018
Equals
0x0000001C
Opcode
Generator
32
AITC_RDATA
HREADY
FM
Figure 10-1. AITC Block Diagram
The AITC performs the following functions:
•
Supports a maximum of 64 interrupt sources
•
Supports fast and normal interrupts
•
Selects normal or fast interrupt request for any interrupt source
•
Indicates pending interrupt sources via a register for normal and fast interrupts
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-1
Operation
•
Detects all pending interrupts and distinguishes by priority level
•
Independently enables or disables any interrupt source
•
Provides a mechanism for software to schedule an interrupt
•
Supports a maximum of 16 software controlled priority levels for normal interrupts and priority masking
10.2 Operation
The interrupt controller consists of a set of control registers and associated logic to perform interrupt masking,
priority support, and hardware acceleration of normal interrupts.
The interrupt source registers (INTSRCH and INTFRCL) are a pair of 32-bit status registers with a single interrupt
source associated with each of the 64 bits. An interrupt line or set of interrupt lines is routed from each interrupt
source to the INTSRCH or INTFRCL register. This configuration allows the ARM920T processor of the
MC9328MX1 to monitor a maximum of 64 distinct interrupt sources.
Interrupt requests can be forcibly asserted through the interrupt force registers (INTFRCH and INTFRCL). Each
bit in these registers is logically ORed with the corresponding hardware request line prior to input to the INTSRCH
or INTFRCL registers.
There is a corresponding set of interrupt enable registers (INTENABLEH and INTENABLEL), each 32 bits wide,
that allow individual bit masking of the INTSRCH and INTFRCL registers. There is also a corresponding set of
interrupt type registers (INTTYPEH and INTTYPEL) that selects whether an interrupt source generates a normal
or fast interrupt to the ARM920T processor.
There is a corresponding set of normal interrupt pending registers (NIPNDH and NIPNDL) that indicate pending
normal interrupt requests, and are equivalent to the logical AND of the interrupt source registers (INTSRCH and
INTSRCL), the interrupt enable registers (INTENABLEH and INTENABLEL), and the NOT of the interrupt type
registers (INTTYPEH and INTTYPEL). The NIPNDH and NIPNDL register bits are bit-wise NORed together to
generate the nIRQ signal that is routed to the ARM920T processor. This ARM920T processor input signal is
maskable by the normal interrupt disable bit (I bit) in the program status register (CPSR). The normal interrupt
vector register (NIVECSR) indicates the vector index of highest priority pending normal interrupt.
There is a corresponding set of fast interrupt pending registers (FIPNDH and FIPNDL) that indicate pending fast
interrupt requests, and are equivalent to the logical AND of the interrupt source registers (INTSRCH and
INTSRCL), the interrupt enable registers (INTENABLEH and INTENABLEL), and the interrupt type registers
(INTTYPEH and INTTYPEL). The FIPNDH and FIPNDL register bits are bit-wise NORed together to generate
the nFIQ signal that is routed to the ARM920T processor. This ARM920T processor input signal is maskable by
the fast interrupt disable bit (F bit) in the CPSR. The fast interrupt vector register (FIVECSR) indicates the vector
index of highest priority pending fast interrupt.
All interrupt controller registers are readable and writable in supervisor mode only. Writes attempted to read-only
registers are ignored. These registers must be written with 32-bit stores only.
The INTFRCH and INTFRCL registers are provided for software generation of interrupts. By enabling interrupts
for these bit positions, software can force an interrupt request. This register also provides an alternate method of
interrupt assertion for debugging hardware interrupt service routines.
The interrupt requests are prioritized in the following order:
1. Fast interrupt requests, in order of highest number
2. Normal interrupt requests, in order of highest priority level, then highest source number with the
same priority
MC9328MX1 Reference Manual, Rev. 6.1
10-2
Freescale Semiconductor
AITC Interrupt Controller Signals
The AITC provides 16 software controlled priority levels for normal interrupts and every interrupt can be placed in
any priority level. The AITC also provides a normal interrupt priority level mask (NIMASK) that disables any
interrupt with a priority level less than or equal to the mask. When a level 0 normal interrupt and a level 1 normal
interrupt are asserted at the same time, the level 1 normal interrupt is selected unless NIMASK has disabled level 1
normal interrupts. When two level 1 normal interrupts are asserted at the same time, the level 1 normal interrupt
with the highest source number is selected unless NIMASK has disabled level 1 normal interrupts.
10.3 AITC Interrupt Controller Signals
The active-low INTIN [63:0] input signals indicate that a peripheral device is requesting an interrupt to the
interrupt controller. The interrupt controller recognizes an interrupt is asserted on the rising edge of the clock and
does not latch and hold the interrupt. The peripheral must keep the interrupt request asserted until the software
acknowledges and clears the interrupt request.
The interrupt source assignment of INTIN [63:0] is shown Table 10-1. Interrupt sources in the table that are labeled
‘unused’ may be used by software to force an interrupt request for a specific source using either the INTFRCH or
INTRFRCL registers.
In Table 10-1, some signals are shown with overbars to represent the logic inside the chip. However, all
asserted interrupts result in the associated bit being a 1 in the Interrupt Source Registers
Table 10-1. Interrupt Assignment
Bit #
Name of Interrupt
Bit #
Name of Interrupt
Bit #
Name of Interrupt
Bit #
Name of Interrupt
0
UART3_MINT_PFERR
16 SIM_DATA
32
Unused
48 USBD_INT [1]
1
UART3_MINT_RTS
17 RTC_INT
33
PEN_DATA_INT
49 USBD_INT [2]
2
UART3_MINT_DTR
18 RTC_SAM_INT
34
PWM_INT
50 USBD_INT [3]
3
UART3_MINT_UARTC
19 UART2_MINT_PFERR
35
MMC_IRQ
51 USBD_INT [4]
4
UART3_MINT_TX
20 UART2_MINT_RTS
36
SSI2_TX_INT
52 USBD_INT [5]
5
PEN_UP_INT
21 UART2_MINT_DTR
37
SSI2_RX_INT
53 USBD_INT [6]
6
CSI_INT
22 UART2_MINT_UARTC
38
SSI2_RX_ERR_INT /
SSI2_TX_ERR-INT
54 UART3_MINT_RX
7
MMA_MAC_INT
23 UART2_MINT_TX
39
I2C_INT
55 BTSYS
8
MMA_INT
24 UART2_MINT_RX
40
SPI2_INT
56 BTTIM
9
COMP_INT
25 UART1_MINT_PFERR
41
SPI1_INT
57 BTWUI
10
MSIRQ
26 UART1_MINT_RTS
42
SSI_TX_INT
58 TIMER2_INT
11
GPIO_INT_PORTA
27 UART1_MINT_DTR
43
SSI_TX_ERR_INT
59 TIMER1_INT
12
GPIO_INT_PORTB
28 UART1_MINT_UARTC
44
SSI_RX_INT
60 DMA_ERR
13
GPIO_INT_PORTC
29 UART1_MINT_TX
45
SSI_RX_ERR_INT
61 DMA_INT
14
LCDC_INT
30 UART1_MINT_RX
46
TOUCH_INT
62 GPIO_INT_PORTD
15
SIM_IRQ
31 Unused
47
USBD_INT [0]
63 WDT_INT
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-3
Programming Model
10.4 Programming Model
The AITC module includes 26 user-accessible 32-bit registers. All of these registers are single cycle access
because the AITC sits on the native bus of the ARM920T processor. Table 10-2 summarizes these registers and
their addresses. Table 10-3 provides an overview of the register fields.
Table 10-2. AITC Module Register Memory Map
Description
Name
Address
Interrupt Control Register
INTCNTL
0x00223000
Normal Interrupt Mask Register
NIMASK
0x00223004
Interrupt Enable Number Register
INTENNUM
0x00223008
Interrupt Disable Number Register
INTDISNUM
0x0022300C
Interrupt Enable Register High
INTENABLEH
0x00223010
Interrupt Enable Register Low
INTENABLEL
0x00223014
Interrupt Type Register High
INTTYPEH
0x00223018
Interrupt Type Register Low
INTTYPEL
0x0022301C
Normal Interrupt Priority Level Register 7
NIPRIORITY7
0x00223020
Normal Interrupt Priority Level Register 6
NIPRIORITY6
0x00223024
Normal Interrupt Priority Level Register 5
NIPRIORITY5
0x00223028
Normal Interrupt Priority Level Register 4
NIPRIORITY4
0x0022302C
Normal Interrupt Priority Level Register 3
NIPRIORITY3
0x00223030
Normal Interrupt Priority Level Register 2
NIPRIORITY2
0x00223034
Normal Interrupt Priority Level Register 1
NIPRIORITY1
0x00223038
Normal Interrupt Priority Level Register 0
NIPRIORITY0
0x0022303C
Normal Interrupt Vector and Status Register
NIVECSR
0x00223040
Fast Interrupt Vector and Status Register
FIVECSR
0x00223044
Interrupt Source Register High
INTSRCH
0x00223048
Interrupt Source Register Low
INTSRCL
0x0022304C
Interrupt Force Register High
INTFRCH
0x00223050
Interrupt Force Register Low
INTFRCL
0x00223054
Normal Interrupt Pending Register High
NIPNDH
0x00223058
Normal Interrupt Pending Register Low
NIPNDL
0x0022305C
Fast Interrupt Pending Register High
FIPNDH
0x00223060
Fast Interrupt Pending Register Low
FIPNDL
0x00223064
MC9328MX1 Reference Manual, Rev. 6.1
10-4
Freescale Semiconductor
Programming Model
Table 10-3. Register Field Summary
Name
31 30 29 28 27 26 25 24 23 22 21
R 0
0
0
0
0
0
0
0
0
0
20
19
0
INTCNTL
18
17
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
0
0
0
0
0
0
0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0 0 0 0 0 0
NIAD FIAD
W
R 0
0
0
0
0
0
0
0
0
0
0
0
0
NIMASK
NIMASK
W
R 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0 0 0 0 0 0 0 0 0
INTENNUM
W
R 0
ENNUM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0 0 0 0 0 0 0 0 0
INTDISNUM
W
DISNUM
R
INTENABLEH
INTENABLE [63:32]
W
R
INTENABLEL
INTENABLE [31:0]
W
R
INTTYPEH
INTTYPE [63:32]
W
R
INTTYPEL
INTTYPE [31:0]
W
R
NIPRIORITY7
NIPR63
NIPR62
NIPR61
NIPR60
NIPR59
NIPR58
NIPR57
NIPR56
NIPR55
NIPR54
NIPR53
NIPR52
NIPR51
NIPR50
NIPR49
NIPR48
NIPR47
NIPR46
NIPR45
NIPR44
NIPR43
NIPR42
NIPR41
NIPR40
NIPR39
NIPR38
NIPR37
NIPR36
NIPR35
NIPR34
NIPR33
NIPR32
NIPR31
NIPR30
NIPR29
NIPR28
NIPR27
NIPR26
NIPR25
NIPR24
NIPR23
NIPR22
NIPR21
NIPR20
NIPR19
NIPR18
NIPR17
NIPR16
NIPR15
NIPR14
NIPR13
NIPR12
NIPR11
NIPR10
NIPR9
NIPR8
NIPR7
NIPR6
NIPR5
NIPR4
NIPR3
NIPR2
NIPR1
NIPR0
W
R
NIPRIORITY6
W
R
NIPRIORITY5
W
R
NIPRIORITY4
W
R
NIPRIORITY3
W
R
NIPRIORITY2
W
R
NIPRIORITY1
W
R
NIPRIORITY0
W
R
NIVECTOR
NIPRILVL
NIVECSR
W
R
FIVECTOR
FIVECSR
W
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-5
Programming Model
Table 10-3. Register Field Summary (continued)
Name
31 30 29 28 27 26 25 24 23 22 21
20
19
R
18
17
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTIN [63:32]
INTSRCH
W
R
INTIN [31:0]
INTSRCL
W
R
INTFRCH
FORCE [63:32]
W
R
INTFRCL
FORCE [31:0]
W
R
NIPEND [63:32]
NIPNDH
W
R
NIPEND [31:0]
NIPNDL
W
R
FIPEND [63:32]
FIPNDH
W
R
FIPEND [31:0]
FIPNDL
W
10.4.1 Interrupt Control Register
The Interrupt Control Register (INTCNTL) is located on the ARM920T processor’s native bus, is accessible in 1
cycle, and can be accessed only in supervisor mode. This register must be accessed only on word (32-bit)
boundaries.
INTCNTL
BIT
TYPE
31
Addr
0x00223000
Interrupt Control Register
30
29
28
27
26
25
24
23
22
21
20
19
NIAD
FIAD
18
17
16
r
r
r
r
r
r
r
r
r
r
r
rw
rw
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
10-6
Freescale Semiconductor
Programming Model
Table 10-4. Interrupt Control Register Description
Name
Description
Reserved
Bits 31–21
Reserved—These bits are reserved and should read 0.
NIAD
Bit 20
Normal Interrupt Arbiter Disable—Enables/Disables the assertion of a
bus request to the ARM9 core when the normal interrupt signal (nIRQ) is
asserted. When an alternate master has ownership of the bus when a
normal interrupt occurs, the bus is given back to the ARM9 core after the
DMA device has completed its accesses, so the IRQ_DIS bit does not
affect alternate master accesses that are in progress.
Settings
0 = Disregard the normal interrupt
flag when evaluating bus
requests
1 = Normal interrupt flag prevents
alternate masters from
accessing the system bus
Note: To prevent an alternate master from accessing the bus during
an interrupt service routine, do not clear the interrupt flag until the end of
the service routine.
FIAD
Bit 19
Fast Interrupt Arbiter Disable—Enables/Disables the assertion of a
bus request to the ARM9 core when the fast interrupt signal (nFIQ) is
asserted. When an alternate master has ownership of the bus when a
fast interrupt occurs, the bus is given back to the ARM9 core after the
DMA device has completed its accesses, so the IRQ_DIS bit does not
affect alternate master accesses that are in progress.
0 = Disregard the fast interrupt flag
when evaluating bus requests
1 = Fast interrupt flag prevents
alternate masters from
accessing the system bus
Note: To prevent an alternate master from accessing the bus during
an interrupt service routine, do not clear the interrupt flag until the end of
the service routine.
Reserved
Bits 18–0
Reserved—These bits are reserved and should read 0.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-7
Programming Model
10.4.2 Normal Interrupt Mask Register
The Normal Interrupt Mask Register (NIMASK) controls the normal interrupt mask level. All normal interrupts
with a priority level less than or equal to the NIMASK are disabled. The priority levels of normal interrupts are
determined by the normal interrupt priority level registers (NIPRIORITY7, NIPRIORITY6, NIPRIORITY5,
NIPRIORITY4, NIPRIORITY3, NIPRIORITY2, NIPRIORITY1, and NIPRIORITY0). The reset state of this
register does not disable any normal interrupts.
Writing all 1’s, or –1, to the NIMASK sets the normal interrupt mask to –1 and does not disable any normal
interrupt priority levels.
This hardware mechanism creates reentrant normal interrupt routines by disabling lower priority normal interrupts.
Refer to Section 10.5.6, “Writing Reentrant Normal Interrupt Routines,” on page 10-35 for more details on the use
of the NIMASK register.
This register is located on the ARM920T processor’s native bus, is accessible in 1 cycle, and can be accessed only
in supervisor mode. This register must be accessed only on word (32-bit) boundaries.
NIMASK
Addr
0x00223004
Normal Interrupt Mask Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
NIMASK
TYPE
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
RESET
0x001F
Table 10-5. Normal Interrupt Mask Register Description
Name
Description
Reserved
Bits 31–5
Reserved—These bits are reserved and should read 0.
NIMASK
Bits 4–0
Normal Interrupt Mask—Controls normal interrupt
mask level. All normal interrupts of priority level less
than or equal to the NIMASK are disabled. Settings
are shown in decimal. Setting bit 4 disables all normal
interrupts.
Settings
0 = Disable priority level 0 normal interrupts
1 = Disable priority level 1 and lower normal interrupts
...
16+ = Disable all normal interrupts.
MC9328MX1 Reference Manual, Rev. 6.1
10-8
Freescale Semiconductor
Programming Model
10.4.3 Interrupt Enable Number Register
The Interrupt Enable Number Register (INTENNUM) provides hardware accelerated enabling of interrupts. Any
write to INTENNUM enables one interrupt source. For example, when the 6 LSBs = 000000, interrupt source 0 is
enabled; when the 6 LSBs = 000001, interrupt source 1 is enabled, and so forth. This register is decoded into a
single hot mask that is logically ORed with the INTENABLEH and the INTENABLEL registers.
This hardware mechanism removes the requirement for an atomic read/modify/write sequence to enable an
interrupt source. For example, to enable interrupts 10 and 20, the software performs two writes to the AITC: first
write 10, then write 20 to the INTENNUM register (the order of the writes is irrelevant to the AITC).
This register is located on the ARM920T processor’s native bus, is accessible in 1 cycle, and can be accessed only
in supervisor mode. This register must be accessed only on word (32-bit) boundaries. This register is self-clearing
and therefore always reads back all 0s.
INTENNUM
Addr
0x00223008
Interrupt Enable Number Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
ENNUM
TYPE
r
r
r
r
r
r
r
r
r
r
slfclr
slfclr
slfclr
slfclr
slfclr
slfclr
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-6. Interrupt Enable Number Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
ENNUM
Bits 5–0
Interrupt Enable Number—Enables/Disables the interrupt
source associated with this value.
Settings
0x00 = Enable interrupt source 0
0x01 = Enable interrupt source 1
...
0x3F = Enable interrupt source 63
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-9
Programming Model
10.4.4 Interrupt Disable Number Register
The Interrupt Disable Number Register (INTDISNUM) provides hardware accelerated disabling of interrupts. Any
write to this register disables one interrupt source. When the 6 LSBs = 000000, then interrupt source 0 is disabled;
when the 6 LSBs = 000001, then interrupt source 1 is disabled, and so forth. This register is decoded into a single
hot mask that is inverted and logically ANDed with the INTENABLEH and the INTENABLEL registers.
This hardware mechanism removes the requirement for an atomic read/modify/write sequence to disable an
interrupt source. To disable interrupts 10 and 20, the software performs two writes to the AITC: first write 10, then
write 20 to INTDISNUM register (the order of the writes is irrelevant to the AITC).
This register is located on the ARM920T processor’s native bus, is accessible in 1 cycle, and can be accessed only
in supervisor mode. This register must be accessed only on word (32-bit) boundaries. This register is self-clearing
and therefore always reads back all 0s.
INTDISNUM
Addr
0x0022300C
Interrupt Disable Number Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DISNUM
TYPE
r
r
r
r
r
r
r
r
r
r
slfclr
slfclr
slfclr
slfclr
slfclr
slfclr
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-7. Interrupt Disable Number Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
DISNUM
Bits 5–0
Interrupt Disable Number—Enables/Disables the
interrupt source associated with this value.
Settings
0x00 = Disable interrupt source 0
0x01 = Disable interrupt source 1
...
0x3F = Disable interrupt source 63
MC9328MX1 Reference Manual, Rev. 6.1
10-10
Freescale Semiconductor
Programming Model
10.4.5 Interrupt Enable Register High and Interrupt Enable Register Low
The Interrupt Enable Register High (INTENABLEH) and the Interrupt Enable Register Low (INTENABLEL)
registers enable pending interrupt requests to the ARM920T processor. Each bit in these registers corresponds to an
interrupt source available in the system. The reset state of both registers is all interrupts masked.
These registers are updated by the following methods:
•
Write directly to the INTENABLEH and INTENABLEL registers
•
Set bits with the INTENNUM register
•
Clear bits with the INTDISNUM register
These registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed
only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.
10.4.5.1 Interrupt Enable Register High
INTENABLEH
BIT
31
30
Addr
0x00223010
Interrupt Enable Register High
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INTENABLE [63:48]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
INTENABLE [47:32]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-8. Interrupt Enable Register High Description
Name
Description
INTENABLE
Bits 31–0
Interrupt Enable—Enables/Disables the individual bit interrupt sources to
request a normal interrupt or a fast interrupt. When INTENABLE is set and the
corresponding interrupt source is asserted, the interrupt controller asserts a
normal or a fast interrupt request depending on the associated INTTYPEH
and INTTYPEL setting.
Settings
0 = Interrupt disabled
1 = Interrupt enabled and
generates a normal or
fast interrupt upon
assertion
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-11
Programming Model
10.4.5.2 Interrupt Enable Register Low
INTENABLEL
BIT
31
Addr
0x00223014
Interrupt Enable Register Low
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INTENABLE [31:16]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
INTENABLE [15:0]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-9. Interrupt Enable Register Low Description
Name
Description
Settings
INTENABLE
Bits 31–0
Interrupt Enable—Enables/Disables the individual bit interrupt sources to
request a normal interrupt or a fast interrupt. When INTENABLE is set and the
corresponding interrupt source is asserted, the interrupt controller asserts a
normal or a fast interrupt request depending on the associated INTTYPEH and
INTTYPEL setting.
0 = Interrupt disabled
1 = Interrupt enabled and
generates a normal or
fast interrupt upon
assertion
MC9328MX1 Reference Manual, Rev. 6.1
10-12
Freescale Semiconductor
Programming Model
10.4.6 Interrupt Type Register High and Interrupt Type Register Low
The Interrupt Type Register High (INTTYPEH) and the Interrupt Type Register Low (INTTYPEL) registers select
whether a pending interrupt source, when enabled with the INTENABLEH and INTENABLEL registers, creates a
normal interrupt or a fast interrupt to the ARM920T processor. Each bit in this register corresponds to an interrupt
source available in the system. The reset state of both registers is all interrupts generate a normal interrupt.
These registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed
only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.
10.4.6.1 Interrupt Type Register High
INTTYPEH
BIT
31
Addr
0x00223018
Interrupt Type Register High
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INTTYPE [63:48]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
INTTYPE [47:32]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-10. Interrupt Type Register High Description
Name
INTTYPE
Bits 31–0
Description
Interrupt Type—Controls whether the individual interrupt sources
request a normal interrupt or a fast interrupt.
When a INTTYPE bit is set and the corresponding interrupt source is
asserted, the interrupt controller asserts a fast interrupt request.
Settings
0 = Interrupt source generates a
normal interrupt (nIRQ)
1 = Interrupt source generates a fast
interrupt (nFIQ)
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-13
Programming Model
10.4.6.2 Interrupt Type Register Low
INTTYPEL
BIT
31
Addr
0x0022301C
Interrupt Type Register Low
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INTTYPE [31:16]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
INTTYPE [15:0]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-11. Interrupt Type Register Low Description
Name
INTTYPE
Bits 31–0
Description
Settings
Interrupt Type—Controls whether the individual interrupt sources
request a normal interrupt or a fast interrupt.
When a bit is set in INTTYPE and the corresponding interrupt source
is asserted, the interrupt controller asserts a fast interrupt request.
0 = Interrupt source generates a
normal interrupt (nIRQ)
1 = Interrupt source generates a fast
interrupt (nFIQ)
10.4.7 Normal Interrupt Priority Level Registers
The normal interrupt priority level registers (NIPRIORITY7, NIPRIORITY6, NIPRIORITY5, NIPRIORITY4,
NIPRIORITY3, NIPRIORITY2, NIPRIORITY1, and NIPRIORITY0) provide a software controllable
prioritization of normal interrupts. Normal interrupts with a higher priority level preempt normal interrupts with a
lower priority. The reset state of these registers forces all normal interrupts to the lowest priority level.
When a level 0 normal interrupt and a level 1 normal interrupt are asserted at the same time, the level 1 normal
interrupt is selected assuming that NIMASK has not disabled level 1 normal interrupts. When two level 1 normal
interrupts are asserted at the same time, the level 1 normal interrupt with the highest source number is selected, also
assuming that NIMASK has not disabled level 1 normal interrupts.
These registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed
only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.
MC9328MX1 Reference Manual, Rev. 6.1
10-14
Freescale Semiconductor
Programming Model
10.4.7.1 Normal Interrupt Priority Level Register 7
NIPRIORITY7
BIT
31
30
29
28
27
NIPR63
TYPE
Addr
0x00223020
Normal Interrupt Priority Level Register 7
26
25
24
23
NIPR62
22
21
20
19
NIPR61
18
17
16
NIPR60
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
NIPR59
TYPE
10
9
8
NIPR58
NIPR57
NIPR56
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-12. Normal Interrupt Priority Level Register 7 Description
Name
Description
NIPR63
Bits 31–28
Normal Interrupt Priority Level—Selects the software controlled
priority level for the associated normal interrupt source.
NIPR62
Bits 27–24
These registers do not affect the prioritization of fast interrupt
priorities.
Settings
0000 = Lowest priority normal interrupt
...
1111 = Highest priority normal interrupt
NIPR61
Bits 23–20
NIPR60
Bits 19–16
NIPR59
Bits 15–12
NIPR58
Bits 11–8
NIPR57
Bits 7–4
NIPR56
Bits 3–0
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-15
Programming Model
10.4.7.2 Normal Interrupt Priority Level Register 6
NIPRIORITY6
BIT
31
30
29
28
27
NIPR55
TYPE
Addr
0x00223024
Normal Interrupt Priority Level Register 6
26
25
24
23
NIPR54
22
21
20
19
NIPR53
18
17
16
NIPR52
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
l6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
NIPR51
TYPE
10
9
8
NIPR50
NIPR49
NIPR48
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-13. Normal Interrupt Priority Level Register 6 Description
Name
Description
Settings
NIPR55
Bits 31–28
Normal Interrupt Priority Level—Selects the software controlled
priority level for the associated normal interrupt source.
0000 = Lowest priority normal interrupt
...
1111 = Highest priority normal interrupt
NIPR54
Bits 27–24
These registers do not affect the prioritization of fast interrupt
priorities.
NIPR53
Bits 23–20
NIPR52
Bits 19–16
NIPR51
Bits 15–12
NIPR50
Bits 11–8
NIPR49
Bits 7–4
NIPR48
Bits 3–0
MC9328MX1 Reference Manual, Rev. 6.1
10-16
Freescale Semiconductor
Programming Model
10.4.7.3 Normal Interrupt Priority Level Register 5
NIPRIORITY5
BIT
31
30
29
28
27
NIPR47
TYPE
Addr
0x00223028
Normal Interrupt Priority Level Register 5
26
25
24
23
NIPR46
22
21
20
19
NIPR45
18
17
16
NIPR44
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
NIPR43
TYPE
10
9
8
NIPR42
NIPR41
NIPR40
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-14. Normal Interrupt Priority Level Register 5 Description
Name
Description
NIPR47
Bits 31–28
Normal Interrupt Priority Level—Selects the software controlled
priority level for the associated normal interrupt source.
NIPR46
Bits 27–24
These registers do not affect the prioritization of fast interrupt
priorities.
Settings
0000 = Lowest priority normal interrupt
...
1111 = Highest priority normal interrupt
NIPR45
Bits 23–20
NIPR44
Bits 19–16
NIPR43
Bits 15–12
NIPR42
Bits 11–8
NIPR41
Bits 7–4
NIPR40
Bits 3–0
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-17
Programming Model
10.4.7.4 Normal Interrupt Priority Level Register 4
NIPRIORITY4
BIT
31
30
29
28
27
NIPR39
TYPE
Addr
0x0022302C
Normal Interrupt Priority Level Register 4
26
25
24
23
NIPR38
22
21
20
19
NIPR37
18
17
16
NIPR36
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
NIPR35
TYPE
10
9
8
NIPR34
NIPR33
NIPR32
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-15. Normal Interrupt Priority Level Register 4 Description
Name
Description
NIPR39
Bits 31–28
Normal Interrupt Priority Level—Selects the software controlled
priority level for the associated normal interrupt source.
NIPR38
Bits 27–24
These registers do not affect the prioritization of fast interrupt
priorities.
Settings
0000 = Lowest priority normal interrupt
...
1111 = Highest priority normal interrupt
NIPR37
Bits 23–20
NIPR36
Bits 19–16
NIPR35
Bits 15–12
NIPR34
Bits 11–8
NIPR33
Bits 7–4
NIPR32
Bits 3–0
MC9328MX1 Reference Manual, Rev. 6.1
10-18
Freescale Semiconductor
Programming Model
10.4.7.5 Normal Interrupt Priority Level Register 3
NIPRIORITY3
BIT
31
30
29
28
27
NIPR31
TYPE
Addr
0x00223030
Normal Interrupt Priority Level Register 3
26
25
24
23
22
NIPR30
21
20
19
NIPR29
18
17
16
NIPR28
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
NIPR27
TYPE
10
9
8
NIPR26
NIPR25
NIPR24
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-16. Normal Interrupt Priority Level Register 3 Description
Name
NIPR31
Bits 31–28
NIPR30
Bits 27–24
Description
Normal Interrupt Priority Level—Selects the software
controlled priority level for the associated normal interrupt
source.
Settings
0000 = Lowest priority normal interrupt
...
1111 = Highest priority normal interrupt
These registers do not affect the prioritization of fast interrupt
priorities.
NIPR29
Bits 23–20
NIPR28
Bits 19–16
NIPR27
Bits 15–12
NIPR26
Bits 11–8
NIPR25
Bits 7–4
NIPR24
Bits 3–0
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-19
Programming Model
10.4.7.6 Normal Interrupt Priority Level Register 2
NIPRIORITY2
BIT
31
30
29
28
27
NIPR23
TYPE
Addr
0x00223034
Normal Interrupt Priority Level Register 2
26
25
24
23
NIPR22
22
21
20
19
NIPR21
18
17
16
NIPR20
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
NIPR19
TYPE
10
9
8
NIPR18
NIPR17
NIPR16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-17. Normal Interrupt Priority Level Register 2 Description
Name
NIPR23
Bits 31–28
NIPR22
Bits 27–24
Description
Normal Interrupt Priority Level—Selects the software
controlled priority level for the associated normal interrupt
source.
Settings
0000 = Lowest priority normal interrupt
...
1111 = Highest priority normal interrupt
These registers do not affect the prioritization of fast interrupt
priorities.
NIPR21
Bits 23–20
NIPR20
Bits 19–16
NIPR19
Bits 15–12
NIPR18
Bits 11–8
NIPR17
Bits 7–4
NIPR16
Bits 3–0
MC9328MX1 Reference Manual, Rev. 6.1
10-20
Freescale Semiconductor
Programming Model
10.4.7.7 Normal Interrupt Priority Level Register 1
NIPRIORITY1
BIT
31
30
29
28
27
NIPR15
TYPE
Addr
0x00223038
Normal Interrupt Priority Level Register 1
26
25
24
23
NIPR14
22
21
20
19
NIPR13
18
17
16
NIPR12
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
NIPR11
TYPE
10
9
8
NIPR10
NIPR9
NIPR8
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-18. Normal Interrupt Priority Level Register 1 Description
Name
NIPR15
Bits 31–28
NIPR14
Bits 27–24
Description
Normal Interrupt Priority Level—Selects the software
controlled priority level for the associated normal interrupt
source.
Settings
0000 = Lowest priority normal interrupt
...
1111 = Highest priority normal interrupt
These registers do not affect the prioritization of fast interrupt
priorities.
NIPR13
Bits 23–20
NIPR12
Bits 19–16
NIPR11
Bits 15–12
NIPR10
Bits 11–8
NIPR9
Bits 7–4
NIPR8
Bits 3–0
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-21
Programming Model
10.4.7.8 Normal Interrupt Priority Level Register 0
NIPRIORITY0
BIT
31
30
29
28
27
26
NIPR7
TYPE
Addr
0x0022303C
Normal Interrupt Priority Level Register 0
25
24
23
22
NIPR6
21
20
19
18
NIPR5
17
16
NIPR4
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
NIPR3
TYPE
9
8
NIPR2
NIPR1
NIPR0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-19. Normal Interrupt Priority Level Register 0 Description
Name
NIPR7
Bits 31–28
NIPR6
Bits 27–24
Description
Normal Interrupt Priority Level—Selects the software
controlled priority level for the associated normal interrupt
source.
Settings
0000 = Lowest priority normal interrupt
...
1111 = Highest priority normal interrupt
These registers do not affect the prioritization of fast interrupt
priorities.
NIPR5
Bits 23–20
NIPR4
Bits 19–16
NIPR3
Bits 15–12
NIPR2
Bits 11–8
NIPR1
Bits 7–4
NIPR0
Bits 3–0
MC9328MX1 Reference Manual, Rev. 6.1
10-22
Freescale Semiconductor
Programming Model
10.4.8 Normal Interrupt Vector and Status Register
The Normal Interrupt Vector and Status Register (NIVECSR) specifies the priority of the highest pending normal
interrupt and provides the vector index of the interrupt’s service routine. This number can be directly used as an
index into a vector table to select the highest pending normal interrupt source.
This read-only register is located on the ARM920T processor’s native bus, is accessible in 1 cycle, and can be
accessed only in supervisor mode. This register must be accessed only on word (32-bit) boundaries.
NIVECSR
BIT
31
Addr
0x00223040
Normal Interrupt Vector and Status Register
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
NIVECTOR
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
RESET
0xFFFF
BIT
15
14
13
12
11
10
9
8
NIPRILVL
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
0xFFFF
Table 10-20. Normal Interrupt Vector and Status Register Description
Name
Description
Settings
NIVECTOR
Bits 31–16
Normal Interrupt Vector—Indicates vector index for the
highest pending normal interrupt. Settings are shown in
decimal.
0 = Interrupt 0 highest priority pending normal
interrupt
1 = Interrupt 1 highest priority pending normal
interrupt
...
63 = Interrupt 63 highest priority pending
normal interrupt
64+ = No normal interrupt request pending
NIPRILVL
Bits 15–0
Normal Interrupt Priority Level—Indicates the priority level
of the highest priority normal interrupt. This number can be
written to the NIMASK to disable the current priority normal
interrupts to build a reentrant normal interrupt system.
Settings are shown in decimal.
0 = Highest priority normal interrupt is level 0
1 = Highest priority normal interrupt is level 1
...
15 = Highest priority normal interrupt is level 15
16+ = No normal interrupt request pending
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-23
Programming Model
10.4.9 Fast Interrupt Vector and Status Register
The Fast Interrupt Vector and Status Register (FIVECSR) specifies the priority of the highest pending fast interrupt
and provides the vector index for the interrupt’s service routine. This number can be directly used as an index into
a vector table to select the highest pending fast interrupt source.
This read-only register is located on the ARM920T processor’s native bus, is accessible in 1 cycle, and can be
accessed only in supervisor mode. This register must be accessed only on word (32-bit) boundaries.
FIVECSR
BIT
31
Addr
0x00223044
Fast Interrupt Vector and Status Register
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FIVECTOR [31:16]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
RESET
0xFFFF
BIT
15
14
13
12
11
10
9
8
FIVECTOR [15:0]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
0xFFFF
Table 10-21. Fast Interrupt Vector and Status Register Description
Name
FIVECTOR
Bits 31–0
Description
Fast Interrupt Vector—Indicates vector index for
the highest pending fast interrupt.
Settings
0 = Interrupt 0 is highest pending fast interrupt
1 = Interrupt 1 is highest pending fast interrupt
...
63 = Interrupt 63 is highest pending fast interrupt
64+ = not used, does not occur
MC9328MX1 Reference Manual, Rev. 6.1
10-24
Freescale Semiconductor
Programming Model
10.4.10 Interrupt Source Register High and Interrupt Source Register Low
The Interrupt Source Register High (INTSRCH) and the Interrupt Source Register Low (INTSRCL) registers are
each 32 bits wide. INTSRCH and INTSRCL reflect the status of all interrupt request inputs into the interrupt
controller. Bit positions that are not used always read 0 (no request pending). The peripheral circuits generating the
requests determine the state of this register out of reset; normally, the requests are inactive.
These read-only registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be
accessed only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.
10.4.10.1 Interrupt Source Register High
INTSRCH
BIT
31
Addr
0x00223048
Interrupt Source Register High
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INTIN [63:48]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
INTIN [47:32]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-22. Interrupt Source Register High Description
Name
INTIN
Bits 31–0
Description
Interrupt Source—Indicates the state of the corresponding hardware
interrupt source.
Settings
0 = Interrupt source negated
1 = Interrupt source asserted
NOTE:
The peripheral circuits generating the requests determine the state of this register
out of reset; normally, the requests are inactive. This read-only register must be
accessed only on word (32-bit) boundaries.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-25
Programming Model
10.4.10.2 Interrupt Source Register Low
INTSRCL
BIT
31
Addr
0x0022304C
Interrupt Source Register Low
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INTIN [31:16]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
INTIN [15:0]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-23. Interrupt Source Register Low Description
Name
INTIN
Bits 31–0
Description
Interrupt Source—Indicates the state of the corresponding hardware
interrupt source.
Settings
0 = Interrupt source negated
1 = Interrupt source asserted
NOTE:
The state of this register out of reset is determined by the peripheral circuits
generating the requests; normally, the requests are inactive. This read-only register
must be accessed only on word (32-bit) boundaries.
MC9328MX1 Reference Manual, Rev. 6.1
10-26
Freescale Semiconductor
Programming Model
10.4.11 Interrupt Force Register High and Interrupt Force Register Low
The Interrupt Force Register High (INTFRCH) and the Interrupt Force Register Low (INTFRCL) registers are each
32 bits wide. The interrupt forces registers allow for software generation of interrupts for each of the possible
interrupt sources for functional or debugging purposes. The system level design can reserve one or more sources
for software purposes to allow software to self-schedule interrupts by forcing one or more of these sources in the
appropriate interrupt force register(s).
These registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed
only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.
10.4.11.1 Interrupt Force Register High
INTFRCH
BIT
31
Addr
0x00223050
Interrupt Force Register High
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FORCE [63:48]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
FORCE [47:32]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-24. Interrupt Force Register High Description
Name
FORCE
Bits 31–0
Description
Interrupt Source Force Request—Forces a request for the
corresponding interrupt source.
Settings
0 = Standard interrupt operation
1 = Interrupt forced asserted
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-27
Programming Model
10.4.11.2 Interrupt Force Register Low
INTFRCL
BIT
31
Addr
0x00223054
Interrupt Force Register Low
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FORCE [31:16]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
FORCE [15:0]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-25. Interrupt Force Register Low Description
Name
FORCE
Bits 31–0
Description
Interrupt Source Force Request—Forces a request for the
corresponding interrupt source.
Settings
0 = Standard interrupt operation
1 = Interrupt forced asserted
MC9328MX1 Reference Manual, Rev. 6.1
10-28
Freescale Semiconductor
Programming Model
10.4.12 Normal Interrupt Pending Register High and Normal Interrupt
Pending Register Low
The Normal Interrupt Pending Register High (NIPNDH) and the Normal Interrupt Pending Register Low
(NIPNDL) registers are 32-bits wide and monitor the outputs of the enable and masking operations. These registers
are actually only a set of buffers, so the reset state of these registers is determined by the normal interrupt enable
registers, the interrupt mask register, and the interrupt source registers.
These read-only registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be
accessed only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.
10.4.12.1 Normal Interrupt Pending Register High
NIPNDH
BIT
Addr
0x00223058
Normal Interrupt Pending Register High
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
NIPEND [63:48]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
NIPEND [47:32]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-26. Normal Interrupt Pending Register High Description
Name
Description
Settings
NIPEND
Bits 31–0
Normal Interrupt Pending Bit—Indicates whether a normal interrupt is
pending. When a normal interrupt enable bit is set and the
corresponding interrupt source is asserted, the interrupt controller
asserts a normal interrupt request. The normal interrupt pending bits
reflect the interrupt input lines that are asserted and are currently
enabled to generate a normal interrupt.
0 = No normal interrupt request
1 = Normal interrupt request pending
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-29
Programming Model
10.4.12.2 Normal Interrupt Pending Register Low
NIPNDL
BIT
Addr
0x0022305C
Normal Interrupt Pending Register Low
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
NIPEND [31:16]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
NIPEND [15:0]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-27. Normal Interrupt Pending Register Low Description
Name
Description
Settings
NIPEND
Bits 31–0
Normal Interrupt Pending Bit—Indicates whether a normal interrupt is
pending. When a normal interrupt enable bit is set and the
corresponding interrupt source is asserted, the interrupt controller
asserts a normal interrupt request. The normal interrupt pending bits
reflect the interrupt input lines that are asserted and are currently
enabled to generate a normal interrupt.
0 = No normal interrupt request
1 = Normal interrupt request pending
MC9328MX1 Reference Manual, Rev. 6.1
10-30
Freescale Semiconductor
Programming Model
10.4.13 Fast Interrupt Pending Register High and Fast Interrupt Pending
Register Low
The Fast Interrupt Pending Register High (FIPNDH) and the Fast Interrupt Pending Register Low (FIPNDL)
registers are 32-bits wide and monitor the outputs of the enable and masking operations. These registers are
actually only a set of buffers, so the reset state of these registers is determined by the fast interrupt enable registers,
the interrupt mask register, and the interrupt source registers.
These read-only registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be
accessed only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.
10.4.13.1 Fast Interrupt Pending Register High
FIPNDH
BIT
Addr
0x00223060
Fast Interrupt Pending Register High
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FIPEND [63:48]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
FIPEND [47:32]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-28. Fast Interrupt Pending Register High Description
Name
FIPEND
Bits 31–0
Description
Settings
Fast Interrupt Pending Bit—Indicates if a fast interrupt request is
pending. When a fast interrupt enable bit is set and the corresponding
interrupt source is asserted, the interrupt controller asserts a fast
interrupt request. The fast interrupt pending bits reflect the interrupt input
lines that are asserted and are currently enabled to generate a fast
interrupt.
0 = No fast interrupt request
pending
1 = Fast interrupt request pending
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-31
Programming Model
10.4.13.2 Fast Interrupt Pending Register Low
FIPNDL
BIT
Addr
0x00223064
Fast Interrupt Pending Register Low
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FIPEND [31:16]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
FIPEND [15:0]
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 10-29. Fast Interrupt Pending Register Low Description
Name
Description
Settings
FIPEND
Bits 31–0
Fast Interrupt Pending Bit—Indicates if a fast interrupt request is
pending. When a fast interrupt enable bit is set and the corresponding
interrupt source is asserted, the interrupt controller asserts a fast interrupt
request. The fast interrupt pending bits reflect the interrupt input lines that
are asserted and are currently enabled to generate a fast interrupt.
0 = No fast interrupt request
pending
1 = Fast interrupt request pending
MC9328MX1 Reference Manual, Rev. 6.1
10-32
Freescale Semiconductor
ARM920T Processor Interrupt Controller Operation
10.5 ARM920T Processor Interrupt Controller Operation
This section discusses the ARM920T processor prioritization of various exceptions and interrupt sources, two
methods of enabling or disabling interrupts, and provides a typical pipeline sequence.
10.5.1 ARM920T Processor Prioritization of Exception Sources
The ARM920T processor prioritizes the various exceptions as follows:
•
Reset (highest priority)
•
Data Abort
•
Fast Interrupt
•
Normal Interrupt
•
Prefetch Abort
•
Undefined Instruction and SWI (lowest priority)
10.5.2 AITC Prioritization of Interrupt Sources
The AITC module prioritizes the various interrupt sources by source number. Higher source numbers have higher
priority. Fast interrupts always have higher priority than normal interrupts.
Interrupt requests are prioritized as follows:
1. Fast interrupt requests, in order of highest source number
2. Normal interrupt requests, in order of highest priority level, then in order of highest source number
with the same priority level
10.5.3 Assigning and Enabling Interrupt Sources
The interrupt controller provides flexible assignment of any interrupt source to either of the two ARM920T
processor interrupt request inputs. This is done by setting the appropriate bits in the INTENABLEH and
INTENABLEL registers and the INTTYPEH and INTTYPEL registers. Interrupt assignment is usually done once
during system initialization and does not affect interrupt latency.
Interrupt assignment is the first of three steps required to enable an interrupt source, and this is done by the
MC9328MX1 hardware. The second step is to program the source to generate interrupt requests. The final step is to
enable the interrupt inputs in the ARM920T processor by clearing the normal interrupt disable (I) and/or the fast
interrupt disable (F) bits in the processor status register (CPSR).
10.5.4 Enabling Interrupts Sources
There are two methods of enabling or disabling interrupts in the AITC. The first method is to directly read the
INTENABLEH and INTENABLEL registers, logically OR or BIT CLEAR these registers with a generated mask,
then write back to the INTENABLEH and INTENABLEL registers.
The second method is performing an atomic write to source number of the INTENNUM register. The AITC
decodes this 6-bit register and enables one of the 64 interrupt sources. The AITC automatically generates a single
hot enable mask and logically ORs this mask to the correct INTENABLEH and INTENABLEL register. To disable
interrupts, the procedure is exactly the same except the source number is written to the INTDISNUM register.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-33
ARM920T Processor Interrupt Controller Operation
10.5.5 Typical Interrupt Entry Sequences
The Table 10-30 is a typical pipeline sequence for the ARM920T processor when a normal interrupt occurs.
Assuming single cycle memories, it takes approximately 6 clocks from the acknowledgement of the normal
interrupt within the ARM920T processor until the first opcode of the interrupt routine is fetched.
Table 10-30. Typical Hardware Accelerated Normal Interrupt Entry Sequence
Time
Address
–2
–1
nIRQ
Assert
Last ADDR
before nIRQ
1
2
3
4
5
Link
Adjust
Fetch
Dec
Exec
Data
Wrbk
Fetch
Dec
6
7
8
Fetch
Dec
Exec
Fetch
Dec
nIRQ
ACK
Fetch
+4 / +2
0
Dec
Exec
Fetch
Dec
+8 / +4
Fetch
0x00000018
+4
+8
Fetch
Vector Table
Vector
N/A
nIRQ Routine
+4
+8
Fetch
The Table 10-31 on page 10-34 is a typical pipeline sequence for the ARM920T processor when a fast interrupt
occurs, assuming that the FIQ service routine begins at 0x0000001C and single cycle memories.
Table 10-31. Typical Fast Interrupt Entry Sequence
Time
Address
–2
–1
nFIQ
Assert
Last ADDR before nFIQ
+4 / +2
+8 / +4
0x0000001C
Fetch
0
1
2
3
Link
Adjust
Fetch
Dec
Exec
Fetch
Dec
nFIQ
ACK
Dec
Exec
Fetch
Dec
Fetch
+4
+8
Fetch
MC9328MX1 Reference Manual, Rev. 6.1
10-34
Freescale Semiconductor
ARM920T Processor Interrupt Controller Operation
10.5.6 Writing Reentrant Normal Interrupt Routines
The AITC can create a reentrant normal interrupt system. This enables preempting of lower priority level interrupts
by higher priority level interrupts. This requires a small amount of software support and overhead. The following
shows the steps necessary to accomplish this:
1. Push the link register (LR_IRQ) onto the stack (SP_IRQ).
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Push the saved status register (SPSR_IRQ) onto the stack.
Read the current value of NIMASK and push this value onto the stack.
Read current priority level via NIVECSR.
Interrupts of the equal or lesser priority than the current priority level must be masked via the
NIMASK register by writing value from NIVECSR.
Clear the I bit in the ARM920T processor via a MSR / MRS command sequence (a higher priority
normal interrupt can preempt a lower priority one) and change the operating mode of the ARM920T
processor to system mode from IRQ mode.
Push the System Mode Link Register (LR) onto the stack (SP_USER).
The traditional interrupt service routine is now included.
Pop the System Mode Link Register (LR) from the stack (SP_USER).
Set the I bit in the ARM920T processor via a MSR/MRS command sequence (disables all normal
interrupts) and change the operating mode of the ARM920T processor to IRQ mode from system
mode.
Pop the original value of the normal interrupt mask and write the value to the NIMASK register.
Pop the Saved Status Register from the stack (SP_IRQ).
Pop the link register from the stack into the PC.
Return from nIRQ.
NOTE:
These steps are still in development and are subject to change. Steps 1, 2, 13, and
14 are automatically done by most C compilers and are included for completeness.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
10-35
ARM920T Processor Interrupt Controller Operation
MC9328MX1 Reference Manual, Rev. 6.1
10-36
Freescale Semiconductor
Chapter 11
External Interface Module (EIM)
11.1 Overview
The External Interface Module (EIM) handles the interface to devices external to the MC9328MX1, including
generation of chip selects for external peripherals and memory, and provides the following features:
•
Six chip selects for external devices: CS0, covering a range of 32 Mbyte, and CS1–CS5, covering a range
of 16 Mbyte each
•
Selectable protection for each chip select
•
Reset programmable data port size for CS0
•
Programmable data port size for each chip select
•
Address suppression during burst mode operations
•
Synchronous burst mode support for burst flash devices
•
Programmable wait-state generator for each chip select
•
Supports big endian and little endian modes of operation
•
Programmable general output capability for unused chip select outputs
11.2 EIM I/O Signals
The EIM I/O signals provide communication and control pathways between external devices and the
MC9328MX1. A summary of the I/O signal pins is provided in Table 11-2 on page 11-4. Each signal is described
in the following sections.
11.2.1 Address Bus
The A [24:0] signals are address bus outputs used to address external devices.
11.2.2 Data Bus
The D [31:0] signals are bidirectional data bus pins used to transfer data between the MC9328MX1 and an external
device.
11.2.3 Read/Write
The R/W output signal indicates if the current bus access is in a read or write cycle. A high (logic one) level
indicates a read cycle, and a low (logic zero) level indicates a write cycle.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
11-1
EIM I/O Signals
11.2.4 Control Signals
The OE and EB [3:0] signals are used to control external device’s interface to the external data bus.
11.2.4.1 OE—Output Enable
This active-low output signal indicates the bus access is a read, and enable slave devices to drive the data bus with
read data.
11.2.4.2 EB [3:0]—Enable Bytes
These active-low output pins indicate active data bytes for the current access. They may be configured to assert for
read and write cycles or for write cycles only as programmed in the CS configuration registers. EB [0] corresponds
to D [31:24], EB [1] corresponds to D [23:16], EB [2] corresponds to D [15:8], and EB [3] corresponds to D [7:0].
In the case of a 16-bit operation, or controlling the enable byte signals for half-word operation, either EB[0] or
EB[1] may be used for D[31:16], and either EB[2] or EB[3] may be used for D[15:0]. For word addressing, any of
on the EB[3:0] signals may be used.
This is especially useful when interfacing to external devices or memories that require strict timing control over the
write enable signal. Since there is no way to control the timing of the EIM WE signal, any one of the EB[3:0]
signals (if not already being used for enable byte control), may be used as the write enable signal. The bits WEA
and WEN in the Chip Select Control registers are used to vary the timing of these signals according to the bit
settings in those registers. The corresponding EB[3:0] signal that can be used for a corresponding set of D[31:0]
signals follows the EB[3:0] to D[31:0] mapping given above.
NOTE:
The pulse of OE, R/W, EB, and CS signals cannot be configured to less than one
system clock period (HCLK).
11.2.4.3 DTACK—Data Transfer Acknowledge
The DTACK signal is the external input data acknowledge signal that only supported by CS[5]. When the external
DTACK signal is used as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus
cycle is not terminated by the external DTACK signal after 1022 clocks counts have elapsed.
The maximum wait state supported by the DTACK signal at 96 MHz is 10.645us. This can be calculated by
dividing the number of maximum wait state cycles (in this case 1022) by the system clock frequency (HCLK). For
designs requiring a longer wait state time greater than 10.645us, it is necessary to reduce the system clock
frequency HCLK to an appropriate value that is less than 96 MHz. The system clock HCLK can be divided by
setting the BLCK_DIV bits in the Clock Source Control Register to the desired value. For more detailed
information about setting the BCLK_DIV bits, see Chapter 12, “Phase-Locked Loop and Clock Controller.”
11.2.5 Chip Select Outputs
11.2.5.1 Chip Select 0 (CS0)
The CS0 output signal is active-low and is asserted based on a decode of internal address bus bits A[31:24] of the
accessed address, and at reset is based on the value of the BOOTMOD [3:0] inputs. The port size is determined by
the state of the BOOTMOD[3:0] inputs. See Section 8.2, “System Boot Mode Selection,” on page 8-7 for more
information.
MC9328MX1 Reference Manual, Rev. 6.1
11-2
Freescale Semiconductor
Pin Configuration for EIM
11.2.5.2 Chip Select 1–Chip Select 5 (CS1–CS5)
The CS1 through CS5 output signals are active-low and are asserted based on a decode of the internal address bus
bits A [31:24] of the accessed address. When disabled, these pins can be used as programmable general-purpose
outputs. Table 11-1 specifies the address range for each Chip Select output.
Table 11-1. Chip Select Address Range
CSEN [x]
A [31:24]
Chip Select
Cleared
–
Inactive
Set
0001000x
CS0
Set
00010010
CS1
Set
00010011
CS2
Set
00010100
CS3
Set
00010101
CS4
Set
00010110
CS5
11.2.6 Burst Mode Signals
11.2.6.1 BCLK—Burst Clock
The BCLK output signal is used to clock external burst capable devices to synchronize the loading and
incrementing of addresses, and delivery of burst read data to the EIM. Its behavior is affected by the BCM bit in the
EIM configuration register and the SYNC, BCD, PME, and BCS bits in the EIM control registers.
11.2.6.2 LBA—Load Burst Address
The LBA active-low output signal is asserted during burst mode accesses to cause the external burst capable device
to load a new starting burst address. Assertion of LBA indicates that a valid address is present on the address bus.
Its behavior is affected by the SYNC, BCD, PME, and BCS bits in the EIM control registers.
11.2.6.3 ECB—End Current Burst
The ECB active-low input signal is asserted by external burst capable devices to indicate the end of the current
(continuous) burst sequence. Following assertion, the EIM terminates the current burst sequence and initiates a
new one.
11.3 Pin Configuration for EIM
Table 11-2 lists the pins used for the EIM module. Many of these pins are multiplexed with other functions on the
device, and must be configured for EIM operation.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
11-3
Pin Configuration for EIM
Table 11-2. EIM Pin List
Pin Name
Direction
Description
External I/O Signals
D [31:0]
Input/
Output
External 32-bit data bus
A [24:0]
Output
External address bus
CS [5:0]
Output
Active low external chip selects
DTACK
Input
EB [3:0]
Output
Active low external enable bytes signals. EB [0] controls D [31:24]*
OE
Output
Active low output enable for external data bus
BCLK (burst clock)
Output
Clock for external synchronous memories (such as burst flash) - burst clock.
LBA
Output
Active low signal sent to flash device causing the external device to latch the address.
RW
Output
Indicates whether external access is a read (high) or write (low) cycle
ECB
Input
External input data acknowledge signal for CS5
Input signal identifies when to end an external burst access
*EB [1] controls D [23:16], EB [2] controls D [15:8], EB [3] controls D [7:0]
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 32.5.1, “Data Direction Registers,” on
page 32-8 for details.
Table 11-3. Pin Configuration
Pins
Setting
Configuration Procedure
D [31:0]
Not Multiplexed
A [24]
Primary function of GPIO Port
A [0]
1. Clear bit 0 of Port A GPIO In Use Register (GIUS_A)
2. Clear bit 0 of Port A General Purpose Register (GPR_A)
A [23:16]
Primary function of GPIO Port
A [31:24]
1. Clear bits [31:24] of Port A GPIO In Use Register (GIUS_A)
2. Clear bits [31:24] of Port A General Purpose Register (GPR_A)
A [15:1]
Not Multiplexed
A [0]
Primary function of GPIO Port
A [21]
1. Clear bit 21 of Port A GPIO In Use Register (GIUS_A)
2. Clear bit 21 of Port A General Purpose Register (GPR_A)
CS [5:4]
Primary function of GPIO Port
A [23:22]
1. Clear bits [23:22] of Port A GPIO In Use Register (GIUS_A)
2. Clear bits [23:22] of Port A General Purpose Register (GPR_A)
CS [3]
Primary function of pin shared
with SDRAM’s CSD1
1. Clear bit 1 (SDCS1_SEL) of Function Muxing Control Register (FMCR)
MC9328MX1 Reference Manual, Rev. 6.1
11-4
Freescale Semiconductor
Typical EIM System Connections
Table 11-3. Pin Configuration (continued)
Pins
Setting
Configuration Procedure
CS [2]
Primary function of pin shared
with SDRAM’s CSD0
1. Clear bit 0 (SDCS0_SEL) of Function Muxing Control Register (FMCR)
CS [1:0]
Not Multiplexed
DTACK
Primary function of GPIO Port
A[17
EB [3:0]
Not Multiplexed
OE
Not Multiplexed
BCLK
Primary function of GPIO Port
A [18]
1. Clear bit 18 of Port A GPIO In Use Register (GIUS_A)
2. Clear bit 18 of Port A General Purpose Register (GPR_A)
LBA
Primary function of GPIO Port
A [19]
1. Clear bit 19 of Port A GPIO In Use Register (GIUS_A)
2. Clear bit 19 of Port A General Purpose Register (GPR_A)
RW
Not Multiplexed
ECB
Primary function of GPIO Port
A [20]
1. Clear bit 17 of Port A GPIO In Use Register (GIUS_A)
2. Clear bit 17 of the Port A General Purpose Register (GPR_A
1. Clear bit 20 of Port A GPIO In Use Register (GIUS_A)
2. Clear bit 20 of Port A General Purpose Register (GPR_A)
11.4 Typical EIM System Connections
The following figures show example connections of the EIM with burst and asynchronous memories:
•
Figure 11-1 illustrates a typical set of EIM interfaces to external memory and peripherals.
•
Figure 11-2 illustrates the EIM interface to two supported external burst flash devices.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
11-5
Typical EIM System Connections
A [31:0]
A [16:0]
CS2
EB [0]
CS
EB [0]
OE
D [31:0]
EB [0]
EB [1]
CS1
RW
RW
D [31:16]
A [19:1]
EB [2]
OE
D [15:0]
A0
CS3
UBS
LBS
WE
RAM
64Kx16
OE
Data [15:0]
Address [18:0]
AMD
Flash
OE 512Kx16
WE
Data [15:0]
RS
E
R’W
ECB
Address [15:0]
CS
CS0
EB [2]
RAM
128Kx8
Data [7:0]
CS
OE
External
Interface
Module
WE
OE
D [31:24]
A [16:1]
EB [1]
Address [16:0]
D [7:0]
ACIA
R/W
Data [7:0]
LBA
BCLK
A0
CS5
CS4
EB [3]
RS
E
RW
D [7:0]
LCD
Control
R/W
Data [7:0]
Figure 11-1. Example of EIM Interface to Memory and Peripherals
MC9328MX1 Reference Manual, Rev. 6.1
11-6
Freescale Semiconductor
Typical EIM System Connections
A [21:2]
A [31:0]
Address [19:0]
LBA
ADV#
CS0
CE#
EB [0]
WE#
OE
OE
BCLK
OE#
AMD
BURST
FLASH
CLK
RDY
ECB
D [31:16]
D [31:0]
DQ [15:0]
1Mx16
External
Interface
Module
A [21:2]
Address [19:0]
ADV#
CS1
CE#
WE#
EB [1]
OE
CS3
BCLK
CS4
OE#
CLK
AMD
BURST
FLASH
RDY
CS5
D [15:0]
DQ [15:0]
1Mx16
A [16:1]
EB [2]
EB [2]
EB [3]
EB [3]
UBS
LBS
CS2
RW
Address [15:0]
CS
RW
RAM
64Kx16
WE
OE
OE
D [15:1]
Data [15:0]
Figure 11-2. Example of EIM Interface to Burst Memory
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
11-7
EIM Functionality
11.5 EIM Functionality
11.5.1 Configurable Bus Sizing
The EIM supports byte, halfword, and word operands, allowing access to 8-bit ports, 16-bit ports, and 32-bit ports.
It does not support misaligned transfers.
The port size is programmable via the DSZ bits in the corresponding chip select control register. In addition, the
portion of the data bus used for transfer to or from an 8-bit port or 16-bit port is programmable via the same bits.
An 8-bit port can reside on external data bus bits D [31:24], D [23:16], D [15:8] or D [7:0]. A 16-bit port can reside
on external data bus bits D [31:16] or D [15:0].
Word access to or from an 8-bit port requires four external bus cycles to complete the transfer. Word access to or
from a 16-bit port requires two external bus cycles to complete the transfer. Half-word access to or from an 8-bit
port requires two external bus cycles to complete the transfer. In the case of a multi-cycle transfer, the lower two
address bits, A [1:0], are incremented appropriately.
The EIM has a data multiplexer that routes the four bytes of the AHB interface data bus to the required positions to
allow proper interfacing to memory and peripherals.
11.5.2 Programmable Output Generation
Unused chip select outputs can be configured to provide a programmable output signal. This functionality is not
provided for the CS [0] output signal. When the CSEN bit is cleared, CS [0] is always inactive. To operate as a
programmable output pin, the corresponding CSEN control bit must be cleared.
11.5.3 Burst Mode Operation
When burst mode is enabled, the EIM attempts to burst read data from as many sequential address locations as
possible, limited only by the length of the burst flash internal page buffer, or the non-sequential nature of the
ARM920T processor code or data stream. The EIM only displays the first address accessed in a burst sequence
unless the page mode emulation (PME) bit is set.
For the first access in a burst sequence, the EIM asserts load burst address (LBA), causing the external burst device
to latch the starting burst address, and then toggles the burst clock (BCLK) for a predefined number of cycles to
latch the first unit of data. Subsequently read data units are burst from the external device in fewer clock cycles,
realizing an overall increase in bus bandwidth.
Burst accesses is terminated by the EIM when it detects that the next ARM920T processor access is not sequential
in nature, or when the external burst device needs additional cycles to retrieve the next requested memory location.
In the latter case, the burst flash device provides an ECB signal to the EIM whenever it must terminate the
on-going burst sequence and initiate a new (long first access) burst sequence.
11.5.4 Burst Clock Divisor
In some cases it is necessary to slow the external bus in relation to the internal bus to allow accesses to burst
devices that have a maximum operating frequency that is lower than the operating frequency of the internal AHB
bus. The internal bus frequency can be divided by 2, 3, or 4 for presentation on the external bus in burst mode
operation.
MC9328MX1 Reference Manual, Rev. 6.1
11-8
Freescale Semiconductor
EIM Functionality
Programming the BCD bits to various values (see Table 11-5, "Chip Select Control Registers Description") affects
two signals on the external bus, LBA (load burst address) and BCLK (burst clock). The LBA signal is asserted
immediately and remains asserted until the first falling edge of the BCLK signal. The BCLK signal runs with a
50% duty cycle until a non-sequential internal request is received or an external ECB signal is recognized.
When programming these bits, ensure that the WSC and DOL fields are coordinated to provide the desired external
bus waveforms. For example, when the BCD bits are programmed to 01, the DOL bits must be programmed to
0001, 0011, 0101, … . When the BCD bits are programmed to 10, the DOL must be programmed to 0010, 0101,
1000, … .
The BCM bit in the EIM configuration register has priority over the BCD bits. When BCM = 1, the BCLK runs at
maximum frequency.
11.5.5 Burst Clock Start
To allow greater flexibility in achieving the minimum number of wait states on burst accesses, the user can
determine when they want the BCLK (burst clock) to start toggling. This allows the BCLK to be skewed from the
point of data capture on the system clock by any number of system clock phases. Use caution when setting these
bits in conjunction with the BCD, WSC, and DOL bits. See the external timing diagrams for some examples of
how to use the BCS, BCD, WSC, and DOL bits together.
11.5.6 Page Mode Emulation
Setting the PME bit causes the EIM to perform burst accesses by emulating page mode operation. The LBA signal
remains asserted for the entire access, the burst clock does not send a signal, and the external address asserts for
each access made. The initial access timing is dictated by the WSC bits and the page mode access timing is dictated
by the DOL bits.
The EIM can take advantage of improved page timing for sequential accesses only. Accesses that are on the page,
however are not sequential in nature, have their timing dictated by the WSC bits. The page size can be set via the
PSZ bits to 4, 8, 16, or 32 words (the word size is determined by the data width of the external memory, such as the
DSZ bits).
11.5.7 Error Conditions
The following conditions cause an error condition to be asserted to the ARM920T processor:
•
Access to a disabled chip select (access to a mapped chip select address space where the CSEN bit in the
corresponding chip select control register is clear)
•
Write access to a write-protected chip select address space (the WP bit in the corresponding chip select
control register is set)
•
User access to a supervisor-protected chip select address space (the SP bit in the corresponding chip select
control register is set)
•
User read or write access to a chip select control register or the EIM configuration register
•
Byte or halfword access to a chip select control register or the EIM configuration register
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
11-9
Programming Model
11.6 Programming Model
The EIM module includes thirteen user-accessible 32-bit registers. There is a common register called the EIM
Configuration Register that contains control bits that configure the EIM for certain operation modes. The other
twelve registers are pairs of control registers for each chip select. The layout of the control register is slightly
different for the CS0 register output because CS [0] does not support the programmable output function. These
registers are accessible only in supervisor mode with word (32-bit) reads and writes.
Complete decoding is not performed, so shadowing can occur with these registers. The user must not attempt to
address these registers at any other address location other than those listed in Table 11-4.
Table 11-4. EIM Module Register Memory Map
Description
Name
Address
Chip Select 0 Upper Control Register
CS0U
0x00220000
Chip Select 0 Lower Control Register
CS0L
0x00220004
Chip Select 1 Upper Control Register
CS1U
0x00220008
Chip Select 1 Lower Control Register
CS1L
0x0022000C
Chip Select 2 Upper Control Register
CS2U
0x00220010
Chip Select 2 Lower Control Register
CS2L
0x00220014
Chip Select 3 Upper Control Register
CS3U
0x00220018
Chip Select 3 Lower Control Register
CS3L
0x0022001C
Chip Select 4 Upper Control Register
CS4U
0x00220020
Chip Select 4 Lower Control Register
CS4L
0x00220024
Chip Select 5 Upper Control Register
CS5U
0x00220028
Chip Select 5 Lower Control Register
CS5L
0x0022002C
EIM Configuration Register
EIM
0x00220030
MC9328MX1 Reference Manual, Rev. 6.1
11-10
Freescale Semiconductor
Programming Model
11.6.1 Chip Select 0 Control Registers
The layout of the Chip Select 0 control registers are slightly different from the other Chip Select control registers
because CS [0] does not support the programmable output function.
The 64 bits of control are divided into two registers, Chip Select 0 Upper Control Register and Chip Select 0 Lower
Control Register.
•
Bits [63:32] are located in Chip Select 0 Upper Control Register.
•
Bits [31:0] are located in Chip Select 0 Lower Control Register.
11.6.1.1 Chip Select 0 Upper Control Register
BIT
63
62
61
60
59
58
BCD
TYPE
Addr
0x00220000
Chip Select 0 Upper Control Register1
CS0U
57
56
55
BCS
54
PSZ
53
52
PME
SYNC
51
50
49
48
DOL
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
38
37
36
35
34
33
32
RESET
0x0000
BIT
47
46
45
44
43
CNC
TYPE
42
41
40
39
WSC
WWS
EDC
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
rw
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
RESET
0x3E00
1For
bit descriptions, see Table 11-5 on page 11-14.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
11-11
Programming Model
11.6.1.2 Chip Select 0 Lower Control Register
BIT
31
30
29
28
27
26
OEA
TYPE
Addr
0x00220004
Chip Select 0 Lower Control Register1
CS0L
25
24
23
22
OEN
21
20
19
18
WEA
17
16
WEN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
CSA
TYPE
11
10
EBC
9
8
7
DSZ
SP
WP
CSEN
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
r
rw
r
r
r
rw
0
0
0
0
1
*
*
*
0
0
0
0
0
0
0
1
RESET
0x0801
1For
bit descriptions, see Table 11-5 on page 11-14.
*Configurable on reset.
11.6.2 Chip Select 1–Chip Select 5 Control Registers
The layout of the control registers for Chip Selects 1 through 5 are identical.
The 64 bits of control per chip select are divided into an Upper and a Lower register.
•
Bits [63:32] are located in Chip Select x Upper Control Register.
•
Bits [31:0] are located in Chip Select x Lower Control Register.
11.6.2.1 Chip Select 1–Chip Select 5 Upper Control Registers
For bit descriptions for all of these registers, see Table 11-5 on page 11-14.
MC9328MX1 Reference Manual, Rev. 6.1
11-12
Freescale Semiconductor
Programming Model
CS1U
CS2U
CS3U
CS4U
CS5U
BIT
Chip Select 1 Upper Control Register
Chip Select 2 Upper Control Register
Chip Select 3 Upper Control Register
Chip Select 4 Upper Control Register
Chip Select 5 Upper Control Register
63
62
61
DTACK_SEL
TYPE
Addr
0x00220008
0x00220010
0x00220018
0x00220020
0x00220028
60
59
58
BCD
57
56
55
BCS
54
PSZ
53
52
PME
SYNC
51
50
49
48
DOL
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
38
37
36
35
34
33
32
RESET
0x0000
BIT
47
46
45
44
43
CNC
TYPE
42
41
40
39
WSC
WWS
EDC
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
11-13
Programming Model
11.6.2.2 Chip Select 1–Chip Select 5 Lower Control Registers
For bit descriptions for Chip Select 1–Chip Select 5 registers, see Table 11-5.
CS1L
CS2L
CS3L
CS4L
CS5L
BIT
Chip Select 1 Lower Control Register
Chip Select 2 Lower Control Register
Chip Select 3 Lower Control Register
Chip Select 4 Lower Control Register
Chip Select 5 Lower Control Register
31
30
29
28
27
26
OEA
TYPE
Addr
0x0022000C
0x00220014
0x0022001C
0x00220024
0x0022002C
25
24
23
22
OEN
21
20
19
18
WEA
17
16
WEN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
PA
CSEN
RESET
0x0000
BIT
15
14
13
12
CSA
TYPE
11
10
EBC
9
8
DSZ
SP
WP
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
r
rw
r
r
rw
rw
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
RESET
0x0802
Table 11-5. Chip Select Control Registers Description
Name
Description
DTACK_SEL
Bit 63
DTACK Select—This bit is used to select the
functionality of the DTACK input signal for CS5 to
support either a generic DTACK signal or the Compact
Flash/PCMCIA wait function. To select the DTACK
functionality on CS5, the WSC bits for CS5 must be set to
111111.
Reserved
Bit 62
Reserved—These bits are reserved and should read 0.
BCD
Bits 61–60
Burst Clock Divisor—Contains the value used to program
the burst clock divisor. See Section 11.5.4, “Burst Clock
Divisor,” for more information on the burst clock divisors.
When the BCM bit is set (BCM = 1) in the EIM configuration
register, BCD is ignored.
Settings
0 = Generic DTACK function
1 = Compact Flash/PCMCIA wait function
00 = Divisor is 1
01 = Divisor is 2
10 = Divisor is 3
11 = Divisor is 4
BCD is cleared by a hardware reset.
MC9328MX1 Reference Manual, Rev. 6.1
11-14
Freescale Semiconductor
Programming Model
Table 11-5. Chip Select Control Registers Description (continued)
Name
Description
Settings
BCS
Bits 59–56
Burst Clock Start—Determines the number of half cycles
after LBA assertion before the first rising edge of BCLK
(burst clock) is seen. A value of 0 results in a half clock
delay, not an immediate assertion. When the BCM bit is set
(BCM = 1) in the EIM configuration register, this overrides
the BCS bits. BCS is cleared by a hardware reset.
0000 = 1 half cycle before BCLK (burst clock)
0001 = 2 half cycles before BCLK (burst
clock)
...
1111 = 16 half cycles before BCLK (burst
clock)
PSZ
Bits 55–54
Page Size—Indicates the number of words (where “word” is
defined by the port size or DSZ bits) in a page in memory.
This ensures that the EIM does not burst past a page
boundary when the PME bit is set.
00 = 4 words in a page
01 = 8 words in a page
10 = 16 words in a page
11 = 32 words in a page
PSZ is cleared by a hardware reset.
PME
Bit 53
Page Mode Emulation—Enables/Disables page mode
emulation in burst mode. When PME is set, the external
address asserts for each piece of data requested.
Additionally, the LBA and BCLK signals behave as they do
when an asynchronous access is performed.
0 = Disables page mode emulation
1 = Enables page mode emulation
PME is cleared by a hardware reset.
SYNC
Bit 52
Synchronous Burst Mode Enable—Enables/Disables
synchronous burst mode. When enabled, the EIM is capable
of interfacing to burst flash devices through additional burst
control signals: BCLK (burst clock), LBA, and ECB. The
sequencing of these additional I/Os is controlled by other
EIM configuration register bit settings as defined below.
0 = Disables synchronous burst mode
1 = Enables synchronous burst mode
SYNC is cleared by a hardware reset.
DOL
Bits 51–48
Data Output Length—Specifies the expected number of
system clock cycles required for burst read data to be valid
on the data bus before it is latched by the EIM. The reset
value specifies that burst data is held for a single system
clock period. As system clock frequencies increase, it may
become necessary to delay sampling the data for multiple
system clock periods to meet burst flash max frequency
specifications and/or EIM data setup time requirements. DOL
has no effect on EIM data latching when SYNC = 0.
0000 = 1system clock delays
0001 = 1system clock delays
0010 = 2system clock delays
0011 = 3system clock delays
...
1111 = 15 system clock delays
DOL is cleared by a hardware reset.
CNC
Bits 47–46
Chip Select Negation Clock Cycles—Specifies the
minimum number of clock cycles a chip select must remain
negated after it is negated.
00 = Minimum negation is 0 clock cycles
01 = Minimum negation is 1 clock cycle
10 = Minimum negation is 2 clock cycles
11 = Minimum negation is 3 clock cycles
CNC has no effect on write accesses when any CSA bit is
set.
CNC is cleared by a hardware reset.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
11-15
Programming Model
Table 11-5. Chip Select Control Registers Description (continued)
Name
WSC
Bits 45–40
Description
Settings
Wait State Control—
For SYNC = 0:
WSC programs the number of wait-states for an access to
the external device connected to the chip select. Table 11-6,
"Chip Select Wait State and Burst Delay Encoding" shows
the encoding of this field. When WWS is cleared, setting:
• WSC = 000000 results in 2 clock transfers
• WSC = 000001 results in 2 clock transfers
• WSC = 001110 results in 15 clock transfers
• WSC = 111110 results in 63 clock transfers
• WSC=111111 selects DTACK input functionality for
CS5
See Table 11-6, "Chip Select Wait State and
Burst Delay Encoding"
For SYNC = 1:
WSC programs the number of system clock cycles required
for the initial access of a burst sequence initiated by the EIM
to an external burst device. See Table 11-6, "Chip Select
Wait State and Burst Delay Encoding" and to the EIM
synchronous burst read timing diagrams for further details.
to, the WSC
WSC is set to 111110 by a hardware reset for CS0.
WSC is cleared by a hardware reset for CS1–CS5.
Reserved
Bit 39
Reserved—This bit is reserved and should read 0.
WWS
Bits 38–36
Write Wait State—Determines whether additional
wait-states are required for write cycles. This is useful for
writing to memories that require additional data setup time.
See Table 11-6, "Chip Select Wait State and
Burst Delay Encoding"
WWS is cleared by a hardware reset.
EDC
Bits 35–32
Extra Dead Cycles—Determines whether idle cycles are
inserted after a read cycle for back-to-back external transfers
to eliminate data bus contention. This is useful for slow
memory and peripherals that use long CS or OE to output
data three-state times. Idle cycles are not inserted for
back-to-back external reads from the same chip select.
0000 = 0 Idle cycles inserted
0001 = 1 Idle cycle inserted
...
1111 = 15 Idle cycles inserted
EDC is cleared by a hardware reset.
MC9328MX1 Reference Manual, Rev. 6.1
11-16
Freescale Semiconductor
Programming Model
Table 11-5. Chip Select Control Registers Description (continued)
Name
OEA
Bits 31–28
Description
OE Assert—Determines when OE is asserted during read
cycles.
For SYNC = 0:
OEA determines the number of half clocks before OE asserts
during a read cycle.
Settings
0000 = 0 half clocks before assertion
0001 = 1 half clock before assertion
...
1111 = 15 half clocks before assertion
For SYNC = 1:
After the initial burst access, OE is asserted continuously for
subsequent burst accesses, and is not affected by OEA (see
burst read timing diagrams for more detail). The behavior of
OE on the initial burst access is the same as when SYNC =
0.
When the EBC bit in the corresponding register is clear, the
EB [3:0] outputs are similarly affected.
The OEA bits do not affect the cycle length.
OEA is cleared by a hardware reset.
OEN
Bits 27–24
OE Negate—Determines when OE is negated during a read
cycle. Setting the SYNC bit (SYNC = 1) overrides OEN and
OE negates at the end of a read access and no sooner.
When EBC in the corresponding register is clear, the EB
[3:0] outputs are similarly affected.
0000 = 0 half clocks before end of access
0001 = 1 half clock before end of access
...
1111 = 15 half clocks before end of access
OEN does not affect the cycle length.
OEN is cleared by a hardware reset.
WEA
Bits 23–20
EB [3:0] Assert—Determines when EB [3:0] is asserted
during write cycles. This is useful to meet data setup time
requirements for slow memories.
0000 = 0 half clocks before assertion
0001 = 1 half clock before assertion
...
1111 = 15 half clocks before assertion
WEA does not affect the cycle length.
WEA is cleared by a hardware reset.
WEN
Bits 19–16
EB [3:0] Negate During Write—Determines when EB [3:0]
outputs are negated during a write cycle. This is useful to
meet data hold time requirements for slow memories.
0000 = 0 half clocks before end of access
0001 = 1 half clock before end of access
...
1111 = 15 half clocks before end of access
WEN does not affect the cycle length.
WEN is cleared by a hardware reset.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
11-17
Programming Model
Table 11-5. Chip Select Control Registers Description (continued)
Name
CSA
Bits 15–12
Description
Chip Select Assert—Determines when chip select is
asserted and negated for devices that require additional
address setup time and additional address/data hold times.
CSA affects only external writes, and is ignored on external
reads.
CSA does not affect the cycle length.
Settings
0000 = 0 clocks before assertion and 0
clocks following negation
0001 = 1 clock before assertion and 1 clock
following negation
...
1111 = 15 clocks before assertion and 15
clocks after negation
CSA is cleared by a hardware reset.
EBC
Bit 11
Enable Byte Control—Indicates the access types that
assert the enable byte outputs (EB [3:0]).
EBC is set by a hardware reset.
DSZ
Bits 10–8
Data Port Size—Defines the width of the external device’s
data port as shown in the table, DSZ Bit Encoding, to the
right. At hardware reset, the value of DSZ is 000 for
CS1– CS5. For CS0, DSZ is mapped based on the value of
the EIM_BOOT_DSZ [2:0] bits. EIM_BOOT_DSZ [2] maps to
DSZ [2], EIM_BOOT_DSZ [1] maps to DSZ [1] and
EIM_BOOT_DSZ [0] maps to DSZ [0].
Reserved
Bit 7
Reserved—This bit is reserved and should read 0.
SP
Bit 6
Supervisor Protect—Prevents accesses to the address
range defined by the corresponding chip select when the
access is attempted in the User mode of ARM9 core
operation.
SPI is cleared by a hardware reset.
Reserved
Bit 5
Reserved—This bit is reserved and should read 0.
WP
Bit 4
Write Protect—Prevents writes to the address range
defined by the corresponding chip select.
WP is cleared by a hardware reset.
Reserved
Bits 3–2
0 = Both read and write accesses assert the
EB [3:0] outputs, thus configuring the
access as byte enables
1 = Only write accesses assert the EB [3:0]
outputs, thus configuring the access as
byte write enables; the EB [3:0] outputs
are configured as byte write enables for
accesses to dual x16 or quad x8
memories
000 = 8-bit port, resides on D [31:24] pins
001 = 8-bit port, resides on D [23:16] pins
010 = 8-bit port, resides on D [15:8] pins
011 = 8-bit port, resides on D [7:0] pins
100 = 16-bit port, resides on D [31:16] pins
101 = 16-bit port, resides on D [15:0] pins
11x = 32-bit port
0 = User mode accesses are allowed in the
range of chip select
1 = User mode accesses are prohibited;
attempts to access an address mapped
by this chip select in User mode results
in a TEA to the ARM9 core and no
assertion of the chip select output
0 = Writes are allowed in the range of chip
select
1 = Writes are prohibited; attempts to write to
an address mapped by this chip select
result in a TEA to the ARM9 core and no
assertion of the chip select output
Reserved—These bits are reserved and should read 0.
MC9328MX1 Reference Manual, Rev. 6.1
11-18
Freescale Semiconductor
Programming Model
Table 11-5. Chip Select Control Registers Description (continued)
Name
PA
Bit 1
Description
Settings
Pin Assert—Controls the chip select pin when it is operating
as a programmable output pin (when the CSEN bit is clear).
0 = Brings the chip select output to logic-low
1 = Brings the chip select output to logic-high
PA is not available (reserved) for CS0.
PA is set by a hardware reset for CS1–CS5.
CSEN
Bit 0
Chip Select Enable—Controls the operation of the chip
select pin.
Except for CS0, CSEN is cleared by reset, disabling the chip
select output pin. When enabled, the PA control bit is
ignored. CSEN in the CS0 control register is set at reset to
allow CS0 to select from an external boot ROM.
CSEN is set by a hardware reset for CS0.
CSEN is cleared by a hardware reset for CS1–CS5.
0 = Chip select function is disabled; attempts
to access an address mapped by this
chip select results in an error and no
assertion of the chip select output
When disabled, the pin is a general
purpose output controlled by the value
of PA control bit. When CSEN in the
CS0 control register is clear, CS0 is
inactive.
1 = Chip select is enabled, and is asserted
when presented with a valid AHB
access.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
11-19
Programming Model
11.6.3 EIM Configuration Register
Table 11-6. Chip Select Wait State and Burst Delay Encoding
Number of Wait-States
WSC [5:0]
WWS = 0
WWS = 1
WWS = 7
Read Access
Write Access
Read Access
Write Access
Read Access
Write Access
000000
1
1
1
1
1
7
000001
1
1
1
2
1
8
000010
2
2
2
3
2
9
000011
3
3
3
4
3
10
000100
4
4
4
5
4
11
000101
5
5
5
6
5
12
000110
6
6
6
7
6
13
000111
7
7
7
8
7
14
001000
8
8
8
9
8
15
001001
9
9
9
10
9
16
001010
10
10
10
11
10
17
001011
11
11
11
12
11
18
001100
12
12
12
13
12
19
001101
13
13
13
14
13
20
001110
14
14
14
15
14
21
001111
15
15
15
16
15
22
010000
16
16
16
17
16
23
010001
17
17
17
18
17
24
010010
18
18
18
19
18
25
010011
19
19
19
20
19
26
010100
20
20
20
21
20
27
010101
21
21
21
22
21
28
010110
22
22
22
23
22
29
010111
23
23
23
24
23
30
011000
24
24
24
25
24
31
011001
25
25
25
26
25
32
011010
26
26
26
27
26
33
011011
27
27
27
28
27
34
011100
28
28
28
29
28
35
011101
29
29
29
30
29
36
011110
30
30
30
31
30
37
MC9328MX1 Reference Manual, Rev. 6.1
11-20
Freescale Semiconductor
Programming Model
Table 11-6. Chip Select Wait State and Burst Delay Encoding (continued)
Number of Wait-States
WSC [5:0]
WWS = 0
WWS = 1
WWS = 7
Read Access
Write Access
Read Access
Write Access
Read Access
Write Access
011111
31
31
31
32
31
38
100000
32
32
32
33
32
39
100001
33
33
33
34
33
40
100010
34
34
34
35
34
41
100011
35
35
35
36
35
42
100100
36
36
36
37
36
43
100101
37
37
37
38
37
44
100110
38
38
38
39
38
45
100111
39
39
39
40
39
46
101000
40
40
40
41
40
47
101001
41
41
41
42
41
48
101010
42
42
42
43
42
49
101011
43
43
43
44
43
50
101100
44
44
44
45
44
51
101101
45
45
45
46
45
52
101110
46
46
46
47
46
53
101111
47
47
47
48
47
54
110000
48
48
48
49
48
55
110001
49
49
49
50
49
56
110010
50
50
50
51
50
57
110011
51
51
51
52
51
58
110100
52
52
52
53
52
59
110101
53
53
53
54
53
60
110110
54
54
54
55
54
61
110111
55
55
55
56
55
62
111000
56
56
56
57
56
63
111001
57
57
57
58
57
63
111010
58
58
58
59
58
63
111011
59
59
59
60
59
63
111100
60
60
60
61
60
63
111101
61
61
61
62
61
63
111110
62
62
62
63
62
63
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
11-21
Programming Model
Table 11-6. Chip Select Wait State and Burst Delay Encoding (continued)
Number of Wait-States
WSC [5:0]
WWS = 0
WWS = 1
WWS = 7
Read Access
Write Access
Read Access
Write Access
Read Access
Write Access
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
111111
The EIM Configuration Register contains the bit that controls the operation of the burst clock.
EIM
Addr
0x00220030
EIM Configuration Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
BCM
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 11-7. EIM Configuration Register Description
Name
Description
Settings
Reserved
Bits 31–3
Reserved—These bits are reserved and should read 0.
BCM
Bit 2
Burst Clock Mode—Selects the burst clock
mode of operation.
BCM is cleared by a hardware reset.
Reserved
Bits 1–0
0 = The burst clock runs only when accessing a chip select
range with the SYNC bit set. When the burst clock is not
running, it remains in a logic 0 state; when the burst clock
is running, it is configured by the BCD and BCS bits in the
chip select control register.
1 = The burst clock runs all the time (independent of chip
select accesses).
Reserved—These bits are reserved and should read 0.
MC9328MX1 Reference Manual, Rev. 6.1
11-22
Freescale Semiconductor
Chapter 12
Phase-Locked Loop and Clock Controller
12.1 Introduction
To produce the wide range of on-chip clock frequencies required by the MC9328MX1, the core clock generator
uses a two-stage phase locked loop (PLL). The first stage is a premultiplier PLL. If the input crystal frequency is
32.768 kHz, the premultiplier multiplies it by a factor of 512 to 16.78 MHz. If the input crystal frequency is 32
kHz, the premultiplier multiplies it to 16.384 MHz. The second stage is a digital PLL (DPLL) that produces an
output frequency determined by system requirements and used throughout the entire system. The two DPLLs
(MCU PLL and System PLL) use digital and mixed analog/digital chips to provide clock generation for wireless
communication and other applications. Power management of the MC9328MX1 is accomplished by controlling
the operation of the premultiplier, MCU PLL and System PLL units, as shown in Figure 12-1 on page 12-2.
12.2 Clock Sources
The distribution of clocks in the MC9328MX1 is shown in Figure 12-1 on page 12-2. Clock signal name
definitions are provided in Table 12-1 on page 12-2.
The 32kHz clock source can be configured in two ways. The user can place a 32 kHz or 32.768 kHz crystal across
EXTAL32K and XTAL32K with appropriate load capacitors. Alternately, an external 32 kHz or 32.768 kHz
oscillator can be used; the signal is AC coupled into EXTAL32K and XTAL32K is floated.
The 16 MHz external crystal oscillator is not recommended for use and must be disabled using the CSCR register.
Note that the 32 kHz oscillator must be used and satisfies all system requirements.
12.2.1 Low Frequency Clock Source
The MC9328MX1 can use either a 32 kHz or a 32.768 kHz crystal as the external low frequency source.
Throughout this chapter, the low frequency crystal is referred to as the 32 kHz crystal. The signal from the external
32 kHz crystal is the source of the CLK32 signal that is sent to the real time clock (RTC). The output of the 32 kHz
crystal is also input to the premultiplier PLL to produce the 16.78 MHz signal that is input to the MCU PLL (it is
16.78 MHz if a 32.768 kHz crystal is used). The output of the MCU PLL is sent to the prescaler (PRESC) module
to produce the fast clock (FCLK) signal for the ARMTDMI core.
The 16.384 MHz output of the premultiplier PLL also can be a source for the System PLL by setting the
System_SEL bit in the Clock Source Control Register to produce all of the system clocks from a single 32 kHz
crystal oscillator. See Section 12.3.1, “DPLL Phase and Frequency Jitter,” for more detailed information on phase
and frequency jitter specifications using this configuration.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
12-1
Clock Sources
12.2.2 High Frequency Clock Source
The System PLL produces the USBPLLCLK signal that is the source for the following clock signals:
•
CLK48M—for the USB
•
HCLK and BCLK—HCLK is the MC9328MX1 system clock and BCLK goes to the ARMTDMI core.
•
Peripheral Clocks 1, 2, and 3—The peripheral clocks (PERCLK) provide clock signals to both integrated
and external peripherals.
There are two possible external high frequency clock sources for the System PLL—an external 16 MHz oscillator
or the Bluetooth reference clock signal. The source is selected by the CLK16_SEL bit in the Clock Source Control
Register.
OSC32
OSC_EN
OSC16
0
RFBTCLK16
CLK16M
CLK32
SYNC Logic
RTC
HCLK
1
System
PLL
1
System PLLCLK
USBDIV
CLK48M
USB
0
CLK16_SEL
System_SEL
FCLK
PRESC
BCLK
MCU PLL
BCLKDIV
PREMULT
HCLK
System
PERCLK1
PCLKDIV1
PERCLK2
PCLKDIV2
OSC32
XTALOSC
CPU
CLK32
Internal
Peripherals
PERCLK3
PCLKDIV3
000
SPLLEN
PLL Stop &
Wake-Up Logic
HCLK
CLK48M
CLK16M
PREMCLK
FCLK
MPLLEN
Note: PREMCLK is the signal name after
the System_SEL controlled MUX output.
PREMCLK i th
i
lt
CLKO
CLKO
CLK0SEL [2:0]
ft
th S t
SEL
t ll d MUX
t
t
Figure 12-1. Clock Controller Module
S
Table 12-1. Clock Controller Module Signal Descriptions
Signal Names
I/O
Description
Default
RFBTCLK16
I
16 MHz clock input from an external Bluetooth RF module through the internal BTA
module.
Stop
CLK48M
O
Continuous 48 MHz clock output when System PLL is enabled or when external
48 MHz clock is selected.
Run
FCLK
O
Fast clock (FCLK) output to the CPU.
Run
MC9328MX1 Reference Manual, Rev. 6.1
12-2
Freescale Semiconductor
DPLL Output Frequency Calculation
Table 12-1. Clock Controller Module Signal Descriptions (continued)
Signal Names
I/O
Description
Default
HCLK
O
System clock (HCLK) output to the CPU (as BCLK) and to the system. This is a
continuous clock (when the system is not in sleep mode) normally used for bus
non-stop system logic (such as bus arbiter or interrupt controller) when the system is
running.
Run
CLKO
O
Output internal clock to the CLKO pin.
Run
PERCLK1, 2, 3
O
Output clocks used by the peripheral modules.
Run
12.3 DPLL Output Frequency Calculation
The DPLL (both the MCU PLL and System PLL) produce a high frequency clock that exhibits both a low
frequency jitter and a low phase jitter. The DPLL output clock frequency (fdpll) is determined by the
Equation 12-1:
fdpll = 2fref • MFI + MFN / (MFD+1)
PD + 1
Eqn. 12-1
where:
•
fref is the reference frequency
•
MFI is an integer part of a multiplication factor (MF)
•
MFN is the numerator and MFD is the denominator of the MF
•
PD is the predivider factor
12.3.1 DPLL Phase and Frequency Jitter
Spectral purity of the DPLL output clock is characterized by both phase and frequency jitter. Phase jitter is a
measure of clock phase fluctuations relative to an ideal clock phase. The output clock also can be skewed relative
to the reference clock. Frequency jitter is a measure of clock period fluctuations relative to an ideal clock period.
Frequency jitter is calculated as a difference of phase jitter values for adjacent clocks.
DPLL jitter requirements vary according to system configuration. For many stand-alone processors and
asynchronous multiprocessor applications, only the frequency jitter value is important (slow phase jitter and clock
skew do not affect system performance). In these systems, it is not necessary to adjust the output clock phase with
an input clock phase. The clock generation mode in which slow phase fluctuations are permissible is called
Frequency Only Lock (FOL) mode.
Phase error is sometimes important for synchronous applications and sampling analog-to-digital (A/D) and
digital-to-analog (D/A) precision converters. The DPLL mode providing minimum phase jitter and skew
elimination is Frequency and Phase Lock (FPL) mode. The DPLL mode is user selectable.
The DPLL communicates with the clock module. This block contains a control register and provides an interface
between the DPLL and the ARMTDMI core.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
12-3
MC9328MX1 Power Management
12.4 MC9328MX1 Power Management
The operation of the PLL and clock controller at different stages of power management is described in the
following sections.
12.4.1 PLL Operation at Power-Up
The crystal oscillator begins oscillating within several hundred milliseconds of initial power-up. While reset
remains asserted, the PLL begins the lockup sequence and locks 1 ms after the crystal oscillator becomes stable.
After lockup occurs, the system clock is available at the default System PLL output frequency of 96 MHz (when a
32 kHz crystal is used).
12.4.2 PLL Operation at Wake-Up
When the device is awakened from stop mode by a wake-up event, the DPLL locks within 300 μs. The crystal
oscillator is always on after initial power-up, so crystal startup time is not a factor. The PLL output clock starts
operating as soon as it achieves lock.
12.4.3 ARM920T Processor Low-Power Modes
The MC9328MX1 provides two power saving modes, doze and stop:
•
In stop mode, the MCU PLL and the System PLL are shut down and only the 32 kHz clock is running.
•
In doze mode, the CPU executes a wait for interrupt instruction.
These modes are controlled by the clock control logic and a sequence of CPU instructions. Most of the peripheral
modules can enable or disable the incoming clock signal (PERCLK 1, 2, or 3) through clock gating circuitry from
the peripheral bus.
12.4.4 SDRAM Power Modes
When the SDRAM controller (SDRAMC) is enabled, the external SDRAM operates in distributed-refresh mode or
in self-refresh mode (as shown in Table 12-2). The SDRAM wake-up latency is approximately 20 system clock
cycles (HCLK). The SDRAMC can wake up from self-refresh mode when it is in a SDRAM cycle. In doze mode,
the SDRAM enters self-refresh mode. When a bus cycle accesses the SDRAM or SyncFlash, the controller wakes
up and completes the bus cycle, then returns to self-refresh mode.
Table 12-2. SDRAM/SyncFlash Operation During Power Modes
SDRAM
Run
Doze
Stop
SDRAM
Distributed-refresh
Self-refresh
Self-refresh
SyncFlash
Run
Low-power mode
Deep power-down mode
12.4.5 Power Management in the Clock Controller
Power management in the MC9328MX1 is achieved by controlling the duty cycles of the clock system efficiently.
The clocking control scheme is shown in Table 12-3.
MC9328MX1 Reference Manual, Rev. 6.1
12-4
Freescale Semiconductor
Programming Model
Table 12-3. Power Management in the Clock Controller
Device/Signal
System PLL
Shut-Down Conditions
Wake-Up Conditions
When 0 is written to the SPEN bit and the PLL shut-down count
times out (for details see the SD_CNT settings in Table 12-5 on
page 12-6).
When IRQ or FIQ is asserted.
When 0 is written to the MPEN bit.
When IRQ or FIQ is asserted, or 1 is
written to the MPEN bit.
Premultiplier
Same as System PLL.
Same as System PLL.
CLK32
Continuously running.
Continuously running.
MCU PLL
12.5 Programming Model
The PLL and Clock Controller module includes six user-accessible 32-bit registers. Table 12-4 summarizes these
registers and their addresses.
Table 12-4. PLL and Clock Controller Module Register Memory Map
Description
Name
Address
Clock Source Control Register
CSCR
0x0021B000
Peripheral Clock Divider Register
PCDR
0x0021B020
MCU PLL Control Register 0
MPCTL0
0x0021B004
MCU PLL and System Clock Control Register 1
MPCTL1
0x0021B008
System PLL Control Register 0
SPCTL0
0x0021B00C
System PLL Control Register 1
SPCTL1
0x0021B010
12.5.1 Clock Source Control Register
This register controls the various clock sources to the internal modules of the MC9328MX1. It allows the bypass of
the 32 kHz derived clock source to the System PLL when the design requires clock signals with greater frequency
and phase jitter performance than the internal PLL using the 32 kHz clock source provides.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
12-5
Programming Model
CSCR
Addr
0x0021B000
Clock Source Control Register
BIT
31
30
29
28
CLKO_SEL
TYPE
27
26
USB_DIV
25
24
23
SD_CNT
22
21
SPLL_
RESTART
MPLL_
RESTART
20
19
18
17
16
CLK16
_SEL
OSC
_EN
System
_SEL
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
r
r
rw
rw
rw
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
SPEN
MPEN
RESET
0x0F00
BIT
15
14
13
PRESC
TYPE
12
11
10
9
8
7
BCLK_DIV
rw
r
rw
rw
rw
rw
r
r
r
r
r
r
r
r
rw
rw
1
0
1
0
1
1
0
0
0
0
0
0
0
0
1
1
RESET
0xAC03
Table 12-5. Clock Source Control Register Description
Name
Description
Settings
CLKO_SEL
Bits 31–29
CLKO Select—Selects the clock signal source that is
output on the CLKO pin.
000 = PERCLK1
001 = HCLK
010 = CLK48M
011 = CLK16M
100 = PREMCLK
101 = FCLK
USB_DIV
Bits 28–26
USB Divider—Contains the integer divider value used to
generate the CLK48M signal for the USB modules.
000 = System PLL clock divide by 1
001 = System PLL clock divide by 2
.
.
.
111 = System PLL clock divide by 8
SD_CNT
Bits 25–24
Shut-Down Control—Contains the value that sets the
duration of System PLL clock output after 0 is written to
the SPEN bit. The power controller requests the bus
before System PLL shutdown. Any unmasked interrupt
event enables the System PLL.
00 = System PLL shuts down after next
rising edge of CLK32 is detected and the
current bus cycle is completed. A
minimum of 16 HCLK cycles is
guaranteed from writing
¡°0¡± to SPEN
bit.
01 = System PLL shuts down after the second
rising edge of CLK32 is detected.
10 = System PLL shuts down after the third
rising edge of CLK32 is detected.
11 = System PLL shuts down after forth rising
edge of CLK32 is detected.
Reserved
Bit 23
Reserved—This bit is reserved and should read 0.
MC9328MX1 Reference Manual, Rev. 6.1
12-6
Freescale Semiconductor
Programming Model
Table 12-5. Clock Source Control Register Description (continued)
Name
Description
Settings
SPLL_
RESTART
Bit 22
SPLL Restart—Restarts System PLL at new assigned
frequency. SPLL_RESTART self-clears after 1 (min) or 2
(max) cycles of CLK32.
0 = No Effect
1 = Restarts System PLL at new frequency
MPLL_
RESTART
Bit 21
MPLL Restart—Restarts the MCU PLL at a new assigned
frequency. MPLL_RESTART self-clears after 1 (min) or 2
(max) cycles of CLK32.
0 = No Effect
1 = Restarts MCU PLL at new frequency
Reserved
Bits 20–19
Reserved—These bits are reserved and should read 0.
CLK16_SEL
Bit 18
CLK16 Select—Selects the clock source of the 16 MHz
clock. When set, RFBTCLK16 is selected. When cleared,
the 16 MHz clock from OSC16 is selected.
0 = Selects the external 16 MHz oscillator
source
1 = Selects the Bluetooth reference clock
RFBTCLK16
OSC_EN
Bit 17
Oscillator Enable—Enables the 16 MHz oscillator circuit
when set (available when using an external crystal input).
When clear, the oscillator circuit control is disabled which
bypasses the oscillator circuit when using external clock
input. This oscillator is not recommended for use.
0 = Disable the external 16 MHz oscillator
circuit (Recommended)
1 = Enable the external 16 MHz oscillator circuit
System_SEL
Bit 16
System Select—Selects the clock source of the System
PLL input. When set, the external high frequency clock
input is selected.
0 = Clock source is the internal premultiplier
1 = Clock source is the external high frequency
clock
PRESC
Bit 15
Prescaler—Defines the MPU PLL clock prescaler.
0 = Prescaler divides by 1
1 = Prescaler divides by 2
Reserved
Bit 14
Reserved—This bit is reserved and should read 0.
BCLK_DIV
Bits 13–10
BClock Divider—Contains the 4-bit integer divider values
for the generation of the BCLK and HCLK.
Reserved
Bits 9–2
Reserved—These bits are reserved and should read 0.
SPEN
Bit 1
System PLL Enable—Enables/Disables the System PLL.
When software writes 0 to SPEN, the System PLL shuts
down after SDCNT times out. SPEN sets automatically
when SPLLEN asserts, and on system reset.
0 = System PLL disabled
1 = System PLL enabled
MPEN
Bit 0
MCU PLL Enable—Enables/Disables the MCU PLL.
When cleared, the MCU PLL is disabled. When software
writes 0 to MPEN, the PLL shuts down immediately.
MPEN sets automatically when MPLLEN asserts, and on
system reset.
0 = MCU PLL disabled
1 = MCU PLL enabled
0000 = System PLLCLK divided by 1
0001 = System PLLCLK divided by 2
...
1111 = System PLLCLK divided by 16
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
12-7
Programming Model
12.5.2 Peripheral Clock Divider Register
Each peripheral module in the MC9328MX1 uses clock signals from one of the three clock sources shown in
Table 12-6. The three peripheral clock dividers (PCLKDIV1, PCLKDIV2, PCLKDIV3) provide flexible clock
configuration capability so that a minimum set of clock frequencies can satisfy a large group of modules to achieve
better power efficiency.
Table 12-6. Clock Sources for Peripherals
Clock Source
PERCLK1
UART1, UART2, Timer1, Timer2, PWM
PERCLK2
ASP, LCD, SD, SIM, SPI 1, SPI 2
PERCLK3
SSI
HCLK
SDRAM, CSI, Memory Stick, I2C, DMA
PCDR
BIT
Peripheral
Addr
0x0021B020
Peripheral Clock Divider Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PCLK_DIV3
TYPE
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
7
6
5
4
3
2
1
0
RESET
0x000B
BIT
15
14
13
12
11
10
9
8
PCLK_DIV2
TYPE
PCLK_DIV1
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
1
0
1
1
1
0
1
1
RESET
0x00BB
Table 12-7. Peripheral Clock Divider Register Description
Name
Description
Reserved
Bits 31–23
Reserved—These bits are reserved and should read 0.
PCLK_DIV3
Bits 22–16
Peripheral Clock Divider 3—Contains the 7-bit integer divider that produces
the PERCLK3 clock signal for the peripherals. The input to the PCLK_DIV3
divider circuit is System PLLCLK.
Reserved
Bits 15–8
Reserved—These bits are reserved and should read 0.
Settings
0000000 = Divide by 1
0000001 = Divide by 2
…
1111111 = Divide by 128
MC9328MX1 Reference Manual, Rev. 6.1
12-8
Freescale Semiconductor
Programming Model
Table 12-7. Peripheral Clock Divider Register Description (continued)
Name
Description
Settings
PCLK_DIV2
Bits 7–4
Peripheral Clock Divider 2—Contains the 4-bit integer divider that produces
the PERCLK2 clock signal for the peripherals. The input to the PCLK_DIV2
divider circuit is System PLLCLK.
0000 = Divide by 1
0001 = Divide by 2
…
1111 = Divide by 16
PCLK_DIV1
Bits 3–0
Peripheral Clock Divider 1—Contains the 4-bit integer divider that produces
the PERCLK1 clock signal for the peripherals. The input to the PCLK_DIV1
divider circuit is System PLLCLK.
0000 = Divide by 1
0001 = Divide by 2
…
1111 = Divide by 16
12.5.3 Programming Digital Phase Locked Loops
There are two DPLLs in the MC9328MX1—the MCU PLL and the System PLL. The MCU PLL primarily
generates FCLK to the CPU, and the System PLL derives all system clocks to the entire MC9328MX1 and
generates clocks that produce the programmable frequency range required by modules such as the USB, UARTs,
and SSI.
The MCU PLL derives the ARM920T processor’s CPU clock FCLK, and the System PLL derives the ARM920T
processor’s CPU clock BCLK, as well as the system clocks PERCLK 1, 2, and 3, and HCLK. The MCU PLL
frequency is determined by the speed requirement of the ARM920T processor. The recommended settings for both
MCU PLL and System PLL, which produces the least amount of signal jitter, are shown in Table 12-8.
Table 12-8. Sample Frequency Table
Premultiplier Input
Crystal Frequency
PLL Input Frequency
(Premultiplier Output)
PD
MFD
MFI
MFN
PLL Output
Frequency
32 kHz
16.384 MHz
0
63
5
55
192 MHz
12.5.3.1 MCU PLL Control Register 0
The MCU PLL Control Register 0 (MPCTL0) is a 32-bit register that controls the operation of the MCU PLL. The
MPCTL0 control bits are described in the following sections. A delay of 56 FCLK cycles (about 10–30 FCLK
cycles for MCU PLL controller plus 2–26 FCLK cycles are necessary to get EDRAM_IDLE and SDRAM_IDLE
signals) is required between two write accesses to MPCTL0 register. The following is a procedure for changing the
MCU PLL settings:
1. Program the desired values of PD, MFD, MFI, and MFN into the MPCTL0.
2. Set the MPLL_RESTART bit in the CSCR (it will self-clear).
3. New PLL settings will take place.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
12-9
Programming Model
MPCTL0
BIT
Addr
0x0021B004
MCU PLL Control Register 0
31
30
29
28
27
26
25
24
23
22
21
PD
TYPE
20
19
18
17
16
MFD
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
7
6
5
4
3
2
1
0
RESET
0x003F
BIT
15
14
13
12
11
10
9
8
MFI
TYPE
MFN
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
1
0
1
0
0
0
0
1
1
0
1
1
1
RESET
0x1437
Table 12-9. MCU PLL Control Register 0 Description
Name
Description
Settings
Reserved
Bits 31–30
Reserved—These bits are reserved and should read 0.
PD
Bits 29–26
Predivider Factor—Defines the predivider factor (PD) applied to the PLL input
frequency. PD is an integer between 0 and 15 (inclusive). PD is chosen to ensure
that the resulting output frequency remains within the specified range. When a new
value is written into PD bits, the PLL loses its lock; after a time delay, the PLL
re-locks. The output of the MCU PLL is determined by Equation 12-1.
0000 = 0
0001 = 1
…
1111 = 15
MFD
Bits 25–16
Multiplication Factor (Denominator Part)—Defines the denominator part of the
BRM value for the MF. When a new value is written into the MFD bits, the PLL loses
its lock; after a time delay, the PLL re-locks.
0x000 = Reserved
0x001 = 1
…
0x3FF = 1023
Reserved
Bits 15–14
Reserved—These bits are reserved and should read 0.
MFI
Bits 13–10
Multiplication Factor (Integer)—Defines the integer part of the BRM value for the
MF. The MFI is encoded so that MFI < 5 results in MFI = 5. When a new value is
written into the MFI bits, the PLL loses its lock: after a time delay, the PLL re-locks.
The VCO oscillates at a frequency determined by Equation 12-1. Where PD is the
division factor of the predivider, MFI is the integer part of the total MF, MFN is the
numerator of the fractional part of the MF, and MFD is its denominator part. The MF
is chosen to ensure that the resulting VCO output frequency remains within the
specified range.
0000–0101 = 5
0110 = 6
...
1111 = 15
MFN
Bits 9–0
Multiplication Factor (Numerator)—Defines the numerator of the BRM value for
the MF. When a new value is written into the MFN bits, the PLL loses its lock; after
a time delay, the PLL re-locks.
0x000 = 0
0x001 = 1
...
0x3FE = 1022
0x3FF = Reserved
MC9328MX1 Reference Manual, Rev. 6.1
12-10
Freescale Semiconductor
Programming Model
12.5.3.2 MCU PLL and System Clock Control Register 1
The MCU PLL and System Clock Control Register 1 (MPCTL1) is a 32-bit register that directs the operation of the
on-chip MCU PLL. The MPCTL1 control bits are described in Table 12-10.
MPCTL1
Addr
0x0021B008
MCU PLL and System Clock Control Register 1
BIT
31
30 29
TYPE
r
r
0
0
28
27
26
25
24
23
22
21
20
19
18
17
16
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14 13
12
11
10
9
8
7
BRMO
TYPE
r
r
r
r
r
r
r
r
r
rw
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 12-10. MCU PLL and System Clock Control Register 1 Description
Name
Description
Reserved
Bits 31–7
Reserved—These bits are reserved and should read 0.
BRMO
Bit 6
BRM Order—Controls the BRM order. The first order BRM is used if a MF fractional
part is both more than 1/10 and less than 9/10. In other cases, the second order
BRM is used. The BRMO bit is cleared by a hardware reset. A delay of reference
cycles is required between two write accesses to BRMO.
Reserved
Bits 5–0
Reserved—These bits are reserved and should read 0.
Settings
0 = BRM contains
first order
1 = BRM contains
second order
12.5.4 Generation of 48 MHz Clocks
The USB interface clock (CLK48M) is used internally by the USB module. Its frequency is set to 48 MHz using
the PLL control registers assuming a default input clock frequency 16.384 MHz. This input clock frequency
assumes a 32 kHz crystal input.
The predivider/multiplier output depends on the input clock frequency as shown in Table 12-11.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
12-11
Programming Model
Table 12-11. System PLL Multiplier Factor
Premultiplier Input
Crystal Frequency
32 kHz
PLL Input Frequency
(Premultiplier Output)
PD
MFD
MFI
MFN
PLL Output
Frequency
USBDIV
1
63
5
55
96 MHz
2
16.384 MHz
USB Clock
Frequency
48 MHz
The default setting exception is USB_DIV. The user must program this to 001.
12.5.4.1 System PLL Control Register 0
The System PLL Control Register 0 (SPCTL0) is a 32-bit register that controls the operation of the System PLL.
The SPCTL0 control bits are described in the following sections. A delay of 30 System PLLCLK cycles is required
between two write accesses to SPCTL0 register. The following is a procedure for changing the System PLL
settings:
1. Program the desired values of PD, MFD, MFI, and MFN into the SPCTL0.
2. Set the SPLL_RESTART bit in the CSCR (it will self-clear).
3. New PLL settings will take place.
SPCTL0
BIT
31
30
29
28
27
26
25
24
23
22
21
PD
TYPE
Addr
0x0021B00C
System PLL Control Register 0
20
19
18
17
16
MFD
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
7
6
5
4
3
2
1
0
RESET
0x043F
BIT
15
14
13
12
11
10
9
8
MFI
TYPE
MFN
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
1
0
1
0
0
0
0
1
1
0
1
1
1
RESET
0x1437
Table 12-12. System PLL Control Register 0 Description
Name
Description
Settings
Reserved
Bits 31–30
Reserved—These bits are reserved and should read 0.
PD
Bits 29–26
Predivider Factor—Defines the predivider factor (PD) that is applied to the PLL input
frequency. PD is an integer between 0 and 15 (inclusive). The System PLL oscillates at a
frequency determined by Equation 12-1. The PD is chosen to ensure that the resulting
VCO output frequency remains within the specified range. When a new value is written
into the PD bits, the PLL loses its lock: after a time delay, the PLL re-locks.
0000 = 0
0001 = 1
…
1111 = 15
MC9328MX1 Reference Manual, Rev. 6.1
12-12
Freescale Semiconductor
Programming Model
Table 12-12. System PLL Control Register 0 Description (continued)
Name
Description
Settings
MFD
Bits 25–16
Multiplication Factor (Denominator Part)—Defines the denominator part of the BRM
value for the MF. When a new value is written into the MFD9–MFD0 bits, the PLL loses
its lock: after a time delay, the PLL re-locks.
0x000 = Reserved
0x001 = 1
…
0x3FF = 1023
Reserved
Bits 15–14
Reserved—These bits are reserved and should read 0.
MFI
Bits 13–10
Multiplication Factor (Integer Part)—Defines the integer part of the BRM value for the
MF. The MFI is decoded so that MFI < 5 results in MFI = 5.
The System PLL oscillates at a frequency determined by Equation 12-1.
Where PD is the division factor of the predivider, MFI is the integer part of the total MF,
MFN is the numerator of the fractional part of the MF, and MFD is the denominator part of
the MF. The MF is chosen to ensure that the resulting VCO output frequency remains
within the specified range. When a new value is written into the MFI bits, the PLL loses its
lock; after a time delay, the PLL re-locks.
0000–0101 = 5
0110 = 6
...
1111 = 15
MFN
Bits 9–0
Multiplication Factor (Numerator Part)—Defines the numerator part of the BRM value
for the MF. When a new value is written into the MFN bits, the PLL loses its lock; after a
time delay, the PLL re-locks.
0x000 = 0
0x001 = 1
...
0x3FE = 1022
0x3FF = Reserved
12.5.4.2 System PLL Control Register 1
The System PLL control register 1 (SPCTL1) is a 32-bit read/write register in the MCU memory map that directs
the operation of the System PLL. The SPCTL1 control bits are described in this section.
SPCTL1
Addr
0x0021B010
System PLL Control Register 1
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
LF
TYPE
6
BRMO
rw
r
r
r
r
r
r
r
r
rw
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
12-13
Programming Model
Table 12-13. System PLL Control Register 1 Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
LF
Bit 15
Lock Flag—Indicates whether the System PLL is locked. When set, the
System PLL clock output is valid. When cleared, the System PLL clock
output remains at logic high.
Reserved
Bits 14–7
Reserved—These bits are reserved and should read 0.
BRMO
Bit 6
BRM Order Bit—Controls the BRM order. The first order BRM is used if a
MF fractional part is both more than 1/10 and less than 9/10. In other cases,
the second order BRM is used. The BRMO bit is cleared by a hardware
reset.
Reserved
Bits 5–0
Reserved—These bits are reserved and should read 0.
Settings
0 = System PLL is not locked
1 = System PLL is locked
0 = BRM has first order
1 = BRM has second order
MC9328MX1 Reference Manual, Rev. 6.1
12-14
Freescale Semiconductor
Chapter 13
DMA Controller
The Direct Memory Access Controller (DMAC) of the MC9328MX1 provides eleven channels supporting linear
memory, 2D memory, FIFO and end-of-burst enable FIFO transfers to provide support for a wide variety of DMA
operations.
13.1 Features
The MC9328MX1 DMAC features are:
•
Eleven channels support linear memory, FIFO, and end-of-burst enable FIFO for both source and
destination.
•
Any one of the eleven channels can be configured to support 2D memory.
•
Increment, decrement, and no-change support for source and destination addresses.
•
Each channel is configurable to response to any of the 32 DMA request signals.
•
Supports 8, 16, or 32-bit FIFO and memory port size data transfers.
•
Supports both big and little endian.
•
DMA is configurable to a maximum of 16 words, 32 half-words, or 64 bytes for each channel.
•
Bus utilization control for the channel that is not trigger by a DMA request.
•
Burst time-out errors terminate the DMA cycle when the burst cannot be completed within a programmed
time count.
•
Buffer overflow errors terminate the DMA cycle when the internal buffer receives more than 64 bytes of
data. This is useful when the source mode is set to end-of-burst enable FIFO, in case the DMA_EOBI signal
is not detected after 64 bytes of data are received.
•
Transfer errors terminate the DMA cycle when a transfer error is detected during a DMA burst.
•
DMA request time-out errors are generated for channels that are triggered by DMA requests to interrupt the
CPU when a DMA request is not asserted after a programmed time count.
•
Interrupts provided to the interrupt controller (and subsequently to the core) on bulk data transfer complete
or transfer error.
•
Each peripheral supporting DMA transfer generates a DMA_REQ signal to the DMA controller, assuming
that each FIFO has a unique system address and generates a dedicated DMA_REQ signal to the DMA
controller. For example, an USB device with 8 end-points has 8 DMA request signals to the DMA if they
all support DMA transfer.
•
The DMA controller provides an acknowledge signal to the peripheral after a DMA burst is complete. This
signal is sometimes used by the peripheral to clear some status bits.
•
Repeat data transfer function supports automatic USB host–USB device bulk/iso data stream transfer.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
13-1
Block Diagram
13.2 Block Diagram
SPI
AIPI
IP Bus
IP Bus
AHB
CSI
DMA
I2S
IP Bus
DMA_REQ [31:0], DMA_ACK,
DMA_EOBO, DMA_EOBI,
DMA_EOBO_CNT,
DMA_EOBI_CNT
UART
MIG
Figure 13-1. DMAC in MC9328MX1
System
Registers
AHB_BUS_ARB
DMA_EOBI, DMA_EOBI_CNT
Prioritize
BUS_REQ
Channel 0
registers
Source Sel
Channel 1
registers
Source Sel
Channel n
registers
Source Sel
DMA_REQ [31:0]i
AHB_BUS_ARB
Bus Arbiter
AHB_CNTL
AHB_A [31:0]
AHB_D [31:0]
AHB I/F
Cntl Signal
Generation
BG
AHB I/F
Address
Generation
DMA_ACK,
DMA_EOBO, and
DMA_EOBO_CNT
Generation
AHB I/F
Data Buffer
Interrupt
Generation
DMA_ACK
DMA_EOBO
DMA_EOBO_CNT
DMA_ERR
DMA_INT
16 × 32 Data
FIFO
Figure 13-2. DMAC Block Diagram
MC9328MX1 Reference Manual, Rev. 6.1
13-2
Freescale Semiconductor
Signal Description
DMA_REQ
DMA_DATA
DMA_ACK
Figure 13-3. DMA Request and Acknowledge Timing Diagram
Display
Linear Memory
2D Memory
W-Size
X-Size
Y-Size =
no. of
X-Size
Source or
Destination
Address
Y-Size
W-Size
Figure 13-4. 2D Memory Diagram
13.3 Signal Description
The MC9328MX1 signal descriptions are identified in Table 13-1.
Table 13-1. Signal Description
Signal
Description
AHB_xxx
AHB bus signals
IP Bus
IP bus signals
DMA_REQ
DMA request signal generated by peripherals. One FIFO should generate one DMA_REQ signal. This
signal must be negated by the peripheral automatically before the rising edge of DMA_ACK. It is
usually negated when the FIFO is read.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
13-3
Programming Model
Table 13-1. Signal Description (continued)
Signal
Description
DMA_ACK
DMA request acknowledge generated by the DMA controller to signal the end of a DMA burst.
DMA_EOBI
This signal is asserted by the USB device when the last data of the burst is read from the FIFO.
DMA_EOBI_CNT
This signal is asserted by the USB device when the last data of the burst is read from the FIFO to
indicate the number of valid bytes.
DMA_EOBO
This signal is asserted by the DMA controller when the last data of the burst is written to the FIFO.
DMA_EOBO_CNT
This signal is asserted by the DMA controller when the last data of the burst is written to the FIFO to
indicate the number of valid bytes.
DMA_ERR
This signal is asserted by DMA controller when any DMA error is detected.
DMA_INT
This signal is asserted by DMA controller when data transfer is complete—that is, the data count
reaches the desired level.
13.3.1 Big Endian and Little Endian
The BIG_ENDIAN signal determines the MC9328MX1 memory endian configuration. BIG_ENDIAN is a static
pin to the processor and if it is driven logic-high at power on reset the processor's memory system is configured as
big endian. If it is driven logic-low at power on reset the processor's memory system is configured as little endian.
The pin should not be changed after power on reset (POR) deasserts or during operation.
13.4 Programming Model
The DMA module includes 107 user-accessible 32-bit registers. These registers are divided into three groups by
function:
•
General registers for all functional blocks (see Section 13.4.1, on page 13-8)
•
2D memory registers to control the display width and the x and y of the window (see Section 13.4.2, on page
13-16)
•
Channel registers to control and configure channels 0–10 (see Section 13.4.3, on page 13-18)
Table 13-2 summarizes these registers and their addresses.
Table 13-2. DMA Module Register Memory Map
Description
Name
Address
DMA Control Register
DCR
0x00209000
DMA Interrupt Status Register
DISR
0x00209004
DMA Interrupt Mask Register
DIMR
0x00209008
General Registers
MC9328MX1 Reference Manual, Rev. 6.1
13-4
Freescale Semiconductor
Programming Model
Table 13-2. DMA Module Register Memory Map (continued)
Description
Name
Address
DMA Burst Time-Out Status Register
DBTOSR
0x0020900C
DMA Request Time-Out Status Register
DRTOSR
0x00209010
DMA Transfer Error Status Register
DSESR
0x00209014
DMA Buffer Overflow Status Register
DBOSR
0x00209018
DMA Burst Time-Out Control Register
DBTOCR
0x0020901C
2D Memory Registers
W-Size Register A
WSRA
0x00209040
X-Size Register A
XSRA
0x00209044
Y-Size Register A
YSRA
0x00209048
W-Size Register B
WSRB
0x0020904C
X-Size Register B
XSRB
0x00209050
Y-Size Register B
YSRB
0x00209054
Channel 0 Source Address Register
Channel 0 Destination Address Register
Channel 0 Count Register
Channel 0 Control Register
Channel 0 Request Source Select Register
Channel 0 Burst Length Register
Channel 0 Request Time-Out Register
Channel 0 Bus Utilization Control Register
SAR0
DAR0
CNTR0
CCR0
RSSR0
BLR0
RTOR0
BUCR0
0x00209080
0x00209084
0x00209088
0x0020908C
0x00209090
0x00209094
0x00209098
0x00209098
Channel 1 Source Address Register
Channel 1 Destination Address Register
Channel 1 Count Register
Channel 1 Control Register
Channel 1 Request Source Select Register
Channel 1 Burst Length Register
Channel 1 Request Time-Out Register
Channel 1 Bus Utilization Control Register
SAR1
DAR1
CNTR1
CCR1
RSSR1
BLR1
RTOR1
BUCR1
0x002090C0
0x002090C4
0x002090C8
0x002090CC
0x002090D0
0x002090D4
0x002090D8
0x002090D8
Channel 2 Source Address Register
Channel 2 Destination Address Register
Channel 2 Count Register
Channel 2 Control Register
Channel 2 Request Source Select Register
Channel 2 Burst Length Register
Channel 2 Request Time-Out Register
Channel 2 Bus Utilization Control Register
SAR2
DAR2
CNTR2
CCR2
RSSR2
BLR2
RTOR2
BUCR2
0x00209100
0x00209104
0x00209108
0x0020910C
0x00209110
0x00209114
0x00209118
0x00209118
Channel Registers
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
13-5
Programming Model
Table 13-2. DMA Module Register Memory Map (continued)
Description
Name
Address
Channel 3 Source Address Register
Channel 3 Destination Address Register
Channel 3 Count Register
Channel 3 Control Register
Channel 3 Request Source Select Register
Channel 3 Burst Length Register
Channel 3 Request Time-Out Register
Channel 3 Bus Utilization Control Register
SAR3
DAR3
CNTR3
CCR3
RSSR3
BLR3
RTOR3
BUCR3
0x00209140
0x00209144
0x00209148
0x0020914C
0x00209150
0x00209154
0x00209158
0x00209158
Channel 4 Source Address Register
Channel 4 Destination Address Register
Channel 4 Count Register
Channel 4 Control Register
Channel 4 Request Source Select Register
Channel 4 Burst Length Register
Channel 4 Request Time-Out Register
Channel 4 Bus Utilization Control Register
SAR4
DAR4
CNTR4
CCR4
RSSR4
BLR4
RTOR4
BUCR4
0x00209180
0x00209184
0x00209188
0x0020918C
0x00209190
0x00209194
0x00209198
0x00209198
Channel 5 Source Address Register
Channel 5 Destination Address Register
Channel 5 Count Register
Channel 5 Control Register
Channel 5 Request Source Select Register
Channel 5 Burst Length Register
Channel 5 Request Time-Out Register
Channel 5 Bus Utilization Control Register
SAR5
DAR5
CNTR5
CCR5
RSSR5
BLR5
RTOR5
BUCR5
0x002091C0
0x002091C4
0x002091C8
0x002091CC
0x002091D0
0x002091D4
0x002091D8
0x002091D8
Channel 6 Source Address Register
Channel 6 Destination Address Register
Channel 6 Count Register
Channel 6 Control Register
Channel 6 Request Source Select Register
Channel 6 Burst Length Register
Channel 6 Request Time-Out Register
Channel 6 Bus Utilization Control Register
SAR6
DAR6
CNTR6
CCR6
RSSR6
BLR6
RTOR6
BUCR6
0x00209200
0x00209204
0x00209208
0x0020920C
0x00209210
0x00209214
0x00209218
0x00209218
Channel 7 Source Address Register
Channel 7 Destination Address Register
Channel 7 Count Register
Channel 7 Control Register
Channel 7 Request Source Select Register
Channel 7 Burst Length Register
Channel 7 Request Time-Out Register
Channel 7 Bus Utilization Control Register
SAR7
DAR7
CNTR7
CCR7
RSSR7
BLR7
RTOR7
BUCR7
0x00209240
0x00209244
0x00209248
0x0020924C
0x00209250
0x00209254
0x00209258
0x00209258
Channel 8 Source Address Register
Channel 8 Destination Address Register
Channel 8 Count Register
Channel 8 Control Register
Channel 8 Request Source Select Register
Channel 8 Burst Length Register
Channel 8 Request Time-Out Register
Channel 8 Bus Utilization Control Register
SAR8
DAR8
CNTR8
CCR8
RSSR8
BLR8
RTOR8
BUCR8
0x00209280
0x00209284
0x00209288
0x0020928C
0x00209290
0x00209294
0x00209298
0x00209298
MC9328MX1 Reference Manual, Rev. 6.1
13-6
Freescale Semiconductor
Programming Model
Table 13-2. DMA Module Register Memory Map (continued)
Description
Name
Address
Channel 9 Source Address Register
Channel 9 Destination Address Register
Channel 9 Count Register
Channel 9 Control Register
Channel 9 Request Source Select Register
Channel 9 Burst Length Register
Channel 9 Request Time-Out Register
Channel 9 Bus Utilization Control Register
SAR9
DAR9
CNTR9
CCR9
RSSR9
BLR9
RTOR9
BUCR9
0x002092C0
0x002092C4
0x002092C8
0x002092CC
0x002092D0
0x002092D4
0x002092D8
0x002092D8
Channel 10 Source Address Register
Channel 10 Destination Address Register
Channel 10 Count Register
Channel 10 Control Register
Channel 10 Request Source Select Register
Channel 10 Burst Length Register
Channel 10 Request Time-Out Register
Channel 10 Bus Utilization Control Register
SAR10
DAR10
CNTR10
CCR10
RSSR10
BLR10
RTOR10
BUCR10
0x00209300
0x00209304
0x00209308
0x0020930C
0x00209310
0x00209314
0x00209318
0x00209318
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
13-7
Programming Model
13.4.1 General Registers
This section describes the function of the general registers.
13.4.1.1 DMA Control Register
The DMA Control Register (DCR) controls the input of the system clock and the resetting of the DMA module.
DCR
Addr
0x00209000
DMA Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
DRST
DEN
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
r
r
r
r
r
r
r
r
r
r
r
r
r
r
w
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-3. DMA Control Register Description
Name
Description
Settings
Reserved
Bits 31–2
Reserved—These bits are reserved and should read 0.
DRST
Bit 1
DMA Reset—Generates a 3-cycle reset pulse that resets the entire DMA
module, bringing the module to its reset condition. DRST always reads 0.
0 = No effect
1 = Generates a 3-cycle reset pulse
DEN
Bit 0
DMA Enable—Enables/Disables the system clock to the DMA module.
0 = DMA disable
1 = DMA enable
MC9328MX1 Reference Manual, Rev. 6.1
13-8
Freescale Semiconductor
Programming Model
13.4.1.2 DMA Interrupt Status Register
The DMA Interrupt Status Register (DISR) contains the interrupt status of each channel in the DMAC. The status
bit is set whenever the corresponding DMA channel data transfer is complete. When any bit in the DMA Interrupt
Status Register (DISR) is set and the corresponding bit in the interrupt mask register is cleared, a DMA_INT is
asserted to the interrupt controller (AITC). When an interrupt occurs, the interrupt service routine must check the
DISR to determine the interrupting channel. Each bit is cleared by writing 1 to it. The DISR bit cannot be cleared
when the DMA channel is disabled.
DISR
Addr
0x00209004
DMA Interrupt Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
15
TYPE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-4. DMA Interrupt Status Register Description
Name
Description
Reserved
Bits 31–11
Reserved—These bits are reserved and should read 0.
CH10–CH0
Bits 10–0
Channel 10 to 0 Interrupt Status—Indicates the interrupt status for each
DMA channel.
Settings
0 = No interrupt
1 = Interrupt is pending
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
13-9
Programming Model
13.4.1.3 DMA Interrupt Mask Register
The DMA Interrupt Mask Register (DIMR) masks both normal interrupts and error interrupts generated by the
corresponding channel. There is one control bit for each channel. When an interrupt is masked, the interrupt
controller does not generate an interrupt request to the AITC, however the status of the interrupt can be observed
from the interrupt status register, burst time-out status register, request time-out status register, or the transfer error
status register. At reset, all the interrupts are masked and all the bits in this register are set to 1.
DIMR
Addr
0x00209008
DMA Interrupt Mask Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
15
TYPE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
RESET
0x07FF
Table 13-5. DMA Interrupt Mask Register Description
Name
Description
Reserved
Bits 31–11
Reserved—These bits are reserved and should read 0.
CH10–CH0
Bits 10–0
Channel 10 to 0—Controls the interrupts for each DMA channel.
Settings
0 = Enables interrupts
1 = Disables interrupts
MC9328MX1 Reference Manual, Rev. 6.1
13-10
Freescale Semiconductor
Programming Model
13.4.1.4 DMA Burst Time-Out Status Register
A burst time-out is set when a DMA burst cannot be completed within the number of clock cycles specified in the
DMA Burst Time-Out Control Register (DBTOCR) of the channel. When any bit is set in this register and the
corresponding bit in the interrupt mask register is cleared, a DMA_ERR is asserted to the interrupt controller
(AITC). The DMA burst time-out status register (DBTOSR) indicates the channel, if any, that is currently being
serviced and whether a burst time-out was detected. Each bit is cleared by writing 1 to it.
DBTOSR
Addr
0x0020900C
DMA Burst Time-Out Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-6. DMA Burst Time-Out Status Register Description
Name
Description
Reserved
Bits 31–11
Reserved—These bits are reserved and should read 0.
CH10–CH0
Bits 10–0
Channel 10 to 0—Indicates the burst time-out status of each DMA channel.
Settings
0 = No burst time-out
1 = Burst time-out
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
13-11
Programming Model
13.4.1.5 DMA Request Time-Out Status Register
A DMA request time-out is set when there is no DMA request from the selected DMA_REQ source within the
pre-assigned number of clock cycles specified in the request time-out control register (DBTOCR) for the channel.
When any bit is set in this register and the corresponding bit in the interrupt mask register is cleared, a DMA_ERR
is asserted to the AITC. The DMA Request Time-Out Status Register (DRTOSR) indicates the enabled channel, if
any, that detected a DMA request time-out. Clear each bit by writing 1 to it.
DRTOSR
Addr
0x00209010
DMA Request Time-Out Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
15
TYPE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-7. DMA Request Time-Out Status Register Description
Name
Description
Reserved
Bits 31–11
Reserved—These bits are reserved and should read 0.
CH10–CH0
Bits 10–0
Channel 10 to 0—Indicates the request time-out status of each DMA
channel.
Settings
0 = No DMA request time-out
1 = DMA request time-out
MC9328MX1 Reference Manual, Rev. 6.1
13-12
Freescale Semiconductor
Programming Model
13.4.1.6 DMA Transfer Error Status Register
A DMA transfer error is set when the AHB bus signal HRESP [1:0] = ERROR is asserted during a DMA transfer.
When any bit is set in this register and the corresponding bit in the interrupt mask register is cleared, a DMA_ERR
is asserted to the AITC. The DMA Transfer Error Status Register (DSESR) indicates the channel, if any, detected a
transfer error during a DMA burst. Clear each bit by writing 1 to it.
DSESR
Addr
0x00209014
DMA Transfer Error Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
15
TYPE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-8. DMA Transfer Error Status Register Description
Name
Description
Reserved
Bits 31–11
Reserved—These bits are reserved and should read 0.
CH10–CH0
Bits 10–0
Channel 10 to 0—Indicates the DMA transfer error status of each DMA
channel.
Settings
0 = No transfer error
1 = Transfer error
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
13-13
Programming Model
13.4.1.7 DMA Buffer Overflow Status Register
The DMA Buffer Overflow Status Register (DBOSR) indicates whether the internal buffer of the DMA Controller
overflowed during a data transfer. The channel is not enabled until the corresponding bit is cleared. When any bit is
set in this register and the corresponding bit in the interrupt mask register is cleared, a DMA_ERR is asserted to the
AITC.
DBOSR
Addr
0x00209018
DMA Buffer Overflow Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-9. DMA Buffer Overflow Status Register Description
Name
Description
Reserved
Bits 31–11
Reserved—These bits are reserved and should read 0.
CH10–CH0
Bits 10–0
Channel 10 to 0—Indicates the buffer overflow error status of each
DMA channel.
Settings
0 = No buffer overflow occurred
1 = Buffer overflow occurred
MC9328MX1 Reference Manual, Rev. 6.1
13-14
Freescale Semiconductor
Programming Model
13.4.1.8 DMA Burst Time-Out Control Register
This register sets the time-out for DMA transfer cycle for all DMA channels, so that the DMA controller can
release the AHB and IP buses on error. An internal counter starts counting when a DMA burst cycle starts, and
resets to zero when the burst is completed. When the counter reaches the count value set in the register, it asserts an
interrupt and sets the corresponding error bit in the DMA burst time-out error register. The system clock is used as
input clock to the counter.
DBTOCR
Addr
0x0020901C
DMA Burst Time-Out Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
EN
TYPE
CNT
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-10. DMA Burst Time-Out Control Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
EN
Bit 15
Enable—Enables/Disables the burst time-out.
CNT
Bits 14–0
Count—Contains the time-out count down value.
Settings
0 = Disables burst time-out
1 = Enables burst time-out
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
13-15
Programming Model
13.4.2 2D Memory Registers (A and B)
The two sets of 2D memory registers allow any one channel of the eleven channels to select any register set to
define the respective 2D memory size.
13.4.2.1 W-Size Registers
The W-Size registers (WSRA and WSRB) define the number of bytes that make up the display width. This allows
the DMA controller to calculate the next starting address of another row by adding the source/destination address
to the contents of the W-Size register.
WSRA
WSRB
Addr
0x00209040
0x0020904C
W-Size Register A
W-Size Register B
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WS
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-11. W-Size Registers Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
WS
Bits 15–0
W-Size—Contains the number of bytes that make up the display width.
MC9328MX1 Reference Manual, Rev. 6.1
13-16
Freescale Semiconductor
Programming Model
13.4.2.2 X-Size Registers
The X-Size registers (XSRA and XSRB) contain the number of bytes per row of the window. The value of this
register is used by the DMA controller to determine when to jump to the next row.
XSRA
XSRB
Addr
0x00209044
0x00209050
X-Size Register A
X-Size Register B
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
XS
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-12. X-Size Registers Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
XS
Bits 15–0
X-Size—Contains the number of bytes per row that define the X-Size of the 2D memory.
Settings
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
13-17
Programming Model
13.4.2.3 Y-Size Registers
The Y-Size registers (YSRA and YSRB) contain the number of rows in the 2D memory window. This setting is
used by the DMA controller to calculate the total size of the transfer.
YSRA
YSRB
Addr
0x00209048
0x00209054
Y-Size Register A
Y-Size Register B
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
YS
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-13. Y-Size Registers Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
YS
Bits 15–0
Y-Size—Contains the number of rows that make up the 2D memory window.
13.4.3 Channel Registers
Channels 0 to 10 support linear memory, 2D memory, FIFO, and end-of-burst enable FIFO transfer. Only one
enabled channel may be configured for 2D memory at any time.
The interrupt request DMA_REQ [31:0] does not have a priority assigned. The only priority available is the
priority that is defined for each channel: channel 10 has the highest priority and channel 0 has the lowest priority.
Channel priority is implemented only when more than one request occurs at the same time, otherwise, channels are
serviced on a first come, first serve basis.
Each channel generates a normal interrupt to the interrupt handler when the data count reaches the selected value
and the channel source mode is not set to end-of-burst enable FIFO.
Each channel generates an error interrupt to the interrupt handler when the following conditions exist:
•
A DMA request time-out is true
•
A DMA burst time-out is true during a burst cycle
•
The internal buffer overflows during a burst cycle
•
A transfer error acknowledge is asserted during a burst cycle
MC9328MX1 Reference Manual, Rev. 6.1
13-18
Freescale Semiconductor
Programming Model
13.4.3.1 Channel Source Address Register
Each of the channel source address registers contain the source address for the DMA cycle. The value of the
register remains unchanged throughout the DMA process. If the memory direction bit (MDIR) in the channel
control register (CCR) is clear (indicating a memory address increment), then the channel source address register
contains the starting address of the memory block. If MDIR is set (indicating a memory address decrement), then
the channel source address register contains the ending address of the memory block.
SAR0
SAR1
SAR2
SAR3
SAR4
SAR5
SAR6
SAR7
SAR8
SAR9
SAR10
BIT
Addr
0x00209080
0x002090C0
0x00209100
0x00209140
0x00209180
0x002091C0
0x00209200
0x00209240
0x00209280
0x002092C0
0x00209300
Channel 0 Source Address Register
Channel 1 Source Address Register
Channel 2 Source Address Register
Channel 3 Source Address Register
Channel 4 Source Address Register
Channel 5 Source Address Register
Channel 6 Source Address Register
Channel 7 Source Address Register
Channel 8 Source Address Register
Channel 9 Source Address Register
Channel 10 Source Address Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SA [31:16]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SA [15:2]
TYPE
SA [1] SA [0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-14. Channel Source Address Register Description
Name
Description
SA [31:2]
Bits 31–2
Source Address—Contains the source address from where data is read during a DMA transfer.
SA [1], SA [0]
Bits 1–0
Source Address [1] and Source Address [0]—To ensure that all addresses are word-aligned these bits
are set internally to 0. These bits will be read/write as any value if and only if running in big endian and
source mode set to FIFO. This is to allow FIFO to use offset address during big endian mode.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
13-19
Programming Model
13.4.3.2 Destination Address Registers
Each of the destination address registers (DARx) contain the destination address for a DMA cycle. The value of the
register remains unchanged throughout the DMA process. If the memory direction bit (MDIR) in the channel
control register (CCR) is clear (indicating a memory address increment), then the destination address register
contains the starting address of the memory block. If MDIR is set (indicating a memory address decrement), then
the destination address register contains the ending address of the memory block.
DAR0
DAR1
DAR2
DAR3
DAR4
DAR5
DAR6
DAR7
DAR8
DAR9
DAR10
BIT
Addr
0x00209084
0x002090C4
0x00209104
0x00209144
0x00209184
0x002091C4
0x00209204
0x00209244
0x00209284
0x002092C4
0x00209304
Channel 0 Destination Address Register
Channel 1 Destination Address Register
Channel 2 Destination Address Register
Channel 3 Destination Address Register
Channel 4 Destination Address Register
Channel 5 Destination Address Register
Channel 6 Destination Address Register
Channel 7 Destination Address Register
Channel 8 Destination Address Register
Channel 9 Destination Address Register
Channel 10 Destination Address Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DA [31:16]
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DA [15:2]
TYPE
DA [1] DA [0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-15. Channel Destination Address Registers Description
Name
Description
DA [31:2]
Bits 31–2
Destination Address—Contains the destination address to which data is written to during a DMA transfer.
DA [1], DA [0]
Bits 1–0
Destination Address [1] and Destination Address [0]—To ensure that all addresses are word-aligned,
these bits are set internally to 0.
MC9328MX1 Reference Manual, Rev. 6.1
13-20
Freescale Semiconductor
Programming Model
13.4.3.3 Channel Count Registers
Each of the channel count registers (CNTRx) contain the number of bytes of data to be transferred. There is an
internal counter that counts up (number of bytes—4 for word, 2 for halfword and 1 for byte) for every DMA
transfer. The internal counter is compared with the register after every transfer. When the counter value matches
with the register value, the channel is disabled until the CEN bit is cleared and reset, or the RPT bit in the
associated channel control register is set to 1. The internal counter is reset to 0 when the channel is enabled again.
The length of the last DMA burst can be shorter than the regular burst length specified in the burst length register.
However, when data is transferred out from an I/O FIFO and the last burst is less than BL, the I/O device must
generate a DMA request for the last transfer. When data is transferred to an I/O FIFO and the last burst is less than
BL, only the remaining number of data is transferred.
When the source mode is set to end-of-burst enable FIFO, this register becomes a read only register and the value
of the register is the number of bytes being transferred.
CNTR0
CNTR1
CNTR2
CNTR3
CNTR4
CNTR5
CNTR6
CNTR7
CNTR8
CNTR9
CNTR10
BIT
Addr
0x00209088
0x002090C8
0x00209108
0x00209148
0x00209188
0x002091C8
0x00209208
0x00209248
0x00209288
0x002092C8
0x00209308
Channel 0 Count Register
Channel 1 Count Register
Channel 2 Count Register
Channel 3 Count Register
Channel 4 Count Register
Channel 5 Count Register
Channel 6 Count Register
Channel 7 Count Register
Channel 8 Count Register
Channel 9 Count Register
Channel 10 Count Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CNT
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNT
RESET
0x0000
Table 13-16. Channel Count Registers Description
Name
Description
Reserved
Bits 31–24
Reserved—These bits are reserved and should read 0.
CNT
Bits 23–0
Count—Contains the number of bytes of data to be transferred during a DMA cycle.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
13-21
Programming Model
13.4.3.4 Channel Control Registers
Each of the channel control registers (CCRx) controls and displays the status of a DMA channel operation.
NOTE:
While any one of the eleven channels may be configured for 2D memory, only one
enabled channel may be configured for 2D memory at any time, This constraint
does not apply to configuring the DMA channels for linear memory, FIFO, and
end-of-burst enable FIFO.
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
CCR7
CCR8
CCR9
CCR10
Addr
0x0020908C
0x002090CC
0x0020910C
0x0020914C
0x0020918C
0x002091CC
0x0020920C
0x0020924C
0x0020928C
0x002092CC
0x0020930C
Channel 0 Control Register
Channel 1 Control Register
Channel 2 Control Register
Channel 3 Control Register
Channel 4 Control Register
Channel 5 Control Register
Channel 6 Control Register
Channel 7 Control Register
Channel 8 Control Register
Channel 9 Control Register
Channel 10 Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
DMOD
TYPE
10
SMOD
9
8
MDIR MSEL
DSIZ
SSIZ
REN RPT FRC
CEN
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
w
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-17. Channel Control Registers Description
Name
Description
Reserved
Bits 31–14
Reserved—These bits are reserved and should read 0.
DMOD
Bits 13–12
Destination Mode—Selects the destination transfer mode.
Settings
00 = Linear memory
01 = 2D memory
10 = FIFO
11 = End-of-burst enable FIFO
MC9328MX1 Reference Manual, Rev. 6.1
13-22
Freescale Semiconductor
Programming Model
Table 13-17. Channel Control Registers Description (continued)
Name
Description
Settings
SMOD
Bits 11–10
Source Mode—Selects the source transfer mode.
00 = Linear memory
01 = 2D memory
10 = FIFO
11 = End-of-burst enable FIFO
MDIR
Bit 9
Memory Direction—Selects the memory address direction.
0 = Memory address increment
1 = Memory address decrement
MSEL
Bit 8
Memory Select—Selects the 2D memory register set when either
source and/or destination is programmed to 2D memory mode.
0 = 2D memory register set A selected
1 = 2D memory register set B selected
DSIZ
Bits 7–6
Destination Size—Selects the destination size of a data transfer.
00 = 32-bit destination port
01 = 8-bit destination port
10 = 16-bit destination port
11 = Reserved
SSIZ
Bits 5–4
Source Size—Selects the source size of data transfer.
Note: DSIZ1:DSIZ0 always reads/writes 00 when destination
mode is programmed as end-of-burst enable FIFO, because
end-of-burst operation only works for 32-bit FIFO.
Note: SSIZ1:SSIZ0 always reads/writes 00 when destination
mode is programmed as end-of-burst enable FIFO, because end of
burst operation only works for 32-bit FIFO.
00 = 32-bit source port
01 = 8-bit source port
10 = 16-bit source port
11 = Reserved
REN
Bit 3
Request Enable—Enables/Disables the DMA request signal. When
REN is set, the DMA burst is initiated by the DMA_REQ signal from
the I/O FIFO. When REN is cleared, DMA transfer is initiated by
CEN.
0 = Disables the DMA request signal
(when the peripheral asserts a
DMA request, no DMA transfer is
triggered); DMA transfer is
initiated by CEN only
1 = Enables the DMA request signal
(when the peripheral asserts a
DMA request, a DMA transfer is
triggered)
RPT
Bit 2
Repeat—Enables/Disables the data transfer repeat function. When
enabled and when the counter reaches the value set in Count
Register, the Count Register is reset to its zero, an interrupt is
asserted, and the corresponding channel bit in the Interrupt Mask
Register is cleared. The address is reloaded from the source and
destination address register for the next DMA burst. Data transfer is
carried out continuously until the channel is disabled or it completes
the last cycle after RPT is cleared.
If enabling the repeat function, do not change source and
destination addresses on the fly. If it is necessary to change
source and destination addresses, do it after a complete DMA cycle
finishes and then re-start the channel again.
0 = Disables repeat function
1 = Enables repeat function
Note: To correctly terminate a repeat enabled channel[x], user is
required to first set RSSR[x] to 0, then set CCR[x]-REN to 1, and
finally CCR[x]-CEN to 0.
FRC
Bit 1
Force a DMA Cycle—Forces a DMA cycle to occur. FRC always
reads 0.
0 = No effect
1 = Force DMA cycle
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
13-23
Programming Model
Table 13-17. Channel Control Registers Description (continued)
Name
CEN
Bit 0
Description
Settings
DMA Channel Enable—Enables/Disables the DMA channel.
0 = Disables the DMA channel
1 = Enables the DMA channel
Note:
1. Program all of the channel settings before enabling the channel.
2. To restart a channel, clear CEN, and then set CEN to 1.
When the source mode is set to end-of-burst enable FIFO, the burst length is determined by the input signals
DMA_EOBI and DMA_EOBI_CNT, and the DMA burst (from peripheral to memory) can be terminated only by
disabling the channel (clearing the corresponding CEN bit in channel control register). The count register
(CNTR0-CNTR10) becomes read-only and indicates the number of bytes being transferred. This setting is
typically used when the channel is configured to transfer data from an endpoint FIFO of a USB device to an
endpoint data packet buffer in system memory.
When the destination mode is set to end-of-burst enable FIFO, the channel operates the same as in normal FIFO
mode, the only difference is that at the end of each burst, the DMA controller generates a DMA_EOBO and
DMA_EOBO_CNT signal to the peripheral. This setting is typically used when the I/O channel is configured to
transfer data from an endpoint data packet buffer in system memory to an endpoint FIFO of a USB device.
Table 13-18. DMA_EOBO_CNT and DMA_EOBI_CNT Settings
DMA_EOBI_CNT [1:0] or
DMA_EOBO_CNT [1:0]
Number of Bytes Per Transfer
00
4
01
1
10
2
11
3
MC9328MX1 Reference Manual, Rev. 6.1
13-24
Freescale Semiconductor
Programming Model
13.4.3.5 Channel Request Source Select Registers
Each of the 32-bit channel request source select registers (RSSRx) selects one of the 32 DMA request signals
(DMA_REQ [31:0]) to initiate a DMA transfer for the corresponding channel.
RSSR0
RSSR1
RSSR2
RSSR3
RSSR4
RSSR5
RSSR6
RSSR7
RSSR8
RSSR9
RSSR10
Addr
0x00209090
0x002090D0
0x00209110
0x00209150
0x00209190
0x002091D0
0x00209210
0x00209250
0x00209290
0x002092D0
0x00209310
Channel 0 Request Source Select Register
Channel 1 Request Source Select Register
Channel 2 Request Source Select Register
Channel 3 Request Source Select Register
Channel 4 Request Source Select Register
Channel 5 Request Source Select Register
Channel 6 Request Source Select Register
Channel 7 Request Source Select Register
Channel 8 Request Source Select Register
Channel 9 Request Source Select Register
Channel 10 Request Source Select Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
RSS
TYPE
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-19. Channel Request Source Select Registers Description
Name
Description
Reserved
Bits 31–5
Reserved—These bits are reserved and should read 0.
RSS
Bits 4–0
Request Source Select—Selects one of the 32 DMA_REQ signals
that initiates a DMA transfer cycle for the channel.
Settings
00000 = select DMA_REQ [0]
00001 = select DMA_REQ [1]
...
11111 = select DMA_REQ [31]
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
13-25
Programming Model
13.4.3.6 Channel Burst Length Registers
The Channel Burst Length registers (BLRx) control the burst length of a DMA cycle. For a FIFO channel setting,
the burst length is normally assigned according to the FIFO size of the selected I/O device, or by the FIFO level at
which its DMA_REQ signal is asserted.
For example, when the UART RxD FIFO is 12 × 8 and it asserts DMA_REQ when it receives more than 8 bytes of
data, BL is 8. When the memory port size also is 8-bit, the DMA burst is 8-byte reads followed by 8-byte writes.
When the memory port size is smaller than the I/O port size, the burst length of the byte writes is doubled. For
example, the I/O port is 32-bit, the memory port is 16-bit, and the burst length is set to 32. In this configuration, the
DMA performs 8 word burst reads and 16 halfword burst writes for I/O to memory transfer.
BLR0
BLR1
BLR2
BLR3
BLR4
BLR5
BLR6
BLR7
BLR8
BLR9
BLR10
Channel 0 Burst Length Register
Channel 1 Burst Length Register
Channel 2 Burst Length Register
Channel 3 Burst Length Register
Channel 4 Burst Length Register
Channel 5 Burst Length Register
Channel 6 Burst Length Register
Channel 7 Burst Length Register
Channel 8 Burst Length Register
Channel 9 Burst Length Register
Channel 10 Burst Length Register
0x00209094
0x002090D4
0x00209114
0x00209154
0x00209194
0x002091D4
0x00209214
0x00209254
0x00209294
0x002092D4
0x00209314
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
BL
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-20. Channel Burst Length Registers Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
BL
Bits 5–0
Burst Length—Contains the number of data bytes that
are transferred in a DMA burst.
Settings
000000 = 64 bytes read follow 64 bytes write
000001 = 1byte read follow 1 byte write
000010 = 2 bytes read follow 2 bytes write
....
111111 = 63 bytes read follow 63 bytes write
MC9328MX1 Reference Manual, Rev. 6.1
13-26
Freescale Semiconductor
Programming Model
13.4.3.7 Channel Request Time-Out Registers
The channel request time-out registers (RTOx) set the time-out for DMA_REQ from the selected request source of
the channel, which detects any discontinuity of data transfer. The request time-out takes effect only when the
corresponding request enable (REN) bit in the channel control register (CCR) is set. An internal counter starts
counting when a DMA channel is enabled, the burst is completed, and the counter is reset to zero when a DMA
request is detected. When the counter reaches the count value set in the register, it asserts an interrupt and sets its
error bit in the DMA request time-out status register. The input clock of the counter is selectable from either the
system clock (HCLK) or input crystal (CLK32K).
NOTE:
This register shares the same address as the bus utilization control register.
RTOR0
RTOR1
RTOR2
RTOR3
RTOR4
RTOR5
RTOR6
RTOR7
RTOR8
RTOR9
RTOR10
Channel 0 Request Time-Out Register
Channel 1 Request Time-Out Register
Channel 2 Request Time-Out Register
Channel 3 Request Time-Out Register
Channel 4 Request Time-Out Register
Channel 5 Request Time-Out Register
Channel 6 Request Time-Out Register
Channel 7 Request Time-Out Register
Channel 8 Request Time-Out Register
Channel 9 Request Time-Out Register
Channel 10 Request Time-Out Register
0x00209098
0x002090D8
0x00209118
0x00209158
0x00209198
0x002091D8
0x00209218
0x00209258
0x00209298
0x002092D8
0x00209318
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
EN
CLK
PSC
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNT
RESET
0x0000
Table 13-21. Channel Request Time-Out Registers Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
EN
Bit 15
Enable—Enables/Disables the DMA request time-out.
Settings
0 = Disables DMA request time-out
1 = Enables DMA request time-out
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
13-27
Programming Model
Table 13-21. Channel Request Time-Out Registers Description (continued)
Name
Description
Settings
CLK
Bit 14
Clock Source—Selects the counter of input clock source.
0 = HCLK
1 = 32.768 kHz
PSC
Bit 13
Prescaler Count—Sets the prescaler of the input clock.
0 = Divide by 1
1 = Divide by 256
CNT
Bits 12–0
Request Time-Out Count—Contains the time-out count down value for the internal counter. This value
remains unchanged through out the DMA process.
13.4.3.8 Channel 0 Bus Utilization Control Register
The Bus Utilization Control register (BUCRx) controls the bus utilization of an enabled channel when the request
enable (REN) bit in channel control register (CCR) is cleared. The channel does not request a DMA transfer until
the counter reaches the count value set in the register except for the very first burst. This counter is cleared when
the channel burst is started. When the count value is set to zero, the DMA carries on burst transfers one after
another until it reaches the value set in count register. In this case, the user must be careful not to violate the
maximum bus request latency of other devices.
NOTE:
This register shares the same address of request time-out register.
MC9328MX1 Reference Manual, Rev. 6.1
13-28
Freescale Semiconductor
Programming Model
BUCR0
BUCR1
BUCR2
BUCR3
BUCR4
BUCR5
BUCR6
BUCR7
BUCR8
BUCR9
BUCR10
Channel 0 Bus Utilization Control Register
Channel 1 Bus Utilization Control Register
Channel 2 Bus Utilization Control Register
Channel 3 Bus Utilization Control Register
Channel 4 Bus Utilization Control Register
Channel 5 Bus Utilization Control Register
Channel 6 Bus Utilization Control Register
Channel 7 Bus Utilization Control Register
Channel 8 Bus Utilization Control Register
Channel 9 Bus Utilization Control Register
Channel 10 Bus Utilization Control Register
0x00209098
0x002090D8
0x00209118
0x00209158
0x00209198
0x002091D8
0x00209218
0x00209258
0x00209298
0x002092D8
0x00209318
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
CCNT
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 13-22. Channel 0 Bus Utilization Control Registers Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
CCNT
Bits 15–0
Clock Count—Sets the number of system clocks that must occur before the memory channel releases the
AHB, before the next DMA request for the channel.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
13-29
DMA Request Table
13.5 DMA Request Table
Table 13-23 identifies the dedicated DMA request signal and its associated peripheral.
Table 13-23. DMA Request Table
DMA Request
Peripheral
DMA_REQ [31]
UART 1 Receive DMA Request
DMA_REQ [30]
UART 1 Transmit DMA Request
DMA_REQ [29]
UART 2 Receive DMA Request
DMA_REQ [28]
UART 2 Transmit DMA Request
DMA_REQ [27]
SPI 2 Transmit DMA RequestMSHC
DMA Request
DMA_REQ [26]
SPI 2 Receive DMA RequestMSHC DMA
Request
DMA_REQ [25]
USB Device End Point 5 DMA Request
DMA_REQ [24]
USB Device End Point 4 DMA Request
DMA_REQ [23]
USB Device End Point 3 DMA Request
DMA_REQ [22]
USB Device End Point 2 DMA Request
DMA_REQ [21]
USB Device End Point 1 DMA Request
DMA_REQ [20]
USB Device End Point 0 DMA Request
DMA_REQ [19]
Reserved
DMA_REQ [18]
Reserved
DMA_REQ [17]
SSI Receive DMA Request
DMA_REQ [16]
SSI Transmit DMA Request
DMA_REQ [15]
SPI 1 Transmit DMA Request
DMA_REQ [14]
SPI 1 Receive DMA Request
DMA_REQ [13]
SDHC DMA Request
DMA_REQ [12]
Ext_DMA
DMA_REQ [11]
DSPA MAC DMA Request
DMA_REQ [10]
DSPA DCT DIN DMA Request
DMA_REQ [9]
DSPA DCT DOUT DMA Request
DMA_REQ [8]
MSHC DMA Request
DMA_REQ [7]
CSI Receive FIFO DMA Request
DMA_REQ [6]
CSI Statistic FIFO DMA Request
DMA_REQ [5]
SSI2 Receive DMA Request
DMA_REQ [4]
SSI2 Transmit DMA Request
DMA_REQ [3]
UART3 Receive DMA Request
DMA_REQ [2]
UART3 Transmit DMA Request
DMA_REQ [1]
Reserved
DMA_REQ [0]
Reserved
MC9328MX1 Reference Manual, Rev. 6.1
13-30
Freescale Semiconductor
Chapter 14
Watchdog Timer Module
14.1 General Overview
The watchdog timer module of the MC9328MX1 protects against system failures by providing a method of
escaping from unexpected events or programming errors. Once activated, the timer must be serviced by software
on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the watchdog timer
module either asserts a system reset signal WDT_RST or a interrupt request signal WDT_INT depending on
software configuration. Table 14-1 on page 14-5 shows the watchdog timer module’s input and output signals. A
state machine that demonstrates the time-out operation of the counter operation is shown in Figure 14-2 on
page 14-4.
14.2 Watchdog Timer Operation
The following sections describe the operation and programming of the watchdog timer module.
14.2.1 Timing Specifications
The watchdog timer provides time-out periods from 0.5 seconds up to 64 seconds with a time resolution of 0.5
seconds. As shown in Figure 14-1, the watchdog timer uses the CLK2HZ clock (from RTC module) as an input to
achieve the resolution of 0.5 seconds and a frequency of 2 Hz. This clock is connected to the input of a 7-bit
counter to obtain a range of 0.5 to 64 seconds. The user can determine the time-out period by writing to the
watchdog time-out field (WT[6:0]) in the Watchdog Control Register (WCR).
WHALT
WDE
7-bit Counter
CLK2HZ
0
CLK32K
1
(Time-Out)
Test Mode (TMD bit)
Figure 14-1. Watchdog Timer Functional Block Diagram
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
14-1
Watchdog After Reset
14.2.2 Watchdog During Reset
14.2.2.1 Power-On Reset
During a power-on reset (POR) all registers are reset to their reset values and the counter is placed in the idle state
until the watchdog is enabled. The Watchdog Status Register (WSTR) contains the source of the reset event and the
interrupt status bit TINT is reset to 0.
14.2.2.2 Software Reset
When software reset occurs, the software reset (SWR) bit in Watchdog Control Register (WCR) is set to 1, all
registers of the Watchdog module are reset to their reset values and the counter is placed in the idle state until the
watchdog is enabled.
14.3 Watchdog After Reset
After reset, watchdog timer operation can be divided into four states: initial load, countdown, reload, and time-out.
The following sections define each of the watchdog timer states after reset.
14.3.1 Initial Load
The Watchdog Control Register (WCR) bits WT[6:0] must be written to before the watchdog is enabled. The
watchdog is then enabled by setting the one-time writable watchdog enable (WDE) bit in the WCR. The time-out
value is loaded into the counter after the service sequence is written to the Watchdog Service Register (WSR) or
after the watchdog is enabled. The service sequence is described in Section 14.3.3, “Reload.” The counter state
machine is shown in Figure 14-2 on page 14-4.
14.3.2 Countdown
The counter is activated after the Watchdog is enabled and begins to count down from its initial programmed value.
If any system errors have occurred which prevents the software from servicing the Watchdog Service Register
(WSR), the timer will time-out when the counter reaches zero. If the WSR is serviced prior to the counter reaching
zero, the watchdog reloads its counter to the time-out value indicated by bits WT[6:0] of the WCR and re-start the
countdown. A reset will reset the counter and place it in the idle state at any time during the countdown. The
counter state machine is shown in Figure 14-2 on page 14-4.
14.3.3 Reload
The recommended service sequence is to write a $5555 followed by a $AAAA to the WSR. To reload the counter,
the writes must take place within the time-out value indicated by bits WT[6:0] of the WCR. Any number of
instructions can be executed between the two writes. This service sequence is also used to activate the counter
during the initial load. See Section 14.3.1, “Initial Load.”
If the WSR is not loaded with a $5555 prior to a write of $AAAA to the WSR, the counter will not be reloaded. If
any value other than $AAAA is written to the WSR after $5555, the counter will not be reloaded.
MC9328MX1 Reference Manual, Rev. 6.1
14-2
Freescale Semiconductor
Watchdog Control
14.3.4 Time-Out
If the counter reaches zero, the TOUT bit in WSTR (Watchdog Status Register) is set to 1 indicating that watchdog
has timed out. Reading the TOUT bit will clear it.
If the counter reaches zero, the watchdog asserts either a system reset signal WDT_RST or an interrupt request
signal WDT_INT depending on the state of the WIE bit in the WCR. A 1 written to WIE configures the watchdog
to generate a interrupt request signal to the interrupt handler. When a watchdog time-out interrupt is asserted, the
TINT bit in WSTR (Watchdog Status Register) is set to 1 to indicate that an interrupt request is generated and the
reading of this bit clears the interrupt and this bit. A 0 written to the WIE bit configures the watchdog to generate a
WDT_RST signal to reset the module. The counter state machine is shown in Figure 14-2 on page 14-4.
14.3.5 Halting the Counter
The watchdog counting can be halted at any time by setting the WHALT bit (WCR[15]) to 1. The counter
immediately stops counting and the counter value is held at the last value. The WHALT bit can be cleared by
writing 0 to it or it can be automatically cleared by the occurrence of any of three system events, fast interrupt, slow
interrupt, or system reset. The counter resumes counting from the stopped value. No other configurations are
affected.
14.4 Watchdog Control
14.4.1 Interrupt Control
The watchdog timer generates interrupt request signal WDT_INT as a result of a WDOG time-out when WIE bit of
WCR set to 1. The TINT bit of WSTR is set to 1 to indicate that the interrupt request has been generated. Reading
the TINT bit clears the interrupt and this status bit.
14.4.2 Reset Sources
The watchdog timer generates reset signal WDT_RST as a result of a WDOG time-out. This signal is an output to
the Reset Module for system reset generation.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
14-3
State Machine
14.5 State Machine
Idle
No
No
Resets
Negated
?
Time-out
Value
?
Yes
No
Watchdog
Enabled
?
Yes
Yes
Start Counter
Decrement Counter
Yes
Counting
Resumed
(fiq, irq,
reset)
?
No
Counting
Halted
(WHALT=1)
?
Yes
Counter
Suspended
No
Reload Counter
Yes
WSR
Service
d
No
Count = 0
No
?
Yes
Assert Time-out
Indication
No
Interrupt
Request
?
Yes
Assert wdt_rst
Assert wdt_int
Reset
Module
Interrupt
Handler
Figure 14-2. Counter State Machine
MC9328MX1 Reference Manual, Rev. 6.1
14-4
Freescale Semiconductor
Watchdog Timer I/O Signals
14.6 Watchdog Timer I/O Signals
Table 14-1shows the watchdog timer module input and output signals.
Table 14-1. Watchdog Timer I/O Signals
Signal Name
I/O
Description
FIQ
I
Fast Interrupt
IRQ
I
Normal Interrupt
IPS_HARD_ASYNC_RESET
I
WDOG global reset from reset module
IPS_CONT_CLK
I
96 MHz system clock
IPS_CONT_CLK
I
96 MHz system clock inverted
IPS_GATED_CLK
I
Bus clock
IPS_GATED_CLK
I
Bus clock inverted
CLK2HZ
I
2 Hz clock input from RTC module output
CLK32K
I
in test mode, counter clock becomes 32 kHz clock
IPS_MODULE_EN
I
Watchdog module enable
IPS_BYTE_15_8
I
Bit 15 to 8 enable
IPS_BYTE_7_0
I
Bit 7 to 0 enable
IPS_MRW
I
Module read/write signal
IPS_ADDR[11:2]
I
Module address bus
IPS_WDATA[31:0]
I
Module write data bus
SCAN_MODE
I
Indicates scan mode selection
SCAN_RESET
I
Indicates scan reset
IPS_CONT_CLK_EN
O
ips_cont_clk enable
IPS_XFR_ERR
O
Transfer error acknowledge
IPS_XFR_WAIT
O
Transfer wait acknowledge
IPS_RDATA[31:0]
O
Module read data bus
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
14-5
Programming Model
14.7 Programming Model
The watchdog timer has three registers in its programming model: Watchdog Control Register (WCR), Watchdog
Service Register (WSR), and Watchdog Status Register (WSTR).
.
Name
WCR
($00201000)
15
R
14
13
12
11
WHAL
T
10
9
8
7
6
5
0
0
0
WT[6:0]
4
WIE
3
2
1
0
TMD SWR WDEC WDE
W
WSR
($00201004)
WSTR
($00201008)
R
WSR[15:0]
W
R
0
0
0
0
0
0
0
TINT
0
0
0
0
0
0
0
TOUT
W
14.7.1 Watchdog Control Register
The WCR is a 32-bit read/write (byte writable) register. It controls the Watchdog operation. See Table 14-2 on
page 14-6 for bit descriptions and settings.
WCR
Addr
0x00201000
Watchdog Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
WIE
TMD
SWR
WDEC
WDE
RESET
0x0000
BIT
15
14
13
12
WHALT
TYPE
11
10
9
8
7
6
WT
rw
rw
rw
rw
rw
rw
rw
rw
r
r
r
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 14-2. Watchdog Control Register Description
Name
Description
Reserved
Bits 31–15
Reserved—These bits are reserved and should read 0.
WHALT
Bit 15
Watchdog Halt—When set, the watchdog counter immediately stops
counting and the counter value is held at the last value. The WHALT
bit can be cleared by writing 0 to it or it can be automatically cleared by
the occurrence of any of three system events, fast interrupt, slow
interrupt, or system reset.
Settings
0 = Counter is not halted
1 = Counter is halted
MC9328MX1 Reference Manual, Rev. 6.1
14-6
Freescale Semiconductor
Programming Model
Table 14-2. Watchdog Control Register Description (continued)
Name
Description
Settings
WT
Bits 14–8
Watchdog Time-Out Field—This 7-bit field contains the time-out
value and is loaded into the Watchdog counter after the service routine
has been performed. After reset, WT[6:0] must be written before
enabling the Watchdog.
Reserved
Bits 7–5
Reserved—These bits are reserved and should read 0.
WIE
Bit 4
Watchdog Interrupt Enable—Determines if the WDT_RST is
asserted or WDT_INT is asserted upon a watchdog time-out.
1 = Assert WDT_INT
0 = Assert WDT_RST
TMD
Bit 3
Test Mode Enable—Determines if WDOG timer is in test mode.
0 = Use 2 Hz clock as counter clock
1 = Use CLK32K as counter clock
SWR
Bit 2
Software Reset Enable—Determines if a software reset is enabled.
0 = Software reset is not enabled
1 = Software reset is enabled
WDEC
Bit 1
Watchdog Enable Control—Controls the write access of the WDE
bit.
0 = WDE bit is write once only
1 = WDE bit is write multiple
WDE
Bit 0
Watchdog Enable—Enables or disables the watchdog module. Write
once-only if WDEC bit is low. Write multiple if WDEC bit is high
0 = Disable Watchdog
1 = Enable Watchdog
Note:
Set to desired time-out value.
This bit is used only for test purposes
14.7.2 Watchdog Service Register
The Watchdog Service register contains the watchdog service sequence. When Watchdog is enabled, the Watchdog
requires that a service sequence be written to the Watchdog Service Register (WSR) as described in Table 14-3.
WSR
Addr
0x00201004
Watchdog Service Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WSR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 14-3. Watchdog Service Register Description
Name
Reserved
Bits 31–16
Description
Settings
Reserved—These bits are reserved and should read 0.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
14-7
Programming Model
Table 14-3. Watchdog Service Register Description (continued)
Name
Description
WSR
Bits 15–0
Settings
Watchdog Service Register—This 15-bit field contains the
watchdog service sequence.
Both writes must occur in the order listed prior to the time-out,
however any number of instructions can be executed between
the two writes.
The service sequence must be performed
as follows:
a) Write $5555 to the Watchdog Service
Register (WSR).
b) Write $AAAA to the Watchdog Service
Register (WSR)
14.7.3 Watchdog Status Register
The WSTR is a read-only register which records the source of the RESET_OUT event and interrupt status. It is
cleared by reset. It records the source of the RESET_OUT event and interrupt status. RESET_OUT can be
generated by the following sources which are listed in priority from highest to lowest: Power-on reset, External
reset (RESET_IN), and Watchdog Time-out.
.
WSTR
Addr
0x00201008
Watchdog Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
TINT
TYPE
TOUT
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 14-4. Watchdog Status Register Description
Name
Description
Reserved
Bits 31–9
Reserved—These bits are reserved and should read 0.
TINT
Bit 8
Time-Out Interrupt—Indicates whether the time-out
interrupt generated
Reserved
Bits 7–1
Reserved—These bits are reserved and should read 0.
TOUT
Bit 0
Time-Out—Indicates whether the watchdog timer times out.
Settings
0 = No time-out interrupt generated
1 = Time-out interrupt generated
0 = Watchdog timer does not time-out.
1 = Watchdog timer times out.
MC9328MX1 Reference Manual, Rev. 6.1
14-8
Freescale Semiconductor
Chapter 15
Analog Signal Processor (ASP)
The analog signal processor (ASP) module of the MC9328MX1 consists of an ADC for touch panel input.
15.1 Features
The ASP modules offers the following features:
•
9-bit PADC for touch panel and low voltage detection
•
On-chip voltage reference for ADC
•
12 × 16-bit FIFO for PADC sample
•
Embedded touch panel circuitry
•
Supports auto and manual sampling mode
•
Programmable pen down and pen-up interrupt to interrupt handler
•
Provides data-ready and FIFO-full interrupt to interrupt handler
•
True differential input
•
Support for temperature compensation by software
15.2 ASP Signal Description
The ASP system block diagram is shown in Figure 15-1 on page 15-2. It illustrates the operation of the individual
modules that comprise the ASP.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
15-1
ASP Signal Description
Voltage
Detect
Uip, Uin
PX1
PY1
SAMPLE RATE CTRL REG
U
PX2
From Touch
Panel
PEN CONTROL REGISTER
SWITCH CNRL
&
INPUT SELECT
LOGIC
X
SWITCH
CIRCUIT
COMPARE CONTROL REG
INPUT SELECT
PADC
PEN SAMPLE REG (12X16-bit)
Y
comp_int
PY2
touch_int
For Touch Interrupt Generation
pen_up_int
INTERRUPT
GENERATOR
pen_data_int
Figure 15-1. ASP System Block Diagram
Table 15-1. ASP Interface Signal Description
Signal Name
Description
Uip, Uin
External analog input signal (U-channel) to Pen ADC
PX1, PX2, PY1, PY2
Touch panel interface signals
MC9328MX1 Reference Manual, Rev. 6.1
15-2
Freescale Semiconductor
ASP Signal Description
U-channel -ve Input
Ru2
QVDD
Rref1
Ru1
QVDD
GND
U-channel +ve Input
RVP
RVM
UIP UIN
Rpd
SW1
SW3
SW2
SW4
PX1
PY1
Cd
USEL
Touch
Panel
USEL
R1A
Pen ADC
Rp1
MIP(+)
R1B
R2A
MIM(-)
PADC_OP
PADC_OM
AZSEL
Rp2
R2B
AZSEL
SW5
SW7
SW6
SW8
PX2
PY2
Read X: SW[8:1] = 1100 0110
Read Y: SW[8:1] = 0011 1001
Auto zero: SW[8:1] = 0000 0000
Auto Calibration X SW[8:1] = 1100 1100
Auto Calibration Y SW[8:1] = 0011 0011
Default: SW [8:1] = 0010 000
Figure 15-2. Simplified ASP Signal Path Diagram
Table 15-2. Simplified ASP Signal Path Parameters
Parameter
Description
Typical Value
Rp1, Rp2, Ru1, Ru2
Pen ADC Input Resister
200kOhm
Cd
Noise Decoupling Cap
0.01uF
Rpd
Pen-Down Detect Resister
100kOhm
Rref
Analog Reference Resister
40kOhm
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
15-3
Interrupt Generation
Table 15-2. Simplified ASP Signal Path Parameters
Parameter
Description
Typical Value
QVDD
ASP Power Supply
1.8V
GND
ASP Circuit Ground
0V
15.3 Interrupt Generation
The following interrupts are provided:
•
Pen Touch (pen down) Interrupt (IRQ number = 46)
It is generated upon pen down event, can be programmed for level trigger or edge
trigger.
•
Pen Data Compare Interrupt (IRQ number = 9)
Every pen sample is compared with a desired value. If it is greater than (or less
than, programmable) the desired value, an interrupt will be generated.
•
Pen-up Interrupt (IRQ number = 5)
In Auto XYU or ZXYU mode, with PUIE bit set, whenever a pen-up event is
detected, an interrupt signal is generated and sent to the interrupt controller.
•
Pen FIFO Data Ready Interrupt (IRQ number = 33)
It is generated whenever there is at least 1 valid data in the FIFO.
•
Pen FIFO Full Interrupt (IRQ number = 33)
15.4 Pen ADC (PADC) Operation
The Pen ADC, which has 9-bit accuracy, supports interfacing with a touch panel (X and Y-channel) and a low
voltage auxiliary input (U-channel). The sampling sequence as well as the sample rate is user selectable and is up
to 9.6kHz for U-channel input, and 1.2kHz for XYU + Auto Zero input.
There are 8 switches for the touch panel X and Y input signals, 2 switches for U-channel signal. In manual mode,
the switches are turned off/on per the input command from the Switch Control and Input Select Logic block. In
auto mode, they are controlled by a state machine, which is able to automatically generate proper switch settings to
select the target input signal for the PADC.
Sample data is stored into the Pen Sample FIFO, which is in 16-bit unsigned integer format. The FIFO is circular
buffer design, so if the data is not read fast enough, the FIFO will overflow and old data will be overwritten. When
an overflow occurs, the POV status bit is set in the Interrupt/Error Status Register.
MC9328MX1 Reference Manual, Rev. 6.1
15-4
Freescale Semiconductor
Pen ADC (PADC) Operation
Table 15-3. Pen ADC Operation
AUTO
PADE
MOD
AZE
Data Format in the
Pen Sample FIFO
Notes
1
1
00
Don’t Care
ADC idle
No A/D sample
01
0
X,Y,X,Y....
Only sample pen input, Disable U input
with auto-zero disabled
01
1
AZ,X,Y,AZ,X,Y....
Only sample pen input, Disable U input
with auto-zero enabled
10
0
X,Y,U,X,Y,U...
Sample pen input and U input with
auto-zero disabled
10
1
AZ,X,Y,U,AZ,X,Y,U,...
Sample pen input and U input with
auto-zero enabled
11
Don’t Care
U,U,U...
Only sample U input
Don’t Care
0
Don’t Care
Don’t Care
No valid data
Pen idle state
0
1
00
Don’t Care
ADC idle
No A/D sample
01
0
X
In this manual mode, only sample when
PADE is toggled from 0 to 1 by software.
01
1
AZ, X
10
0
Y
10
1
AZAZ, Y
11
Don’t Care
U
When the Pen A/D is configured for AUTO sampling, the sampling operation is carried out continuously allowing
the software to read the samples when either the Data Ready or ADC FIFO Full interrupts occur. In manual mode,
the AUTO bit is clear, the Pen ADC samples data only when the PADE bit is toggled from 0 to 1 by software.In
order to get next data, software should restore PADE bit to 0, then set it to 1.
15.4.1 Current-Mode Operation
The ADC is operated in current-mode. The output digital sample is proportional to the differential input current (Δ
i). Each of the input voltages (Vp, Vm) are converted to current (ip, im) by R1, R2, respectively. The other end of
the resister, R1a, R2b are clamped at 300 mV by internal circuitry.
Therefore:
•
ip = (Vp - V1a) / R1
•
im = (Vm - V2b) / R2
Where ip and im are limited to
•
-2.5µA ≤ ip ≤ +9.5µA
•
-2.5µA ≤ im ≤ +9.5µA
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
15-5
Pen ADC (PADC) Operation
Calculation for Δ i is as follows:
-12µA ≤ Δ i ≤ +12µA
Eqn. 15-1
As a result, the input range can be adjusted to fit different panels by tuning the resister value.
NOTE:
The voltage level at all input pins, including XY and U channel, must not exceed
QVDD—that is, 1.8 V.
15.4.2 Sample Rate Control
Table 15-4 shows the maximum PADC sample rates.
Table 15-4. Pen ADC Maximum Sample Rate
MODE (Auto)
DMCNT
IDLECNT
DSCNT
Maximum
Sample Rate
ZXY
0
0
1
1.5 kHz
ZXYU
0
0
1
1.1 kHz
U
0
0
0
9.6 kHz
idle
idle
idle
t3
t1
t2
data Z
into
FIFO
data X
into
FIFO
data Y
into
FIFO
data U
into
FIFO
data Z
into
FIFO
data X
into
FIFO
data Y
into
FIFO
data U
into
FIFO
t1 = Transistor switching and input selecting set up time, controlled by DSCNT
t2 = Data setup time, controlled by DSCNT and DMCNT
t3 = Point to point capture idle time, controlled by IDLECNT
Figure 15-3. Pen Input Sampling Timing
Figure 15-3 shows the sample timing when AUTO = 1, AZE = 1 and MOD [1:0] = 10.
The output data rate can be calculated using the equations shown in Table 15-5. The variables used in the equations
are fields of the Pen A/D Sample Rate Control Register (ASP_PSMPLRG).
MC9328MX1 Reference Manual, Rev. 6.1
15-6
Freescale Semiconductor
Pen ADC (PADC) Operation
•
DSCNT (t1): Data setup count. This controls the time for the MUX and touch panel to settle. The max value
is 1.575ms at ACLK = 12MHz.
•
DMCNT (t2): Decimation count. This controls the number of samples to be averaged, which effectively
performs a simple comb filter as the second-stage decimation filter.
•
IDLECNT (t3): Idle count. This controls the idle time after each set of measurement. During the idle time,
all touch panel control switches are turned off, hence saving current consumption by the touch panel.
NOTE:
For channels X and Y, DSCNT must be at least 1 to allow sufficient settling time
of the touch panel and the MUX.
Table 15-5. Output Data Rate Equations
MOD
AZE
01
0
Equations for Output Data Rate
(X,Y,X,Y, …)
fclk
----------------------------------------------------------------------------------------------------------2 × ( DSCNT + DMCNT + 1 ) + IDLECNT
01
1
( DSCNT ≥ 1 )
(Z,X,Y,Z,X,Y, …)
fclk
-----------------------------------------------------------------------------------------------------------3 × ( DSCNT + DMCNT + 1 ) + IDLECNT
10
0
( DSCNT ≥ 1 )
(X,Y,U,X,Y,U, …)
fclk
----------------------------------------------------------------------------------------------------------3 × ( DSCNT + DMCNT + 1 ) + IDLECNT
10
1
( DSCNT ≥ 1 )
(Z,X,Y,U,Z,X,Y,U, …)
fclk
----------------------------------------------------------------------------------------------------------4 × ( DSCNT + DMCNT + 1 ) + IDLECNT
11
X
( DSCNT ≥ 1 )
(U,U,U, …)
fclk
-------------------------------------------------------------------------------------------------( DSCNT + DMCNT + 1 ) + IDLECNT
( DSCNT ≥ 0 )
The best value for the analog clock ACLK is 12 MHz, which can be controlled by the PADC_CLK field of the
Clock Divide Register. The decimation ratio of the filter is 1260, therefore fclk = ACLK/1260. When ACLK =
12 MHz, fclk will be 9.6 kHz.
Some examples are provided to illustrate how to calculate the output data rate:
1. If MOD [1:0] = 01 and AZE = 0, the X and Y channels are selected and the auto-zero measurement
is disabled. The maximum output data rate for each channel is 2.4 kHz when DSCNT = 1, DMCNT
= 0 and IDLECNT = 0.
To get a 200Hz output data rate, set DSCNT = 1, DMCNT = 0, IDLECNT = 44
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
15-7
Pen ADC (PADC) Operation
2. If MOD [1:0] = 10 and AZE = 1, all the channels are selected, with auto-zero measurement enabled.
Maximum output data rate for each channel is 1.2 kHz when DSCNT = 1, DMCNT = 0 and
IDLECNT = 0.
To get a 200Hz output data rate, set DSCNT = 1, DMCNT = 7 (for example, if the decimation ratio
= 8, IDLECNT = 12.
3. If MOD [1:0] = 11, only U channel is selected and the AZE bit is ignored. Maximum output data
rate is 9.6 kHz when DMCNT = 0 and IDLECNT = 0. DSCNT can be set to 0 as there is no need
for the settling time for the touch panel and MUX.
To get a 200Hz output data rate, set DSCNT = 0, DMCNT = 0, IDLECNT = 47.
15.4.3 Auto Zero Function
Due to the large amount of flicker noise in MOS devices which degrades ADC accuracy, an auto-zero
measurement method is introduced to store the flicker noise data during each set of measurements. This data will
be subtracted from the output sample, by the user’s software. It is recommended that the auto-zero measurement
always be enabled.
There are 2 options for the auto-zero point.
•
AZ_SEL = 1: this option includes the 200k resistors
•
AZ_SEL = 0: this option excludes the 200k resistors
15.4.4 Pen-Down Detection
The pen-down interrupt function is provided for idle mode configuration. In idle mode, PX1 is used as a trigger pin
for pen-down interrupt generation. PX1 is normally pulled-up to VDD by Rpd, while PY2 is pulled-down to GND
by SW6. When the pen is down, PX1 shorts to PY1 and then pulled to GND. A falling edge is produced which
triggers the interrupt circuit to generate a pen-down interrupt.
15.4.5 Pen-Up Detection (Method 1 - Compare Value)
Using this method, a pen up condition is detected by sample value comparison.
Because the sample value of pen up is always smaller than that of pen down; this property can be used to detect pen
up.
The value in the Compare Control Register is compared to every pen sample. If the sample is smaller than the
register value, an interrupt is generated. The user should set a compare value which lies between the pen-up and
minimum pen-down value. The compare value is panel-dependent and the user should experiment to determine the
optimum setting.
15.4.6 Pen Up Detection (Method 2 - Detect Rising Edge)
Using this method, a pen up condition is detected by sampling the level on PX1 pin, its trigger determined by level
going high. The method is similar to the one used for pen down detection.
This method is available only in Auto XYU or Auto ZXYU mode. During the time slot for U, the switches are
automatically configured to be the same as for pen down detection (idle mode), for example only SW6 is on. PX1
is normally pulled-down by SW6 when the pen touched the screen. When the pen is up, PX1 is released and pulled
up by the external resistor Rpd. When the level goes high it is reflected by PUIS bit in the interrupt status register.
MC9328MX1 Reference Manual, Rev. 6.1
15-8
Freescale Semiconductor
Programming Model
15.4.7 Temperature Compensation
In general, the characteristics of the ADC changes with temperature. In order to keep the ADC stable, either a
compensation circuit or a compensation algorithm is required. Since a temperature compensation circuit doesn’t
exist in the ASP, compensation needs to be done using software.
Auto calibration mode provides the necessary switch settings to help software to provide temperature
compensation.
Auto calibration mode is enabled by setting the ACAL bit and it works only in auto ZXY mode. The switch
settings for X are changed from C6 to CC; and Y is changed from 39 to 33. This connects the ADC +ve input to
QVDD; while the ADC -ve input is connected to GND. This results in a differential input voltage equal to QVDD,
which is fixed using an external regulator.
The Software calibration loop involves three steps:
1. At the beginning of panel calibration routine, enable auto ZXY + auto-calibration mode and get samples for X
and Y. Store the AZ corrected samples in memory for use as a principle reference. Then disable the auto calibration
mode and return to normal modes for sampling.
2. Every time a pen down condition is detected, or at regular time intervals, repeat step 1 to get an updated
reference sample for X & Y. Compare the sample value with the principle reference taken in step 1 to determine
the percentage change.
3. During normal sampling, apply the calculated percentage changes to AZ corrected samples. This will
compensate for the effect of temperature drift on the ADC gain.
15.5 Programming Model
The ASP module includes eight 32-bit registers. Table 15-6 summarizes these registers and their addresses.
Table 15-6. ASP Module Register Memory Map
Description
Name
Address
ASP Control Register
ASP_ACNTLCR
0x00215010
Pen A/D Sample Rate Control Register
ASP_PSMPLRG
0x00215014
Compare Control Register
ASP_CMPCNTL
0x00215030
Interrupt Control Register
ASP_ICNTLR
0x00215018
Interrupt/Error Status Register
ASP_ISTATR
0x0021501C
Pen Sample FIFO
ASP_PADFIFO
0x00215000
Clock Divide Register
ASP_CLKDIV
0x0021502C
ASP FIFO Pointer Register
ASP_FIFO_PTR
0x00215034
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
15-9
Programming Model
15.5.1 ASP Control Register
The Control Register determines the configuration of PADC block.
ASP_ACNTLCR
BIT
31
30
29 28
27
26
25
24
ASWB ACAL CLKEN
TYPE
Addr
0x00215010
Control Register
23
22
SWRST
21
20
U_SEL
AZ_SEL
19
18
17
16
r
r
r
r
rw
rw
rw
r
rw
r
rw
rw
r
r
r
r
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
3
2
1
0
PADE
BGE
RESET
0x0200
BIT
15
14
13 12
11
10
9
8
7
6
5
4
AZE
AUTO
MOD
SW8
SW7
SW6
SW5
SW4
SW3
SW2
SW1
rw
rw
rw rw
rw
rw
rw
rw
rw
rw
rw
rw
r
r
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TYPE
0
RESET
0x0000
Table 15-7. Control Register Description
Name
Description
Settings
Reserved
Bits 31–28
Reserved—These bits are reserved and should read 0.
ASWB
Bit 27
Auto Mode Switch Bypass—Controls the switch settings in Auto XY
mode with AZ off. When enabled, switch settings take the value of
SW[7...0], otherwise is determined by internal logic. This is only for ATE
test (debug) purpose.
1 = Bypass Enable. Switches are
set by SW[7:0]
0 = Bypass Disable. Switches are
set by internal logic
ACAL
Bit 26
Auto Mode Calibration—Enables/Disables switch settings for
auto-calibration in auto-ZXY mode. Switch settings for X / Y are changed
from C6 / 39, to CC / 33 respectively.
1 = Enable
0 = Disable
CLKEN
Bit 25
Clock Enable—Enables/Disables the clock into the Pen ADC clock
generator. This is used to save power when the Pen ADC is not in use.
0 = Disable clock into the ADC
clock generator
1 = Enable clock into Pen ADC
clock generator
Reserved
Bit 24
Reserved—This bit is reserved and should read 0.
SWRST
Bit 23
Software Reset—Resets the entire ASP module. All ASP registers will
be restored to default value upon reset.
Reserved
Bit 22
Reserved—This bit is reserved and should read 0.
U_SEL
Bit 21
U-Channel Resistor Selection—Selects which external resistor to use
for U-channel measurement.
0 = No effect
1 = Reset -This automatically
restores to 0
0 = Resistor at UIN and UIP pins
1 = Resistor at R1a and R2a pins
MC9328MX1 Reference Manual, Rev. 6.1
15-10
Freescale Semiconductor
Programming Model
Table 15-7. Control Register Description (continued)
Name
Description
Settings
AZ_SEL
Bit 20
Auto-Zero Position Selection—Selects the position of auto-zero
measurement.
Reserved
Bits 19–16
Reserved—These bits are reserved and should read 0.
AZE
Bit 15
Auto-Zero Enable—Enables/Disables the auto-zero measurement.
0 = No auto-zero measurement
1 = Auto-zero measurement taken
before every pin input
measurement
AUTO
Bit 14
Auto Sampling—Enables/Disables Pen A/D auto sampling function.
When set, transistor switches are sampled for selected analog inputs X,
Y, or U. This process repeats when the IDLE counter reaches zero. In
AUTO mode, the IDLE counter is reloaded when it reaches zero.
0 = Auto sampling off (Manual
mode sampling is selected)
1 = Auto sampling on
MOD
Bits 13–12
Mode—Selects the analog input signals for A/D sampling dependent on
AUTO bit setting. See Table 15-3.
00 = No input signal selected
01 = Auto XY, or Manual X
10 = Auto XYU, or Manual Y
11 = selects only U
SW8
Bit 11
Switch Control—Turns the transistor switches on/off when the AUTO
function is off or when the Pen A/D is off in touch panel idle state.
0 = Transistor off
1 = Transistor on
SW7
Bit 10
In manual modes, switches are set according to the configuration of
SW[8...1] bits.
SW6
Bit 9
In auto modes, switches are set by internal logic. SW[8...1] are ignored
and should be set to 0. Normal settings for sampling X is [11000110]; Y is
[00111001].
SW5
Bit 8
0 = Measurement taken without the
external resistor at the R1a
and R2a pins
1 = Measurement taken with the
external resistor at R1a and
R2a pins
Exception cases occur when ACAL bit or ASWB bits are set.
SW4
Bit 7
SW3
Bit 6
SW2
Bit 5
SW1
Bit 4
Reserved
Bits 3–2
Reserved—These bits are reserved and should read 0.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
15-11
Programming Model
Table 15-7. Control Register Description (continued)
Name
Description
Settings
PADE
Bit 1
Pen A/D Enable—Enables/Disables the Pen A/D Controller. This bit
must be set after all other control bits are set. After this bit is set, A/D
starts sampling. This bit must be cleared by software when the touch
penal is in idle state for power saving—that is, waiting for a pen interrupt.
When this bit is clear, it flushes the Pen Sample FIFO.
0 = Pen A/D disabled
1 = Pen A/D enabled
BGE
Bit 0
Voltage Reference Enable—Enables/Disables the voltage reference
circuit.
0 = Disable Voltage Ref
1 = Enable Voltage Ref
15.5.2 Pen A/D Sample Rate Control Register
The Pen A/D Sample Rate Control Register selects the sampling rate for touch pen input. Each application may
require different pen input sampling rates. The maximum A/D sampling rate is limited by the A/D design and the
input signal data setup time. The design is targeted to support up to a 200 Hz data rate for each input signal. The
user must set the data setup time and idle time for power saving.
ASP_PSMPLRG
Addr
0x00215014
Pen A/D Sample Rate Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0X0000
BIT
15
14
13
12
DMCNT
TYPE
11
10
9
8
BIT_SELECT
IDLECNT
DSCNT
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0X0000
Table 15-8. Pen A/D Sample Rate Control Register Description
Name
Reserved
Bits 31–15
Description
Settings
Reserved—These bits are reserved and should read 0.
MC9328MX1 Reference Manual, Rev. 6.1
15-12
Freescale Semiconductor
Programming Model
Table 15-8. Pen A/D Sample Rate Control Register Description (continued)
Name
Description
Settings
DMCNT
Bits 14–12
Decimation Ratio Count—Controls the decimation
ratio of the second-stage FIR. Input clock to this
counter is fclk.
000 = Decimation ratio is 1
001 = Decimation ratio is 2
010 = Decimation ratio is 3
011 = Decimation ratio is 4
100 = Decimation ratio is 5
101 = Decimation ratio is 6
110 = Decimation ratio is 7
111 = Decimation ratio is 8
BIT_SELECT
Bits 11–10
Bit Select—Controls which bits to select from the FIR
output.
00 = 16 bits starting from 1st MSB of FIR output
01 = 16 bits starting from 2nd MSB of FIR output
10 = 16 bits starting from 3rd MSB of FIR output
11 = 16 bits starting from 4th MSB of FIR output
IDLECNT
Bits 9–4
Idle Count—Controls the number of clocks between
the last capture and the first capture of two pen input
points. Input clock to this counter is fclk.
0x00 = 0 clock
0x01 = 1 clock
...
0x3F = 63 clocks
DSCNT
Bits 3–0
Data Setup Count—Controls the input signal data
set up time after the transistor switching circuit and
input select are settled. Input clock to this counter is
fclk.
0000 = 0 clock
0001 = 1 clocks
...
1111 = 15 clocks
15.5.3 Compare Control Register
The Compare Control Register is used to detect the out-of-range samples on the selected input. Typical application
of this function is to detect a pen-up event, or to serve as an alarm when the external input is beyond a specific
range.
ASP_CMPCNTL
BIT
TYPE
31
30
Addr
0x00215030
Compare Control Register
29
28
27
26
25
24
23
22
21
20
19
18
INT
CC
17
16
INSEL
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0X0000
BIT
15
14
13
12
11
10
9
8
COMPARE VALUE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0X0000
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
15-13
Programming Model
Table 15-9. Compare Control Register Description
Name
Description
Settings
Reserved
Bits 31–20
Reserved—These bits are reserved and should read 0.
INT
Bit 19
Interrupt Status—Sets when a trigger event is
detected. Write 1 to clear.
0 = No trigger event was detected
1 = A trigger event was detected
CC
Bit 18
Compare Control—Controls the compare operation.
0 = Trigger when the compare value is
greater than the sample
1 = Trigger when the sample is greater
than the compare value
INSEL
Bits 17–16
Input Select—Selects the input samples to compare
with.
00 = No compare, interrupt disabled
01 = Channel X
10 = Channel Y
11 = Channel U
COMPARE VALUE
Bits 15–0
Compare Value—Contains the value to compare with the selected sample.
15.5.4 Interrupt Control Register
The Interrupt Control Register enables and controls each interrupt function. All interrupts are grouped into one of
the two outputs to the system interrupt handler: TOUCH_INT and PEN_DATA_INT.
ASP_ICNTLR
Addr
0x00215018
Interrupt Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0X0000
BIT
15
14
13
12
11
10
9
8
7
PUIE
TYPE
POL EDGE PIRQE
PFFE PDRE
r
r
r
r
r
r
r
r
r
rw
rw
rw
r
r
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0X0000
Table 15-10. Interrupt Control Register Description
Name
Reserved
Bits 31–11
Description
Settings
Reserved—These bits are reserved and should read 0.
MC9328MX1 Reference Manual, Rev. 6.1
15-14
Freescale Semiconductor
Programming Model
Table 15-10. Interrupt Control Register Description (continued)
Name
Description
Settings
PUIE
Bit 10
Pen-up Enable - Enables/Disables Pen-up Interrupt signal.
The interrupt request no. is 5
0 = Disable
1 = Enable
Reserved
Bits 9–7
Reserved—These bits are reserved and should read 0.
POL
Bit 6
Pen Interrupt Polarity—Selects the polarity of the TOUCH_INT input signal
for interrupt trigger.
0 = Active low, or falling edge
1 = Active high, or rising edge
EDGE
Bit 5
Edge Enable—Selects edge or level trigger on the TOUCH_INT input signal.
0 = Level trigger
1 = Edge trigger
PIRQE
Bit 4
Pen Interrupt Enable—Enables/Disables generation of the pen interrupt
signal, TOUCH_INT.
0 = Disable
1 = Enable
Reserved
Bits 3–2
Reserved—These bits are reserved and should read 0.
PFFE
Bit 1
Pen FIFO Full Interrupt Enable—Enables/Disables the pen sample FIFO
full interrupt.
0 = Disable
1 = Enable
PDRE
Bit 0
Pen Data Ready Interrupt Enable—Enables/Disables the pen sample ready
interrupt.
0 = Disable
1 = Enable
15.5.5 Interrupt/Error Status Register
The Interrupt/Error Status Register shows the source of interrupts when there is an interrupt event. Each
interrupt status bit in this register can be cleared by either writing 1 to it or by reading/writing the
associated data register, depending on the nature of interrupt.
ASP_ISTATR
Addr
0x0021501C
Interrupt/Error Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
PFF
PDR
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
PUIS
TYPE
7
6
POV
PEN
r
r
r
r
r
r
r
r
rw
rw
r
r
r
r
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0X0000
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
15-15
Programming Model
Table 15-11. Interrupt/Error Status Register Description
Name
Description
Settings
Reserved
Bits 31–11
Reserved—These bits are reserved and should read 0.
PUIS
Bit 10
Pen-up Status—Bit is set when a pen-up event is pending.
Clear by writing 1.
Reserved
Bits 9–8
Reserved—These bits are reserved and should read 0.
POV
Bit 7
Pen Sample Data Overflow—Indicates whether there has been
a pen sample data overflow in the Pen Sample FIFO. It will not
generate an interrupt on overflow. It is recommended that
software clear this bit at the beginning of a pen capture and
check for an error at the end of a stroke. Clear by writing 1.
0 = No overflow
1 = FIFO overflow
PEN
Bit 6
Pen Interrupt—Indicates that a pen touch interrupt is pending.
Clear by writing 1.
0 = No PEN interrupt is pending
1 = PEN interrupt is pending
Reserved
Bits 5–2
Reserved—These bits are reserved and should read 0.
PFF
Bit 1
Pen Sample FIFO Full—Indicates that the Pen Sample FIFO is
full. Reading the data in Pen Sample FIFO will clear this bit
automatically.
0 = Pen sample FIFO is not full
1 = Pen sample FIFO is full
PDR
Bit 0
Pen Data Ready—Indicates that at least one valid data sample
is available in the Pen Sample FIFO. Reading all the data in the
Pen Sample FIFO will clear this bit automatically.
0 = No valid data in pen sample
FIFO
1 = At least one valid data in the
pen sample FIFO
0 = No pen-up interrupt is pending
1 = Pen-up interrupt is pending
15.5.6 Pen Sample FIFO
The 12x16 Pen Sample FIFO holds the sample data after Pen A/D sampling. The data structure is
controlled by the MOD bits of control register.
ASP_PADFIFO
Addr
0x00215000
Pen Sample FIFO
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0X0000
BIT
15
14
13
12
11
10
9
8
7
SAMPLE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0X0000
MC9328MX1 Reference Manual, Rev. 6.1
15-16
Freescale Semiconductor
Programming Model
Table 15-12. Pen Sample FIFO Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
SAMPLE
Bits 15–0
Sample—Holds the sample data after Pen A/D sampling. The data structure is controlled by the
MOD bits of control register. The format of the pen sample data is a 16-bit unsigned word format.
15.5.7 Clock Divide Register
The Clock Divide Register controls the divide ratio for the ASP Clocks. The system clock is divided down
to generate the clocks for the pen ADC.
ASP_CLKDIV
Addr
0x0021502C
Clock Divide Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0X0000
BIT
15
14
13
12
11
10
9
8
PADC_CLK
TYPE
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0X0000
Table 15-13. Clock Divide Register Description
Name
Description
Reserved
Bits 31–5
Reserved—These bits are reserved and should read 0.
PADC_CLK
Bits 4–0
PADC Clock Divider—Selects the divide ratio to generate the
clock for use by the pen ADC.
Settings
0x00 = Clock disabled
0x01 = Divider ratio is 2
...
0x1F = Divider ratio is 32
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
15-17
Programming Model
15.5.8 ASP FIFO Pointer Register
Pen FIFO in the ASP module has the write pointer and read pointer reflected in this register.
ASP_FIFO_PTR
Addr
0x00215034
ASP FIFO Pointer Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BIT16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
BIT 0
RESET
0X0000
BIT
15
14
13
12
11
10
9
8
7
6
PEN_FIFO_READ_POINTER
TYPE
PEN_FIFO_WRITE_POINTER
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0X0000
Table 15-14. ASP FIFO Pointer Register Description
Name
Description
Reserved
Bits 31–5
Reserved—These bits are reserved and should read 0.
PEN_FIFO_READ_POINTER
Bits 7–4
PEN_FIFO_READ_POINTER—Holds the read pointer of PADC FIFO.
PEN_FIFO_WRITE_POINTER
Bits 3–0
PEN_FIFO_WRITE_POINTER—Holds the write pointer of PADC FIFO.
MC9328MX1 Reference Manual, Rev. 6.1
15-18
Freescale Semiconductor
Chapter 16
Bluetooth Accelerator (BTA)
This chapter describes the Bluetooth Accelerator (BTA) which, controlled by software running on the ARM core,
implements baseband protocols and other low-level link routines of the Bluetooth baseband.
This chapter covers the following main topics:
•
Bluetooth Primer
•
BTA Overview
•
Pin Configuration for BTA
•
Programming Model
IMPORTANT:
On-chip accelerator hardware is not supported by software. An external
Bluetooth chip interfaced to a UART is recommended.
16.1 Bluetooth Primer
Bluetooth is a short-range radio link intended to replace the cable connecting portable and/or fixed electronic
devices. Key features of Bluetooth technology are robustness, low complexity, low-power, and low cost.
Bluetooth operates in the unlicensed ISM band at 2.4 GHz and uses frequency hopping to combat interference and
fading. A symbol rate of 1 Mbps utilizing binary shaped FM modulation minimizes transceiver complexity. A
slotted channel is applied with a nominal slot length of 625 µs. For full duplex transmission, a time division duplex
scheme exchanges packets through the channel. Each packet is transmitted on a different hop frequency and
typically occupies a single slot, however can extend to a maximum of five slots.
A Bluetooth system provides a point-to-point connection (only two Bluetooth units involved), or a
point-to-multipoint connection where the channel is shared among several Bluetooth units. Two or more units
sharing the same channel (set of hopping frequencies) form a piconet. One Bluetooth unit acts as the master of the
piconet and any the other units act as slaves. A maximum of seven slaves can be active in the piconet, and many
more slaves can remain locked to the master in a so-called parked state. Parked slaves cannot be active on the
channel, however remain synchronized to the master.
Multiple piconets with overlapping coverage areas form a scatternet. Each piconet has a single master, and a master
in one piconet can serve as a slave in another piconet. Slaves can participate in different piconets on a time-division
multiplex basis. The piconets are not synchronized in time or frequency.
A Bluetooth system consists of a radio unit, a link control unit, and a support unit for link management and host
terminal interface functions (see Figure 16-1 on page 16-2). The radio, link controller, and link manager are
described in the Specification of the Bluetooth System, version 1.1.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-1
BTA Overview
16.2 BTA Overview
Figure 16-2 on page 16-3 shows the functional blocks of the BTA and its internal signals or connections.
BTA core features include:
•
Low level baseband processing engine featuring:
— Packet assembler/disassembler
— HEC and CRC generation and checks
— Encryption/decryption
— Whitening/de-whitening
— 1/3 FEC and 2/3 FEC encoding/decoding
•
Hop frequency selection co-processing module
•
32 words (of 16 bits each) bit buffer (Rx and Tx buffer)
•
Maintenance of native/estimated Bluetooth clocks
•
Access code correlation with bit/frame timing extraction
•
Programmable RF controller supports two front ends, including:
— MC13180
— Silicon Wave (SiW 1502)
•
SPI controller interface to RF front ends
•
Joint detection for timing, frequency, and packet synchronization and Maximum Likelihood Sequence
Estimation (MLSE/JD) pre-processor for improved RF performance
•
Bluetooth Application Timer (BAT)
•
Low-power support
•
IP-bus interface (16-bit Blue-line Standard, version 2.0)
2.4 GHz
Bluetooth Radio
Bluetooth
Link Controller
Bluetooth
Link Manager
and I/O
Figure 16-1. Functional Blocks in a Bluetooth System
MC9328MX1 Reference Manual, Rev. 6.1
16-2
Freescale Semiconductor
Module Descriptions
IP Bus I/F
Wake-Up Timer
Wake-Up 1
Wake-Up 2
Comp.
Comp.
Wake-Up 3
IP Bus Interface
Wake-Up
Counter
32 kHz
Clock
Comp.
Bluetooth Core
Bit Buffer
Correlator
Access Code
IP Interface
Threshold
Trigger
• Interface Control
• Bus Buffering
• Multi Clock Sync
Comp.
Co-Processor
Controller
• Freq. Hop Generator
• Control FSM
• Native Clock
• Estimated Clock
• Bit and Frame Timing
• Interrupt Generation
BitBuf
Timer
• BT App. Timer
Radio Interface
Bluetooth Pipeline
HEC,
CRC
Encrypt
White
FEC
DSP
• SPI
• μWire
• Programmable RF I/O
• PWM and RSSI
• TxPower PWM
Figure 16-2. Functional Blocks in the Bluetooth Accelerator
The main blocks include the Bluetooth pipeline, a bit buffer, the correlator functions, a wake-up timer, an IP bus
interface, a radio interface to an external radio, a co-processor for hop frequency generation, and a Bluetooth
application timer. The following sections contain an in-depth explanation of each block.
16.3 Module Descriptions
16.3.1 Bluetooth Core
The Bluetooth core implements low level time critical baseband routines. Through the IP bus, a number of registers
in the Bluetooth core can be accessed to write to the control words and to retrieve the status of the Bluetooth core.
Within the Bluetooth core, the main functional blocks are:
•
IP bus interface
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-3
Module Descriptions
•
Sequencer
•
Bluetooth pipeline processor
•
Bit buffer
•
Correlator
•
Application timer
•
Hop Selection Co-Processor
•
Radio control
16.3.1.1 IP Bus Interface
The Bluetooth core interfaces to the IP 2.0 bus. The IP bus clock (ips_cont_clk) ranges from 24 MHz to 100 MHz.
Running the clock outside of these ranges will cause the interface to fail due to internal synchronization logic.
The IP bus clock is faster than, and out of phase with, the internal 8 MHz clock. The Bluetooth module inserts
dynamic wait states to synchronize the IP bus clock with this internal clock. Table 16-1 shows the recommended
settings for inserting dynamic wait-states into the internal read and write cycles (by using the ips_xfr_wait signal)
to complete the read/write cycle. Refer to Section 16.5.9.1, “Clock Control Register.”
Table 16-1. CLK_CONTROL Register Settings for Synchronization
BT1_CLK_IN_DIV Value
ips_clk (MHz)
BT1_WSLOT Value
BT1_RSLOT Value
16
24
2
2
32
2
2
40
4
4
48
4
4
64
4
6
80
6
2, (6)
96
6
2, (6)
24
4
4
32
4
4
40
4
2
48
2
2
64
3
3
80
3
2, (3)
96
3
2, (3)
24
MC9328MX1 Reference Manual, Rev. 6.1
16-4
Freescale Semiconductor
Module Descriptions
Table 16-1. CLK_CONTROL Register Settings for Synchronization (continued)
BT1_CLK_IN_DIV Value
ips_clk (MHz)
BT1_WSLOT Value
BT1_RSLOT Value
32
16
6
6
24
C
C
32
9
3
40
9
3
48
B
3
64
3
3
80
7
6, (7)
96
6
6, (7)
16.3.1.2 Sequencer
The sequencer is the main controller in the Bluetooth core. The sequencer handles all timing and synchronization
of all the other BTA units. The sequencer provides control over the following units:
•
Bluetooth clocks
•
Interrupt generation
•
Top-level Bluetooth pipeline
•
Bit and frame timing
The pipeline control and bit and frame timing is handled by the Bluetooth pipeline processor, which is discussed in
Section 16.3.1.3, “Bluetooth Pipeline Processor.”
16.3.1.2.1 Bluetooth Clocks
For Bluetooth packet timing purposes, the Bluetooth core maintains two internal clocks: NativeClk and
EstimatedClk. The Bluetooth related clocks and counters maintained by the Bluetooth core are listed in Table 16-2.
Table 16-2. Bluetooth Clocks and Counters
Name
Bit Size
Input Frequency
Precision
Purpose
NativeCount
12
8 MHz
High
Generate native 3.2 kHz SysTick.
EstimatedCount
12
8 MHz
High
Generate estimated 3.2 kHz SysTick of a remote
master. The count is updated each time the access
code is triggered unless a special override bit is set.
OffsetCount
12
8 MHz
High
Difference between NativeCount and
EstimatedCount.
NativeClk
28
3.2 kHz
Low (power down)
High (operation)
Free-running native clock of the unit. When the unit
is the master of a communication, the remote slave
must synchronize to this clock.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-5
Module Descriptions
Table 16-2. Bluetooth Clocks and Counters (continued)
Name
Bit Size
Input Frequency
Precision
Purpose
EstimatedClk
28
3.2 kHz
Low (power down)
High (operation)
Estimate of the remote master’s NativeClk. Set by
software and updated by the EstimatedCount.
OffsetClk
28
3.2 kHz
Low (power down)
High (operation)
Difference between NativeClk and EstimatedClk.
This is updated each SysTick.
When the unit is the master of a piconet, its NativeClk is used for timing of slots, hopping frequency sequence,
whitening/de-whitening initialization, and so on.
NativeClk is a free-running 28 bit counter updated at a frequency of 3.2 kHz. The 3.2 kHz clock is generated by
dividing the high precision 8 MHz clock by 2,500 using a 12-bit counter (NativeCount). Bluetooth specifications
stipulate that, in connection states of high activity, a worst case accuracy of ± 20 ppm is expected for the native
clock. In low-power states (Standby, Hold or Park modes), a relaxed accuracy of ± 250 ppm is allowed.
NOTE:
When temperature drift and aging are taken into account, the requirement of the
high precision clock is more likely to be around ± 10 ppm.
EstimatedClk is a clock that is maintained by the unit when it operates as a slave, and it keeps track of a remote
master’s NativeClk. During a page scan, when the slave unit receives an access code trigger from the master, it
presets the EstimatedCount with an expected count and sets the two least significant bits of EstimatedClk to “00.”
This value causes the unit to respond 625 µs later, relative to the beginning of the time slot, regardless of whether it
receives the first or second page within the time slot.
Later in the link setup, the EstimatedClk is updated with the remote master’s native clock, which is sent in the FHS
packet. EstimatedClk is incremented by the EstimatedCount. During active connection state, whenever the access
code is triggered from the master’s transmission, EstimatedCount is updated with an expected count, therefore
preventing the EstimatedClk from drifting away from the remote master’s NativeClk.
A third value, OffsetClk, maintains the difference between EstimatedClk and NativeClk. OffsetClk is updated at
every NativeClk tick. Writing to the OFFSET_CLK_LOW and OFFSET_CLK_HIGH registers will update
EstimatedClk with the sum of NativeClk and OffsetClk on the next NativeClk tick.
16.3.1.2.2 Interrupt Generation
The Bluetooth core provides three interrupt lines:
1. A combination of three interrupts that are Logical-OR’ed together into a single active-high wire. This
one-shot interrupt is termed “BTsys.”
2. An interrupt triggered by the Bluetooth application timer termed “BTtim.”
3. An interrupt generated during the wake-up sequence termed “BTwui.”
The interrupts are summarized and described in Table 16-3 on page 16-7.
MC9328MX1 Reference Manual, Rev. 6.1
16-6
Freescale Semiconductor
Module Descriptions
Table 16-3. Bluetooth Core Interrupts
Interrupt Type
Frequency
Description
SysTick
3.2 kHz (fixed)
SysTick is the main Bluetooth heartbeat. The phrase depends on whether
the NativeClk (when unit is the master) or EstimatedClk (when unit is the
slave) is used.
EndOfHeader (EOH)
800 Hz (max)
EOH interrupts are issued after a header has been decoded during
receive of certain types of packets. For ID, NULL and POLL packets, no
interrupt is generated. For HVx and FHS packets, an interrupt is
generated after the packet header (because packet length is fixed). For
DMx, DHx, AUX and DV packets, an interrupt is generated after the
payload header has been decoded. This interrupt is maskable via the
COMMAND Register.
EndOfFrame (EOF)
1.6 kHz (max)
Generated after any received or transmitted frame. This interrupt is
maskable via the COMMAND Register.
BTtim
BTtimer
–
User programmable Bluetooth application-specific timer.
BTwui
BT wakeup 2
–
Interrupt that occurs during the wakeup sequence. The interrupt is
generated when the PLL is enabled and when it has stabilized.
BTsys
BT wakeup 3
16.3.1.3 Bluetooth Pipeline Processor
The Bluetooth core contains a Bluetooth pipeline in which all low-level processing is handled in dedicated
hardware. The pipeline units are controlled by the sequencer, however each unit contains an additional, small
controller to perform its function independently. The units communicate via a dedicated serial wire. The control is
handled by a request/acknowledge scheme when data is available. The pipeline contains the following four units:
•
HEC/CRC generator and checker
•
Encryption and decryption engine
•
Whitening and de-whitening logic
•
FEC coding and decoding
The four units process incoming or outgoing Bluetooth packets. Figure 16-3 shows the format of a Bluetooth
packet.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-7
Module Descriptions
Single-Slot Packet
Multi-Slot Packet
2
1
5
2
1
9
4
L_CH
FLOW
LENGTH
L_CH
FLOW
LENGTH
Undefined
72
Bluetooth
Packet
OR
Access Code
AM_ADDR
3
54
Header
TYPE
4
0 to 2745
Payload
Header
FLOW ARQN SEQN
1
1
1
Payload
HEC
8
Figure 16-3. Bluetooth Packet Format
The packet type information is available from the payload header field, which is the first one or two bytes of the
payload depending on the packet type. The packet header and length information can be determined from this field.
The PACKET_HEADER and PAYLOAD_HEADER Registers hold header information. In transmit mode, these
registers are written. In receive mode, these registers are read.
Each of the subsections of the Pipeline Processor are discussed in detail in the next sections.
16.3.1.3.1 HEC/CRC Generator and Checker
The Header Error Correction (HEC) and Cyclic Redundancy Check (CRC) unit can be enabled or disabled by
software. If enabled, the unit operation depends on the direction of the bit stream transfer.
Transmit Function—When a Bluetooth packet is to be transmitted by the unit, the HEC/CRC unit performs the
following sequence of actions:
1. Generate the HEC for the packet header.
2. Generate the payload CRC based on the length supplied by software.
3. The software must specify the HEC/CRC initialization word by writing the initialization word to
the HECCRC_CONTROL register. The initialization word is derived from the Bluetooth clock. The
generation of the initialization word is described in the Specification of the Bluetooth System,
version 1.1.
4. Raise a flag to the sequencer after the last CRC bit has been encoded. This is used for zero stuffing
(when necessary) before FEC encoding.
Receive Function—When a Bluetooth packet is received, the HEC/CRC unit performs the following sequence of
actions:
1. Extract the type and length information from the bit stream. This information is used to control the
remaining parts of the bit stream.
MC9328MX1 Reference Manual, Rev. 6.1
16-8
Freescale Semiconductor
Module Descriptions
The type information is available from the packet header and length information fields in the payload header
field, which is the first one or two bytes of the payload, depending on the packet type. The CRC is the last
16 bits in the bit stream. The length information indicates the number of bytes in the payload excluding the
payload header and the CRC code.
2. Evaluate the HEC.
3. Calculate the CRC.
If the HEC/CRC unit reads an erroneous type or length field because of channel errors, the Bluetooth core
will decode the stream incorrectly. The software must detect this condition by reading the HEC and CRC
status from the STATUS register and act accordingly.
NOTE:
Errors in the type information field will probably be detected by the HEC check.
The length information field cannot be validated until the CRC has been received.
Table 16-4 shows the relationship between packet types and the type of coding they imply. This information is
encoded into a look-up table used in the controller.
Table 16-4. Packet Types and FEC/CRC Processing
Packet
Type
Length
CRC Enabled
1/3 FEC
Enabled
2/3 FEC
Enabled
NULL
0000
5
Disabled
Disabled
Disabled
POLL
0001
5
Disabled
Disabled
Disabled
FHS
0010
5
Enabled
Disabled
Enabled
DM1
0011
5
Enabled
Disabled
Enabled
DH1
0100
5
Enabled
Disabled
Disabled
HV1
0101
5
Disabled
Enabled
Disabled
HV2
0110
5
Disabled
Disabled
Enabled
HV3
0111
5
Disabled
Disabled
Disabled
DV
1000
5
Enabled1
Disabled
Enabled1
AUX1
1001
5
Disabled
Disabled
Disabled
DM3
1010
9
Enabled
Disabled
Enabled
DH3
1011
9
Enabled
Disabled
Disabled
_b
1100
92
Disabled
Disabled
Disabled2
_b
1101
92
Disabled
Disabled
Disabled2
DM5
1110
9
Enabled
Disabled
Enabled
DH5
1111
9
Enabled
Disabled
Disabled
1.
CRC and 2/3 FEC are performed on the data field only.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-9
Module Descriptions
2.
Not defined in the standard yet.
16.3.1.3.2 Encryption and Decryption Engine
The encryption engine handles all low-level time-critical Bluetooth security functions for encryption and
decryption of user information (payload only). The key bit stream uses a method derived from the summation
stream cipher generator attributable to Massey and Rueppel. Encryption and decryption are carried out without
intervention from the Bluetooth core.
The encryption engine uses a local controller to perform initialization and runtime control. Encryption is enabled
by software copying the CRC polynomial to the BTA. This task consists of writing thirteen 16-bit words in a row
to the ENCRYPTION_CONTROL_X13 register. When the last word has been written, the engine starts initializing
the registers as specified in the standard. The sequence takes 240 cycles to complete. When this sequence is
complete, the encryption engine is armed and ready to perform encryption/decryption on the payload in the
following slot.
IMPORTANT:
During the initialization cycle, the BTA uses LW0 and LW1 in the bit buffer (see
Section 16.3.1.4, Bit Buffer) to store temporary information. Any information
stored in LW0 and LW1 will be overwritten.
Initialization of the encryption engine requires an encryption key, the Bluetooth address of the master and clock
information. The sequence to be written into the engine during initialization is shown in Table 16-5 and the
nomenclature used in the table is as follows:
•
CL[0] contains CL7-0, CL[1] contains CL15-8 and CL[2] contains CL23-16. (see the Specification of the
Bluetooth System v. 1.1)
•
CL0 through CL25 correspond to CLK1 through CLK26 of the currently used clock; that is, CL0-25 equal
CLK1-26 right-shifted by one.
•
Kc’[0] though Kc’[15] specify the 128 bit encryption key.
•
Addr[0] through Addr[5] are the Bluetooth address (BD_ADDR) of the master.
If no initialization value is written to the unit, encryption is disabled.
Table 16-5. Writing Sequence for Encryption Engine Initialization
Word Number
Bits 15–8
Bits 7–0
0
Kc’[1]
Kc’[0]
1
Kc’[3]
Kc’[2]
2
Kc’[5]
Kc’[4]
3
Kc’[7]
Kc’[6]
4
Kc’[9]
Kc’[8]
5
Kc’[11]
Kc’[10]
6
Kc’[13]
Kc’[12]
7
Kc’[15]
Kc’[14]
MC9328MX1 Reference Manual, Rev. 6.1
16-10
Freescale Semiconductor
Module Descriptions
Table 16-5. Writing Sequence for Encryption Engine Initialization (continued)
Word Number
Bits 15–8
Bits 7–0
8
Addr[1]
Addr[0]
9
Addr[3]
Addr[2]
10
Addr[5]
Addr[4]
11
CL[1]
CL[0]
12
111000CL25CL24
CL[2]
16.3.1.3.3 Whitening/De-Whitening
According to the Bluetooth specifications, all packets must be scrambled to randomize the data from highly
redundant patterns and to minimize DC bias in the packet. The whitening unit performs this scrambling
(whitening) and descrambling (de-whitening) of the packet header and payload (including the CRC) during
transmit and receive.
Whitening is enabled or disabled by software. To enable whitening, write the initialization word specified in the
Bluetooth standard to the WHITE_CONTROL register. To disable, write all zeros to the same register. There is no
status information available for the whitening/de-whitening unit.
16.3.1.3.4 FEC Coding/Decoding
The forward error correction (FEC) is a standard block encoder/decoder algorithm. Two forms of FEC are used in
the Bluetooth standard:
•
1/3 FEC: Repeating each bit so that each bit occurs three times in a row. Simple majority decision is used
in decoding—that is, if two or more bits are equal, the value of these bits is used.
•
2/3 FEC: Using a (15, 10) shortened Hamming code with a minimum distance of 4. This encoding allows
correction of one-bit errors and detection of two-bit errors. For each block of 10 bits, 5 redundant bits are
appended. In the receive decoding, the BTA checks each 15 bit block for errors and sets the REC2 and
NREC flags in the status register accordingly.
FEC can be enabled or disabled by software according to the packet type.
16.3.1.4 Bit Buffer
The bit buffer is a 512-bit memory bank used for four different purposes. It is software accessible, and is arranged
as eight 64-bit “long words,” designated LW0 through LW7. Software views each long word as four concatenated
16 bit words that are accessed independently. Figure 16-4 illustrates the arrangement of the long words in the bit
buffer.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-11
Module Descriptions
Bit 63
Bit 0
LW0 (64 Bits)
Word 3 (16 bits)
Word 2 (16 bits)
Word 1 (16 bits)
Word 0 (16 bits)
Bit 127
Bit 64
LW1 (64 Bits)
Word 7 (16 bits)
Word 6 (16 bits)
Word 5(16 bits)
Word 4 (16 bits)
Bit 191
Bit 128
LW2 (64 Bits)
Word 11 (16 bits)
Word 10 (16 bits)
Word 9 (16 bits)
Word 8 (16 bits)
Bit 255
Bit 192
LW3 (64 Bits)
Word 15 (16 bits)
Word 14 (16 bits)
Word 13 (16 bits)
Word 12 (16 bits)
Bit 319
Bit 256
LW4 (64 Bits)
Word 19 (16 bits)
Word 18 (16 bits)
Word 17 (16 bits)
Word 16 (16 bits)
Bit 383
Bit 320
LW5 (64 Bits)
Word 23 (16 bits)
Word 22 (16 bits)
Word 21 (16 bits)
Word 20 (16 bits)
Bit 447
Bit 384
LW6 (64 Bits)
Word 27 (16 bits)
Word 26 (16 bits)
Word 25 (16 bits)
Word 24 (16 bits)
Bit 511
Bit 448
LW7 (64 Bits)
Word 31 (16 bits)
Word 30 (16 bits)
Word 29 (16 bits)
Word 28 (16 bits)
Figure 16-4. BitBuf Memory
The BTA uses time sharing to minimize the amount of hardware required. Time sharing of the bit buffer is feasible
because the functions requiring the module are active at different times during a receive or transmit function.
Table 16-6 lists the uses of the bit buffer and the number of bits used for each function. The order is chosen so that
the first function in the table function is the first in time to be executed.
Table 16-6. Functions Using the Bit Buffer
Function
Buffer Size (Bits)
Transmit
Receive
Encryption initialization
128
Used
Used
Correlation
512
Not used
Used
Receive
512
Not used
Used
Transmit
512
Used
Not used
Users must never access the contents of the bit buffer during the encryption initialization or correlation phases.
16.3.1.5 Correlator
The correlator performs correlation using eight times oversampling of the incoming bit stream to extract the bit
timing information and correlates against the 64-bit access code. The access code is written by software to BTA
registers SYNCH_WORD_0, SYNCH_WORD_1, SYNCH_WORD_2, and SYNCH_WORD_3.
The threshold for the correlator is programmable via the THRESHOLD register. The correlation peak value in the
most recent correlation window can be read from the same register.
Software access to the bit buffer is prohibited during correlation because of the bit buffer time sharing (see section
16.3.1.4).
MC9328MX1 Reference Manual, Rev. 6.1
16-12
Freescale Semiconductor
Module Descriptions
16.3.1.6 Bluetooth Application Timer
The Bluetooth core includes a 12-bit Bluetooth Application Timer (BAT) that can be configured to generate
periodic interrupts. The BAT is programmable via the Bluetooth Application Timer Register (BAT). When the
software writes a value to the BAT register, the timer is initialized to this value.
The BAT is clocked with the 8 MHz clock and is decremented by one at each clock tick. When the timer expires, a
“BTtim” interrupt is generated and the counter is automatically reloaded with the value written to the BAT register.
The “BTtim” interrupt can be masked via the ENABLE bit of the BAT register.
16.3.1.7 Hop Selection Co-Processor
The frequency selection scheme of the Bluetooth system consists of two parts:
•
Sequence Selection
•
Mapping of this sequence on the hop frequencies and the RF module frequency synthesizer programming
The hop selection co-processor is used to perform part of the computation that selects the hop frequency according
to the Bluetooth specifications. Software must complete the addition of F (specified in the Bluetooth
specifications) and must also perform the modulo operation.
The selection is initiated by writing to the HOP0 to HOP4 registers. Once the selection has been initiated, software
can read the result back from the HOP_FREQ_OUT register. The software must then complete the sequence
selection computation and map the selected channel to RF module frequency synthesizer programming parameters.
The sequence to be written into the co-processor is as shown in Table 16-7.
Table 16-7. Hop Selection Co-Processor Writing Sequence
Register Description
Register Name
Bits
Notes
Hop 0 (Frequency In) Register
HOP0
CLK_LOW
CLK15-0 of the used clock
Hop 1 (Frequency In) Register
HOP1
CLK_HIGH
CLK25-16 of the used clock
Hop 2 (Frequency In) Register
HOP2
LAPUAP_LOW
LAP15-0
Hop 3 (Frequency In) Register
HOP3
LAPUAP_HIGH
{UAP3-0, LAP 23-16}
Hop 4 (Frequency In) Register
HOP4
SYS, STATE
See Section 16.5.11.5, “Hop 4 (Frequency In)
Register,” on page 16-88
16.3.1.8 Radio Control
The radio interface supports two RF front ends:
•
Motorola Radio, MC13180, SPI Interface
•
SiliconWave Radio, SiW1502, SPI Interface
The selection of the used interface is determined via software by writing to the RF_CONTROL register. Table 16-8
on page 16-14 describes the interface of the Bluetooth pins to each of the RF front ends. Some pins are
configurable as inputs and outputs, depending on which radio module is used. The reset values are shown for the
output configurations.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-13
Module Descriptions
Table 16-8. Bluetooth Pin Mapping for Various Radio Interfaces
Name
Direction
Reset
MC13180
SiW1502
BT1
IN
—
Ref_Clk (In: 24 MHz)
Ref_Clk (In: 16 MHz)
BT2
Tri-State Out
Hi-Z
Tx_Data
TxData
BT3
In
—
Rx_Data
RxData
BT4
In
—
spi_data_in
SPI_TXD
BT5
In/Out
In
In: Frame_Synch
Out: PWM_RSSI
BT6
Out
Low
PWM_Tx/GPO1
Reset_RM
BT7
Out
Low
Diversity/BTRFOSC
Diversity/Enable_RM
BT8
Tri-State Out
Hi-Z
PWM_RSSI
TxEN
BT9
Out
Low
RxTx_en
HOP_STRB
BT10
Out
High
BTRFOSC/GPO2
BTRFOSC/GPO2
BT11
Out
High
spi_en
SPI_SS
BT12
Tri-State Out
Hi-Z
spi_data_out
SPI_RXD
BT13
Out
Low
spi_clk
SPI_CLK
16.3.1.8.1 Frequency Synthesizer and Timing Control
Data is written to the RF front ends through the SPI_WORD0, SPI_WORD1, SPI_WORD2, SPI_WORD3,
SPI_READ_ADDR and SPI_WRITE_ADDR registers. These registers are primarily used to program the frequency
synthesizer of the RF front-end. Depending on the RF front end used, only some of the six interface registers are
required.
In addition to the data interface, the Bluetooth core includes two registers, TIME_A_B and TIME_C_D, that are
used to specify the timing of control signals to the RF module. The time written to the these registers refer to the
number of µs before SysTick.
16.3.1.8.2 Pulse Width Modulators
RF control includes two pulse width modulators (PWMs) used to control transmit power and to generate the
Received Signal Strength Indicator (RSSI). Both PWMs are clocked by the 8 MHz clock providing a resolution of
125 ns. They share the same 6-bit PWM counter. The transmit PWM and RSSI PWM are enabled by the
PWM_TX_EN and RSSI_EN bits in the RF_CONTROL register respectively. When enabled, the PWM provides a
pulse resolution of 32 steps and cycle time of 8 µs. The desired transmit power is written to the PWM_TX register
while the RSSI value is written to the PWM_RSSI register.
MC9328MX1 Reference Manual, Rev. 6.1
16-14
Freescale Semiconductor
Module Descriptions
16.3.1.8.3 Radio Module Interfaces
MC13180 Radio (3 Wire SPI)
The MC13180 radio is programmed via a three wire serial programming interface (SPI) comprised of the spi_data,
spi_en, and spi_clk lines.
The BTA supports 16-bit SPI reads from and writes to the radio. The MC13180 radio registers are accessed via
register addresses. The BTA uses “burst” writes to the MC13180 radio by requiring that only the first of up to four
consecutive register addresses be specified.
Data is written to the MC13180 radio as follows:
1. Write up to four 16-bit words to the SPI_WORD0 through SPI_WORD3 registers. The data is
automatically buffered by the BTA and is not written to the radio until the address is specified in step
2.
2. Write the address of the first register to the SPI_WRITE_ADDR register. Once the address has been
written, the BTA writes the buffered data word(s) to the MC13180 radio one word at a time. The
radio increments the address of the radio register by one after each write.
The mapping of the data written to the SPI_WORD0 through SPI_WORD3 registers in the programming sequence
illustrated in Figure 16-5.
WRITE
SPI_W_Addr
READ
7
r/w Address (Bits 6-0)
don’t care
SPI_0
Word 0 (Bits 15-0)
SPI_1
Word 1 (Bits 15-0)
SPI_0
Low indicates write
SPI_Data
_In
Address
Word 0
don’t care
SPI_R_Addr
7
r/w Address (Bits 6-0)
Word 0 (Bits 15-0)
High indicates read
Word 1
SPI_Data
_In
SPI_Clk
SPI_Data
_Out
SPI_EN
SPI_Clk
Address
TriStated
Tri-Stated
Word 0
TriStated
SPI_EN
Figure 16-5. Programming Interfaces for the MC13180 Radio
Data is read from the MC13180 radio as follows:
1. Write the address of the first MC13180 register to be read to the SPI_READ_ADDR register. Once
the address has been written, the BTA retrieves data words from the MC13180 radio.
2. Read a 16 bit words from the SPI_WORD0 register.
The software must poll for the DONE flag in the SPI_STATUS register before reading or writing new data from or
to the SPI.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-15
Module Descriptions
Writing to the SPI_READ_ADDR or SPI_WRITE_ADDR register overrides any previous SPI address maintained
in that register by the Bluetooth core.
The timing of the MC13180 radio is shown in Figure 16-6 on page 16-16.
Software
writes to BTA
EOF/AAO/
Idle Mode
Time B
Software
writes to BTA
EOF/AAO/
Idle Mode
Time B
SPI_Data
SPI_Clk
SPI_En
RxTx_En
Tx_Data
Can be tristated, depending
on the RF_Control register
Can be tristated, depending
on the RF_Control register
Bluetooth packet data
Frame_Synch
Rx_Data
Bluetooth packet data
SysTick
Idle
SysTick
Tx
SysTick
Idle
Rx
Figure 16-6. Timing of the RF Module Control Signals for the MC13180 Radio
SiliconWave Radio (4 Wire SPI)
The SiliconWave radio is programmed via a four-wire serial programming interface (SPI) comprised of the
SPI_TXD, SPI_RXD, SPI_CLK, /SPI_SS. The definition of the signal direction is with reference to the Radio.
The BTA supports byte SPI reads from and writes to the radio. The SiliconWave radio registers are accessed via
register addresses. The BTA uses “burst” writes to the SiliconWave radio by requiring that only the first of up to
eight consecutive register addresses be specified.
Data is written to the SiliconWave radio as follows:
1. Write up to eight bytes to the SPI_WORD0 through SPI_WORD3 registers. The data is automatically
buffered by the BTA and is not written to the radio until the address is specified in step 2.
2. Write the address of the first register to the SPI_WRITE_ADDR register. Once the address has been
written, the BTA writes the buffered data word(s) to the SiWave radio one word at a time. The radio
increments the address of the radio register by one after each write.
MC9328MX1 Reference Manual, Rev. 6.1
16-16
Freescale Semiconductor
Module Descriptions
The mapping of the data written to the SPI_WORD0 through SPI_WORD3 registers in the programming sequence
illustrated in Figure 16-7.
Write
15
SPI_W_Addr
Read
7
r/w Command (Bit 14-8)
7
15
Address (Bit 7-0)
SPI_0
Byte 0 (Bit 15-8)
Byte 1 (Bit 7-0)
SPI_1
Byte 2 (Bit 31-24)
Byte 3 (Bit 23-16)
SPI_R_Addr
SPI_0
r/w
C omman d (Bit 1 4-8)
Byte 0 (Bit 15-8)
Hig h ind icates wri te
SPI_Data_In
Command,
Address
Address (Bit 7-0)
Byte 1 (Bit 7-0)
Lo w ind icates rea d
Byt e 0,1
B yt e 2, 3
Command,
Address
SPI_Data_In
SPI_Clk
SPI_Data_Out
SPI_EN
SPI_Clk
t ri-stated
Byte 0, 1
SPI_EN
Figure 16-7. Programming Interface for the SiWave Radio
Data is read from the SiliconWave radio as follows:
1. Write the address of the SiliconWave register to be read to the SPI_READ_ADDR register. After the
address has been written, the BTA retrieves data bytes from the SiliconWave radio.
2. Read up to two bytes from the SPI_WORD0 register.
The software must poll for the DONE flag of the SPI_STATUS register before reading or writing new data from or
to the SPI.
Writing to the SPI_READ_ADDR or SPI_WRITE_ADDR register overrides any previous SPI address maintained
in that register by the Bluetooth core.
The timing of the SiliconWave radio is shown in Figure 16-8.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-17
Module Descriptions
EOF/AAO/
IdleMode
Time B D
SW write to BTA
SW write to BTA
EOF/AAO/
IdleMode
Time B
SPI_RXD
(BT12)
SPI_CLK
(BT13)
/SPI_SS
(BT11)
RxT x_en
(BT9)
If T x_Tr _
i En =1 ( BUT BT 8 itself is n ot T RI ST AT ED
TxEn
(BT8)
Tx_data
( 1) Ca n be t ristated depe nding on RF_ Contro l Register
BT pa cket dat a
Sa me as (1)
BT packet data
Rx_data
SysTick
Idle
SysTick
Tx
Rx
Idle
Figure 16-8. Timing of RF Module Control Signals for the SiWave Radio
16.3.2 Wake-Up Module
The BTA provides a wake-up module for power saving operation. Figure 16-9 shows the block diagram of the
wake-up module.
WakeUp_1
compare
WakeUp_2
compare
BT1clkHold
WU_Count
WakeUp_delta4
BTRFOSC
+
WakeUp_4
compare
Figure 16-9. Block Diagram of the Wake-Up Module
The wake-up module consists of a wake-up counter clocked by a 32 kHz clock. The counter can be reset by
software by setting the CLR_CNT bit in the WU_CONTROL register.
MC9328MX1 Reference Manual, Rev. 6.1
16-18
Freescale Semiconductor
Module Descriptions
Power-down timing can be programmed via three wake-up registers. When the software specifies a power-down,
the wake-up counts must be set up by writing to the WAKEUP_1, WAKEUP_2, and WAKEUP_DELTA4
registers. The power-down process is then started by writing to the PDE bit in the WU_CONTROL register.
All three wake-up compare registers specify wake-up times in 31.25 µs units (31.25 µs is the reciprocal of 32 kHz).
The wake-up times indicate the elapsed time from when the power-down process is started (wake-up counter is
reset upon request). The wake-up events (WU1, WU2 and WU4) are generated when the WU_COUNT register
value equals their respective wake-up compare registers.
The three wake-up compare registers are used as follows:
1. After software determines that a power-down has to be performed, the WAKEUP_1 register specifies
the delay until the BTRFOSC and BT1ClkHold signals are asserted. The assertion of BTRFOSC
signals a power-down request to the oscillator source. Immediately after the activation of BTRFOSC
(which is synchronized with the Bluetooth master clock), BT1ClkHold is asserted. BT1ClkHold
results in a synchronized hold of the Bluetooth master clock. The actual stopping of the source clock
must not happen before BT1ClkHold is asserted.
2. The WAKEUP_2 register specifies the delay until BTRFOSC is deasserted, which is the actual
wake-up event. Once the BTRFOSC signal is deasserted, the source clock must be turned on.
3. The WAKEUP_4 register holds the value at which the Bluetooth clock is enabled again
(BT1ClkHold goes high). After receiving a WU2 event, WAKEUP_4 is updated with the sum of
the WU_COUNT and WAKEUP_DELTA4 registers. The WAKEUP_DELTA4 value defines the
amount of time that the oscillator needs to stabilize after having been turned on by the deassertion
of BTRFOSC. When the counter reaches the WAKEUP_4 value, the BT1ClkHold signal is de
asserted and the Bluetooth master clock is started.
Figure 16-10 shows the timing of the wake-up signals.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-19
Pin Configuration for BTA
Software w rites
to pow er dow n
an d clea rs co unt er
WU 1
W U2
W U4
Software cl ears
po wer-d own e nab le,
cou nter and i nterrup t
PD E
WakeUp_1
WU 1
WU 2
Wak eUp_2
About 4m s
WU_Count+Wak eUp_del ta4
WU 4
BT1C lkH old
BTR FOSC
About 1.2s
BTwui
Figure 16-10. Timing of the Wake-Up Signals
After resuming from a power down the total BT power-down time is determined from the difference between the
values in the WAKEUP_4 and WAKEUP_1 Registers.
The current value of the power-down counter can be read at any time from the WU_COUNT register.
An interrupt is generated at the end of the BT1ClkHold interval (on a WU4 event). In the interrupt, the PDE bit is
cleared, and the external wake-up signal source is removed.
16.4 Pin Configuration for BTA
There are 15 pins used for the BTA module. Of these, 13 pins are multiplexed with other functions on the device,
and must be configured for BTA operation.
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 32.5.1, “Data Direction Registers,” on
page 32-8 for details.
MC9328MX1 Reference Manual, Rev. 6.1
16-20
Freescale Semiconductor
Programming Model
Table 16-9. Pin Configuration
Pin
Setting
BT1
Primary function of
GPIO Port C [31]
1. Clear bit 31 of Port C GPIO In Use Register (GIUS_C)
Primary function of
GPIO Port C [30]
1. Clear bit 30 of Port C GPIO In Use Register (GIUS_C)
Primary function of
GPIO Port C [29]
1. Clear bit 29 of Port C GPIO In Use Register (GIUS_C)
Primary function of
GPIO Port C [28]
1. Clear bit 28 of Port C GPIO In Use Register (GIUS_C)
Primary function of
GPIO Port C [27]
1. Clear bit 27 of Port C GPIO In Use Register (GIUS_C)
Primary function of
GPIO Port C [26]
1. Clear bit 26 of Port C GPIO In Use Register (GIUS_C)
Primary function of
GPIO Port C [25]
1. Clear bit 25 of Port C GPIO In Use Register (GIUS_C)
Primary function of
GPIO Port C [24]
1. Clear bit 24 of Port C GPIO In Use Register (GIUS_C)
Primary function of
GPIO Port C [23]
1. Clear bit 23 of Port C GPIO In Use Register (GIUS_C)
Primary function of
GPIO Port C [22]
1. Clear bit 22 of Port C GPIO In Use Register (GIUS_C)
Primary function of
GPIO Port C [21]
1. Clear bit 21 of Port C GPIO In Use Register (GIUS_C)
Primary function of
GPIO Port C [20]
1. Clear bit 20 of Port C GPIO In Use Register (GIUS_C)
Primary function of
GPIO Port C [19]
1. Clear bit 19 of Port C GPIO In Use Register (GIUS_C)
BT2
BT3
BT4
BT5
BT6
BT7
BT8
BT9
BT10
BT11
BT12
BT13
Configuration Procedure
2. Clear bit 31 of Port C General Purpose Register (GPR_C)
2. Clear bit 30 of Port C General Purpose Register (GPR_C)
2. Clear bit 29 of Port C General Purpose Register (GPR_C)
2. Clear bit 28 of Port C General Purpose Register (GPR_C)
2. Clear bit 27 of Port C General Purpose Register (GPR_C)
2. Clear bit 26 of Port C General Purpose Register (GPR_C)
2. Clear bit 25 of Port C General Purpose Register (GPR_C)
2. Clear bit 24 of Port C General Purpose Register (GPR_C)
2. Clear bit 23 of Port C General Purpose Register (GPR_C)
2. Clear bit 22 of Port C General Purpose Register (GPR_C)
2. Clear bit 21 of Port C General Purpose Register (GPR_C)
2. Clear bit 20 of Port C General Purpose Register (GPR_C)
2. Clear bit 19 of Port C General Purpose Register (GPR_C)
16.5 Programming Model
The BTA module includes 93 user-accessible 32-bit registers. Only the lower 16 bits (bits 0-15) are used in each
register. For the Bluetooth Accelerator, the register behavior may change between write and read functions. For
clarification, when the behavior changes significantly, the same address is given two different names. Table 16-10
on page 16-22 summarizes these registers and their addresses. Table 16-11 on page 16-24 provides an alternate
view of the memory map.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-21
Programming Model
Table 16-10. BTA Module Register Memory Map
Description
Name
Address
Read/Write
COMMAND
0x00216000
Write
STATUS
0x00216000
Read
Packet Header Register
PACKET_HEADER
0x00216004
Write/Read
Payload Header Register
PAYLOAD_HEADER
0x00216008
Write/Read
NATIVE_COUNT
0x0021600C
Write/Read
ESTIMATED_COUNT
0x00216010
Write/Read
Offset Count Register
OFFSET_COUNT
0x00216014
Write/Read
Native Clock Low Register
NATIVECLK_LOW
0x00216018
Write/Read
Native Clock High Register
NATIVECLK_HIGH
0x0021601C
Write/Read
Estimated Clock Low Register
ESTIMATED_CLK_LOW
0x00216020
Write/Read
Estimated Clock High Register
ESTIMATED_CLK_HIGH
0x00216024
Write/Read
Offset Clock Low Register
OFFSET_CLK_LOW
0x00216028
Write/Read
Offset Clock High Register
OFFSET_CLK_HIGH
0x0021602C
Write/Read
HECCRC Control Register
HECCRC_CONTROL
0x00216030
Write
WHITE_CONTROL
0x00216034
Write
Encryption Control X13 Register
ENCRYPTION_CONTROL_X13
0x00216038
Write
Correlation Time Setup Register
CORRELATION_TIME_SETUP
0x00216040
Write
Correlation Time Stamp Register
CORRELATION_TIME_STAMP
0x00216040
Read
RF_GPO
0x00216048
Write
PWM Received Signal Strength Indicator Register
PWM_RSSI
0x0021604C
Write/Read
Time A & B Register
TIME_A_B
0x00216050
Write
Time C & D Register
TIME_C_D
0x00216054
Write
PWM_TX
0x00216058
Write
RF Control Register
RF_CONTROL
0x0021605C
Write
RF Status Register
RF_STATUS
0x0021605C
Read
RX Time Register
RX_TIME
0x00216060
Write
TX Time Register
TX_TIME
0x00216064
Write
BAT
0x00216068
Write
Command Register
Status Register
Native Count Register
Estimated Count Register
White Control Register
RF GPO Register
PWM TX Register
Bluetooth Application Timer Register
MC9328MX1 Reference Manual, Rev. 6.1
16-22
Freescale Semiconductor
Programming Model
Table 16-10. BTA Module Register Memory Map (continued)
Address
Read/Write
THRESHOLD
0x0021606C
Write
CORRELATION_MAX
0x0021606C
Read
Synch Word 0 Register
SYNCH_WORD_0
0x00216070
Write
Synch Word 1 Register
SYNCH_WORD_1
0x00216074
Write
Synch Word 2 Register
SYNCH_WORD_2
0x00216078
Write
Synch Word 3 Register
SYNCH_WORD_3
0x0021607C
Write
Buf Word 0 (LW0) Register
BUF_WORD_0 (LW0)
0x00216080
Write/Read
Buf Word 1 (LW0) Register
BUF_WORD_1 (LW0)
0x00216084
Write/Read
Buf Word 2 (LW0) Register
BUF_WORD_2 (LW0)
0x00216088
Write/Read
Threshold Register
…
…
Correlation Max Register
…
Name
…
Description
Buf Word 29 (LW7) Register
BUF_WORD_29 (LW7)
0x002160F4
Write/Read
Buf Word 30 (LW7) Register
BUF_WORD_30 (LW7)
0x002160F8
Write/Read
Buf Word 31 (LW7) Register
BUF_WORD_31 (LW7)
0x002160FC
Write/Read
Wake-Up 1 Register
WAKEUP_1
0x00216100
Write/Read
Wake-Up 2 Register
WAKEUP_2
0x00216104
Write/Read
WAKEUP_DELTA4
0x0021610C
Write
WAKEUP_4
0x0021610C
Read
Wake-Up Control Register
WU_CONTROL
0x00216110
Write
Wake-Up Status Register
WU_STATUS
0x00216110
Read
Wake-Up Count Register
WU_COUNT
0x00216114
Read
CLK_CONTROL
0x00216118
Write/Read
SPI Word0 Register
SPI_WORD0
0x00216120
Write/Read
SPI Word1 Register
SPI_WORD1
0x00216124
Write
SPI Word2 Register
SPI_WORD2
0x00216128
Write
SPI Word3 Register
SPI_WORD3
0x0021612C
Write
SPI Write Address Register
SPI_WRITE_ADDR
0x00216130
Write
SPI Read Address Register
SPI_READ_ADDR
0x00216134
Write
SPI_CONTROL
0x00216138
Write
Wake-Up Delta4 Register
Wake-Up 4 Register
Clock Control Register
SPI Control Register
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-23
Programming Model
Table 16-10. BTA Module Register Memory Map (continued)
Description
Name
Address
Read/Write
SPI_STATUS
0x00216138
Read
HOP0
0x00216140
Write
HOP_FREQ_OUT
0x00216140
Read
Hop 1 (Frequency In) Register
HOP1
0x00216144
Write
Hop 2 (Frequency In) Register
HOP2
0x00216148
Write
Hop 3 (Frequency In) Register
HOP3
0x0021614C
Write
Hop 4 (Frequency In) Register
HOP4
0x00216150
Write
INTERRUPT_VECTOR
0x00216160
Write/Read
SYNC_METRIC
0x00216170
Read
SYNC_FC
0x00216174
Read
Word Reverse Register
WORD_REVERSE
0x00216178
Write/Read
Byte Reverse Register
BYTE_REVERSE
0x0021617C
Write/Read
SPI Status Register
Hop 0 (Frequency In) Register
Hop Frequency Out Register
Interrupt Vector Register
Synchronization Metric Register
Synchronize Frequency Carrier Register
Table 16-11. BTA Module Register Overview
Functional
Unit
Address
Read
Write
Sequencer
0x00216000
COMMAND
STATUS
0x00216004
PACKET_HEADER
PACKET_HEADER
0x00216008
PAYLOAD_HEADER
PAYLOAD_HEADER
0x0021600C
NATIVE_COUNT
NATIVE_COUNT
0x00216010
ESTIMATED_COUNT
ESTIMATED_COUNT
0x00216014
OFFSET_COUNT
OFFSET_COUNT
0x00216018
NATIVECLK_LOW
NATIVECLK_LOW
0x0021601C
NATIVECLK_HIGH
NATIVECLK_HIGH
0x00216020
ESTIMATED_CLK_LOW
ESTIMATED_CLK_LOW
0x00216024
ESTIMATED_CLK_HIGH
ESTIMATED_CLK_HIGH
0x00216028
OFFSET_CLK_LOW
OFFSET_CLK_LOW
0x0021602C
OFFSET_CLK_HIGH
OFFSET_CLK_HIGH
Bluetooth
Clocks
MC9328MX1 Reference Manual, Rev. 6.1
16-24
Freescale Semiconductor
Programming Model
Table 16-11. BTA Module Register Overview (continued)
Address
Read
Bluetooth
Pipeline
0x00216030
HECCRC_CONTROL
0x00216034
WHITE_CONTROL
0x00216038
ENCRYPTION_CONTROL_X13
0x00216040
CORRELATION_TIME_SETUP
0x00216048
RF_GPO
0x0021604C
PWM_RSSI
0x00216050
TIME_A_B
0x00216054
TIME_C_D
0x00216058
PWM_TX
0x0021605C
RF_CONTROL
0x00216060
RX_TIME
0x00216064
TX_TIME
Timer
0x00216068
BAT
Correlator
0x0021606C
THRESHOLD
0x00216070
SYNCH_WORD_0
0x00216074
SYNCH_WORD_1
0x00216078
SYNCH_WORD_2
0x0021607C
SYNCH_WORD_3
0x00216080
BUF_WORD_0 (LW0)
BUF_WORD_0 (LW0)
0x00216084
BUF_WORD_1 (LW0)
BUF_WORD_1 (LW0)
0x00216088
BUF_WORD_2 (LW0)
BUF_WORD_2 (LW0)
…
Bit
Buffer
Write
CORRELATION_TIME_STAMP
PWM_RSSI
RF_STATUS
CORRELATION_MAX
…
Radio
Control
…
Functional
Unit
0x002160F4
BUF_WORD_29 (LW7)
BUF_WORD_29 (LW7)
0x002160F8
BUF_WORD_30 (LW7)
BUF_WORD_30 (LW7)
0x002160FC
BUF_WORD_31 (LW7)
BUF_WORD_31 (LW7)
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-25
Programming Model
Table 16-11. BTA Module Register Overview (continued)
Functional
Unit
Address
Read
Write
Wake-Up
0x00216100
WAKEUP_1
WAKEUP_1
0x00216104
WAKEUP_2
WAKEUP_2
0x0021610C
WAKEUP_DELTA4
WAKEUP_4
0x00216110
WU_CONTROL
WU_STATUS
0x00216114
WU_COUNT
System
0x00216118
CLK_CONTROL
CLK_CONTROL
SPI
0x00216120
SPI_WORD0
SPI_WORD0
0x00216124
SPI_WORD1
0x00216128
SPI_WORD2
0x0021612C
SPI_WORD3
0x00216130
SPI_WRITE_ADDR
0x00216134
SPI_READ_ADDR
0x00216138
SPI_CONTROL
SPI_STATUS
0x00216140
HOP0
HOP_FREQ_OUT
0x00216144
HOP1
0x00216148
HOP2
0x0021614C
HOP3
0x00216150
HOP4
Interrupt
0x00216160
INTERRUPT_VECTOR
Joint
Detection
0x00216170
SYNC_METRIC
0x00216174
SYNC_FC
Frequency
Hopping
Reversing
INTERRUPT_VECTOR
0x00216178
WORD_REVERSE
WORD_REVERSE
0x0021617C
BYTE_REVERSE
BYTE_REVERSE
MC9328MX1 Reference Manual, Rev. 6.1
16-26
Freescale Semiconductor
Programming Model
16.5.1 Sequencer Registers
Three addresses correlate to sequencing functions. The Command Register and Status Register are write and read
registers associated with one address.
16.5.1.1 Command Register
The write-only Command Register controls the BTA functions such as enabling or disabling interrupts, controlling
the Bluetooth pipeline, and setting the correlation window size.
Reading address 0x00216000 returns the Status Register (see section 16.5.1.2). The Command Register bits and
their settings are described in Table 16-12 on page 16-27.
COMMAND
Addr
0x00216000
Command Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
OS
CWS
IDP
MS
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
AAO
EHI
EFI
PIPE
w
w
w
w
r
r
r
r
r
w
w
r
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
CMD
RESET
0x0004
Table 16-12. Command Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
AAO
Bit 15
Abort All Operations—Indicates that the BTA must abort the current
process. For example, when the software detects that the packet is not
addressed to the unit, it aborts the reception. AAO initializes the FSM in
the BTA and must always be 1 whenever a CMD is given.
0 = Do not abort
1 = Abort
EHI
Bit 14
Enable End-of-Header Interrupt—Enables/Disables the End-of-Header
interrupt during packet reception.
0 = Disable EHI interrupt
1 = Enable EHI interrupt
EFI
Bit 13
Enable End-of-Frame Interrupt—Enables/Disables the End-of-Frame
interrupt during packet reception and transmission.
0 = Disable EFI interrupt
1 = Enable EFI interrupt
PIPE
Bit 12
Bluetooth Pipeline Processing Control—Determines whether to
bypass the Bluetooth pipeline module. When bypass is selected (PIPE is
set), data flows directly between the Bit Buffer and the RF sub-modules.
0 = Bluetooth pipeline enabled
1 = Bypass Bluetooth pipeline
after the header trailer bits
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-27
Programming Model
Table 16-12. Command Register Description (continued)
Name
Description
Settings
Reserved
Bits 11–7
Reserved—These bits are reserved and should read 0.
OS
Bit 6
Override ESTIMATEDCLK 2 LSBs—Overrides the two least significant
bits of the ESTIMATEDCLK when a trigger is received by the unit
operating as a slave during synchronization.
0 = Preset the two LSBs to 00
1 = Do not preset the two LSBs
CWS
Bit 5
Correlation Window Size—Selects the correlation window size. When
window search is selected (CWS is cleared), the window size is
controlled by the TX_TIME and RX_TIME Registers. (see section
16.5.4.10 and 16.5.4.11 respectively for details).
0 = Window search
1 = Continuous search
Reserved
Bit 4
Reserved—This bit is reserved and should read 0.
IDP
Bit 3
ID Packet—Indicates that the packet to transmit is an ID packet (as
specified in the Bluetooth specification) that contains only the access
code.
0 = Non ID packet type
1 = ID packet type
MS
Bit 2
NATIVECLK/ESTIMATEDCLK Selection—Determines which of the two
clocks maintained by the Bluetooth core is used as SYSTICK.
0 = ESTIMATEDCLK
1 = NATIVECLK
CMD
Bits 1–0
Command—Determines the BTA’s mode of operation.
00 = Idle
01 = Receive
10 = Transmit
11 = Continuous Rx/Tx test mode
16.5.1.2 Status Register
The read-only Status Register returns status information about the BTA, including the lower two bits of the
Bluetooth clock, information about FEC and CRC errors, the current operating state of the BTA and the long word
bit buffer currently used by the BTA. The Status Register bits and their settings are described in Table 16-13 on
page 16-29.
MC9328MX1 Reference Manual, Rev. 6.1
16-28
Freescale Semiconductor
Programming Model
STATUS
Addr
0x00216000
Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
MS2LSB
TYPE
13
12
11
10
9
REC1
REC2
NREC
CRC16
HEC8
MS
STATE
BUF_ADDR
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
RESET
0x0040
Table 16-13. Status Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
MS2LSB
Bits 15–14
2 LSBs of the Current Bluetooth Clock—Returns the 2 LSB bits of the current Bluetooth clock
(NATIVECLK or ESTIMATEDCLK).
REC1
Bit 13
Recoverable 1/3 FEC Check—Indicates that a 1/3
FEC was performed.
0 = No correction made
1 = Correction made
Note: Although all 1/3 FEC errors are “recoverable,”
the decoded bit may be incorrect.
REC2
Bit 12
Recoverable 2/3 FEC Check—Indicates that a
correctable 1-bit error occurred.
0 = No correctable error
1 = Correctable error
NREC
Bit 11
Non-Recoverable Error in 2/3 FEC—Indicates that a
non-recoverable 2/3 FEC (more than 1-bit error)
occurred.
0 = No unrecoverable error
1 = Unrecoverable error
CRC16
Bit 10
Payload CRC Error—Indicates an error in the payload
CRC checksum.
0 = No CRC error
1 = CRC error
HEC8
Bit 9
Packet Header HEC Error—Indicates an error in
packet HEC checking.
0 = No HEC error
1 = HEC error
Reserved
Bits 8–7
Reserved—These bits are reserved and should read 0.
MS
Bit 6
NATIVECLK/ESTIMATEDCLK—Indicates which of the
two clocks maintained by the Bluetooth core is used as
SYSTICK.
0 = ESTIMATEDCLK
1 = NATIVECLK
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-29
Programming Model
Table 16-13. Status Register Description (continued)
Name
Description
Settings
STATE
Bits 5–3
Operating State of the BTA—Reflects the current
operating state of the BTA.
000 = Idle state
001 = Standby for receive state
010 = Correlation phase in the receive state
011 = Receiving data in the receive state
100 = Standby for transmit state
101 = Transmitting preamble in the transmit state
110 = Transmitting data in the transmit state
111 = Reserved
BUF_ADDR
Bits 2–0
Pointer to Long Word Bit Buffer—Points to the long word bit buffer for data reading. The software can read
any long word in the bit buffer up to (but not including) the long word currently used by the BTA. (It can read
up to BUF_ADDR-1) The software must keep track of the last long word accessed.
MC9328MX1 Reference Manual, Rev. 6.1
16-30
Freescale Semiconductor
Programming Model
16.5.1.3 Packet Header Register
The Packet Header Register is used for both receiving and transmitting. During a read, the Packet Header Register
contains the 10-bit packet header of the most recently received Bluetooth packet. When written to, the Packet
Header Register specifies the 10-bit packet header of the Bluetooth packet to transmit. The Packet Header Register
bits and their settings are described in Table 16-14.
PACKET_HEADER
Addr
0x00216004
Packet Header Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SEQN ARQN FLOW
TYPE
TYPE
AM_ADDR
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-14. Packet Header Register Description
Name
Description
Reserved
Bits 31–10
Reserved—These bits are reserved and should read 0.
SEQN
Bit 9
SEQN—Defined in the Bluetooth header standard.
ARQN
Bit 8
ARQN—Defined in the Bluetooth header standard.
FLOW
Bit 7
FLOW—Defined in the Bluetooth header standard.
TYPE
Bits 6–3
TYPE—Defined in the Bluetooth header standard.
AM_ADDR
Bits 2–0
AM_Addr—Defined in the Bluetooth header standard.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-31
Programming Model
16.5.1.4 Payload Header Register
The Payload Header Register is used for both receiving and transmitting. When read, the Payload Header Register
contains the 8- or 12-bit packet header of the most recently received Bluetooth packet. When written to, the
Payload Header Register specifies the 8- or 12-bit packet header of the Bluetooth packet to transmit. The Payload
Header Register bits and their settings are described in Table 16-15.
PAYLOAD_HEADER
Addr
0x00216008
Payload Header Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
LENGTH
TYPE
FLOW
L_CH
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-15. Payload Header Register Description
Name
Description
Reserved
Bits 31–12
Reserved—These bits are reserved and should read 0.
LENGTH
Bits 11–3
Payload Length—Contains a 5- or 9-bit payload length determined by packet type.
FLOW
Bit 2
Flow—Defined in the Bluetooth standard.
L_CH
Bits 1–0
Logical Channel—Defined in the Bluetooth standard.
MC9328MX1 Reference Manual, Rev. 6.1
16-32
Freescale Semiconductor
Programming Model
16.5.2 Bluetooth Clocks Registers
Nine registers have Bluetooth clocking functions.
16.5.2.1 Native Count Register
The Native Count Register contains a high resolution counter that generates the NATIVECLK by dividing the 8
MHz clock by 2,500 to generate a 3.2 kHz SYSTICK that updates the NATIVECLK registers. The Native Count
Register field is described in Table 16-16.
NATIVE_COUNT
Addr
0x0021600C
Native Count Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
NATIVE_COUNT
TYPE
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-16. Native Count Register Description
Name
Description
Reserved
Bits 31–12
Reserved—These bits are reserved and should read 0.
NATIVE_COUNT
Bits 11–0
Native Count—Contains the NATIVECOUNT counter, which divides the high precision 8 MHz
clock to generate the 3.2 kHz SYSTICK.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-33
Programming Model
16.5.2.2 Estimated Count Register
The Estimated Count Register contains the high resolution counter that generates the ESTIMATEDCLK by
dividing the 8 MHz clock by 2,500 to generate a 3.2 kHz SYSTICK that updates the ESTIMATEDCLK registers.
The Estimated Count Register bits are defined in Table 16-17.
ESTIMATED_COUNT
Addr
0x00216010
Estimated Count Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
ESTIMATED_COUNT
TYPE
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
RESET
0x0004
Table 16-17. Estimated Count Register Description
Name
Description
Reserved
Bits 31–12
Reserved—These bits are reserved and should read 0.
ESTIMATED_COUNT
Bits 11–0
Estimated Count—Contains the ESTIMATEDCOUNT counter, which is clocked by the
high precision 8 MHz clock and preset by the access code triggering.
MC9328MX1 Reference Manual, Rev. 6.1
16-34
Freescale Semiconductor
Programming Model
16.5.2.3 Offset Count Register
The Offset Count Register contains a high resolution counter that generates OFFSETCLK by dividing the 8 MHz
clock by 2,500 to generate a 3.2 kHz SYSTICK that updates the OFFSETCLK registers. The Offset Count Register
bits are described in Table 16-18.
OFFSET_COUNT
Addr
0x00216014
Offset Count Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
OFFSET_COUNT
TYPE
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-18. Offset Count Register Description
Name
Description
Reserved
Bits 31–12
Reserved—These bits are reserved and should read 0.
OFFSET_COUNT
Bits 11–0
Off Set Count—Contains the OFFSETCOUNT, which generates OFFSETCLK.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-35
Programming Model
16.5.2.4 Native Clock Low Register
The Native Clock Low Register concatenated with the Native Clock High Register (see section 16.5.2.5) comprise
the free-running Bluetooth NATIVECLK. The Native Clock Low Register contains the 16 least significant bits
(LSB) of the 28-bit NATIVECLK.
Writing to the Offset Clock Low Register and the Offset Clock High Register updates ESTIMATEDCLK with the
sum of NATIVECLK and OFFSETCLK on the next NATIVECLK tick.
The Native Clock Low Register bits are described in Table 16-19.
NATIVECLK_LOW
Addr
0x00216018
Native Clock Low Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
NATIVECLK_LOW
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-19. Native Clock Low Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
NATIVECLK_LOW
Bits 15–0
Lower Two Bytes of the NATIVECLK—Contains the LSB (bits 15–0) of the 28-bit
NATIVECLK.
MC9328MX1 Reference Manual, Rev. 6.1
16-36
Freescale Semiconductor
Programming Model
16.5.2.5 Native Clock High Register
The Native Clock High Register concatenated with the Native Clock Low Register (see section 16.5.2.4) comprise
the free-running Bluetooth NATIVECLK. The Native Clock High Register contains the 12 most significant bits
(MSBs) of the 28-bit NATIVECLK.
Writing to the Offset Clock Low Register and the Offset Clock High Register updates ESTIMATEDCLK with the
sum of NATIVECLK and OFFSETCLK on the next NATIVECLK tick.
The Native Clock High Register bits are described in Table 16-20.
NATIVECLK_HIGH
Addr
0x0021601C
Native Clock High Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
NATIVECLK_HIGH
TYPE
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-20. Native Clock High Register Description
Name
Description
Reserved
Bits 31–12
Reserved—These bits are reserved and should read 0.
NATIVECLK_HIGH
Bits 11–0
High Bits of the NATIVECLK—Contains the MSBs (bits 27–16) of the 28-bit NATIVECLK.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-37
Programming Model
16.5.2.6 Estimated Clock Low Register
The Estimated Clock Low Register concatenated with the Estimated Clock High Register (see section 16.5.2.7)
comprise the estimated Bluetooth clock. The Estimated Clock Low Register contains the 16 least significant bits
(LSB) of the 28-bit ESTIMATEDCLK. The Estimated Clock Low Register bits are described in Table 16-21.
ESTIMATED_CLK_LOW
Addr
0x00216020
Estimated Clock Low Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
ESTIMATED_CLK_LOW
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
RESET
0x0005
Table 16-21. Estimated Clock Low Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
ESTIMATED_CLK_LOW
Bits 15–0
Lower 2 Bytes of the ESTIMATEDCLK—Contains the LSB (bits 15–0) of the 28-bit
ESTIMATEDCLK.
MC9328MX1 Reference Manual, Rev. 6.1
16-38
Freescale Semiconductor
Programming Model
16.5.2.7 Estimated Clock High Register
The Estimated Clock High Register concatenated with the Estimated Clock Low Register (see section 16.5.2.6)
comprise the estimated Bluetooth clock. The Estimated Clock High Register contains the 12 most significant bits
(MSBs) of the 28-bit ESTIMATEDCLK. The Estimated Clock High Register bits are described in Table 16-22.
ESTIMATED_CLK_HIGH
Addr
0x00216024
Estimated Clock High Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
ESTIMATED_CLK_HIGH
TYPE
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-22. Estimated Clock High Register Description
Name
Description
Reserved
Bits 31–12
Reserved—These bits are reserved and should read 0.
ESTIMATED_CLK_HIGH
Bits 11–0
High Bits of the ESTIMATEDCLK—Contains the MSBs (bits 27–16) of the 28-bit
ESTIMATEDCLK.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-39
Programming Model
16.5.2.8 Offset Clock Low Register
The Offset Clock Low Register concatenated with the Offset Clock High Register (see section 16.5.2.9) comprise
the difference between the native Bluetooth clock and the master Bluetooth clock. The Offset Clock Low Register
contains the 16 least significant bits (LSB) of the 28-bit OFFSETCLK. Offset Clock Low Register bits are
described in Table 16-23.
OFFSET_CLK_LOW
Addr
0x00216028
Offset Clock Low Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
OFFSET_CLK_LOW
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-23. Offset Clock Low Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
OFFSET_CLK_LOW
Bits 15–0
Lower 2 Bytes of OFFSETCLK—Contains the LSB (bits 15–0) of the 28-bit OFFSETCLK.
MC9328MX1 Reference Manual, Rev. 6.1
16-40
Freescale Semiconductor
Programming Model
16.5.2.9 Offset Clock High Register
The Offset Clock High Register concatenated with the Offset Clock Low Register (see section 16.5.2.8) comprise
the difference between the native Bluetooth clock and the master Bluetooth clock. The Offset Clock High Register
contains the 12 most significant bits (MSBs) of the 28-bit OFFSETCLK. The Offset Clock High Register bits are
described in Table 16-24.
OFFSET_CLK_HIGH
Addr
0x0021602C
Offset Clock High Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
OFFSET_CLK_HIGH
TYPE
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-24. Offset Clock High Register Description
Name
Description
Reserved
Bits 31–12
Reserved—These bits are reserved and should read 0.
OFFSET_CLK_HIGH
Bits 11–0
High Bits of OFFSETCLK—Contains the MSBs (bits 27–16) of the 28-bit OFFSETCLK.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-41
Programming Model
16.5.3 Bluetooth Pipeline Registers
Three registers control the units in the Bluetooth Pipeline.
16.5.3.1 HECCRC Control Register
The write-only HECCRC Control Register specifies the initialization word for the HEC and the CRC checksum
generation. The initialization word is derived from the Bluetooth clock, as described in the Specification of the
Bluetooth System, version 1.1. The HECCRC Control Register bits are described in Table 16-25.
HECCRC_CONTROL
Addr
0x00216030
HECCRC Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
HECCRC_INIT
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-25. HECCRC Control Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
HECCRC_INIT
Bits 15–0
HEC and CRC Initialization
Field—Initializes the registers for generating
the check bits for HEC and CRC.
Initialization values for the payload CRC registers. The
lower byte (bits 7:0) is the same for both HEC and CRC
while the upper byte (bits 15:8) is all 0s.
MC9328MX1 Reference Manual, Rev. 6.1
16-42
Freescale Semiconductor
Programming Model
16.5.3.2 White Control Register
The write-only White Control Register writes the whitening initialization word. The whitening initialization word
is derived from the master Bluetooth clock as specified in Specification of the Bluetooth System, version 1.1. The
White Control Register bits are described in Table 16-26.
WHITE_CONTROL
Addr
0x00216034
White Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WHITE_INIT
TYPE
r
r
r
r
r
r
r
r
r
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-26. White Control Register Description
Name
Description
Reserved
Bits 31–7
Reserved—These bits are reserved and should read 0.
WHITE_INIT
Bits 6–0
Whitening Unit Initialization Field—Initializes the registers
that generate the whitening sequence.
Settings
Initialization values for the registers that
generate the whitening sequence.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-43
Programming Model
16.5.3.3 Encryption Control X13 Register
The write-only Encryption Control X13 Register sets up the encryption key and enables encryption. Thirteen
values are written to the register in a row to accomplish those functions. To disable encryption, do not write to the
Encryption Control X13 Register. The Encryption Control X13 Register bits are described in Table 16-27.
ENCRYPTION_CONTROL_X13
Addr
0x00216038
Encryption Control X13 Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
ENCRYPT
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-27. Encryption Control X13 Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
ENCRYPT
Bits 15–0
Encryption Words—Receives a sequence of 13 words to initialize and set up
the encryption engine.
Settings
To disable encryption, do
not write to this register.
MC9328MX1 Reference Manual, Rev. 6.1
16-44
Freescale Semiconductor
Programming Model
16.5.4 Radio Control Registers
Nine addresses correlate to radio control functions. The Correlation Time Setup Register and Correlation Time
Stamp Register are write and read registers associated with one address. Similarly, the RF Control Register and RF
Status Register are write and read registers associated with one address.
16.5.4.1 Correlation Time Setup Register
The write-only Correlation Time Setup Register is used when the unit is in slave mode to adjust the
synchronization with the master clock. When the unit detects a valid access code, ideally 64 µs have passed since
the last master clock tick, however because of delays through the radio and other external devices, the time may not
be exactly 64 µs. The Correlation Time Setup Register can be used to adjust the time slightly. Reading address
0x00216040 returns the Correlation Time Stamp Register (see section 16.5.4.2). The Correlation Time Setup
Register bits are explained in Table 16-28 on page 16-45.
CORRELATION_TIME_SETUP
Addr
0x00216040
Correlation Time Setup Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
EST_PRELOAD_TIME
TYPE
r
r
r
r
r
r
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
RESET
0x0201
Table 16-28. Correlation Time Setup Register Description
Name
Description
Reserved
Bits 31–10
Reserved—These bits are reserved and should read 0.
EST_PRELOAD_TIME
Bits 9–0
Set Correlation Time—Holds the preload time value. The EST_PRELOAD_TIME value is loaded
into the ESTIMATEDCLK counter when the trigger is asserted during correlation in slave mode.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-45
Programming Model
16.5.4.2 Correlation Time Stamp Register
The read-only Correlation Time Stamp Register contains the time value when a valid access code is detected. The
time refers to the count value of the current clock when the correlation peak value is detected. The count is the
NATIVECOUNT when the unit is in master mode, or the ESTIMATEDCOUNT when the unit is in slave mode.
The Correlation Time Stamp Register bits are explained in Table 16-29.
CORRELATION_TIME_
STAMP
Addr
0x00216040
Correlation Time Stamp Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
CORR_TIME
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-29. Correlation Time Stamp Register Description
Name
Description
Reserved
Bits 31–12
Reserved—These bits are reserved and should read 0.
CORR_TIME
Bits 11–0
Get Correlation Time—Indicates the time when the trigger was asserted.
MC9328MX1 Reference Manual, Rev. 6.1
16-46
Freescale Semiconductor
Programming Model
16.5.4.3 RF GPO Register
The write-only RF GPO Register controls two general-purpose outputs in the RF interface that are generally used
only in Philsar or MC13180 mode. The RF GPO Register bits are explained in Table 16-30.
RF_GPO
Addr
0x00216048
RF GPO Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
GPO_
EN2
GPO_
EN1
RESET
0x0000
BIT
15
TYPE
14
13
12
11
10
9
8
7
GPO_ GPO_
DOUT2 DOUT1
r
r
r
r
r
r
r
r
r
r
w
w
r
r
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-30. RF GPO Register Description
Name
Description
Settings
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
GPO_EN2
Bit 5
GPO Enable—Enables/Disables the general purpose output to the BT9 pad.
When disabled, the normal pin value is forced on the output pin.
0 = Disabled
1 = Enabled
GPO_EN1
Bit 4
GPO Enable—Enables the general purpose output to the BT6 pad when the
PWM_TX_EN in the RF_CONTROL Register is set.
0 = Disabled
1 = Enabled
Reserved
Bits 3–2
Reserved—These bits are reserved and should read 0.
GPO_DOUT2
Bit 1
GPO Data Out—Holds the data value driven out to BT9 when GPO_EN2 is set to Enabled.
GPO_DOUT1
Bit 0
GPO Data Out—Holds the data value driven out to BT6 when GPO_EN1 is set to Enabled.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-47
Programming Model
16.5.4.4 PWM Received Signal Strength Indicator Register
Writing to the PWM Received Signal Strength Indicator Register takes effect only when the RSSIOR bit is set in
the RF Control Register.
When writing to the PWM Received Signal Strength Indicator Register, the 6-bit PWM output is forced onto the
BT8 pin and can be used as a standard PWM. The value written to the PWM Received Signal Strength Indicator
Register refers to a relative power of 0 (lowest) to 31 (maximum).
Reading the PWM Received Signal Strength Indicator Register returns the value of the digitized RSSI. This
reading will either be the peak RSSI value or the current RSSI value, depending on the value of the PEAK_HLD
bit in the RF Control Register.
The PWM Received Signal Strength Indicator Register bits are explained in Table 16-31.
PWM Received Signal Strength Indicator
Register
PWM_RSSI
Addr
0x0021604C
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
PWM_RSSI
TYPE
r
r
r
r
r
r
r
r
r
r
rw1
rw1
rw1
rw1
rw1
rw1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
1.
Write functions are only valid for the MC13180 radio.
Table 16-31. PWM Received Signal Strength Indicator Register Description (MC13180)
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
PWM_RSSI
Bits 5–0
Pulse Width Modulation Setting/Received Signal Strength Indicator—Sets the PWM for RSSI power
control for MC13180 radios. When read, returns the RSSI digitized by the BTA. The returned value will either
be the peak RSSI value or the current RSSI value, depending on the value of the PEAK_HLD bit in the RF
Control Register.
MC9328MX1 Reference Manual, Rev. 6.1
16-48
Freescale Semiconductor
Programming Model
16.5.4.5 Time A & B Register
The write-only Time A & B Register sets up the radio module timing. The timing unit (for TIME_A and TIME_B)
is expressed in “µs before the next SYSTICK.” The Time A & B Register bits are explained in Table 16-32.
TIME_A_B
Addr
0x00216050
Time A & B Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
TIME_B
TYPE
TIME_A
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-32. Time A & B Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
TIME_B
Bits 15–8
Time B—Sets the Timing B of the signals interfacing to the RF module.
TIME_A
Bits 7–0
Time A—Sets the Timing A of the signals interfacing to the RF module.
Settings
The timing unit is
expressed in “µs before
the next SYSTICK”.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-49
Programming Model
16.5.4.6 Time C & D Register
The write-only Time C & D Register sets up radio module timing. The timing unit (for TIME_C and TIME_D) is
expressed in “µs before the next SYSTICK.” The Time C & D Register bits are explained in Table 16-33.
TIME_C_D
Addr
0x00216054
Time C & D Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
TIME_D
TYPE
TIME_C
r
r
r
w
w
w
w
w
r
r
r
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-33. Time C & D Register Description
Name
Description
Settings
Reserved
Bits 31–13
Reserved—These bits are reserved and should read 0.
TIME_D
Bits 12–8
Time D—Sets the timing D of the signals
interfacing to the RF module.
Reserved
Bits 7–5
Reserved—These bits are reserved and should read 0.
TIME_C
Bits 4–0
Time C—Sets the timing C of the signals
interfacing to the RF module.
The timing unit is expressed in “µs before the next
SYSTICK”. See Figure 16-6 on page 16-16 for more details.
The timing unit is expressed in “µs before the next
SYSTICK”. See Figure 16-8 on page 16-18 for more details.
MC9328MX1 Reference Manual, Rev. 6.1
16-50
Freescale Semiconductor
Programming Model
16.5.4.7 PWM TX Register
The write-only PWM TX Register controls the transmitting power of the MC13180 radio. The value written to the
PWM TX Register refers to a relative transmitting power of 0 (lowest) to 31 (maximum). The PWM TX Register
bits are explained in Table 16-34.
PWM_TX
Addr
0x00216058
PWM TX Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
PWM_TX
TYPE
r
r
r
r
r
r
r
r
r
r
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-34. PWM TX Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
PWM_TX
Bits 5–0
Pulse Width Modulation—Sets the PWM for transmit power control.
Note:
This applies to the MC13180 radio only.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-51
Programming Model
16.5.4.8 RF Control Register
The write-only RF Control Register controls various radio parameters such as the operation of the Joint Detect
module, tri-stating of the BT2 pin, and operation of the RSSI. Reading address 0x0021605C returns the RF Status
Register (see section 16.5.4.9). The RF Control Register bits are explained in Table 16-35.
RF_CONTROL
Addr
0x0021605C
RF Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
BT5_OE
BT1_CONT
BT11_
AUTO_
SPIKE
RESET
0x0000
BIT
15
14
13
12
RSSIOR BIST XPOL
TYPE
11
10
9
8
7
TX_TRI
PEAK RSSI PWM_
CLE DIV SEL
_EN
_HLD _EN TX_EN
DELAY
_HOP
_STROBE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
RESET
0x1005
Table 16-35. RF Control Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
RSSIOR
Bit 15
RSSI Override—Selects normal RSSI mode, or whether
the RSSI value is controlled by writing to the PWM
Received Signal Strength Indicator Register (ARM Control)
and displayed on BT8. This bit must be set for this device.
0 = Normal RSSI functionality
1 = ARM controlled PWM
BIST
Bit 14
BIST Mode—Sets the JD/MLSE module in normal or BIST
mode.
0 = Normal
1 = BIST mode
XPOL
Bit 13
Rx/Tx Polarity—Changes the polarity of the RxData and
TxData signals to the radio.
0 = Normal
1 = Inverted
TX_TRI_EN
Bit 12
Tri-State Enable—Enables/Disables the tri-state mode of
the BT2 pin when not transmitting data.
0 = Disable tri-state when not
transmitting data
1 = Enable tri-state when not
transmitting data
CLE
Bit 11
Closed Loop Enable—Enables the closed loop for PLL.
0 = Tx (open loop)
1 = Rx (closed loop)
DIV
Bit 10
Antenna Diversity Selection—Selects the antenna.
0 = Antenna 0
1 = Antenna 1
MC9328MX1 Reference Manual, Rev. 6.1
16-52
Freescale Semiconductor
Programming Model
Table 16-35. RF Control Register Description (continued)
Name
Description
Settings
SEL
Bit 9
Selection—Selects the operation (either diversity selection
or oscillator enable) of BT7 pin.
0 = Oscillator enable operation
1 = Diversity selection
PEAK_HLD
Bit 8
Peak Hold for the RSSI PWM Operation—Selects the
PWM_RSSI peak hold mode. If peak hold is disabled
(PEAK_HLD = 0), the RSSI will be continuously updated
during data packet reception.
0 = PWM_RSSI tracks the analog
RSSI
1 = PWM_RSSI remains at last
peak value
RSSI_EN
Bit 7
Enable for the PWM_RSSI—Controls the PWM_RSSI
operation.
0 = Disable the RSSI PWM
operation
1 = Enable the RSSI PWM
operation
PWM_TX_EN
Bit 6
Enable for the PWM_TX—Controls the PWM_TX
operation.
0 = Disable the TX PWM
operation
1 = Enable the TX PWM
operation
BT5_OE
Bit 5
Enable BT5 as an Output—Controls the direction of the
BT5 pin.
0 = BT5 is an input
1 = BT5 is an output
BT1_CONT
Bit 4
BT1 Continuous Output—Controls the gating of BT1 clock
output.
0 = BT1 clock output is gated
1 = BT1 clock output is
continuous
BT11_AUTO_SPIKE
Bit 3
Enable Auto Spike Generation—Controls the automatic
generation of a spike on EOF.
0 = Do not generate spike on
EOF
1 = Generate spike on EOF
DELAY_HOP_STROBE
Bits 2–0
Delay HOP Strobe—Delays the HOP strobe on BT9 in the
SiliconWave radio.
000 = No delay
001 = 2µs
010 = 4µs
100 = 8µs
111 = 15µs
All other settings reserved
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-53
Programming Model
16.5.4.9 RF Status Register
The read-only RF Status Register indicates the operation of the radio. Most of the bits return the value written to
the RF Control Register. The RF Status Register bits are explained in Table 16-36.
RF_STATUS
Addr
0x0021605C
RF Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
RSSIOR BIST XPOL
TYPE
12
11
10
9
8
7
PWM
BT11
TX_TRI_
PEAK RSSI
_TX BT5_OE BT1_CONT _AUTO
CLE DIV SEL
EN
_HLD _EN
_EN
_SPIKE
DELAY
_HOP
_STROBE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
RESET
0x1005
Table 16-36. RF Status Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
RSSIOR
Bit 15
RSSI Override—Indicates the RSSI operating mode.
0 = Normal RSSI functionality
1 = CPU controlled PWM
BIST
Bit 14
BIST Mode—Indicates the whether JD/MLSE module is in
normal or BIST mode.
0 = Normal
1 = BIST mode
XPOL
Bit 13
Rx/Tx Polarity—Changes polarity of the RxData and
TxData signals to the radio.
0 = Normal
1 = Inverted
TX_TRI_EN
Bit 12
Tri-State Enable—Indicates the setting for the tri-state
control for the BT2 pin.
0 = Disable tri-state when not
transmitting data
1 = Enable tri-state when not
transmitting data
CLE
Bit 11
Closed Loop Enable—Indicates whether closed loop for
the PLL is enabled.
0 = Disable closed loop
1 = Enable closed loop
DIV
Bit 10
Antenna Diversity Selection—Indicates the antenna
currently used.
0 = Antenna 0
1 = Antenna 1
SEL
Bit 9
Selection—Indicates the operation (either diversity
selection or oscillator enable) of BT7 pin.
0 = Oscillator enable operation
1 = Diversity selection
MC9328MX1 Reference Manual, Rev. 6.1
16-54
Freescale Semiconductor
Programming Model
Table 16-36. RF Status Register Description (continued)
Name
Description
Settings
PEAK_HLD
Bit 8
Peak Hold for the RSSI PWM Operation—Indicates the
mode of operation of the PWM_RSSI.
0 = PWM_RSSI tracks the analog
RSSI
1 = PWM_RSSI remains at last
peak value
RSSI_EN
Bit 7
Enable for the PWM_RSSI—Indicates whether the
PWM_RSSI operation is enabled.
0 = Disable the RSSI PWM
operation
1 = Enable the RSSI PWM
operation
PWM_TX_EN
Bit 6
Enable for the PWM_TX—Indicates whether the
PWM_TX operation is enabled.
0 = Disable the TX PWM operation
1 = Enable the TX PWM operation
BT5_OE
Bit 5
Enable BT5 as an Output—Controls the direction of the
BT5 pad.
0 = BT5 is an input
1 = BT5 is an output
BT1_CONT
Bit 4
BT1 Continuous Output—Controls the gating of BT1
clock output.
0 = BT1 clock output is gated
1 = BT1 clock output is continuous
BT11_AUTO_SPIKE
Bit 3
Enable Auto Spike Generation—Controls the automatic
generation of a spike on EOF.
0 = Do not generate spike on EOF
1 = Generate spike on EOF
DELAY_HOP_STROBE
Bits 2–0
Delay HOP Strobe—Delays the HOP strobe on BT9 in the
SiliconWave radio.
000 = No delay
001 = 2µs
010 = 4µs
100 = 8µs
111 = 15µs
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-55
Programming Model
16.5.4.10 RX Time Register
The write-only RX Time Register defines the receive correlation window start and stop time to the MS_CLK. The
RX Time Register bits are explained in Table 16-37.
RX_TIME
Addr
0x00216060
RX Time Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
RX_TIME_END
TYPE
RX_TIME_START
r
r
w
w
w
w
w
w
r
r
r
w
w
w
w
w
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
RESET
0x1E07
Table 16-37. RX Time Register Description
Name
Description
Reserved
Bits 31–14
Reserved—These bits are reserved and should read 0.
RX_TIME_END
Bits 13–8
Correlation Stop Time—Sets the middle 6 bits of the search
window end time. The MS_CLK is a 12-bit clock that counts
from 0 (0x000) to 2499 (0x9C3). The RX_TIME_END field
defines the bits x.
MS_CLK[11:0] = 101x xxxx x000.
Reserved
Bits 7–5
Reserved—These bits are reserved and should read 0.
RX_TIME_START
Bits 4–0
Correlation Start Time—Sets the middle 5 bits of the search
window start time. The MS_CLK is a 12-bit clock that counts
from 0 (0x000) to 2499 (x9C3). The RX_TIME_START field
defines the bits x.
MS_CLK [11:0] = 1001 xxxx x000.
Settings
RX_TIME_END can range from
000000 to 111000, which means the
search window end time ranges from
64µs to 127µs.
RX_TIME_START can range from
00000 to 11000, which means that the
search window start time ranges from
288µs and 312µs.
MC9328MX1 Reference Manual, Rev. 6.1
16-56
Freescale Semiconductor
Programming Model
16.5.4.11 TX Time Register
The write-only TX Time Register defines the transmit start time to the MS_CLK. The TX Time Register bits are
explained in Table 16-38.
TX_TIME
Addr
0x00216064
TX Time Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
TX_TIME_START
TYPE
r
r
r
r
r
r
r
r
r
r
r
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-38. TX Time Register Description
Name
Description
Reserved
Bits 31–5
Reserved—These bits are reserved and should read 0.
TX_TIME_START
Bits 4–0
Correlation Start Time—Sets the middle 5 bits of the correlation
start time. The MS_CLK is a 12-bit clock that counts from 0
(0x000) to 2499 (x9C3). The TX_TIME_START field defines the
bits x.
MS_CLK [11:0] = 1001 xxxx x000.
Settings
TX_TIME_START can range from
00000 to 11000, which means
that the search window start time
ranges from 288 µs and 312 µs.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-57
Programming Model
16.5.5 Timer Register
There is only one timer register.
16.5.5.1 Bluetooth Application Timer Register
The write-only Bluetooth Application Timer Register controls the Bluetooth Application Timer (BAT). When
enabled, this timer generates period interrupts. The Bluetooth Application Timer Register enables the BAT and sets
up its period in ticks of 8 MHz.
The Bluetooth Application Timer Register bits are explained in Table 16-39.
BAT
Addr
0x00216068
Bluetooth Application Timer Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
EN
TYPE
TIMER
w
r
r
r
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-39. Bluetooth Application Timer Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
EN
Bit 15
Enable Bluetooth Application Timer—Enables/Disables the BAT and
interrupt.
Reserved
Bits 14–12
Reserved—These bits are reserved and should read 0.
TIMER
Bits 11–0
Timer Preset Value—Receives the preset value written to the Bluetooth
application timer. The timer is clocked by the 8 MHz clock. An interrupt is
issued after the count is reached and automatic reloading is performed.
Settings
0 = Disable timer and interrupt
1 = Enable timer and interrupt
Preset value written to the
application timer
MC9328MX1 Reference Manual, Rev. 6.1
16-58
Freescale Semiconductor
Programming Model
16.5.6 Correlator Registers
Five addresses pertain to correlator functions. The Threshold Register and Correlation Max Register are write and
read registers associated with one address.
16.5.6.1 Threshold Register
The write-only Threshold Register determines when an access code is considered valid. When the radio receives a
message, the BTA calculates the correlation between the access word written to the appropriate Synch Word X
Register (see Synch Word 0 Register (Write)) and the bits in the received message. When the correlation value
exceeds the value in the Threshold Register, the access code is considered valid.
The correlation depends on the signal strength and the access code. The values written to the Threshold Register
determine the signal energy level and the threshold required to accept the access word. The signal levels and
threshold values are functions of the values written to the Threshold Register. Reading address 0x0021606C
returns the Correlation Max Register (see section 16.5.6.2).
The Threshold Register bits, when used with the MC13180 radio, are explained in Table 16-40. The Threshold
Register bits, when used with the SiliconWave radio, are explained in Table 16-41.
THRESHOLD
Addr
0x0021606C
Threshold Register (MC13180)
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
THRESHOLD_II
(MC13180)
THRESHOLD_I (MC13180)
THRESHOLD (SiliconWave)
TYPE
r
r
r
r
r
r
r
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
RESET
0x01C2
Table 16-40. Threshold Register Description (MC13180)
Name
Description
Settings
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
THRESHOLD_II
Bits 7–4
Signal Energy—Sets the clipping level for the access code
correlation.
Default setting is 0.5625
THRESHOLD_I
Bits 3–0
Threshold Value—Sets the threshold value for the access code
correlation.
Default setting is 1.25
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-59
Programming Model
Table 16-41. Threshold Register Description (SiliconWave)
Name
Description
Reserved
Bits 31–9
Reserved—These bits are reserved and should read 0.
THRESHOLD
Bits 8–0
Threshold Value—Sets the threshold value for the access code correlation.
Table 16-42. Signal Energy Levels and Threshold Levels
THRESHOLD_I
THRESHOLD
THRESHOLD_II
Signal Energy
0
0.50000
0
0.5000
1
0.53125
1
0.5625
2
0.56250
2
0.6250
3
0.59375
3
0.6875
4
0.62500
4
0.7500
5
0.65625
5
0.8125
6
0.68750
6
0.8750
7
0.71875
7
0.9375
8
0.75000
8
1.0000
9
0.78125
9
1.0625
10
0.81250
10
1.1250
11
0.84375
11
1.1875
12
0.87500
12
1.2500
13
0.90625
13
1.3125
14
0.93750
14
1.3750
15
0.96875
15
1.4375
Note:
Levels vary according to the values written to the THRESHOLD_I and THRESHOLD_II fields.
MC9328MX1 Reference Manual, Rev. 6.1
16-60
Freescale Semiconductor
Programming Model
16.5.6.2 Correlation Max Register
The read-only Correlation Max Register contains the peak correlation value that is calculated when a valid access
code is detected. A value of 0 corresponds to no correlation, and a value of 511 corresponds to a perfect match. The
Correlation Max Register bits are explained in Table 16-43.
CORRELATION_MAX
Addr
0x0021606C
Correlation Max Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
VALUE
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
RESET
0x01C2
Table 16-43. Correlation Max Register Description
Name
Description
Settings
Reserved
Bits 31–9
Reserved—These bits are reserved and should read 0.
VALUE
Bits 8–0
Maximum Correlation Value—Contains the maximum correlation value during the correlation
phase.
Note:
N/A in MC13180 mode.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-61
Programming Model
16.5.6.3 Synch Word 0 Register
The write-only Synch Word X registers specify the access code that the correlator attempts to match. Bits 0–15 of
the correct access code are written to the Synch Word 0 Register; bits 16–31 to the Synch Word 1 Register; bits
32–47 to the Synch Word 2 Register; and bits 48–63 to the Synch Word 3 Register.
Synch Word 0 Register bits are explained in Table 16-44.
SYNCH_WORD_0
Addr
0x00216070
Synch Word 0 Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WORD
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-44. Synch Word 0 Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
WORD
Bits 15–0
Part of Synchronization Code—Receives bits [15:0] of the 64-bit access code for the correlation.
MC9328MX1 Reference Manual, Rev. 6.1
16-62
Freescale Semiconductor
Programming Model
16.5.6.4 Synch Word 1 Register
The write-only Synch Word 1 Register bits are explained in Table 16-45.
SYNCH_WORD_1
Addr
0x00216074
Synch Word 1 Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WORD
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-45. Synch Word 1 Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
WORD
Bits 15–0
Part of Synchronization Code—Receives bits [31:16] of the 64-bit access code for the correlation.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-63
Programming Model
16.5.6.5 Synch Word 2 Register
The write-only Synch Word 2 Register bits are explained in Table 16-46.
SYNCH_WORD_2
Addr
0x00216078
Synch Word 2 Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WORD
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-46. Synch Word 2 Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
WORD
Bits 15–0
Part of Synchronization Code—Receives bits [47:32] of the 64-bit access code for the correlation.
MC9328MX1 Reference Manual, Rev. 6.1
16-64
Freescale Semiconductor
Programming Model
16.5.6.6 Synch Word 3 Register
The write-only Synch Word 3 Register bits are explained in Table 16-47.
SYNCH_WORD_3
Addr
0x0021607C
Synch Word 3 Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WORD
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
1
1
0
1
1
0
1
0
0
0
1
0
0
1
0
1
RESET
0xDA25
Table 16-47. Synch Word 3 Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
WORD
Bits 15–0
Part of Synchronization Code—Receives bits [63:48] of the 64-bit access code for the correlation.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-65
Programming Model
16.5.7 Bit Buffer Registers
Thirty-two addresses correlate to bit buffer functions. The Buf Word 0 (LW0) Register through the Buf Word 31
(LW7) Register are used as the eight long words (LW0 through LW7) in the Bit Buffer Sub-Module. The registers
access the portions of the long words shown in Figure 16-4 on page 16-12.
16.5.7.1 Buffer Word Registers
The BTA keeps track of the most recently accessed long word accessed by the BTA. The Bluetooth software polls
the BTA status (BUF_ADDR bit of the Status Register) to avoid Bit Buffer overrun or underrun.
The Buf Word 0 (LW0) Register to Buf Word 31 (LW7) Register bits are explained in Table 16-48.
BUF_WORD_0 (LW0)
BUF_WORD_1 (LW0)
...
BUF_WORD_30 (LW7)
BUF_WORD_31 (LW7)
Addr
0x00216080
0x00216084
...
0x002160F8
0x002160FC
Buf Word 0 (LW0) Register
Buf Word 1 (LW0) Register
...
Buf Word 30 (LW7) Register
Buf Word 31 (LW7) Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WORD
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-48. Buf Word 0 (LW0) Register to Buf Word 31 (LW7) Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
WORD
Bits 15–0
Data Word—Contains the value read from or written to the bit buffer.
MC9328MX1 Reference Manual, Rev. 6.1
16-66
Freescale Semiconductor
Programming Model
Table 16-49. Bit Buffer Registers Numbers and Addresses
BUF_
WORD_
Register
Long
Word #
Address
BUF_
WORD_
Register
Long
Word #
Address
BUF_
WORD_
Register
Long
Word #
Address
0
LW0
0x00216080
12
LW3
0x002160B0
24
LW6
0x002160E0
1
LW0
0x00216084
13
LW3
0x002160B4
25
LW6
0x002160E4
2
LW0
0x00216088
14
LW3
0x002160B8
26
LW6
0x002160E8
3
LW0
0x0021608C
15
LW3
0x002160BC
27
LW6
0x002160EC
4
LW1
0x00216090
16
LW4
0x002160C0
28
LW7
0x002160F0
5
LW1
0x00216094
17
LW4
0x002160C4
29
LW7
0x002160F4
6
LW1
0x00216098
18
LW4
0x002160C8
30
LW7
0x002160F8
7
LW1
0x0021609C
19
LW4
0x002160CC
31
LW7
0x002160FC
8
LW2
0x002160A0
20
LW5
0x002160D0
9
LW2
0x002160A4
21
LW5
0x002160D4
10
LW2
0x002160A8
22
LW5
0x002160D8
11
LW2
0x002160AC
23
LW5
0x002160DC
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-67
Programming Model
16.5.8 Wake-Up Registers
Five addresses pertain to wake-up functions. The Wake-Up Control Register and Wake-Up Status Register are
write and read registers associated with one address.
16.5.8.1 Wake-Up 1 Register
The Wake-Up 1 Register contains the comparator value that determines the time for the power-down event.
The Wake-Up 1 Register bits are explained in Table 16-50.
WAKEUP_1
Addr
0x00216100
Wake-Up 1 Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
TIME
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
RESET
0x0001
Table 16-50. Wake-Up 1 Register Description
Name
Description
Reserved
Bits 31–2
Reserved—These bits are reserved and should read 0.
TIME
Bits 1–0
Value for Wake-Up Timer 1—Sets wake-up timer 1 for low-power
operation. The timer is clocked by the 32 kHz clock.
Settings
Recommend using
values greater than 1.
MC9328MX1 Reference Manual, Rev. 6.1
16-68
Freescale Semiconductor
Programming Model
16.5.8.2 Wake-Up 2 Register
The Wake-Up 2 Register contains the comparator value that determines the wake-up time. The value written to this
register can be read back from the register. The Wake-Up 2 Register bits are explained in Table 16-51.
WAKEUP_2
Addr
0x00216104
Wake-Up 2 Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
TIME
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
RESET
0x55AA
Table 16-51. Wake-Up 2 Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
TIME
Bits 15–0
Value for Wake-Up Timer 2—Sets
wake-up timer 2 for low-power operation.
The timer is clocked by the 32 kHz clock.
A non-zero value enables wake-up on the time value specified
(WU_COUNT = WAKEUP_2).
Writing 0x0000 to this register disables timed wake-up, and only
an external event will wake up the BTA.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-69
Programming Model
16.5.8.3 Wake-Up Delta4 Register
The write-only Wake-Up Delta4 Register contains the delta value that is added to the WU_COUNT value. The
sum is written to the Wake-Up 4 Register on wake-up. The value determines the time from wake up until the
Bluetooth master clock is started.
Reading address 0x0021610C returns the Wake-Up 4 Register (see section 16.5.8.4). The Wake-Up Delta4
Register bits are explained in Table 16-52.
WAKEUP_DELTA4
Addr
0x0021610C
Wake-Up Delta4 Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
TIME
TYPE
r
r
r
r
r
r
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
1
0
0
0
1
1
0
1
0
0
RESET
0x0234
Table 16-52. Wake-Up Delta4 Register Description
Name
Description
Reserved
Bits 31–10
Reserved—These bits are reserved and should read 0.
TIME
Bits 9–0
Delta Value for Wake-Up Timer 4—Sets the wake-up timer delta value that is added to the
WU_COUNT value after a wake-up event.
MC9328MX1 Reference Manual, Rev. 6.1
16-70
Freescale Semiconductor
Programming Model
16.5.8.4 Wake-Up 4 Register
The read-only Wake-Up 4 Register contains the time when the Bluetooth master clock is started
(WU_COUNT + WAKEUP_DELTA4). The WAKEUP_DELTA4 register bits are explained in Table 16-53.
WAKEUP_4
Addr
0x0021610C
Wake-Up 4 Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
TIME
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
RESET
0x0018
Table 16-53. Wake-Up 4 Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
TIME
Bits 15–0
Value for Wake-Up Timer 4—Contains the time value when the Bluetooth master clock was started.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-71
Programming Model
16.5.8.5 Wake-Up Control Register
The write-only Wake-Up Control Register enables or disables power-down and resets the wake-up counter.
Reading address 0x00216110 returns the Wake-Up Status Register (see section 16.5.8.6). The Wake-Up Control
Register bits are explained in Table 16-54.
WU_CONTROL
Addr
0x00216110
Wake-Up Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
PDE
CLR_CNT
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
r
r
r
r
r
r
r
r
r
r
r
w
w
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
RESET
0x0008
Table 16-54. Wake-Up Control Register Description
Name
Description
Settings
Reserved
Bits 31–5
Reserved—These bits are reserved and should read 0.
PDE
Bit 4
Power Down Enable—Enables/Disables the powerdown
mode.
0 = Disable power down and clear
WU_STATUS bit BTWUI
1 = Enable power down
CLR_CNT
Bit 3
Wake-Up Counter Reset—Resets the wake-up counter in
the wake up module.
0 = Do not reset the wake-up counter
1 = Reset the wake-up counter
Reserved
Bits 2–0
Reserved—These bits are reserved and should read 0.
MC9328MX1 Reference Manual, Rev. 6.1
16-72
Freescale Semiconductor
Programming Model
16.5.8.6 Wake-Up Status Register
The read-only Wake-Up Status Register indicates whether an interrupt has occurred, the clock status and the
whether power-down is enabled. It also contains the delta value that was written to the Wake-Up Delta4 Register
(see section 16.5.8.3). The Wake-Up Status Register bits are explained in Table 16-55.
WU_STATUS
Addr
0x00216110
Wake-Up Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
BTWUI
BT1_CLK_HOLD
PDE
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
6
WAKEUP_DELTA4
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-55. Wake-Up Status Register Description
Name
Description
Settings
Reserved
Bits 31–13
Reserved—These bits are reserved and should read 0.
WAKEUP_DELTA4
Bits 12–3
Wake Up Delta 4 Value—Returns the value that was written to the Wakeup_Delta4
Register.
BTWUI
Bit 2
Interrupt Indicator—Indicates that WU4 occurred.
0 = No interrupt
1 = Interrupt
BT1_CLK_HOLD
Bit 1
Bluetooth Clock—Indicates the status of the Bluetooth Clock
0 = BT clock running
1 = BT clock stopped
PDE
Bit 0
Power Down Enable—Indicates status of power down enable
function.
0 = Power down disabled
1 = Power down enabled
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-73
Programming Model
16.5.8.7 Wake-Up Count Register
The read-only Wake-Up Count Register indicates the value of the counter used by the wake-up comparators. The
Wake-Up Count Register bits are explained in Table 16-56.
WU_COUNT
Addr
0x00216114
Wake-Up Count Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
COUNT
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-56. Wake-Up Count Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
COUNT
Bits 15–0
Counter Value—Holds the count value used by the comparators in the wake-up units to trigger
wake-up interrupts.
MC9328MX1 Reference Manual, Rev. 6.1
16-74
Freescale Semiconductor
Programming Model
16.5.9 System Register
One register correlates to system control functions.
16.5.9.1 Clock Control Register
The write-only Clock Control Register configures the clocks of the radio module interface to the IP bus. See
Section 16.3.1.1, “IP Bus Interface,” for more information on the synchronization between the IP clock and the
BTA clock. The Clock Control Register bits are explained in Table 16-57.
CLK_CONTROL
Addr
0x00216118
Clock Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
RFM
TYPE
10
9
8
7
BT1_RSLOT
BT1_WSLOT
BT1_CLK_IN_DIV
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
rw
rw
r
r
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-57. Clock Control Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
RFM
Bits 15–13
RF Mode Selection—Selects the RF module serial interface standard.
Reserved
Bit 12
Reserved—This bit is reserved and should read 0.
BT1_RSLOT
Bits 11–8
Bluetooth RSlot—See Section 16.3.1.1, “IP Bus Interface.”
BT1_WSLOT
Bits 7–4
Bluetooth WSlot—See Section 16.3.1.1, “IP Bus Interface.”
Reserved
Bits 3–2
Reserved—These bits are reserved and should read 0.
Settings
011 = MC13180
100 = SiliconWave
All other settings reserved
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-75
Programming Model
Table 16-57. Clock Control Register Description (continued)
Name
Description
BT1_CLK_IN_DIV
Bits 1–0
Settings
BT1 Clock In Frequency Divider Select—Selects the frequency
division of the BT1 clock in.
00 = Idle
01 = 16
10 = 24
11 = 32
16.5.10 SPI Registers
Seven addresses pertain to SPI functions. The SPI Control Register and SPI Status Register are write and read
registers associated with one address.
The SPI registers program the radio modules, and have different implementations according to the radio module
used. For the specific values written to the SPI registers, see the radio specifications. A maximum of four data
words are buffered by writing multiple words in a row to the registers SPI_WORD0, SPI_WORD1, SPI_WORD2
and SPI_WORD3.
NOTE:
The software must poll the DONE bit of the SPI Status Register before reading or
writing new data from or to the SPI.
16.5.10.1 SPI Word0 Register
The SPI Word0 Register bits, when the MC13180 radio is used, are described in Table 16-58.
The SPI Word0 Register bits, when the SiliconWave radio is used, are described in Table 16-59.
SPI_WORD0
Addr
0x00216120
SPI Word0 Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WORD0 (MC13180)
BYTE0 (SiliconWave)
TYPE
BYTE1 (SiliconWave)
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
16-76
Freescale Semiconductor
Programming Model
Table 16-58. SPI Word0 Register Description (MC13180)
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
WORD0
Bits 15–0
Word of Data—Contains word 0 of the data read
from or written to the RF module
The address of the register from which data is read or
written is automatically post-incremented after a data
read or write. The start address is written to the SPI
Read Address Register before reads are performed or
to the SPI Write Address Register after writes are
performed.
Table 16-59. SPI Word0 Register Description (SiliconWave)
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
BYTE0
Bits 15–8
Byte 0—Contains the upper byte of the data read
from or written to the RF module.
BYTE1
Bits 7–0
Byte 1—Contains the lower byte of the data read
from or written to the RF module.
The address of the register from which data is read or
written is automatically post-incremented after a data
read or write. The start address is written to the SPI
Read Address Register before reads are performed or
to the SPI Write Address Register after writes are
performed.
16.5.10.2 SPI Word1 Register
The write-only SPI Word1 Register bits, when the MC13180 radio is used, are described in Table 16-60. The
write-only SPI Word1 Register bits, when the SiliconWave radio is used, are described in Table 16-61.
SPI_WORD1
Addr
0x00216124
SPI Word1 Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WORD1 (MC13180)
BYTE2 (SiliconWave)
TYPE
BYTE3 (SiliconWave)
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-77
Programming Model
Table 16-60. SPI Word1 Register Description (MC13180)
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
WORD1
Bits 15–0
Word of Data—Contains word 1 of the data read from or written to the RF module
.
Table 16-61. SPI Word1 Register Description (SiliconWave)
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
BYTE2
Bits 15–8
Byte 2—Contents vary according to the RF module used.
BYTE3
Bits 7–0
Byte 3—Contents vary according to the RF module used.
16.5.10.3 SPI Word2 Register
The write-only SPI Word2 Register bits, when the MC13180 radio is used, are described in Table 16-62. The
write-only SPI Word2 Register bits, when the SiliconWave radio is used, are described in Table 16-63.
SPI_WORD2
Addr
0x00216128
SPI Word2 Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WORD2 (MC13180)
BYTE4 (SiliconWave)
TYPE
BYTE5 (SiliconWave)
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
16-78
Freescale Semiconductor
Programming Model
Table 16-62. SPI Word2 Register Description (MC13180)
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
WORD2
Bits 15–0
Word of Data—Contains word 2 of the data read from or written to the RF module.
Table 16-63. SPI Word2 Register Description (SiliconWave)
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
BYTE4
Bits 15–8
Byte 4—Contents vary according to the RF module used.
BYTE5
Bits 7–0
Byte 5—Contents vary according to the RF module used.
16.5.10.4 SPI Word3 Register
The write-only SPI Word3 Register bits, when the SiliconWave radio is used, are described in Table 16-64. The
write-only SPI Word3 Register bits, when the SiliconWave radio is used, are described in Table 16-65.
SPI_WORD3
Addr
0x0021612C
SPI Word3 Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WORD3 (MC13180)
BYTE6 (SiliconWave)
TYPE
BYTE7 (SiliconWave)
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-79
Programming Model
Table 16-64. SPI Word3 Register Description (MC13180)
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
WORD3
Bits 15–0
Word of Data—Contains word 3 of the data read from or written to the RF module.
Table 16-65. SPI Word3 Register Description (SiliconWave)
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
BYTE6
Bits 15–8
Byte 6—Contents vary according to the RF module used.
BYTE7
Bits 7–0
Byte 7—Contents vary according to the RF module used.
16.5.10.5 SPI Write Address Register
The write-only SPI Write Address Register determines the address of the first radio register to write to. Writing to
this register overrides any previous SPI writes by the Bluetooth Core. The SPI Write Address Register bits, when
the MC13180 radio is used, are explained in Table 16-66. The SPI Write Address Register bits, when the
SiliconWave radio is used, are explained in Table 16-67.
SPI_WRITE_ADDR
Addr
0x00216130
SPI Write Address Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
Don’t Care (MC13180)
R/W
TYPE
R/W
ADDRESS (MC13180)
COMMAND (SiliconWave)
ADDRESS (SiliconWave)
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
16-80
Freescale Semiconductor
Programming Model
Table 16-66. SPI Write Address Register Description (MC13180)
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
Don’t Care
Bits 15–8
Don’t Care—Ignored by the BTA.
R/W
Bit 7
Read/Write—Tells the radio if it is a read or write cycle.
ADDRESS
Bits 6–0
Radio Register Address—Contains the address of the first radio register that the buffered SPI Word0
Register entries are written to. The address is automatically post-incremented in the radio register.
Set to 0.
Table 16-67. SPI Write Address Register Description (SiliconWave)
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
R/W
Bit 15
Read/Write—Tells the radio if it is a read or write cycle.
Set to 1.
COMMAND
Bits 14–8
Command—Specifies the command sent to the radio.
See the SiliconWave
specification sheet.
ADDRESS
Bits 7–0
Radio Register Address—Contains the address of the first radio register that the buffered SPI Word0
Register entries are written to. The address is automatically post-incremented in the radio register.
16.5.10.6 SPI Read Address Register
The write-only SPI Read Address Register contains the address of the first radio register that will be read from the
SPI Word0 Register. Any address written to the SPI Read Address Register overrides any previous SPI address
maintained by the Bluetooth core. The SPI Read Address Register bits, when the MC13180 radio is used, are
explained in Table 16-68. The SPI Read Address Register bits, when the SiliconWave radio is used, are explained
in Table 16-69.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-81
Programming Model
SPI_READ_ADDR
Addr
0x00216134
SPI Read Address Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
Don’t Care (MC13180)
R/W
TYPE
R/W
ADDRESS (MC13180)
COMMAND (SiliconWave)
ADDRESS (SiliconWave)
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-68. SPI Read Address Register Description (MC13180)
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
Don’t Care
Bits 15–8
Don’t Care—Ignored by the BTA.
R/W
Bit 7
Read/Write—Tells the radio if it is a read or write cycle.
ADDRESS
Bits 6–0
Philsar Register Address—Contains the address of the register read from the SPI Word0 Register.
Set to 1.
Table 16-69. SPI Read Address Register Description (SiliconWave)
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
R/W
Bit 15
Read/Write—Tells the radio if it is a read or write cycle.
Set to 0.
COMMAND
Bits 14–8
Command—Specifies the command sent to the radio.
See the SiliconWave
specification sheet.
ADDRESS
Bits 7–0
Philsar Register Address—Contain the address of the register read from the SPI Word0 Register.
MC9328MX1 Reference Manual, Rev. 6.1
16-82
Freescale Semiconductor
Programming Model
16.5.10.7 SPI Control Register
The write-only SPI Control Register sets up the mapping of values written to SPI registers to the signals between
the BTA and the radio module. The SPI Control Register selects the radio module and sets up the duty cycle of the
SPI clock. Reading address 0x00216138 returns the SPI Status Register (see section 16.5.10.8). The SPI Control
Register bits are explained in Table 16-70.
SPI_CONTROL
Addr
0x00216138
SPI Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
BYTE_ONLY
SPI_CLKINV
w
w
w
w
w
w
w
w
w
w
w
w
r
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TYPE
13
12
11
SPI_CLKDIV3
10
9
SPI_CLKDIV2
SPI_CLKDIV1
SPI_MODE
RESET
0x0000
Table 16-70. SPI Control Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
BYTE_ONLY
Bit 15
Byte/Word—Specifies whether the current data is a byte
or a word.
0 = Normal
1 = Single bytes only
SPI_CLKINV
Bit 14
Inverted SPI Clock—Specifies whether the SPI clock
output is inverted.
0 = Normal
1 = Inverted
SPI_CLKDIV3
Bits 13–12
State 3 Delay—Controls the SPI clock space period. See
Figure 16-11 on page 16-84 for details.
SPI_CLKDIV2
Bits 11–8
State 2 Delay—Controls the SPI clock mark period. See
Figure 16-11 on page 16-84 for details.
These divider settings determine the duty
cycle division ratio for high and low signal
levels, as well as for the clock. The ratios are
specified as the target ratios minus one.
SPI_CLKDIV1
Bits 7–4
State 1 Delay—Controls the SPI clock space period. See
Figure 16-11 on page 16-84 for details.
Reserved
Bit 3
Reserved—This bit is reserved and should read 0.
SPI_MODE
Bits 2–0
SPI Mode Selection—Sets SPI mode according to the
radio used.
011 = MC13180
100 = SiliconWave
All Other Settings Reserved
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-83
Programming Model
SPI State
1
2
3
1
2
3
1
2
3
1
2
3
SPI_EN
SPI_CLK
Figure 16-11. SPI Clock Dividers Determine Duty Cycle of SPI Clock
MC9328MX1 Reference Manual, Rev. 6.1
16-84
Freescale Semiconductor
Programming Model
16.5.10.8 SPI Status Register
The read-only SPI Status Register indicates that the SPI is active and is used only with the Philsar, MC13180 and
SiliconWave radios. The SPI Status Register indicates whether the Philsar, MC13180, or SiliconWave radios are
currently busy reading or writing data. The SPI Status Register bits are explained in Table 16-71.
SPI_STATUS
Addr
0x00216138
SPI Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
DONE
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
RESET
0x0001
Table 16-71. SPI Status Register Description
Name
Description
Reserved
Bits 31–1
Reserved—These bits are reserved and should read 0.
DONE
Bit 0
SPI Active or Ready—Indicates whether the BTA is currently reading or
writing data from/to the Philsar/MC13180/SiliconWave radio.
Settings
0 = Currently reading/writing data
1 = Reading/writing done
16.5.11 Frequency Hopping Registers
Five addresses pertain to frequency hopping functions. The Hop 0 (Frequency In) Register and Hop Frequency Out
Register are write and read registers associated with one address.
The write-only frequency hopping registers (HOP0, HOP1, HOP2, HOP3, HOP4) select the frequency hopping
sequence. See Section 16.3.1.7, “Hop Selection Co-Processor,” for a discussion of the contents written to the
register.
Reading address 0x00216140 returns the Hop Frequency Out Register (see section 16.5.11.6). The read-only Hop
Frequency Out Register returns the partially computed hopping frequency channel based on the sequence written to
the Hopping Frequency Registers.
The Register bits are explained in Table 16-72 through Table 16-76.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-85
Programming Model
16.5.11.1 Hop 0 (Frequency In) Register
HOP0
Addr
0x00216140
Hop 0 (Frequency In) Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
CLK_LOW
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-72. Hop 0 (Frequency In) Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
CLK_LOW
Bits 15–0
Lower Part of the Current Clock—Contains bits
[15:0] of the clock that selects the hop frequency.
CLK [15:0] of the current clock
CLK0 is written but ignored by the Bluetooth core as
it is not required by the standard
16.5.11.2 Hop 1 (Frequency In) Register
HOP1
Addr
0x00216144
Hop 1 (Frequency In) Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
CLK_HIGH
TYPE
r
r
r
r
r
r
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
16-86
Freescale Semiconductor
Programming Model
Table 16-73. Hop 1 (Frequency In) Register Description
Name
Description
Settings
Reserved
Bits 31–10
Reserved—These bits are reserved and should read 0.
CLK_HIGH
Bits 9–0
Upper Part of the Current Clock—Contains bits [25:16] of the clock that
selects the hop frequency.
CLK [25:16] of the
current clock
16.5.11.3 Hop 2 (Frequency In) Register
HOP2
Addr
0x00216148
Hop 2 (Frequency In) Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
LAPUAP_LOW
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-74. Hop 2 (Frequency In) Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
LAPUAP_LOW
Bits 15–0
Lower Part of the Combined LAP and 4 LSBs of UAP—Contains
bits [15:0] of the LAP.
Settings
ADDR [15:0] of the LAP
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-87
Programming Model
16.5.11.4 Hop 3 (Frequency In) Register
HOP3
Addr
0x0021614C
Hop 3 (Frequency In) Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
LAPUAP_HIGH
TYPE
r
r
r
r
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-75. Hop 3 (Frequency In) Register Description
Name
Description
Settings
Reserved
Bits 31–12
Reserved—These bits are reserved and should read 0.
LAPUAP_HIGH
Bits 11–0
Upper Part of the Combined LAP and 4 LSBs of
UAP—Contains bits [23:16] of the LAP and bits 3-0 of the UAP.
ADDR [23:16] of the LAP
and ADDR [3:0] of the UAP
16.5.11.5 Hop 4 (Frequency In) Register
HOP4
Addr
0x00216150
Hop 4 (Frequency In) Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SYS
TYPE
STATE
r
r
r
r
r
r
r
r
r
r
r
r
r
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
16-88
Freescale Semiconductor
Programming Model
Table 16-76. Hop 4 (Frequency In) Register Description
Name
Description
Settings
Reserved
Bits 31–3
Reserved—These bits are reserved and should read 0.
SYS
Bit 2
Hop System—Controls whether the unit is a 23-hop or 79-hop
system.
0 = 79-hop system
1 = 23-hop system
STATE
Bits 1–0
Hop State—Controls the operation of the hop co-processor
according to the operating state of the unit.
00 = Page/inquiry scan
01 = Page/inquiry
10 = Page/inquiry response
11 = Connection
16.5.11.6 Hop Frequency Out Register
The read-only Hop Frequency Out Register returns the partially computed hopping frequency channel based on the
sequence written to the Hopping Frequency Registers. The software performs a subsequent module-79 or
module-23 operation (according to the country) to complete the computation. The Hop Frequency Out Register bits
are explained in Table 16-77.
HOP_FREQ_OUT
Addr
0x00216140
Hop Frequency Out Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
HOP_OUT
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-77. Hop Frequency Out Register Description
Name
Description
Settings
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
HOP_OUT
Bits 7–0
Hopping Sequence Selection Output—Reads
from the hopping sequence co-processor output
after the Hopping Frequency Registers have been
written. Software must complete the computation of
the hop frequency channel.
This register reads the results of the partial
computation to select the hop frequency.
Software is expected to complete the addition
of F (see the Bluetooth specifications) and
also the modulo operation.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-89
Programming Model
16.5.12 Interrupt Register
There is one interrupt control register.
16.5.12.1 Interrupt Vector Register
Reading the Interrupt Vector Register indicates the last BTA interrupt that occurred. The BTA generates the
following interrupts:
•
Timer interrupt
•
Interrupt when a frame is received or transmitted
•
Interrupt when the header of a frame is received or transmitted
•
SYSTICK interrupt
When 1 is written to any bit in the Interrupt Vector Register, the interrupt flag associated with that bit is cleared.
The Interrupt Vector Register bits are described in Table 16-78.
INTERRUPT_VECTOR
Addr
0x00216160
Interrupt Vector Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
TIMER
EOF
EOH
SYSTICK
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0X0000
Table 16-78. Interrupt Vector Register Description
Name
Description
Settings
Reserved
Bits 31–4
Reserved—These bits are reserved and should read 0.
TIMER
Bit 3
Timer Interrupt—Indicates whether a Bluetooth application timer interrupt has
occurred. Write 1 to clear.
0 = No timer interrupt
1 = Timer interrupt
EOF
Bit 2
End of Frame Interrupt—Indicates whether an end of frame transmission and
reception has occurred. Write 1 to clear.
0 = No EOF interrupt
1 = EOF interrupt
EOH
Bit 1
End of Header Interrupt—Indicates whether an end of header reception has
occurred. See Section 16.5.1, “Sequencer Registers.” Write 1 to clear.
0 = No EOH interrupt
1 = EOH interrupt
MC9328MX1 Reference Manual, Rev. 6.1
16-90
Freescale Semiconductor
Programming Model
Table 16-78. Interrupt Vector Register Description (continued)
Name
Description
SYSTICK
Bit 0
Settings
0 = No SYSTICK
interrupt
1 = SYSTICK interrupt
SYSTICK Interrupt—Indicates whether a SYSTICK of the current clock has
occurred. Write 1 to clear.
16.5.13 Joint Detect Registers
Two addresses pertain to joint detection functions. These registers are primarily used for testing the Bluetooth
radio.
16.5.13.1 Synchronization Metric Register
The read-only Synchronization Metric Register returns the peak value of the correlation energy. The energy
depends primarily on the access word. The Synchronization Metric Register bits are explained in Table 16-79.
SYNC_METRIC
Addr
0x00216170
Synchronization Metric Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SYNC_METRIC
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-79. Synchronization Metric Register Description
Name
Description
Reserved
Bits 31–15
Reserved—These bits are reserved and should read 0.
SYNC_METRIC
Bits 14–0
Synchronization Metric—Indicates the peak value of the correlation energy.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-91
Programming Model
16.5.13.2 Synchronize Frequency Carrier Register
The read-only Synchronize Frequency Carrier Register (SYNC_FC) returns the offset from the carrier frequency.
The resolution is 1/128 MHz per bit. The Synchronize Frequency Carrier Register bits are explained in
Table 16-80.
SYNC_FC
Addr
0x00216174
Synchronize Frequency Carrier Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SYNC_FC
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-80. Synchronize Frequency Carrier Register Description
Name
Description
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
SYNC_FC
Bits 7–0
Carrier Frequency Offset—Indicates the offset from the carrier frequency with a resolution of 1/128
MHz per bit.
MC9328MX1 Reference Manual, Rev. 6.1
16-92
Freescale Semiconductor
Programming Model
16.5.14 Bit Reverse Registers
Two addresses pertain to reversing functions.
16.5.14.1 Word Reverse Register
The Word Reverse Register is written with the 16-bit word to be bit reversed. When read, the register gives the bit
reversed word. The Word Reverse Register bits are explained in Table 16-81.
WORD_REVERSE
Addr
0x00216178
Word Reverse Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
WORD_REVERSED
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-81. Word Reverse Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
WORD_REVERSED
Bits 15–0
Word to be Bit Reversed—Receives the 16-bit
word to be bit reversed.
This register is written with the 16-bit
word to be bit reversed.
Word Reversed—Returns the bit reversed word.
When read, it gives the bit reversed
word.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
16-93
Programming Model
16.5.14.2 Byte Reverse Register
The Byte Reverse Register (BYTE_REVERSE) is written with the byte to be bit reversed. On reading the register
gives the bit reversed word. The Byte Reverse Register register bits are explained in Table 16-82.
BYTE_REVERSE
Addr
0x0021617C
Byte Reverse Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
BYTE_REVERSED
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 16-82. Byte Reverse Register Description
Name
Description
Settings
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
BYTE_REVERSED
Bits 7–0
Byte to be Bit Reversed—Receives the byte
to be bit reversed.
This register is written with the byte to be
bit reversed.
Byte Reversed—Receives the bit reversed
byte.
When read, it gives the bit reversed byte.
MC9328MX1 Reference Manual, Rev. 6.1
16-94
Freescale Semiconductor
Chapter 17
Multimedia Accelerator (MMA)
17.1 Introduction
Many digital signal processing algorithms require iterative operations that can be closely pipelined, however they
require irregular addressing for data access. These algorithms include FIR filtering, correlation, and FFT
operations. In many system implementations, these operations account for a large percentage of the total
processing cycles.
The multimedia accelerator (MMA) provides theMC9328MX1 with digital signal processing capability while
maintaining efficient utilization of system and bus resources. The MMA in conjunction with the ARM9 processor
core (ARM920T processor), form a hybrid operating environment that combines the efficiency and simplicity of a
RISC processor with the powerful, number crunching, iterative operations of a digital signal processor. The RISC
processor implements the algorithms and processes, assisted by the MMA in crucial digital signal processing
operations. Applications include MPEG or MP3 encoding/decoding and speech compression/decompression such
as G.723.1, CELP, or RPE-LTP for GSM.
17.2 MMA Operation
The MMA module consists of two major blocks—a multiply-accumulate (MAC) block and a discrete cosine
transform (DCT) block. Each of these blocks has its own set of control registers. The control registers are accessed
by the ARM920T processor for configuration as well as data input and result access.
The ARM920T processor enables the signal processing functions in the MMA, which then automatically issues
data access requests to the MC9328MX1’s embedded SRAM (eSRAM) through the memory controller to perform
the required functions. The MMA can read from or write to the eSRAM. Output data is stored in the internal FIFO
of the MMA. If the FIFO is not cleared, MMA processes halt so that no output data is overwritten or lost.
17.2.1 Memory Access
The MMA supports only 32–bit access to its registers because the bus interface to the system bus, referred to as the
Advanced High-performance Bus (AHB), is 32 bits wide. Because the MMA processes data that is 24 bits wide,
access to memory is always in 32–bit words. The MMA supports both big endian and little endian access.
The MMA’s access to the eSRAM is shared with the liquid crystal display controller (LCDC) and the ARM920T
processor. LCDC access to the eSRAM has the highest priority, followed by ARM920T processor access, and
finally MMA access. For this reason, data access latency of the MMA to the eSRAM can be as long as the LCDC
data burst access.
Figure 17-2 on page 17-3 shows the data access to theeSRAM by the MMA and the ARM920T processor.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-1
MMA Operation
AHB Access
Control
AHB
Ctrl Registers
Data Port
ARM920T Core
DCT
MAC
Data Access Controller
Memory
Controller
eSRAM
External
Memory
Figure 17-1. MMA Data Access
17.2.2 MAC
The MAC block provides theMC9328MX1 with fast multiply-accumulate capability. It can perform 1-D × 1-D,
1-D × 2-D, 2-D × 1-D and 2-D × 2-D matrix multiplication to support applications such as MPEG audio encoder
subband filtering, decoder subband synthesis, and MP3 IMDCT.
17.2.2.1 Basic MAC Operation
Two circular data addressing units in the MMA provide the control to fetch data for two operands. All memory
access is in 32–bit words. The MAC can perform 24–bit × 24–bit signed, unsigned, or alternating sign
multiplication. The 48–bit multiplier output is added to a 56–bit accumulator, allowing for 8–bit overflow. After a
user-defined number of MAC iterations, the accumulator value is stored in a 32 × 32–bit FIFO and the accumulator
is cleared. The user can select which 32–bit subset of the 56–bit accumulator result is stored in the FIFO.
17.2.2.2 Data Access
The two operands for the multiplier are supplied by the X and Y registers. The data for these two registers is loaded
from memory by the data access controller. The MMA maintains two circular buffers in theeSRAM, one each for
the X and Y operands.
To limit how long the bus is held when the MMA accesses memory, the MMA_MAC_BURST register sets the
number of burst cycles permitted for each access, after which theeSRAM is released. The MMA resumes operation
if there are no othereSRAM access requests pending.
Circular buffer operation for the X registers is shown in Figure 17-2 on page 17-3.
MC9328MX1 Reference Manual, Rev. 6.1
17-2
Freescale Semiconductor
MMA Operation
eSRAM
Base Register
Points to the start
address of the circular
buffer.
+
INDEX_LOAD
Index Register
Address Index
Base register added
to Index register to
produce Address
Index
Increment Register
Modify Register
This value is added to the
Index Register after every
XCOUNT iteration if the
X INDEX INCR bit is set.
This value is added to the
Address Index after each
access.
+
Length
+
Address Index added to the
Base Register to yield the
actual physical location
a) Initially
b) After every
MMA_MAC_XCOUNT
iteration if the
X INDEX LOAD bit is set.
Length Register
Determines the size of the circular buffer. Actual
Index = (index - length). Actual physical location
is (Actual Index + Base)
Figure 17-2. Circular Buffering Operation
17.2.2.3 Cache
The X operand access has an associated cache and cache controller. Initially, the cache is cleared and the X
operand data is accessed from theeSRAM and stored in the cache. Subsequent accesses to the same address cause a
cache hit and the data is accessed from the cache.
The cache is a memory block of 512 24–bit words. Each word also has an associated valid bit to indicate data
validity. The cache can be enabled or disabled. To fully use the cache, the base address of the operand must be on a
2K boundary. When a data access matches an address in the cache and the valid bit for that word is set, data is
fetched from the cache. When the valid bit is cleared, data is accessed from theeSRAM or from external memory
and stored in the cache, and the valid bit is set. The cache is cleared only by writing 1 to the CACHE CLR bit. This
action also registers the base address of the 2K boundary as the valid cache block address. The user must program
the MMA_MAC_XBASE register and the MMA_MAC_XINDEX register before clearing the cache.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-3
MMA Operation
17.2.3 DCT/iDCT
The DCT/iDCT block in the MMA performs 2-D 8 × 8 discrete cosine transforms and inverse discrete cosine
transforms on 8 × 8 blocks of pixel data. The design is based on a distributed arithmetic processor that computes
two bits at a time. Latency is approximately 170 clock cycles after filling the input FIFO.
Figure 17-3 is a block diagram of the DCT/iDCT.
64 × 16
Data Buffer
AHB
or
Mem Ctrl
Interface
FIFO
(32 × 32)
DCT
Figure 17-3. DCT/iDCT Architecture
The DCT/iDCT can be programmed to access data through the AHB bus or through the memory controller. When
the memory controller is used, addresses are generated automatically—the user programs the start and destination
addresses, the number of blocks in the X-direction (XCOUNT) and Y-direction (YCOUNT), and the address
offsets. The source address and destination address can be same.
Input data is loaded into a 32 × 32 FIFO. Each word in the FIFO represents two 16–bit pixels. The accuracy of the
input data is 9 bits for a DCT, so the 7 least significant bits (LSBs) must be zero-filled. For an iDCT, the accuracy
is 12 bits, so the 4 LSBs must be zero-filled.
DCT Format
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
D2
D1
D0
0
0
0
0
iDCT Format
D11
D10
D9
D8
D7
D6
D5
D4
D3
Figure 17-4. Data Formatting for DCT and iDCT
The DCT/iDCT is enabled by writing 1 to the DCT ENA bit in the MMA_DCTCTRL register. After the bit is set,
the DCT/iDCT is performed automatically. When the process is complete, an interrupt is generated and the DCT
ENA bit is cleared. In this way, a DCT/iDCT can be run for an entire frame of data.
MC9328MX1 Reference Manual, Rev. 6.1
17-4
Freescale Semiconductor
Programming Model
17.3 Programming Model
The MMA module includes 33 user-accessible 32-bit registers. Table 17-1 on page 17-5 summarizes these
registers and their addresses.
Table 17-1. MMA Module Register Memory Map
Description
Name
Address
MMA MAC Control Registers
MMA MAC Module Register
MMA_MAC_MOD
0x00222000
MMA MAC Control Register
MMA_MAC_CTRL
0x00222004
MMA MAC Multiply Counter Register
MMA_MAC_MULT
0x00222008
MMA MAC Accumulate Counter Register
MMA_MAC_ACCU
0x0022200C
MMA MAC Interrupt Register
MMA_MAC_INTR
0x00222010
MMA MAC Interrupt Mask Register
MMA_MAC_INTR_MASK
0x00222014
MMA MAC FIFO Register
MMA_MAC_FIFO
0x00222018
MMA MAC FIFO Status Register
MMA_MAC_FIFO_STAT
0x0022201C
MMA MAC Burst Count Register
MMA_MAC_BURST
0x00222020
MMA MAC Bit Select Register
MMA_MAC_BITSEL
0x00222024
MMA MAC X Register Control Registers
MMA MAC X Base Address Register
MMA_MAC_XBASE
0x00222200
MMA MAC X Index Register
MMA_MAC_XINDEX
0x00222204
MMA MAC X Length Register
MMA_MAC_XLENGTH
0x00222208
MMA MAC X Modify Register
MMA_MAC_XMODIFY
0x0022220C
MMA MAC X Increment Register
MMA_MAC_XINCR
0x00222210
MMA MAC X Count Register
MMA_MAC_XCOUNT
0x00222214
MMA MAC Y Register Control Registers
MMA MAC Y Base Address Register
MMA_MAC_YBASE
0x00222300
MMA MAC Y Index Register
MMA_MAC_YINDEX
0x00222304
MMA MAC Y Length Register
MMA_MAC_YLENGTH
0x00222308
MMA MAC Y Modify Register
MMA_MAC_YMODIFY
0x0022230C
MMA MAC Y Increment Register
MMA_MAC_YINCR
0x00222310
MMA MAC Y Count Register
MMA_MAC_YCOUNT
0x00222314
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-5
Programming Model
Table 17-1. MMA Module Register Memory Map (continued)
Description
Name
Address
MMA DCT/iDCT Registers
DCT/iDCT Control Register
MMA_DCTCTRL
0x00222400
DCT/iDCT Version Register
MMA_DCTVERSION
0x00222404
DCT/iDCT IRQ Enable Register
MMA_DCTIRQENA
0x00222408
DCT/iDCT IRQ Status Register
MMA_DCTIRQSTAT
0x0022240C
DCT/iDCT Source Data Address
MMA_DCTSRCDATA
0x00222410
DCT/iDCT Destination Data Address
MMA_DCTDESDATA
0x00222414
DCT/iDCT X-Offset Address
MMA_DCTXOFF
0x00222418
DCT/iDCT Y-Offset Address
MMA_DCTOFF
0x0022241C
DCT/iDCT XY Count
MMA_DCTXYCNT
0x00222420
DCT/iDCT Skip Address
MMA_DCTSKIP
0x00222424
DCT/iDCT Data FIFO
MMA_DCTFIFO
0x00222500
17.3.1 MMA MAC Control Registers
There are 10 registers that control general MMA MAC operation.
17.3.1.1 MMA MAC Module Register
MMA_MAC_MOD
BIT
31
Addr
0x00222000
MMA MAC Module Register
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
rw
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RST
TYPE
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
MOD ENAB
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
17-6
Freescale Semiconductor
Programming Model
Table 17-2. MMA MAC Module Register Description
Name
Description
Settings
RST
Bit 31
Software Reset for the MAC—indicates whether the reset sequence is
complete.
Reserved
Bits 30–1
Reserved—These bits are reserved and should read 0.
MOD ENAB
Bit 0
Module Enable—Enables or disables the MAC.
0 = Reset is complete
1 = Reset is in progress
0 = Disable the MAC
1 = Enable the MAC
17.3.1.2 MMA MAC Control Register
MMA_MAC_CTRL
16
Y SIGNED
17
Y SIGN
INI
18
Y SIGN
ALT
19
Y_DATA_SEL
20
Y
INDEX
LOAD
21
Y
INDEX
INCR
22
Y INDEX CLR
23
Y MODIFY PRESET
24
X SIGNED
25
X SIGN
INI
26
X SIGN
ALT
27
X_DATA_SEL
28
X INDEX
LOAD
29
X INDEX
INCR
30
X INDEX CLR
TYPE
31
X MODIFY PRESET
BIT
Addr
0x00222004
MMA MAC Control Register
w
w
rw
rw
rw
rw
rw
rw
w
w
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
CACHE
CLR
CACHE
EN
OP EN
RESET
0x0000
BIT
15
TYPE
14
13
12
11
10
9
8
7
r
r
r
r
r
r
r
r
r
r
r
r
r
w
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-3. MMA MAC Control Register Description
Name
Description
Settings
X MODIFY
PRESET
Bit 31
X Modify Preset—Presets MMA_MAC_XMODIFY register
to value 0x00000004.
0 = MMA_MAC_XMODIFY Register is not
preset
1 = MMA_MAC_XMODIFY Register is
preset to value 0x00000004
X INDEX CLR
Bit 30
X Index Clear—Clears MMA_MAC_XINDEX register to
value of 0x00000000.
0 = MMA_MAC_XINDEX Register is not
reset.
1 = MMA_MAC_XINDEX Register is reset
to value 0x00000000
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-7
Programming Model
Table 17-3. MMA MAC Control Register Description (continued)
Name
Description
Settings
X INDEX INCR
Bit 29
X Index Increment—Determines whether the
MMA_MAC_XINDEX register in the XDAC module is
incremented by the value in the MMA_MAC_XINCR
register for every (MMA_MAC_XCOUNT + 1) iteration.
X INDEX INCR is used with X INDEX LOAD.
0 = MMA_MAC_XINDEX is not
incremented
1 = MMA_MAC_XINDEX register is
incremented
X INDEX LOAD
Bit 28
X Index Load—Determines whether the index in the
XDAC module is loaded with the values in the
MMA_MAC_XINDEX register for every
(MMA_MAC_XCOUNT + 1) iteration. When set, the Index
is reloaded with the MMA_MAC_XINDEX register value.
When cleared, the index retains the last stored value.
0 = XDAC index register is not reloaded
1 = XDAC index register is reloaded
X_DATA_SEL
Bit 27
X Data Select—Selects which bits in the 32-bit data bus
are used to create the 24-bit operand.
0 = Bits [23:0] used as operand
1 = Bits [31:8] used as operand
Note: When the cache is enabled, X_DATA_SEL must
be set to one.
X SIGN ALT
Bit 26
X Operand Sign Alternate—Determines whether the X
operand alternates its operand sign of the operation.
0 = X operand sign is not alternated
1 = X operand sign is alternated
X SIGN INI
Bit 25
X Operand Initial Sign—Determines the X operand initial
sign of the operation with x.
0 = +(x)
1 = -(x)
X SIGNED
Bit 24
X Operand Signed—Determines whether the X operand
is signed or unsigned. When set, the X operand is a signed
value. When cleared, the X operand is unsigned.
0 = X operand is unsigned
1 = X operand is signed
Y MODIFY
PRESET
Bit 23
Y Modify Preset—Presets MMA_MAC_YMODIFY register
to value 0x00000004.
0 = MMA_MAC_YMODIFY Register is not
preset
1 = MMA_MAC_YMODIFY Register is
preset to value 0x00000004
Y INDEX CLR
Bit 22
Y Index Clear—Setting this bits clears the
MMA_MAC_YINDEX register to value 0x00000000.
0 = MMA_MAC_YINDEX is not reset
1 = MMA_MAC_YINDEX is reset to value
of 0x000 0000
Y INDEX INCR
Bit 21
Y Index Increment—Determines whether the
MMA_MAC_YINDEX register in the YDAC module is
incremented by the value in the MMA_MAC_YINCR
register for every (MMA_MAC_YCOUNT + 1) iteration.
Y INDEX INCR is used with Y INDEX LOAD.
0 = MMA_MAC_YINDEX is not
incremented
1 = MMA_MAC_YINDEX is incremented
Y INDEX LOAD
Bit 20
Y Index Load—Determines whether the index in the
YDAC module is loaded with the values in the
MMA_MAC_YINDEX register for every
(MMA_MAC_YCOUNT + 1) iteration. When set, the index
is reloaded with the MMA_MAC_YINDEX register value.
When cleared, the index retains the last stored value.
0 = Index register is not reloaded
1 = Index register is reloaded
Y_DATA_SEL
Bit 19
Y Data Select—Selects which bits in the 32-bit data bus
are used to create the 24-bit operand.
0 = Bits [23:0] used as operand
1 = Bits [31:8] used as operand
MC9328MX1 Reference Manual, Rev. 6.1
17-8
Freescale Semiconductor
Programming Model
Table 17-3. MMA MAC Control Register Description (continued)
Name
Description
Settings
Y SIGN ALT
Bit 18
Y Operand Sign Alternate—Determines whether the Y
operand alternates its operand sign of the operation.
0 = Y operand sign is not alternated
1 = Y operand sign is alternated
Y SIGN INI
Bit 17
Y Operand Initial Sign—Determines whether the Y
operand initial sign of the operation with y.
0 = +(y)
1 = -(y)
Y SIGNED
BIT 16
Y Operand Signed—Determines whether the Y operand
is signed or unsigned. When set, the Y operand is a signed
value. When cleared, the Y operand is unsigned.
0 = Y operand is unsigned
1 = Y operand is signed
Reserved
Bits 15–3
Reserved—These bits are reserved and should read 0.
CACHE CLR
Bit 2
Cache Clear—Clears the X operand cache and writes the
(base + index) register value into the cache block register.
0 = No effect
1 = Clear X operand cache and write
(base+index) register value into the
cache block register
CACHE EN
Bit 1
Cache Enable—Enables or disables the X operand cache.
0 = X operand cache is disabled
1 = X operand cache is enabled
OP EN
Bit 0
Operation Enable—Initiates MAC operation and indicates
if the operation is complete. The operation does not start if
MMA_MAC_MULT register contains 0.
0 = MAC operation is complete
1 = Initiate MAC operation or MAC
operation is not complete
17.3.1.3 MMA MAC Multiply Counter Register
MMA_MAC_MULT
Addr
0x00222008
MMA MAC Multiply Counter Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0X0000
BIT
15
14
13
12
11
10
9
8
MULT COUNTER
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0X0000
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-9
Programming Model
Table 17-4. MMA MAC Multiply Counter Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
MULT COUNTER
Bits 15–0
Multiply Counter—Determines the number of multiply operations that the MAC module performs. For
proper operation, this value must be an integer multiple of the (MMA_MAC_ACCU + 1) value.
17.3.1.4 MMA MAC Accumulate Counter Register
MMA_MAC_ACCU
Addr
0x0022200C
MMA MAC Accumulate Counter Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0X0000
BIT
15
14
13
12
11
10
9
8
ACCU COUNTER
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0X0000
Table 17-5. MMA MAC Accumulate Counter Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
ACCU
COUNTER
Bits 15–0
Accumulate Counter—Determines the number of accumulate operations that the MAC module performs
before writing the accumulated result to the FIFO. The value written to this register is the actual value
minus 1 (0x0003 for four accumulate operations).
MC9328MX1 Reference Manual, Rev. 6.1
17-10
Freescale Semiconductor
Programming Model
17.3.1.5 MMA MAC Interrupt Register
MMA_MAC_INTR
Addr
0x00222010
MMA MAC Interrupt Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
OP
ERROR
OP
END
FIFO
EMPT
FIFO
HALF
FIFO
FULL
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
6
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
RESET
0x0004
Table 17-6. MMA MAC Interrupt Register Description
Name
Description
Settings
Reserved
Bits 31–5
Reserved—These bits are reserved and should read 0.
OP ERROR
Bit 4
OP ERROR Interrupt—Sets when there is a memory access
error from the bus. Write 1 to clear
0 = No error in operation.
1 = Error in operation.
OP END
Bit 3
Operation End Interrupt—Sets when the MAC operation
ends. Write a 1 to clear.
0 = MAC operation is not complete
1 = MAC operation is complete
FIFO EMPT
Bit 2
FIFO Empty Interrupt—Sets when the FIFO is empty. Write
a 1 to clear.
0 = FIFO is not empty
1 = FIFO is empty
FIFO HALF
Bit 1
FIFO Half Full Interrupt—Sets when the FIFO is half full.
Write a 1 to clear.
0 = FIFO is not half full
1 = FIFO is half full
FIFO FULL
Bit 0
FIFO Full Interrupt—Sets when the FIFO is full. Write a 1 to
clear.
0 = FIFO is not full
1 = FIFO is full
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-11
Programming Model
17.3.1.6 MMA MAC Interrupt Mask Register
MMA_MAC_INTR_MASK
MMA MAC Interrupt Mask Register
Addr
0x00222014
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
OP
OP
FIFO FIFO FIFO
ERRO
END EMPT HALF FULL
R
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
RESET
0x001F
Table 17-7. MMA MAC Interrupt Mask Register Description
Name
Description
Settings
Reserved
Bits 31–5
Reserved—These bits are reserved and should read 0.
OP ERROR
Bit 4
OP ERROR Mask—Masks the OP ERROR Interrupt.
0 = Mask on/enable interrupt
1 = Mask off/disable interrupt.
OP END
Bit 3
Operation End Interrupt Mask—Masks the OP END interrupt.
0 = Mask on/enable interrupt
1 = Mask off/disable interrupt
FIFO EMPT
Bit 2
FIFO Empty Interrupt Mask—Masks the FIFO EMPT interrupt.
0 = Mask on/enable interrupt
1 = Mask off/disable interrupt
FIFO HALF
Bit 1
FIFO Half Full Interrupt Mask—Masks the FIFO HALF interrupt.
0 = Mask on/enable interrupt
1 = Mask off/disable interrupt
FIFO FULL
Bit 0
FIFO Full Interrupt Mask—Masks the FIFO FULL interrupt.
0 = Mask on/enable interrupt
1 = Mask off/disable interrupt
MC9328MX1 Reference Manual, Rev. 6.1
17-12
Freescale Semiconductor
Programming Model
17.3.1.7 MMA MAC FIFO Register
MMA_MAC_FIFO
BIT
31
30
Addr
0x00222018
MMA MAC FIFO Register
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FIFO REGISTER
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
FIFO REGISTER
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-8. MMA MAC FIFO Register Description
Name
FIFO REGISTER
Bits 31–0
Description
FIFO Read Register—Returns FIFO output.
17.3.1.8 MMA MAC FIFO Status Register
MMA_MAC_FIFO_STAT
BIT
31
30
29
Addr
0x0022201C
MMA MAC FIFO Status Register
28
27
26
25
24
23
22
21
20
19
18
17
16
FIFO COUNT
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
FIFO
EMPT
FIFO
HALF
FIFO
FULL
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
RESET
0x0004
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-13
Programming Model
Table 17-9. MMA MAC FIFO Status Register Description
Name
Description
Settings
Reserved
Bits 31–21
Reserved—These bits are reserved and should read 0.
FIFO COUNT
Bits 20–16
FIFO Data Count—Indicates the number of data in the FIFO.
Reserved
Bits 15–3
Reserved—These bits are reserved and should read 0.
FIFO EMPT
Bit 2
FIFO Empty Status—Indicates the status of the FIFO EMPT
interrupt.
See description
FIFO HALF
Bit 1
FIFO Half Full Status—Indicates the status of the FIFO HALF
interrupt.
See description
FIFO FULL
Bit 0
FIFO Full Status—Indicates the status of the FIFO FULL interrupt.
See description
See description
17.3.1.9 MMA MAC Burst Count Register
MMA_MAC_BURST
Addr
0x00222020
MMA MAC Burst Count Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
BURST COUNT
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-10. MMA MAC Burst Count Register Description
Name
Description
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
BURST COUNT
Bits 7–0
Memory Access Burst Count—Determines the maximum number of read accesses to
memory allowed in one burst. This feature ensures that the MMA does not hold the memory
bus for too long.
MC9328MX1 Reference Manual, Rev. 6.1
17-14
Freescale Semiconductor
Programming Model
17.3.1.10 MMA MAC Bit Select Register
MMA_MAC_BITSEL
Addr
0x00222024
MMA MAC Bit Select Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
BITSEL
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-11. MMA MAC Bit Select Register Description
Name
Description
Reserved
Bits 31–3
Reserved—These bits are reserved and should read 0.
BITSEL
Bits 2–0
Accumulator Output Bit Select—Selects which 32–bit subset of the
56–bit accumulator is stored in the FIFO.
Settings
000 = bits 31:0
001 = bits 35:4
010 = bits 39:8
011 = bits 43:12
100 = bits 47:16
101 = bits 51:20
110 = bits 55:24
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-15
Programming Model
17.3.2 MMA MAC XY Count Accumulate Register
MMA MAC XY Count Accumulate
Register
MMA_MAC_XYACCU
BIT
31
30
29
28
27
26
25
24
23
22
Addr
0x00222040
21
20
19
18
17
16
MMA_MAC_XY_COUNT
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
MMA_MAC_XY_COUNT
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
17-16
Freescale Semiconductor
Programming Model
17.3.3 MMA MAC X Register Control Registers
There are 6 registers that reside in the X operand Data Access Controller (XDAC). The XDAC has an associated
cache. The initial access by the XDAC is a cache miss, so the operand is fetched from memory and stored in the
cache. Subsequent accesses to the same location cause cache hits, so the data is loaded from the cache instead of
from memory.
17.3.3.1 MMA MAC X Base Address Register
MMA_MAC_XBASE
BIT
31
30
29
MMA MAC X Base Address Register
28
27
26
25
24
23
Addr
0x00222200
22
21
20
19
18
17
16
XBASE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
XBASE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-12. MMA MAC X Base Address Register Description
Name
XBASE
Bits 31–0
Description
X Base Address—Determines the base/start address of the X data buffer. Writing 0 to this register
will force the module to use the data stored in the cache when Cache_En bit is set.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-17
Programming Model
17.3.3.2 MMA MAC X Index Register
MMA_MAC_XINDEX
Addr
0x00222204
MMA MAC X Index Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
XINDEX
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-13. MMA MAC X Index Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
XINDEX
Bits 15–0
MAC X Index—Determines part of the offset from the base address.
The X Address Index (actual access address) is equal to MMA_MAC_XBASE + contents of
MMA_MAC_XINDEX + [contents of MMA_MAC_XMODIFY + the number of iterations since initialization, the
index last wrapped, or the last MMA_MAC_XCOUNT iterations (when the X INDEX LOAD bit is set)].
17.3.3.3 MMA MAC X Length Register
MMA_MAC_XLENGTH
BIT
31
30
29
Addr
0x00222208
MMA MAC X Length Register
28
27
26
25
24
23
22
21
20
19
18
17
16
COLUMN
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
LENGTH
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
17-18
Freescale Semiconductor
Programming Model
Table 17-14. MMA MAC X Length Register Description
Name
Description
COLUMN
Bits 31–16
Column Size—MMA_MAC_XINDEX wraps around to the base of the buffer when MMA_MAC_XINDEX +
MMA_MAC_XINCR is greater than COLUMN. Writing 0 to this register will disable the wrapping of address.
Note: Note: If the current MMA_MAC_XINDEX is 12 and the COLUMN is 16, MMA_MAC_XINCR is 8, then
the next XINDEX will be (12+8)% 16 == 4. The physical address is 4 + MMA_MAC_XBASE.
LENGTH
Bits 15–0
Circular Length—Circular Length - Determines the size of the X data buffer. Address_Index wraps back to
base of buffer when Address_Index + MMA_MAC_XMODIFY is greater than LENGTH. Writing 0 to this
register will disable the wrapping of address.
Note: Note: If the current Address_Index is 12 and the LENGTH is 16, MMA_MAC_XMODIFY is 8, then the
next Address_Index will be (12+8)% 16 == 4. The physical address is 4 + MMA_MAC_XBASE.
17.3.3.4 MMA MAC X Modify Register
MMA_MAC_XMODIFY
Addr
0x0022220C
MMA MAC X Modify Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
XMODIFY
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
RESET
0x0004
Table 17-15. MMA MAC X Modify Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
XMODIFY
Bits 15–0
X Increment—Determines the size of the increment to the X Address Index after each iteration.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-19
Programming Model
17.3.3.5 MMA MAC X Increment Register
MMA_MAC_XINCR
Addr
0x00222210
MMA MAC X Increment Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
XINCR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-16. MMA MAC X Increment Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
XINCR
Bits 15–0
X Increment—Determines the size of the increment to the X Address Index after each
(MMA_MAC_XCOUNT +1) iteration.
17.3.3.6 MMA MAC X Count Register
This 16–bit read/write register sets the MAC Count value for the increment of the Index register when the
X INDEX INCR bit in the MMA_MAC_CTRL register is set.
MMA_MAC_XCOUNT
Addr
0x00222214
MMA MAC X Count Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
XCOUNT
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
RESET
0x0004
MC9328MX1 Reference Manual, Rev. 6.1
17-20
Freescale Semiconductor
Programming Model
Table 17-17. MMA MAC X Count Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
XCOUNT
Bits 15–0
X Count—Determines the number of iterations required to:
• reload the XDAC Address Index with [MMA_MAC_XBASE + MMA_MAC_XINDEX] (when the
X INDEX LOAD bit is set)
or,
• increment the MMA_MAC_XINDEX by the value in MMA_MAC_XINCR (when the X INDEX INCR bit
is set). The value written to this register is the actual value minus 1 (0x0003 for four iterations).
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-21
Programming Model
17.3.4 MMA MAC Y Register Control Registers
There are six registers that reside in the Y operand Data Access Controller (YDAC). The YDAC does not have a
cache, so it always fetches data from memory.
17.3.4.1 MMA MAC Y Base Address Register
MMA_MAC_YBASE
BIT
31
30
29
MMA MAC Y Base Address Register
28
27
26
25
24
23
Addr
0x00222300
22
21
20
19
18
17
16
YBASE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
YBASE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-18. MMA MAC Y Base Address Register Description
Name
Description
YBASE
Bits 31–0
Y Base Address—Determines the base/start address of the Y data buffer.
17.3.4.2 MMA MAC Y Index Register
MMA_MAC_YINDEX
Addr
0x00222304
MMA MAC Y Index Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
YINDEX
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
17-22
Freescale Semiconductor
Programming Model
Table 17-19. MMA MAC Y Index Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
YINDEX
Bits 15–0
Y Index—Determines part of the offset from the base address.
The Y Address Index (actual access address) is equal to MMA_MAC_YBASE + MMA_MAC_YINDEX +
[MMA_MAC_YMODIFYr × the number of iterations since initialization, the index last wrapped, or the last
MMA_MAC_YCOUNT iterations (if the Y INDEX LOAD bit is set)].
17.3.4.3 MMA MAC Y Length Register
MMA_MAC_YLENGTH
BIT
31
30
29
Addr
0x00222308
MMA MAC Y Length Register
28
27
26
25
24
23
22
21
20
19
18
17
16
COLUMN
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
LENGTH
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-20. MMA MAC Y Length Register Description
Name
COLUMN
Bits 31–16
Description
Column Size—MMA_MAC_YINDEX wraps around to the base of the buffer when MMA_MAC_YINDEX +
MMA_MAC_YINCR is greater than COLUMN. Writing 0 to this register will disable the wrapping of address.
Note: Note: If the current MMA_MAC_YINDEX is 12 and the COLUMN is 16, MMA_MAC_YINCR is 8, then
the next YINDEX will be (12+8)% 16 == 4. The physical address is 4 + MMA_MAC_YBASE.
LENGTH
Bits 15–0
Circular Length—Circular Length - Determines the size of the Y data buffer. Address_Index wraps back to
base of buffer when Address_Index + MMA_MAC_YMODIFY is greater than LENGTH. Writing 0 to this
register will disable the wrapping of address.
Note: Note: If the current Address_Index is 12 and the LENGTH is 16, MMA_MAC_YMODIFY is 8, then the
next Address_Index will be (12+8)% 16 == 4. The physical address is 4 + MMA_MAC_YBASE.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-23
Programming Model
17.3.4.4 MMA MAC Y Modify Register
MMA_MAC_YMODIFY
Addr
0x0022230C
MMA MAC Y Modify Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
YMODIFY
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
RESET
0x0004
Table 17-21. MMA MAC Y Modify Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
YMODIFY
Bits 15–0
Y Increment—Determines the size of the increment to the Y Address Index after each iteration.
17.3.4.5 MMA MAC Y Increment Register
MMA_MAC_YINCR
Addr
0x00222310
MMA MAC Y Increment Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
YINCR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
17-24
Freescale Semiconductor
Programming Model
Table 17-22. MMA MAC Y Increment Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
YINCR
Bits 15–0
Y Increment—Determines the size of the increment to the MMA_MAC_YINDEX register after each
(MMA_MAC_YCOUNT+1) iteration.
17.3.4.6 MMA MAC Y Count Register
MMA_MAC_YCOUNT
Addr
0x00222314
MMA MAC Y Count Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
YCOUNT
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-23. MMA MAC Y Count Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
YCOUNT
Bits 15–0
Y Count—Determines the number of iterations required to:
• reload the YDAC Address Index with [MMA_MAC_YBASE + MMA_MAC_YINDEX] (when the
Y INDEX LOAD bit is set)
or,
• increment MMA_MAC_YINDEX by the value in MMA_MAC_YINCR (when the Y INDEX INCR bit is
set). The value written to this register is the actual value minus 1 (0x0003 for four iterations).
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-25
Programming Model
17.3.5 MMA DCT/iDCT Registers
There are 11 registers that control DCT/iDCT functions.
17.3.5.1 DCT/iDCT Control Register
This register controls the function of DCT/iDCT and the interface module. This is a read/write register.
MMA_DCTCTRL
BIT
TYPE
31 30
Addr
0x00222400
DCT/iDCT Control Register
29
28 27 26 25
24
23
22
21
20
19
18
17
16
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
DCT/
IDCT
DCT ENA
RESET
0x0000
BIT
15 14
13
12 11 10
DCT_HWORD_SWAP
TYPE
9
DATAINSHIFT
8
7
SEMA
EN
DCT
XPOSE
DCT
SW
CLK
RST
EN
DCT
BY
PASS
ARMMCM
SEL
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-24. DCT/iDCT Control Register Description
Name
Description
Setting
Reserved
Bits 31–14
Reserved—These bits are reserved and should read 0.
DCT_HWORD
_SWAP
Bit 13
DCT Half-Word Swap—This bit determines if the
data is swapped in half-word (16-bit) or word (32-bit).
DATAINSHIFT
Bits 12–9
DATAINSHIFT—Reserved for future use and should be written with 0 for normal operation.
SEMAEN
Bit 8
SEMAEN—Reserved for future use and must be written with 0 for normal operation.
DCTXPOSE
Bit 7
DCT Transpose—Enables/Disables the DCT output
to be transposed.
0 = Disable transpose
1 = Enable transpose
DCTCLKEN
Bit 6
DCT Clock Enable—Enables/Disables the DCT
clock to save power when DCT is not in use.
0 = Disable clock
1 = Enable clock
SWRST
Bit 5
Software Reset—Resets the DCT Module.
0 = No effect
1 = Resets DCT module
0 = Not swap data in half word, result in
data{data[31:0]}
1 = Swap data in half word data{data[15:0],
data[31:16]
MC9328MX1 Reference Manual, Rev. 6.1
17-26
Freescale Semiconductor
Programming Model
Table 17-24. DCT/iDCT Control Register Description (continued)
Name
Description
Setting
DCTBYPASS
Bit 4
DCT Bypass—Enables DCT/iDCT input data to be
bypassed to the output without being transformed.
0 = Perform transform
1 = Bypass
ARMMCMSEL
Bits 3–2
ARM/Memory Controller Select—Controls
DCT/iDCT module data input and output.
00 = Data in and out through memory controller
01 = Data in through memory controller and out
through ARM9 core.
10 = Data in through ARM9 core and out through
memory controller.
11 = Data in and out through ARM9 core.
DCT/IDCT
Bit 1
DCT/IDCT—Selects either DCT or iDCT.
0 = iDCT
1 = DCT
DCT ENA
Bit 0
DCT Enable—Enables/Disables the DCT/iDCT.
If data is accessed through the memory controller,
DCT ENA is reset to zero after an 8 × 8 transform is
completed.
0 = DCT disabled
1 = DCT enabled
17.3.5.2 DCT/iDCT Version Register
MMA_DCTVERSION
BIT
31
30
29
Addr
0x00222404
DCT/iDCT Version Register
28
27
26
25
24
23
22
21
20
19
18
17
16
VERSION NUMBER
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
VERSION NUMBER
TYPE
r
r
r
r
r
r
r
r
r
RESET
0x0000
Table 17-25. DCT/iDCT Version Register Description
Name
VERSION NUMBER
Bits 31–0
Description
Version Number—Contains the version number of the DCT/iDCT block.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-27
Programming Model
17.3.5.3 DCT/iDCT IRQ Enable Register
MMA_DCTIRQENA
Addr
0x00222408
DCT/iDCT IRQ Enable Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
ERR
INTR
EN
DODEN
DIDEN
DOIEN
DIIEN
DCT
COMP
RESET
0x0000
BIT
15
TYPE
14
13
12
11
10
9
8
7
6
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-26. DCT/iDCT IRQ Enable Register Description
Name
Description
Settings
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
ERRINTREN
Bit 5
Error Interrupt Enable—Enables/Disables interrupt generation when
an error occurs while accessing memory through the memory controller.
0 = Interrupt disabled
1 = Interrupt enabled
DODEN
Bit 4
DMA Output Data Enable—Enables/Disables interrupt generation
when the DMA data out request signal is asserted.
0 = Interrupt disabled
1 = Interrupt enabled
DIDEN
Bit 3
DMA Input Data Enable—Enables/Disables interrupt generation when
the DMA data in request signal is asserted.
0 = Interrupt disabled
1 = Interrupt enabled
DOIEN
Bit 2
Data Output Interrupt Enable—Enables/Disables interrupt generation
when the data out signal is asserted.
0 = Interrupt disabled
1 = Interrupt enabled
DIIEN
Bit 1
Data Input Interrupt Enable—Enables/Disables interrupt generation
when the data in signal is asserted.
0 = Interrupt disabled
1 = Interrupt enabled
DCTCOMP
Bit 0
DCT Complete—Enables/Disables interrupt generation when the DCT
block completes a set of 8 × 8 transforms.
0 = Interrupt disabled
1 = Interrupt enabled
MC9328MX1 Reference Manual, Rev. 6.1
17-28
Freescale Semiconductor
Programming Model
17.3.5.4 DCT/iDCT IRQ Status Register
MMA_DCTIRQSTAT
Addr
0x0022240C
DCT/iDCT IRQ Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
FIFO
FULL
FIFO
EMP
ERR
INTR
DOUT
INTR
DIN
INTR
DCT
COMP
RESET
0x0000
BIT
TYPE
15
14
13
12
11
10
9
8
7
6
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-27. DCT/iDCT IRQ Status Register Description
Name
Description
Settings
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
FIFO FULL
Bit 5
FIFO Full—Indicates whether the FIFO is full or not. Remains high until all
data is read from the FIFO. Write a 1 to clear.
0 = Output FIFO is not filled
1 = Output FIFO is filled, some
data left unread
FIFO EMP
Bit 4
FIFO Empty—Indicates whether the FIFO is filled with input data or not.The
bit is cleared automatically when the input FIFO becomes full. Write a 1 to
clear.
0 = Input FIFO is not filled
1 = Input FIFO is full
ERR INTR
Bit 3
Error Interrupt—Indicates whether an error has occurred while accessing
memory through the memory controller. Write a 1 to clear.
0 = No error has occurred
1 = An error has occurred
DOUTINTR
Bit 2
Data Out Interrupt—Determines when the data out interrupt is asserted.
Write a 1 to clear.
0 = Data out interrupt has
occurred
1 =Data out interrupt has not
occurred
DININTR
Bit 1
Data In Interrupt—Determines when the data in interrupt is asserted. Write
a 1 to clear.
0 = Data In interrupt has
occurred
1 =Data In interrupt has not
occurred
DCTCOMP
Bit 0
Transform Complete—Indicates whether a transform has completed.
Write a 1 to clear.
0 = Transform is not complete
1 = Transform is complete
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-29
Programming Model
17.3.5.5 DCT/iDCT Source Data Address
MMA_DCTSRCDATA
BIT
31
30
29
Addr
0x00222410
DCT/iDCT Source Data Address
28
27
26
25
24
23
22
21
20
19
18
17
16
DCT_SRC_ADDR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DCT_SRC_ADDR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-28. DCT/iDCT Source Data Address Register Description
Name
Description
DCT_SRC_ADDR
Bits 31–0
DCT Source Address—Determines the source address of the data to be transformed.
17.3.5.6 DCT/iDCT Destination Data Address
DCT/iDCT Destination Data
Address
MMA_DCTDESDATA
BIT
31
30
29
28
27
26
25
24
23
Addr
0x00222414
22
21
20
19
18
17
16
DCT_DES_ADDR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DCT_DES_ADDR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-29. DCT/iDCT Destination Data Address Register Description
Name
DCT_DES_ADDR
Bits 31–0
Description
DCT Destination Address—Determines the destination address for the transformed data.
MC9328MX1 Reference Manual, Rev. 6.1
17-30
Freescale Semiconductor
Programming Model
17.3.5.7 DCT/iDCT X-Offset Address
MMA_DCTXOFF
Addr
0x00222418
DCT/iDCT X-Offset Address
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
X-OFFSET
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-30. DCT/iDCT X-Offset Address Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
X-OFFSET
Bits 15–0
X Offset—Determines the offset address along the X-direction from the last transformed block. For
the first block, the start address is the same as MMA_DCTSRCDATA or MMA_DCTDESDATA. For
the following blocks the start address is [MMA_DCTSRCDATA or MMA_DCTDESDATA] +
(X-OFFSET × N) where N = 1, …(X-COUNT – 1) along the X-direction.
17.3.5.8 DCT/iDCT Y-Offset Address
MMA_DCTOFF
Addr
0x0022241C
DCT/iDCT Y-Offset Address
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
Y-OFFSET
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-31
Programming Model
Table 17-31. DCT/iDCT Y-Offset Address Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
Y-OFFSET
Bits 15–0
Y Offset—Determines the number of bytes to skip in the Y direction when accessing each
successive row in a block of data.
17.3.5.9 DCT/iDCT XY Count
MMA_DCTXYCNT
Addr
0x00222420
DCT/iDCT XY Count
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
Y-COUNT
TYPE
X-COUNT
r
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-32. DCT/iDCT XY Count Register Description
Name
Description
Reserved
Bits 31–15
Reserved—These bits are reserved and should read 0.
Y-COUNT
Bits 14–8
Y Count—Controls the number of blocks to be transformed in the Y direction.
Reserved
Bit 7
Reserved—This bit is reserved and should read 0.
X-COUNT
Bits 6–0
X Count—Controls the number of blocks to be transformed in the X direction.
MC9328MX1 Reference Manual, Rev. 6.1
17-32
Freescale Semiconductor
Programming Model
17.3.5.10 DCT/iDCT Skip Address
MMA_DCTSKIP
Addr
0x00222424
DCT/iDCT Skip Address
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SKIP_ADDR
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-33. DCT/iDCT Skip Address Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
SKIP_ADDR
Bits 15–0
SKIP_ADDR—Determines the number of bytes to skip in the X direction when accessing
each successive row in a block of data.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
17-33
Programming Model
17.3.5.11 DCT/iDCT Data FIFO
MMA_DCTFIFO
BIT
31
30
Addr
0x00222500
DCT/iDCT Data FIFO
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DATA
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DATA
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 17-34. DCT/iDCT Data FIFO Register Description
Name
Description
DATA
Bits 31–0
Data—Stores input data to be transformed and the outputs the data after transformation. Writing to this register
stores input data in the FIFO. Reading this register retrieves the results of the transformation from the FIFO. The
FIFO is 32 × 32–bits.
MC9328MX1 Reference Manual, Rev. 6.1
17-34
Freescale Semiconductor
Chapter 18
Serial Peripheral Interface Modules (SPI 1 and SPI 2)
The MC9328MX1 contains two identical serial peripheral interface modules (SPI 1 and SPI 2). Due to pin
availability, the SPI 2 module operates in master mode only and does not support the SPI Ready (SPI_RDY)
control signal function.
SPI 1 signals are multiplexed with GPIO ports as primary functions. See Chapter 2, “Signal Descriptions and Pin
Assignments,” for detailed pin assignments. SPI 2 signals are connected to the “IN” and “OUT” ports of the GPIO
modules. The user must configure the corresponding GPIO registers to make SPI 1 and SPI 2 signals available at
the pins. See Section 18.2.3, “Pin Configuration for SPI 1 and SPI 2,” for more information about selecting SPI 1
and SPI 2 signals.
Table 18-1. SPI 1 and SPI 2 Signal Multiplexing
SPI Signal Names
Connect to GPIO Signal
SPI1_SPI_RDY
Primary function of GPIO port C [13]
SPI1_SCLK
Primary function of GPIO port C [14]
SPI1_SS
Primary function of GPIO port C [15]
SPI1_MISO
Primary function of GPIO port C [16]
SPI1_MOSI
Primary function of GPIO port C [17]
SPI2_SCLK
AIN of GPIO port A [0] or AIN of port D [7]
SPI2_SS
AIN of GPIO port A [17] or AIN of port D [8]
SPI2_RXD
AOUT of GPIO port A [1] or AOUT of port D [9]
SPI2_TXD
BIN of GPIO port D [31] or AIN of port D [10]
18.1 SPI Block Diagram
This section describes how the SPI modules communicate with external devices.
Each SPI module has one 8 × 16-bit receive buffer (RXFIFO) and one 8 × 16-bit transmit buffer (TXFIFO). The
SPI ready (SPI_RDY) and slave select (SS) control signals enable fast data communication with fewer software
interrupts. The block diagram shown in Figure 18-1 on page 18-2is the same for each SPI module, except that the
SPI 2 module does not support the SPI_RDY control signal function.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
18-1
Operation
IP BUS INTERFACE
SPI_RDY1
CLOCK
GENERATOR
CONTROL
SS
SCLK
MISO
SHIFT REGISTER
MOSI
RX FIFO
TX FIFO
1. SPI 2 module does not support
SPI_RDY control signal function.
Figure 18-1. SPI Module Block Diagram
18.2 Operation
To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as a master,
two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY signal (input).
The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2 Sample Period Control Register
(PERIODREG2) can also be programmed to a fixed data transfer rate for either SPI 1 or SPI 2.
When the SPI 1 module is configured as a slave, the user can configure the SPI 1 Control Register
(CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS becomes an input signal,
and is used to latch data into or load data out to the internal data shift registers, as well as to increment the data
FIFO. Figure 18-2 on page 18-3 shows the generic SPI timing.
18.2.1 Phase and Polarity Configurations
The SPI master uses the SCLK signal to transfer data in and out of the shift register. Data is clocked by one of four
programmable clock phase and polarity combinations, selected through the phase (PHA) and polarity (POL) bits in
the CONTROLREG1 and CONTROLREG2 registers.
In Phase 0 operation (PHA=0) and SCLK Polarity active low (POL=0), output data changes on falling edges of the
SCLK signal and input data is shifted in on rising edges. The most significant bit (MSB) is output when the CPU
loads the transmitted data.
In Phase 0 operation (PHA=0) and SCLK Polarity active high (POL=1), output data changes on rising edges of the
SCLK signal and input data is shifted in on falling edges. The most significant bit (MSB) is output on the first
rising edge of the SCLK signal.
In Phase 1 operation (PHA=1) and SCLK Polarity active low (POL=0), output data changes on rising edges of the
SCLK signal and input data is shifted in on falling edges. The MSB is output on the first rising edge of the SCLK
signal.
In Phase 1 operation (PHA=1) and SCLK Polarity active high (POL=1), output data changes on falling edges of the
SCLK signal and input data is shifted in on rising edges. The MSB is output when the CPU loads the transmitted
data.
MC9328MX1 Reference Manual, Rev. 6.1
18-2
Freescale Semiconductor
Operation
This flexibility allows the SPI modules to operate with most currently available serial peripheral devices.
Figure 18-2 shows the relationship of the polarity and phase settings.
18.2.2 Signals
The following signals are used to control the serial peripheral interface master:
•
Master Out Slave In (MOSI)—In master mode, this bidirectional signal is a TX output signal from the data
shift register. In slave mode, it is an RX input.
•
Master In Slave Out (MISO)—In master mode, this bidirectional signal is a RX input signal to the data shift
register. In slave mode, it is a TX output.
•
SPI Clock (SCLK)—In master mode, this bidirectional signal is an SPI clock output. In slave mode, it is an
input.
•
Slave Select (SS)—In master mode, this bidirectional signal is an output. In slave mode, it is an input.
•
SPI Ready (SPI_RDY)—Used only in master mode to edge- or level-trigger an SPI burst. The SPI 2 module
does not support this signal.
(POL=1, PHA=1) SCLK
(POL=1, PHA=0) SCLK
(POL=0, PHA=1) SCLK
(POL=0, PHA=0) SCLK
MISO
Bn Bn-1 Bn-2 Bn-3 ...
...
B1
B0
MOSI
Bn Bn-1 Bn-2 Bn-3 ...
...
B1
B0
Figure 18-2. SPI Generic Timing
18.2.3 Pin Configuration for SPI 1 and SPI 2
Table 18-1 lists the pins used for the SPI 1 and SPI 2 modules. These pins are multiplexed with other functions on
the device, and must be configured for SPI operation.
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 32.5.1, “Data Direction Registers,” on
page 32-8 for details.
Table 18-2. SPI Pin Configuration
Setting1
Pin
SPI1_SPI_RDY
Primary function of
GPIO port C [13]
Configuration Procedure
1. Clear bit 13 of Port C GPIO In Use Register (GIUS_C)
2. Clear bit 13 of Port C General Purpose Register (GPR_C)
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
18-3
Operation
Table 18-2. SPI Pin Configuration (continued)
Pin
Setting1
Configuration Procedure
SPI1_SCLK
Primary function of
GPIO port C [14]
1. Clear bit 14 of Port C GPIO In Use Register (GIUS_C)
2. Clear bit 14 of Port C General Purpose Register (GPR_C)
SPI1_SS
Primary function of
GPIO port C [15]
1. Clear bit 15 of Port C GPIO In Use Register (GIUS_C)
2. Clear bit 15 of Port C General Purpose Register (GPR_C)
SPI1_MISO
Primary function of
GPIO port C [16]
1. Clear bit 16 of Port C GPIO In Use Register (GIUS_C)
2. Clear bit 16 of Port C General Purpose Register (GPR_C)
SPI1_MOSI
Primary function of
GPIO port C [17]
1. Clear bit 17 of Port C GPIO In Use Register (GIUS_C)
2. Clear bit 17 of Port C General Purpose Register (GPR_C)
SPI2_SCLK2
AIN of GPIO port A [0]
1. Set bit 0 of port A GPIO In Use Register (GIUS_A)
2. Clear bits 1 and 0 of port A Output Configuration Register 1 (OCR1_A)
3. Set bit 0 of port A Data Direction Register (DDIR_A)
AIN of port D [7]
1. Set bit 7 of port D GPIO In Use Register (GIUS_D)
2. Clear bits 15 and 14 of port D Output Configuration Register 1 (OCR1_D)
3. Set bit 7 of port D Data Direction Register (DDIR_D)
AIN of GPIO port A
[17]
1. Set bit 17 of port A GPIO In Use Register (GIUS_A)
2. Clear bits 3 and 2 of port A Output Configuration Register 2 (OCR2_A)
3. Set bit 17 of port A Data Direction Register (DDIR_A)
AIN of port D [8]
1. Set bit 8 of port D GPIO In Use Register (GIUS_D)
2. Clear bits 17 and 16 of port D Output Configuration Register 1 (OCR1_D)
3. Set bit 8 of port D Data Direction Register (DDIR_D)
AOUT of GPIO port A
[1]
1.
2.
3.
4.
Set bit 1 of port A GPIO In Use Register (GIUS_A)
Clear bits 3 and 2 of port A Input Configuration Register A1 (ICONFA1_A)
Clear bit 1 of port A Data Direction Register (DDIR_A)
Clear bit 8 in the FMCR register.
AOUT of GPIO port D
[9]
1.
2.
3.
4.
Set bit 9 of Port D GPIO In Use Register (GIUS_D)
Clear bits 19 and 18 of Port D Input Configuration Register D1 (ICONFA1_D)
Clear bit 9 of Port D Data Direction Register (DDIR_D)
Set bit 8 in the FMCR register
BIN of GPIO port D
[31]
1. Set bit 31 of port D GPIO In Use Register (GIUS_D)
2. Clear bit 31 and set bit 30 of port D Output Configuration Register 2 (OCR2_D)
3. Set bit 31 of port D Data Direction Register (DDIR_D)
AIN of port D [10]
1. Set bit 10 of port D GPIO In Use Register (GIUS_D)
2. Clear bits 21 and 20 of port D Output Configuration Register 1 (OCR1_D)
3. Set bit 10 of port D Data Direction Register (DDIR_D)
SPI2_SS2
SPI2_RXD2
SPI2_TXD2
1.
2.
SPI 1 pins must only be configured if SPI 1 is being used. SPI 2 pins must only be configured if SPI 2 is being used.
Only one of the two pins must be set-up for the SPI 2 signal.
MC9328MX1 Reference Manual, Rev. 6.1
18-4
Freescale Semiconductor
Programming Model
18.3 Programming Model
Each SPI module includes eight 32-bit registers. Table 18-3 summarizes these registers and their addresses.
Table 18-3. SPI Module Register Memory Map
Description
Name
Address
SPI 1 Rx Data Register
RXDATAREG1
0x00213000
SPI 1 Tx Data Register
TXDATAREG1
0x00213004
SPI 1 Control Register
CONTROLREG1
0x00213008
SPI 1 Interrupt Control/Status Register
INTREG1
0x0021300C
SPI 1 Test Register
TESTREG1
0x00213010
SPI 1 Sample Period Control Register
PERIODREG1
0x00213014
SPI 1 DMA Control Register
DMAREG1
0x00213018
SPI 1 Soft Reset Register
RESETREG1
0x0021301C
SPI 2 Rx Data Register
RXDATAREG2
0x00219000
SPI 2 Tx Data Register
TXDATAREG2
0x00219004
SPI 2 Control Register
CONTROLREG2
0x00219008
SPI 2 Interrupt Control/Status Register
INTREG2
0x0021900C
SPI 2 Test Register
TESTREG2
0x00219010
SPI 2 Sample Period Control Register
PERIODREG2
0x00219014
SPI 2 DMA Control Register
DMAREG2
0x00219018
SPI 2 Soft Reset Register
RESETREG2
0x0021901C
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
18-5
Programming Model
18.3.1 Receive (RX) Data Registers
The SPI receive data registers are read-only registers that form the top word of the 8 × 16 RXFIFOs for each SPI
module. These registers hold data received from an external SPI device during a data transaction.
RXDATAREG1
RXDATAREG2
Addr
0x00213000
0x00219000
SPI 1 Rx Data Register
SPI 2 Rx Data Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DATA
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-4. SPI 1 Rx Data Register and SPI 2 Rx Data Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
DATA
Bits 15–0
DATA—Holds the top word of data received into the FIFO. Not valid when the Receive Data Ready (RR) bit
in the corresponding Interrupt Control/Status Register (INTREG1 or INTREG2) is cleared.
MC9328MX1 Reference Manual, Rev. 6.1
18-6
Freescale Semiconductor
Programming Model
18.3.2 Transmit (TX) Data Registers
The SPI transmit data registers are write-only data registers that form the top word of the 8 × 16 TXFIFOs for each
SPI module. The TXFIFO can be written to as long as it is not full, even when the exchange (XCH) bit in the
corresponding SPI control register (CONTROLREG1 or CONTROLREG2) is set. This allows user write access to
the TXFIFO during an SPI data exchange process. Writes to these registers are ignored when the SPI module is
disabled (SPIEN bit of the corresponding SPI control register is cleared).
TXDATAREG1
TXDATAREG2
Addr
0x00213004
0x00219004
SPI 1 Tx Data Register
SPI 2 Tx Data Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DATA
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-5. SPI 1 Tx Data Register and SPI 2 Tx Data Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
DATA
Bits 15–0
DATA—Holds the top word of data loaded into the FIFO. Data written to this register can be 8 or 16 bits. The
number of bits actually transmitted is determined by the BIT_COUNT field of the corresponding SPI control
register. If this field contains more bits than the number specified by BIT_COUNT, the extra bits are ignored.
For example, to transfer 10 bits of data, a 16-bit word must be written to this register. Bits 9-0 are shifted out
and bits 15-10 are ignored. When the SPI module is operating in slave mode, ‘0’s are shifted out when the
FIFO is not full.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
18-7
Programming Model
18.3.3 Control Registers
The SPI control registers allow the user to enable the SPI modules, select the operating modes, specify the divider
value, phase, and polarity of the clock, configure the SS and SPI_RDY control signals (for SPI 1), and define the
transfer length.
CONTROLREG1
CONTROLREG2
Addr
0x00213008
0x00219008
SPI 1 Control Register
SPI 2 Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
PHA
POL
RESET
0x0000
BIT
15
14
13
DATARATE
TYPE
12
11
DRCTL
10
9
MODE SPIEN
8
XCH
7
SSPOL SSCTL
BIT_COUNT
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0/11
0
0
0
0
0
0
0
0
0
0
RESET
0x0000 / 0x04001
1.
In CONTROLREG2, the MODE bit is set to 1.
Table 18-6. SPI 1 Control Register and SPI 2 Control Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
DATARATE
Bits 15–13
Data Rate—Selects the divide value of SCLK from the
PERCLK2 in the PLL and Clock Control Module.
000 = Divide by 4
001 = Divide by 8
010 = Divide by 16
011 = Divide by 32
100 = Divide by 64
101 = Divide by 128
110 = Divide by 256
111 = Divide by 512
DRCTL
Bits 12–11
SPI_RDY Control—Selects the waveform of the SPI_RDY input
signal when the SPI 1 module operates in master mode. In slave
mode, DRCTL is ignored.
Because the SPI 2 module does not support the SPI_RDY
control signal function, DRCTL must be written with 00 in
CONTROLREG2.
00 = Ignore SPI_RDY
01 = Falling edge triggers input
10 = Active low level triggers input
11 = Reserved
MODE
Bit 10
SPI Mode Select—Selects the mode for the SPI 1 module. In
CONTROLREG2, MODE is set by the hardware.
0 = Slave mode
1 = Master mode
MC9328MX1 Reference Manual, Rev. 6.1
18-8
Freescale Semiconductor
Programming Model
Table 18-6. SPI 1 Control Register and SPI 2 Control Register Description (continued)
Name
Description
Settings
SPIEN
Bit 9
SPI Module Enable—Enables/Disables the serial peripheral
interface. SPIEN must be asserted before an exchange is
initiated. Writing 0 to SPIEN flushes the receive and transmit
FIFOs.
0 = Disable the SPI
1 = Enable the SPI
XCH
Bit 8
Exchange—Initiates a data exchange in master mode. XCH
remains set while the exchange is in progress, or while the SPI
module is waiting for an active SPI_RDY control signal input.
XCH is automatically cleared when all data in the TXFIFO and
shift register are shifted out.
In slave mode, XCH must be cleared.
0 = Idle
1 = Initiates exchange (write) or busy
(read)
SSPOL
Bit 7
SS Polarity Select—Selects the polarity of the SS signal (in
both master and slave mode).
0 = Active low
1 = Active high
SSCTL
Bit 6
SS Wave Form Select—Selects the output wave form for the
SS signal when in master mode.
In master mode:
0 = SS stays low between SPI bursts
1 = Insert pulse between SPI bursts
Controls RXFIFO advancement when in slave mode for SPI 1
only.
In slave mode:
0 = RXFIFO advanced by BIT_COUNT
1 = RXFIFO advanced by SS rising edge
PHA
Bit 5
Phase—Controls the clock/data phase relationship (see
Figure 18-2 on page 18-3).
0 = Phase 0 operation
1 = Phase 1 operation
POL
Bit 4
Polarity—Controls the polarity of the SCLK signal (see
Figure 18-2 on page 18-3).
0 = Active high polarity (0 = idle)
1 = Active low polarity (1 = idle)
BIT_COUNT
Bits 3–0
Bit Count—This field selects the length of the transfer. A
maximum of 16bits can be transferred.
0000 = 1–bit transfer
0001 = 2–bit transfer
...
1111 = 16–bit transfer
In master mode, a 16-bit data word is loaded from TxFIFO to
shift register and only the least n bits (n=BIT COUNT) are shifted
out. The next 16-bit word is then loaded to shift register.
In slave mode and when SSCTL bit is 0 this field controls the
number of bits received as a data word loaded to RxFIFO. When
SSCTL bit is 1 and SS rising edge is faster than BIT COUNT is
treated, then this field is don’t care.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
18-9
Programming Model
18.3.4 Interrupt Control/Status Registers
The SPI interrupt control status registers allow the user to enable various interrupt signals and monitor the status of
those interrupts.
INTREG1
INTREG2
Addr
0x0021300C
0x0021900C
SPI 1 Interrupt Control/Status Register
SPI 2 Interrupt Control/Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
BO
RO
RF
RH
RR
TF
TH
TE
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
BOEN ROEN RFEN RHEN RREN TFEN THEN TEEN
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-7. SPI 1 Interrupt Control/Status Register and
SPI 2 Interrupt Control/Status Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
BOEN
Bit 15
Bit Count Overflow Interrupt Enable—Enables/Disables the Bit
Count Overflow Interrupt.
0 = Disable interrupt
1 = Enable interrupt
ROEN
BIT 14
RXFIFO Overflow Interrupt Enable—Enables/Disables the RXFIFO
Overflow Interrupt.
0 = Disable interrupt
1 = Enable interrupt
RFEN
Bit 13
RXFIFO Full Interrupt Enable—Enables/Disables the RXFIFO Full
Interrupt.
0 = Disable interrupt
1 = Enable interrupt
RHEN
Bit 12
RXFIFO Half Interrupt Enable—Enables/Disables the RXFIFO
Half-Full Interrupt.
0 = Disable interrupt
1 = Enable interrupt
RREN
Bit 11
RXFIFO Data Ready Interrupt Enable—Enables/Disables the
RXFIFO Data Ready Interrupt.
0 = Disable interrupt
1 = Enable interrupt
TFEN
Bit 10
TXFIFO Full Interrupt Enable—Enables/Disables the TXFIFO Full
Interrupt.
0 = Disable interrupt
1 = Enable interrupt
THEN
Bit 9
TXFIFO Half Interrupt Enable—Enables/Disables the TXFIFO
Half-Empty Interrupt.
0 = Disable interrupt
1 = Enable interrupt
MC9328MX1 Reference Manual, Rev. 6.1
18-10
Freescale Semiconductor
Programming Model
Table 18-7. SPI 1 Interrupt Control/Status Register and
SPI 2 Interrupt Control/Status Register Description (continued)
Name
Description
Settings
TEEN
Bit 8
TXFIFO Empty Interrupt Enable—Enables/Disables the TXFIFO
Empty Interrupt.
0 = Disable interrupt
1 = Enable interrupt
BO
Bit 7
Bit Count Overflow—Indicates that a bit count overflow has occurred.
BO is applicable for the SPI 1 module only when the bits of
CONTROLREG1 are set so that
MODE = 0 and SSCTL = 1. The overflow occurs when the slave
receives more than 16 bits in one burst. BO is cleared after a data read
from the RXDATAREG1 register. There is no way to determine which
data word overflowed, so the bad data word can still be in the FIFO if it
is not empty.
0 = No bit count overflow error
1 = At least one data word in RXFIFO
has a bit count overflow error
RO
Bit 6
RXFIFO Overflow—Indicates that the RXFIFO has overflowed. At
least one newly written data word has been lost. The RO flag is
automatically cleared after a data read.
0 = No RXFIFO overflow error
1 = At least one data word in the
RXFIFO has been overwritten
RF
Bit 5
RXFIFO Full Status—Indicates that the RXFIFO is full.
0 = Less than 8 data words are in the
RXFIFO
1 = 8 data words are in the RXFIFO
RH
Bit 4
RXFIFO Half Status—Indicates that the RXFIFO is at least half-full.
0 = Less than 4 data words are in the
RXFIFO
1 = At least 4 data words are in the
RXFIFO
RR
Bit 3
RXFIFO Data Ready Status—Indicates that the RXFIFO is empty.
0 = The RXFIFO is empty
1 = At least one data word is in the
RXFIFO
TF
Bit 2
TXFIFO Full Status—Indicates that the TXFIFO is full.
0 = Less than 8 data words are in the
TXFIFO
1 = 8 data words are in the TXFIFO
TH
Bit 1
TXFIFO Half Status—Indicates that the TXFIFO is at least half-empty.
0 = Less than 4 empty slots are in the
TXFIFO
1 = At least 4 empty slots are in the
TXFIFO
TE
Bit 0
TXFIFO Empty Status—Indicates that the TXFIFO is empty.
0 = At least one data word is in the
TXFIFO
1 = The TXFIFO is empty, however
data shifting may still be
on-going. To be sure no data
transaction is on-going, check
the XCH bit(s) in the Control
Register(s).
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
18-11
Programming Model
18.3.5 Test Registers
The SPI test registers allow the user to internally connect the receive and transmit sections, display the status of the
state machine, and monitor the contents of the receive and transmit FIFOs.
TESTREG1
TESTREG2
Addr
0x00213010
0x00219010
SPI 1 Test Register
SPI 2 Test Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
LBC
TYPE
10
9
8
SSTATUS
RXCNT
TXCNT
r
rw
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-8. SPI 1 Test Register and SPI 2 Test Register Description
Name
Description
Settings
Reserved
Bits 31–15
Reserved—These bits are reserved and should read 0.
LBC
Bit 14
Loop Back Control—Internally connects the receive and transmit
sections internally for test purposes.
Reserved
Bits 13–12
Reserved—These bits are reserved and should read 0.
SSTATUS
Bits 11–8
State Machine Status—Indicates the state machine status (used for test purposes only).
RXCNT
Bits 7–4
RXFIFO Counter—Indicates the number of data words in the RXFIFO.
0 = RX and TX sections are not
internally connected
1 = RX and TX sections are
internally connected
0000 = RXFIFO is empty
0001 = 1 data word in RXFIFO
0010 = 2 data words in RXFIFO
0011 = 3 data words in RXFIFO
0100 = 4 data words in RXFIFO
0101 = 5 data words in RXFIFO
0110 = 6 data words in RXFIFO
0111 = 7 data words in RXFIFO
1000 = 8 data words in RXFIFO
MC9328MX1 Reference Manual, Rev. 6.1
18-12
Freescale Semiconductor
Programming Model
Table 18-8. SPI 1 Test Register and SPI 2 Test Register Description (continued)
Name
Description
TXCNT
Bits 3–0
Settings
TXFIFO Counter—Indicates the number of data words in the TXFIFO.
0000 = TXFIFO is empty
0001 = 1 data word in TXFIFO
0010 = 2 data words in TXFIFO
0011 = 3 data words in TXFIFO
0100 = 4 data words in TXFIFO
0101 = 5 data words in TXFIFO
0110 = 6 data words in TXFIFO
0111 = 7 data words in TXFIFO
1000 = 8 data words in TXFIFO
18.3.6 Sample Period Control Registers
The SPI sample period control registers allow the user to select the clock source for the counter and to set the wait
between data transactions. The wait is only applicable when the SPI module is operating in master mode.
PERIODREG1
PERIODREG2
Addr
0x00213014
0x00219014
SPI 1 Sample Period Control Register
SPI 2 Sample Period Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
CSRC
TYPE
WAIT
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 18-9. SPI 1 Sample Period Control Register and
SPI 2 Sample Period Control Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
CSRC
Bit 15
Clock Source—Selects the clock source for the counter.
Settings
0 = Bit clock
1 = 32.768 kHz or 32 kHz clock
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
18-13
Programming Model
Table 18-9. SPI 1 Sample Period Control Register and
SPI 2 Sample Period Control Register Description (continued)
Name
Description
WAIT
Bits 14–0
Settings
Wait—Determines the number of clocks inserted between data
transactions (when operating in master mode).
0x0000 = 0 clock
0x0001 = 1 clock
0x0002 = 2 clocks
…
0x7FFF = 32,767 clocks
18.3.7 DMA Control Registers
The SPI DMA control registers allow the user to enable DMA requests when the FIFOs are full, empty, or half-full.
These registers also contain status bits for FIFO full, empty, and half-empty conditions.
DMAREG1
DMAREG2
Addr
0x00213018
0x00219018
SPI 1 DMA Control Register
SPI 2 DMA Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
THDMA
TEDMA
RFDMA
RHDMA
RESET
0x0000
BIT
15
14
13
12
THDEN
TEDEN
RFDEN
RHDEN
rw
rw
rw
rw
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TYPE
11
10
9
8
RESET
0x0000
Table 18-10. SPI 1 DMA Control Register and SPI 2 DMA Control Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
THDEN
Bit 15
THDEN—Enables/Disables the TXFIFO Half
DMA Request.
0 = Disabled
1 = Enabled
TEDEN
Bit 14
TEDEN—Enables/Disables the TXFIFO
Empty DMA Request.
0 = Disabled
1 = Enabled
RFDEN
Bit 13
RFDEN—Enables/Disables the RXFIFO Full
DMA Request.
0 = Disabled
1 = Enabled
MC9328MX1 Reference Manual, Rev. 6.1
18-14
Freescale Semiconductor
Programming Model
Table 18-10. SPI 1 DMA Control Register and SPI 2 DMA Control Register Description (continued)
Name
Description
Settings
RHDEN
Bit 12
RHDEN—Enables/Disables the RXFIFO Half
DMA Request.
0 = Disabled
1 = Enabled
Reserved
Bits 11–8
Reserved—These bits are reserved and should read 0.
THDMA
Bit 7
TXFIFO Half Status—Indicates when the
transmit FIFO is half-empty.
0 = There are less than 4 empty slots in the TXFIFO
1 = There are at least 4 empty slots in the TXFIFO
TEDMA
Bit 6
TXFIFO Empty Status—Indicates when the
transmit FIFO is empty.
0 = There is at least one data word in the TXFIFO
1 = The TXFIFO is empty, however data shifting may still be
on-going. To be sure no data transaction is on-going,
read the XCH bit in the Control Registers.
RFDMA
Bit 5
RXFIFO Full Status—Indicates when the
receive FIFO is full.
0 = There are less than 8 data words in the RXFIFO
1 = There are 8 data words in the RXFIFO
RHDMA
Bit 4
RXFIFO Half Status—Indicates when the
receive FIFO is half-full.
0 = There are less than 4 data words in the RXFIFO
1 = There are at least 4 data words in the RXFIFO
Reserved
Bits 3–0
Reserved—These bits are reserved and should read 0.
18.3.8 Soft Reset Registers
The SPI soft reset registers allow the user to reset the SPI module.
RESETREG1
RESETREG2
Addr
0x0021301C
0x0021901C
SPI 1 Soft Reset Register
SPI 2 Soft Reset Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
START
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
18-15
Programming Model
Table 18-11. SPI 1 Soft Reset Register and SPI 2 Soft Reset Register Description
Name
Description
Reserved
Bits 31–1
Reserved—These bits are reserved and should read 0.
START
Bit 0
Start—Executes soft reset.
Settings
0 = No soft reset
1 = Soft reset
MC9328MX1 Reference Manual, Rev. 6.1
18-16
Freescale Semiconductor
Chapter 19
LCD Controller
19.1 Introduction
The Liquid Crystal Display Controller (LCDC) provides display data for external gray-scale or color LCD panels.
The LCDC is capable of supporting black-and-white, gray-scale, passive-matrix color, and active-matrix color
LCD panels.
19.2 Features
•
Support for single (non-split) screen monochrome/color LCD panels and self-refresh type LCD panels
•
16 simultaneous gray-scale levels from a palette of 16 for monochrome display
•
Support for:
— 4/8/12 bits per pixel (bpp) for passive color panel
— 4/8/12/16 bpp for TFT panel
— Up to 256 colors out of a palette of 4096 colors for an 8 bpp display and 4096 colors for a 12 bpp display
— True 64K colors for 16 bpp
— Additional support details are shown in Table 19-1
Table 19-1. Supported Panel Characteristics
Panel Type
Monochrome
Bit/Pixel
Panel Interface (Bits)
Number of Gray Level/Color
1
1, 2, 4, 8
Black-and-white
2
1, 2, 4, 8
4
4
1, 2, 4, 8
16
CSTN
4,8,12
8
16, 256, 4096
TFT
4, 8
16
16, 256
12, 16
12, 16
4096, 64K
•
Standard panel interface for common LCD drivers
•
Panel interface of 16-, 12-, 8-, 4-, 2-, and 1-bit-wide LCD panel data bus for monochrome or color panels
•
For 4 bpp and 8 bpp a palette table is used for re-mapping of data from memory, independent of type of
panel used. For the 1 bpp, 2 bpp, 12 bpp and 16 bpp the palette table is by-passed.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-1
LCDC Operation
•
Direct interface to active color panels (TFT) such as NEC and Sharp
•
Dedicated signals facilitate interface to Sharp HR-TFT panels such as 320 × 240
•
Capability to share system memory or eSRAM for display memory
•
Hardware-generated cursor with blink, color, and size programmability
•
Logical operation between color hardware cursor and background
•
Hardware panning (soft horizontal scrolling)
•
8-bit pulse-width modulator for software contrast control
AHB
Interrupt
FIFO
(Line Buffer)
DMA
Pan
Shift
4/8 Bit Color
1 bpp
2 bpp
4 bpp
16-Bit Active Color
Palette Color Look
Up Table
16-Bit Hardware
Cursor
Passive
4 bpp (Gray)
Interface
FRC Color
TFT
H/W Cursor
Non-Color
FRC Gray
Interface Buffer
Interface Logic
LCDC_CLK
(PerCLK2)
LD [15:0]
FLM/VSYNC
LP/HSYNC
LSCLK
ACD/OE
PS
CLS
REV
SPL_SPR
CONTRAST
Figure 19-1. LCDC Block Diagram
19.3 LCDC Operation
19.3.1 LCD Screen Format
The number of pixels forming the screen width and screen height of the LCD panel are software programmable.
Figure 19-2 shows the relationship between the screen size and memory window.
MC9328MX1 Reference Manual, Rev. 6.1
19-2
Freescale Semiconductor
LCDC Operation
Virtual Page Width (VPW)
Screen Starting Address (SSA)
Screen Height (YMAX)
Virtual Page Height (VPH)
Screen Width (XMAX)
Figure 19-2. LCD Screen Format
The Screen Width (XMAX) and Screen Height (YMAX) parameters specify the LCD panel size. The LCDC will
start scanning the display memory at the location pointed to by the Screen Starting Address (SSA) register,
represented by the shaded area in Figure 19-2, for display on the LCD panel.
The maximum page width is specified by the Virtual Page Width (VPW) parameter. Virtual Page Height (VPH)
does not affect the LCDC and is limited only by memory size. By changing the SSA register, a screen-sized
window can be vertically or horizontally scrolled (panned) anywhere inside the virtual page boundaries. The
software must control the starting address in the SSA properly so that the scanning logic’s System Memory Pointer
(SMP) stays within the VPW and VPH limits to prevent the display of strange artifacts on the screen.
VPH is used by the programmer only for boundary checks. There is no VPH parameter internal to the LCDC.
VPW is used in calculating the RAM starting address representing the beginning of each displayed line. SSA sets
the address of data for the first line of a frame. For each subsequent line, VPW is added to an accumulation
initialized by the SSA to yield the starting address of that line.
19.3.2 Panning
Panning Offset (POS) is expressed in bits, not pixels, so when operating in any mode other than 1 bpp, only even
pixel boundaries are valid. In 12 bpp mode, the pixels are aligned to 16-bit boundaries, and POS also must align to
these boundaries.
SSA and POS are located in isolated registers and are double buffered because they are dynamic parameters likely
to change while the LCDC is running. New values of SSA and POS do not take effect until the beginning of the
next frame. A typical panning algorithm includes an interrupt at the beginning of the frame. In the interrupt service
routine, POS and/or SSA are updated (the old values are internally latched). The updates take effect on the next
frame.
19.3.3 Display Data Mapping
The LCDC supports 1/2/4 bpp in monochrome mode and 4/8/12/16 bpp in color mode. System memory data
mapping in 2/4/8/12/16 bpp modes is shown in Figure 19-4 and in Figure 19-5.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-3
LCDC Operation
NOTE:
In 12 bpp mode, 16 bits of memory are used for each set of 12 bits, leaving 4 bits
unused. In 16 bpp mode, all 16 bits are used. Refer to Figure 19-5 and Table 19-7.
P0
P1
P2
P3
LCD Screen
Figure 19-3. Pixel Location on Display Screen
MC9328MX1 Reference Manual, Rev. 6.1
19-4
Freescale Semiconductor
LCDC Operation
1 bpp Mode, Little Endian
1 bpp Mode, Big Endian
Byte
Address
Sample Bit-to-Pixel Mapping
3
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
P24
P25
P26
P27
P28
P29
P30
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
P22
P23
1
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
P8
P9
P10
P11
P12
P13
P14
P15
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P0
P1
P2
P3
P4
P5
P6
P7
P17
P18
P19
P20
P21
Sample Bit-to-Pixel Mapping
0
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
1
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
P14
P15
2
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
P16
P17
P18
P19
P20
P21
P22
P23
3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P24
P25
P26
P27
P28
P29
P30
P31
P31
2
P16
Byte
Address
P0
P1
P8
P9
2 bpp Mode, Little Endian
Sample Bit-to-Pixel Mapping
3
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
P13
P14
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
1
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
P9
P4
0
Bit 7
P10
P5
Bit 6
Bit 5
P0
Bit 4
Bit 3
P11
P5
P12
P6
P13
P7
Sample Bit-to-Pixel Mapping
0
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
1
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
2
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
P0
P11
P6
P1
P10
P4
Byte
Address
P15
2
P8
P3
2 bpp Mode, Big Endian
Byte
Address
P12
P2
Bit 8
P4
P7
Bit 2
Bit 1
P2
Bit 0
P1
P5
P8
3
P3
Bit 7
Bit 6
Bit 5
P3
P6
P9
P12
4 bpp Mode, Little Endian
P2
P7
P10
Bit 4
Bit 3
P13
Bit 8
P11
Bit 2
Bit 1
P14
Bit 0
P15
4 bpp Mode, Big Endian
Byte
Address
Sample Bit-to-Pixel Mapping
Byte
Address
Sample Bit-to-Pixel Mapping
3
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
0
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
1
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
2
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
P6
P7
P0
2
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
1
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
P4
P5
P2
0
Bit 7
Bit 6
Bit 5
P2
Bit 8
P3
Bit 4
Bit 3
Bit 2
P0
Bit 1
P1
P3
P4
Bit 0
3
Bit 7
P1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
P6
8 bpp Mode, Little Endian
Bit 8
P5
Bit 1
Bit 0
P7
8 bpp Mode, Big Endian
Byte
Address
Sample Bit-to-Pixel Mapping
Byte
Address
Sample Bit-to-Pixel Mapping
3
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
0
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
1
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
2
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
P3
P0
2
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
1
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
P2
P1
Bit 8
P1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 8
P2
Bit 2
Bit 1
Bit 0
3
Bit 7
Bit 6
Bit 5
P0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P3
P0 = Red0Green0Blue0
P1 = Red1Green1Blue1
Figure 19-4. Display Data Mapping, 1/2/4/8 bpp Modes
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-5
LCDC Operation
Table 19-2. Display Mapping in 12 bpp, CSTN Panel, Little Endian
16 bpp Mode, Little Endian
Byte
Address
3
2
Sample Bit-to-Pixel Mapping
Bit 31
Bit 30
Red1 [4]
Red1 [3]
Bit 29
Bit 23
Bit 22
Bit 28
Bit 27
Bit 26
Bit 21
Bit 20
Bit 19
Bit 18
Green1 [2] Green1 [1] Green1 [0] Blue1 [4] Blue1 [3] Blue1 [2]
1
0
Bit 15
Bit 14
Red0 [4]
Red0 [3]
Bit 7
Bit 6
Bit 25
Bit 24
Red1 [2] Red1 [1] Red1 [0] Green1 [5] Green1 [4] Green1 [3]
Bit 13
Bit 12
Bit 11
Bit 17
Bit 16
Blue1 [1]
Blue1 [0]
Bit 9
Bit 8
Bit 10
Red0 [2] Red0 [1] Red0 [0] Green0 [5] Green0 [4] Green0 [3]
Bit 5
Bit 4
Bit 3
Bit 2
Green0 [2] Green0 [1] Green0 [0] Blue0 [4] Blue0 [3] Blue0 [2]
Bit 1
Bit 0
Blue0 [1]
Blue0 [0]
Bit 25
Bit 24
16 bpp Mode, Big Endian
Byte
Address
0
1
Sample Bit-to-Pixel Mapping
Bit 31
Bit 30
Red0 [4]
Red0 [3]
Bit 29
Bit 23
Bit 22
Bit 28
Bit 27
Bit 26
Red0 [2] Red0 [1] Red0 [0] Green0 [5] Green0 [4] Green0 [3]
Bit 21
Bit 20
Bit 19
Bit 18
Green0 [2] Green0 [1] Green0 [0] Blue0 [4] Blue0 [3] Blue0 [2]
2
3
Bit 15
Bit 14
Red1 [4]
Red1 [3]
Bit 13
Bit 7
Bit 6
Bit 12
Bit 11
Bit 17
Bit 16
Blue0 [1]
Blue0 [0]
Bit 9
Bit 8
Bit 10
Red1 [2] Red1 [1] Red1 [0] Green1 [5] Green1 [4] Green1 [3]
Bit 5
Bit 4
Bit 3
Bit 2
Green1 [2] Green1 [1] Green1 [0] Blue1 [4] Blue1 [3] Blue1 [2]
Bit 1
Bit 0
Blue1 [1]
Blue1 [0]
Table 19-3. Display Mapping in 12 bpp, CSTN Panel, Little Endian
Byte Address
3
2
1
0
Bit-to-Pixel Mapping
B31
B30
B29
B28
B27
B26
B25
B24
–
–
–
–
R13
R12
R11
RI0
B23
B22
B21
B20
B19
B18
B17
B16
G13
G12
G11
GI0
B13
B12
B11
BI0
B15
B14
B13
B12
B11
B10
B9
B8
–
–
–
–
R03
R02
R01
RO0
B7
B6
B5
B4
B3
B2
B1
BO
GO3
G02
G01
GO0
BO3
B02
B01
BO0
PO = RGBo P1= RGB1
MC9328MX1 Reference Manual, Rev. 6.1
19-6
Freescale Semiconductor
LCDC Operation
:
Table 19-4. Display Mapping in 12 bpp, CSTN Panel, Big Endian
Byte Address
0
1
2
3
Bit-to-Pixel Mapping
B31
B30
B29
B28
B27
B26
B25
B24
–
–
–
–
R03
R02
R01
RO0
B23
B22
B21
B20
B19
B18
B17
B16
GO3
G02
G01
GO0
BO3
B02
B01
BO0
B15
B14
B13
B12
B11
B10
B9
B8
–
–
–
–
R13
R12
R11
RI0
B7
B6
B5
B4
B3
B2
B1
BO
G13
G12
G11
GI0
B13
B12
B11
BI0
PO = RGBo P1= RGB1
Figure 19-5. Display Data Mapping, 16 bpp Mode
19.3.4 Black-and-White Operation
The 1 bpp mode is also known as black-and-white mode because each pixel is always either fully on or fully off.
19.3.5 Gray-Scale Operation
The LCDC generates a maximum of 16 gray levels. These gray levels are defined by 2 or 4 bits of display data for
each pixel. Using 2 bpp, the LCDC displays 4 shades of gray, and using 4 bpp, the LCDC displays all 16 shades.
The shades of gray are obtained by controlling the number of frames in which the pixel is “on” over a period of 16
frames. This method is known as Frame Rate Control (FRC). For more information on FRC, see Section 19.3.7,
“Frame Rate Modulation Control (FRC).”
The use of the mapping RAM is shown in Figure 19-6. When using 2 bpp, the 2-bit code is mapped to one of 4 gray
levels, and when using 4 bpp, the 4-bit code is mapped to one of 16 gray levels. Because crystal formulations and
driving voltages vary, the visual gray effect may or may not be linearly related to the frame rate. A logarithmic
scale such as 0, 1/4, 1/2 and 1 might be more pleasing than a linearly spaced scale such as 0, 5/16, 11/16 and 1 for
certain graphics.
Figure 19-6 illustrates gray-scale pixel generation. The flexible mapping scheme allows the user to optimize the
visual effect for a specific panel or application.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-7
LCDC Operation
7 6 5 4 3 2 1 0
1 0
2 bpp Data
1 1 0 0
4 bpp Data
- - - - - - - - 1 1 1 0
FRC
1
To Panel
Figure 19-6. Gray-Scale Pixel Generation
19.3.6 Color Generation
The value corresponding to each color pixel on the screen is represented by a 4-, 8-, 12- or 16-bit code in the
display memory.
For the 4- and 8- bit modes use the LCDC’s color mapping RAM to map the data to a 12-bit RGB code. For passive
matrix color displays, 4-bit and 8-bit mode, the 12-bit RGB code from the mapping RAM is output to the FRC
blocks that independently process the code corresponding to the red, green, and blue components of each pixel to
generate the required shade and intensity.
For active matrix display, the 12-bit output from the mapping RAM is output to the panel.
For 12-bit mode for passive matrix color display, the mapping RAM is by-passed and output directly to the FRC
block.
In 16-bit mode, pixel data is simply moved from display memory to the 16-bit LCDC output bus.
For active matrix displays, the 16-bit RGB code from the mapping RAM is output to the panel. For passive color
display, the maximum color depth is 12-bit and 16-bit color is not supported.
Figure 19-7 and Figure 19-8 on page 19-10 illustrate passive matrix and active matrix color pixel generation.
MC9328MX1 Reference Manual, Rev. 6.1
19-8
Freescale Semiconductor
LCDC Operation
7 6 5 4 3 2 1 0
1 0 1 1
4 bpp Data
1 1 0 0 1 1 0 1
8 bpp Data
0 1 0 1 1 1 0 0 1 1 0 1 1 1 0 1
R
G
12 bpp Data
B
Color
RAM
Inside
LCDC
256 rows
- - - - - - - - 1 1 1 0
FRC
FRC
FRC
1 0 1
To Panel
Figure 19-7. Passive Matrix Color Pixel Generation
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-9
LCDC Operation
.
7 6 5 4 3 2 1 0
1 0 1 1
4 bpp Data
1 1 0 0 1 1 0 1
8 bpp Data
0 1 0 1 1 1 0 0 1 1 0 1 1 1 0 1
R
G
12 bpp/16 bpp Data
B
Color
RAM
Inside
LCDC
256 rows
1 1 1 1 0 0 1 1 1 1 0 0
1 1 1 1 0 0 1 1 1 1 0 0
To Panel
Figure 19-8. Active Matrix Color Pixel Generation
19.3.7 Frame Rate Modulation Control (FRC)
Circuitry inside the LCDC generates intermediate gray-scale colors on the panel by adjusting the density of zeroes
and ones that appear over the frames. The LCDC can generate 16 simultaneous gray-scale levels.
Table 19-5. Gray Palette Density
Gray Code
(Hexadecimal)
Density
Density
(Decimal)
0
0
0
1
1/8
0.125
2
1/5
0.2
3
1/4
0.25
4
1/3
0.333
5
2/5
0.4
6
4/9
0.444
7
1/2
0.5
8
5/9
0.555
9
3/5
0.6
A
2/3
0.666
MC9328MX1 Reference Manual, Rev. 6.1
19-10
Freescale Semiconductor
LCDC Operation
Table 19-5. Gray Palette Density (continued)
Gray Code
(Hexadecimal)
Density
Density
(Decimal)
B
3/4
0.75
C
4/5
0.8
D
7/8
0.875
E
14/15
0.933
F
1
1
Note:
Overbars indicate repeating decimal numbers.
19.3.8 Panel Interface Signals and Timing
The LCDC continuously provides pixel data to the LCD panel via the LCD panel interface. Panel interface signals
are illustrated in Figure 19-9 on page 19-11.
LD [15:0]
FLM/VSYNC
LP/HSYNC
LSCLK
ACD/OE
PS
CLS
REV
SPL_SPR
CONTRAST
LCD Controller
Figure 19-9. LCDC Interface Signals
The format, timing, and polarity of the panel interface signals are programmable. There are two basic modes,
passive and active, selected by the TFT register bit. The user must also select either grayscale mode or color mode.
SPL_SPR, PS, CLS, and REV are additional interface signals required for Sharp HR-TFT panels.
19.3.8.1 Pin Configuration for LCDC
Figure 19-9 shows the signals used for the LCDC. These pins are multiplexed with other functions on the device,
and must be configured for LCDC operation before they can be used.
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 32.5.1, “Data Direction Registers,” on
page 32-8 for details.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-11
LCDC Operation
Table 19-6. Pin Configuration
Pin
Setting
LD [15:0]
FLM/VSYNC
LP/HSYNC
LSCLK
ACD/OE
CONTRAST
SPL_SPR
PS
CLS
REV
Configuration Procedure
Primary function of
GPIO Port D [30:15]
1. Clear bits [30:15] of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [14]
1. Clear bit 14 of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [13]
1. Clear bit 13 of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [6]
1. Clear bit 6 of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [12]
1. Clear bit 12 of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [11]
1. Clear bit 11 of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [10]
1. Clear bit 10 of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [9]
1. Clear bit 9 of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [8]
1. Clear bit 8 of Port D GPIO In Use Register (GIUS_D)
Primary function of
GPIO Port D [7]
1. Clear bit 7 of Port D GPIO In Use Register (GIUS_D)
2. Clear bits [30:15] of Port D General Purpose Register (GPR_D)
2. Clear bit 14 of Port D General Purpose Register (GPR_D)
2. Clear bit 13 of Port D General Purpose Register (GPR_D)
2. Clear bit 6 of Port D General Purpose Register (GPR_D)
2. Clear bit 12 of Port D General Purpose Register (GPR_D)
2. Clear bit 11 of Port D General Purpose Register (GPR_D)
2. Clear bit 10 of Port D General Purpose Register (GPR_D)
2. Clear bit 9 of Port D General Purpose Register (GPR_D)
2. Clear bit 8 of Port D General Purpose Register (GPR_D)
2. Clear bit 7 of Port D General Purpose Register (GPR_D)
19.3.8.2 Passive Matrix Panel Interface Signals
Figure 19-10 shows the LCD interface timing for monochrome panels and Figure 19-11 shows the LCD interface
timing for passive matrix color panels. Signal polarities are shown positive, however it can be reversed by clearing
the bits in the Panel Configuration Register (PCR). The data bus timing for passive panels is controlled by the shift
clock (LSCLK), line pulse (LP), first line marker (FLM), alternate crystal direction (ACD), and line data (LD)
signals. Operation of the panel interface is accomplished in the following steps:
1. LSCLK clocks the pixel data into the display driver’s internal shift register.
2. LP signifies the end of the current line of serial data and latches the shifted pixel data into a wide
latch.
3. FLM marks the first line of the displayed page. The LD (and the associated LP), enclosed by the
FLM signal, marks the first line of the current frame.
4. ACD toggles after a pre-programmed number of FLM pulses. This signal refreshes the LCD panel.
NOTE:
The LD bus width is programmable to 1, 2, 4, or 8 bits in monochrome mode (the
COLOR bit in the Panel Configuration register is set to 0). Data is justified to the
least significant bits of the LD [15:0] bus. Passive color displays use a fixed 2-2/3
pixels of data per 8-bit vector as shown in Figure 19-11 on page 19-13.
MC9328MX1 Reference Manual, Rev. 6.1
19-12
Freescale Semiconductor
LCDC Operation
FLM
LP
LINE 1
LINE 2
LINE 3
LINE 4
LINE n
LINE 1
LP
1
2
3
59
60
m/4-1
m/4
LSCLK
LD0
[0,0]
[0,4]
[0,8]
[0,232]
[0,236]
[0,m-8]
[0,m-4]
LD1
[0,1]
[0,5]
[0,9]
[0,233]
[0,237]
[0,m-7]
[0,m-3]
LD2
[0,2]
[0,6]
[0,10]
[0,234]
[0,238]
[0,m-6]
[0,m-2]
LD3
[0,3]
[0,7]
[0,11]
[0,235]
[0,239]
[0,m-5]
[0,m-1]
Figure 19-10. LCDC Interface Timing for 4-bit Data Width Gray-Scale Panels
FLM
LP
LINE 1
LINE 2
LINE 3
LINE 4
LINE n
LINE 1
LP
1
2
3
89
90
3*m/8-1 3*m/8
LD7
R[0,0]
B[0,2]
G[0,5]
B[0,234] G[0,237]
B[0,m-6] G[0,m-3]
LD6
G[0,0]
R[0,3]
B[0,5]
R[0,235] B[0,237]
R[0,m-5] B[0,m-3]
LD5
B[0,0]
G[0,3]
R[0,6]
G[0,235] R[0,238]
G[0,m-5] R[0,m-2]
LD4
R[0,1]
B[0,3]
G[0,6]
B[0,235] G[0,238]
B[0,m-5] G[0,m-2]
LD3
G[0,1]
R[0,4]
B[0,6]
R[0,236] B[0,238]
R[0,m-4] B[0,m-2]
LD2
B[0,1]
G[0,4]
R[0,7]
G[0,236] R[0,239]
G[0,m-4] R[0,m-1]
LD1
R[0,2]
B[0,4]
G[0,7]
B[0,236] G[0,239]
B[0,m-4] G[0,m-1]
LD0
G[0,2]
R[0,5]
B[0,7]
R[0,237] B[0,239]
R[0,m-3] B[0,m-1]
LSCLK
Figure 19-11. LCDC Interface Timing for 8-Bit Data Passive Matrix Color Panels
19.3.8.3 Passive Panel Interface Timing
Figure 19-12 on page 19-14 shows the horizontal timing (timing of one line), including both the line pulse (LP) and
the data. The width of LP and delays both before and after LP are programmable. The parameters used for panel
interface timing are:
•
•
•
•
XMAX (X size) defines the number of pixels per line. XMAX is the total number of pixels per line.
H_WAIT_1 defines the delay from the end of data output to the beginning of LP.
H_WIDTH (horizontal sync pulse width) defines the width of the FLM pulse, and H_WIDTH must be at
least 1.
H_WAIT_2 defines the delay from the end of LP to the beginning of data output.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-13
LCDC Operation
NOTE:
All parameters are defined in unit of pixel clock period, unless stated otherwise.
19.3.9 8 bpp Mode Color STN Panel
Hwait2+2
Hwait2+2
VSYN
(last line)
Hwidth
4
Hwait1
XMAX
(first line)
Hwidth
HSYN
LSCLK
Ts
LD[15:0]
Figure 19-12. Horizontal Sync Pulse Timing in Passive Mode
PASS_FRAME_WAIT
YMAX
(lines)
FLM
LP
LSCLK
End of last line
Start of frame
Figure 19-13. Vertical Sync Pulse Timing Passive, Color, (Non-TFT) Mode
19.3.9.1 Active Matrix Panel Interface Signals
Figure 19-14 on page 19-16 shows the LCD interface timing for an active matrix color TFT panel. In this figure
signals are shown with negative polarity (FLMPOL=1, LPPOL=1, CLKPOL=0, OEPOL=1). In TFT mode, the
LSCLK is automatically inverted. The panel interface timing for active matrix panels is sometimes referred to as a
“digital CRT” and is controlled by the shift clock (LSCLK), horizontal sync pulse (HSYNC, the LP pin in passive
mode), vertical sync pulse (VSYNC, the FLM pin in passive mode), output enable (OE, the ACD pin in passive
mode), and line data (LD) signals. The sequence of events for active matrix interface timing is:
1. LSCLK latches data into the panel on its negative edge (when positive polarity is selected). In active
mode, LSCLK runs continuously.
MC9328MX1 Reference Manual, Rev. 6.1
19-14
Freescale Semiconductor
LCDC Operation
2. HSYNC causes the panel to start a new line.
3. VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
4. OE functions as an output enable signal to the CRT. This output enable signal is similar to the
blanking output in a CRT and enables the data to be shifted onto the display. When disabled, the
data is invalid and the trace is off.
In 4- and 8-bit mode, the LD [15:12] bits define red, the LD [10:7] bits define green, and the LD [4:1] bits define
blue. In 16-bit mode, the LD [15:11] bits define red, the LD [10:5] bits define green, and the LD [4:0] bits define
blue.
The actual TFT color channel assignments are shown in Table 19-7. In 4 bpp and 8 bpp, bits LD11, LD6, LD5 and
LD0 are fixed at 0.
Table 19-7. TFT Color Channel Assignments
LD
15
LD
14
LD
13
LD
12
LD
11
LD
10
LD
9
LD
8
LD
7
LD
6
LD
5
LD
4
LD
3
LD
2
LD
1
LD
0
4 bpp
R3
R2
R1
R0
–
G3
G2
G1
G0
–
–
B3
B2
B1
B0
–
8 bpp
R3
R2
R1
R0
–
G3
G2
G1
G0
–
–
B3
B2
B1
B0
–
12 bpp
R3
R2
R1
R0
–
G3
G2
G1
G0
–
–
B3
B2
B1
B0
–
16 bpp
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-15
LCDC Operation
VSYNC
HSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n
LINE 1
HSYNC
OE
1
2
3
239
240
m-1
m
LD15
R4[0,0]
R4[0,1]
R4[0,2]
R4[0,238] R4[0,239]
R4[0,m-2] R4[0,m-1]
LD14
R3[0,0]
R3[0,1]
R3[0,2]
R3[0,238] R3[0,239]
R3[0,m-2] R3[0,m-1]
LD13
R2[0,0]
R2[0,1]
R2[0,2]
R2[0,238] R2[0,239]
R2[0,m-2] R2[0,m-1]
LD12
R1[0,0]
R1[0,1]
R1[0,2]
R1[0,238] R1[0,239]
R1[0,m-2] R1[0,m-1]
LD11
R0[0,0]
R0[0,1]
R0[0,2]
R0[0,238] R0[0,239]
R0[0,m-2] R0[0,m-1]
LD10
G5[0,0]
G5[0,1]
G5[0,2]
G5[0,238] G5[0,239]
G5[0,m-2] G5[0,m-1]
LD9
G4[0,0]
G4[0,1]
G4[0,2]
G4[0,238] G4[0,239]
G4[0,m-2] G4[0,m-1]
LD8
G3[0,0]
G3[0,1]
G3[0,2]
G3[0,238] G3[0,239]
G3[0,m-2] G3[0,m-1]
LD7
G2[0,0]
G2[0,1]
G2[0,2]
G2[0,238] G2[0,239]
G2[0,m-2] G2[0,m-1]
LD6
G1[0,0]
G1[0,1]
G1[0,2]
G1[0,238] G1[0,239]
G1[0,m-2] G1[0,m-1]
LD5
G0[0,0]
G0[0,1]
G0[0,2]
G0[0,238] G0[0,239]
G0[0,m-2] G0[0,m-1]
LD4
B4[0,0]
B4[0,1]
B4[0,2]
B4[0,238] B4[0,239]
B4[0,m-2] B4[0,m-1]
LD3
B3[0,0]
B3[0,1]
B3[0,2]
B3[0,238] B3[0,239]
B3[0,m-2] B3[0,m-1]
LD2
B2[0,0]
B2[0,1]
B2[0,2]
B2[0,238] B2[0,239]
B2[0,m-2] B2[0,m-1]
LD1
B1[0,0]
B1[0,1]
B1[0,2]
B1[0,238] B1[0,239]
B1[0,m-2] B1[0,m-1]
LD0
B0[0,0]
B0[0,1]
B0[0,2]
B0[0,238] B0[0,239]
B0[0,m-2] B0[0,m-1]
LSCLK
Figure 19-14. LCDC Interface Timing for Active Matrix Color Panels
19.3.9.2 Active Panel Interface Timing
Figure 19-15 on page 19-17 shows the horizontal timing (timing of one line), including both the horizontal sync
pulse and the data. The width of HSYNC and delays both before and after HSYNC are programmable. The timing
signal parameters are defined as follows:
•
H_WIDTH defines the width of the HSYNC pulse and must be at least 1.
•
H_WAIT_2 defines the delay from the end of HSYNC to the beginning of the OE pulse.
•
H_WAIT_1 defines the delay from end of OE to the beginning of the HSYNC pulse.
•
XMAX defines the (total) number of pixels per line.
NOTE:
All parameters are defined in pixel periods, not LSCLK periods.
MC9328MX1 Reference Manual, Rev. 6.1
19-16
Freescale Semiconductor
LCDC Operation
H_WIDTH
H_WAIT_2
XMAX
H_WAIT_1
LSCLK
HSYNC
OE
DATA
VSYNC
Figure 19-15. Horizontal Sync Pulse Timing in TFT Mode
Figure 19-16 shows the vertical timing (timing of one frame). The delay from the end of one frame until the
beginning of the next is programmable. The memory timing signal parameters are:
•
V_WAIT_1 is a delay measured in lines. For V_WAIT_1= 1 there is a delay of one HSYNC
(time = one line period) before VSYNC. The HSYNC pulse is output during the V_WAIT_1 delay.
•
For V_WIDTH (vertical sync pulse width) = 0, VSYNC encloses one HSYNC pulse.
For V_WIDTH = 2, VSYNC encloses two HSYNC pulses.
•
V_WAIT_2 is a delay measured in lines. For V_WAIT_2 = 1, there is a delay of one HSYNC
(time = one line period) after VSYNC. The HSYNC pulse is output during the V_WAIT_2 delay.
End of frame
V_WIDTH
(lines)
Beginning of frame
YMAX
VSYNC
HSYNC
OE
V_WAIT_1
V_WAIT_2
Figure 19-16. Vertical Sync Pulse Timing TFT Mode
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-17
Programming Model
19.4 Programming Model
The LCDC memory space contains fifteen 32-bit registers for display parameters, a read-only status register, and a
256 x 12 Color Mapping RAM. The color mapping RAM is physically located inside the Palette Lookup Table
module.
Table 19-8 summarizes these registers and their addresses. Only WORD access is supported. Byte and halfword
access is undefined.
Table 19-8. LCDC Register Memory Map
Description
Name
Address
Screen Start Address Register
SSA
0x00205000
Size Register
SIZE
0x00205004
Virtual Page Width Register
VPW
0x00205008
LCD Cursor Position Register
CPOS
0x0020500C
LCD Cursor Width Height and Blink Register
LCWHB
0x00205010
LCD Color Cursor Mapping Register
LCHCC
0x00205014
Panel Configuration Register
PCR
0x00205018
Horizontal Configuration Register
HCR
0x0020501C
Vertical Configuration Register
VCR
0x00205020
Panning Offset Register
POS
0x00205024
Sharp Configuration 1 Register
LSCR1
0x00205028
PWM Contrast Control Register
PWMR
0x0020502C
DMA Control Register
DMACR
0x00205030
Refresh Mode Control Register
RMCR
0x00205034
Interrupt Configuration Register
LCDICR
0x00205038
Interrupt Status Register
LCDISR
0x00205040
Figure 19-9 on page 19-19 provides a quick overview of the fields of all the registers. There are intentional gaps
between the addresses for the read-write register section and the status register, and between the status register and
the mapping RAM.
MC9328MX1 Reference Manual, Rev. 6.1
19-18
Freescale Semiconductor
Programming Model
Table 19-9. Register Memory Mapping Summary
Register Register
Name
Location
Register Bits
31
(15)
30
(14)
29
28
27
26
(13) (12) (11) (10)
25
(9)
24
(8)
23
(7)
22
(6)
21 20
(5) (4)
19
(3)
18
(2)
17
(1)
16
(0)
Screen Start Address - SSA
SSA
0x00205000
Screen Start Address - SSA
Screen Width - XMAX
SIZE
0x00205004
Screen Height - YMAX
VPW
0x00205008
Virtual Page Width - VPW
CC1
CPOS
CC0
OP
Cursor X Position - CXP
0x0020500C
Cursor Y Position - CYP
BK_EN
LCWHB
Cursor Width - CW
Cursor Height - CH
0x00205010
BD
LCHCC
0x00205014
Cursor Red - CUR_COL_R
TFT
PCR
COLOR
Cursor Green - CUR_COL_G
Bus Width
PBSIZ
Bits Per Pixel
BPIX
PIX
POL
FLM
POL
Cursor Blue - CUR_COL_B
END_
CLK OE SCLK END_ BYTE_
REV _VS
POL POL IDLE SEL SWAP
LP
POL
0x00205018
ACD SEL
SCLK SHARP
SEL
Crystal Direction Toggle - ACD
Pixel Clock Divider - PCD
Horizontal Sync Width - H_WIDTH
HCR
0x0020501C
Horizontal Wait 1 - H_WAIT_1
Horizontal Wait 2 - H_WAIT_2
Vertical Sync Width - V_WIDTH
VCR
0x00205020
Vertical Wait 1 - V_WAIT_1
POS
Vertical Wait 2 - V_WAIT_2
0x00205024
Panning Offset - POS
PS_RISE_DELAY
LSCR1
CLS_RISE_DELAY
0x00205028
REV_TOGGLE_DELAY
Gray 1
Gray 2
CLS High Width
PWMR
0x0020502C
LD
MSK
CC
SCR1 SCR0 _EN
DMA High Mark - HM
BURST
DMACR
Pulse Width - PW
0x00205030
DMA Trigger Mark - TM
RMCR
0x00205034
LCDICR
0x00205038
INT
SYN
LCDISR
0x00205040
UDR ERR
_ERR _RES
LCDC
_EN
SELF
_REF
INT
CON
EOF
BOF
0x00205800
First RAM Location(R [3:0], G [3:0], B [3:0])
0x00205BFC
Last RAM Location(R [3:0], G [3:0], B [3:0])
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-19
Programming Model
19.4.1 Screen Start Address Register
The Screen Start Address Register specifies the start address of the LCD screen. See Figure 19-2.
SSA
BIT
Addr
0x00205000
Screen Start Address Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SSA
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSA
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-10. Screen Start Address Register Description
Name
Description
SSA
Bits 31–2
Screen Start Address of LCD Panel—Holds pixel data for a new frame from the SSA address. This field
must start at a location that enables a complete picture to be stored in a 4 Mbyte memory boundary (A [21:0]).
A [31:22] has a fixed value for a picture’s image.
Reserved
Bits 1–0
Reserved—These bits are reserved and should read 0.
MC9328MX1 Reference Manual, Rev. 6.1
19-20
Freescale Semiconductor
Programming Model
19.4.2 Size Register
The Size Register defines the height and width of the LCD screen.
SIZE
BIT
Addr
0x00205004
Size Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
XMAX
TYPE
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
YMAX
TYPE
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-11. Size Register Description
Name
Description
Reserved
Bits 31–26
Reserved—These bits are reserved and should read 0.
XMAX
Bits 25–20
Screen Width Divided by 16—Holds screen x-axis size, divided by 16. For black-and-white panels (1 bpp),
XMAX [20] is ignored, forcing the x-axis of the screen size to be a multiple of 32 pixels/line.
Reserved
Bits 19–9
Reserved—These bits are reserved and should read 0.
YMAX
Bits 8–0
Screen Height—Specifies the height of the LCD panel in terms of pixels or lines. The lines are numbered
from 1 to YMAX for a total of YMAX lines.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-21
Programming Model
19.4.3 Virtual Page Width Register
The Virtual Page Width Register defines the width of the virtual page for the LCD panel. See Figure 19-2 on
page 19-3.
VPW
Addr
0x00205008
Virtual Page Width Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
VPW
TYPE
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-12. Virtual Page Width Register Description
Name
Description
Reserved
Bits 31–10
Reserved—These bits are reserved and should read 0.
VPW
Bits 9–0
Virtual Page Width—Defines the virtual page width of the LCD panel. The VPW bits represent the number of
32-bit words required to hold the data for one virtual line. VPW is used in calculating the starting address
representing the beginning of each displayed line.
MC9328MX1 Reference Manual, Rev. 6.1
19-22
Freescale Semiconductor
Programming Model
19.4.4 Panel Configuration Register
The Panel Configuration Register defines all of the properties of the LCD screen.
PCR
Addr
0x00205018
Panel Configuration Register
BIT
31
30
TFT
COLOR
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
TYPE
29
28
27
PBSIZ
26
25
24
23
22
21
20
19
18
17
16
PIX
POL
FLM
POL
LP
POL
CLK
POL
OE
POL
SCLK
IDLE
END_
SEL
SWAP_SEL
REV_
VS
rw
rw
rw
rw
rw
rw
rw
r
r
rw
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
BPIX
RESET
0x0000
BIT
15
14
13
12
ACD
SEL
TYPE
11
10
9
8
ACD
7
6
SCLK
SEL
SHARP
PCD
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-13. Panel Configuration Register Description
Name
Description
Settings
TFT
Bit 31
Interfaces to TFT Display—Controls the format and
timing of the output control signals. Active and passive
displays use different signal timing formats as described
in Section 19.3.8, “Panel Interface Signals and Timing.”
TFT also controls the use of the FRC in color mode.
0 = The LCD panel is a passive display
1 = The LCD panel is an active display: “digital
CRT” signal format, FRC is bypassed, LD
bus width is fixed at 16-bits
COLOR
Bit 30
Interfaces to Color Display—Activates three channels of
FRC in passive mode to allow use of the special 2 2/3
pixels per output vector format.
0 = The LCD panel is a monochrome display
1 = The LCD panel is a color display
PBSIZ
Bits 29–28
Panel Bus Width—Specifies the panel bus width.
Applicable for monochrome or passive matrix color
monitors. For active (TFT) color panels, the panel bus
width is fixed at 16. For passive color panels, only an 8-bit
panel bus width is supported.
00 = 1-bit
01 = 2-bit
10 = 4-bit
11 = 8-bit
BPIX
Bits 27–25
Bits Per Pixel—Indicates the number of bits per pixel in
memory.
000 = 1 bpp, FRC bypassed
001 = 2 bpp
010 = 4 bpp
011 = 8 bpp
100 = 12 bpp/16 bpp (16 bits of memory used)
11x = reserved
1x1 = reserved
PIXPOL
Bit 24
Pixel Polarity—Sets the polarity of the pixels.
0 = Active high
1 = Active low
Note:
For a TFT panel, set COLOR=1
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-23
Programming Model
Table 19-13. Panel Configuration Register Description (continued)
Name
Description
Settings
FLMPOL
Bit 23
First Line Marker Polarity—Sets the polarity of the first
line marker symbol.
0 = Active high
1 = Active low
LPPOL
Bit 22
Line Pulse Polarity—Sets the polarity of the line pulse
signal.
0 = Active high
1 = Active low
CLKPOL
Bit 21
LCD Shift Clock Polarity—Sets the polarity of the active
edge of the LCD shift clock.
0 = Active negative edge of LSCLK (in TFT
mode, active on positive edge of LSCLK)
1 = Active positive edge of LSCLK (in TFT
mode, active on negative edge of LSCLK)
OEPOL
Bit 20
Output Enable Polarity—Sets the polarity of the output
enable signal.
0 = Active high
1 = Active low
SCLKIDLE
Bit 19
LSCLK Idle Enable—Enables/Disables LSCLK when
VSYNC is idle in TFT mode.
0 = Disable LSCLK
1 = Enable LSCLK
END_SEL
Bit 18
Endian Select—Selects the image download into
memory as big or little endian format.
0 = Little endian
1 = Big endian
SWAP_SEL
Bit 17
Swap Select—Controls the swap of data in little endian
mode (when END_SEL = 1 this bit has no effect).
0 = 16 bpp mode
1 = 8 bpp. 4 bpp, 2 bpp, 1 bpp mode
REV_VS
Bit 16
Reverse Vertical Scan—Selects the vertical scan
direction as normal or reverse (the image flips along the
x-axis). The SSA register must be changed accordingly.
0 = Vertical scan in normal direction
1 = Vertical scan in reverse direction
ACDSEL
Bit 15
ACD Clock Source Select—Selects the clock source
used by the alternative crystal direction counter.
0 = Use FRM as clock source for ACD count
1 = Use LP/HSYN as clock source for ACD
count
ACD
Bits 14–8
Alternate Crystal Direction—Toggles the ACD signal
once every 1-16 FLM cycles based on the value specified
in this field. The actual number of FLM cycles between
toggles is the programmed value plus one.
For active mode (TFT=1), this parameter is not
used.
For passive mode (TFT=0), see description.
SCLKSEL
Bit 7
LSCLK Select—Selects whether to enable or disable
LSCLK in TFT mode when there is no data output.
0 = Disable OE and LSCLK in TFT mode when
no data output
1 = Always enable LSCLK in TFT mode even if
there is no data output
SHARP
Bit 6
Sharp Panel Enable—Enables/Disables signals for
Sharp HR-TFT panels.
0 = Disable Sharp signals
1 = Enable Sharp signals
MC9328MX1 Reference Manual, Rev. 6.1
19-24
Freescale Semiconductor
Programming Model
Table 19-13. Panel Configuration Register Description (continued)
Name
PCD
Bits 5–0
Description
Settings
Pixel Clock Divider—Specifies the divide ratio applied to
LCDC_CLK. The LCDC_CLK (PerCLK2) is divided down
by the Pixel Clock Divider to generate the pixel clock. The
LSCLK will be the same as pixel clock in TFT mode, and
will be 1/8 the frequency of the pixel clock in passive
mode.
TFT (TFT bit = 1)
000000 = divide ratio is 1
000001 = divide ratio is 2
000010 = divide ratio is 3
…
111111 = divide ratio is 64
For passive displays (TFT bit = 0), the frequency of
LSCLK must be < 1/9 HCLK at 12 bpp and < 1/15 HCLK
at 4 or 8 bpp. For passive matrix color panels (COLOR = 1
and PBSIZ = 11), PCD must be ≥ 2 and PCLK_DIV2
(PCDR Register) must = 0 (divide by 1). See
Phase-Locked Loop and Clock Controller chapter in this
manual for PCDR register information.
Passive (TFT bit = 0)
000000 = divide ratio is 81
000001 = divide ratio is 161
000010 = divide ratio is 24
…
111111 = divide ratio is 512
For active displays (TFT bit = 1), the frequency of LSCLK
must be < 1/5 HCLK. When PCD = 0, the pixel clock
frequency is equal to the LCDC_CLK frequency.
Note 1: Do not use. For passive panels, PCD
must be greater than or equal to 2 or 000010.
See application notes at http:\\www.freescale.com\imx.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-25
Programming Model
19.4.5 Horizontal Configuration Register
The Horizontal Configuration Register defines the horizontal sync pulse timing.
HCR
BIT
Addr
0x0020501C
Horizontal Configuration Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
H_WIDTH
TYPE
rw
rw
rw
rw
rw
rw
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0400
BIT
15
14
13
12
11
10
9
8
H_WAIT_1
TYPE
H_WAIT_2
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-14. Horizontal Configuration Register Description
Name
Description
H_WIDTH
Bits 31–26
Horizontal Sync Pulse Width—Specifies the number of pixel clk periods that HSYNC is activated. The
active time is equal to (H_WIDTH + 1) of the pixel clk period. For Sharp HR-TFT panels, H_WIDTH is
typically set to 1.
Reserved
Bits 25–16
Reserved—These bits are reserved and should read 0.
H_WAIT_1
Bits 15–8
Wait Between OE and HSYNC—Specifies the number of pixel clk periods between the last LD of each line
and the beginning of the HSYNC. Total delay time equals (H_WAIT_1 + 1). For Sharp HR-TFT panels,
H_WAIT_1 is typically set to 14.
H_WAIT_2
Bits 7–0
Wait Between HSYNC and Start of Next Line—Specifies the number of pixel clk periods between the end
of HSYNC and the beginning of the first data of next line. Total delay time equals (H_WAIT_2 + 3).
MC9328MX1 Reference Manual, Rev. 6.1
19-26
Freescale Semiconductor
Programming Model
19.4.6 Vertical Configuration Register
The Vertical Configuration Register defines the vertical sync pulse timing.
VCR
BIT
Addr
0x00205020
Vertical Configuration Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
V_WIDTH
TYPE
rw
rw
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
RESET
0x0401
BIT
15
14
13
12
11
10
9
8
V_WAIT_1
TYPE
V_WAIT_2
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-15. Vertical Configuration Register Description
Name
Description
V_WIDTH
Bits 31–26
Vertical Sync Pulse Width—Specifies the width, in lines, of the VSYNC pulse for active (TFT =1) mode.
For a value of “000001”, the vertical sync pulse encompasses one HSYNC pulse. For a value of “000002”,
the vertical sync pulse encompasses two HSYNC pulses, and so on. For passive (TFT=0) mode and
non-color mode, see Figure 19-12.
Reserved
Bits 25–16
Reserved—These bits are reserved and should read 0.
V_WAIT_1
Bits 15–8
Wait Between Frames 1—Defines the delay, in lines, between the end of the OE pulse and the beginning
of the VSYNC pulse for active (TFT=1) mode. This field has no meaning in passive non-color mode. The
actual delay is (V_WAIT_1). In passive color mode, this field is the delay, measured in virtual clock periods,
between the last line of the frame to the beginning of the next frame.
V_WAIT_2
Bits 7–0
Wait Between Frames 2—Defines the delay, in lines, between the end of the VSYNC pulse and the
beginning of the OE pulse of the first line in active (TFT=1) mode. The actual delay is V_WAIT_2 ) lines.
Set this field to zero for passive non-color mode. The minimum value of this field is 0x01.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-27
Programming Model
19.4.7 Panning Offset Register
The Panning Offset Register sets up the panning for the image.
POS
Addr
0x00205024
Panning Offset Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
POS
TYPE
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-16. Panning Offset Register Description
Name
Description
Reserved
Bits 31–5
Reserved—These bits are reserved and should read 0.
POS
Bits 4–0
Panning Offset—Defines the number of bits that the
data from memory is panned to the left before
processing. POS is read by the LCDC once at the
beginning of each frame.
Settings
To achieve panning of the final image by N bits:
Bits Per Pixel
POS
Effective # of Bits
Panned on Image
1
N
N
2
2N
N
4
4N
N
8
8N
N
12
16N
N
MC9328MX1 Reference Manual, Rev. 6.1
19-28
Freescale Semiconductor
Programming Model
19.4.8 LCD Cursor Position Register
The LCD Cursor Position Register is used to determine the starting position of the cursor on the LCD panel.
CPOS
BIT
31
30
29
CC
TYPE
Addr
0x0020500C
LCD Cursor Position Register
28
27
26
25
24
23
22
21
OP
20
19
18
17
16
CXP
rw
rw
r
rw
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
CYP
TYPE
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-17. LCD Cursor X Position Register Description
Name
CC
Bits 31–30
Description
Cursor Control—Controls the format of the cursor and the
type of arithmetic operations.
Settings
When OP = 0
00 = Transparent, cursor is disabled
01 = Full cursor (Black for non-color
displays; full-color for color displays)
10 = Reversed video
11 = Full (white) cursor
When OP = 1, and color mode
00 = Transparent, cursor is disabled
01 = OR between background and cursor
10 = XOR between background and cursor
11 = AND between background and cursor
Reserved
Bit 29
Reserved—This bit is reserved and should read 0.
OP
Bit 28
Arithmetic Operation Control—Enables/Disables
arithmetic operations between the background and the
cursor.
Reserved
Bits 27–26
Reserved—These bits are reserved and should read 0.
CXP
Bits 25–16
Cursor X Position—Represents the cursor’s horizontal starting position X in pixel count (from 0 to XMAX).
Reserved
Bits 15–9
Reserved—These bits are reserved and should read 0.
CYP
Bits 8–0
Cursor Y Position—Represents the cursor’s vertical starting position Y in pixel count (from 0 to YMAX).
0 = Disable arithmetic operation
1 = Enable arithmetic operation
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-29
Programming Model
19.4.9 LCD Cursor Width Height and Blink Register
The LCD Cursor Width Height and Blink Register is used to determine the width and height of the cursor, and how
it blinks.
LCWHB
BIT
31
30
29
28
27
BK_EN
TYPE
Addr
0x00205010
LCD Cursor Width Height and Blink Register
26
25
24
23
22
21
20
19
CW
18
17
16
CH
rw
r
r
rw
rw
rw
rw
rw
r
r
r
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
RESET
0X0101
BIT
15
14
13
12
11
10
9
8
BD
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
RESET
0X007F
Table 19-18. LCD Cursor Width Height and Blink Register Description
Name
Description
Settings
BK_EN
Bit 31
Blink Enable—Determines whether the blink enable cursor
will blink or remain steady.
0 = Blink is disabled
1 = Blink is enabled
Reserved
Bits 30–29
Reserved—These bits are reserved and should read 0.
CW
Bits 28–24
Cursor Width—Specifies the width of the hardware cursor in
pixels.
Reserved
Bits 23–21
Reserved—These bits are reserved and should read 0.
CH
Bits 20–16
Cursor Height—Specifies the height of the hardware cursor
in pixels.
Reserved
Bits 15–8
Reserved—These bits are reserved and should read 0.
BD
Bits 7–0
Blink Divisor—Sets the cursor blink rate. A 32 Hz clock from RTC is used to clock the 8-bit up counter. When
the counter value equals BD, the cursor toggles on/off.
This field can be any value between 1 and 31
(setting this field to zero disables the cursor)
This field can be any value between 1 and 31
(setting this field to zero disables the cursor)
MC9328MX1 Reference Manual, Rev. 6.1
19-30
Freescale Semiconductor
Programming Model
19.4.10 LCD Color Cursor Mapping Register
The LCD Color Cursor Mapping Register defines the color of the cursor in passive or TFT color modes.
LCHCC
Addr
0x00205014
LCD Color Cursor Mapping Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
CUR_COL_R
TYPE
8
CUR_COL_G
CUR_COL_B
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-19. LCD Color Cursor Mapping Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
CUR_COL_R
Bits 15–11
Cursor Red Field—Defines the red component of the
cursor color in color mode.
For 8 bpp/12 bpp:
0000x = No red
...
1111x = Full red
For 16 bpp:
00000 = No red
...
11111 = Full red
CUR_COL_G
Bits 10–5
Cursor Green Field—Defines the green component of
the cursor color in color mode.
For 8 bpp/12 bpp:
0000xx = No green
....
1111xx = Full green
For 16 bpp:
000000 = No green
...
111111 = Full green
CUR_COL_B
Bits 4–0
Cursor Blue Field—Defines the blue component of
the cursor color in color mode.
For 8 bpp/12 bpp:
0000x = No blue
...
1111x = Full blue
For 16 bpp:
00000 = No blue
...
11111 = Full blue
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-31
Programming Model
19.4.11 Sharp Configuration 1 Register
For 2 bpp modes, full black and full white are the two predefined display levels. The other two intermediate
gray-scale shading densities can be adjusted within the Sharp Configuration 1 Register. This register also controls
the relative delay timing of the additional signals CLS, REV, and PS required for Sharp TFT displays. The TFT
timing diagram that shows the relationship between these signals is shown in Figure 19-17 on page 19-33.
LSCR1
BIT
Sharp Configuration 1 Register
31
30
29
28
27
26
25
24
23
22
21
PS_RISE_DELAY
TYPE
0x00205028
20
19
18
17
16
CLS_RISE_DELAY
rw
rw
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0400
BIT
15
14
13
12
11
10
9
8
7
REV_TOGGLE_DELAY
TYPE
GRAY 1
GRAY 2
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
1
1
0
1
1
1
0
0
1
1
RESET
0x0373
Table 19-20. Sharp Configuration 1 Register Description
Name
Description
PS_RISE_DELAY
Bits 31–26
PS Rise Delay—Controls the delay of the rising edge of
PS relative to the falling edge of CLS. Delay is measured
in LCDC_CLK (PerCLK2) periods.
Reserved
Bits 25–24
Reserved—These bits are reserved and should read 0.
CLS_RISE_DELAY
Bits 23–16
CLS Rise Delay—Controls the delay of the rising edge of
CLS relative to the last LD of the line. Delay is measured
in LCDC_CLK (PerCLK2) periods.
Reserved
Bits 15–12
Reserved—These bits are reserved and should read 0.
Settings
000000 = 0 LSCLK periods
000001 = 1 LSCLK period
...
111111 = 63 LSCLK periods
00000000 = 1 LSCLK period
00000001 = 2 LSCLK periods
...
11111111 = 256 LSCCLK periods
REV_TOGGLE_DELAY REV Toggle Delay—Controls the transition delay of REV
Bits 11–8
relative to the last LD of the line. Delay is measured in
LCDC_CLK (PerCLK2) periods.
0000 = 1 LSCLK period
0001 = 2 LSCLK periods
...
1111 = 16 LSCLK periods
GRAY 2
Bits 7–4
Gray-Scale 2—Represents one of the two gray-scale
shading densities.
This field is programmable to any value
between 0 and 16 (0 and 16 are
defined as two of the four colors).
GRAY 1
Bits 3–0
Gray-Scale 1—Represents the other gray-scale shading.
This field is programmable to any value
between 0 and 16 (0 and 16 are
already defined as two of the four
colors).
MC9328MX1 Reference Manual, Rev. 6.1
19-32
Freescale Semiconductor
Programming Model
XMAX
LSCLK
R0-R5
G0-G5
B0-B5
D1 D2
D320
SPL
SPR
D320
1 CLK
Hwait1
Hwait1
Hwait2
LP
cls_rise_delay + 1
cls_width
CLS
PS
ps_rise_delay
rev_tog_delay +1
rev_tog_delay +1
REV
Falling edge of PS aligns with rising edge of CLS
The rising edge delay of PS is programmed by PS_RISE_DELAY
CLS_HI_WIDTH is equal to PWM_SCR0 • 256 + PWM_WIDTH in units of LSCLK.
SPL/SPR pulse width is fixed and aligned to the first data of the line.
REV toggles every LP period.
Figure 19-17. Horizontal Timing in MC9328MX1
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-33
Programming Model
19.4.12 PWM Contrast Control Register
The PWM Contrast Control Register is used to control the signal output at the CONTRAST pin, which controls the
contrast of the LCD panel.
PWMR
BIT
Addr
0x0020502C
PWM Contrast Control Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CLS_HI_WIDTH
TYPE
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
LDMSK
TYPE
9
SCR
8
CC_EN
PW
rw
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-21. PWM Contrast Control Register Description
Name
Description
Settings
Reserved
Bits 31–25
Reserved—These bits are reserved and should read 0.
CLS_HI_
WIDTH
Bit 24–16
CLS High Pulse Width—Controls the Hi Pulse width of CLS in units of SCLK. The actual pulse width =
CLS_HI_WDITH +1.
LDMSK
Bit 15
LD Mask—Enables/Disables the LD outputs to zero for panel power-off
sequence as required by Sharp TFT or other panels.
Reserved
Bits 14–11
Reserved—These bits are reserved and should read 0.
SCR
Bits 10–9
Source Select—Selects the input clock source for the PWM counter. The
PWM output frequency is equal to the frequency of the input clock divided
by 256.
00 = Line pulse
01 = Pixel clock
10 = LCD clock
11 = Reserved
CC_EN
Bit 8
Contrast Control Enable—Enables/Disables the contrast control function.
0 = Contrast control is off
1 = Contrast control is on
PW
Bits 7–0
Pulse-Width—Controls the pulse-width of the built-in pulse-width modulator, which controls the contrast of the
LCD screen.
0 = LD [15:0] is normal
1 = LD [15:0] always equals 0
MC9328MX1 Reference Manual, Rev. 6.1
19-34
Freescale Semiconductor
Programming Model
19.4.13 Refresh Mode Control Register
The Refresh Mode Control Register is used to control refresh characteristics.
RMCR
Addr
0x00205034
Refresh Mode Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
LCDC_EN SELF_REF
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-22. Refresh Mode Control Register Description
Name
Description
Settings
Reserved
Bits 31–2
Reserved—These bits are reserved and should read 0.
LCDC_EN
Bit 1
LCDC Enable—Enables/Disables the LCDC.
0 = Disable the LCDC
1 = Enable the LCDC
SELF_REF
Bit 0
Self-Refresh—Enables/Disables self-refresh mode.
0 = Disable self-refresh
1 = Enable self-refresh
NOTE:
1. On entering self-refresh mode, the LSCLK and LD [15:0] signals stay low. HYSN and VSYN operate
normally.
2. Except for the SSA and Mapping RAM registers, all configurations must be performed before
enabling the LCDC to avoid a malfunction.
3. The SSA must always match the address range of the RAM selected. If the user wants to switch
between various types of RAM, the LCDC must be disabled before switching.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-35
Programming Model
19.4.14 DMA Control Register
There is a 16 × 32 bit line buffer in the LCDC that stores DMA data from system memory. The DMA Control
Register controls the DMA burst length and when to trigger a DMA burst in terms of the number of data bytes left
in the pixel buffer.
DMACR
BIT
Addr
0x00205030
DMA Control Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
BURST
TYPE
17
16
HM
rw
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
7
6
5
4
3
2
1
0
RESET
0x8008
BIT
15
14
13
12
11
10
9
8
TM
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
RESET
0x0002
Table 19-23. DMA Control Register Description
Name
Description
Settings
BURST
Bit 31
Burst Length—Determines whether the burst length is fixed or
dynamic.
0 = Burst length is dynamic
1 = Burst length is fixed
Reserved
Bits 30–20
Reserved—These bits are reserved and should read 0.
HM
Bits 19–16
DMA High Mark—Establishes the high mark for DMA requests. For dynamic burst length, once the DMA
request is made, data is loaded and the pixel buffer continues to be filled until the number of empty words left
in the DMA FIFO is equal to the high mark minus 2. For fixed burst length, the burst length (in words) of each
request is equal to the DMA high mark setting.
Reserved
Bits 15–4
Reserved—These bits are reserved and should read 0.
TM
Bits 3–0
DMA Trigger Mark—Sets the low level mark in the pixel buffer to trigger a DMA request. The low level mark
equals the number of words left in the pixel buffer.
NOTE:
For SDRAM access, a fixed burst length of 8 is recommended
fixed burst length = 1
high mark = 8
low mark = 4
For bus that is heavy loaded that requires SDRAM access, a dynamic burst length
is recommended
fixed burst length = 0
MC9328MX1 Reference Manual, Rev. 6.1
19-36
Freescale Semiconductor
Programming Model
high mark = 3
low mark = 8
For an especially heavily loaded system, increasing the low mark value increases
the chance of granting of the system bus, at the expense of more frequent bus
requests.
The low mark should never be set higher than 10, and high mark should always
be set to 3.
19.4.15 Interrupt Configuration Register
The Interrupt Configuration Register is used to configure the interrupt conditions.
LCDICR
Addr
0x00205038
Interrupt Configuration Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0X0000
BIT
15
14
13
12
11
10
9
8
7
INT SYN
TYPE
INT CON
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
r
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-24. Interrupt Configuration Register Description
Name
Description
Reserved
Bits 31–3
Reserved—These bits are reserved and should read 0.
INTSYN
Bit 2
Interrupt Source—Determines if an interrupt flag is set during last
data/first data of frame loading or on last data/first data of frame
output to the LCD panel.
Note: There is a latency between loading the last/first data of
frame to output to LCD panel.
Reserved
Bit 1
Reserved—This bit is reserved and should read 0.
INTCON
Bit 0
Interrupt Condition—Determines if an interrupt condition is set at
the beginning or the end of frame condition.
Settings
0 = Interrupt flag is set on loading the last
data/first data of frame from memory
1 = Interrupt flag is set on output of the last
data/first data of frame to LCD panel
0 = Interrupt flag is set when the End of
Frame (EOF) is reached
1 = Interrupt flag is set when the Beginning
of Frame (BOF) is reached
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-37
Programming Model
19.4.16 Interrupt Status Register
The read-only Interrupt Status Register indicates whether an interrupt has occurred. The interrupt flag is cleared by
reading the register.
LCDISR
Addr
0x00205040
Interrupt Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
EOF
BOF
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
UDR_ ERR_
ERR
RES
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 19-25. Interrupt Status Register Description
Name
Description
Settings
Reserved
Bits 31–4
Reserved—These bits are reserved and should read 0.
UDR_ERR
Bit 3
Under Run Error—Indicates whether the LCDC FIFO has hit an under-run
condition. This is when the data output rate is faster than the data input rate
to the FIFO. Under-run can cause erroneous data output to LD. The LD data
output rate must be adjusted to prevent this error.
0 = Interrupt has not occurred
1 = Interrupt has occurred
ERR_RES
Bit 2
Error Response—Indicates whether the LCDC has issued a read data
request and has received a response from the memory controller not equal to
‘OK.’ It is cleared by reading the status register, at power on reset, or when
the LCDC is disabled.
0 = Interrupt has not occurred
1 = Interrupt has occurred
EOF
Bit 1
End of Frame—Indicates whether the end of frame has been reached. It is
cleared by reading the status register, at power on reset, or when the LCDC
is disabled.
0 = Interrupt has not occurred
1 = Interrupt has occurred
BOF
Bit 0
Beginning of Frame—Indicates whether the beginning of frame has been
reached. It is cleared by reading the status register, at power on reset, or
when the LCDC is disabled.
0 = Interrupt has not occurred
1 = Interrupt has occurred
MC9328MX1 Reference Manual, Rev. 6.1
19-38
Freescale Semiconductor
Programming Model
19.4.17 Mapping RAM Registers
The mapping RAM is used for mapping 4-bit codes for grayscale to the 16 gray shades, and for mapping 4- or 8-bit
color codes to either the 4096 (for active panels) or 512 colors (for passive panels). The color RAM
(0x00205800-0x00205BFC) contains 256 entries and each entry is 12 bits wide. Each RAM entry use 4 bytes of
address space. The RAM can be accessed with word transactions only and the address must be word aligned.
Unimplemented bits are read as 0. Byte or halfword access to the RAM corrupts its contents. All read/write data
use least significant twelve bits.
In 4 bpp mode, the first sixteen RAM entries are used. In 8 bpp mode, all 256 RAM entries are used. The color
RAM is not initialized at reset. With any given panel, only one of the following settings is valid:
•
1 bpp monochrome mode
•
4 bpp gray-scale mode
•
4 bpp passive matrix color mode
•
8 bpp passive matrix color mode
•
4 bpp active matrix color mode
•
8 bpp active matrix color mode
•
12/16 bpp active matrix color mode
19.4.17.1 One Bit/Pixel Monochrome Mode
The mapping RAM is not used in this mode because the LCDC uses the display data in memory to drive the panel
directly.
19.4.17.2 Four Bits/Pixel Gray-Scale Mode
In four bits/pixel gray-scale mode, a 4-bit code represents a gray-scale level. The first 16 mapping RAM entries
must be written to define the codes for all 16 combinations.
BIT
11
10
9
8
7
6
5
4
3
2
1
0
GPM
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
0
0
0
0
0
0
0
0
?
?
?
?
RESET
Table 19-26. Four Bits/Pixel Gray-Scale Mode
Name
Description
Reserved
Bits 11–4
Reserved—These bits are reserved and should read 0.
GPM
Bits 3–0
Gray Palette Map—Represents the gray-scale level for a given pixel code.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-39
Programming Model
19.4.17.3 Four Bits/Pixel Passive Matrix Color Mode
In four bits/pixel passive matrix color mode, a 4-bit code represents a 12-bit color. Because just four bits are used
to encode the color, a maximum of 16 colors can be selected out of a palette of 4096. The first 16 mapping RAM
entries must be written to define the codes for the 16 available combinations.
BIT
11
10
9
8
7
6
5
R
TYPE
4
3
2
G
1
0
B
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
?
?
?
?
?
?
?
?
?
?
?
?
RESET
0X???
Table 19-27. Four Bits/Pixel Passive Matrix Color Mode
Name
Description
R
Bits 11–8
Red Level (color display)—Represents the red component level in the color.
G
Bits 7–4
Green Level (color display)—Represents the green component level in the color.
B
Bits 3–0
Blue Level (color display)—Represents the blue component level in the color.
19.4.17.4 Eight Bits/Pixel Passive Matrix Color Mode
In eight bits/pixel passive matrix color mode, an 8-bit code represents a 12-bit color. Because eight bits are used to
encode the color, a maximum of 256 colors can be selected out of a palette of 4096. All 256 mapping RAM entries
must be written to define the codes for the 256 available combinations.
BIT
11
10
9
8
7
6
5
R
TYPE
4
3
2
G
1
0
B
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
?
?
?
?
?
?
?
?
?
?
?
?
RESET
0x???
Table 19-28. Eight Bits/Pixel Passive Matrix Color Mode
Name
Description
R
Bits 11–8
Red Level (color display)—Represents the red component level in the color.
G
Bits 7–4
Green Level (color display)—Represents the green component level in the color.
B
Bits 3–0
Blue Level (color display)—Represents the blue component level in the color.
MC9328MX1 Reference Manual, Rev. 6.1
19-40
Freescale Semiconductor
Programming Model
19.4.17.5 Four Bits/Pixel Active Matrix Color Mode
In four bits/pixel active color mode, a 4-bit code represents a 12-bit color. Because just four bits are used to encode
the color, a maximum of 16 colors can be selected out of a palette of 4096. The first 16 mapping RAM entries must
be written to define the codes for the 16 available combinations.
BIT
11
10
9
8
7
6
5
R
TYPE
4
3
2
G
1
0
B
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
?
?
?
?
?
?
?
?
?
?
?
?
RESET
0x???
Table 19-29. Four Bits/Pixel Active Matrix Color Mode
Name
Description
R
Bits 11–8
Red Level (color display)—Represents the red component level in the color.
G
Bits 7–4
Green Level (color display)—Represents the green component level in the color.
B
Bits 3–0
Blue Level (color display)—Represents the blue component level in the color.
19.4.17.6 Eight Bits/Pixel Active Matrix Color Mode
In eight bits/pixel active color mode, an 8-bit code represents a 12-bit color. Because eight bits are used to encode
the color, a maximum of 256 colors can be selected out of a palette of 4096. All 256 mapping RAM entries must be
written to define the codes for the 256 available combinations.
BIT
11
10
9
8
7
6
5
R
TYPE
4
3
2
G
1
0
B
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
?
?
?
?
?
?
?
?
?
?
?
?
RESET
0x???
Table 19-30. Eight Bits/Pixel Active Matrix Color Mode
Name
Description
R
Bits 11–8
Red Level (color display)—Represents the red component level in the color.
G
Bits 7–4
Green Level (color display)—Represents the green component level in the color.
B
Bits 3–0
Blue Level (color display)—Represents the blue component level in the color.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
19-41
Programming Model
19.4.17.7 Twelve Bits/Pixel and Sixteen Bits/Pixel Active Matrix Color Mode
In this mode the mapping RAM is not used, because the LCDC uses the display data in memory to drive the panel
directly.
MC9328MX1 Reference Manual, Rev. 6.1
19-42
Freescale Semiconductor
Chapter 20
Multimedia Card/Secure Digital Host Controller Module
(MMC/SD)
20.1 Introduction
The Multimedia Card (MMC) is a universal low cost data storage and communication medium implemented as a
hardware card with a simple control unit and a compact, easy-to-implement interface that is designed to cover a
wide variety of applications such as electronic toys, organizers, PDAs, and smart phones. MMC communication is
based on an advanced 7-pin serial bus designed to operate in a low voltage range at medium speed (20 Mbps).
The Secure Digital Card (SD) is an evolution of the MMC with an additional 2 pins in the form factor that is
specifically designed to meet the security, capacity, performance, and environmental requirements inherent in new
audio and video consumer electronic devices. The physical form factor, pin assignment, and data transfer protocol
are compatible with the MMC. The SD is composed of a memory card and an I/O card. The memory card includes
a copyright protection mechanism that complies with the security requirements of the Secure Digital Music
Initiative (SDMI) standard, and is faster and has a higher memory capacity. The I/O card combines high-speed data
I/O with low-power consumption for mobile electronic devices.
The Multimedia Card/Secure Digital Host Controller module (MMC/SD module) integrates MMC support with
SD memory and I/O functions. The copyright protection mechanism employs mutual authentication and a new
cipher algorithm, and is handled in software post-processing.
20.2 Features List
The MMC/SD module includes the following features:
•
Compatible with the MultiMediaCard System Specification (SPI mode excluded), version 3.1
•
Compatible to 1/4 bit with the SD Memory Card Specification (SPI mode excluded), version 1.0 and SD I/O
Specification (SPI mode excluded), version 1.0 with 1 or 4 channel(s)
•
20–100 Mbps maximum data rate supports up to 10 cards (including one SD card)
•
Password protection for cards
•
Built-in programmable frequency counter for MMC/SD bus
•
Maskable hardware interrupt for card detection (insertion/removal), SD I/O interrupt, internal status, and
FIFO status
•
Contains an integrated 32 × 16-bit FIFO
•
Supports plug-and-play (PnP)
•
Supports many SD functions including multiple I/O and combined I/O and memory
•
Supports up to seven I/O functions plus one memory on a single SD I/O card
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-1
MMC/SD Module Block Diagram
•
Card can interrupt MMC/SD module
•
MMC/SD module is IP bus compatible with Motorola’s microcontrollers
•
Supports single or multiple block access, or stream access to the card for read, write, or erase operations
•
Supports SD I/O ReadWait and interrupt detection during 1- or 4-bit access
20.3 MMC/SD Module Block Diagram
Figure 20-1 is the block diagram of the MMC/SD module. Figure 20-2 is the system interconnection diagram for
the MMC/SD Host Controller module.
Secure Digital Host Controller
(SDHC)
Channel Control
Configuration
Application
Bus
IP
Gasket
(Application
Adapter)
System
StateMachine
&
DMA
Handler
CMD Channel
StateMachine
Logic
Control
CMD
CRC
CMD/
Data
Channel
Tx/Rx
Handler
Register
Handler
32x16
FIFO
Data
Logic
Control
Data Channel
StateMachine
IPS_CLK
DAT3
DAT2
DAT1
CRC
DAT0
CLK_20M
Inner CLK
Access CLK
IPG_CLK
CLK_DIV
Inner CLK
MMC/SD Bus Clock
MMC_CLK
System Clock Controller
Figure 20-1. MMC/SD Module Block Diagram
Secure Digital Host Controller
Multimedia Card Controller
Transceiver
I/O Memory
Card
DMA
Interface
IPBus
IP
Gasket
IP Bus
Figure 20-2. System Interconnection with MMC/SD Module
MC9328MX1 Reference Manual, Rev. 6.1
20-2
Freescale Semiconductor
MMC/SD Module and Card Information
20.4 MMC/SD Module and Card Information
The following sections provide information about the MMC and SD cards, signal descriptions, module and card
communication, and pin configuration.
20.4.1 MMC and SD Card Pin Assignments and Registers
The MMC and SD cards are 7- or 9-pin cards that operate as external memory storage for the MC9328MX1. The
pin assignment and form factor are shown in Table 20-1.
There are three types of cards:
•
Read-only (ROM) cards—manufactured with fixed data content and used as distribution media, such as
for software, audio, and video.
•
Read/write (RW) cards—typically sold blank and used as mass data storage or end user storage, such as
FLASH, one-time programmable (OTP), or multiple-time programmable (MTP).
•
I/O cards—typically feature an additional interface link and are intended for communication (such as
modems).
Table 20-1. MMC/SD Card Pin Assignment
Form Factor and Pinout
1 2 3 4 5 6 7 8
32 mm
9
SD Card
Pin
Number
MMC Card
1
Reserved
1-Bit Mode
4-Bit Mode
Card Detect
Data Line DAT [3]
2
Command / Response (CMD)
3
Supply Voltage Ground (Vss)
4
Supply Voltage (Vdd)
5
Clock (CLK)
6
Supply Voltage Ground (Vss)
7
Data Line DAT [0]
8
Interrupt (IRQ)
Data Line DAT [1]
or Interrupt (IRQ)
9
ReadWait (RW)
Data Line DAT [2]
or ReadWait (RW)
24 mm
These pins appear
on the SD card only
Each card has a set of information registers that hold the operating parameters and other card conditions and are
described in Table 20-2.
Table 20-2. MMC/SD Card Registers
MMC or SD
Identifier
Register Name
Both
CID
Card Identification Number
Description
Each card has a unique CID.
Size
(Bits)
1281
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-3
MMC/SD Module and Card Information
Table 20-2. MMC/SD Card Registers (continued)
Identifier
Both
RCA
Relative Card Address
Assigned by the MMC/SD module during initialization.
16
Both
DSR
Driver Stage
Configures the card’s output drivers. Usage is optional,
not required.
16
Both
CSD
Card Specific Data
Contains information on the card’s operating
conditions.
Both
OCR
Operation Conditions
Indicates the card’s operating voltage range. Detects
restricted cards and indicates whether power-up is
complete. Usage is optional, not required.
32
Both
CSR
Card Status Register
Contains card’s error and status information. Sent to
the MMC/SD module in response format R1.
32
SD only
SCS
SD Card Status
Contains status information proprietary to the SD card
(such as protection, card type, and bus width).
512
SD only
SCR
SD Configuration Register
Contains additional configuration information only
applicable to the SD card.
64
1.
Register Name
Size
(Bits)
MMC or SD
Description
1281
There can be fewer bits for the SD I/O Card, depending on implementation (see SDIO Card Specification, version
1.0 for more information).
NOTE:
The SD I/O card contains additional registers that are not included in Table 20-2.
20.4.2 Communication
The MMC/SD module and the card communicate via commands, responses, and data bytes, defined as follows:
•
Commands—Commands initiate operations. Commands are transferred serially on the SD_CMD line from
the MMC/SD module to a single card or to all cards. Each command token is preceded by a start bit (0) and
concluded by an end bit (1). The total length of a command is 48 bits, and is protected by CRC bits.
•
Responses—Responses are answers to commands and cannot be initiated. Responses are transferred
serially on the SD_CMD lines from a single addressed card or multiple responses can be sent synchronously
from all cards to the MMC/SD module. The format of each response varies based on the command that
initiated the response. See Section 20.7.8.5, “Response Formats,” for more information.
•
Data—Data is transferred via the SD_DAT line(s) from the card to the MMC/SD module or from the
MMC/SD module to the card. Not all operations include data transfer.
20.4.3 Signal Description
The MMC/SD module uses six I/O pins to communicate with external MMC and SD cards.
•
SD_CMD—Bidirectional command/response signal between the MMC/SD module and the card.
Open-drain for initialization state and push-pull for fast command transfers.
•
SD_CLK—MMC/SD module to card clock signal (output).
MC9328MX1 Reference Manual, Rev. 6.1
20-4
Freescale Semiconductor
Functional Description
•
SD_DAT [3:0]—Four bidirectional data signals. When in push-pull mode, one card or the MMC/SD
module can drive each line at a time.
20.4.4 Pin Configuration for the MMC/SD Module
Section 20.4.3, “Signal Description,” lists the pins used by the MMC/SD module. These pins are multiplexed with
other functions on the device and must be configured for MMC/SD module operation.
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 32.5.1, “Data Direction Registers,” on
page 32-8 for details.
Table 20-3. Pin Configuration
Pin
Setting
Configuration Procedure
SD_CMD
Primary function of GPIO
Port B [13]
1. Clear bit 13 of Port B GPIO in Use Register (GIUS_B)
2. Clear bit 13 of Port B General Purpose Register (GPR_B)
3. Set bit 13 of Port B Pulling Enable Register (PUEN_B)
SD_CLK
Primary function of GPIO
Port B [12]
1. Clear bit 12 of Port B GPIO in Use Register (GIUS_B)
2. Clear bit 12 of Port B General Purpose Register (GPR_B
SD_DAT [3]
Primary function of GPIO
Port B [11]
1. Clear bit 11 of Port B GPIO in Use Register (GIUS_B)
2. Clear bit 11 of Port B General Purpose Register (GPR_B))
SD_DAT [2]
Primary function of GPIO
Port B [10]
1. Clear bit 10 of Port B GPIO in Use Register (GIUS_B)
2. Clear bit 10 of Port B General Purpose Register (GPR_B)
3. Set bit 10 of Port B Pulling Enable Register (PUEN_B)
SD_DAT1:1. Clear bit 9 of Port B GPIO in Use Register (GIUS_B)
SD_DAT [1]
Primary function of GPIO
Port B [9]
1. Clear bit 9 of Port B GPIO in Use Register (GIUS_B)
2. Clear bit 9 of Port B General Purpose Register (GPR_B)
3. Set bit 9 of Port B Pulling Enable Register (PUEN_B)
SD_DAT [0]
Primary function of GPIO
Port B [8]
1. Clear bit 8 of Port B GPIO in Use Register (GIUS_B)
2. Clear bit 8 of Port B General Purpose Register (GPR_B)
3. Set bit 8 of Port B Pulling Enable Register (PUEN_B)
20.5 Functional Description
Figure 20-1 on page 20-2 shows a block diagram of the MMC/SD module. The following sections provide brief
functional descriptions of the major system blocks, including the DMA interface, memory controller (register
handler), logic/command controller, and system clock controller.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-5
Functional Description
20.5.1 DMA Interface
The DMA interface block controls all data routing between the external data bus (DMA access), internal MMC/SD
module data bus, and internal system FIFO access through a dedicated state machine that monitors the status of
FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/SD module (inner system) and
the application (user programming).
DMA Interface
FIFO
Empty/Full
Control
Byte Counter
(0~511)
Host/DMA
R/W Access
Handler
EFB/FFB
Control
RAM_ADDR
RAM_RW
Register
File
RAM
32 x 4-bit
FIFO
Status
Data Path
Multiplexer
R/W from
Application,
R/W from Host,
Handshake
to Host,
Host Status
FSM
RAM_DATA
EFB/FFB for
Application,
EFB/FFB for Host,
MMC_DREQ_B,
DATA_IN,
DATA_OUT
Figure 20-3. DMAC Interface Block Diagram
The DMAC interface block also handles burst requests to the external DMA controller, the internal register
write-error detection, the SD I/O's ReadWait handling, and all IP-related output responses.
20.5.1.1 DMA Burst Request
In the MMC/SD module, there is a 32 × 16-bit FIFO to decrease the latency during the data transfer on the
MMC/SD bus. The FIFO is configured differently for 1-bit and 4-bit access modes. The FIFO is operated as four 8
× 16-bit FIFOs for 1-bit access and as one 32 × 16-bit FIFO for 4-bit access.
Code Example 20-1. DMA Configuration Example
// DMAC init for SDHC channel setup
*(P_U32)DMA_DCR
= 0x0001;
// Enable the DMA (DEN)
*(P_U32)DMA_IMR
= 0x07FF;
// Disable all I/O Channel IRQ
if (direction == 1){
//write
*(P_U32)DMA_SAR1
= Memory_Addr; // Source Address
*(P_U32)DMA_DAR1
= 0x00214038;
// Destination Address
}
else{
//read
*(P_U32)DMA_DAR1
= Memory_Addr; // Destination Address
*(P_U32)DMA_SAR1
= 0x00214038;
// Source Address
}
*(P_U32)DMA_CNTR1
= Size;
// Set No of Byte transfer
*(P_U32)DMA_CCR1
= dir; // Ch1: FIFO as the target, Linear Mem source,
// Mem inc, 16-bit target, 32-bit source,
// Request Enable, DMA Disable
*(P_U32)DMA_RSSR1
= 0x000D;
// Ch1: DMA request select; SDHC is bit[13]
MC9328MX1 Reference Manual, Rev. 6.1
20-6
Freescale Semiconductor
Functional Description
if(SD_4bit_enable)
*(P_U32)DMA_BLR1= 0x0000; // Ch1: No. of FIFO to be read, burst length x32
else
*(P_U32)DMA_BLR1= 0x0010;
// Ch1: No. of FIFO to be read, burst length x8
// Start DMA and Poll end of DMA transfer done
*(P_U32)DMA_ISR = 0x0002;
// Clear DMA ISR for MMC
*(P_U32)DMA_CCR1 = dir_en;
// Ch1: FIFO as the target, Linear Mem source,
// Mem inc, 16-bit target, 32-bit source,
// Request Enable, DMA Enable
while ( ((*(P_U32)DMA_ISR) & 0x2) ==0 );//wait for the data transfer complete
*(P_U32)DMA_ISR = 0x0002;
// Clear DMA ISR for MMC
*(P_U32)DMA_CCR1 = dir;
// Ch1: FIFO as the target, Linear Mem source,
// Mem inc, 16-bit target, 32-bit source,
// Request Enable, DMA Disable
// End of DMA usage
Access via
System
DMA
1-bit FIFO Mode
Byte 0,1
Byte 2,3
Byte 16,17
Byte 14,15
Byte 46,47
Byte 62,63
DAT0
Access via
System
DMA
4-bit FIFO Mode
Byte 0,1
Byte 8,9
Byte 2,3
Byte 56,57
Byte 60,61
Byte 62,63
DAT0
DAT1
DAT2
DAT3
Figure 20-4. FIFO Usage for Different Modes
20.5.1.2 Write-Error Detection
To avoid incorrect register access and provide error indications, the DMA interface monitors the transfer type and
access size of data transactions, generates bus errors, and ignores the current invalid configuration. See Table 20-4
on page 20-12 for the valid register addresses.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-7
Functional Description
20.5.2 Memory Controller (Register Handler)
The memory controller provides SD I/O-IRQ and ReadWait service handling, card detection, command response
handling, and all MMC/SD module interrupt handling. It is the sub-module where the user must place the register
table. Figure 20-5 shows the memory controller block diagram.
DATA from
Post-Processor
Application
Bus
SDIO-IRQ
Interrupter
&
Card Detection
Circuitry
Memory Controller
Configuration
Register
Handler
Interrupt
Handler
Data
IRQ_B
SDIO-ReadWait
Logic
IPS_CLK
Operation
Pause
Operation
Resume
Command
Response
Circuitry
CMD from
Post-Processor
Figure 20-5. Memory Controller Block Diagram
20.5.2.1 SD I/O—IRQ and ReadWait Service Handling
There is a 1-bit or 4-bit interrupt response from the SD I/O peripheral card. In 1-bit mode, the interrupt response is
simply that the SD_DAT [1] line is held low and is not used as data. The memory controller use SD_CLK to
sample the status of SD_DAT[1] and generates and interrupt according to this low and the system interrupt
continues until the source is removed (SD_DAT [1] returns to a high level).
Because pin 8 of the SD card is shared by the IRQ and SD_DAT [1] lines in 4-bit SD mode, an interrupt is sent by
the card and recognized by the MMC/SD module only during a specific time. This is known as the interrupt period.
The controller must sample SD_DAT [1] during this period to determine the IRQ status of the attached card. The
interrupt period happens only at the boundary of each block (512 bytes).
ReadWait is another feature in SD I/O. It allows the user to submit command(s) during the data transfer. In
ReadWait mode, the block temporarily pauses the data transfer operation counter and related status, however it
keeps the clock running and allows the user to submit command(s) normally. After all commands are submitted,
the user can switch back to the data transfer operation and all counter and status values are resumed as access
continues. The feature is only available with a ReadWait enabled SDIO device.
20.5.2.2 Card Detection
The SD_DAT [3] pin detects card presence and is pulled low by default. When there is no card on the MMC/SD
bus, SD_DAT [3] shows a low voltage level. When any card is inserted on the bus, the card’s SD_DAT [3] pin
pulls the bus line high to trigger the memory controller block’s detection circuit and interrupt the processor to
indicate that a card is inserted. The detection circuitry is sampled by the MC9328MX1 system clock (HCLK),
therefore card detection is still valid even if the MMC/SD module is not enabled. Similarly, card removal also
MC9328MX1 Reference Manual, Rev. 6.1
20-8
Freescale Semiconductor
Functional Description
generates an interrupt. Because the mechanism is based on the value of the SD_DAT [3] line, only single-card
systems benefit from card detection. After the card is detected, the user must mask the card detection interrupt to
avoid misleading interrupt generation during card access as the SD_DAT lines change.
CMD3
MMC/SD
Detector
To System IRQ_B
Figure 20-6. Card Detection Mechanism
20.5.2.3 MMC/SD Module Interrupt Handling
Interrupts generated from the MMC/SD module originate from errors or are status indicators. The MMC/SD
module checks response and data CRCs and the internal watchdog timer. An error is generated when any of those
checks fail. Status indicators include response done, transfer done, and FIFO status. Interrupt masking and
generation is handled in the interrupt handler block.
20.5.3 Logic and Command Interpreters
The two interpreters are built similarly and consist of 3 parts: inner state machine, sub-module controller, and CRC
accelerator.
The command controller handles all interrupts related to the command line (SD_CMD) including command data
sequence generation, command response extraction, CRC generation and checking, and response time-out. A state
machine, logic controller, and CRC accelerator control these functions.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-9
Functional Description
Command Interpreter
CRC_IN
CMD
DFF
CRC_REG
CMD_REG
RESP_FIFO
CMD_SR
CMD_CFG
DAT_CFG
DAT_FIFO
DAT_REG
DAT_SR
CRC_REG
CRC_IN
CMD
Port
CMD
FSM for CMD
Packet Route
&
Content Extraction
READWAIT_CFG
CMD
Sampler
Logic Interpreter
IRQ
Extractor
FSM for DAT
DAT
Sampler
DAT
DFF
DAT
Port
DAT[0:3]
IRQ_CFG
Figure 20-7. Block Diagram for Logic and Command Interpreters
The CRC Generation and Detection Block is one of the primary hardware functions in the module. To minimize
the gate count, the internal command shift register is also used for the CRC shift register (see Figure 20-8 on
page 20-11). The polynomials for CRC generation are:
For SD_CMD:
Generator polynomial: G(x) = x7 + x3 + 1
M(x) = (first bit) • xn + (second bit) • xn-1 + … + (last bit) • x0
CRC [6:0] = Remainder [(M(x) • x7) / G(x)]
Eqn. 20-1
Generator polynomial: G(x) = x16 + x12 + x5 + 1
M(x) = (first bit) • xn + (second bit) • xn-1 + … + (last bit) • x0
CRC [15:0] = Remainder [(M(x) • x16) / G(x)]
Eqn. 20-2
For SD_DAT:
MC9328MX1 Reference Manual, Rev. 6.1
20-10
Freescale Semiconductor
Functional Description
CLR_CRC
ZERO
CRC IN
CRC
BUS[0]
CRC
BUS[1]
CRC
BUS[2]
CRC
BUS[3]
CRC
BUS[4]
CRC
BUS[5]
CRC
BUS[6]
CRC OUT
Figure 20-8. Command CRC Shift Register (SD_DAT Has a Similar Structure)
20.5.4 System Clock Controller
To maximize the power-saving capability of the MMC/SD module, two clock stages are used within. The input
clock, PERCLK2, runs at a frequency between 20–100 MHz and passes through a prescaler to adjust and maintain
the inner clock to under 20 MHz, the maximum operating frequency of the MMC/SD cards. The output of this
prescaler is called CLK_20M. Only about 10% of the total circuit runs on this clock.
CLK_20M feeds into a user-programmable clock divider. The resulting clock is called CLK_DIV and it runs at a
frequency between 0–20 MHz. This clock runs most of the circuitry in the module.
The prescaler and divider ratios are set in the MMC/SD Clock Rate Register (CLK_RATE).
The clocks are paused while they are not used, such as when the FIFO is full during the card read operation or
when there are no further read operations to the FIFO.
IPG_CLK
Inner
Bus Clock Divider
Prescaler
IPS_CLK
DMA
Handler
Register
Table
Memory
Controller
FIFO
CMD
Interrupter
DAT
Interrupter
CLK_20M
CLK_DIV
Transceiver
Figure 20-9. Clock Tree for the MMC/SD Module
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-11
Programming Model
The system clock controller sets the rate of the MMC/SD module main clock and checks whether it is on or off.
The clock is turned off by setting the STOP_CLK bit in the MMC/SD Clock Control Register (STR_STP_CLK)
and is turned on by setting the START_CLK bit. To change the clock rate, the application writes new prescaler and
divider values in the CLK_RATE register.
CLK_ON
CLK_OFF
START_CLK
STOP_CLK
From DAT
Clock
Control
Signal
Synchronizer
External
CLK
Control
Inner
CLK
Control
FSM
CLK_DIV
CLK_EN
DFF
From MEM
Gate
CLK_RATE
CLK_20M
Prescaler
System
Clock
CLK
Prescaler
SDHC_CLK
CLK_DIV
Counter
Figure 20-10. System Clock Control Unit
The clock controller also ensures that every clock stop occurs when all clocks are low so the clock division and
enable/disable occur without generating a glitch in the process. The stop clock data unit enables the data state
machine to stop the clock when the application is too slow and does not update the FIFO on time in a multiple
block/stream write or read.
20.5.4.1 Card Clock Control
The MMC/SD host controller controls the clocking for the MMC/SD cards. The MMC/SD module can lower the
clock frequency or even turn off the clock to the cards to save energy. The MMC/SD module provides at least 8
clock cycles after the last MMC/SD bus transaction (command, response, data, CRC) before shutting off the clock.
20.6 Programming Model
The MMC/SD Host Controller module includes fifteen 32-bit registers that the application configures before every
operation on the multimedia bus. Table 20-4 summarizes these registers and their addresses.
Table 20-4. Multimedia Controller Register Memory Map
Description
Name
Address
MMC/SD Clock Control Register
STR_STP_CLK
0x00214000
MMC/SD Status Register
STATUS
0x00214004
MC9328MX1 Reference Manual, Rev. 6.1
20-12
Freescale Semiconductor
Programming Model
Table 20-4. Multimedia Controller Register Memory Map (continued)
Description
Name
Address
MMC/SD Clock Rate Register
CLK_RATE
0x00214008
MMC/SD Command and Data Control Register
CMD_DAT_CONT
0x0021400C
MMC/SD Response Time-Out Register
RES_TO
0x00214010
MMC/SD Read Time-Out Register
READ_TO
0x00214014
MMC/SD Block Length Register
BLK_LEN
0x00214018
MMC/SD Number of Blocks Register
NOB
0x0021401C
MMC/SD Revision Number Register
REV_NO
0x00214020
MMC/SD Interrupt Mask Register
INT_MASK
0x00214024
MMC/SD Command Number Register
CMD
0x00214028
MMC/SD Higher Argument Register
ARGH
0x0021402C
MMC/SD Lower Argument Register
ARGL
0x00214030
MMC/SD Response FIFO Register
RES_FIFO
0x00214034
MMC/SD Buffer Access Register
BUFFER_ACCESS
0x00214038
20.6.1 MMC/SD Clock Control Register
The MMC/SD Clock Control Register allows the user to reset the system, enable the MMC/SD module, and
control the MMC/SD module clock.
NOTE:
To perform a system soft-reset and an MMC/SD module enable, the user must
program the MMC/SD Clock Control Register with a particular sequence of
values. The programmer must first write the value 0x0008, then 0x000D, and then
write 0x0005 eight times.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-13
Programming Model
STR_STP_CLK
Addr
0x00214000
MMC/SD Clock Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
3
2
1
0
MMCSD
_RESET
MMCSD_
ENABLE
START
_CLK
STOP
_CLK
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
6
5
ENDIAN
TYPE
r
r
r
r
r
r
r
r
r
r
rw
r
w
rw
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 20-5. MMC/SD Clock Control Register Description
Name
Description
Settings
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
ENDIAN
Bit 5
ENDIAN FIFO Mode Selection—Setting this bit selects the Endian
mode of the FIFO.
Reserved
Bit 4
Reserved—This bit is reserved and should read 0.
MMCSD_RESET
Bit 3
MMCSD Reset—Resets the MMC/SD module.
0 = No effect
1 = Reset the MMC/SD module
MMCSD_ENABLE
Bit 2
MMC/SD Enable—Enables/Disables the MMC/SD module. When
the module is disabled, the clock source and all internal operations
are halted.
0 = Disable MMC/SD module
1 = Enable MMC/SD module
START_CLK
Bit 1
Start Clock—Starts the MMC/SD module clock. The
MMCSD_ENABLE bit must be set for START_CLK to have any
meaning. When START_CLK is changed while the MMC/SD
module is in a transmission period, the status of the operation
determines when the clock is started. Otherwise, the clock begins
immediately. Setting a value of 11 on Bits 1:0 is prohibited.
0 = MMC/SD clock inactive
1 = MMC/SD clock active
0 = Little endian
1 = Big endian
Note: A transmission period is defined as the time from a card
data-access-related command is submitted to the end of the data
access operation.
MC9328MX1 Reference Manual, Rev. 6.1
20-14
Freescale Semiconductor
Programming Model
Table 20-5. MMC/SD Clock Control Register Description (continued)
Name
Description
STOP_CLK
Bit 0
Settings
Stop Clock—Stops the MMC/SD clock. The MMCSD_ENABLE bit
must be set for STOP_CLK to have any meaning. When
STOP_CLK is changed while the MMC/SD module is in a
transmission period, the status of the operation determines when
the clock is stopped. Otherwise, the clock halts immediately.
Setting a value of 11 on Bits 1:0 is prohibited.
0 = MMC/SD clock active
1 = MMC/SD clock stopped
Note: A transmission period is defined as the time from a card
data-access-related command is submitted to the end of the data
access operation.
20.6.2 MMC/SD Status Register
The read-only MMC/SD Status Register provides the programmer with information about the status of MMC/SD
module operations, application FIFO status, and error conditions.
STATUS
Addr
0x00214004
MMC/SD Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
CARD
CARD SDIO_ END_ WRITE DATA_ WR_CRC
APPL APPL RESP
_BUS
_PREINT_
CMD_ _OP_ TRANS_ _ERROR
_BUFF _BUFF _CRC
_CLK
SENCE ACTIVE RESP DONE
DONE
_CODE
_FF
_FE _ERR
_RUN
TYPE
CRC_ CRC_
TIME
TIME
READ WRITE _OUT _OUT
_ERR _ERR _RESP _READ
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 20-6. MMC/SD Status Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
CARD_PRESENCE
Bit 15
Card Presence—Detects whether an MMC/SD card is
present based on SD_DAT [3].
0 = No cards are present
1 = At least 1 card is present
SDIO_INT_ACTIVE
Bit 14
SD I/O Interrupt Active—Indicates whether an interrupt is
detected at the SD I/O card. A separate acknowledge
command to the card is required to clear this interrupt.
0 = No interrupt detected
1 = Interrupt detected via SDIO
card bus
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-15
Programming Model
Table 20-6. MMC/SD Status Register Description (continued)
Name
Description
Settings
END_CMD_RESP
Bit 13
End Command Response—Indicates that the command
was successfully transmitted to the card. A response
package is expected after each successful command
operation. END_CMD_RESP is clear when the clock is
stopped.
0 = Command not successful,
incomplete, or not
applicable (no response)
1 = Command transmitted
successfully (response
received)
WRITE_OP_DONE
Bit 12
Write Operation Done—Indicates when an access
operation is complete. The flash card needs extra idle time
to write and it requires the MMC/SD module to wait until the
card writes the buffered data to the inner flash memory. The
MMC/SD module automatically detects the status.
WRITE_OP_DONE determines the end of the write
operation.
0 = Write operation in progress
or incomplete
1 = Write operation complete
DATA_TRANS_DONE
Bit 11
Data Transfer Done—Indicates that a data transfer is
complete. DATA_TRANS_DONE determines the end of the
read operation.
0 = Data transfer in progress or
incomplete
1 = Data transfer complete
WR_CRC_ERROR_CODE
Bits 10–9
Write CRC Error Code—Specifies whether there was a
CRC error, and if so, what kind. The error code is valid only
when a CRC error has occurred (Bit 5, RESP_CRC_ERR, is
set).
00 = No transmission error,
CRC status is 010
(positive)
01 = Transmission error, CRC
status is 110 (negative)
10 = No CRC response
11 = Reserved
CARD_BUS_CLK_RUN
Bit 8
MMC/SD Card Clock Running—Indicates whether the
clock is running. The clock rate setting and system
configuration can be modified when the clock is turned off
by setting the STOP_CLK bit of the STR_STP_CLK
register.
0 = MMC/SD clock is not
running
1 = MMC/SD clock is running
APPL_BUFF_FF
Bit 7
Application Buffer FIFO Full—Indicates the status of the
32 x 16-bit inner data FIFO. Usually used in the card read
operation.
0 = Buffer is not full
1 = Buffer is full
APPL_BUFF_FE
Bit 6
Application Buffer FIFO Empty—Indicates the status of
the 32 x 16-bit inner data FIFO. Usually used in the card
write operation.
0 = Buffer is not empty
1 = Buffer is empty
RESP_CRC_ERR
Bit 5
Response CRC Error—Indicates that a transmission error
occurred on the SD_CMD line during the command and
response transfer. This type of error usually results from the
electrical environment.
0 = No error
1 = Response CRC error
occurred
Note: RESP_CRC_ERR is cleared only by an internal
status change or by removing the source of the error.
Reserved
Bit 4
Reserved—This bit is reserved and should read 0.
MC9328MX1 Reference Manual, Rev. 6.1
20-16
Freescale Semiconductor
Programming Model
Table 20-6. MMC/SD Status Register Description (continued)
Name
CRC_READ_ERR
Bit 3
Description
CRC Read Error—Indicates that a transmission error
occurred on the SD_DAT line during a card read. The user
should re-try the transmission.
Settings
0 = No error
1 = CRC read error occurred
Note: CRC_READ_ERR is cleared only by an internal
status change or by removing the source of the error.
CRC_WRITE_ERR
Bit 2
CRC Write Error—Indicates that a transmission error
occurred on the SD_DAT line during a card write. See the
WR_CRC_ERROR_CODE field for more information.
0 = No error
1 = CRC write error occurred
Note: CRC_WRITE_ERR is cleared only by an internal
status change or by removing the source of the error.
TIME_OUT_RESP
Bit 1
Time-Out Response Error—Indicates that a command
response is not received in the time specified in the
RES_TO register. This can be caused by:
• An unsupported command received at the card(s)
• Another MMC/SD_OP_COND command submitted after
all cards have sent their voltage ranges and the power-up
routine is finished
• An identification command issued when all cards are
already in standby state
• No card is on the bus
0 = No error
1 = Time-out response error
occurred
Note: TIME_OUT_RESP is cleared only by an internal
status change or by removing the source of the error.
TIME_OUT_READ
Bit 0
Time-Out Read Data Error—Indicates that the expected
data from the card is not received in the time specified in the
READ_TO register. TIME_OUT_READ is cleared only by an
internal status change or by removing the source of the
error.
0 = No error
1 = Time-out read data error
occurred
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-17
Programming Model
20.6.3 MMC/SD Clock Rate Register
The MMC/SD Clock Rate Register defines the clock divider values for CLK_20M and CLK_DIV. These two
signals are used to clock the MMC/SD module. See Section 20.5.4, “System Clock Controller,” for more
information on clock schemes.
NOTE:
The user can write to the MMC/SD Clock Rate Register only when the bus clock
is stopped. Check the CARD_BUS_CLK_RUN bit of the STATUS register to
determine the state of the bus clock.
CLK_RATE
Addr
0x00214008
MMC/SD Clock Rate Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
PRESCALER
TYPE
CLK RATE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
RESET
0x0036
Table 20-7. MMC/SD Clock Rate Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
PRESCALER
Bits 5–3
Prescaler Divider—Specifies the divider value to generate
CLK_20M. PERCLK2 feeds into the MMC/SD module from the clock
controller.
Settings
000 = CLK_20M is PERCLK2
001 = CLK_20M is PERCLK2 ÷ 2
010 = CLK_20M is PERCLK2 ÷ 3
(recommended)
011 = CLK_20M is PERCLK2 ÷ 3
100 = CLK_20M is PERCLK2 ÷ 4
101 = CLK_20M is PERCLK2 ÷ 5
(recommended)
110 = CLK_20M is PERCLK2 ÷ 5
111 = CLK_20M is PERCLK2 ÷ 5
MC9328MX1 Reference Manual, Rev. 6.1
20-18
Freescale Semiconductor
Programming Model
Table 20-7. MMC/SD Clock Rate Register Description (continued)
Name
Description
CLK RATE
Bits 2–0
Settings
Inner Bus Clock Divider—Specifies the divider value to generate
CLK_DIV. The CLK_20M signal feeds into the inner bus clock
divider from the prescaler.
000 = CLK_DIV is CLK_20M
001 = CLK_DIV is CLK_20M ÷ 2
010 = CLK_DIV is CLK_20M ÷ 4
011 = CLK_DIV is CLK_20M ÷ 8
100 = CLK_DIV is CLK_20M ÷ 16
101 = CLK_DIV is CLK_20M ÷ 32
110 = CLK_DIV is CLK_20M ÷ 64
111 = CLK_DIV is CLK_20M ÷ 128
20.6.4 MMC/SD Command and Data Control Register
The MMC/SD Command and Data Control Register allows the user to specify the format of data and response, and
to control the ReadWait cycle.
CMD_DAT_CONT
BIT
31
30 29
TYPE
r
r
0
0
MMC/SD Command and Data Control
Register
Addr
0x0021400C
28
27
26
25
24
23
22
21
20
19
18 17
16
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
INIT
BUSY
STREAM
_BLOCK
WRITE
_READ
DATA_
ENABLE
RESET
0x0000
BIT
15
TYPE
14 13
12
11
10
CMD_
RESP_
LONG_
OFF
STOP_
READ
WAIT
START_
READ
WAIT
9
8
BUS_
WIDTH
FORMAT_
OF_
RESPONSE
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 20-8. MMC/SD Command and Data Control Register Description
Name
Description
Settings
Reserved
Bits 31–13
Reserved—These bits are reserved and should read 0.
CMD_RESP_LONG_OFF
Bit 12
Command Response Long Off—Allows bit clearance when
status is read. used in ReadWait cycle.
0 = Bit not cleared when read
1 = Allows bit clearance
STOP_READWAIT
Bit 11
Stop ReadWait—Ends the ReadWait cycle.
0 = No effect
1 = Ends cycle
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-19
Programming Model
Table 20-8. MMC/SD Command and Data Control Register Description (continued)
Name
Description
Settings
START_READWAIT
Bit 10
Start ReadWait—Starts the ReadWait cycle.
0 = No effect
1 = Starts cycle
BUS_WIDTH
Bits 9–8
Bus Width—Specifies the width of the data bus.
00 = 1-bit
01 = Reserved
10 = 4-bit
11 = Reserved
INIT
Bit 7
Initialize—Specifies whether the optional 80 clock cycle prefix
(to initialize the card) will occur before every command. INIT
enables/disables the 80 clock initialization time.
0 = Disable 80 clocks
1 = Enable 80 clocks
BUSY
Bit 6
Busy Signal—Specifies whether a busy signal is expected
after the current command. A busy signal occurs when the
SD_DAT line is pulled low while there are no free data receive
buffers. Only SEND_STATUS (CMD13) and
SELECT/DESELECT_CARD (CMD7) are used during busy. A
busy signal is expected after the stop transmission, card
select, erase, and program CID commands. Normally used in
write-related operations.
0 = No busy signal expected
1 = Busy signal expected after
current command
STREAM_BLOCK
Bit 5
Stream or Block—Specifies whether the data transfer of the
current command is in stream or block mode.
0 = Block mode
1 = Stream mode
WRITE_READ
Bit 4
Write or Read—Specifies whether the data transfer of the
current command is a write or read operation.
0 = Read
1 = Write
DATA_ENABLE
Bit 3
Data Transfer—Specifies whether the current command
includes a data transfer.
0 = No data transfer included
1 = Data transfer included
FORMAT_OF
_RESPONSE
Bits 2–0
Format of Response—Sets the response format. See
Section 20.7.8.5, “Response Formats.”
000 = No response
001 = Format R1
010 = Format R2
011 = Format R3
100 = Format R4
101 = Format R5
110 = Format R6
MC9328MX1 Reference Manual, Rev. 6.1
20-20
Freescale Semiconductor
Programming Model
20.6.5 MMC/SD Response Time-Out Register
The MMC/SD Response Time-Out Register defines the time-out error for a received response.
RES_TO
Addr
0x00214010
MMC/SD Response Time-Out Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
RESPONSE TIME OUT
TYPE
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
RESET
0x0040
Table 20-9. MMC/SD Response Time-Out Register Description
Name
Description
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
RESPONSE TIME OUT
Bits 7–0
Response Time-Out—Specifies the number of clock counts
between the command and when the MMC/SD module turns on the
time-out error for the received response.
Settings
0x01 = 1 clock counts
...
0xFF = 255 clock counts
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-21
Programming Model
20.6.6 MMC/SD Read Time-Out Register
The MMC/SD Read Time-Out Register defines the time-out error for received data.
READ_TO
Addr
0x00214014
MMC/SD Read Time-Out Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DATA READ TIME OUT
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
0xFFFF
Table 20-10. MMC/SD Read Time-Out Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
DATA READ TIME OUT
Bits 15–0
Received Data Time-Out—Specifies the number of clocks between the command and
when the MMC/SD module turns on the time-out error for the received data. The unit is
CLK_20M ÷ 256. A value of 0x2DB4 is recommended.
MC9328MX1 Reference Manual, Rev. 6.1
20-22
Freescale Semiconductor
Programming Model
20.6.7 MMC/SD Block Length Register
The MMC/SD Block Length Register defines how many bytes are in a block.
BLK_LEN
Addr
0x00214018
MMC/SD Block Length Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
BLOCK LENGTH
TYPE
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 20-11. MMC/SD Block Length Register Description
Name
Description
Reserved
Bits 31–10
Reserved—These bits are reserved and should read 0.
BLOCK LENGTH
Bits 9–0
Block Length—Specifies the number of bytes in a block, and is
normally set to 0x200 for MMC/SD module data transactions. The
value is specified in the card’s CSD
Note: This version of Host Controller only supports fixed block
lengths of 0x200.
Settings
0x000 = 0 byte
0x001 = 1 byte
...
0x3FF = 1023 bytes
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-23
Programming Model
20.6.8 MMC/SD Number of Blocks Register
The MMC/SD Number of Blocks Register defines the number of blocks in a data transfer.
NOB
Addr
0x0021401C
MMC/SD Number of Blocks Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
NOB
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 20-12. MMC/SD Number of Blocks Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
NOB
Bits 15–0
Block Length—Specifies the number of blocks in a data transfer. One
block is a possibility.
Settings
0x0000 = 0 block
0x0001 = 1 block
...
0xFFFF = 65535 blocks
MC9328MX1 Reference Manual, Rev. 6.1
20-24
Freescale Semiconductor
Programming Model
20.6.9 MMC/SD Revision Number Register
The read-only MMC/SD Revision Number Register is a read-only register that displays the revision number of the
module.
REV_NO
Addr
0x00214020
MMC/SD Revision Number Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
REVISION NUMBER
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
RESET
0x0390
Table 20-13. MMC/SD Revision Number Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
REVISION NUMBER
Bits 15–0
Module Revision Number—Specifies the revision number of the
MMC/SD module.
Settings
Fixed at 0x0390
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-25
Programming Model
20.6.10 MMC/SD Interrupt Mask Register
When certain conditions exist in the module, the MMC/SD module has the ability to set an interrupt. The
MMC/SD Interrupt Mask Register allows the user to control whether these interrupts occur.
Rewriting this register clears the interrupt MMC_IRQ. When the interrupt source is from the SD I/O, the MMC/SD
module continues to interrupt the system. In this case, the user must write to the internal registers on the SD I/O
card. This is the only way to acknowledge the interrupt. In the interrupt service routine the status indicators should
be polled.
INT_MASK
Addr
0x00214024
MMC/SD Interrupt Mask Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
AUTO_
CARD_
DETECT
DAT0
_EN
SDIO
BUF_
READY
END_
CMD_
RES
WRITE
_OP_
DONE
DATA_
TRAN
RESET
0x0000
BIT
15
TYPE
14
13
12
11
10
9
8
7
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 20-14. MMC/SD Interrupt Mask Register Description
Name
Description
Settings
Reserved
Bits 31–7
Reserved—These bits are reserved and should read 0.
AUTO_CARD_DETECT
Bit 6
Auto Card Detect (SD card only)—Masks the auto card
detect interrupt. Card insertion results in the SD_DAT [3:0]
pins changing from 0111 to 1111, and card removal results in
the pins changing from 1111 to 0111. After the card is
detected, the user program must mask
AUTO_CARD_DETECT to avoid misleading interrupt
generation while the SD_DAT lines change during card
access.
0 = Not masked
1 = Masked
DAT0_EN
Bit 5
SD_DAT0 Enable—Identifies how the SD I/O interrupt is
detected. An interrupt is determined by SD_DAT [1] = 0,
however this bit is an optional setting for the SDIO bit.
0 = SD I/O’s Interrupt detection
based on:
SD_DAT [3:1] = 110
1 = SD I/O’s Interrupt detection
based on:
SD_DAT [3:0] = 1101
SDIO
Bit 4
MMC/SD I/O—Masks the interrupt from the SD I/O card to
the MMC/SD module I/O interrupt mask.
0 = Not masked
1 = Masked
MC9328MX1 Reference Manual, Rev. 6.1
20-26
Freescale Semiconductor
Programming Model
Table 20-14. MMC/SD Interrupt Mask Register Description (continued)
Name
Description
Settings
BUF_READY
Bit 3
Buffer Ready—Masks the Application buffer FIFO ready (full
or empty) interrupt.
0 = Not masked
1 = Masked
END_CMD_RES
Bit 2
End Command Response—Masks the end command
response interrupt.
0 = Not masked
1 = Masked
WRITE_OP_DONE
Bit 1
Write Operation Done—Masks the write operation done
interrupt.
0 = Not masked
1 = Masked
DATA_TRAN
Bit 0
Data Transfer Done—Masks the data transfer done
interrupt.
0 = Not masked
1 = Masked
Table 20-15 summarizes the interrupt mechanisms used in the MMC/SD module.
Table 20-15. Interrupt Mechanisms
Int #
STATUS
Register Source
Bit Name (Number)
1
Interrupt/
Status Clear
Method
Generate
Interrupt?
INT_MASK Register
Bit Name (Number)
TIME_OUT_READ (0)
No, alert via the
DATA_TRANS_DONE
bit in the MMC/SD
Status Register
DATA_TRAN (0)
Clear status by setting
STOP_CLK in
STR_STP_CLK
2
TIME_OUT_RESP (1)
No, alert via the
END_CMD_RESP
bit in the MMC/SD
Status Register
END_CMD_RES (2)
Clear status by setting
STOP_CLK in
STR_STP_CLK
3
CRC_WRITE_ERR (2)
No, alert via the
DATA_TRANS_DONE
bit in the MMC/SD
Status Register
DATA_TRAN (0)
Clear status by setting
STOP_CLK in
STR_STP_CLK
4
CRC_READ_ERR (3)
No, alert via the
DATA_TRANS_DONE
bit in the MMC/SD
Status Register
DATA_TRAN (0)
Clear status by setting
STOP_CLK in
STR_STP_CLK
5
RESP_CRC_ERR (5)
No, alert via the
END_CMD_RESP
bit in the MMC/SD
Status Register
END_CMD_RES (2)
Clear status by setting
STOP_CLK in
STR_STP_CLK
6
APPL_BUFF_FE (6)
Yes
BUF_READY (3)
Clear interrupt by writing
to INT_MASK bit
Clear status by writing to
BUFFER_ACCESS
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-27
Programming Model
Table 20-15. Interrupt Mechanisms (continued)
Int #
STATUS
Register Source
Bit Name (Number)
Generate
Interrupt?
INT_MASK Register
Bit Name (Number)
7
APPL_BUFF_FF (7)
Yes
BUF_READY (3)
Clear interrupt by writing
to INT_MASK bit
Clear status by reading
BUFFER_ACCESS
8
DATA_TRANS_DONE (11)
Yes
DATA_TRAN (0)
Clear interrupt by writing
to INT_MASK bit
Clear status by setting
STOP_CLK in
STR_STP_CLK
9
WRITE_OP_DONE (12)
Yes
WRITE_OP_DONE (1)
Clear interrupt by writing
to INT_MASK bit
Clear status by setting
STOP_CLK in
STR_STP_CLK
10
END_CMD_RESP (13)
Yes
END_CMD_RES (2)
Clear interrupt by writing
to INT_MASK bit
Clear status by setting
STOP_CLK in
STR_STP_CLK
11
SDIO_INT_ACTIVE (14)
Yes
SDIO (4)
Clear interrupt by writing
to INT_MASK bit;
Clear status by resolving
interrupt source on SD I/O
card (requires separate
acknowledge command
to SD I/O card)
12
CARD_PRESENCE (15)
Yes
AUTO_CARD_DETECT
(6)
Clear interrupt by writing
to INT_MASK bit
Clear status by removing
card (this is a status
indicator, not an error)
Interrupt/
Status Clear
Method
20.6.11 Commands and Arguments
The MMC/SD module communicates with the MMC/SD card(s) by sending commands and arguments. The
command to send is set in the MMC/SD Command Number Register (CMD), and the argument is defined in two
registers, the MMC/SD Higher Argument Register (ARGH) and the MMC/SD Lower Argument Register (ARGL).
The full list of commands is shown in Table 20-25 on page 20-58.
MC9328MX1 Reference Manual, Rev. 6.1
20-28
Freescale Semiconductor
Programming Model
20.6.11.1 MMC/SD Command Number Register
CMD
Addr
0x00214028
MMC/SD Command Number Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
COMMAND NUMBER
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 20-16. MMC/SD Command Number Register Description
Name
Description
Settings
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
COMMAND NUMBER
Bits 5–0
Command Number—Specifies the command number to be
executed.
0x00 = CMD0
0x01 = CMD1
...
0x3F = CMD63
20.6.11.2 MMC/SD Higher Argument Register
ARGH
Addr
0x0021402C
MMC/SD Higher Argument Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
ARGUMENT HIGH
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-29
Programming Model
Table 20-17. MMC/SD Higher Argument Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
ARGUMENT HIGH
Bits 15–0
Higher Argument—Specifies the higher word of the argument for the current command.
20.6.11.3 MMC/SD Lower Argument Register
ARGL
Addr
0x00214030
MMC/SD Lower Argument Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
ARGUMENT LOW
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 20-18. MMC/SD Lower Argument Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
ARGUMENT LOW
Bits 15–0
Lower Argument—Specifies the lower word of the argument for the current command.
MC9328MX1 Reference Manual, Rev. 6.1
20-30
Freescale Semiconductor
Programming Model
20.6.12 MMC/SD Response FIFO Register
The read-only MMC/SD Response FIFO Register holds the response sent back to the MMC/SD module after every
command. The size of this FIFO is 8 × 32-bits, however only bits 15-0 are valid data.
NOTE:
The MMC/SD module does not copy the last 8 bits of CID/CSD into this FIFO,
which is its CRC and stop bit, because the incoming CRC is automatically
validated by the module CRC check mechanism during receive.
RES_FIFO
Addr
0x00214034
MMC/SD Response FIFO Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
RESPONSE CONTENT
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 20-19. MMC/SD Response FIFO Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
RESPONSE CONTENT
Bits 15–0
Response Content—Contains the responses to every command that is sent by the
MMC/SD module. This size of this FIFO register is 8x16-bit.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-31
Functional Example for the MMC/SD Module
20.6.13 MMC/SD Buffer Access Register
The MMC/SD Buffer Access Register contains the data transmitted to or received from the card during data access
operations.
BUFFER_ACCESS
Addr
0x00214038
MMC/SD Buffer Access Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
FIFO CONTENT
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 20-20. MMC/SD Buffer Access Register Description
Name
Description
Settings
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
FIFO CONTENT
Bits 15–0
FIFO Content—Holds transfer or receive data between system memory and card memory.
The size of the FIFO buffer is 8 x16-bit in 1-bit mode, and 32 x16-bit in 4-bit mode. FIFO Full or
Empty active MMC_IRQ and MMC_DREQ. Only a completed FIFO read or write can clear the
MMC_DREQ request.
20.7 Functional Example for the MMC/SD Module
All communication between the MMC/SD module and the cards is controlled by the MMC/SD module. The
MMC/SD module sends commands of two types: broadcast and addressed (point-to-point) commands.
Broadcast commands are intended for all cards. These include commands such as GO_IDLE_STATE (CMD0),
SEND_OP_COND (CMD1), ALL_SEND_CID (CMD2), and SET_RELATIVE_ADDR (CMD3), that are broadcast out
to all cards to go to a common condition. With broadcast-type commands, all cards are in open-drain mode to avoid
bus contention.
After the broadcast command SET_RELATIVE_ADDR is issued, cards enter standby state, and only addressed
commands are used. In this state, the pins SD_CMD and SD_DAT [3:0] operate in push-pull mode for maximum
drive at maximum operation frequency.
Addressed commands are sent to the card selected by SELECT/DESELECT_CARD (CMD7) and require a response
from that card.
MC9328MX1 Reference Manual, Rev. 6.1
20-32
Freescale Semiconductor
Functional Example for the MMC/SD Module
The MMC and the SD are similar products and with the exception of the 4x bandwidth and the built-in encryption,
they are programmed similarly. The following sections illustrate how to initialize, access, and protect the cards.
20.7.1 Basic Operation
Code Example 20-2 on page 20-33 is the program flow used to submit a command to the card(s), <command_no> is
the targeted command, <argh_no,argl_no> are the corresponding arguments, <cmd_dat_cont> is the command
configuration required, and <int_mask_value> is the interrupt mask in the user program.
Code Example 20-2. Send_Cmd_Wait_Resp
send_cmd_wait_resp(command_no, argh_no, argl_no, cmd_dat_cont, int_mask_value)
{
write_reg(COMMAND, <command_no>);
write_reg(ARGH, <argh_no>);
write_reg(ARGL, <argl_no>);
write_reg(CMD_DAT_CONT, <cmd_dat_cont>);
write_reg(STR_STP_CLK, 0x6);
read_reg(STATUS);
while(!STATUS[8]) Read_reg(STATUS);
l// Wait until clock is started
//
to submit commands
while(irq_status);
// Wait interrupt generated
//
(End Command Response)
Write_reg(INT_MASK, <int_mask_value>);
read_reg(STATUS);
// Check whether interrupt is an
//
End Command Response or a Time
//
out.
write_reg(STR_STP_CLK, 0x5);
read_reg(STATUS);
while(STATUS[8]) Read_reg(STATUS);
// Wait until clock is stopped;
//
command - response end.
}
20.7.2 Card Identification State
All data communication during the card identification state uses the command line (SD_CMD) only.
While in card identification state, the MMC/SD module performs the following steps:
1. Detects the cards
2. Resets all cards that are in the card identification state
3. Validates operation voltage range
4. Identifies the cards
5. Asks each card (separately, on its own SD_CMD line) to publish its relative card address (RCA)
20.7.2.1 Card Detect
The Code Example 20-3 demonstrates how to detect a card via the MMC/SD module.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-33
Functional Example for the MMC/SD Module
Code Example 20-3. Card_Detect
card_detect()
{
while(irq_status);
// Wait interrupt generated (Card
//
Presence)
while(!STATUS[15]) Read_reg(STATUS); // Wait until card is detected
Write_reg(INT_MASK, 0x40);
}
20.7.2.2 Reset
There are three types of reset available for the MMC/SD module:
•
Hardware reset—Resets both the card(s) and the MMC/SD module, driven by power on reset (POR).
•
Software reset—Resets the MMC/SD module only. This is controlled via the MMC/SD Clock Control
Register (STR_STP_CLK). See Section 20.6.1, “MMC/SD Clock Control Register,” for more information
on software resets.
•
Card reset—Resets the cards only. GO_IDLE_STATE (CMD0) sets the MMC and SD memory cards into
idle state. IO_RW_DIRECT (CMD52) resets the SD I/O Card. The cards are initialized with a default relative
card address (RCA = 0x0001) and with a default driver stage register setting (lowest speed, highest driving
current capability).
Code Example 20-4. Software_Reset
software_reset()
{
write_reg(STR_STP_CLK, 0x8);
write_reg(STR_STP_CLK, 0xd);
write_reg(STR_STP_CLK, 0x5);
write_reg(STR_STP_CLK, 0x5);
write_reg(STR_STP_CLK, 0x5);
write_reg(STR_STP_CLK, 0x5);
write_reg(STR_STP_CLK, 0x5);
write_reg(STR_STP_CLK, 0x5);
write_reg(STR_STP_CLK, 0x5);
write_reg(STR_STP_CLK, 0x5);
write_reg(CLK_RATE, 0x3F);
// Set the lowest clock for
//
initialization
write_reg(READ_TO, 0x2DB4);
send_cmd_wait_resp(CMD_GO_IDLE_STATE, 0x0, 0x0, 0x80, 0x40);
}
20.7.2.3 Voltage Validation
All cards can communicate with the MMC/SD module using any operating voltage within the specification range.
The supported minimum and maximum Vdd values are defined in the Operation Conditions Register (OCR) on the
card.
Cards that store the card identification number (CID) and card-specific data (CSD) in the payload memory are able
to communicate this information only under data transfer Vdd conditions. When the MMC/SD module and card
have incompatible Vdd ranges, the card is not able to complete the identification cycle and cannot send CSD data.
For this purpose, the special commands SEND_OP_COND (CMD1), SD_APP_OP_COND (ACMD41 for SD
Memory), and IO_SEND_OP_COND (CMD5 for SD I/O) are designed to provide a mechanism to identify and
reject cards that do not match the Vdd range desired by the MMC/SD module. The MMC/SD module sends the
required Vdd voltage window as the operand of these commands. Cards that cannot perform data transfer in the
specified range disconnect from the bus and go to inactive state.
MC9328MX1 Reference Manual, Rev. 6.1
20-34
Freescale Semiconductor
Functional Example for the MMC/SD Module
By uses these commands without including the voltage range as the operand, the MMC/SD module can query each
card and determine the common voltage range before sending out-of-range cards into the inactive state. This query
is used when the MMC/SD module is able to select a common voltage range or when the user requires notification
that cards are not usable.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-35
Functional Example for the MMC/SD Module
Code Example 20-5. Voltage_Validation
voltage_validation(voltage_range_h, voltage_range_l,voltage_set_h,voltage_set_l)
{
send_cmd_wait_resp(IO_RW_DIRECT, 0x8800, 0x0608, 0x05, 0x40);
// Reset IO card
send_cmd_wait_resp(IO_SEND_OP_COND, 0x0, 0x0, 0x04, 0x40);
// Send SDIO operation voltage command
if (End Command Response true & No. of IO functions> 0)
// it is an SDIO card
{
IORDY = 0;
while (!(IORDY in I/O ORC))
// set voltage range
{
send_cmd_wait_resp(IO_SEND_OP_COND,voltage_set_h,voltage_set_l,0x04,0x40);
}
if(Memory Present flag true)
Card = combo;
// i.e. SDIO + Memory
else
Card = sdio;
}
else
// SD or MMC
{
send_cmd_wait_resp(APP_CMD, voltage_range_h, voltage_range_l, 0x03, 0x40);
// MMC, SD reset
send_cmd_wait_resp(APP_CMD, 0x0, 0x0, 0x01, 0x40);
// Application Command follows
if(End Command Response true)
{
send_cmd_wait_resp(SEND_OP_COND, 0x0, 0x0, 0x01, 0x40);
// SD card found
while(!(card init finished))
{
send_cmd_wait_resp(APP_CMD, 0x0, 0x0, 0x01, 0x40);
send_cmd_wait_resp(SEND_OP_COND, voltage_range_h, voltage_set_l,0x03,0x40);
}
Card = sd;
}
else
{
send_cmd_wait_resp(SEND_OP_COND, voltage_range_h, voltage_range_l, 0x03, 0x40);
// MMC card found
if(End Command Response true)
{
Card = mmc;
while(!(card init finished))
{
send_cmd_wait_resp(SEND_OP_COND,voltage_set_h,voltage_set_l,0x03,0x40);
}
}
}
}
}
else
{
Card = No card or failed contact;
}
MC9328MX1 Reference Manual, Rev. 6.1
20-36
Freescale Semiconductor
Functional Example for the MMC/SD Module
20.7.2.4 Card Registry
Card registry differs for the MMC and the SD cards. For the MMC cards, the identification process starts at clock
rate Fod. The SD_CMD line output drivers are open-drain and allow parallel card operation during this process.
The registration process is accomplished as follows:
1. The bus is activated.
2. The MMC/SD module broadcasts SEND_OP_COND (CMD1) to receive operation conditions.
3. The response is the wired AND operation of the Operation Condition Registers from all cards.
4. The incompatible cards are set to inactive state.
5. The MMC/SD module broadcasts ALL_SEND_CID (CMD2) to all active cards.
6. The active cards simultaneously send CID numbers serially. Cards with outgoing CID bits that do
not match the bits on the command line stop transmitting and must wait for the next identification
cycle. One card successfully transmits a full CID to the MMC/SD module and goes into
identification state.
7. The MMC/SD module issues SET_RELATIVE_ADDR (CMD3) to that card. This new address is
called the relative card address (RCA); it is shorter than the CID and addresses the card. The
assigned card changes to standby state, it does not react to further identification cycles, and its
output switches from open-drain to push-pull.
8. The MMC/SD module repeats steps 5 through 7 until it receives a time-out condition.
For the SD card, the identification process starts at clock rate Fod, and the SD_CMD line output drives are
push-pull drivers instead of open-drain. The registration process is accomplished as follows:
1. The bus is activated.
2. The MMC/SD module broadcasts SD_APP_OP_COND (ACMD41).
3. The cards respond with the content of their Operation Condition Registers.
4. The incompatible cards are set to inactive state.
5. The MMC/SD module broadcasts ALL_SEND_CID (CMD2) to all active cards.
6. The cards send back their unique card identification numbers (CIDs) and go into identification state.
7. The MMC/SD module issues SET_RELATIVE_ADDR (CMD3) to an active card with an address.
This new address is called the relative card address (RCA); it is shorter than the CID and addresses
the card. The assigned card changes to standby state. The MMC/SD module can re-issue this
command to change the RCA. The RCA of the card is the last assigned value.
8. The MMC/SD module repeats steps 5 through 7 with all active cards.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-37
Functional Example for the MMC/SD Module
Code Example 20-6. Card_Registry
card_registry()
{
while(ResponseTO from STATUS)
{
if(card==combo or sdio)
{
send_cmd_wait_resp(ALL_SEND_CID, 0x00, 0x00, 0x02, 0x40);
send_cmd_wait_resp(SET_RELATIVE_ADDR, 0x00, 0x00, 0x01, 0x40);
rca = SDIO_RCA = address from response FIFO;
}
else if(card==sd)
{
send_cmd_wait_resp(ALL_SEND_CID, 0x00, 0x00, 0x02, 0x40);
send_cmd_wait_resp(SET_RELATIVE_ADDR, 0x00, 0x00, 0x01, 0x40);
rca = SD_RCA = address from response FIFO;
}
else if(card==mmc)
{
send_cmd_wait_resp(ALL_SEND_CID, 0x00, 0x00, 0x02, 0x40);
rca = MMC_RCA = 0x1;
send_cmd_wait_resp(SET_RELATIVE_ADDR, MMC_RCA, 0x00, 0x01, 0x40);
}
else
exit due to card not identified;
}
send_cmd_wait_resp(SELECT_CARD, rca, 0x00, 0x41, 0x40);
}
20.7.3 Card Access
This section discusses the MMC/SD card access with block write and read, stream write and read, erase and wide
bus selection and deselection.
20.7.3.1 Block Access: Block Write and Block Read
The module supports both block write and block read operation to the card. Block Mode data transfers are grouped
as 512 byte package/block and they are protected by CRC.
20.7.3.1.1 Block Write
During the block write commands (CMD24–CMD27), one or more blocks of data are transferred from the
MMC/SD module to the card with a CRC appended to the end of each block by the MMC/SD module. When the
CRC fails, the card indicates the failure on the SD_DAT line, the transferred data is discarded and not written, and
all further transmitted blocks (in multiple block write mode) are ignored. A card supporting block write is always
able to accept a block of data of the size defined by WRITE_BL_LEN.
When the MMC/SD module uses partial blocks with accumulated lengths that are not block aligned and block
misalignment is not allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card detects the block
alignment error and aborts programming before the beginning of the first misaligned block. The card sets the
ADDRESS_ERROR bit in the Card Status Register, ignores all further data transfers, and waits in the receive state
for a stop command. The write operation is aborted when the MMC/SD module tries to write over a write protected
area. In this case, the card sets the WP_VIOLATION bit in the Card Status Register.
Block write commands are used to program the CID and CSD registers which do not require a previous block
length setting. The transferred data is CRC protected.
MC9328MX1 Reference Manual, Rev. 6.1
20-38
Freescale Semiconductor
Functional Example for the MMC/SD Module
When a part of the CSD or CID register is stored in ROM, this unchangeable part must match the corresponding
part of the receive buffer or the card reports an error and does not change any register contents.
Some cards can require long and unpredictable times to write a block of data. After receiving a block of data and
completing the CRC check, the card begins writing. When the write buffer is full and unable to accept new data,
the card holds the SD_DAT line(s) low. The MMC/SD module can poll the status of the card by sending a
SEND_STATUS (CMD13) at any time, and the card responds with its status. The READY_FOR_DATA bit in the
Card Status Register indicates whether the card can accept new data or when a write is still in progress. The
MMC/SD module can deselect the card by issuing SELECT/DESELECT_CARD (CMD7), which displaces the card
into the disconnect state and releases the SD_DAT line(s) without interrupting the write operation. When the card
is reselected using SELECT/DESELECT_CARD (CMD7), when programming is still in progress and the write
buffer is unavailable, the SD_DAT line(s) are pulled low. Code Example 20-7 provides the program code for the
block write with DMA.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-39
Functional Example for the MMC/SD Module
Code Example 20-7. Block_Write with DMA
block_write(rca, nob, addr_h, addr_l, buswidth)
{
send_cmd_wait_resp(SEND_STATUS, rca, 0x00, 0x01, 0x40);
while(!Ready for data in card status is true)
{
send_cmd_wait_resp(SEND_STATUS, rca, 0x00, 0x01, 0x40);
}
write_reg(NOB, <nob>);
send_cmd_wait_resp(SET_BLOCKLEN, 0x00, 0x0200, 0x01, 0x40);
if(buswidth==4-bit mode)
{
send_cmd_wait_resp(APP_CMD, rca, 0x0, 0x01, 0x40);
send_cmd_wait_resp(SET_BUS_WIDTH, 0x00, 0x02, 0x01, 0x40);
}
// Configure the DMA for FIFO write operation (BUFFER_ACCESS,
// SDRAM_ADDR, nob);
//
//
//
//
Set
Set
Set
Set
DMA
DMA
DMA
DMA
source address = SDRAM_ADDR
target address = BUFFER_ACCESS
total byte transfer = nob
burst depth = 8 if 1-bit mode, = 32 if 4-bit mode
if(nob==1)
{ if(buswidth=4-bit mode)
send_cmd_wait_resp(WRITE_SINGLE_BLOCK, addr_h, addr_l, 0x219,
0x40);
else
0x40);
send_cmd_wait_resp(WRITE_SINGLE_BLOCK, addr_h, addr_l, 0x19,
}
else
{ if(buswidth=4-bit mode)
send_cmd_wait_resp(WRITE_MULTIPLE_BLOCK, addr_h, addr_l, 0x219,
0x40);
else
0x40);
}
send_cmd_wait_resp(WRITE_MULTIPLE_BLOCK, addr_h, addr_l, 0x19,
}
while(!FIFO empty in STATUS is true);
Enable DMA operation;
while(!Access Operation Done in STATUS true);
while(!card bus is stop);
if(nob > 1)
{
send_cmd_wait_resp(STOP_TRANS, 0x00, 0x00, 0x1, 0x40);
}
Code Example 20-8 on page 20-41 provides the program code for the block write with polling.
MC9328MX1 Reference Manual, Rev. 6.1
20-40
Freescale Semiconductor
Functional Example for the MMC/SD Module
Code Example 20-8. Block_Write with Polling
block_write(rca, nob, addr_h, addr_l, buswidth)
{
send_cmd_wait_resp(SEND_STATUS, rca, 0x00, 0x01, 0x40);
while(!Ready for data in card status is true)
{
send_cmd_wait_resp(SEND_STATUS, rca, 0x00, 0x01, 0x40);
}
write_reg(NOB, <nob>);
send_cmd_wait_resp(SET_BLOCKLEN, 0x00, 0x0200, 0x01, 0x40);
if(buswidth==4-bit mode)
{
send_cmd_wait_resp(APP_CMD, rca, 0x0, 0x01, 0x40);
send_cmd_wait_resp(SET_BUS_WIDTH, 0x00, 0x02, 0x01, 0x40);
}
if(nob==1)
{ if(buswidth=4-bit mode)
send_cmd_wait_resp(WRITE_SINGLE_BLOCK, addr_h, addr_l, 0x219, 0x40);
else
send_cmd_wait_resp(WRITE_SINGLE_BLOCK, addr_h, addr_l, 0x19, 0x40);
}
else
if(buswidth==4-bit mode)
send_cmd_wait_resp(WRITE_MULTIPLE_BLOCK, addr_h, addr_l, 0x219, 0x40);
send_cmd_wait_resp(WRITE_MULTIPLE_BLOCK, addr_h, addr_l, 0x19, 0x40);
}
while(!FIFO empty in STATUS is true);
{
for(i=0;i<(nob*8);i++)
{
while(!FIFO full in STATUS);// polling instead of irq or dma req
for(j=0;j<32;j++)
{
BUFFER_ACCESS = SDRAM_ADDR[i*32+j];
}
}
else// 1-bit mode
{
for(i=0;i<(nob*32);i++)
{
while(!FIFO full in STATUS);// polling instead of irq or dma req
for(j=0;j<8;j++)
{
BUFFER_ACCESS = SDRAM_ADDR[i*8+j];
}
}
}
while(!Access Operation Done in STATUS true);
while(!card bus is stop);
if(nob > 1)
{
send_cmd_wait_resp(STOP_TRANS, 0x00, 0x00, 0x1, 0x40);
}
}
20.7.3.1.2 Block Read
In Block Mode transfer, CRC is used and appended to the end of each block ensuring data transfer integrity.
READ_SINGLE_BLOCK (CMD17) initiates a block read and after completing the transfer, the card returns to the
transfer state. READ_MULTIPLE_BLOCK (CMD18) starts a transfer of several consecutive blocks. Blocks are
continuously transferred until a stop command is issued. When the MMC/SD module uses partial blocks with an
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-41
Functional Example for the MMC/SD Module
accumulated length that is not block aligned and block misalignment is not allowed, the card detects a block
misalignment at the beginning of the first mis-aligned block, set the ADDRESS_ERROR error bit in the Card
Status Register, abort transmission, and wait in the data state for a stop command. Code Example 20-9 provides the
program code for the block read with DMA.
Code Example 20-9. Block_Read with DMA
block_read(rca, nob, addr_h, addr_l, buswidth)
{
send_cmd_wait_resp(SEND_STATUS, rca, 0x00, 0x01, 0x40);
while(!Ready for data in card status is true)
{
send_cmd_wait_resp(SEND_STATUS, rca, 0x00, 0x01, 0x40);
}
write_reg(NOB, <nob>);
send_cmd_wait_resp(SET_BLOCKLEN, 0x00, 0x0200, 0x01, 0x40);
if(buswidth==4-bit mode)
{
send_cmd_wait_resp(APP_CMD, rca, 0x0, 0x01, 0x40);
send_cmd_wait_resp(SET_BUS_WIDTH, 0x00, 0x02, 0x01, 0x40);
}
// Configure the DMA for FIFO read operation (BUFFER_ACCESS,
SDRAM_ADDR, nob);
//
//
//
//
Set
Set
Set
Set
DMA
DMA
DMA
DMA
source address = BUFFER_ACCESS
target address = SDRAM_ADDR
total byte transfer = nob
burst depth = 8 if 1-bit mode, = 32 if 4-bit mode
if(nob==1)
{ if(buswidth=4-bit mode)
send_cmd_wait_resp(READ_SINGLE_BLOCK, addr_h, addr_l, 0x209,
0x40);
else
0x40);
send_cmd_wait_resp(READ_SINGLE_BLOCK, addr_h, addr_l, 0x09,
}
else
{ if(buswidth=4-bit mode)
send_cmd_wait_resp(READ_MULTIPLE_BLOCK, addr_h, addr_l, 0x209,
0x40);
else
0x40);
}
send_cmd_wait_resp(READ_MULTIPLE_BLOCK, addr_h, addr_l, 0x09,
}
Enable DMA operation;
while(!Data Transfer Done in STATUS true);
while(!card bus is stop);
if(nob > 1)
{
send_cmd_wait_resp(STOP_TRANS, 0x00, 0x00, 0x1, 0x40);
}
Code Example 20-10 on page 20-43 provides the program code for the block read with polling.
MC9328MX1 Reference Manual, Rev. 6.1
20-42
Freescale Semiconductor
Functional Example for the MMC/SD Module
Code Example 20-10. Block_Read with Polling
block_read(rca, nob, addr_h, addr_l, buswidth)
{
send_cmd_wait_resp(SEND_STATUS, rca, 0x00, 0x01, 0x40);
while(!Ready for data in card status is true)
{
send_cmd_wait_resp(SEND_STATUS, rca, 0x00, 0x01, 0x40);
}
write_reg(NOB, <nob>);
send_cmd_wait_resp(SET_BLOCKLEN, 0x00, 0x0200, 0x01, 0x40);
if(buswidth==4-bit mode)
{
send_cmd_wait_resp(APP_CMD, rca, 0x0, 0x01, 0x40);
send_cmd_wait_resp(SET_BUS_WIDTH, 0x00, 0x02, 0x01, 0x40);
}
if(nob==1)
{ if(buswidth=4-bit mode)
send_cmd_wait_resp(READ_SINGLE_BLOCK, addr_h, addr_l, 0x209, 0x40);
else
send_cmd_wait_resp(READ_SINGLE_BLOCK, addr_h, addr_l, 0x09, 0x40);
}
else
{ if(buswidth=4-bit mode)
send_cmd_wait_resp(READ_MULTIPLE_BLOCK, addr_h, addr_l, 0x209, 0x40);
else
send_cmd_wait_resp(READ_MULTIPLE_BLOCK, addr_h, addr_l, 0x09, 0x40);
}
if(buswidth==4-bit mode)
{
for(i=0;i<(nob*8);i++)
{
while(!FIFO full in STATUS);// polling instead of irq or dma req
for(j=0;j<32;j++)
{
SDRAM_ADDR[i*32+j] = BUFFER_ACCESS;
}
}
}
else// 1-bit mode
{
for(i=0;i<(nob*32);i++)
{
while(!FIFO full in STATUS);// polling instead of irq or dma req
for(j=0;j<8;j++)
{
SDRAM_ADDR[i*8+j] = BUFFER_ACCESS;
}
}
}
while(!Data Transfer Done in STATUS true);
while(!card bus is stop);
if(nob > 1)
{
send_cmd_wait_resp(STOP_TRANS, 0x00, 0x00, 0x1, 0x40);
}
}
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-43
Functional Example for the MMC/SD Module
20.7.3.2 Stream Access—Stream Write and Stream Read (MMC Only)
The module also supports Stream Mode access to the card. In Stream Mode data is transferred in bytes and no CRC
appended at the end of each package/block. So it is relatively more effective. However with CRC, the user may use
either the checking mechanism to verify the content, or the bit content self-independent, like raw sound track.
20.7.3.2.1 Stream Write
WRITE_DAT_UNTIL_STOP (CMD20) starts the data transfer from the MMC/SD module to the card, beginning at
the specified address and continuing until the MMC/SD module issues a stop command. When partial blocks are
allowed (CSD parameter WRITE_BL_PARTIAL is set), the data stream can start and stop at any address within
the card address space, otherwise it can only start and stop at block boundaries. Because the amount of data to be
transferred is not determined in advance, a CRC cannot be used. When the end of the memory range is reached
while sending data and no stop command is sent by the MMC/SD module, any additional data transferred is
discarded.
The maximum clock frequency for a stream write operation is given by Equation 20-3 using fields of the
Card-Specific Data Register.
WRITE_BL_LEN
– NSAC
8•2
MAXIMUM SPEED = MIN ⎛⎝ TRAN_SPEED, --------------------------------------------------------------------⎞⎠
TAAC • R2W_FACTOR
•
TRAN_SPEED = Maximum Data Transfer Rate
•
READ_BL_LEN = Maximum Read Data Block Length
•
NSAC = Data Read Access Time 2 in CLK Cycles
•
TAAC = Data Read Access Time 1
•
R2W_FACTOR = Write Speed Factor
Eqn. 20-3
When the MMC/SD module attempts to use a frequency higher than the value defined in Equation 20-3, the card
may be unable to process the data, causing an overrun condition. When an overrun condition is detected, the card
stops programming, sets the OVERRUN error bit in the Card Status Register, ignores all further data transfer
attempts, and waits in the receive state for a stop command. When the MMC/SD module tries to write over a
write-protected area, the write operation is aborted and the card sets the WP_VIOLATION bit in the Card Status
Register.
Code Example 20-11 on page 20-45 provides the program code for the stream write.
MC9328MX1 Reference Manual, Rev. 6.1
20-44
Freescale Semiconductor
Functional Example for the MMC/SD Module
Code Example 20-11. Stream_Write
stream_write(rca, nob, addr_h, addr_l, buswidth)
{
send_cmd_wait_resp(SEND_STATUS, rca, 0x00, 0x01, 0x40);
while(!Ready for data in card status is true)
{
send_cmd_wait_resp(SEND_STATUS, rca, 0x00, 0x01, 0x40);
}
write_reg(NOB, 0xffff);
send_cmd_wait_resp(SET_BLOCKLEN, 0x00, 0x0200, 0x01, 0x40);
if(buswidth==4-bit mode)
{
send_cmd_wait_resp(APP_CMD, rca, 0x0, 0x01, 0x40);
send_cmd_wait_resp(SET_BUS_WIDTH, 0x00, 0x02, 0x01, 0x40);
}
send_cmd_wait_resp(WRITE_DAT_UNTIL_STOP, addr_h, addr_l, 0x79, 0x40);
while(!FIFO empty in STATUS is true);
if(buswidth==4-bit mode)
{
for(i=0;i<(nob*8);i++)
{
while(!FIFO full in STATUS);// polling instead of irq or dma req
for(j=0;j<32;j++)
{
SDRAM_ADDR[i*32+j] = BUFFER_ACCESS;
}
}
}
else// 1-bit mode
{
for(i=0;i<(nob*32);i++)
{
while(!FIFO full in STATUS);// polling instead of irq or dma req
for(j=0;j<8;j++)
{
SDRAM_ADDR[i*8+j] = BUFFER_ACCESS;
}
}
}
send_cmd_wait_resp(STOP_TRANS, 0x00, 0x00, 0x1, 0x40);
}
20.7.3.2.2 Stream Read
READ_DAT_UNTIL_STOP (CMD11) controls a stream-oriented data transfer. This command instructs the card to
send its data, starting at a specified address, until the MMC/SD module sends STOP_TRANSMISSION (CMD12).
The stop command has an execution delay due to the serial command transmission and the data transfer stops after
the end bit of the stop command. When the end of the memory range is reached while sending data and no stop
command is sent by the MMC/SD module, any subsequent data sent is considered undefined.
The maximum clock frequency for a stream read operation is given by Equation 20-4 and uses fields of the
Card-Specific Data Register.
READ_BL_LEN
8•2
– NSAC
MAXIMUM SPEED = MIN ⎛ TRAN_SPEED, ------------------------------------------------------------------⎞
⎝
⎠
TAAC
•
TRAN_SPEED = Maximum Data Transfer Rate
•
READ_BL_LEN = Maximum Read Data Block Length
•
NSAC = Data Read Access Time 2 in CLK Cycles
Eqn. 20-4
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-45
Functional Example for the MMC/SD Module
•
TAAC = Data Read Access Time 1
When the MMC/SD module attempts to use a frequency higher than the value defined in Equation 20-4, the card
may be unable to sustain data transfer, causing an underrun condition. When an underrun condition is detected, the
card sets the UNDERRUN error bit in the Card Status Register, aborts the transmission, and waits in the data state
for a stop command. Code Example 20-12 provides the program code for the stream read.
Code Example 20-12. Stream_Read
stream_read(rca, nob, addr_h, addr_l, buswidth)
{
send_cmd_wait_resp(SEND_STATUS, rca, 0x00, 0x01, 0x40);
while(!Ready for data in card status is true)
{
send_cmd_wait_resp(SEND_STATUS, rca, 0x00, 0x01, 0x40);
}
write_reg(NOB, 0xffff);
send_cmd_wait_resp(SET_BLOCKLEN, 0x00, 0x0200, 0x01, 0x40);
if(buswidth==4-bit mode)
{
send_cmd_wait_resp(APP_CMD, rca, 0x0, 0x01, 0x40);
send_cmd_wait_resp(SET_BUS_WIDTH, 0x00, 0x02, 0x01, 0x40);
}
send_cmd_wait_resp(READ_DAT_UNTIL_STOP, addr_h, addr_l, 0x29, 0x40);
if(buswidth==4-bit mode)
{
for(i=0;i<(nob*8);i++)
{
while(!FIFO full in STATUS);// polling instead of irq or dma req
for(j=0;j<32;j++)
{
SDRAM_ADDR[i*32+j] = BUFFER_ACCESS;
}
}
}
else// 1-bit mode
{
for(i=0;i<(nob*32);i++)
{
while(!FIFO full in STATUS);// polling instead of irq or dma req
for(j=0;j<8;j++)
{
SDRAM_ADDR[i*8+j] = BUFFER_ACCESS;
}
}
}
send_cmd_wait_resp(STOP_TRANS, 0x00, 0x00, 0x1, 0x40);
}
20.7.3.3 Erase—Group Erase (MMC Only) and Sector Erase
It is often desirable to erase multiple sectors simultaneously to enhance the data throughput. Identification of these
sectors is accomplished with the Tag commands.
MultimediaCard and Secure Digital support the Sector Erase commands (CMD 32–33), while the Group Erase
commands (CMD 35–36) are only supported by MMC.
The unit of measure for an erase is either a sector or an erase group. The size of an erase group is card-specific and
set in the CSD Register. To define particular sectors to erase, all selected sectors must lie within the same erase
group. Alternately, the user can erase multiple erase groups at a time.
MC9328MX1 Reference Manual, Rev. 6.1
20-46
Freescale Semiconductor
Functional Example for the MMC/SD Module
To erase efficiently, select a group of sectors or erase groups by using either TAG_SECTOR_START (CMD32) or
TAG_ERASE_GROUP_START (CMD35) which identifies the starting address. Follow this command with either
TAG_SECTOR_END (CMD 33) or TAG_ERASE_GROUP_END (CMD36). All sectors or erase groups within the
range are selected. The user can deselect a sector or erase group using the UNTAG_SECTOR (CMD34) or
UNTAG_ERASE_GROUP (CMD37) commands.
To erase by sectors, perform the following command sequence:
1. TAG_SECTOR_START (CMD32)
2. TAG_SECTOR_END (CMD33)
3. UNTAG_SECTOR (CMD34), to optionally de-select sectors within the address range
4. ERASE (CMD38)
To erase by groups, perform the following command sequence:
1. TAG_ERASE_GROUP_START (CMD35)
2. TAG_ERASE_GROUP_END (CMD36)
3. UNTAG_ERASE_GROUP (CMD37), to optionally de-select erase groups within the address range
4. ERASE (CMD38)
Up to 16 UNTAG* commands can be sent within one erase cycle. When an ERASE, TAG*, or UNTAG* command
is received out-of-sequence, the card sets the ERASE_SEQ_ERROR bit in the Card Status Register and resets the
whole sequence. When an out-of-sequence command (except SEND_STATUS) is received, the card sets the
ERASE_RESET status bit in the Card Status Register, resets the erase sequence, and executes the last command.
When the erase range includes write protected sectors, they are left intact, only the non-protected sectors are
erased, and the WP_ERASE_SKIP status bit in the Card Status Register is set. The address field in the TAG*
commands is a sector or a group address in byte units. The card ignores all least significant bits (LSBs) below the
group or sector size, respectively.
As with block write, the card indicates that an erase is in progress by holding the SD_DAT line(s) low. The actual
erase time can be quite long, and the MMC/SD module can issue SELECT/DESELECT_CARD (CMD7) to deselect
the card.
20.7.3.4 Wide Bus Selection or Deselection
Wide bus (4-bit bus width) operation mode is selected or deselected using SET_BUS_WIDTH (ACMD6). The
default bus width after power-up or GO_IDLE_STATE (CMD0) is 1-bit. SET_BUS_WIDTH (ACMD6) is only valid
in a transfer state which means the bus width can be changed only after a card is selected by
SELECT/DESELECT_CARD (CMD7).
20.7.4 Protection Management
Three write-protection methods for the cards are supported in the SDHC module:
•
Card internal write protection (card responsibility)
•
Mechanical write protection switch (MMC/SD module responsibility only)
•
Password protection card lock operation
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-47
Functional Example for the MMC/SD Module
20.7.4.1 Card Internal Write Protection
Card data can be protected against write and erase. By setting the permanent or temporary write-protect bits in the
CSD, the entire card can be permanently write-protected by the manufacturer or content provider. For cards that
support write-protection of groups of sectors by setting the WP_GRP_ENABLE bit in the CSD, portions of the
data can be protected, and the write-protection can be changed by the application. The write-protection is in units
of WP_GRP_SIZE sectors as specified in the CSD. The commands SET_WRITE_PROT and CLR_WRITE_PROT
control the protection of the addressed group.
The SEND_WRITE_PROT command is similar to a single block read command. The card sends a data block
containing 32 write protection bits (representing 32 write protect groups starting at the specified address) followed
by 16 CRC bits. The address field in the write protect commands is a group address in byte units. The card ignores
all LSBs below the group size.
20.7.4.2 Mechanical Write Protect Switch
A mechanical sliding tab on the side of the card allows the user to set or clear write protection on a card. When the
sliding tab is positioned with the window open, the card is write protected, and when the window is closed, the card
contents can be changed.
A proper, matched switch on the socket side indicates to the MMC/SD module that the card is write protected. The
MMC/SD module is responsible for protecting the card. The position of the write protect switch is unknown to the
internal circuitry of the card.
20.7.4.3 Password Protect
The password protection feature enables the MMC/SD module to lock and unlock a card with a password. The
password is stored in the 128-bit PWD Register and its size is set in the 8-bit PWD_LEN Register. These registers
are non-volatile so that a power cycle does not erase them.
Locked cards respond to and execute certain commands. This means that the MMC/SD module is allowed to reset,
initialize, select, and query for status, however it is not allowed to access data on the card. When the password is
set (as indicated by a nonzero value of PWD_LEN), the card is locked automatically after power on. As with the
CSD and CID Register write commands, the lock/unlock commands are available in transfer state only. In this
state, the command does not include an address argument and the card must be selected before using it. The card
lock/unlock commands have the structure and bus transaction types of a regular single block write command. The
transferred data block includes all of the required information for the command (the password setting mode, the
PWD itself, and card lock/unlock). The command data block size is defined by the MMC/SD module before it
sends the card lock/unlock command, and has the structure shown in Table 20-21.
Table 20-21. Structure of Command Data Block
Byte#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Reserved
Reserved
Reserved
Reserved
ERASE
LOCK_
UNLOCK
CLR_
PWD
SET_
PWD
1
PWD_LEN
2
...
PWD
PWD_LEN +1
MC9328MX1 Reference Manual, Rev. 6.1
20-48
Freescale Semiconductor
Functional Example for the MMC/SD Module
The bit settings are as follows:
•
ERASE—Setting forces an erase operation. All other bits must be zero, and only the command byte is sent.
•
LOCK_UNLOCK—Setting locks the card. LOCK_UNLOCK can be set simultaneously with SET_PWD,
however not with CLR_PWD.
•
CLR_PWD—Setting clears the password data.
•
SET_PWD—Setting saves the password data to memory.
•
PWD_LEN—Defines the length of the password in bytes.
•
PWD—The password (new or currently used, depending on the command).
The following sections list the command sequences to set/reset a password, lock/unlock the card, and force an
erase.
20.7.4.3.1 Setting the Password
1. Select a card (SELECT/DESELECT_CARD, CMD7), if not already selected.
2. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card lock/unlock
mode (Byte 0 in Table 20-21), the 8-bit PWD_LEN, and the number of bytes of the new password.
When a password replacement is done, the block size must take into account that both the old and
the new passwords are sent with the command.
3. Send LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line including the
16-bit CRC. The data block indicates the mode (SET_PWD = 1), the length (PWD_LEN), and the
password (PWD) itself. When a password replacement is done, the length value (PWD_LEN)
includes the length of both passwords, the old and the new one, and the PWD field includes the old
password (currently used) followed by the new password.
4. When the password is matched, the new password and its size are saved into the PWD and
PWD_LEN fields, respectively. When the old password sent is not correct in size and/or content
with the expected password, the LOCK_UNLOCK_FAILED error bit is set in the Card Status
Register and the password is not changed.
NOTE:
The password length field (PWD_LEN) indicates whether a password is currently
set. When this field is nonzero, there is a password set and the card locks itself after
power-up. It is possible to lock the card immediately in the current power session
by setting the LOCK_UNLOCK bit (while setting the password) or sending an
additional command for card locking.
20.7.4.3.2 Resetting the Password
1. Select a card (SELECT/DESELECT_CARD, CMD7), if not already selected.
2. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card lock/unlock
mode (Byte 0 in Table 20-21), the 8-bit PWD_LEN, and the number of bytes of the current
password.
3. Send LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line including the
16-bit CRC. The data block indicates the mode (CLR_PWD = 1), the length (PWD_LEN), and the
password (PWD) itself. The LOCK_UNLOCK bit is ignored.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-49
Functional Example for the MMC/SD Module
4. When the password is matched, the PWD field is cleared and PWD_LEN is set to 0. When the
password sent is not correct in size and/or content with the expected password, the
LOCK_UNLOCK_FAILED error bit is set in the Card Status Register and the password is not
changed.
20.7.4.3.3 Locking a Card
1. Select a card (SELECT/DESELECT_CARD, CMD7), if not already selected.
2. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card lock/unlock
mode (Byte 0 in Table 20-21), the 8-bit PWD_LEN, and the number of bytes of the current
password.
3. Send LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line including the
16-bit CRC. The data block indicates the mode (LOCK_UNLOCK = 1), the length (PWD_LEN),
and the password (PWD) itself.
4. When the password is matched, the card is locked and the CARD_IS_LOCKED status bit is set in
the Card Status Register. When the password sent is not correct in size and/or content with the
expected password, the LOCK_UNLOCK_FAILED error bit is set in the Card Status Register and
the lock fails.
NOTE:
It is possible to set the password and to lock the card in the same sequence. In this
case, the MMC/SD module performs all the required steps for setting the password
(see Section 20.7.4.3.1, “Setting the Password,” on page 20-49), however it is
necessary to set the LOCK_UNLOCK bit in Step 3 when the new password
command is sent.
When the password is previously set (PWD_LEN is not 0), the card is locked automatically after power on reset.
An attempt to lock a locked card or to lock a card that does not have a password fails and the
LOCK_UNLOCK_FAILED error bit is set in the Card Status Register.
20.7.4.3.4 Unlocking the Card
1. Select a card (SELECT/DESELECT_CARD, CMD7), if not already selected.
2. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card lock/unlock
mode (Byte 0 in Table 20-21), the 8-bit PWD_LEN, and the number of bytes of the current
password.
3. Send LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line including the
16-bit CRC. The data block indicates the mode (LOCK_UNLOCK = 0), the length (PWD_LEN),
and the password (PWD) itself.
4. When the password is matched, the card is unlocked and the CARD_IS_LOCKED status bit is
cleared in the Card Status Register. When the password sent is not correct in size and/or content
with the expected password, the LOCK_UNLOCK_FAILED error bit is set in the Card Status
Register and the card remains locked.
NOTE:
The unlocking function is only valid for the current power session. When the PWD
field is not clear, the card is locked automatically on the next power up.
An attempt to unlock an unlocked card fails and the LOCK_UNLOCK_FAILED error bit is set in the Card Status
Register.
MC9328MX1 Reference Manual, Rev. 6.1
20-50
Freescale Semiconductor
Functional Example for the MMC/SD Module
20.7.4.3.5 Forcing Erase
When the user has forgotten the password (PWD content), it is possible to access the card after clearing all the data
on the card. This forced erase operation erases all card data and all password data.
1. Select a card (SELECT/DESELECT_CARD, CMD7), if not already selected.
2. Set the block length (SET_BLOCKLEN, CMD16) to 1 byte. Only the 8-bit card lock/unlock byte
(Byte 0 in Table 20-21) is sent.
3. Send LOCK/UNLOCK (CMD42) with the appropriate data byte on the data line including the 16-bit
CRC. The data block indicates the mode (ERASE = 1). All other bits must be zero.
4. When the ERASE bit is the only bit set in the data field, all card content is erased, including the
PWD and PWD_LEN fields, and the card is no longer locked. When any other bits are set, the
LOCK_UNLOCK_FAILED error bit is set in the Card Status Register and the card retains all of its
data, and remains locked.
An attempt to use a force erase on an unlocked card fails and the LOCK_UNLOCK_FAILED error bit is set in the
Card Status Register.
20.7.5 Card Status Register
The response format R1 contains a 32-bit card status field. This field transmits the card’s status information (which
is stored in a local status register) to the MMC/SD module. When not specified, the status entries are always related
to the last command issued.
Table 20-22 defines the different entries of the Card Status Register. The type and clear condition fields in the table
are abbreviated as follows:
Type:
•
E—Error bit.
•
S—Status bit.
•
R—Detected and set for the actual command response.
•
X—Detected and set during command execution. The MMC/SD module must poll the card by issuing the
status command to read these bits.
Clear Condition:
•
A—According to the card current state.
•
B—Always related to the previous command. Reception of a valid command clears it (with a delay of one
command).
•
C—Clear by read.
Table 20-22. Card Status Register Description
Settings
Description
Clear
Condition
Bit
Bit Name
Type
31
OUT_OF
_RANGE
ER
0 = No error
1 = Error
The command’s argument is out of the allowed
range for this card.
C
30
ADDRESS
_ERROR
ERX
0 = No error
1 = Error
A misaligned address not matching the block
length is used in the command.
C
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-51
Functional Example for the MMC/SD Module
Table 20-22. Card Status Register Description (continued)
Settings
Clear
Condition
Bit
Bit Name
Type
Description
29
BLOCK_LEN
_ERROR
ER
0 = No error
1 = Error
The transferred block length is not allowed, or
the number of transferred bytes does not match
the block length.
C
28
ERASE_SEQ
_ERROR
ER
0 = No error
1 = Error
The sequence of erase commands is invalid.
C
27
ERASE
_PARAM
EX
0 = No error
1 = Error
The selected sectors or groups for erase are
invalid.
C
26
WP
_VIOLATION
ERX
0 = No error
1 = Protected Block
An attempt is made to program a write
protected block.
C
0 = Card Unlocked
1 = Card Locked
The card is locked by the MMC/SD module.
A
25
CARD_IS
_LOCKED
SX
24
LOCK
_UNLOCK
_FAILED
ERX
0 = No error
1 = Error
Any of the following has occurred:
• Password incorrect in length or content
• An attempt to lock a locked card
• An attempt to unlock an unlocked card
• A forced erase attempted on an unlocked card
C
23
COM_CRC
_ERROR
ER
0 = No error
1 = Error
The CRC check of the previous command
failed.
B
22
ILLEGAL
_COMMAND
ER
0 = No error
1 = Error
The executed command is not legal for the card
state.
B
21
CARD_ECC
_FAILED
EX
0 = No failure
1 = Failure
Card internal ECC is applied but failed to
correct the data.
C
20
CC_ERROR
ERX
0 = No error
1 = Error
Internal card controller error.
C
19
ERROR
ERX
0 = No error
1 = Error
A general or an unknown error occurred during
the operation.
C
18
UNDERRUN
EX
0 = No error
1 = Error
The card could not sustain data transfer in
stream read mode.
C
17
OVERRUN
EX
0 = No error
1 = Error
The card could not sustain data programming
in stream write mode.
C
16
CID/CSD_
OVERWRITE
ERX
0 = No error
1 = Error
Any of the following has occurred:
• The CID register is already written and cannot
be overwritten
• The read-only section of the CSD does not
match the card content
• An attempt is made to reverse the copy (set
as original) or permanent WP (unprotected) bits
C
MC9328MX1 Reference Manual, Rev. 6.1
20-52
Freescale Semiconductor
Functional Example for the MMC/SD Module
Table 20-22. Card Status Register Description (continued)
Bit
Bit Name
15
Clear
Condition
Type
Settings
Description
WP_ERASE
_SKIP
SX
0 = All selected areas
erased
1 = Some selected areas
are protected
Parts of the selected erase area are protected.
Only partial address space is erased due to
existing write protected blocks.
C
14
CARD_ECC
_DISABLED
SX
0 = Internal ECC used
1 = Internal ECC
disabled
The command is executed without using the
internal ECC.
A
13
ERASE
_RESET
SR
0 = Erase completed
1 = Erase sequence not
completed
An out-of-sequence erase command is
received, so the erase sequence is cleared
before executing.
C
CURRENT
_STATE
SX
0000 (0) = Idle
0001 (1) = Ready
0010 (2) = Identification
0011 (3) = Standby
0100 (4) = Transfer
0101 (5) = Data
0110 (6) = Receive
0111 (7) = Programming
1000 (8) = Disconnect
1001 (9)–1111 (15) are
Reserved
The state of the card when receiving the
command. When the command execution
causes a state change, it is visible to the
MMC/SD module in the response to the next
command.
B
READY_FOR
_DATA
SX
0 = Not ready
1 = Ready
Corresponds to buffer empty signalling on the
bus
A
SR
0 = Disabled
1 = Enabled
The card expects an ACMD, or indication that
the command is interpreted as an ACMD.
C
12:9
8
7:6
Reserved
5
APP_CMD
4:0
Reserved
20.7.6 SD Status Register
The SD Status Register contains status bits that are related to the SD card proprietary features and are available for
future application-specific usage. The size of the SD Status Register is one 512-bit data block. The content of this
register (and a 16-bit CRC) is transmitted to the MMC/SD module over the SD_DAT bus when the MMC/SD
module sends the SD_STATUS (ACMD13) command. This command consists of APP_CMD (CMD55) followed by
CMD13. SD_STATUS (ACMD13) can only be sent to a card in transfer state. SD Status Register structure is
described in this section.
Table 20-22 defines the different entries of the SD Status Register. The type and clear condition fields in the table
are abbreviated as follows:
Type:
•
E—Error bit.
•
S—Status bit.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-53
Functional Example for the MMC/SD Module
•
R—Detected and set for the actual command response.
•
X—Detected and set during command execution. The MMC/SD module must poll the card by issuing the
status command to read these bits.
Clear Condition:
•
A—According to the card current state.
•
B—Always related to the previous command. Reception of a valid command clears it (with a delay of one
command).
•
C—Clear by read
Table 20-23. SD Status Register
Bit
Bit Name
Type
Settings
Clear
Condition
Description
511:510
DAT_BUS_WIDTH
SR
00 = 1-bit width
01 = reserved
10 = 4-bit width
11 = reserved
Shows the currently defined data bus
width that is defined by
SET_BUS_WIDTH (ACMD6, 1-bit
width is default)
A
509
SECURED_MODE
SR
0 = Not in secured mode
1 = In secured mode
Card is in secured mode of operation
A
508:496
Reserved
495:480
SD_CARD_TYPE
SR
0 = SD Memory Cards
1 = SD I/O Cards
Selects between SD Memory and
SD I/O cards.
A
479:448
SIZE_OF_
PROTECTED_AREA
SR
See Description
Size of protected area (in units
defined by SET_BLOCKLEN,
CMD16)
A
447:312
Reserved
311:0
Reserved for manufacturer
20.7.7 SD I/O
I/O access differs from memory access because the I/O registers can be written and read individually and directly
without a File Allocation Table (FAT) file structure or the concept of blocks (although block access is supported).
These registers allow access to the I/O data, control of the I/O functions, report on status of data, and transfer I/O
data to/from the MMC/SD module.
Each SD I/O card can have between 1 and 7 functions plus one memory function built into it. A function is a
self-contained I/O device. These functions can be identical or completely different from each other. All I/O
functions are organized as a collection of registers, and there are a maximum of 131,072 registers possible for each
I/O function.
20.7.7.1 SD I/O Interrupts
To allow the SD I/O card to interrupt the MMC/SD module, and interrupt function is available on a pin on the SD
interface. Pin 8, used as SD_DAT [1] when operating in the 4-bit SD mode, signals the card’s interrupt to the
MMC/SD module. The use of the interrupt is optional for each card or function within a card. The SD I/O interrupt
MC9328MX1 Reference Manual, Rev. 6.1
20-54
Freescale Semiconductor
Functional Example for the MMC/SD Module
is level sensitive, which means that the interrupt line must be held active (low) until it is either recognized and
acted upon by the MMC/SD module or deasserted due to the end of the interrupt period. After the MMC/SD
module has serviced the interrupt, the interrupt status bit is cleared via an I/O write to the appropriate bit in the
SD I/O card internal registers. The interrupt output of all SD I/O cards is active low and the MMC/SD module
provides pull-up resistors on all data lines (SD_DAT [3:0]).
The MMC/SD module samples the level of Pin 8 (SD_DAT [1]/IRQ) into the interrupt detector only during the
interrupt period. At all other times, the MMC/SD module ignores this value.
NOTE:
The interrupt period is applicable for both memory and I/O operations. The
definition of the interrupt period for operations with single blocks is different from
the definition for multiple block data transfers.
20.7.7.2 SD I/O Suspend and Resume
Within a multi-function SD I/O or a card with both I/O and memory functions, there are multiple devices (I/O and
memory) that share access to the MMC/SD bus. To share access to the MMC/SD module among multiple devices,
SD I/O and combo cards optionally implement the concept of suspend/resume. When a card supports
suspend/resume, the MMC/SD module can temporarily halt a data transfer operation to one function or memory
(suspend) to free the bus for a higher priority transfer to a different function or memory. After this higher-priority
transfer is complete, the original transfer is resumed (re-started) where it left off. Support of suspend/resume is
optional on a per-card basis.
To perform the suspend/resume operation on the MMC/SD bus, the MMC/SD module performs the following
steps:
1. Determines the function currently using the SD_DAT [3:0] line(s).
2. Requests the lower priority or slower transaction to suspend.
3. Waits for the transaction suspension to complete.
4. Begins the higher priority transaction.
5. Waits for the completion of the higher priority transaction.
6. Restores the suspended transaction.
20.7.7.3 SD I/O ReadWait
The optional ReadWait (RW) operation is defined only for the SD 1-bit and 4-bit modes. The ReadWait operation
allows the MMC/SD module to signal a card that it is reading multiple registers (IO_RW_EXTENDED, CMD53) to
temporarily stall the data transfer while allowing the MMC/SD module to send commands to any function within
the SD I/O device. To determine when a card supports the ReadWait protocol, the MMC/SD module must test
capability bits in the card internal registers. The timing for ReadWait is based on the interrupt period.
Code Example 20-13 on page 20-56 provides the programming code for the SD I/O RW operation.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-55
Functional Example for the MMC/SD Module
Code Example 20-13. Read_Wait
block_read_with_read_wait_without_DMA(rca, nob, addr_h, addr_l, buswidth)
{
send_cmd_wait_resp(SEND_STATUS, rca, 0x00, 0x01, 0x40);
while(!Ready for data in card status is true)
{
send_cmd_wait_resp(SEND_STATUS, rca, 0x00, 0x01, 0x40);
}
write_reg(NOB, <nob>);
send_cmd_wait_resp(SET_BLOCKLEN, 0x00, 0x0200, 0x01, 0x40);
if(buswidth==4-bit mode)
{
send_cmd_wait_resp(APP_CMD, rca, 0x0, 0x01, 0x40);
send_cmd_wait_resp(SET_BUS_WIDTH, 0x00, 0x02, 0x01, 0x40);
}
write_reg(CMD_DAT_CONT, set bit 10); // Enable Read Wait at the
// following block boundary
if(nob==1)
send_cmd_wait_resp(READ_SINGLE_BLOCK, addr_h, addr_l, 0x09, 0x40);
else
send_cmd_wait_resp(READ_MULTIPLE_BLOCK, addr_h, addr_l, 0x09, 0x40);
if(buswidth==4-bit mode)
{
for(i=0;i<(nob*8);i++)
{
while(!FIFO full in STATUS);// polling instead of irq or dma req
for(j=0;j<32;j++)
{
SDRAM_ADDR[i*32+j] = BUFFER_ACCESS;
}
send_cmd_wait_resp(IO_RW_DIRECT, arg_h, arg_l, 0x5, 0x40);
write_reg(CMD_DAT_CONT, set bit 11 to stop Read Wait);
}
}
else// 1-bit mode
{
for(i=0;i<(nob*32);i++)
{
while(!FIFO full in STATUS);// polling instead of irq or dma req
for(j=0;j<8;j++)
{
SDRAM_ADDR[i*8+j] = BUFFER_ACCESS;
}
send_cmd_wait_resp(IO_RW_DIRECT, arg_h, arg_l, 0x5, 0x40);
write_reg(CMD_DAT_CONT, set bit 11 to stop Read Wait);
}
}
while(!Data Transfer Done in STATUS true);
while(!card bus is stop);
if(nob > 1)
{
send_cmd_wait_resp(STOP_TRANS, 0x00, 0x00, 0x41, 0x40);
}
}
20.7.8 Commands and Responses
This section describes application-specific and general commands in addition to the command types and formats.
Table 20-25 on page 20-58 is a list of all the MMC/SD module commands. Section 20.7.8.5, “Response Formats,”
identifies and describes all command response formats.
MC9328MX1 Reference Manual, Rev. 6.1
20-56
Freescale Semiconductor
Functional Example for the MMC/SD Module
20.7.8.1 Application-Specific and General Commands
The MMC/SD module system is designed to provide a standard interface for a variety of applications types. In this
environment, there is a need for specific customers/applications features. To implement these features, two types of
generic commands are defined in the standard: application-specific commands (ACMD) and general commands
(GEN_CMD).
When the card receives the APP_CMD (CMD55) command, the card expects the next command to be an
application-specific command. ACMDs have the same structure as regular MMC commands and can have the
same CMD number. The card recognizes it as ACMD because it appears after APP_CMD (CMD55). When the
command immediately following the APP_CMD (CMD55) is not a defined application-specific command, the
standard command is used.
For example, when the card has a definition for SD_STATUS (ACMD13), and receives CMD13 immediately
following APP_CMD (CMD55), this is interpreted as SD_STATUS (ACMD13). However, when the card receives
CMD7 immediately following APP_CMD (CMD55) and the card does not have a definition for ACMD7, this is
interpreted as the standard (SELECT/DESELECT_CARD)CMD7.
To use one of the manufacturer specific ACMDs the MMC/SD module must perform the following steps:
1. Send APP_CMD (CMD55).
— The card responds to the MMC/SD module, indicating that the APP_CMD bit is set and an ACMD is
now expected.
2. Send the required ACMD.
— The card responds to the MMC/SD module, indicating that the APP_CMD bit is set and that the
accepted command is interpreted as an ACMD. When a non-ACMD is sent it is handled by the card as
a normal MMC command and the APP_CMD bit in the Card Status Register stays clear.
When an invalid command is sent (neither ACMD nor CMD) it is handled as a standard MMC illegal command
error.
The bus transaction for a GEN_CMD is the same as the single block read or write commands (WRITE_BLOCK,
CMD24 or READ_SINGLE_BLOCK,CMD17). In this case, the argument denotes the direction of the data transfer
rather than the address and the data block has vendor-specific format and meaning.
The card must be selected (in transfer state) before sending GEN_CMD (CMD56). The data block size is defined by
SET_BLOCKLEN (CMD16). The response to GEN_CMD (CMD56) is in R1b format.
20.7.8.2 Command Types
Both application-specific and general commands are divided into the following four types:
•
Broadcast command (BC)—Sent to all cards; no responses returned.
•
Broadcast Command with Response (BCR)—Sent to all cards; responses received from all cards
simultaneously.
•
Addressed (Point-to-Point) Command (AC)—Sent to the card that is selected; does not include a data
transfer on the SD_DAT line(s).
•
Addressed (Point-to-Point) Data Transfer Command (ADTC)—Sent to the card that is selected;
includes data transfer on the SD_DAT line(s).
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-57
Functional Example for the MMC/SD Module
20.7.8.3 Command Formats
All commands are sent over the SD_CMD line, are a fixed length of 48 bits, and are in the format shown in
Table 20-24.
Table 20-24. Command Format
Bit 47
Bit 46
Bits 45–40
Bits 39–8
Bits 7–1
Bit 0
Description
Start Bit
Transmission Bit
Command Index
Argument
CRC7
End Bit
Value
0
1
x
x
x
1
•
Transmission Bit—A 1 indicates a transmission from the MMC/SD module to a card.
•
Command Index—Contains the binary-coded number of the command index.
•
Argument—Some commands require an address that is coded in 32 bits.
20.7.8.4 Commands for the MMC/SD Module
Table 20-25 list all the MMC/SD module’s commands, their type, argument, format, and description.
Table 20-25. Commands for MMC/SD Module
CMD
INDEX
Type
CMD0
BC
CMD1
BCR
CMD2
Argument
Response
Format
Abbreviation
Description
–
GO_IDLE
_STATE
Resets all MMC and SD memory cards to
idle state.
[31:0] OCR
without busy
R3
SEND_OP
_COND
Asks all MMC and SD memory cards in
idle state to send their operation
conditions register contents on the
SD_CMD line.
BCR
[31:0] stuff bits
R2
ALL_SEND_CID
Asks all cards to send their CID numbers
on the SD_CMD line.
CMD3
AC
[31:16] RCA
[15:0] stuff bits
R1
R6 (SD I/O)
SET_RELATIVE
_ADDR
Assigns the argument as the relative
address of the card.
CMD4
BC
[31:16] DSR
[15:0] stuff bits
–
SET_DSR
CMD5
BC
[31:0] OCR
without busy
R4
IO_SEND_OP
_COND
CMD6
[31:0] stuff bits
Programs the DSR of all cards.
Asks all SD I/O cards in idle state to send
their operation conditions register
contents on the SD_CMD line.
Reserved
MC9328MX1 Reference Manual, Rev. 6.1
20-58
Freescale Semiconductor
Functional Example for the MMC/SD Module
Table 20-25. Commands for MMC/SD Module (continued)
CMD
INDEX
Type
CMD7
AC
Argument
[31:16] RCA
[15:0] stuff bits
Response
Format
R1b
CMD8
Abbreviation
SELECT/
DESELECT
_CARD
Description
Toggles a card between stand-by and
transfer states or between programming
and disconnect states. The card is
selected by its own relative address and
is deselected by any other address.
Address 0 deselects all cards.
Reserved
CMD9
AC
[31:16] RCA
[15:0] stuff bits
R2
SEND_CSD
Asks addressed card to sends its
card-specific data (CSD) on the SD_CMD
line.
CMD10
AC
[31:16] RCA
[15:0] stuff bits
R2
SEND_CID
Asks addressed card to send its
card-identification (CID) on the SD_CMD
line.
CMD11
ADTC
[31:0] data
address
R1
READ_DAT
_UNTIL_STOP
Reads data stream from the card, starting
at the given address, until a
STOP_TRANSMISSION command.
CMD12
AC
[31:0] stuff bits
R1b
STOP_
TRANSMISSION
Forces the card to stop transmission.
CMD13
AC
[31:16] RCA
[15:0] stuff bits
R1
SEND_STATUS
Asks addressed card to send its status
register.
CMD14
Reserved
CMD15
AC
[31:16] RCA
[15:0] stuff bits
–
GO_INACTIVE
_STATE
Sets the card to inactive state to protect
the card stack against communication
breakdowns.
CMD16
AC
[31:0] block
length
R1
SET_
BLOCKLEN
Sets the block length (in bytes) for all
future block commands (read and write).
Default block length is specified in the
CSD.
CMD17
ADTC
[31:0] data
address
R1
READ_SINGLE
_BLOCK
Reads a block of the size selected by the
SET_BLOCKLEN command.
CMD18
ADTC
[31:0] data
address
R1
READ_
MULTIPLE
_BLOCK
Transfers data blocks from the card to the
MMC/SD module continuously until
interrupted by a STOP_TRANSMISSION
command.
CMD19
CMD20
Reserved
ADTC
[31:0] data
address
R1
WRITE_DAT_
UNTIL_STOP
Writes data stream from the MMC/SD
module, starting at the given address,
until a STOP_TRANSMISION command
is issued.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-59
Functional Example for the MMC/SD Module
Table 20-25. Commands for MMC/SD Module (continued)
CMD
INDEX
Type
Argument
Response
Format
CMD21:23
Abbreviation
Description
Reserved
CMD24
ADTC
[31:0] data
address
R1
WRITE_BLOCK
Writes a block of the size selected by the
SET_BLOCKLEN command.
CMD25
ADTC
[31:0] data
address
R1
WRITE_
MULTIPLE_
BLOCK
Writes blocks of data continuously until a
STOP_TRANSMISSION command is
issued.
CMD26
ADTC
[31:0] stuff bits
R1
PROGRAM_CID
Programs the card identification register.
CMD26 is issued only once per card. The
card contains hardware to prevent this
operation after the first programming.
Normally CMD26 is reserved for the
manufacturer.
CMD27
ADTC
[31:0] stuff bits
R1
PROGRAM
_CSD
Programs the programmable bits of the
CSD.
CMD28
AC
[31:0] data
address
R1b
SET_WRITE
_PROT
Sets the write protection bit of the
addressed group (when the card provides
write protection features). The properties
of write protection are coded in the CSD
Register (WP_GRP_SIZE).
CMD29
AC
[31:0] data
address
R1b
CLR_WRITE
_PROT
Clears the write protection bit of the
addressed group (when the card provides
write protection features).
CMD30
ADTC
[31:0] write
protect
data address
R1
SEND_WRITE
_PROT
CMD31
Asks the card to send the status of the
write protection bits (when the card
provides write protection features).
Reserved
CMD32
AC
[31:0] data
address
R1
TAG_SECTOR
_START
Selects the start address of the range to
be erased for sector erasing.
CMD33
AC
[31:0] data
address
R1
TAG_SECTOR
_END
Sets the address of the last sector in a
continuous range within the selected
erase group, or the address of a single
sector to be selected for erase.
CMD34
AC
[31:0] data
address
R1
UNTAG_
SECTOR
Removes one previously selected sector
from the erase selection.
CMD35
AC
[31:0] data
address
R1
TAG_ERASE
_GROUP
_START
Selects the start address of the range to
be erased for group erasing.
CMD36
AC
[31:0] data
address
R1
TAG_ERASE
_GROUP_END
Sets the address of the last erase group
within a continuous range to be selected
for erase.
MC9328MX1 Reference Manual, Rev. 6.1
20-60
Freescale Semiconductor
Functional Example for the MMC/SD Module
Table 20-25. Commands for MMC/SD Module (continued)
CMD
INDEX
Type
CMD37
AC
[31:0] data
address
R1
UNTAG_ERASE
_GROUP
CMD38
AC
[31:0] stuff bits
R1b
ERASE
CMD39
AC
[31:16] RCA
[15] register
write flag
[14:8] register
address
[7:0] register
data
R4
FAST_IO
CMD40
BCR
[31:0] stuff bits
R5
GO_IRQ_STATE
Argument
Response
Format
CMD41
CMD42
Abbreviation
Description
Removes one previously selected erase
group from the erase selection.
Erases all selected sectors.
Writes and reads 8-bit (register) data
fields. Addresses a card and a register
and provides the data for writing when the
write flag is set. The R4 response
contains data read from the address
register. Accesses application dependent
registers that are not defined in MMC and
SD standards.
Sets the system into interrupt state.
reserved
ADTC
[31:0] stuff bits
R1b
CMD43:51
LOCK_UNLOCK
Sets/resets the password or lock/unlock
the card. The size of the data block is set
by the SET_BLOCKLEN command.
reserved
CMD52
–
[31:0] stuff bits
R5
IO_RW_DIRECT
Access a single register within the total
128k of register space in any I/O function.
CMD53
–
[31:0] stuff bits
R5
IO_RW_
EXTENDED
Access multiple I/O registers with a single
command. It allows the reading or writing
of a large number of I/O registers.
CMD54
reserved
CMD55
AC
[31:16] RCA
[15:0] stuff bits
R1
APP_CMD
Indicates to the card that the next
command is an application specific
command rather that a standard
command.
CMD56
ADTC
[31:1] stuff bits
[0]: RD/WR1
R1b
GEN_CMD
Transfers a data block to the card or gets
a data block from the card for general
purpose or application specific
commands. The size of the data block is
set by the SET_BLOCKLEN command.
CMD57:63
reserved
ACMDs are preceded by the APP_CMD (CMD55) command. Commands listed below are used for SD only.
SD commands not listed below are not supported in this module.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-61
Functional Example for the MMC/SD Module
Table 20-25. Commands for MMC/SD Module (continued)
CMD
INDEX
Type
ACMD6
AC
[31:2] stuff bits
[1:0] bus width
ACMD13
ADTC
ACMD22
Response
Format
Abbreviation
Description
R1
SET_BUS
_WIDTH
Defines the data bus width to be used for
data transfer.
00 = 1-bit and 10 = 4-bit bus
(The allowed data bus widths are given in
the SCR Register.)
[31:0] stuff bits
R1
SD_STATUS
ADTC
[31:0] stuff bits
R1
SEND_NUM_
WR_SECTORS
Sends the number of written (without
errors) sectors. Responds with 32
bit + CRC data block.
ACMD23
AC
[31:23] stuff bits
[22:0] number
of blocks
R1
SET_WR_BLK
_ERASE
_COUNT
Sets the number of write blocks to be
pre-erased before writing (used for faster
execution of the
WRITE_MULTIPLE_BLOCK (CMD 25). 1
= default (one write block).
ACMD41
BCR
[31:0] OCR
R3
SD_APP_OP
_COND
ACMD42
AC
[31:1] stuff bits
[0] SET_CD
R1
SET_CLR_
CARD_DETECT
ACMD51
ADTC
[31:0] stuff bits
R1
SEND_SCR
1.
Argument
Sends the SD memory card status.
Asks the accessed card to send its
operating condition register (OCR)
content on the SD_CMD line.
Connects (1) or disconnects (0) the 50
kOhm pull-up resistor on the CD/SD_DAT
[3] (pin 1) of the card. The pull-up is used
for card detection.
Reads the SD Configuration Register.
1—The MMC/SD module receives a block of data from the card
0—The MMC/SD module sends a block of data to the card
20.7.8.5 Response Formats
Table 20-25 on page 20-58 lists all commands supported by the MMC/SD module and their response formats. All
responses are sent via the command line SD_CMD. The response transmission always starts with the left bit of the
bit stream corresponding to the response codeword. The code length depends on the response type.
The first two bits of the response are the start bit and the direction bit. The second bit indicates the direction of
transmission. Other response bits are dependent on the type of response.
Table 20-26 through Table 20-32 describe the command response formats. In the tables a value denoted by x
indicates a variable entry. All responses except for type R3 are protected by a CRC. Every command codeword is
terminated by the end bit.
20.7.8.5.1 R1—Normal Response
•
Response length is 48 bits
•
Bits 45:40 contain the binary-coded number of the command index generating the response
•
The status of the card is coded in 32 bits (Card Status Register)
MC9328MX1 Reference Manual, Rev. 6.1
20-62
Freescale Semiconductor
Functional Example for the MMC/SD Module
NOTE:
When data transfer to the card is involved, a busy signal can appear on the data line
after the transmission of each block of data. The MMC/SD module must check for
busy after data block transmission.
Table 20-26. R1 Response
Bit 47
Bit 46
Bits 45-40
Bits 39-8
Bits 7-1
Bit 0
Description
Start Bit
Transmission Bit
Command Index
Card Status
CRC7
End Bit
Value
0
0
x
x
x
1
20.7.8.5.2 R1b—Normal Response with Busy
•
Identical to R1 with an optional busy signal transmitted on the data line
•
Card can become busy after receiving these commands based on its state prior to the command reception.
The MMC/SD module must check for busy at the response.
20.7.8.5.3 R2—CID, CSD Register
•
Response length is 136 bits
•
CID contents sent as response to ALL_SEND_CID (CMD 2) and SEND_CID (CMD10)
•
CSD contents sent as response to SEND_CSD (CMD9)
•
Only the bits [127…1] of the CID and CSD are transferred (the reserved bit [0] of these registers is replaced
by the end bit of the response)
Table 20-27. R2 Response
Bit 135
Bit 134
Bits 133-128
Bits 127-1
Bit 0
Description
Start Bit
Transmission Bit
Reserved
CID/CSD including CRC7
End Bit
Value
0
0
111111
x
1
20.7.8.5.4 R3—OCR Register
•
Response length is 48 bits
•
OCR contents sent as response to SEND_OP_COND (CMD1, MMC) or SD_APP_OP_COND (ACMD41, SD)
Table 20-28. R3 Response
Bit 47
Bit 46
Bits 45-40
Bits 39-8
Bits 7-1
Bit 0
Description
Start Bit
Transmission Bit
Reserved
OCR
Reserved
End Bit
Value
0
0
111111
x
1111111
1
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-63
Functional Example for the MMC/SD Module
20.7.8.5.5 R4—Fast I/O for MMC Only
•
Response length is 48 bits
•
Argument field contains the RCA of the addressed card, the register address to be read-out or written-to, and
the registers’ contents
Table 20-29. R4 Response
Argument Bits 39-8
Bit 47
Bit 46
Bits 45-40
Bits 39-24
Bits 23-16
Bits 15-8
Bits 7-1
Bit 0
Description
Start
Bit
Transmission
Bit
CMD39
RCA
Register
Address
Register
Content
CRC7
End
Bit
Value
0
0
100111
x
x
x
x
1
20.7.8.5.6 R4b—SD I/O Only
Table 20-30. R4b Response
Argument Bits 39-8
Bit 47
Bits
45-40
Bit 46
Bit 39
Bits
38-36
Bit 35
Bits
34-32
Bits
31-8
Bits
7-1
Bit 0
Description
Start
Bit
Direction
Bit
Reserved
Card is
Ready
Number
of I/O Functions
Memory
Present
Stuff
Bits
I/O
ORC
Reserved
End
Bit
Value
0
0
x
x
x
x
x
x
x
1
Bits 7-1
Bit 0
20.7.8.5.7 R5—Interrupt Request (for MMC Only)
•
Response length is 48 bits
•
Argument field contains the RCA of the addressed card
Table 20-31. R5 Response
Argument Bits 39-8
Bit 47
Bit 46
Bits 45-40
Bits 39-24
Bits 23-8
Description
Start Bit
Transmission Bit
CMD40
RCA
Reserved
CRC7
End Bit
Value
0
0
101000
x
x
x
1
20.7.8.5.8 R6—SD I/O Only
Card status bits change when SET_RELATIVE_ADDR (CMD3) is sent to an I/O only card. In this case, the 16 bits
of response are the SD I/O-only values:
•
Bit [15]—COM_CRC_ERROR
MC9328MX1 Reference Manual, Rev. 6.1
20-64
Freescale Semiconductor
Functional Example for the MMC/SD Module
•
Bit [14]—ILLEGAL_COMMAND
•
Bit [13]—ERROR
•
Bit [12:0]—Reserved
Table 20-32. R6 Response
Argument Bits 39-8
Bit 47
Bit 46
Bits 45-40
Bits 39-24
Bits 23-8
Bits 7-1
Bit 0
Description
Start Bit
Direction Bit
CMD3
RCA
Card Status
CRC7
End Bit
Value
0
0
000011
x
x
x
1
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
20-65
Functional Example for the MMC/SD Module
MC9328MX1 Reference Manual, Rev. 6.1
20-66
Freescale Semiconductor
Chapter 21
Memory Stick Host Controller (MSHC) Module
21.1 Overview
This chapter describes how data is transferred to a Memory Stick device and discusses how to configure and
program the Memory Stick Host Controller (MSHC) module.
21.2 Features
The MSHC module provides the following features:
•
Integrated 8-byte (4-half-word) FIFO buffers for transmit and receive
•
Integrated CRC circuit
•
Host bus clock supports HCLK maximum setting (96 MHz)
•
DMA support with selectable DMA request condition based on FIFO status
•
Automatic command execution (can be toggled on/off) when an interrupt from the Memory Stick is detected
•
Built-in Serial Clock Divider: maximum 25 MHz serial data transfer rate
•
Protocol is started by writing to the Memory Stick Command Register from the ARM920T core
•
Data is requested by DMA or interrupt requests to the ARM920T core on entering the data period
•
RDY time-out period can be set by the number of serial clock cycles
•
Interrupt can be output to the ARM920T core when a time-out occurs
•
CRC can be turned off during test mode
•
Two integrated general purpose input ports
•
16-bit host bus access (byte access not supported)
21.3 Block Diagram and Description
Figure 21-1 on page 21-2 shows a high-level block diagram of the MSHC module.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
21-1
Memory Stick Interface
Bus State
Controller
Host Bus
Interface
Registers
Interrupt Request
(MSHC_XINT)
DMA Request
(DMA_REQ [8])
Transfer Protocol
Controller
FIFO
Interrupt Request
Controller
Parallel to
Serial
Serial to
Parallel
MS_SDIO
16-Bit
CRC
SCLKO
Controller
DMA Request
Controller
MS_SCLKO
MS_PI0
General-Purpose
Inputs
Power Save
Controller
HCLK
MS_BS
MS_PI1
SCLK Divider
MS_SCLKI
Figure 21-1. Memory Stick Host Controller Simplified Block Diagram
21.4 Memory Stick Interface
The MC9328MX1 provides support for the standard Memory Stick interface. Devices that conform to both the
Memory Stick form factor and protocol are supported. Figure 21-2 on page 21-3 shows the interface signals
required by the Memory Stick hardware.
MC9328MX1 Reference Manual, Rev. 6.1
21-2
Freescale Semiconductor
Memory Stick Interface
MC9328MX1
Buffer
BS
MS_BS
SDIR
EN
SDIO_OUT
MS_SDIO
SDIO_IN
Memory Stick
Host Controller
MS_SCLKO
SCLKO
MS_SCLKI
SCLKI
PI [0]
MS_PI[0]
PI [1]
MS_PI[1]
Figure 21-2. Memory Stick Interface
NOTE:
The Memory Stick interface signals are multiplexed with GPIO signals. For
detailed information, see Section 32.5.1, “Data Direction Registers,” on page 32-8.
21.4.1 Signal Description
The MSHC module uses the following six signals to interface with the external Memory Stick device:
•
MS_BS—Memory Stick Bus State (Output): Serial bus control signal.
•
MS_SDIO—Memory Stick Serial Data Input/Output.
•
MS_SCLKO—Memory Stick Serial Clock Output: Serial protocol clock signal.
•
MS_SCLKI—Memory Stick External Clock Input: External clock source for the SCLK divider.
•
MS_PI0—General Purpose Input 0. Supports Memory Stick insertion/extraction detection.
•
MS_PI1—General Purpose Input 1. Supports Memory Stick insertion/extraction detection.
21.4.2 Pin Configuration for the MSHC Module
Section 21.4.1, “Signal Description,” includes the pins used by the MSHC module. These pins are multiplexed
with other functions on the device, and must be configured for Memory Stick operation.
NOTE:
The user must ensure that the data direction bits in the GPIO are set to the correct
direction for proper operation. See Section 32.5.1, “Data Direction Registers,” on
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
21-3
Memory Stick Host Controller Operation
page 32-8 for details.
Table 21-1. Pin Configuration
Pin
Setting
Configuration Procedure
MS_BS
Alternate function of
GPIO Port B [13]
1. Clear bit 13 of Port B GPIO In Use register (GIUS_B)
2. Set bit 13 of Port B General Purpose register (GPR_B)
MS_SCLKO
Alternate function of
GPIO Port B [12]
1. Clear bit 12 of Port B GPIO In Use register (GIUS_B)
2. Set bit 12 of Port B General Purpose register (GPR_B)
MS_SDIO
Alternate function of
GPIO Port B [11]
1. Clear bit 11 of Port B GPIO In Use register (GIUS_B)
2. Set bit 11 of Port B General Purpose register (GPR_B)
MS_SCLKI
Alternate function of
GPIO Port B [10]
1. Clear bit 10 of Port B GPIO In Use register (GIUS_B)
2. Set bit 10 of Port B General Purpose register (GPR_B)
MS_PI1
Alternate function of
GPIO Port B [9]
1. Clear bit 9 of Port B GPIO In Use register (GIUS_B)
2. Set bit 9 of Port B General Purpose register (GPR_B)
MS_PI0
Alternate function of
GPIO Port B [8]
1. Clear bit 8 of Port B GPIO In Use register (GIUS_B)
2. Set bit 8 of Port B General Purpose register (GPR_B)
21.5 Memory Stick Host Controller Operation
The MSHC module consists of the following functions:
•
DATA FIFO Operation
•
Bus State Control Operation
•
SDIO Interrupt Operation
•
Reset Operation
•
Power Save Mode Operation
•
Auto Command Function Operation
•
Serial Clock Divider Operation
•
MC9328MX1 System-level DMA Transfer Operation
21.5.1 Data FIFO Operation
The MSHC module features an integrated 8-byte (4-half-word) data FIFO to transmit and receive data. FIFO
access is accomplished through reads from the Memory Stick Receive FIFO Data Register and writes to the
Memory Stick Transmit FIFO Data Register.
For receiving data, the receive buffer empty (RBE) and receive buffer full (RBF) status flags are provided to
determine the type of accesses allowed or expected. When RBE = 0, data reads from the buffer are valid, and when
RBE = 1 data reads from the buffer are invalid. When the receiver FIFO is not full, RBF = 0, and when the receiver
FIFO is full and requires service, RBF = 1.
MC9328MX1 Reference Manual, Rev. 6.1
21-4
Freescale Semiconductor
Memory Stick Host Controller Operation
For transmitting data, the transmit buffer empty (TBE) and transmit buffer full (TBF) status flags are provided.
When TBE = 0, the transmit buffer contains data that is pending transmission and when TBE = 1 the buffer is
empty. When TBF = 1, the transmit buffer is full and data writes to the buffer are ignored. When TBF = 0, there is
room for data in the transmit buffer.
21.5.2 Bus State Control Operation
The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS, MS_SDIO,
and MS_SCLKO (or MS_SCLKI). Communication is always initiated by the MSHC module and operates the bus
in either four-state or two-state access mode.
The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according to its
attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet transmissions occur.
During the BS1, BS2, and BS3 states, packet communications are executed. The BS1, BS2, and BS3 states are
regarded as one packet length and one communication transfer is always completed within one packet length (in
four-state access mode).
The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When an error
occurs during packet communication, the mode is shifted to two-state access mode, and the BS0 and BS1 bus states
are automatically repeated to avoid a bus collision on the SDIO.
21.5.3 MSHC Module Interrupt Operation
The MSHC module provides a single interrupt to the interrupt controller. For interrupt pin assignments, see
Chapter 10, “Interrupt Controller (AITC).”
21.5.3.1 Interrupt Sources
The MSHC module provides interrupt source and status flags. Generally, after MSIRQ assertion (when an interrupt
event occurs), there is distinction in the MSHC module about how to clear the interrupt to the ARM920T processor
(MSIRQ negate) and clearing the interrupt condition in the MSHC module (Interrupt Flag Clear). Table 21-2
summarizes the interrupt sources that assert MSIRQ to the interrupt controller.
Table 21-2. MSHC Module Interrupt Sources Summary
Interrupt
Flag Name
(Register)
MSIRQ Interrupt
Enable Setting(s)
MSIRQ Interrupt
Disable Setting(s)
Interrupt Flag
Clear
INT (MSCS)
MSICS [INTEN] = 1
MSICS [INTEN] = 0
Read MSICS
Depends on
interrupt source
RDY (MSICS)
MSICS [INTEN] = 1
MSCS [SIEN] = 1
MSICS [INTEN] = 0
Write MSCMD
Read MSICS
SIF (MSICS)
MSICS [INTEN] = 1
MSCS [SIEN] = 1
MSC2 [ACD] = 0
MSICS [INTEN] = 0
or
MSC2 [ACD] = 1
Write MSCMD
Read MSICS
MSIRQ Negate
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
21-5
Memory Stick Host Controller Operation
Table 21-2. MSHC Module Interrupt Sources Summary (continued)
Interrupt
Flag Name
(Register)
MSIRQ Interrupt
Enable Setting(s)
MSIRQ Interrupt
Disable Setting(s)
Interrupt Flag
Clear
DRQ (MSICS)1
MSICS [DRQSL] = 1
MSICS [INTEN] = 1
MSICS [INTEN] = 0
or
MSICS [DRQSL] = 0
Write MSTDATA
for Write TPC2
Read MSRDATA
for Read TPC
MSIRQ Negate
Read MSICS
or
Write MSTDATA
for Write TPC
Read MSRDATA
for Read TPC
PIN (MSICS)
MSICS [INTEN] = 1
MSICS [PINEN] = 1
MSPPCD [PIENx]3 = 1
MSICS [INTEN] = 0
Read MSPPCD
Read MSICS
FAE (MSICS)
MSICS [INTEN] = 1
MSFAECS [FAEEN] = 1
MSICS [INTEN] = 0
Read MSFAECS
Read MSICS
CRC (MSICS)
MSICS [INTEN] = 1
MSCS [SIEN] = 1
MSICS [INTEN] = 0
Write MSCMD
Read MSICS
TOE (MSICS)
MSICS [INTEN] = 1
MSCS [SIEN] = 1
MSCS [BSYCNT > 0
MSICS [INTEN] = 0
Write MSCMD
Read MSICS
1.
2.
3.
DRQ (MSICS):
When DAKEN (MSCS) = 0
DRQ (MSICS) = 1 when Rx FIFO receives at least 1 half-word (RFF = don’t care) for receive
DRQ (MSICS) = 1 when Tx FIFO has at least 1 empty slot available (TFE = don’t care) for transmit
When DAKEN (MSCS) = 1
DRQ (MSICS) = 1 when Rx FIFO is full (RFF = 1case) for receive
DRQ (MSICS) = 1 when Tx FIFO is empty (TFE = 1 case) for transmit
or
DRQ (MSICS) = 1 when Rx FIFO receives at least 1 half-word (RFF = 0 case) for receive
DRQ (MSICS) = 1 when Tx FIFO has at least 1 empty slot available (TFE = 0 case) for transmit
TPC, means Transfer Protocol Command
PIENx is used for either PIEN0 or PIEN1 bit of the MSPPCD register
21.5.3.2 SDIO Interrupt Operation
An interrupt transfer (INT) state from the Memory Stick to the MSHC module can occur during BS0, as shown in
Figure 21-3.
MC9328MX1 Reference Manual, Rev. 6.1
21-6
Freescale Semiconductor
Memory Stick Host Controller Operation
BS
BS0
SDIO
INT
1
3
5
7
SCLK
2
4
6
Figure 21-3. Memory Stick Interrupt Transfer State (BS0) Operation
When the Memory Stick detects BS0 at the timing indicated by point 2 in Figure 21-3, the INT transfer state is
started at timing indicated at point 3. The MSHC module can terminate MS_SCLKO after the timing transition
indicated by point 3 (MS_SCLKO = low). When an interrupt occurs, it is reflected in the Memory Stick Interrupt
Control/Status Register and SDIO is asserted high (interrupt) by the Memory Stick. When SDIO = HIGH (INT) is
detected during BS0 the INT bit of the Memory Stick Interrupt Control/Status Register (MSCR) is read and the
interrupt status is checked.
The detection of INT from the Memory Stick occurs in following conditions:
1. MC9328MX1 is in Normal operation mode or Doze mode and the MSHC module is enabled
(MSCEN bit is set).
2. Under condition 1, the MSHC module is in Normal operation mode (PWS bit = 0).
3. The MSHC module recognizes INT when the SDIO remains high for 3 SCLK cycles during BS0.
21.5.4 Reset Operation
The Memory Stick Control/Status Register’s RST bit (MSCS [RST]) provides a mechanism for software resets.
When 1 is written to the RST bit, the MSHC module is reset and an associated I/O reset is initiated.
A value of 1 is maintained for the RST bit for more than SCLK 2 clocks and then must be returned to 0 to perform
reset in synchronization with the clock.
A reset of the MSHC module results in:
1. Register operation (Status after RST = 1 and immediately after RST = 0)
— Memory Stick Command Register (MSCMD) = 0x0000
— Memory Stick Control/Status Register (MSCS) = 0x050A
— Memory Stick Receive FIFO Data Register (MSRDATA) and Memory Stick Transmit FIFO Data
Register (MSTDATA) = 0x0000
— Memory Stick Interrupt Control/Status Register (MSICS) = 0x0080
— Memory Stick Parallel Port Control/Data Register (MSPPCD) = 0x0000
— Memory Stick Control 2 Register (MSC2) = ACD, RED and LEND bit = 0. MSCEN bit is not changed
— Memory Stick Auto Command Register (MSACD) = 0x7001
— Memory Stick FIFO Access Error Control/Status Register (MSFAECS) = 0x0000
— Memory Stick Serial Clock Divider Register (MSCLKD) = no change
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
21-7
Memory Stick Host Controller Operation
— Memory Stick DMA Request Control Register (MSDRQC) = 0x0000
2. Output signal status
— MS_BS —> Low level
— MS_SDIO_OUT —> Low level
— MS_SCLK —> Low level
3. Internal operation
— Internal Interrupt Request signal (MSIRQ) —> High level (Negated)
— Internal DMA Request signal —> High level (Negated)
— The Transmit/Receive FIFOs are cleared
4. The executing protocol is terminated
21.5.5 Power Save Mode Operation
Figure 21-4, “Power Save Mode,” on page 21-8 depicts the Power Save Mode of the MSHC module.
NOTE:
The separate “Power Save Mode” feature of the MSHC module must not be
confused with the power save mode features of the i.MX system as described in
Chapter 12, “Phase-Locked Loop and Clock Controller.”
Entering Power Save Mode
Execute SLEEP for the
SET_CMD to turn the
Memory Stick into SLEEP mode
Set the PWS bit of the
MSCS register to 1
Cancelling Power Save Mode
Set the PWS bit of the
MSCS register to 0
Perform wake-up operations
for the Memory Stick
Figure 21-4. Power Save Mode
After the MSHC module is placed in power save mode (PWS = 1), the Memory Stick cannot be placed in SLEEP
mode because the protocol cannot be started. The user must place the Memory Stick into SLEEP mode before
placing the MSHC module in Power Save Mode (PWS = 1). Also, first cancel Power Save mode (PWS = 0) before
waking up the Memory Stick.
MC9328MX1 Reference Manual, Rev. 6.1
21-8
Freescale Semiconductor
Memory Stick Host Controller Operation
In Power save mode, the MSHC module can detect and MS_PI [1:0] input status interrupt change. Table 21-3
shows i.MX and MSHC module Power Save Mode combination and whether or not MSHC module can detect
them.
Table 21-3. Interrupt Detect Capability on Power Save Mode
MC9328MX1
Power Save Mode
MSHC Module
PWS
MS_PI [1:0]
Interrupt
MS_SDIO
Interrupt
Doze
0 (No PWS)
Detectable
Detectable
Doze
1 (PWS)
Detectable
Not detectable
Sleep
X
Not detectable
Not detectable
21.5.5.1 Register Access During Power Save Mode
Note that the following registers cannot be written while the MSHC module is in Power Save Mode (PWS bit = 1).
•
MSCMD, MSTDATA, MSC2 (except MSCEN bit), MSACD, MSFAECS, and MSDRQC register
21.5.5.2 Register Access while MSHC Module is Disabled
The following register must only be written in MSHC module disable mode (MSCEN bit = 0).
•
SRC bit and DIV [1:0] bits of MSCLKD register
Setting the MSCEN bit from 1 to 0 causes all of MSHC module’s registers to initialize except the MSCEN bit of
MSC2 register and the MSCLKD register.
The following procedure is used to initialize the MSHC module registers for operation:
1. Set the MSCEN bit of MSC2 to 1.
2. Write the value to other registers or other bits of MSC2
3. ...... etc.
21.5.6 Auto Command Function
The MSHC module supports an Auto Command function. Auto Command automatically executes GET_INT or
READ_REG on the host interface for checking status after SET_CMD ends.
With this function, the INT signal from the Memory Stick is detected and the command set in the Memory Stick
Auto Command Register is executed.
The result of an automatically executed command (the value of the read register) is put in the receive data buffer.
The time required and ARM920T processor load is lower with this function than when the ARM920T processor
executes SET_CMD and then GET_INT (or READ_REG).
NOTE:
Be sure that READ_SIZE is set to 4 half-words or less when executing
READ_REG using the ACD.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
21-9
Memory Stick Host Controller Operation
Figure 21-5 on page 21-10 indicates the ARM920T core processing and host interface operations when the ACD is
used. This figure illustrates BLOCK_READ in SET_CMD execution.
When ACD is Not Used
ARM9 Core
When ACD is Used
MSHC Module
BLOCK_READ
Executed
ARM9 Core
BLOCK_READ
Executed
BLOCK_READ
Ends
Wait for
Interrupt
MSHC Module
BLOCK_READ
Ends
Wait for
Interrupt
MSIRQ
Output
Interrupt
Access MSICS
Register
Wait for INT
from MS
Wait for SIF
Interrupt
Wait for INT
from MS
INT from
Memory Stick
MSIRQ
INT from
Memory Stick
Output
Interrupt
Access MSICS
Register
Execute
GET_INT
Execute
GET_INT
GET_INT
Ends
GET_INT
Ends
Wait for
Interrupt
MSIRQ
MSIRQ
Output
Interrupt
Access MSICS
Register
Access MSICS
Register
Access FIFO
(Results of
GET_INT)
Access FIFO
(Results of
GET_INT)
Output
Interrupt
Figure 21-5. Auto Command Function Operation
NOTE:
When a CRC error or TOE occurs processing terminates without performing ACD
and an interrupt signal MSIRQ is output.
Be sure to set the ACD bit of Control register 2 to 1 immediately before executing
ACD (in Figure 21-5 on page 21-10, immediately before executing
BLOCK_READ).
The ACD bit of Memory Stick Control register 2 is automatically set to 0 after
ACD ends (in Figure 21-5 on page 21-10, after GET_INT ends).
MC9328MX1 Reference Manual, Rev. 6.1
21-10
Freescale Semiconductor
Memory Stick Host Controller Operation
21.5.7 Serial Clock Divider Operation
The MC9328MX1 MSHC module provides for flexible transfer rate control with a configurable Serial Clock
Divider. Four settings are supported by the Divider: /1, /2, /4, and /8. When internal HCLK is used, the setting /1 is
provided for manufacturer testing and should not be used.
Figure 21-6 illustrates the MSHC module serial clock divider and Table 21-4 provides the settings.
DIV [1:0]
SRC
DIV 8
1:1
HCLK
internal
0
DIV 4
1:0
MS_SCLKI
external
1
DIV 2
0:1
DIV 1
0:0
SCLK (internal)
MS_SCLKO is generated by this SCLK
Figure 21-6. MSHC Module Serial Clock Divider
Table 21-4. Serial Clock Divider Settings
Source Select Bit
(SRC Bit of MSCLKD)
Divide Bits
(DIV [1:0] of MSCLKD)
Serial Clock
Source
Divide Ratio
SCLKO Output
0
0:0
—
—
Not supported
0
0:1
HCLK
Divide by 2
1/2 HCLK
0
1:0
HCLK
Divide by 4
1/4 HCLK
0
1:1
HCLK
Divide by 8
1/8 HCLK
1
0:0
SCLKI
Divide by 1
SCLKI
1
0:1
SCLKI
Divide by 2
1/2 SCLKI
1
1:0
SCLKI
Divide by 4
1/4 SCLKI
1
1:1
SCLKI
Divide by 8
1/8 SCLKI
21.5.8 System-Level DMA Transfer Operation
The MSHC module DMA request bit is assigned to DMA_REQ [8] in the MC9328MX1 DMA request signals.
Please refer to the Chapter 13, “DMA Controller,” more detail information. Table 21-5 on page 21-12 summarizes
the important data of the MSHC module to configure the DMA general and DMA I/O registers. Because the Rx
and Tx share the same memory address, only 1 DMA channel can be used for DMA transfer—that is, it cannot use
2 DMA channels to handle Rx and Tx separately. This implies that the every time the MSHC module is switched
from the transmit to the receive operation or the vice versa, the DMA registers need to be reconfigured.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
21-11
Programming Model
Table 21-5. MSHC Module DMA Configuration Options
Parameter
MSHC Module RX
MSHC Module TX
FIFO SIZE
16-bit
16-bit
Memory size
32-bit
32-bit
DMA Burst length setting
2 bytes or
8 bytes
2 bytes or
8 bytes
DMA source select setting
8
dma_req [8]
8
dma_req [8]
DMA channels available for use
Channel 0–10
(FIFO to Memory)
Channel 0–10
(Memory to FIFO)
Memory address
User specified
User specified
Peripheral address
0x0021A0004
(MSRDATA)
0x0021A004
(MSTDATA)
Byte count
User specified
User specified
Request Time-out
Supported
Supported
DMA interrupt
Supported
Supported
21.6 Programming Model
The MSHC module includes 11 user-accessible 16-bit registers. All registers are 16 bits wide and 16-bit aligned.
Because the MSHC module does not support byte access, the user must access on a word basis. Table 21-6
summarizes the MSHC module registers and addresses.
Table 21-6. MSHC Module Register Memory Map
Description
Name
Address
Memory Stick Command Register
MSCMD
0x0021A000
Memory Stick Control/Status Register
MSCS
0x0021A002
Memory Stick Transmit FIFO Data Register
MSTDATA
0x0021A004
Memory Stick Receive FIFO Data Register
MSRDATA
0x0021A004
Memory Stick Interrupt Control/Status Register
MSICS
0x0021A006
Memory Stick Parallel Port Control/Data Register
MSPPCD
0x0021A008
Memory Stick Control 2 Register
MSC2
0x0021A00A
Memory Stick Auto Command Register
MSACD
0x0021A00C
Memory Stick FIFO Access Error Control/Status Register
MSFAECS
0x0021A00E
MC9328MX1 Reference Manual, Rev. 6.1
21-12
Freescale Semiconductor
Memory Stick Command Register
Table 21-6. MSHC Module Register Memory Map (continued)
Description
Name
Address
Memory Stick Serial Clock Divider Register
MSCLKD
0x0021A010
Memory Stick DMA Request Control Register
MSDRQC
0x0021A012
21.7 Memory Stick Command Register
The Memory Stick Command Register. The bit position assignments for this register are shown in the following
register display. The settings for this register are described in Table 21-7.
Protocol is started by writing to the Memory Stick Command Register. The data transfer direction is extracted from
the PID code. The CRC16 bit is transferred during the data period even when the data size is 0. Disabled when the
data size is 0 and the NOCRC bit of Control Register 1 is 1. Data cannot be written to the Memory Stick Command
Register when the RDY bit of the MSICS register is 0 (during protocol execution).
MSCMD
BIT
15
14
13
12
11
10
9
8
7
6
PID
TYPE
Addr
0x0021A000
Memory Stick Command Register
5
4
3
2
1
0
DATA SIZE
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 21-7. Memory Stick Command Register Description
Name
Description
Setting
PID
Bits 15–12
Packet ID—Holds the PID code.
0000 = Reserved
0001 = Reserved
0010 = READ_PAGE_DATA
0100 = READ_REG
0111 = GET_INT
1000 = SET_R/W_REG_ADRS
1011 = WRITE_REG
1101 = WRITE_PAGE_DATA
1110 = SET_CMD
1111 = Reserved
Reserved
Bits 11–10
Reserved—These bits are reserved and should read 0.
DATA SIZE
Bits 9–0
Data Size—Sets the data size, in bytes, based on the PID code.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
21-13
Memory Stick Command Register
21.7.1 Memory Stick Control/Status Register
The bit position assignments for the Memory Stick Control/Status Register are shown in the following register
display. The settings for this register are described in Table 21-8.
This register is initialized on power up or when RST bit of Memory Stick Control/Status Register is 1.
MSCS
BIT
TYPE
Addr
0x0021A002
Memory Stick Control/Status Register
15
14
13
12
11
10
9
RST
PWS
SIEN
DAKEN
NOCRC
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
1
0
8
7
6
INT
DRQ
rw
r
r
r
1
0
0
0
BSYCNT
5
4
3
2
1
0
RBE
RBF
TBE
TBF
r
r
r
r
r
0
1
0
1
0
RESET
0x050A
Table 21-8. Memory Stick Control/Status Register Description
Name
Description
Setting
RST
Bit 15
Reset—Resets the MSHC module.
0 = No Reset
1 = Reset MSHC module
PWS
Bit 14
Power Save—Enables/Disables power save mode. Data can
only be written to MSCS register and the MSICS register when
PWS is 1. It is not possible to write to PWS while the protocol is
executing.
0 = Power save disabled
1 = Power save enabled
SIEN
Bit 13
Serial Interface Enable—Enables/Disables serial Interface
output enabled. Normally set to 1 during operation.
0 = Serial interface disabled
1 = Serial interface enabled
DAKEN
Bit 12
XDAK Enable—Configures the internal DMA transfer protocol
by enabling the DMA acknowledge signal XDAK. This XDAK
signal supports 4-half-word burst DMA transfer. Therefore, when
the user needs to configure the module for 4-half-word DMA
burst transfer mode, DAKEN bit must be set to 1. When the user
needs to configure the module for 1-half-word burst DMA
transfer mode, DAKEN bit can be set to either value.
0 = XDAK input disabled
1 = XDAK input enabled
See NOTE of the RFF and TFE bits of the MSDRQC register.
NOCRC
Bit 11
No CRC—Controls whether a CRC will be added to the end of
the data array. Normally, this bit remains at 0 during operation.
0 = CRC on
1 = CRC off
BSYCNT
Bits 10–8
Busy Count—Sets the maximum BSY time-out time to wait until
the RDY signal is output from the card. RDY time-out error
detection is not performed when BSYCNT = 0 and exceeding 5 ×
4 + 2 = 22 SCLK cycles causes a RDY time-out error.
000 = No RDY time-out error detection
performed
001 = 1 × 4 + 2 = 6 SCLK
010 = 2 × 4 + 2 = 10 SCLK
011 = 3 × 4 + 2 = 14 SCLK
100 = 4 × 4 + 2 = 18 SCLK
101 = 5 × 4 + 2 = 22 SCLK
110 = 6 × 4 + 2 = 26 SCLK
111 = 7 × 4 + 2 = 30 SCLK
MC9328MX1 Reference Manual, Rev. 6.1
21-14
Freescale Semiconductor
Memory Stick Command Register
Table 21-8. Memory Stick Control/Status Register Description (continued)
Name
Description
Setting
INT
Bit 7
Interrupt Status—Indicates whether an interrupt condition was
generated. The status will change even when the interrupt itself
is disabled via the INTEN bit of the MSICS register.
0 = No interrupt condition occurred
1 = Interrupt condition occurred
DRQ
Bit 6
DMA Request—Indicates that data was requested. The status
will change even when the interrupt itself is disabled via the
DRQEN bit of the MSICS register.
0 = No DMA request occurred
1 = DMA request occurred
Reserved
Bits 5–4
Reserved—These bits are reserved and should read 0.
RBE
Bit 3
Receive Buffer Empty Flag—Indicates whether there is data in
the receive buffer or not.
0 = Data available in receiver data buffer
1 = Receiver data buffer EMPTY
RBF
Bit 2
Receive Buffer Full Flag—Indicates whether the receive buffer
is full or not.
0 = Receiver data buffer NOT FULL
1 = Receiver data buffer FULL
TBE
Bit 1
Transmit Buffer Empty Flag—Indicates whether there is data in
the transmit buffer or not.
0 = Data in the transmit data buffer
1 = Transmit data buffer EMPTY
TBF
Bit 0
Transmit Buffer Full Flag—Indicates whether the transmit
buffer is full or not.
0 = Transmit data buffer NOT FULL
1 = Transmit data buffer FULL
21.7.2 Memory Stick Transmit FIFO Data Register
The write-only Memory Stick Transmit FIFO Data Register is a 16-bit register. The bit position assignments for
this register are shown in the following register display. The settings for this register are described in Table 21-9.
This register’s value and the FIFO pointers are initialized on power up or when RST bit of Memory Stick
Control/Status Register is 1.
Big/little endian mode of the FIFO DATA register can be set by the LEND bit of the MSC2 register. The default
setting is big-endian. When the LEND bit is 0, the MSHC module handles the FIFO data in big-endian. In
big-endian mode, to send only one byte of data, the data byte must be written in bits 15 through 8. When the LEND
bit is 1, the MSHC module handles the FIFO data in little-endian. In little-endian mode, to send only one byte of
data, the data byte must be written in bits 7 through 0.
When TBF is 1, write data is ignored and it is not stored to the FIFO. The Transmit FIFO DATA register must be
written only when the MSCS register’s DRQ bit or MSICS register’s DRQ bit is 1, and must not be written before
setting a write command to the Memory Stick Command Register.
MSTDATA
BIT
15
Addr
0x0021A004
Memory Stick Transmit FIFO Data Register
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TX DATA BUFFER
TYPE
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
21-15
Memory Stick Command Register
Table 21-9. Memory Stick Transmit FIFO Data Register Description
Name
Description
TX DATA BUFFER
Bits 15–0
Transmit FIFO Data Buffer—Holds data to transmit. If the buffer is full (MSCS bit TBF=1),
the new write data is ignored.
21.7.3 Memory Stick Receive FIFO Data Register
The read-only Memory Stick Receive FIFO Data Register is a 16-bit register. The bit position assignments for this
register are shown in the following register display. The settings for this register are described in Table 21-10.
This register’s value and the FIFO pointers are initialized on power up or when RST bit of Memory Stick
Control/Status Register is 1.
Big/little endian mode of the FIFO DATA register can be set by the LEND bit of the MSC2 register. The default
setting is big-endian. When the LEND bit is 0, the MSHC module handles the FIFO data in big-endian. In
big-endian mode, one data byte incoming via the MS_SDIO pin is received to bits 15 through 8 and next data byte
is received to bits 7 through 0 in MSRDATA. Therefore, when only one byte of data is received from the Memory
Stick, the valid data byte is put into bits 15 through 8 in MSRDATA.
When the LEND bit is 1, the MSHC module handles the FIFO data in little-endian. In little-endian mode, one data
byte incoming via the MS_SDIO pin is received to bits 7 through 0 and next byte data is received to bits 15 through
8 in MSRDATA. Therefore, when only one data byte is received from the Memory Stick, the valid data byte is put
into bits 7 through 0 in MSRDATA.
When RBE is 1, invalid data is read and the FIFO read operation is ignored. The receive FIFO DATA register must
be read only when the MSCS register’s DRQ bit or MSICS register’s DRQ bit is 1.
Memory Stick Receive FIFO Data
Register
MSRDATA
BIT
15
14
13
12
11
10
9
8
7
Addr
0x0021A004
6
5
4
3
2
1
0
RX DATA BUFFER
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 21-10. Memory Stick Receive FIFO Data Register Description
Name
RX DATA BUFFER
Bits 15–0
Description
Receiver FIFO Data Buffer—Holds received data. If the buffer is empty (MSCS bit
RBE=1), the read data is invalid.
21.7.4 Memory Stick Interrupt Control/Status Register
Memory Stick Interrupt Control/Status Register is a 16-bit register. The bit position assignments for this register
are shown in the following register display. The settings for this register are described in Table 21-11.
MC9328MX1 Reference Manual, Rev. 6.1
21-16
Freescale Semiconductor
Memory Stick Command Register
This register is initialized on power up or when RST bit of Memory Stick Control/Status Register is 1. When the
MSICS register is read by the host, the internal interrupt signal MSIRQ is set to high level (negated).
Memory Stick Interrupt Control/Status
Register
MSICS
BIT
TYPE
15
14
13
12
11
10
9
INTEN
DRQSL
PINEN
rw
rw
rw
r
r
r
r
0
0
0
0
0
0
0
8
Addr
0x0021A006
7
6
5
4
RDY
SIF
DRQ
PIN
r
r
r
r
r
0
1
0
0
0
3
2
1
0
FAE
CRC
TOE
r
r
r
r
0
0
0
0
RESET
0x0080
Table 21-11. Memory Stick Interrupt Control/Status Register Description
Name
Description
Setting
INTEN
Bit 15
MSIRQ Enable—Enables/Disables the internal interrupt request MSIRQ signal
output. The MSIRQ interrupt signal is generated when an interrupt condition
occurs after INTEN has been set to 1.
0 = Interrupt disabled
1 = Interrupt enabled
DRQSL
Bit 14
Data Transfer Request MSIRQ Enable—This bit is set to 1 when MSIRQ output
is enabled during data transfer request and it is set to 0 when disabled (initial
value). Also, this bit enables operation of the DRQ bit of MSICS register.
0 = Disabled
1 = Enabled
Note: The DRQSL bit must be disabled if a DMA transfer is used to/from the
MSHC module's FIFO. For data transfers to the FIFO by CPU (non-DMA
operation), the DRQSL bit may be enabled. Setting DRQSL to 1 must be used with
DAKEN = 1. Upon detection of a Data Transfer Request interrupt (DRQ bit in the
MSICS register is set) during the interrupt service routine, the MSICS register must
be read after either writing to MSTDATA (for Write TPC) or reading from
MSRDATA (for Read TPC). This operation is needed to accurately detect the
status of the interrupt status bits.
PINEN
Bit 13
MS_PI [1:0] Level Change MSIRQ Enable—Enables/Disables the MSIRQ output
due to a change in the level at the MS_PI [1:0] pins. When a level change on
MS_PI [1:0] occurs while PINEN = 0, MSIRQ can be output when the user sets
PINEN = 1. To avoid this, the user must wait more than 32 HCLKs before setting
PINEN to 1 after setting the PIENx bit of MSPPCD register to 1.
Reserved
Bits 12–8
Reserved—These bits are reserved and should read 0.
RDY
Bit 7
Ready—Indicates whether communications with the memory stick are in progress
or have ended. Clear by writing to the Memory Stick Command Register. MSIRQ
asserts when RDY transitions from 0 to 1 to signal that the protocol has ended. An
internal interrupt request (MSIRQ) for this bit is negated by reading the MSICS
register (when INTEN = 1).
0 = Disabled
1 = Enabled
0 = Protocol in progress
1 = Protocol ended
Note: Data cannot be written to the Memory Stick Command Register while the
protocol is executing.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
21-17
Memory Stick Command Register
Table 21-11. Memory Stick Interrupt Control/Status Register Description (continued)
Name
Description
Setting
SIF
Bit 6
Serial I/F Interrupt—Indicates that a Serial I/F Interrupt has been generated. For
SIF, an interrupt signal is output separately from RDY. (See Figure 21-3, “Memory
Stick Interrupt Transfer State (BS0) Operation,” on page 21-7).
Cleared by writing to the Memory Stick Command Register.
An internal interrupt request (MSIRQ) for this bit is negated by reading the MSICS
register (when INTEN = 1).
0 = No serial I/F Interrupt
1 = Serial I/F Interrupt
generated
DRQ
Bit 5
Data Transfer Request—Indicates that a data transfer request condition
occurred. The DRQ bit can be changed only when the MSICS bit DRQSL is 1.
Cleared by writing to the FIFO (when PID is a write command) or reading the FIFO
(when PID is a read command), and then an internal interrupt request (MSIRQ) is
negated (when DRQSL = 1). Also the interrupt request (MSIRQ) for this bit is
negated by reading the MSICS register.
0 = No data transfer
request condition
occurs
1 = Data transfer request
condition occurs
NOTE:
When the DRQEN bit of the MSDRQC register is set to 0, the internal DMA
request signal is not generated even when this DRQ bit is 1.
PIN
Bit 4
Parallel Input—Indicates whether the parallel input level has changed on pins
MS_PI [1:0]. This bit is cleared by reading the MSPPCD. An internal interrupt
request (MSIRQ) for this bit is negated by reading the MSICS register (when
INTEN = 1).
0 = Parallel Input level
unchanged
1 = Parallel Input level
change
Reserved
Bit 3
Reserved—This bit is reserved and should read 0.
FAE
Bit 2
FIFO Access Error—Indicates that a FIFO access error occurred. Cleared when
the MSFAECS register is read. This status bit is enabled/disabled with the FAEEN
bit of the MSFAECS register. An internal interrupt request (MSIRQ) for this bit is
negated by reading the MSICS register (when INTEN = 1).
0 = No FIFO access error
1 = FIFO access error
occurred
CRC
Bit 1
CRC Error—Indicates that a CRC error occurred. Cleared when data is written to
the Memory Stick Command Register.
BS output is set to Low level when a CRC error occurs. Also, RDY becomes 1 and
an interrupt signal is output. An internal interrupt request (MSIRQ) for this bit is
negated by reading the MSICS register (when INTEN = 1).
0 = No CRC error
1 = CRC error occurred
TOE
Bit 0
Time-Out Error—Indicates that a BSY time-out error occurred. Cleared when data
is written to the Memory Stick Command Register. Exceeding the number of
clocks set using BSYCNT of the Control register is taken as a card malfunction
and an RDY time-out error (TOE) is sent out. Also, RDY becomes 1 and an
interrupt signal is output.
An internal interrupt request (MSIRQ) for this bit is negated by reading the MSICS
register (when INTEN = 1).
0 = No BSY time-out error
1 = BSY time-out error
21.7.5 Memory Stick Parallel Port Control/Data Register
The Memory Stick Parallel Port Control/Data Register is a 16-bit register. The bit position assignments for this
register are shown in the following register display. The settings for this register are described in Table 21-12.
This register is initialized on power up or when RST bit of Memory Stick Control/Status Register is 1.
MC9328MX1 Reference Manual, Rev. 6.1
21-18
Freescale Semiconductor
Memory Stick Command Register
Parallel input MS_PIN [1:0] is configured using two flip-flops each running at 1/16 clock.
•
The parallel input pin MS_PI [1:0] is pulled up internally.
•
The XPIN [1:0] bit is 1 when the MS_PI [1:0] pin is Low level, and 0 when High level.
It takes 30 HCLK cycles for a value from the parallel input pin PI [1:0] to be reflected on bits XPIN [1:0].This
detection is available in following conditions:
•
MC9328MX1 is in Normal operation mode or Doze mode and the MSHC module must be enabled
(MSCEN bit is set).
•
Under the above condition, MSHC module is in Normal operation mode (PWS bit = 0) or Power Save Mode
(PWS bit = 1).
Memory Stick Parallel Port Control/Data
Register
MSPPCD
BIT
TYPE
15
14
13
12
11
PIEN1
PIEN0
10
9
8
7
6
5
4
XPIN1
XPIN0
Addr
0x0021A008
3
2
1
0
r
r
rw
rw
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 21-12. Memory Stick Parallel Port Control/Data Register Description
Name
Description
Setting
Reserved
Bits 15–14
Reserved—These bits are reserved and should read 0.
PIEN1
Bit 13
PIEN1—Enables/Disables parallel port data input on
MS_PI1.
0 = Parallel input port disabled
1 = Parallel input port enabled
PIEN0
Bit 12
PIEN0—Enables/Disables parallel port data input on
MS_PI0.
0 = Parallel input port disabled
1 = Parallel input port enabled
Reserved
Bits 11–6
Reserved—These bits are reserved and should read 0.
XPIN1
Bit 5
XPIN1—Indicates status of the MS_PI1 pin.
0 = Parallel input port is high level
1 = Parallel input port is low level
XPIN0
Bit 4
XPIN0—Indicates status of the MS_PI0 pin.
0 = Parallel input port is high level
1 = Parallel input port is low level
Reserved
Bits 3–0
Reserved—These bits are reserved and should read 0.
21.7.6 Memory Stick Control 2 Register
The Memory Stick Control 2 Register is a 16-bit register. The bit position assignments for this register are shown
in the following register display. The settings for this register are described in Table 21-13. For other operation
description see Section 21.5.6, “Auto Command Function,” on page 21-9.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
21-19
Memory Stick Command Register
This register is initialized on power up or when RST bit of Memory Stick Control/Status Register is 1.
MSC2
Addr
0x0021A00A
Memory Stick Control 2 Register
BIT
15
14
ACD
RED
rw
rw
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
TYPE
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LEND
MSCEN
r
rw
rw
0
0
0
RESET
0x0000
Table 21-13. Memory Stick Control 2 Register Description
Name
Description
Setting
ACD
Bit 15
Auto Command—Enables/Disables auto command. When set, a
command is automatically executed after an INT is detected from
Memory Stick.
0 = Auto command disabled
1 = Auto command enabled
RED
Bit 14
Rise Edge Data—Sets the edge at which serial data is loaded into the
module.
0 = Serial data loaded at rising edge
of the clock.
1 = Serial data loaded at falling edge
of the clock
Reserved
Bits 13–2
Reserved—These bits are reserved and should read 0.
LEND
Bit 1
Little Endian Enable—Sets the FIFO data to Big or Little Endian.
0 = Big endian
1 = Little endian
MSCEN
Bit 0
MSHC Enable—Enables/Disables the MSHC module.
0 = MSHC module is disabled
1 = MSHC module is enabled
Note:
MSCEN bit is NOT reset by setting RST bit of MSCS register.
21.7.7 Memory Stick Auto Command Register
The Memory Stick Auto Command Register is a 16-bit register. The bit position assignments for this register are
shown in the following register display. The settings for this register are described in Table 21.7.7.
MSACD
BIT
15
14
13
12
11
10
9
8
7
6
APID
TYPE
Addr
0x0021A00C
Memory Stick Auto Command Register
5
4
3
2
1
0
ADATASIZE
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
RESET
0x7001
MC9328MX1 Reference Manual, Rev. 6.1
21-20
Freescale Semiconductor
Memory Stick Command Register
Table 21-14. Memory Stick Auto Command Register Description
Name
Description
Setting
APID
Bits 15–12
Auto Command PID—Sets the PID to be automatically
executed.
Reserved
Bits 11–10
Reserved—These bits are reserved and should read 0.
ADATASIZE
Bits 9–0
Auto Command Data Size—Sets the data size in bytes.
0100 = READ_REG
0111 = GET_INT
All Others Reserved
21.7.8 Memory Stick FIFO Access Error Control/Status Register
The Memory Stick FIFO Access Error Control/Status Register is a 16-bit register. This register’s purpose is to
detect an invalid FIFO access from Host bus side. For example, when Rx FIFO is empty, when Host or DMAC
reads the FIFO, the access means that underrun operation is caused. When Tx FIFO is full, when Host or DMAC
writes the FIFO, the access means that overrun operation is caused. However, because the FIFO’s pointer does not
advance in spite of these invalid accesses, user does not need to clear the FIFO in such cases. This register would
be useful for debugging Host’s and DMAC’s FIFO access operation.
This register is initialized on power up or when RST bit of Memory Stick Control/Status Register is 1.
The bit position assignments for this register are shown in the following register display. The settings for this
register are described in Table 21-15.
Memory Stick FIFO Access Error
Control/Status Register
MSFAECS
BIT
15
14
13
12
11
10
9
8
7
6
5
Addr
0x0021A00E
4
3
2
FAEEN
TYPE
1
0
RUN
TOV
r
r
r
r
r
r
r
rw
r
r
r
r
r
r
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 21-15. Memory Stick FIFO Access Error Control/Status Register Description
Name
Description
Reserved
Bits 15–9
Reserved—These bits are reserved and should read 0.
FAEEN
Bit 8
FIFO Access Error Detection Enable—Enables/Disables the
detection of the host’s invalid FIFO access on bits RUN and TOV.
This bit also enables the FIFO Access Error (FAE) interrupt status
bit (MSICS register).
Reserved
Bits 7–2
Reserved—These bits are reserved and should read 0.
Setting
0 = FIFO access error detection disabled
1 = FIFO access error detection enabled
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
21-21
Memory Stick Command Register
Table 21-15. Memory Stick FIFO Access Error Control/Status Register Description (continued)
Name
Description
Setting
RUN
Bit 1
Rx FIFO Underrun Access—Indicates that the host attempted a
read access when the Rx FIFO is empty (RBE = 1). When this bit is
set, the FAE interrupt status bit is set in MSICS register. This
detection is available in case of FAEEN = 1. Clear by writing 1.
0 = No Rx FIFO access error
1 = Rx FIFO access error
TOV
Bit 0
Tx FIFO Overrun Access—Indicates that the host attempted a
write access when the Tx FIFO is full (TBF = 1). When this bit is set,
the FAE interrupt status bit is also set in MSICS register. This
detection is available in case of FAEEN = 1. Cleared by writing 1.
0 = No Tx FIFO access error
1 = Tx FIFO access error
21.7.9 Memory Stick Serial Clock Divider Register
The Memory Stick Serial Clock Divider Register is a 16-bit register. The bit position assignments for this register
are shown in the following register display. The settings for this register are described in Table 21-16.
This register is initialized on power up.
NOTE:
This register is not initialized by the RST bit of the Memory Stick Control/Status
Register.
MSCLKD
BIT
15
Addr
0x0021A010
Memory Stick Serial Clock Divider Register
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SRC
TYPE
0
DIV
rw
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
RESET
0x0002
Table 21-16. Memory Stick Serial Clock Divider Register Description
Name
SRC
Bit 15
Description
Source Clock of Divider—Selects whether the SCLKI pin or the internal
HCLK will be the source clock of the divider. This bit must not be set to 1
during normal operation.
Setting
0 = Select HCLK as source clock
1 = Reserved
Note: The SRC bit is NOT reset by setting the RST bit of the MSCS
register. A DIV setting of 00 is not supported when SRC = 0.
Reserved
Bits 14–2
Reserved—These bits are reserved and should read 0.
MC9328MX1 Reference Manual, Rev. 6.1
21-22
Freescale Semiconductor
Memory Stick Command Register
Table 21-16. Memory Stick Serial Clock Divider Register Description (continued)
Name
DIV
Bits 1–0
Description
Setting
Divide Ratio—Selects the divide ratio. The divider supports 2n divide
ratio, where N = 0,1,2,3. This bit must not be written after set MSCEN bit
to 1. This bit must be modified only when MSCEN bit is 0(disabled).
00 = Divide by 1
01 = Divide by 2
10 = Divide by 4
11 = Divide by 8
Note: The DIV bits are NOT reset by setting the RST bit of the MSCS
register. A DIV setting of 00 is not supported when SRC = 0.
Note: SRC = 0 and N = 0 (divide by 1) are used only for debugging
purposes.
21.7.10 Memory Stick DMA Request Control Register
The Memory Stick DMA Request Control Register (MSDRQC) is a 16-bit register. The bit position assignments
for MSDRQC are shown in the following register display. The settings for this register are described in
Table 21-17 on page 21-23.
This register is initialized on power up or when RST bit of Memory Stick Control/Status Register is 1.
When the DMA controller is used with the MSHC module, the DMAC Burst Length register value must be either 2
bytes or 8 bytes, because that MSHC module’s FIFO depth is 4 half-words (8 bytes) and the user can configure a
DMA request condition either 1 half-word or 4 half-words. The following describes the MSHC module’s DMA
request operation in a special case.
When MSRDATA is transferred out by DMA Controller and the last burst data is less than the DMAC Burst
Length register’s value, then MSHC module generates a DMA request signal for the last burst transfer when
receive a last byte data on the Read type TPC. This DMA request capability is needed to communicate with DMA
Controller.
Memory Stick DMA Request Control
Register
MSDRQC
BIT
15
14
13
12
11
10
9
8
7
6
5
DRQEN
TYPE
4
Addr
0x0021A012
3
2
1
RFF
0
TFE
rw
r
r
r
r
r
r
r
r
r
r
rw
r
r
r
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 21-17. Memory Stick DMA Request Control Register Description
Name
DRQEN
Bit 15
Description
DMA Request Enable—Enables/Disables operation of the DMA
request signal.
Note:
Reserved
Bits 14–5
Setting
0 = Disable DMA transfer requests
1 = Enable DMA transfer requests
This bit must be set to 1 before initiating DMA transfer.
Reserved—These bits are reserved and should read 0.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
21-23
Programmer’s Reference
Table 21-17. Memory Stick DMA Request Control Register Description (continued)
Name
RFF
Bit 4
Description
Setting
Rx FIFO Full DMA Request—Controls the DMA request signal in case
PID/APID is a read command.
0 = Generate DMA request when
Rx FIFO has received at least
one half-word (use for DMA
transfer of 1 half-word (16 bits))
1 = Generate DMA request when
Rx FIFO is full (4 half-words)
Note: This bit is effective only in case of DAKEN bit of MSCS register
is 1. When DAKEN is 0, MSHC module generates DMA request in
condition of RFF = 0. Therefore, when user need to use in condition of
RFF = 1, DAKEN bit must be set to 1.
Reserved
Bits 3–1
Reserved—These bits are reserved and should read 0.
TFE
Bit 0
Tx FIFO Empty DMA Request—Controls the DMA request signal in
case of PID is a write command.
Note: This bit is effective only in case of DAKEN bit of MSCS register
is 1. When DAKEN is 0, MSHC module generates DMA request in
condition of TFE = 0. Therefore, when user need to use in condition of
TFE = 1, DAKEN bit must be set to 1.
0 = Generate DMA request when at
least 1 empty slot is available in
Tx FIFO (use for DMA transfer
of 1 half-word (16 bits))
1 = Generate DMA request when
Tx FIFO is empty
21.8 Programmer’s Reference
21.8.1 Memory Stick Serial Interface Overview
The Memory Stick Protocol requires 3 interface signal line connections for data transfers: MS_BS, MS_SDIO, and
MS_SCLKO (or MS_SCLKI). MS_PI [1:0] pin inputs detect insertion/removal of Memory Stick. Communication
is always started from the MSHC module and operates the bus in either Four State Access or Two State Access
mode.
MS_BS classifies data on SDIO into one of four states (BS0, BS1, BS2 or BS3) according to the attribute and
transfer direction. BS0 state has no packet communication going on while three states (BS1, BS2, and BS3) have
packet communication being executed. BS1 through BS3 are regarded as one packet and one communication
transfer is always completed within one packet (in Four State Access Mode).
BS
SDIO
BS0
INT
BS1
TPC
BS2
Data or RDY/BSY
BS3
BS0
RDY/BSY or Data
INT
SCLK
Figure 21-7. Memory Stick Bus Four State Access Protocol
MC9328MX1 Reference Manual, Rev. 6.1
21-24
Freescale Semiconductor
Programmer’s Reference
Table 21-18. Serial Interface Signal Specifications
Signal
I/O Host
(MSHC) Side
MS_SDIO
Input/Output
Description
Serial Data Bus. The direction of the data and the data itself changes at each Bus
State. Data is 8 bit, MSB first.
MS_PI0
Input
Parallel Port Data Input. Memory Stick Insertion/Extraction detect 0.
MS_BS
Output
Indicates Bus State (0:3) on SDIO and its timing of starting transfer.
MS_PI1
Input
Parallel Port Data Input. Memory Stick Insertion/Extraction detect 1.
MS_SCLKI
Input
External Clock input to the serial clock generation circuit.
MS_SCLKO
(Serial Clock)
Output
Signal on MS_BS and MS_SDIO is output on trailing edge and input (latched) at
leading edge. It is always output except during BS0 period.
Table 21-19. Four State Access Mode
State
MS_BS
State Name
Description
BS0
LOW
INT Transfer State
A state in which packet communication is not active,
and (MS_SDIO) is used as a transmission line for INT
signals (interruption)
BS1
HIGH
TPC State
BS2
LOW
Hand Shake State (Read Protocol)
Waiting for RDY signal
Data Transfer State (Write Protocol)
Transferring data to Memory Stick
Data Transfer State (Read Protocol)
Reading data from Memory Stick
BS3
HIGH
Handshake State (Write Protocol)
Packet Starts and transfers Transfer Protocol
Command (TPC) from MSHC module to Memory
Stick
Waiting for RDY signal
Memory Stick usually operates in Four State Access Mode from BS0 through BS3. However, when an error occurs
during packet communication, the mode is shifted to Two State Access Mode in which states BS0 and BS1 are
automatically repeated to avoid bus collision on SDIO. See Section 21.8.3, “Transfer Protocol Command (TPC).”
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
21-25
Programmer’s Reference
21.8.2 Protocol
Bus State sequences of write packet which transfer data from the MSHC module to the Memory Stick differ from
those of read packet which transfer data from the Memory Stick to the MSHC module.
21.8.2.1 Write Packet
BS
SDIO
BS0
BS1
INT
BS2
TPC
Memory Stick
Data
BS3
CRC
BS0
RDY/BSY
Host
INT
Memory Stick
SCLK
Figure 21-8. Write Packet
Table 21-20. Write Packet
Bus State
Direction
Description
BS1 (TPC)
MSHC module to
Memory Stick
Transfers Write TPC
BS2 (Data)
MSHC module to
Memory Stick
Transfer Data + CRC to SDIO from HOST
BS3 (Handshake)
Memory Stick to MSHC
module
During BSY output (High/Low signal) on SDIO, Memory Stick decides
whether packet can be terminated normally or not, and reflects the result to
the corresponding register, then outputs RDY (a signal inverting at every
1SCLK) on SDIO.
BS0 (INT)
Memory Stick to MSHC
module
when some interruption factors occur as a result of Memory Stick inner
operation, INT (HIGH signal) is output on SDIO. During BS0 period, SDIO
signal line is used as INT signal line which does not synchronize with SCLK.
MC9328MX1 Reference Manual, Rev. 6.1
21-26
Freescale Semiconductor
Programmer’s Reference
21.8.2.2 Read Packet
BS
BS0
SDIO
BS1
INT
BS2
TPC
Memory Stick
BS3
RDY/BSY
Host
Data
BS0
CRC
INT
Memory Stick
SCLK
Figure 21-9. Read Packet
Table 21-21. Read Packet
Bus State
Direction
Description
BS1 (TPC)
MSHC module to
Memory Stick
Transfers Read TPC.
BS2 (Handshake)
Memory Stick to MSHC
module
Memory Stick outputs BSY (High/Low signal) on SDIO until reading data is
ready to transfer. When ready, it outputs RDY (inverting signal at every
1SCLK).
BS3 (Data)
Memory Stick to MSHC
module
Data + CRC are output on MS_SDIO from Memory Stick.
BS0 (INT)
Memory Stick to MSHC
module
When some interruption factors occur as a result of Memory Stick inner
operation, INT (High) signal is output on SDIO. During BS0 period, SDIO
signal line is used as INT signal line which does not synchronize with SCLK.
21.8.3 Transfer Protocol Command (TPC)
The MSHC module can directly access registers and PageBuffer on the Memory Stick by TPC. The TPC code is
8-bit data which is coded by TPC 4-bit data and one’s complement TPC 4-bit data for error check. TPC 4-bit code
described as follows:
Table 21-22. TPC Code Specification
Name
TPC [3:0]
Operation
Description
READ_PAGE
_DATA
0
0
1
0
Transfer from
Page Buffer
TPC for reading from PageBuffer in units of page
(= 512 bytes). Data is fixed length of 512 bytes + CRC (16-bit).
READ_REG
0
1
0
0
Read register
TPC for reading from the register which address was set.
Address and Data length are set by SET_R/W_REG_ADRS.
Actual Data length: the value which was set + CRC (16bit).
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
21-27
Programmer’s Reference
Table 21-22. TPC Code Specification (continued)
Name
TPC [3:0]
Operation
Description
GET_INT
0
1
1
1
Read INT register
Only INT register: 1 byte is read. Setting by
SET_R/W_REG_ADRS TPC is not necessary.
Read INT register operation is provided as an independent
TPC, as INT register is accessed frequently. Data is fixed
length of 1 byte + CRC (16-bit).
WRITE_PAGE
_DATA
1
1
0
1
Transfer to PageBuffer
TPC for writing to PageBuffer in units of page (= 512 bytes).
Address and Data are fixed length of 512 bytes + CRC (16-bit).
WRITE_REG
1
0
1
1
Write register
TPC for writing to the register whose address was set. Address
and Data length are set by SET_R/W_REG_ADRS. Actual
Data length: the value which was set + CRC (16-bit).
SET_R/W_
REG_ADRS
1
0
0
0
Address setting of
READ_REG
WRITE_REG
TPC for setting values which determine the register accessed
by WRITE_REG and READ_REG.
Values to be set are the following 4 bytes (fixed length). Data is
fixed length of 4 bytes + CRC (16-bit).
READ_REG:
- Starting address for READ_REG: Starting address
of the register to be read
- Consecutive size for READ_REG: The number of registers to
be read consecutively.
WRITE_REG:
- Starting address for WRITE_REG: Starting address of the
register to be written.
- Consecutive size for WRITE_REG: The number of registers
to be written consecutively.
SET_CMD
1
1
1
0
Set CMD
CMD to be executed by Flash Memory Controller, such as
operation for Flash Memory is transferred.
Data is fixed length of CMD (8bit) + CRC (16-bit).
Flash memory controller starts operation when CMD is set by
this TPC, and posts the result by INT.
Reserved
0
0
0
1
—
—
21.8.4 Protocol Error
21.8.4.1 Overview
Because High and Low MS_BS signals express Bus States respectively, bus collision occurs when a difference in
Bus State between Host and Memory Stick arises for some cause. To avoid this, Memory Stick shifts to Two State
Access Mode automatically when an error occurs in a packet.
MC9328MX1 Reference Manual, Rev. 6.1
21-28
Freescale Semiconductor
Programmer’s Reference
BS
BS0
BS1
SDIO
BS0
BS1
TPC
TPC
Z
Host
BS0
Memory Stick
Host
Z
SCLK
Figure 21-10. Two State Access Mode
In Two State Access Mode, operation is performed with recognition that MS_BS = LOW is BS0 and MS_BS =
HIGH is BS1.
Table 21-23. Bus State in Two State Access Mode
Bus State
Direction
Description
BS0
—
Under normal conditions, BS0 is regarded as high impedance state,
regardless of INT signal output period. There is no output even when INT
signal is active.
BS1 (TPC)
MSHC module to
Memory Stick
Memory Stick accepts TPC.
When Memory Stick shifts to Two State Access Mode, time-out occurs during the Handshake State of the packet
on Host, and the failure of communicating packet is detected.
BS
BS0
BS1
Host–BS2
Memory Stick–BS0
SDIO
Time-out on Host
BS0
Data
TPC
Memory Stick
Host–BS1
(memory
stick–BS1)
Host
Z
SCLK
Figure 21-11. Write Packet Time-Out
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
21-29
Programmer’s Reference
Host–BS2
BS
BS0
BS1
SDIO
Memory Stick–BS0
Time-out on Host
BS0
TPC
Memory Stick
Host
Z
SCLK
Figure 21-12. Read Packet Time-Out
NOTE:
When a time-out occurs in BS2 of a read packet, the bus state does not shift to BS3.
21.8.4.2 Two State Access Mode Factor
Table 21-24. Two State Access Mode Factor
Error
TPC Code Error
Description
4 Bit Error Check
Code Error
—
Undefined TPC
—
Unacceptable TPC
TPC is received, however the Memory Stick is not capable of
executing it due to internal status.
Short TPC State
When BS1 is under 8 SCLKO.
Write Packet CRC
Error
CRC error occurred in the data transferred from MSHC module.
Short Data State
Not all data are accepted because data state of BS is shorter than the
setting on Memory Stick.
Handshake Error
Short Handshake
State
BS is switched before the output of RDY, though Memory Stick is
operating normally.
Power Supply On
—
—
Data Error
When no error occurs in BS1, the bus state shifts to BS2, BS3 and enters Four State Access Mode. When an error
described above occurs, it returns to Two State Access Mode again.
MC9328MX1 Reference Manual, Rev. 6.1
21-30
Freescale Semiconductor
Programmer’s Reference
21.8.5 Signal Timing
21.8.5.1 Timing
BS
SDIO
D2
D1
D0
1
D7
D6
3
SCLK
2
4
1 Change timing of BS
2 Timing to detect BS change on Memory Stick side
1 Timing to output LSB of final data
2 Timing to latch LSB of final data
3 Timing to output MSB of first data
4 Timing to latch MSB of first data
Figure 21-13. Signal Timing
•
Timing of SCLK, SDIO and BS
— Sender outputs SDIO signal at SCLK fall (output side), and latches it at SCLK rise (input side).
•
BS signal is output synchronizing with SCLK fall
•
Relation between BS change and data
— When BS changes to shift to the next state, and Bus State is not extended, new BS is output
synchronizing with the output timing of final data LSB on SDIO in the previous state.
•
TPC, data and CRC are MSB first
21.8.5.2 Bus State Extension
When it is difficult to switch BS signal in the same timing as the final data, in TPC State and Data State, it is
possible to continue that Bus State without switching the BS signal even after the final data transfer. However, in
Data State, HIGH must be output on SDIO during the period when Bus State is continued without switching after
the transfer of the last bit. In TPC State, signals on SDIO in this period are not prescribed.
BS
SDIO
D0
D7
D6
SCLK
Figure 21-14. Bus State Extension
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
21-31
Programmer’s Reference
21.8.5.3 Data Transfer Extension
When data transferred from the MSHC module cannot be output to catch the next fall of SCLK, or data transferred
from the Memory Stick to the MSHC module cannot be received from the rise of next SCLK because the MSHC
module buffer is full, the next data transfer can be delayed by keeping SCLK high.
BS
SDIO
D1
D0
D7
D6
SCLK
Figure 21-15. SCLK Extension for Data Wait
MC9328MX1 Reference Manual, Rev. 6.1
21-32
Freescale Semiconductor
Chapter 22
Pulse-Width Modulator (PWM)
The pulse-width modulator (PWM) of the MC9328MX1 is optimized to use 16-bit resolution and a 4 × 16 data
FIFO to generate high quality sound from stored audio files and to generate tones. Figure 22-1 illustrates the block
diagram of the pulse-width modulator.
PERCLK1
CLK32
MPU Interface
4-Word FIFO
CLKSRC
Sample Compare
Divider
Prescaler
PCLK
Output
Control
PWMO
Counter
Period
Figure 22-1. Pulse-Width Modulator Block Diagram
22.1 Introduction
The PWM can be programmed to select one of two clock signals as its source frequency. The selected clock signal
is passed through a divider and a prescaler before being input to the counter. The output is available at the
pulse-width modulator output (PWMO) external pin.
22.2 PWM Signals
22.2.1 Clock Signals
As shown in Figure 22-1, the clock source (CLKSRC) bit in the PWM control (PWMC) register selects the source
clock—PERCLK1 (the default) or CLK32—to be used by the PWM. The selected clock signal is then sent through
a divider and a prescaler to produce the PCLK signal.
The clock selection (CLKSEL) field in the PWMC selects the frequency of the output of the divider chain. The
incoming clock source is divided by a binary value between 2 and 16.
For 16 kHz audio applications, CLKSEL = 01, divide by 4. For DC-level applications, CLKSEL = 11, divide by
16. See Table 22-7 on page 22-8 for a complete list of settings for the PWMC register.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
22-1
PWM Operation
Adjust the 7-bit prescaler to achieve lower sampling rates by programming the PRESCALER field in the PWMC
register with any number between 0 and 127 to scale down the incoming clock source by a corresponding factor of
1 to 128.
22.2.2 Pin Configuration for PWM
Figure 22-1 shows the signals used for the PWM module. The PWMO pin is multiplexed with other functions on
the device, and must be configured for PWM operation. Table 22-1 describes the procedure for the PWM pin
configuration.
NOTE:
The user must ensure that the data direction bit in the GPIO is set to the correct
direction for proper operation. See Section 32.5.1, “Data Direction Registers,” on
page 32-8 for details.
Table 22-1. Pin Configuration
Pin
Setting
PWMO
Primary function of
GPIO Port A [2]
Configuration Procedure
1.Clear bit 2 of Port A GPIO In Use register (GIUS_A)
2. Clear bit 2 of Port A General Purpose register (GPR_A)
22.3 PWM Operation
The pulse-width modulator has three modes of operation—playback, tone, and digital-to-analog (D/A) converter.
22.3.1 Playback Mode
In playback mode, the pulse-width modulator uses the data from a sound file to output the resulting audio through
an external speaker. To reproduce the best quality of sound from a sound file, it is necessary to use a sampling
frequency that is equal to or an even multiple of the sampling frequency used to record the sound.
The PWM produces variable-width pulses at a constant frequency. The width of the pulse is proportional to the
analog voltage of a particular audio sample. At the beginning of a sample period cycle, the PWMO pin is set to 1
and the counter begins counting up from 0x0000. The sample value is compared on each count of the prescaler
clock. When the sample and count values match, the PWMO signal is cleared to 0. The counter continues counting,
and when it overflows from 0xFFFF to 0x0000, another sample period cycle begins. The prescaler clock (PCLK)
runs 256 times faster than the sampling rate when the PERIOD field of the PWM period (PWMP) register is at its
maximum value.
Figure 22-2 illustrates how variable width pulses affect an audio waveform.
Pulse-Width Modulation Stream
Filtered Audio
Figure 22-2. Audio Waveform Generation
MC9328MX1 Reference Manual, Rev. 6.1
22-2
Freescale Semiconductor
Programming Model
Digital sample values are loaded into the pulse-width modulator as 16-bit words (big endian format). A 4-word
FIFO minimizes interrupt overhead. A maskable interrupt is generated when there are 1 or 0 words in the FIFO, in
which case the software can write two 16-bit samples into the FIFO. Interrupts occur every 50 μs, if the REPEAT
field of the PWMC register is set to 0, when a 16 kHz sampling frequency is being used to play back sampled data,
when writing two 16-bit data at each interrupt.
22.3.2 Tone Mode
When the value stored in the PWMP register < 0xFFFE, the PWM operates in tone mode and generates a
continuous tone at a single frequency which is determined by the settings in the PWM registers.
22.3.3 Digital-to-Analog Converter (D/A) Mode
The pulse-width modulator outputs a frequency with a different pulse width if a low-pass filter is added at the
PWMO signal. It produces a different DC level when programmed using the sample fields in the PWM sample
(PWMS) register. When used in this manner, the PWM becomes a D/A converter.
22.4 Programming Model
The PWM module includes 4 user-accessible 32-bit registers. Table 22-2 summarizes these registers and their
addresses.
Table 22-2. PWM Module Register Memory Map
Description
Name
Address
PWM Control Register
PWMC
0x00208000
PWM Sample Register
PWMS
0x00208004
PWM Period Register
PWMP
0x00208008
PWM Counter Register
PWMCNT
0x0020800C
22.4.1 PWM Control Register
The PWM Control Register controls the operation of the pulse-width modulator, and it also contains the status of
the PWM FIFO. The register bit assignments are shown in the following register display. The register settings are
described in Table 22-3 on page 22-4.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
22-3
Programming Model
PWMC
BIT
Addr
0x00208000
PWM Control Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
HCTR BCTR
TYPE
SWR
r
r
r
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
IRQ
IRQ
EN
FIFO
AV
EN
REPEAT
CLKSEL
w
rw
RESET
0x0000
BIT
15
14
13
12
CLK
SRC
TYPE
11
10
9
8
PRESCALER
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
r
rw
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
RESET
0x0020*
Table 22-3. PWM Control Register Description
Name
Description
Settings
Reserved
Bits 31–19
Reserved—These bits are reserved and should read 0.
HCTR
Bit 18
Halfword FIFO Data Swapping—Swapping upper and lower write data
which to PWMS.
0 = Do not swap
1 = Swap
BCTR
Bit 17
Byte FIFO Data Swapping—Swapping bits[15:8] and bits[7:0] data
which from PWMS to FIFO.
0 = Do not swap
1 = Swap
SWR
Bit 16
Software Reset—Enables a reset of the PWM. After five system clock
cycles, the SWR bit releases automatically.
0 = No action taken
1 = Reset the PWM
CLKSRC
Bit 15
Clock Source—Selects the clock source for the pulse-width modulator.
0 = Selects PERCLK1 source
1 = Selects CLK32 source
The CLK32 frequency is
determined by the frequency of
the reference crystal.
PRESCALER
Bits 14–8
Prescaler—Scales down the incoming clock by dividing the incoming clock signal by the value contained in
the PRESCALER field+1. The prescaler is normally used to generate a low single-tone PWMO signal. For
voice modulation, these bits are set to 0 (divide by 1).
IRQ
Bit 7
Interrupt Request—Indicates that the FIFO contains 1 or 0 words,
which signals the need to write no more than three 16-bit words into the
PWMS register. The IRQ bit automatically clears itself after this register
is read, eliminating an extra write cycle in the interrupt service routine. If
the IRQEN bit is 0, the IRQ bit can be polled to indicate the status of the
period comparator. For debugging purposes, the IRQ bit can be set to
immediately post a PWM interrupt.
0 = FIFO contains more than 1
sample word
1 = FIFO contains 1 or 0 sample
words
IRQEN
Bit 6
Interrupt Request Enable—Enables/Disables the pulse-width
modulator interrupt. When IRQEN is low, the interrupt is disabled.
0 = PWM interrupt is disabled
1 = PWM interrupt is enabled
MC9328MX1 Reference Manual, Rev. 6.1
22-4
Freescale Semiconductor
Programming Model
Table 22-3. PWM Control Register Description (continued)
Name
Description
Settings
FIFOAV
Bit 5
FIFO Available—Indicates that the FIFO is available for at least one word of sample data. Data words can
be written to the FIFO as long as the FIFOAV bit is set. If the FIFO is written to while the FIFOAV bit is
cleared, the write is ignored.
EN
Bit 4
Enable—Enables/Disables the pulse-width modulator. If the EN bit is
not enabled, writes to any register in the PWM are ignored.
When the pulse-width modulator is disabled, it is in low-power mode, the
output pin is forced to 0, and the following events occur:
• The clock prescaler is reset and frozen.
• The counter is reset and frozen.
• The FIFO is flushed.
When the pulse-width modulator is enabled, it begins a new period, and
the following events occur:
• The output pin is set to start a new period.
• The prescaler and counter are released and begin counting.
• The IRQ bit is set, therefore indicating that the FIFO is empty.
0 = PWM is disabled
1 = PWM is enabled
REPEAT
Bits 3–2
Sample Repeats—Selects the number of times each sample is
repeated. The repeat feature reduces the interrupt overhead, reduces
CPU loading when audio data is played back at a higher rate, and allows
the use of a lower-cost low-pass filter.
00 = No repeat
(play the sample once)
01 = Repeat one time
(play the sample twice)
10 = Repeat three times (play
the sample four times)
11 = Repeat seven times (play
the sample eight times)
For example, if the audio data is sampled at 8 kHz and the data is
played back at 8 kHz again, an 8 kHz hum (carrier) is generated during
playback. To filter this carrier, a high-quality low-pass filter is required.
For a higher playback rate, it is possible to reconstruct samples at
16 kHz by using the sample twice. This method shifts the carrier from an
audible 8 kHz to a less sensitive 16 kHz frequency range, resulting in
better output sound quality.
CLKSEL
Bits 1–0
Clock Selection—Selects the output of the sampling clock.
The approximate sampling rates are calculated using a 16 MHz clock
source (PRESCALER = 0 and PERIOD = default).
00 = Divide by 2—produces a
32 kHz sampling rate
01 = Divide by 4—produces a
16 kHz sampling rate
10 = Divide by 8—produces an
8 kHz sampling rate
11 = Divide by 16—provides a
4 kHz sampling rate
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
22-5
Programming Model
22.4.1.1 HCTR and BCTR Bit Description
When the endian format of the wave data stored in external memory is not compatible to the system endian format,
these two bits control the swapping of the data to the PWM FIFO. The data port size used by the external memory
must be used in conjunction with these two bits.
Table 22-4. HCTR and BCTR Bit Swapping
HCTR
BCTR
Swapping
0
0
No
0
1
Swapping bits[15:8] to bits[7:0] and bits[7:0] to bits[15:8]
1
0
Swapping bits[31:16] to bits[15:0] and bits[15:0] to bits[31:16]
1
1
Swapping bit[s31:16] to bits[15:0] and bits[15:0] to bits[15:0] to bits[31:16], and after that
swapping bits[15:8] to bits[7:0] and bits[7:0] to bits[15:8]
Note: Only the lower 16 bits are passed to PWM 16-bit FIFO after swapping.
22.4.2 PWM Sample Register
The PWM Sample Register is the input to the FIFO. Writing successive audio sample values to this register
automatically loads the values into the FIFO. The pulse-width modulator free-runs at the last set duty-cycle setting
until the FIFO is reloaded or the pulse-width modulator is disabled. If the value in this register is higher than the
PERIOD + 1, the output is never reset, which results in a 100% duty-cycle.
The register bit assignments are shown in the following register display. The register settings are described in
Table 22-5.
PWMS
Addr
0x00208004
PWM Sample Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SAMPLE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RESET
0xXXXX
MC9328MX1 Reference Manual, Rev. 6.1
22-6
Freescale Semiconductor
Programming Model
Table 22-5. PWM Sample Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
SAMPLE
Bits 15–0
Sample—Contains a two-sample word. This word is written to the pulse-width modulator.
22.4.3 PWM Period Register
This register controls the pulse-width modulator period. When the counter value matches PERIOD + 1, the counter
is reset to start another period. The following equation applies:
PWMO (Hz) = PCLK (Hz) ÷ (PERIOD + 2)
Eqn. 22-1
Writing 0xFFFF to this register achieves the same result as writing 0xFFFE.
The register bit assignments are shown in the following register display. The register settings are described in
Table 22-6.
PWMP
Addr
0x00208008
PWM Period Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
PERIOD
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
RESET
0xFFFE
Table 22-6. PWM Period Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
PERIOD
Bits 15–0
Period—Represents the pulse-width modulator’s period control value.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
22-7
Programming Model
22.4.4 PWM Counter Register
The read-only PWM Counter Register contains the current count value and can be read at any time without
disturbing the counter. The register bit assignments are shown in the following register display. The register
settings are described in Table 22-7.
PWMCNT
Addr
0x0020800C
PWM Counter Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
COUNT
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 22-7. PWM Counter Register Description
Name
Description
Reserved
Bits 31–16
Reserved—These bits are reserved and should read 0.
COUNT
Bits 15–0
Count—Represents the current count value.
MC9328MX1 Reference Manual, Rev. 6.1
22-8
Freescale Semiconductor
Chapter 23
Real-Time Clock (RTC)
This chapter discusses how to operate and program the real-time clock (RTC) module that maintains the system
clock, provides stopwatch, alarm, and interrupt functions, and supports the following features:
•
Full clock—days, hours, minutes, seconds
•
Minute countdown timer with interrupt
•
Programmable daily alarm with interrupt
•
Sampling timer with interrupt
•
Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts
•
Operation at 32.768 kHz or 32 kHz (determined by reference clock crystal)
As shown in the RTC block diagram (Figure 23-1), the real-time clock module consists of the following blocks:
•
Prescaler
•
Time-of-day (TOD) clock counter
•
Alarm
•
Sampling timer
•
Minute stopwatch
•
Associated control and bus interface hardware
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
23-1
Operation
CLK2HZ
32.768K OR 32K
CLK32HZ
TOD CLOCK
SAMPLING
TIMER
PRESCALER
1 PPS
1 PPM
MINUTE
1 PPH
HOUR
1 PPD
DAY
CLOCK
CONTROL
RTC_INT
RTC_SAM_INT
SECOND
INTERRUPT
CONTROL
INTERRUPT
ENABLE
INTERRUPT
STATUS
ALARM COMPARATOR
SECOND
LATCH
MINUTE
LATCH
HOUR
LATCH
ADDRESS
IPBUS
DECODE
DATA
MINUTE STOPWATCH
BUS CONTROL
Figure 23-1. Real-Time Clock Block Diagram
23.1 Operation
The prescaler converts the incoming crystal reference clock to a 1 Hz signal which is used to increment the
seconds, minutes, hours, and days TOD counters. The alarm functions, when enabled, generate RTC interrupts
when the TOD settings reach programmed values. The sampling timer generates fixed-frequency interrupts, and
the minute stopwatch allows for efficient interrupts on minute boundaries.
23.1.1 Prescaler and Counter
The prescaler divides the reference clock down to 1 Hz. The reference frequencies of 32.768 kHz and 32 kHz are
supported. The prescaler stages are tapped to support the sampling timer.
The counter portion of the RTC module consists of four groups of counters that are physically located in three
registers:
•
The 6-bit seconds counter is located in the SECONDS register
•
The 6-bit minutes counter and the 5-bit hours counter are located in the HOURMIN register
•
The 9-bit day counter is located in the DAYR register
These counters cover a 24-hour clock over 512 days. All three registers can be read or written at any time.
Interrupts signal when each of the four counters increments, and can be used to indicate when a counter rolls over.
For example, each tick of the seconds counter causes the 1 Hz interrupt flag to be set. When the seconds counter
rolls from 59 to 00, the minute counter increments and the MIN interrupt flag is set. The same is true for the minute
counter with the HR signal, and the hour counter with the DAY signal.
MC9328MX1 Reference Manual, Rev. 6.1
23-2
Freescale Semiconductor
Operation
23.1.2 Alarm
There are three alarm registers that mirror the three counter registers. An alarm is set by accessing the real-time
clock alarm registers (ALRM_HM, ALRM_SEC, and DAYALARM) and loading the exact time that the alarm
should generate an interrupt. When the TOD clock value and the alarm value coincide, if the ALM bit in the
real-time clock interrupt enable register (RTCIENR) is set, an interrupt occurs.
NOTE:
If the alarm is not disabled, it will reoccur every 512 days. If a single alarm is
desired, the alarm function must be disabled through the RTC Interrupt Enable
register (RTCIENR).
23.1.3 Sampling Timer
The sampling timer is designed to support application software. The sampling timer generates a periodic interrupt
with the frequency specified by the SAMx bits of the RTCIENR register. This timer can be used for digitizer
sampling, keyboard debouncing, or communication polling. The sampling timer operates only if the real-time
clock is enabled. Table 23-1 lists the interrupt frequencies of the sampling timer for the possible reference clocks.
Multiple SAMx bits may be set in the RTC Interrupt Enable Register (RTCIENR). The corresponding bits in the
RTC Interrupt Status Register (RTCISR) will be set at the noted frequencies.
Table 23-1. Sampling Timer Frequencies
Sampling
Frequency
32.768 kHz
Reference Clock
32 kHz
Reference Clock
SAM7
512 Hz
500 Hz
SAM6
256 Hz
250 Hz
SAM5
128 Hz
125 Hz
SAM4
64 Hz
62.5 Hz
SAM3
32 Hz
31.25 Hz
SAM2
16 Hz
15.625 Hz
SAM1
8 Hz
7.8125 Hz
SAM0
4 Hz
3.90625 Hz
23.1.4 Minute Stopwatch
The minute stopwatch performs a countdown with a one minute resolution. It can be used to generate an interrupt
on a minute boundary—for example, to turn off the LCD controller after five minutes of inactivity, program a
value of 0x04 into the Stopwatch Count (CNT) field of the Stopwatch Minutes (STPWCH) register (see
Table 23-12 on page 23-16 for a complete list of settings for the STPWCH register). At each minute, the value in
the stopwatch is decremented. When the stopwatch value reaches -1, the interrupt occurs. The value of the register
does not change until it is reprogrammed. Note that the actual delay includes the seconds from setting the
stopwatch to the next minute tick.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
23-3
Programming Model
23.2 Programming Model
The RTC module includes ten 32-bit registers. Table 23-2 summarizes these registers and their addresses.
Table 23-2. RTC Module Register Memory Map
Description
Name
Address
RTC Days Counter Register
DAYR
0x00204020
RTC Hours and Minutes Counter Register
HOURMIN
0x00204000
RTC Seconds Counter Register
SECONDS
0x00204004
RTC Day Alarm Register
DAYALARM
0x00204024
RTC Hours and Minutes Alarm Register
ALRM_HM
0x00204008
RTC Seconds Alarm Register
ALRM_SEC
0x0020400C
RTC Control Register
RCCTL
0x00204010
RTC Interrupt Status Register
RTCISR
0x00204014
RTC Interrupt Enable Register
RTCIENR
0x00204018
Stopwatch Minutes Register
STPWCH
0x0020401C
23.2.1 RTC Days Counter Register
The real-time clock days counter register (DAYR) is used to program the day for the TOD clock. When the HOUR
field of the HOURMIN register rolls over from 23 to 00, the day counter increments. It can be read or written at
any time. After a write, the time changes to the new value. This register cannot be reset because the real-time clock
is always enabled at reset.
NOTE:
This day counter only supports halfword and word write operations. That means
that all 9 bits must be set simultaneously.
MC9328MX1 Reference Manual, Rev. 6.1
23-4
Freescale Semiconductor
Programming Model
DAYR
Addr
0x00204020
RTC Days Counter Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DAYS
TYPE
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
?
?
?
?
?
?
?
?
?
RESET
0x0???
Table 23-3. RTC Days Counter Register Description
Name
Description
Reserved
Bits 31–9
Reserved—These bits are reserved and should read 0.
DAYS
Bits 8–0
Day Setting—Indicates the current day count.
Settings
DAYS can be set to any value between 0
and 511.
23.2.2 RTC Hours and Minutes Counter Register
The real-time clock hours and minutes counter register (HOURMIN) is used to program the hours and minutes for
the TOD clock. It can be read or written at any time. After a write, the time changes to the new value. This register
cannot be reset because the real-time clock is always enabled at reset.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
23-5
Programming Model
HOURMIN
Addr
0x00204000
RTC Hours and Minutes Counter Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
HOURS
TYPE
MINUTES
r
r
r
rw
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
0
0
0
?
?
?
?
?
0
0
?
?
?
?
?
?
RESET
0x????
Table 23-4. RTC Hours and Minutes Counter Register Description
Name
Description
Settings
Reserved
Bits 31–13
Reserved—These bits are reserved and should read 0.
HOURS
Bits 12–8
Hour Setting—Indicates the current hour.
Reserved
Bits 7–6
Reserved—These bits are reserved and should read 0.
MINUTES
Bits 5–0
Minute Setting—Indicates the current minute.
HOURS can be set to any value between 0 and 23.
MINUTES can be set to any value between 0 and 59.
MC9328MX1 Reference Manual, Rev. 6.1
23-6
Freescale Semiconductor
Programming Model
23.2.3 RTC Seconds Counter Register
The real-time clock seconds register (SECONDS) is used to program the seconds for the TOD clock. It can be read
or written at any time. After a write, the time changes to the new value. This register cannot be reset because the
real-time clock is always enabled at reset.
SECONDS
Addr
0x00204004
RTC Seconds Counter Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SECONDS
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
?
?
?
?
?
?
RESET
0X00??
=
Table 23-5. RTC Seconds Counter Register Description
Name
Description
Settings
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
SECONDS
Bits 5–0
Seconds Setting—Indicates the current second.
SECONDS can be set to any value between 0 and 59.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
23-7
Programming Model
23.2.4 RTC Day Alarm Register
The real-time clock day alarm (DAYALARM) register is used to configure the day for the alarm. The alarm
settings can be read or written at any time.
DAYALARM
Addr
0x00204024
RTC Day Alarm Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
DAYSAL
TYPE
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 23-6. RTC Day Alarm Register Description
Name
Description
Reserved
Bits 31–9
Reserved—These bits are reserved and should read 0.
DAYSAL
Bits 8–0
Day Setting of the Alarm—Indicates the current day setting of
the alarm.
Settings
DAYSAL can be set to any value between
0 and 511.
MC9328MX1 Reference Manual, Rev. 6.1
23-8
Freescale Semiconductor
Programming Model
23.2.5 RTC Hours and Minutes Alarm Register
The real-time clock hours and minutes alarm (ALRM_HM) register is used to configure the hours and minutes
setting for the alarm. The alarm settings can be read or written at any time.
ALRM_HM
Addr
0x00204008
RTC Hours and Minutes Alarm Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
HOURS
TYPE
MINUTES
r
r
r
rw
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 23-7. RTC Hours and Minutes Alarm Register Description
Name
Description
Reserved
Bits 31–13
Reserved—These bits are reserved and should read 0.
HOURS
Bits 12–8
Hour Setting of the Alarm—Indicates the current hour setting
of the alarm.
Reserved
Bits 7–6
Reserved—These bits are reserved and should read 0.
MINUTES
Bits 5–0
Minute Setting of the Alarm—Indicates the current minute
setting of the alarm.
Settings
HOURS can be set to any value between
0 and 23.
MINUTES can be set to any value
between 0 and 59.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
23-9
Programming Model
23.2.6 RTC Seconds Alarm Register
The real-time clock seconds alarm (ALRM_SEC) register is used to configure the seconds setting for the alarm.
The alarm settings can be read or written at any time.
ALRM_SEC
Addr
0x0020400C
RTC Seconds Alarm Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
SECONDS
TYPE
r
r
r
r
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 23-8. RTC Seconds Alarm Register Description
Name
Description
Reserved
Bits 31–6
Reserved—These bits are reserved and should read 0.
SECONDS
Bits 6–0
Seconds Setting of the Alarm—Indicates the current
seconds setting of the alarm.
Settings
SECONDS can be set to any value between 0
and 59.
MC9328MX1 Reference Manual, Rev. 6.1
23-10
Freescale Semiconductor
Programming Model
23.2.7 RTC Control Register
The real-time clock control (RTCCTL) register is used to enable the real-time clock module and specify the
reference frequency information for the prescaler.
RCCTL
Addr
0x00204010
RTC Control Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESET
0x0000
BIT
15
14
13
12
11
10
9
8
7
EN
TYPE
XTL
SWR
r
r
r
r
r
r
r
r
rw
rw
rw
r
r
r
r
rw
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
RESET
0x0080
Table 23-9. RTC Control Register Description
Name
Description
Settings
Reserved
Bits 31–8
Reserved—These bits are reserved and should read 0.
EN
Bit 7
Enable—Enables/Disables the real-time clock. The software
reset bit (SWR) has no effect on this bit.
0 = Disable the real-time clock
1 = Enable the real-time clock
XTL
Bits 6–5
Crystal Selection—Selects the proper input crystal frequency.
It is important to set these bits correctly or the real-time clock
will be inaccurate.
00 = 32.768 kHz
01 = 32 kHz
11 = 32.768 kHz
Reserved
Bits 4–1
Reserved—These bits are reserved and should read 0.
SWR
Bit 0
Software Reset—Resets the module to its default state.
However, a software reset will have no effect on the clock
enable (EN) bit.
0 = No effect.
1 = Reset the module to its default state.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
23-11
Programming Model
23.2.8 RTC Interrupt Status Register
The real-time clock interrupt status register (RTCISR) indicates the status of the various real-time clock interrupts,
except for the 2Hz bit. When an event of the types included in this register occurs, if the corresponding bit in the
RTC Interrupt Enable Register (RTCIENR) is set, then the bit will be set in this register. These bits are cleared by
writing a value of 1, which also clears the interrupt. Interrupts may occur when the system clock is idle or in sleep
mode. For more information about the frequency of the sampling timer interrupts (SAM7-SAM0), refer to Table
23-1.
RTCISR
Addr
0x00204014
RTC Interrupt Status Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
HR
1HZ
DAY
ALM
MIN
SW
RESET
0x0000
BIT
15
SAM7
TYPE
14
13
12
11
10
9
8
SAM6 SAM5 SAM4 SAM3 SAM2 SAM1 SAM0
2HZ
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 23-10. RTC Interrupt Status Register Description
Name
Description
Settings
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
SAM7
Bit 15
Sampling Timer Interrupt Flag at SAM7 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 512,
500, or 600 Hz. The actual rate of the interrupt depends on the input clock
value. See Table 23-1.
0 = No SAM7 interrupt occurred
1 = A SAM7 interrupt occurred
SAM6
Bit 14
Sampling Timer Interrupt Flag at SAM6 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 256,
250, or 300 Hz. The actual rate of the interrupt depends on the input clock
value. See Table 23-1.
0 = No SAM6 interrupt occurred
1 = A SAM6 interrupt occurred
SAM5
Bit 13
Sampling Timer Interrupt Flag at SAM5 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 128,
125, or 150 Hz. The actual rate of the interrupt depends on the input clock
value. See Table 23-1.
0 = No SAM5 interrupt occurred
1 = A SAM5 interrupt occurred
SAM4
Bit 12
Sampling Timer Interrupt Flag at SAM4 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 64,
62.5, or 75 Hz. The actual rate of the interrupt depends on the input clock
value. See Table 23-1.
0 = No SAM4 interrupt occurred
1 = A SAM4 interrupt occurred
MC9328MX1 Reference Manual, Rev. 6.1
23-12
Freescale Semiconductor
Programming Model
Table 23-10. RTC Interrupt Status Register Description (continued)
Name
Description
Settings
SAM3
Bit 11
Sampling Timer Interrupt Flag at SAM3 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 32,
31.25, or 37.5 Hz. The actual rate of the interrupt depends on the input clock
value. See Table 23-1.
0 = No SAM3 interrupt occurred
1 = A SAM3 interrupt occurred
SAM2
Bit 10
Sampling Timer Interrupt Flag at SAM2 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 16,
15.625, or 18.75 Hz. The actual rate of the interrupt depends on the input
clock value. See Table 23-1.
0 = No SAM2 interrupt occurred
1 = A SAM2 interrupt occurred
SAM1
Bit 9
Sampling Timer Interrupt Flag at SAM1 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 8,
7.8125, or 9.375 Hz. The actual rate of the interrupt depends on the input
clock value. See Table 23-1.
0 = No SAM1 interrupt occurred
1 = A SAM1 interrupt occurred
SAM0
Bit 8
Sampling Timer Interrupt Flag at SAM0 Frequency—Indicates that an
interrupt has occurred. If enabled, this bit is periodically set at a rate of 4,
3.90625, or 4.6875 Hz. The actual rate of the interrupt depends on the input
clock value. See Table 23-1.
0 = No SAM0 interrupt occurred
1 = A SAM0 interrupt occurred
2HZ
Bit 7
2 Hz Flag—Indicates that a 2Hz status event has occurred. If enabled, this
bit is set at intervals of every 2 Hz.
0 = No 2 Hz event occurred
1 = A 2 Hz interval event occurred
Reserved
Bit 6
Reserved—This bit is reserved and should read 0.
HR
Bit 5
Hour Flag—Indicates that the hour counter has incremented. If enabled,
0 = No 1-hour interrupt occurred
this bit is set on every increment of the hour counter in the time-of-day clock. 1 = A 1-hour interrupt occurred
1HZ
Bit 4
1 Hz Flag—Indicates that the second counter has incremented. If enabled,
this bit is set on every increment of the second counter of the time-of-day
clock.
0 = No 1 Hz interrupt occurred
1 = A 1 Hz interrupt occurred
DAY
Bit 3
Day Flag—Indicates that the day counter has incremented. If enabled, this
bit is set on every increment of the day counter of the time-of-day clock.
0 = No 24-hour rollover interrupt
occurred
1 = A 24-hour rollover interrupt
occurred
ALM
Bit 2
Alarm Flag—Indicates that the real-time clock matches the value in the
alarm registers. Note that the alarm will reoccur every 512 days. For a single
alarm, clear the interrupt enable for this bit in the interrupt service routine.
0 = No alarm interrupt occurred
1 = An alarm interrupt occurred
MIN
Bit 1
Minute Flag—Indicates that the minute counter has incremented. If
enabled, this bit is set on every increment of the minute counter in the
time-of-day clock.
0 = No 1-minute interrupt occurred
1 = A 1-minute interrupt occurred
SW
Bit 0
Stopwatch Flag—Indicates that the stopwatch countdown timed out.
0 = The stopwatch did not
time-out.
1 = The stopwatch timed out.
MC9328MX1 Reference Manual, Rev. 6.1
Freescale Semiconductor
23-13
Programming Model
23.2.9 RTC Interrupt Enable Register
The real-time clock interrupt enable register (RTCIENR) is used to enable/disable the various real-time clock
interrupts except the 2HZ bit (RTCIENR[7]). When an event of the types included in this register occurs, if that bit
in this register is set, then the corresponding bit will be set in the RTC Interrupt Status Register (RTCISR). For
more information about the frequency of the sampling timer interrupts (SAM7-SAM0), refer to Table 23-1.
RTCIENR
Addr
0x00204018
RTC Interrupt Enable Register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
HR
1HZ
DAY
ALM
MIN
SW
RESET
0x0000
BIT
15
SAM7
TYPE
14
13
12
11
10
9
8
SAM6 SAM5 SAM4 SAM3 SAM2 SAM1 SAM0
2HZ
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0x0000
Table 23-11. RTC Interrupt Enable Register Description
Name
Description
Settings
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
SAM7
Bit 15
Sampling Timer Interrupt Flag at SAM7 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 7. The
frequency of this interrupt is shown in Table 23-1.
0 = SAM7 interrupt is disabled
1 = SAM7 interrupt is enabled
SAM6
Bit 14
Sampling Timer Interrupt Flag at SAM6 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 6. The
frequency of this interrupt is shown in Table 23-1.
0 = SAM6 interrupt is disabled
1 = SAM6 interrupt is enabled
SAM5
Bit 13
Sampling Timer Interrupt Flag at SAM5 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 5. The
frequency of this interrupt is shown in Table 23-1.
0 = SAM5 interrupt is disabled
1 = SAM5 interrupt is enabled
SAM4
Bit 12
Sampling Timer Interrupt Flag at SAM4 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 4. The
frequency of this interrupt is shown in Table 23-1.
0 = SAM4 interrupt is disabled
1 = SAM4 interrupt is enabled
SAM3
Bit 11
Sampling Timer Interrupt Flag at SAM3 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 3. The
frequency of this interrupt is shown in Table 23-1.
0 = SAM3 interrupt is disabled
1 = SAM3 interrupt is enabled
SAM2
Bit 10
Sampling Timer Interrupt Flag at SAM2 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 2. The
frequency of this interrupt is shown in Table 23-1.
0 = SAM2 interrupt is disabled
1 = SAM2 interrupt is enabled
MC9328MX1 Reference Manual, Rev. 6.1
23-14
Freescale Semiconductor
Programming Model
Table 23-11. RTC Interrupt Enable Register Description (continued)
Name
Description
Settings
SAM1
Bit 9
Sampling Timer Interrupt Flag at SAM1 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 1. The
frequency of this interrupt is shown in Table 23-1.
0 = SAM1 interrupt is disabled
1 = SAM1 interrupt is enabled
SAM0
Bit 8
Sampling Timer Interrupt Flag at SAM0 Interrupt
Enable—Enables/Disables the real-time sampling timer interrupt 0. The
frequency of this interrupt is shown in Table 23-1.
0 = SAM0 interrupt is disabled
1 = SAM0 interrupt is enabled
2HZ
Bit 7
2 Hz Interrupt Enable—Enables/Disables the 2 Hz bit at a 2 Hz rate.
0 = The 2 Hz clock is disabled
1 = The 2 Hz clock is enabled
Reserved
Bit 6
Reserved—This bit is reserved and should read 0.
HR
Bit 5
Hour Interrupt Enable—Enables/Disables an interrupt whenever the
hour counter of the real-time clock increments.
0 = The 1-hour interrupt is disabled
1 = The 1-hour interrupt is enabled
1HZ
Bit 4
1 Hz Interrupt Enable—Enables/Disables an interrupt whenever the
second counter of the real-time clock increments.
0 = The 1 Hz interrupt is disabled
1 = The 1 Hz interrupt is
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement