Silicon Labs EFM32HG Reference Manual

Silicon Labs EFM32HG  Reference Manual

Preliminary

...the world's most energy friendly microcontrollers

EFM32HG Reference Manual

Happy Gecko Series

Preliminary • 32-bit ARM Cortex-M0+ processor running at up to 25 MHz • Up to 64 kB Flash and 8 kB RAM memory • Energy efficient and autonomous peripherals • Ultra low power Energy Modes with sub-µA operation • Fast wake-up time of only 2 µs The EFM32HG microcontroller series revolutionizes the 8- to 32-bit market with a combination of unmatched performance and ultra low power consumption in both active- and sleep modes. EFM32HG devices consume as little as 114 µA/MHz in run mode.

EFM32HG's low energy consumption outperforms any other available 8-, 16-, and 32-bit solution. The EFM32HG includes autonomous and energy efficient peripherals, high overall chip- and analog integration, and the performance of the industry standard 32-bit ARM Cortex-M0+ processor.

2015-03-16 - Happy Gecko Family - d0321_Rev0.90

1

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

1 Energy Friendly Microcontrollers

1.1 Typical Applications

The EFM32HG Happy Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications. These devices are developed to minimize the energy consumption by lowering both the power and the active time, over all phases of MCU operation. This unique combination of ultra low energy consumption and the performance of the 32-bit ARM Cortex-M0+ processor, help designers get more out of the available energy in a variety of applications.

Ultra low energy EFM32HG microcontrollers are perfect for:

• Gas metering • Energy metering • Water metering • Smart metering • Alarm and security systems • Health and fitness applications • Industrial and home automation

0 1 2 3 4

1.2 EFM32HG Development

Because EFM32HG use the Cortex-M0+ CPU, embedded designers benefit from the largest development ecosystem in the industry, the ARM ecosystem. The development suite spans the whole design process and includes powerful debug tools, and some of the world’s top brand compilers.

Libraries with documentation and user examples shorten time from idea to market.

The range of EFM32HG devices ensure easy migration and feature upgrade possibilities.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

2

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

2 About This Document

This document contains reference material for the EFM32HG series of microcontrollers. All modules and peripherals in the EFM32HG series devices are described in general terms. Not all modules are present in all devices, and the feature set for each device might vary. Such differences, including pin-out, are covered in the device-specific datasheets.

2.1 Conventions Register Names

Register names are given as a module name prefix followed by the short register name: TIMERn_CTRL - Control Register The "n" denotes the numeric instance for modules that might have more than one instance.

Some registers are grouped which leads to a group name following the module prefix: GPIO_Px_DOUT - Port Data Out Register, where x denotes the port instance (A,B,...).

Bit Fields

Registers contain one or more bit fields which can be 1 to 32 bits wide. Multi-bit fields are denoted with (x:y), where x is the start bit and y is the end bit.

Address

The address for each register can be found by adding the base address of the module (found in the Memory Map), and the offset address for the register (found in module Register Map).

Access Type

The register access types used in the register descriptions are explained in Table 2.1 (p. 3) .

Table 2.1. Register Access Types

Access Type

R RW RW1 RW1H W1 W RWH

Description

Read only. Writes are ignored.

Readable and writable.

Readable and writable. Only writes to 1 have effect.

Readable, writable and updated by hardware. Only writes to 1 have effect.

Read value undefined. Only writes to 1 have effect.

Write only. Read value undefined.

Readable, writable and updated by hardware.

Number format

0x prefix is used for hexadecimal numbers.

0b prefix is used for binary numbers.

Numbers without prefix are in decimal representation.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

3

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Reserved

Registers and bit fields marked with reserved are reserved for future use. These should be written to 0 unless otherwise stated in the Register Description. Reserved bits might be read as 1 in future devices.

Reset Value

The reset value denotes the value after reset.

Registers denoted with X have an unknown reset value and need to be initialized before use. Note that, before these registers are initialized, read-modify-write operations might result in undefined register values.

Pin Connections

Pin connections are given as a module prefix followed by a short pin name: USn_TX (USARTn TX pin) The pin locations referenced in this document are given in the device-specific datasheet.

2.2 Related Documentation

Further documentation on the EFM32HG family and the ARM Cortex-M0+ can be found at the Silicon Laboratories and ARM web pages: www.silabs.com

www.arm.com

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

4

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

3 System Overview

3.1 Introduction

The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM Cortex-M0+, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32HG microcontroller is well suited for any battery operated application, as well as other systems requiring high performance and low-energy

consumption, see Figure 3.1 (p. 6) .

3.2 Features

ARM Cortex-M0+ CPU platform • High Performance 32-bit processor @ up to 25 MHz • Wake-up Interrupt Controller • Flexible Energy Management System • 20 nA @ 3 V Shutoff Mode • 0.5 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention • 0.9 µA @ 3 V Deep Sleep Mode, including RTC with 32768 Hz oscillator, Power-on Reset, Brown-out Detector, RAM and CPU retention • 46 µA/MHz @ 3 V Sleep Mode • 114 µA/MHz @ 3 V Run Mode, with code executed from flash • 64/32 KB Flash8/4 KB RAMUp to 37 General Purpose I/O pins • Configurable push-pull, open-drain, pull-up/down, input filter, drive strength • Configurable peripheral I/O locations • 16 asynchronous external interrupts • Output state retention and wake-up from Shutoff Mode • 4 Channel DMA Controller • Alternate/primary descriptors with scatter-gather/ping-pong operation • 4 Channel Peripheral Reflex System • Autonomous inter-peripheral signaling enables smart operation in low energy modes • Universal Serial Bus (USB) • Fully USB 2.0 compliant • Crystal free operation • On-chip PHY and embedded 5V to 3.3V regulator • Hardware AES with 128-bit Keys in 54 cyclesCommunication interfaces • 2× Universal Synchronous/Asynchronous Receiver/Transmitter • Triple buffered full/half-duplex operation • 4-16 data bits • 1× Low Energy UART • Autonomous operation with DMA in Deep Sleep Mode • 1× I 2 C Interface with SMBus support • Address recognition in Stop Mode • Timers/Counters • 3× 16-bit Timer/Counter • 3 Compare/Capture/PWM channels • Dead-Time Insertion on TIMER0 • 24-bit Real-Time Counter 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

5

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• 1× 16-bit Pulse Counter • Asynchronous pulse counting/quadrature decoding • Watchdog Timer with dedicated RC oscillator @ 50 nA • Ultra low power precision analog peripherals • 12-bit 1 Msamples/s Analog to Digital Converter • 8 input channels and on-chip temperature sensor • Single ended or differential operation • Conversion tailgating for predictable latency • Current Digital to Analog Converter • Source or sink a configurable constant current • 1× Analog Comparator • Programmable speed/current • Capacitive sensing with up to 8 inputs • Supply Voltage Comparator • Ultra efficient Power-on Reset and Brown-Out Detector2-pin Serial Wire Debug interface

Temperature range -40 to 85°C (EFM32HGxxxFxx) or -40 to 105°C (EFM32HGxxxFxxN)

Single power supply 1.98 - 3.8 VPackages • QFN24 • QFN32 • TQFP48 • CSP36

3.3 Block Diagram

Figure 3.1 (p. 6) shows the block diagram of EFM32HG. The color indicates peripheral availability

in the different energy modes, described in Section 3.4 (p. 7) .

Figure 3.1. Block Diagram of EFM32HG

Core and Mem ory

Happy Gecko

Clock Managem ent Energy Managem ent Volt age Regulat or Volt age Com parat or ARM Cort ex ™ M0+ processor Brown- out Det ect or Power- on Reset Flash Program Mem ory RAM Mem ory Serial Int erfaces USART Low Energy UART™ I 2 C Low Energy USB Debug Interface w/ MTB DMA Cont roller 3 2 - bit bus Per ipher al Ref lex Syst em I/ O Port s Tim ers and Triggers Ex t ernal Int errupt s General Purpose I/ O Tim er/ Count er Real Tim e Count er Pin Reset Pin Wakeup Pulse Count er Wat chdog Tim er Analog Int erfaces ADC Analog Com parat or Current DAC Securit y Hardware AES 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

6

www.silabs.com

Preliminary

Figure 3.2. Energy Mode Indicator ...the world's most energy friendly microcontrollers 0 1 2 3 4 Note

In the energy mode indicator, the numbers indicates Energy Mode, i.e EM0-EM4.

3.4 Energy Modes

There are five different Energy Modes (EM0-EM4) in the EFM32HG, see Table 3.1 (p. 8) . The

EFM32HG is designed to achieve a high degree of autonomous operation in low energy modes. The intelligent combination of peripherals, RAM with data retention, DMA, low-power oscillators, and short wake-up time, makes it attractive to remain in low energy modes for long periods and thus saving energy consumption.

Tip

Throughout this document, the first figure in every module description contains an Energy Mode

Indicator showing which energy mode(s) the module can operate (see Table 3.1 (p. 8) ).

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

7

www.silabs.com

Preliminary

Table 3.1. Energy Mode Description

Energy Mode Name Description

...the world's most energy friendly microcontrollers 0 1 2 3 4

EM0 – Energy Mode 0 (Run mode) In EM0, the CPU is running and consuming as little as 114 µA/MHz, when running code from flash. All peripherals can be active.

0 1 2 3 4

EM1 – Energy Mode 1 (Sleep Mode) In EM1, the CPU is sleeping and the power consumption is only 46 µA/MHz.

All peripherals, including DMA, PRS and memory system, are still available.

0 1 2 3 4 0 1 2 3 4

EM2 – Energy Mode 2 (Deep Sleep Mode) In EM2 the high frequency oscillator is turned off, but with the 32.768 kHz oscillator running, selected low energy peripherals (RTC, PCNT, LEUART, I 2 C, USB, WDOG and ACMP) are still available. This gives a high degree of autonomous operation with a current consumption as low as 0.9 µA with RTC enabled. Power-on Reset, Brown-out Detection and full RAM and CPU retention is also included.

EM3 - Energy Mode 3 (Stop Mode) In EM3, the low-frequency oscillator is disabled, but there is still full CPU and RAM retention, as well as Power-on Reset, Pin reset, EM4 wake-up and Brown-out Detection, with a consumption of only 0.5 µA. The low-power ACMP, asynchronous external interrupt, PCNT, and I 2 C can wake-up the device. Even in this mode, the wake-up time is a few microseconds.

0 1 2 3 4

EM4 – Energy Mode 4 (Shutoff Mode) In EM4, the current is down to 20 nA and all chip functionality is turned off except the pin reset, GPIO pin wake-up, GPIO pin retention and the Power On Reset. All pins are put into their reset state.

3.5 Product Overview

Table 3.2 (p. 8) shows a device overview of the EFM32HG Microcontroller Series, including

peripheral functionality. For more information, the reader is referred to the device specific datasheets.

Table 3.2. EFM32HG Microcontroller Series

108F32 108F64 32 4 17 64 8 17 110F32 110F64 32 4 17 64 8 17 2 1 2 2 2 1 1 1 1 1 1 1 3 (9) 3 (9) 3 (9) 3 (9) 1 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 (1) 1 (1) 1 (2) 1 (2) 1 (2) 1 (2) Y Y QFN24 QFN24 QFN24 QFN24 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

8

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

210F32 210F64 222F32 222F64 308F32 308F64 309F32 309F64 310F32 310F64 321F32 321F64 322F32 322F64 350F32 350F64 32 4 24 64 8 24 32 4 37 64 8 37 32 8 14 Y 64 8 14 Y 32 8 14 Y 64 8 14 Y 32 8 21 Y 64 8 21 Y 32 8 34 Y 64 8 34 Y 32 8 34 Y 64 8 34 Y 32 8 22 Y 64 8 22 Y 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 (9) 3 (9) 3 (9) 3 (9) 3 (9) 3 (9) 3 (9) 3 (9) 3 (9) 3 (9) 3 (9) 3 (9) 3 (9) 3 (9) 3 (9) 3 (9) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (4) 1 (4) 1 (4) 1 (4) 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 (4) 1 (4) 1 (4) 1 (4) 1 (4) 1 (4) 1 (4) 1 (4) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (1) 1 (5) 1 (5) 1 (5) 1 (2) 1 (2) 1 (2) 1 (2) 1 (5) 1 (5) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (5) Y Y Y Y Y Y Y Y Y Y Y Y QFN32 QFN32 QFP48 QFP48 QFN24 QFN24 QFN24 QFN24 QFN32 QFN32 QFP48 QFP48 QFP48 QFP48 CSP36 CSP36

3.6 Device Revision

The device revision number is read from the ROM Table. The major revision number and the chip family number is read from PID0 and PID1 registers. The minor revision number is extracted from the PID2 and

PID3 registers, as illustrated in Figure 3.3 (p. 9) . The Fam[5:2] and Fam[1:0] must be combined

to complete the chip family number, while the Minor Rev[7:4] and Minor Rev[3:0] must be combined to form the complete revision number.

Figure 3.3. Revision Number Extraction

31:8 PID2 (0 xF0 0 FFFE8 ) 7:4 3:0 Minor Rev[7:4] 31:8 PID0 (0 xF0 0 FFFE0 ) 7:6 Fam [1:0] 5:0 Major Rev[5:0] 31:8 PID3 (0 xF0 0 FFFEC) 7:4 3:0 Minor Rev[3:0] PID1 (0 xF0 0 FFFE4 ) 31:4 3:0 Fam [5:2] 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

9

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

For the latest revision of the Happy Gecko family, the chip family number is 0x05 and the major revision

number is 0x01. The minor revision number is to be interpreted according to Table 3.3 (p. 10) .

Table 3.3. Minor Revision Number Interpretation

Minor Rev[7:0]

0x00

Revision

A 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

10

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

4 System Processor

0 1 2 3 4

CM0 + Core 3 2 - bit ALU

Single cycle 32- bit m ult iplier Cont rol Logic Syst em Int erface NVIC Int erface Thum b & Thum b- 2 Decode Single Cycle I/ O Int erface

Quick Facts What?

The industry leading Cortex-M0+ processor from ARM is the CPU in the EFM32HG microcontrollers.

Why?

The ARM Cortex-M0+ is designed for exceptional short response time, high code density, and high 32-bit throughput while maintaining a strict cost and power consumption budget.

How?

Combined with the ultra low energy peripherals available, the Cortex-M0+ makes the EFM32HG devices perfect for 8- to 32 bit applications. The processor is featuring a 2 stage pipeline, dedicated single cycle I/O interface, efficient single cycle instructions, Thumb/Thumb-2 instruction set support, and fast interrupt handling.

4.1 Introduction

The ARM Cortex-M0+ 32-bit RISC processor provides outstanding computational performance and exceptional system response to interrupts while meeting low cost requirements and low power consumption.

The ARM Cortex-M0+ implemented is revision r0p1.

4.2 Features

• 2-stage pipeline • Thumb/Thumb-2 instruction subset • Enhanced levels of performance, energy efficiency, and code density • Enables direct portability to other ARM Cortex-M processors • Hardware single-cycle multiplication • Enables 32-bit multiplication in a single cycle • Dedicated Single-cycle I/O interface • Provides immediate acces to all GPIO-registers • Enables the processor to simultanously fetch the next instructions over the System bus • Configurable IRQ-latency • Allows developers to select a trade-off between interrupt response time and predictability • Up to 1.08 DMIPS/MHz • 24-bit System Tick Timer for Real-Time Operating System (RTOS) • Excellent 32-bit migration choice for 8/16 bit architecture based designs • Simplified stack-based programmer's model is compatible with traditional ARM architecture and retains the programming simplicity of legacy 8- and 16-bit architectures • Integrated power modes 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

11

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• Sleep Now mode for immediate transfer to low power state • Sleep on Exit mode for entry into low power state after the servicing of an interrupt • Ability to extend power savings to other system components • Optimized for low latency, nested interrupts

4.3 Functional Description

For a full functional description of the ARM Cortex-M0+ (r0p1) implementation in the EFM32HG family, the reader is referred to the ARM Cortex-M0+ Devices Generic User Guide.

4.3.1 Interrupt Operation

Figure 4.1. Interrupt Operation

Module IFS[n] Int errupt condit ion IFC[n] IEN[n] set clear IF[n] IRQ Cort ex - M0+ NVIC SETENA[n]/ CLRENA[n] Act ive int errupt set clear SETPEND[n]/ CLRPEND[n] Soft ware generat ed int errupt Int errupt request The EFM32HG devices have up to 21 interrupt request lines (IRQ) which are connected to the Cortex-

M0+. Each of these lines (shown in Table 4.1 (p. 12) ) are connected to one or more interrupt flags in

one or more modules. The interrupt flags are set by hardware on an interrupt condition. It is also possible to set/clear the interrupt flags through the IFS/IFC registers. Each interrupt flag is then qualified with its own interrupt enable bit (IEN register), before being OR'ed with the other interrupt flags to generate the IRQ. A high IRQ line will set the corresponding pending bit (can also be set/cleared with the SETPEND/ CLRPEND bits in ISPR0/ICPR0) in the Cortex-M0+ NVIC. The pending bit is then qualified with an enable bit (set/cleared with SETENA/CLRENA bits in ISER0/ICER0) before generating an interrupt request to

the core. Figure 4.1 (p. 12) illustrates the interrupt system. For more information on how the interrupts

are handled inside the Cortex-M0+, the reader is referred to the ARM Cortex-M0+ Devices Generic User Guide.

Table 4.1. Interrupt Request Lines (IRQ)

7 8 9 10 11 3 4 5 6 1 2

IRQ #

0

Source

DMA GPIO_EVEN TIMER0 ACMP0 ADC0 I2C0 GPIO_ODD TIMER1 USART1_RX USART1_TX LEUART0 PCNT0 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

12

www.silabs.com

15 16 17 18

IRQ #

12 13 14 19 20

Preliminary

...the world's most energy friendly microcontrollers

Source

RTC CMU VCMP MSC AES USART0_RX USART0_TX USB TIMER2 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

13

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

5 Memory and Bus System

0 1 2 3 4

ARM Cortex- M0 + DMA Controller Flash RAM Peripherals Quick Facts What?

A low latency memory system, including low energy flash and RAM with data retention, makes extended use of low-power energy modes possible.

Why?

RAM retention reduces the need for storing data in flash and enables frequent use of the ultra low energy modes EM2 and EM3 with as little as 0.5 µA current consumption.

How?

Low energy and non-volatile flash memory stores program and application data in all energy modes and can easily be reprogrammed in system. Low leakage RAM, with data retention in EM0 to EM3, removes the data restore time penalty, and the DMA ensures fast autonomous transfers with predictable response time.

5.1 Introduction

The EFM32HG contains an AMBA AHB Bus system allowing bus masters to access the memory mapped address space. A multilayer AHB bus matrix, using a Round-robin arbitration scheme, connects the

master bus interfaces to the AHB slaves (Figure 5.1 (p. 15) ). The bus matrix allows several AHB

slaves to be accessed simultaneously. An AMBA APB interface is used for the peripherals, which are accessed through an AHB-to-APB bridge connected to the AHB bus matrix. The AHB bus masters are: • Cortex-M0+ System: Used for instruction fetches, data and debug access (0x00000000 0xDFFFFFFF).

DMA: Can access SRAM, Flash and peripherals (0x00000000 - 0xDFFFFFFF), except GPIO (0x40006000 - 0x40007000).

USB DMA: Can access SRAM and Flash (0x00000000 - 0x3FFFFFFF), and the AHB-peripherals: USB and AES.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

14

www.silabs.com

Preliminary

Figure 5.1. EFM32HG Bus System ...the world's most energy friendly microcontrollers

Cort ex Syst em AHB Mult ilayer Bus Mat rix Flash RAM AES USB DMA USB DMA AHB/ APB Bridge Peripheral 0 Peripheral n

5.2 Functional Description

The memory segments are mapped together with the internal segments of the Cortex-M0+ into the

system memory map shown by Figure 5.2 (p. 16)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

15

www.silabs.com

Preliminary

Figure 5.2. System Address Space ...the world's most energy friendly microcontrollers

The embedded SRAM is located at address 0x20000000 in the memory map of the EFM32HG. It is also mapped in code space at address 0x10000000 to keep compatibility towards Cortex-M3 and Cortex-M4 EFM32-devices, that uses this code-space mapped SRAM for faster instruction fetching.

5.2.1 Peripherals

The peripherals are mapped into the peripheral memory segment, each with a fixed size address range

according to Table 5.1 (p. 16) , Table 5.2 (p. 17) and Table 5.3 (p. 17) .

Table 5.1. Memory System Core Peripherals

Core peripherals Address Range

0xF0040000 - 0xF007FFFF 0x400E0000 - 0x400E03FF 0x400CA000 - 0x400CA3FF 0x400C8000 - 0x400C83FF 0x400C6000 - 0x400C63FF 0x400C4000 - 0x400C43FF 0x400C2000 - 0x400C3FFF 0x400C0000 - 0x400C03FF

Module Name

MTB AES RMU CMU EMU USB DMA MSC 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

16

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Table 5.2. Memory System Low Energy Peripherals

Low Energy peripherals Address Range

0x40088000 - 0x400883FF 0x40086000 - 0x400863FF 0x40084000 - 0x400843FF 0x40080000 - 0x400803FF

Module Name

WDOG PCNT0 LEUART0 RTC

Table 5.3. Memory System Peripherals

Peripherals Address Range

0x400CC000 - 0x400CC3FF 0x40010800 - 0x40010BFF 0x40010400 - 0x400107FF 0x40010000 - 0x400103FF 0x4000C400 - 0x4000C7FF 0x4000C000 - 0x4000C3FF 0x4000A000 - 0x4000A3FF 0x40006000 - 0x40006FFF 0x40004000 - 0x400043FF 0x40002000 - 0x400023FF 0x40001000 - 0x400013FF 0x40000000 - 0x400003FF

Module Name

PRS TIMER2 TIMER1 TIMER0 USART1 USART0 I2C0 GPIO IDAC0 ADC0 ACMP0 VCMP

5.2.2 Bus Matrix

The Bus Matrix connects the memory segments to the bus masters: • Code: CPU instruction or data fetches from the code space • System: CPU read and write to the SRAM and peripherals • DMA: Access to SRAM, Flash and peripherals • USB DMA: Access to SRAM and Flash

5.2.2.1 Arbitration

The Bus Matrix uses a round-robin arbitration algorithm which enables high throughput and low latency while starvation of simultaneous accesses to the same bus slave are eliminated. Round-robin does not assign a fixed priority to each bus master. The arbiter does not insert any bus wait-states.

5.2.2.2 Access Performance

The Bus Matrix is a multi-layer energy optimized AMBA AHB compliant bus with an internal bandwidth equal to 4 times a single AHB-bus.

The Bus Matrix accepts new transfers initiated by each master in every clock cycle without inserting any wait-states. The slaves, however, may insert wait-states depending on their internal throughput and the clock frequency.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

17

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

The Cortex-M0+, the DMA Controller, and the peripherals run on clocks that can be prescaled separately.

When accessing a peripheral which runs on a frequency equal to or faster than the HFCORECLK, the number of wait cycles per access, in addition to master arbitration, is given by:

Memory Wait Cycles with Clock Equal or Faster than HFCORECLK

N cycles = 2 + N slave cycles , (5.1) where N slave cycles is the wait cycles introduced by the slave.

When accessing a peripheral running on a clock slower than the HFCORECLK, wait-cycles are introduced to allow the transfer to complete on the peripheral clock. The number of wait cycles per access, in addition to master arbitration, is given by:

Memory Wait Cycles with Clock Slower than CPU

N cycles = (2 + N slave cycles ) x f HFCORECLK /f HFPERCLK , (5.2) where N slave cycles is the number of wait cycles introduced by the slave.

For general register access, N slave cycles = 1.

More details on clocks and prescaling can be found in Chapter 11 (p. 96) .

5.3 Access to Low Energy Peripherals (Asynchronous Registers) 5.3.1 Introduction

The Low Energy Peripherals are capable of running when the high frequency oscillator and core system is powered off, i.e. in energy mode EM2 and in some cases also EM3. This enables the peripherals to perform tasks while the system energy consumption is minimal.

The Low Energy Peripherals are: • Low Energy UART - LEUART • Pulse Counter - PCNT • Real Time Counter - RTC • Watchdog - WDOG All Low Energy Peripherals are memory mapped, with automatic data synchronization. Because the Low Energy Peripherals are running on clocks asynchronous to the core clock, there are some constraints on how register accesses can be done, as described in the following sections.

5.3.1.1 Writing

Every Low Energy Peripheral has one or more registers with data that needs to be synchronized into the Low Energy clock domain to maintain data consistency and predictable operation. There are two different synchronization mechanisms on the Happy Gecko; immediate synchronization, and delayed synchronization. Immediate synchronization is available for the RTC and results in an immediate update of the target registers. Delayed synchronization is used for the other Low Energy Peripherals, and for these peripherals, a write operation requires 3 positive edges on the clock of the Low Energy Peripheral being accessed. Registers requiring synchronization are marked "Asynchronous" in their description header.

5.3.1.1.1 Delayed synchronization

After writing data to a register which value is to be synchronized into the Low Energy Peripheral using delayed synchronization, a corresponding busy flag in the _SYNCBUSY register (e.g.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

18

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

LEUART_SYNCBUSY) is set. This flag is set as long as synchronization is in progress and is cleared upon completion.

Note

Subsequent writes to the same register before the corresponding busy flag is cleared is not supported. Write before the busy flag is cleared may result in undefined behavior.

In general, the SYNCBUSY register only needs to be observed if there is a risk of multiple write access to a register (which must be prevented). It is not required to wait until the relevant flag in the SYNCBUSY register is cleared after writing a register. E.g EM2 can be entered immediately after writing a register.

See Figure 5.3 (p. 19) for a more detailed overview of the write operation.

Figure 5.3. Write operation to Low Energy Peripherals

Writ e[0:n] Set 0 Set 1 Set n Core Clock Dom ain Core Clock Regist er 0 Regist er 1 .

.

.

Regist er n Freeze Low Frequency Clock Dom ain Low Frequency Clock Synchronizer 0 Synchronizer 1 .

.

.

Synchronizer n Low Frequency Clock Regist er 0 Sync Regist er 1 Sync .

.

.

Regist er n Sync Synchronizat ion Done Syncbusy Regist er 0 Syncbusy Regist er 1 .

.

.

Syncbusy Regist er n Clear 0 Clear 1 Clear n

5.3.1.1.2 Immediate synchronization

Contrary to the peripherals with delayed synchronization, data written to peripherals with immediate synchronization, takes effect in the peripheral immediately. They are updated immediately on the peripheral write access. If a write is set up close to a peripheral clock edge, the write is delayed to after the clock edge. This will introduce wait-states on peripheral access. In the worst case, there can be three wait-state cycles of the HFCORECLK_LE and an additional wait-state equivalent of up to 315 ns.

For peripherals with immediate synchronization, the SYNCBUSY registers are still present and serve two purposes: (1) commands written to a peripheral with immediate synchronization are not executed before the first peripheral clock after the write. During this period, the SYNCBUSY flag in the command register is set, indicating that the command has not yet been executed; (2) to maintain backwards compatibility with the EFM32G series, SYNCBUSY registers are also present for other registers. These are however, always 0, indicating that register writes are always safe.

Note

If the application must be compatible with the EFM32G series, all Low Energy Peripherals should be accessed as if they only had delayed synchronization, i.e. using SYNCBUSY.

5.3.1.2 Reading

When reading from Low Energy Peripherals, the data is synchronized regardless of the originating clock domain. Registers updated/maintained by the Low Energy Peripheral are read directly from the Low 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

19

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Energy clock domain. Registers residing in the core clock domain, are read from the core clock domain.

See Figure 5.4 (p. 20) for a more detailed overview of the read operation.

Note

Writing a register and then immediately reading back the value of the register may give the impression that the write operation is complete. This is not necessarily the case. Please refer to the SYNCBUSY register for correct status of the write operation to the Low Energy Peripheral.

Figure 5.4. Read operation from Low Energy Peripherals

Core Clock Dom ain

Core Clock Regist er 0 Regist er 1 .

.

.

Regist er n Freeze

Low Frequency Clock Dom ain

Low Frequency Clock Synchronizer 0 Synchronizer 1 .

.

.

Synchronizer n Low Frequency Clock Regist er 0 Sync Regist er 1 Sync .

.

.

Regist er n Sync Read Synchronizer Read Dat a HW St at us Regist er 0 HW St at us Regist er 1 .

.

.

HW St at us Regist er m Low Energy Peripheral Main Funct ion

5.3.2 FREEZE register

For Low Energy Peripherals with delayed synchronization there is a _FREEZE register (e.g. RTC_FREEZE), containing a bit named REGFREEZE. If precise control of the synchronization process is required, this bit may be utilized. When REGFREEZE is set, the synchronization process is halted, allowing the software to write multiple Low Energy registers before starting the synchronization process, thus providing precise control of the module update process. The synchronization process is started by clearing the REGFREEZE bit.

Note

The FREEZE register is also present on peripherals with immediate synchronization, but has no effect.

5.4 Flash

The Flash retains data in any state and typically stores the application code, special user data and security information. The Flash memory is typically programmed through the debug interface, but can also be erased and written to from software.

• Up to 64 kB of memory • Page size of 1024 bytes (minimum erase unit) • Minimum 20 000 erase cycles • More than 10 years data retention at 85°C • Lock-bits for memory protection • Data retention in any state 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

20

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

5.5 SRAM

The primary task of the SRAM memory is to store application data. Additionally, it is possible to execute instructions from SRAM, and the DMA may used to transfer data between the SRAM, Flash and peripherals.

• Up to 8 kB memory • Data retention of the entire memory in EM0 to EM3

5.6 Device Information (DI) Page

The DI page contains calibration values, a unique identification number and other useful data. See the table below for a complete overview.

Table 5.4. Device Information Page Contents

DI Address

0x0FE08020 0x0FE08028 0x0FE08030 0x0FE08040 0x0FE08048 0x0FE08050 0x0FE08058 0x0FE08078 0x0FE08098 0x0FE081B0 0x0FE081B2 0x0FE081B4 0x0FE081B6 0x0FE081B8 0x0FE081BA 0x0FE081BC 0x0FE081BE 0x0FE081C8 0x0FE081C9 0x0FE081CA 0x0FE081CB 0x0FE081CC 0x0FE081CD

Register

CMU_LFRCOCTRL CMU_HFRCOCTRL CMU_AUXHFRCOCTRL ADC0_CAL ADC0_BIASPROG ACMP0_CTRL CMU_LCDCTRL

Description

Register reset value.

Register reset value.

Register reset value.

Register reset value.

Register reset value.

Register reset value.

Register reset value.

IDAC0_CAL CMU_USHFRCOCTRL DI_CRC CAL_TEMP_0 ADC0_CAL_1V25 ADC0_CAL_2V5 ADC0_CAL_VDD ADC0_CAL_5VDIFF Register reset value.

Register reset value.

[15:0]: DI data CRC-16.

[7:0] Calibration temperature (°C).

[14:8]: Gain for 1V25 reference, [6:0]: Offset for 1V25 reference.

[14:8]: Gain for 2V5 reference, [6:0]: Offset for 2V5 reference.

[14:8]: Gain for VDD reference, [6:0]: Offset for VDD reference.

[14:8]: Gain for 5VDIFF reference, [6:0]: Offset for 5VDIFF reference.

ADC0_CAL_2XVDD [14:8]: Reserved (gain for this reference cannot be calibrated), [6:0]: Offset for 2XVDD reference.

ADC0_TEMP_0_READ_1V25 IDAC0_CAL_RANGE0 IDAC0_CAL_RANGE1 IDAC0_CAL_RANGE2 IDAC0_CAL_RANGE3 [15:4] Temperature reading at 1V25 reference, [3:0]: Reserved.

[7:0]: Current range 0 tuning.

[7:0]: Current range 1 tuning.

[7:0]: Current range 2 tuning.

[7:0]: Current range 3 tuning.

USHFRCO_COARSECAL_BAND_25[6:0]: Coarse tuning for the 24 MHz USHFRCO band.

USHFRCO_FINECAL_BAND_25 [5:0]: Fine tuning for the 24 MHz USHFRCO band.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

21

www.silabs.com

DI Address

0x0FE081CE 0x0FE081CF 0x0FE081D4 0x0FE081D5 0x0FE081D6 0x0FE081D7 0x0FE081D8 0x0FE081DC 0x0FE081DD 0x0FE081DE 0x0FE081DF 0x0FE081E0 0x0FE081F0 0x0FE081F4 0x0FE081F8 0x0FE081FA 0x0FE081FC 0x0FE081FE 0x0FE081FF

Preliminary

...the world's most energy friendly microcontrollers

Register Description

USHFRCO_COARSECAL_BAND_48[6:0]: Coarse tuning for the 48 MHz USHFRCO band.

USHFRCO_FINECAL_BAND_48 AUXHFRCO_CALIB_BAND_1 [5:0]: Fine tuning for the 48 MHz USHFRCO band.

[7:0]: Tuning for the 1.2 MHz AUXHFRCO band.

AUXHFRCO_CALIB_BAND_7 AUXHFRCO_CALIB_BAND_11 AUXHFRCO_CALIB_BAND_14 AUXHFRCO_CALIB_BAND_21 [7:0]: Tuning for the 6.6 MHz AUXHFRCO band.

[7:0]: Tuning for the 11 MHz AUXHFRCO band.

[7:0]: Tuning for the 14 MHz AUXHFRCO band.

[7:0]: Tuning for the 21 MHz AUXHFRCO band.

HFRCO_CALIB_BAND_1 HFRCO_CALIB_BAND_7 HFRCO_CALIB_BAND_11 HFRCO_CALIB_BAND_14 HFRCO_CALIB_BAND_21 UNIQUE_0 UNIQUE_1 MEM_INFO_FLASH MEM_INFO_RAM PART_NUMBER PART_FAMILY PROD_REV [7:0]: Tuning for the 1.2 MHz HFRCO band.

[7:0]: Tuning for the 6.6 MHz HFRCO band.

[7:0]: Tuning for the 11 MHz HFRCO band.

[7:0]: Tuning for the 14 MHz HFRCO band.

[7:0]: Tuning for the 21 MHz HFRCO band.

[31:0] Unique number.

[63:32] Unique number.

[15:0]: Flash size, kbyte count as unsigned integer (e.g.

128).

[15:0]: Ram size, kbyte count as unsigned integer (e.g. 16).

[15:0]: EFM32 part number as unsigned integer (e.g. 230).

[7:0]: EFM32 part family number (Gecko = 71, Giant Gecko = 72, Tiny Gecko = 73, Leopard Gecko=74, Wonder Gecko=75, Zero Gecko=76, Happy Gecko=77).

[7:0]: EFM32 Production ID.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

22

www.silabs.com

Preliminary

6 DBG - Debug Interface

...the world's most energy friendly microcontrollers 0 1 2 3 4

ARM Cortex- M0 + DBG Debug Data Quick Facts What?

The DBG (Debug Interface) is used to program and debug EFM32HG devices.

Why?

The Debug Interface makes it easy to re program and update the system in the field, and allows debugging with minimal I/O pin usage.

How?

The Cortex-M0+ supports advanced debugging features. EFM32HG devices only use two port pins for debugging or programming. The internal and external state of the system can be examined with debug extensions supporting instruction or data access break- and watch points.

6.1 Introduction

The EFM32HG devices include hardware debug support through a 2-pin serial-wire debug (SWD) interface.

For more technical information about the debug interface the reader is referred to: • ARM Cortex-M0+ Technical Reference Manual • ARM CoreSight Components Technical Reference Manual • ARM Debug Interface v5 Architecture Specification

6.2 Features

• Flash Patch and Breakpoint (FPB) unit • Implement breakpoints and code patches • Data Watch point and Trace (DWT) unit • Implement watch points, trigger resources and system profiling

6.3 Functional Description

There are two debug pins available on the device. Their operation is described in the following section.

6.3.1 Debug Pins

The following pins are the debug connections for the device: • Serial Wire Clock input (SWCLK): This pin is enabled after reset and has a built-in pull down.

• Serial Wire Data Input/Output (SWDIO): This pin is enabled after reset and has a built-in pull-up.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

23

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

The debug pins can be enabled and disabled through GPIO_ROUTE, see Section 26.3.4.1 (p. 529)

. Please remeberer that upon disabling, debug contact with the device is lost. Also note that, because the debug pins have pull-down and pull-up enabled by default, leaving them enabled might increase the current consumption with up to 200 µA if left connected to supply or ground.

6.3.2 Debug and EM2/EM3

Leaving the debugger connected when issuing a WFI or WFE to enter EM2 or EM3 will make the system enter a special EM2. This mode differs from regular EM2 and EM3 in that the high frequency clocks are still enabled, and certain core functionality is still powered in order to maintain debug-functionality.

Because of this, the current consumption in this mode is closer to EM1 and it is therefore important to disconnect the debugger before doing current consumption measurements.

6.4 Debug Lock and Device Erase

The debug access to the Cortex-M0+ is locked by clearing the Debug Lock Word (DLW) and resetting

the device, see Section 7.3.2 (p. 30) .

When debug access is locked, the debug interface remains accessible but the connection to the Cortex-

M0+ core and the whole bus-system is blocked as shown in Figure 6.2 (p. 25) . This mechanism is

controlled by the Authentication Access Port (AAP) as illustrated by Figure 6.1 (p. 24) . The AAP is

only accessible from a debugger and not from the core.

Figure 6.1. AAP - Authentication Access Port

DEVICEERASE ERASEBUSY SerialWire debug int erface SW- DP AHB- AP Aut hent icat ion Access Port (AAP) DLW[3:0] = = 0x F

Cortex

As seen from Figure 6.1 (p. 24) , the AAP is situated after the AHB-AP, meaning it should be accessed

like any other peripheral from the debug. The address of the AAP is 0xF0E00000 as can also be seen

from Figure 5.2 (p. 16) .

Note

This is different from some other EFM32 devices, where the AAP is integrated as a separate AP (Access Port), please see the reference manual of the respective devices.

The debugger can access the AAP-registers, and only these registers just after reset, for the time of the

AAP-window outlined in Figure 6.2 (p. 25) . If the device is locked, access to the core and bus-system

is blocked even after code execution starts, and the debugger can only access the AAP-registers. If the device is not locked, the AAP is no longer accessible after code execution starts, and the debugger can access the core and bus-system normally. The AAP window can be extended by issuing the bit pattern

on SWDIO/SWCLK as shown in Figure 6.3 (p. 25) . This pattern should be applied just before reset

is deasserted, and will give the debugger more time to access the AAP.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

24

www.silabs.com

Figure 6.2. Device Unlock

Preliminary

...the world's most energy friendly microcontrollers

Reset Locked No access 150 us Unlocked No access Ex t ended unlocked No access AAP Program ex ecut ion Program ex ecut ion AAP Cort ex 47 us Ex t ended AAP Program ex ecut ion Cort ex 255 x 47 us

Figure 6.3. AAP Expansion

SWDIO SWCLK AAP ex pand If the device is locked, it can be unlocked by writing a valid key to the AAP_CMDKEY register and then setting the DEVICEERASE bit of the AAP_CMD register via the debug interface. The commands are not executed before AAP_CMDKEY is invalidated, so this register should be cleared to to start the erase operation. This operation erases the main block of flash, all lock bits are reset and debug access through the AHB-AP is enabled. The operation takes 40 ms to complete. Note that the SRAM contents will also be deleted during a device erase, while the UD-page is not erased.

Even if the device is not locked, the can device can be erased through the AAP, using the above procedure during the AAP window. This can be useful if the device has been programmed with code that, e.g., disables the debug interface pins on start-up, or does something else that prevents communication with a debugger.

If the device is locked, the debugger may read the status from the AAP_STATUS register. When the ERASEBUSY bit is set low after DEVICEERASE of the AAP_CMD register is set, the debugger may set the SYSRESETREQ bit in the AAP_CMD register. After reset, the debugger may resume a normal debug session through the AHB-AP. If the device is not locked, the device erase starts when the AAP window closes, so it is not possible to poll the status.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

25

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

6.5 Register Map

The offset register address is relative to the registers base address.

Offset

0x000 0x004

0x008 0x0FC

Name

AAP_CMD AAP_CMDKEY

AAP_STATUS AAP_IDR

Type

W1 W1 R R

Description

Command Register Command Key Register

Status Register AAP Identification Register

6.6 Register Description 6.6.1 AAP_CMD - Command Register Offset

0x000

Reset Access Bit Position Name Bit

31:2

1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SYSRESETREQ 0 W1

System Reset Request

A system reset request is generated when set to 1. This register is write enabled from the AAP_CMDKEY register.

DEVICEERASE 0 W1

Erase the Flash Main Block, SRAM and Lock Bits

When set, all data and program code in the main block is erased, the SRAM is cleared and then the Lock Bit (LB) page is erased.

This also includes the Debug Lock Word (DLW), causing debug access to be enabled after the next reset. The information block User Data page (UD) is left unchanged, but the User data page Lock Word (ULW) is erased. This register is write enabled from the AAP_CMDKEY register.

6.6.2 AAP_CMDKEY - Command Key Register Offset

0x004

Bit Position Reset Access Name Bit

31:0

Name

WRITEKEY

Reset

0x00000000

Access

W1

Description CMD Key Register

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

26

www.silabs.com

Bit Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

The key value must be written to this register to write enable the AAP_CMD register. After AAP_CMD is written, this register should be cleared to excecute the command.

Value 0xCFACC118 Mode WRITEEN Description Enable write to AAP_CMD

6.6.3 AAP_STATUS - Status Register Offset

0x008

Reset Access Bit Position Name Bit

31:1

0

Name

Reserved

ERASEBUSY

Reset

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 This bit is set when a device erase is executing.

Access

R

Description Device Erase Command Status 6.6.4 AAP_IDR - AAP Identification Register Offset

0x0FC

Bit Position Reset Access Name Bit

31:0

Name Reset Access Description

ID 0x16E60001 R

AAP Identification Register

Access port identification register in compliance with the ARM ADI v5 specification (JEDEC Manufacturer ID) .

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

27

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

7 MSC - Memory System Controller

0 1 2 3 4

01000101011011100110010101110010 01100111011110010010000001001101 01101001011000110111001001101111 00100000011100100111010101101100 01100101011100110010000001110100 01101000011001010010000001110111 01101111011100100110110001100100 00100000011011110110011000100000 01101100011011110111011100101101 01100101011011100110010101110010 01100111011110010010000001101101 01101001011000110111001001101111 01100011011011110110111001110100 01110010011011110110110001101100 01100101011100100010000001100100 01100101011100110110100101100111 01101110001000010100010101101110

Quick Facts What?

The user can perform Flash memory read, read configuration and write operations through the Memory System Controller (MSC) .

Why?

The MSC allows the application code, user data and flash lock bits to be stored in non volatile Flash memory. Certain memory system functions, such as program memory wait-states and bus faults are also configured from the MSC peripheral register interface, giving the developer the ability to dynamically customize the memory system performance, security level, energy consumption and error handling capabilities to the requirements at hand.

How?

The MSC integrates a low-energy Flash IP with a charge pump, enabling minimum energy consumption while eliminating the need for external programming voltage to erase the memory. An easy to use write and erase interface is supported by an internal, fixed-frequency oscillator and autonomous flash timing and control reduces software complexity while not using other timer resources.

Application code may dynamically scale between high energy optimization and high code execution performance through advanced read modes.

A highly efficient low energy instruction cache reduces the number of flash reads significantly, thus saving energy.

Performance is also improved when wait states are used, since many of the wait-states are eliminated. Built-in performance counters can be used to measure the efficiency of the instruction cache.

7.1 Introduction

The Memory System Controller (MSC) is the program memory unit of the EFM32HG microcontroller.

The flash memory is readable and writable from both the Cortex-M0+ and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock bits.

There is also a read-only page in the information block containing system and device calibration data.

Read and write operations are supported in the energy modes EM0 and EM1.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

28

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

7.2 Features

• AHB read interface • Scalable access performance to optimize the Cortex-M0+ code interface • Zero wait-state access up to 16 MHz and one wait-state for 16 MHz and above • Advanced energy optimization functionality • Instruction Cache • DMA read support in EM0 and EM1 • Command and status interface • Flash write and erase • Accessible from Cortex-M0+ in EM0 • DMA write support in EM0 and EM1 • Core clock independent Flash timing • Internal oscillator and internal timers for precise and autonomous Flash timing • General purpose timers are not occupied during Flash erase and write operations • Configurable interrupt erase abort • Improved interrupt predictability • Memory and bus fault control • Security features • Lockable debug access • Page lock bits • SW Mass erase Lock bits • User data lock bits • End-of-write and end-of-erase interrupts

7.3 Functional Description

The size of the main block is device dependent. The largest size available is 64 kB (64 pages). The information block has 1024 bytes available for user data. The information block also contains chip configuration data located in a reserved area. The main block is mapped to address 0x00000000 and

the information block is mapped to address 0x0FE00000. Table 7.1 (p. 30) outlines how the Flash

is mapped in the memory space. All Flash memory is organized into 1024 byte pages.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

29

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Table 7.1. MSC Flash Memory Mapping

Block

Main 1 Reserved

Page

.

0 63

Base address

0x00000000

Write/Erase by Software readable

Software, debug Yes 0x0000FC00 0x00010000 Software, debug Yes Software, debug Yes -

Purpose/Name

User code and data

Size

32 kB - 64 kB ~24 MB Information Reserved 0 1 2 0x0FE00000 0x0FE00400 0x0FE04000 0x0FE04400 0x0FE08000 0x0FE08400 0x0FE10000 Software, debug Yes Write: Software, debug Yes Erase: Debug only Yes Reserved for flash expansion User Data (UD) Reserved Lock Bits (LB) Reserved Device Information (DI) Reserved Reserved for flash expansion 1 kB 1 kB 1 kB Rest of code space 1 Block/page erased by a device erase

7.3.1 User Data (UD) Page Description

This is the user data page in the information block. The page can be erased and written by software. The page is erased by the ERASEPAGE command of the MSC_WRITECMD register. Note that the page is

not erased by a device erase operation. The device erase operation is described in Section 6.4 (p. 24) .

7.3.2 Lock Bits (LB) Page Description

This page contains the following information: • Debug Lock Word (DLW) • User data page Lock Word (ULW) • Mass erase Lock Word (MLW) • Main block Page Lock Words (PLWs)

The words in this page are organized as shown in Table 7.2 (p. 30) :

Table 7.2. Lock Bits Page Structure

… 1 0 127 126 125 N DLW ULW MLW PLW[N] … PLW[1] PLW[0] 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

30

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Word 127 is the debug lock word (DLW). The four LSBs of this word are the debug lock bits. If these bits are 0xF, then debug access is enabled. If the bits are not 0xF, then debug access to the core is locked.

See Section 6.4 (p. 24) for details on how to unlock the debug access.

Word 126 is the user page lock word (ULW). Bit 0 of this word is the User Data Page lock bit. Bit 1 in this word locks the Lock Bits Page.

Word 125 is the mass erase lock word (MLW). Bit 0 locks the entire flash. The mass erase lock bits will not have any effect on device erases initiated from the Authentication Access Port (AAP) registers. The

AAP is described in more detail in Section 6.4 (p. 24) .

There are 32 page lock bits per page lock word (PLW). Bit 0 refers to the first page and bit 31 refers to the last page within a PLW. Thus, PLW[0] contains lock bits for page 0-31 in the main block. Similarly, PLW[1] contains lock bits for page 32-63 and so on. A page is locked when the bit is 0. A locked page cannot be erased or written.

The lock bits can be reset by a device erase operation initiated from the Authentication Access Port

(AAP) registers. The AAP is described in more detail in Section 6.4 (p. 24) . Note that the AAP is only

accessible from the debug interface, and cannot be accessed from the Cortex-M0+ core.

7.3.3 Device Information (DI) Page

This read-only page holds the calibration data for the oscillator and other analog peripherals from the

production test as well as a unique device ID. The page is further described in Section 5.6 (p. 21) .

7.3.4 Post-reset Behavior

Calibration values are automatically written to registers by the MSC before application code startup. The values are also available to read from the DI page for later reference by software. Other information such as the device ID and production date is also stored in the DI page and is readable from software.

7.3.4.1 One Wait-state Access

After reset, the HFCORECLK is normally 14 MHz from the HFRCO and the MODE field of the MSC_READCTRL register is set to WS1 (one wait-state). The reset value must be WS1 as an uncalibrated HFRCO may produce a frequency higher than 16 MHz. Software must not select a zero wait-state mode unless the clock is guaranteed to be 16 MHz or below, otherwise the resulting behavior is undefined. If a HFCORECLK frequency above 16 MHz is to be set by software, the MODE field of the MSC_READCTRL register must be set to WS1 before the core clock is switched to the higher frequency clock source.

When changing to a lower frequency, the MODE field of the MSC_READCTRL register can be set to WS0, but only after the frequency transition is completed. If the HFRCO is used, wait until the oscillator is stable on the new frequency. Otherwise, the behavior is unpredictable.

7.3.4.2 Zero Wait-state Access

At 16 MHz and below, read operations from flash may be performed without any wait-states. Zero wait state access greatly improves code execution performance at frequencies from 16 MHz and below.

7.3.4.3 Instruction Cache

The MSC includes an instruction cache. The instruction cache for the internal flash memory is enabled by default, but can be disabled by setting IFCDIS in MSC_READCTRL. When enabled, the instruction cache typically reduces the number of flash reads significantly, thus saving energy. In most cases a cache hit-rate of more than 70 % is achievable. When a 32-bit instruction fetch hits in the cache the data 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

31

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

is returned to the processor in one clock cycle. Thus, performance is also improved when wait-states are used (i.e. running at frequencies above 16 MHz).

The instruction cache is connected directly to the Cortex-M0+ and functions as a memory access filter

between the processor and the memory system, as illustrated in Figure 7.1 (p. 32) . The cache

consists of an access filter, lookup logic, a 128x32 SRAM (512 bytes) and two performance counters.

The access filter checks that the address for the access is of an instruction in the code space (instructions in RAM outside the code space are not cached). If the address matches, the cache lookup logic and SRAM is enabled. Otherwise, the cache is bypassed and the access is forwarded to the memory system.

The cache is then updated when the memory access completes. The performance counters, when enabled, keep track of the number of cache hits and misses. The cache consists of 16 8-word cachelines organized as 4 sets with 4 ways. The cachelines are filled up continuously one word at a time as the individual words are requested by the processor. Thus, not all words of a cacheline might be valid at a given time.

Figure 7.1. Instruction Cache

Cort ex AHB- Lit e Bus Inst ruct ion Cache Cache Look- up Logic Access Filt er 128x 32 SRAM Perform ance Count ers AHB- Lit e Bus CODE Mem ory Space By default, the instruction cache is automatically invalidated when the contents of the flash is changed (i.e. written or erased). In many cases, however, the application only makes changes to data in the flash, not code. In this case, the automatic invalidate feature can be disabled by setting AIDIS in MSC_READCTRL. The cache can (independent of the AIDIS setting) be manually invalidated by writing 1 to INVCACHE in MSC_CMD.

In general it is highly recommended to keep the cache enabled all the time. However, for some sections of code with very low cache hit-rate more energy-efficient execution can be achieved by disabling the cache temporarily. To measure the hit-rate of a code-section, the built-in performance counters can be used. Before the section, start the performance counters by writing 1 to STARTPC in MSC_CMD.

This starts the performance counters, counting from 0. At the end of the section, stop the performance counters by writing 1 to STOPPC in MSC_CMD. The number of cache hits and cache misses for that section can then be read from MSC_CACHEHITS and MSC_CACHEMISSES respectively. The total number of 32-bit instruction fetches will be MSC_CACHEHITS + MSC_CACHEMISSES. Thus, the cache hit-ratio can be calculated as MSC_CACHEHITS / (MSC_CACHEHITS + MSC_CACHEMISSES).

When MSC_CACHEHITS overflows the CHOF interrupt flag is set. When MSC_CACHEMISSES overflows the CMOF interrupt flag is set. These flags must be cleared explicitly by software. The range of the performance counters can thus be extended by increasing a counter in the MSC interrupt routine. The performance counters only count when a cache lookup is performed. If the lookup fails, MSC_CACHEMISSES is increased. If the lookup is successful, MSC_CACHEHITS is increased. For example, a cache lookup is not performed if the cache is disabled or the code is executed from RAM outside the code space.

The cache content is not retained in EM2, EM3 and EM4. The cache is therefore invalidated regardless of the setting of AIDIS in MSC_READCTRL when entering these energy modes. Applications that switch frequently between EM0 and EM2/3 and execute the very same non-looping code almost every time will most likely benefit from putting this code in RAM. The interrupt vectors can also be put in RAM to reduce current consumption even further.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

32

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

7.3.5 Erase and Write Operations

The AUXHFRCO is used for timing during flash write and erase operations. To achieve correct timing, the MSC_TIMEBASE register has to be configured according to the settings in CMU_AUXHFRCOCTRL.

BASE in MSC_TIMEBASE defines how many AUXCLK cycles - 1 there is in 1 us or 5 us, depending on the configuration of PERIOD. To ensure that timing of flash write and erase operations is within the specification of the flash, the value written to BASE should give at least a 10% margin with respect to the period, i.e. for the 1 us PERIOD, the number of cycles should at least span 1.1 us, and for the 5 us period they should span at least 5.5 us. For the 1 MHz band, PERIOD in MSC_TIMEBASE should be set to 5US, while it should be set to 1US for all other AUXHFRCO bands.

Both page erase and write operations require that the address is written into the MSC_ADDRB register.

For erase operations, the address may be any within the page to be erased. Load the address by writing 1 to the LADDRIM bit in the MSC_WRITECMD register. The LADDRIM bit only has to be written once when loading the first address. After each word is written the internal address register ADDR will be incremented automatically by 4. The INVADDR bit of the MSC_STATUS register is set if the loaded address is outside the flash and the LOCKED bit of the MSC_STATUS register is set if the page addressed is locked. Any attempts to command erase of or write to the page are ignored if INVADDR or the LOCKED bits of the MSC_STATUS register are set. To abort an ongoing erase, set the ERASEABORT bit in the MSC_WRITECMD register.

When a word is written to the MSC_WDATA register, the WDATAREADY bit of the MSC_STATUS register is cleared. When this status bit is set, software or DMA may write the next word.

A single word write is commanded by setting the WRITEONCE bit of the MSC_WRITECMD register.

The operation is complete when the BUSY bit of the MSC_STATUS register is cleared and control of the flash is handed back to the AHB interface, allowing application code to resume execution.

For a DMA write the software must write the first word to the MSC_WDATA register and then set the WRITETRIG bit of the MSC_WRITECMD register. DMA triggers when the WDATAREADY bit of the MSC_STATUS register is set.

It is possible to write words twice between each erase by keeping at 1 the bits that are not to be changed.

Let us take as an example writing two 16 bit values, 0xAAAA and 0x5555. To safely write them in the same flash word this method can be used: • Write 0xFFFFAAAA (word in flash becomes 0xFFFFAAAA) • Write 0x5555FFFF (word in flash becomes 0x5555AAAA) Note that there is a maximum of two writes to the same word between each erase due to a physical limitation of the flash.

Note

During a write or erase, flash read accesses will be stalled, effectively halting code execution from flash. Code execution continues upon write/erase completion. Code residing in RAM may be executed during a write/erase operation.

Note

The MSC_WDATA and MSC_ADDRB registers are not retained when entering EM2 or lower energy modes.

7.3.5.1 Mass erase

A mass erase can be initiated from software using ERASEMAIN0 in MSC_WRITECMD. This command will start a mass erase of the entire flash. Prior to initiating a mass erase, MSC_MASSLOCK must be unlocked by writing 0x631A to it. After a mass erase has been started, this register can be locked again to prevent runaway code from accidentally triggering a mass erase.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

33

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

The regular flash page lock bits will not prevent a mass erase. To prevent software from initiating mass erases, use the mass erase lock bits in the mass erase lock word (MLW).

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

34

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

7.4 Register Map

The offset register address is relative to the registers base address.

Offset

0x000

0x004 0x008

0x00C

0x010 0x018 0x01C

0x02C

0x030 0x034

0x038 0x03C

0x040 0x044

0x048 0x050

0x054 0x058

Name

MSC_CTRL

MSC_READCTRL MSC_WRITECTRL

MSC_WRITECMD

MSC_ADDRB MSC_WDATA MSC_STATUS

MSC_IF

MSC_IFS MSC_IFC

MSC_IEN MSC_LOCK

MSC_CMD MSC_CACHEHITS

MSC_CACHEMISSES MSC_TIMEBASE

MSC_MASSLOCK MSC_IRQLATENCY

Type

R R RW RW RW RW RW RW W1 RW RW R R W1 W1 RW RW W1

Description

Memory System Control Register

Read Control Register Write Control Register

Write Command Register

Page Erase/Write Address Buffer Write Data Register Status Register

Interrupt Flag Register

Interrupt Flag Set Register Interrupt Flag Clear Register

Interrupt Enable Register Configuration Lock Register

Command Register Cache Hits Performance Counter

Cache Misses Performance Counter Flash Write and Erase Timebase

Mass Erase Lock Register Irq Latency Register

7.5 Register Description 7.5.1 MSC_CTRL - Memory System Control Register Offset

0x000

Reset Access Bit Position Name Bit

31:1

0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BUSFAULT 1 RW

Bus Fault Response Enable

When this bit is set, the memory system generates bus error response.

Value 0 1 Mode GENERATE IGNORE Description A bus fault is generated on access to unmapped code and system space.

Accesses to unmapped address space is ignored.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

35

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

7.5.2 MSC_READCTRL - Read Control Register Offset

0x004

Reset Access Bit Position Name Bit

31:8

7

6:5

4 3 2:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RAMCEN 0 RW Enable instruction caching for RAM in code-space.

Reserved

RAM Cache Enable

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

AIDIS 0 RW

Automatic Invalidate Disable

When this bit is set the cache is not automatically invalidated when a write or page erase is performed.

IFCDIS 0 RW Disable instruction cache for internal flash memory.

Internal Flash Cache Disable

MODE 0x1 RW

Read Mode

If software wants to set a core clock frequency above 16 MHz, this register must be set to WS1 before the core clock is switched to the higher frequency. When changing to a lower frequency, this register can be set to WS0 after the frequency transition has been completed. After reset, the core clock is 14 MHz from the HFRCO but the MODE field of MSC_READCTRL register is set to WS1.

This is because the HFRCO may produce a frequency above 16 MHz before it is calibrated. If the HFRCO is used as clock source, wait until the oscillator is stable on the new frequency to avoid unpredictable behavior.

Value 0 1 Mode WS0 WS1 Description Zero wait-states inserted in fetch or read transfers.

One wait-state inserted for each fetch or read transfer. This mode is required for a core frequency above 16 MHz.

7.5.3 MSC_WRITECTRL - Write Control Register Bit Position Offset

0x008

Reset Access Name Bit

31:2

1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

IRQERASEABORT 0 RW

Abort Page Erase on Interrupt

When this bit is set to 1, any Cortex interrupt aborts any current page erase operation.

WREN 0 RW

Enable Write/Erase Controller

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

36

www.silabs.com

Bit Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

When this bit is set, the MSC write and erase functionality is enabled.

7.5.4 MSC_WRITECMD - Write Command Register Bit Position Offset

0x00C

Reset Access Name Bit

31:13

12

11:9

8

7:6

5 4 3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CLEARWDATA 0 W1

Clear WDATA state

Will set WDATAREADY and DMA request. Should only be used when no write is active.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

ERASEMAIN0 0 W1

Mass erase region 0

Initiate mass erase of region 0. For devices supporting read-while-write, this is the lower half of the flash. For other devices it is the entire flash. Before use MSC_MASSLOCK must be unlocked. To completely prevent access from software, clear bit 0 in the mass erase lock-word (MLW).

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

ERASEABORT 0 W1 Writing to this bit will abort an ongoing erase sequence.

Abort erase sequence

WRITETRIG 0 W1

Word Write Sequence Trigger

Functions like MSC_CMD_WRITEONCE, but will set MSC_STATUS_WORDTIMEOUT if no new data is written to MSC_WDATA within the 30 µs timeout.

WRITEONCE 0 W1

Word Write-Once Trigger

Start write of the first word written to MSC_WDATA, then add 4 to ADDR and write the next word if available within a 30 µs timeout.

When ADDR is incremented past the page boundary, ADDR is set to the base of the page.

WRITEEND 0 W1

End Write Mode

Write 1 to end write mode when using the WRITETRIG command.

ERASEPAGE 0 W1

Erase Page

Erase any user defined page selected by the MSC_ADDRB register. The WREN bit in the MSC_WRITECTRL register must be set in order to use this command.

LADDRIM 0 W1

Load MSC_ADDRB into ADDR

Load the internal write address register ADDR from the MSC_ADDRB register. The internal address register ADDR is incremented automatically by 4 after each word is written. When ADDR is incremented past the page boundary, ADDR is set to the base of the page.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

37

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

7.5.5 MSC_ADDRB - Page Erase/Write Address Buffer Offset

0x010

Bit Position Reset Access Name Bit

31:0

Name Reset Access Description

ADDRB 0x00000000 RW

Page Erase or Write Address Buffer

This register holds the page address for the erase or write operation. This register is loaded into the internal MSC_ADDR register when the LADDRIM field in MSC_WRITECMD is set. The MSC_ADDR register is not readable. This register is not retained when entering EM2 or lower energy modes.

7.5.6 MSC_WDATA - Write Data Register Offset

0x018

Bit Position Reset Access Name Bit

31:0

Name Reset Access Description

WDATA 0x00000000 RW

Write Data

The data to be written to the address in MSC_ADDR. This register must be written when the WDATAREADY bit of MSC_STATUS is set. This register is not retained when entering EM2 or lower energy modes.

7.5.7 MSC_STATUS - Status Register Offset

0x01C

Reset Access Bit Position Name

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

38

www.silabs.com

2 1 0 5 4

Bit

31:7

6 3

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PCRUNNING 0 R

Performance Counters Running

This bit is set while the performance counters are running. When one performance counter reaches the maximum value, this bit is cleared.

ERASEABORTED 0 R

The Current Flash Erase Operation Aborted

When set, the current erase operation was aborted by interrupt.

WORDTIMEOUT 0 R

Flash Write Word Timeout

When this bit is set, MSC_WDATA was not written within the timeout. The flash write operation timed out and access to the flash is returned to the AHB interface. This bit is cleared when the ERASEPAGE, WRITETRIG or WRITEONCE commands in MSC_WRITECMD are triggered.

WDATAREADY 1 R

WDATA Write Ready

When this bit is set, the content of MSC_WDATA is read by MSC Flash Write Controller and the register may be updated with the next 32-bit word to be written to flash. This bit is cleared when writing to MSC_WDATA.

INVADDR 0 R

Invalid Write Address or Erase Page

Set when software attempts to load an invalid (unmapped) address into ADDR.

LOCKED 0 R

Access Locked

When set, the last erase or write is aborted due to erase/write access constraints.

BUSY 0 R

Erase/Write Busy

When set, an erase or write operation is in progress and new commands are ignored.

7.5.8 MSC_IF - Interrupt Flag Register Bit Position Offset

0x02C

Reset Access Name

1 0

Bit

31:4

3 2

Name

Reserved

CMOF

Reset

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Set when MSC_CACHEMISSES overflows.

CHOF 0 Set when MSC_CACHEHITS overflows.

WRITE Set when a write is done.

ERASE Set when erase is done.

0 0

Access

R R R R

Description Cache Misses Overflow Interrupt Flag Cache Hits Overflow Interrupt Flag Write Done Interrupt Read Flag Erase Done Interrupt Read Flag

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

39

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

7.5.9 MSC_IFS - Interrupt Flag Set Register Offset

0x030

Reset Access Bit Position Name

2 1 0

Bit

31:4

3

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CMOF 0 Set the CMOF flag and generate interrupt.

CHOF 0 Set the CHOF flag and generate interrupt.

W1 W1 WRITE 0 Set the write done bit and generate interrupt.

W1 ERASE 0 Set the erase done bit and generate interrupt.

W1

Cache Misses Overflow Interrupt Set Cache Hits Overflow Interrupt Set Write Done Interrupt Set Erase Done Interrupt Set 7.5.10 MSC_IFC - Interrupt Flag Clear Register Bit Position Offset

0x034

Reset Access Name

2 1 0

Bit

31:4

3

Name Reset Access Description

Reserved

CMOF 0 Clear the CMOF interrupt flag.

CHOF 0 Clear the CHOF interrupt flag.

WRITE Clear the write done bit.

0 ERASE Clear the erase done bit.

0

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

W1

Cache Misses Overflow Interrupt Clear

W1 W1 W1

Cache Hits Overflow Interrupt Clear Write Done Interrupt Clear Erase Done Interrupt Clear

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

40

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

7.5.11 MSC_IEN - Interrupt Enable Register Offset

0x038

Reset Access Bit Position Name

1 0

Bit

31:4

3 2

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CMOF 0 RW

Cache Misses Overflow Interrupt Enable

Enable the cache misses performance counter overflow interrupt.

CHOF 0 RW Enable the cache hits performance counter overflow interrupt.

Cache Hits Overflow Interrupt Enable

WRITE 0 Enable the write done interrupt.

RW

Write Done Interrupt Enable

ERASE 0 Enable the erase done interrupt.

RW

Erase Done Interrupt Enable 7.5.12 MSC_LOCK - Configuration Lock Register Offset

0x03C

Bit Position Reset Access Name Bit

31:16

15:0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LOCKKEY 0x0000 RW

Configuration Lock

Write any other value than the unlock code to lock access to MSC_CTRL, MSC_READCTRL, MSC_WRITECTRL and MSC_TIMEBASE. Write the unlock code to enable access. When reading the register, bit 0 is set when the lock is enabled.

Mode Read Operation UNLOCKED LOCKED Write Operation LOCK UNLOCK Value 0 1 0 0x1B71 Description MSC registers are unlocked.

MSC registers are locked.

Lock MSC registers.

Unlock MSC registers.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

41

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

7.5.13 MSC_CMD - Command Register Offset

0x040

Reset Access Bit Position Name

1 0

Bit

31:3

2

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

STOPPC 0 W1 Use this command bit to stop the performance counters.

Stop Performance Counters

STARTPC 0 W1

Start Performance Counters

Use this command bit to start the performance counters. The performance counters always start counting from 0.

INVCACHE 0 W1 Use this register to invalidate the instruction cache.

Invalidate Instruction Cache 7.5.14 MSC_CACHEHITS - Cache Hits Performance Counter Offset

0x044

Bit Position Reset Access Name Bit

31:20

19:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CACHEHITS 0x00000 R

Cache hits since last performance counter start command.

Use to measure cache performance for a particular code section.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

42

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

7.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter Offset

0x048

Bit Position Reset Access Name Bit

31:20

19:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CACHEMISSES 0x00000 R

Cache misses since last performance counter start command.

Use to measure cache performance for a particular code section.

7.5.16 MSC_TIMEBASE - Flash Write and Erase Timebase Bit Position Offset

0x050

Reset Access Name Bit

31:17

16

15:6

5:0

Name Reset Access Description

Reserved

Value 0 1 Mode 1US 5US

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PERIOD 0 RW

Sets the timebase period

Decides whether TIMEBASE specifies the number of AUX cycles in 1 us or 5 us. 5 us should only be used with 1 MHz AUXHFRCO band.

Description TIMEBASE period is 1 us.

TIMEBASE period is 5 us.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BASE 0x10 RW

Timebase used by MSC to time flash writes and erases

Should be set to the number of full AUX clock cycles in the period given by MSC_TIMEBASE_PERIOD. I.e. 1.1 us or 5.5. us with PERIOD cleared or set, respectively. The resetvalue of the timebase matches a 14 MHz AUXHFRCO, which is the default frequency of the AUXHFRCO.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

43

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

7.5.17 MSC_MASSLOCK - Mass Erase Lock Register Offset

0x054

Bit Position Reset Access Name Bit

31:16

15:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LOCKKEY 0x0001 RW

Mass Erase Lock

Write any other value than the unlock code to lock access the the ERASEMAIN0 and ERASEMAIN1 commands. Write the unlock code 631A to enable access. When reading the register, bit 0 is set when the lock is enabled. Locked by default.

Mode Read Operation UNLOCKED LOCKED Write Operation LOCK UNLOCK Value 0 1 0 0x631A Description Mass erase unlocked.

Mass erase locked.

Lock mass erase.

Unlock mass erase.

7.5.18 MSC_IRQLATENCY - Irq Latency Register Offset

0x058

Reset Access Bit Position Name Bit

31:8

7:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

IRQLATENCY 0x00 RW

Irq Latency Register

Specify the minimum number of HCORECLK-cycles to wait before handling an interrupt after it has been asserted. This can be used to achieve deterministic (zero-jitter) behavior when handling interrupts, at the cost of speed. To achieve zero-jitter with zero wait states in flash, set this to 9.

IRQLATENCY 0 1 - 255 Description Interrupts will be handled as quickly as possible.

The CM0+ will use at least IRQLATENCY+6 HFCORECLK-cycles to handle interrupts.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

44

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

8 DMA - DMA Controller

0 1 2 3 4

DMA cont roller Flash RAM Peripherals

Quick Facts What?

The DMA controller can move data without CPU intervention, effectively reducing the energy consumption for a data transfer.

Why?

The DMA can perform data transfers more energy efficiently than the CPU and allows autonomous operation in low energy modes.

The LEUART can for instance provide full UART communication in EM2, consuming only a few µA by using the DMA to move data between the LEUART and RAM.

How?

The DMA controller has multiple highly configurable, prioritized DMA channels.

Advanced transfer modes such as ping-pong and scatter-gather make it possible to tailor the controller to the specific needs of an application.

8.1 Introduction

The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.

This has the benefit of reducing the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes for example when moving data from the USART to RAM. The DMA controller uses the PL230 µDMA controller licensed from ARM 1 . Each of the PL230s channels on the EFM32 can be connected to any of the EFM32 peripherals.

8.2 Features

• The DMA controller is accessible as a memory mapped peripheral • Possible data transfers include • RAM/Flash to peripheral • RAM to Flash • Peripheral to RAM • RAM/Flash to RAM • The DMA controller has 4 independent channels • Each channel has one (primary) or two (primary and alternate) descriptors • The configuration for each channel includes • Transfer mode • Priority • Word-count • Word-size (8, 16, 32 bit) • The transfer modes include • Basic (using the primary or alternate DMA descriptor) 1 ARM PL230 homepage [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0417a/index.html] 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

45

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• Ping-pong (switching between the primary or alternate DMA descriptors, for continuous data flow to/from peripherals) • Scatter-gather (using the primary descriptor to configure the alternate descriptor) • Each channel has a programmable transfer length • Channels 0 and 1 support looped transfers • Channel 0 supports 2D copy • A DMA channel can be triggered by any of several sources: • Communication modules (USART, LEUART) • Timers (TIMER) • Analog modules (ACMP, ADC) • Software • Programmable mapping between channel number and peripherals - any DMA channel can be triggered by any of the available sources • Interrupts upon transfer completion • Data transfer to/from LEUART in EM2 is supported by the DMA, providing extremely low energy consumption while performing UART communications

8.3 Block Diagram

An overview of the DMA and the modules it interacts with is shown in Figure 8.1 (p. 46) .

Figure 8.1. DMA Block Diagram

Int errupt s Cort ex AHB Peripheral Peripheral AHB t o APB bridge Configurat ion cont rol APB block APB m em ory m apped regist ers Configurat ion Channel select REQ/ ACK DMA Core AHB block AHB- Lit e m ast er int erface DMA dat a t ransfer Error Channel done DMA cont rol block The DMA Controller consists of four main parts: • An APB block allowing software to configure the DMA controller • An AHB block allowing the DMA to read and write the DMA descriptors and the source and destination data for the DMA transfers • A DMA control block controlling the operation of the DMA, including request/acknowledge signals for the connected peripherals • A channel select block routing the right peripheral request to each DMA channel 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

46

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

8.4 Functional Description

The DMA Controller is highly flexible. It is capable of transferring data between peripherals and memory without involvement from the processor core. This can be used to increase system performance by off-loading the processor from copying large amounts of data or avoiding frequent interrupts to service peripherals needing more data or having available data. It can also be used to reduce the system energy consumption by making the DMA work autonomously with the LEUART for data transfer in EM2 without having to wake up the processor core from sleep.

The DMA Controller contains 4 independent channels. Each of these channels can be connected to any

of the available peripheral trigger sources by writing to the configuration registers, see Section 8.4.1 (p.

47) . In addition, each channel can be triggered by software (for large memory transfers or for

debugging purposes).

What the DMA Controller should do (when one of its channels is triggered) is configured through channel descriptors residing in system memory. Before enabling a channel, the software must therefore take care to write this configuration to memory. When a channel is triggered, the DMA Controller will first read the channel descriptor from system memory, and then it will proceed to perform the memory transfers as specified by the descriptor. The descriptor contains the memory address to read from, the memory address to write to, the number of bytes to be transferred, etc. The channel descriptor is described in

detail in Section 8.4.3 (p. 57) .

In addition to the basic transfer mode, the DMA Controller also supports two advanced transfer modes; ping-pong and scatter-gather. Ping-pong transfers are ideally suited for streaming data for high-speed peripheral communication as the DMA will be ready to retrieve the next incoming data bytes immediately while the processor core is still processing the previous ones (and similarly for outgoing communication).

Scatter-gather involves executing a series of tasks from memory and allows sophisticated schemes to be implemented by software.

Using different priority levels for the channels and setting the number of bytes after which the DMA Controller re-arbitrates, it is possible to ensure that timing-critical transfers are serviced on time.

8.4.1 Channel Select Configuration

The channel select block allows selecting which peripheral's request lines (dma_req, dma_sreq) to connect to each DMA channel.

This configuration is done by software through the control registers DMA_CH0_CTRL DMA_CH3_CTRL, with SOURCESEL and SIGSEL components. SOURCESEL selects which peripheral to listen to and SIGSEL picks which output signals to use from the selected peripheral.

All peripherals are connected to dma_req. When this signal is triggered, the DMA performs a number of transfers as specified by the channel descriptor (2 R ). The USARTs are additionally connected to the dma_sreq line. When only dma_sreq is asserted but not dma_req, then the DMA will perform exactly one transfer only (given that dma_sreq is enabled by software).

Note

A DMA channel should not be active when the clock to the selected peripheral is off.

8.4.2 DMA control 8.4.2.1 DMA arbitration rate

You can configure when the controller arbitrates during a DMA transfer. This enables you to reduce the latency to service a higher priority channel.

The controller provides four bits that configure how many AHB bus transfers occur before it re-arbitrates.

These bits are known as the R_power bits because the value you enter, R, is raised to the power of two 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

47

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

and this determines the arbitration rate. For example, if R = 4 then the arbitration rate is 2 4 , that is, the controller arbitrates every 16 DMA transfers.

Table 8.1 (p. 48) lists the arbitration rates.

Table 8.1. AHB bus transfer arbitration interval

R_power b0000 b0001 b0010 b0011 b0100 b0101 b0110 Arbitrate after x DMA transfers x = 1 x = 2 x = 4 x = 8 x = 16 x = 32 x = 64 b0111 b1000 b1001 b1010 - b1111 x = 128 x = 256 x = 512 x = 1024

Note

You must take care not to assign a low-priority channel with a large R_power because this prevents the controller from servicing high-priority requests, until it re-arbitrates.

The number of dma transfers N that need to be done is specified by the user. When N > 2 R and is not an integer multiple of 2 R then the controller always performs sequences of 2 R transfers until N < 2 R remain to be transferred. The controller performs the remaining N transfers at the end of the DMA cycle.

You store the value of the R_power bits in the channel control data structure. See Section 8.4.3.3 (p.

60) for more information about the location of the R_power bits in the data structure.

8.4.2.2 Priority

When the controller arbitrates, it determines the next channel to service by using the following information: • the channel number • the priority level, default or high, that is assigned to the channel.

You can configure each channel to use either the default priority level or a high priority level by setting the DMA_CHPRIS register.

Channel number zero has the highest priority and as the channel number increases, the priority of a

channel decreases. Table 8.2 (p. 48) lists the DMA channel priority levels in descending order of

priority.

Table 8.2. DMA channel priority

0 1 2 Channel number Priority level setting High High High Descending order of channel priority Highest-priority DMA channel 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

48

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

0 1 2 3 Channel number 3 Priority level setting High Default Default Default Default Descending order of channel priority Lowest-priority DMA channel

After a DMA transfer completes, the controller polls all the DMA channels that are available. Figure 8.2 (p.

49) shows the process it uses to determine which DMA transfer to perform next.

Figure 8.2. Polling flowchart

St art polling Is t here a channel request ?

No Yes Are any channel request s using a high priorit y level ?

No Yes Select channel t hat has t he lowest channel num ber and is set t o high priorit y- level Select channel t hat has t he lowest channel num ber St art DMA t ransfer

8.4.2.3 DMA cycle types

The cycle_ctrl bits control how the controller performs a DMA cycle. You can set the cycle_ctrl bits as

Table 8.3 (p. 49) lists.

Table 8.3. DMA cycle types

cycle_ctrl b000 b001 b010 b011 b100 Description Channel control data structure is invalid Basic DMA transfer Auto-request Ping-pong Memory scatter-gather using the primary data structure 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

49

www.silabs.com

cycle_ctrl b101 b110 b111

Preliminary

...the world's most energy friendly microcontrollers

Description Memory scatter-gather using the alternate data structure Peripheral scatter-gather using the primary data structure Peripheral scatter-gather using the alternate data structure

Note

The cycle_ctrl bits are located in the channel_cfg memory location that Section 8.4.3.3 (p.

60) describes.

For all cycle types, the controller arbitrates after 2 R DMA transfers. If you set a low-priority channel with a large 2 R value then it prevents all other channels from performing a DMA transfer, until the low-priority DMA transfer completes. Therefore, you must take care when setting the R_power, that you do not significantly increase the latency for high-priority channels.

8.4.2.3.1 Invalid

After the controller completes a DMA cycle it sets the cycle type to invalid, to prevent it from repeating the same DMA cycle.

8.4.2.3.2 Basic

In this mode, you configure the controller to use either the primary or the alternate data structure. After you enable the channel C and the controller receives a request for this channel, then the flow for this DMA cycle is as follows: 1. The controller performs 2 R transfers. If the number of transfers remaining becomes zero, then the

flow continues at step 3 (p. 50) .

2. The controller arbitrates: • if a higher-priority channel is requesting service then the controller services that channel

• if the peripheral or software signals a request to the controller then it continues at step 1 (p. 50) .

3. The controller sets dma_done[C] HIGH for one HFCORECLK cycle. This indicates to the host processor that the DMA cycle is complete.

8.4.2.3.3 Auto-request

When the controller operates in this mode, it is only necessary for it to receive a single request to enable it to complete the entire DMA cycle. This enables a large data transfer to occur, without significantly increasing the latency for servicing higher priority requests, or requiring multiple requests from the processor or peripheral.

You can configure the controller to use either the primary or the alternate data structure. After you enable the channel C and the controller receives a request for this channel, then the flow for this DMA cycle is as follows: 1. The controller performs 2 R transfers for channel C. If the number of transfers remaining is zero the

flow continues at step 3 (p. 50) .

2. The controller arbitrates. When channel C has the highest priority then the DMA cycle continues at

step 1 (p. 50) .

3. The controller sets dma_done[C] HIGH for one HFCORECLK cycle. This indicates to the host processor that the DMA cycle is complete.

8.4.2.3.4 Ping-pong

In ping-pong mode, the controller performs a DMA cycle using one of the data structures (primary or alternate) and it then performs a DMA cycle using the other data structure. The controller continues to 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

50

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

switch from primary to alternate to primary… until it reads a data structure that is invalid, or until the host processor disables the channel.

Figure 8.3 (p. 51) shows an example of a ping-pong DMA transaction.

Figure 8.3. Ping-pong example

Task A: Prim ary, cycle_ct rl = b011, 2 R = 4, N = 6 Request Task A Request Task B: Alt ernat e, cycle_ct rl = b011, 2 R = 4, N = 12 Request Request Request Task B

dma_done[C] dma_done[C]

Task C: Prim ary, cycle_ct rl = b011, 2 R = 2, N = 2 Request Task C

dma_done[C]

Task D: Alt ernat e, cycle_ct rl = b011, 2 R = 4, N = 5 Request Request Task E: Prim ary, cycle_ct rl = b011, 2 R = 4, N = 7 Task E Request Request Task D

dma_done[C] dma_done[C]

End: Alt ernat e, cycle_ct rl = b000 Invalid

In Figure 8.3 (p. 51) :

Task A 1. The host processor configures the primary data structure for task A.

2. The host processor configures the alternate data structure for task B. This enables the controller to immediately switch to task B after task A completes, provided that a higher priority channel does not require servicing.

3. The controller receives a request and performs four DMA transfers.

4. The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority.

5. The controller performs the remaining two DMA transfers.

6. The controller sets dma_done[C] HIGH for one arbitration process.

HFCORECLK cycle and enters the After task A completes, the host processor can configure the primary data structure for task C. This enables the controller to immediately switch to task C after task B completes, provided that a higher priority channel does not require servicing.

After the controller receives a new request for the channel and it has the highest priority then task B commences: 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

51

www.silabs.com

Task B

Preliminary

...the world's most energy friendly microcontrollers

7. The controller performs four DMA transfers.

8. The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority.

9. The controller performs four DMA transfers.

10.The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority.

11.The controller performs the remaining four DMA transfers.

12.The controller sets dma_done[C] HIGH for one arbitration process.

HFCORECLK cycle and enters the After task B completes, the host processor can configure the alternate data structure for task D.

After the controller receives a new request for the channel and it has the highest priority then task C commences: Task C 13.The controller performs two DMA transfers.

14.The controller sets dma_done[C] HIGH for one arbitration process.

HFCORECLK cycle and enters the After task C completes, the host processor can configure the primary data structure for task E.

After the controller receives a new request for the channel and it has the highest priority then task D commences: Task D 15.The controller performs four DMA transfers.

16.The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority.

17.The controller performs the remaining DMA transfer.

18.The controller sets dma_done[C] HIGH for one arbitration process.

HFCORECLK cycle and enters the After the controller receives a new request for the channel and it has the highest priority then task E commences: Task E 19.The controller performs four DMA transfers.

20.The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority.

21.The controller performs the remaining three DMA transfers.

22.The controller sets dma_done[C] HIGH for one arbitration process.

HFCORECLK cycle and enters the If the controller receives a new request for the channel and it has the highest priority then it attempts to start the next task. However, because the host processor has not configured the alternate data structure, and on completion of task D the controller set the cycle_ctrl bits to b000, then the ping-pong DMA transaction completes.

Note

You can also terminate the ping-pong DMA cycle in Figure 8.3 (p. 51) , if you configure

task E to be a basic DMA cycle by setting the cycle_ctrl field to 3’b001.

8.4.2.3.5 Memory scatter-gather

In memory scatter-gather mode the controller receives an initial request and then performs four DMA transfers using the primary data structure. After this transfer completes, it starts a DMA cycle using the 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

52

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

alternate data structure. After this cycle completes, the controller performs another four DMA transfers using the primary data structure. The controller continues to switch from primary to alternate to primary… until either: • the host processor configures the alternate data structure for a basic cycle • it reads an invalid data structure.

Note

After the controller completes the N primary transfers it invalidates the primary data structure by setting the cycle_ctrl field to b000.

The controller only asserts dma_done[C] when the scatter-gather transaction completes using an auto request cycle.

In scatter-gather mode, the controller uses the primary data structure to program the alternate data

structure. Table 8.4 (p. 53) lists the fields of the channel_cfg memory location for the primary data

structure, that you must program with constant values and those that can be user defined.

Table 8.4. channel_cfg for a primary data structure, in memory scatter-gather mode

Bit Field Constant-value fields: [31:30} dst_inc [29:28] [27:26] dst_size src_inc [25:24] [17:14] [3] src_size R_power next_useburst Value b10 b10 b10 b10 b0010 0 Description Configures the controller to use word increments for the address Configures the controller to use word transfers Configures the controller to use word increments for the address Configures the controller to use word transfers Configures the controller to perform four DMA transfers For a memory scatter-gather DMA cycle, this bit must be set to zero [2:0] cycle_ctrl User defined values: [23:21] dst_prot_ctrl b100 Configures the controller to perform a memory scatter-gather DMA cycle Configures the state of HPROT 1 when the controller writes the destination data [20:18] src_prot_ctrl Configures the state of HPROT when the controller reads the source data [13:4] n_minus_1 N 2 Configures the controller to perform N DMA transfers, where N is a multiple of four 1 ARM PL230 homepage [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0417a/index.html] 2 Because the R_power field is set to four, you must set N to be a multiple of four. The value given by N/4 is the number of times that you must configure the alternate data structure.

See Section 8.4.3.3 (p. 60) for more information.

Figure 8.4 (p. 54) shows a memory scatter-gather example.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

53

www.silabs.com

Preliminary

Figure 8.4. Memory scatter-gather example ...the world's most energy friendly microcontrollers

Init ializat ion: 1. Configure prim ary t o enable t he copy A, B, C, and D operat ions: cycle_ct rl = b100, 2 R = 4, N = 16.

2. Writ e t he prim ary source dat a t o m em ory, using t he st ruct ure shown in t he following t able.

Dat a for Task A Dat a for Task B Dat a for Task C Dat a for Task D src_dat a_end_pt r 0x 0A000000 0x 0B000000 0x 0C000000 0x 0D000000 dst _dat a_end_pt r 0x 0AE00000 0x 0BE00000 0x 0CE00000 0x 0DE00000 channel_cfg cycle_ct rl = b101, 2 R = 4, N = 3 cycle_ct rl = b101, 2 R = 2, N = 8 cycle_ct rl = b101, 2 R = 8, N = 5 cycle_ct rl = b010, 2 R = 4, N = 4 Unused 0x XXXXXXXX 0x XXXXXXXX 0x XXXXXXXX 0x XXXXXXXX Mem ory scat t er- gat her t ransact ion:

Primary Alternate

Copy from A in m em ory, t o Alt ernat e Request Copy from B in m em ory, t o Alt ernat e Aut o request Aut o request Task A N = 3, 2 R = 4 Aut o request Aut o request Aut o request Aut o request Aut o request Copy from C in m em ory, t o Alt ernat e Task B N = 8, 2 R = 2 Copy from D in m em ory, t o Alt ernat e Aut o request Aut o request Aut o request Task C Task D N = 5, 2 R = 8 N = 4, 2 R = 4

dma_done[C]

In Figure 8.4 (p. 54) :

Initialization 1. The host processor configures the primary data structure to operate in memory scatter-gather mode by setting cycle_ctrl to b100. Because a data structure for a single channel consists of four words then you must set 2 R to 4. In this example, there are four tasks and therefore N is set to 16.

2. The host processor writes the data structure for tasks A, B, C, and D to the memory locations that the primary src_data_end_ptr specifies.

3. The host processor enables the channel.

The memory scatter-gather transaction commences when the controller receives a request on dma_req[ ] or a manual request from the host processor. The transaction continues as follows: Primary, copy A Task A Primary, copy B Task B Primary, copy C 1. After receiving a request, the controller performs four DMA transfers. These transfers write the alternate data structure for task A.

2. The controller generates an auto-request for the channel and then arbitrates.

3. The controller performs task A. After it completes the task, it generates an auto-request for the channel and then arbitrates.

4. The controller performs four DMA transfers. These transfers write the alternate data structure for task B.

5. The controller generates an auto-request for the channel and then arbitrates.

6. The controller performs task B. After it completes the task, it generates an auto-request for the channel and then arbitrates.

7. The controller performs four DMA transfers. These transfers write the alternate data structure for task C.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

54

www.silabs.com

Task C Primary, copy D Task D

8.4.2.3.6 Peripheral scatter-gather

In peripheral scatter-gather mode the controller receives an initial request from a peripheral and then it performs four DMA transfers using the primary data structure. It then immediately starts a DMA cycle using the alternate data structure, without re-arbitrating.

Note

These are the only circumstances, where the controller does not enter the arbitration process after completing a transfer using the primary data structure.

After this cycle completes, the controller re-arbitrates and if the controller receives a request from the peripheral that has the highest priority then it performs another four DMA transfers using the primary data structure. It then immediately starts a DMA cycle using the alternate data structure, without re arbitrating. The controller continues to switch from primary to alternate to primary… until either: • the host processor configures the alternate data structure for a basic cycle • it reads an invalid data structure.

Note

Preliminary

...the world's most energy friendly microcontrollers

8. The controller generates an auto-request for the channel and then arbitrates.

9. The controller performs task C. After it completes the task, it generates an auto-request for the channel and then arbitrates.

10.The controller performs four DMA transfers. These transfers write the alternate data structure for task D.

11.The controller sets the cycle_ctrl bits of the primary data structure to b000, to indicate that this data structure is now invalid.

12.The controller generates an auto-request for the channel and then arbitrates.

13.The controller performs task D using an auto-request cycle.

14.The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process.

After the controller completes the N primary transfers it invalidates the primary data structure by setting the cycle_ctrl field to b000.

The controller asserts dma_done[C] when the scatter-gather transaction completes using a basic cycle.

In scatter-gather mode, the controller uses the primary data structure to program the alternate data

structure. Table 8.5 (p. 55) lists the fields of the channel_cfg memory location for the primary data

structure, that you must program with constant values and those that can be user defined.

Table 8.5. channel_cfg for a primary data structure, in peripheral scatter-gather mode

Bit Field Constant-value fields: [31:30] [29:28] dst_inc dst_size [27:26] [25:24] src_inc src_size [17:14] [2:0] R_power cycle_ctrl User defined values: [23:21] dst_prot_ctrl Value Description b10 b10 b10 b10 b0010 b110 Configures the controller to use word increments for the address Configures the controller to use word transfers Configures the controller to use word increments for the address Configures the controller to use word transfers Configures the controller to perform four DMA transfers Configures the controller to perform a peripheral scatter-gather DMA cycle Configures the state of HPROT when the controller writes the destination data 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

55

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Bit [20:18] [13:4] Field src_prot_ctrl n_minus_1 Value N 1 Description Configures the state of HPROT when the controller reads the source data Configures the controller to perform N DMA transfers, where N is a multiple of four [3] next_useburst When set to 1, the controller sets the chnl_useburst_set [C] bit to 1 after the alternate transfer completes 1 Because the R_power field is set to four, you must set N to be a multiple of four. The value given by N/4 is the number of times that you must configure the alternate data structure.

See Section 8.4.3.3 (p. 60) for more information.

Figure 8.5 (p. 56) shows a peripheral scatter-gather example.

Figure 8.5. Peripheral scatter-gather example

Init ializat ion: 1. Configure prim ary t o enable t he copy A, B, C, and D operat ions: cycle_ct rl = b110, 2 R = 4, N = 16.

2. Writ e t he prim ary source dat a in m em ory, using t he st ruct ure shown in t he following t able.

Dat a for Task A Dat a for Task B Dat a for Task C Dat a for Task D src_dat a_end_pt r 0x 0A000000 0x 0B000000 0x 0C000000 0x 0D000000 dst _dat a_end_pt r 0x 0AE00000 0x 0BE00000 0x 0CE00000 0x 0DE00000 channel_cfg cycle_ct rl = b111, 2 R = 4, N = 3 cycle_ct rl = b111, 2 R = 2, N = 8 cycle_ct rl = b111, 2 R = 8, N = 5 cycle_ct rl = b001, 2 R = 4, N = 4 Unused 0x XXXXXXXX 0x XXXXXXXX 0x XXXXXXXX 0x XXXXXXXX Peripheral scat t er- gat her t ransact ion:

Primary Alternate

Request Copy from A in m em ory, t o Alt ernat e For all prim ary t o alt ernat e t ransit ions, t he cont roller does not ent er t he arbit rat ion process and im m ediat ely perform s t he DMA t ransfer t hat t he alt ernat e channel cont rol dat a st ruct ure specifies.

Task A N = 3, 2 R = 4 Request Copy from B in m em ory, t o Alt ernat e Task B Copy from C in m em ory, t o Alt ernat e Request Request Request Request N = 8, 2 R = 2 Task C N = 5, 2 R = 8 Copy from D in m em ory, t o Alt ernat e Request Task D N = 4, 2 R = 4

dma_done[C]

In Figure 8.5 (p. 56) :

Initialization 1. The host processor configures the primary data structure to operate in peripheral scatter-gather mode by setting cycle_ctrl to b110. Because a data structure for a single channel consists of four words then you must set 2 R to 4. In this example, there are four tasks and therefore N is set to 16.

2. The host processor writes the data structure for tasks A, B, C, and D to the memory locations that the primary src_data_end_ptr specifies.

3. The host processor enables the channel.

The peripheral scatter-gather transaction commences when the controller receives a request on dma_req[ ] . The transaction continues as follows: 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

56

www.silabs.com

Primary, copy A Task A

Preliminary

...the world's most energy friendly microcontrollers

1. After receiving a request, the controller performs four DMA transfers. These transfers write the alternate data structure for task A.

2. The controller performs task A.

3. After the controller completes the task it enters the arbitration process.

After the peripheral issues a new request and it has the highest priority then the process continues with: Primary, copy B Task B 4. The controller performs four DMA transfers. These transfers write the alternate data structure for task B.

5. The controller performs task B. To enable the controller to complete the task, the peripheral must issue a further three requests.

6. After the controller completes the task it enters the arbitration process.

After the peripheral issues a new request and it has the highest priority then the process continues with: Primary, copy C Task C 7. The controller performs four DMA transfers. These transfers write the alternate data structure for task C.

8. The controller performs task C.

9. After the controller completes the task it enters the arbitration process.

After the peripheral issues a new request and it has the highest priority then the process continues with: Primary, copy D Task D 10.The controller performs four DMA transfers. These transfers write the alternate data structure for task D.

11.The controller sets the cycle_ctrl bits of the primary data structure to b000, to indicate that this data structure is now invalid.

12.The controller performs task D using a basic cycle.

13.The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process.

8.4.2.4 Error signaling

If the controller detects an ERROR response on the AHB-Lite master interface, it: • disables the channel that corresponds to the ERROR • sets dma_err HIGH.

After the host processor detects that dma_err is HIGH, it must check which channel was active when the ERROR occurred. It can do this by: 1. Reading the DMA_CHENS register to create a list of disabled channels.

When a channel asserts dma_done[ ] then the controller disables the channel. The program running on the host processor must always keep a record of which channels have recently asserted their dma_done[ ] outputs.

2. It must compare the disabled channels list from step 1 (p. 57) , with the record of the channels that

have recently set their dma_done[ ] outputs. The channel with no record of dma_done[C] being set is the channel that the ERROR occurred on.

8.4.3 Channel control data structure

You must provide an area of system memory to contain the channel control data structure. This system memory must: 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

57

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• provide a contiguous area of system memory that the controller and host processor can access • have a base address that is an integer multiple of the total size of the channel control data structure.

Figure 8.6 (p. 58) shows the memory that the controller requires for the channel control data structure,

when all 4 channels and the optional alternate data structure are in use.

Figure 8.6. Memory map for 4 channels, including the alternate data structure

Alt ernat e dat a st ruct ure Alt ernat e_Ch_3 Alt ernat e_Ch_2 Alt ernat e_Ch_1 Alt ernat e_Ch_0 0x 080 0x 070 0x 060 0x 050 0x 040 Prim ary dat a st ruct ure Prim ary_Ch_3 Prim ary_Ch_2 Prim ary_Ch_1 Prim ary_Ch_0 0x 040 0x 030 0x 020 0x 010 0x 000 Unused Cont rol Dest inat ion End Point er Source End Point er 0x 00C 0x 008 0x 004 0x 000

This structure in Figure 8.6 (p. 58) uses bytes of system memory. The controller uses the lower 8

address bits to enable it to access all of the elements in the structure and therefore the base address must be at 0xXXXXXX00 .

You can configure the base address for the primary data structure by writing the appropriate value in the DMA_CTRLBASE register.

You do not need to set aside the full bytes if all dma channels are not used or if all alternate descriptors are not used. If, for example, only 4 channels are used and they only need the primary descriptors, then only 64 bytes need to be set aside.

Table 8.6 (p. 58) lists the address bits that the controller uses when it accesses the elements of the

channel control data structure.

Table 8.6. Address bit settings for the channel control data structure

Address bits [7] A [6] C[2] [5] C[1] [4] C[0] [3:0] 0x0, 0x4, or 0x8 Where: A C[2:0] Address[3:0] Selects one of the channel control data structures: A = 0 Selects the primary data structure.

A = 1 Selects the alternate data structure.

Selects the DMA channel.

Selects one of the control elements: 0x0 0x4 0x8 0xC Selects the source data end pointer.

Selects the destination data end pointer.

Selects the control data configuration.

The controller does not access this address location. If required, you can enable the host processor to use this memory location as system memory.

Note

It is not necessary for you to calculate the base address of the alternate data structure because the DMA_ALTCTRLBASE register provides this information.

Figure 8.7 (p. 59) shows a detailed memory map of the descriptor structure.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

58

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 8.7. Detailed memory map for the 4 channels, including the alternate data structure

Alt ernat e for channel 3 Unused Cont rol Dest inat ion End Point er Source End Point er 0x 07C 0x 078 0x 074 0x 070 Alt ernat e for channel 1 Alt ernat e for channel 0 Prim ary for channel 3 Unused Cont rol Dest inat ion End Point er Source End Point er Unused Cont rol Dest inat ion End Point er Source End Point er Unused Cont rol Dest inat ion End Point er Source End Point er 0x 05C 0x 058 0x 054 0x 050 0x 04C 0x 048 0x 044 0x 040 0x 03C 0x 038 0x 034 0x 030 Alt ernat e dat a st ruct ure Prim ary for channel 1 Prim ary for channel 0 Unused Cont rol Dest inat ion End Point er Source End Point er Unused Cont rol Dest inat ion End Point er Source End Point er 0x 01C 0x 018 0x 014 0x 010 0x 00C 0x 008 0x 004 0x 000 Prim ary dat a st ruct ure The controller uses the system memory to enable it to access two pointers and the control information that it requires for each channel. The following subsections will describe these 32-bit memory locations and how the controller calculates the DMA transfer address.

8.4.3.1 Source data end pointer

The src_data_end_ptr memory location contains a pointer to the end address of the source data.

Figure 8.7 (p. 59) lists the bit assignments for this memory location.

Table 8.7. src_data_end_ptr bit assignments

Bit [31:0] Name src_data_end_ptr Description Pointer to the end address of the source data Before the controller can perform a DMA transfer, you must program this memory location with the end address of the source data. The controller reads this memory location when it starts a 2 R DMA transfer.

Note

The controller does not write to this memory location.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

59

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

8.4.3.2 Destination data end pointer

The dst_data_end_ptr memory location contains a pointer to the end address of the destination data.

Table 8.8 (p. 60) lists the bit assignments for this memory location.

Table 8.8. dst_data_end_ptr bit assignments

Bit [31:0] Name dst_data_end_ptr Description Pointer to the end address of the destination data Before the controller can perform a DMA transfer, you must program this memory location with the end address of the destination data. The controller reads this memory location when it starts a 2 R DMA transfer.

Note

The controller does not write to this memory location.

8.4.3.3 Control data configuration

For each DMA transfer, the channel_cfg memory location provides the control information for the

controller. Figure 8.8 (p. 60) shows the bit assignments for this memory location.

Figure 8.8. channel_cfg bit assignments

31 30 29 28 27 26 25 24 23 21 20 18 17 14 R_power 13 dst _inc src_inc dst _size src_size src_prot _ct rl dst _prot _ct rl n_m inus_1 4 3 2 0 cycle_ct rl nex t _useburst

Table 8.9 (p. 60) lists the bit assignments for this memory location.

Table 8.9. channel_cfg bit assignments

Bit [31:30] Name dst_inc Description Destination address increment.

The address increment depends on the source data width as follows: Source data width = byte b00 = byte.

b01 = halfword.

b10 = word.

b11 = no increment. Address remains set to the value that the dst_data_end_ptr memory location contains.

Source data width = halfword Source data width = word b00 = reserved.

b01 = halfword.

b10 = word.

b11 = no increment. Address remains set to the value that the dst_data_end_ptr memory location contains.

b00 = reserved.

b01 = reserved.

b10 = word.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

60

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Bit Name Description b11 = no increment. Address remains set to the value that the dst_data_end_ptr memory location contains.

[29:28] dst_size [27:26] src_inc [25:24] src_size [23:21] dst_prot_ctrl [20:18] src_prot_ctrl [17:14] R_power Destination data size.

Note

You must set dst_size to contain the same value that src_size contains.

Set the bits to control the source address increment. The address increment depends on the source data width as follows: Source data width = byte Source data width = halfword Source data width = word b00 = byte.

b01 = halfword.

b10 = word.

b11 = no increment. Address remains set to the value that the src_data_end_ptr memory location contains.

b00 = reserved.

b01 = halfword.

b10 = word.

b11 = no increment. Address remains set to the value that the src_data_end_ptr memory location contains.

b00 = reserved.

b01 = reserved.

b10 = word.

b11 = no increment. Address remains set to the value that the src_data_end_ptr memory location contains.

Set the bits to match the size of the source data: b00 = byte b01 = halfword b10 = word b11 = reserved.

Set the bits to control the state of HPROT when the controller writes the destination data.

Bit [23] Bit [22] Bit [21] This bit has no effect on the DMA.

This bit has no effect on the DMA.

Controls the state of HPROT as follows: 0 = HPROT is LOW and the access is non-privileged.

1 = HPROT is HIGH and the access is privileged.

Set the bits to control the state of HPROT when the controller reads the source data.

Bit [20] Bit [19] Bit [18] This bit has no effect on the DMA.

This bit has no effect on the DMA.

Controls the state of HPROT as follows: 0 = HPROT is LOW and the access is non-privileged.

1 = HPROT is HIGH and the access is privileged.

Set these bits to control how many DMA transfers can occur before the controller re-arbitrates.

The possible arbitration rate settings are: b0000 b0001 b0010 b0011 b0100 b0101 b0110 b0111 Arbitrates after each DMA transfer.

Arbitrates after 2 DMA transfers.

Arbitrates after 4 DMA transfers.

Arbitrates after 8 DMA transfers.

Arbitrates after 16 DMA transfers.

Arbitrates after 32 DMA transfers.

Arbitrates after 64 DMA transfers.

Arbitrates after 128 DMA transfers.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

61

www.silabs.com

Bit [13:4] [3] [2:0]

Preliminary

...the world's most energy friendly microcontrollers

Name n_minus_1 next_useburst cycle_ctrl Description b1000 b1001 b1010 - b1111 Arbitrates after 256 DMA transfers.

Arbitrates after 512 DMA transfers.

Arbitrates after 1024 DMA transfers. This means that no arbitration occurs during the DMA transfer because the maximum transfer size is 1024.

Prior to the DMA cycle commencing, these bits represent the total number of DMA transfers that the DMA cycle contains. You must set these bits according to the size of DMA cycle that you require.

The 10-bit value indicates the number of DMA transfers, minus one. The possible values are: b000000000 = 1 DMA transfer b000000001 = 2 DMA transfers b000000010 = 3 DMA transfers b000000011 = 4 DMA transfers b000000100 = 5 DMA transfers .

.

.

b111111111 = 1024 DMA transfers.

The controller updates this field immediately prior to it entering the arbitration process. This enables the controller to store the number of outstanding DMA transfers that are necessary to complete the DMA cycle.

Controls if the chnl_useburst_set [C] bit is set to a 1, when the controller is performing a peripheral scatter-gather and is completing a DMA cycle that uses the alternate data structure.

Note

Immediately prior to completion of the DMA cycle that the alternate data structure specifies, the controller sets the chnl_useburst_set [C] bit to 0 if the number of remaining transfers is less than 2 R . The setting of the next_useburst bit controls if the controller performs an additional modification of the chnl_useburst_set [C] bit.

In peripheral scatter-gather DMA cycle then after the DMA cycle that uses the alternate data structure completes , either: 0 = the controller does not change the value of the chnl_useburst_set [C] bit. If the chnl_useburst_set [C] bit is 0 then for all the remaining DMA cycles in the peripheral scatter gather transaction, the controller responds to requests on dma_req[ ] and dma_sreq[ ] , when it performs a DMA cycle that uses an alternate data structure.

1 = the controller sets the chnl_useburst_set [C] bit to a 1. Therefore, for the remaining DMA cycles in the peripheral scatter-gather transaction, the controller only responds to requests on dma_req[ ] , when it performs a DMA cycle that uses an alternate data structure.

The operating mode of the DMA cycle. The modes are: b000 b001 b010 b011 b100 Stop. Indicates that the data structure is invalid.

Basic. The controller must receive a new request, prior to it entering the arbitration process, to enable the DMA cycle to complete.

Auto-request. The controller automatically inserts a request for the appropriate channel during the arbitration process. This means that the initial request is sufficient to enable the DMA cycle to complete.

Ping-pong. The controller performs a DMA cycle using one of the data structures. After the DMA cycle completes, it performs a DMA cycle using the other data structure. After the DMA cycle completes and provided that the host processor has updated the original data structure, it performs a DMA cycle using the original data structure. The controller continues to perform DMA cycles until it either reads an invalid data structure or the

host processor changes the cycle_ctrl bits to b001 or b010. See Section 8.4.2.3.4 (p.

50) .

Memory scatter/gather. See Section 8.4.2.3.5 (p. 52) .

b101 When the controller operates in memory scatter-gather mode, you must only use this value in the primary data structure.

Memory scatter/gather. See Section 8.4.2.3.5 (p. 52) .

b110 When the controller operates in memory scatter-gather mode, you must only use this value in the alternate data structure.

Peripheral scatter/gather. See Section 8.4.2.3.6 (p. 55) .

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

62

www.silabs.com

Bit Name

Preliminary

...the world's most energy friendly microcontrollers

Description b111 When the controller operates in peripheral scatter-gather mode, you must only use this value in the primary data structure.

Peripheral scatter/gather. See Section 8.4.2.3.6 (p. 55) .

When the controller operates in peripheral scatter-gather mode, you must only use this value in the alternate data structure.

At the start of a DMA cycle, or 2 R DMA transfer, the controller fetches the channel_cfg from system memory. After it performs 2 R , or N, transfers it stores the updated channel_cfg in system memory.

The controller does not support a dst_size value that is different to the src_size value. If it detects a mismatch in these values, it uses the src_size value for source and destination and when it next updates the n_minus_1 field, it also sets the dst_size field to the same as the src_size field.

After the controller completes the N transfers it sets the cycle_ctrl field to b000, to indicate that the channel_cfg data is invalid. This prevents it from repeating the same DMA transfer.

8.4.3.4 Address calculation

To calculate the source address of a DMA transfer, the controller performs a left shift operation on the n_minus_1 value by a shift amount that src_inc specifies, and then subtracts the resulting value from the source data end pointer. Similarly, to calculate the destination address of a DMA transfer, it performs a left shift operation on the n_minus_1 value by a shift amount that dst_inc specifies, and then subtracts the resulting value from the destination end pointer.

Depending on the value of src_inc and dst_inc, the source address and destination address can be calculated using the equations: src_inc = b00 and dst_inc = b00 src_inc = b01 and dst_inc = b01 src_inc = b10 and dst_inc = b10 src_inc = b11 and dst_inc = b11 • source address = src_data_end_ptr - n_minus_1 • destination address = dst_data_end_ptr - n_minus_1.

• source address = src_data_end_ptr - (n_minus_1 << 1) • destination address = dst_data_end_ptr - (n_minus_1 << 1).

• source address = src_data_end_ptr - (n_minus_1 << 2) • destination address = dst_data_end_ptr - (n_minus_1 << 2).

• source address = src_data_end_ptr • destination address = dst_data_end_ptr.

Table 8.10 (p. 63) lists the destination addresses for a DMA cycle of six words.

Table 8.10. DMA cycle of six words using a word increment

Initial values of channel_cfg, prior to the DMA cycle src_size = b10, dst_inc = b10, n_minus_1 = b101, cycle_ctrl = 1 End Pointer Count Difference 1 DMA transfers 0x2AC 0x2AC 0x2AC 0x2AC 0x2AC 5 4 3 2 1 0x14 0x10 0xC 0x8 0x4 Address 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0 Final values of channel_cfg, after the DMA cycle 0x0 0x2AC src_size = b10, dst_inc = b10, n_minus_1 = 0, cycle_ctrl = 0 1 This value is the result of count being shifted left by the value of dst_inc.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

63

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Table 8.11 (p. 64) lists the destination addresses for a DMA transfer of 12 bytes using a halfword

increment.

Table 8.11. DMA cycle of 12 bytes using a halfword increment

Initial values of channel_cfg, prior to the DMA cycle src_size = b00, dst_inc = b01, n_minus_1 = b1011, cycle_ctrl = 1, R_power = b11 End Pointer Count Difference 1 Address DMA transfers 0x5E7 0x5E7 0x5E7 0x5E7 0x5E7 9 8 11 10 7 0x16 0x14 0x12 0x10 0xE 0x5D1 0x5D3 0x5D5 0x5D7 0x5D9 0x5E7 0x5E7 0x5E7 Values of channel_cfg after 2 R DMA transfers 4 6 5 0xC 0xA 0x8 0x5DB 0x5DD 0x5DF src_size = b00, dst_inc = b01, n_minus_1 = b011, cycle_ctrl = 1, R_power = b11 End Pointer Count Difference Address 0x5E7 3 0x6 0x5E1 DMA transfers 0x5E7 0x5E7 0x5E7 2 1 0 0x4 0x2 0x0 0x5E3 0x5E5 0x5E7 Final values of channel_cfg, after the DMA cycle src_size = b00, dst_inc = b01, n_minus_1 = 0, cycle_ctrl = 0 2 , R_power = b11 1 This value is the result of count being shifted left by the value of dst_inc.

2 After the controller completes the DMA cycle it invalidates the channel_cfg memory location by clearing the cycle_ctrl field.

8.4.4 Interaction with the EMU

The DMA interacts with the Energy Management Unit (EMU) to allow transfers from , e.g., the LEUART to occur in EM2. The EMU can wake up the DMA sufficiently long to allow data transfers to occur. See section "DMA Support" in the LEUART documentation.

8.4.5 Interrupts

The PL230 dma_done[n:0] signals (one for each channel) as well as the dma_err signal, are available as interrupts to the Cortex-M0+ core. They are combined into one interrupt vector, DMA_INT. If the interrupt for the DMA is enabled in the ARM Cortex-M0+ core, an interrupt will be made if one or more of the interrupt flags in DMA_IF and their corresponding bits in DMA_IEN are set.

8.5 Examples

A basic example of how to program the DMA for transferring 42 bytes from the USART1 to memory location 0x20003420. Assumes that the channel 0 is currently disabled, and that the DMA_ALTCTRLBASE register has already been configured.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

64

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Example 8.1. DMA Transfer

1. Configure the channel select for using USART1 with DMA channel 0 a. Write SOURCESEL=0b001101 and SIGSEL=XX to DMA_CHCTRL0 2. Configure the primary channel descriptor for DMA channel 0 a. Write XX (read address of USART1) to src_data_end_ptr b. Write 0x20003420 + 40 to dst_data_end_ptr c c. Write these values to channel_cfg for channel 0: i. dst_inc=b01 (destination halfword address increment) ii. dst_size=b01 (halfword transfer size) iii. src_inc=b11 (no address increment for source) iv. src_size=01 (halfword transfer size) v. dst_prot_ctrl=000 (no cache/buffer/privilege) vi. src_prot_ctrl=000 (no cache/buffer/privilege) vii.R_power=b0000 (arbitrate after each DMA transfer) viii.n_minus_1=d20 (transfer 21 halfwords) ix. next_useburst=b0 (not applicable) x. cycle_ctrl=b001 (basic operating mode) 3. Enable the DMA a. Write EN=1 to DMA_CONFIG 4. Disable the single requests for channel 0 (i.e., do not react to data available, wait for buffer full) a. Write DMA_CHUSEBURSTS[0]=1 5. Enable buffer-full requests for channel 0 a. Write DMA_CHREQMASKC[0]=1 6. Use the primary data structure for channel 0 a. Write DMA_CHALTC[0]=1 7. Enable channel 0 a. Write DMA_CHENS[0]=1 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

65

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

8.6 Register Map

The offset register address is relative to the registers base address.

Offset

0x000 0x004

0x008 0x00C

0x010 0x014

0x018

0x01C 0x020

0x024 0x028

0x02C

0x030 0x034

0x038 0x03C

0x04C 0xE10

0xE18

0x1000 0x1004

0x1008 0x100C

0x1100 0x1104 0x1108 0x110C 0x1110 0x1114

Name

DMA_STATUS DMA_CONFIG

DMA_CTRLBASE DMA_ALTCTRLBASE

DMA_CHWAITSTATUS DMA_CHSWREQ

DMA_CHUSEBURSTS

DMA_CHUSEBURSTC DMA_CHREQMASKS

DMA_CHREQMASKC DMA_CHENS

DMA_CHENC

DMA_CHALTS DMA_CHALTC

DMA_CHPRIS DMA_CHPRIC

DMA_ERRORC DMA_CHREQSTATUS

DMA_CHSREQSTATUS

DMA_IF DMA_IFS

DMA_IFC DMA_IEN

DMA_CH0_CTRL DMA_CH1_CTRL DMA_CH2_CTRL DMA_CH3_CTRL DMA_CH4_CTRL DMA_CH5_CTRL

Type

RW RW RW RW R W RW R R W1 RW1H W1 RW1 W1 RW1 W1 RW1 W1 RW1 W1 RW R R R W1 W1 RW RW RW

Description

DMA Status Registers DMA Configuration Register

Channel Control Data Base Pointer Register Channel Alternate Control Data Base Pointer Register

Channel Wait on Request Status Register Channel Software Request Register

Channel Useburst Set Register

Channel Useburst Clear Register Channel Request Mask Set Register

Channel Request Mask Clear Register Channel Enable Set Register

Channel Enable Clear Register

Channel Alternate Set Register Channel Alternate Clear Register

Channel Priority Set Register Channel Priority Clear Register

Bus Error Clear Register Channel Request Status

Channel Single Request Status

Interrupt Flag Register Interrupt Flag Set Register

Interrupt Flag Clear Register Interrupt Enable register

Channel Control Register Channel Control Register Channel Control Register Channel Control Register Channel Control Register Channel Control Register

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

66

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

8.7 Register Description 8.7.1 DMA_STATUS - DMA Status Registers Offset

0x000

Reset Access Bit Position Name Bit

31:21

20:16

15:8

7:4

3:1

0

Name

Reserved

5 6 7 8 9 10 Value 0 1 2 3 4

Reset

Mode IDLE RDCHCTRLDATA RDSRCENDPTR RDDSTENDPTR RDSRCDATA WRDSTDATA WAITREQCLR WRCHCTRLDATA STALLED DONE PERSCATTRANS

Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CHNUM 0x05 Number of available DMA channels minus one.

R

Reserved

Channel Number

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

STATE 0x0 R

Control Current State

State can be one of the following. Higher values (11-15) are undefined.

Description Idle Reading channel controller data Reading source data end pointer Reading destination data end pointer Reading source data Writing destination data Waiting for DMA request to clear Writing channel controller data Stalled Done Peripheral scatter-gather transition

Reserved

EN

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 When this bit is 1, the DMA is enabled.

R

DMA Enable Status 8.7.2 DMA_CONFIG - DMA Configuration Register Offset

0x004

Reset Access Bit Position Name Bit

31:6

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

67

www.silabs.com

Bit

5

4:1

0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

CHPROT 0 W

Channel Protection Control

Control whether accesses done by the DMA controller are privileged or not. When CHPROT = 1 then HPROT is HIGH and the access is privileged. When CHPROT = 0 then HPROT is LOW and the access is non-privileged.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

EN 0 Set this bit to enable the DMA controller.

W

Enable DMA 8.7.3 DMA_CTRLBASE - Channel Control Data Base Pointer Register Offset

0x008

Bit Position Reset Access Name Bit

31:0

Name Reset Access Description

CTRLBASE 0x00000000 RW

Channel Control Data Base Pointer

The base pointer for a location in system memory that holds the channel control data structure. This register must be written to point to a location in system memory with the channel control data structure before the DMA can be used. Note that ctrl_base_ptr[8:0] must be 0.

8.7.4 DMA_ALTCTRLBASE - Channel Alternate Control Data Base Pointer Register Offset

0x00C

Bit Position Reset Access Name Bit

31:0

Name

ALTCTRLBASE

Reset

0x00000080

Access

R

Description Channel Alternate Control Data Base Pointer

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

68

www.silabs.com

Bit Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

The base address of the alternate data structure. This register will read as DMA_CTRLBASE + 0x80.

8.7.5 DMA_CHWAITSTATUS - Channel Wait on Request Status Register Bit Position Offset

0x010

Reset Access Name

1 0 4 3 2

Bit

31:6

5

Name Reset Access Description

Reserved

CH5WAITSTATUS

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

1 Status for wait on request for channel 5.

CH4WAITSTATUS 1 Status for wait on request for channel 4.

CH3WAITSTATUS 1 Status for wait on request for channel 3.

CH2WAITSTATUS 1 Status for wait on request for channel 2.

R R R R

Channel 5 Wait on Request Status Channel 4 Wait on Request Status Channel 3 Wait on Request Status Channel 2 Wait on Request Status

CH1WAITSTATUS 1 Status for wait on request for channel 1.

CH0WAITSTATUS 1 Status for wait on request for channel 0.

R R

Channel 1 Wait on Request Status Channel 0 Wait on Request Status 8.7.6 DMA_CHSWREQ - Channel Software Request Register Bit Position Offset

0x014

Reset Access Name Bit

31:6

5

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH5SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 5 Software Request

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

69

www.silabs.com

2 1 0

Bit

4 3

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

CH4SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 4 Software Request

CH3SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 3 Software Request

CH2SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 2 Software Request

CH1SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 1 Software Request

CH0SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 0 Software Request 8.7.7 DMA_CHUSEBURSTS - Channel Useburst Set Register Bit Position Offset

0x018

Reset Access Name

3 2 1 0

Bit

31:6

5 4

Name Reset Access Description

Reserved

Value 0 1

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH5USEBURSTS 0 See description for channel 0.

CH4USEBURSTS 0 See description for channel 0.

CH3USEBURSTS 0 See description for channel 0.

CH2USEBURSTS 0 See description for channel 0.

CH1USEBURSTS 0 See description for channel 0.

RW1H RW1H RW1H RW1H RW1H

Channel 5 Useburst Set Channel 4 Useburst Set Channel 3 Useburst Set Channel 2 Useburst Set Channel 1 Useburst Set

CH0USEBURSTS 0 RW1H

Channel 0 Useburst Set

Write to 1 to enable the useburst setting for this channel. Reading returns the useburst status. After the penultimate 2^R transfer completes, if the number of remaining transfers, N, is less than 2^R then the controller resets the chnl_useburst_set bit to 0.

This enables you to complete the remaining transfers using dma_req[] or dma_sreq[]. In peripheral scatter-gather mode, if the next_useburst bit is set in channel_cfg then the controller sets the chnl_useburst_set[C] bit to a 1, when it completes the DMA cycle that uses the alternate data structure.

Mode SINGLEANDBURST BURSTONLY Description Channel responds to both single and burst requests Channel responds to burst requests only 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

70

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

8.7.8 DMA_CHUSEBURSTC - Channel Useburst Clear Register Offset

0x01C

Reset Access Bit Position Name

4 3 2 1 0

Bit

31:6

5

Name Reset Access Description

Reserved

CH5USEBURSTC

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 W1 Write to 1 to disable useburst setting for this channel.

CH4USEBURSTC 0 W1 Write to 1 to disable useburst setting for this channel.

CH3USEBURSTC 0 W1 Write to 1 to disable useburst setting for this channel.

CH2USEBURSTC 0 W1 Write to 1 to disable useburst setting for this channel.

CH1USEBURSTC 0 W1 Write to 1 to disable useburst setting for this channel.

CH0USEBURSTC 0 W1 Write to 1 to disable useburst setting for this channel.

Channel 5 Useburst Clear Channel 4 Useburst Clear Channel 3 Useburst Clear Channel 2 Useburst Clear Channel 1 Useburst Clear Channel 0 Useburst Clear 8.7.9 DMA_CHREQMASKS - Channel Request Mask Set Register Bit Position Offset

0x020

Reset Access Name Bit

31:6

5 4 3

Name

Reserved

CH5REQMASKS Write to 1 to disable peripheral requests for this channel.

CH4REQMASKS 0 RW1 Write to 1 to disable peripheral requests for this channel.

CH3REQMASKS

Reset

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 0

Access

RW1 RW1

Description Channel 5 Request Mask Set Channel 4 Request Mask Set Channel 3 Request Mask Set

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

71

www.silabs.com

Bit

2 1 0

Preliminary Name Reset Access

Write to 1 to disable peripheral requests for this channel.

CH2REQMASKS 0 RW1 Write to 1 to disable peripheral requests for this channel.

CH1REQMASKS 0 RW1 Write to 1 to disable peripheral requests for this channel.

CH0REQMASKS 0 RW1 Write to 1 to disable peripheral requests for this channel.

...the world's most energy friendly microcontrollers

Description Channel 2 Request Mask Set Channel 1 Request Mask Set Channel 0 Request Mask Set 8.7.10 DMA_CHREQMASKC - Channel Request Mask Clear Register Offset

0x024

Reset Access Bit Position Name

4 3 2 1 0

Bit

31:6

5

Name Reset Access Description

Reserved

CH5REQMASKC

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 W1 Write to 1 to enable peripheral requests for this channel.

CH4REQMASKC 0 W1 Write to 1 to enable peripheral requests for this channel.

CH3REQMASKC 0 W1 Write to 1 to enable peripheral requests for this channel.

CH2REQMASKC 0 W1 Write to 1 to enable peripheral requests for this channel.

CH1REQMASKC 0 W1 Write to 1 to enable peripheral requests for this channel.

CH0REQMASKC 0 W1 Write to 1 to enable peripheral requests for this channel.

Channel 5 Request Mask Clear Channel 4 Request Mask Clear Channel 3 Request Mask Clear Channel 2 Request Mask Clear Channel 1 Request Mask Clear Channel 0 Request Mask Clear 8.7.11 DMA_CHENS - Channel Enable Set Register Offset

0x028

Reset Access Bit Position Name

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

72

www.silabs.com

3 2 1 0

Bit

31:6

5 4

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH5ENS 0 RW1

Channel 5 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

CH4ENS 0 RW1

Channel 4 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

CH3ENS 0 RW1

Channel 3 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

CH2ENS 0 RW1

Channel 2 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

CH1ENS 0 RW1

Channel 1 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

CH0ENS 0 RW1

Channel 0 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

8.7.12 DMA_CHENC - Channel Enable Clear Register Bit Position Offset

0x02C

Reset Access Name

3 2 1 0

Bit

31:6

5 4

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH5ENC 0 W1

Channel 5 Enable Clear

Write to 1 to disable this channel. See also description for channel 0.

CH4ENC 0 W1

Channel 4 Enable Clear

Write to 1 to disable this channel. See also description for channel 0.

CH3ENC 0 W1

Channel 3 Enable Clear

Write to 1 to disable this channel. See also description for channel 0.

CH2ENC 0 W1

Channel 2 Enable Clear

Write to 1 to disable this channel. See also description for channel 0.

CH1ENC 0 W1

Channel 1 Enable Clear

Write to 1 to disable this channel. See also description for channel 0.

CH0ENC 0 W1

Channel 0 Enable Clear

Write to 1 to disable this channel. Note that the controller disables a channel, by setting the appropriate bit, when either it completes the DMA cycle, or it reads a channel_cfg memory location which has cycle_ctrl = b000, or an ERROR occurs on the AHB-Lite bus.

A read from this field returns the value of CH0ENS from the DMA_CHENS register.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

73

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

8.7.13 DMA_CHALTS - Channel Alternate Set Register Offset

0x030

Reset Access Bit Position Name

3 2 1 0

Bit

31:6

5 4

Name Reset Access Description

Reserved

CH5ALTS

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 RW1 Write to 1 to select the alternate structure for this channel.

CH4ALTS 0 RW1 Write to 1 to select the alternate structure for this channel.

CH3ALTS 0 RW1 Write to 1 to select the alternate structure for this channel.

CH2ALTS 0 RW1 Write to 1 to select the alternate structure for this channel.

CH1ALTS 0 RW1 Write to 1 to select the alternate structure for this channel.

CH0ALTS 0 RW1 Write to 1 to select the alternate structure for this channel.

Channel 5 Alternate Structure Set Channel 4 Alternate Structure Set Channel 3 Alternate Structure Set Channel 2 Alternate Structure Set Channel 1 Alternate Structure Set Channel 0 Alternate Structure Set 8.7.14 DMA_CHALTC - Channel Alternate Clear Register Bit Position Offset

0x034

Reset Access Name

4 3 2

Bit

31:6

5

Name Reset Access Description

Reserved

CH5ALTC

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 W1 Write to 1 to select the primary structure for this channel.

CH4ALTC 0 W1 Write to 1 to select the primary structure for this channel.

CH3ALTC 0 W1 Write to 1 to select the primary structure for this channel.

CH2ALTC 0 W1

Channel 5 Alternate Clear Channel 4 Alternate Clear Channel 3 Alternate Clear Channel 2 Alternate Clear

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

74

www.silabs.com

Bit

1 0

Preliminary Name Reset Access

Write to 1 to select the primary structure for this channel.

CH1ALTC 0 W1 Write to 1 to select the primary structure for this channel.

CH0ALTC 0 W1 Write to 1 to select the primary structure for this channel.

...the world's most energy friendly microcontrollers

Description Channel 1 Alternate Clear Channel 0 Alternate Clear 8.7.15 DMA_CHPRIS - Channel Priority Set Register Offset

0x038

Reset Access Bit Position Name

3 2 1 0

Bit

31:6

5 4

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH5PRIS 0 RW1

Channel 5 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

CH4PRIS 0 RW1

Channel 4 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

CH3PRIS 0 RW1

Channel 3 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

CH2PRIS 0 RW1

Channel 2 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

CH1PRIS 0 RW1

Channel 1 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

CH0PRIS 0 RW1

Channel 0 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

8.7.16 DMA_CHPRIC - Channel Priority Clear Register Offset

0x03C

Reset Access Bit Position Name Bit

31:6

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

75

www.silabs.com

3 2 1 0

Bit

5 4

Preliminary Name Reset Access

CH5PRIC 0 Write to 1 to clear high priority for this channel.

W1 CH4PRIC 0 Write to 1 to clear high priority for this channel.

W1 CH3PRIC 0 Write to 1 to clear high priority for this channel.

W1 CH2PRIC 0 Write to 1 to clear high priority for this channel.

W1 CH1PRIC 0 Write to 1 to clear high priority for this channel.

W1 CH0PRIC 0 Write to 1 to clear high priority for this channel.

W1

...the world's most energy friendly microcontrollers

Description Channel 5 High Priority Clear Channel 4 High Priority Clear Channel 3 High Priority Clear Channel 2 High Priority Clear Channel 1 High Priority Clear Channel 0 High Priority Clear 8.7.17 DMA_ERRORC - Bus Error Clear Register Bit Position Offset

0x04C

Reset Access Name Bit

31:1

0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

ERRORC 0 RW

Bus Error Clear

This bit is set high if an AHB bus error has occurred. Writing a 1 to this bit will clear the bit. If the error is deasserted at the same time as an error occurs on the bus, the error condition takes precedence and ERRORC remains asserted.

8.7.18 DMA_CHREQSTATUS - Channel Request Status Bit Position Offset

0xE10

Reset Access Name Bit

31:6

5

Name

Reserved

CH5REQSTATUS

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 R

Channel 5 Request Status

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

76

www.silabs.com

Bit

4 3 2 1 0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

CH4REQSTATUS 0 R

Channel 4 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

CH3REQSTATUS 0 R

Channel 3 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

CH2REQSTATUS 0 R

Channel 2 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

CH1REQSTATUS 0 R

Channel 1 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

CH0REQSTATUS 0 R

Channel 0 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

8.7.19 DMA_CHSREQSTATUS - Channel Single Request Status Offset

0xE18

Reset Access Bit Position Name Bit

31:6

5 4 3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH5SREQSTATUS 0 R

Channel 5 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

CH4SREQSTATUS 0 R

Channel 4 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

CH3SREQSTATUS 0 R

Channel 3 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

CH2SREQSTATUS 0 R

Channel 2 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

CH1SREQSTATUS 0 R

Channel 1 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

CH0SREQSTATUS 0 R

Channel 0 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

77

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

8.7.20 DMA_IF - Interrupt Flag Register Offset

0x1000

Reset Access Bit Position Name Bit

31 1 0 3 2

30:6

5 4

Name Reset Access Description

ERR 0 R This flag is set when an error has occurred on the AHB bus.

DMA Error Interrupt Flag

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH5DONE 0 R

DMA Channel 5 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

CH4DONE 0 R

DMA Channel 4 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

CH3DONE 0 R

DMA Channel 3 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

CH2DONE 0 R

DMA Channel 2 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

CH1DONE 0 R

DMA Channel 1 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

CH0DONE 0 R

DMA Channel 0 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

8.7.21 DMA_IFS - Interrupt Flag Set Register Offset

0x1004

Reset Access Bit Position Name Bit

31

30:6

5 4 3

Name Reset Access Description

ERR 0 Set to 1 to set DMA error interrupt flag.

Reserved

W1

DMA Error Interrupt Flag Set

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH5DONE 0 W1

DMA Channel 5 Complete Interrupt Flag Set

Write to 1 to set the corresponding DMA channel complete interrupt flag.

CH4DONE 0 W1

DMA Channel 4 Complete Interrupt Flag Set

Write to 1 to set the corresponding DMA channel complete interrupt flag.

CH3DONE 0 W1

DMA Channel 3 Complete Interrupt Flag Set

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

78

www.silabs.com

Bit

2 1 0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Write to 1 to set the corresponding DMA channel complete interrupt flag.

CH2DONE 0 W1

DMA Channel 2 Complete Interrupt Flag Set

Write to 1 to set the corresponding DMA channel complete interrupt flag.

CH1DONE 0 W1

DMA Channel 1 Complete Interrupt Flag Set

Write to 1 to set the corresponding DMA channel complete interrupt flag.

CH0DONE 0 W1

DMA Channel 0 Complete Interrupt Flag Set

Write to 1 to set the corresponding DMA channel complete interrupt flag.

8.7.22 DMA_IFC - Interrupt Flag Clear Register Offset

0x1008

Reset Access Bit Position Name Bit

31 3 2 1 0

30:6

5 4

Name Reset Access Description

ERR 0 W1

DMA Error Interrupt Flag Clear

Set to 1 to clear DMA error interrupt flag. Note that if an error happened, the Bus Error Clear Register must be used to clear the DMA.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH5DONE 0 W1

DMA Channel 5 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

CH4DONE 0 W1

DMA Channel 4 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

CH3DONE 0 W1

DMA Channel 3 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

CH2DONE 0 W1

DMA Channel 2 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

CH1DONE 0 W1

DMA Channel 1 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

CH0DONE 0 W1

DMA Channel 0 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

8.7.23 DMA_IEN - Interrupt Enable register Offset

0x100C

Reset Access Bit Position Name

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

79

www.silabs.com

1 0 4 3 2

Bit

31

30:6

5

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

ERR 0 Set this bit to enable interrupt on AHB bus error.

RW

Reserved

DMA Error Interrupt Flag Enable

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH5DONE 0 RW

DMA Channel 5 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

CH4DONE 0 RW

DMA Channel 4 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

CH3DONE 0 RW

DMA Channel 3 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

CH2DONE 0 RW

DMA Channel 2 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

CH1DONE 0 RW

DMA Channel 1 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

CH0DONE 0 RW

DMA Channel 0 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

8.7.24 DMA_CHx_CTRL - Channel Control Register Offset

0x1100

Bit Position Reset Access Name Bit

31:22

21:16

15:4

3:0

Name Reset Access Description

Reserved

SOURCESEL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x00 Select input source to DMA channel.

RW

Source Select

Value 0b000000 0b001000 0b001100 0b001101 0b010000 0b010100 0b011000 0b011001 0b011010 0b110000 0b110001 Mode NONE ADC0 USART0 USART1 LEUART0 I2C0 TIMER0 TIMER1 TIMER2 MSC AES Value SOURCESEL = 0b000000 (NONE) Mode Description No source selected Analog to Digital Converter 0 Universal Synchronous/Asynchronous Receiver/Transmitter 0 Universal Synchronous/Asynchronous Receiver/Transmitter 1 Low Energy UART 0 I2C 0 Timer 0 Timer 1 Timer 2 Advanced Encryption Standard Accelerator

Reserved

SIGSEL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 Select input signal to DMA channel.

RW

Signal Select

Description 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

80

www.silabs.com

Bit Preliminary Name Reset Access

Value 0bxxxx SOURCESEL = 0b001000 (ADC0) 0b0000 0b0001 SOURCESEL (USART0) 0b0000 0b0001 0b0010 SOURCESEL (USART1) 0b0000 0b0001 0b0010 0b0011 = = 0b0100 SOURCESEL (LEUART0) 0b0000 0b0001 = 0b010000 0b0010 SOURCESEL = 0b010100 (I2C0) 0b0000 0b0001 SOURCESEL (TIMER0) 0b0000 0b0001 0b0010 0b0011 SOURCESEL (TIMER1) 0b0000 = = 0b001100 0b001101 0b011000 0b011001 ADC0SINGLE ADC0SCAN USART0RXDATAV USART0TXBL USART0TXEMPTY USART1RXDATAV USART1TXBL USART1TXEMPTY USART1RXDATAVRIGHT USART1TXBLRIGHT LEUART0RXDATAV LEUART0TXBL LEUART0TXEMPTY I2C0RXDATAV I2C0TXBL TIMER0UFOF TIMER0CC0 TIMER0CC1 TIMER0CC2 0b0001 0b0010 0b0011 SOURCESEL (TIMER2) = 0b011010 TIMER1UFOF TIMER1CC0 TIMER1CC1 TIMER1CC2 0b0000 0b0001 0b0010 0b0011 SOURCESEL = 0b110000 (MSC) 0b0000 SOURCESEL = 0b110001 (AES) 0b0000 0b0001 0b0010 0b0011 Mode OFF TIMER2UFOF TIMER2CC0 TIMER2CC1 TIMER2CC2 MSCWDATA AESDATAWR AESXORDATAWR AESDATARD AESKEYWR

...the world's most energy friendly microcontrollers

Description

Description Channel input selection is turned off ADC0SINGLE ADC0SCAN USART0RXDATAV REQ/SREQ USART0TXBL REQ/SREQ USART0TXEMPTY USART1RXDATAV REQ/SREQ USART1TXBL REQ/SREQ USART1TXEMPTY USART1RXDATAVRIGHT REQ/SREQ USART1TXBLRIGHT REQ/SREQ LEUART0RXDATAV LEUART0TXBL LEUART0TXEMPTY I2C0RXDATAV I2C0TXBL TIMER0UFOF TIMER0CC0 TIMER0CC1 TIMER0CC2 TIMER1UFOF TIMER1CC0 TIMER1CC1 TIMER1CC2 TIMER2UFOF TIMER2CC0 TIMER2CC1 TIMER2CC2 MSCWDATA AESDATAWR AESXORDATAWR AESDATARD AESKEYWR 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

81

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

9 RMU - Reset Management Unit

0 1 2 3 4

RESETn POWERON BROWNOUT LOCKUP SYSRESETREQ WATCHDOG Reset Managem ent Unit RESET

Quick Facts What?

The RMU ensures correct reset operation.

It is responsible for connecting the different reset sources to the reset lines of the EFM32HG.

Why?

A correct reset sequence is needed to ensure safe and synchronous startup of the EFM32HG. In the case of error situations such as power supply glitches or software crash, the RMU provides proper reset and startup of the EFM32HG.

How?

The Power-on Reset and Brown-out Detector of the EFM32HG provides power line monitoring with exceptionally low power consumption. The cause of the reset may be read from a register, thus providing software with information about the cause of the reset.

9.1 Introduction

The RMU is responsible for handling the reset functionality of the EFM32HG.

9.2 Features

• Reset sources • Power-on Reset (POR) • Brown-out Detection (BOD) on the following power domains: • Regulated domain • Unregulated domain • Analog Power Domain 0 (AVDD0) • Analog Power Domain 1 (AVDD1) • RESETn pin reset • Watchdog reset • EM4 wakeup reset from pin • Software triggered reset (SYSRESETREQ) • Core LOCKUP condition • EM4 Detection • A software readable register indicates the cause of the last reset

9.3 Functional Description

The RMU monitors each of the reset sources of the EFM32HG. If one or more reset sources go active, the RMU applies reset to the EFM32HG. When the reset sources go inactive the EFM32HG starts up.

At startup the EFM32HG loads the stack pointer and program entry point from memory, and starts execution.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

82

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

As seen in Figure 9.1 (p. 83) the Power-on Reset, Brown-out Detectors, Watchdog timeout and

RESETn pin all reset the whole system including the Debug Interface. A Core Lockup condition or a System reset request from software resets the whole system except the Debug Interface.

Whenever a reset source is active, the corresponding bit in the RMU_RSTCAUSE register is set. At startup the program code may investigate this register in order to determine the cause of the reset. The register must be cleared by software.

Figure 9.1. RMU Reset Input Sources and Connections.

POR V DD AVDD0 BOD V DD_REGULATED BOD BOD AVDD1 RESETn BOD Filt er EM4 wakeup WDOG Reset Managem ent Unit BROWNOUT_UNREGn BROWNOUT_REGn BROWNOUT_AVDD0 BROWNOUT_AVDD1 POWERONn em 4 RMU_RSTCAUSE RCCLR LOCKUP Edge- t o- pulse filt er LOCKUPRDIS SYSREQRST PORESETn SYSRESETn Debug Int erface Core Cort ex Peripherals

9.3.1 RMU_RSTCAUSE Register

The RMU_RSTCAUSE register indicates the reason for the last reset. The register should be cleared after the value has been read at startup. Otherwise the register may indicate multiple causes for the reset at next startup.

The following procedure must be done to clear RMU_RSTCAUSE: 1. Write a 1 to RCCLR in RMU_CMD 2. Write a 1 to bit 0 in EMU_AUXCTRL 3. Write a 0 to bit 0 in EMU_AUXCTRL

RMU_RSTCAUSE should be interpreted according to Table 9.1 (p. 84) . X bits are don't care. Notice

that it is possible to have multiple reset causes. For example, an external reset and a watchdog reset may happen simultaneously.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

83

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Table 9.1. RMU Reset Cause Register Interpretation

Register Value

0bXXX XXXX XXX1 0bXXX 0XXX XX10 0bXXX XXX0 0100 0bXXX XXXX 1X00 0bXXX XXX1 XX00 0bXXX XX10 0000 0b000 01X0 0000 0b000 1XX0 0XX0 0b001 1XX0 0XX0 0b010 0000 0000 0b100 0000 0000

Cause

A Power-on Reset has been performed. X bits are don't care.

A Brown-out has been detected on the unregulated power.

A Brown-out has been detected on the regulated power.

An external reset has been applied.

A watchdog reset has occurred.

A lockup reset has occurred.

A system request reset has occurred.

The system has woken up from EM4.

The system has woken up from EM4 on an EM4 wakeup reset request from pin.

A Brown-out has been detected on Analog Power Domain 0 (AVDD0).

A Brown-out has been detected on Analog Power Domain 1 (AVDD1).

Note

When exiting EM4 with external reset, both the BODREGRST and BODUNREGRST in RSTCAUSE might be set (i.e. are invalid)

9.3.2 Power-On Reset (POR)

The POR ensures that the EFM32HG does not start up before the supply voltage V DD has reached the threshold voltage VPORthr (see Device Datasheet Electrical Characteristics for details). Before the threshold voltage is reached, the EFM32HG is kept in reset state. The operation of the POR is illustrated

in Figure 9.2 (p. 84) , with the active low POWERONn reset signal. The reason for the “unknown”

region is that the corresponding supply voltage is too low for any reliable operation.

Figure 9.2. RMU Power-on Reset Operation

V V DD VPORt hr POWERONn Unknown t im e

9.3.3 Brown-Out Detector Reset (BOD)

The EFM32HG has 4 brownout detectors, one for the unregulated 3.0 V power, one for the regulated internal power, one for Analog Power Domain 0 (AVDD0), and one for Analog Power Domain 1 (AVDD1).

The BODs are constantly monitoring the voltages. Whenever the unregulated or regulated power drops below the VBODthr value (see Electrical Characteristics for details), or if the AVDD0 or AVDD1 drops below the voltage at the decouple pin (DEC), the corresponding active low BROWNOUTn line is held low. The BODs also include hysteresis, which prevents instability in the corresponding BROWNOUTn line when the supply is crossing the VBODthr limit or the AVDD bods drops below decouple pin (DEC).

The operation of the BOD is illustrated in Figure 9.3 (p. 85) . The “unknown” regions are handled

by the POR module.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

84

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 9.3. RMU Brown-out Detector Operation

V VBODt hr V DD BROWNOUTn Unknown VBODhyst VBODhyst Unknown t im e

9.3.4 RESETn pin Reset

Forcing the RESETn pin low generates a reset of the EFM32HG. The RESETn pin includes an on chip pull-up resistor, and can therefore be left unconnected if no external reset source is needed. Also connected to the RESETn line is a filter which prevents glitches from resetting the EFM32HG.

9.3.5 Watchdog Reset

The Watchdog circuit is a timer which (when enabled) must be cleared by software regularly. If software does not clear it, a Watchdog reset is activated. This functionality provides recovery from a software stalemate. Refer to the Watchdog section for specifications and description.

9.3.6 Lockup Reset

A Cortex-M0+ lockup is the result of the core being locked up because of an unrecoverable exception following the activation of the processor’s built-in system state protection hardware.

For more information about the Cortex-M0+ lockup conditions see the ARMv7-M Architecture Reference Manual. The Lockup reset does not reset the Debug Interface. Set the LOCKUPRDIS bit in the RMU_CTRL register in order to disable this reset source.

9.3.7 System Reset Request

Software may initiate a reset (e.g. if it finds itself in a non-recoverable state). By writing to the SYSRESETREQ bit in the Application Interrupt and Reset Control Register (see the Cortex-M0+ reference manual), a reset is issued. The SYSRESETREQ does not reset the Debug Interface.

9.3.8 EM4 Reset

Whenever EM4 is entered, the EM4RST bit is set. This bit enables the user to identify that the device has been in EM4. Upon wake-up this bit should be cleared by software.

9.3.9 EM4 Wakeup Reset

Whenever the system is woken up from EM4 on a pin wake-up request, the EM4WURST bit is set. This bit enables the user to identify that the device was woken up from EM4 using a pin wake-up request.

Upon wake-up this bit should be cleared by software.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

85

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

9.4 Register Map

The offset register address is relative to the registers base address.

Offset

0x000 0x004

0x008

Name

RMU_CTRL RMU_RSTCAUSE

RMU_CMD

Type

RW R W1

Description

Control Register Reset Cause Register

Command Register

9.5 Register Description 9.5.1 RMU_CTRL - Control Register Offset

0x000

Reset Access Bit Position Name Bit

31:1

0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LOCKUPRDIS 0 RW

Lockup Reset Disable

Set this bit to disable the LOCKUP signal (from the Cortex) from resetting the device.

9.5.2 RMU_RSTCAUSE - Reset Cause Register Offset

0x004

Reset Access Bit Position Name Bit

31:11

10 9 8

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BODAVDD1 0 R

AVDD1 Bod Reset

Set if analog power domain 1 brown out detector reset has been performed. Must be cleared by software. Please see Table 9.1 (p.

84) for details on how to interpret this bit.

BODAVDD0 0 R

AVDD0 Bod Reset

Set if analog power domain 0 brown out detector reset has been performed. Must be cleared by software. Please see Table 9.1 (p.

84) for details on how to interpret this bit.

EM4WURST 0 R

EM4 Wake-up Reset

Set if the system has been woken up from EM4 from a reset request from pin. Must be cleared by software. Please see Table 9.1 (p.

84) for details on how to interpret this bit.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

86

www.silabs.com

Bit

7 6 5 4 3 2 1 0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

EM4RST 0 R

EM4 Reset

Set if the system has been in EM4. Must be cleared by software. Please see Table 9.1 (p. 84) for details on how to interpret this bit.

SYSREQRST 0 R

System Request Reset

Set if a system request reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 84) for details on how

to interpret this bit.

LOCKUPRST 0 R

LOCKUP Reset

Set if a LOCKUP reset has been requested. Must be cleared by software. Please see Table 9.1 (p. 84) for details on how to interpret

this bit.

WDOGRST 0 R

Watchdog Reset

Set if a watchdog reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 84) for details on how to interpret

this bit.

EXTRST 0 R

External Pin Reset

Set if an external pin reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 84) for details on how to

interpret this bit.

BODREGRST 0 R

Brown Out Detector Regulated Domain Reset

Set if a regulated domain brown out detector reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 84)

for details on how to interpret this bit.

BODUNREGRST 0 R

Brown Out Detector Unregulated Domain Reset

Set if a unregulated domain brown out detector reset has been performed. Must be cleared by software. Please see Table 9.1 (p.

84) for details on how to interpret this bit.

PORST 0 R

Power On Reset

Set if a power on reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 84) for details on how to interpret

this bit.

9.5.3 RMU_CMD - Command Register Offset

0x008

Reset Access Bit Position Name Bit

31:1

0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RCCLR 0 W1

Reset Cause Clear

Set this bit to clear the LOCKUPRST and SYSREQRST bits in the RMU_RSTCAUSE register. Use the HRCCLR bit in the EMU_AUXCTRL register to clear the remaining bits.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

87

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

10 EMU - Energy Management Unit

0 1 2 3 4

Quick Facts What?

The EMU (Energy Management Unit) handles the different low energy modes in the EFM32HG microcontrollers.

Why?

The need for performance and peripheral functions varies over time in most applications. By efficiently scaling the available resources in real-time to match the demands of the application, the energy consumption can be kept at a minimum.

How?

With a broad selection of energy modes, a high number of low-energy peripherals available even in EM2, and short wake up time (2 µs from EM2 and EM3), applications can dynamically minimize energy consumption during program execution.

10.1 Introduction

The Energy Management Unit (EMU) manages all the low energy modes (EM) in EFM32HG microcontrollers. Each energy mode manages if the CPU and the various peripherals are available. The energy modes range from EM0 to EM4, where EM0, also called run mode, enables the CPU and all peripherals. The lowest recoverable energy mode, EM3, disables the CPU and most peripherals while maintaining wake-up and RAM functionality. EM4 disables everything except the POR, pin reset and optionally GPIO state retention and EM4 reset wakeup request.

The various energy modes differ in: • Energy consumption • CPU activity • Reaction time • Wake-up triggers • Active peripherals • Available clock sources Low energy modes EM1 to EM4 are enabled through the application software. In EM1-EM3, a range of wake-up triggers return the microcontroller back to EM0. EM4 can only return to EM0 by power on reset, external pin reset or EM4 GPIO wakeup request.

10.2 Features

• Energy Mode control from software • Flexible wakeup from low energy modes • Low wakeup time 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

88

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

10.3 Functional Description

The Energy Management Unit (EMU) is responsible for managing the wide range of energy modes

available in EFM32HG. An overview of the EMU module is shown in Figure 10.1 (p. 89) .

Figure 10.1. EMU Overview

Peripheral bus Cont rol and st at us regist ers Energy Managem ent St at e Machine Cort ex Volt age regulat or syst em Oscillat or syst em Reset syst em Mem ory syst em Int errupt cont roller The EMU is available as a peripheral on the peripheral bus. The energy management state machine is triggered from the Cortex-M0+ and controls the internal voltage regulators, oscillators, memories and interrupt systems in the low energy modes. Events from the interrupt or reset systems can in turn cause the energy management state machine to return to its active state. This is further described in the following sections.

10.3.1 Energy Modes

There are five main energy modes available in EFM32HG, called Energy Mode 0 (EM0) through Energy Mode 4 (EM4). EM0, also called the active mode, is the energy mode in which any peripheral function can be enabled and the Cortex-M0+ core is executing instructions. EM1 through EM4, also called low energy modes, provide a selection of reduced peripheral functionality that also lead to reduced energy consumption, as described below.

Figure 10.2 (p. 90) shows the transitions between different energy modes. After reset the EMU will

always start in EM0. A transition from EM0 to another energy mode is always initiated by software. EM0 is the highest activity mode, in which all functionality is available. EM0 is therefore also the mode with highest energy consumption.

The low energy modes EM1 through EM4 result in less functionality being available, and therefore also reduced energy consumption. The Cortex-M0+ is not executing instructions in any low energy mode.

Each low energy mode provides different energy consumptions associated with it, for example because a different set of peripherals are enabled or because these peripherals are configured differently.

A transition from EM0 to a low energy mode can only be triggered by software.

A transition from EM1 – EM3 to EM0 can be triggered by an enabled interrupt or event. In addition, a chip reset will return the device to EM0. A transition from EM4 can only be triggered by a pin reset, power-on reset, or EM4 GPIO wakeup request.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

89

www.silabs.com

Preliminary

Figure 10.2. EMU Energy Mode Transitions ...the world's most energy friendly microcontrollers

Act ive m ode

EM0 EM1

Low energy m odes

EM2 EM3 EM4

No direct transitions between EM1, EM2 or EM3 are available, as can also be seen from Figure 10.2 (p.

90) . Instead, a wakeup will transition back to EM0, in which software can enter any other low energy

mode. An overview of the supported energy modes and the functionality available in each mode is shown

in Table 10.1 (p. 91) . Most peripheral functionality indicated as "On" in a particular energy mode can

also be turned off from software in order to save further energy.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

90

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Table 10.1. EMU Energy Mode Overview

EM0

1 Wakeup time to EM0 MCU clock tree High frequency peripheral clock trees Core voltage regulator High frequency oscillator I 2 C full functionality Low frequency peripheral clock trees Low frequency oscillator Real Time Counter LEUART PCNT ACMP I 2 C receive address recognition IDAC Watchdog Pin interrupts RAM voltage regulator/RAM retention Brown Out Reset Power On Reset Pin Reset GPIO state retention EM4 Reset Wakeup Request 1 Energy Mode 0/Active Mode 2 Energy Mode 1/2/3/4 3 When the 1 kHz ULFRCO is selected On On On On On On On On On On On On On On On On On On On On The different Energy Modes are summarized in the following sections.

On On On On On On On -

EM2

2 2 µs On On On On On On On On On On On On On On On On On On -

EM1

2 On On On On On On On On On

10.3.1.1 EM0

• The high frequency oscillator is active • High frequency clock trees are active • All peripheral functionality is available -

EM3

2 2 µs On 3 On On On On On On On On On 3 On On On On On On -

EM4

2 160 µs -

10.3.1.2 EM1

• The high frequency oscillator is active • MCU clock tree is inactive • High frequency peripheral clock trees are active • All peripheral functionality is available

10.3.1.3 EM2

• The high frequency oscillator is inactive 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

91

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• The high frequency peripheral and MCU clock trees are inactive • The low frequency oscillator and clock trees are active • Low frequency peripheral functionality is available • Wakeup through peripheral interrupt or asynchronous pin interrupt • RAM and register values are preserved

10.3.1.4 EM3

• Both high and low frequency oscillators and clock trees are inactive • Wakeup through asynchronous pin interrupts, I 2 C address recognition or ACMP edge interrupt • Watchdog and some low frequency peripherals available when ULFRCO (1 kHz clock) has been selected • All other peripheral functionality is disabled • RAM and register values are preserved

10.3.1.5 EM4

• All oscillators and regulators are inactive • RAM and register values are not preserved • Optional GPIO state retention • Wakeup from external pin reset or pins that support EM4 wakeup

10.3.2 Entering a Low Energy Mode

A low energy mode is entered by first configuring the desired Energy Mode through the EMU_CTRL

register and the SLEEPDEEP bit in the Cortex-M0+ System Control Register, see Table 10.2 (p. 92) .

A Wait For Interrupt (WFI) or Wait For Event (WFE) instruction from the Cortex-M0+ triggers the transition into a low energy mode.

The transition into a low energy mode can optionally be delayed until the lowest priority Interrupt Service Routine (ISR) is exited, if the SLEEPONEXIT bit in the Cortex-M0+ System Control Register is set.

Entering the lowest energy mode, EM4, is done by writing a sequence to the EM4CTRL bitfield in the EMU_CTRL register. Writing a zero to the EM4CTRL bitfield will restart the power sequence.

EM2BLOCK prevents the EMU to enter EM2 or lower, and it will instead enter EM1.

EM3 is equal to EM2, except that the LFACLK/LFBCLK are disabled in EM3. The LFACLK/LFBCLK must be disabled by the user before entering low energy mode.

The EMVREG bit in EMU_CTRL can be used to prevent the voltage regulator from being turned off in low energy modes. The device will then essentially stay in EM1 (with HF oscillators disabled) when entering a low energy mode. Note that if a DMA transfer is initiated in this mode, the HF-oscillators will start and remain enabled until the device is woken up from an EM2 interrupt.

Table 10.2. EMU Entering a Low Energy Mode

Low Energy Mode EM4CTRL EMVREG EM2BLOCK SLEEPDEEP

EM1 EM2 EM4 0 0 Write sequence: 2, 3, 2, 3, 2, 3, 2, 3, 2 x 0 x x 0 x 0 1 x

Cortex-M0+ Instruction

WFI or WFE WFI or WFE x (‘x’ means don’t care) 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

92

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

10.3.3 Leaving a Low Energy Mode

In each low energy mode a selection of peripheral units are available, and software can either enable or disable the functionality. Enabled interrupts that can cause wakeup from a low energy mode are shown

in Table 10.3 (p. 93) . The wakeup triggers always return the EFM32 to EM0. Additionally, any reset

source will return to EM0.

Table 10.3. EMU Wakeup Triggers from Low Energy Modes

Peripheral Wakeup Trigger EM0

1 RTC USART LEUART I 2 C I 2 C TIMER CMU DMA MSC ADC Any enabled interrupt Receive / transmit Receive / transmit Any enabled interrupt Receive address recognition Any enabled interrupt Any enabled interrupt Any enabled interrupt Any enabled interrupt Any enabled interrupt AES PCNT ACMP VCMP Any enabled interrupt Any enabled interrupt Any enabled edge interrupt Any enabled edge interrupt Pin interrupts Pin Asynchronous Reset EM4 wakeup on supported pins Asynchronous Power Cycle Off/On 1 Energy Mode 0/Active Mode 2 Energy mode 1/2/3/4 3 When the 1 kHz ULFRCO is selected 4 When using an external clock -

EM1

2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

EM2

2 Yes Yes Yes Yes Yes Yes Yes Yes Yes -

EM3

2 Yes 3 Yes Yes Yes Yes Yes Yes 4 Yes -

EM4

2 Yes Yes Yes 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

93

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

10.4 Register Map

The offset register address is relative to the registers base address.

Offset

0x000 0x008

0x024

Name

EMU_CTRL EMU_LOCK

EMU_AUXCTRL

Type

RW RW RW

Description

Control Register Configuration Lock Register

Auxiliary Control Register

10.5 Register Description 10.5.1 EMU_CTRL - Control Register Offset

0x000

Reset Access Bit Position Name

1 0

Bit

31:4

3:2

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

EM4CTRL 0x0 RW

Energy Mode 4 Control

This register is used to enter Energy Mode 4, in which the device only wakes up from an external pin reset, from a power cycle, or EM4 wakeup reset request. Energy Mode 4 is entered when the EM4 sequence is written to this bitfield.

EM2BLOCK 0 RW

Energy Mode 2 Block

This bit is used to prevent the MCU to enter Energy Mode 2 or lower.

EMVREG 0 RW Control the voltage regulator in low energy modes 2 and 3.

Energy Mode Voltage Regulator Control

Value 0 1 Mode REDUCED FULL Description Reduced voltage regulator drive strength in EM2 and EM3.

Full voltage regulator drive strength in EM2 and EM3.

10.5.2 EMU_LOCK - Configuration Lock Register Offset

0x008

Bit Position Reset Access Name Bit

31:16

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

94

www.silabs.com

Bit

15:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

LOCKKEY 0x0000 RW

Configuration Lock Key

Write any other value than the unlock code to lock all EMU registers, except the interrupt registers, from editing. Write the unlock code to unlock. When reading the register, bit 0 is set when the lock is enabled.

Mode Read Operation UNLOCKED LOCKED Write Operation LOCK UNLOCK Value 0 1 0 0xADE8 Description EMU registers are unlocked.

EMU registers are locked.

Lock EMU registers.

Unlock EMU registers.

10.5.3 EMU_AUXCTRL - Auxiliary Control Register Offset

0x024

Reset Access Bit Position Name Bit

31:1

0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

HRCCLR 0 RW

Hard Reset Cause Clear

Write to 1 and then 0 to clear the POR, BOD and WDOG reset cause register bits. See also the Reset Management Unit (RMU).

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

95

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

11 CMU - Clock Management Unit

0 1 2 3 4

Oscillat ors CMU WDOG clock LETIMER clock Peripheral A clock Peripheral B clock Peripheral C clock Peripheral D clock CPU clock

Quick Facts What?

The CMU controls oscillators and clocks.

EFM32HG supports five different oscillators with minimized power consumption and short start-up time. An additional separate RC oscillator is used for flash programming. The CMU also has HW support for calibration of RC oscillators.

Why?

Oscillators and clocks contribute significantly to the power consumption of the MCU. With the low power oscillators combined with the flexible clock control scheme, it is possible to minimize the energy consumption in any given application.

How?

The CMU can configure different clock sources, enable/disable clocks to peripherals on an individual basis and set the prescaler for the different clocks. The short oscillator start-up times makes duty-cycling between active mode and the different low energy modes (EM2-EM4) very efficient. The calibration feature ensures high accuracy RC oscillators. Several interrupts are available to avoid CPU polling of flags.

11.1 Introduction

The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32HG. The CMU provides the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not wasting power on peripherals and oscillators that are inactive.

11.2 Features

• Multiple clock sources available: • 1-21 MHz High Frequency RC Oscillator (HFRCO) • 4-25 MHz High Frequency Crystal Oscillator (HFXO) • 32768 Hz Low Frequency RC Oscillator (LFRCO) • 32768 Hz Low Frequency Crystal Oscillator (LFXO) • 1000 Hz Ultra Low Frequency RC Oscillator (ULFRCO) • 48/24 MHz Universal Serial High Frequency RC Oscillator (USHFRCO) • Low power oscillators • Low start-up times • Separate prescaler for High Frequency Core Clocks (HFCORECLK) and Peripheral Clocks (HFPERCLK) 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

96

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• Individual clock prescaler selection for each Low Energy Peripheral • Clock Gating on an individual basis to core modules and all peripherals • Selectable clocks can be output on two pins for use externally.

• Auxiliary 1-21 MHz RC oscillator (AUXHFRCO) for flash programming.

11.3 Functional Description

An overview of the CMU is shown in Figure 11.1 (p. 98) . The number of peripheral modules that are

connected to the different clocks varies from device to device.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

97

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 11.1. CMU Overview

AUXHFRCO HFXO HFRCO USHFRCO LFXO LFRCO Tim eout AUXCLK MSC (Flash Program m ing) Tim eout Tim eout Tim eout Tim eout Tim eout CMU_HFPERCLKEN0.TIMER0

Clock Gat e HFPERCLK TIMER0 CMU_HFPERCLKDIV.HFPERCLKEN

/ 1 or / 2 prescaler HFPERCLK CMU_HFPERCLKDIV.HFPERCLKDIV

clock swit ch CMU_CTRL.HFCLKDIV

HFCLK DIV HFCLK CMU_HFPERCLKEN0.TIMER1

CMU_HFPERCLKEN0.I2C0

Clock Gat e .

.

.

Clock Gat e HFPERCLK TIMER1 .

.

.

HFPERCLK I2C0 EM0 Clock Gat e HFCORECLK CM0 CMU_CMD.HFCLKSEL

CMU_HFCORECLKDIV prescaler HFCORECLK CMU_HFCORECLKEN0.DMA

CMU_HFCORECLKEN0.LE

Clock Gat e .

.

.

Clock Gat e HFCORECLK DMA .

.

.

HFCORECLK LE clock swit ch CMU_HFCORECLKEN0.USBC

CMU_CMD.USBCCLKSEL

HFCORECLK USBC clock swit ch CMU_LFCLKSEL.USBLE

LFCCLK USBLE / 2 or / 4 CMU_LFACLKEN0.RTC

Clock Gat e LFACLK RTC clock swit ch LFACLK CMU_LFCLKSEL.LFA / LFAE prescaler CMU_LFAPRESC0.RTC

PCNTn_S0 PCNTnCLK CMU_PCNTCTRL.PCNTnCLKSEL

CMU_LFCLKSEL.LFB / LFBE clock swit ch LFBCLK CMU_LFBPRESC0.LEUART0

prescaler CMU_LFBCLKEN0.LEUART0

Clock Gat e LFBCLK LEUART0 ULFRCO WDOGCLK WDOG_CTRL.CLKSEL

WDOG

11.3.1 System Clocks 11.3.1.1 HFCLK - High Frequency Clock

HFCLK is the selected High Frequency Clock. This clock is used by the CMU and drives the two prescalers that generate HFCORECLK and HFPERCLK. The HFCLK can be driven by a high-frequency oscillator (HFRCO, USHFRCO or HFXO) or one of the low-frequency oscillators (LFRCO or LFXO). By 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

98

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

default the HFRCO is selected. In most applications, one of the high frequency oscillators will be the preferred choice. To change the selected HFCLK write to HFCLKSEL in CMU_CMD. The HFCLK is running in EM0 and EM1.

HFCLK can optionally be divided down by setting HFCLKDIV in CMU_CTRL to a nonzero value. This divides down HFCLK to all high frequency components, and combined with the HFCORECLK and HFPERCLK prescalers the HFCLK divider allows for more flexible clock division.

11.3.1.2 HFCORECLK - High Frequency Core Clock

HFCORECLK is a prescaled version of HFCLK. This clock drives the Core Modules, which consists of the CPU and modules that are tightly coupled to the CPU, e.g. MSC, DMA etc. This also includes the interface to the Low Energy Peripherals. Some of the modules that are driven by this clock can be clock gated completely when not in use. This is done by clearing the clock enable bit for the specific module in CMU_HFCORECLKEN0. The frequency of HFCORECLK is set using the CMU_HFCORECLKDIV register. The setting can be changed dynamically and the new setting takes effect immediately.

The USB Core runs on HFCORECLK USBC . Selectable clock sources are LFXO, LFRCO and USHFRCO.

When the USB Core is active this clock must be switched to a 32 kHz clock (LFRCO or LFXO) when entering EM2. The USB Core uses this clock for monitoring the USB bus. The switch is done by writing USBCCLKSEL in CMU_CMD. The currently active clock can be checked by reading CMU_STATUS.

The clock switch can take up to 1.5 32 kHz cycle (45 us). To avoid polling the clock selection status when switching from 32 kHz to HFCLK when coming up from EM2 the USBCHFCLKSEL interrupt can be used. EM3 is not supported when the USB is active.

Note

Note that if HFPERCLK runs faster than HFCORECLK, the number of clock cycles for each bus-access to peripheral modules will increase with the ratio between the clocks. Please

refer to Section 5.2.2.2 (p. 17) for more details.

11.3.1.3 HFPERCLK - High Frequency Peripheral Clock

Like HFCORECLK, HFPERCLK can also be a prescaled version of HFCLK. This clock drives the High-Frequency Peripherals. All the peripherals that are driven by this clock can be clock gated completely when not in use. This is done by clearing the clock enable bit for the specific peripheral in CMU_HFPERCLKEN0. The frequency of HFPERCLK is set using the CMU_HFPERCLKDIV register.

The setting can be changed dynamically and the new setting takes effect immediately.

Note

Note that if HFPERCLK runs faster than HFCORECLK, the number of clock cycles for each bus-access to peripheral modules will increase with the ratio between the clocks. E.g. if a bus-access normally takes three cycles, it will take 9 cycles if HFPERCLK runs three times as fast as the HFCORECLK.

11.3.1.4 LFACLK - Low Frequency A Clock

LFACLK is the selected clock for the Low Energy A Peripherals. There are four selectable sources for LFACLK: LFRCO, LFXO, HFCORECLK/2 and ULFRCO. In addition, the LFACLK can be disabled. From reset, the LFACLK source is set to LFRCO. However, note that the LFRCO is disabled from reset. The selection is configured using the LFA field in CMU_LFCLKSEL. The HFCORECLK/2 setting allows the Low Energy A Peripherals to be used as high-frequency peripherals.

Note

If HFCORECLK/2 is selected as LFACLK, the clock will stop in EM2/3.

Each Low Energy Peripheral that is clocked by LFACLK has its own prescaler setting and enable bit. The prescaler settings are configured using CMU_LFAPRESC0 and the clock enable bits can be found in 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

99

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

CMU_LFACLKEN0. When operating in oversampling mode, the pulse counters are clocked by LFACLK.

This is configured for each pulse counter (n) individually by setting PCNTnCLKSEL in CMU_PCNTCTRL.

11.3.1.5 LFBCLK - Low Frequency B Clock

LFBCLK is the selected clock for the Low Energy B Peripherals. There are four selectable sources for LFBCLK: LFRCO, LFXO, HFCORECLK/2 and ULFRCO. In addition, the LFBCLK can be disabled. From reset, the LFBCLK source is set to LFRCO. However, note that the LFRCO is disabled from reset. The selection is configured using the LFB field in CMU_LFCLKSEL. The HFCORECLK/2 setting allows the Low Energy B Peripherals to be used as high-frequency peripherals.

Note

If HFCORECLK/2 is selected as LFBCLK, the clock will stop in EM2/3.

Each Low Energy Peripheral that is clocked by LFBCLK has its own prescaler setting and enable bit.

The prescaler settings are configured using CMU_LFBPRESC0 and the clock enable bits can be found in CMU_LFBCLKEN0.

11.3.1.6 LFCCLK - Low Frequency C Clock

LFCCLK is the selected clock for the Low Energy C Peripherals. There are two selectable sources for LFCCLK: LFRCO and LFXO. In addition, the LFCCLK can be disabled. From reset, the LFCCLK source is set to LFRCO. However, note that the LFRCO is disabled from reset. The selection is configured using the LFC field in CMU_LFCLKSEL.

11.3.1.7 PCNTnCLK - Pulse Counter n Clock

Each available pulse counter is driven by its own clock, PCNTnCLK where n is the pulse counter instance number. Each pulse counter can be configured to use an external pin (PCNTn_S0) or LFACLK as PCNTnCLK.

11.3.1.8 WDOGCLK - Watchdog Timer Clock

The Watchdog Timer (WDOG) can be configured to use one of three different clock sources: LFRCO, LFXO or ULFRCO. ULFRCO (Ultra Low Frequency RC Oscillator) is a separate 1 kHz RC oscillator that also runs in EM3.

11.3.1.9 AUXCLK - Auxiliary Clock

AUXCLK is a 1-21 MHz clock driven by a separate RC oscillator, AUXHFRCO. This clock is used for flash programming operation. During flash programming this clock will be active. If the AUXHFRCO has not been enabled explicitly by software, the MSC module will automatically start and stop it. The AUXHFRCO is enabled by writing a 1 to AUXHFRCOEN in CMU_OSCENCMD.

11.3.2 Oscillator Selection 11.3.2.1 Start-up Time

The different oscillators have different start-up times. For the RC oscillators, the start-up time is fixed, but both the LFXO and the HFXO have configurable start-up time. At the end of the start-up time a ready flag is set to indicated that the start-up time has exceeded and that the clock is available. The low start up time values can be used for an external clock source of already high quality, while the higher start-up times should be used when the clock signal is coming directly from a crystal. The startup time for HFXO and LFXO can be set by configuring the HFXOTIMEOUT and LFXOTIMEOUT bitfields, respectively.

Both bitfields are located in CMU_CTRL. For HFXO it is also possible to enable a glitch detection filter by setting HFXOGLITCHDETEN in CMU_CTRL. The glitch detector will reset the start-up counter if a glitch is detected, making the start-up process start over again.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

100

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

There are individual bits for each oscillator indicating the status of the oscillator: • ENABLED - Indicates that the oscillator is enabled • READY - Start-up time is exceeded • SELECTED - Start-up time is exceeded and oscillator is chosen as clock source These status bits are located in the CMU_STATUS register.

11.3.2.2 Switching Clock Source

The HFRCO oscillator is a low energy oscillator with extremely short wake-up time. Therefore, this oscillator is always chosen by hardware as the clock source for HFCLK when the device starts up (e.g.

after reset and after waking up from EM2 and EM3). After reset, the HFRCO frequency is 14 MHz.

Software can switch between the different clock sources at run-time. E.g., when the HFRCO is the clock source, software can switch to HFXO by writing the field HFCLKSEL in the CMU_CMD command

register. See Figure 11.2 (p. 101) for a description of the sequence of events for this specific operation.

Note

It is important first to enable the HFXO since switching to a disabled oscillator will effectively stop HFCLK and only a reset can recover the system.

During the start-up period HFCLK will stop since the oscillator driving it is not ready. This effectively stalls the Core Modules and the High-Frequency Peripherals. It is possible to avoid this by first enabling the HFXO and then wait for the oscillator to become ready before switching the clock source. This way, the system continues to run on the HFRCO until the HFXO has timed out and provides a reliable clock.

This sequence of events is shown in Figure 11.3 (p. 102) .

A separate flag is set when the oscillator is ready. This flag can also be configured to generate an interrupt.

Figure 11.2. CMU Switching from HFRCO to HFXO before HFXO is ready

CMU_CMD.HFCLKSEL

CMU_OSCENCMD.HFRCOEN

CMU_OSCENCMD.HFRCODIS

CMU_OSCENCMD.HFXOEN

CMU_OSCENCMD.HFXODIS

CMU_STATUS.HFRCORDY

CMU_STATUS.HFRCOENS

CMU_STATUS.HFRCOSEL

CMU_STATUS..HFXORDY

CMU_STATUS.HFXOENS

CMU_STATUS.HFXOSEL

HFCLK HFRCO HFXO 00 02 00 HFXO t im e- out period 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

101

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 11.3. CMU Switching from HFRCO to HFXO after HFXO is ready

00 02 00 CMU_CMD.HFCLKSEL

CMU_OSCENCMD.HFRCOEN

CMU_OSCENCMD.HFRCODIS

CMU_OSCENCMD.HFXOEN

CMU_OSCENCMD.HFXODIS

CMU_STATUS.HFRCORDY

CMU_STATUS.HFRCOENS

CMU_STATUS.HFRCOSEL

CMU_STATUS.HFXORDY

CMU_STATUS.HFXOENS

CMU_STATUS.HFXOSEL

HFCLK HFRCO HFXO HFXO t im e- out period Switching clock source for LFACLK and LFBCLK is done by setting the LFA and LFB fields in CMU_LFCLKSEL. To ensure no stalls in the Low Energy Peripherals, the clock source should be ready before switching to it.

Note

To save energy, remember to turn off all oscillators not in use.

11.3.3 Oscillator Configuration 11.3.3.1 HFXO and LFXO

The crystal oscillators are by default configured to ensure safe startup and operation of the most common crystals. In order to optimize startup margin, startup time and power consumption for a given crystal, it is possible to adjust the gain in the oscillator. HFXO gain can be increased by setting HFXOBOOST field in CMU_CTRL, LFXO gain can be increased by setting LFXOBOOST field in CMU_CTRL. It is important that the boost settings, along with the crystal load capacitors are matched to the crystals in use. Correct values for these parameters can be found using the energyAware Designer.

The HFXO crystal is connected to the HFXTAL_N/HFXTAL_P pins as shown in Figure 11.4 (p. 102)

Figure 11.4. HFXO Pin Connection

C L1 4- 25 MHz C L2 HFXTAL_N HFXTAL_P EFM32 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

102

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Similarly, the LFXO crystal is connected to the LFXTAL_N/LFXTAL_P pins as shown in Figure 11.5 (p.

103)

Figure 11.5. LFXO Pin Connection

C L1 32.768kHz

C L2 LFXTAL_N LFXTAL_P EFM32 It is possible to connect an external clock source to HFXTAL_N/LFXTAL_N pin of the HFXO or LFXO oscillator. By configuring the HFXOMODE/LFXOMODE fields in CMU_CTRL, the HFXO/LFXO can be bypassed.

11.3.3.2 USHFRCO

The USHFRCO has a startup time of 6 microseconds. This timeout needs to be configured in the TIMEOUT bit field of CMU_USHFRCOCTRL before starting the oscillator. The USHFCRO can be suspended by setting the SUSPEND bit in CMU_USHFRCOCTRL. From suspended state, the startup time is 200 nanoseconds. The USHFRCO has two frequency bands, 48MHz and 24MHz, configured in the BAND bit field in CMU_USHFRCOCONF. The frequency can be tuned by configuring the TUNING bit field in CMU_USHFRCOCTRL. For finer grained calibration, FINETUNING in CMU_USHFRCOTUNE can be used.

Note

When the USHFRCO is selected as HFCLK, the clock divider controlled by USHFRCODIV2DIS in CMU_USHFRCOCONF needs to be enabled. When switching frequency band or enabling/disabling the USHFRCO clock divider, the USHFRCO should not be selected as clock source for HFCLK or USBC.

The USHFRCO can be automatically calibrated during USB communication to achieve sufficient accuracy. This feature is enabled by setting EN in CMU_USBCRCTRL. When operating USB in Low Speed mode, the LSMODE bit in CMU_USBCRCTRL also needs to be set. USB clock recovery will automatically tune the FINETUNING bit field in CMU_USHFRCOTUNE.

11.3.3.3 HFRCO, LFRCO and AUXHFRCO

The HFRCO and AUXHFRCO can be set to one of several different frequency bands from 1 MHz to 28 MHz by setting the BAND field in CMU_HFRCOCTRL and CMU_AUXHFRCOCTRL.The HFRCO and AUXHFRCO frequency bands are calibrated during production test, and the production tested calibration values can be read from the Device Information (DI) page. The DI page contains a separate tuning value for each frequency band. During reset, HFRCO and AUXHFRCO tuning values are set to the production calibrated values for the 14 MHz band, which is the default frequency band. When changing to a different HFRCO or AUXHFRCO band, make sure to also update the tuning value.

The LFRCO and is also calibrated in production and its TUNING value is set to the correct value during reset.

11.3.3.4 RC oscillator calibration

It is possible to calibrate the HFRCO, AUXHFRCO, USHFRCO and LFRCO to achieve higher accuracy (see the device datasheets for details on accuracy). The frequency is adjusted by changing the TUNING 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

103

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

fields in CMU_HFRCOCTRL/CMU_AUXHFRCOCTRL/CMU_LFRCOCTRL. Changing to a higher value will result in a higher frequency. Please refer to the datasheet for stepsize details.

For the USHFRCO, the frequency can be tuned using the TUNING field in CMU_USHFRCOCTRL.

The USHFRCO also employs a second set of FINETUNING registers in CMU_USHFRCOTUNE with smaller step-size allowing for much finer tuning. The FINETUNING registers are inteded for temperature/ voltage calibration, and is what the clock recovery hardware is using to keep the frequency constant over temperature. Note that for the USHFRCO both the TUNING and FINTUNING bit-fields are inverted, meaning that a higher value gives a lower frequency.

The CMU has built-in HW support to efficiently calibrate the RC oscillators at run-time, see Figure 11.6 (p.

104) The concept is to select a reference and compare the RC frequency with the reference frequency.

When the calibration circuit is started, one down-counter running on a selectable clock (DOWNSEL in CMU_CALCTRL) and one up-counter running on a selectable clock (UPSEL in CMU_CALCTRL) are started simultaneously. The top value for the down-counter must be written to CMU_CALCNT before calibration is started. The smallest value that can be written to the CMU_CALCNT is 1. The down-counter counts for CMU_CALCNT+1 cycles. When the down-counter has reached 0, the up-counter is sampled and the CALRDY interrupt flag is set. If CONT in CMU_CALCTRL is cleared, the counters are stopped at this point. If continuous mode is selected by setting CONT in CMU_CALCTRL the down-counter reloads the top value and continues counting and the up-counter restarts from 0. Software can then read out the sampled up-counter value from CMU_CALCNT. Then it is easy to find the ratio between the reference and the oscillator subject to the calibration. Overflows of the up-counter will not occur. If the up-counter reaches its top value before the down counter reaches 0, the top counter stays at its top value. Calibration can be stopped by writing CALSTOP in CMU_CMD. With this HW support, it is simple to write efficient calibration algorithms in software.

Figure 11.6. HW-support for RC Oscillator Calibration

DOWNCLK Dom ain USHFRCO AUXHFRCO HFRCO CMU_CALCTRL.DOWNSEL

DOWNCLK LFRCO HFXO LFXO (Default ) HFCLK 20- bit down- count er = 0 ?

UPCLK Dom ain USHFRCO AUXHFRCO HFRCO LFRCO HFXO LFXO CMU_CALCTRL.REFSEL

UPCLK SYNC 20- bit up- count er HFCLK Dom ain Reload down- count er wit h t op value in cont inouous m ode.

TOP Take snapshot of up- count er in up- count er bufffer. If in cont inouous m ode, rest art up- count er from 0.

20- bit up- count er buffer Writ e t op- value using CMU_CALCNT before st art ing calibrat ion.

SYNC CMU_CALCNT SYNC Set CMU_IF.CALRDY

The counter operation for single and continuous mode are shown in Figure 11.7 (p. 105) and Figure 11.8 (p. 105) respectively.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

104

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 11.7. Single Calibration (CONT=0)

Up- count er sam pled and CALRDY int errupt flag set .

Sam pled value available in CMU_CALCNT.

Up- count er 0 TOP Down- count er 0 Calibrat ion St art ed Calibrat ion St opped (count ers st opped)

Figure 11.8. Continuous Calibration (CONT=1)

Up- count er sam pled and CALRDY int errupt flag set .

Sam pled value available in CMU_CALCNT.

Up- count er 0 TOP Down- count er 0 Calibrat ion St art ed Up- count er sam pled and CALRDY int errupt flag set .

Sam pled value available in CMU_CALCNT.

11.3.4 Output Clock on a Pin

It is possible to configure the CMU to output clocks on two pins. This clock selection is done using CLKOUTSEL0 and CLKOUTSEL1 fields in CMU_CTRL. The output pins must be configured in the CMU_ROUTE register.

• LFRCO, LFXO, HFCLK or the qualified clock from any of the oscillators can be output on one pin (CMU_OUT1). A qualified clock will not have any glitches or skewed duty-cycle during startup. For LFXO and HFXO you need to configure LFXOTIMEOUT and HFXOTIMEOUT in CMU_CTRL correctly to guarantee a qualified clock.

• HFRCO, HFXO, HFCLK/2, HFCLK/4, HFCLK/8, HFCLK/16, ULFRCO or AUXHFRCO can be output on another pin (CMU_OUT0) Note that HFXO and HFRCO clock outputs to pin can be unstable after startup and should not be output on a pin before HFXORDY/HFRCORDY is set high in CMU_STATUS.

11.3.5 Protection

It is possible to lock the control- and command registers to prevent unintended software writes to critical clock settings. This is controlled by the CMU_LOCK register.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

105

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

11.4 Register Map

The offset register address is relative to the registers base address.

Offset

0x000

0x004 0x008

0x00C

0x010 0x014

0x018 0x01C

0x020

0x024 0x028

0x02C

0x030

0x078 0x080

0x084 0x0D0

0x0D4 0x0D8

0x0DC

0x034 0x038

0x03C

0x040 0x044

0x050

0x054

0x058 0x060 0x064

0x068 0x070

Name

CMU_CTRL

CMU_HFCORECLKDIV CMU_HFPERCLKDIV

CMU_HFRCOCTRL

CMU_LFRCOCTRL CMU_AUXHFRCOCTRL

CMU_CALCTRL CMU_CALCNT

CMU_OSCENCMD

CMU_CMD CMU_LFCLKSEL

CMU_STATUS

CMU_IF

CMU_IFS CMU_IFC

CMU_IEN

CMU_HFCORECLKEN0 CMU_HFPERCLKEN0

CMU_SYNCBUSY

CMU_FREEZE

CMU_LFACLKEN0 CMU_LFBCLKEN0 CMU_LFCCLKEN0

CMU_LFAPRESC0 CMU_LFBPRESC0

CMU_PCNTCTRL CMU_ROUTE

CMU_LOCK CMU_USBCRCTRL

CMU_USHFRCOCTRL CMU_USHFRCOTUNE

CMU_USHFRCOCONF

Type

RW RW RW RW RW RW RW RWH W1 W1 RW R R RW RW RW RW RW RWH RW W1 W1 RW RW RW R RW RW RW RW RW RW

Description

CMU Control Register

High Frequency Core Clock Division Register High Frequency Peripheral Clock Division Register

HFRCO Control Register

LFRCO Control Register AUXHFRCO Control Register

Calibration Control Register Calibration Counter Register

Oscillator Enable/Disable Command Register

Command Register Low Frequency Clock Select Register

Status Register

Interrupt Flag Register

Interrupt Flag Set Register Interrupt Flag Clear Register

Interrupt Enable Register

High Frequency Core Clock Enable Register 0 High Frequency Peripheral Clock Enable Register 0

Synchronization Busy Register

Freeze Register

Low Frequency A Clock Enable Register 0 (Async Reg) Low Frequency B Clock Enable Register 0 (Async Reg) Low Frequency C Clock Enable Register 0 (Async Reg)

Low Frequency A Prescaler Register 0 (Async Reg) Low Frequency B Prescaler Register 0 (Async Reg)

PCNT Control Register I/O Routing Register

Configuration Lock Register USB Clock Recovery Control

USHFRCO Control USHFRCO Frequency Tune

USHFRCO Configuration

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

106

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

11.5 Register Description 11.5.1 CMU_CTRL - CMU Control Register Offset

0x000

Reset Access Bit Position Name Bit

31:27

26:23 22:20 19:18 17 16:14

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CLKOUTSEL1 0x0 RW

Clock Output Select 1

Controls the clock output multiplexer. To actually output on the pin, set CLKOUT1PEN in CMU_ROUTE.

5 6 7 2 3 4 Value 0 1 3 4 5 6 7 8 Value 0 1 2 CLKOUTSEL0 0x0 RW

Clock Output Select 0

Controls the clock output multiplexer. To actually output on the pin, set CLKOUT0PEN in CMU_ROUTE.

LFXOTIMEOUT Mode LFRCO LFXO HFCLK LFXOQ HFXOQ LFRCOQ HFRCOQ AUXHFRCOQ USHFRCO Mode HFRCO HFXO HFCLK2 HFCLK4 HFCLK8 HFCLK16 ULFRCO AUXHFRCO 0x3 Configures the start-up delay for LFXO.

RW Description LFRCO (directly from oscillator).

LFXO (directly from oscillator).

HFCLK (undivided).

LFXO (qualified).

HFXO (qualified).

LFRCO (qualified).

HFRCO (qualified).

AUXHFRCO (qualified).

USHFRCO Description HFRCO (directly from oscillator).

HFXO (directly from oscillator).

HFCLK/2.

HFCLK/4.

HFCLK/8.

HFCLK/16.

ULFRCO (directly from oscillator).

AUXHFRCO (directly from oscillator).

LFXO Timeout

Value 0 1 2 3 Mode 8CYCLES 1KCYCLES 16KCYCLES 32KCYCLES Description Timeout period of 8 cycles.

Timeout period of 1024 cycles.

Timeout period of 16384 cycles.

Timeout period of 32768 cycles.

LFXOBUFCUR 0 RW

LFXO Boost Buffer Current

This value has been updated to the correct level during calibration and should not be changed.

HFCLKDIV 0x0 RW

HFCLK Division

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

107

www.silabs.com

Bit

13 12:11 10:9

8

7 6:5

4

3:2 1:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access

Use to divide HFCLK frequency by (HFCLKDIV + 1).

LFXOBOOST 1 Adjusts start-up boost current for LFXO.

RW

Description LFXO Start-up Boost Current

Value 0 1 Mode 70PCENT 100PCENT LFXOMODE 0x0 RW

LFXO Mode

Set this to configure the external source for the LFXO. The oscillator setting takes effect when 1 is written to LFXOEN in CMU_OSCENCMD. The oscillator setting is reset to default when 1 is written to LFXODIS in CMU_OSCENCMD.

Value 0 1 2 Mode XTAL BUFEXTCLK DIGEXTCLK Description 32.768 kHz crystal oscillator.

An AC coupled buffer is coupled in series with LFXTAL_N pin, suitable for external sinus wave (32.768 kHz).

Digital external clock on LFXTAL_N pin. Oscillator is effectively bypassed.

RW Description 70 %.

100 %.

HFXO Timeout

HFXOTIMEOUT 0x3 Configures the start-up delay for HFXO.

Value 0 1 2 3 Mode 8CYCLES 256CYCLES 1KCYCLES 16KCYCLES Description Timeout period of 8 cycles.

Timeout period of 256 cycles.

Timeout period of 1024 cycles.

Timeout period of 16384 cycles.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

HFXOGLITCHDETEN 0 RW

HFXO Glitch Detector Enable

This bit enables the glitch detector which is active as long as the start-up ripple-counter is counting. A detected glitch will reset the ripple-counter effectively increasing the start-up time. Once the ripple-counter has timed-out, glitches will not be detected.

HFXOBUFCUR 0x1 RW

HFXO Boost Buffer Current

This value has been set during calibration and should not be changed.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

HFXOBOOST 0x3 Used to adjust start-up boost current for HFXO.

RW

HFXO Start-up Boost Current

Value 0 1 2 3 Value 0 1 2 Mode 50PCENT 70PCENT 80PCENT 100PCENT HFXOMODE 0x0 RW

HFXO Mode

Set this to configure the external source for the HFXO. The oscillator setting takes effect when 1 is written to HFXOEN in CMU_OSCENCMD. The oscillator setting is reset to default when 1 is written to HFXODIS in CMU_OSCENCMD.

Mode XTAL BUFEXTCLK DIGEXTCLK Description 50 %.

70 %.

80 %.

100 % (default).

Description 4-25 MHz crystal oscillator.

An AC coupled buffer is coupled in series with HFXTAL_N, suitable for external sine wave (4-25 MHz). The sine wave should have a minimum of 200 mV peak to peak.

Digital external clock on HFXTAL_N pin. Oscillator is effectively bypassed.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

108

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

11.5.2 CMU_HFCORECLKDIV - High Frequency Core Clock Division Register Bit Position Offset

0x004

Reset Access Name Bit

31:9

8

7:4

3:0

Name Reset Access Description

Reserved

HFCORECLKLEDIV

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Additional division factor for HFCORECLKLE.

RW

Additional Division Factor For HFCORECLKLE

Value 0 1 4 5 6 7 8 9 Value 0 1 2 3 Mode DIV2 DIV4 Description HFCORECLK divided by 2.

HFCORECLK divided by 4.

Reserved

HFCORECLKDIV

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 Specifies the clock divider for HFCORECLK.

RW

HFCORECLK Divider

Mode HFCLK HFCLK2 HFCLK4 HFCLK8 HFCLK16 HFCLK32 HFCLK64 HFCLK128 HFCLK256 HFCLK512 Description HFCORECLK = HFCLK.

HFCORECLK = HFCLK/2.

HFCORECLK = HFCLK/4.

HFCORECLK = HFCLK/8.

HFCORECLK = HFCLK/16.

HFCORECLK = HFCLK/32.

HFCORECLK = HFCLK/64.

HFCORECLK = HFCLK/128.

HFCORECLK = HFCLK/256.

HFCORECLK = HFCLK/512.

11.5.3 CMU_HFPERCLKDIV - High Frequency Peripheral Clock Division Register Bit Position Offset

0x008

Reset Access Name Bit

31:9

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

109

www.silabs.com

Bit

8

7:4

3:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

HFPERCLKEN 1 Set to enable the HFPERCLK.

Reserved

RW

HFPERCLK Enable

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

HFPERCLKDIV 0x0 Specifies the clock divider for the HFPERCLK.

RW

HFPERCLK Divider

2 3 4 5 6 7 8 9 Value 0 1 Mode HFCLK HFCLK2 HFCLK4 HFCLK8 HFCLK16 HFCLK32 HFCLK64 HFCLK128 HFCLK256 HFCLK512 Description HFPERCLK = HFCLK.

HFPERCLK = HFCLK/2.

HFPERCLK = HFCLK/4.

HFPERCLK = HFCLK/8.

HFPERCLK = HFCLK/16.

HFPERCLK = HFCLK/32.

HFPERCLK = HFCLK/64.

HFPERCLK = HFCLK/128.

HFPERCLK = HFCLK/256.

HFPERCLK = HFCLK/512.

11.5.4 CMU_HFRCOCTRL - HFRCO Control Register Bit Position Offset

0x00C

Reset Access Name Bit

31:17

16:12

11

10:8 7:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SUDELAY Always write this field to 0.

0x00

Reserved

RW

HFRCO Start-up Delay

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BAND 0x3 RW

HFRCO Band Select

Write this field to set the frequency band in which the HFRCO is to operate. When changing this setting there will be no glitches on the HFRCO output, hence it is safe to change this setting even while the system is running on the HFRCO. To ensure an accurate frequency, the HFTUNING value should also be written when changing the frequency band. The calibrated tuning value for the different bands can be read from the Device Information page.

Value 0 1 2 3 4 Mode 1MHZ 7MHZ 11MHZ 14MHZ 21MHZ Description 1 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

7 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

11 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

14 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

21 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

TUNING 0x80 RW

HFRCO Tuning Value

Writing this field adjusts the HFRCO frequency (the higher value, the higher frequency). This field is updated with the production calibrated value for the 14 MHz band during reset, and the reset value might therefore vary between devices.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

110

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

11.5.5 CMU_LFRCOCTRL - LFRCO Control Register Offset

0x010

Reset Access Bit Position Name Bit

31:7

6:0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TUNING 0x40 RW

LFRCO Tuning Value

Writing this field adjusts the LFRCO frequency (the higher value, the higher frequency). This field is updated with the production calibrated value during reset, and the reset value might therefore vary between devices.

11.5.6 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register Bit Position Offset

0x014

Reset Access Name Bit

31:11

10:8 7:0

Name

Reserved

BAND 0x0 RW

AUXHFRCO Band Select

Write this field to set the frequency band in which the AUXHFRCO is to operate. When changing this setting there will be no glitches on the AUXHFRCO output, hence it is safe to change this setting even while the system is using the AUXHFRCO. To ensure an accurate frequency, the AUXTUNING value should also be written when changing the frequency band. The calibrated tuning value for the different bands can be read from the Device Information page. Flash erase and write use this clock. If it is changed to another value than the default, MSC_TIMEBASE must also be configured to ensure correct flash erase and write operation.

Value 0 1 2 3 7 Mode 14MHZ 11MHZ 7MHZ 1MHZ 21MHZ

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

Description 14 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

11 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

7 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

1 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

21 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

TUNING 0x80 RW

AUXHFRCO Tuning Value

Writing this field adjusts the AUXHFRCO frequency (the higher value, the higher frequency).This field is updated with the production calibrated value during reset, and the reset value might therefore vary between devices.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

111

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

11.5.7 CMU_CALCTRL - Calibration Control Register Offset

0x018

Reset Access Bit Position Name Bit

31:7

6 5:3 2:0

Name Reset Access Description

Reserved

CONT

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Set this bit to enable continuous calibration.

RW DOWNSEL 0x0 RW Selects clock source for the calibration down-counter.

Continuous Calibration Calibration Down-counter Select

3 4 5 6 Value 0 1 2 Mode HFCLK HFXO LFXO HFRCO LFRCO AUXHFRCO USHFRCO Description Select HFCLK for down-counter.

Select HFXO for down-counter.

Select LFXO for down-counter.

Select HFRCO for down-counter.

Select LFRCO for down-counter.

Select AUXHFRCO for down-counter.

Select USHFRCO for down-counter.

Calibration Up-counter Select

UPSEL 0x0 RW Selects clock source for the calibration up-counter.

3 4 5 Value 0 1 2 Mode HFXO LFXO HFRCO LFRCO AUXHFRCO USHFRCO Description Select HFXO as up-counter.

Select LFXO as up-counter.

Select HFRCO as up-counter.

Select LFRCO as up-counter.

Select AUXHFRCO as up-counter.

Select USHFRCO as up-counter.

11.5.8 CMU_CALCNT - Calibration Counter Register Offset

0x01C

Bit Position Reset Access Name Bit

31:20

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

112

www.silabs.com

Bit

19:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

CALCNT 0x00000 RWH

Calibration Counter

Write top value before calibration. Read calibration result from this register when Calibration Ready flag has been set.

11.5.9 CMU_OSCENCMD - Oscillator Enable/Disable Command Register Bit Position Offset

0x020

Reset Access Name Bit

31:12

11 10 9 8 7 6 5 4 3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USHFRCODIS 0 W1

USHFRCO Disable

Disables the USHFRCO. USHFRCOEN has higher priority if written simultaneously.

USHFRCOEN Enables the USHFRCO.

0 W1

USHFRCO Enable

LFXODIS 0 W1

LFXO Disable

Disables the LFXO. LFXOEN has higher priority if written simultaneously.

LFXOEN Enables the LFXO.

0 W1

LFXO Enable

LFRCODIS 0 W1

LFRCO Disable

Disables the LFRCO. LFRCOEN has higher priority if written simultaneously.

LFRCOEN Enables the LFRCO.

0 W1

LFRCO Enable

AUXHFRCODIS 0 W1

AUXHFRCO Disable

Disables the AUXHFRCO. AUXHFRCOEN has higher priority if written simultaneously. WARNING: Do not disable this clock during a flash erase/write operation.

AUXHFRCOEN Enables the AUXHFRCO.

HFXOEN Enables the HFXO.

0 0 W1 HFXODIS 0 W1

HFXO Disable

Disables the HFXO. HFXOEN has higher priority if written simultaneously. WARNING: Do not disable the HFRXO if this oscillator is selected as the source for HFCLK.

W1

AUXHFRCO Enable HFXO Enable

HFRCODIS 0 W1

HFRCO Disable

Disables the HFRCO. HFRCOEN has higher priority if written simultaneously. WARNING: Do not disable the HFRCO if this oscillator is selected as the source for HFCLK.

HFRCOEN Enables the HFRCO.

0 W1

HFRCO Enable

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

113

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

11.5.10 CMU_CMD - Command Register Offset

0x024

Reset Access Bit Position Name

4 3 2:0

Bit

31:8

7:5

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USBCCLKSEL 0x0 W1

USB Core Clock Select

Selects the clock for HFCORECLK USBC . The status register is updated when the clock switch has taken effect.

Value 2 3 4 Mode LFXO LFRCO USHFRCO Description Select LFXO as HFCORECLK USBC .

Select LFRCO as HFCORECLK USBC .

Select USHFRCO as HFCORECLK USBC .

CALSTOP 0 Stops the calibration counters.

W1

Calibration Stop

CALSTART 0 W1

Calibration Start

Starts the calibration, effectively loading the CMU_CALCNT into the down-counter and start decrementing.

HFCLKSEL 0x0 W1

HFCLK Select

Selects the clock source for HFCLK. Note that selecting an oscillator that is disabled will cause the system clock to stop. Check the status register and confirm that oscillator is ready before switching.

Value 1 2 3 4 5 Mode HFRCO HFXO LFRCO LFXO USHFRCODIV2 Description Select HFRCO as HFCLK.

Select HFXO as HFCLK.

Select LFRCO as HFCLK.

Select LFXO as HFCLK.

Select USHFRCO divided by two as HFCLK.

11.5.11 CMU_LFCLKSEL - Low Frequency Clock Select Register Offset

0x028

Reset Access Bit Position Name Bit

31:21

20

Name Reset Access Description

Reserved

LFBE

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 This bit redefines the meaning of the LFB field.

RW

Clock Select for LFB Extended

Value 0 Mode DISABLED Description LFBCLK is disabled (when LFB = DISABLED).

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

114

www.silabs.com

Bit

19:17

16

15:6

5:4 3:2 1:0

Preliminary

...the world's most energy friendly microcontrollers

Name

Value 1 Value 0 1 Mode ULFRCO Mode DISABLED ULFRCO

Reset Access Description

Description ULFRCO selected as LFBCLK (when LFB = DISABLED).

Reserved

LFAE

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 This bit redefines the meaning of the LFA field.

RW

Clock Select for LFA Extended

Description LFACLK is disabled (when LFA = DISABLED).

ULFRCO selected as LFACLK (when LFA = DISABLED).

Reserved

LFC

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x1 Selects the clock source for LFCCLK.

RW

Clock Select for LFC

Value 0 1 2 Mode DISABLED LFRCO LFXO Description LFCCLK clock disabled.

LFRCO selected as LFCCLK clock LFXO selected as LFCCLK clock LFB 0x1 Selects the clock source for LFBCLK.

LFB 0 1 2 3 LFBE 0 0 0 0 0 1 LFA 0x1 Selects the clock source for LFACLK.

LFA 0 1 2 3 LFAE 0 0 0 0 0 1 RW RW

Clock Select for LFB

Mode Disabled LFRCO LFXO HFCORECLKLEDIV2 ULFRCO

Clock Select for LFA

Mode Disabled LFRCO LFXO HFCORECLKLEDIV2 ULFRCO Description LFBCLK is disabled LFRCO selected as LFBCLK LFXO selected as LFBCLK HFCORECLK LE divided by two is selected as LFBCLK ULFRCO selected as LFBCLK Description LFACLK is disabled LFRCO selected as LFACLK LFXO selected as LFACLK HFCORECLK LE divided by two is selected as LFACLK ULFRCO selected as LFACLK

11.5.12 CMU_STATUS - Status Register Offset

0x02C

Reset Access Bit Position Name Bit

31:27

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

115

www.silabs.com

Bit

26

25:24

23 22 21 20

19

18 17 16

15

14 13 12 11 10 9 8 7 6 5 4 3 2

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

USHFRCODIV2SEL 0 R USHFRCO divided by two is selected a HFCLK clock source.

USHFRCODIV2 Selected

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USHFRCOSUSPEND 0 R

USHFRCO is suspended

Set when the USHFRCO is suspended, either by CMU or USB.

USHFRCO Ready

USHFRCORDY 0 R USHFRCO is enabled and start-up time has exceeded.

USHFRCOENS USHFRCO is enabled.

0 R

USHFRCO Enable Status

USBCHFCLKSYNC 0 Set when USBC is synchronous to HFCLK.

R

USBC is synchronous to HFCLK

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USBCUSHFRCOSEL 0 R USHFRCO is selected (and active) as HFCORECLK USBC .

USBCLFRCOSEL 0 R

USBC USHFRCO Selected USBC LFRCO Selected

LFRCO is selected (and active) as HFCORECLK USBC .

USBCLFXOSEL 0 R

USBC LFXO Selected

LFXO is selected (and active) as HFCORECLK USBC .

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

R

Calibration Busy

CALBSY Calibration is on-going.

0 LFXOSEL 0 LFXO is selected as HFCLK clock source.

R

LFXO Selected LFRCO Selected

LFRCOSEL 0 LFRCO is selected as HFCLK clock source.

HFXOSEL 0 HFXO is selected as HFCLK clock source.

HFRCOSEL 1 HFRCO is selected as HFCLK clock source.

R R R LFXORDY 0 R LFXO is enabled and start-up time has exceeded.

LFXOENS LFXO is enabled.

0 R LFRCORDY 0 R LFRCO is enabled and start-up time has exceeded.

LFRCOENS LFRCO is enabled.

0 R AUXHFRCORDY 0 R AUXHFRCO is enabled and start-up time has exceeded.

AUXHFRCOENS AUXHFRCO is enabled.

0 R HFXORDY 0 R HFXO is enabled and start-up time has exceeded.

HFXOENS HFXO is enabled.

0 R

HFXO Selected HFRCO Selected LFXO Ready LFXO Enable Status LFRCO Ready LFRCO Enable Status AUXHFRCO Ready AUXHFRCO Enable Status HFXO Ready HFXO Enable Status

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

116

www.silabs.com

Bit

1 0

Preliminary Name Reset Access

HFRCORDY 1 R HFRCO is enabled and start-up time has exceeded.

HFRCOENS HFRCO is enabled.

1 R

...the world's most energy friendly microcontrollers

Description HFRCO Ready HFRCO Enable Status 11.5.13 CMU_IF - Interrupt Flag Register Bit Position Offset

0x030

Reset Access Name

7

6

Bit

31:10

9 8 5 4 3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USBCHFOSCSEL 0 R Set when USBC is coming from a High Frequency Oscillator.

USBC HF-oscillator Selected Interrupt Flag

USHFRCORDY 0 R Set when USHFRCO is ready (start-up time exceeded).

Reserved

USHFRCO Ready Interrupt Flag

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

Calibration Overflow Interrupt Flag

CALOF 0 Set when calibration overflow has occurred CALRDY 0 Set when calibration is completed.

R R AUXHFRCORDY 0 R Set when AUXHFRCO is ready (start-up time exceeded).

LFXORDY 0 R Set when LFXO is ready (start-up time exceeded).

Calibration Ready Interrupt Flag AUXHFRCO Ready Interrupt Flag LFXO Ready Interrupt Flag LFRCO Ready Interrupt Flag

LFRCORDY 0 R Set when LFRCO is ready (start-up time exceeded).

HFXORDY 0 R Set when HFXO is ready (start-up time exceeded).

HFRCORDY 1 R Set when HFRCO is ready (start-up time exceeded).

HFXO Ready Interrupt Flag HFRCO Ready Interrupt Flag

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

117

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

11.5.14 CMU_IFS - Interrupt Flag Set Register Offset

0x034

Reset Access Bit Position Name

7

6

Bit

31:10

9 8 5 4 3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USBCHFOSCSEL 0 W1

USBC HF-oscillator Selected Interrupt Flag Set

Write to 1 to set the USBC HF-oscillator Selected Interrupt Flag.

USHFRCORDY 0 W1 Write to 1 to set the USHFRCO Ready Interrupt Flag.

Reserved

USHFRCO Ready Interrupt Flag Set

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CALOF 0 W1 Write to 1 to set the Calibration Overflow Interrupt Flag.

Calibration Overflow Interrupt Flag Set

CALRDY 0 W1

Calibration Ready Interrupt Flag Set

Write to 1 to set the Calibration Ready(completed) Interrupt Flag.

AUXHFRCO Ready Interrupt Flag Set

AUXHFRCORDY 0 W1 Write to 1 to set the AUXHFRCO Ready Interrupt Flag.

LFXORDY 0 Write to 1 to set the LFXO Ready Interrupt Flag.

W1 LFRCORDY 0 W1 Write to 1 to set the LFRCO Ready Interrupt Flag.

HFXORDY 0 W1 Write to 1 to set the HFXO Ready Interrupt Flag.

HFRCORDY 0 W1 Write to 1 to set the HFRCO Ready Interrupt Flag.

LFXO Ready Interrupt Flag Set LFRCO Ready Interrupt Flag Set HFXO Ready Interrupt Flag Set HFRCO Ready Interrupt Flag Set 11.5.15 CMU_IFC - Interrupt Flag Clear Register Offset

0x038

Reset Access Bit Position Name Bit

31:10

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

118

www.silabs.com

7

6 5 1 0 4 3 2

Bit

9 8

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

USBCHFOSCSEL 0 W1

USBC HF-oscillator Selected Interrupt Flag Clear

Write to 1 to clear the USBC HF-oscillator Selected Interrupt Flag.

USHFRCORDY 0 W1 Write to 1 to clear the USHFRCO Ready Interrupt Flag.

USHFRCO Ready Interrupt Flag Clear

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

Calibration Overflow Interrupt Flag Clear

CALOF 0 W1 Write to 1 to clear the Calibration Overflow Interrupt Flag.

CALRDY 0 W1 Write to 1 to clear the Calibration Ready Interrupt Flag.

AUXHFRCORDY 0 W1 Write to 1 to clear the AUXHFRCO Ready Interrupt Flag.

LFXORDY 0 W1 Write to 1 to clear the LFXO Ready Interrupt Flag.

LFRCORDY 0 W1 Write to 1 to clear the LFRCO Ready Interrupt Flag.

HFXORDY 0 W1 Write to 1 to clear the HFXO Ready Interrupt Flag.

HFRCORDY 0 W1 Write to 1 to clear the HFRCO Ready Interrupt Flag.

Calibration Ready Interrupt Flag Clear AUXHFRCO Ready Interrupt Flag Clear LFXO Ready Interrupt Flag Clear LFRCO Ready Interrupt Flag Clear HFXO Ready Interrupt Flag Clear HFRCO Ready Interrupt Flag Clear 11.5.16 CMU_IEN - Interrupt Enable Register Bit Position Offset

0x03C

Reset Access Name

7

6

Bit

31:10

9 8 5 4

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USBCHFOSCSEL 0 RW Set to enable the USBC HF-oscillator Selected Interrupt Flag.

USBC HF-oscillator Selected Interrupt Flag Clear

USHFRCORDY 0 Set to enable the USHFRCO Ready Interrupt.

RW

Reserved

USHFRCO Ready Interrupt Enable

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

Calibration Overflow Interrupt Enable

CALOF 0 Set to enable the Calibration Overflow Interrupt.

RW CALRDY 0 Set to enable the Calibration Ready Interrupt.

RW AUXHFRCORDY 0 Set to enable the AUXHFRCO Ready Interrupt.

RW

Calibration Ready Interrupt Enable AUXHFRCO Ready Interrupt Enable

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

119

www.silabs.com

1 0

Bit

3 2

Preliminary Name Reset

LFXORDY 0 Set to enable the LFXO Ready Interrupt.

LFRCORDY 0 Set to enable the LFRCO Ready Interrupt.

HFXORDY 0 Set to enable the HFXO Ready Interrupt.

HFRCORDY 0 Set to enable the HFRCO Ready Interrupt.

Access

RW RW RW RW

...the world's most energy friendly microcontrollers

Description LFXO Ready Interrupt Enable LFRCO Ready Interrupt Enable HFXO Ready Interrupt Enable HFRCO Ready Interrupt Enable 11.5.17 CMU_HFCORECLKEN0 - High Frequency Core Clock Enable Register 0 Bit Position Offset

0x040

Reset Access Name

2 1 0

Bit

31:5

4 3

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USB 0 Set to enable the clock for USB.

USBC 0 Set to enable the clock for USBC.

RW RW

Universal Serial Bus Interface Clock Enable Universal Serial Bus Interface Core Clock Enable

LE 0 RW

Low Energy Peripheral Interface Clock Enable

Set to enable the clock for LE. Interface used for bus access to Low Energy peripherals.

DMA 0 Set to enable the clock for DMA.

RW

Direct Memory Access Controller Clock Enable

AES 0 Set to enable the clock for AES.

RW

Advanced Encryption Standard Accelerator Clock Enable 11.5.18 CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0 Bit Position Offset

0x044

Reset Access Name

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

120

www.silabs.com

Bit

31:12

11 10 9 8 7 6 5 4 3 2 1 0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Reserved

I2C0

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Set to enable the clock for I2C0.

ADC0 0 Set to enable the clock for ADC0.

VCMP 0 Set to enable the clock for VCMP.

GPIO 0 Set to enable the clock for GPIO.

IDAC0 0 Set to enable the clock for IDAC0.

PRS 0 Set to enable the clock for PRS.

ACMP0 0 Set to enable the clock for ACMP0.

USART1 0 RW RW RW RW RW RW RW RW

I2C 0 Clock Enable Analog to Digital Converter 0 Clock Enable Voltage Comparator Clock Enable General purpose Input/Output Clock Enable Current Digital to Analog Converter 0 Clock Enable Peripheral Reflex System Clock Enable Analog Comparator 0 Clock Enable Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable

Set to enable the clock for USART1.

USART0 0 RW

Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable

Set to enable the clock for USART0.

TIMER2 0 Set to enable the clock for TIMER2.

TIMER1 0 Set to enable the clock for TIMER1.

TIMER0 0 Set to enable the clock for TIMER0.

RW RW RW

Timer 2 Clock Enable Timer 1 Clock Enable Timer 0 Clock Enable 11.5.19 CMU_SYNCBUSY - Synchronization Busy Register Bit Position Offset

0x050

Reset Access Name Bit

31:9

8

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LFCCLKEN0 0 R

Low Frequency C Clock Enable 0 Busy

Used to check the synchronization status of CMU_LFCCLKEN0.

Value 0 1 Description CMU_LFCCLKEN0 is ready for update.

CMU_LFCCLKEN0 is busy synchronizing new value.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

121

www.silabs.com

5

4

1

0

3

2

Bit

7

6

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LFBPRESC0 0 R

Low Frequency B Prescaler 0 Busy

Used to check the synchronization status of CMU_LFBPRESC0.

Value 1 Value 0 1 Description CMU_LFBPRESC0 is busy synchronizing new value.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LFBCLKEN0 0 R

Low Frequency B Clock Enable 0 Busy

Used to check the synchronization status of CMU_LFBCLKEN0.

Description CMU_LFBCLKEN0 is ready for update.

CMU_LFBCLKEN0 is busy synchronizing new value.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LFAPRESC0 0 R

Low Frequency A Prescaler 0 Busy

Used to check the synchronization status of CMU_LFAPRESC0.

Value 0 1 Description CMU_LFAPRESC0 is ready for update.

CMU_LFAPRESC0 is busy synchronizing new value.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LFACLKEN0 0 R

Low Frequency A Clock Enable 0 Busy

Used to check the synchronization status of CMU_LFACLKEN0.

Value 0 1 Description CMU_LFACLKEN0 is ready for update.

CMU_LFACLKEN0 is busy synchronizing new value.

11.5.20 CMU_FREEZE - Freeze Register Bit Position Offset

0x054

Reset Access Name Bit

31:1

0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

REGFREEZE 0 RW

Register Update Freeze

When set, the update of the Low Frequency clock control registers is postponed until this bit is cleared. Use this bit to update several registers simultaneously.

Value 0 1 Mode UPDATE FREEZE Description Each write access to a Low Frequency clock control register is updated into the Low Frequency domain as soon as possible.

The LE Clock Control registers are not updated with the new written value.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

122

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

11.5.21 CMU_LFACLKEN0 - Low Frequency A Clock Enable Register 0 (Async Reg) Bit Position Offset

0x058

Reset Access Name Bit

31:1

0

Name Reset Access Description

Reserved

RTC

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Set to enable the clock for RTC.

RW

Real-Time Counter Clock Enable 11.5.22 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg) Bit Position Offset

0x060

Reset Access Name Bit

31:1

0

Name Reset Access Description

Reserved

LEUART0

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Set to enable the clock for LEUART0.

RW

Low Energy UART 0 Clock Enable 11.5.23 CMU_LFCCLKEN0 - Low Frequency C Clock Enable Register 0 (Async Reg) Bit Position Offset

0x064

Reset Access Name Bit

31:1

0

Name

Reserved

USBLE

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 RW

Universal Serial Bus Low Energy Clock Clock Enable

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

123

www.silabs.com

Bit Preliminary Name Reset

Set to enable the clock for USBLE.

Access

...the world's most energy friendly microcontrollers

Description 11.5.24 CMU_LFAPRESC0 - Low Frequency A Prescaler Register 0 (Async Reg) Bit Position Offset

0x068

Reset Access Name Bit

31:4

3:0

Name Reset Access Description

Reserved

RTC

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 Configure Real-Time Counter prescaler RW

Real-Time Counter Prescaler

10 11 12 13 14 15 4 5 6 7 8 9 Value 0 1 2 3 Mode DIV1 DIV2 DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 DIV256 DIV512 DIV1024 DIV2048 DIV4096 DIV8192 DIV16384 DIV32768 Description LFACLK RTC = LFACLK LFACLK RTC = LFACLK/2 LFACLK RTC = LFACLK/4 LFACLK RTC = LFACLK/8 LFACLK RTC = LFACLK/16 LFACLK RTC = LFACLK/32 LFACLK RTC = LFACLK/64 LFACLK RTC = LFACLK/128 LFACLK RTC = LFACLK/256 LFACLK RTC = LFACLK/512 LFACLK RTC = LFACLK/1024 LFACLK RTC = LFACLK/2048 LFACLK RTC = LFACLK/4096 LFACLK RTC = LFACLK/8192 LFACLK RTC = LFACLK/16384 LFACLK RTC = LFACLK/32768

11.5.25 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg) Bit Position Offset

0x070

Reset Access Name Bit

31:2

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

124

www.silabs.com

Bit

1:0

Preliminary Name Reset

LEUART0 0x0 Configure Low Energy UART 0 prescaler Value 0 1 2 3 Mode DIV1 DIV2 DIV4 DIV8

Access

RW

...the world's most energy friendly microcontrollers

Description Low Energy UART 0 Prescaler

Description LFBCLK LEUART0 = LFBCLK LFBCLK LEUART0 = LFBCLK/2 LFBCLK LEUART0 = LFBCLK/4 LFBCLK LEUART0 = LFBCLK/8

11.5.26 CMU_PCNTCTRL - PCNT Control Register Offset

0x078

Reset Access Bit Position Name Bit

31:2

1 0

Name Reset Access Description

Reserved

PCNT0CLKSEL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 RW This bit controls which clock that is used for the PCNT.

PCNT0 Clock Select

Value 0 1 PCNT0CLKEN 0 This bit enables/disables the clock to the PCNT.

RW Value 0 1 Mode LFACLK PCNT0S0 Description PCNT0 is disabled.

PCNT0 is enabled.

Description LFACLK is clocking PCNT0.

External pin PCNT0_S0 is clocking PCNT0.

PCNT0 Clock Enable 11.5.27 CMU_ROUTE - I/O Routing Register Offset

0x080

Reset Access Bit Position Name Bit

31:5

4:2

Name

Reserved

LOCATION

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 RW

I/O Location

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

125

www.silabs.com

1 0

Bit Preliminary Access

...the world's most energy friendly microcontrollers

Description Name Reset

Decides the location of the CMU I/O pins.

Value 0 1 2 3 Mode LOC0 LOC1 LOC2 LOC3 CLKOUT1PEN 0 When set, the CLKOUT1 pin is enabled.

CLKOUT0PEN 0 When set, the CLKOUT0 pin is enabled.

RW Description Location 0 Location 1 Location 2 Location 3

CLKOUT1 Pin Enable

RW

CLKOUT0 Pin Enable 11.5.28 CMU_LOCK - Configuration Lock Register Offset

0x084

Bit Position Reset Access Name Bit

31:16

15:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LOCKKEY 0x0000 RW

Configuration Lock Key

Write any other value than the unlock code to lock CMU_CTRL, CMU_HFCORECLKDIV, CMU_HFPERCLKDIV, CMU_HFRCOCTRL, CMU_LFRCOCTRL, CMU_AUXHFRCOCTRL, CMU_OSCENCMD, CMU_CMD, CMU_LFCLKSEL, CMU_HFCORECLKEN0, CMU_HFPERCLKEN0, CMU_LFACLKEN0, CMU_LFBCLKEN0, CMU_LFAPRESC0, CMU_LFBPRESC0, CMU_USHFRCOCTRL, CMU_USHFRCOFTUNE and CMU_PCNTCTRL from editing. Write the unlock code to unlock. When reading the register, bit 0 is set when the lock is enabled.

Mode Read Operation UNLOCKED LOCKED Write Operation LOCK UNLOCK Value 0 1 0 0x580E Description CMU registers are unlocked.

CMU registers are locked.

Lock CMU registers.

Unlock CMU registers.

11.5.29 CMU_USBCRCTRL - USB Clock Recovery Control Offset

0x0D0

Reset Access Bit Position Name

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

126

www.silabs.com

Bit

31:2

1 0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LSMODE 0 RW

Low Speed Clock Recovery Mode

This bit must be set to 1 if clock recovery is used when operating as a Low Speed USB device.

EN 0 RW This bit enables and disables the USB clock recovery feature.

Clock Recovery Enable 11.5.30 CMU_USHFRCOCTRL - USHFRCO Control Offset

0x0D4

Reset Bit Position Access Name Bit

31:20

19:12

11:10

9 8

7

6:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TIMEOUT 0xFF RW

USHFRCO Timeout

Timeout value in HFCLK cycles for USHFRCO startup. The timeout needs to be at least 6 µs.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SUSPEND 0 Set this bit to suspend the USHFRCO.

RW

USHFRCO suspend

DITHEN 0 RW

USHFRCO dither enable

Setting this bit dithers the oscillator control value every four oscillator cycles. In effect this gives an average USHFRCO frequency between FINETUNING and FINETUNING+1.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TUNING 0x40 RW

USHFRCO frequency adjust

This field controls the output frequency of the USHFRCO in coarse steps. The reset value is factory calibrated to generate a USB oscillator frequency of 48 MHz. Notice that higher value gives lower frequency.

11.5.31 CMU_USHFRCOTUNE - USHFRCO Frequency Tune Offset

0x0D8

Reset Bit Position Access Name Bit

31:6

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

127

www.silabs.com

Bit

5:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

FINETUNING 0x20 RWH

Oscillator fine frequency adjust

This field controls the output frequency of the USHFRCO in fine steps. The reset value is factory calibrated to generate a USHFRCO frequency of 48 MHz. This register is modified by the clock recovery hardware to fine-tune the USHFRCO to meet the requirements for USB clock tolerance. Notice that higher value gives lower frequency

11.5.32 CMU_USHFRCOCONF - USHFRCO Configuration Offset

0x0DC

Reset Access Bit Position Name Bit

31:5

4

3

2:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USHFRCODIV2DIS 0 RW

USHFRCO divider for HFCLK disable

Set this bit to bypass the divider for USHFRCO to HFCLK. Must not be changed while USHFRCO is selected as HFCLK or the 48 MHz band is selected.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BAND 0x1 RW

USHFRCO Band Select

Write this field to set the frequency band in which the USHFRCO is to operate. Note that the switching of band on this oscillator is not glitch-free and it should be selected as neither USBC clock nor HFCLK when changing band.

Value 1 3 Mode 48MHZ 24MHZ Description 48 MHz band. NOTE: Also set the TUNING and FINETUNING value when changing band.

24 MHz band. NOTE: Also set the TUNING and FINETUNING value when changing band.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

128

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

12 WDOG - Watchdog Timer

0 1 2 3 4

Count er value Wat chdog clear Tim eout period Syst em reset Tim e

Quick Facts What?

The WDOG (Watchdog Timer) resets the system in case of a fault condition, and can be enabled in all energy modes as long as the low frequency clock source is available.

Why?

If a software failure or external event renders the MCU unresponsive, a Watchdog timeout will reset the system to a known, safe state.

How?

An enabled Watchdog Timer implements a configurable timeout period. If the CPU fails to re-start the Watchdog Timer before it times out, a full system reset will be triggered. The Watchdog consumes insignificant power, and allows the device to remain safely in low energy modes for up to 256 seconds at a time.

12.1 Introduction

The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a software failure.

12.2 Features

• Clock input from selectable oscillators • Internal 32.768 Hz RC oscillator • Internal 1 kHz RC oscillator • External 32.768 Hz XTAL oscillator • Configurable timeout period from 9 to 256k watchdog clock cycles • Individual selection to keep running or freeze when entering EM2 or EM3 • Selection to keep running or freeze when entering debug mode • Selection to block the CPU from entering Energy Mode 4 • Selection to block the CMU from disabling the selected watchdog clock

12.3 Functional Description

The watchdog is enabled by setting the EN bit in WDOG_CTRL. When enabled, the watchdog counts up to the period value configured through the PERSEL field in WDOG_CTRL. If the watchdog timer is not cleared to 0 (by writing a 1 to the CLEAR bit in WDOG_CMD) before the period is reached, the chip is reset. If a timely clear command is issued, the timer starts counting up from 0 again. The watchdog can optionally be locked by writing the LOCK bit in WDOG_CTRL. Once locked, it cannot be disabled or reconfigured by software.

The watchdog counter is reset when EN is reset.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

129

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

12.3.1 Clock Source

Three clock sources are available for use with the watchdog, through the CLKSEL field in WDOG_CTRL.

The corresponding clocks must be enabled in the CMU. The SWOSCBLOCK bit in WDOG_CTRL can be written to prevent accidental disabling of the selected clocks. Also, setting this bit will automatically start the selected oscillator source when the watchdog is enabled. The PERSEL field in WDOG_CTRL is used to divide the selected watchdog clock, and the timeout for the watchdog timer can be calculated like this:

WDOG Timeout Equation

T TIMEOUT = (2 3+PERSEL + 1)/f, (12.1) where f is the frequency of the selected clock.

It is recommended to clear the watchdog first, if PERSEL is changed while the watchdog is enabled.

To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to the module clock.

Note

Before changing the clock source for WDOG, the EN bit in WDOG_CTRL should be cleared. In addition to this, the WDOG_SYNCBUSY value should be zero.

12.3.2 Debug Functionality

The watchdog timer can either keep running or be frozen when the device is halted by a debugger. This configuration is done through the DEBUGRUN bit in WDOG_CTRL. When code execution is resumed, the watchdog will continue counting where it left off.

12.3.3 Energy Mode Handling

The watchdog timer can be configured to either keep on running or freeze when entering EM2 or EM3.

The configuration is done individually for each energy mode in the EM2RUN and EM3RUN bits in WDOG_CTRL. When the watchdog has been frozen and is re-entering an energy mode where it is running, the watchdog timer will continue counting where it left off. For the watchdog there is no difference between EM0 and EM1. The watchdog does not run in EM4, and if EM4BLOCK in WDOG_CTRL is set, the CPU is prevented from entering EM4.

Note

If the WDOG is clocked by the LFXO or LFRCO, writing the SWOSCBLOCK bit will effectively prevent the CPU from entering EM3. When running from the ULFRCO, writing the SWOSCBLOCK bit will prevent the CPU from entering EM4.

12.3.4 Register access

Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to the HFCORECLK, special considerations must be taken when accessing registers. Please refer to

Section 5.3 (p. 18) for a description on how to perform register accesses to Low Energy Peripherals.

note that clearing the EN bit in WDOG_CTRL will reset the WDOG module, which will halt any ongoing register synchronization.

Note

Never write to the WDOG registers when it is disabled, except to enable it by setting WDOG_CTRL_EN or when changing the clock source using WDOG_CTRL_CLKSEL.

Make sure that the enable is registered (i.e. WDOG_SYNCBUSY_CTRL goes low), before writing other registers.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

130

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

12.4 Register Map

The offset register address is relative to the registers base address.

Offset

0x000

0x004

0x008

Name

WDOG_CTRL

WDOG_CMD

WDOG_SYNCBUSY

Type

RW W1 R

Description

Control Register

Command Register

Synchronization Busy Register

12.5 Register Description 12.5.1 WDOG_CTRL - Control Register (Async Reg)

For more information about Asynchronous Registers please see Section 5.3 (p. 18) .

Offset

0x000

Reset Access Bit Position Name Bit

31:14

13:12 11:8

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CLKSEL 0x0 RW

Watchdog Clock Select

Selects the WDOG oscillator, i.e. the clock on which the watchdog will run.

Value 0 1 2 Mode ULFRCO LFRCO LFXO Description ULFRCO LFRCO LFXO RW

Watchdog Timeout Period Select

PERSEL 0xF Select watchdog timeout period.

10 11 12 13 14 15 4 5 6 7 8 9 Value 0 1 2 3 Description Timeout period of 9 watchdog clock cycles.

Timeout period of 17 watchdog clock cycles.

Timeout period of 33 watchdog clock cycles.

Timeout period of 65 watchdog clock cycles.

Timeout period of 129 watchdog clock cycles.

Timeout period of 257 watchdog clock cycles.

Timeout period of 513 watchdog clock cycles.

Timeout period of 1k watchdog clock cycles.

Timeout period of 2k watchdog clock cycles.

Timeout period of 4k watchdog clock cycles.

Timeout period of 8k watchdog clock cycles.

Timeout period of 16k watchdog clock cycles.

Timeout period of 32k watchdog clock cycles.

Timeout period of 64k watchdog clock cycles.

Timeout period of 128k watchdog clock cycles.

Timeout period of 256k watchdog clock cycles.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

131

www.silabs.com

Bit

7

6 5 4 3 2 1 0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Reserved

SWOSCBLOCK 0 RW

Software Oscillator Disable Block

Set to disallow disabling of the selected WDOG oscillator. Writing this bit to 1 will turn on the selected WDOG oscillator if it is not already running.

Value 0 1

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

Description Software is allowed to disable the selected WDOG oscillator. See CMU for detailed description. Note that also CMU registers are lockable.

Software is not allowed to disable the selected WDOG oscillator.

EM4BLOCK 0 Set to prevent the EMU from entering EM4.

Value 0 1 RW

Energy Mode 4 Block

Description EM4 can be entered. See EMU for detailed description.

EM4 cannot be entered.

LOCK 0 RW

Configuration lock

Set to lock the watchdog configuration. This bit can only be cleared by reset.

Value 0 1 EM3RUN Description Watchdog configuration can be changed.

Watchdog configuration cannot be changed.

0 Set to keep watchdog running in EM3.

RW

Energy Mode 3 Run Enable

Value 0 1 EM2RUN Description Watchdog timer is frozen in EM3.

Watchdog timer is running in EM3.

0 Set to keep watchdog running in EM2.

RW

Energy Mode 2 Run Enable

Value 0 1 Description Watchdog timer is frozen in EM2.

Watchdog timer is running in EM2.

DEBUGRUN 0 Set to keep watchdog running in debug mode.

RW Value 0 1

Debug Mode Run Enable

Description Watchdog timer is frozen in debug mode.

Watchdog timer is running in debug mode.

EN 0 Set to enabled watchdog timer.

RW

Watchdog Timer Enable 12.5.2 WDOG_CMD - Command Register (Async Reg)

For more information about Asynchronous Registers please see Section 5.3 (p. 18) .

Offset

0x004

Reset Access Bit Position Name

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

132

www.silabs.com

Bit

31:1

0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CLEAR 0 W1

Watchdog Timer Clear

Clear watchdog timer. The bit must be written 4 watchdog cycles before the timeout.

Value 0 1 Mode UNCHANGED CLEARED Description Watchdog timer is unchanged.

Watchdog timer is cleared to 0.

12.5.3 WDOG_SYNCBUSY - Synchronization Busy Register Offset

0x008

Reset Access Bit Position Name Bit

31:2

1 0

Name Reset Access Description

Reserved

CMD

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 R Set when the value written to CMD is being synchronized.

CTRL 0 R Set when the value written to CTRL is being synchronized.

CMD Register Busy CTRL Register Busy

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

133

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

13 PRS - Peripheral Reflex System

0 1 2 3 4

Tim er ADC DMA PRS Ch PRS Ch

Quick Facts What?

The PRS (Peripheral Reflex System) allows configurable, fast and autonomous communication between the peripherals.

Why?

Events and signals from one peripheral can be used as input signals or triggers by other peripherals and ensure timing-critical operation and reduced software overhead.

How?

Without CPU intervention the peripherals can send reflex signals (both pulses and level) to each other in single- or chained steps. The peripherals can be set up to perform actions based on the incoming reflex signals. This results in improved system performance and reduced energy consumption.

13.1 Introduction

The Peripheral Reflex System (PRS) system is a network which allows the different peripheral modules to communicate directly with each other without involving the CPU. Peripheral modules which send out reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which apply actions depending on the reflex signals received. The format for the reflex signals is not given, but edge triggers and other functionality can be applied by the PRS.

13.2 Features

• 4 configurable interconnect channels • Each channel can be connected to any producing peripheral • Consumers can choose which channel to listen to • Selectable edge detector (rising, falling and both edges) • Software controlled channel output • Configurable level • Triggered pulses

13.3 Functional Description

An overview of the PRS module is shown in Figure 13.1 (p. 135) . The PRS contains 4 interconnect

channels, and each of these can select between all the output reflex signals offered by the producers.

The consumers can then choose which PRS channel to listen to and perform actions based on the reflex signals routed through that channel. The reflex signals can be both pulse signals and level signals.

Synchronous PRS pulses are one HFPERCLK cycle long, and can either be sent out by a producer (e.g., ADC conversion complete) or be generated from the edge detector in the PRS channel. Level signals can have an arbitrary waveform (e.g., Timer PWM output).

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

134

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

13.3.1 Asynchronous Mode

Many reflex signals can operate in two modes, synchronous or asynchronous. A synchronous reflex is clocked on HFPERCLK, and can be used as an input to all reflex consumers, but since they require HFPERCLK, they will not work in EM2/EM3.

Asynchronous reflexes are not clocked on HFPERCLK, and can be used even in EM2/EM3. There is a limitation to reflexes operating in asynchronous mode though: they can only be used by a subset of

the reflex consumers, the ones marked with async support in Table 13.2 (p. 137) . Peripherals that

can produce asynchronous reflexes are marked with async support in Table 13.1 (p. 136) . To use

these reflexes asynchronously, set ASYNC in the CHCTRL register for the PRS channel selecting the reflex signal.

Note

If a peripheral channel with ASYNC set is used in a consumer not supporting asynchronous reflexes, the behaviour is undefined.

13.3.2 Channel Functions

Different functions can be applied to a reflex signal within the PRS. Each channel includes an edge detector to enable generation of pulse signals from level signals. It is also possible to generate output reflex signals by configuring the SWPULSE and SWLEVEL bits. SWLEVEL is a programmable level for each channel and holds the value it is programmed to. The SWPULSE will give out a one-cycle high pulse if it is written to 1, otherwise a 0 is asserted. The SWLEVEL and SWPULSE signals are then XOR'ed with the selected input from the producers to form the output signal sent to the consumers listening to the channel.

Note

The edge detector controlled by EDSEL should only be used when working with synchronous reflexes, i.e., ASYNC in CHCTRL is cleared.

Figure 13.1. PRS Overview

SIGSEL[2:0] SOURCESEL[5:0] ASYNC[n] EDSEL[1:0] SWPULSE[n] SWLEVEL[n] APB bus Signals from producer peripherals Reg Signals t o consum er peripherals

13.3.3 Producers

Each PRS channel can choose between signals from several producers, which is configured in SOURCESEL in PRS_CHx_CTRL. Each of these producers outputs one or more signals which can be selected by setting the SIGSEL field in PRS_CHx_CTRL. Setting the SOURCESEL bits to 0 (Off) leads to a constant 0 output from the input mux. An overview of the available producers is given in

Table 13.1 (p. 136) .

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

135

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Table 13.1. Reflex Producers

Module

ACMP ADC GPIO RTC TIMER LETIMER USART VCMP USB

Reflex Output

Comparator Output Single Conversion Done Scan Conversion Done Pin 0 Input Pin 1 Input Pin 2 Input Pin 3 Input Pin 4 Input Pin 5 Input Pin 6 Input Pin 7 Input Pin 8 Input Pin 9 Input Pin 10 Input Pin 11 Input Pin 12 Input Pin 13 Input Pin 14 Input Pin 15 Input Overflow Compare Match 0 Compare Match 1 Underflow Overflow CC0 Output CC1 Output CC2 Output CH0 CH1 TX Complete RX Data Received IrDA Decoder Output Comparator Output Start of Frame Level Level Level Level Level Level Level Level

Output Format

Level Pulse Pulse Level Level Level Level Level Level Level Level Pulse Pulse Pulse Pulse Pulse Level Level Level Level Level Pulse Pulse Level Level

Async Support

Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

136

www.silabs.com

Module Preliminary Reflex Output

Start of Fram Sent/ Received

...the world's most energy friendly microcontrollers

Output Format Async Support

Yes

13.3.4 Consumers

Consumer peripherals (listed in Table 13.2 (p. 137) ) can be set to listen to a PRS channel and perform

an action based on the signal received on that channel. Most consumers expect pulse input, while some can handle level inputs as well.

Table 13.2. Reflex Consumers

Module

ADC IDAC TIMER USART LEUART PCNT

Reflex Input

Single Mode Trigger Scan Mode Trigger IDAC Enable CC0 Input CC1 Input CC2 Input DTI Fault Source 0 (TIMER0 only) DTI Fault Source 1 (TIMER0 only) DTI Input (TIMER0 only) TX/RX Enable IrDA Encoder Input (USART0 only) RX Input RX Input S0 input S1 input

Input Format

Pulse Pulse Level Pulse/Level Pulse/Level Pulse/Level Pulse Pulse Pulse/Level Pulse Pulse Pulse/Level Pulse/Level Level Level

Async Support

Yes Yes Yes Yes Yes

Note

It is possible to output prs channel 0 - channel 3 onto the GPIO by setting CH0PEN, CH1PEN, CH2PEN, or CH3PEN in the PRS_ROUTE register.

13.3.5 Example

The example below (illustrated in Figure 13.2 (p. 138) ) shows how to set up ADC0 to start single

conversions every time TIMER0 overflows (one HFPERCLK cycle high pulse), using PRS channel 5: • Set SOURCESEL in PRS_CH5_CTRL to 0b011100 to select TIMER0 as input to PRS channel 5.

• Set SIGSEL in PRS_CH5_CTRL to 0b001 to select the overflow signal (from TIMER0).

• Configure ADC0 with the desired conversion set-up.

• Set SINGLEPRSEN in ADC0_SINGLECTRL to 1 to enable single conversions to be started by a high PRS input signal.

• Set SINGLEPRSSEL in ADC0_SINGLECTRL to 0x5 to select PRS channel 5 as input to start the single conversion.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

137

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• Start TIMER0 with the desired TOP value, an overflow PRS signal is output automatically on overflow.

Note that the ADC results needs to be fetched either by the CPU or DMA.

Figure 13.2. TIMER0 overflow starting ADC0 single conversions through PRS channel 5.

TIMER0 Overflow ADC0 St art single conv.

PRS ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

138

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

13.4 Register Map

The offset register address is relative to the registers base address.

Offset

0x000

0x004 0x008

0x010 0x014 0x018 0x01C 0x020 0x024

0x040

Name

PRS_SWPULSE

PRS_SWLEVEL PRS_ROUTE

PRS_CH0_CTRL PRS_CH1_CTRL PRS_CH2_CTRL PRS_CH3_CTRL PRS_CH4_CTRL PRS_CH5_CTRL

PRS_TRACECTRL

Type

W1 RW RW RW RW RW RW RW RW RW

Description

Software Pulse Register

Software Level Register I/O Routing Register

Channel Control Register Channel Control Register Channel Control Register Channel Control Register Channel Control Register Channel Control Register

MTB Trace Control Register

13.5 Register Description 13.5.1 PRS_SWPULSE - Software Pulse Register Offset

0x000

Reset Access Bit Position Name

3 2 1 0

Bit

31:6

5 4

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH5PULSE See bit 0.

CH4PULSE See bit 0.

CH3PULSE See bit 0.

CH2PULSE See bit 0.

CH1PULSE See bit 0.

0 0 0 0 0 W1 W1 W1 W1 W1

Channel 5 Pulse Generation Channel 4 Pulse Generation Channel 3 Pulse Generation Channel 2 Pulse Generation Channel 1 Pulse Generation

CH0PULSE 0 W1

Channel 0 Pulse Generation

Write to 1 to generate one HFPERCLK cycle high pulse. This pulse is XOR'ed with the corresponding bit in the SWLEVEL register and the selected PRS input signal to generate the channel output.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

139

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

13.5.2 PRS_SWLEVEL - Software Level Register Offset Bit Position

0x004

Reset Access Name

3 2 1 0

Bit

31:6

5 4

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH5LEVEL See bit 0.

CH4LEVEL See bit 0.

CH3LEVEL See bit 0.

0 0 0 RW RW RW

Channel 5 Software Level Channel 4 Software Level Channel 3 Software Level

CH2LEVEL See bit 0.

CH1LEVEL See bit 0.

0 0 RW RW

Channel 2 Software Level Channel 1 Software Level

CH0LEVEL 0 RW

Channel 0 Software Level

The value in this register is XOR'ed with the corresponding bit in the SWPULSE register and the selected PRS input signal to generate the channel output.

13.5.3 PRS_ROUTE - I/O Routing Register Offset

0x008

Reset Access Bit Position Name Bit

31:11

10:8

7:4

3

Name Reset Access Description

Reserved

LOCATION

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 Decides the location of the PRS I/O pins.

RW

I/O Location

Value 0 1 2 3 Mode LOC0 LOC1 LOC2 LOC3 Description Location 0 Location 1 Location 2 Location 3

Reserved

CH3PEN

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 RW When set, GPIO output from PRS channel 3 is enabled

CH3 Pin Enable

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

140

www.silabs.com

Bit

2 1 0

Preliminary Name Reset Access

CH2PEN 0 RW When set, GPIO output from PRS channel 2 is enabled CH1PEN 0 RW When set, GPIO output from PRS channel 1 is enabled CH0PEN 0 RW When set, GPIO output from PRS channel 0 is enabled

...the world's most energy friendly microcontrollers

Description CH2 Pin Enable CH1 Pin Enable CH0 Pin Enable 13.5.4 PRS_CHx_CTRL - Channel Control Register Offset

0x010

Reset Access Bit Position Name Bit

31:29

28

27:26

25:24

23:22

21:16

Name

Reserved

Value 0 1 2 3 Mode OFF POSEDGE NEGEDGE

Reset

BOTHEDGES

Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

ASYNC 0 RW Set to disable synchronization of this reflex signal

Reserved

Asynchronous reflex

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

EDSEL Select edge detection.

0x0 RW

Edge Detect Select

Description Signal is left as it is A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

Reserved

SOURCESEL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x00 Select input source to PRS channel.

RW

Source Select

Value 0b000000 0b000001 0b000010 0b001000 0b010000 0b010001 0b011100 0b011101 0b011110 0b100100 0b101000 0b110000 0b110001 Mode NONE VCMP ACMP0 ADC0 USART0 USART1 TIMER0 TIMER1 TIMER2 USB RTC GPIOL GPIOH Description No source selected Voltage Comparator Analog Comparator 0 Analog to Digital Converter 0 Universal Synchronous/Asynchronous Receiver/Transmitter 0 Universal Synchronous/Asynchronous Receiver/Transmitter 1 Timer 0 Timer 1 Timer 2 Universal Serial Bus Interface Real-Time Counter General purpose Input/Output General purpose Input/Output 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

141

www.silabs.com

Bit

15:3

2:0

Preliminary

...the world's most energy friendly microcontrollers

Name

Value 0b110110 Mode PCNT0

Reset Access

Value SOURCESEL = 0b000000 (NONE) 0bxxx SOURCESEL = 0b000001 (VCMP) Mode OFF 0b000 SOURCESEL = 0b000010 (ACMP0) VCMPOUT 0b000 ACMP0OUT SOURCESEL = 0b001000 (ADC0) 0b000 0b001 SOURCESEL (USART0) = 0b010000 ADC0SINGLE ADC0SCAN 0b000 0b001 0b010 SOURCESEL (USART1) = 0b010001 USART0IRTX USART0TXC USART0RXDATAV 0b000 0b001 0b010 SOURCESEL (TIMER0) = 0b011100 USART1IRTX USART1TXC USART1RXDATAV 0b000 0b001 0b010 0b011 0b100 SOURCESEL (TIMER1) 0b000 0b001 0b010 0b011 = 0b011101 0b100 SOURCESEL (TIMER2) 0b000 0b001 = 0b011110 0b010 0b011 0b100 SOURCESEL = 0b100100 (USB) 0b000 0b001 SOURCESEL = 0b101000 (RTC) 0b000 0b001 0b010 SOURCESEL = 0b110000 (GPIO) 0b000 0b001 TIMER0UF TIMER0OF TIMER0CC0 TIMER0CC1 TIMER0CC2 TIMER1UF TIMER1OF TIMER1CC0 TIMER1CC1 TIMER1CC2 TIMER2UF TIMER2OF TIMER2CC0 TIMER2CC1 TIMER2CC2 USBSOF USBSOFSR RTCOF RTCCOMP0 RTCCOMP1 GPIOPIN0 GPIOPIN1

Description

Description Pulse Counter 0

Reserved

SIGSEL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 Select signal input to PRS channel.

RW

Signal Select

Description Channel input selection is turned off Voltage comparator output VCMPOUT Analog comparator output ACMP0OUT ADC single conversion done ADC0SINGLE ADC scan conversion done ADC0SCAN USART 0 IRDA out USART0IRTX USART 0 TX complete USART0TXC USART 0 RX Data Valid USART0RXDATAV USART 1 IRDA out USART1IRTX USART 1 TX complete USART1TXC USART 1 RX Data Valid USART1RXDATAV Timer 0 Underflow TIMER0UF Timer 0 Overflow TIMER0OF Timer 0 Compare/Capture 0 TIMER0CC0 Timer 0 Compare/Capture 1 TIMER0CC1 Timer 0 Compare/Capture 2 TIMER0CC2 Timer 1 Underflow TIMER1UF Timer 1 Overflow TIMER1OF Timer 1 Compare/Capture 0 TIMER1CC0 Timer 1 Compare/Capture 1 TIMER1CC1 Timer 1 Compare/Capture 2 TIMER1CC2 Timer 2 Underflow TIMER2UF Timer 2 Overflow TIMER2OF Timer 2 Compare/Capture 0 TIMER2CC0 Timer 2 Compare/Capture 1 TIMER2CC1 Timer 2 Compare/Capture 2 TIMER2CC2 USB Start of Frame USBSOF USB Start of Frame Sent/Received USBSOFSR RTC Overflow RTCOF RTC Compare 0 RTCCOMP0 RTC Compare 1 RTCCOMP1 GPIO pin 0 GPIOPIN0 GPIO pin 1 GPIOPIN1 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

142

www.silabs.com

Bit Preliminary Name Reset

Value 0b010 0b011 Mode GPIOPIN2 GPIOPIN3 0b100 0b101 0b110 0b111 SOURCESEL = 0b110001 (GPIO) 0b000 GPIOPIN4 GPIOPIN5 GPIOPIN6 GPIOPIN7 0b001 0b010 0b011 0b100 0b101 0b110 GPIOPIN8 GPIOPIN9 GPIOPIN10 GPIOPIN11 GPIOPIN12 GPIOPIN13 GPIOPIN14 0b111 SOURCESEL = 0b110110 (PCNT0) GPIOPIN15 0b000 PCNT0TCC

Access

...the world's most energy friendly microcontrollers

Description

Description GPIO pin 2 GPIOPIN2 GPIO pin 3 GPIOPIN3 GPIO pin 4 GPIOPIN4 GPIO pin 5 GPIOPIN5 GPIO pin 6 GPIOPIN6 GPIO pin 7 GPIOPIN7 GPIO pin 8 GPIOPIN8 GPIO pin 9 GPIOPIN9 GPIO pin 10 GPIOPIN10 GPIO pin 11 GPIOPIN11 GPIO pin 12 GPIOPIN12 GPIO pin 13 GPIOPIN13 GPIO pin 14 GPIOPIN14 GPIO pin 15 GPIOPIN15 Triggered compare match PCNT0TCC

13.5.5 PRS_TRACECTRL - MTB Trace Control Register Offset

0x040

Reset Access Bit Position Name Bit

31:12

11:9 8

7:4

3:1

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TSTOP 0x0 RW Select PRS channel controlling the TSTOP signal to the MTB.

MTB TSTOP PRS select

2 3 4 Value 0 1 5 Mode PRSCH0 PRSCH1 PRSCH2 PRSCH3 PRSCH4 PRSCH5 TSTOPEN 0 RW Set PRS control of the TSTOP-signal going to the MTB.

Description PRS ch 0 is controlling TSTOP.

PRS ch 1 is controlling TSTOP.

PRS ch 2 is controlling TSTOP.

PRS ch 3 is controlling TSTOP.

PRS ch 4 is controlling TSTOP.

PRS ch 5 is controlling TSTOP.

PRS TSTOP Enable

Value 0 1

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TSTART 0x0 RW

MTB TSTART PRS select

Select PRS channel controlling the TSTART signal to the MTB.

Value 0 Mode PRSCH0 Description TSTOP is not controlled by PRS.

TSTOP is controlled by PRS.

Description PRS ch 0 is controlling TSTART.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

143

www.silabs.com

0

Bit Preliminary

...the world's most energy friendly microcontrollers

Name

3 4 5 Value 1 2 Mode PRSCH1 PRSCH2 PRSCH3 PRSCH4 PRSCH5

Reset Access

TSTARTEN 0 RW Set PRS control of the TSTART-signal going to the MTB.

Value 0 1 Description TSTART is not controlled by PRS.

TSTART is controlled by PRS.

Description

Description PRS ch 1 is controlling TSTART.

PRS ch 2 is controlling TSTART.

PRS ch 3 is controlling TSTART.

PRS ch 4 is controlling TSTART.

PRS ch 5 is controlling TSTART.

PRS TSTART Enable

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

144

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14 USB - Universal Serial Bus Controller

0 1 2 3 4

Quick Facts What?

The USB is a full-speed/low-speed USB 2.0

compliant USB Controller that can be used in various Device configurations. The on-chip 3.3V regulator delivers up to 50 mA and can also be used to power external components, eliminating the need for an external LDO. The on-chip regulator allows the system to run from a battery utilizing the full voltage range of the EFM32 still being compliant with the 3.3V +/- 10% USB voltage range.

Why?

USB provides a robust, industry-standard way to interface PCs and other portable devices.

How?

The flexible and highly software-configurable architecture of the USB Controller makes it easy to implement both device- and host capable solutions. The on-chip OTG PHY with software controllable pull-up and pull down resistors reduces the number of external components to a minimum. Third party USB software stacks are also available, reducing the development time substantially.

By utilizing the very low energy consumption in EM2, the USB device will be able to wake up and perform tasks several times a second without violating the 2.5 mA maximum average current during suspend.

14.1 Introduction

The USB is a full-speed/low-speed USB 2.0 compliant device controller. The architecture is very flexible and allows the USB to be used in various and Device-only configurations. The on-chip voltage regulator and PHY reduces the number of external components to a minimum.

14.2 Features

• Fully compliant with Universal Serial Bus Specification, Revision 2.0

• Supports full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) host and device • Low Energy Mode, reducing the average current consumption with up to 90%.

• Dedicated Internal DMA Controller • 6 software-configurable endpoints (3 IN, 3 OUT) in addition to endpoint 0 • 1 KB endpoint memory • Resume/Reset detection in EM2 (during suspend) • Soft connect/disconnect • On-chip PHY 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

145

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• Internal pull-up and pull-down resistors • Internal 3.3V Regulator • Output voltage: 3.3V

• Output current: 50 mA • Input voltage range: 4.0 - 5.5V

• Enabled automatically when input voltage applied • Low quiescent current: 100 uA • Output pin can be used to power the EFM32 itself as well as external components • Regulator voltage output sense feature for detecting USB plug/unplug events (also available in EM2/3)

14.3 USB System Description

A block diagram of the USB is shown in Figure 14.1 (p. 146) .

Figure 14.1. USB Block Diagram

1.5 KB FIFO RAM VREGO Sense Volt age Regulat or (3.3 V) USB_VREGI USB_VREGO AHB Mast er (Async) AHB Slave (Async) APB Slave USB Int errupt SOF PRS USB Core w/ DMA Cont roller USB Syst em (cont rol) OTG PHY USB_DP USB_DM USB_DMPU The USB consists of a digital logic part, an endpoint RAM, PHY and a voltage regulator with output voltage sensor. The voltage regulator provides a stable 3.3 V supply for the PHY, but can also be used to power the EFM32 itself as well as external components.

The digital logic of the USB is split into two parts: system and core.

The system part is accessed using USB registers from offset 0x000 to 0x018 and controls the voltage regulator, Low Energy Mode and enabling/disabling of the PHY and USB pins. This part is clocked by HFCORECLK USB and is accessed using an APB slave interface. The system part can thus be accessed independently of the core part, without HFCORECLK USBC running.

The core part is clocked by HFCORECLK USBC and is accessed using an AHB slave interface. This interface is used for accessing the FIFO contents and the registers in the core part starting at offset 0x3C000. An additional master interface is used by the internal DMA controller of the core. The core part takes care of all the USB protocol related functionality. The clock to the system part must not be disabled when the core part is active.

The two AHB interfaces also features asynchronous AHB bridges, allowing the system and the USB Core to run at different clocks. Note that these asynchronous AHB bridges will add extra delay when 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

146

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

transferring data over these interfaces. The asynchronous bridges will be bypassed when the HFCLK and HFCORECLK USBC are derived from the same clock source, allowing AHB transaction to complete in normal time.

There are several pins associated with the USB. USB_DP and USB_DM are the USB D+ and D pins. These are the USB data signaling pins. USB_VREGI is the input to the voltage regulator and USB_VREGO is the regulated output. USB_DMPU is used to enable/disable an external D- pull-up resistor. This is needed for low-speed device only. USB_DMPU will be high-impedance until enabled from software. Thus, if a defined level is required during start-up an external pull-up/pull-down can be used.

14.3.1 USB Clocks

The USB requires the device to run a 24 MHz crystal (2500 ppm or better), or the Universal Serial High Frequency Oscillator (USHFRCO). The core part of the USB will always run from HFCORECLK USBC , which is 48 MHz. The current consumption for the rest of the device can be reduced by dividing down HFCORECLK using the CMU_HFCORECLKDIV register, or by running the system on a different oscillator, at a lower speed. Bandwidth requirements for the specific USB application must be taken into account when dividing down HFCORECLK. Bandwidth requirements must also be considered when using different oscillators for the USBC and the rest of the system, as this infers extra delay in the asynchronous AHB bridges.

14.3.2 USB Initialization

Follow these steps to enable the USB: 1. Enable the clock to the system part by setting USB in CMU_HFCORECLKEN0.

2. If the internal USB regulator is bypassed (by applying 3.3V on USB_VREGI and USB_VREGO externally), disable the regulator by setting VREGDIS in USB_CTRL.

3. If the PHY is powered from VBUS using the internal regulator, the VREGO sense circuit should be enabled by setting VREGOSEN in USB_CTRL.

4. Enable the USB PHY pins by setting PHYPEN in USB_ROUTE.

5. If low-speed device, set DMPUAP in USB_CTRL to the desired value and then enable the USB_DMPU pin in USB_ROUTE. Set the MODE for the pin to PUSHPULL.

6. Make sure the oscillator is ready and selected in CMU_CMD_USBCCLKSEL.

7. Enable the clock to the core part by setting USBC in CMU_HFCORECLKEN0.

8. Wait for the core to come out of reset. This is easiest done by polling a core register with non-zero reset value until it reads a non-zero value. This takes approximately 20 48-MHz cycles.

9. Start initializing the USB core as described in USB Core Description.

14.3.3 Configurations

The USB is device-only, but with several power options The sections below describe the different configurations. External ESD protection and series resistors for impedance matching are required. The voltage regulator requires a 4.7 uF external decoupling capacitor on the input and a 1 uF external decoupling capacitor on the output. Decoupling not related to USB is not shown in the figures.

14.3.3.1 Bus-powered Device

A bus-powered device configuration is shown in Figure 14.2 (p. 148) . In this configuration the voltage

regulator powers the PHY and the EFM32 at 3.3 V. The voltage regulator output (USB_VREGO) can also be used to power other components of the system.

In this configuration, the VREGO sense circuit should be left disabled.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

147

www.silabs.com

Preliminary

Figure 14.2. Bus-powered Device ...the world's most energy friendly microcontrollers

VDD EFM32 USB_VREGO USB_VREGI USB_DP USB_DM VBUS D+ D GND

14.3.3.2 Self-powered Device

A self-powered device configuration is shown in Figure 14.3 (p. 148) . When the USB is configured as

a self-powered device, the voltage regulator is typically used to power the PHY only, although it may also be used to power other 3.3 V components. When the USB is connected to a host, the voltage regulator is activated. Software can detect this event by enabling the VREGO Sense High (VREGOSH) interrupt. The PHY pins can then be enabled and USB traffic can start. The VREGO Sense Low (VREGOSL) interrupt can be used to detect when VBUS voltage disappears (for example if the USB cable is unplugged).

In this configuration, the VREGO sense circuit must be enabled.

Figure 14.3. Self-powered Device

1.8V – 3.6V

VDD EFM32 USB_VREGO USB_VREGI USB_DP USB_DM VBUS D+ D GND

14.3.3.3 Self-powered Device (with bus-power switch)

A self-powered device (with bus-power switch) may switch power supply to VBUS when connected to a host. This is typically useful for extending the life of battery-powered devices and enables the use of coin-cell driven systems with low maximum peak current. The external components required typically include 2 transistors, 2 diodes and a few resistors. See application note for details. This allows seamless power supply switching between a battery and the voltage regulator output.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

148

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

The VREGO Sense High interrupt is used to detect when VBUS becomes present. Software can then enable the external transistor connected to USB_VREGO, effectively switching the power source. A regular GPIO pin is used to control this transistor. If necessary, the application may have to reduce the current consumption before switching to the USB power source. If VBUS voltage is removed, the circuit switches automatically back to the battery power supply. If necessary software must react quickly to this event and reduce the current consumption (for example by reducing the clock frequency) to avoid

excessive voltage drop. This configuration is shown in Figure 14.4 (p. 149) .

In this configuration, the VREGO sense circuit must be enabled.

Figure 14.4. Self-powered Device (with bus-power switch)

1.8V – 3.6V

Dual- Power Circuit VDD (enable) GPIO USB_VREGO USB_VREGI EFM32 USB_DP USB_DM VBUS D+ D GND

14.3.4 PHY

The USB includes an internal full-speed/low-speed PHY with built-in pull-up/pull-down resistors. During suspend, the PHY enters a low-power state where only the single-ended receivers are active. The PHY is disabled by default and should be enabled by setting PHYPEN in USB_ROUTE before the USB core clock is enabled.

The PHY is powered by the internal voltage regulator output (USB_VREGO). To power the PHY directly from an external source (for example an external 3.3 V LDO), connect both USB_VREGO and USB_VREGI to the external 3.3 V supply voltage. To stop the quiescent current present with the voltage regulator enabled in this configuration, disable the the regulator by setting VREGDIS in USB_CTRL after power up. Then the regulator is effectively bypassed.

When VREGO Sense is enabled, the PHY is automatically disabled internally when the VREGO Sense output is low. This will happen if VBUS-power disappears. The application can detect this by keeping the VREGO Sense Low Interrupt enabled. Note that PHYPEN in USB_ROUTE will not be set to 0 in this case. Also, the PHY must always be disabled manually when there is no voltage applied to VREGO.

14.3.5 Voltage Regulator

The voltage regulator is used to regulate the 5 V VBUS voltage down to 3.3 V which is the operating voltage for the PHY.

A decoupling capacitor is required on USB_VREGI and USB_VREGO. Note that the USB standard requires the total capacitance on VBUS to be 1 uF minimum and 10 uF maximum for regular devices.

OTG devices can have maximum 6.5 uF capacitance on VBUS.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

149

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

The voltage regulator is enabled by default and can thus be used to power the EFM32 itself. Systems not using the USB should disable the regulator by setting VREGDIS in USB_CTRL. A voltage sense circuit monitors the output voltage and can be used to detect when the voltage regulator becomes active. This sense circuit can also be used to detect when the voltage drops (typically due to the USB cable being unplugged). If regulator voltage monitoring is not required (i.e. it is known that the VREGO voltage is always present), the sense circuit should be left disabled.

During suspend, the bias current for the regulator can be reduced if the current requirements in EM2/3 are low. The bias current in EM2/3 is controlled by BIASPROGEM23 in USB_CTRL. When EM2/3 is entered, the bias current for the regulator switches to what is specified in BIASPROGEM23 in USB_CTRL. When entering EM0 again (due to USB resume/reset signaling or any other wake-up interrupt) the regulator switches back to using the value specified in BIASPROGEM01 in USB_CTRL.

14.3.6 Interrupts and PRS

Interrupts from the core and system part share a common USB interrupt line to the CPU. The interrupt flags for the system part are grouped together in the USB_IF register. The interrupt events from the core are controlled by several core interrupt flag registers.

There are two PRS outputs from the USB: SOF and SOFSR. SOF toggles every time an SOF token is received from the USB host or when an SOF token is missed at the start of frame, while SOFSR toggles only when a valid SOF token is received from the USB host. Both PRS outputs must be synchronized in the PRS when used (i.e. it is an asynchronous PRS output). The edge-to-pulse converter in the PRS can be used to convert the edges into pulses if needed. The PRS outputs go to 0 in EM2/3.

14.3.7 USB Low Energy Mode

The USB also features a Low Energy Mode (LEM) that can be used to reduce the current consumption of the USB when there is no data on the lines that can be received. When such a condition is detected the USB can be configured to turn off the clock to the USB Core and possibly suspend the USHFRCO.

Note that if the system is also running off of the USHFRCO, the oscillator will not be suspended when a Low Energy condition is detected.

The condition that can trigger Low Energy Mode is: • Idle - There is no traffic on the lines.

This condition have the enable bit in the USB_CTRL; LEMIDLEEN.

Even though most of the USB operation is identical irregardless of whether Low Energy Mode is enabled, there are two subtle functional differences when Low Energy Mode is enabled: (1) higher access time to the core registers; and (2) no interrupts/PRS on missed SOFs. The higher access time to the core registers is only applicable when LEMOSCCTRL in USB_CTRL is set to SUSPEND, and is due to the fact that on a bus access, the system needs to restart the USHFRCO to complete the transfer. If the application will have several bus USB transactions in a short time, e.g. in the IRQ handler, it is recommended to set the LEMOSCCTRL to GATE during this time. Also, missed SOFs will not generate interrupts or PRS toggles when Low Energy Mode is enabled.

14.3.8 USB in EM2

During suspend and session-off EM2 should be used to save power and meet the average current requirements dictated by the USB standard. Before entering EM2, HFCORECLK USBC must be switched from 48 MHz to 32 kHz (LFXO or LFRCO). This is done using the CMU_CMD and CMU_STATUS registers. Upon EM2 wake-up, HFCORECLK USBC must be switched back to 48 MHz before accessing the core registers. The device always starts up from HFRCO so software must restart HFXO and switch from HFRCO to HFXO. The USB system clock, HFCORECLK USB , must be kept enabled during EM2. The 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

150

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

USB system registers can be accessed immediately upon EM2 wake-up, while running from HFRCO.

Follow the steps outlined the USB Core Description when entering EM2 during suspend and session-off.

The FIFO content is lost when entering EM2. In addition, most of the USB core registers are reset and therefore need to be backed up in RAM.

EM3 cannot be used when the USB is active. However, EM3 can be used while waiting for the internal voltage regulator to be activated (i.e. VBUS becomes 5V).

14.4 USB Core Description

This section describes the programming requirements for the USB Core.

Important features/parameters for the core are: • Device only • Internal DMA (Buffer Pointer Based) • Dedicated TX FIFOS for each endpoint in device mode • 3 IN/OUT endpoints in addition to endpoint 0 (in device mode) • Dynamic FIFO sizing • Non-Periodic Request Queue Depth: 8 The core has the following limitations: • Link Power Management (LPM) is not supported • ADP is not supported • No OTG support (HNP and SRP not supported).

Portions Copyright © 2010 Synopsys, Inc. Used with permission. Synopsys and DesignWare are registered trademarks of Synopsys, Inc.

14.4.1 Overview: Programming the Core

Each significant programming feature of the core is discussed in a separate section.

This chapter uses abbreviations for register names and their fields. For detailed information on registers,

see Section 14.6 (p. 252) .

The application must perform a core initialization sequence. If the cable is connected during power-up, the Current Mode of Operation bit in the Core Interrupt register (USB_GINTSTS.CURMOD) reflects the mode. The core enters Host mode when an “A” plug is connected, or Device mode when a “B” plug is connected.

This section explains the initialization of the core after power-on. The application must follow the initialization sequence irrespective of Host or Device mode operation. All core global registers are initialized according to the core’s configuration.

1. Program the following fields in the Global AHB Configuration (USB_GAHBCFG) register.

• DMA Mode bit • AHB Burst Length field • Global Interrupt Mask bit = 1 • Non-periodic TxFIFO Empty Level (can be enabled only when the core is operating in Slave mode as a host.) • Periodic TxFIFO Empty Level (can be enabled only when the core is operating in Slave mode) 2. Program the following field in the Global Interrupt Mask (USB_GINTMSK) register: • USB_GINTMSK.RXFLVLMSK = 0 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

151

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

3. Program the following fields in USB_GUSBCFG register.

• HNP Capable bit • SRP Capable bit • External HS PHY or Internal FS Serial PHY Selection bit • Time-Out Calibration field • USB Turnaround Time field 4. The software must unmask the following bits in the USB_GINTMSK register.

• OTG Interrupt Mask • Mode Mismatch Interrupt Mask 5. The software can read the USB_GINTSTS.CURMOD bit to determine whether the core is operating

in Host or Device mode. The software the follows either the Section 14.4.1.1 (p. 152) or Device Initialization (p. 153) sequence.

Note

The core is designed to be interrupt-driven. Polling interrupt mechanism is not recommended: this may result in undefined resolutions.

Note

In device mode, just after Power On Reset or a Soft Reset, the USB_GINTSTS.SOF bit is set to 1 for debug purposes. This status must be cleared and can be ignored.

14.4.1.1 Host Initialization

To initialize the core as host, the application must perform the following steps.

1. Program USB_GINTMSK.PRTINT to unmask.

2. Program the USB_HCFG register to select full-speed host.

3. Program the USB_HPRT.PRTPWR bit to 1. This drives VBUS on the USB.

4. Wait for the USB_HPRT.PRTCONNDET interrupt. This indicates that a device is connect to the port.

5. Program the USB_HPRT.PRTRST bit to 1. This starts the reset process.

6. Wait at least 10 ms for the reset process to complete.

7. Program the USB_HPRT.PRTRST bit to 0.

8. Wait for the USB_HPRT.PRTENCHNG interrupt.

9. Read the USB_HPRT.PRTSPD field to get the enumerated speed.

10.Program the USB_HFIR register with a value corresponding to the selected PHY clock. At this point, the host is up and running and the port register begins to report device disconnects, etc. The port is active with SOFs occurring down the enabled port.

11.Program the RXFSIZE register to select the size of the receive FIFO.

12.Program the NPTXFSIZE register to select the size and the start address of the Non-periodic Transmit FIFO for non-periodic transactions.

13.Program the USB_HPTXFSIZ register to select the size and start address of the Periodic Transmit FIFO for periodic transactions.

To communicate with devices, the system software must initialize and enable at least one channel as

described in Device Initialization (p. 153) .

14.4.1.1.1 Host Connection

The following steps explain the host connection flow: 1. When the USB Cable is plugged to the Host port, the core triggers USB_GINTSTS.CONIDSTSCHNG

interrupt.

2. When the Host application detects USB_GINTSTS.CONIDSTSCHNG interrupt, the application can perform one of the following actions: 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

152

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• Turn on VBUS by setting USB_HPRT.PRTPWR = 1 or • Wait for SRP Signaling from Device to turn on VBUS.

3. The PHY indicates VBUS power-on by detecting a VBUS valid voltage level.

4. When the Host Core detects the device connection, it triggers the Host Port Interrupt (USB_GINTSTS.PRTINT) to the application.

5. When USB_GINTSTS.PRTINT is triggered, the application reads the USB_HPRT register to check if the Port Connect Detected (USB_HPRT.PRTCONNDET) bit is set or not.

14.4.1.1.2 Host Disconnection

The following steps explain the host disconnection flow: 1. When the Device is disconnected from the USB Cable (but the cable is still connected to the USB host), the Core triggers USB_GINTSTS.DISCONNINT (Disconnect Detected) interrupt.

Note

If the USB cable is disconnected from the Host port without removing the device, the core generates an additional interrupt - USB_GINTSTS.CONIDSTSCHNG (Connector ID Status Change).

2. The Host application can choose to turn off the VBUS by programming USB_HPRT.PRTPWR = 0.

14.4.1.2 Device Initialization

The application must perform the following steps to initialize the core at device on, power on, or after a mode change from Host to Device.

1. Program the following fields in USB_DCFG register.

• Device Speed • Non-Zero-Length Status OUT Handshake • Periodic Frame Interval 2. Program the USB_GINTMSK register to unmask the following interrupts.

• USB Reset • Enumeration Done • Early Suspend • USB Suspend 3. Wait for the USB_GINTSTS.USBRST interrupt, which indicates a reset has been detected on the USB and lasts for about 10 ms. On receiving this interrupt, the application must perform the steps

listed in Initialization on USB Reset (p. 186)

4. Wait for the USB_GINTSTS.ENUMDONE interrupt. This interrupt indicates the end of reset on the USB. On receiving this interrupt, the application must read the USB_DSTS register to determine the

enumeration speed and perform the steps listed in Initialization on Enumeration Completion (p. 186)

At this point, the device is ready to accept SOF packets and perform control transfers on control endpoint 0.

14.4.1.2.1 Device Connection

The device connect process varies depending on the if the VBUS is on or off when the device is connected to the USB cable.

When VBUS is on When the Device is Connected

If VBUS is on when the device is connected to the USB cable, there is no SRP from the device. The device connection flow is as follows: 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

153

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

1. The device triggers the USB_GINTSTS.SESSREQINT [bit 30] interrupt bit.

2. When the device application detects the USB_GINTSTS.SESSREQINT interrupt, it programs the required bits in the USB_DCFG register.

3. When the Host drives Reset, the Device triggers USB_GINTSTS.USBRST [bit 12] on detecting the Reset. The host then follows the USB 2.0 Enumeration sequence.

When VBUS is off When the Device is Connected

If VBUS is off when the device is connected to the USB cable, the device initiates SRP in OTG Revision 1.3 mode. The device connection flow is as follows: 1. The application initiates SRP by writing the Session Request bit in the OTG Control and Status register. The core perform data-line pulsing followed by VBUS pulsing.

2. The host starts a new session by turning on VBUS, indicating SRP success. The core interrupts the application by setting the Session Request Success Status Change bit in the OTG Interrupt Status register.

3. The application reads the Session Request Success bit in the OTG Control and Status register and programs the required bits in USB_DCFG register.

4. When Host drives Reset, the Device triggers USB_GINTSTS.USBRST on detecting the Reset. The host then follows the USB 2.0 Enumeration sequence.

14.4.1.2.2 Device Disconnection

The device session ends when the USB cable is disconnected or if the VBUS is switched off by the Host.

The device disconnect flow is as follows: 1. When the USB cable is unplugged or when the VBUS is switched off by the Host, the Device core trigger USB_GINTSTS.OTGINT [bit 2] interrupt bit.

2. When the device application detects USB_GINTSTS.OTGINT interrupt, it checks that the USB_GOTGINT.SESENDDET (Session End Detected) bit is set to 1.

14.4.1.2.3 Device Soft Disconnection

The application can perform a soft disconnect by setting the Soft disconnect bit (SFTDISCON) in Device Control Register (USB_DCTL).

Send/Receive USB Transfers -> Soft disconnect->Soft reset->USB Device Enumeration

Sequence of operations: 1. The application configures the device to send or receive transfers.

2. The application sets the Soft disconnect bit (SFTDISCON) in the Device Control Register (USB_DCTL).

3. The application sets the Soft Reset bit (CSFTRST) in the Reset Register (USB_GRSTCTL).

4. Poll the USB_GRSTCTL register until the core clears the soft reset bit, which ensures the soft reset is completed properly.

5. Initialize the core according to the instructions in Device Initialization (p. 153) .

Suspend-> Soft disconnect->Soft reset->USB Device Enumeration

Sequence of operations: 1. The core detects a USB suspend and generates a Suspend Detected interrupt.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

154

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register, the core puts the PHY in suspend mode, and the PHY clock stops.

3. The application clears the Stop PHY Clock bit in the Power and Clock Gating Control register, and waits for the PHY clock to come back. The core takes the PHY back to normal mode, and the PHY clock comes back.

4. The application sets the Soft disconnect bit (SFTDISCON) in Device Control Register (USB_DCTL).

5. The application sets the Soft Reset bit (CSFTRST) in the Reset Register (USB_GRSTCTL).

6. Poll the USB_GRSTCTL register until the core clears the soft reset bit, which ensures the soft reset is completed properly.

7. Initialize the core according to the instructions in Device Initialization (p. 153) .

14.4.2 Modes of operation

• Overview: DMA/Slave modes (p. 155) • DMA Mode (p. 155) • Slave Mode (p. 155)

14.4.2.1 Overview: DMA/Slave modes

The application can operate the core in either of two modes:

• In DMA Mode (p. 155) - The core fetches the data to be transmitted or updates the received data

on the AHB.

• In Slave Mode (p. 155) — The application initiates the data transfers for data fetch and store.

14.4.2.2 DMA Mode

In DMA Mode, the OTG host uses the AHB master Interface for transmit packet data fetch (AHB to USB) and receive data update (USB to AHB). The AHB master uses the programmed DMA address (USB_HCx_DMAADDR register in host mode and USB_DIEPx_DMAADDR/USB_DOEPx_DMAADDR register in device mode) to access the data buffers.

14.4.2.2.1 Transfer-Level Operation

In DMA mode, the application is interrupted only after the programmed transfer size is transmitted or received (provided the core detects no NAK/Timeout/Error response in Host mode, or Timeout/CRC Error in Device mode). The application must handle all transaction errors. In Device mode, all the USB errors are handled by the core itself.

14.4.2.2.2 Transaction-Level Operation

This mode is similar to transfer-level operation with the programmed transfer size equal to one packet size (either maximum packet size, or a short packet size).

14.4.2.3 Slave Mode

In Slave mode, the application can operate the core either in transaction-level (packet-level) operation or in pipelined transaction-level operation.

14.4.2.3.1 Transaction-Level Operation

The application handles one data packet at a time per channel/endpoint in transaction-level operations.

Based on the handshake response received on the USB, the application determines whether to retry the transaction or proceed with the next, until the end of the transfer. The application is interrupted on 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

155

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

completion of every packet. The application performs transaction-level operations for a channel/endpoint

for a transmission (host: OUT/device: IN) or reception (host: IN/device: OUT) as shown in Figure 14.5 (p.

156) and Figure 14.6 (p. 157) .

Host Mode

For an OUT transaction, the application enables the channel and writes the data packet into the corresponding (Periodic or Non-periodic) transmit FIFO. The core automatically writes the channel number into the corresponding (Periodic or Non-periodic) Request Queue, along with the last DWORD write of the packet. For an IN transaction, the application enables the channel and the core automatically writes the channel number into the corresponding Request queue. The application must wait for the packet received interrupt, then empty the packet from the receive FIFO.

Device Mode

For an IN transaction, the application enables the endpoint, writes the data packet into the corresponding transmit FIFO, and waits for the packet completion interrupt from the core. For an OUT transaction, the application enables the endpoint, waits for the packet received interrupt from the core, then empties the packet from the receive FIFO.

Note

The application has to finish writing one complete packet before switching to a different channel/endpoint FIFO. Violating this rule results in an error.

Figure 14.5. Transmit Transaction-Level Operation in Slave Mode

Start Set up the channel/endpoint Write 1 packet to the Transmit FIFO Rewrite packet to the Transmit FIFO Yes Get interrupt?

Yes Get channel/endpoint interrupt status No No Retry required?

No Transfer complete?

Yes Done 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

156

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.6. Receive Transaction-Level Operation in Slave Mode

St art Set up t he Channel / endpoint Yes RXFLVL or Ch/EP int errupt ?

Yes Read Receive St at us Queue No No Ret ry required ?

No Read t he packet from t he Receive FIFO Transfer com plet e?

Yes Done

14.4.2.3.2 Pipelined Transaction-Level Operation

The application can pipeline more than one transaction (IN or OUT) with pipelined transaction-level operation, which is analogous to Transfer mode in DMA mode. In pipelined transaction-level operation, the application can program the core to perform multiple transactions. The advantage of this mode compared to transaction-level operation is that the application is not interrupted on a packet basis.

14.4.2.3.2.1 Host mode

For an OUT transaction, the application sets up a transfer and enables the channel. The application can write multiple packets back-to-back for the same channel into the transmit FIFO, based on the space availability. It can also pipeline OUT transactions for multiple channels by writing into the HCHARn register, followed by a packet write to that channel. The core writes the channel number, along with the last DWORD write for the packet, into the Request queue and schedules transactions on the USB in the same order.

For an IN transaction, the application sets up a transfer and enables the channel, and the core writes the channel number into the Request queue. The application can schedule IN transactions on multiple channels, provided space is available in the Request queue. The core initiates an IN token on the USB only when there is enough space to receive at least of one maximum-packet-size packet of the channel in the top of the Request queue.

14.4.2.3.2.2 Device mode

For an IN transaction, the application sets up a transfer and enables the endpoint. The application can write multiple packets back-to-back for the same endpoint into the transmit FIFO, based on available space. It can also pipeline IN transactions for multiple channels by writing into the USB_DIEPx_CTL 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

157

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

register followed by a packet write to that endpoint. The core writes the endpoint number, along with the last DWORD write for the packet into the Request queue. The core transmits the data in the transmit FIFO when an IN token is received on the USB.

For an OUT transaction, the application sets up a transfer and enables the endpoint. The core receives the OUT data into the receive FIFO, when it has available space. As the packets are received into the FIFO, the application must empty data from it.

From this point on in this chapter, the terms “Pipelined Transaction mode” and “Transfer mode” are used interchangeably.

14.4.3 Host Programming Model

Before you program the Host, read Overview: Programming the Core (p. 151) and Modes of operation (p. 155) .

This section discusses the following topics:

• Channel Initialization (p. 158)

• Halting a Channel (p. 159) • Zero-Length Packets (p. 159)

• Handling Babble Conditions (p. 160) • Handling Disconnects (p. 160) • Host Programming Operations (p. 160)

• Writing the Transmit FIFO in Slave Mode (p. 161) • Reading the Receive FIFO in Slave Mode (p. 161)

14.4.3.1 Channel Initialization

The application must initialize one or more channels before it can communicate with connected devices.

To initialize and enable a channel, the application must perform the following steps.

1. Program the USB_GINTMSK register to unmask the following: 2. Channel Interrupt • Non-periodic Transmit FIFO Empty for OUT transactions (applicable for Slave mode that operates in pipelined transaction-level with the Packet Count field programmed with more than one).

• Non-periodic Transmit FIFO Half-Empty for OUT transactions (applicable for Slave mode that operates in pipelined transaction-level with the Packet Count field programmed with more than one).

3. Program the USB_USB_HAINTMSK register to unmask the selected channels’ interrupts.

4. Program the HCINTMSK register to unmask the transaction-related interrupts of interest given in the Host Channel Interrupt register.

5. Program the selected channel’s USB_HCx_TSIZ register.

Program the register with the total transfer size, in bytes, and the expected number of packets, including short packets. The application must program the PID field with the initial data PID (to be used on the first OUT transaction or to be expected from the first IN transaction).

6. Program the selected channels’ USB_HCx_DMAADDR register(s) with the buffer start address (DMA mode only).

7. Program the USB_HCx_CHAR register of the selected channel with the device’s endpoint characteristics, such as type, speed, direction, and so forth. (The channel can be enabled by setting the Channel Enable bit to 1 only when the application is ready to transmit or receive any packet).

Repeat the above steps for other channels.

Note

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

158

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

De-allocate channel means after the transfer has completed, the channel is disabled. When the application is ready to start the next transfer, the application re-initializes the channel by following these steps.

14.4.3.2 Halting a Channel

The application can disable any channel by programming the USB_HCx_CHAR register with the USB_HCx_CHAR.CHDIS and USB_HCx_CHAR.CHENA bits set to 1. This enables the host to flush the posted requests (if any) and generates a Channel Halted interrupt. The application must wait for the USB_HCx_INT.CHHLTD interrupt before reallocating the channel for other transactions. The host does not interrupt the transaction that has been already started on USB.

In Slave mode operation, before disabling a channel, the application must ensure that there is at least one free space available in the Non-periodic Request Queue (when disabling a non-periodic channel) or the Periodic Request Queue (when disabling a periodic channel). The application can simply flush the posted requests when the Request queue is full (before disabling the channel), by programming the USB_HCx_CHAR register with the USB_HCx_CHAR.CHDIS bit set to 1, and the USB_HCx_CHAR.CHENA bit reset to 0.

The core generates a RXFLVL interrupt when there is an entry in the queue. The application must read/ pop the USB_GRXSTSP register to generate the Channel Halted interrupt.

To disable a channel in DMA mode operation, the application need not check for space in the Request queue. The host checks for space in which to write the Disable request on the disabled channel’s turn during arbitration. Meanwhile, all posted requests are dropped from the Request queue when the USB_HCx_CHAR.CHDIS bit is set to 1.

The application is expected to disable a channel under any of the following conditions: 1. When a USB_HCx_INT.XFERCOMPL interrupt is received during a non-periodic IN transfer or high bandwidth interrupt IN transfer (Slave mode only) 2. When a USB_HCx_INT.STALL, USB_HCx_INT.XACTERR, USB_HCx_INT.BBLERR, or USB_HCx_INT.DATATGLERR interrupt is received for an IN or OUT channel (Slave mode only).

For high-bandwidth interrupt INs in Slave mode, once the application has received a DATATGLERR interrupt it must disable the channel and wait for a Channel Halted interrupt. The application must be able to receive other interrupts (DATATGLERR, NAK, Data, XACTERR, BBLERR) for the same channel before receiving the halt.

3. When a USB_GINTSTS.DISCONNINT (Disconnect Device) interrupt is received. The application must check for the USB_HPRT.PRTCONNSTS, because when the device directly connected to the host is disconnected, USB_HPRT.PRTCONNSTS is reset. The software must issue a soft reset to ensure that all channels are cleared. When the device is reconnected, the host must issue a USB Reset.

4. When the application aborts a transfer before normal completion (Slave and DMA modes).

Note

In DMA mode, keep the following guideline in mind: • Channel disable must not be programmed for periodic channels. At the end of the next frame (in the worst case), the core generates a channel halted and disables the channel automatically.

14.4.3.3 Sending a Zero-Length Packet in Slave/DMA Modes

To send a zero-length data packet, the application must initialize an OUT channel as follows.

1. Program the USB_HCx_TSIZ register of the selected channel with a correct PID, XFERSIZE = 0, and PKTCNT = 1.

2. Program the USB_HCx_CHAR register of the selected channel with CHENA = 1 and the device’s endpoint characteristics, such as type, speed, and direction.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

159

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

The application must treat a zero-length data packet as a separate transfer, and cannot combine it with a non-zero-length transfer.

14.4.3.4 Handling Babble Conditions

The core handles two cases of babble: packet babble and port babble. Packet babble occurs if the device sends more data than the maximum packet size for the channel. Port babble occurs if the core continues to receive data from the device at EOF2 (the end of frame 2, which is very close to SOF).

When the core detects a packet babble, it stops writing data into the Rx buffer and waits for the end of packet (EOP). When it detects an EOP, it flushes already-written data in the Rx buffer and generates a Babble interrupt to the application.

When detects a port babble, it flushes the RxFIFO and disables the port. The core then generates a Port Disabled Interrupt (USB_GINTSTS.PRTINT, USB_HPRT.PRTENCHNG). On receiving this interrupt, the application must determine that this is not due to an overcurrent condition (another cause of the Port Disabled interrupt) by checking USB_HPRT.PRTOVRCURRACT, then perform a soft reset. The core does not send any more tokens after it has detected a port babble condition.

14.4.3.5 Handling Disconnects

If the device is disconnected suddenly, a USB_GINTSTS.DISCONNINT interrupt is generated.

When the application receives this interrupt, it must issue a soft reset by programming the USB_GRSTCTL.CSFTRST bit.

14.4.3.6 Host Programming Operations

Table 14.1 (p. 160) provides links to the programming sequence for the different types of USB

transactions.

Table 14.1. Host Programming Operations

Mode Control Slave IN DMA

Bulk and Control IN Transactions in Slave Mode (p. 164)

Bulk and Control IN Transactions in DMA Mode (p. 170)

Bulk Slave DMA

Bulk and Control IN Transactions in Slave Mode (p. 164)

Bulk and Control IN Transactions in DMA Mode (p. 170)

Interrupt Slave DMA

Interrupt IN Transactions in Slave Mode (p. 174)

Interrupt IN Transactions in DMA Mode (p. 178)

Isochronous Slave DMA OUT/SETUP

Bulk and Control OUT/SETUP Transactions in Slave Mode (p. 162)

Bulk and Control OUT/SETUP Transactions in DMA Mode (p. 166)

Bulk and Control OUT/SETUP Transactions in Slave Mode (p. 162)

Bulk and Control OUT/SETUP Transactions in DMA Mode (p. 166)

Interrupt OUT Transactions in Slave Mode (p. 172)

Interrupt OUT Transactions in DMA Mode (p. 176)

Isochronous IN Transactions in Slave Mode (p. 182)

Isochronous IN Transactions in DMA Mode (p. 184)

Isochronous OUT Transactions in Slave Mode (p. 180)

Isochronous OUT Transactions in DMA Mode (p. 183)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

160

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.4.3.6.1 Writing the Transmit FIFO in Slave Mode

Figure 14.7 (p. 161) shows the flow diagram for writing to the transmit FIFO in Slave mode. The host

automatically writes an entry (OUT request) to the Periodic/Non-periodic Request Queue, along with the last DWORD write of a packet. The application must ensure that at least one free space is available in the Periodic/Non-periodic Request Queue before starting to write to the transmit FIFO. The application must always write to the transmit FIFO in DWORDs. If the packet size is non-DWORD aligned, the application must use padding. The host determines the actual packet size based on the programmed maximum packet size and transfer size.

Figure 14.7. Transmit FIFO Write Task in Slave Mode

St art Read USB_GNPTXSTS / USB_HPTXFSIZ regist ers for available FIFO and Queue spaces USB_GAHBCFG Wait for .

NPTXFEMPLVL or USB_GAHBCFG .

PTXFEMPLVL int errupt No 1 or LPS FIFO space available?

Yes Writ e dat a t o Transm it FIFO Yes More packet s t o send?

No Done MPS : Last Packet Size

14.4.3.6.2 Reading the Receive FIFO in Slave Mode

Figure 14.8 (p. 161) shows the flow diagram for reading the receive FIFO in Slave mode. The

application must ignore all packet statuses other than IN Data Packet (0b0010).

Figure 14.8. Receive FIFO Read Task in Slave Mode

St art Unm ask RXFLVL int errupt Read t he received packet from t he Receive FIFO No RXFLVL Int errupt ?

Yes Mask RXFLVL int errupt Read USB_GRXSTSP PKTSTS = 0b0010?

Yes Yes No Unm ask RXFLVL int errupt No 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

161

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.4.3.6.3 Control Transactions in Slave Mode

Setup, Data, and Status stages of a control transfer must be performed as three separate transfers.

Setup- Data- or Status-stage OUT transactions are performed similarly to the bulk OUT transactions

explained in Bulk and Control OUT/SETUP Transactions in Slave Mode (p. 162) . Data- or Status-

stage IN transactions are performed similarly to the bulk IN transactions explained in Bulk and Control IN Transactions in Slave Mode (p. 164) For all three stages, the application is expected to set the

USB_HC1_CHAR.EPTYPE field to Control. During the Setup stage, the application is expected to set the USB_HC1_TSIZ.PID field to SETUP.

14.4.3.6.4 Bulk and Control OUT/SETUP Transactions in Slave Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 158) . See Figure 14.7 (p. 161) and Figure 14.8 (p.

161) for Read or Write data to and from the FIFO in Slave mode.

A typical bulk or control OUT/SETUP pipelined transaction-level operation in Slave mode is shown in

Figure 14.9 (p. 163) . See channel 1 (ch_1). Two bulk OUT packets are transmitted. A control SETUP

transaction operates the same way but has only one packet. The assumptions are: • The application is attempting to send two maximum-packet-size packets (transfer size = 1,024 bytes).

• The Non-periodic Transmit FIFO can hold two packets (128 bytes for FS).

• The Non-periodic Request Queue depth = 4.

14.4.3.6.4.1 Normal Bulk and Control OUT/SETUP Operations

The sequence of operations in Figure 14.9 (p. 163) (channel 1) is as follows:

1. Initialize channel 1 as explained in Channel Initialization (p. 158) .

2. Write the first packet for channel 1.

3. Along with the last DWORD write, the core writes an entry to the Non-periodic Request Queue.

4. As soon as the non-periodic queue becomes non-empty, the core attempts to send an OUT token in the current frame.

5. Write the second (last) packet for channel 1.

6. The core generates the XFERCOMPL interrupt as soon as the last transaction is completed successfully.

7. In response to the XFERCOMPL interrupt, de-allocate the channel for other transfers.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

162

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.9. Normal Bulk/Control OUT/SETUP and Bulk/Control IN Transactions in Slave Mode

AHB Host USB Device

init_ reg( ch_2) set_ch_en (ch_2) set_ch_en (ch_2)

1 1 2 2 5 Application

init_ reg(ch_1) writ e_t x_fifo ( ch_1) writ e_t x_fifo ( ch_1) 1 MPS 1 MPS

3

ch_1 ch_2 ch_1 ch_2

4 Non- Periodic Request Queue

Assum e t hat t his queue can hold 4 ent ries.

OUT D AT A0 MPS

3

set_ch_en (ch_2) ACK IN

4

D AT A0

5

read_rx_st s read_rx_fifo set_ch_en (ch_2) RXFLVL int errupt 1 MPS ch_1 ch_2 ch_2 ch_2 ACK O UT D AT A1 MPS

7

De- allocat e ( ch_1) XFERCOMPL int errupt

6

ACK IN D AT A1 read_rx_st sre ad_rx_fifo read_rx_st s Disable (ch_2) read_rx_st s De- allocat e (ch_2)

7 9 1 1 1 3

RXFLVL int errupt 1 MPS RXFLVL int errupt XFERCOMPL int errupt RXFLVL int errupt CHHLTD int errupt

6 8

ch_2

1 0 1 2

ACK

14.4.3.6.4.2 Handling Interrupts

The channel-specific interrupt service routine for bulk and control OUT/SETUP transactions in Slave mode is shown in the following code samples.

Interrupt Service Routine for Bulk/Control OUT/SETUP Transactions in Slave Mode Bulk/Control OUT/SETUP

Unmask (NAK/XACTERR/STALL/XFERCOMPL) if (XFERCOMPL) { Reset Error Count Mask ACK De-allocate Channel } else if (STALL) 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

163

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

{ Transfer Done = 1 Unmask CHHLTD Disable Channel } else if (NAK or XACTERR) { Rewind Buffer Pointers Unmask CHHLTD Disable Channel if (XACTERR) { Increment Error Count Unmask ACK } else { Reset Error Count } } else if (CHHLTD) { Mask CHHLTD if (Transfer Done or (Error_count == 3)) { De-allocate Channel } else { Re-initialize Channel } } else if (ACK) { Reset Error Count Mask ACK } The application is expected to write the data packets into the transmit FIFO when space is available in the transmit FIFO and the Request queue. The application can make use of USB_GINTSTS.NPTXFEMP

interrupt to find the transmit FIFO space.

The application is expected to write the requests as and when the Request queue space is available and until the XFERCOMPL interrupt is received.

14.4.3.6.5 Bulk and Control IN Transactions in Slave Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 158) . See Figure 14.7 (p. 161) and Figure 14.8 (p.

161) for read or write data to and from the FIFO in Slave mode.

A typical bulk or control IN pipelined transaction-level operation in Slave mode is shown in Figure 14.9 (p.

163) . See channel 2 (ch_2). The assumptions are:

1. The application is attempting to receive two maximum-sized packets (transfer size = 1,024 bytes).

2. The receive FIFO can contain at least one maximum-packet-size packet and two status DWORDs per packet (72 bytes for FS).

3. The Non-periodic Request Queue depth = 4.

14.4.3.6.5.1 Normal Bulk and Control IN Operations

The sequence of operations in Figure 14.9 (p. 163) is as follows:

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

164

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

1. Initialize channel 2 as explained in Channel Initialization (p. 158) .

2. Set the USB_HC2_CHAR.CHENA bit to write an IN request to the Non-periodic Request Queue.

3. The core attempts to send an IN token after completing the current OUT transaction.

4. The core generates an RXFLVL interrupt as soon as the received packet is written to the receive FIFO.

5. In response to the RXFLVL interrupt, mask the RXFLVL interrupt and read the received packet status to determine the number of bytes received, then read the receive FIFO accordingly. Following this, unmask the RXFLVL interrupt.

6. The core generates the RXFLVL interrupt for the transfer completion status entry in the receive FIFO.

7. The application must read and ignore the receive packet status when the receive packet status is not an IN data packet (USB_GRXSTSR.PKTSTS != 0b0010).

8. The core generates the XFERCOMPL interrupt as soon as the receive packet status is read.

9. In response to the XFERCOMPL interrupt, disable the channel (see Halting a Channel (p. 159) )

and stop writing the USB_HC2_CHAR register for further requests. The core writes a channel disable request to the non-periodic request queue as soon as the USB_HC2_CHAR register is written.

10.The core generates the RXFLVL interrupt as soon as the halt status is written to the receive FIFO.

11.Read and ignore the receive packet status.

12.The core generates a CHHLTD interrupt as soon as the halt status is popped from the receive FIFO.

13.In response to the CHHLTD interrupt, de-allocate the channel for other transfers.

Note

For Bulk/Control IN transfers, the application must write the requests when the Request queue space is available, and until the XFERCOMPL interrupt is received.

14.4.3.6.5.2 Handling Interrupts

The channel-specific interrupt service routine for bulk and control IN transactions in Slave mode is shown in the following code samples.

Interrupt Service Routine for Bulk/Control IN Transactions in Slave Mode

Unmask (XACTERR/XFERCOMPL/BBLERR/STALL/DATATGLERR) if (XFERCOMPL) { Reset Error Count Unmask CHHLTD Disable Channel Reset Error Count Mask ACK } else if (XACTERR or BBLERR or STALL) { Unmask CHHLTD Disable Channel if (XACTERR) { Increment Error Count Unmask ACK } } else if (CHHLTD) { Mask CHHLTD if (Transfer Done or (Error_count == 3)) { De-allocate Channel } else { Re-initialize Channel } 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

165

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

} else if (ACK) { Reset Error Count Mask ACK } else if (DATATGLERR) { Reset Error Count }

14.4.3.6.6 Control Transactions in DMA Mode

Setup, Data, and Status stages of a control transfer must be performed as three separate transfers.

Setup- and Data- or Status-stage OUT transactions are performed similarly to the bulk OUT transactions

explained in Bulk and Control OUT/SETUP Transactions in DMA Mode (p. 166) . Data- or Status-

stage IN transactions are performed similarly to the bulk IN transactions explained in Bulk and Control IN Transactions in DMA Mode (p. 170) . For all three stages, the application is expected to set the

USB_HC1_CHAR.EPTYPE field to Control. During the Setup stage, the application is expected to set the USB_HC1_TSIZ.PID field to SETUP.

14.4.3.6.7 Bulk and Control OUT/SETUP Transactions in DMA Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 158) .

This section discusses the following topics:

• Overview (p. 166) • Normal Bulk and Control OUT/SETUP Operations (p. 166) • NAK Handling with DMA (p. 166)

• Handling Interrupts (p. 168)

14.4.3.6.7.1 Overview

• The application is attempting to send two maximum-packet-size packets (transfer size = 1,024 bytes).

• The Non-periodic Transmit FIFO can hold two packets (128 bytes for FS).

• The Non-periodic Request Queue depth = 4.

14.4.3.6.7.2 Normal Bulk and Control OUT/SETUP Operations

The sequence of operations in Figure 14.9 (p. 163) is as follows:

1. Initialize and enable channel 1 as explained in Channel Initialization (p. 158) .

2. The host starts fetching the first packet as soon as the channel is enabled. For DMA mode, the host uses the programmed DMA address to fetch the packet.

3. After fetching the last DWORD of the second (last) packet, the host masks channel 1 internally for further arbitration.

4. The host generates a CHHLTD interrupt as soon as the last packet is sent.

5. In response to the CHHLTD interrupt, de-allocate the channel for other transfers.

The channel-specific interrupt service routine for bulk and control OUT/SETUP transactions in DMA

mode is shown in Handling Interrupts (p. 168) .

14.4.3.6.7.3 NAK Handling with DMA

1. The Host sends a Bulk OUT Transaction.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

166

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

2. The Device responds with NAK.

3. If the application has unmasked NAK, the core generates the corresponding interrupt(s) to the application.

The application is not required to service these interrupts, since the core takes care of rewinding of buffer pointers and re-initializing the Channel without application intervention.

4. When the Device returns an ACK, the core continues with the transfer.

Optionally, the application can utilize these interrupts. If utilized by the application: • The NAK interrupt is masked by the application.

• The core does not generate a separate interrupt when NAK is received by the Host functionality.

Application Programming Flow

1. The application programs a channel to do a bulk transfer for a particular data size in each transaction.

• Packet Data size can be up to 512 KBytes • Zero-length data must be programmed as a separate transaction.

2. Program the transfer size register with: • Transfer size • Packet Count 3. Program the DMA address.

4. Program the USB_HCx_CHAR to enable the channel.

5. The Interrupt handling by the application is as depicted in the flow diagram.

Note

The NAK interrupts are still generated internally. The application can mask off these interrupts from reaching it. The application can use these interrupts optionally.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

167

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.10. Normal Bulk/Control OUT/SETUP and Bulk/Control IN Transactions in DMA Mode

AHB Host USB Device

init_ reg( ch_2)

1 1 Application

init_ reg( ch_1) 1 MPS

2 Non- Periodic Request Queue

Assum e t hat t his queue can hold 4 ent ries.

1 MPS

2

ch_1 ch_2 ch_1 ch_2 OUT D ATA0 M PS

3

ACK IN

5

De- allocat e (ch_1) 1 MPS CHHLTD int errupt

3 5

ch_1 ch_2 ch_2 ch_2

4

D ATA0 ACK OUT D ATA1 M PS ACK IN D ATA1

4

1 MPS ACK ch_2

6 7

CHHLTD int errupt De- allocat e (ch_2)

8 14.4.3.6.7.4 Handling Interrupts

The channel-specific interrupt service routine for bulk and control OUT/SETUP transactions in DMA mode is shown in the following code samples.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

168

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.11. Interrupt Service Routine for Bulk/Control OUT Transaction in DMA Mode

St art Unm asked t he required USB_HAINTMSK and USB_HCx _INTMSK st at us bit s Int errupt ?

No yes Read USB_HAINT t o det erm ine t he channel which caused t he Int errupt and read t he corresponding USB_HCx _INT No Service based on t he ot her int errupt st at us bit s nam ely: AHBERR, FRMOVRERR, BBLERR and DATATGLERR USB_HCx _INT.

CHHLTD = 1 ?

No USB_HCx _INT.

ACK = 1?

Yes, USB_HCx _INT.STALL = 1 or USB_HCx _INT.XFERCOMPL = 1 Yes , USB_HCx _INT.XACTERR = 1 Yes Reset Err_cnt No USB_HCx _INT.NAK = 1 / USB_HCx _INT.ACK = 1 Err_cnt = Err_cnt + 1 Yes 1. Err_cnt = 1 2. Re- init ialize channel 3. Reprogram Buffer point ers 1. Reset Err_cnt 2. Deallocat e channel 1. Reprogram Buffer point ers 2. Re- init ialize Channel No Err_cnt = = 3 ?

Yes Deallocat e Channel

In Figure 14.11 (p. 169) that the Interrupt Service Routine is not required to handle NAK responses.

This is the difference of proposed flow with respect to current flow. Similar flow is applicable for Control flow also.

The NAK status bits in USB_HCx_INT registers are updated. The application can unmask these interrupts when it requires the core to generate an interrupt for NAK. The NAK status is updated because during Xact_err scenarios, this status provides a means for the application to determine whether the Xact_err occurred three times consecutively or there were NAK responses in between two Xact_err.

This provides a mechanism for the application to reset the error counter accordingly. The application 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

169

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

must read the NAK/ACK along with the xact_err. If NAK/ACK is not set, the Xact_err count must be incremented otherwise application must initialize the Xact_err count to 1.

Bulk/Control OUT/SETUP

Unmask (CHHLTD) if (CHHLTD) { if (XFERCOMPL or STALL) { Reset Error Count (Error_count=1) Mask ACK De-allocate Channel } else if (XACTERR) { if (NAK/ACK) { Error_count = 1 Re-initialize Channel Rewind Buffer Pointers } else { Error_count = Error_count + 1 if (Error_count == 3) { De allocate channel } else { Re-initialize Channel Rewind Buffer Pointers } } } } else if (ACK) { Reset Error Count (Error_count=1) Mask ACK } As soon as the channel is enabled, the core attempts to fetch and write data packets, in multiples of the maximum packet size, to the transmit FIFO when space is available in the transmit FIFO and the Request queue. The core stops fetching as soon as the last packet is fetched.

14.4.3.6.8 Bulk and Control IN Transactions in DMA Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 158) .

A typical bulk or control IN operation in DMA mode is shown in Figure 14.10 (p. 168) . See channel

2 (ch_2).

The assumptions are:

1. The application is attempting to receive two maximum-packet-size packets (transfer size = 1,024 bytes).

2. The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDs per packet (72 bytes for FS).

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

170

www.silabs.com

Preliminary

3. The Non-periodic Request Queue depth = 4.

...the world's most energy friendly microcontrollers

14.4.3.6.8.1 Normal Bulk and Control IN Operations

The sequence of operations in Figure 14.10 (p. 168) is as follows:

1. Initialize and enable channel 2 as explained in Channel Initialization (p. 158) .

2. The host writes an IN request to the Request queue as soon as channel 2 receives the grant from the arbiter. (Arbitration is performed in a round-robin fashion, with fairness.).

3. The host starts writing the received data to the system memory as soon as the last byte is received with no errors.

4. When the last packet is received, the host sets an internal flag to remove any extra IN requests from the Request queue.

5. The host flushes the extra requests.

6. The final request to disable channel 2 is written to the Request queue. At this point, channel 2 is internally masked for further arbitration.

7. The host generates the CHHLTD interrupt as soon as the disable request comes to the top of the queue.

8. In response to the CHHLTD interrupt, de-allocate the channel for other transfers.

14.4.3.6.8.2 Handling Interrupts

The channel-specific interrupt service routine for bulk and control IN transactions in DMA mode is shown in the following flow:

Interrupt Service Routines for Bulk/Control Bulk/Control IN Transactions in DMA Mode Bulk/Control IN

Unmask (CHHLTD) if (CHHLTD) { if (XFERCOMPL or STALL or BBLERR) { Reset Error Count Mask ACK De-allocate Channel } else if (XACTERR) { if (Error_count == 2) { De-allocate Channel } else { Unmask ACK Unmask NAK Unmask DATATGLERR Increment Error Count Re-initialize Channel } } } else if (ACK or NAK or DATATGLERR) { Reset Error Count Mask ACK Mask NAK Mask DATATGLERR } 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

171

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.4.3.6.9 Interrupt OUT Transactions in Slave Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 158) . See Figure 14.7 (p. 161) and Figure 14.8 (p.

161) for read or write data to and from the FIFO in Slave mode.

A typical interrupt OUT operation in Slave mode is shown in Figure 14.12 (p. 173) . See channel 1

(ch_1). The assumptions are: • The application is attempting to send one packet in every frame (up to 1 maximum packet size), starting with the odd frame (transfer size = 1,024 bytes).

• The Periodic Transmit FIFO can hold one packet.

• Periodic Request Queue depth = 4.

14.4.3.6.9.1 Normal Interrupt OUT Operation

The sequence of operations in Figure 14.12 (p. 173) is as follows:

1. Initialize and enable channel 1 as explained in Channel Initialization (p. 158) . The application must

set the USB_HC1_CHAR.ODDFRM bit.

2. Write the first packet for channel 1. For a high-bandwidth interrupt transfer, the application must write the subsequent packets up to MC (maximum number of packets to be transmitted in the next frame times before switching to another channel).

3. Along with the last DWORD write of each packet, the host writes an entry to the Periodic Request Queue.

4. The host attempts to send an OUT token in the next (odd) frame.

5. The host generates an XFERCOMPL interrupt as soon as the last packet is transmitted successfully.

6. In response to the XFERCOMPL interrupt, reinitialize the channel for the next transfer.

14.4.3.6.9.2 Handling Interrupts

The channel-specific interrupt service routine for Interrupt OUT transactions in Slave mode is shown in the following flow: 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

172

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.12. Normal Interrupt OUT/IN Transactions in Slave Mode

AHB Host USB Device

init_ reg(ch_2) set_ch_en ( ch_2)

1 1 2 2 Application

init_ reg( ch_1) writ e_t x_fifo (ch_1) 1 MPS

3

ch_1 ch_2

4

Periodic Request Queue Assum e t hat t his queue can hold

3

OUT D ATA0 M PS Odd fram e

5 6

init_ reg( ch_1) writ e_t x_fifo (ch_1) XFERCOMPL int errupt

5 4

ACK IN read_rx_st s read_rx_fifo read_rx_st s

7 6

1 MPS RXFLVL int errupt 1 MPS RXFLVL int errupt XFERCOMPL int errupt

8

ch_1 ch_2 D ATA0 ACK init_ reg(ch_2) set_ch_en ( ch_2)

9

Even fram e init_ reg( ch_1) writ e_t x_fifo (ch_1) XFERCOMPL int errupt 1 MPS OUT D ATA1 MPS ACK IN D ATA1

Interrupt Service Routine for Interrupt OUT Transactions in Slave Mode Interrupt OUT

Unmask (NAK/XACTERR/STALL/XFERCOMPL/FRMOVRUN) if (XFERCOMPL) { Reset Error Count Mask ACK De-allocate Channel } else if (STALL or FRMOVRUN) { Mask ACK Unmask CHHLTD Disable Channel if (STALL) { Transfer Done = 1 } 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

173

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

} else if (NAK or XACTERR) { Rewind Buffer Pointers Reset Error Count Mask ACK Unmask CHHLTD Disable Channel } else if (CHHLTD) { Mask CHHLTD if (Transfer Done or (Error_count == 3)) { De-allocate Channel } else { Re-initialize Channel (in next b_interval - 1 Frame) } } else if (ACK) { Reset Error Count Mask ACK } The application is expected to write the data packets into the transmit FIFO when the space is available in the transmit FIFO and the Request queue up to the count specified in the MC field before switching to another channel. The application uses the USB_GINTSTS.NPTXFEMP interrupt to find the transmit FIFO space.

14.4.3.6.10 Interrupt IN Transactions in Slave Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 158) . See Transmit FIFO Write Task in Slave Mode

and Receive FIFO Read Task in Slave Mode for read or write data to and from the FIFO in Slave mode.

A typical interrupt-IN operation in Slave mode is shown in Figure 14.12 (p. 173) . See channel 2 (ch_2).

The assumptions are: 1. The application is attempting to receive one packet (up to 1 maximum packet size) in every frame, starting with odd. (transfer size = 1,024 bytes).

2. The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDs per packet (1,031 bytes for FS).

3. Periodic Request Queue depth = 4.

14.4.3.6.10.1 Normal Interrupt IN Operation

The sequence of operations in Figure 14.12 (p. 173) (channel 2) is as follows:

1. Initialize channel 2 as explained in Channel Initialization (p. 158) . The application must set the

USB_HC2_CHAR.ODDFRM bit.

2. Set the USB_HC2_CHAR.CHENA bit to write an IN request to the Periodic Request Queue. For a high-bandwidth interrupt transfer, the application must write the USB_HC2_CHAR register MC (maximum number of expected packets in the next frame) times before switching to another channel.

3. The host writes an IN request to the Periodic Request Queue for each USB_HC2_CHAR register write with a CHENA bit set.

4. The host attempts to send an IN token in the next (odd) frame.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

174

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

5. As soon as the IN packet is received and written to the receive FIFO, the host generates an RXFLVL interrupt.

6. In response to the RXFLVL interrupt, read the received packet status to determine the number of bytes received, then read the receive FIFO accordingly. The application must mask the RXFLVL interrupt before reading the receive FIFO, and unmask after reading the entire packet.

7. The core generates the RXFLVL interrupt for the transfer completion status entry in the receive FIFO.

The application must read and ignore the receive packet status when the receive packet status is not an IN data packet (USB_GRXSTSR.PKTSTS != 0b0010).

8. The core generates an XFERCOMPL interrupt as soon as the receive packet status is read.

9. In response to the XFERCOMPL interrupt, read the USB_HC2_TSIZ.PKTCNT field. If

USB_HC2_TSIZ.PKTCNT != 0, disable the channel (as explained in Halting a Channel (p. 159)

) before re-initializing the channel for the next transfer, if any). If USB_HC2_TSIZ.PKTCNT == 0, reinitialize the channel for the next transfer. This time, the application must reset the USB_HC2_CHAR.ODDFRM bit.

14.4.3.6.10.2 Handling Interrupts

The channel-specific interrupt service routine for an interrupt IN transaction in Slave mode is a follows.

Interrupt IN

Unmask (NAK/XACTERR/XFERCOMPL/BBLERR/STALL/FRMOVRUN/DATATGLERR) if (XFERCOMPL) { Reset Error Count Mask ACK if (USB_HCx_TSIZ.PKTCNT == 0) { De-allocate Channel } else { Transfer Done = 1 Unmask CHHLTD Disable Channel } } else if (STALL or FRMOVRUN or NAK or DATATGLERR or BBLERR) { Mask ACK Unmask CHHLTD Disable Channel if (STALL or BBLERR) { Reset Error Count Transfer Done = 1 } else if (!FRMOVRUN) { Reset Error Count } } else if (XACTERR) { Increment Error Count Unmask ACK Unmask CHHLTD Disable Channel } else if (CHHLTD) { Mask CHHLTD 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

175

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

if (Transfer Done or (Error_count == 3)) { De-allocate Channel } else { Re-initialize Channel (in next b_interval - 1 Frame) } } else if (ACK) { Reset Error Count Mask ACK } The application is expected to write the requests for the same channel when the Request queue space is available up to the count specified in the MC field before switching to another channel (if any).

14.4.3.6.11 Interrupt OUT Transactions in DMA Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 158) .

A typical interrupt OUT operation in DMA mode is shown in Figure 14.13 (p. 177) . See channel 1

(ch_1). The assumptions are: • The application is attempting to transmit one packet in every frame (up to 1 maximum packet size of 1,024 bytes).

• The Periodic Transmit FIFO can hold one packet (1 KB for FS).

• Periodic Request Queue depth = 4.

14.4.3.6.11.1 Normal Interrupt OUT Operation

1. Initialize and enable channel 1 as explained in Channel Initialization (p. 158) .

2. The host starts fetching the first packet as soon the channel is enabled and writes the OUT request along with the last DWORD fetch. In high-bandwidth transfers, the host continues fetching the next packet (up to the value specified in the MC field) before switching to the next channel.

3. The host attempts to send the OUT token in the beginning of the next odd frame.

4. After successfully transmitting the packet, the host generates a CHHLTD interrupt.

5. In response to the CHHLTD interrupt, reinitialize the channel for the next transfer.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

176

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.13. Normal Interrupt OUT/IN Transactions in DMA Mode

init_ reg( ch_2)

1 1 Application

init_ reg( ch_1)

AHB

1 MPS

2 Host USB Periodic Request Queue

Assum e t hat t his queue can hold 4 ent ries.

Device

ch_1 ch_2

3 2

OUT DATA0 MPS Odd fram e

4 5

CHHLTD int errupt init_ reg( ch_1)

3

A CK IN 1 MPS DATA0 ACK 1 MPS CHHLTD int errupt

4

ch_1 ch_2 init_ reg( ch_2)

5

Even fram e init_ reg( ch_1) CHHLTD int errupt 1 MPS OUT D ATA1 MPS ACK IN DATA1

14.4.3.6.11.2 Handling Interrupts

The following code sample shows the channel-specific ISR for an interrupt OUT transaction in DMA mode.

Interrupt OUT

Unmask (CHHLTD) if (CHHLTD) { if (XFERCOMPL) { Reset Error Count Mask ACK if (Transfer Done) { De-allocate Channel } else { 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

177

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Re-initialize Channel (in next b_interval - 1 Frame) } } else if (STALL) { Transfer Done = 1 Reset Error Count Mask ACK De-allocate Channel } else if (NAK or FRMOVRUN) { Mask ACK Rewind Buffer Pointers Re-initialize Channel (in next b_interval - 1 Frame) if (NAK) { Reset Error Count } } else if (XACTERR) { if (Error_count == 2) { De-allocate Channel } else { Increment Error Count Rewind Buffer Pointers Unmask ACK Re-initialize Channel (in next b_interval - 1 Frame) } } } else if (ACK) { Reset Error Count Mask ACK } As soon as the channel is enabled, the core attempts to fetch and write data packets, in maximum packet size multiples, to the transmit FIFO when the space is available in the transmit FIFO and the Request queue. The core stops fetching as soon as the last packet is fetched (the number of packets is determined by the MC field of the USB_HCx_CHAR register).

14.4.3.6.12 Interrupt IN Transactions in DMA Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 158) .

A typical interrupt IN operation in DMA mode is shown in Figure 14.13 (p. 177) . See channel 2 (ch_2).

The assumptions are: • The application is attempting to receive one packet in every frame (up to 1 maximum packet size of 1,024 bytes).

• The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDs per packet (1,032 bytes for FS).

• Periodic Request Queue depth = 4.

14.4.3.6.12.1 Normal Interrupt IN Operation

The sequence of operations in Figure 14.13 (p. 177) (channel 2) is as follows:

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

178

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

1. Initialize and enable channel 2 as explained in Channel Initialization (p. 158) .

2. The host writes an IN request to the Request queue as soon as the channel 2 gets the grant from the arbiter (round-robin with fairness). In high-bandwidth transfers, the host writes consecutive writes up to MC times.

3. The host attempts to send an IN token at the beginning of the next (odd) frame.

4. As soon the packet is received and written to the receive FIFO, the host generates a CHHLTD interrupt.

5. In response to the CHHLTD interrupt, reinitialize the channel for the next transfer.

14.4.3.6.12.2 Handling Interrupts

The channel-specific interrupt service routine for Interrupt IN transactions in DMA mode is as follows.

Interrupt Service Routine for Interrupt IN Transactions in DMA Mode Unmask (CHHLTD) if (CHHLTD) { if (XFERCOMPL) { Reset Error Count Mask ACK if (Transfer Done) { De-allocate Channel } else { Re-initialize Channel (in next b_interval - 1 Frame) } } else if (STALL or BBLERR) { Reset Error Count Mask ACK De-allocate Channel } else if (NAK or DATATGLERR or FRMOVRUN) { Mask ACK Re-initialize Channel (in next b_interval - 1 Frame) if (DATATGLERR or NAK) { Reset Error Count } } else if (XACTERR) { if (Error_count == 2) { De-allocate Channel } else { Increment Error Count Unmask ACK Re-initialize Channel (in next b_interval - 1 Frame) } } } else if (ACK) { Reset Error Count Mask ACK 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

179

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

} As soon as the channel is enabled, the core attempts to write the requests into the Request queue when the space is available up to the count specified in the MC field.

14.4.3.6.13 Isochronous OUT Transactions in Slave Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the connected device, it must

initialize a channel as described in Channel Initialization (p. 158) . See TFigure 14.7 (p. 161) and Figure 14.8 (p. 161) for read or write data to and from the FIFO in Slave mode.

A typical isochronous OUT operation in Slave mode is shown in Figure 14.14 (p. 181) . See channel

1 (ch_1). The assumptions are: • The application is attempting to send one packet every frame (up to 1 maximum packet size), starting with an odd frame. (transfer size = 1,024 bytes).

• The Periodic Transmit FIFO can hold one packet (1 KB).

• Periodic Request Queue depth = 4.

14.4.3.6.13.1 Normal Isochronous OUT Operation

The sequence of operations in Figure 14.14 (p. 181) (channel 1) is as follows:

1. Initialize and enable channel 1 as explained in Channel Initialization (p. 158) . The application must

set the USB_HC1_CHAR.ODDFRM bit.

2. Write the first packet for channel 1. For a high-bandwidth isochronous transfer, the application must write the subsequent packets up to MC (maximum number of packets to be transmitted in the next frame) times before switching to another channel.

3. Along with the last DWORD write of each packet, the host writes an entry to the Periodic Request Queue.

4. The host attempts to send the OUT token in the next frame (odd).

5. The host generates the XFERCOMPL interrupt as soon as the last packet is transmitted successfully.

6. In response to the XFERCOMPL interrupt, reinitialize the channel for the next transfer.

14.4.3.6.13.2 Handling Interrupts

The channel-specific interrupt service routine for isochronous OUT transactions in Slave mode is shown in the following flow: 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

180

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.14. Normal Isochronous OUT/IN Transactions in Slave Mode

AHB Host USB Device

init_ reg( ch_2) set_ch_en ( ch_2)

1 1 2 2 Application

init_reg(ch_1) writ e_t x_fifo ( ch_1) 1 MPS

3

ch_1 ch_2

4 Periodic Requests Queue

Asum e t hat t his queue can hold 4 ent ries.

3 5

OUT DAT A0 MPS Odd fram e

6

XFERCOMPL int errupt init_reg(ch_1) writ e_t x_fifo ( ch_1)

4

IN read_rx_st s read_rx_fifo

6

1 MPS RXFLVL int errupt 1 MPS RXFLVL int errupt

5

DAT A0 read_rx_st s

7

XFERCOMPL int errupt

8

ch_1 ch_2 init_ reg( ch_2) set_ch_en (ch_2)

9

Even fram e OUT DAT A0 MPS XFERCOMPL int errupt init_reg(ch_1) writ e_t x_fifo ( ch_1) 1 MPS IN DATA 0

Interrupt Service Routine for Isochronous OUT Transactions in Slave Mode Isochronous OUT

Unmask (FRMOVRUN/XFERCOMPL) if (XFERCOMPL) { De-allocate Channel } else if (FRMOVRUN) { Unmask CHHLTD Disable Channel } else if (CHHLTD) { Mask CHHLTD De-allocate Channel } 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

181

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.4.3.6.14 Isochronous IN Transactions in Slave Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 158) . See Figure 14.7 (p. 161) and Figure 14.8 (p.

161) for read or write data to and from the FIFO in Slave mode.

A typical isochronous IN operation in Slave mode is shown in Figure 14.14 (p. 181) . See channel 2

(ch_2). The assumptions are: • The application is attempting to receive one packet (up to 1 maximum packet size) in every frame starting with the next odd frame. (transfer size = 1,024 bytes).

• The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDs per packet (1,031 bytes for FS).

• Periodic Request Queue depth = 4.

14.4.3.6.14.1 Normal Isochronous IN Operation

The sequence of operations in Figure 14.14 (p. 181) (channel 2) is as follows:

1. Initialize channel 2 as explained in Channel Initialization (p. 158) . The application must set the

USB_HC2_CHAR.ODDFRM bit.

2. Set the USB_HC2_CHAR.CHENA bit to write an IN request to the Periodic Request Queue. For a high-bandwidth isochronous transfer, the application must write the USB_HC2_CHAR register MC (maximum number of expected packets in the next frame) times before switching to another channel.

3. The host writes an IN request to the Periodic Request Queue for each USB_HC2_CHAR register write with the CHENA bit set.

4. The host attempts to send an IN token in the next odd frame.

5. As soon as the IN packet is received and written to the receive FIFO, the host generates an RXFLVL interrupt.

6. In response to the RXFLVL interrupt, read the received packet status to determine the number of bytes received, then read the receive FIFO accordingly. The application must mask the RXFLVL interrupt before reading the receive FIFO, and unmask it after reading the entire packet.

7. The core generates an RXFLVL interrupt for the transfer completion status entry in the receive FIFO.

This time, the application must read and ignore the receive packet status when the receive packet status is not an IN data packet (USB_GRXSTSR.PKTSTS != 0b0010).

8. The core generates an XFERCOMPL interrupt as soon as the receive packet status is read.

9. In response to the XFERCOMPL interrupt, read the USB_HC2_TSIZ.PKTCNT field. If

USB_HC2_TSIZ.PKTCNT != 0, disable the channel (as explained in Halting a Channel (p. 159)

) before re-initializing the channel for the next transfer, if any. If USB_HC2_TSIZ.PKTCNT == 0, reinitialize the channel for the next transfer. This time, the application must reset the USB_HC2_CHAR.ODDFRM bit.

14.4.3.6.14.2 Handling Interrupts

The channel-specific interrupt service routine for an isochronous IN transaction in Slave mode is as follows.

Isochronous IN

Unmask (XACTERR/XFERCOMPL/FRMOVRUN/BBLERR) if (XFERCOMPL or FRMOVRUN) { if (XFERCOMPL and (USB_HCx_TSIZ.PKTCNT == 0)) 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

182

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

{ Reset Error Count De-allocate Channel } else { Unmask CHHLTD Disable Channel } } else if (XACTERR or BBLERR) { Increment Error Count Unmask CHHLTD Disable Channel } else if (CHHLTD) { Mask CHHLTD if (Transfer Done or (Error_count == 3)) { De-allocate Channel } else { Re-initialize Channel } }

14.4.3.6.15 Isochronous OUT Transactions in DMA Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 158) .

A typical isochronous OUT operation in DMA mode is shown in Figure 14.15 (p. 184) . See channel

1 (ch_1). The assumptions are: • The application is attempting to transmit one packet every frame (up to 1 maximum packet size of 1,024 bytes).

• The Periodic Transmit FIFO can hold one packet (1 KB).

• Periodic Request Queue depth = 4.

14.4.3.6.15.1 Normal Isochronous OUT Operation

1. Initialize and enable channel 1 as explained in Channel Initialization (p. 158) .

2. The host starts fetching the first packet as soon as the channel is enabled, and writes the OUT request along with the last DWORD fetch. In high-bandwidth transfers, the host continues fetching the next packet (up to the value specified in the MC field) before switching to the next channel.

3. The host attempts to send an OUT token in the beginning of the next (odd) frame.

4. After successfully transmitting the packet, the host generates a CHHLTD interrupt.

5. In response to the CHHLTD interrupt, reinitialize the channel for the next transfer.

14.4.3.6.15.2 Handling Interrupts

The channel-specific interrupt service routine for Isochronous OUT transactions in DMA mode is shown in the following flow: 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

183

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.15. Normal Isochronous OUT/IN Transactions in DMA Mode

init_ reg( ch_2)

1 1 Application

init_reg(ch_1)

AHB

1 MPS

2 Host USB Periodic Request Queue

Assum e t hat t his queue can hold 4 ent ries.

Device

ch_1 ch_2

3 2 4

OUT D ATA0 M PS Odd fram e

5

CHHLTD int errupt init_reg(ch_1)

3

IN 1 MPS D ATA0 1 MPS CHHLTD int errupt

4

ch_1 ch_2 init_ reg( ch_2)

5

Even fram e init_reg(ch_1) CHHLTD int errupt 1 MPS OUT D ATA0 M PS IN D ATA0

Interrupt Service Routine for Isochronous OUT Transactions in DMA Mode Isochronous OUT

Unmask (CHHLTD) if (CHHLTD) { if (XFERCOMPL or FRMOVRUN) { De-allocate Channel } }

14.4.3.6.16 Isochronous IN Transactions in DMA Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 158) .

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

184

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

A typical isochronous IN operation in DMA mode is shown in Figure 14.15 (p. 184) . See channel 2

(ch_2). The assumptions are: • The application is attempting to receive one packet in every frame (up to 1 maximum packet size of 1,024 bytes).

• The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDS per packet (1,031 bytes).

• Periodic Request Queue depth = 4.

14.4.3.6.16.1 Normal Isochronous IN Operation

The sequence of operations in Figure 14.15 (p. 184) (channel 2) is as follows:

1. Initialize and enable channel 2 as explained in Channel Initialization (p. 158) .

2. The host writes an IN request to the Request queue as soon as the channel 2 gets the grant from the arbiter (round-robin with fairness). In high-bandwidth transfers, the host performs consecutive writes up to MC times.

3. The host attempts to send an IN token at the beginning of the next (odd) frame.

4. As soon the packet is received and written to the receive FIFO, the host generates a CHHLTD interrupt.

5. In response to the CHHLTD interrupt, reinitialize the channel for the next transfer.

14.4.3.6.16.2 Handling Interrupts

The channel-specific interrupt service routine for an isochronous IN transaction in DMA mode is as follows.

Isochronous IN

Unmask (CHHLTD) if (CHHLTD) { if (XFERCOMPL or FRMOVRUN) { if (XFERCOMPL and (USB_HCx_TSIZ.PKTCNT == 0)) { Reset Error Count De-allocate Channel } else { De-allocate Channel } } else if (XACTERR or BBLERR) { if (Error_count == 2) { De-allocate Channel } else { Increment Error Count Re-enable Channel (in next b_interval - 1 Frame) } } } 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

185

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.4.4 Device Programming Model

Before you program the Device, be sure to read Overview: Programming the Core (p. 151) and Modes of operation (p. 155)

14.4.4.1 Endpoint Initialization

This section addresses the following topics:

• Initialization on USB Reset (p. 186) • Initialization on Enumeration Completion (p. 186)

• Initialization on SetAddress Command (p. 187) • Initialization on SetConfiguration/SetInterface Command (p. 187) • Endpoint Activation (p. 187) • Endpoint Deactivation (p. 187)

• Device DMA/Slave Mode Initialization (p. 188)

14.4.4.1.1 Initialization on USB Reset

1. Set the NAK bit for all OUT endpoints • USB_DOEPx_CTL.SNAK = 1 (for all OUT endpoints) 2. Unmask the following interrupt bits: • USB_USB_DAINTMSK.INEP0 = 1 (control 0 IN endpoint) • USB_USB_DAINTMSK.OUTEP0 = 1 (control 0 OUT endpoint) • USB_DOEPMSK.SETUP = 1 • USB_DOEPMSK.XFERCOMPL = 1 • USB_DIEPMSK.XFERCOMPL = 1 • USB_DIEPMSK.TIMEOUTMSK = 1

3. To transmit or receive data, the device must initialize more registers as specified in Device DMA/ Slave Mode Initialization (p. 188) .

4. Set up the Data FIFO RAM for each of the FIFOs • Program the USB_GRXFSIZ Register, to be able to receive control OUT data and setup data. At a minimum, this must be equal to 1 max packet size of control endpoint 0 + 2 DWORDs (for the status of the control OUT data packet) + 10 DWORDs (for setup packets).

• Program the Device IN Endpoint Transmit FIFO size register (depending on the FIFO number chosen), to be able to transmit control IN data. At a minimum, this must be equal to 1 max packet size of control endpoint 0.

5. Program the following fields in the endpoint-specific registers for control OUT endpoint 0 to receive a SETUP packet • USB_DOEP0TSIZ.SUPCNT = 3 (to receive up to 3 back-to-back SETUP packets) • In DMA mode, USB_DOEP0DMAADDR register with a memory address to store any SETUP packets received At this point, all initialization required to receive SETUP packets is done, except for enabling control OUT endpoint 0 in DMA mode.

14.4.4.1.2 Initialization on Enumeration Completion

1. On the Enumeration Done interrupt (USB_GINTSTS.ENUMDONE, read the USB_DSTS register to determine the enumeration speed.

2. Program the USB_DIEP0CTL.MPS field to set the maximum packet size. This step configures control endpoint 0. The maximum packet size for a control endpoint depends on the enumeration speed.

3. In DMA mode, program the USB_DOEP0CTL register to enable control OUT endpoint 0, to receive a SETUP packet.

• USB_DOEP0CTL.EPENA = 1 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

186

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

At this point, the device is ready to receive SOF packets and is configured to perform control transfers on control endpoint 0.

14.4.4.1.3 Initialization on SetAddress Command

This section describes what the application must do when it receives a SetAddress command in a SETUP packet.

1. Program the USB_DCFG register with the device address received in the SetAddress command 2. Program the core to send out a status IN packet.

14.4.4.1.4 Initialization on SetConfiguration/SetInterface Command

This section describes what the application must do when it receives a SetConfiguration or SetInterface command in a SETUP packet.

1. When a SetConfiguration command is received, the application must program the endpoint registers to configure them with the characteristics of the valid endpoints in the new configuration.

2. When a SetInterface command is received, the application must program the endpoint registers of the endpoints affected by this command.

3. Some endpoints that were active in the prior configuration or alternate setting are not valid in the new configuration or alternate setting. These invalid endpoints must be deactivated.

4. For details on a particular endpoint’s activation or deactivation, see Endpoint Activation (p. 187) and Endpoint Deactivation (p. 187) .

5. Unmask the interrupt for each active endpoint and mask the interrupts for all inactive endpoints in the USB_USB_DAINTMSK register.

6. Set up the Data FIFO RAM for each FIFO. See Data FIFO RAM Allocation (p. 232) for more detail.

7. After all required endpoints are configured, the application must program the core to send a status IN packet.

At this point, the device core is configured to receive and transmit any type of data packet.

14.4.4.1.5 Endpoint Activation

This section describes the steps required to activate a device endpoint or to configure an existing device endpoint to a new type.

1. Program the characteristics of the required endpoint into the following fields of the USB_DIEPx_CTL register (for IN or bidirectional endpoints) or the USB_DOEPx_CTL register (for OUT or bidirectional endpoints).

• Maximum Packet Size • USB Active Endpoint = 1 • Endpoint Start Data Toggle (for interrupt and bulk endpoints) • Endpoint Type • TxFIFO Number 2. Once the endpoint is activated, the core starts decoding the tokens addressed to that endpoint and sends out a valid handshake for each valid token received for the endpoint.

14.4.4.1.6 Endpoint Deactivation

This section describes the steps required to deactivate an existing endpoint.

1. In the endpoint to be deactivated, clear the USB Active Endpoint bit in the USB_DIEPx_CTL register (for IN or bidirectional endpoints) or the USB_DOEPx_CTL register (for OUT or bidirectional endpoints).

2. Once the endpoint is deactivated, the core ignores tokens addressed to that endpoint, resulting in a timeout on the USB.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

187

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.4.4.1.7 Device DMA/Slave Mode Initialization

The application must meed the following conditions to set up the device core to handle traffic.

• In Slave mode, USB_GINTMSK.NPTXFEMPMSK, and USB_GINTMSK.RXFLVLMSK must be unset.

• In DMA mode, the aforementioned interrupts must be masked.

14.4.4.1.8 Transfer Stop Process

When the core is operating as a device, use the following programing sequence if you want to stop any transfers (because of an interrupt from the host, typically a reset).

14.4.4.1.8.1 Transfer Stop Programming Flow for IN Endpoints

Sequence of operations: 1. Disable the IN endpoint by programming USB_DIEP0CTL/USB_DIEPx_CTL.EPDIS = 1.

2. Wait for the USB_DIEPx_INT.EPDISBLD interrupt, which indicates that the IN endpoint is completely disabled. When the EPDISBLD interrupt is asserted, the core clears the following bits: • USB_DIEP0CTL/USB_DIEPx_CTL.EPDIS = 0 • USB_DIEP0CTL/USB_DIEPx_CTL.EPENA = 0 3. Flush the TX FIFO by programming the following bits: • USB_GRSTCTL.TXFFLSH = 1 • USB_GRSTCTL.TXFNUM = FIFO number specific to endpoint 4. The application can start polling till USB_GRSTCTL.TXFFLSH is cleared. When this bit is cleared, it ensures that there is no data left in the TX FIFO.

14.4.4.1.8.2 Transfer Stop Programming Flow for OUT Endpoints

Sequence of operations: 1. Enable all OUT endpoints by setting USB_DOEP0CTL/USB_DOEPx_CTL.EPENA = 1.

2. Before disabling any OUT endpoint, the application must enable Global OUT NAK mode in the core,

according to the instructions in Setting the Global OUT NAK (p. 196) . This ensures that data in the

RX FIFO is sent to the application successfully. Set USB_DCTL.USB_DCTL.SGOUTNAK = 1.

3. Wait for the USB_GINTSTS.GOUTNAKEFF interrupt.

4. Disable all active OUT endpoints by programming the following register bits: • USB_DOEP0CTL/USB_DOEPx_CTL.EPENA = 1 • USB_DOEP0CTL/USB_DOEPx_CTL.EPDIS = 1 • USB_DOEP0CTL/USB_DOEPx_CTL.SNAK = 1 5. Wait for the USB_DOEP0INT/USB_DOEPx_INT.EPDISBLD interrupt for each OUT endpoint programmed in the previous step. The USB_DOEP0INT/USB_DOEPx_INT.EPDISBLD interrupt indicates that the corresponding OUT endpoint is completely disabled. When the EPDISBLD interrupt is asserted, the core clears the following bits: • USB_DOEP0CTL/USB_DOEPx_CTL.EPENA = 0 • USB_DOEP0CTL/USB_DOEPx_CTL.EPDIS = 0

Note

The application must not flush the Rx FIFO, as the Global OUT NAK effective interrupt earlier ensures that there is no data left in the Rx FIFO.

14.4.4.2 Device Programming Operations

Table 14.2 (p. 189) provides links to the programming sequence for different USB transaction types.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

188

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Table 14.2.

Device Mode Control Slave IN SETUP DMA

Generic Non-Periodic (Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode (p. 213) Generic Non-Periodic (Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode (p. 213)

OUT Data Transfers in Slave and DMA Modes (p. 190) OUT Data Transfers in Slave and DMA Modes (p. 190)

Bulk Slave DMA

Generic Non-Periodic (Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode (p. 213) Generic Non-Periodic (Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode (p. 213)

Interrupt Slave DMA

Generic Periodic IN (Interrupt and Isochronous) Data Transfers Without Thresholding (p. 218)

and Generic Periodic IN Data Transfers Without Thresholding Using the Periodic Transfer Interrupt Feature (p.

220)

Generic Periodic IN (Interrupt and Isochronous) Data Transfers Without Thresholding (p. 218)

and Generic Periodic IN Data Transfers Without Thresholding Using the Periodic Transfer Interrupt Feature (p.

220)

Isochronous Slave

Generic Periodic IN (Interrupt and Isochronous) Data Transfers Without Thresholding (p. 218)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

189

OUT

Generic Non-Isochronous OUT Data Transfers Without Thresholding in DMA and Slave Modes (p. 198) Generic Non-Isochronous OUT Data Transfers Without Thresholding in DMA and Slave Modes (p. 198) Generic Non-Isochronous OUT Data Transfers Without Thresholding in DMA and Slave Modes (p. 198) Generic Non-Isochronous OUT Data Transfers Without Thresholding in DMA and Slave Modes (p. 198) Generic Non-Isochronous OUT Data Transfers Without Thresholding in DMA and Slave Modes (p. 198)

and Generic Interrupt OUT Data Transfers Without Thresholding Using Periodic Transfer Interrupt Feature (p.

202)

Generic Non-Isochronous OUT Data Transfers Without Thresholding in DMA and Slave Modes (p. 198)

and Generic Interrupt OUT Data Transfers Without Thresholding Using Periodic Transfer Interrupt Feature (p.

202)

Control Read Transfers (SETUP, Data IN, Status OUT) (p. 193) and

Incomplete Isochronous OUT Data Transfers

www.silabs.com

DMA Preliminary

Generic Periodic IN (Interrupt and Isochronous) Data Transfers Without Thresholding (p. 218)

and Generic Periodic IN Data Transfers Without Thresholding Using the Periodic Transfer Interrupt Feature (p.

220)

...the world's most energy friendly microcontrollers

in DMA and Slave Modes (p. 206)

Control Read Transfers (SETUP, Data IN, Status OUT) (p. 193) and

Incomplete Isochronous OUT Data Transfers in DMA and Slave Modes (p. 206)

14.4.4.2.1 OUT Data Transfers in Slave and DMA Modes

This section describes the internal data flow and application-level operations during data OUT transfers and setup transactions.

14.4.4.2.1.1 Control Setup Transactions

This section describes how the core handles SETUP packets and the application’s sequence for handling setup transactions. To initialize the core after power-on reset, the application must follow the sequence

in Overview: Programming the Core (p. 151) . Before it can communicate with the host, it must initialize

an endpoint as described in Endpoint Initialization (p. 186) . See Packet Read from FIFO in Slave Mode (p. 195) .

Application Requirements

1. To receive a SETUP packet, the USB_DOEPx_TSIZ.SUPCNT field in a control OUT endpoint must be programmed to a non-zero value. When the application programs the SUPCNT field to a non zero value, the core receives SETUP packets and writes them to the receive FIFO, irrespective of the USB_DOEPx_CTL.NAK status and USB_DOEPx_CTL.EPENA bit setting. The SUPCNT field is decremented every time the control endpoint receives a SETUP packet. If the SUPCNT field is not programmed to a proper value before receiving a SETUP packet, the core still receives the SETUP packet and decrements the SUPCNT field, but the application possibly is not be able to determine the correct number of SETUP packets received in the Setup stage of a control transfer.

• USB_DOEPx_TSIZ.SUPCNT = 3 2. In DMA mode, the OUT endpoint must also be enabled, to transfer the received SETUP packet data from the internal receive FIFO to the external memory.

• USB_DOEPx_CTL.EPENA = 1 3. The application must always allocate some extra space in the Receive Data FIFO, to be able to receive up to three SETUP packets on a control endpoint.

• The space to be Reserved is (4 * n) + 6 DWORDs, where n is the number of control endpoints supported by the device. Three DWORDs are required for the first SETUP packet, 1 DWORD is required for the Setup Stage Done DWORD, and 6 DWORDs are required to store two extra SETUP packets among all control endpoints.

• 3 DWORDs per SETUP packet are required to store 8 bytes of SETUP data and 4 bytes of SETUP status (Setup Packet Pattern). The core reserves this space in the receive data • FIFO to write SETUP data only, and never uses this space for data packets.

4. In Slave mode, the application must read the 2 DWORDs of the SETUP packet from the receive FIFO.

In DMA mode, the core writes the 2 DWORDs of SETUP data to the memory.

5. The application must read and discard the Setup Stage Done DWORD from the receive FIFO.

Internal Data Flow

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

190

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

1. When a SETUP packet is received, the core writes the received data to the receive FIFO, without checking for available space in the receive FIFO and irrespective of the endpoint’s NAK and Stall bit settings.

• The core internally sets the IN NAK and OUT NAK bits for the control IN/OUT endpoints on which the SETUP packet was received.

2. For every SETUP packet received on the USB, 3 DWORDs of data is written to the receive FIFO, and the SUPCNT field is decremented by 1.

• The first DWORD contains control information used internally by the core • The second DWORD contains the first 4 bytes of the SETUP command • The third DWORD contains the last 4 bytes of the SETUP command 3. When the Setup stage changes to a Data IN/OUT stage, the core writes an entry (Setup Stage Done DWORD) to the receive FIFO, indicating the completion of the Setup stage.

4. On the AHB side, SETUP packets are emptied either by the DMA or the application. In DMA mode, the SETUP packets (2 DWORDs) are written to the memory location programmed in the USB_DOEPx_DMAADDR register, only if the endpoint is enabled. If the endpoint is not enabled, the data remains in the receive FIFO until the enable bit is set.

5. When either the DMA or the application pops the Setup Stage Done DWORD from the receive FIFO, the core interrupts the application with a USB_DOEPx_INT.SETUP interrupt, indicating it can process the received SETUP packet.

• The core clears the endpoint enable bit for control OUT endpoints.

Application Programming Sequence

1. Program the USB_DOEPx_TSIZ register.

• USB_DOEPx_TSIZ.SUPCNT = 3 2. In DMA mode, program the USB_DOEPx_DMAADDR register and USB_DOEPx_CTL register with the endpoint characteristics and set the Endpoint Enable bit (USB_DOEPx_CTL.EPENA).

• Endpoint Enable = 1 3. In Slave mode, wait for the USB_GINTSTS.RXFLVL interrupt and empty the data packets from the

receive FIFO, as explained in Packet Read from FIFO in Slave Mode (p. 195) . This step can be

repeated many times.

4. Assertion of the USB_DOEPx_INT.SETUP interrupt marks a successful completion of the SETUP Data Transfer.

• On this interrupt, the application must read the USB_DOEPx_TSIZ register to determine the number of SETUP packets received and process the last received SETUP packet.

• In DMA mode, the application must also determine if the interrupt bit USB_DOEPx_INT.BACK2BACKSETUP is set. This bit is set if the core has received more than three back-to-back SETUP packets. If this is the case, the application must ignore the USB_DOEPx_TSIZ.SUPCNT value and use the USB_DOEPx_DMAADDR directly to read out the last SETUP packet received. USB_DOEPx_DMAADDR-8 provides the pointer to the last valid SETUP data.

Note

If the application has not enabled EP0 before the host sends the SETUP packet, the core ACKs the SETUP packet and stores it in the FIFO, but does not write to the memory until EP0 is enabled. When the application enables the EP0 (first enable) and clears the NAK bit at the same time the Host sends DATA OUT, the DATA OUT is stored in the RxFIFO.

The OTG core then writes the setup data to the memory and disables the endpoint. Though the application expects a Transfer Complete interrupt for the Data OUT phase, this does not occur, because the SETUP packet, rather than the DATA OUT packet, enables EP0 the first time. Thus, the DATA OUT packet is still in the RxFIFO until the application re-enables EP0. The application must enable EP0 one more time for the core to process the DATA OUT packet.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

191

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Figure 14.16 (p. 192) charts this flow.

Figure 14.16. Processing a SETUP Packet

Wait for USB_DOEPx _INT.SETUP

No Back2Back Set up Int errupt bit set ?

Yes rem _supcnt = Rd_Reg(USB_DOEPx _TSIZ) Set up_addr = Rd_Reg(USB_DOEPx _DMA set up_cm d[31:0] = m em [4- 2 * rem _supcnt ] set up_cm d[63:32] = m em [5- 2 * rem _supcnt ] set up_cm d[31:0] = m em [set up_addr- 8] set up_cm d[63:32] = m em [set up_addr- 4] Find set up cm d t ype Read ct r- rd/ wr/ 2 st age Writ e set up_np_in_pkt Dat a IN phase 2- st age set up_np_in_pkt Sat a IN phase rcv_out _pkt Dat a OUT phase

14.4.4.2.1.2 Handling More Than Three Back-to-Back SETUP Packets

Per the USB 2.0 specification, normally, during a SETUP packet error, a host does not send more than three back-to-back SETUP packets to the same endpoint. However, the USB 2.0 specification does not limit the number of back-to-back SETUP packets a host can send to the same endpoint.

When this condition occurs, the core generates an interrupt (USB_DOEPx_INT.BACK2BACKSETUP).

In DMA mode, the core also rewinds the DMA address for that endpoint (USB_DOEPx_DMAADDR) and overwrites the first SETUP packet in system memory with the fourth, second with the fifth, and so on. If the BACK2BACKSETUP interrupt is asserted, the application must read the OUT endpoint DMA register (USB_DOEPx_DMAADDR) to determine the final SETUP data in system memory.

In DMA mode, the application can mask the BACK2BACKSETUP interrupt, but after receiving the DOEPINT.SETUP interrupt, the application can read the DOEPINT.BACK2BACKSETUP interrupt bit.

In Slave mode, the application can use the USB_GINTSTS.RXFLVL interrupt to read out the SETUP packets from the FIFO whenever the core receives the SETUP packet.

14.4.4.2.2 Control Transfers

This section describes the various types of control transfers.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

192

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.4.4.2.2.1 Control Write Transfers (SETUP, Data OUT, Status IN)

This section describes control write transfers.

Application Programming Sequence 1. Assertion of the USB_DOEPx_INT.SETUP Packet interrupt indicates that a valid SETUP packet

has been transferred to the application. See OUT Data Transfers in Slave and DMA Modes (p.

190) for more details. At the end of the Setup stage, the application must reprogram the

USB_DOEPx_TSIZ.SUPCNT field to 3 to receive the next SETUP packet.

2. If the last SETUP packet received before the assertion of the SETUP interrupt indicates a data OUT

phase, program the core to perform a control OUT transfer as explained in Generic Non-Isochronous OUT Data Transfers Without Thresholding in DMA and Slave Modes (p. 198) .

In DMA mode, the application must reprogram the USB_DOEPx_DMAADDR register to receive a control OUT data packet to a different memory location.

3. In a single OUT data transfer on control endpoint 0, the application can receive up to 64 bytes. If the application is expecting more than 64 bytes in the Data OUT stage, the application must re-enable the endpoint to receive another 64 bytes, and must continue to do so until it has received all the data in the Data stage.

4. Assertion of the USB_DOEPx_INT.Transfer Completed interrupt on the last data OUT transfer indicates the completion of the data OUT phase of the control transfer.

5. On completion of the data OUT phase, the application must do the following.

• To transfer a new SETUP packet in DMA mode, the application must re-enable the control OUT

endpoint as explained in OUT Data Transfers in Slave and DMA Modes (p. 190) .

• USB_DOEPx_CTL.EPENA = 1 • To execute the received Setup command, the application must program the required registers in the core. This step is optional, based on the type of Setup command received.

6. For the status IN phase, the application must program the core as described in Generic Non-Periodic

perform a data IN transfer.

7. Assertion of the USB_DIEPx_INT.XFERCOMPL interrupt indicates completion of the status IN phase of the control transfer.

8. The previous step must be repeated until the USB_DIEPx_INT.XFERCOMPL interrupt is detected on the endpoint, marking the completion of the control write transfer.

14.4.4.2.2.2 Control Read Transfers (SETUP, Data IN, Status OUT)

This section describes control read transfers.

Application Programming Sequence

1. Assertion of the USB_DOEPx_INT.SETUP Packet interrupt indicates that a valid SETUP packet

has been transferred to the application. See OUT Data Transfers in Slave and DMA Modes (p.

190) for more details. At the end of the Setup stage, the application must reprogram the

USB_DOEPx_TSIZ.SUPCNT field to 3 to receive the next SETUP packet.

2. If the last SETUP packet received before the assertion of the SETUP interrupt indicates a data IN

phase, program the core to perform a control IN transfer as explained in Generic Non-Periodic (Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode (p. 213) .

3. On a single IN data transfer on control endpoint 0, the application can transmit up to 64 bytes. To transmit more than 64 bytes in the Data IN stage, the application must re-enable the endpoint to transmit another 64 bytes, and must continue to do so, until it has transmitted all the data in the Data stage.

4. The previous step must be repeated until the USB_DIEPx_INT.XFERCOMPL interrupt is detected for every IN transfer on the endpoint.

5. The USB_DIEPx_INT.XFERCOMPL interrupt on the last IN data transfer marks the completion of the control transfer’s Data stage.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

193

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

6. To perform a data OUT transfer in the status OUT phase, the application must program the core as

described in OUT Data Transfers in Slave and DMA Modes (p. 190) .

• The application must program the USB_DCFG.NZSTSOUTHSHK handshake field to a proper setting before transmitting an data OUT transfer for the Status stage.

• In DMA mode, the application must reprogram the USB_DOEPx_DMAADDR register to receive the control OUT data packet to a different memory location.

7. Assertion of the USB_DOEPx_INT.XFERCOMPL interrupt indicates completion of the status OUT phase of the control transfer. This marks the successful completion of the control read transfer.

• To transfer a new SETUP packet in DMA mode, the application must re-enable the control OUT

endpoint as explained in OUT Data Transfers in Slave and DMA Modes (p. 190) .

• USB_DOEPx_CTL.EPENA = 1

14.4.4.2.2.3 Two-Stage Control Transfers (SETUP/Status IN)

This section describes two-stage control transfers.

Application Programming Sequence

1. Assertion of the USB_DOEPx_INT.SETUP interrupt indicates that a valid SETUP packet has

been transferred to the application. See OUT Data Transfers in Slave and DMA Modes (p.

190) for more detail. To receive the next SETUP packet, the application must reprogram the

USB_DOEPx_TSIZ.SUPCNT field to 3 at the end of the Setup stage.

2. Decode the last SETUP packet received before the assertion of the SETUP interrupt. If the packet indicates a two-stage control command, the application must do the following.

• To transfer a new SETUP packet in DMA mode, the application must re-enable the control OUT

endpoint. See OUT Data Transfers in Slave and DMA Modes (p. 190) for details.

• USB_DOEPx_CTL.EPENA = 1 • Depending on the type of Setup command received, the application can be required to program registers in the core to execute the received Setup command.

3. For the status IN phase, the application must program the core described in Generic Non-Periodic

perform a data IN transfer.

4. Assertion of the USB_DIEPx_INT.XFERCOMPL interrupt indicates the completion of the status IN phase of the control transfer.

5. The previous step must be repeated until the USB_DIEPx_INT.XFERCOMPL interrupt is detected on the endpoint, marking the completion of the two-stage control transfer.

Example: Two-Stage Control Transfer

These notes refer to Figure 14.17 (p. 195) .

1. SETUP packet #1 is received on the USB and is written to the receive FIFO, and the core responds with an ACK handshake. This handshake is lost and the host detects a timeout.

2. The SETUP packet in the receive FIFO results in a USB_GINTSTS.RXFLVL interrupt to the application, causing the application to empty the receive FIFO.

3. SETUP packet #2 on the USB is written to the receive FIFO, and the core responds with an ACK handshake.

4. The SETUP packet in the receive FIFO sends the application the USB_GINTSTS.RXFLVL interrupt and the application empties the receive FIFO.

5. After the second SETUP packet, the host sends a control IN token for the status phase. The core issues a NAK response to this token, and writes a Setup Stage Done entry to the receive FIFO. This entry results in a USB_GINTSTS.RXFLVL interrupt to the application, which empties the receive FIFO.

After reading out the Setup Stage Done DWORD, the core asserts the USB_DOEPx_INT.SETUP

packet interrupt to the application.

6. On this interrupt, the application processes SETUP Packet #2, decodes it to be a two-stage control command, and clears the control IN NAK bit.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

194

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• USB_DIEPx_CTL.CNAK = 1 7. When the application clears the IN NAK bit, the core interrupts the application with a USB_DIEPx_INT.INTKNTXFEMP. On this interrupt, the application enables the control IN endpoint with a USB_DIEPx_TSIZ.XFERSIZE of 0 and a USB_DIEPx_TSIZ.PKTCNT of 1. This results in a zero-length data packet for the status IN token on the USB.

8. At the end of the status IN phase, the core interrupts the application with a USB_DIEPx_INT.XFERCOMPL interrupt.

Figure 14.17. Two-Stage Control Transfer

Host USB Device Application 1

set up_ x act_1

3

set up_ x act_2 st at us_ x act_2 st at us_ x act_2 SETUP A CK Lo st S ETUP ACK IN NA K IN NAK IN(STATUS) .

ACK Ct l- IN NAK 1 1 RXFLVL INTR idle unt il int r rcv_out_ dat a RXF INTR LVL set up done idle unt il int r RX FLV L IN

4

TR

5

rcv_out_ dat a idle unt il int r rcv_out_ dat a SETUP Intr INTKNTXFEM P Clear IN NAK INTR sts data rdy idle unt il int r proc_ set up_pkt # 2 set up_ in_ np_ pkt XFERCOMP INTR L

8 7

idle unt il int r

6

XFERSIZE = 0 byt es PKTCNT = 1 EPENA = 1

14.4.4.2.2.4 Packet Read from FIFO in Slave Mode

This section describes how to read packets (OUT data and SETUP packets) from the receive FIFO in Slave mode.

1. On catching a USB_GINTSTS.RXFLVL interrupt, the application must read the Receive Status Pop register (USB_GRXSTSP).

2. The application can mask the USB_GINTSTS.RXFLVL interrupt USB_GINTMSK.RXFLVL = 0, until it has read the packet from the receive FIFO.

by writing to 3. If the received packet’s byte count is not 0, the byte count amount of data is popped from the receive Data FIFO and stored in memory. If the received packet byte count is 0, no data is popped from the Receive Data FIFO.

4. The receive FIFO’s packet status readout indicates one of the following.

5. Global OUT NAK Pattern: PKTSTS = Global OUT NAK, BCNT = 0x000, EPNUM = Dont Care (0x0), DPID = Dont Care (0b00). This data indicates that the global OUT NAK bit has taken effect.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

195

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

a. SETUP Packet Pattern: PKTSTS = SETUP, BCNT = 0x008, EPNUM = Control EP Num, DPID = D0. This data indicates that a SETUP packet for the specified endpoint is now available for reading from the receive FIFO.

b. Setup Stage Done Pattern: PKTSTS = Setup Stage Done, BCNT = 0x0, EPNUM = Control EP Num, DPID = Don’t Care (0b00). This data indicates that the Setup stage for the specified endpoint has completed and the Data stage has started. After this entry is popped from the receive FIFO, the core asserts a Setup interrupt on the specified control OUT endpoint.

c. Data OUT Packet Pattern: PKTSTS = DataOUT, BCNT = size of the Received data OUT packet, EPNUM = EPNum on which the packet was received, DPID = Actual Data PID.

d. Data Transfer Completed Pattern: PKTSTS = Data OUT Transfer Done, BCNT = 0x0, EPNUM = OUT EP Num on which the data transfer is complete, DPID = Dont Care (0b00). This data indicates that a OUT data transfer for the specified OUT endpoint has completed. After this entry is popped from the receive FIFO, the core asserts a Transfer Completed interrupt on the specified OUT endpoint.

The encoding for the PKTSTS is listed in Section 14.6 (p. 252) .

6. After the data payload is popped from the receive FIFO, the USB_GINTSTS.RXFLVL interrupt must be unmasked.

7. Steps 1–5 are repeated every time the application detects assertion of the interrupt line due to USB_GINTSTS.RXFLVL. Reading an empty receive FIFO can result in undefined core behavior.

Figure 14.18 (p. 196) provides a flow chart of this procedure.

Figure 14.18. Receive FIFO Packet Read in Slave Mode

wait unt il USB_GINTSTS.RXFLVL

rd_dat a = rd_reg(USB_RXSTSP) packet st ore in m em ory Y rd_dat a.BCNT = 0 N m em [0:dword_cnt - 1] = rd_rx fifo(rd_dat a.EPNUM, dword_cnt ) dword_cnt = BCNT[11:2] + (BCNT[1] | BCNT[0]) rcv_out _pkt ()

14.4.4.2.2.5 Setting the Global OUT NAK

Internal Data Flow 1. When the application sets the Global OUT NAK (USB_DCTL.SGOUTNAK), the core stops writing data, except SETUP packets, to the receive FIFO. Irrespective of the space availability in the receive FIFO, non-isochronous OUT tokens receive a NAK handshake response, and the core ignores isochronous OUT data packets 2. The core writes the Global OUT NAK pattern to the receive FIFO. The application must reserve

enough receive FIFO space to write this data pattern. See Data FIFO RAM Allocation (p. 232) .

3. When either the core (in DMA mode) or the application (in Slave mode) pops the Global OUT NAK pattern DWORD from the receive FIFO, the core sets the USB_GINTSTS.GOUTNAKEFF interrupt.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

196

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

4. Once the application detects this interrupt, it can assume that the core is in Global OUT NAK mode.

The application can clear this interrupt by clearing the USB_DCTL.SGOUTNAK bit.

Application Programming Sequence

1. To stop receiving any kind of data in the receive FIFO, the application must set the Global OUT NAK bit by programming the following field.

• USB_DCTL.SGOUTNAK = 1 2. Wait for the assertion of the interrupt USB_GINTSTS.GOUTNAKEFF. When asserted, this interrupt indicates that the core has stopped receiving any type of data except SETUP packets.

3. The application can receive valid OUT packets after it has set USB_DCTL.SGOUTNAK and before the core asserts the USB_GINTSTS.GOUTNAKEFF interrupt.

4. The application can temporarily USB_GINTMSK.GOUTNAKEFFMSK bit.

mask this interrupt by writing to the • USB_GINTMSK.GINNAKEFFMSK = 0 5. Whenever the application is ready to exit the Global OUT NAK mode, it must clear the USB_DCTL.SGOUTNAK bit. This also clears the USB_GINTSTS.GOUTNAKEFF interrupt.

• USB_DCTL.CGOUTNAK = 1 6. If the application has masked this interrupt earlier, it must be unmasked as follows: • USB_GINTMSK.GOUTNAKEFFMSK = 1

14.4.4.2.2.6 Disabling an OUT Endpoint

The application must use this sequence to disable an OUT endpoint that it has enabled.

Application Programming Sequence

1. Before disabling any OUT endpoint, the application must enable Global OUT NAK mode in the core,

as described in Setting the Global OUT NAK (p. 196) .

• USB_DCTL.SGOUTNAK = 1 • Wait for the USB_GINTSTS.GOUTNAKEFF interrupt 2. Disable the required OUT endpoint by programming the following fields.

• USB_DOEPx_CTL.EPDIS = 1 • USB_DOEPx_CTL.SNAK = 1 3. Wait for the USB_DOEPx_INT.EPDISBLD interrupt, which indicates that the OUT endpoint is completely disabled. When the EPDISBLD interrupt is asserted, the core also clears the following bits.

• USB_DOEPx_CTL.EPDIS = 0 • USB_DOEPx_CTL.EPENA = 0 4. The application must clear the Global OUT NAK bit to start receiving data from other non-disabled OUT endpoints.

• USB_DCTL.SGOUTNAK = 0

14.4.4.2.2.7 Stalling a Non-Isochronous OUT Endpoint

This section describes how the application can stall a non-isochronous endpoint.

1. Put the core in the Global OUT NAK mode, as described in Setting the Global OUT NAK (p. 196) .

2. Disable the required endpoint, as described in Section 14.4.4.2.2.6 (p. 197) .

• When disabling the endpoint, instead of setting the USB_DOEPx_CTL.SNAK bit, set USB_DOEPx_CTL.STALL = 1.

• The Stall bit always takes precedence over the NAK bit.

3. When the application is ready to end the STALL handshake for the endpoint, the USB_DOEPx_CTL.STALL bit must be cleared.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

197

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

4. If the application is setting or clearing a STALL for an endpoint due to a SetFeature.Endpoint Halt or ClearFeature.Endpoint Halt command, the Stall bit must be set or cleared before the application sets up the Status stage transfer on the control endpoint.

14.4.4.2.2.8 Generic Non-Isochronous OUT Data Transfers in DMA and Slave Modes

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the host, it must initialize an endpoint

as described in Endpoint Initialization (p. 186) . See Packet Read from FIFO in Slave Mode (p. 195) .

This section describes a regular non-isochronous OUT data transfer (control, bulk, or interrupt).

Application Requirements

1. Before setting up an OUT transfer, the application must allocate a buffer in the memory to accommodate all data to be received as part of the OUT transfer, then program that buffer’s size and start address (in DMA mode) in the endpoint-specific registers.

1. For OUT transfers, the Transfer Size field in the endpoint’s Transfer Size register must be a multiple of the maximum packet size of the endpoint, adjusted to the DWORD boundary.

if (mps[epnum] mod 4) == 0 transfer size[epnum] = n * (mps[epnum]) //Dword Aligned else transfer size[epnum] = n * (mps[epnum] + 4 - (mps[epnum] mod 4)) //Non Dword Aligned packet count[epnum] = n n > 0 2. In DMA mode, the core stores a received data packet in the memory, always starting on a DWORD boundary. If the maximum packet size of the endpoint is not a multiple of 4, the core inserts byte pads at end of a maximum-packet-size packet up to the end of the DWORD.

3. On any OUT endpoint interrupt, the application must read the endpoint’s Transfer Size register to calculate the size of the payload in the memory. The received payload size can be less than the programmed transfer size.

• Payload size in memory = application-programmed initial transfer size – core updated final transfer size • Number of USB packets in which this payload was received = application-programmed initial packet count – core updated final packet count

Internal Data Flow

1. The application must set the Transfer Size and Packet Count fields in the endpoint-specific registers, clear the NAK bit, and enable the endpoint to receive the data.

2. Once the NAK bit is cleared, the core starts receiving data and writes it to the receive FIFO, as long as there is space in the receive FIFO. For every data packet received on the USB, the data packet and its status are written to the receive FIFO. Every packet (maximum packet size or short packet) written to the receive FIFO decrements the Packet Count field for that endpoint by 1.

• OUT data packets received with Bad Data CRC are flushed from the receive FIFO automatically.

• After sending an ACK for the packet on the USB, the core discards non-isochronous OUT data packets that the host, which cannot detect the ACK, re-sends. The application does not detect multiple back-to-back data OUT packets on the same endpoint with the same data PID. In this case the packet count is not decremented.

• If there is no space in the receive FIFO, isochronous or non-isochronous data packets are ignored and not written to the receive FIFO. Additionally, non-isochronous OUT tokens receive a NAK handshake reply.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

198

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• In all the above three cases, the packet count is not decremented because no data is written to the receive FIFO.

3. When the packet count becomes 0 or when a short packet is received on the endpoint, the NAK bit for that endpoint is set. Once the NAK bit is set, the isochronous or non-isochronous data packets are ignored and not written to the receive FIFO, and non-isochronous OUT tokens receive a NAK handshake reply.

4. After the data is written to the receive FIFO, either the application (in Slave mode) or the core’s DMA engine (in DMA mode), reads the data from the receive FIFO and writes it to external memory, one packet at a time per endpoint.

5. At the end of every packet write on the AHB to external memory, the transfer size for the endpoint is decremented by the size of the written packet.

6. The OUT Data Transfer Completed pattern for an OUT endpoint is written to the receive FIFO on one of the following conditions.

• The transfer size is 0 and the packet count is 0 • The last OUT data packet written to the receive FIFO is a short packet (0 <= packet size < maximum packet size) 7. When either the application or the DMA pops this entry (OUT Data Transfer Completed), a Transfer Completed interrupt is generated for the endpoint and the endpoint enable is cleared.

Application Programming Sequence

1. Program the USB_DOEPx_TSIZ register for the transfer size and the corresponding packet count.

Additionally, in DMA mode, program the USB_DOEPx_DMAADDR register.

2. Program the USB_DOEPx_CTL register with the endpoint characteristics, and set the Endpoint Enable and ClearNAK bits.

• USB_DOEPx_CTL.EPENA = 1 • USB_DOEPx_CTL.CNAK = 1 3. In Slave mode, wait for the USB_GINTSTS.RXFLVL level interrupt and empty the data packets from

the receive FIFO as explained in Packet Read from FIFO in Slave Mode (p. 195) .

• This step can be repeated many times, depending on the transfer size.

4. Asserting the USB_DOEPx_INT.XFERCOMPL interrupt marks a successful completion of the non isochronous OUT data transfer.

5. Read the USB_DOEPx_TSIZ register to determine the size of the received data payload.

Note

The XFERSIZE is not decremented for the last packet. This is as per design behavior.

Slave Mode Bulk OUT Transaction

Figure 14.19 (p. 200) depicts the reception of a single bulk OUT data packet from the USB to the AHB

and describes the events involved in the process.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

199

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.19. Slave Mode Bulk OUT Transaction

Host USB Device Applicatio n init_ out_ ep 1 2

OUT wr_reg(USB_DOEPx _TSIZ) wr_reg(USB_DOEPx _CTL)

3

EPENA = = ACK

5 4

x act_1 U S B PKTCNT = T NAK=1 0 RXFLVL INTR

6

idle unt il int r OUT NAK

7

XFERSIZE= 0 XFER CO R MP

8

rcv_out_pkt() idle unt il int r On new x fer or Rx FIFO not em pt y After a SetConfiguration/SetInterface command, the application initializes all OUT endpoints by setting USB_DOEPx_CTL.CNAK = 1 and USB_DOEPx_CTL.EPENA = 1, and setting a suitable XFERSIZE and PKTCNT in the USB_DOEPx_TSIZ register.

1. Host attempts to send data (OUT token) to an endpoint.

2. When the core receives the OUT token on the USB, it stores the packet in the RxFIFO because space is available there.

3. After writing the complete packet in the RxFIFO, the core then asserts the USB_GINTSTS.RXFLVL

interrupt.

4. On receiving the PKTCNT number of USB packets, the core sets the NAK bit for this endpoint internally to prevent it from receiving any more packets.

5. The application processes the interrupt and reads the data from the RxFIFO.

6. When the application has read all the data (equivalent to XFERSIZE), the core generates a USB_DOEPx_INT.XFERCOMPL interrupt.

7. The application processes the interrupt and uses the setting of the USB_DOEPx_INT.XFERCOMPL

interrupt bit to determine that the intended transfer is complete.

14.4.4.2.2.9 Generic Isochronous OUT Data Transfer in DMA and Slave Modes

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the host, it must initialize an endpoint

as described in Endpoint Initialization (p. 186) . See Packet Read from FIFO in Slave Mode (p. 195) .

This section describes a regular isochronous OUT data transfer.

Application Requirements:

1. All the application requirements for non-isochronous OUT data transfers also apply to isochronous OUT data transfers 2. For isochronous OUT data transfers, the Transfer Size and Packet Count fields must always be set to the number of maximum-packet-size packets that can be received in a single frame and no more.

Isochronous OUT data transfers cannot span more than 1 frame.

• 1 <= packet count[epnum] <= 3 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

200

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

3. In Slave mode, when isochronous OUT endpoints are supported in the device, the application must read all isochronous OUT data packets from the receive FIFO (data and status) before the end of the periodic frame (USB_GINTSTS.EOPF interrupt). In DMA mode, the application must guarantee enough bandwidth to allow emptying the isochronous OUT data packet from the receive FIFO before the end of each periodic frame.

4. To receive data in the following frame, an isochronous OUT endpoint must be enabled after the USB_GINTSTS.EOPF and before the USB_GINTSTS.SOF.

Internal Data Flow

1. The internal data flow for isochronous OUT endpoints is the same as that for non-isochronous OUT endpoints, but for a few differences.

2. When an isochronous OUT endpoint is enabled by setting the Endpoint Enable and clearing the NAK bits, the Even/Odd frame bit must also be set appropriately. The core receives data on a isochronous OUT endpoint in a particular frame only if the following condition is met.

• USB_DOEPx_CTL.DPIDEOF (Even/Odd frame) = USB_DSTS.SOFFN[0] 3. When either the application or the internal DMA completely reads an isochronous OUT data packet (data and status) from the receive FIFO, the core updates the USB_DOEPx_TSIZ.RXDPIDSUPCNT

(Received DPID) field with the data PID of the last isochronous OUT data packet read from the receive FIFO.

Application Programming Sequence

1. Program the USB_DOEPx_TSIZ register for the transfer size and the corresponding packet count.

When in DMA mode, also program the USB_DOEPx_DMAADDR register.

2. Program the USB_DOEPx_CTL register with the endpoint characteristics and set the Endpoint Enable, ClearNAK, and Even/Odd frame bits.

• Endpoint Enable = 1 • CNAK = 1 • Even/Odd frame = (0: Even/1: Odd) 1. In Slave mode, wait for the USB_GINTSTS.Rx StsQ level interrupt and empty the data packets from

the receive FIFO as explained in Packet Read from FIFO in Slave Mode (p. 195) .

• This step can be repeated many times, depending on the transfer size.

1. The assertion of the USB_DOEPx_INT.XFERCOMPL interrupt marks the completion of the isochronous OUT data transfer. This interrupt does not necessarily mean that the data in memory is good.

2. This interrupt can not always be detected for isochronous OUT transfers. Instead, the application can

detect the USB_GINTSTS.INCOMPLP (Incomplete Isochronous OUT data) interrupt. See Incomplete Isochronous OUT Data Transfers in DMA and Slave Modes (p. 206) , for more details

3. Read the USB_DOEPx_TSIZ register to determine the size of the received transfer and to determine the validity of the data received in the frame. The application must treat the data received in memory as valid only if one of the following conditions is met.

• USB_DOEPx_TSIZ.RXDPID = D0 and the number of USB packets in which this payload was received = 1 • USB_DOEPx_TSIZ.RXDPID = D1 and the number of USB packets in which this payload was received = 2 • USB_DOEPx_TSIZ.RXDPID = D2 and the number of USB packets in which this payload was received = 3 • The number of USB packets in which this payload was received = App Programmed Initial Packet Count – Core Updated Final Packet Count The application can discard invalid data packets.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

201

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.4.4.2.2.10 Generic Interrupt OUT Data Transfers Using Periodic Transfer Interrupt Feature

This section describes a regular INTR OUT data transfer with the Periodic Transfer Interrupt feature.

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the host, it must initialize an endpoint

as described in Endpoint Initialization (p. 186) . See Packet Read from FIFO in Slave Mode (p. 195) .

Application Requirements 1. Before setting up a periodic OUT transfer, the application must allocate a buffer in the memory to accommodate all data to be received as part of the OUT transfer, then program that buffer’s size and start address in the endpoint-specific registers.

2. For Interrupt OUT transfers, the Transfer Size field in the endpoint’s Transfer Size register must be a multiple of the maximum packet size of the endpoint, adjusted to the DWORD boundary. The Transfer Size programmed can span across multiple frames based on the periodicity after which the application want to receive the USB_DOEPx_INT.XFERCOMPL interrupt • transfer size[epnum] = n * (mps[epnum] + 4 - (mps[epnum] mod 4)) • packet count[epnum] = n • n > 0 (Higher value of n reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt) • 1 < packet count[epnum] < n (Higher value of n reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt) 3. In DMA mode, the core stores a received data packet in the memory, always starting on a DWORD boundary. If the maximum packet size of the endpoint is not a multiple of 4, the core inserts byte pads at end of a maximum-packet-size packet up to the end of the DWORD. The application will not be informed about the frame number on which a specific packet has been received.

4. On USB_DOEPx_INT.XFERCOMPL interrupt, the application must read the endpoint’s Transfer Size register to calculate the size of the payload in the memory. The received payload size can be less than the programmed transfer size.

• Payload size in memory = application-programmed initial transfer size – core updated final transfer size • Number of USB packets in which this payload was received = application-programmed initial packet count – core updated final packet count.

• If for some reason, the host stops sending tokens, there are no interrupts to the application, and the application must timeout on its own.

5. The assertion of the USB_DOEPx_INT.XFERCOMPL interrupt marks the completion of the interrupt OUT data transfer. This interrupt does not necessarily mean that the data in memory is good.

6. Read the USB_DOEPx_TSIZ register to determine the size of the received transfer and to determine the validity of the data received in the frame.

Internal Data Flow

1. The application must set the Transfer Size and Packet Count fields in the endpoint-specific registers, clear the NAK bit, and enable the endpoint to receive the data.

• The application must enable the USB_DCTL.IGNRFRMNUM

2. When an interrupt OUT endpoint is enabled by setting the Endpoint Enable and clearing the NAK bits, the Even/Odd frame will be ignored by the core.

1. Once the NAK bit is cleared, the core starts receiving data and writes it to the receive FIFO, as long as there is space in the receive FIFO. For every data packet received on the USB, the data packet and its status are written to the receive FIFO. Every packet (maximum packet size or short packet) written to the receive FIFO decrements the Packet Count field for that endpoint by 1.

• OUT data packets received with Bad Data CRC or any packet error are flushed from the receive FIFO automatically.

• Interrupt packets with PID errors are not passed to application. Core discards the packet, sends ACK and does not decrement packet count.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

202

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• If there is no space in the receive FIFO, interrupt data packets are ignored and not written to the receive FIFO. Additionally, interrupt OUT tokens receive a NAK handshake reply.

2. When the packet count becomes 0 or when a short packet is received on the endpoint, the NAK bit for that endpoint is set. Once the NAK bit is set, the isochronous or interrupt data packets are ignored and not written to the receive FIFO, and interrupt OUT tokens receive a NAK handshake reply.

3. After the data is written to the receive FIFO, the core’s DMA engine reads the data from the receive FIFO and writes it to external memory, one packet at a time per endpoint.

4. At the end of every packet write on the AHB to external memory, the transfer size for the endpoint is decremented by the size of the written packet.

5. The OUT Data Transfer Completed pattern for an OUT endpoint is written to the receive FIFO on one of the following conditions.

• The transfer size is 0 and the packet count is 0.

• The last OUT data packet written to the receive FIFO is a short packet (0 < packet size < maximum packet size) 6. When either the application or the DMA pops this entry (OUT Data Transfer Completed), a Transfer Completed interrupt is generated for the endpoint and the endpoint enable is cleared.

14.4.4.2.2.11 Generic Isochronous OUT Data Transfers Using Periodic Transfer Interrupt Feature

This section describes a regular isochronous OUT data transfer with the Periodic Transfer Interrupt feature.

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the host, it must initialize an endpoint

as described in Endpoint Initialization (p. 186) . For packet writes in Slave mode, see: Packet Read from FIFO in Slave Mode (p. 195) .

Application Requirements

1. Before setting up ISOC OUT transfers spanned across multiple frames, the application must allocate buffer in the memory to accommodate all data to be received as part of the OUT transfers, then program that buffer’s size and start address in the endpoint-specific registers.

• The application must mask the USB_GINTSTS.INCOMPLP (Incomplete ISO OUT).

• The application must enable the USB_DCTL.IGNRFRMNUM

2. For ISOC transfers, the Transfer Size field in the USB_DOEPx_TSIZ.XFERSIZE register must be a multiple of the maximum packet size of the endpoint, adjusted to the DWORD boundary. The Transfer Size programmed can span across multiple frames based on the periodicity after which the application wants to receive the USB_DOEPx_INT.XFERCOMPL interrupt • transfer size[epnum] = n * (mps[epnum] + 4 - (mps[epnum] mod 4)) • packet count[epnum] = n • n > 0 (Higher value of n reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt) • 1 =< packet count[epnum] =< n (Higher value of n reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt).

3. In DMA mode, the core stores a received data packet in the memory, always starting on a DWORD boundary. If the maximum packet size of the endpoint is not a multiple of 4, the core inserts byte pads at end of a maximum-packet-size packet up to the end of the DWORD. The application will not be informed about the frame number and the PID value on which a specific OUT packet has been received.

4. The assertion of the USB_DOEPx_INT.XFERCOMPL interrupt marks the completion of the isochronous OUT data transfer. This interrupt does not necessarily mean that the data in memory is good.

• On USB_DOEPx_INT.XFERCOMPL, the application must read the endpoint’s Transfer Size register to calculate the size of the payload in the memory.

• Payload size in memory = application-programmed initial transfer size - core updated final transfer size 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

203

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• Number of USB packets in which this payload was received = application-programmed initial packet count – core updated final packet count.

• If for some reason, the host stop sending tokens, there will be no interrupt to the application, and the application must timeout on its own.

5. The assertion of the USB_DOEPx_INT.XFERCOMPL can also mark a packet drop on USB due to unavailability of space in the RxFifo or due to any packet errors.

• The application must read the USB_DOEPx_INT.PKTDRPSTS (USB_DOEPx_INT.Bit[11] is now used as the USB_DOEPx_INT.PKTDRPSTS) register to differentiate whether the USB_DOEPx_INT.XFERCOMPL was generated due to the normal end of transfer or due to dropped packets. In case of packets being dropped on the USB due to unavailability of space in the RxFifo or due to any packet errors the endpoint enable bit is cleared.

• In case of packet drop on the USB application must re-enable the endpoint after recalculating the values USB_DOEPx_TSIZ.XFERSIZE and USB_DOEPx_TSIZ.PKTCNT.

• Payload size in memory = application-programmed initial transfer size - core updated final transfer size • Number of USB packets in which this payload was received = application-programmed initial packet count - core updated final packet count.

Note

Due to application latencies it is possible that DOEPINT.XFERCOMPL interrupt is generated without DOEPINT.PKTDRPSTS being set, This scenario is possible only if back to-back packets are dropped for consecutive frames and the PKTDRPSTS is merged, but the XFERSIZE and PktCnt values for the endpoint are nonzero. In this case, the application must proceed further by programming the PKTCNT and XFERSIZE register for the next frame, as it would if PKTDRPSTS were being set.

Figure 14.20 (p. 205) gives the application flow for Isochronous OUT Periodic Transfer Interrupt

feature.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

204

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.20. ISOC OUT Application Flow for Periodic Transfer Interrupt Feature Note: 1 . ( micro-) frame number and PID field are not updated for Periodic OUT packets 2 . In Periodic OUT transfers . The application must reenable the endpoint with recalculated values of XferSize and PktCnt 3 . The application must reenable the endpoint after dropped packets for ISOC OU

START Int ialize variables Program t he DMA address USB_DOEPx _DMA =

START Address of the Data Memory

Program Xfer _ size regist er USB_DOEPx _TSIZ.XFERSIZE

XferSize Spanning across multiple Xfers

USB_DOEPx _TSIZ.

Program t he Global INT STS

Program PktCnt for multiple Xfers

INCOMPLPMSK = 0

/ / Mask IncompISOCOUT Interrupt

Program EP Ct rl regist er t o st art t he x fer USB_DOEPx _CTL . CNAK = USB_DOEPx _CTL .EPENA

USB_DOEPx _CTL . SNAK USB_DOEPx _CTL .EPDIS

= = = Wait for USB_DOEPx _INT. XFERCOMPL int errupt and report error if t im eout ex pires Re - com put e XFERSIZE and PKTCNT NO Received Short Packet If USB_DOEPx _TSIZ. PKTCNT= =0 YES NO If USB_DOEPx _INT. PKTDRPSTS = =1 YES ISOC OUT Pkt Drop YES End of Transfer Ret urn NO YES Received Short Packet NO ERROR

Internal Data Flow

1. The application must set the Transfer Size, Packets to be received in a frame and Packet Count Fields in the endpoint-specific registers, clear the NAK bit, and enable the endpoint to receive the data.

2. When an isochronous OUT endpoint is enabled by setting the Endpoint Enable and clearing the NAK bits, the Even/Odd frame will be ignored by the core.

3. Once the NAK bit is cleared, the core starts receiving data and writes it to the receive FIFO, as long as there is space in the receive FIFO. For every data packet received on the USB, the data packet and its status are written to the receive FIFO. Every packet (maximum packet size or short packet) written to the receive FIFO decrements the Packet Count field for that endpoint by 1.

4. When the packet count becomes 0 or when a short packet is received on the endpoint, the NAK bit for that endpoint is set. Once the NAK bit is set, the ISOC packets are ignored and not written to the receive FIFO.

5. After the data is written to the receive FIFO, the core’s DMA engine, reads the data from the receive FIFO and writes it to external memory, one packet at a time per endpoint.

6. At the end of every packet write on the AHB to external memory, the transfer size for the endpoint is decremented by the size of the written packet.

7. The OUT Data Transfer Completed pattern for an OUT endpoint is written to the receive FIFO on one of the following conditions.

• The transfer size is 0 and the packet count is 0 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

205

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• The last OUT data packet written to the receive FIFO is a short packet (0 < packet size < maximum packet size).

8. When the DMA pops this entry (OUT Data Transfer Completed), a Transfer Completed interrupt is generated for the endpoint or the endpoint enable is cleared.

9. OUT data packets received with Bad Data CRC or any packet error are flushed from the receive FIFO automatically.

• In these two cases, the packet count and transfer size registers are not decremented because no data is written to the receive FIFO.

Figure 14.21. Isochronous OUT Core Internal Flow for Periodic Transfer Interrupt Feature

START

A

NO

If (USB_DOEPx _CTL.CNAK = 0b1) && (USB_DOEPx _CTL.EPENA = 0b1) && (DCTL.IGNRFRMNUM = 0b1) &&

NO

OUT Token From Host

YES

Check RXFifo Space Available

YES

NOTE 1 . 2 . 3 . Any Short Packet 4 . 5 . Core will write data to only DWORD Aligned addresses including zero length packet PacketDrop due to unAvailability of Space in RxFifo will generate XferComplete Immediately PktDrop due to EndPoint being disabled will generate XferComplete at End of periodic Frame interval

Disable endpoint YES Receive Pkt and St ore in RXFifo Pkt Cnt -1 NO Received Short Packet Pkt Cnt - 1 DMA Pop Rx Fifo XferSize Max Pkt Size USB_DOEPx _INT.XFERCOMPL = 1 DMA Pop Rx Fifo XferSize Act Pkt Size YES NO

A

NO YES ret urn

Received will generate XferComplete Interrupt

NO

If End Of PerFrInt ISOC Out Packet Naked

YES Disable endpoint

14.4.4.2.2.12 Incomplete Isochronous OUT Data Transfers in DMA and Slave Modes

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the host, it must initialize an endpoint

as described in Endpoint Initialization (p. 186) . See Packet Read from FIFO in Slave Mode (p. 195) .

This section describes the application programming sequence when isochronous OUT data packets are dropped inside the core.

Internal Data Flow

1. For isochronous OUT endpoints, the USB_DOEPx_INT.XFERCOMPL interrupt possibly is not always asserted. If the core drops isochronous OUT data packets, the application could fail to detect the USB_DOEPx_INT.XFERCOMPL interrupt under the following circumstances.

• When the receive FIFO cannot accommodate the complete ISO OUT data packet, the core drops the received ISO OUT data.

• When the isochronous OUT data packet is received with CRC errors • When the isochronous OUT token received by the core is corrupted • When the application is very slow in reading the data from the receive FIFO 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

206

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

2. When the core detects an end of periodic frame before transfer completion to all isochronous OUT endpoints, it asserts the USB_GINTSTS.INCOMPLP (Incomplete Isochronous OUT data) interrupt, indicating that a USB_DOEPx_INT.XFERCOMPL interrupt is not asserted on at least one of the isochronous OUT endpoints. At this point, the endpoint with the incomplete transfer remains enabled, but no active transfers remains in progress on this endpoint on the USB.

3. This step is applicable only if the core is operating in slave mode. Application Programming Sequence 4. This step is applicable only if the core is operating in slave mode. Asserting the USB_GINTSTS.INCOMPLP (Incomplete Isochronous OUT data) interrupt indicates that in the current frame, at least one isochronous OUT endpoint has an incomplete transfer.

5. If this occurs because isochronous OUT data is not completely emptied from the endpoint, the application must ensure that the DMA or the application empties all isochronous OUT data (data and status) from the receive FIFO before proceeding.

• When all data is emptied from the receive FIFO, the application can detect the USB_DOEPx_INT.XFERCOMPL interrupt. In this case, the application must re-enable the endpoint

to receive isochronous OUT data in the next frame, as described in Control Read Transfers (SETUP, Data IN, Status OUT) (p. 193) .

6. When it receives a USB_GINTSTS.incomplete Isochronous OUT data interrupt, the application must read the control registers of all isochronous OUT endpoints (USB_DOEPx_CTL) to determine which endpoints had an incomplete transfer in the current frame. An endpoint transfer is incomplete if both the following conditions are met.

• USB_DOEPx_CTL.DPIDEOF (Even/Odd frame) = USB_DSTS.SOFFN[0] • USB_DOEPx_CTL.EPENA (Endpoint Enable) = 1 7. The previous step must be performed before the USB_GINTSTS.SOF interrupt is detected, to ensure that the current frame number is not changed.

8. For isochronous OUT endpoints with incomplete transfers, the application must discard the data in the memory and disable the endpoint by setting the USB_DOEPx_CTL.EPDIS (Endpoint Disable) bit.

9. Wait for the USB_DOEPx_INT.EPDIS (Endpoint Disabled) interrupt and enable the endpoint to

receive new data in the next frame as explained in Control Read Transfers (SETUP, Data IN, Status OUT) (p. 193) .

• Because the core can take some time to disable the endpoint, the application possibly is not able to receive the data in the next frame after receiving bad isochronous data.

14.4.4.2.3 IN Data Transfers in Slave and DMA Modes

This section describes the internal data flow and application-level operations during IN data transfers.

• Packet Write in Slave Mode (p. 208) • Setting Global Non-Periodic IN Endpoint NAK (p. 208) • Setting IN Endpoint NAK (p. 208)

• IN Endpoint Disable (p. 209)

• Bulk IN Stall (p. 210) • Incomplete Isochronous IN Data Transfers (p. 210)

• Stalling Non-Isochronous IN Endpoints (p. 211)

• Worst-Case Response Time (p. 212) • Choosing the Value of USB_GUSBCFG.USBTRDTIM (p. 212)

• Handling Babble Conditions (p. 213) • Generic Non-Periodic (Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode (p. 213)

• Examples (p. 215)

• Generic Periodic IN Data Transfers Without Thresholding Using the Periodic Transfer Interrupt Feature (p. 220)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

207

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.4.4.2.3.1 Packet Write in Slave Mode

This section describes how the application writes data packets to the endpoint FIFO in Slave mode.

1. The application can either choose polling or interrupt mode.

• In polling mode, application monitors the status of the endpoint transmit data FIFO, by reading the USB_DIEPx_TXFSTS register, to determine, if there is enough space in the data FIFO.

• In interrupt mode, application waits for the USB_DIEPx_INT.TXFEMP interrupt and then reads the USB_DIEPx_TXFSTS register, to determine, if there is enough space in the data FIFO.

• To write a single non-zero length data packet, there must be space to write the entire packet is the data FIFO.

• For writing zero length packet, application must not look for FIFO space.

2. Using one of the above mentioned methods, when the application determines that there is enough space to write a transmit packet, the application must first write into the endpoint control register, before writing the data into the data FIFO. The application, typically must do a read modify write on the USB_DIEPx_CTL, to avoid modifying the contents of the register, except for setting the Endpoint Enable bit.

The application can write multiple packets for the same endpoint, into the transmit FIFO, if space is available. For periodic IN endpoints, application must write packets only for one frame. It can write packets for the next periodic transaction, only after getting transfer complete for the previous transaction.

14.4.4.2.3.2 Setting Global Non-Periodic IN Endpoint NAK Internal Data Flow

1. When the application sets the Global Non-periodic IN NAK bit (USB_DCTL.SGNPINNAK), the core stops transmitting data on the non-periodic endpoint, irrespective of data availability in the Non periodic Transmit FIFO.

2. Non-isochronous IN tokens receive a NAK handshake reply 3. The core asserts the USB_DCTL.SGNPINNAK bit.

USB_GINTSTS.GINNAKEFF interrupt in response to the 4. Once the application detects this interrupt, it can assume that the core is in the Global Non-periodic IN NAK mode. The application can clear this interrupt by clearing the USB_DCTL.SGNPINNAK bit.

Application Programming Sequence

1. To stop transmitting any data on non-periodic IN endpoints, the application must set the USB_DCTL.SGNPINNAK bit. To set this bit, the following field must be programmed • USB_DCTL.SGNPINNAK = 1 2. Wait for the assertion of the USB_GINTSTS.GINNAKEFF interrupt. This interrupt indicates the core has stopped transmitting data on the non-periodic endpoints.

3. The core can transmit valid non-periodic IN data after the application has set the USB_DCTL.SGNPINNAK bit, but before the assertion of the USB_GINTSTS.GINNAKEFF interrupt.

4. The application can optionally mask this interrupt temporarily by writing to the USB_GINTMSK.GINNAKEFFMSK bit.

• USB_GINTMSK.GINNAKEFFMSK = 0 5. To exit Global Non-periodic IN NAK mode, the application must clear the USB_DCTL.SGNPINNAK.

This also clears the USB_GINTSTS.GINNAKEFF interrupt.

• USB_DCTL.SGNPINNAK = 1 6. If the application has masked this interrupt earlier, it must be unmasked as follows: • USB_GINTMSK.GINNAKEFFMSK = 1

14.4.4.2.3.3 Setting IN Endpoint NAK Internal Data Flow

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

208

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

1. When the application sets the IN NAK for a particular endpoint, the core stops transmitting data on the endpoint, irrespective of data availability in the endpoint’s transmit FIFO.

2. Non-isochronous IN tokens receive a NAK handshake reply • Isochronous IN tokens receive a zero-data-length packet reply 3. The core asserts the USB_DIEPx_INT.INEPNAKEFF (IN NAK Effective) interrupt in response to the USB_DIEPx_CTL.SNAK (Set NAK) bit.

4. Once this interrupt is seen by the application, the application can assume that the endpoint is in IN NAK mode. This interrupt can be cleared by the application by setting the USB_DIEPx_CTL. Clear NAK bit.

Application Programming Sequence

1. To stop transmitting any data on a particular IN endpoint, the application must set the IN NAK bit. To set this bit, the following field must be programmed.

• USB_DIEPx_CTL.SNAK = 1 2. Wait for assertion of the USB_DIEPx_INT.INEPNAKEFF (NAK Effective) interrupt. This interrupt indicates the core has stopped transmitting data on the endpoint.

3. The core can transmit valid IN data on the endpoint after the application has set the NAK bit, but before the assertion of the NAK Effective interrupt.

4. The application can mask this interrupt USB_DIEPMSK.INEPNAKEFFMSK (NAK Effective) bit.

temporarily by writing to the • USB_DIEPMSK.INEPNAKEFFMSK (NAK Effective) = 0 5. To exit Endpoint NAK mode, the application must clear the USB_DIEPx_CTL.NAK status. This also clears the USB_DIEPx_INT.INEPNAKEFF (NAK Effective) interrupt.

• USB_DIEPx_CTL.CNAK = 1 6. If the application masked this interrupt earlier, it must be unmasked as follows: • USB_DIEPMSK.INEPNAKEFFMSK (NAK Effective) = 1

14.4.4.2.3.4 IN Endpoint Disable

Use the following sequence to disable a specific IN endpoint (periodic/non-periodic) that has been previously enabled.

Application Programming Sequence:

1. In Slave mode, the application must stop writing data on the AHB, for the IN endpoint to be disabled.

2. The application must set the endpoint in NAK mode. See Setting IN Endpoint NAK (p. 208) .

• USB_DIEPx_CTL.SNAK = 1 3. Wait for USB_DIEPx_INT.INEPNAKEFF (NAK Effective) interrupt.

4. Set the following bits in the USB_DIEPx_CTL register for the endpoint that must be disabled.

• USB_DIEPx_CTL.EPDIS (Endpoint Disable) = 1 • USB_DIEPx_CTL.SNAK = 1 5. Assertion of USB_DIEPx_INT.EPDISBLD (Endpoint Disabled) interrupt indicates that the core has completely disabled the specified endpoint. Along with the assertion of the interrupt, the core also clears the following bits.

• USB_DIEPx_CTL.EPENA = 0 • USB_DIEPx_CTL.EPDIS = 0 6. The application must read the USB_DIEPx_TSIZ register for the periodic IN EP, to calculate how much data on the endpoint was transmitted on the USB.

7. The application must flush the data in the Endpoint transmit FIFO, by setting the following fields in the USB_GRSTCTL register.

• USB_GRSTCTL.TXFNUM = Endpoint Transmit FIFO Number • USB_GRSTCTL.TXFFLSH = 1 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

209

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

The application must poll the USB_GRSTCTL register, until the TXFFLSH bit is cleared by the core, which indicates the end of flush operation. To transmit new data on this endpoint, the application can re-enable the endpoint at a later point.

14.4.4.2.3.5 Bulk IN Stall

These notes refer to Figure 14.22 (p. 210)

1. The application has scheduled an IN transfer on receiving the USB_DIEPx_INT.INTKNTXFEMP (IN Token Received When TxFIFO Empty) interrupt.

2. When the transfer is in progress, the application must force a STALL on the endpoint. This could be because the application has received a SetFeature.Endpoint Halt command. The application sets the Stall bit, disables the endpoint and waits for the USB_DIEPx_INT.EPDISBLD (Endpoint Disabled) interrupt. This generates STALL handshakes for the endpoint on the USB.

3. On receiving the interrupt, the application flushes the Non-periodic Transmit FIFO and clears the USB_DCTL.SGNPINNAK (Global IN NP NAK) bit.

4. On receiving the ClearFeature.Endpoint Halt command, the application clears the Stall bit.

5. The endpoint behaves normally and the application can re-enable the endpoint for new transfers

Figure 14.22. Bulk IN Stall

Host USB Device Application

IN NAK IN ACK IN STAL L INTKNTXFEMP INTR EPDisabled int r idle( wait_int r) set up_ np_in_ pkt x act_ 1 dat a rdy NPTXFEMP INT set up_ np_in_ pkt set_ st all ep_ disable; flush_ nper_ t x_ fifo; Clr Global IN NP Nak

1

do_in_ x fer

2 3 4

IN STAL L wait_for_ host/ app t o clr st all

5

clr_ st all IN NAK IN INTKNT XFEMP do_ in_ x fer new x act A CK

14.4.4.2.3.6 Incomplete Isochronous IN Data Transfers

This section describes what the application must do on an incomplete isochronous IN data transfer.

Internal Data Flow 1. An isochronous IN transfer is treated as incomplete in one of the following conditions.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

210

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

a. The core receives a corrupted isochronous IN token on at least one isochronous IN endpoint. In this case, the application detects a USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt.

b. The application or DMA is slow to write the complete data payload to the transmit FIFO and an IN token is received before the complete data payload is written to the FIFO. In this case, the application detects a USB_DIEPx_INT.INTKNTXFEMP (IN Token Received When TxFIFO Empty) interrupt. The application can ignore this interrupt, as it eventually results in a USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt at the end of periodic frame.

i. The core transmits a zero-length data packet on the USB in response to the received IN token.

2. In either of the aforementioned cases, in Slave mode, the application must stop writing the data payload to the transmit FIFO as soon as possible.

3. The application must set the NAK bit and the disable bit for the endpoint. In DMA mode, the core automatically stops fetching the data payload when the endpoint disable bit is set.

4. The core disables the endpoint, clears the disable bit, and asserts the Endpoint Disable interrupt for the endpoint.

Application Programming Sequence

1. The application can ignore the USB_DIEPx_INT.INTKNTXFEMP (IN Token Received When TxFIFO empty) interrupt on any isochronous IN endpoint, as it eventually results in a USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt.

2. Assertion of the USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt indicates an incomplete isochronous IN transfer on at least one of the isochronous IN endpoints.

3. The application must read the Endpoint Control register for all isochronous IN endpoints to detect endpoints with incomplete IN data transfers.

4. In Slave mode, the application must stop writing data to the Periodic Transmit FIFOs associated with these endpoints on the AHB.

5. In both modes of operation, program the following fields in the USB_DIEPx_CTL register to disable the endpoint.

• USB_DIEPx_CTL.SNAK = 1 • USB_DIEPx_CTL.EPDIS (Endpoint Disable) = 1 6. The USB_DIEPx_INT.EPDISBLD (Endpoint Disabled) interrupt’s assertion indicates that the core has disabled the endpoint.

• At this point, the application must flush the data in the associated transmit FIFO or overwrite the existing data in the FIFO by enabling the endpoint for a new transfer in the next frame. To flush the data, the application must use the USB_GRSTCTL register.

14.4.4.2.3.7 Stalling Non-Isochronous IN Endpoints

This section describes how the application can stall a non-isochronous endpoint.

Application Programming Sequence

1. Disable the IN endpoint to be stalled. Set the Stall bit as well.

2. USB_DIEPx_CTL.EPDIS (Endpoint Disable) = 1, when the endpoint is already enabled • USB_DIEPx_CTL.STALL = 1 • The Stall bit always takes precedence over the NAK bit 3. Assertion of the USB_DIEPx_INT.EPDISBLD (Endpoint Disabled) interrupt indicates to the application that the core has disabled the specified endpoint.

4. The application must flush the Non-periodic or Periodic Transmit FIFO, depending on the endpoint type. In case of a non-periodic endpoint, the application must re-enable the other non-periodic endpoints, which do not need to be stalled, to transmit data.

5. Whenever the application is ready to end the STALL handshake for the endpoint, the USB_DIEPx_CTL.STALL bit must be cleared.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

211

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

6. If the application sets or clears a STALL for an endpoint due to a SetFeature.Endpoint Halt command or ClearFeature.Endpoint Halt command, the Stall bit must be set or cleared before the application sets up the Status stage transfer on the control endpoint.

Special Case: Stalling the Control IN/OUT Endpoint

The core must stall IN/OUT tokens if, during the Data stage of a control transfer, the host sends more IN/OUT tokens than are specified in the SETUP packet. In this case, the application must to enable USB_DIEPx_INT.INTKNTXFEMP and USB_DOEPx_INT.OUTTKNEPDIS interrupts during the Data stage of the control transfer, after the core has transferred the amount of data specified in the SETUP packet. Then, when the application receives this interrupt, it must set the STALL bit in the corresponding endpoint control register, and clear this interrupt.

14.4.4.2.3.8 Worst-Case Response Time

When the acts as a device, there is a worst case response time for any tokens that follow an isochronous OUT. This worst case response time depends on the AHB clock frequency.

The core registers are in the AHB domain, and the core does not accept another token before updating these register values. The worst case is for any token following an isochronous OUT, because for an isochronous transaction, there is no handshake and the next token could come sooner. This worst case value is 7 PHY clocks in FS mode.

If this worst case condition occurs, the core responds to bulk/interrupt tokens with a NAK and drops isochronous and SETUP tokens. The host interprets this as a timeout condition for SETUP and retries the SETUP packet. For isochronous transfers, the INCOMPISOIN and INCOMPLP interrupts inform the application that isochronous IN/OUT packets were dropped.

14.4.4.2.3.9 Choosing the Value of USB_GUSBCFG.USBTRDTIM

The value in USB_GUSBCFG.USBTRDTIM is the time it takes for the MAC, in terms of PHY clocks after it has received an IN token, to get the FIFO status, and thus the first data from PFC (Packet FIFO Controller) block. This time involves the synchronization delay between the PHY and AHB clocks. This delay is 5 clocks.

Once the MAC receives an IN token, this information (token received) is synchronized to the AHB clock by the PFC (the PFC runs on the AHB clock). The PFC then reads the data from the SPRAM and writes it into the dual clock source buffer. The MAC then reads the data out of the source buffer (4 deep).

If the AHB is running at a higher frequency than the PHY (in Low-speed mode), the application can use

a smaller value for USB_GUSBCFG.USBTRDTIM. Figure 14.23 (p. 213) explains the 5-clock delay.

This diagram has the following signals: • tkn_rcvd: Token received information from MAC to PFC • dynced_tkn_rcvd: Doubled sync tkn_rcvd, from pclk to hclk domain • spr_read: Read to SPRAM • spr_addr: Address to SPRAM • spr_rdata: Read data from SPRAM • srcbuf_push: Push to the source buffer • srcbuf_rdata: Read data from the source buffer. Data seen by MAC The application can use the following formula to calculate the value of USB_GUSBCFG.USBTRDTIM: 4 * AHB Clock + 1 PHY Clock = (2 clock sync + 1 clock memory address + 1 clock memory data from sync RAM) + (1 PHY Clock (next PHY clock MAC can sample the 2-clock FIFO output) 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

212

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.23. USBTRDTIM Max Timing Case ERROR wrong image

Host USB Device Application

IN NAK INTKNTXFEMP INTR idle( wait_int r) IN ACK IN STAL L x act_ 1 dat a rdy set up_ np_in_ pkt NPTXFEMP INT set up_ np_in_ pkt EPDisabled int r set_ st all ep_ disable; flush_ nper_ t x_ fifo; Clr Global IN NP Nak

1

do_in_ x fer

2 3 4

IN STAL L wait_for_ host/ app t o clr st all

5

clr_ st all IN NAK IN INTKNT XFEMP do_ in_ x fer new x act A CK

14.4.4.2.3.10 Handling Babble Conditions

If receives a packet that is larger than the maximum packet size for that endpoint, the core stops writing data to the Rx buffer and waits for the end of packet (EOP). When the core detects the EOP, it flushes the packet in the Rx buffer and does not send any response to the host.

If the core continues to receive data at the EOF2 (the end of frame 2, which is very close to SOF), the core generates an early_suspend interrupt (USB_GINTSTS.ERLYSUSP). On receiving this interrupt, the application must check the erratic_error status bit (USB_DSTS.ERRTICERR). If this bit is set, the application must take it as a long babble and perform a soft reset.

14.4.4.2.3.11 Generic Non-Periodic (Bulk and Control) IN Data Transfers in DMA and Slave Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the host, it must initialize an endpoint

as described in Endpoint Initialization (p. 186) . For packet writes in Slave mode, see: Packet Write in Slave Mode (p. 208) .

Application Requirements

1. Before setting up an IN transfer, the application must ensure that all data to be transmitted as part of the IN transfer is part of a single buffer, and must program the size of that buffer and its start address (in DMA mode) to the endpoint-specific registers.

2. For IN transfers, the Transfer Size field in the Endpoint Transfer Size register denotes a payload that constitutes multiple maximum-packet-size packets and a single short packet. This short packet is transmitted at the end of the transfer.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

213

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• To transmit a few maximum-packet-size packets and a short packet at the end of the transfer: • Transfer size[epnum] = n * mps[epnum] + sp (where n is an integer >= 0, and 0 <= sp < mps[epnum]) • If (sp > 0), then packet count[epnum] = n + 1. Otherwise, packet count[epnum] = n a. To transmit a single zero-length data packet: • Transfer size[epnum] = 0 • Packet count[epnum] = 1 b. To transmit a few maximum-packet-size packets and a zero-length data packet at the end of the transfer, the application must split the transfer in two parts. The first sends maximum-packet-size data packets and the second sends the zero-length data packet alone.

c. First transfer: transfer size[epnum] = n * mps[epnum]; packet count = n; d. Second transfer: transfer size[epnum] = 0; packet count = 1; 3. In DMA mode, the core fetches an IN data packet from the memory, always starting at a DWORD boundary. If the maximum packet size of the IN endpoint is not a multiple of 4, the application must arrange the data in the memory with pads inserted at the end of a maximum-packet-size packet so that a new packet always starts on a DWORD boundary.

4. Once an endpoint is enabled for data transfers, the core updates the Transfer Size register. At the end of IN transfer, which ended with a Endpoint Disabled interrupt, the application must read the Transfer Size register to determine how much data posted in the transmit FIFO was already sent on the USB.

5. Data fetched into transmit FIFO = Application-programmed initial transfer size – core-updated final transfer size • Data transmitted on USB = (application-programmed initial packet count – Core updated final packet count) * mps[epnum] • Data yet to be transmitted on USB = (Application-programmed initial transfer size – data transmitted on USB)

Internal Data Flow

1. The application must set the Transfer Size and Packet Count fields in the endpoint-specific registers and enable the endpoint to transmit the data.

2. In Slave mode, the application must also write the required data to the transmit FIFO for the endpoint.

In DMA mode, the core fetches the data from memory according to the application setting for the endpoint.

3. Every time a packet is written into the transmit FIFO, either by the core’s internal DMA (in DMA mode) or the application (in Slave Mode), the transfer size for that endpoint is decremented by the packet size. The data is fetched from the memory (DMA/Application), until the transfer size for the endpoint becomes 0. After writing the data into the FIFO, the “number of packets in FIFO” count is incremented (this is a 3-bit count, internally maintained by the core for each IN endpoint transmit FIFO. The maximum number of packets maintained by the core at any time in an IN endpoint FIFO is eight). For zero-length packets, a separate flag is set for each FIFO, without any data in the FIFO.

4. Once the data is written to the transmit FIFO, the core reads it out upon receiving an IN token. For every non-isochronous IN data packet transmitted with an ACK handshake, the packet count for the endpoint is decremented by one, until the packet count is zero. The packet count is not decremented on a TIMEOUT.

5. For zero length packets (indicated by an internal zero length flag), the core sends out a zero-length packet for the IN token and decrements the Packet Count field.

6. If there is no data in the FIFO for a received IN token and the packet count field for that endpoint is zero, the core generates a IN Tkn Rcvd When FIFO Empty Interrupt for the endpoint, provided the endpoint NAK bit is not set. The core responds with a NAK handshake for non-isochronous endpoints on the USB.

7. For Control IN endpoint, if there is a TIMEOUT condition, the USB_DIEPx_INT.TIMEOUT interrupt is generated.

8. When the transfer size is 0 and the packet count is 0, the transfer complete interrupt for the endpoint is generated and the endpoint enable is cleared.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

214

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Application Programming Sequence

1. Program the USB_DIEPx_TSIZ register with the transfer size and corresponding packet count. In DMA mode, also program the USB_DIEPx_DMAADDR register.

2. Program the USB_DIEPx_CTL register with the endpoint characteristics and set the CNAK and Endpoint Enable bits.

3. In slave mode when transmitting non-zero length data packet, the application must poll the USB_DIEPx_TXFSTS register (where x is the FIFO number associated with that endpoint) to determine whether there is enough space in the data FIFO. The application can optionally use USB_DIEPx_INT.TXFEMP before writing the data.

14.4.4.2.3.12 Examples Slave Mode Bulk IN Transaction

These notes refer to Figure 14.24 (p. 215) .

1. The host attempts to read data (IN token) from an endpoint.

2. On receiving the IN token on the USB, the core returns a NAK handshake, because no data is available in the transmit FIFO.

3. To indicate to the application that there was no data to send, the core generates a USB_DIEPx_INT.INTKNTXFEMP (IN Token Received When TxFIFO Empty) interrupt.

4. When data is ready, the application sets up the USB_DIEPx_TSIZ register with the Transfer Size and Packet Count fields.

5. The application writes one maximum packet size or less of data to the Non-periodic TxFIFO.

6. The host reattempts the IN token.

7. Because data is now ready in the FIFO, the core now responds with the data and the host ACKs it.

8. Because the XFERSIZE is now zero, the intended transfer is complete. The device core generates a USB_DIEPx_INT.XFERCOMPL interrupt.

9. The application processes the interrupt and uses the setting of the USB_DIEPx_INT.XFERCOMPL

interrupt bit to determine that the intended transfer is complete.

Figure 14.24. Slave Mode Bulk IN Transaction

Host 1 USB

IN NAK IN NAK

Device 3 2

IN

5 Application

INTKNTXFEMP INTR wait for x fer idle unt il int r new x fer rdy?

4

Yes wr_reg(ep. DIEPTSIZn ) x act_1 set up_np_ in_pkt()

6

IN

7 8 9

Tim eout = ACK XFERCOMPL INTR idle unt il int r 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

215

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Slave Mode Bulk IN Transfer (Pipelined Transaction)

These notes refer to Figure 14.25 (p. 217)

1. The host attempts to read data (IN token) from an endpoint.

2. On receiving the IN token on the USB, the core returns a NAK handshake, because no data is available in the transmit FIFO.

3. To indicate that there was no data to send, the core generates an USB_DIEPx_INT.INTKNTXFEMP

(In Token Received When TxFIFO Empty) interrupt.

4. When data is ready, the application sets up the USB_DIEPx_TSIZ register with the transfer size and packet count.

5. The application writes one maximum packet size or less of data to the Non-periodic TxFIFO.

6. The host reattempts the IN token.

7. Because data is now ready in the FIFO, the core responds with the data, and the host ACKs it.

8. When the TxFIFO level falls below the halfway mark, the core generates a USB_GINTSTS.NPTXFEMP (NonPeriodic TxFIFO Empty) interrupt. This triggers the application to start writing additional data packets to the FIFO.

9. A data packet for the second transaction is ready in the TxFIFO.

10.A data packet for third transaction is ready in the TxFIFO while the data for the second packet is being sent on the bus.

11.The second data packet is sent to the host.

12.The last short packet is sent to the host.

13.Because the last packet is sent and XFERSIZE is now zero, the intended transfer is complete. The core generates a USB_DIEPx_INT.XFERCOMPL interrupt.

14.The application processes the interrupt and uses the setting of the USB_DIEPx_INT.XFERCOMPL

interrupt bit to determine that the intended transfer is complete 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

216

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.25. Slave Mode Bulk IN Transfer (Pipelined Transaction)

Host USB Device Application 2 1

IN NAK

3

INTKNTXFEMP INTR

4

idle unt il int r wr_reg( x fer_ size_reg) pkt_ cnt = 1

6

x act_ 1 of 3 IN

5 7

x act_ 1 set up_ np_in_pkt NPTX FEMP

8

x act_2 3 ACK IN

9

x act_ 2

2 1 1

x act_3 x act_2

1 0

set up_ np_in_pkt set up_ np_in_pkt ACK x act_3 3 IN 1 byt e ACK

1 2 1 3 1 4

XFERCOMPL INTR idle unt il int r

Slave Mode Bulk IN Two-Endpoint Transfer

These notes refer to Figure 14.26 (p. 218)

1. The host attempts to read data (IN token) from endpoint 1.

2. On receiving the IN token on the USB, the core returns a NAK handshake, because no data is available in the transmit FIFO for endpoint 1, and generates a USB_DIEP1_INT.INTKNTXFEMP (In Token Received When TxFIFO Empty) interrupt.

3. The application processes the interrupt and initializes USB_DIEP1_TSIZ register with the Transfer Size and Packet Count fields. The application starts writing the transaction data to the transmit FIFO.

4. The application writes one maximum packet size or less of data for endpoint 1 to the Non-periodic TxFIFO.

5. Meanwhile, the host attempts to read data (IN token) from endpoint 2.

6. On receiving the IN token on the USB, the core returns a NAK handshake, because no data is available in the transmit FIFO for endpoint 2, and the core generates a USB_DIEP2_INT.INTKNTXFEMP (In Token Received When TxFIFO Empty) interrupt.

7. Because the application has completed writing the packet for endpoint 1, it initializes the USB_DIEP2_TSIZ register with the Transfer Size and Packet Count fields. The application starts writing the transaction data into the transmit FIFO for endpoint 2.

8. The host repeats its attempt to read data (IN token) from endpoint 1.

9. Because data is now ready in the TxFIFO, the core returns the data, which the host ACKs.

10.Meanwhile, the application has initialized the data for the next two packets in the TxFIFO (ep2.xact1

and ep1.xact2, in order).

11.The host repeats its attempt to read data (IN token) from endpoint 2.

12.Because endpoint 2’s data is ready, the core responds with the data (ep2.xact_1), which the host ACKs.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

217

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

13.Meanwhile, the application has initialized the data for the next two packets in the TxFIFO (ep2.xact2

and ep1.xact3, in order). The application has finished initializing data for the two endpoints involved in this scenario.

14.The host repeats its attempt to read data (IN token) from endpoint 1.

15.Because data is now ready in the FIFO, the core responds with the data, which the host ACKs.

16.The host repeats its attempt to read data (IN token) from endpoint 2.

17.With data now ready in the FIFO, the core responds with the data, which the host ACKs.

18.With the last packet for endpoint 2 sent and its XFERSIZE now zero, the intended transfer is complete.

The core generates a USB_DIEP2_INT.XFERCOMPL interrupt for this endpoint.

19.The application processes the interrupt and uses the setting of the USB_DIEP2_INT.XFERCOMPL

interrupt bit to determine that the intended transfer on endpoint 2 is complete.

20.The host repeats its attempt to read data (IN token) from endpoint 1 (last transaction).

21.With data now ready in the FIFO, the core responds with the data, which the host ACKs.

22.Because the last endpoint one packet has been sent and XFERSIZE is now zero, the intended transfer is complete. The core generates a USB_DIEP1_INT.XFERCOMPL interrupt for this endpoint.

23.The application processes the interrupt and uses the setting of the USB_DIEP1_INT.XFERCOMPL

interrupt bit to determine that the intended transfer on endpoint 1 is complete.

Figure 14.26. Slave Mode Bulk IN Two-Endpoint Transfer

Host 1 8 5 11 USB

IN, ep1 NAK

6 2 Device

IN, ep2 NA K IN,ep1 ep1.xact_1

9

512 bytes .

ACK IN, ep2 512 bytes

12

ep1.xact_2

ep2.xact_1

13 10 Application

EP_NUM 1 register set XferSize = 1025 bytes PktCnt = 3 EPEna = 1 ep1.InTkn

TxF Emp intr

3

idle until intr ep2.InTknTxF

Emp intr

7

EP_NUM 2 registers XferSize = 522 bytes PktCnt = 2 EPEna = 1

ep2 drvr

idle until intr

4

ep1.setup_np_in_pkt

ep1.setup_np_in_pkt

ep2.setup_np_in_pkt

14

ep2.setup_np_in_pkt

ACK IN, ep1

15

ep2.xact_2

ep1.xact_2

512 bytes ep1.xact_3

ep1.xact_2

ep1.setup_np_in_pkt

16 20

ACK IN, ep2 10 bytes

17 18 19

idle until intr xfer_complete =1 IN,ep1 1 byte ACK

21 22

ep1.Xfer

Comp intr ep2.XferCompl intr xfer_complete = 1 idle until intr

23 14.4.4.2.3.13 Generic Periodic IN (Interrupt and Isochronous) Data Transfers

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 151) . Before it can communicate with the host, it must initialize an endpoint

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

218

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

as described in Endpoint Initialization (p. 186) . For packet writes in Slave mode, see: Packet Write in Slave Mode (p. 208) .

Application Requirements

1. Application requirements 1, 2, 3, and 4 of Generic Non-Periodic (Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode (p. 213) also apply to periodic IN data transfers,

except for a slight modification of Requirement 2.

• The application can only transmit multiples of maximum-packet-size data packets or multiples of maximum-packet-size packets, plus a short packet at the end. To transmit a few maximum-packet size packets and a short packet at the end of the transfer, the following conditions must be met.

• transfer size[epnum] = n * mps[epnum] + sp(where n is an integer # 0, and 0 >= sp < mps[epnum]) • If (sp > 0), packet count[epnum] = n + 1Otherwise, packet count[epnum] = n; • mc[epnum] = packet count[epnum] • The application cannot transmit a zero-length data packet at the end of transfer. It can transmit a single zero-length data packet by it self. To transmit a single zero-length data packet, • transfer size[epnum] = 0 • packet count[epnum] = 1 • mc[epnum] = packet count[epnum] 2. The application can only schedule data transfers 1 frame at a time.

• (USB_DIEPx_TSIZ.MC – 1) * USB_DIEPx_CTL.MPS =< USB_DIEPx_TSIZ.XFERSIZE =< USB_DIEPx_TSIZ.MC * USB_DIEPx_CTL.MPS

• USB_DIEPx_TSIZ.PKTCNT = USB_DIEPx_TSIZ.MC

• If USB_DIEPx_TSIZ.XFERSIZE < USB_DIEPx_TSIZ.MC * USB_DIEPx_CTL.MPS, the last data packet of the transfer is a short packet.

3. This step is not applicable for isochronous data transfers, only for interrupt transfers.

The application can schedule data transfers for multiple frames, only if multiples of max packet sizes (up to 3 packets), must be transmitted every frame. This is can be done, only when the core is operating in DMA mode. This is not a recommended mode though.

• ((n*USB_DIEPx_TSIZ.MC) - 1)*USB_DIEPx_CTL.MPS <= USB_DIEPx_TSIZ.XFERSIZE <= n*USB_DIEPx_TSIZ.MC*USB_DIEPx_CTL.MPS

• USB_DIEPx_TSIZ.PKTCNT = n*USB_DIEPx_TSIZ.MC

• n is the number of frames for which the data transfers are scheduled Data Transmitted per frame in this case would be USB_DIEPx_TSIZ.MC*USB_DIEPx_CTL.MPS, in all the frames except the last one. In the frame “n”, the data transmitted would be (USB_DIEPx_TSIZ.XFERSIZE - (n-1)*USB_DIEPx_TSIZ.MC*USB_DIEPx_CTL.MPS) 4. For Periodic IN endpoints, the data must always be prefetched 1 frame ahead for transmission in the next frame. This can be done, by enabling the Periodic IN endpoint 1 frame ahead of the frame in which the data transfer is scheduled.

5. The complete data to be transmitted in the frame must be written into the transmit FIFO (either by the application or the DMA), before the Periodic IN token is received. Even when 1 DWORD of the data to be transmitted per frame is missing in the transmit FIFO when the Periodic IN token is received, the core behaves as when the FIFO was empty. When the transmit FIFO is empty, 6. A zero data length packet would be transmitted on the USB for ISO IN endpoints • A NAK handshake would be transmitted on the USB for INTR IN endpoints 7. For a High Bandwidth IN endpoint with three packets in a frame, the application can program the endpoint FIFO size to be 2*max_pkt_size and have the third packet load in after the first packet has been transmitted on the USB.

Internal Data Flow

1. The application must set the Transfer Size and Packet Count fields in the endpoint-specific registers and enable the endpoint to transmit the data.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

219

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

2. In Slave mode, the application must also write the required data to the associated transmit FIFO for the endpoint. In DMA mode, the core fetches the data for the endpoint from memory, according to the application setting.

3. Every time either the core’s internal DMA (in DMA mode) or the application (in Slave mode) writes a packet to the transmit FIFO, the transfer size for that endpoint is decremented by the packet size. The data is fetched from DMA or application memory until the transfer size for the endpoint becomes 0.

4. When an IN token is received for an periodic endpoint, the core transmits the data in the FIFO, if available. If the complete data payload (complete packet) for the frame is not present in the FIFO, then the core generates an IN Token Received When TxFIFO Empty Interrupt for the endpoint.

• A zero-length data packet is transmitted on the USB for isochronous IN endpoints • A NAK handshake is transmitted on the USB for interrupt IN endpoints 5. The packet count for the endpoint is decremented by 1 under the following conditions: • For isochronous endpoints, when a zero- or non-zero-length data packet is transmitted • For interrupt endpoints, when an ACK handshake is transmitted • When the transfer size and packet count are both 0, the Transfer Completed interrupt for the endpoint is generated and the endpoint enable is cleared.

6. At the “Periodic frame Interval” (controlled by USB_DCFG.PERFRINT), when the core finds non empty any of the isochronous IN endpoint FIFOs scheduled for the current frame non-empty, the core generates a USB_GINTSTS.INCOMPISOIN interrupt.

Application Programming Sequence (Transfer Per Frame)

1. Program the USB_DIEPx_TSIZ register. In DMA mode, also program the USB_DIEPx_DMAADDR register.

2. Program the USB_DIEPx_CTL register with the endpoint characteristics and set the CNAK and Endpoint Enable bits.

3. In Slave mode, write the data to be transmitted in the next frame to the transmit FIFO.

4. Asserting the USB_DIEPx_INT.INTKNTXFEMP (In Token Received When TxFifo Empty) interrupt indicates that either the DMA or application has not yet written all data to be transmitted to the transmit FIFO.

5. If the interrupt endpoint is already enabled when this interrupt is detected, ignore the interrupt. If it is not enabled, enable the endpoint so that the data can be transmitted on the next IN token attempt.

• If the isochronous endpoint is already enabled when this interrupt is detected, see Incomplete Isochronous IN Data Transfers (p. 210) for more details.

6. The core handles timeouts internally on interrupt IN endpoints programmed as periodic endpoints without application intervention. The application, thus, never detects a USB_DIEPx_INT.TIMEOUT

interrupt for periodic interrupt IN endpoints.

7. Asserting the USB_DIEPx_INT.XFERCOMPL interrupt with no USB_DIEPx_INT.INTKNTXFEMP (In Token Received When TxFifo Empty) interrupt indicates the successful completion of an isochronous IN transfer. A read to the USB_DIEPx_TSIZ register must indicate transfer size = 0 and packet count = 0, indicating all data is transmitted on the USB.

8. Asserting the USB_DIEPx_INT.XFERCOMPL interrupt, with or without indicate transfer size = 0 and packet count = 0, indicating all data is transmitted on the USB.

the USB_DIEPx_INT.INTKNTXFEMP (In Token Received When TxFifo Empty) interrupt, indicates the successful completion of an interrupt IN transfer. A read to the USB_DIEPx_TSIZ register must 9. Asserting the USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt with none of the aforementioned interrupts indicates the core did not receive at least 1 periodic IN token in the current frame.

10.For isochronous IN endpoints, see Incomplete Isochronous IN Data Transfers (p. 210) , for more

details.

14.4.4.2.3.14 Generic Periodic IN Data Transfers Using the Periodic Transfer Interrupt Feature

This section describes a typical Periodic IN (ISOC / INTR) data transfer with the Periodic Transfer Interrupt feature.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

220

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

1. Before setting up an IN transfer, the application must ensure that all data to be transmitted as part of the IN transfer is part of a single buffer, and must program the size of that buffer and its start address (in DMA mode) to the endpoint-specific registers.

2. For IN transfers, the Transfer Size field in the Endpoint Transfer Size register denotes a payload that constitutes multiple maximum-packet-size packets and a single short packet. This short packet is transmitted at the end of the transfer.

a. To transmit a few maximum-packet-size packets and a short packet at the end of the transfer: • Transfer size[epnum] = n * mps[epnum] + sp (where n is an integer > 0, and 0 < sp < mps[epnum]. A higher value of n reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt) • If (sp > 0), then packet count[epnum] = n + 1. Otherwise, packet count[epnum] = n b. To transmit a single zero-length data packet: • Transfer size[epnum] = 0 • Packet count[epnum] = 1 c. To transmit a few maximum-packet-size packets and a zero-length data packet at the end of the transfer, the application must split the transfer in two parts. The first sends maximum-packet-size data packets and the second sends the zero-length data packet alone.

• First transfer: transfer size[epnum] = n * mps[epnum]; packet count = n; • Second transfer: transfer size[epnum] = 0; packet count = 1; d. The application can only transmit multiples of maximum-packet-size data packets or multiples of maximum-packet-size packets, plus a short packet at the end. To transmit a few maximum-packet size packets and a short packet at the end of the transfer, the following conditions must be met.

• transfer size[epnum] = n * mps[epnum] + sp (where n is an integer > 0, and 0 < sp < mps[epnum]) • If (sp > 0), packet count[epnum] = n + 1 Otherwise, packet count[epnum] = n; • mc[epnum] = number of packets to be sent out in a frame.

e. The application cannot transmit a zero-length data packet at the end of transfer. It can transmit a single zero-length data packet by itself. To transmit a single zero-length data packet, • transfer size[epnum] = 0 • packet count[epnum] = 1 • mc[epnum] = packet count[epnum] 3. In DMA mode, the core fetches an IN data packet from the memory, always starting at a DWORD boundary. If the maximum packet size of the IN endpoint is not a multiple of 4, the application must arrange the data in the memory with pads inserted at the end of a maximum-packet-size packet so that a new packet always starts on a DWORD boundary.

4. Once an endpoint is enabled for data transfers, the core updates the Transfer Size register. At the end of IN transfer, which ended with a Endpoint Disabled interrupt, the application must read the Transfer Size register to determine how much data posted in the transmit FIFO was already sent on the USB.

• Data fetched into transmit FIFO = Application-programmed initial transfer size - core-updated final transfer size • Data transmitted on USB = (application-programmed initial packet count - Core updated final packet count) * mps[epnum] • Data yet to be transmitted on USB = (Application-programmed initial transfer size - data transmitted on USB) 5. The application can schedule data transfers for multiple frames, only if multiples of max packet sizes (up to 3 packets), must be transmitted every frame. This is can be done, only when the core is operating in DMA mode.

• ((n*USB_DIEPx_TSIZ.MC) - 1)*USB_DIEPx_CTL.MPS <= USB_DIEPx_TSIZ.XFERSIZE <= n*USB_DIEPx_TSIZ.MC*USB_DIEPx_CTL.MPS

• USB_DIEPx_TSIZ.PKTCNT = n*USB_DIEPx_TSIZ.MC

• n is the number of frames for which the data transfers are scheduled. Data Transmitted per frame in this case is USB_DIEPx_TSIZ.MC*USB_DIEPx_CTL.MPS in all frames except the last one. In frame n, the data transmitted is (USB_DIEPx_TSIZ.XFERSIZE – (n – 1) * USB_DIEPx_TSIZ.MC

* USB_DIEPx_CTL.MPS) 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

221

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

6. For Periodic IN endpoints, the data must always be prefetched 1 frame ahead for transmission in the next frame. This can be done, by enabling the Periodic IN endpoint 1 frame ahead of the frame in which the data transfer is scheduled.

7. The complete data to be transmitted in the frame must be written into the transmit FIFO, before the Periodic IN token is received. Even when 1 DWORD of the data to be transmitted per frame is missing in the transmit FIFO when the Periodic IN token is received, the core behaves as when the FIFO was empty. When the transmit FIFO is empty, • A zero data length packet would be transmitted on the USB for ISOC IN endpoints • A NAK handshake would be transmitted on the USB for INTR IN endpoints • USB_DIEPx_TSIZ.PKTCNT is not decremented in this case.

8. For a High Bandwidth IN endpoint with three packets in a frame, the application can program the endpoint FIFO size to be 2 * max_pkt_size and have the third packet load in after the first packet has been transmitted on the USB.

Figure 14.27. Periodic IN Application Flow for Periodic Transfer Interrupt Feature

START

NOTE Requirements For XferSize and PktCnt programming 1 . 2 . 5 . Core will read packets from System Memory only from DWORD aligned .

6 . Short Packets are not allowed in between Xfers If MaxPktSize is not DWORD aligned .

7 . Thresholding in not supported for the Periodic Transfer Interrupt enhancement

· · Int ialize variables · Program t he DMA address DIEPDMA

START Address of the Data Memory

· Program Xfer USB_DIEPx _TSIZ XFERSIZE = USB_DIEPx _TSIZ PKTCNT =

XferSize Spanning across multiple Xfers Program PktCnt for multiple Xfers

USB_DIEPx _TSIZ.MC

= Max Number of Packets in a

· Program t he Global INT STS USB_GINTMSK. INCOMPLSOCINMSK = 0b0

/ / Mask IncompISOCIN Interrupt

· Program EP Ct rl regist er t o st art t he x fer USB_DIEPx _CTL.CNAK = t x_fifo_ num; USB_DIEPx _CTL.EPENA

= 0b0 USB_DIEPx _CTL.EPDIS = If USB_DIEPx _TSIZ XFERSIZE != 0 or USB_DIEPx _TSIZ PKTCNT != 0 no De- a llo ca t e Da t a Ra m Mem o r y · Yes ret urn

Internal Data Flow

1. The application must set the Transfer Size and Packet Count fields in the endpoint-specific registers and enable the endpoint to transmit the data.

• The application must enable the USB_DCTL.IGNRFRMNUM

2. When an isochronous OUT endpoint is enabled by setting the Endpoint Enable and clearing the NAK bits, the Even/Odd frame will be ignored by the core.

• Subsequently the core updates the Even / Odd bit on its own 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

222

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

3. Every time either the core’s internal DMA writes a packet to the transmit FIFO, the transfer size for that endpoint is decremented by the packet size. The data is fetched from DMA or application memory until the transfer size for the endpoint becomes 0.

4. When an IN token is received for a periodic endpoint, the core transmits the data in the FIFO, if available. If the complete data payload (complete packet) for the frame is not present in the FIFO, then the core generates an IN Token Received When TxFifo Empty Interrupt for the endpoint.

• A zero-length data packet is transmitted on the USB for isochronous IN endpoints • A NAK handshake is transmitted on the USB for interrupt IN endpoints 5. If an IN token comes for an endpoint on the bus, and if the corresponding TxFIFO for that endpoint has at least 1 packet available, and if the USB_DIEPx_CTL.NAK bit is not set, and if the internally maintained even/odd bit match with the bit 0 of the current frame number, then the core will send this data out on the USB. The core will also decrement the packet count. Core also toggles the MultCount in USB_DIEPx_CTL register and based on the value of MultCount the next PID value is sent.

• If the IN token results in a timeout (core did not receive the handshake or handshake error), core rewind the FIFO pointers. Core does not decrement packet count. It does not toggle PID.

USB_DIEPx_INT.TIMEOUT interrupt will be set which the application could check.

• At the end of periodic frame interval (Based on the value programmed in the USB_DCFG.PERFRINT register, core will internally set the even/odd internal bit to match the next frame.

6. The packet count for the endpoint is decremented by 1 under the following conditions: • For isochronous endpoints, when a zero- or non-zero-length data packet is transmitted • For interrupt endpoints, when an ACK handshake is transmitted 7. The data PID of the transmitted data packet is based on the value of USB_DIEPx_TSIZ.MC

programmed by the application. In case the USB_DIEPx_TSIZ.MC value is set to 3 then, for a particular frame the core expects to receive 3 Isochronous IN token for the respective endpoint. The data PIDs transmitted will be D2 followed by D1 and D0 respectively for the tokens.

• If any of the tokens responded with a zero-length packet due to non-availability of data in the TxFIFO, the packet is sent in the next frame with the pending data PID. For example, in a frame, the first received token is responded to with data and data PID value D2. If the second token is responded to with a zero-length packet, the host is expected not to send any more tokens for the respective endpoint in the current frame. When a token arrives in the next frame it will be responded to with the pending data PID value of D1.

• Similarly the second token of the current frame gets responded with D0 PID. The host is expected to send only two tokens for this frame as the first token got responded with D1 PID.

8. When the transfer size and packet count are both 0, the Transfer Completed interrupt for the endpoint is generated and the endpoint enable is cleared.

9. The USB_GINTSTS.INCOMPISOIN will be masked by the application hence at the Periodic Frame interval (controlled by USB_DCFG.PERFRINT), even though the core finds non-empty any of the isochronous IN endpoint FIFOs, USB_GINTSTS.INCOMPISOIN interrupt will not be generated.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

223

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.28. Periodic IN Core Internal Flow for Periodic Transfer Interrupt Feature

START

If (USB_DIEPx _CTL.CNAK = 0b1) && (USB_DIEPx CTL.EPENA = 0b1) && (USB_DCTL.IGNRFRMNUM = 0b1)

NOTE 1 . 2 . 3 . Core will fetch data only from DWORD Aligned addresses 4 . The DATA PID of the packet which was not sent in the previous ( micro) frame will remain the same 5 . Short Packets are not allowed in between transfers can have a Short Packet

IN Token From Host

YES

Check Data Available

NO · · Int errupt IN Xm it NAK Packet WAIT YES · · ·

not change

· · · · Transm it Dat a Packet

If 0 If PktCnt 0 && XferSize

YES NO USB_DIEPx _INT.XFERCOMPL = 1 ret urn

14.4.5 OTG Revision 1.3 Programming Model

This section describes the OTG programming model when the core is configured to support OTG Revision 1.3 of the specification.

The core is an OTG device supporting HNP and SRP. When the core is connected to an “A” plug, it is referred to as an A-device. When the core is connected to a “B” plug it is referred to as a B-device. In Host mode, the core turns off Vbus to conserve power. SRP is a method by which the B-device signals the A-device to turn on Vbus power. A device must perform both data-line pulsing and Vbus pulsing, but a host can detect either data-line pulsing or Vbus pulsing for SRP. HNP is a method by which the B-device negotiates and switches to host role. In Negotiated mode after HNP, the B-device suspends the bus and reverts to the device role.

14.4.5.1 A-Device Session Request Protocol

The application must set the SRP-Capable bit in the Core USB Configuration register. This enables the core to detect SRP as an A-device.

1. To save power, the application suspends and turns off port power when the bus is idle by writing the Port Suspend and Port Power bits in the Host Port Control and Status register.

2. PHY indicates port power off by detecting that VBUS voltage level is no longer valid.

3. The device must detect SE0 for at least 2 ms to start SRP when Vbus power is off.

4. To initiate SRP, the device turns on its data line pull-up resistor for 5 to 10 ms. The core detects data-line pulsing.

5. The device drives Vbus above the A-device session valid (2.0 V minimum) for Vbus pulsing.

The core interrupts the application on detecting SRP. The Session Request Detected bit is set in Global Interrupt Status register (USB_GINTSTS.SESSREQINT).

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

224

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

6. The application must service the Session Request Detected interrupt and turn on the Port Power bit by writing the Port Power bit in the Host Port Control and Status register. The PHY indicates port power-on by detecting a valid VBUS level.

7. When the USB is powered, the device connects, completing the SRP process.

14.4.5.2 B-Device Session Request Protocol

The application must set the SRP-Capable bit in the Core USB Configuration register. This enables the core to initiate SRP as a B-device. SRP is a means by which the core can request a new session from the host.

1. To save power, the host suspends and turns off port power when the bus is idle. PHY indicates port power off by detecting a not valid VBUS level.

The core sets the Early Suspend bit in the Core Interrupt register after 3 ms of bus idleness. Following this, the core sets the USB Suspend bit in the Core Interrupt register.

The PHY indicates the end of the B-device session by detecting a VBUS level below session valid.

2. PHY to enables the VBUS discharge function to speed up Vbus discharge.

3. The PHY indicates the session’s end by detecting a session end voltage level on VBUS. This is the initial condition for SRP. The core requires 2 ms of SE0 before initiating SRP.

The application must wait until Vbus discharges to 0.2 V after USB_GOTGCTL.BSESVLD is deasserted. This discharge time can be obtained from the datasheet.

4. The application initiates SRP by writing the Session Request bit in the OTG Control and Status register. The core perform data-line pulsing followed by Vbus pulsing.

5. The host detects SRP from either the data-line or Vbus pulsing, and turns on Vbus. The PHY indicates Vbus power-on by detecting a valid VBUS level.

6. The core performs Vbus pulsing.

The host starts a new session by turning on Vbus, indicating SRP success. The core interrupts the application by setting the Session Request Success Status Change bit in the OTG Interrupt Status register. The application reads the Session Request Success bit in the OTG Control and Status register.

7. When the USB is powered, the core connects, completing the SRP process.

14.4.5.3 A-Device Host Negotiation Protocol

HNP switches the USB host role from the A-device to the B-device. The application must set the HNP Capable bit in the Core USB Configuration register to enable the core to perform HNP as an A#device.

1. The core sends the B-device a SetFeature b_hnp_enable descriptor to enable HNP support. The B-device’s ACK response indicates that the B-device supports HNP. The application must set Host Set HNP Enable bit in the OTG Control and Status register to indicate to the core that the B-device supports HNP.

2. When it has finished using the bus, the application suspends by writing the Port Suspend bit in the Host Port Control and Status register.

3. When the B-device observes a USB suspend, it disconnects, indicating the initial condition for HNP.

The B-device initiates HNP only when it must switch to the host role; otherwise, the bus continues to be suspended.

The core sets the Host Negotiation Detected interrupt in the OTG Interrupt Status register, indicating the start of HNP.

The PHY turns off the D+ and D- pulldown resistors to indicate a device role. The PHY enable the D + pull-up resistor indicates a connect for B-device.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

225

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

The application must read the Current Mode bit in the OTG Control and Status register to determine Device mode operation.

4. The B-device detects the connection, issues a USB reset, and enumerates the core for data traffic.

5. The B-device continues the host role, initiating traffic, and suspends the bus when done.

The core sets the Early Suspend bit in the Core Interrupt register after 3 ms of bus idleness. Following this, the core sets the USB Suspend bit in the Core Interrupt register.

6. In Negotiated mode, the core detects the suspend, disconnects, and switches back to the host role.

The core turns on the D+ and D- pulldown resistors to indicate its assumption of the host role.

7. The core sets the Connector ID Status Change interrupt in the OTG Interrupt Status register. The application must read the connector ID status in the OTG Control and Status register to determine the core’s operation as an A-device. This indicates the completion of HNP to the application. The application must read the Current Mode bit in the OTG Control and Status register to determine Host mode operation.

8. The B-device connects, completing the HNP process.

14.4.5.4 B-Device Host Negotiation Protocol

HNP switches the USB host role from B-device to A-device. The application must set the HNP-Capable bit in the Core USB Configuration register to enable the core to perform HNP as a B-device.

1. The A-device sends the SetFeature b_hnp_enable descriptor to enable HNP support. The core’s ACK response indicates that it supports HNP. The application must set the Device HNP Enable bit in the OTG Control and Status register to indicate HNP support.

The application sets the HNP Request bit in the OTG Control and Status register to indicate to the core to initiate HNP.

2. When it has finished using the bus, the A-device suspends by writing the Port Suspend bit in the Host Port Control and Status register.

The core sets the Early Suspend bit in the Core Interrupt register after 3 ms of bus idleness. Following this, the core sets the USB Suspend bit in the Core Interrupt register.

The core disconnects and the A-device detects SE0 on the bus, indicating HNP. The core enables the D+ and D- pulldown resistors to indicate its assumption of the host role.

The A-device responds by activating its D+ pull-up resistor within 3 ms of detecting SE0. The core detects this as a connect.

The core sets the Host Negotiation Success Status Change interrupt in the OTG Interrupt Status register, indicating the HNP status. The application must read the Host Negotiation Success bit in the OTG Control and Status register to determine host negotiation success. The application must read the Current Mode bit in the Core Interrupt register (USB_GINTSTS) to determine Host mode operation.

3. The application sets the reset bit (USB_HPRT.PRTRST) and the core issues a USB reset and enumerates the A-device for data traffic 4. The core continues the host role of initiating traffic, and when done, suspends the bus by writing the Port Suspend bit in the Host Port Control and Status register.

5. In Negotiated mode, when the A-device detects a suspend, it disconnects and switches back to the host role. The core disables the D+ and D- pulldown resistors to indicate the assumption of the device role.

6. The application must read the Current Mode bit in the Core Interrupt (USB_GINTSTS) register to determine the Host mode operation.

7. The core connects, completing the HNP process.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

226

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.4.6 OTG Revision 2.0 Programming Model

OTG Revision 2.0 supports the new Attach Detection Protocol (ADP). This protocol enables a local device (an OTG device or Embedded Host) to detect when a remote device is attached or detached.

Note

ADP is not supported by the core.

In addition to ADP, OTG Revision 2.0 also supports enhanced SRP and HNP, which are described in the following sections:

• OTG Revision 2.0 Session Request Protocol (p. 227)

• OTG Revision 2.0 Host Negotiation Protocol (p. 229)

Note

VBUS pulsing is not supported in OTG Revision 2.0 mode.

14.4.6.1 OTG Revision 2.0 Session Request Protocol

When the core is behaving as an A-device, it can power off VBUS when no session is active until the B-device initiates a SRP. The SRP detection is handled by the core.

Figure 14.29 (p. 228) illustrates the programming steps that need to be performed by A-device’s

application (core as A-device) when B-device initiates a SRP to establish a connection.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

227

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.29. SRP Detection by Core When Operating as A-device

Host m ode (PHY not driving VBUS) Program USB_GINTMSK.

(Unm ask OTGINT, MODEMIS, SESSREQINT) No If host ’ s applicat ion decides t o t urn on VBUS volunt arily, t hen t he applicat ion need not wait for SRP from device No Int errupt?

Yes Read USB_GINTSTS GINTSTS.

SESSREQINT = 1 ?

Yes Host Init ializat ion St eps. Refer t o t he Host Init ializat ion sect ion of t his chapt er for m ore inform at ion.

(In t his st ep t he OTG FSM is in a_host st at e.) Not e: If MODEMIS int errupt is det ect ed during t his process, connect or has been plugged out or int erchanged. confirm ed by reading USB_GINTSTS.CONIDSTSCHNG

Host Transact ions

Figure 14.30 (p. 229) illustrates the steps that need to be performed by B-device’s application (core

as B-device) in order to establishing a connection with A-device by signaling a SRP.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

228

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.30. SRP Initiation by the Core When Acting as a B-Device

Device (OTG FSM in b_idle st at e) 1. Program USB_GINTMSK (unm ask OTGINT) 2. Read USB_GOTGCTL Yes VBUS is already being driven and hence t here is no need for a SRP ) USB_GOTGCTL.

BSESVLD = 1 ?

No Device Init ializat ion St eps . inform at ion Device Init ializat ion sect ion of t his chapt er.

Set USB_GOTGCTL.

SESREQ = 1 Int errupt ?

No Yes No Read USB_GINTSTS No USB_GINTSTS.

OTGINT = 1?

Yes Read USB_GOTGINT No Device Transact ions USB_GOTGINT .

SESREQSUCS TSCHNG = Yes 1. Read USB_GOTGCTL 2. Clear USB_GOTGINT .SESREQSU

CSTSCHNG by writ ing a USB_GOTGCTL .

SESREQSCS = Yes Device Init ializat ion St eps. inform at ion Device Init ializat ion sect ion of t his .

Note

The programming flow illustrated in Figure 14.30 (p. 229) is similar to OTG revision 1.3.

This is because the presence or absence of VBUS pulsing is transparent to the application.

14.4.6.2 OTG Revision 2.0 Host Negotiation Protocol

When the core is operating as A-device, the application must execute a GetStatus() operation to the B device with a frequency of THOST_REQ_POLL to determine the state of the host request flag in the B-device. If the host request flag is set in B-device it must program the core to change its role within THOST_REQ_SUSP.

Figure 14.31 (p. 230) shows the programming steps that need to be performed by A-device’s application (core as A-device) in order to change its role to device. In Figure 14.31 (p. 230) , the A-

device performs a role change, becomes a B-device and then reverts back to host (A-device) mode of operation.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

229

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.31. HNP When the Core is an A-Device

Host t o Device t o Host Host m ode (Send Set Feat ure Com m and t o enable b_hnp_enable feat ure in HNP capable devices. HNP polling m echanism is also involved. This is done when OTG FSM is in a_host st at e) C1 1. Unm ask USB_GINTSTS.ERLYSUSP

of t his chapt er , see Device Init ializat ion sect ion Program Unm ask USB_GINTSTS. OTGINT Int errupt ?

No No Yes Read USB_GINTSTS Yes St art of Device t ransact ions End of Device t ransact ions Int errupt ?

No Read USB_GINTSTS Check t hat CURMOD = 0 Yes Host Init ializat ion St eps . inform at ion Init ializat ion sect ion .

Host Mode Transact ions No No Read USB_GINTSTS No USB_GINTSTS.

OTGINT Yes Int errupt ?

No Yes USB_GOTGINT.

HSTNEGDET =1?

Yes Read USB_GINTSTS.CURMOD

USB_GINTSTS.

ERLYSUSP = 1 ?

Yes Int errupt ?

No No Read USB_GINTSTS USB_GINTSTS.

USBSUSP = 1 ?

Yes Applicat ion st art s 200 Rem ain as Host applicat ion can t ake a call whet her t o swit ch off VBUS or not ) No USB_GINTSTS.

CURMOD = 0?

Yes C1 No Int errupt wit hin 200 m s yes Read USB_GINTSTS USB_GINTSTS.WKUPINT = 1 or USB_GINTSTS.RESETDET ?

Figure 14.32 (p. 231) shows the programming steps that need to be performed by B-device’s application (core as B-device) in order to change its role to Host. In Figure 14.32 (p. 231) , the B-

device performs a role change, becomes a Host and then reverts back to Device mode of operation.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

230

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 14.32. HNP When the Core is a B-Device

C1 Device m ode (Receive Set Feat ure Com m and and OTG FSM is in b_peripheral st at e) 1. Program USB_GOTGCTL.DEVSETHNPEN = 1 2. Program USB_GOTGCTL.HNPREQ = 1 Int errupt ?

No No Read USB_GINTSTS USB_GINTSTS.

ERLYSUSP = 1?

Yes No Int errupt ?

No Read USB_GINTSTS No USB_GINTSTS.

USBSUSP = 1?

Yes Int errupt ?

No Yes No Read USB_GINTSTS USB_GINTSTS.

OTGINT = 1?

Yes C1 Read USB_GOTGINT USB_GOTGINT.

HSTNEGSUCSTSCHNG = 1 ?

Yes Clear USB_GOTGINT.

HSTNEGSUCSTSCHNG Read USB_GOTGCTL USB_GOTGCTL.

HSTNEGSUCS = 1 ?

Yes Read USB_GINTSTS. Check t hat CURMOD = 1.

No Rem ain as Device Host Init ializat ion St eps (USB_HPRT.PRTPWR should not be program m ed). For m ore inform at ion, see Host Init ializat ion sect ion in t his chapt er.

St art of Host t ransact ions End of Host t ransact ions Set USB_HPRT.PRTSUSP = 1.

Unm ask GINTSTS.OTGINT.

(USB_HPRT.PRTPWR should not be program m ed) Does B device want t o rem ain host?

No No Yes Program USB_HPRT.PRTRES = 1 for a predefined t im e.

The applicat ion should ensure t hat t his process happens wit hin m s Int errupt ?

No Read USB_GINTSTS USB_GINTSTS.

DISCONNINT = 1 ?

Yes Read USB_GINTSTS.CURMOD

and ensure it is 0. Device Init ializat ion St eps Device Init ializat ion Device Mode Transact ions

Note

During HNP process where the B-device is going to assume the role of a host, the B-device application needs to ensure that a USB reset process is programmed (in USB_HPRT 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

231

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

register) within 150 ms (TB_ACON_BSE0) of getting a USB_HPRT.PRTCONNDET

interrupt.

14.4.7 FIFO RAM Allocation 14.4.7.1 Data FIFO RAM Allocation

External RAM must be allocated among different FIFOs in the core before any transactions can start.

The application must follow this procedure every time it changes core FIFO RAM allocation.

The application must allocate data RAM per FIFO based on the AHB’s operating frequency, the PHY Clock frequency, the available AHB bandwidth, and the performance required on the USB. Based on the above mentioned criteria, the application must provide a table as described below with RAM sizes for each FIFO in each mode.

The core shares a single FIFO RAM between transmit FIFO(s) and receive FIFO.

In DMA mode—The FIFO RAM is also used for storing the some register information.

The Device mode Endpoint DMA address registers (USB_DIEP0DMAADDR, USB_DOEP0DMAADDR, USB_DIEPx_DMAADDR, USB_DOEPx_DMAADDR) and Host mode Channel DMA registers (USB_HCx_DMAADDR) are stored in the FIFO RAM.

• These register information are stored at the end of the FIFO RAM after the space allocated for receive and Transmit FIFO. These register space must also be taken into account when calculating the total FIFO depth of the core as explained in the following sections.

The registers USB_DIEPx_DMAADDR/USB_DOEPx_DMAADDR are maintained in RAM.

The following rules apply while calculating how much RAM space must be allocated to store these registers.

Host Mode:

• Slave mode only: No space needed.

• DMA mode: One location per channel.

Device Mode:

• Slave mode only: No space needed.

• DMA mode: One location per end point direction.

14.4.7.1.1 Device Mode 14.4.7.1.1.1 Tx FIFO Operation

When allocating data RAM for FIFOs in Device mode keep in mind these factors: 1. Receive FIFO RAM allocation: • RAM for SETUP Packets: 4 * n + 6 locations must be Reserved in the receive FIFO to receive up to n SETUP packets on control endpoints, where n is the number of control endpoints the device core supports. The core does not use these locations, which are Reserved for SETUP packets, to write any other data.

• One location for Global OUT NAK • Status information is written to the FIFO along with each received packet. Therefore, a minimum space of (Largest Packet Size / 4) + 1 must be allotted to receive packets. If a high-bandwidth endpoint is enabled, or multiple isochronous endpoints are enabled, then at least two (Largest 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

232

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Packet Size / 4) + 1 spaces must be allotted to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1 spaces are recommended so that when the previous packet is being transferred to AHB, the USB can receive the subsequent packet. If AHB latency is high, you must allocate enough space to receive multiple packets. This is critical to prevent dropping any isochronous packets.

• Along with each endpoint's last packet, transfer complete status information is also pushed to the FIFO. Typically, one location for each OUT endpoint is recommended.

2. Transmit FIFO RAM Allocation: The minimum RAM space required for each IN Endpoint Transmit FIFO is the maximum packet size for that particular IN endpoint.

More space allocated in the transmit IN Endpoint FIFO results in a better performance on the USB and can hide latencies on the AHB.

Table 14.3.

FIFO Name

Receive data FIFO Transmit FIFO 0 Transmit FIFO 1 Transmit FIFO 2 ...

Transmit FIFO i

Data RAM Size

rx_fifo_size. This must include RAM for setup packets, OUT endpoint control information and data OUT packets, as mentioned earlier.

tx_fifo_size[0] tx_fifo_size[1] tx_fifo_size[2] ...

tx_fifo_size[i] With this information, the following registers must be programmed as follows: 1. Receive FIFO Size Register (USB_GRXFSIZ) USB_GRXFSIZ.Receive FIFO Depth = rx_fifo_size; 2. Device IN Endpoint Transmit FIFO0 Size Register (USB_GNPTXFSIZ) USB_GNPTXFSIZ.non-periodic Transmit FIFO Depth = tx_fifo_size[0]; USB_GNPTXFSIZ.non-periodic Transmit RAM Start Address = rx_fifo_size; 3. Device IN Endpoint Transmit FIFO#1 Size Register (USB_DIEPTXF1) USB_DIEPTXF1. Transmit RAM Start Address = USB_GNPTXFSIZ.FIFO0 Transmit RAM Start Address + tx_fifo_size[0]; 4. Device IN Endpoint Transmit FIFO#2 Size Register (USB_DIEPTXF2) USB_DIEPTXF2.Transmit RAM Start Address = USB_DIEPTXF1.Transmit RAM Start Address + tx_fifo_size[1]; 5. Device IN Endpoint Transmit FIFO#i Size Register (USB_DIEPTXFi) USB_DIEPTXFm.Transmit RAM Start Address = USB_DIEPTXFi-1.Transmit RAM Start Address + tx_fifo_size[i-1]; 6. The transmit FIFOs and receive FIFO must be flushed after the RAM allocation is done, for the proper functioning of the FIFOs.

• USB_GRSTCTL.TXFNUM = 0x10 • USB_GRSTCTL.TXFFLSH = 1 • USB_GRSTCTL.RXFFLSH = 1 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

233

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

The application must wait until the TXFFLSH bit and the RXFFLSH bits are cleared before performing any operation on the core.

14.4.7.1.2 Host Mode

Considerations for allocating data RAM for Host Mode FIFOs are listed here:

Receive FIFO RAM allocation:

Status information is written to the FIFO along with each received packet. Therefore, a minimum space of (Largest Packet Size / 4) + 2 must be allotted to receive packets. If a high-bandwidth channel is enabled, or multiple isochronous channels are enabled, then at least two (Largest Packet Size / 4) + 2 spaces must be allotted to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 2 spaces are recommended so that when the previous packet is being transferred to AHB, the USB can receive the subsequent packet. If AHB latency is high, you must allocate enough space to receive multiple packets.

Along with each host channel’s last packet, information on transfer complete status and channel halted is also pushed to the FIFO. So two locations must be allocated for this.

For handling NAK in DMA mode, the application must determine the number of Control/Bulk OUT endpoint data that must fit into the TX_FIFO at the same instant. Based on this, one location each is required for Control/Bulk OUT endpoints.

For example, when the host addresses one Control OUT endpoint and three Bulk OUT endpoints, and all these must fit into the non-periodic TX_FIFO at the same time, then four extra locations are required in the RX FIFO to store the rewind status information for each of these endpoints.

Transmit FIFO RAM allocation

The minimum amount of RAM required for the Host Non-periodic Transmit FIFO is the largest maximum packet size among all supported non-periodic OUT channels.

More space allocated in the Transmit Non-periodic FIFO results in better performance on the USB and can hide AHB latencies. Typically, two Largest Packet Sizes’ worth of space is recommended, so that when the current packet is under transfer to the USB, the AHB can get the next packet. If the AHB latency is large, then you must allocate enough space to buffer multiple packets.

The minimum amount of RAM required for Host periodic Transmit FIFO is the largest maximum packet size among all supported periodic OUT channels. If there is at lease one High Bandwidth Isochronous OUT endpoint, then the space must be at least two times the maximum packet size of that channel.

14.4.7.1.2.1 Internal Register Storage Space Allocation

When operating in DMA mode, the DMA address register for each host channel (USB_HCx_DMAADDR) is stored in the FIFO RAM. One location for each channel must be reserved for this.

Table 14.4.

FIFO Name

Receive Data FIFO Non-periodic Transmit FIFO IN Endpoint Transmit FIFO

Data RAM Size

rx_fifo_size tx_fifo_size[0] tx_fifo_size[1] With this information, the following registers must be programmed: 1. Receive FIFO Size Register (USB_GRXFSIZ) • USB_GRXFSIZ.RXFDEP = rx_fifo_size; 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

234

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

2. Non-periodic Transmit FIFO Size Register (USB_GNPTXFSIZ) • USB_GNPTXFSIZ.NPTXFDEP = tx_fifo_size[0]; • USB_GNPTXFSIZ.NPTXFSTADDR = rx_fifo_size; 3. Host Periodic Transmit FIFO Size Register (USB_HPTXFSIZ) • USB_HPTXFSIZ.PTXFSIZE = tx_fifo_size[1]; • USB_HPTXFSIZ.PTXFSTADDR = USB_GNPTXFSIZ.NPTXFSTADDR + tx_fifo_size[0]; 4. The transmit FIFOs and receive FIFO must be flushed after RAM allocation for proper FIFO function.

• USB_GRSTCTL.TXFNUM = 0x10 • USB_GRSTCTL.TXFFLSH = 1 • USB_GRSTCTL.RXFFLSH = 1 • The application must wait until the TXFFLSH bit and the RXFFLSH bits are cleared before performing any operation on the core.

14.4.7.1.3 Summary of Guidelines for Choosing Data FIFO RAM Depth in Host Mode 14.4.7.1.3.1 RX FIFO size

The RX FIFO size must be equal to at least twice the largest value of MPS size used. The recommended minimum RXFIFO depth = ((largest packet size/4)*2)+2. (+2) is required by the core for the status quadlets internally.

14.4.7.1.3.2 Non periodic TX FIFO size

This should be equal to at least twice the largest value of MPS size used. The recommended minimum non-periodic TXFIFO depth = ((largest packet size/4)*2).

14.4.7.1.3.3 Periodic TX FIFO size

The recommended size for Periodic TXFIFO is sum total of (MPS*MC)/4 for all the channels.

Note

Note: In the above recommendations, always round off the MPS value to the nearest multiple of 4. For example, if the largest value of MPS=125, use the rounded-off value, which is 128.

14.4.7.1.4 Calculating the Total FIFO Size

The RxFIFO is shared between the host and device. The Host TxFIFOs are also shared with Device IN endpoint TxFIFOs 0 through n.

There are three ways to calculate the total FIFO size.

Method 1

Use this method if you are using the following conditions: • Minimum FIFO depth allocation • The FIFO must equal at least one MaxPacketSize (MPS).

Device RxFIFO = • (4 * number of control endpoints + 6) + ((largest USB packet used / 4) + 1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK

Note

Include the Control OUT endpoint in the number of OUT endpoints.

Host RxFIFO = 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

235

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• Slave mode Minimum requirement: (largest USB packet used / 4) + 1 for status information + 1 transfer complete • DMA mode (largest USB packet used / 4) + 1 for status information + 1 transfer complete + 1 location each bulk/ control out endpoint for handling NAK scenario Host Non-Periodic TxFIFO = • largest non-periodic USB packet used / 4 Host Periodic TxFIFO = • Sum total of (MPS*MC)/4 of all periodic channels or 1500 locations, whichever is lower.

Device IN Endpoint TxFIFOs (a separate FIFO is allocated to each IN endpoint) = • IN Endpoints Max packet Size / 4

Method 2

Use this method if you are using the recommended minimum FIFO depth allocation with support for high-bandwidth endpoints. This FIFO allocation enables the core to transfer a packet on the USB while the previous (next) packet is simultaneously transferred to the AHB. This FIFO allocation improves the core’s performance.

Device RxFIFO = • (4 * number of control endpoints + 6) + 2 * ((largest USB packet used / 4) + 1) +(2 * number of OUT endpoints) + 1 Host RxFIFO = • Slave mode 2 * ((largest USB packet used / 4) + 1 + 1) • DMA mode 2 * ((largest USB packet used / 4) + 1 + 1) + 1 location each bulk/control out endpoint for handling NAK scenario Host Non-Periodic TxFIFO = • 2 * (largest non-periodic USB packet used / 4) Host Periodic TxFIFO = • Sum total of (MPS*MC)/4 for all periodic channels or 1500 location, whichever is lower.

Device IN Endpoint-Specific TxFIFOs (a separate FIFO is allocated to each endpoint) = • 2 * (max_pkt_size for the endpoint) / 4.

//DMA mode OTG Total RAM = (Device RxFIFO or Host RxFIFO; choose the largest one) + 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

236

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

((Host Non-Periodic TxFIFO + Host peiodic TxFIFO) or (Device IN Endpoint TxFIFO #0 + #1 + #2 + #n)); choose the largest one + (1 location per Host channel or 1 location per Device Endpoint direction; choose the largest one) //Slave mode OTG Total RAM = (Device RxFIFO or Host RxFIFO; choose the largest one) + ((Host Non-Periodic TxFIFO + Host peiodic TxFIFO) or (Device IN Endpoint TxFIFO #0 + #1 + #2 + #n)); choose the largest one

Method 3

Use this method if you are using the recommended FIFO depth allocation that supports high-bandwidth endpoints and high AHB latency.

Note

• x = (AHB latency + time to transfer largest packet on AHB) / time to transfer largest packet on USB.

• The value of x is an integer. Any fractional value is rounded to the nearest integer. For example: x = 20 ms / 17,039 ms = 1.17 ms = 2 ms.

Device RxFIFO = • (4 * number of control endpoints + 6) + (x + 1) * ((largest USB packet used / 4) + 1)+ (2 * number of OUT endpoints) + 1

Note

Include the Control OUT endpoint in the number of OUT endpoints.

Host RxFIFO = • Slave mode (x + 1) * ((largest USB packet used / 4) + 1 + 1) • DMA mode (x + 1) * ((largest USB packet used / 4) + 1 + 1) + 1 location each bulk/control out endpoint for handling NAK scenario Host Non-Periodic TxFIFO = • (x + 1) * (largest non-periodic USB packet used / 4) Host Periodic TxFIFO = • (x+1) * (Sum total of (MPS*MC)/4 of all periodic channels or 1500 locations, whichever is lower).

Device IN Endpoint-Specific TxFIFOs (a separate FIFO is allocated to each endpoint) = • (x+1)*(max_pkt_size for the endpoint)/4 //DMA mode OTG Total RAM = (Device RxFIFO or Host RxFIFO; choose the largest one) + ((Host Non-Periodic TxFIFO + Host periodic TxFIFO) OR (Device IN Endpoint TxFIFO #0 + #1 + #2 + #n); choose the largest one) + (1 location per Host channel or 1 location per Device Endpoint direction; choose 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

237

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

the largest one) //Slave mode OTG Total RAM = (Device RxFIFO or Host RxFIFO; choose the largest one) + ((Host Non-Periodic TxFIFO + Host periodic TxFIFO) OR (Device IN Endpoint TxFIFO #0 + #1 + #2 + #n); choose the largest one)

14.4.7.2 Dynamic FIFO Allocation

The application can change the RAM allocation for each FIFO during the operation of the core.

14.4.7.2.1 Host Mode

In Host mode, before changing FIFO data RAM allocation, the application must determine the following.

All channels are disabled • All FIFOs are empty

Once these conditions are met, the application can reallocate FIFO data RAM as explained in Data FIFO RAM Allocation (p. 232) .

After reallocating the FIFO data RAM, the application must flush all FIFOs in the core using the USB_GRSTCTL.TXFFLSH (TxFIFO Flush) and USB_GRSTCTL.RXFFLSH (RxFIFO Flush) fields.

Flushing is required to reset the pointers in the FIFOs for proper FIFO operation after reallocation. For

more information on flushing FIFOs, see Flushing TxFIFOs in the Core (p. 238) and Flushing RxFIFOs in the Core (p. 239) .

14.4.7.2.2 Device Mode

In Device mode, before changing FIFO data RAM allocation, the application must determine the following.

• All IN and OUT endpoints are disabled • NAK mode is enabled in the core on all IN endpoints • Global OUT NAK mode is enabled in the core • All FIFOs are empty

Once these conditions are met, the application can reallocate FIFO data RAM as explained in Data FIFO RAM Allocation (p. 232) . When NAK mode is enabled in the core, the core responds with a NAK

handshake on all tokens received on the USB, except for SETUP packets.

After the reallocating the FIFO data RAM, the application must flush all FIFOs in the core using the USB_GRSTCTL.TXFFLSH (TxFIFO Flush) and USB_GRSTCTL.RXFFLSH (RxFIFO Flush) fields.

Flushing is required to reset the pointers in the FIFOs for proper FIFO operation after reallocation. For

more information on flushing FIFOs, see Flushing TxFIFOs in the Core (p. 238) and Flushing RxFIFOs in the Core (p. 239) .

14.4.7.2.3 Flushing TxFIFOs in the Core

The application can flush all TxFIFOs in the core using USB_GRSTCTL.TXFFLSH as follows: 1. Check that USB_GINTSTS.GINNAKEFF=0. If this bit is cleared then set USB_DCTL.SGNPINNAK=1.

2. Wait for USB_GINTSTS.GINNAKEFF=1, which indicates the NAK setting has taken effect to all IN endpoints.

3. Poll USB_GRSTCTL.AHBIDLE until it is 1.

AHBIdle = H indicates that the core is not writing anything to the FIFO.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

238

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

4. Check that USB_GRSTCTL.TXFFLSH =0. If it is 0, then write the TxFIFO number you want to flush to USB_GRSTCTL.TXFNUM.

5. Set USB_GRSTCTL.TXFFLSH=1and wait for it to clear.

6. Set the USB_DCTL.GCNPINNAK bit.

14.4.7.2.4 Flushing RxFIFOs in the Core

The application can flush all RxFIFOs in the core using USB_GRSTCTL.RXFFLSH as follows: 1. Check the status of the USB_GINTSTS.GOUTNAKEFF bit. If it has been cleared, then set USB_DCTL.SGOUTNAK=1. Else, clear USB_GINTSTS.GOUTNAKEFF.

NAK Effective interrupt = 1 indicates that the core is not writing to FIFO.

2. Wait for USB_GINTSTS.GOUTNAKEFF=1, which indicates the NAK setting has taken effect to all OUT endpoints.

3. Poll the USB_GRSTCTL.AHBIDLE until it is 1.

AHBIDLE = 1 indicates that the core is not reading anything from the FIFO.

4. Set USB_GRSTCTL.RXFFLSH=1 and wait for it to clear.

5. Set the USB_DCTL.GCOUTNAK bit.

The Core Interrupt Handler

Figure 14.33. Core Interrupt Handler

ot g_int r_ handler Wait for int errupt Clear int errupt Generat e host global soft ware int errupt Yes Read USB_HPRT Generat e port specific soft ware int errupt.

Yes Read USB_GINTSTS OTG int errupt?

Yes Read Generat e OTG soft ware int errupt No Host global int errupt?

No Host Port Int errupt?

No Read USB_HAINT No Host/ Device com m on int errupt?

No RTL in Device m ode?

Yes Device global int errupt?

No Read USB_DAINT Yes IN endpoint int errupt?

Yes Generat e gobal soft ware int errupt Generat e device global soft ware int errupt Yes Read USB_DIEPx _INT Generat e IN endpoint- specific Clear int errupt Read USB_HCx _INT Generat e channel specific soft ware int errupt.

No Read USB_DOEPx _INT Generat e OUT endpoint- specific 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

239

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.4.8 Suspend/Resume and SRP

This chapter describes different methods of saving power when the USB is suspended. This chapter discusses the following topics:

• Placing PHY in Low Power Mode Without Entering Suspend (p. 240) • When the Core is in Host Mode (p. 240)

• When the Core is in Device Mode (p. 241) • Suspend (p. 241) • Using EM2 (p. 241) • Overview of the EM2 Programming Model (p. 241) • Using EM2 when the Core is in Host Mode (p. 241)

• EM2 when the Core is in Device Mode (p. 244)

• Clock Gating (EM0 and EM1) (p. 246) • Internal Clock Gating when the Core is in Host Mode (p. 246)

• Internal Clock Gating when the Core is in Device Mode (p. 247)

14.4.8.1 Placing PHY in Low Power Mode Without Entering Suspend

The core can place the PHY in low power mode (the differential receiver is disabled) without entering suspend.

14.4.8.1.1 When the Core is in Host Mode Programming flow for the Host Core to put PHY in low power mode

1. To turn off port power, perform write operation to set the following bits in the USB_HPRT register: • USB_HPRT.PRTPWR = 0; • USB_HPRT.PRTENA = 0; 2. To put PHY in low power mode, perform read-modify-write operation to set the following bits in the USB_PCGCCTL register: • USB_PCGCCTL.STOPPCLK = 1 • USB_PCGCCTL.GATEHCLK = 0

Programming flow for the Host Core to make PHY exit low power mode

If your device is non-SRP capable, the host must implement polling to detect the device connection by turning on the port and exiting PHY low power mode periodically and checking for connect.

1. To turn on port power, perform write operation to set the following bits in the USB_HPRT register: • USB_HPRT.PRTPWR = 1 • USB_HPRT.PRTENA = 0 2. To exit PHY low power mode, perform read-modify-write operation to set the following bits in the USB_PCGCCTL register: • USB_PCGCCTL.STOPPCLK = 0 • USB_PCGCCTL.STOPHCLK = 0 3. Wait for the USB_HPRT Port Connect Detected (PRTCONNDET) bit to be set and do the enumeration of the device.

If your device is SRP-capable, when the device initiates SRP request, the Host core asynchronously detects SRP and the PHY exits low power mode.

1. Wait for Session Request from the device, or New Session Detected Interrupt (SESSREQINT) in the USB_GINTSTS register.

2. To turn on port power, perform write operation to set the following bits in the USB_HPRT register: 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

240

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• USB_HPRT.PRTPWR = 1 • USB_HPRT.PRTENA = 0 3. Wait for the USB_HPRT Port Connect Detected (PRTCONNDET) bit to be set and do the enumeration of Device.

14.4.8.1.2 When the Core is in Device Mode

To make PHY enter low power mode, complete the following steps: 1. Ensure that the following signals are set as follows: • VBUS voltage level must be below the session valid level (VBUS is not active) • DP/DM must be SE0 2. From the application, perform read-modify-write operation to set USB_PCGCCTL.STOPPCLK = 1.

14.4.8.2 Suspend

When the core is in Suspend, the following power conservation options are available to use:

• Using EM2 (p. 241) : You can enter EM2, turning off power (and reseting) parts of the core

• Clock Gating (EM0 and EM1) (p. 246) : You can choose gate the AHB clock to some parts of the core Internal Clock Gating when the Core is in Host Mode (p. 246)

This section discusses methods of conserving power by using one of the above methods.

14.4.8.2.1 Using EM2 14.4.8.2.1.1 Overview of the EM2 Programming Model

When the USB is suspended or the session is not valid, the PHY is driven into Suspend mode, stopping the PHY clock to reduce power consumption in the PHY and the core. To further reduce power consumption, the core also supports AHB clock gating and using EM2.

The following sections show the procedures you must follow to use EM2 while in suspend/session-off.

During EM2, the clock to the core must be switched to one of the 32 kHz sources (LFRCO or LFXO).

This core needs this clock to detect Resume and SRP events.

14.4.8.2.1.2 EM2 when the Core is in Host Mode Host Mode Suspend in EM2

Sequence of operations: 1. Back up the essential registers of the core. Read and store the following core registers: • USB_GINTMSK • USB_GOTGCTL • USB_GAHBCFG • USB_GUSBCFG • USB_GRXFSIZ • USB_GNPTXFSIZ • USB_DCFG • USB_DCTL • USB_DAINTMSK • USB_DIEPMSK • USB_DOEPMSK • USB_DIEPx_CTL • USB_DIEPx_TSIZ • USB_DIEPx_DMAADDR • USB_PCGCCTL • USB_DIEPTXFn 2. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

241

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

3. The application sets the Power Clamp bit in the Power and Clock Gating Control register.

4. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control register.

5. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register, the core suspends the PHY and the PHY clock stops. If USB_HCFG.ENA32KHZS is set, switch the USBC clock to 32 kHz.

6. Enter EM2.

Host Mode Resume in EM2

Sequence of operations: 1. The resume event starts by the application waking up from EM2 (on an interrupt) 2. Switch USBC clock back to 48 MHz.

3. The application clears the Stop PHY Clock bit and the core takes the PHY back to normal mode.

The PHY clock starts up.

4. The application clears the Power Clamp bit. The core starts driving Resume signaling on the USB.

5. The application clears the Reset to Power-Down Modules bit.

6. The application programs registers in the CSR and sets the Port Resume bit in Host Port CSR (Setting the Port Resume bit is required by the core, although Resume signaling starts earlier).

7. The application clears the Port Resume bit and the core stops driving Resume signaling.

The core is in normal operating mode.

Note

The application must insert delays of at least 2 PHY clocks between all steps in this sequence. This requirement applies to all USB EM2 programming sequences.

Host Mode Remote Wakeup in EM2

Sequence of operations: 1. The core detects Remote Wakeup signaling on the USB. The PHY exits suspend mode and the PHY clock restarts.

2. The core generates a Remote Wakeup Detected interrupt. The Remote Wakeup interrupt is generated using the 32 kHz clock depending on the USB_HCFG.RESVALID (ResumeValidPeriod) programmed.

The Host Core starts resume signaling at this stage.

3. The USBC clock is switched back to normal 48 MHz clock.

4. The application clears the Stop PHY Clock bit.

5. The application clears the Power Clamp bit.

6. The application clears the Reset to Power-Down Modules bit 7. The application programs CSRs and sets the Port Resume bit. The core continues to drive Resume signaling on the USB.

8. The application clears the Port Resume bit and the core stops driving Resume signaling.

The core enters normal operating mode.

Host Mode Session End in EM2

Sequence of operations: 1. Back up the essential registers of the core. Read and store the following core registers: • USB_GINTMSK • USB_GOTGCTL • USB_DCTL • USB_DAINTMSK 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

242

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• USB_GAHBCFG • USB_GUSBCFG • USB_GRXFSIZ • USB_GNPTXFSIZ • USB_DCFG • USB_DIEPMSK • USB_DOEPMSK • USB_DIEPx_CTL • USB_DIEPx_TSIZ • USB_DIEPx_DMAADDR • USB_PCGCCTL • USB_DIEPTXFn 2. The application sets the Port Suspend bit in the Host Port CSR and the core drives a USB suspend.

3. The application clears the Port Power bit.

4. The application sets the Power Clamp bit in the Power and Clock Gating Control register, and the core clamps the signals between the internal modules on different power rails.

5. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control register.

6. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register, and the core suspends the PHY, stopping the PHY clock.

7. Switch USBC clock to 32 kHz.

8. Enter EM2.

Host Mode Session Start (EM2 -> EM0)

Sequence of operations: 1. Exit EM2/Enter EM0).

2. Switch USBC clock back to 48 MHz.

3. The application clears the Stop PHY Clock bit.

4. The application clears the Power Clamp bit. The application clears the Reset to Power-Down Modules bit.

5. The application programs CSRs and sets the Port Power bit to turn on VBUS.

6. The core detects the connection and drives the USB reset.

The core enters normal operating mode.

Host Mode Session End (EM0 -> EM2)

Sequence of operations: 1. Back up the essential registers of the core. Read and store the following core registers: • USB_GINTMSK • USB_GOTGCTL • USB_GAHBCFG • USB_GUSBCFG • USB_GRXFSIZ • USB_GNPTXFSIZ • USB_DCFG • USB_DCTL • USB_DAINTMSK • USB_DIEPMSK • USB_DOEPMSK • USB_DIEPx_CTL • USB_DIEPx_TSIZ • USB_DIEPx_DMAADDR • USB_PCGCCTL • USB_DIEPTXFn 2. The application sets the Port Suspend bit in the Host Port CSR and the core drives a USB suspend.

3. The application clears the Port Power bit.

4. The application sets the Power Clamp bit in the Power and Clock Gating Control register, and the core clamps the signals between the internal modules on different power rails.

5. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control register.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

243

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

6. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register.

7. Enter EM2.

Host Mode Sessions Start (SRP) (EM2 -> EM0)

Sequence of operations: 1. The core detects SRP (data line pulsing) on the bus. The core de-asserts the suspend_n signal to the PHY, generating the PHY clock. The SRP Detected interrupt is generated.

2. The application clears the Stop PHY Clock bit, the core deasserts the suspend_n signal to the PHY to generate the PHY clock.

3. The power (VDD_DN) is turned on and stabilizes.

4. The application clears the Power Clamp bit.

5. The application clears the Reset to Power-Down Modules bit.

6. The application programs the CSRs, and sets the Port Power bit to turn on VBUS.

7. The core detects device connection and drives a USB reset.

The core enters normal operating mode.

14.4.8.2.1.3 EM2 when the Core is in Device Mode Device Mode Suspend With EM2

In Device mode, the device validates the host-driven Resume signal for a period of 1.5 µs (75 clock cycles at 48 MHz). With a 32-KHz clock, 2.34 ms is required (75 clock cycles at 32 KHz) to detect the resume. Hence, the application programs USB_DCFG.RESVALID with a value of 4 clock cycles (125 µs). If the core is in Suspend mode, the device thus detects the resume and the host signals a resume for a minimum of 125 µs.

If the device is being reset from suspend, it begins a high-speed detection handshake after detecting SE0 for no fewer than 2.5 µs. With a 48-MHz clock, detection occurs after 120 clock cycles (2.5 µs).

With a 32-kHz clock, 120 clock cycles signifies 3.75 msec. Hence, a programmable value of 4 clock cycles (125 µs) is used to detect reset.

The 32-KHz Suspend feature incorporates switching to the 32-KHz clock during suspend and resume/ remote wakeup until the system comes up and starts driving 48 MHz.

Sequence of operations: 1. Detect Suspend state. Wait for an interrupt from the device core and check that USB_GINTSTS.USBSUSP is set to 1.

2. Back up the essential registers of the core. Read and store the following core registers: • USB_GINTMSK • USB_GOTGCTL • USB_GAHBCFG • USB_GUSBCFG • USB_GRXFSIZ • USB_GNPTXFSIZ • USB_DCFG • USB_DCTL • USB_DAINTMSK • USB_DIEPMSK • USB_DOEPMSK • USB_DIEPx_CTL • USB_DIEPx_TSIZ • USB_DIEPx_DMAADDR • USB_PCGCCTL • USB_DIEPTXFn 3. The application sets the PWRCLMP bit in the Power and Clock Gating Control (USB_PCGCCTL) register.

4. The application sets the USB_PCGCCTL.RSTPDWNMODULE bit.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

244

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

5. The application sets the USB_PCGCCTL.STOPPCLK bit.

6. Switch USB Core Clock (USBC) to 32 kHz.

7. Enter EM2.

Device Mode Resume (EM2 -> EM0)

Sequence if operations: 1. The core detects Resume signaling on the USB. The core generates a Resume Detected interrupt.

2. Switch USB Core Clock (USBC) back to 48 MHz.

3. The application clears the STOPPCLK bit.

4. The application clears the USB_PCGCCTL.PWRCLMP and USB_PCGCCTL.RSTPDWNMODULE

bits.

5. Restore the USB_GUSBCFG and USB_DCFG registers with the values stored during the Save operation before entering EM2.

6. Restore the following core registers with the values stored during the Save operation before entering EM2: • USB_GINTMSK • USB_GOTGCTL • USB_GUSBCFG • USB_GRXFSIZ • USB_GNPTXFSIZ • USB_DAINTMSK • USB_DIEPMSK • USB_DOEPMSK • USB_DIEPx_CTL • USB_DIEPx_TSIZ • USB_DIEPx_DMAADDR • USB_DIEPTXFn 7. The application programs CSRs, then sets the Power-On Programming Done bit in the Device Control register.

Device Mode Remote Wakeup (EM2 -> EM0)

Sequence if operations: 1. An interrupt wakes up the device from EM2.

2. Switch USB Core Clock (USBC) back to 48 MHz.

3. The application clears the STOPPCLK and GATEHCLK bits in the USB_PCGCCTL register.

4. The application clears the USB_PCGCCTL.PWRCLMP and USB_PCGCCTL.RSTPDWNMODULE

bits.

5. Restore the USB_GUSBCFG and USB_DCFG registers with the values stored during the Save operation before entering EM2 .

6. Drive remote wakeup from the core. Program USB_DCTL by performing write-only operation with the following values: • USB_DCTL.RMTWKUPSIG = 1 • Other Bits = Value stored during the Save operation before entering EM2 7. Clear all interrupt status. Wait for at least 1 millisecond of remote wakeup time and then program GINSTS register with 0xFFFFFFFF to clear all the status register fields.

8. Restore the following core registers with the values stored during the Save operation before entering EM2: • USB_GINTMSK • USB_GOTGCTL • USB_GUSBCFG • USB_GRXFSIZ • USB_GNPTXFSIZ • USB_DAINTMSK 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

245 • USB_DIEPMSK • USB_DOEPMSK • USB_DIEPx_CTL • USB_DIEPx_TSIZ • USB_DIEPx_DMAADDR • USB_DIEPTXFn

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

9. Wait for remote wakeup time (1-15ms) and then program USB_DCTL by performing read-modify write to set USB_DCTL.RMTWKUPSIG = 0.

Device Mode Session End (EM0 -> EM2)

Sequence of operations: 1. The core detects a USB suspend and generates a Suspend Detected interrupt. The host turns off VBUS.

2. The application sets the Power Clamp bit in the Power and Clock Gating Control register.

3. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control register.

4. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register.

5. Switch USB Core clock (USBC) to 32 kHz.

6. Enter EM2.

Device Mode Session Start (EM2 -> EM0)

Sequence of operations: 1. The core detects VBUS on (voltage level within session-valid). A New Session Detected interrupt is generated.

2. Switch USB Core clock (USBC) back to 48 MHz.

3. The application clears the Stop PHY Clock bit.

4. The application clears the Power Clamp bit.

5. The application clears the Reset to Power-Down Modules bit.

6. The application programs CSRs.

7. The cores detects a USB reset.

The core enters normal operating mode.

14.4.8.2.2 Using Clock Gating in EM0/EM1

The core supports HCLK gating to reduce dynamic power to internal modules to the core during Suspend/ session-off state in EM0 and EM1.

14.4.8.2.2.1 Internal Clock Gating when the Core is in Host Mode

The following sections show the procedures you must follow to use the clock gating feature.

Host Mode Suspend and Resume With Clock Gating

Sequence of operations: 1. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend.

2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, the core gates the hclk internally.

3. The core remains in Suspend mode.

4. The application clears the Gate hclk and Stop PHY Clock bits, and the PHY clock is generated.

5. The application sets the Port Resume bit, and the core starts driving Resume signaling.

6. The application clears the Port Resume bit after at least 20 ms.

7. The core is in normal operating mode.

Host Mode Suspend and Remote Wakeup With Clock Gating

Sequence of operations: 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

246

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

1. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend.

2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, and the core gates hclk internally.

3. The core remains in Suspend mode 4. The Remote Wakeup signaling from the device is detected. The core generates a Remote Wakeup Detected interrupt.

5. The application clears the Gate hclk and Stop PHY Clock bits. The core sets the Port Resume bit.

6. The application clears the Port Resume bit after at least 20 ms.

7. The core is in normal operating mode.

Host Mode Session End and Start With Clock Gating

Sequence of operations: 1. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend.

2. The application clears the Port Power bit. The core turns off VBUS.

3. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, and the core gates hclk internally.

4. The core remains in Low-Power mode.

5. The application clears the Gate hclk bit and the application clears the Stop PHY Clock bit to start the PHY clock.

6. The application sets the Port Power bit to turn on VBUS.

7. The core detects device connection and drives a USB reset.

8. The core is in normal operating mode.

Host Mode Session End and SRP With Clock Gating

Sequence of operations: 1. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend.

2. The application clears the Port Power bit. The core turns off VBUS.

3. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, and the core gates hclk internally.

4. The core remains in Low-Power mode.

5. SRP (data line pulsing) from the device is detected. An SRP Request Detected interrupt is generated.

6. The application clears the Gate hclk bit and the Stop PHY Clock bit.

7. The core sets the Port Power bit to turn on VBUS.

8. The core detects device connection and drives a USB reset.

9. The core is in normal operating mode.

14.4.8.2.2.2 Internal Clock Gating when the Core is in Device Mode

The following sections show the procedures you must follow to use the clock gating feature.

Device Mode Suspend and Resume With Clock Gating

Sequence of operations: 1. The core detects a USB suspend and generates a Suspend Detected interrupt.

2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, and the core gates hclk.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

247

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

3. The core remains in Suspend mode.

4. The Resume signaling from the host is detected. A Resume Detected interrupt is generated.

5. The application clears the Gate hclk bit and the Stop PHY Clock bit.

6. The host finishes Resume signaling.

7. The core is in normal operating mode.

Device Mode Suspend and Remote Wakeup With Clock Gating

Sequence of operations: 1. The core detects a USB suspend and generates a Suspend Detected interrupt.

2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, the core gates hclk.

3. The core remains in Suspend mode.

4. The application clears the Gate hclk bit and the Stop PHY Clock bit.

5. The application sets the Remote Wakeup bit in the Device Control register, the core starts driving Remote Wakeup signaling.

6. The host drives Resume signaling.

7. The core is in normal operating mode.

Device Mode Session End and Start With Clock Gating

Sequence of operations: 1. The core detects a USB suspend, and generates a Suspend Detected interrupt. The host turns off VBUS.

2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, and the core gates hclk.

3. The core remains in Low-Power mode.

4. The new session is detected (A session-valid voltage is detected). A New Session Detected interrupt is generated.

5. The application clears the Gate hclk and Stop PHY Clock bits.

6. The core detects USB reset.

7. The core is in normal operating mode

Device Mode Session End and SRP With Clock Gating

Sequence of operations: 1. The core detects a USB suspend, and generates a Suspend Detected interrupt. The host turns off VBUS.

2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, and the core gates hclk.

3. The core remains in Low-Power mode.

4. The application clears the Gate hclk and Stop PHY Clock bits.

5. The application sets the SRP Request bit, and the core drives data line and VBUS pulsing.

6. The host turns on VBUS, detects device connection, and drives a USB reset.

7. The core is in normal operating mode.

14.4.9 Register Usage

Only the Core Global, Power and Clock Gating, Data FIFO Access, and Host Port registers can be accessed in both Host and Device modes. When the core is operating in one mode, either Device or 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

248

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Host, the application must not access registers from the other mode. If an illegal access occurs, a Mode Mismatch interrupt is generated and reflected in the Core Interrupt register (USB_GINTSTS.MODEMIS).

When the core switches from one mode to another, the registers in the new mode must be reprogrammed as they would be after a power-on reset.

The memory map for the core is as follows: • Core Global Registers are located in the address offset-range [0x3C000, 0x3C3FF] and typically start with first letter G.

• Host Mode Registers are located in the address offset-range [0x3C400, 0x3C7FF] and start with first letter H.

• Device Mode Registers are located in the address offset-range [0x3C800, 0x3CDFF] and start with first letter D.

• The Power and Clock Gating register is located at offset 0x3CE00.

• The Device EP/Host Channel FIFOs start at address offset 0x3D000 with 4K spacing. These registers, available in both Host and Device modes, are used to read or write the FIFO space for a specific endpoint or a channel, in a given direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the channel.

• The Direct RAM Access area start at address offset 0x5C000.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

249

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.5 Register Map Name

USB_CTRL

USB_STATUS USB_IF

USB_IFS USB_IFC USB_IEN

USB_ROUTE USB_GAHBCFG

USB_GUSBCFG

USB_GRSTCTL

USB_GINTSTS

USB_GINTMSK

USB_GRXSTSR

USB_GRXSTSP

USB_GRXFSIZ USB_GNPTXFSIZ

USB_GDFIFOCFG USB_DIEPTXF1

USB_DIEPTXF2 USB_DIEPTXF3

USB_DCFG

USB_DCTL

USB_DSTS

USB_DIEPMSK

USB_DOEPMSK USB_DAINT

USB_DAINTMSK

USB_DIEPEMPMSK USB_DIEP0CTL

USB_DIEP0INT

USB_DIEP0TSIZ USB_DIEP0DMAADDR

USB_DIEP0TXFSTS USB_DIEP0_CTL

USB_DIEP0_INT

USB_DIEP0_TSIZ USB_DIEP0_DMAADDR

USB_DIEP0_TXFSTS

USB_DIEP1_CTL

USB_DIEP1_INT

The offset register address is relative to the registers base address.

Offset

0x3C818

0x3C81C

0x3C834 0x3C900

0x3C908

0x3C910 0x3C914

0x3C918 0x3C920

0x3C928

0x3C930 0x3C934

0x3C938

0x3C940

0x3C948

0x000

0x004 0x008

0x00C 0x010 0x014

0x018 0x3C008

0x3C00C

0x3C010

0x3C014

0x3C018

0x3C01C

0x3C020

0x3C024 0x3C028

0x3C05C 0x3C104

0x3C108 0x3C10C

0x3C800

0x3C804

0x3C808

0x3C810

0x3C814

Type

R RW RW RWH RWH RW RW R RWH RWH RW RW R RWH RWH RW R R W1 W1 RW RW RW RWH RWH RWH RW R R RW RW RW RW RW RW RW RWH R RW RW

Description

System Control Register

System Status Register Interrupt Flag Register

Interrupt Flag Set Register Interrupt Flag Clear Register Interrupt Enable Register

I/O Routing Register AHB Configuration Register

USB Configuration Register

Reset Register

Interrupt Register

Interrupt Mask Register

Receive Status Debug Read Register

Receive Status Read and Pop Register

Receive FIFO Size Register Non-periodic Transmit FIFO Size Register

Global DFIFO Configuration Register Device IN Endpoint Transmit FIFO 1 Size Register

Device IN Endpoint Transmit FIFO 2 Size Register Device IN Endpoint Transmit FIFO 3 Size Register

Device Configuration Register

Device Control Register

Device Status Register

Device IN Endpoint Common Interrupt Mask Register

Device OUT Endpoint Common Interrupt Mask Register Device All Endpoints Interrupt Register

Device All Endpoints Interrupt Mask Register

Device IN Endpoint FIFO Empty Interrupt Mask Register Device IN Endpoint 0 Control Register

Device IN Endpoint 0 Interrupt Register

Device IN Endpoint 0 Transfer Size Register Device IN Endpoint 0 DMA Address Register

Device IN Endpoint 0 Transmit FIFO Status Register Device IN Endpoint x+1 Control Register

Device IN Endpoint x+1 Interrupt Register

Device IN Endpoint x+1 Transfer Size Register Device IN Endpoint x+1 DMA Address Register

Device IN Endpoint x+1 Transmit FIFO Status Register

Device IN Endpoint x+1 Control Register

Device IN Endpoint x+1 Interrupt Register

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

250

www.silabs.com

Offset

0x3CB74 0x3CE00

0x3D000

...

0x3D5FC

0x3E000

...

0x3E5FC 0x3F000

...

0x3F5FC 0x40000

...

0x405FC

0x5C000

...

0x5C7FC

0x3C950 0x3C954

0x3C958

0x3C960

0x3C968

0x3C970 0x3C974

0x3C978 0x3CB00

0x3CB08

0x3CB10

0x3CB14 0x3CB20

0x3CB28

0x3CB30

0x3CB34

0x3CB40

0x3CB48

0x3CB50

0x3CB54

0x3CB60

0x3CB68

0x3CB70

Name

USB_DIEP1_TSIZ USB_DIEP1_DMAADDR

USB_DIEP1_TXFSTS

USB_DIEP2_CTL

USB_DIEP2_INT

USB_DIEP2_TSIZ USB_DIEP2_DMAADDR

USB_DIEP2_TXFSTS USB_DOEP0CTL

USB_DOEP0INT

USB_DOEP0TSIZ

USB_DOEP0DMAADDR USB_DOEP0_CTL

USB_DOEP0_INT

USB_DOEP0_TSIZ

USB_DOEP0_DMAADDR

USB_DOEP1_CTL

USB_DOEP1_INT

USB_DOEP1_TSIZ

USB_DOEP1_DMAADDR

USB_DOEP2_CTL

USB_DOEP2_INT

USB_DOEP2_TSIZ

USB_DOEP2_DMAADDR USB_PCGCCTL

USB_FIFO0D0 USB_FIFO0Dx USB_FIFO0D383

USB_FIFO1D0 USB_FIFO1Dx USB_FIFO1D383 USB_FIFO2D0 USB_FIFO2Dx USB_FIFO2D383 USB_FIFO3D0 USB_FIFO3Dx USB_FIFO3D383

USB_FIFORAM0 USB_FIFORAMx USB_FIFORAM511

Preliminary

...the world's most energy friendly microcontrollers

Type

RW RWH RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R RWH RWH RW RW R RWH RWH RW RW RWH RWH RWH RW RWH RWH RWH RW RWH RWH RWH

Description

Device IN Endpoint x+1 Transfer Size Register Device IN Endpoint x+1 DMA Address Register

Device IN Endpoint x+1 Transmit FIFO Status Register

Device IN Endpoint x+1 Control Register

Device IN Endpoint x+1 Interrupt Register

Device IN Endpoint x+1 Transfer Size Register Device IN Endpoint x+1 DMA Address Register

Device IN Endpoint x+1 Transmit FIFO Status Register Device OUT Endpoint 0 Control Register

Device OUT Endpoint 0 Interrupt Register

Device OUT Endpoint 0 Transfer Size Register

Device OUT Endpoint 0 DMA Address Register Device OUT Endpoint x+1 Control Register

Device OUT Endpoint x+1 Interrupt Register

Device OUT Endpoint x+1 Transfer Size Register

Device OUT Endpoint x+1 DMA Address Register

Device OUT Endpoint x+1 Control Register

Device OUT Endpoint x+1 Interrupt Register

Device OUT Endpoint x+1 Transfer Size Register

Device OUT Endpoint x+1 DMA Address Register

Device OUT Endpoint x+1 Control Register

Device OUT Endpoint x+1 Interrupt Register

Device OUT Endpoint x+1 Transfer Size Register

Device OUT Endpoint x+1 DMA Address Register Power and Clock Gating Control Register

Device EP 0 FIFO Device EP 0 FIFO Device EP 0 FIFO

Device EP 1 FIFO Device EP 1 FIFO Device EP 1 FIFO Device EP 2 FIFO Device EP 2 FIFO Device EP 2 FIFO Device EP 3 FIFO Device EP 3 FIFO Device EP 3 FIFO

Direct Access to Data FIFO RAM for Debugging (2 KB) Direct Access to Data FIFO RAM for Debugging (2 KB) Direct Access to Data FIFO RAM for Debugging (2 KB)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

251

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.6 Register Description 14.6.1 USB_CTRL - System Control Register Offset

0x000

Reset Access Bit Position Name

8

7

Bit

31:26

25:24

23:22

21:20

19:18

17 16

15:10

9

6

5:4

3:2

1

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BIASPROGEM23 0x0 RW

Regulator Bias Programming Value in EM2/3

Regulator bias current setting in EM2/3 (i.e. while USB in suspend).

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BIASPROGEM01 0x0 RW Regulator bias current setting in EM0/1 (i.e. while USB active).

Regulator Bias Programming Value in EM0/1

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

VREGOSEN 0 RW Set this bit to enable USB_VREGO voltage level sensing.

VREGDIS 0 Set this bit to disable the voltage regulator.

RW

Reserved

VREGO Sense Enable Voltage Regulator Disable

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LEMIDLEEN 0 RW Set this bit to enter low energy mode during bus idle.

Reserved

Low Energy Mode on Bus Idle Enable

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LEMPHYCTRL 0 RW

Low Energy Mode USB PHY Control

Configuration for USB PHY control when Low Energy Mode is active Value 0 1 Value 0 1 2 Mode NONE LEM Description The USB PHY is not affected by Low Energy Mode.

The USB PHY is put into an energy saving state when Low Energy Mode is active.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LEMOSCCTRL 0x2 RW

Low Energy Mode Oscillator Control

Configuration for oscillator control when Low Energy Mode is active Mode NONE GATE SUSPEND Description Low Energy Mode has no effect on neither USBC or USHFRCO.

The USBC clock is gated when Low Energy Mode is active.

The USBC clock is gated, and USHFRCO is suspended (if not selected as HFCLK) when Low Energy Mode is active.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DMPUAP 0 RW Use this bit to select the active polarity of the USB_DMPU pin.

DMPU Active Polarity

Value 0 Mode LOW Description USB_DMPU is active low.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

252

www.silabs.com

Bit

0

Name

Value 1

Reserved

Mode HIGH

Preliminary

...the world's most energy friendly microcontrollers

Reset Access Description

Description USB_DMPU is active high.

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

14.6.2 USB_STATUS - System Status Register Bit Position Offset

0x004

Reset Access Name

1

0

Bit

31:3

2

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LEMACTIVE 0 This bit is set when Low Energy Mode is active.

R

Reserved

Low Energy Mode Active

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

VREGOS 0 R

VREGO Sense Output

USB_VREGO Voltage Sense output. 0 when no USB_VREGO voltage, 1 when USB_VREGO above approximately 1.8 V. Always 0 when VREGOSEN in USB_CTRL is 0.

14.6.3 USB_IF - Interrupt Flag Register Bit Position Offset

0x008

Reset Access Name Bit

31:2

1 0

Name Reset Access Description

Reserved

VREGOSL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

1 R Set when USB_VREGO drops below approximately 1.8 V.

VREGOSH 1 R Set when USB_VREGO goes above approximately 1.8 V.

VREGO Sense Low Interrupt Flag VREGO Sense High Interrupt Flag

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

253

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.6.4 USB_IFS - Interrupt Flag Set Register Offset

0x00C

Reset Access Bit Position Name Bit

31:2

1 0

Name Reset Access Description

Reserved

VREGOSL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 W1 Write to 1 to set the VREGO Sense Low Interrupt Flag.

VREGOSH 0 W1 Write to 1 to set the VREGO Sense High Interrupt Flag.

Set VREGO Sense Low Interrupt Flag Set VREGO Sense High Interrupt Flag 14.6.5 USB_IFC - Interrupt Flag Clear Register Bit Position Offset

0x010

Reset Access Name Bit

31:2

1 0

Name Reset Access Description

Reserved

VREGOSL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 W1 Write to 1 to clear the VREGO Sense Low Interrupt Flag.

VREGOSH 0 W1 Write to 1 to clear the VREGO Sense High Interrupt Flag.

Clear VREGO Sense Low Interrupt Flag Clear VREGO Sense High Interrupt Flag 14.6.6 USB_IEN - Interrupt Enable Register Bit Position Offset

0x014

Reset Access Name

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

254

www.silabs.com

Bit

31:2

1 0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Reserved

VREGOSL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Enable interrupt on VREGO Sense Low.

VREGOSH 0 Enable interrupt on VREGO Sense High.

RW RW

VREGO Sense Low Interrupt Enable VREGO Sense High Interrupt Enable 14.6.7 USB_ROUTE - I/O Routing Register Bit Position Offset

0x018

Reset Access Name

1

0

Bit

31:3

2

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DMPUPEN 0 When set, the USB_DMPU pin is enabled.

Reserved

RW

DMPU Pin Enable

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PHYPEN 0 RW

USB PHY Pin Enable

When set, the USB PHY and USB pins are enabled. The USB_DP and USB_DM are changed from regular GPIO pins to USB pins.

14.6.8 USB_GAHBCFG - AHB Configuration Register

This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.

Offset

0x3C008

Reset Access Bit Position Name Bit

31:24

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

255

www.silabs.com

6

5 4:1

Bit

23 22 21

20:8

7 0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

AHBSINGLE 0 RW

AHB Single Support

This bit is set to enable SINGLE burst transfers for the remaining data in a transfer when the USB core is operating in FMA mode.

When cleared, the remaining data is set using INCR burst size transfers. When set the remaining data is sent using a SINGLE burst size transfer.

NOTIALLDMAWRIT 0 RW

Notify All DMA Writes

This bit is programmed to enable the System DMA Done functionality for all the DMA write Transactions corresponding to the Channel/ Endpoint. This bit is valid only when USB_GAHBCFG.REMMEMSUPP is set to 1. When set, the core asserts int_dma_req for all the DMA write transactions on the AHB interface along with int_dma_done, chep_last_transact and chep_number signal informations.

The core waits for sys_dma_done signal for all the DMA write transactions in order to complete the transfer of a particular Channel/ Endpoint. When cleared, the core asserts int_dma_req signal only for the last transaction of DMA write transfer corresponding to a particular Channel/Endpoint. Similarly, the core waits for sys_dma_done signal only for that transaction of DMA write to complete the transfer of a particular Channel/Endpoint.

REMMEMSUPP 0 RW

Remote Memory Support

This bit is programmed to enable the functionality to wait for the system DMA Done Signal for the DMA Write Transfers. When set, the int_dma_req output signal is asserted when HSOTG DMA starts write transfer to the external memory. When the core is done with the Transfers it asserts int_dma_done signal to flag the completion of DMA writes from HSOTG. The core then waits for sys_dma_done signal from the system to proceed further and complete the Data Transfer corresponding to a particular Channel/Endpoint. When cleared, the int_dma_req and int_dma_done signals are not asserted and the core proceeds with the assertion of the XferComp interrupt as soon as the DMA write transfer is done at the HSOTG Core Boundary and it doesn't wait for the sys_dma_done signal to complete the DATA.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NPTXFEMPLVL 0 RW

Non-Periodic TxFIFO Empty Level

This bit is used only in Slave mode. In host mode this bit indicates when the Non-Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (USB_GINTSTS.NPTXFEMP) is triggered. In device mode, this bit indicates when IN endpoint Transmit FIFO empty interrupt (USB_DIEP0INT/USB_DIEPx_INT.TXFEMP) is triggered.

Value 0 1 Mode HALFEMPTY EMPTY Description Host Mode: USB_GINTSTS.NPTXFEMP interrupt indicates that the Non-Periodic TxFIFO is half empty.

Device Mode: USB_DIEP0INT/USB_DIEPx_INT.TXFEMP interrupt indicates that the IN Endpoint TxFIFO is half empty.

Host Mode: USB_GINTSTS.NPTXFEMP interrupt indicates that the Non-Periodic TxFIFO is completely empty.

Device Mode: USB_DIEP0INT/USB_DIEPx_INT.TXFEMP interrupt indicates that the IN Endpoint TxFIFO is completely empty.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DMAEN 0 RW

DMA Enable

When set to 0 the core operates in Slave mode. When set to 1 the core operates in a DMA mode.

HBSTLEN 0x0 This field is used in DMA mode.

RW

Burst Length/Type

Value 0 1 3 5 7 Mode SINGLE INCR INCR4 INCR8 INCR16 Description Single transfer.

Incrementing burst of unspecified length.

4-beat incrementing burst.

8-beat incrementing burst.

16-beat incrementing burst.

GLBLINTRMSK 0 RW

Global Interrupt Mask

The application uses this bit to mask or unmask the interrupt line assertion to itself. Irrespective of this bit's setting, the interrupt status registers are updated by the core. Set to unmask.

14.6.9 USB_GUSBCFG - USB Configuration Register

This register can be used to configure the core after power-on or a changing to Host mode or Device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

256

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Bit Position Offset

0x3C00C

Reset Access Name Bit

31

30:29

28

27:23

22

21:14

13:10

9:6

5

4:3

2:0

Name Reset Access Description

CORRUPTTXPKT 0 W1

Corrupt Tx packet

This bit is for debug purposes only. Never Set this bit to 1. The application should always write 0 to this bit.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXENDDELAY 0 RW

Tx End Delay

Writing 1 to this bit enables the core to follow the TxEndDelay timings as per UTMI+ specification 1.05 section 4.1.5 for opmode signal during remote wakeup.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TERMSELDLPULSE 0 RW

TermSel DLine Pulsing Selection

This bit selects utmi_termselect to drive data line pulse during SRP.

Value 0 1 Mode TXVALID TERMSEL Description Data line pulsing using utmi_txvalid.

Data line pulsing using utmi_termsel.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USBTRDTIM 0x5 RW

USB Turnaround Time

Sets the turnaround time in PHY clocks. Specifies the response time For a MAC request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). Always write this field to 5.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 RW

Full-Speed Serial Interface Select

FSINTF Always write this bit to 0.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TOUTCAL Always write this field to 0.

0x0 RW

Timeout Calibration 14.6.10 USB_GRSTCTL - Reset Register

The application uses this register to reset various hardware features inside the core.

Offset Bit Position

0x3C010

Reset Access Name

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

257

www.silabs.com

Bit

31 30

29:11

10:6 5 4

3:2

1 0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

AHBIDLE 1 R

AHB Master Idle

Indicates that the AHB Master State Machine is in the IDLE condition.

DMAREQ 0 R Indicates that the DMA request is in progress. Used for debug.

DMA Request Signal

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXFNUM 0x00 RW

TxFIFO Number

This is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not be changed until the core clears the TxFIFO Flush bit.

Value 0 1 2 3 4 5 6 16 Mode F0 F1 F2 F3 F4 F5 F6 FALL Description Host mode: Non-periodic TxFIFO flush.

Device: Tx FIFO 0 flush Host mode: Periodic TxFIFO flush.

Device: TXFIFO 1 flush.

Device mode: TXFIFO 2 flush.

Device mode: TXFIFO 3 flush.

Device mode: TXFIFO 4 flush.

Device mode: TXFIFO 5 flush.

Device mode: TXFIFO 6 flush.

Flush all the transmit FIFOs in device or host mode.

TXFFLSH 0 RW1H

TxFIFO Flush

This bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the midst of a transaction. The application must write this bit only after checking that the core is neither writing to the TxFIFO nor reading from the TxFIFO. NAK Effective Interrupt ensures the core is not reading from the FIFO. USB_GRSTCTL.AHBIDLE ensures the core is not writing anything to the FIFO. Flushing is normally recommended when FIFOs are reconfigured. FIFO flushing is also recommended during device endpoint disable. The application must wait until the core clears this bit before performing any operations. This bit takes eight clocks to clear.

RXFFLSH 0 RW1H

RxFIFO Flush

The application can flush the entire RxFIFO using this bit, but must first ensure that the core is not in the middle of a transaction. The application must only write to this bit after checking that the core is neither reading from the RxFIFO nor writing to the RxFIFO. The application must wait until the bit is cleared before performing any other operations. This bit requires 8 clocks to clear.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PIUFSSFTRST 0 RW1H

PIU FS Dedicated Controller Soft Reset

Resets the PIU FS Dedicated Controller All module state machines in FS Dedicated Controller of PIU are reset to the IDLE state.

Used to reset the FS Dedicated controller in PIU in case of any PHY Errors like Loss of activity or Babble Error resulting in the PHY remaining in RX state for more than one frame boundary CSFTRST 0 RW1H

Core Soft Reset

Resets the core by clearing the interrupts and all the CSR registers except the following register bits: USB_PCGCCTL.RSTPDWNMODULE, USB_PCGCCTL.GATEHCLK, USB_PCGCCTL.PWRCLMP, USB_GUSBCFG.FSINTF, USB_HCFG.FSLSPCLKSEL, USB_DCFG.DEVSPD.

All module state machines (except the AHB Slave Unit) are reset to the IDLE state, and all the transmit FIFOs and the receive FIFO are flushed. Any transactions on the AHB Master are terminated as soon as possible, after gracefully completing the last data phase of an AHB transfer. Any transactions on the USB are terminated immediately. The application can write to this bit any time it wants to reset the core. This is a self-clearing bit and the core clears this bit after all the necessary logic is reset in the core, which can take several clocks, depending on the current state of the core. Once this bit is cleared software must wait at least 3 clock cycles before doing any access to the core. Software must also must check that bit 31 of this register is 1 (AHB Master is IDLE) before starting any operation.

14.6.11 USB_GINTSTS - Interrupt Register

This register interrupts the application for system-level events in the current mode (Device mode or Host mode). Some of the bits in this register are valid only in Host mode, while others are valid in Device mode only. This register also indicates the current mode. To clear the interrupt status bits of type RW1H, the application must write 1 into the bit.

The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

258

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

The application must clear the USB_GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.

Bit Position Offset

0x3C014

Reset Access Name Bit

31

30:24

23 22 21 20 19 18

17:16

15

Name Reset Access Description

WKUPINT 0 RW1H

Resume/Remote Wakeup Detected Interrupt

Wakeup Interrupt during Suspend state. In Device mode this interrupt is asserted only when Host Initiated Resume is detected on USB. In Host mode this interrupt is asserted only when Device Initiated Remote Wakeup is detected on USB. This bit can be set only by the core and the application should write 1 to clear.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RESETDET 0 RW1H

Reset detected Interrupt

In Device mode, this interrupt is asserted when a reset is detected on the USB in EM2 when the device is in Suspend.

In Host mode, this interrupt is not asserted.

FETSUSP 0 RW1H

Data Fetch Suspended

This interrupt is valid only in DMA mode. This interrupt indicates that the core has stopped fetching data for IN endpoints due to the unavailability of TxFIFO space or Request Queue space. This interrupt is used by the application for an endpoint mismatch algorithm.

For example, after detecting an endpoint mismatch, the application: Sets a Global non-periodic IN NAK handshake, Disables In endpoints, Flushes the FIFO, Determines the token sequence from the IN Token Sequence, Re-enables the endpoints, Clears the Global non-periodic IN NAK handshake.

If the Global non-periodic IN NAK is cleared, the core has not yet fetched data for the IN endpoint, and the IN token is received: the core generates an IN Token Received when FIFO Empty interrupt. The OTG then sends the host a NAK response. To avoid this scenario, the application can check the USB_GINTSTS.FETSUSP interrupt, which ensures that the FIFO is full before clearing a Global NAK handshake. Alternatively, the application can mask the IN Token Received when FIFO Empty interrupt when clearing a Global IN NAK handshake.

INCOMPLP 0 RW1H

Incomplete Periodic Transfer

In Host mode, the core sets this interrupt bit when there are incomplete periodic transactions still pending which are scheduled for the current frame. In Device mode, the core sets this interrupt to indicate that there is at least one isochronous OUT endpoint on which the transfer is not completed in the current frame. This bit can be set only by the core and the application should write 1 to clear it.

INCOMPISOIN 0 RW1H

Incomplete Isochronous IN Transfer

The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in the current frame.

OEPINT 0 R

OUT Endpoints Interrupt

The core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of the core (in Device mode). The application must read the Device All Endpoints Interrupt (USB_DAINT) register to determine the exact number of the OUT endpoint on which the interrupt occurred, and then read the corresponding Device OUT Endpoint-x Interrupt (USB_DOEP0INT/USB_DOEPx_INT) register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding USB_DOEP0INT/USB_DOEPx_INT register to clear this bit.

IEPINT 0 R

IN Endpoints Interrupt

The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the core (in Device mode). The application must read the Device All Endpoints Interrupt (USB_DAINT) register to determine the exact number of the IN endpoint on Device IN Endpoint-x Interrupt (USB_DIEP0INT/USB_DIEPx_INT) register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding USB_DIEP0INT/USB_DIEPx_INT register to clear this bit.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

EOPF 0 RW

End of Periodic Frame Interrupt

Indicates that the period specified in the Periodic Frame Interval field of the Device Configuration register (DCFG_PERFRINT) has been reached in the current microframe.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

259

www.silabs.com

5

4 3 10

9:8

7

Bit

14 13 12 11 6

2:1

0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

ISOOUTDROP 0 RW1H

Isochronous OUT Packet Dropped Interrupt

The core sets this bit when it fails to write an isochronous OUT packet into the RxFIFO because the RxFIFO does not have enough space to accommodate a maximum packet size packet for the isochronous OUT endpoint.

ENUMDONE 0 RW1H

Enumeration Done

The core sets this bit to indicate that speed enumeration is complete. The application must read the Device Status (USB_DSTS) register to obtain the enumerated speed.

USBRST 0 RW1H

USB Reset

The core sets this bit to indicate that a reset is detected on the USB.

USBSUSP 0 RW1H

USB Suspend

The core sets this bit to indicate that a suspend was detected on the USB. The core enters the Suspended state when there is no activity on the bus for an extended period of time.

ERLYSUSP 0 RW1H

Early Suspend

The core sets this bit to indicate that an Idle state has been detected on the USB for 3 ms.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

GOUTNAKEFF 0 R

Global OUT NAK Effective

Indicates that the Set Global OUT NAK bit in the Device Control register (USB_DCTL.SGOUTNAK), set by the application, has taken effect in the core. This bit can be cleared by writing the Clear Global OUT NAK bit in the Device Control register (USB_DCTL.CGOUTNAK).

GINNAKEFF 0 R

Global IN Non-periodic NAK Effective

Indicates that the Set Global Non-periodic IN NAK bit in the Device Control register (USB_DCTL.SGNPINNAK), set by the application, has taken effect in the core. That is, the core has sampled the Global IN NAK bit set by the application. This bit can be cleared by clearing the Clear Global Non-periodic IN NAK bit in the Device Control register (USB_DCTL.CGNPINNAK). This interrupt does not necessarily mean that a NAK handshake is sent out on the USB. The STALL bit takes precedence over the NAK bit.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXFLVL 0 R

RxFIFO Non-Empty

Indicates that there is at least one packet pending to be read from the RxFIFO.

SOF 0 RW1H

Start of Frame

In Host mode, the core sets this bit to indicate that an SOF (FS) or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to this bit to clear the interrupt.

In Device mode, in the core sets this bit to indicate that an SOF token has been received on the USB. The application can read the Device Status register to get the current frame number. This interrupt is seen only when the core is operating at full-speed (FS). This bit can be set only by the core and the application should write 1 to clear it.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CURMOD Indicates the current mode.

0 R

Current Mode of Operation

Value 0 Mode DEVICE Description Device mode.

14.6.12 USB_GINTMSK - Interrupt Mask Register

This register works with the Interrupt Register (USB_GINTSTS) to interrupt the application. When an interrupt bit is masked (bit is 0), the interrupt associated with that bit is not generated. However, the USB_GINTSTS register bit corresponding to that interrupt is still set.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

260

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Bit Position Offset

0x3C018

Reset Access Name Bit

31 22 21 20 19 18 14 13 12 11 10 6

5

4

30:24

23

17:16

15

9:8

7

Name Reset Access Description

WKUPINTMSK 0 Set to 1 to unmask WKUPINT interrupt.

Reserved

RW

Resume/Remote Wakeup Detected Interrupt Mask

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RESETDETMSK 0 Set to 1 to unmask RESETDET interrupt.

FETSUSPMSK 0 Set to 1 to unmask FETSUSP interrupt.

INCOMPLPMSK 0 Set to 1 to unmask INCOMPLP interrupt.

INCOMPISOINMSK 0 Set to 1 to unmask INCOMPISOIN interrupt.

OEPINTMSK 0 Set to 1 to unmask OEPINT interrupt.

RW RW RW RW RW

Reset detected Interrupt Mask Data Fetch Suspended Mask Incomplete Periodic Transfer Mask Incomplete Isochronous IN Transfer Mask OUT Endpoints Interrupt Mask

IEPINTMSK 0 Set to 1 to unmask IEPINT interrupt.

Reserved

RW

IN Endpoints Interrupt Mask

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

EOPFMSK 0 Set to 1 to unmask EOPF interrupt.

RW

End of Periodic Frame Interrupt Mask

ISOOUTDROPMSK 0 Set to 1 to unmask ISOOUTDROP interrupt.

ENUMDONEMSK 0 Set to 1 to unmask ENUMDONE interrupt.

USBRSTMSK 0 Set to 1 to unmask USBRST interrupt.

RW RW RW

Isochronous OUT Packet Dropped Interrupt Mask Enumeration Done Mask USB Reset Mask

USBSUSPMSK 0 Set to 1 to unmask USBSUSP interrupt.

RW

USB Suspend Mask

ERLYSUSPMSK 0 Set to 1 to unmask ERLYSUSP interrupt.

Reserved

RW

Early Suspend Mask

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

GOUTNAKEFFMSK 0 Set to 1 to unmask GOUTNAKEFF interrupt.

GINNAKEFFMSK 0 Set to 1 to unmask GINNAKEFF interrupt.

Reserved

RW RW

Global OUT NAK Effective Mask Global Non-periodic IN NAK Effective Mask

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXFLVLMSK 0 RW

Receive FIFO Non-Empty Mask

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

261

www.silabs.com

Bit

3

2

1

0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Set to 1 to unmask RXFLVL interrupt.

SOFMSK 0 Set to 1 to unmask SOF interrupt.

Reserved

RW

Start of Frame Mask

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

MODEMISMSK 0 Set to 1 to unmask MODEMIS interrupt.

Reserved

RW

Mode Mismatch Interrupt Mask

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

14.6.13 USB_GRXSTSR - Receive Status Debug Read Register

A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO.

The receive status contents must be interpreted differently in Host and Device modes. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core Interrupt register (USB_GINTSTS.RXFLVL) is asserted.

Offset

0x3C01C

Bit Position Reset Access Name Bit

31:25

24:21 20:17 16:15

Name Reset Access Description

Reserved

3 4 5 6 7

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

FN 0x0 R

Frame Number

This is the least significant 4 bits of the Frame number in which the packet is received on the USB.

PKTSTS 0x0 Indicates the status of the received packet.

R

Packet Status (host or device)

Value 1 2 Mode GOUTNAK PKTRCV XFERCOMPL SETUPCOMPL TGLERR SETUPRCV CHLT Description Device mode: Global OUT NAK (triggers an interrupt).

Host mode: IN data packet received.

Device mode: OUT data packet received.

Host mode: IN transfer completed (triggers an interrupt).

Device mode: OUT transfer completed (triggers an interrupt).

Device mode: SETUP transaction completed (triggers an interrupt).

Host mode: Data toggle error (triggers an interrupt).

Device mode: SETUP data packet received.

Host mode: Channel halted (triggers an interrupt).

DPID 0x0 R

Data PID (host or device)

Host mode: Indicates the Data PID of the received packet. Device mode: Indicates the Data PID of the received OUT data packet.

Value 0 1 2 Mode DATA0 DATA1 DATA2 Description DATA0 PID.

DATA1 PID.

DATA2 PID.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

262

www.silabs.com

Bit

14:4 3:0

Preliminary

...the world's most energy friendly microcontrollers

Name

Value 3 Mode MDATA

Reset Access Description

Description MDATA PID.

BCNT 0x000 R

Byte Count (host or device)

Host mode: Indicates the byte count of the received IN data packet.

Device mode: Indicates the byte count of the received data packet.

CHEPNUM 0x0 R

Channel Number host only / Endpoint Number

Host mode: Indicates the channel number to which the current received packet belongs.

Device mode: Indicates the endpoint number to which the current received packet belongs.

14.6.14 USB_GRXSTSP - Receive Status Read and Pop Register

A read to the Receive Status Read and Pop register returns the contents of the top of the Receive FIFO and pops the top data entry out of the RxFIFO. The receive status contents must be interpreted differently in Host and Device modes. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core Interrupt register (USB_GINTSTS.RXFLVL) is asserted.

Offset

0x3C020

Bit Position Reset Access Name Bit

31:25

24:21 20:17 16:15 4 5 6 7

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

FN 0x0 R

Frame Number

This is the least significant 4 bits of the Frame number in which the packet is received on the USB.

PKTSTS 0x0 Indicates the status of the received packet.

R

Packet Status (host or device)

Value 1 2 3 Mode GOUTNAK PKTRCV XFERCOMPL SETUPCOMPL TGLERR SETUPRCV CHLT Description Device mode: Global OUT NAK (triggers an interrupt).

Host mode: IN data packet received.

Device mode: OUT data packet received.

Host mode: IN transfer completed (triggers an interrupt).

Device mode: OUT transfer completed (triggers an interrupt).

Device mode: SETUP transaction completed (triggers an interrupt).

Host mode: Data toggle error (triggers an interrupt).

Device mode: SETUP data packet received.

Host mode: Channel halted (triggers an interrupt).

DPID 0x0 R Host mode: Indicates the Data PID of the received packet.

Data PID (host or device)

Device mode: Indicates the Data PID of the received OUT data packet.

Value 0 Mode DATA0 Description DATA0 PID.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

263

www.silabs.com

Bit

14:4 3:0

Preliminary

...the world's most energy friendly microcontrollers

Name

Value 1 2 3 Mode DATA1 DATA2 MDATA

Reset Access Description

Description DATA1 PID.

DATA2 PID.

MDATA PID.

BCNT 0x000 R

Byte Count (host or device)

Host mode: Indicates the byte count of the received IN data packet.

Device mode: Indicates the byte count of the received data packet.

CHEPNUM 0x0 R

Channel Number host only / Endpoint Number

Host mode: Indicates the channel number to which the current received packet belongs.

Device mode: Indicates the endpoint number to which the current received packet belongs.

14.6.15 USB_GRXFSIZ - Receive FIFO Size Register

The application can program the RAM size that must be allocated to the RxFIFO.

Offset

0x3C024

Bit Position Reset Access Name Bit

31:10

9:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXFDEP 0x200 RW

RxFIFO Depth

This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.

14.6.16 USB_GNPTXFSIZ - Non-periodic Transmit FIFO Size Register

The application can program the RAM size and the memory start address for the Non-periodic TxFIFO.

Offset

0x3C028

Bit Position Reset Access Name

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

264

www.silabs.com

Bit

31:16

15:10

9:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

NPTXFINEPTXF0DEP 0x0200 RW

Non-periodic TxFIFO Depth host only / IN Endpoint TxFIFO 0 Depth

This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NPTXFSTADDR 0x200 RW

Non-periodic Transmit RAM Start Address host only

This field contains the memory start address for Non-periodic Transmit FIFO RAM. Programmed values must not exceed the reset value.

14.6.17 USB_GDFIFOCFG - Global DFIFO Configuration Register Offset

0x3C05C

Bit Position Reset Access Name Bit

31:16 15:0

Name Reset Access Description

EPINFOBASEADDR 0x05F8 RW This field provides the start address of the EP info controller.

Endpoint Info Base Address

GDFIFOCFG 0x0600 RW

DFIFO Config

This field is for dynamic programming of the DFIFO Size. This value takes effect only when the application programs a non zero value to this register. The core does not have any corrective logic if the FIFO sizes are programmed incorrectly.

14.6.18 USB_DIEPTXF1 - Device IN Endpoint Transmit FIFO 1 Size Register

This register holds the size and memory start address of IN endpoint TxFIFO 1 in Device mode. For IN endpoint FIFO 0 use USB_GNPTXFSIZ register for programming the size and memory start address.

Offset

0x3C104

Bit Position Reset Access Name Bit

31:26

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

265

www.silabs.com

Bit

25:16

15:11

10:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

INEPNTXFDEP 0x200 RW

IN Endpoint TxFIFO Depth

This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNTXFSTADDR 0x400 RW

IN Endpoint FIFO 1 Transmit RAM Start Address

This field contains the memory start address for IN endpoint Transmit FIFO 1.

14.6.19 USB_DIEPTXF2 - Device IN Endpoint Transmit FIFO 2 Size Register

This register holds the size and memory start address of IN endpoint TxFIFO 2 in Device mode. For IN endpoint FIFO 0 use USB_GNPTXFSIZ register for programming the size and memory start address.

Offset

0x3C108

Bit Position Reset Access Name Bit

31:26

25:16

15:11

10:0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNTXFDEP 0x200 RW

IN Endpoint TxFIFO Depth

This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNTXFSTADDR 0x600 RW

IN Endpoint FIFO 2 Transmit RAM Start Address

This field contains the memory start address for IN endpoint Transmit FIFO 2.

14.6.20 USB_DIEPTXF3 - Device IN Endpoint Transmit FIFO 3 Size Register

This register holds the size and memory start address of IN endpoint TxFIFO 3 in Device mode. For IN endpoint FIFO 0 use USB_GNPTXFSIZ register for programming the size and memory start address.

Offset

0x3C10C

Bit Position Reset Access Name

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

266

www.silabs.com

Bit

31:26

25:16

15:12

11:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNTXFDEP 0x200 RW

IN Endpoint TxFIFO Depth

This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNTXFSTADDR 0x800 RW

IN Endpoint FIFO 3 Transmit RAM Start Address

This field contains the memory start address for IN endpoint Transmit FIFO 3.

14.6.21 USB_DCFG - Device Configuration Register

This register configures the core in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.

Offset

0x3C800

Bit Position Reset Access Name Bit

31:26

25:16

15

Name Reset Access Description

RESVALID 0x02 RW

Resume Validation Period

This field is effective only when USB_DCFG.ENA32KHZSUSP is set. It will control the resume period when the core resumes from suspend. The core counts for RESVALID number of clock cycles to detect a valid resume when USB_DCFG.ENA32KHZSUSP is set.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

ERRATICINTMSK 0 RW

14:13

12:11 10:4 3 2 1:0

Reserved

Value 0 1 2 3 Mode 80PCNT 85PCNT 90PCNT 95PCNT

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PERFRINT 0x0 RW

Periodic Frame Interval

Indicates the time within a frame at which the application must be notified using the End Of Periodic Frame Interrupt. This can be used to determine if all the isochronous traffic for that frame is complete.

Description 80% of the frame interval.

85% of the frame interval.

90% of the frame interval.

95% of the frame interval.

DEVADDR 0x00 RW

Device Address

The application must program this field after every SetAddress control command.

ENA32KHZSUSP 0 RW

Enable 32 KHz Suspend mode

When this bit is set, the core expects that the PHY clock during Suspend is switched from 48 MHz to 32 KHz.

NZSTSOUTHSHK 0 RW

Non-Zero-Length Status OUT Handshake

The application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the OUT transaction of a control transfer's Status stage. When set to 1 send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application. When set to 0 send the received OUT packet to the application (zerolength or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register.

DEVSPD 0x0 RW

Device Speed

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

267

www.silabs.com

Bit Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Indicates the speed at which the application requires the core to enumerate, or the maximum speed the application can support.

However, the actual bus speed is determined only after the chirp sequence is completed, and is based on the speed of the USB host to which the core is connected.

Value 2 3 Mode LS FS Description Low speed (PHY clock is 6 MHz). If you select 6 MHz LS mode, you must do a soft reset.

Full speed (PHY clock is 48 MHz).

14.6.22 USB_DCTL - Device Control Register Offset

0x3C804

Reset Access Bit Position Name Bit

31:17

16 15

14:12

11 10 9 8 7 6:4

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NAKONBBLE 0 RW

NAK on Babble Error

Set NAK automatically on babble. The core sets NAK automatically for the endpoint on which babble is received.

IGNRFRMNUM 0 RW

Ignore Frame number For Isochronous End points

When set to 0 the core transmits the packets only in the frame number in which they are intended to be transmitted. When set to 1 the core ignores the frame number, sending packets immediately as the packets are ready.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PWRONPRGDONE 0 RW

Power-On Programming Done

The application uses this bit to indicate that register programming is completed after a wake-up from Power Down mode.

CGOUTNAK 0 A write to this field clears the Global OUT NAK.

W1

Clear Global OUT NAK

SGOUTNAK 0 W1

Set Global OUT NAK

A write to this field sets the Global OUT NAK. The application uses this bit to send a NAK handshake on all OUT endpoints.

The application must set this bit only after making sure that the Global OUT NAK Effective bit in the Core Interrupt Register (USB_GINTSTS.GOUTNAKEFF) is cleared.

CGNPINNAK 0 W1 A write to this field clears the Global Non-periodic IN NAK.

Clear Global Non-periodic IN NAK

SGNPINNAK 0 W1

Set Global Non-periodic IN NAK

A write to this field sets the Global Non-periodic IN NAK. The application uses this bit to send a NAK handshake on all non-periodic IN endpoints. The application must set this bit only after making sure that the Global IN NAK Effective bit in the Core Interrupt Register (USB_GINTSTS.GINNAKEFF) is cleared.

TSTCTL 0x0 Set to a non-zero value to enable test control.

RW

Test Control

2 3 4 Value 0 1 Mode DISABLE J K SE0NAK PACKET Description Test mode disabled.

Test_J mode.

Test_K mode.

Test_SE0_NAK mode.

Test_Packet mode.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

268

www.silabs.com

3 2 1 0

Bit Preliminary

...the world's most energy friendly microcontrollers

Name

Value 5 Mode FORCE

Reset Access Description

Description Test_Force_Enable.

GOUTNAKSTS 0 R

Global OUT NAK Status

When this bit is 0 a handshake is sent based on the FIFO Status and the NAK and STALL bit settings. When this bit is 1 no data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions.

All isochronous OUT packets are dropped.

GNPINNAKSTS 0 R

Global Non-periodic IN NAK Status

When this bit is 0 a handshake is sent out based on the data availability in the transmit FIFO. When this bit is 1 a NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO.

SFTDISCON 1 RW

Soft Disconnect

The application uses this bit to signal the core to do a soft disconnect. As long as this bit is set, the host does not see that the device is connected, and the device does not receive signals on the USB. The core stays in the disconnected state until the application clears this bit. When suspended, the minimum duration for which the core must keep this bit set is 1 ms + 2.5 us. When IDLE or performing transactions, the minimum duration for which the core must keep this bit set is 2.5 us.

RMTWKUPSIG 0 RW

Remote Wakeup Signaling

When the application sets this bit, the core initiates remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the Suspend state. As specified in the USB 2.0 specification, the application must clear this bit 1-15 ms after setting it.

14.6.23 USB_DSTS - Device Status Register

This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from Device All Interrupts (USB_DAINT) register.

Offset

0x3C808

Bit Position Reset Access Name Bit

31:24

23:22 21:8

7:4

3 2:1

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DEVLNSTS 0x0 R

Device Line Status

Indicates the current logic level USB data lines: DEVLNSTS[1]: Logic level of D+; DEVLNSTS[0]: Logic level of D-.

SOFFN 0x0000 R

Frame Number of the Received SOF

This field contains a Frame number. This field may return a non zero value if read immediately after power on reset. In case the register bits reads non zero immediately after power on reset it does not indicate that SOF has been received from the host. The read value of this interrupt is valid only after a valid connection between host and device is established.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

ERRTICERR 0 R

Erratic Error

The core sets this bit to report any erratic errors (PHY error) Due to erratic errors, the core goes into Suspended state and an interrupt is generated to the application with Early Suspend bit of the Core Interrupt register (USB_GINTSTS.ERLYSUSP). If the early suspend is asserted due to an erratic error, the application can only perform a soft disconnect recover.

ENUMSPD 0x1 R

Enumerated Speed

Indicates the speed at which the core has come up after speed detection through a chirp sequence.

Value 2 Mode LS Description Low speed (PHY clock is running at 6 MHz).

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

269

www.silabs.com

0

Bit Preliminary

...the world's most energy friendly microcontrollers

Name

Value 3 Mode FS

Reset Access Description

Description Full speed (PHY clock is running at 48 MHz).

SUSPSTS 0 R

Suspend Status

In Device mode, this bit is set as long as a Suspend condition is detected on the USB. The core enters the Suspended state when there is no activity on the bus for an extended period of time. The core comes out of the suspend when there is any activity on the bus or when the application writes to the Remote Wakeup Signaling bit in the Device Control register (USB_DCTL.RMTWKUPSIG).

14.6.24 USB_DIEPMSK - Device IN Endpoint Common Interrupt Mask Register

This register works with each of the Device IN Endpoint Interrupt (USB_DIEP0INT/USB_DIEPx_INT) registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the USB_DIEP0INT/USB_DIEPx_INT register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.

Bit Position Offset

0x3C810

Reset Access Name

5

4

7

6

Bit

31:14

13

12:9

8 3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NAKMSK 0 Set to 1 to unmask NAK Interrupt.

Reserved

RW

NAK interrupt Mask

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXFIFOUNDRNMSK 0 Set to 1 to unmask TXFIFOUNDRN Interrupt.

RW

Reserved

Fifo Underrun Mask

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNAKEFFMSK 0 Set to 1 to unmask INEPNAKEFF Interrupt.

Reserved

RW

IN Endpoint NAK Effective Mask

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INTKNTXFEMPMSK 0 Set to 1 to unmask INTKNTXFEMP Interrupt.

RW

IN Token Received When TxFIFO Empty Mask

TIMEOUTMSK 0 RW

Timeout Condition Mask

Set to 1 to unmask Interrupt TIMEOUT. Applies to Non-isochronous endpoints.

AHBERRMSK 0 Set to 1 to unmask AHBERR Interrupt.

RW

AHB Error Mask

RW

Endpoint Disabled Interrupt Mask

EPDISBLDMSK 0 Set to 1 to unmask EPDISBLD Interrupt.

XFERCOMPLMSK 0 Set to 1 to unmask XFERCOMPL Interrupt.

RW

Transfer Completed Interrupt Mask

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

270

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.6.25 USB_DOEPMSK - Device OUT Endpoint Common Interrupt Mask Register

This register works with each of the Device OUT Endpoint Interrupt (USB_DOEP0INT/ USB_DOEPx_INT) registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the USB_DOEP0INT/USB_DOEPx_INT register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.

Offset

0x3C814

Reset Access Bit Position Name

7

6

Bit

31:14

13 12

11:9

8 5 4 3 2 1 0

Name Reset Access Description

Reserved

NAKMSK

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Set to 1 to unmask NAK Interrupt.

BBLEERRMSK 0 Set to 1 to unmask BBLEERR Interrupt.

RW RW

NAK interrupt Mask Babble Error interrupt Mask

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

OUTPKTERRMSK 0 Set to 1 to unmask OUTPKTERR Interrupt.

Reserved

RW

OUT Packet Error Mask

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BACK2BACKSETUP 0 RW

Back-to-Back SETUP Packets Received Mask

Set to 1 to unmask BACK2BACKSETUP Interrupt. Applies to control OUT endpoints only.

STSPHSERCVDMSK 0 RW

Status Phase Received Mask

Set to 1 to unmask STSPHSERCVD Interrupt. Applies to control OUT endpoints only.

OUTTKNEPDISMSK 0 RW

OUT Token Received when Endpoint Disabled Mask

Set to 1 to unmask OUTTKNEPDIS Interrupt. Applies to control OUT endpoints only.

SETUPMSK 0 RW

SETUP Phase Done Mask

Set to 1 to unmask SETUP Interrupt. Applies to control endpoints only.

RW

AHB Error

AHBERRMSK 0 Set to 1 to unmask AHBERR Interrupt.

EPDISBLDMSK 0 Set to 1 to unmask EPDISBLD Interrupt.

XFERCOMPLMSK 0 Set to 1 to unmask XFERCOMPL Interrupt.

RW RW

Endpoint Disabled Interrupt Mask Transfer Completed Interrupt Mask 14.6.26 USB_DAINT - Device All Endpoints Interrupt Register

When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register interrupts the application using the Device OUT Endpoints Interrupt bit or Device IN Endpoints Interrupt bit of 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

271

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

the Core Interrupt register (USB_GINTSTS.OEPINT or USB_GINTSTS.IEPINT, respectively). There is one interrupt bit per endpoint. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding Device Endpoint Interrupt register (USB_DIEP0INT/USB_DIEPx_INT, USB_DOEP0INT/ USB_DOEPx_INT).

Offset

0x3C818

Reset Access Bit Position Name Bit

31:20

19 18 17 16

15:4

3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

OUTEPINT3 0 R

OUT Endpoint 3 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DOEP2_INT are set.

OUTEPINT2 0 R

OUT Endpoint 2 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DOEP1_INT are set.

OUTEPINT1 0 R

OUT Endpoint 1 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DOEP0_INT are set.

OUTEPINT0 0 R

OUT Endpoint 0 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DOEP0INT are set.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPINT3 0 R

IN Endpoint 3 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DIEP2_INT are set.

INEPINT2 0 R

IN Endpoint 2 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DIEP1_INT are set.

INEPINT1 0 R

IN Endpoint 1 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DIEP0_INT are set.

INEPINT0 0 R

IN Endpoint 0 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DIEP0INT are set.

14.6.27 USB_DAINTMSK - Device All Endpoints Interrupt Mask Register

The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register to interrupt the application when an event occurs on a device endpoint. However, the Device All Endpoints Interrupt (USB_DAINT) register bit corresponding to that interrupt is still set.

Offset

0x3C81C

Reset Access Bit Position Name

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

272

www.silabs.com

Bit

31:20

19 18 17 16

15:4

3 2 1 0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

OUTEPMSK3 0 Set to 1 to unmask USB_DAINT.OUTEPINT3.

RW OUTEPMSK2 0 Set to 1 to unmask USB_DAINT.OUTEPINT2.

RW OUTEPMSK1 0 Set to 1 to unmask USB_DAINT.OUTEPINT1.

RW

OUT Endpoint 3 Interrupt mask Bit OUT Endpoint 2 Interrupt mask Bit OUT Endpoint 1 Interrupt mask Bit

OUTEPMSK0 0 Set to 1 to unmask USB_DAINT.OUTEPINT0.

RW

Reserved

OUT Endpoint 0 Interrupt mask Bit

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RW

IN Endpoint 3 Interrupt mask Bit

INEPMSK3 0 Set to 1 to unmask USB_DAINT.INEPINT3.

INEPMSK2 0 Set to 1 to unmask USB_DAINT.INEPINT2.

INEPMSK1 0 Set to 1 to unmask USB_DAINT.INEPINT1.

INEPMSK0 0 Set to 1 to unmask USB_DAINT.INEPINT0.

RW RW RW

IN Endpoint 2 Interrupt mask Bit IN Endpoint 1 Interrupt mask Bit IN Endpoint 0 Interrupt mask Bit 14.6.28 USB_DIEPEMPMSK - Device IN Endpoint FIFO Empty Interrupt Mask Register

This register is used to control the IN endpoint FIFO empty interrupt generation (USB_DIEP0INT/ USB_DIEPx_INT.TXFEMP).

Offset

0x3C834

Bit Position Reset Access Name Bit

31:16

15:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DIEPEMPMSK 0x0000 RW

IN EP Tx FIFO Empty Interrupt Mask Bits

These bits acts as mask bits for USB_DIEP0INT.TXFEMP/USB_DIEPx_INT.TXFEMP interrupt. One bit per IN Endpoint: Bit 0 for IN EP 0, bit 6 for IN EP 6.

14.6.29 USB_DIEP0CTL - Device IN Endpoint 0 Control Register

This section describes the Control IN Endpoint 0 Control register. Nonzero control endpoints use registers for endpoints 1 - 6.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

273

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Bit Position Offset

0x3C900

Reset Access Name Bit

31 30

29:28

27 26 25:22 21

20

19:18 17

16

15

14:2

1:0

Name Reset Access Description

EPENA 0 RW1H

Endpoint Enable

In DMA mode this bit indicates that data is ready to be transmitted on the endpoint. The core clears this bit before setting the following interrupts on this endpoint: Endpoint Disabled, Transfer Completed.

EPDIS 0 RW1H

Endpoint Disable

The application sets this bit to stop transmitting data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint Disabled Interrupt. The application must set this bit only if Endpoint Enable is already set for this endpoint.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SNAK 0 W1

Set NAK

A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint.

CNAK 0 W1 A write to this bit clears the NAK bit for the endpoint.

Clear NAK

TXFNUM 0x0 RW

TxFIFO Number

This value is set to the FIFO number that is assigned to IN Endpoint 0.

STALL 0 RW1H

Handshake

The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global Nonperiodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

EPTYPE 0x0 R Hardcoded to 0. Endpoint 0 is always a control endpoint.

Endpoint Type

NAKSTS When this bit is 0 the core is transmitting non-NAK handshakes based on the FIFO status. When this bit is 1 the core is transmitting NAK handshakes on this endpoint. When this bit is set, either by the application or core, the core stops transmitting data, even if there is data available in the TxFIFO. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Reserved

0 R

NAK Status

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USBACTEP 1 R

USB Active Endpoint

This bit is always 1, indicating that control endpoint 0 is always active in all configurations and interfaces.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

MPS 0x0 RW

Maximum Packet Size

The application must program this field with the maximum packet size for the current logical endpoint.

Value 0 1 2 3 Mode 64B 32B 16B 8B Description 64 bytes.

32 bytes.

16 bytes.

8 bytes.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

274

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.6.30 USB_DIEP0INT - Device IN Endpoint 0 Interrupt Register

This register indicates the status of endpoint 0 with respect to USB- and AHB-related events. The application must read this register when the IN Endpoints Interrupt bit of the Core Interrupt register (USB_GINTSTS.IEPINT) is set. Before the application can read this register, it must first read the Device All Endpoints Interrupt (USB_DAINT) register to get the exact endpoint number for the Device Endpoint Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the USB_DAINT and USB_GINTSTS registers.

Bit Position Offset

0x3C908

Reset Access Name

5

4

Bit

31:14

13 12 11

10:8

7 6 3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NAKINTRPT 0 RW1H

NAK Interrupt

The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo.

BBLEERR 0 RW1H

NAK Interrupt

The core generates this interrupt when babble is received for the endpoint.

PKTDRPSTS 0 RW1H

Packet Drop Status

This bit indicates to the application that an ISO OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXFEMP 1 R

Transmit FIFO Empty

This interrupt is asserted when the TxFIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the TxFIFO Empty Level bit in the Core AHB Configuration register (USB_GAHBCFG.NPTXFEMPLVL).

INEPNAKEFF Applies to periodic IN endpoints only. This bit can be cleared when the application clears the IN endpoint NAK by writing to USB_DIEP0CTL.CNAK. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core).

The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Reserved

0 RW1H

IN Endpoint NAK Effective

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INTKNTXFEMP 0 RW1H

IN Token Received When TxFIFO is Empty

Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

TIMEOUT 0 RW1H

Timeout Condition

Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

AHBERR 0 RW1H

AHB Error

This is generated in DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address.

EPDISBLD 0 RW1H

Endpoint Disabled Interrupt

This bit indicates that the endpoint is disabled per the application's request.

XFERCOMPL 0 RW1H

Transfer Completed Interrupt

This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

275

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.6.31 USB_DIEP0TSIZ - Device IN Endpoint 0 Transfer Size Register

The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using Endpoint Enable bit of the Device Control Endpoint 0 Control register (USB_DIEP0CTL.EPENA), the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit. Nonzero endpoints use the registers for endpoints 1-6.

Offset

0x3C910

Bit Position Reset Access Name Bit

31:21

20:19

18:7

6:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PKTCNT 0x0 RW

Packet Count

Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0. This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

XFERSIZE 0x00 RW

Transfer Size

Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet.

The core decrements this field every time a packet from the external memory is written to the TxFIFO.

14.6.32 USB_DIEP0DMAADDR - Device IN Endpoint 0 DMA Address Register Offset

0x3C914

Bit Position Reset Access Name Bit

31:0

Name Reset Access Description

DIEP0DMAADDR 0xXXXXXXXX RW

DMA Address

Holds the start address of the external memory for fetching endpoint data. For control endpoints, this field stores control OUT data packets as well as SETUP transaction data packets. When more than three SETUP packets are received back-to-back, the SETUP data packet in the memory is overwritten. This register is incremented on every AHB transaction. The application can give only a DWORD-aligned address. The data for this register field is stored in RAM. Thus, the reset value is undefined (X).

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

276

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.6.33 USB_DIEP0TXFSTS - Device IN Endpoint 0 Transmit FIFO Status Register

This read-only register contains the free space information for the Device IN endpoint 0 TxFIFO.

Offset

0x3C918

Bit Position Reset Access Name Bit

31:16

15:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SPCAVAIL 0x0200 R

TxFIFO Space Available

Indicates the amount of free space available in the Endpoint TxFIFO. Values are in terms of 32-bit words.

14.6.34 USB_DIEPx_CTL - Device IN Endpoint x+1 Control Register

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset

0x3C920

Bit Position Reset Access Name Bit

31 30 29 28

Name Reset Access Description

EPENA 0 RW1H

Endpoint Enable

In DMA mode for IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP Phase Done, Endpoint Disabled, Transfer Completed. For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.

EPDIS 0 RW1H

Endpoint Disable

The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete.

The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint Disabled interrupt. The application must set this bit only if Endpoint Enable is already set for this endpoint.

SETD1PIDOF 0 W1

Set DATA1 PID / Odd Frame

For bulk and interrupt endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field in this register to DATA1ODD.

For isochronous endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field to odd (DATA1ODD).

SETD0PIDEF 0 W1

Set DATA0 PID / Even Frame

For bulk and interrupt endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field in this register to DATA0EVEN.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

277

www.silabs.com

Bit

27 26 25:22 21

20

19:18 17 16 15

14:11

10:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

For isochronous endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field to odd (DATA0EVEN).

SNAK 0 W1

Set NAK

A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint.

CNAK 0 W1 A write to this bit clears the NAK bit for the endpoint.

Clear NAK

TXFNUM 0x0 RW

TxFIFO Number

These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints.

STALL 0 RW1H

Handshake

For bulk and interrupt endpoints: The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. In this case only the application can clear this bit, never the core.

When control endpoint: The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint.

If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

EPTYPE 0x0 RW This is the transfer type supported by this logical endpoint.

Endpoint Type

Value 0 1 2 3 NAKSTS 0 R

NAK Status

When this bit is 0 the core is transmitting non-NAK handshakes based on the FIFO status. When this bit is 1 the core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit the core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet. For non-isochronous IN endpoints the core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO. For isochronous IN endpoints the core sends out a zero-length data packet, even if there data is available in the TxFIFO. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

DPIDEOF 0 R

Endpoint Data PID / Even or Odd Frame

For interrupt/bulk endpoints this field contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The applications use the SETD1PIDOF and SETD0PIDEF fields of this register to program either DATA0 or DATA1 PID. For isochronous endpoints, this field indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SETD0PIDEF and SETD1PIDOF fields in this register.

Value 0 1 Mode CONTROL ISO BULK INT Mode DATA0EVEN DATA1ODD Description Control Endpoint.

Isochronous Endpoint.

Bulk Endpoint.

Interrupt Endpoint.

Description DATA0 PID / Even Frame.

DATA1 PID / Odd Frame.

USBACTEP 0 RW

USB Active Endpoint

Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

MPS 0x000 RW

Maximum Packet Size

The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

14.6.35 USB_DIEPx_INT - Device IN Endpoint x+1 Interrupt Register

This register indicates the status of an endpoint with respect to USB- and AHB-related events. The application must read this register when the IN Endpoints Interrupt bit of the Core Interrupt register (USB_GINTSTS.IEPINT) is set. Before the application can read this register, it must first read the 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

278

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Device All Endpoints Interrupt (USB_DAINT) register to get the exact endpoint number for the Device Endpoint x+1 Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the USB_DAINT and USB_GINTSTS registers.

Bit Position Offset

0x3C928

Reset Access Name

5

4

Bit

31:14

13 12 11

10:8

7 6 3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NAKINTRPT 0 RW1H

NAK Interrupt

The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo.

BBLEERR 0 RW1H

NAK Interrupt

The core generates this interrupt when babble is received for the endpoint.

PKTDRPSTS 0 RW1H

Packet Drop Status

This bit indicates to the application that an ISO OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXFEMP 1 R

Transmit FIFO Empty

This interrupt is asserted when the TxFIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the TxFIFO Empty Level bit in the Core AHB Configuration register (USB_GAHBCFG.NPTXFEMPLVL).

INEPNAKEFF Applies to periodic IN endpoints only. This bit can be cleared when the application clears the IN endpoint NAK by writing to USB_DIEPx_CTL.CNAK. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Reserved

0 RW1H

IN Endpoint NAK Effective

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INTKNTXFEMP 0 RW1H

IN Token Received When TxFIFO is Empty

Applies to non-periodic IN endpoints only. Indicates that an IN token was received when the associated TxFIFO (periodic/non periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

TIMEOUT 0 RW1H

Timeout Condition

Applies only to Control IN endpoints. Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

AHBERR 0 RW1H

AHB Error

This is generated only in DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address.

EPDISBLD 0 RW1H

Endpoint Disabled Interrupt

This bit indicates that the endpoint is disabled per the application's request.

XFERCOMPL 0 RW1H

Transfer Completed Interrupt

This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

279

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.6.36 USB_DIEPx_TSIZ - Device IN Endpoint x+1 Transfer Size Register

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint x+1 Control register (USB_DIEPx_CTL.EPENA), the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit.

Offset

0x3C930

Bit Position Reset Access Name Bit

31

30:29 28:19 18:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

MC 0x0 RW

Multi Count

For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.

PKTCNT 0x000 RW

Packet Count

Indicates the total number of USB packets that constitute the Transfer Size amount of data. This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

XFERSIZE 0x00000 RW

Transfer Size

Indicates the transfer size in bytes. The core interrupts the application only after it has exhausted the transfer size amount of data.

The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the TxFIFO.

14.6.37 USB_DIEPx_DMAADDR - Device IN Endpoint x+1 DMA Address Register Offset

0x3C934

Bit Position Reset Access Name Bit

31:0

Name Reset Access Description

DMAADDR 0xXXXXXXXX RW

DMA Address

Holds the start address of the external memory for fetching endpoint data. For control endpoints, this field stores control OUT data packets as well as SETUP transaction data packets. When more than three SETUP packets are received back-to-back, the SETUP 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

280

www.silabs.com

Bit Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

data packet in the memory is overwritten. This register is incremented on every AHB transaction. The application can give only a DWORD-aligned address. The data for this register field is stored in RAM. Thus, the reset value is undefined (X).

14.6.38 USB_DIEPx_TXFSTS - Device IN Endpoint x+1 Transmit FIFO Status Register

This read-only register contains the free space information for the Device IN endpoint TxFIFO.

Offset

0x3C938

Bit Position Reset Access Name Bit

31:16

15:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SPCAVAIL 0x0200 R

TxFIFO Space Available

Indicates the amount of free space available in the Endpoint TxFIFO. Values are in terms of 32-bit words.

14.6.39 USB_DOEP0CTL - Device OUT Endpoint 0 Control Register

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset

0x3CB00

Reset Bit Position Access Name Bit

31 30

29:28

27 26

Name Reset Access Description

EPENA 0 RW1H

Endpoint Enable

In DMA mode this bit indicates that the application has allocated the memory to start receiving data from the USB. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP Phase Done, Endpoint Disabled, Transfer Completed.

In DMA mode, this bit must be set for the core to transfer SETUP data packets into memory.

EPDIS 0 R

Endpoint Disable

This bit is always 0. The application cannot disable control OUT endpoint 0.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SNAK 0 W1

Set NAK

A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set bit on a Transfer Completed interrupt, or after a SETUP is received on the endpoint.

CNAK 0 W1 A write to this bit clears the NAK bit for the endpoint.

Clear NAK

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

281

www.silabs.com

Bit

25:22

21 20 19:18 17

16

15

14:2

1:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

STALL 0 RW1H

Handshake

The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

SNP 0 RW

Snoop Mode

This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory.

EPTYPE 0x0 R Hardcoded to 0. Endpoint 0 is always a control endpoint.

Endpoint Type

NAKSTS 0 R

NAK Status

When this bit is 0 the core is transmitting non-NAK handshakes based on the FIFO status. When this bit is 1 the core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit, the core stops receiving data, even if there is space in the RxFIFO to accommodate the incoming packet. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USBACTEP 1 R

USB Active Endpoint

This bit is always 1, indicating that a control endpoint 0 is always active in all configurations and interfaces.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

MPS 0x0 R

Maximum Packet Size

The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN Endpoint 0.

Value 0 1 2 3 Mode 64B 32B 16B 8B Description 64 bytes.

32 bytes.

16 bytes.

8 bytes.

14.6.40 USB_DOEP0INT - Device OUT Endpoint 0 Interrupt Register

This register indicates the status of endpoint 0 with respect to USB- and AHB-related events. The application must read this register when the OUT Endpoints Interrupt bit of the Core Interrupt register (USB_GINTSTS.OEPINT) is set. Before the application can read this register, it must first read the Device All Endpoints Interrupt (USB_DAINT) register to get the exact endpoint number for the Device Endpoint Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the USB_DAINT and USB_GINTSTS registers.

Offset

0x3CB08

Reset Bit Position Access Name Bit

31:16

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

282

www.silabs.com

1 0

Bit

15

14

13 12 11

10:7

6 5 4 3 2

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

STUPPKTRCVD 0 RW

Setup Packet Received

The core generates this interrupt when a setup packet is received.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NAKINTRPT 0 RW1H

NAK Interrupt

The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo.

BBLEERR 0 RW1H

NAK Interrupt

The core generates this interrupt when babble is received for the endpoint.

PKTDRPSTS 0 RW1H

Packet Drop Status

This bit indicates to the application that an ISO OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BACK2BACKSETUP 0 RW1H

Back-to-Back SETUP Packets Received

This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint.

STSPHSERCVD 0 RW1H

Status Phase Received For Control Write

This interrupt is valid only for Control OUT endpoints and only in Scatter Gather DMA mode. This interrupt is generated only after the core has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer.

The interrupt indicates to the application that the host has switched from data phase to the status phase of a Control Write transfer.

The application can use this interrupt to ACK or STALL the Status phase, after it has decoded the data phase. This is applicable only in Case of Scatter Gather DMA mode.

OUTTKNEPDIS 0 RW1H

OUT Token Received When Endpoint Disabled

Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

SETUP 0 RW1H

Setup Phase Done

Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet.

AHBERR 0 RW1H

AHB Error

This is generated only in DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address.

EPDISBLD 0 RW1H

Endpoint Disabled Interrupt

This bit indicates that the endpoint is disabled per the application's request.

XFERCOMPL 0 RW1H

Transfer Completed Interrupt

This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

14.6.41 USB_DOEP0TSIZ - Device OUT Endpoint 0 Transfer Size Register

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint x+1 Control register (USB_DOEPx_CTL.EPENA), the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit.

Offset

0x3CB10

Reset Access Bit Position Name

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

283

www.silabs.com

Bit

31

30:29

28:20

19

18:7

6:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SUPCNT 0x0 RW

SETUP Packet Count

This field specifies the number of back-to-back SETUP data packets the endpoint can receive.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PKTCNT 0 RW

Packet Count

This field is decremented to zero after a packet is written into the RxFIFO.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

XFERSIZE 0x00 RW

Transfer Size

Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet.

The core decrements this field every time a packet is read from the RxFIFO and written to the external memory.

14.6.42 USB_DOEP0DMAADDR - Device OUT Endpoint 0 DMA Address Register Offset

0x3CB14

Bit Position Reset Access Name Bit

31:0

Name Reset Access Description

DOEP0DMAADDR 0xXXXXXXXX RW

DMA Address

Holds the start address of the external memory for storing endpoint data. For control endpoints, this field stores control OUT data packets as well as SETUP transaction data packets. When more than three SETUP packets are received back-to-back, the SETUP data packet in the memory is overwritten. This register is incremented on every AHB transaction. The application can give only a DWORD-aligned address. The data for this register field is stored in RAM. Thus, the reset value is undefined (X).

14.6.43 USB_DOEPx_CTL - Device OUT Endpoint x+1 Control Register

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

284

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Bit Position Offset

0x3CB20

Reset Access Name Bit

31 30 29 28 27 26

25:22

21 20 19:18 17

Name Reset Access Description

EPENA 0 RW1H

Endpoint Enable

In DMA mode this bit indicates that the application has allocated the memory to start receiving data from the USB. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP Phase Done, Endpoint Disabled, Transfer Completed.

For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.

EPDIS 0 RW1H

Endpoint Disable

The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete.

The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint Disabled interrupt. The application must set this bit only if Endpoint Enable is already set for this endpoint.

SETD1PIDOF 0 W1

Set DATA1 PID / Odd Frame

For bulk and interrupt endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field in this register to DATA1ODD. For isochronous endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field to odd (DATA1ODD).

SETD0PIDEF 0 W1

Set DATA0 PID / Even Frame

For bulk and interrupt endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field in this register to DATA0EVEN. For isochronous endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field to odd (DATA0EVEN).

SNAK 0 W1

Set NAK

A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint.

CNAK 0 W1 A write to this bit clears the NAK bit for the endpoint.

Reserved

Clear NAK

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

STALL 0 RW1H

STALL Handshake

For non-control, non-isochronous endpoints: The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core.

For control endpoints: The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint.

If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

SNP 0 RW

Snoop Mode

This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory.

EPTYPE 0x0 RW This is the transfer type supported by this logical endpoint.

Endpoint Type

Value 0 1 2 3 NAKSTS Mode CONTROL ISO BULK INT 0 R Description Control Endpoint.

Isochronous Endpoint.

Bulk Endpoint.

Interrupt Endpoint.

NAK Status

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

285

www.silabs.com

Bit

16 15

14:11

10:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

When this bit is 0 the core is transmitting non-NAK handshakes based on the FIFO status. When this bit is 1 the core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit the core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

DPIDEOF 0 R

Endpoint Data PID / Even-odd Frame

For interrupt/bulk endpoints: Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application use the SETD1PIDOF and SETD0PIDEF fields of this register to program either DATA0 or DATA1 PID.

For isochronous endpoints: Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SETD1PIDOF and SETD0PIDEF fields in this register.

Value 0 1 Mode DATA0EVEN DATA1ODD Description DATA0 PID / Even Frame.

DATA1 PID / Odd Frame.

USBACTEP 0 RW

USB Active Endpoint

Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

MPS 0x000 RW

Maximum Packet Size

The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

14.6.44 USB_DOEPx_INT - Device OUT Endpoint x+1 Interrupt Register

This register indicates the status of an endpoint with respect to USB- and AHB-related events. The application must read this register when the OUT Endpoints Interrupt bit of the Core Interrupt register (USB_GINTSTS.OEPINT) is set. Before the application can read this register, it must first read the Device All Endpoints Interrupt (USB_DAINT) register to get the exact endpoint number for the Device Endpoint Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the USB_DAINT and USB_GINTSTS registers.

Bit Position Offset

0x3CB28

Reset Access Name Bit

31:16

15

14

13 12

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

STUPPKTRCVD 0 RW

Setup Packet Received

The core generates this interrupt when a setup packet is received.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NAKINTRPT 0 RW1H

NAK Interrupt

The core generates this interrupt when a NAK is transmitted or received by the device.

BBLEERR 0 RW1H

Babble Error

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

286

www.silabs.com

Bit

11

10:7

6 5 4 3 2 1 0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

The core generates this interrupt when babble is received for the endpoint.

PKTDRPSTS 0 RW1H

Packet Drop Status

This bit indicates to the application that an ISO OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BACK2BACKSETUP 0 RW1H

Back-to-Back SETUP Packets Received

Applies to Control OUT endpoints only. This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint.

STSPHSERCVD 0 RW1H

Status Phase Received For Control Write

This interrupt is valid only for Control OUT endpoints and only in Scatter Gather DMA mode. This interrupt is generated only after the core has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer.

The interrupt indicates to the application that the host has switched from data phase to the status phase of a Control Write transfer.

The application can use this interrupt to ACK or STALL the Status phase, after it has decoded the data phase. This is applicable only in Case of Scatter Gather DMA mode.

OUTTKNEPDIS 0 RW1H

OUT Token Received When Endpoint Disabled

Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

SETUP 0 RW1H

Setup Phase Done

Applies to control OUT endpoints only. Indicates that the SETUP phase for the control endpoint is complete and no more back to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet.

AHBERR 0 RW1H

AHB Error

This is generated only in DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address.

EPDISBLD 0 RW1H

Endpoint Disabled Interrupt

This bit indicates that the endpoint is disabled per the application's request.

XFERCOMPL 0 RW1H

Transfer Completed Interrupt

This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

14.6.45 USB_DOEPx_TSIZ - Device OUT Endpoint x+1 Transfer Size Register

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint x+1 Control register (USB_DOEPx_CTL.EPENA), the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit.

Offset Bit Position

0x3CB30

Reset Access Name Bit

31

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

287

www.silabs.com

Bit

30:29 28:19 18:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

RXDPIDSUPCNT 0x0 R

Receive Data PID / SETUP Packet Count

For isochronous OUT endpoints: This is the data PID received in the last packet for this endpoint.

For control OUT Endpoints: This field specifies the number of back-to-back SETUP data packets the endpoint can receive.

Value 0 1 2 3 Mode DATA0 DATA2 DATA1 MDATA Description DATA0 PID.

DATA2 PID / 1 Packet.

DATA1 PID / 2 Packets.

MDATA PID / 3 Packets.

PKTCNT 0x000 RW

Packet Count

This field is decremented to zero after a packet is written into the RxFIFO.

XFERSIZE 0x00000 RW

Transfer Size

Indicates the transfer size in bytes. The core interrupts the application only after it has exhausted the transfer size amount of data.

The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the RxFIFO and written to the external memory.

14.6.46 USB_DOEPx_DMAADDR - Device OUT Endpoint x+1 DMA Address Register Offset

0x3CB34

Bit Position Reset Access Name Bit

31:0

Name Reset Access Description

DMAADDR 0xXXXXXXXX RW

DMA Address

Holds the start address of the external memory for storing endpoint data. For control endpoints, this field stores control OUT data packets as well as SETUP transaction data packets. When more than three SETUP packets are received back-to-back, the SETUP data packet in the memory is overwritten. This register is incremented on every AHB transaction. The application can give only a DWORD-aligned address. The data for this register field is stored in RAM. Thus, the reset value is undefined (X).

14.6.47 USB_PCGCCTL - Power and Clock Gating Control Register

This register is available in Host and Device modes. The application use this register to control the core's power-down and clock gating features.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

288

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Bit Position Offset

0x3CE00

Reset Access Name Bit

31:7

6

5:4

3 2 1 0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PHYSLEEP 0 Indicates that the PHY is in Sleep State.

Reserved

R

PHY In Sleep

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RSTPDWNMODULE 0 RW

Reset Power-Down Modules

The application sets this bit to reset the part of the USB that is powered down during EM2. The application clears this bit to release reset after an waking up from EM2 when the PHY clock is back at 48/6 MHz. Accessing core registers is possible only when this bit is set to 0.

PWRCLMP 0 RW

Power Clamp

The application sets this bit before the power is turned off to clamp the signals between the power-on modules and the power-off modules of the USB core. The application clears the bit to disable the clamping.

GATEHCLK 0 RW

Gate HCLK

The application sets this bit to gate the clock (HCLK) to modules other than the AHB Slave and Master and wakeup logic when the USB is suspended or the session is not valid. The application clears this bit when the USB is resumed or a new session starts.

STOPPCLK 0 RW

Stop PHY clock

The application sets this bit to stop the PHY clock when the USB is suspended, the session is not valid, or the device is disconnected.

The application clears this bit when the USB is resumed or a new session starts.

14.6.48 USB_FIFO0Dx - Device EP 0 FIFO

This register is used to read or write the FIFO space for endpoint 0, in a given direction.

Offset

0x3D000

Bit Position Reset Access Name Bit

31:0

Name Reset Access

FIFO0D 0xXXXXXXXX FIFO 0 push/pop region. Used in slave mode.

RW

Description Device EP 0

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

289

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

14.6.49 USB_FIFO1Dx - Device EP 1 FIFO

This register is used to read or write the FIFO space for endpoint 1, in a given direction.

Offset

0x3E000

Bit Position Reset Access Name Bit

31:0

Name Reset Access

FIFO1D 0xXXXXXXXX FIFO 1 push/pop region. Used in slave mode.

RW

Description Device EP 1 FIFO 14.6.50 USB_FIFO2Dx - Device EP 2 FIFO

This register is used to read or write the FIFO space for endpoint 2, in a given direction.

Offset

0x3F000

Bit Position Reset Access Name Bit

31:0

Name Reset Access

FIFO2D 0xXXXXXXXX FIFO 2 push/pop region. Used in slave mode.

RW

Description Device EP 2 FIFO 14.6.51 USB_FIFO3Dx - Device EP 3 FIFO

This register is used to read or write the FIFO space for endpoint 3, in a given direction.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

290

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Bit Position Offset

0x40000

Reset Access Name Bit

31:0

Name Reset Access

FIFO3D 0xXXXXXXXX FIFO 3 push/pop region. Used in slave mode.

RW

Description Device EP 3 FIFO 14.6.52 USB_FIFORAMx - Direct Access to Data FIFO RAM for Debugging (2 KB) Offset

0x5C000

Bit Position Reset Access Name Bit

31:0

Name Reset Access

FIFORAM 0xXXXXXXXX RW Direct Access to Data FIFO RAM for Debugging (2 KB)

Description FIFO RAM

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

291

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

15 I

2

C - Inter-Integrated Circuit Interface

0 1 2 3 4

V DD Ot her I 2 C m ast er EFM32 I 2 C m ast er/ slave SCL SDA Ot her I 2 C slave I 2 C EEPROM

Quick Facts What?

The I 2 C interface allows communication on I 2 C-buses with the lowest energy consumption possible.

Why?

I 2 C is a popular serial bus that enables communication with a number of external devices using only two I/O pins.

How?

With the help of DMA, the I 2 C interface allows I 2 C communication with minimal CPU intervention. Address recognition is available in all energy modes (except EM4), allowing the MCU to wait for data on the I 2 C-bus with sub-µA current consumption.

15.1 Introduction

The I 2 C module provides an interface between the MCU and a serial I 2 C-bus. It is capable of acting as both master and slave, and supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system. The interface provided to software by the I 2 C module allows both fine-grained control of the transmission process and close to automatic transfers. Automatic recognition of slave addresses is provided in all energy modes (except EM4).

15.2 Features

• True multi-master capability • Support for different bus speeds • Standard-mode (Sm) bit rate up to 100 kbit/s • Fast-mode (Fm) bit rate up to 400 kbit/s • Fast-mode Plus (Fm+) bit rate up to 1 Mbit/s • Arbitration for both master and slave (allows SMBus ARP) • Clock synchronization and clock stretching • Hardware address recognition • 7-bit masked address • General call address • Active in all energy modes (except EM4) • 10-bit address support • Error handling • Clock low timeout • Clock high timeout • Arbitration lost • Bus error detection • Double buffered data • Full DMA support 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

292

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

15.3 Functional Description

An overview of the I 2

C module is shown in Figure 15.1 (p. 293) .

Figure 15.1. I 2 C Overview

Peripheral Bus I2Cn_SDA I2Cn_SCL Pin ct rl I 2 C Cont rol and St at us Sym bol Generat or Transm it Buffer Transm it Shift Regist er Receive Buffer Receive Shift Regist er Receive Cont roller Clock generat or Address Recognizer

15.3.1 I 2 C-Bus Overview

The I 2 C-bus uses two wires for communication; a serial data line (SDA) and a serial clock line (SCL) as

shown in Figure 15.2 (p. 293) . As a true multi-master bus it includes collision detection and arbitration

to resolve situations where multiple masters transmit data at the same time without data loss.

Figure 15.2. I 2 C-Bus Example

I 2 C m ast er #1 I 2 C m ast er #2 I 2 C slave #1 V DD I 2 C slave #2 I 2 C slave #3 R p SDA SCL Each device on the bus is addressable by a unique address, and an I 2 C master can address all the devices on the bus, including other masters.

Both the bus lines are open-drain. The maximum value of the pull-up resistor can be calculated as a function of the maximal rise-time tr for the given bus speed, and the estimated bus capacitance Cb as

shown in Equation 15.1 (p. 293) .

I 2 C Pull-up Resistor Equation

Rp(max) = (tr/0.8473) x Cb.

(15.1) The maximal rise times for 100 kHz, 400 kHz and 1 MHz I 2 C are 1 µs, 300 ns and 120 ns respectively.

Note

The GPIO drive strength can be used to control slew rate.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

293

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Note

If V dd drops below the voltage on SCL and SDA lines, the MCU could become back powered and pull the SCL and SDA lines low.

15.3.1.1 START and STOP Conditions

START and STOP conditions are used to initiate and stop transactions on the I 2 C-bus. All transactions on

the bus begin with a START condition (S) and end with a STOP condition (P). As shown in Figure 15.3 (p.

294) , a START condition is generated by pulling the SDA line low while SCL is high, and a STOP

condition is generated by pulling the SDA line high while SCL is high.

Figure 15.3. I 2 C START and STOP Conditions

SDA SCL S START condit ion P STOP condit ion The START and STOP conditions are easily identifiable bus events as they are the only conditions on the bus where a transition is allowed on SDA while SCL is high. During the actual data transmission, SDA is only allowed to change while SCL is low, and must be stable while SCL is high. One bit is transferred per clock pulse on the I 2

C-bus as shown in Figure 15.2 (p. 293) .

Figure 15.4. I 2 C Bit Transfer on I 2 C-Bus

SDA SCL Dat a change allowed Dat a st able Dat a change allowed

15.3.1.2 Bus Transfer

When a master wants to initiate a transfer on the bus, it waits until the bus is idle and transmits a START condition on the bus. The master then transmits the address of the slave it wishes to interact with and a single R/W bit telling whether it wishes to read from the slave (R/W bit set to 1) or write to the slave (R/W bit set to 0).

After the 7-bit address and the R/W bit, the master releases the bus, allowing the slave to acknowledge the request. During the next bit-period, the slave pulls SDA low (ACK) if it acknowledges the request, or keeps it high if it does not acknowledge it (NACK).

Following the address acknowledge, either the slave or master transmits data, depending on the value of the R/W bit. After every 8 bits (one byte) transmitted on the SDA line, the transmitter releases the line to allow the receiver to transmit an ACK or a NACK. Both the data and the address are transmitted with the most significant bit first.

The number of bytes in a bus transfer is unrestricted. The master ends the transmission after a (N)ACK by sending a STOP condition on the bus. After a STOP condition, any master wishing to initiate a transfer 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

294

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

on the bus can try to gain control of it. If the current master wishes to make another transfer immediately after the current, it can start a new transfer directly by transmitting a repeated START condition (Sr) instead of a STOP followed by a START.

Examples of I 2

C transfers are shown in Figure 15.5 (p. 295) , Figure 15.6 (p. 295) , and Figure 15.7 (p.

295) . The identifiers used are:

• ADDR - Address • DATA - Data • S - Start bit • Sr - Repeated start bit • P - Stop bit • W/R - Read(1)/Write(0) • A - ACK • N - NACK

Figure 15.5. I 2 C Single Byte Write to Slave

S ADDR W A DATA A P

Figure 15.6. I 2 C Double Byte Read from Slave

S ADDR R A DATA A DATA N P

Figure 15.7. I 2 C Single Byte Write, then Repeated Start and Single Byte Read

S ADDR W A DATA A Sr ADDR R A DATA N P

15.3.1.3 Addresses

I 2 C supports both 7-bit and 10-bit addresses. When using 7-bit addresses, the first byte transmitted after the START-condition contains the address of the slave that the master wants to contact. In the 7-bit

address space, several addresses are reserved. These addresses are summarized in Table 15.1 (p.

295) , and include a General Call address which can be used to broadcast a message to all slaves

on the I 2 C-bus.

Table 15.1. I 2 C Reserved I 2 C Addresses

I 2 C Address R/W Description

0000-000 0000-000 0000-001 0000-010 0000-011 0000-1XX 1111-1XX 1111-0XX 0 1 X X X X X X General Call address START byte Reserved for the C-Bus format Reserved for a different bus format Reserved for future purposes Reserved for future purposes Reserved for future purposes 10 Bit slave addressing mode 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

295

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

15.3.1.4 10-bit Addressing

To address a slave using a 10-bit address, two bytes are required to specify the address instead of one. The seven first bits of the first byte must then be 1111 0XX, where XX are the two most significant bits of the 10-bit address. As with 7-bit addresses, the eight bit of the first byte determines whether the master wishes to read from or write to the slave. The second byte contains the eight least significant bits of the slave address.

When a slave receives a 10-bit address, it must acknowledge both the address bytes if they match the address of the slave.

When performing a master transmitter operation, the master transmits the two address bytes and then

the remaining data, as shown in Figure 15.8 (p. 296) .

Figure 15.8. I 2 C Master Transmitter/Slave Receiver with 10-bit Address

S ADDR (1st 7 bit s) W A Addr (2nd byt e) A DATA A P When performing a master receiver operation however, the master first transmits the two address bytes in a master transmitter operation, then sends a repeated START followed by the first address byte and then receives data from the addressed slave. The slave addressed by the 10-bit address in the first two address bytes must remember that it was addressed, and respond with data if the address transmitted after the repeated start matches its own address. An example of this (with one byte transmitted) is shown

in Figure 15.9 (p. 296) .

Figure 15.9. I 2 C Master Receiver/Slave Transmitter with 10-bit Address

S ADDR (1st 7 bit s) W A Addr (2nd byt e) A Sr ADDR (1st 7 bit s) R A DATA N P

15.3.1.5 Arbitration, Clock Synchronization, Clock Stretching

Arbitration and clock synchronization are features aimed at allowing multi-master buses. Arbitration occurs when two devices try to drive the bus at the same time. If one device drives it low, while the other drives it high, the one attempting to drive it high will not be able to do so due to the open-drain bus configuration. Both devices sample the bus, and the one that was unable to drive the bus in the desired direction detects the collision and backs off, letting the other device continue communication on the bus undisturbed.

Clock synchronization is a means of synchronizing the clock outputs from several masters driving the bus at once, and is a requirement for effective arbitration.

Slaves on the bus are allowed to force the clock output on the bus low in order to pause the communication on the bus and give themselves time to process data or perform any real-time tasks they might have. This is called clock stretching.

Arbitration is supported by the I 2 C module for both masters and slaves. Clock synchronization and clock stretching is also supported.

15.3.2 Enable and Reset

The I 2 C is enabled by setting the EN bit in the I2Cn_CTRL register. Whenever this bit is cleared, the internal state of the I 2 C is reset, terminating any ongoing transfers.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

296

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Note

When enabling the I 2 C, the ABORT command or the Bus Idle Timeout feature must be applied prior to use even if the BUSY flag is not set.

15.3.3 Safely Disabling and Changing Slave Configuration

The I 2 C slave is partially asynchronous, and some precautions are necessary to always ensure a safe slave disable or slave configuration change. These measures should be taken, if (while the slave is enabled) the user cannot guarantee that an address match will not occur at the exact time of slave disable or slave configuration change.

Worst case consequences for an address match while disabling slave or changing configuration is that the slave may end up in an undefined state. To reset the slave back to a known state, the EN bit in I2Cn_CTRL must be reset. This should be done regardless of whether the slave is going to be re-enabled or not.

15.3.4 Clock Generation

The SCL signal generated by the I 2 C master determines the maximum transmission rate on the bus.

The clock is generated as a division of the peripheral clock, and is given by Equation 15.2 (p. 297) :

I 2 C Maximum Transmission Rate

f SCL = 1/(T low + T high ), (15.2) where T low and T high is the low and high periods of the clock signal respectively, given below. When the clock is not streched, the low and high periods of the clock signal are:

I 2 C High and Low Cycles Equations

T high = (N high × (CLKDIV + 1) + 4)/f HFPERCLK , T low = (N low × (CLKDIV + 1) + 4)/f HFPERCLK .

(15.3) The values of N low and N high and thus the ratio between the high and low parts of the clock signal is

controlled by CLHR in the I2Cn_CTRL register. The available modes are summarized in Table 15.2 (p.

298) along with the highest I

2 C-bus frequencies in the given modes that can be achieved without violating the timing specifications of the I 2 C-bus. The maximum data hold time is dependent on the DIV and is given by:

Maximum Data Hold Time

t HD,DAT-max = (5+DIV)/f HFPERCLK .

(15.4)

Note

DIV must be set to 1 or higher during slave mode operation.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

297

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Table 15.2. I 2 C Clock Mode

HFPERCLK frequency (MHz)

24 21 14 11 6.6

1.2

2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2

Clock Low High Ratio (CLHR)

0 1 59 49 46 47 92 78 66 91 76 68 91 74 68 93 80 70

Sm max frequency (kHz)

93 81 400 400 333 400 314 261 400 253

Fm max frequency (kHz)

400 400 400 400 396 355 263 74 70 47 875 538 560 687 647 439 412 388

Fm+ max frequency (kHz)

1000 685 571 874 807 499 263 74 70 47

15.3.5 Arbitration

Arbitration is enabled by default, but can be disabled by setting the ARBDIS bit in I2Cn_CTRL. When arbitration is enabled, the value on SDA is sensed every time the I 2 C module attempts to change its value. If the sensed value is different than the value the I 2 C module tried to output, it is interpreted as a simultaneous transmission by another device, and that the I 2 C module has lost arbitration.

Whenever arbitration is lost, the ARBLOST interrupt flag in I2Cn_IF is set, any lines held are released, and the I 2 C device goes idle. If an I 2 C master loses arbitration during the transmission of an address, another master may be trying to address it. The master therefore receives the rest of the address, and if the address matches the slave address of the master, the master goes into either slave transmitter or slave receiver mode.

Note

Arbitration can be lost both when operating as a master and when operating as a slave.

15.3.6 Buffers 15.3.6.1 Transmit Buffer and Shift Register

The I 2 C transmitter is double buffered through the transmit buffer and transmit shift register as shown in

Figure 15.1 (p. 293) . A byte is loaded into the transmit buffer by writing to I2Cn_TXDATA. When the

transmit shift register is empty and ready for new data, the byte from the transmit buffer is then loaded into the shift register. The byte is then kept in the shift register until it is transmitted. When a byte has been transmitted, a new byte is loaded into the shift register (if available in the transmit buffer). If the transmit buffer is empty, then the shift register also remains empty. The TXC flag in I2Cn_STATUS and 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

298

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

the TXC interrupt flags in I2Cn_IF are then set, signaling that the transmit shift register is out of data. TXC is cleared when new data becomes available, but the TXC interrupt flag must be cleared by software.

Whenever a byte is loaded from the transmit buffer to the transmit shift register, the TXBL flag in I2Cn_STATUS and the TXBL interrupt flag in I2Cn_IF are set. This indicates that there is room in the buffer for more data. TXBL is cleared automatically when data is written to the buffer.

If a write is attempted to the transmit buffer while it is not empty, the TXOF interrupt flag in I2Cn_IF is set, indicating the overflow. The data already in the buffer remains preserved, and no new data is written.

The transmit buffer and the transmit shift register can be cleared by setting command bit CLEARTX in I2Cn_CMD. This will prevent the I 2 C module from transmitting the data in the buffer and the shift register, and will make them available for new data. Any byte currently being transmitted will not be aborted.

Transmission of this byte will be completed.

15.3.6.2 Receive Buffer and Shift Register

Like the transmitter, the I 2 C receiver is double buffered. The receiver uses the receive buffer and receive

shift register as shown in Figure 15.1 (p. 293) . When a byte has been fully received by the receive

shift register, it is loaded into the receive buffer if there is room for it. Otherwise, the byte waits in the shift register until space becomes available in the buffer.

When a byte becomes available in the receive buffer, the RXDATAV in I2Cn_STATUS and RXDATAV interrupt flag in I2Cn_IF are set. The data can now be fetched from the buffer using I2Cn_RXDATA.

Reading from this register will pull a byte out of the buffer, making room for a new byte and clearing RXDATAV in I2Cn_STATUS and RXDATAV in I2Cn_IF in the process.

If a read from the receive buffer is attempted through I2Cn_RXDATA while the buffer is empty, the RXUF interrupt flag in I2Cn_IF is set, and the data read from the buffer is undefined.

I2Cn_RXDATAP can be used to read data from the receive buffer without removing it from the buffer.

The RXUF interrupt flag in I2Cn_IF will never be set as a result of reading from I2Cn_RXDATAP, but the data read through I2Cn_RXDATAP when the receive buffer is empty is still undefined.

Once a transaction is complete (STOP sent or received), the receive buffer needs to be flushed (all received data must be picked up) before starting a new transaction.

15.3.7 Master Operation

A bus transaction is initiated by transmitting a START condition (S) on the bus. This is done by setting the START bit in I2Cn_CMD. The command schedules a START condition, and makes the I 2 C module generate a start condition whenever the bus becomes free.

The I 2 C-bus is considered busy whenever another device on the bus transmits a START condition. Until a STOP condition is detected, the bus is owned by the master issuing the START condition. The bus is considered free when a STOP condition is transmitted on the bus. After a STOP is detected, all masters that have data to transmit send a START condition and begin transmitting data. Arbitration ensures that collisions are avoided.

When the START condition has been transmitted, the master must transmit a slave address (ADDR) with an R/W bit on the bus. If this address is available in the transmit buffer, the master transmits it immediately, but if the buffer is empty, the master holds the I 2 C-bus while waiting for software to write the address to the transmit buffer.

After the address has been transmitted, a sequence of bytes can be read from or written to the slave, depending on the value of the R/W bit (bit 0 in the address byte). If the bit was cleared, the master has entered a master transmitter role, where it now transmits data to the slave. If the bit was set, it has entered a master receiver role, where it now should receive data from the slave. In either case, an unlimited number of bytes can be transferred in one direction during the transmission.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

299

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

At the end of the transmission, the master either transmits a repeated START condition (Sr) if it wishes to continue with another transfer, or transmits a STOP condition (P) if it wishes to release the bus.

15.3.7.1 Master State Machine

The master state machine is shown in Figure 15.10 (p. 300) . A master operation starts in the far

left of the state machine, and follows the solid lines through the state machine, ending the operation or continuing with a new operation when arriving at the right side of the state machine.

Branches in the path through the state machine are the results of bus events and choices made by software, either directly or indirectly. The dotted lines show where I 2 C-specific interrupt flags are set along the path and the full-drawn circles show places where interaction may be required by software to let the transmission proceed.

Figure 15.10. I 2 C Master State Machine

0/ 1 Idle/ busy Wait ing for idle S 57 Mast er t ransm it t er 97 ADDR W A Bus st at e/ event Transm it t ed by self S Sr Received from slave START condit ion P STOP condit ion Repeat ed START condit ion A ACK ADDR W ADDR R N NACK Slave address + writ e (R/ W bit cleared) Slave address + read (R/ W bit set ) Bus st at e (STATE) Int errupt flag set Int eract ion required. Wait st at es insert ed unt il m anual or aut om at ic int eract ion has been perform ed Go t o st at e Mast er receiver ADDR R Arbit rat ion lost ADDR R ADDR W ADDR X N 9F A 93 N 9B DATA DATA Arb. lost , ADDR m at ch Arb. lost , ADDR m at ch Arb. lost , no m at ch B3 A N D7 DF Arb. lost 1 A N 73 71 X P Sr P Sr Arb. lost Slave t ransm it t er Slave receiver 0 57 1 0 57 1 P Bus reset 0

15.3.7.2 Interactions

Whenever the I 2 C module is waiting for interaction from software, it holds the bus clock SCL low, freezing all bus activities, and the BUSHOLD interrupt flag in I2Cn_IF is set. The action(s) required by software depends on the current state the of the I 2 C module. This state can be read from the I2Cn_STATE register.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

300

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

As an example, Table 15.4 (p. 303) shows the different states the I

2 C goes through when operating as a Master Transmitter, i.e. a master that transmits data to a slave. As seen in the table, when a start condition has been transmitted, a requirement is that there is an address and an R/W bit in the transmit buffer. If the transmit buffer is empty, then the BUSHOLD interrupt flag is set, and the bus is held until data becomes available in the buffer. While waiting for the address, I2Cn_STATE has a value 0x57, which can be used to identify exactly what the I 2 C module is waiting for.

Note

The bus would never stop at state 0x57 if the address was available in the transmit buffer.

The different interactions used by the I 2

C module are listed in Table 15.3 (p. 301) in prioritized order. If

a set of different courses of action are possible from a given state, the course of action using the highest priority interactions, that first has everything it is waiting for is the one that is taken.

Table 15.3. I 2 C Interactions in Prioritized Order

Interaction

STOP* ABORT CONT* NACK* ACK* ADDR+W -> TXDATA ADDR+R -> TXDATA START* TXDATA RXDATA None

Priority

1 2 3 4 5 6 7 8 9 10 11

Software action

Set the STOP command bit in I2Cn_CMD

Automatically continues if

PSTOP is set (STOP pending) in I2Cn_STATUS Set the ABORT command bit in I2Cn_CMD Never, the transmission is aborted Set the CONT command bit in I2Cn_CMD Set the NACK command bit in I2Cn_CMD PCONT is set in I2Cn_STATUS (CONT pending) PNACK is set in I2Cn_STATUS (NACK pending) Set the ACK command bit in I2Cn_CMD AUTOACK is set in I2Cn_CTRL or PACK is set in I2Cn_STATUS (ACK pending) Write an address to the transmit buffer with the R/W bit set Write an address to the transmit buffer with the R/W bit cleared Address is available in transmit buffer with R/W bit set Address is available in transmit buffer with R/W bit cleared Set the START command bit in I2Cn_CMD PSTART is set in I2Cn_STATUS (START pending) Write data to the transmit buffer Read data from receive buffer No interaction is required Data is available in transmit buffer Space is available in receive buffer

The commands marked with a * in Table 15.3 (p. 301) can be issued before an interaction is required.

When such a command is issued before it can be used/consumed by the I 2 C module, the command is set in a pending state, which can be read from the STATUS register. A pending START command can for instance be identified by PSTART having a high value.

Whenever the I 2 C module requires an interaction, it checks the pending commands. If one or a combination of these can fulfill an interaction, they are consumed by the module and the transmission continues without setting the BUSHOLD interrupt flag in I2Cn_IF to get an interaction from software.

The pending status of a command goes low when it is consumed.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

301

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

When several interactions are possible from a set of pending commands, the interaction with the highest

priority, i.e. the interaction closest to the top of Table 15.3 (p. 301) is applied to the bus.

Pending commands can be cleared by setting the CLEARPC command bit in I2Cn_CMD.

15.3.7.2.1 Automatic ACK Interaction

When receiving addresses and data, an ACK command in I2Cn_CMD is normally required after each received byte. When AUTOACK is set in I2Cn_CTRL, an ACK is always pending, and the ACK-pending bit PACK in I2Cn_STATUS is thus always set, even after an ACK has been consumed. This can be used to reduce the amount of software interaction required during a transfer.

15.3.7.3 Reset State

After a reset, the state of the I 2 C-bus is unknown. To avoid interrupting transfers on the I 2 C-bus after a reset of the I 2 C module or the entire MCU, the I 2 C-bus is assumed to be busy when coming out of a reset, and the BUSY flag in I2Cn_STATUS is thus set. To be able to carry through master operations on the I 2 C-bus, the bus must be idle.

The bus goes idle when a STOP condition is detected on the bus, but on buses with little activity, the time before the I 2 C module detects that the bus is idle can be significant. There are two ways of assuring that the I 2 C module gets out of the busy state.

• Use the ABORT command in I2Cn_CMD. When the ABORT command is issued, the I 2 C module is instructed that the bus is idle. The I 2 C module can then initiate master operations.

• Use the Bus Idle Timeout. When SCL has been high for a long period of time, it is very likely that the bus is idle. Set BITO in I2Cn_CTRL to an appropriate timeout period and set GIBITO in I2Cn_CTRL.

If activity has not been detected on the bus within the timeout period, the bus is then automatically assumed idle, and master operations can be initiated.

Note

If operating in slave mode, the above approach is not necessary.

15.3.7.4 Master Transmitter

To transmit data to a slave, the master must operate as a master transmitter. Table 15.4 (p. 303)

shows the states the I 2 C module goes through while acting as a master transmitter. Every state where an interaction is required has the possible interactions listed, along with the result of the interactions.

The table also shows which interrupt flags are set in the different states. The interrupt flags enclosed in parenthesis may be set. If the BUSHOLD interrupt in I2Cn_IF is set, the module is waiting for an interaction, and the bus is frozen. The value of I2Cn_STATE will be equal to the values given in the table when the BUSHOLD interrupt flag is set, and can be used to determine which interaction is required to make the transmission continue.

The interrupt flag START in I2Cn_IF is set when the I 2 C module transmits the START.

A master operation is started by issuing a START command by setting START in I2Cn_CMD. ADDR +W, i.e. the address of the slave to address + the R/W bit is then required by the I 2 C module. If this is not available in the transmit buffer, then the bus is held and the BUSHOLD interrupt flag is set. The value of I2Cn_STATE will then be 0x57. As seen in the table, the I 2 C module also stops in this state if the address is not available after a repeated start condition.

To continue, write a byte to I2Cn_TXDATA with the address of the slave in the 7 most significant bits and the least significant bit cleared (ADDR+W). This address will then be transmitted, and the slave will reply with an ACK or a NACK. If no slave replies to the address, the response will also be NACK. If the address was acknowledged, the master now has four choices. It can send a data byte by placing it in I2Cn_TXDATA (the master should check the TXBL interrupt flag before writing to I2Cn_TXDATA), this byte is then transmitted. The master can also stop the transmission by sending a STOP, it can send a repeated start by sending START, or it can send a STOP and then a START as soon as possible.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

302

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

If a NACK was received, the master has to issue a CONT command in addition to providing data in order to continue transmission. This is not standard I 2 C, but is provided for flexibility. The rest of the options are similar to when an ACK was received.

If a new byte was transmitted, an ACK or NACK is received after the transmission of the byte, and the master has the same options as for when the address was sent.

The master may lose arbitration at any time during transmission. In this case, the ARBLOST interrupt flag in I2Cn_IF is set. If the arbitration was lost during the transfer of an address, and SLAVE in I2Cn_CTRL is set, the master then checks which address was transmitted. If it was the address of the master, then the master goes to slave mode.

After a master has transmitted a START and won any arbitration, it owns the bus until it transmits a STOP. After a STOP, the bus is released, and arbitration decides which bus master gains the bus next.

The MSTOP interrupt flag in I2Cn_IF is set when a STOP condition is transmitted by the master.

Table 15.4. I 2 C Master Transmitter

0x57 0x57 Start transmitted Repeated start transmitted

I2Cn_IF

START interrupt flag (BUSHOLD interrupt flag) START interrupt flag (BUSHOLD interrupt flag)

Required interaction Response

ADDR +W -> TXDATA ADDR+W will be sent STOP STOP + START ADDR +W -> TXDATA STOP will be sent and bus released.

STOP will be sent and bus released. Then a START will be sent when bus becomes idle.

ADDR+W will be sent STOP STOP + START None STOP will be sent and bus released.

STOP will be sent and bus released. Then a START will be sent when bus becomes idle.

0x97 ADDR+W transmitted TXBL interrupt flag (TXC interrupt flag) ADDR+W transmitted, ACK received ACK interrupt flag (BUSHOLD interrupt flag) 0x9F ADDR+W transmitted,NACK received NACK (BUSHOLD interrupt flag) TXDATA STOP START STOP + START DATA will be sent STOP will be sent. Bus will be released Repeated start condition will be sent STOP will be sent and the bus released. Then a START will be sent when the bus becomes idle DATA will be sent CONT + TXDATA STOP START STOP + START STOP will be sent. Bus will be released Repeated start condition will be sent STOP will be sent and the bus released. Then a START will be sent when the bus becomes idle None 0xD7 Data transmitted Data transmitted,ACK received TXBL interrupt flag (TXC interrupt flag) ACK interrupt flag (BUSHOLD interrupt flag) TXDATA STOP DATA will be sent STOP will be sent. Bus will be released 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

303

www.silabs.com

0xDF Data transmitted,NACK received Stop transmitted Arbitration lost

Preliminary

...the world's most energy friendly microcontrollers

I2Cn_IF

NACK(BUSHOLD interrupt flag) MSTOP interrupt flag ARBLOST interrupt flag

Required interaction Response

START STOP + START Repeated start condition will be sent STOP will be sent and the bus released. Then a START will be sent when the bus becomes idle DATA will be sent CONT + TXDATA STOP START STOP + START STOP will be sent. Bus will be released Repeated start condition will be sent STOP will be sent and the bus released. Then a START will be sent when the bus becomes idle None START None START START will be sent when bus becomes idle START will be sent when bus becomes idle

15.3.7.5 Master Receiver

To receive data from a slave, the master must operate as a master receiver, see Table 15.5 (p. 305) .

This is done by transmitting ADDR+R as the address byte instead of ADDR+W, which is transmitted to become a master transmitter. The address byte loaded into the data register thus has to contain the 7 bit slave address in the 7 most significant bits of the byte, and have the least significant bit set.

When the address has been transmitted, the master receives an ACK or a NACK. If an ACK is received, the ACK interrupt flag in I2Cn_IF is set, and if space is available in the receive shift register, reception of a byte from the slave begins. If the receive buffer and shift register is full however, the bus is held until data is read from the receive buffer or another interaction is made. Note that the STOP and START interactions have a higher priority than the data-available interaction, so if a STOP or START command is pending, the highest priority interaction will be performed, and data will not be received from the slave.

If a NACK was received, the CONT command in I2Cn_CMD has to be issued in order to continue receiving data, even if there is space available in the receive buffer and/or shift register.

After a data byte has been received the master must ACK or NACK the received byte. If an ACK is pending or AUTOACK in I2Cn_CTRL is set, an ACK is sent automatically and reception continues if space is available in the receive buffer.

If a NACK is sent, the CONT command must be used in order to continue transmission. If an ACK or NACK is issued along with a START or STOP or both, then the ACK/NACK is transmitted and the reception is ended. If START in I2Cn_CMD is set alone, a repeated start condition is transmitted after the ACK/NACK. If STOP in I2Cn_CMD is set, a stop condition is sent regardless of whether START is set. If START is set in this case, it is set as pending.

As when operating as a master transmitter, arbitration can be lost as a master receiver. When this happens the ARBLOST interrupt flag in I2Cn_IF is set, and the master has a possibility of being selected as a slave given the correct conditions.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

304

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Table 15.5. I 2 C Master Receiver

0x57 0x57 0x93 0x9B 0xB3 START transmitted Repeated START transmitted

I2Cn_IF

START interrupt flag (BUSHOLD interrupt flag) START interrupt flag(BUSHOLD interrupt flag)

Required interaction Response

ADDR +R -> TXDATA ADDR+R will be sent STOP STOP + START ADDR +R -> TXDATA STOP will be sent and bus released.

STOP will be sent and bus released. Then a START will be sent when bus becomes idle.

ADDR+R will be sent STOP STOP + START None STOP will be sent and bus released.

STOP will be sent and bus released. Then a START will be sent when bus becomes idle.

ADDR+R transmitted ADDR+R transmitted, ACK received ADDR+R transmitted,NACK received Data received Stop received Arbitration lost TXBL interrupt flag (TXC interrupt flag) ACK interrupt flag(BUSHOLD) NACK(BUSHOLD) RXDATA interrupt flag(BUSHOLD interrupt flag) MSTOP interrupt flag ARBLOST interrupt flag RXDATA STOP START STOP + START Start receiving STOP will be sent and the bus released Repeated START will be sent STOP will be sent and the bus released. Then a START will be sent when the bus becomes idle Continue, start receiving CONT + RXDATA STOP START STOP + START STOP will be sent and the bus released Repeated START will be sent STOP will be sent and the bus released. Then a START will be sent when the bus becomes idle ACK will be transmitted, reception continues ACK + RXDATA NACK + CONT + RXDATA ACK/ NACK + STOP ACK/ NACK + START ACK/ NACK + STOP + START None START None NACK will be transmitted, reception continues ACK/NACK will be sent and the bus will be released.

ACK/NACK will be sent, and then a repeated start condition.

ACK/NACK will be sent and the bus will be released. Then a START will be sent when the bus becomes idle START will be sent when bus becomes idle 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

305

www.silabs.com

Preliminary I2Cn_IF

...the world's most energy friendly microcontrollers

Required interaction Response

START START will be sent when bus becomes idle

15.3.8 Bus States

The I2Cn_STATE register can be used to determine which state the I 2 C module and the I 2 C bus are in at a given time. The register consists of the STATE bit-field, which shows which state the I 2 C module is at in any ongoing transmission, and a set of single-bits, which reveal the transmission mode, whether the bus is busy or idle, and whether the bus is held by this I 2 C module waiting for a software response.

The possible values of the STATE field are summarized in Table 15.6 (p. 306) . When this field is

cleared, the I 2 C module is not a part of any ongoing transmission. The remaining status bits in the

I2Cn_STATE register are listed in Table 15.7 (p. 306) .

Table 15.6. I 2 C STATE Values

Mode

IDLE WAIT START ADDR ADDRACK DATA DATAACK 3 4 5 6 1 2

Value

0

Description

No transmission is being performed by this module.

Waiting for idle. Will send a start condition as soon as the bus is idle.

Start being transmitted Address being transmitted or has been received Address ACK/NACK being transmitted or received Data being transmitted or received Data ACK/NACK being transmitted or received

Table 15.7. I 2 C Transmission Status

Bit

BUSY MASTER TRANSMITTER BUSHOLD NACK

Description

Set whenever there is activity on the bus. Whether or not this module is responsible for the activity cannot be determined by this byte.

Set when operating as a master. Cleared at all other times.

Set when operating as a transmitter; either a master transmitter or a slave transmitter. Cleared at all other times Set when the bus is held by this I 2 C module because an action is required by software.

Only valid when bus is held and STATE is ADDRACK or DATAACK. In that case it is set if a NACK was received. In all other cases, the bit is cleared.

Note

I2Cn_STATE reflects the internal state of the I 2 C module, and therefore only held constant as long as the bus is held, i.e. as long as BUSHOLD in I2Cn_STATUS is set.

15.3.9 Slave Operation

The I 2 C module operates in master mode by default. To enable slave operation, i.e. to allow the device to be addressed as an I 2 C slave, the SLAVE bit in I2Cn_CTRL must be set. In this case the slave operates in a mixed mode, both capable of starting transmissions as a master, and being addressed as a slave.

When operating in the slave mode, HFPERCLK frequency must be higher than 4.2 MHz for Standard mode, 11 MHz for Fast-mode, and 24.4 MHz for Fast-mode Plus.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

306

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

15.3.9.1 Slave State Machine

The slave state machine is shown in Figure 15.11 (p. 307) . The dotted lines show where I

2 C-specific interrupt flags are set. The full-drawn circles show places where interaction may be required by software to let the transmission proceed.

Figure 15.11. I 2 C Slave State Machine

0/ 1 Idle/ busy S Bus st at e/ event Transm it t ed by self Received from m ast er Bus st at e (STATE) Int errupt flag set Int eract ion required. Clock st ret ching applied unt il m anual or aut om at ic int eract ion has been perform ed Go t o st at e Slave t ransm it t er 73 ADDR R A Slave receiver 71 ADDR W N A N DATA A D5 N DD P Sr Arb. lost DATA B1 A P Sr N 0 41 1 0 41 X Arb. lost 1

15.3.9.2 Address Recognition

The I 2 C module provides automatic address recognition for 7-bit addresses. 10-bit address recognition is

not fully automatic, but can be assisted by the 7-bit address comparator as shown in Section 15.3.11 (p.

311) . Address recognition is supported in all energy modes (except EM4).

The slave address, i.e. the address which the I 2 C module should be addressed with, is defined in the I2Cn_SADDR register. In addition to the address, a mask must be specified, telling the address comparator which bits of an incoming address to compare with the address defined in I2Cn_SADDR.

The mask is defined in I2Cn_SADDRMASK, and for every zero in the mask, the corresponding bit in the slave address is treated as a don’t-care.

An incoming address that fails address recognition is automatically replied to with a NACK. Since only the bits defined by the mask are checked, a mask with a value 0x00 will result in all addresses being accepted. A mask with a value 0x7F will only match the exact address defined in I2Cn_SADDR, while a mask 0x70 will match all addresses where the three most significant bits in I2Cn_SADDR and the incoming address are equal.

If GCAMEN in I2Cn_CTRL is set, the general call address is always accepted regardless of the result of the address recognition. The start-byte, i.e. the general call address with the R/W bit set is ignored unless it is included in the defined slave address.

When an address is accepted by the address comparator, the decision of whether to ACK or NACK the address is passed to software.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

307

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

15.3.9.3 Slave Transmitter

When SLAVE in I2Cn_CTRL is set, the RSTART interrupt flag in I2Cn_IF will be set when repeated START conditions are detected. After a START or repeated START condition, the bus master will transmit an address along with an R/W bit. If there is no room in the receive shift register for the address, the bus will be held by the slave until room is available in the shift register. Transmission then continues and the address is loaded into the shift register. If this address does not pass address recognition, it is automatically NACK’ed by the slave, and the slave goes to an idle state. The address byte is in this case discarded, making the shift register ready for a new address. It is not loaded into the receive buffer.

If the address was accepted and the R/W bit was set (R), indicating that the master wishes to read from the slave, the slave now goes into the slave transmitter mode. Software interaction is now required to decide whether the slave wants to acknowledge the request or not. The accepted address byte is loaded into the receive buffer like a regular data byte. If no valid interaction is pending, the bus is held until the slave responds with a command. The slave can reject the request with a single NACK command.

The slave will in that case go to an idle state, and wait for the next start condition. To continue the transmission, the slave must make sure data is loaded into the transmit buffer and send an ACK. The loaded data will then be transmitted to the master, and an ACK or NACK will be received from the master.

Data transmission can also continue after a NACK if a CONT command is issued along with the NACK.

This is not standard I 2 C however.

If the master responds with an ACK, it may expect another byte of data, and data should be made available in the transmit buffer. If data is not available, the bus is held until data is available.

If the response is a NACK however, this is an indication of that the master has received enough bytes and wishes to end the transmission. The slave now automatically goes idle, unless CONT in I2Cn_CMD is set and data is available for transmission. The latter is not standard I 2 C.

The master ends the transmission by sending a STOP or a repeated START. The SSTOP interrupt flag in I2Cn_IF is set when the master transmits a STOP condition. If the transmission is ended with a repeated START, then the SSTOP interrupt flag is not set.

Note

The SSTOP interrupt flag in I2Cn_IF will be set regardless of whether the slave is participating in the transmission or not, as long as SLAVE in I2Cn_CTRL is set and a STOP condition is detected If arbitration is lost at any time during transmission, the ARBLOST interrupt flag in I2Cn_IF is set, the bus is released and the slave goes idle.

See Table 15.8 (p. 309) for more information.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

308

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Table 15.8. I 2 C Slave Transmitter

0x41 0x75 0xD5 0xDD Repeated START received ADDR + R received Arbitration lost

I2Cn_IF

RSTART interrupt flag (BUSHOLD interrupt flag) ADDR interrupt flag

Required interaction Response

RXDATA ACK + TXDATA Receive and compare address ACK will be sent, then DATA RXDATA interrupt flag (BUSHOLD interrupt flag) Data transmitted TXBL interrupt flag (TXC interrupt flag) Data transmitted, ACK received ACK interrupt flag (BUSHOLD interrupt flag) Data transmitted, NACK received Stop received NACK interrupt flag (BUSHOLD interrupt flag) SSTOP interrupt flag ARBLOST interrupt flag NACK NACK + CONT + TXDATA None TXDATA None CONT + TXDATA None START None START NACK will be sent, slave goes idle NACK will be sent, then DATA.

DATA will be transmitted The slave goes idle DATA will be transmitted The slave goes idle START will be sent when bus becomes idle The slave goes idle START will be sent when the bus becomes idle

15.3.9.4 Slave Receiver

A slave receiver operation is started in the same way as a slave transmitter operation, with the exception that the address transmitted by the master has the R/W bit cleared (W), indicating that the master wishes to write to the slave. The slave then goes into slave receiver mode.

To receive data from the master, the slave should respond to the address with an ACK and make sure space is available in the receive buffer. Transmission will then continue, and the slave will receive a byte from the master.

If a NACK is sent without a CONT, the transmission is ended for the slave, and it goes idle. If the slave issues both the NACK and CONT commands and has space available in the receive buffer, it will be open for continuing reception from the master.

When a byte has been received from the master, the slave must ACK or NACK the byte. The responses here are the same as for the reception of the address byte.

The master ends the transmission by sending a STOP or a repeated START. The SSTOP interrupt flag is set when the master transmits a STOP condition. If the transmission is ended with a repeated START, then the SSTOP interrupt flag in I2Cn_IF is not set.

Note

The SSTOP interrupt flag in I2Cn_IF will be set regardless of whether the slave is participating in the transmission or not, as long as SLAVE in I2Cn_CTRL is set and a STOP condition is detected If arbitration is lost at any time during transmission, the ARBLOST interrupt flag in I2Cn_IF is set, the bus is released and the slave goes idle.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

309

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

See Table 15.9 (p. 310) for more information.

Table 15.9. I 2 C - Slave Receiver

0x71 0xB1 Repeated START received ADDR + W received Data received Stop received Arbitration lost

I2Cn_IF

RSTART interrupt flag (BUSHOLD interrupt flag)

Required interaction Response

RXDATA Receive and compare address ADDR interrupt flag RXDATA interrupt flag (BUSHOLD interrupt flag) ACK + RXDATA NACK NACK + CONT + RXDATA ACK will be sent and data will be received NACK will be sent, slave goes idle NACK will be sent and DATA will be received.

ACK will be sent and data will be received RXDATA interrupt flag (BUSHOLD interrupt flag) ACK + RXDATA NACK NACK + CONT + RXDATA SSTOP interrupt flag ARBLOST interrupt flag None START None START NACK will be sent and slave will go idle NACK will be sent and data will be received The slave goes idle START will be sent when bus becomes idle The slave goes idle START will be sent when the bus becomes idle

15.3.10 Transfer Automation

The I 2 C can be set up to complete transfers with a minimal amount of interaction.

15.3.10.1 DMA

DMA can be used to automatically load data into the transmit buffer and load data out from the receive buffer. When using DMA, software is thus relieved of moving data to and from memory after each transferred byte.

15.3.10.2 Automatic ACK

When AUTOACK in I2Cn_CTRL is set, an ACK is sent automatically whenever an ACK interaction is possible and no higher priority interactions are pending.

15.3.10.3 Automatic STOP

A STOP can be generated automatically on two conditions. These apply only to the master transmitter.

If AUTOSN in I2Cn_CTRL is set, the I 2 C module ends a transmission by transmitting a STOP condition when operating as a master transmitter and a NACK is received.

If AUTOSE in I2Cn_CTRL is set, the I 2 C module always ends a transmission when there is no more data in the transmit buffer. If data has been transmitted on the bus, the transmission is ended after the (N)ACK has been received by the slave. If a START is sent when no data is available in the transmit buffer and AUTOSE is set, then the STOP condition is sent immediately following the START. Software must thus make sure data is available in the transmit buffer before the START condition has been fully transmitted if data is to be transferred.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

310

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

15.3.11 Using 10-bit Addresses

When using 10-bit addresses in slave mode, set the I2Cn_SADDR register to 1111 0XX where XX are the two most significant bits of the 10-bit address, and set I2Cn_SADDRMASK to 0xFF. Address matches will now be given on all 10-bit addresses where the two most significant bits are correct.

When receiving an address match, the slave must acknowledge the address and receive the first data byte. This byte contains the second part of the 10-bit address. If it matches the address of the slave, the slave should ACK the byte to continue the transmission, and if it does not match, the slave should NACK it.

When the master is operating as a master transmitter, the data bytes will follow after the second address byte. When the master is operating as a master receiver however, a repeated START condition is sent after the second address byte. The address sent after this repeated START is equal to the first of the address bytes transmitted previously, but now with the R/W byte set, and only the slave that found a match on the entire 10-bit address in the previous message should ACK this address. The repeated start should take the master into a master receiver mode, and after the single address byte sent this time around, the slave begins transmission to the master.

15.3.12 Error Handling 15.3.12.1 ABORT Command

Some bus errors may require software intervention to be resolved. The I 2 C module provides an ABORT command, which can be set in I2Cn_CMD, to help resolve bus errors.

When the bus for some reason is locked up and the I 2 C module is in the middle of a transmission it cannot get out of, or for some other reason the I 2 C wants to abort a transmission, the ABORT command can be used.

Setting the ABORT command will make the I 2 C module discard any data currently being transmitted or received, release the SDA and SCL lines and go to an idle mode. ABORT effectively makes the I 2 C module forget about any ongoing transfers.

15.3.12.2 Bus Reset

A bus reset can be performed by setting the START and STOP commands in I2Cn_CMD while the transmit buffer is empty. A START condition will then be transmitted, immediately followed by a STOP condition. A bus reset can also be performed by transmitting a START command with the transmit buffer empty and AUTOSE set.

15.3.12.3 I 2 C-Bus Errors

An I 2 C-bus error occurs when a START or STOP condition is misplaced, which happens when the value on SDA changes while SCL is high during bit-transmission on the I 2 C-bus. If the I 2 C module is part of the current transmission when a bus error occurs, any data currently being transmitted or received is discarded, SDA and SCL are released, the BUSERR interrupt flag in I2Cn_IF is set to indicate the error,

and the module automatically takes a course of action as defined in Table 15.10 (p. 311) .

Table 15.10. I 2 C Bus Error Response

In a master/slave operation

Misplaced START

Treated as START. Receive address.

Misplaced STOP

Go idle. Perform any pending actions.

15.3.12.4 Bus Lockup

A lockup occurs when a master or slave on the I 2 C-bus has locked the SDA or SCL at a low value, preventing other devices from putting high values on the bus, and thus making communication on the bus impossible.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

311

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Many slave-only devices operating on an I 2 C-bus are not capable of driving SCL low, but in the rare case that SCL is stuck LOW, the advice is to apply a hardware reset signal to the slaves on the bus. If this does not work, cycle the power to the devices in order to make them release SCL.

When SDA is stuck low and SCL is free, a master should send 9 clock pulses on SCL while tristating the SDA. This procedure is performed in the GPIO module after clearing the I2C_ROUTE register and disabling the I2C module. The device that held the bus low should release it sometime within those 9 clocks. If not, use the same approach as for when SCL is stuck, resetting and possibly cycling power to the slaves.

Lockup of SDA can be detected by keeping count of the number of continuous arbitration losses during address transmission. If arbitration is also lost during the transmission of a general call address, i.e.

during the transmission of the STOP condition, which should never happen during normal operation, this is a good indication of SDA lockup.

Detection of SCL lockups can be done using the timeout functionality defined in Section 15.3.12.6 (p.

312)

15.3.12.5 Bus Idle Timeout

When SCL has been high for a significant amount of time, this is a good indication of that the bus is idle. On an SMBus system, the bus is only allowed to be in this state for a maximum of 50 µs before the bus is considered idle.

The bus idle timeout BITO in I2Cn_CTRL can be used to detect situations where the bus goes idle in the middle of a transmission. The timeout can be configured in BITO, and when the bus has been idle for the given amount of time, the BITO interrupt flag in I2Cn_IF is set. The bus can also be set idle automatically on a bus idle timeout. This is enabled by setting GIBITO in I2Cn_CTRL.

When the bus idle timer times out, it wraps around and continues counting as long as its condition is true. If the bus is not set idle using GIBITO or the ABORT command in I2Cn_CMD, this will result in periodic timeouts.

Note

This timeout will be generated even if SDA is held low.

The bus idle timeout is active as long as the bus is busy, i.e. BUSY in I2Cn_STATUS is set. The timeout can be used to get the I 2

C module out of the busy-state it enters when reset, see Section 15.3.7.3 (p.

302) .

15.3.12.6 Clock Low Timeout

The clock timeout, which can be configured in CLTO in I2Cn_CTRL, starts counting whenever SCL goes low, and times out if SCL does not go high within the configured timeout. A clock low timeout results in CLTOIF in I2Cn_IF being set, allowing software to take action.

When the timer times out, it wraps around and continues counting as long as SCL is low. An SCL lockup will thus result in periodic clock low timeouts as long as SCL is low.

15.3.13 DMA Support

The I 2 C module has full DMA support. The DMA controller can write to the transmit buffer using the I2Cn_TXDATA register, and it can read from the receive buffer using the RXDATA register. A request for the DMA controller to read from the I 2 C receive buffer can come from the following source: • Data available in the receive buffer A write request can come from one of the following sources: 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

312

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• Transmit buffer and shift register empty. No data to send • Transmit buffer empty

15.3.14 Interrupts

The interrupts generated by the I 2 C module are combined into one interrupt vector, I2C_INT. If I 2 C interrupts are enabled, an interrupt will be made if one or more of the interrupt flags in I2Cn_IF and their corresponding bits in I2Cn_IEN are set.

15.3.15 Wake-up

The I 2 C receive section can be active all the way down to energy mode EM3, and can wake up the CPU on address interrupt. All address match modes are supported.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

313

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

15.4 Register Map

The offset register address is relative to the registers base address.

Offset

0x000

0x004

0x008 0x00C

0x010 0x014

0x018 0x01C

0x020 0x024 0x028

0x02C

0x030

0x034

0x038

Name

I2Cn_CTRL

I2Cn_CMD

I2Cn_STATE I2Cn_STATUS

I2Cn_CLKDIV I2Cn_SADDR

I2Cn_SADDRMASK I2Cn_RXDATA

I2Cn_RXDATAP I2Cn_TXDATA I2Cn_IF

I2Cn_IFS

I2Cn_IFC

I2Cn_IEN

I2Cn_ROUTE

Type

W1 W1 RW RW RW W1 R R RW R W R RW RW R

Description

Control Register

Command Register

State Register Status Register

Clock Division Register Slave Address Register

Slave Address Mask Register Receive Buffer Data Register

Receive Buffer Data Peek Register Transmit Buffer Data Register Interrupt Flag Register

Interrupt Flag Set Register

Interrupt Flag Clear Register

Interrupt Enable Register

I/O Routing Register

15.5 Register Description 15.5.1 I2Cn_CTRL - Control Register Offset

0x000

Reset Access Bit Position Name Bit

31:19

18:16 15

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CLTO 0x0 RW

Clock Low Timeout

Use to generate a timeout when CLK has been low for the given amount of time. Wraps around and continues counting when the timeout is reached.

Value 0 1 2 3 4 5 GIBITO Mode OFF 40PCC 80PCC 160PCC 320PPC 1024PPC 0 RW Description Timeout disabled Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout.

Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout.

Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout.

Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout.

Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout.

Go Idle on Bus Idle Timeout

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

314

www.silabs.com

7

6

Bit

14

13:12

11:10

9:8 5 4 3 2

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

When set, the bus automatically goes idle on a bus idle timeout, allowing new transfers to be initiated.

Value 0 1 Description A bus idle timeout has no effect on the bus state.

A bus idle timeout tells the I 2 C module that the bus is idle, allowing new transfers to be initiated.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BITO 0x0 RW

Bus Idle Timeout

Use to generate a timeout when SCL has been high for a given amount time between a START and STOP condition. When in a bus transaction, i.e. the BUSY flag is set, a timer is started whenever SCL goes high. When the timer reaches the value defined by BITO, it sets the BITO interrupt flag. The BITO interrupt flag will then be set periodically as long as SCL remains high. The bus idle timeout is active as long as BUSY is set. It is thus stopped automatically on a timeout if GIBITO is set. It is also stopped a STOP condition is detected and when the ABORT command is issued. The timeout is activated whenever the bus goes BUSY, i.e.

a START condition is detected.

Value 0 1 2 3 Mode OFF 40PCC 80PCC 160PCC Description Timeout disabled Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout.

Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout.

Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CLHR 0x0 RW

Clock Low High Ratio

Determines the ratio between the low and high parts of the clock signal generated on SCL as master.

Value 0 1 2 Mode STANDARD ASYMMETRIC FAST Description The ratio between low period and high period counters (N low :N high ) is 4:4 The ratio between low period and high period counters (N low :N high ) is 6:3 The ratio between low period and high period counters (N low :N high ) is 11:6

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

GCAMEN 0 RW

General Call Address Match Enable

Set to enable address match on general call in addition to the programmed slave address.

Value 0 1 Value 0 1 Description General call address will be NACK'ed if it is not included by the slave address and address mask.

When a general call address is received, a software response is required.

ARBDIS 0 RW

Arbitration Disable

A master or slave will not release the bus upon losing arbitration.

Description When a device loses arbitration, the ARB interrupt flag is set and the bus is released.

When a device loses arbitration, the ARB interrupt flag is set, but communication proceeds.

AUTOSN 0 RW

Automatic STOP on NACK

Write to 1 to make a master transmitter send a STOP when a NACK is received from a slave.

Value 0 1 Description Stop is not automatically sent if a NACK is received from a slave.

The master automatically sends a STOP if a NACK is received from a slave.

AUTOSE 0 RW

Automatic STOP when Empty

Write to 1 to make a master transmitter send a STOP when no more data is available for transmission.

Value 0 1 AUTOACK Description A stop must be sent manually when no more data is to be transmitted.

The master automatically sends a STOP when no more data is available for transmission.

0 Set to enable automatic acknowledges.

RW

Automatic Acknowledge

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

315

www.silabs.com

1 0

Bit Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Value 0 1 Description Software must give one ACK command for each ACK transmitted on the I 2 C bus.

Addresses that are not automatically NACK'ed, and all data is automatically acknowledged.

SLAVE 0 RW Set this bit to allow the device to be selected as an I 2 C slave.

Addressable as Slave

Value 0 1 EN Description All addresses will be responded to with a NACK Addresses matching the programmed slave address or the general call address (if enabled) require a response from software. Other addresses are automatically responded to with a NACK.

0 Use this bit to enable or disable the I 2 C module.

RW

I 2 C Enable

Value 0 1 Description The I 2 C module is disabled. And its internal state is cleared The I 2 C module is enabled.

15.5.2 I2Cn_CMD - Command Register Offset

0x004

Reset Access Bit Position Name

1 0 4 3 2

Bit

31:8

7 6 5

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CLEARPC 0 Set to clear pending commands.

W1

Clear Pending Commands

CLEARTX 0 W1

Clear TX

Set to clear transmit buffer and shift register. Will not abort ongoing transfer.

ABORT 0 W1

Abort transmission

Abort the current transmission making the bus go idle. When used in combination with STOP, a STOP condition is sent as soon as possible before aborting the transmission. The stop condition is subject to clock synchronization.

CONT 0 W1 Set to continue transmission after a NACK has been received.

Continue transmission

NACK 0 W1

Send NACK

Set to transmit a NACK the next time an acknowledge is required.

ACK 0 W1

Send ACK

Set to transmit an ACK the next time an acknowledge is required.

STOP 0 Set to send stop condition as soon as possible.

W1

Send stop condition

START 0 W1

Send start condition

Set to send start condition as soon as possible. If a transmission is ongoing and not owned, the start condition will be sent as soon as the bus is idle. If the current transmission is owned by this module, a repeated start condition will be sent. Use in combination with a STOP command to automatically send a STOP, then a START when the bus becomes idle.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

316

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

15.5.3 I2Cn_STATE - State Register Offset

0x008

Reset Access Bit Position Name

4 3 2 1 0

Bit

31:8

7:5

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

STATE 0x0 R

Transmission State

The state of any current transmission. Cleared if the I 2 C module is idle.

2 3 4 Value 0 1 5 6 Mode IDLE WAIT START ADDR ADDRACK DATA DATAACK Description No transmission is being performed.

Waiting for idle. Will send a start condition as soon as the bus is idle.

Start transmitted or received Address transmitted or received Address ack/nack transmitted or received Data transmitted or received Data ack/nack transmitted or received BUSHOLD 0 R Set if the bus is currently being held by this I 2 C module.

Bus Held

NACKED 0 R

Nack Received

Set if a NACK was received and STATE is ADDRACK or DATAACK.

TRANSMITTER 0 R

Transmitter

Set when operating as a master transmitter or a slave transmitter. When cleared, the system may be operating as a master receiver, a slave receiver or the current mode is not known.

MASTER 0 R

Master

Set when operating as an I 2 C master. When cleared, the system may be operating as an I 2 C slave.

BUSY 1 R

Bus Busy

Set when the bus is busy. Whether the I 2 C module is in control of the bus or not has no effect on the value of this bit. When the MCU comes out of reset, the state of the bus is not known, and thus BUSY is set. Use the ABORT command or a bus idle timeout to force the I 2 C module out of the BUSY state.

15.5.4 I2Cn_STATUS - Status Register Offset

0x00C

Reset Access Bit Position Name Bit

31:9

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

317

www.silabs.com

6 5 4 3 2 1 0

Bit

8 7

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

RXDATAV 0 R

RX Data Valid

Set when data is available in the receive buffer. Cleared when the receive buffer is empty.

TXBL 1 R

TX Buffer Level

Indicates the level of the transmit buffer. Set when the transmit buffer is empty, and cleared when it is full.

TXC 0 R

TX Complete

Set when a transmission has completed and no more data is available in the transmit buffer. Cleared when a new transmission starts.

PABORT 0 R

Pending abort

An abort is pending and will be transmitted as soon as possible.

PCONT 0 R

Pending continue

A continue is pending and will be transmitted as soon as possible.

PNACK 0 R

Pending NACK

A not-acknowledge is pending and will be transmitted as soon as possible.

PACK 0 R

Pending ACK

An acknowledge is pending and will be transmitted as soon as possible.

PSTOP 0 R

Pending STOP

A stop condition is pending and will be transmitted as soon as possible.

PSTART 0 R

Pending START

A start condition is pending and will be transmitted as soon as possible.

15.5.5 I2Cn_CLKDIV - Clock Division Register Offset

0x010

Bit Position Reset Access Name Bit

31:9

8:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DIV 0x000 RW

Clock Divider

Specifies the clock divider for the I 2 C. Note that DIV must be 1 or higher when slave is enabled.

15.5.6 I2Cn_SADDR - Slave Address Register Offset

0x014

Bit Position Reset Access Name

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

318

www.silabs.com

Bit

31:8

7:1

0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

ADDR 0x00 Specifies the slave address of the device.

Reserved

RW

Slave address

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

15.5.7 I2Cn_SADDRMASK - Slave Address Mask Register Bit Position Offset

0x018

Reset Access Name Bit

31:8

7:1

0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

MASK 0x00 RW

Slave Address Mask

Specifies the significant bits of the slave address. Setting the mask to 0x00 will match all addresses, while setting it to 0x7F will only match the exact address specified by ADDR.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

15.5.8 I2Cn_RXDATA - Receive Buffer Data Register Bit Position Offset

0x01C

Reset Access Name Bit

31:8

7:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXDATA 0x00 R

RX Data

Use this register to read from the receive buffer. Buffer is emptied on read access.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

319

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

15.5.9 I2Cn_RXDATAP - Receive Buffer Data Peek Register Offset

0x020

Bit Position Reset Access Name Bit

31:8

7:0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXDATAP 0x00 R

RX Data Peek

Use this register to read from the receive buffer. Buffer is not emptied on read access.

15.5.10 I2Cn_TXDATA - Transmit Buffer Data Register Offset

0x024

Bit Position Reset Access Name Bit

31:8

7:0

Name Reset Access Description

Reserved

TXDATA

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x00 W Use this register to write a byte to the transmit buffer.

TX Data 15.5.11 I2Cn_IF - Interrupt Flag Register Offset

0x028

Reset Access Bit Position Name Bit

31:17

16 15

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SSTOP 0 R

Slave STOP condition Interrupt Flag

Set when a STOP condition has been received. Will be set regardless of the EFM32 being involved in the transaction or not.

CLTO 0 R

Clock Low Timeout Interrupt Flag

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

320

www.silabs.com

7 6 5 4 3 2 1 0

Bit

9 8 14 13 12 11 10

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Set on each clock low timeout. The timeout value can be set in CLTO bit field in the I2Cn_CTRL register.

BITO 0 R

Bus Idle Timeout Interrupt Flag

Set on each bus idle timeout. The timeout value can be set in the BITO bit field in the I2Cn_CTRL register.

RXUF 0 R

Receive Buffer Underflow Interrupt Flag

Set when data is read from the receive buffer through the I2Cn_RXDATA register while the receive buffer is empty.

TXOF 0 R

Transmit Buffer Overflow Interrupt Flag

Set when data is written to the transmit buffer while the transmit buffer is full.

BUSHOLD 0 R Set when the bus becomes held by the I 2 C module.

Bus Held Interrupt Flag

BUSERR 0 R

Bus Error Interrupt Flag

Set when a bus error is detected. The bus error is resolved automatically, but the current transfer is aborted.

ARBLOST Set when arbitration is lost.

0 MSTOP 0 R

Master STOP Condition Interrupt Flag

Set when a STOP condition has been successfully transmitted. If arbitration is lost during the transmission of the STOP condition, then the MSTOP interrupt flag is not set.

NACK 0 Set when a NACK has been received.

R R

Arbitration Lost Interrupt Flag Not Acknowledge Received Interrupt Flag

ACK 0 Set when an ACK has been received.

R

Acknowledge Received Interrupt Flag

RXDATAV 0 R

Receive Data Valid Interrupt Flag

Set when data is available in the receive buffer. Cleared automatically when the receive buffer is read.

TXBL 1 R

Transmit Buffer Level Interrupt Flag

Set when the transmit buffer becomes empty. Cleared automatically when new data is written to the transmit buffer.

TXC 0 R

Transfer Completed Interrupt Flag

Set when the transmit shift register becomes empty and there is no more data in the transmit buffer.

ADDR 0 R

Address Interrupt Flag

Set when incoming address is accepted, i.e. own address or general call address is received.

RSTART 0 Set when a repeated start condition is detected.

R

Repeated START condition Interrupt Flag

START 0 R Set when a start condition is successfully transmitted.

START condition Interrupt Flag 15.5.12 I2Cn_IFS - Interrupt Flag Set Register Offset

0x02C

Reset Access Bit Position Name Bit

31:17

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

321

www.silabs.com

1 0 7 6

5:4

3 2 14 13 12 11 10 9 8

Bit

16 15

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

SSTOP 0 Write to 1 to set the SSTOP interrupt flag.

CLTO 0 Write to 1 to set the CLTO interrupt flag.

BITO 0 Write to 1 to set the BITO interrupt flag.

RXUF 0 Write to 1 to set the RXUF interrupt flag.

TXOF 0 Write to 1 to set the TXOF interrupt flag.

W1 W1 W1 W1 W1 BUSHOLD 0 Write to 1 to set the BUSHOLD interrupt flag.

BUSERR 0 Write to 1 to set the BUSERR interrupt flag.

W1 W1 W1 ARBLOST 0 Write to 1 to set the ARBLOST interrupt flag.

MSTOP 0 Write to 1 to set the MSTOP interrupt flag.

W1

Set SSTOP Interrupt Flag Set Clock Low Interrupt Flag Set Bus Idle Timeout Interrupt Flag Set Receive Buffer Underflow Interrupt Flag Set Transmit Buffer Overflow Interrupt Flag Set Bus Held Interrupt Flag Set Bus Error Interrupt Flag Set Arbitration Lost Interrupt Flag Set MSTOP Interrupt Flag

NACK 0 Write to 1 to set the NACK interrupt flag.

ACK 0 Write to 1 to set the ACK interrupt flag.

Reserved

W1 W1

Set Not Acknowledge Received Interrupt Flag Set Acknowledge Received Interrupt Flag

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXC 0 Write to 1 to set the TXC interrupt flag.

ADDR 0 Write to 1 to set the ADDR interrupt flag.

RSTART 0 Write to 1 to set the RSTART interrupt flag.

START 0 Write to 1 to set the START interrupt flag.

W1 W1 W1 W1

Set Transfer Completed Interrupt Flag Set Address Interrupt Flag Set Repeated START Interrupt Flag Set START Interrupt Flag 15.5.13 I2Cn_IFC - Interrupt Flag Clear Register Offset

0x030

Reset Access Bit Position Name Bit

31:17

16

Name

Reserved

SSTOP

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 W1

Clear SSTOP Interrupt Flag

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

322

www.silabs.com

Bit

2 1 0 15 14 13 12 11 6

5:4

3 8 7 10 9

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Write to 1 to clear the SSTOP interrupt flag.

CLTO 0 Write to 1 to clear the CLTO interrupt flag.

BITO 0 Write to 1 to clear the BITO interrupt flag.

RXUF 0 Write to 1 to clear the RXUF interrupt flag.

W1 W1 W1 TXOF 0 Write to 1 to clear the TXOF interrupt flag.

W1 BUSHOLD 0 Write to 1 to clear the BUSHOLD interrupt flag.

W1

Clear Clock Low Interrupt Flag Clear Bus Idle Timeout Interrupt Flag Clear Receive Buffer Underflow Interrupt Flag Clear Transmit Buffer Overflow Interrupt Flag Clear Bus Held Interrupt Flag

BUSERR 0 Write to 1 to clear the BUSERR interrupt flag.

W1 ARBLOST 0 Write to 1 to clear the ARBLOST interrupt flag.

W1

Clear Bus Error Interrupt Flag Clear Arbitration Lost Interrupt Flag

MSTOP 0 Write to 1 to clear the MSTOP interrupt flag.

NACK 0 Write to 1 to clear the NACK interrupt flag.

W1 W1

Clear MSTOP Interrupt Flag Clear Not Acknowledge Received Interrupt Flag

ACK 0 Write to 1 to clear the ACK interrupt flag.

Reserved

W1

Clear Acknowledge Received Interrupt Flag

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

Clear Transfer Completed Interrupt Flag

TXC 0 Write to 1 to clear the TXC interrupt flag.

ADDR 0 Write to 1 to clear the ADDR interrupt flag.

W1 W1 RSTART 0 Write to 1 to clear the RSTART interrupt flag.

W1 START 0 Write to 1 to clear the START interrupt flag.

W1

Clear Address Interrupt Flag Clear Repeated START Interrupt Flag Clear START Interrupt Flag 15.5.14 I2Cn_IEN - Interrupt Enable Register Offset

0x034

Reset Access Bit Position Name Bit

31:17

16

Name Reset Access Description

Reserved

SSTOP Enable interrupt on SSTOP.

0

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RW

SSTOP Interrupt Enable

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

323

www.silabs.com

13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

15 14

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

CLTO 0 Enable interrupt on clock low timeout.

BITO 0 Enable interrupt on bus idle timeout.

RXUF 0 Enable interrupt on receive buffer underflow.

TXOF 0 Enable interrupt on transmit buffer overflow.

BUSHOLD Enable interrupt on bus-held.

0 RW RW RW RW RW BUSERR Enable interrupt on bus error.

0 ARBLOST 0 Enable interrupt on loss of arbitration.

RW RW MSTOP Enable interrupt on MSTOP.

0 RW NACK 0 RW Enable interrupt when not-acknowledge is received.

Clock Low Interrupt Enable Bus Idle Timeout Interrupt Enable Receive Buffer Underflow Interrupt Enable Transmit Buffer Overflow Interrupt Enable Bus Held Interrupt Enable Bus Error Interrupt Enable Arbitration Lost Interrupt Enable MSTOP Interrupt Enable Not Acknowledge Received Interrupt Enable

ACK 0 Enable interrupt on acknowledge received.

RXDATAV 0 Enable interrupt on receive buffer full.

TXBL 0 Enable interrupt on transmit buffer level.

TXC 0 Enable interrupt on transfer completed.

ADDR 0 Enable interrupt on recognized address.

RW RW RW RW RW

Acknowledge Received Interrupt Enable Receive Data Valid Interrupt Enable Transmit Buffer level Interrupt Enable Transfer Completed Interrupt Enable Address Interrupt Enable

RSTART 0 RW

Repeated START condition Interrupt Enable

Enable interrupt on transmitted or received repeated START condition.

START 0 RW Enable interrupt on transmitted or received START condition.

START Condition Interrupt Enable 15.5.15 I2Cn_ROUTE - I/O Routing Register Offset

0x038

Reset Access Bit Position Name Bit

31:11

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

324

www.silabs.com

7:2

1 0

Bit

10:8

Preliminary

...the world's most energy friendly microcontrollers

Name Reset

LOCATION 0x0 Decides the location of the I 2 C I/O pins.

Access

RW

Description I/O Location

4 5 6 Value 0 1 2 3 Mode LOC0 LOC1 LOC2 LOC3 LOC4 LOC5 LOC6 Description Location 0 Location 1 Location 2 Location 3 Location 4 Location 5 Location 6

Reserved

SCLPEN

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 When set, the SCL pin of the I 2 C is enabled.

SDAPEN 0 When set, the SDA pin of the I 2 C is enabled.

RW RW

SCL Pin Enable SDA Pin Enable

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

325

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

16 USART - Universal Synchronous Asynchronous Receiver/Transmitter

0 1 2 3 4

DMA cont roller

EFM32

RAM USART RX/ MISO TX/ MOSI CLK CS IrDA Sm art Cards USART SPI

Quick Facts What?

The USART handles high-speed UART, SPI bus, SmartCards, and IrDA communication.

Why?

Serial communication is frequently used in embedded systems and the USART allows efficient communication with a wide range of external devices.

How?

The USART has a wide selection of operating modes, frame formats and baud rates. The multi-processor mode allows the USART to remain idle when not addressed. Triple buffering and DMA support makes high data rates possible with minimal CPU intervention and it is possible to transmit and receive large frames while the MCU remains in EM1.

16.1 Introduction

The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, and IrDA devices.

16.2 Features

• Asynchronous and synchronous (SPI) communication • Full duplex and half duplex • Separate TX/RX enable • Separate receive / transmit 2-level buffers, with additional separate shift registers • Programmable baud rate, generated as an fractional division from the peripheral clock (HFPERCLK USARTn ) • Max bit-rate • SPI master mode, peripheral clock rate/2 • SPI slave mode, peripheral clock rate/8 • UART mode, peripheral clock rate/16, 8, 6, or 4 • Asynchronous mode supports • Majority vote baud-reception • False start-bit detection • Break generation/detection • Multi-processor mode • Synchronous mode supports • All 4 SPI clock polarity/phase configurations • Master and slave mode • Data can be transmitted LSB first or MSB first • Configurable number of data bits, 4-16 (plus the parity bit, if enabled) 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

326

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• HW parity bit generation and check • Configurable number of stop bits in asynchronous mode: 0.5, 1, 1.5, 2 • HW collision detection • Multi-processor mode • IrDA modulator on USART0USART1 • SmartCard (ISO7816) mode • I2S mode • Separate interrupt vectors for receive and transmit interrupts • Loopback mode • Half duplex communication • Communication debugging • PRS RX input

16.3 Functional Description

An overview of the USART module is shown in Figure 16.1 (p. 327) .

Figure 16.1. USART Overview

Peripheral Bus USn_CS U(S)n_TX USn_CLK Pin ct rl UART Cont rol and st at us IrDA m odulat or TX Buffer (2- level FIFO) TX Shift Regist er RX Buffer (2- level FIFO) !RXBLOCK

RX Shift Regist er Baud rat e generat or U(S)n_RX PRS input s IrDA dem odulat or

16.3.1 Modes of Operation

The USART operates in either asynchronous or synchronous mode.

In synchronous mode, a separate clock signal is transmitted with the data. This clock signal is generated by the bus master, and both the master and slave sample and transmit data according to this clock.

Both master and slave modes are supported by the USART. The synchronous communication mode is compatible with the Serial Peripheral Interface Bus (SPI) standard.

In asynchronous mode, no separate clock signal is transmitted with the data on the bus. The USART receiver thus has to determine where to sample the data on the bus from the actual data. To make this possible, additional synchronization bits are added to the data when operating in asynchronous mode, resulting in a slight overhead.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

327

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

Asynchronous or synchronous mode can be selected by configuring SYNC in USARTn_CTRL. The

options are listed with supported protocols in Table 16.1 (p. 328) . Full duplex and half duplex

communication is supported in both asynchronous and synchronous mode.

Table 16.1. USART Asynchronous vs. Synchronous Mode

SYNC

0 1

Communication Mode

Asynchronous Synchronous

Supported Protocols

RS-232, RS-485 (w/external driver), IrDA, ISO 7816 SPI, MicroWire, 3-wire 1 1 0 1 1 1

Table 16.2 (p. 328) explains the functionality of the different USART pins when the USART operates

in different modes. Pin functionality enclosed in square brackets is optional, and depends on additional

configuration parameters. LOOPBK and MASTER are discussed in Section 16.3.2.5 (p. 336) and

Section 16.3.3.3 (p. 344) respectively.

Table 16.2. USART Pin Usage

SYNC LOOPBK MASTER Pin functionality U(S)n_RX (MISO) USn_CLK USn_CS

1 1 0 1 0 0 0 1 x x 0 1

U(S)n_TX (MOSI)

Data out Data out/in Data in Data out Data out/in Data out/in Data in Data out Data in Clock in Clock out Clock in Clock out [Driver enable] [Driver enable] Slave select [Auto slave select] Slave select [Auto slave select]

16.3.2 Asynchronous Operation 16.3.2.1 Frame Format

The frame format used in asynchronous mode consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking. A frame starts with one start-bit (S), where the line is driven low for one bit-period. This signals the start of a frame, and is used for synchronization.

Following the start bit are 4 to 16 data bits and an optional parity bit. Finally, a number of stop-bits, where

the line is driven high, end the frame. An example frame is shown in Figure 16.2 (p. 328) .

Figure 16.2. USART Asynchronous Frame Format

Fram e St op or idle S 0 1 2 3 4 [5] [6] [7] [8] [P] St op St art or idle

The number of data bits in a frame is set by DATABITS in USARTn_FRAME, see Table 16.3 (p. 329) , and the number of stop-bits is set by STOPBITS in USARTn_FRAME, see Table 16.4 (p. 329) .

Whether or not a parity bit should be included, and whether it should be even or odd is defined by PARITY, also in USARTn_FRAME. For communication to be possible, all parties of an asynchronous transfer must agree on the frame format being used.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

328

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Table 16.3. USART Data Bits

1000 1001 1010 1011 1100 1101

DATA BITS [3:0]

0001 0010 0011 0100 0101 0110 0111

Table 16.4. USART Stop Bits

STOP BITS [1:0]

00 01 10 11 11 12 13 14 15 16 5 6

Number of Data bits

4 7 8 (Default) 9 10

Number of Stop bits

0.5

1 (Default) 1.5

2 The order in which the data bits are transmitted and received is defined by MSBF in USARTn_CTRL.

When MSBF is cleared, data in a frame is sent and received with the least significant bit first. When it is set, the most significant bit comes first.

The frame format used by the transmitter can be inverted by setting TXINV in USARTn_CTRL, and the format expected by the receiver can be inverted by setting RXINV in USARTn_CTRL. These bits affect the entire frame, not only the data bits. An inverted frame has a low idle state, a high start-bit, inverted data and parity bits, and low stop-bits.

16.3.2.1.1 Parity bit Calculation and Handling

When parity bits are enabled, hardware automatically calculates and inserts any parity bits into outgoing frames, and verifies the received parity bits in incoming frames. This is true for both asynchronous and synchronous modes, even though it is mostly used in asynchronous communication. The possible parity

modes are defined in Table 16.5 (p. 330) . When even parity is chosen, a parity bit is inserted to make

the number of high bits (data + parity) even. If odd parity is chosen, the parity bit makes the total number of high bits odd.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

329

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Table 16.5. USART Parity Bits

STOP BITS [1:0]

00 01 10 11

Description

No parity bit (Default) Reserved Even parity Odd parity

16.3.2.2 Clock Generation

The USART clock defines the transmission and reception data rate. When operating in asynchronous

mode, the baud rate (bit-rate) is given by Equation 16.1 (p. 330)

USART Baud Rate

br = f HFPERCLK /(oversample x (1 + USARTn_CLKDIV/256)) (16.1) where f HFPERCLK is the peripheral clock (HFPERCLK USARTn ) frequency and oversample is the

oversampling rate as defined by OVS in USARTn_CTRL, see Table 16.6 (p. 330) .

Table 16.6. USART Oversampling

OVS [1:0]

00 01 10 11 8 6 4

oversample

16 The USART has a fractional clock divider to allow the USART clock to be controlled more accurately than what is possible with a standard integral divider.

The clock divider used in the USART is a 15-bit value, with a 13-bit integral part and a 2-bit fractional part. The fractional part is configured in the two LSBs of DIV in USART_CLKDIV. The lowest achievable baud rate at 32 MHz is about 244 bauds/sec.

Fractional clock division is implemented by distributing the selected fraction over four baud periods. The fractional part of the divider tells how many of these periods should be extended by one peripheral clock cycle.

Given a desired baud rate br desired , the clock divider USARTn_CLKDIV can be calculated by using

Equation 16.2 (p. 330) :

USART Desired Baud Rate

USARTn_CLKDIV = 256 x (f HFPERCLK /(oversample x br desired ) - 1) (16.2)

Table 16.7 (p. 331) shows a set of desired baud rates and how accurately the USART is able to

generate these baud rates when running at a 4 MHz peripheral clock, using 16x or 8x oversampling.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

330

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Table 16.7. USART Baud Rates @ 4MHz Peripheral Clock

Desired baud rate [baud/s] USARTn_OVS =00 USARTn_CLKDIV/256 Actual baud rate [baud/s]

600 1200 415,75 207,25 599,88 1200,48 2400 4800 9600 14400 103,25 51 25 16,25 2398,082 4807,692 9615,385 14492,75 19200 28800 38400 57600 76800 115200 230400 12 7,75 5,5 3,25 2,25 1,25 0 19230,77 28571,43 38461,54 58823,53 76923,08 111111,1 250000 -0,02 0,04 -0,08 0,16 0,16 0,64 0,16 -0,79 0,16 2,12 0,16 -3,55 8,51

Error %

51 33,75 25 16,25 12 7,75 5,5 3,25 1,25

USARTn_OVS =01 USARTn_CLKDIV/256 Actual baud rate [baud/s]

832,25 415,75 207,25 103,25 600,06 1199,76 2400,96 4796,163 9615,385 14388,49 19230,77 28985,51 38461,54 57142,86 76923,08 117647,1 222222,2

Error %

0,01 -0,02 0,04 -0,08 0,16 -0,08 0,16 0,64 0,16 -0,79 0,16 2,12 -3,55

16.3.2.3 Data Transmission

Asynchronous data transmission is initiated by writing data to the transmit buffer using one of the

methods described in Section 16.3.2.3.1 (p. 331) . When the transmission shift register is empty and

ready for new data, a frame from the transmit buffer is loaded into the shift register, and if the transmitter is enabled, transmission begins. When the frame has been transmitted, a new frame is loaded into the shift register if available, and transmission continues. If the transmit buffer is empty, the transmitter goes to an idle state, waiting for a new frame to become available.

Transmission is enabled through the command register USARTn_CMD by setting TXEN, and disabled by setting TXDIS in the same command register. When the transmitter is disabled using TXDIS, any ongoing transmission is aborted, and any frame currently being transmitted is discarded. When disabled, the TX output goes to an idle state, which by default is a high value. Whether or not the transmitter is enabled at a given time can be read from TXENS in USARTn_STATUS.

When the USART transmitter is enabled and there is no data in the transmit shift register or transmit buffer, the TXC flag in USARTn_STATUS and the TXC interrupt flag in USARTn_IF are set, signaling that the transmitter is idle. The TXC status flag is cleared when a new frame becomes available for transmission, but the TXC interrupt flag must be cleared by software.

16.3.2.3.1 Transmit Buffer Operation

The transmit-buffer is a 2-level FIFO buffer. A frame can be loaded into the buffer by writing to USARTn_TXDATA, USARTn_TXDATAX, USARTn_TXDOUBLE or USARTn_TXDOUBLEX. Using USARTn_TXDATA allows 8 bits to be written to the buffer, while using USARTn_TXDOUBLE will write 2 frames of 8 bits to the buffer. If 9-bit frames are used, the 9th bit of the frames will in these cases be set to the value of BIT8DV in USARTn_CTRL.

To set the 9th bit directly and/or use transmission control, USARTn_TXDATAX and USARTn_TXDOUBLEX must be used. USARTn_TXDATAX allows 9 data bits to be written, as well as a set of control bits regarding the transmission of the written frame. Every frame in the buffer is stored with 9 data bits and additional transmission control bits. USARTn_TXDOUBLEX allows two 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

331

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

frames, complete with control bits to be written at once. When data is written to the transmit buffer using USARTn_TXDATAX and USARTn_TXDOUBLEX, the 9th bit(s) written to these registers override the value in BIT8DV in USARTn_CTRL, and alone define the 9th bits that are transmitted if 9-bit

frames are used. Figure 16.3 (p. 332) shows the basics of the transmit buffer when DATABITS in

USARTn_FRAME is configured to less than 10 bits.

Figure 16.3. USART Transmit Buffer Operation

Peripheral Bus TXDOUBLE, TXDOUBLEX TX buffer elem ent 1 Writ e CTRL TXDATA, TXDATAX Writ e CTRL TX buffer elem ent 0 Shift regist er Writ e CTRL When writing more frames to the transmit buffer than there is free space for, the TXOF interrupt flag in USARTn_IF will be set, indicating the overflow. The data already in the transmit buffer is preserved in this case, and no data is written.

In addition to the interrupt flag TXC in USARTn_IF and status flag TXC in USARTn_STATUS which are set when the transmitter is idle, TXBL in USARTn_STATUS and the TXBL interrupt flag in USARTn_IF are used to indicate the level of the transmit buffer. TXBIL in USARTn_CTRL controls the level at which these bits are set. If TXBIL is cleared, they are set whenever the transmit buffer becomes empty, and if TXBIL is set, they are set whenever the transmit buffer goes from full to half-full or empty. Both the TXBL status flag and the TXBL interrupt flag are cleared automatically when their condition becomes false The transmit buffer, including the transmit shift register can be cleared by setting CLEARTX in USARTn_CMD. This will prevent the USART from transmitting the data in the buffer and shift register, and will make them available for new data. Any frame currently being transmitted will not be aborted.

Transmission of this frame will be completed.

16.3.2.3.2 Frame Transmission Control

The transmission control bits, which can be written using USARTn_TXDATAX and USARTn_TXDOUBLEX, affect the transmission of the written frame. The following options are available: • Generate break: By setting TXBREAK, the output will be held low during the stop-bit period to generate a framing error. A receiver that supports break detection detects this state, allowing it to be used e.g.

for framing of larger data packets. The line is driven high before the next frame is transmitted so the next start condition can be identified correctly by the recipient. Continuous breaks lasting longer than a USART frame are thus not supported by the USART. GPIO can be used for this.

• Disable transmitter after transmission: If TXDISAT is set, the transmitter is disabled after the frame has been fully transmitted.

• Enable receiver after transmission: If RXENAT is set, the receiver is enabled after the frame has been fully transmitted. It is enabled in time to detect a start-bit directly after the last stop-bit has been transmitted.

• Unblock receiver after transmission: If UBRXAT is set, the receiver is unblocked and RXBLOCK is cleared after the frame has been fully transmitted.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

332

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• Tristate transmitter after transmission: If TXTRIAT is set, TXTRI is set after the frame has been fully transmitted, tristating the transmitter output. Tristating of the output can also be performed automatically by setting AUTOTRI. If AUTOTRI is set TXTRI is always read as 0.

Note

When in SmartCard mode with repeat enabled, none of the actions, except generate break, will be performed until the frame is transmitted without failure. Generation of a break in SmartCard mode with repeat enabled will cause the USART to detect a NACK on every frame.

16.3.2.4 Data Reception

Data reception is enabled by setting RXEN in USARTn_CMD. When the receiver is enabled, it actively samples the input looking for a transition from high to low indicating the start baud of a new frame. When a start baud is found, reception of the new frame begins if the receive shift register is empty and ready for new data. When the frame has been received, it is pushed into the receive buffer, making the shift register ready for another frame of data, and the receiver starts looking for another start baud. If the receive buffer is full, the received frame remains in the shift register until more space in the receive buffer is available. If an incoming frame is detected while both the receive buffer and the receive shift register are full, the data in the shift register is overwritten, and the RXOF interrupt flag in USARTn_IF is set to indicate the buffer overflow.

The receiver can be disabled by setting the command bit RXDIS in USARTn_CMD. Any frame currently being received when the receiver is disabled is discarded. Whether or not the receiver is enabled at a given time can be read out from RXENS in USARTn_STATUS.

16.3.2.4.1 Receive Buffer Operation

When data becomes available in the receive buffer, the RXDATAV flag in USARTn_STATUS, and the RXDATAV interrupt flag in USARTn_IF are set, and when the buffer becomes full, RXFULL in USARTn_STATUS and the RXFULL interrupt flag in USARTn_IF are set. The status flags RXDATAV and RXFULL are automatically cleared by hardware when their condition is no longer true. This also goes for the RXDATAV interrupt flag, but the RXFULL interrupt flag must be cleared by software. When the RXFULL flag is set, notifying that the buffer is full, space is still available in the receive shift register for one more frame.

Data can be read from the receive buffer in a number of ways. USARTn_RXDATA gives access to the 8 least significant bits of the received frame, and USARTn_RXDOUBLE makes it possible to read the 8 least significant bits of two frames at once, pulling two frames from the buffer. To get access to the 9th, most significant bit, USARTn_RXDATAX must be used. This register also contains status information regarding the frame. USARTn_RXDOUBLEX can be used to get two frames complete with the 9th bits and status bits.

When a frame is read from the receive buffer using USARTn_RXDATA or USARTn_RXDATAX, the frame is pulled out of the buffer, making room for a new frame. USARTn_RXDOUBLE and USARTn_RXDOUBLEX pull two frames out of the buffer. If an attempt is done to read more frames from the buffer than what is available, the RXUF interrupt flag in USARTn_IF is set to signal the underflow, and the data read from the buffer is undefined.

Frames can be read from the receive buffer without removing the data by using USARTn_RXDATAXP and USARTn_RXDOUBLEXP. USARTn_RXDATAXP gives access the first frame in the buffer with status bits, while USARTn_RXDOUBLEXP gives access to both frames with status bits. The data read from these registers when the receive buffer is empty is undefined. If the receive buffer contains one valid frame, the first frame in USARTn_RXDOUBLEXP will be valid. No underflow interrupt is generated by a read using these registers, i.e. RXUF in USARTn_IF is never set as a result of reading from USARTn_RXDATAXP or USARTn_RXDOUBLEXP.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

333

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

The basic operation of the receive buffer when DATABITS in USARTn_FRAME is configured to less

than 10 bits is shown in Figure 16.4 (p. 334) .

Figure 16.4. USART Receive Buffer Operation

Peripheral Bus RXDOUBLE RXDOUBLEX RXDOUBLEXP RX buffer elem ent 0 St at us RXDATA, RXDATAX, RXDATAXP RX buffer elem ent 1 St at us Shift regist er St at us The receive buffer, including the receive shift register can be cleared by setting CLEARRX in USARTn_CMD. Any frame currently being received will not be discarded.

16.3.2.4.2 Blocking Incoming Data

When using hardware frame recognition, as detailed in Section 16.3.2.8 (p. 340) and

Section 16.3.2.9 (p. 341) , it is necessary to be able to let the receiver sample incoming frames without

passing the frames to software by loading them into the receive buffer. This is accomplished by blocking incoming data.

Incoming data is blocked as long as RXBLOCK in USARTn_STATUS is set. When blocked, frames received by the receiver will not be loaded into the receive buffer, and software is not notified by the RXDATAV flag in USARTn_STATUS or the RXDATAV interrupt flag in USARTn_IF at their arrival. For data to be loaded into the receive buffer, RXBLOCK must be cleared in the instant a frame is fully received by the receiver. RXBLOCK is set by setting RXBLOCKEN in USARTn_CMD and disabled by setting RXBLOCKDIS also in USARTn_CMD. There is one exception where data is loaded into the receive buffer even when RXBLOCK is set. This is when an address frame is received when operating

in multi-processor mode. See Section 16.3.2.8 (p. 340) for more information.

Frames received containing framing or parity errors will not result in the FERR and PERR interrupt flags in USARTn_IF being set while RXBLOCK in USARTn_STATUS is set. Hardware recognition is not applied to these erroneous frames, and they are silently discarded.

Note

If a frame is received while RXBLOCK in USARTn_STATUS is cleared, but stays in the receive shift register because the receive buffer is full, the received frame will be loaded into the receive buffer when space becomes available even if RXBLOCK is set at that time.

The overflow interrupt flag RXOF in USARTn_IF will be set if a frame in the receive shift register, waiting to be loaded into the receive buffer is overwritten by an incoming frame even though RXBLOCK in USARTn_STATUS is set.

16.3.2.4.3 Clock Recovery and Filtering

The receiver samples the incoming signal at a rate 16, 8, 6 or 4 times higher than the given baud rate, depending on the oversampling mode given by OVS in USARTn_CTRL. Lower oversampling rates make higher baud rates possible, but give less room for errors.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

334

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

When a high-to-low transition is registered on the input while the receiver is idle, this is recognized as a start-bit, and the baud rate generator is synchronized with the incoming frame.

For oversampling modes 16, 8 and 6, every bit in the incoming frame is sampled three times to gain a level of noise immunity. These samples are aimed at the middle of the bit-periods, as visualized in

Figure 16.5 (p. 335) . With OVS=0 in USARTn_CTRL, the start and data bits are thus sampled at

locations 8, 9 and 10 in the figure, locations 4, 5 and 6 for OVS=1 and locations 3, 4, and 5 for OVS=2.

The value of a sampled bit is determined by majority vote. If two or more of the three bit-samples are high, the resulting bit value is high. If the majority is low, the resulting bit value is low.

Majority vote is used for all oversampling modes except 4x oversampling. In this mode, a single sample

is taken at position 3 as shown in Figure 16.5 (p. 335) .

Majority vote can be disabled by setting MVDIS in USARTn_CTRL.

If the value of the start bit is found to be high, the reception of the frame is aborted, filtering out false start bits possibly generated by noise on the input.

Figure 16.5. USART Sampling of Start and Data Bits

Idle St art bit Bit 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 0 1 2 3 4 5 6 1 2 3 4 5 1 2 3 4 1 2 3 4 If the baud rate of the transmitter and receiver differ, the location each bit is sampled will be shifted towards the previous or next bit in the frame. This is acceptable for small errors in the baud rate, but for larger errors, it will result in transmission errors.

When the number of stop bits is 1 or more, stop bits are sampled like the start and data bits as seen in

Figure 16.6 (p. 336) . When a stop bit has been detected by sampling at positions 8, 9 and 10 for normal mode, or 4, 5 and 6 for smart mode, the USART is ready for a new start bit. As seen in Figure 16.6 (p.

336) , a stop-bit of length 1 normally ends at c, but the next frame will be received correctly as long as

the start-bit comes after position a for OVS=0 and OVS=3, and b for OVS=1 and OVS=2.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

335

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 16.6. USART Sampling of Stop Bits when Number of Stop Bits are 1 or More

a b n’ t h bit 1 st op bit 13 14 15 16 1 2 3 4 5 6 7 8 9 10 0/ 1 X X X X X c Idle or st art bit 7 8 1 2 3 4 5 6 0/ 1 X 4 6 1 2 3 4 5 0/ 1 1 1 2 3 0/ 1 1 When working with stop bit lengths of half a baud period, the above sampling scheme no longer suffices.

In this case, the stop-bit is not sampled, and no framing error is generated in the receiver if the stop bit is not generated. The line must still be driven high before the next start bit however for the USART to successfully identify the start bit.

16.3.2.4.4 Parity Error

When parity bits are enabled, a parity check is automatically performed on incoming frames. When a parity error is detected in an incoming frame, the data parity error bit PERR in the frame is set, as well as the interrupt flag PERR in USARTn_IF. Frames with parity errors are loaded into the receive buffer like regular frames.

PERR can be accessed by reading the frame from the receive buffer using the USARTn_RXDATAX, USARTn_RXDATAXP, USARTn_RXDOUBLEX or USARTn_RXDOUBLEXP registers.

If ERRSTX in USARTn_CTRL is set, the transmitter is disabled on received parity and framing errors. If ERRSRX in USARTn_CTRL is set, the receiver is disabled on parity and framing errors.

16.3.2.4.5 Framing Error and Break Detection

A framing error is the result of an asynchronous frame where the stop bit was sampled to a value of 0.

This can be the result of noise and baud rate errors, but can also be the result of a break generated by the transmitter on purpose.

When a framing error is detected in an incoming frame, the framing error bit FERR in the frame is set.

The interrupt flag FERR in USARTn_IF is also set. Frames with framing errors are loaded into the receive buffer like regular frames.

FERR can be accessed by reading the frame from the receive buffer using the USARTn_RXDATAX, USARTn_RXDATAXP, USARTn_RXDOUBLEX or USARTn_RXDOUBLEXP registers.

If ERRSTX in USARTn_CTRL is set, the transmitter is disabled on parity and framing errors. If ERRSRX in USARTn_CTRL is set, the receiver is disabled on parity and framing errors.

16.3.2.5 Local Loopback

The USART receiver samples U(S)n_RX by default, and the transmitter drives U(S)n_TX by default.

This is not the only option however. When LOOPBK in USARTn_CTRL is set, the receiver is connected

to the U(S)n_TX pin as shown in Figure 16.7 (p. 337) . This is useful for debugging, as the USART

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

336

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

can receive the data it transmits, but it is also used to allow the USART to read and write to the same pin, which is required for some half duplex communication modes. In this mode, the U(S)n_TX pin must be enabled as an output in the GPIO.

Figure 16.7. USART Local Loopback

LOOBPK = 0 µC USART TX RX U(S)n_TX U(S)n_RX LOOBPK = 1 µC USART TX RX U(S)n_TX U(S)n_RX

16.3.2.6 Asynchronous Half Duplex Communication

When doing full duplex communication, two data links are provided, making it possible for data to be sent and received at the same time. In half duplex mode, data is only sent in one direction at a time.

There are several possible half duplex setups, as described in the following sections.

16.3.2.6.1 Single Data-link

In this setup, the USART both receives and transmits data on the same pin. This is enabled by setting LOOPBK in USARTn_CTRL, which connects the receiver to the transmitter output. Because they are both connected to the same line, it is important that the USART transmitter does not drive the line when receiving data, as this would corrupt the data on the line.

When communicating over a single data-link, the transmitter must thus be tristated whenever not transmitting data. This is done by setting the command bit TXTRIEN in USARTn_CMD, which tristates the transmitter. Before transmitting data, the command bit TXTRIDIS, also in USARTn_CMD, must be set to enable transmitter output again. Whether or not the output is tristated at a given time can be read from TXTRI in USARTn_STATUS. If TXTRI is set when transmitting data, the data is shifted out of the shift register, but is not put out on U(S)n_TX.

When operating a half duplex data bus, it is common to have a bus master, which first transmits a request to one of the bus slaves, then receives a reply. In this case, the frame transmission control bits, which can be set by writing to USARTn_TXDATAX, can be used to make the USART automatically disable transmission, tristate the transmitter and enable reception when the request has been transmitted, making it ready to receive a response from the slave.

Tristating the transmitter can also be performed automatically by the USART by using AUTOTRI in USARTn_CTRL. When AUTOTRI is set, the USART automatically tristates U(S)n_TX whenever the transmitter is idle, and enables transmitter output when the transmitter goes active. If AUTOTRI is set TXTRI is always read as 0.

Note

Another way to tristate the transmitter is to enable wired-and or wired-or mode in GPIO.

For wired-and mode, outputting a 1 will be the same as tristating the output, and for wired or mode, outputting a 0 will be the same as tristating the output. This can only be done on buses with a pull-up or pull-down resistor respectively.

16.3.2.6.2 Single Data-link with External Driver

Some communication schemes, such as RS-485 rely on an external driver. Here, the driver has an extra input which enables it, and instead of tristating the transmitter when receiving data, the external driver must be disabled.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

337

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

This can be done manually by assigning a GPIO to turn the driver on or off, or it can be handled automatically by the USART. If AUTOCS in USARTn_CTRL is set, the USn_CS output is automatically activated one baud period before the transmitter starts transmitting data, and deactivated when the last bit has been transmitted and there is no more data in the transmit buffer to transmit, or the transmitter becomes disabled. This feature can be used to turn the external driver on when transmitting data, and turn it off when the data has been transmitted.

Figure 16.8 (p. 338) shows an example configuration where USn_CS is used to automatically enable

and disable an external driver.

Figure 16.8. USART Half Duplex Communication with External Driver

µC USART CS TX RX The USn_CS output is active low by default, but its polarity can be changed with CSINV in USARTn_CTRL. AUTOCS works regardless of which mode the USART is in, so this functionality can also be used for automatic chip/slave select when in synchronous mode (e.g. SPI).

16.3.2.6.3 Two Data-links

Some limited devices only support half duplex communication even though two data links are available.

In this case software is responsible for making sure data is not transmitted when incoming data is expected.

16.3.2.7 Large Frames

As each frame in the transmit and receive buffers holds a maximum of 9 bits, both the elements in the buffers are combined when working with USART-frames of 10 or more data bits.

To transmit such a frame, at least two elements must be available in the transmit buffer. If only one element is available, the USART will wait for the second element before transmitting the combined frame.

Both the elements making up the frame are consumed when transmitting such a frame.

When using large frames, the 9th bits in the buffers are unused. For an 11 bit frame, the 8 least significant bits are thus taken from the first element in the buffer, and the 3 remaining bits are taken from the second

element as shown in Figure 16.9 (p. 339) . The first element in the transmit buffer, i.e. element 0 in Figure 16.9 (p. 339) is the first element written to the FIFO, or the least significant byte when writing

two bytes at a time using USARTn_TXDOUBLE.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

338

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 16.9. USART Transmission of Large Frames

Peripheral Bus TX buffer elem ent 1 0 1 2 TX buffer elem ent 0 0 1 2 3 4 5 6 7 Shift regist er 0 1 2 3 4 5 6 7 0 1 2 Writ e CTRL Writ e CTRL Writ e CTRL

As shown in Figure 16.9 (p. 339) , frame transmission control bits are taken from the second element

in FIFO.

The two buffer elements can be written at the same time using the USARTn_TXDOUBLE or USARTn_TXDOUBLEX register. The TXDATAX0 bitfield then refers to buffer element 0, and TXDATAX1 refers to buffer element 1.

Figure 16.10. USART Transmission of Large Frames, MSBF

Peripheral Bus TX buffer elem ent 1 0 1 2 TX buffer elem ent 0 0 1 2 3 4 5 6 7 2 1 0 7 6 5 4 3 2 1 0 Shift regist er

Figure 16.10 (p. 339) illustrates the order of the transmitted bits when an 11 bit frame is transmitted

with MSBF set. If MSBF is set and the frame is smaller than 10 bits, only the contents of transmit buffer 0 will be transmitted.

When receiving a large frame, BYTESWAP in USARTn_CTRL determines the order the way the large frame is split into the two buffer elements. If BYTESWAP is cleared, the least significant 8 bits of the received frame are loaded into the first element of the receive buffer, and the remaining bits are loaded

into the second element, as shown in Figure 16.11 (p. 340) . The first byte read from the buffer thus

contains the 8 least significant bits. Set BYTESWAP to reverse the order.

The status bits are loaded into both elements of the receive buffer. The frame is not moved from the receive shift register before there are two free spaces in the receive buffer.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

339

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 16.11. USART Reception of Large Frames

Peripheral Bus RX buffer elem ent 0 St at us 0 1 2 3 4 5 6 7 RX buffer elem ent 1 St at us 0 1 2 St at us Shift regist er 0 1 2 3 4 5 6 7 0 1 2 The two buffer elements can be read at the same time using the USARTn_RXDOUBLE or USARTn_RXDOUBLEX register. RXDATA0 then refers to buffer element 0 and RXDATA1 refers to buffer element 1.

Large frames can be used in both asynchronous and synchronous modes.

16.3.2.8 Multi-Processor Mode

To simplify communication between multiple processors, the USART supports a special multi-processor mode. In this mode the 9th data bit in each frame is used to indicate whether the content of the remaining 8 bits is data or an address.

When multi-processor mode is enabled, an incoming 9-bit frame with the 9th bit equal to the value of MPAB in USARTn_CTRL is identified as an address frame. When an address frame is detected, the MPAF interrupt flag in USARTn_IF is set, and the address frame is loaded into the receive register. This happens regardless of the value of RXBLOCK in USARTn_STATUS.

Multi-processor mode is enabled by setting MPM in USARTn_CTRL, and the value of the 9th bit in address frames can be set in MPAB. Note that the receiver must be enabled for address frames to be detected. The receiver can be blocked however, preventing data from being loaded into the receive buffer while looking for address frames.

Example 16.1 (p. 340) explains basic usage of the multi-processor mode:

Example 16.1. USART Multi-processor Mode Example

1. All slaves enable multi-processor mode and, enable and block the receiver. They will now not receive data unless it is an address frame. MPAB in USARTn_CTRL is set to identify frames with the 9th bit high as address frames.

2. The master sends a frame containing the address of a slave and with the 9th bit set.

3. All slaves receive the address frame and get an interrupt. They can read the address from the receive buffer. The selected slave unblocks the receiver to start receiving data from the master.

4. The master sends data with the 9th bit cleared.

5. Only the slave with RX enabled receives the data. When transmission is complete, the slave blocks the receiver and waits for a new address frame.

When a slave has received an address frame and wants to receive the following data, it must make sure the receiver is unblocked before the next frame has been completely received in order to prevent data loss.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

340

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

BIT8DV in USARTn_CTRL can be used to specify the value of the 9th bit without writing to the transmit buffer with USARTn_TXDATAX or USARTn_TXDOUBLEX, giving higher efficiency in multi-processor mode, as the 9th bit is only set when writing address frames, and 8-bit writes to the USART can be used when writing the data frames.

16.3.2.9 Collision Detection

The USART supports a basic form of collision detection. When the receiver is connected to the output of the transmitter, either by using the LOOPBK bit in USARTn_CTRL or through an external connection, this feature can be used to detect whether data transmitted on the bus by the USART did get corrupted by a simultaneous transmission by another device on the bus.

For collision detection to be enabled, CCEN in USARTn_CTRL must be set, and the receiver enabled.

The data sampled by the receiver is then continuously compared with the data output by the transmitter.

If they differ, the CCF interrupt flag in USARTn_IF is set. The collision check includes all bits of the transmitted frames. The CCF interrupt flag is set once for each bit sampled by the receiver that differs from the bit output by the transmitter. When the transmitter output is disabled, i.e. the transmitter is tristated, collisions are not registered.

16.3.2.10 SmartCard Mode

In SmartCard mode, the USART supports the ISO 7816 I/O line T0 mode. With exception of the stop bits (guard time), the 7816 data frame is equal to the regular asynchronous frame. In this mode, the receiver pulls the line low for one baud, half a baud into the guard time to indicate a parity error. This NAK can for instance be used by the transmitter to re-transmit the frame. SmartCard mode is a half duplex asynchronous mode, so the transmitter must be tristated whenever not transmitting data.

To enable SmartCard mode, set SCMODE in USARTn_CTRL, set the number of databits in a frame to 8, and configure the number of stopbits to 1.5 by writing to STOPBITS in USARTn_FRAME.

The SmartCard mode relies on half duplex communication on a single line, so for it to work, both the receiver and transmitter must work on the same line. This can be achieved by setting LOOPBK in USARTn_CTRL or through an external connection. The TX output should be configured as open-drain in the GPIO module.

When no parity error is identified by the receiver, the data frame is as shown in Figure 16.12 (p. 341)

. The frame consists of 8 data bits, a parity bit, and 2 stop bits. The transmitter does not drive the output line during the guard time.

Figure 16.12. USART ISO 7816 Data Frame Without Error

ISO 7816 Fram e wit hout error St op or idle S 0 1 2 3 4 5 6 7 P St op St art or idle If a parity error is detected by the receiver, it pulls the line I/O line low after half a stop bit, see

Figure 16.13 (p. 342) . It holds the line low for one bit-period before it releases the line. In this case,

the guard time is extended by one bit period before a new transmission can start, resulting in a total of 3 stop bits.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

341

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 16.13. USART ISO 7816 Data Frame With Error

St op or idle S 0 1 2 3 ISO 7816 Fram e wit h error 4 5 6 7 P St op NAK St op St art or idle On a parity error, the NAK is generated by hardware. The NAK generated by the receiver is sampled as the stop-bit of the frame. Because of this, parity errors when in SmartCard mode are reported with both a parity error and a framing error.

When transmitting a T0 frame, the USART receiver on the transmitting side samples position 16, 17 and

18 in the stop-bit to detect the error signal when in 16x oversampling mode as shown in Figure 16.14 (p.

342) . Sampling at this location places the stop-bit sample in the middle of the bit-period used for the

error signal (NAK).

If a NAK is transmitted by the receiver, it will thus appear as a framing error at the transmitter, and the FERR interrupt flag in USARTn_IF will be set. If SCRETRANS USARTn_CTRL is set, the transmitter will automatically retransmit a NACK’ed frame. The transmitter will retransmit the frame until it is ACK’ed by the receiver. This only works when the number of databits in a frame is configured to 8.

Set SKIPPERRF in USARTn_CTRL to make the receiver discard frames with parity errors. The PERR interrupt flag in USARTn_IF is set when a frame is discarded because of a parity error.

Figure 16.14. USART SmartCard Stop Bit Sampling

P 1/ 2 st op bit NAK or st op 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 X X X X X X St op 7 8 1 2 3 4 5 6 7 8 9 10 X X 4 6 1 2 3 4 5 6 7 8 x 1 2 3 4 5 x For communication with a SmartCard, a clock signal needs to be generated for the card. This clock output can be generated using one of the timers. See the ISO 7816 specification for more info on this clock signal.

SmartCard T1 mode is also supported. The T1 frame format used is the same as the asynchronous frame format with parity bit enabled and one stop bit. The USART must then be configured to operate in asynchronous half duplex mode.

16.3.3 Synchronous Operation

Most of the features in asynchronous mode are available in synchronous mode. Multi-processor mode can be enabled for 9-bit frames, loopback is available and collision detection can be performed.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

342

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

16.3.3.1 Frame Format

The frames used in synchronous mode need no start and stop bits since a single clock is available to all parts participating in the communication. Parity bits cannot be used in synchronous mode.

The USART supports frame lengths of 4 to 16 bits per frame. Larger frames can be simulated by transmitting multiple smaller frames, i.e. a 22 bit frame can be sent using two 11-bit frames, and a 21 bit frame can be generated by transmitting three 7-bit frames. The number of bits in a frame is set using DATABITS in USARTn_FRAME.

The frames in synchronous mode are by default transmitted with the least significant bit first like in asynchronous mode. The bit-order can be reversed by setting MSBF in USARTn_CTRL.

The frame format used by the transmitter can be inverted by setting TXINV in USARTn_CTRL, and the format expected by the receiver can be inverted by setting RXINV, also in USARTn_CTRL.

16.3.3.2 Clock Generation

The bit-rate in synchronous mode is given by Equation 16.3 (p. 343) . As in the case of asynchronous

operation, the clock division factor have a 13-bit integral part and a 2-bit fractional part.

USART Synchronous Mode Bit Rate

br = f HFPERCLK /(2 x (1 + USARTn_CLKDIV/256)) (16.3) Given a desired baud rate brdesired, the clock divider USARTn_CLKDIV can be calculated using

Equation 16.4 (p. 343)

USART Synchronous Mode Clock Division Factor

USARTn_CLKDIV = 256 x (f HFPERCLK /(2 x brdesired) - 1) (16.4) When the USART operates in master mode, the highest possible bit rate is half the peripheral clock rate.

When operating in slave mode however, the highest bit rate is an eighth of the peripheral clock: • Master mode: br max = f HFPERCLK /2 • Slave mode: br max = f HFPERCLK /8 On every clock edge data on the data lines, MOSI and MISO, is either set up or sampled. When CLKPHA in USARTn_CTRL is cleared, data is sampled on the leading clock edge and set-up is done on the trailing edge. If CLKPHA is set however, data is set-up on the leading clock edge, and sampled on the trailing edge. In addition to this, the polarity of the clock signal can be changed by setting CLKPOL in USARTn_CTRL, which also defines the idle state of the clock. This results in four different modes which

are summarized in Table 16.8 (p. 343) . Figure 16.15 (p. 344) shows the resulting timing of data

set-up and sampling relative to the bus clock.

Table 16.8. USART SPI Modes

1 2

SPI mode

0 3 0 1

CLKPOL

0 1 1 0

CLKPHA

0 1

Leading edge

Rising, sample Rising, set-up Falling, sample Falling, set-up

Trailing edge

Falling, set-up Falling, sample Rising, set-up Rising, sample 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

343

www.silabs.com

Preliminary

Figure 16.15. USART SPI Timing ...the world's most energy friendly microcontrollers

USn_CLK CLKPOL = 0 CLKPOL = 1 USn_CS USn_TX/ USn_RX CLKPHA = 0 X CLKPHA = 1 X 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 X X If CPHA=1, the TX underflow flag, TXUF, will be set on the first setup clock edge of a frame in slave mode if TX data is not available. If CPHA=0, TXUF is set if data is not available in the transmit buffer three HFPERCLK cycles prior to the first sample clock edge. The RXDATAV flag is updated on the last sample clock edge of a transfer, while the RX overflow interrupt flag, RXOF, is set on the first sample clock edge if the receive buffer overflows. When a transfer has been performed, interrupt flags TXBL and TXC are updated on the first setup clock edge of the succeeding frame, or when CS is deasserted.

16.3.3.3 Master Mode

When in master mode, the USART is in full control of the data flow on the synchronous bus. When operating in full duplex mode, the slave cannot transmit data to the master without the master transmitting to the slave. The master outputs the bus clock on USn_CLK.

Communication starts whenever there is data in the transmit buffer and the transmitter is enabled. The USART clock then starts, and the master shifts bits out from the transmit shift register using the internal clock.

When there are no more frames in the transmit buffer and the transmit shift register is empty, the clock stops, and communication ends. When the receiver is enabled, it samples data using the internal clock when the transmitter transmits data. Operation of the RX and TX buffers is as in asynchronous mode.

16.3.3.3.1 Operation of USn_CS Pin

When operating in master mode, the USn_CS pin can have one of two functions, or it can be disabled.

If USn_CS is configured as an output, it can be used to automatically generate a chip select for a slave by setting AUTOCS in USARTn_CTRL. If AUTOCS is set, USn_CS is activated when a transmission begins, and deactivated directly after the last bit has been transmitted and there is no more data in the transmit buffer. By default, USn_CS is active low, but its polarity can be inverted by setting CSINV in USARTn_CTRL.

When USn_CS is configured as an input, it can be used by another master that wants control of the bus to make the USART release it. When USn_CS is driven low, or high if CSINV is set, the interrupt flag SSM in USARTn_IF is set, and if CSMA in USARTn_CTRL is set, the USART goes to slave mode.

16.3.3.3.2 AUTOTX

A synchronous master is required to transmit data to a slave in order to receive data from the slave. In some cases, only a few words are transmitted and a lot of data is then received from the slave. In that case, one solution is to keep feeding the TX with data to transmit, but that consumes system bandwidth.

Instead AUTOTX can be used.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

344

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

When AUTOTX in USARTn_CTRL is set, the USART transmits data as long as there is available space in the RX shift register for the chosen frame size. This happens even though there is no data in the TX buffer. The TX underflow interrupt flag TXUF in USARTn_IF is set on the first word that is transmitted which does not contain valid data.

During AUTOTX the USART will always send the previous sent bit, thus reducing the number of transitions on the TX output. So if the last bit sent was a 0, 0's will be sent during AUTOTX and if the last bit sent was a 1, 1's will be sent during AUTOTX.

16.3.3.3.3 Synchronous Master Sample Delay

To improve speed in certain conditions by reducing the setup-time requirements for the SPI slave, the master can be configured to sample the data one half SCLK-cycle later, i.e. on the next setup edge, which, in SPI mode 0, is the rising edge. This is enabled by setting SMSDELAY in USARTn_CTRL and can be used together with all SPI slaves that does not set up new data before the next setup edge, as the propagation delay of SCLK will ensure sufficient hold time.

Note

If used together with another Silicon Laboratories chip utilizing SSSEARLY, a very thorough understanding of the timing is required.

Figure 16.16. USART SPI timing with SMSDELAY

USn_CLK USn_CS USn_TX (MOSI) X USn_RX (MISO) X 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 X X Ordinary Sam ple Edge Sam ple Edge wit h SMSDELAY

16.3.3.4 Slave Mode

When the USART is in slave mode, data transmission is not controlled by the USART, but by an external master. The USART is therefore not able to initiate a transmission, and has no control over the number of bytes written to the master.

The output and input to the USART are also swapped when in slave mode, making the receiver take its input from USn_TX (MOSI) and the transmitter drive USn_RX (MISO).

To transmit data when in slave mode, the slave must load data into the transmit buffer and enable the transmitter. The data will remain in the USART until the master starts a transmission by pulling the USn_CS input of the slave low and transmitting data. For every frame the master transmits to the slave, a frame is transferred from the slave to the master. After a transmission, MISO remains in the same state as the last bit transmitted. This also applies if the master transmits to the slave and the slave TX buffer is empty.

If the transmitter is enabled in synchronous slave mode and the master starts transmission of a frame, the underflow interrupt flag TXUF in USARTn_IF will be set if no data is available for transmission to the master.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

345

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

If the slave needs to control its own chip select signal, this can be achieved by clearing CSPEN in the ROUTE register. The internal chip select signal can then be controlled through CSINV in the CTRL register. The chip select signal will be CSINV inverted, i.e. if CSINV is cleared, the chip select is active and vice versa.

16.3.3.4.1 Synchronous Slave Setup Early

To improve speed in certain conditions by improving the setup time when running in slave mode, the slave can be configured to set up data one half SCLK-cycle earlier, i.e. on the previous sample edge, which, for SPI mode 0, is the falling edge. This is enabled by setting SSSEARLY in USARTn_CTRL and can be used with all SPI masters that samples the data on the sample edge, as the SCLK propagation delay will ensure sufficient hold time.

Note

If used together with another Silicon Laboratories chip utilizing SMSDELAY, a very thorough understanding of the timing is required.

Figure 16.17. USART SPI Slave Timing with SSSEARLY

USn_CLK USn_CS USn_TX (MOSI) X USn_RX (MISO) X 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 X X

16.3.3.5 Synchronous Half Duplex Communication

Half duplex communication in synchronous mode is very similar to half duplex communication in

asynchronous mode as detailed in Section 16.3.2.6 (p. 337) . The main difference is that in this mode,

the master must generate the bus clock even when it is not transmitting data, i.e. it must provide the slave with a clock to receive data. To generate the bus clock, the master should transmit data with the transmitter tristated, i.e. TXTRI in USARTn_STATUS set, when receiving data. If 2 bytes are expected from the slave, then transmit 2 bytes with the transmitter tristated, and the slave uses the generated bus clock to transmit data to the master. TXTRI can be set by setting the TXTRIEN command bit in USARTn_CMD.

Note

When operating as SPI slave in half duplex mode, TX has to be tristated (not disabled) during data reception if the slave is to transmit data in the current transfer.

16.3.3.6 I2S

I2S is a synchronous format for transmission of audio data. The frame format is 32-bit, but since data is always transmitted with MSB first, an I2S device operating with 16-bit audio may choose to only process the 16 msb of the frame, and only transmit data in the 16 msb of the frame.

In addition to the bit clock used for regular synchronous transfers, I2S mode uses a separate word clock.

When operating in mono mode, with only one channel of data, the word clock pulses once at the start of each new word. In stereo mode, the word clock toggles at the start of new words, and also gives away 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

346

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

whether the transmitted word is for the left or right audio channel; A word transmitted while the word clock is low is for the left channel, and a word transmitted while the word clock is high is for the right.

When operating in I2S mode, the CS pin is used as a the word clock. In master mode, this is automatically driven by the USART, and in slave mode, the word clock is expected from an external master.

16.3.3.6.1 Word Format

The general I2S word format is 32 bits wide, but the USART also supports 16-bit and 8-bit words. In addition to this, it can be specified how many bits of the word should actually be used by the USART.

These parameters are given by FORMAT in USARTn_I2SCTRL.

As an example, configuring FORMAT to using a 32-bit word with 16-bit data will make each word on the I2S bus 32-bits wide, but when receiving data through the USART, only the 16 most significant bits of each word can be read out of the USART. Similarly, only the 16 most significant bits have to be written to the USART when transmitting. The rest of the bits will be transmitted as zeroes.

16.3.3.6.2 Major Modes

The USART supports a set of different I2S formats as shown in Table 16.9 (p. 347) , but it is not limited

to these modes. MONO, JUSTIFY and DELAY in USARTn_I2SCTRL can be mixed and matched to create an appropriate format. MONO enables mono mode, i.e. one data stream instead of two which is the default. JUSTIFY aligns data within a word on the I2S bus, either left or right which can bee seen in

figures Figure 16.20 (p. 348) and Figure 16.21 (p. 348) . Finally, DELAY specifies whether a new I2S

word should be started directly on the edge of the word-select signal, or one bit-period after the edge.

Table 16.9. USART I2S Modes

Mode

Regular I2S Left-Justified Right-Justified Mono 0 0

MONO

0 1 0 1

JUSTIFY

0 0 0 0

DELAY

1 0 1 1

CLKPOL

0 0

The regular I2S waveform is shown in Figure 16.18 (p. 347) and Figure 16.19 (p. 348) . The first

figure shows a waveform transmitted with full accuracy. The wordlength can be configured to 32-bit, 16-bit or 8-bit using FORMAT in USARTn_I2SCTRL. In the second figure, I2S data is transmitted with reduced accuracy, i.e. the data transmitted has less bits than what is possible in the bus format.

Note that the msb of a word transmitted in regular I2S mode is delayed by one cycle with respect to word select

Figure 16.18. USART Standard I2S waveform

USn_CLK USn_CS (word select ) USn_TX/ USn_RX LSB MSB Right channel Left channel LSB MSB Right channel 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

347

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Figure 16.19. USART Standard I2S waveform (reduced accuracy)

USn_CLK USn_CS (word select ) USn_TX/ USn_RX Right channel MSB LSB Left channel MSB Right channel

A left-justified stream is shown in Figure 16.20 (p. 348) . Note that the MSB comes directly after the

edge on the word-select signal in contradiction to the regular I2S waveform where it comes one bit period after.

Figure 16.20. USART Left-justified I2S waveform

USn_CLK USn_CS (word select ) USn_TX/ USn_RX Right channel MSB LSB Left channel MSB Right channel

A right-justified stream is shown in Figure 16.21 (p. 348) . The left and right justified streams are equal

when the data-size is equal to the word-width.

Figure 16.21. USART Right-justified I2S waveform

USn_CLK USn_TX/ USn_RX LSB Right channel MSB Left channel LSB Right channel 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

348

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

In mono-mode, the word-select signal pulses at the beginning of each word instead of toggling for each

word. Mono I2S waveform is shown in Figure 16.22 (p. 349) .

Figure 16.22. USART Mono I2S waveform

USn_CLK USn_CS (word select ) USn_TX/ USn_RX Right channel MSB LSB Left channel MSB Right channel

16.3.3.6.3 Using I2S Mode

When using the USART in I2S mode, DATABITS in USARTn_FRAME must be set to 8 or 16 data-bits.

8 databits can be used in all modes, and 16 can be used in the modes where the number of bytes in the I2S word is even. In addition to this, MSBF in USARTn_CTRL should be set, and CLKPOL and CLKPHA in USARTn_CTRL should be cleared.

The USART does not have separate TX and RX buffers for left and right data, so when using I2S in stereo mode, the application must keep track of whether the buffers contain left or right data. This can be done by observing TXBLRIGHT, RXDATAVRIGHT and RXFULLRIGHT in USARTn_STATUS. TXBLRIGHT tells whether TX is expecting data for the left or right channel. It will be set with TXBL if right data is expected. The receiver will set RXDATAVRIGHT if there is at least one right element in the buffer, and RXFULLRIGHT if the buffer is full of right elements.

When using I2S with DMA, separate DMA requests can be used for left and right data by setting DMASPLIT in USARTn_I2SCTRL.

In both master and slave mode the USART always starts transmitting on the LEFT channel after being enabled. In master mode, the transmission will stop if TX becomes empty. In that case, TXC is set.

Continuing the transmission in this case will make the data-stream continue where it left off. To make the USART start on the LEFT channel after going empty, disable and re-enable TX.

16.3.4 PRS-triggered Transmissions

If a transmission must be started on an event with very little delay, the PRS system can be used to trigger the transmission. The PRS channel to use as a trigger can be selected using TSEL in USARTn_TRIGCTRL. When a positive edge is detected on this signal, the receiver is enabled if RXTEN in USARTn_TRIGCTRL is set, and the transmitter is enabled if TXTEN in USARTn_TRIGCTRL is set.

Only one signal input is supported by the USART.

The AUTOTX feature can also be enabled via PRS. If an external SPI device sets a pin high when there is data to be read from the device, this signal can be routed to the USART through the PRS system and be used to make the USART clock data out of the external device. If AUTOTXTEN in USARTn_TRIGCTRL is set, the USART will transmit data whenever the PRS signal selected by TSEL is high given that there is enough room in the RX buffer for the chosen frame size. Note that if there is no data in the TX buffer when using AUTOTX, the TX underflow interrupt will be set.

AUTOTXTEN can also be combined with TXTEN to make the USART transmit a command to the external device prior to clocking out data. To do this, disable TX using the TXDIS command, load the 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

349

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

TX buffer with the command and enable AUTOTXTEN and TXTEN. When the selected PRS input goes high, the USART will now transmit the loaded command, and then continue clocking out while both the PRS input is high and there is room in the RX buffer

16.3.5 PRS RX Input

The USART can be configured to receive data directly from a PRS channel by setting RXPRS in USARTn_INPUT. The PRS channel used is selected using RXPRSSEL in USARTn_INPUT. This way, for example, a differential RX signal can be input to the ACMP and the output routed via PRS to the USART.

16.3.6 DMA Support

The USART has full DMA support. The DMA controller can write to the transmit buffer using the registers USARTn_TXDATA, USARTn_TXDATAX, USARTn_TXDOUBLE and USARTn_TXDOUBLEX, and it can read from the receive buffer using the registers USARTn_RXDATA, USARTn_RXDATAX, USARTn_RXDOUBLE and USARTn_RXDOUBLEX. This enables single byte transfers, 9 bit data + control/status bits, double byte and double byte + control/status transfers both to and from the USART.

A request for the DMA controller to read from the USART receive buffer can come from the following source: • Data available in the receive buffer.

• Data available in the receive buffer and data is for the RIGHT I2S channel. Only used in I2S mode.

A write request can come from one of the following sources: • Transmit buffer and shift register empty. No data to send.

• Transmit buffer has room for more data.

• Transmit buffer has room for RIGHT I2S data. Only used in I2S mode.

Even though there are two sources for write requests to the DMA, only one should be used at a time, since the requests from both sources are cleared even though only one of the requests are used.

In some cases, it may be sensible to temporarily stop DMA access to the USART when an error such as a framing error has occurred. This is enabled by setting ERRSDMA in USARTn_CTRL.

16.3.7 Transmission Delay

By configuring TXDELAY in USARTn_CTRL, the transmitter can be forced to wait a number of bit periods from it is ready to transmit data, to it actually transmits the data. This delay is only applied to the first frame transmitted after the transmitter has been idle. When transmitting frames back-to-back the delay is not introduced between the transmitted frames.

This is useful on half duplex buses, because the receiver always returns received frames to software during the first stop-bit. The bus may still be driven for up to 3 baud periods, depending on the current frame format. Using the transmission delay, a transmission can be started when a frame is received, and it is possible to make sure that the transmitter does not begin driving the output before the frame on the bus is completely transmitted.

TXDELAY in USARTn_CTRL only applies to asynchronous transmission.

16.3.8 Interrupts

The interrupts generated by the USART are combined into two interrupt vectors. Interrupts related to reception are assigned to one interrupt vector, and interrupts related to transmission are assigned to the other. Separating the interrupts in this way allows different priorities to be set for transmission and reception interrupts.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

350

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

The transmission interrupt vector groups the transmission-related interrupts generated by the following interrupt flags: • TXC • TXBL • TXOF • CCF The reception interrupt on the other hand groups the reception-related interrupts, triggered by the following interrupt flags: • RXDATAV • RXFULL • RXOF • RXUF • PERR • FERR • MPAF • SSM If USART interrupts are enabled, an interrupt will be made if one or more of the interrupt flags in USART_IF and their corresponding bits in USART_IEN are set.

16.3.9 IrDA Modulator/Demodulator

The IrDA modulator on USART0 USART1 implements the physical layer of the IrDA specification, which is necessary for communication over IrDA. The modulator takes the signal output from the USART module, and modulates it before it leaves USART0 USART1. In the same way, the input signal is demodulated before it enters the actual USART module. The modulator is only available on USART0 USART1, and implements the original Rev. 1.0 physical layer and one high speed extension which supports speeds from 2.4 kbps to 1.152 Mbps.

The data from and to the USART is represented in a NRZ (Non Return to Zero) format, where the signal value is at the same level through the entire bit period. For IrDA, the required format is RZI (Return to Zero Inverted), a format where a “1” is signalled by holding the line low, and a “0” is signalled by a short

high pulse. An example is given in Figure 16.23 (p. 351) .

Figure 16.23. USART Example RZI Signal for a given Asynchronous USART Frame

USART (NRZ) IrDA (RZI) Idle S 0 1 2 3 4 5 6 7 P St op Idle The IrDA module is enabled by setting IREN. The USART transmitter output and receiver input is then routed through the IrDA modulator.

The width of the pulses generated by the IrDA modulator is set by configuring IRPW in USARTn_IRCTRL. Four pulse widths are available, each defined relative to the configured bit period

as listed in Table 16.10 (p. 352) .

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

351

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers Table 16.10. USART IrDA Pulse Widths

IRPW

00 01 10 11

Pulse width OVS=0

1/16 2/16 3/16 4/16

Pulse width OVS=1

1/8 2/8 3/8 N/A

Pulse width OVS=2

1/6 2/6 N/A N/A

Pulse width OVS=3

1/4 N/A N/A N/A By default, no filter is enabled in the IrDA demodulator. A filter can be enabled by setting IRFILT in USARTn_IRCTRL. When the filter is enabled, an incoming pulse has to last for 4 consecutive clock cycles to be detected by the IrDA demodulator.

Note that by default, the idle value of the USART data signal is high. This means that the IrDA modulator generates negative pulses, and the IrDA demodulator expects negative pulses. To make the IrDA module use RZI signalling, both TXINV and RXINV in USARTn_CTRL must be set.

The IrDA module can also modulate a signal from the PRS system, and transmit a modulated signal to the PRS system. To use a PRS channel as transmitter source instead of the USART, set IRPRSEN in USARTn_IRCTRL high. The channel is selected by configuring IRPRSSEL in USARTn_IRCTRL.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

352

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

16.4 Register Map

The offset register address is relative to the registers base address.

Offset

0x000

0x004

0x008

0x00C

0x010

0x014 0x018

0x01C 0x020

0x024 0x028

0x02C 0x030

0x034 0x038

0x03C

0x040

0x044 0x048

0x04C

0x050

0x054

0x058 0x05C

Name

USARTn_CTRL

USARTn_FRAME

USARTn_TRIGCTRL

USARTn_CMD

USARTn_STATUS

USARTn_CLKDIV USARTn_RXDATAX

USARTn_RXDATA USARTn_RXDOUBLEX

USARTn_RXDOUBLE USARTn_RXDATAXP

USARTn_RXDOUBLEXP USARTn_TXDATAX

USARTn_TXDATA USARTn_TXDOUBLEX

USARTn_TXDOUBLE

USARTn_IF

USARTn_IFS USARTn_IFC

USARTn_IEN

USARTn_IRCTRL

USARTn_ROUTE

USARTn_INPUT USARTn_I2SCTRL

Type

RW RW RW W1 R RW R R R R R R W W W W R W1 W1 RW RW RW RW RW

Description

Control Register

USART Frame Format Register

USART Trigger Control register

Command Register

USART Status Register

Clock Control Register RX Buffer Data Extended Register

RX Buffer Data Register RX Buffer Double Data Extended Register

RX FIFO Double Data Register RX Buffer Data Extended Peek Register

RX Buffer Double Data Extended Peek Register TX Buffer Data Extended Register

TX Buffer Data Register TX Buffer Double Data Extended Register

TX Buffer Double Data Register

Interrupt Flag Register

Interrupt Flag Set Register Interrupt Flag Clear Register

Interrupt Enable Register

IrDA Control Register

I/O Routing Register

USART Input Register I2S Control Register

16.5 Register Description 16.5.1 USARTn_CTRL - Control Register Offset

0x000

Reset Access Bit Position Name Bit

31 30

Name Reset Access Description

SMSDELAY 0 RW

Synchronous Master Sample Delay

Delay Synchronous Master sample point to the next setup edge to improve timing and allow communication at higher speeds.

MVDIS 0 RW Disable majority vote for 16x, 8x and 6x oversampling modes.

Majority Vote Disable

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

353

www.silabs.com

Bit

29 28 27:26 25 24 23 22 21 20 19 18 17 16

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

AUTOTX 0 RW

Always Transmit When RX Not Full

Transmits as long as RX is not full. If TX is empty, underflows are generated.

BYTESWAP 0 RW Set to switch the order of the bytes in double accesses.

Byteswap In Double Accesses

Value 0 1 Description Normal byte order Byte order swapped TXDELAY 0x0 RW

TX Delay Transmission

Configurable delay before new transfers. Frames sent back-to-back are not delayed.

Value 0 1 2 3 Mode NONE SINGLE DOUBLE TRIPLE Description Frames are transmitted immediately Transmission of new frames are delayed by a single baud period Transmission of new frames are delayed by two baud periods Transmission of new frames are delayed by three baud periods SSSEARLY 0 RW

Synchronous Slave Setup Early

Setup data on sample edge in synchronous slave mode to improve MOSI setup time.

ERRSTX 0 RW

Disable TX On Error

When set, the transmitter is disabled on framing and parity errors (asynchronous mode only) in the receiver.

Value 0 1 Description Received framing and parity errors have no effect on transmitter Received framing and parity errors disable the transmitter ERRSRX 0 RW

Disable RX On Error

When set, the receiver is disabled on framing and parity errors (asynchronous mode only).

Value 0 1 Description Framing and parity errors have no effect on receiver Framing and parity errors disable the receiver ERRSDMA 0 RW

Halt DMA On Error

When set, DMA requests will be cleared on framing and parity errors (asynchronous mode only).

Value 0 1 Description Framing and parity errors have no effect on DMA requests from the USART DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set BIT8DV 0 RW

Bit 8 Default Value

The default value of the 9th bit. If 9-bit frames are used, and an 8-bit write operation is done, leaving the 9th bit unspecified, the 9th bit is set to the value of BIT8DV.

SKIPPERRF 0 RW

Skip Parity Error Frames

When set, the receiver discards frames with parity errors (asynchronous mode only). The PERR interrupt flag is still set.

SCRETRANS 0 RW

SmartCard Retransmit

When in SmartCard mode, a NACK'ed frame will be kept in the shift register and retransmitted if the transmitter is still enabled.

SCMODE 0 RW Use this bit to enable or disable SmartCard mode.

SmartCard Mode

AUTOTRI 0 RW

Automatic TX Tristate

When enabled, TXTRI is set by hardware whenever the transmitter is idle, and TXTRI is cleared by hardware when transmission starts.

Value 0 1 AUTOCS Description The output on U(S)n_TX when the transmitter is idle is defined by TXINV U(S)n_TX is tristated whenever the transmitter is idle 0 RW

Automatic Chip Select

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

354

www.silabs.com

Bit

15 14 13 12 11 10 9 8

7

6:5

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

When enabled, the output on USn_CS will be activated one baud-period before transmission starts, and deactivated when transmission ends.

CSINV 0 RW

Chip Select Invert

Default value is active low. This affects both the selection of external slaves, as well as the selection of the microcontroller as a slave.

Value 0 1 Description Chip select is active low Chip select is active high TXINV 0 RW

Transmitter output Invert

The output from the USART transmitter can optionally be inverted by setting this bit.

Value 0 1 Description Output from the transmitter is passed unchanged to U(S)n_TX Output from the transmitter is inverted before it is passed to U(S)n_TX RXINV 0 RW Setting this bit will invert the input to the USART receiver.

Value 0 1

Receiver Input Invert

Description Input is passed directly to the receiver Input is inverted before it is passed to the receiver TXBIL 0 RW Determines the interrupt and status level of the transmit buffer.

TX Buffer Interrupt Level

Value 0 1 Mode EMPTY HALFFULL Description TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty.

TXBL is cleared when the buffer becomes nonempty.

TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty.

TXBL is cleared when the buffer becomes full.

CSMA 0 RW

Action On Slave-Select In Master Mode

This register determines the action to be performed when slave-select is configured as an input and driven low while in master mode.

Value 0 1 Mode NOACTION GOTOSLAVEMODE Description No action taken Go to slave mode MSBF 0 RW

Most Significant Bit First

Decides whether data is sent with the least significant bit first, or the most significant bit first.

Value 0 1 Description Data is sent with the least significant bit first Data is sent with the most significant bit first CLKPHA 0 RW

Clock Edge For Setup/Sample

Determines where data is set-up and sampled according to the bus clock when in synchronous mode.

Value 0 1 Mode SAMPLELEADING SAMPLETRAILING Description Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode CLKPOL 0 RW

Clock Polarity

Determines the clock polarity of the bus clock used in synchronous mode.

Value 0 1

Reserved

OVS Mode IDLELOW IDLEHIGH 0x0 RW Description The bus clock used in synchronous mode has a low base value The bus clock used in synchronous mode has a high base value

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

Oversampling

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

355

www.silabs.com

4 3 2 1 0

Bit Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Sets the number of clock periods in a UART bit-period. More clock cycles gives better robustness, while less clock cycles gives better performance.

Value 0 1 2 3 Mode X16 X8 X6 X4 Description Regular UART mode with 16X oversampling in asynchronous mode Double speed with 8X oversampling in asynchronous mode 6X oversampling in asynchronous mode Quadruple speed with 4X oversampling in asynchronous mode MPAB 0 RW

Multi-Processor Address-Bit

Defines the value of the multi-processor address bit. An incoming frame with its 9th bit equal to the value of this bit marks the frame as a multi-processor address frame.

MPM 0 RW

Multi-Processor Mode

Multi-processor mode uses the 9th bit of the USART frames to tell whether the frame is an address frame or a data frame.

Value 0 1 Description The 9th bit of incoming frames has no special function An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set CCEN 0 RW

Collision Check Enable

Enables collision checking on data when operating in half duplex modus.

Value 0 1 Description Collision check is disabled Collision check is enabled. The receiver must be enabled for the check to be performed LOOPBK 0 RW

Loopback Enable

Allows the receiver to be connected directly to the USART transmitter for loopback and half duplex communication.

Value 0 1 Description The receiver is connected to and receives data from U(S)n_RX The receiver is connected to and receives data from U(S)n_TX SYNC 0 RW

USART Synchronous Mode

Determines whether the USART is operating in asynchronous or synchronous mode.

Value 0 1 Description The USART operates in asynchronous mode The USART operates in synchronous mode

16.5.2 USARTn_FRAME - USART Frame Format Register Offset

0x004

Reset Access Bit Position Name Bit

31:14

13:12

Name Reset Access Description

Reserved

STOPBITS

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x1 Determines the number of stop-bits used.

RW

Stop-Bit Mode

Value 0 Mode HALF Description The transmitter generates a half stop bit. Stop-bits are not verified by receiver 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

356

www.silabs.com

Bit

11:10

9:8

7:4

3:0

Preliminary

...the world's most energy friendly microcontrollers

Name

Value 1 2 3

Reset

Mode ONE ONEANDAHALF TWO

Access Description

Description One stop bit is generated and verified The transmitter generates one and a half stop bit. The receiver verifies the first stop bit The transmitter generates two stop bits. The receiver checks the first stop-bit only

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PARITY 0x0 RW

Parity-Bit Mode

Determines whether parity bits are enabled, and whether even or odd parity should be used. Only available in asynchronous mode.

Value 0 2 3 Mode NONE EVEN ODD Description Parity bits are not used Even parity are used. Parity bits are automatically generated and checked by hardware.

Odd parity is used. Parity bits are automatically generated and checked by hardware.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DATABITS 0x5 RW This register sets the number of data bits in a USART frame.

Data-Bit Mode

6 7 8 9 10 11 12 13 Value 1 2 3 4 5 Mode FOUR FIVE SIX SEVEN EIGHT NINE TEN ELEVEN TWELVE THIRTEEN FOURTEEN FIFTEEN SIXTEEN Description Each frame contains 4 data bits Each frame contains 5 data bits Each frame contains 6 data bits Each frame contains 7 data bits Each frame contains 8 data bits Each frame contains 9 data bits Each frame contains 10 data bits Each frame contains 11 data bits Each frame contains 12 data bits Each frame contains 13 data bits Each frame contains 14 data bits Each frame contains 15 data bits Each frame contains 16 data bits

16.5.3 USARTn_TRIGCTRL - USART Trigger Control register Bit Position Offset

0x008

Reset Access Name Bit

31:7

6 5 4

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

AUTOTXTEN 0 RW

AUTOTX Trigger Enable

When set, AUTOTX is enabled as long as the PRS channel selected by TSEL has a high value.

TXTEN 0 RW

Transmit Trigger Enable

When set, the PRS channel selected by TSEL sets TXEN, enabling the transmitter on positive trigger edges.

RXTEN 0 RW

Receive Trigger Enable

When set, the PRS channel selected by TSEL sets RXEN, enabling the receiver on positive trigger edges.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

357

www.silabs.com

Bit

3

2:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TSEL 0x0 RW

Trigger PRS Channel Select

Select USART PRS trigger channel. The PRS signal can enable RX and/or TX, depending on the setting of RXTEN and TXTEN.

Value 0 1 2 3 4 5 Mode PRSCH0 PRSCH1 PRSCH2 PRSCH3 PRSCH4 PRSCH5 Description PRS Channel 0 selected PRS Channel 1 selected PRS Channel 2 selected PRS Channel 3 selected PRS Channel 4 selected PRS Channel 5 selected

16.5.4 USARTn_CMD - Command Register Bit Position Offset

0x00C

Reset Access Name Bit

31:12

11 10 9 8 7 6 5 4 3 2 1

Name Reset Access Description

Reserved

CLEARRX

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 W1 Set to clear receive buffer and the RX shift register.

CLEARTX 0 W1 Set to clear transmit buffer and the TX shift register.

Clear RX Clear TX

TXTRIDIS 0 Disables tristating of the transmitter output.

TXTRIEN 0 Tristates the transmitter output.

W1 W1

Transmitter Tristate Disable Transmitter Tristate Enable

RXBLOCKDIS 0 W1

Receiver Block Disable

Set to clear RXBLOCK, resulting in all incoming frames being loaded into the receive buffer.

RXBLOCKEN 0 W1

Receiver Block Enable

Set to set RXBLOCK, resulting in all incoming frames being discarded.

MASTERDIS 0 W1

Master Disable

Set to disable master mode, clearing the MASTER status bit and putting the USART in slave mode.

MASTEREN 0 W1

Master Enable

Set to enable master mode, setting the MASTER status bit. Master mode should not be enabled while TXENS is set to 1. To enable both master and TX mode, write MASTEREN before TXEN, or enable them both in the same write operation.

TXDIS Set to disable transmission.

0 W1

Transmitter Disable

TXEN 0 Set to enable data transmission.

RXDIS 0 W1 W1

Transmitter Enable Receiver Disable

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

358

www.silabs.com

Bit

0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.

RXEN 0 Set to activate data reception on U(S)n_RX.

W1

Receiver Enable 16.5.5 USARTn_STATUS - USART Status Register Bit Position Offset

0x010

Reset Access Name Bit

31:13

12 11 10 9 8 7 6 5 4 3 2 1

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXFULLRIGHT 0 R

RX Full of Right Data

When set, the entire RX buffer contains right data. Only used in I2S mode.

RXDATAVRIGHT 0 R

RX Data Right

When set, reading RXDATA or RXDATAX gives right data. Else left data is read. Only used in I2S mode.

TXBSRIGHT 0 R

TX Buffer Expects Single Right Data

When set, the TX buffer expects at least a single right data. Else it expects left data. Only used in I2S mode.

TXBDRIGHT 0 R

TX Buffer Expects Double Right Data

When set, the TX buffer expects double right data. Else it may expect a single right data or left data. Only used in I2S mode.

RXFULL 0 R

RX FIFO Full

Set when the RXFIFO is full. Cleared when the receive buffer is no longer full. When this bit is set, there is still room for one more frame in the receive shift register.

RXDATAV 0 R

RX Data Valid

Set when data is available in the receive buffer. Cleared when the receive buffer is empty.

TXBL 1 R

TX Buffer Level

Indicates the level of the transmit buffer. If TXBIL is cleared, TXBL is set whenever the transmit buffer is empty, and if TXBIL is set, TXBL is set whenever the transmit buffer is half-full or empty.

TXC 0 R

TX Complete

Set when a transmission has completed and no more data is available in the transmit buffer and shift register. Cleared when data is written to the transmit buffer.

TXTRI 0 R

Transmitter Tristated

Set when the transmitter is tristated, and cleared when transmitter output is enabled. If AUTOTRI in USARTn_CTRL is set this bit is always read as 0.

RXBLOCK 0 R

Block Incoming Data

When set, the receiver discards incoming frames. An incoming frame will not be loaded into the receive buffer if this bit is set at the instant the frame has been completely received.

MASTER 0 R

SPI Master Mode

Set when the USART operates as a master. Set using the MASTEREN command and clear using the MASTERDIS command.

TXENS 0 Set when the transmitter is enabled.

R

Transmitter Enable Status

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

359

www.silabs.com

Bit

0

Preliminary Name Reset

RXENS 0 Set when the receiver is enabled.

Access

R

...the world's most energy friendly microcontrollers

Description Receiver Enable Status 16.5.6 USARTn_CLKDIV - Clock Control Register Offset

0x014

Bit Position Reset Access Name Bit

31:21

20:6 5:3

2:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DIV 0x0000 RW Specifies the fractional clock divider for the USART.

DIVEXT 0x0 RW Specifies the extended fractional clock divider for the USART.

Extended Fractional Clock Divider

Reserved

Fractional Clock Divider

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

16.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register Offset

0x018

Bit Position Reset Access Name Bit

31:16

15 14

13:9

8:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

FERR 0 R

Data Framing Error

Set if data in buffer has a framing error. Can be the result of a break condition.

PERR 0 R

Data Parity Error

Set if data in buffer has a parity error (asynchronous mode only).

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXDATA 0x000 R

RX Data

Use this register to access data read from the USART. Buffer is cleared on read access.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

360

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

16.5.8 USARTn_RXDATA - RX Buffer Data Register Bit Position Offset

0x01C

Reset Access Name Bit

31:8

7:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXDATA 0x00 R

RX Data

Use this register to access data read from USART. Buffer is cleared on read access. Only the 8 LSB can be read using this register.

16.5.9 USARTn_RXDOUBLEX - RX Buffer Double Data Extended Register Bit Position Offset

0x020

Reset Access Name Bit

31 30

29:25

24:16 15 14

13:9

8:0

Name Reset Access Description

FERR1 0 R

Data Framing Error 1

Set if data in buffer has a framing error. Can be the result of a break condition.

PERR1 0 R

Data Parity Error 1

Set if data in buffer has a parity error (asynchronous mode only).

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXDATA1 0x000 Second frame read from buffer.

R

RX Data 1

FERR0 0 R

Data Framing Error 0

Set if data in buffer has a framing error. Can be the result of a break condition.

PERR0 0 R

Data Parity Error 0

Set if data in buffer has a parity error (asynchronous mode only).

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXDATA0 First frame read from buffer.

0x000 R

RX Data 0

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

361

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

16.5.10 USARTn_RXDOUBLE - RX FIFO Double Data Register Offset

0x024

Reset Access Bit Position Name Bit

31:16

15:8 7:0

Name Reset Access Description

Reserved

RXDATA1

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x00 Second frame read from buffer.

RXDATA0 First frame read from buffer.

0x00 R R

RX Data 1 RX Data 0 16.5.11 USARTn_RXDATAXP - RX Buffer Data Extended Peek Register Bit Position Offset

0x028

Reset Access Name Bit

31:16

15 14

13:9

8:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

FERRP 0 R

Data Framing Error Peek

Set if data in buffer has a framing error. Can be the result of a break condition.

PERRP 0 R

Data Parity Error Peek

Set if data in buffer has a parity error (asynchronous mode only).

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXDATAP 0x000 R Use this register to access data read from the USART.

RX Data Peek

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

362

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

16.5.12 USARTn_RXDOUBLEXP - RX Buffer Double Data Extended Peek Register Bit Position Offset

0x02C

Reset Access Name Bit

31 30

29:25

24:16 15 14

13:9

8:0

Name Reset Access Description

FERRP1 0 R

Data Framing Error 1 Peek

Set if data in buffer has a framing error. Can be the result of a break condition.

PERRP1 0 R

Data Parity Error 1 Peek

Set if data in buffer has a parity error (asynchronous mode only).

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXDATAP1 0x000 Second frame read from FIFO.

R

RX Data 1 Peek

FERRP0 0 R

Data Framing Error 0 Peek

Set if data in buffer has a framing error. Can be the result of a break condition.

PERRP0 0 R

Data Parity Error 0 Peek

Set if data in buffer has a parity error (asynchronous mode only).

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXDATAP0 First frame read from FIFO.

0x000 R

RX Data 0 Peek 16.5.13 USARTn_TXDATAX - TX Buffer Data Extended Register Bit Position Offset

0x030

Reset Access Name Bit

31:16

15 14

Name Reset Access Description

Reserved

RXENAT TXDISAT

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Set to enable reception after transmission.

0 W W

Enable RX After Transmission Clear TXEN After Transmission

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

363

www.silabs.com

Bit

13 12 11

10:9

8:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Set to disable transmitter and release data bus directly after transmission.

TXBREAK 0 W

Transmit Data As Break

Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value of TXDATA.

TXTRIAT 0 W Set to tristate transmitter by setting TXTRI after transmission.

Set TXTRI After Transmission

UBRXAT 0 W

Unblock RX After Transmission

Set clear RXBLOCK after transmission, unblocking the receiver.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXDATAX 0x000 W

TX Data

Use this register to write data to the USART. If TXEN is set, a transfer will be initiated at the first opportunity.

16.5.14 USARTn_TXDATA - TX Buffer Data Register Bit Position Offset

0x034

Reset Access Name Bit

31:8

7:0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXDATA 0x00 W

TX Data

This frame will be added to TX buffer. Only 8 LSB can be written using this register. 9th bit and control bits will be cleared.

16.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register Bit Position Offset

0x038

Reset Access Name Bit

31 30

Name Reset

RXENAT1 0 Set to enable reception after transmission.

TXDISAT1 0

Access

W W

Description Enable RX After Transmission Clear TXEN After Transmission

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

364

www.silabs.com

Bit

29 28 27

26:25

24:16 15 14 13 12 11

10:9

8:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Set to disable transmitter and release data bus directly after transmission.

TXBREAK1 0 W

Transmit Data As Break

Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value of USARTn_TXDATA.

TXTRIAT1 0 W Set to tristate transmitter by setting TXTRI after transmission.

Set TXTRI After Transmission

UBRXAT1 0 W

Unblock RX After Transmission

Set clear RXBLOCK after transmission, unblocking the receiver.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXDATA1 0x000 Second frame to write to FIFO.

W

TX Data

RXENAT0 0 Set to enable reception after transmission.

W

Enable RX After Transmission

TXDISAT0 0 W

Clear TXEN After Transmission

Set to disable transmitter and release data bus directly after transmission.

TXBREAK0 0 W

Transmit Data As Break

Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value of TXDATA.

TXTRIAT0 0 W Set to tristate transmitter by setting TXTRI after transmission.

Set TXTRI After Transmission

UBRXAT0 0 W

Unblock RX After Transmission

Set clear RXBLOCK after transmission, unblocking the receiver.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXDATA0 First frame to write to buffer.

0x000 W

TX Data 16.5.16 USARTn_TXDOUBLE - TX Buffer Double Data Register Bit Position Offset

0x03C

Reset Access Name Bit

31:16

15:8 7:0

Name Reset Access Description

Reserved

TXDATA1

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x00 Second frame to write to buffer.

TXDATA0 First frame to write to buffer.

0x00 W W

TX Data TX Data

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

365

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

16.5.17 USARTn_IF - Interrupt Flag Register Offset

0x040

Reset Access Bit Position Name Bit

31:13

12 11 10 9 8 7 6 5 4 3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CCF 0 R

Collision Check Fail Interrupt Flag

Set when a collision check notices an error in the transmitted data.

SSM 0 R

Slave-Select In Master Mode Interrupt Flag

Set when the device is selected as a slave when in master mode.

MPAF 0 R Set when a multi-processor address frame is detected.

Multi-Processor Address Frame Interrupt Flag

FERR 0 R

Framing Error Interrupt Flag

Set when a frame with a framing error is received while RXBLOCK is cleared.

PERR 0 R

Parity Error Interrupt Flag

Set when a frame with a parity error (asynchronous mode only) is received while RXBLOCK is cleared.

TXUF 0 R

TX Underflow Interrupt Flag

Set when operating as a synchronous slave, no data is available in the transmit buffer when the master starts transmission of a new frame.

TXOF 0 R

TX Overflow Interrupt Flag

Set when a write is done to the transmit buffer while it is full. The data already in the transmit buffer is preserved.

RXUF 0 R

RX Underflow Interrupt Flag

Set when trying to read from the receive buffer when it is empty.

RXOF 0 R

RX Overflow Interrupt Flag

Set when data is incoming while the receive shift register is full. The data previously in the shift register is lost.

RXFULL 0 Set when the receive buffer becomes full.

R

RX Buffer Full Interrupt Flag

RXDATAV 0 R Set when data becomes available in the receive buffer.

RX Data Valid Interrupt Flag

TXBL 1 R

TX Buffer Level Interrupt Flag

Set when the buffer becomes empty if TXBIL is cleared, and is set whenever the transmit buffer goes from full to half-full or empty if TXBIL is set.

TXC 0 R

TX Complete Interrupt Flag

This interrupt is used after a transmission when both the TX buffer and shift register are empty.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

366

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

16.5.18 USARTn_IFS - Interrupt Flag Set Register Offset

0x044

Reset Access Bit Position Name Bit

31:13

12 11 10 9 8 7 6 5 4 3

2:1

0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CCF 0 Write to 1 to set the CCF interrupt flag.

SSM 0 Write to 1 to set the SSM interrupt flag.

MPAF 0 Write to 1 to set the MPAF interrupt flag.

FERR 0 Write to 1 to set the FERR interrupt flag.

PERR 0 Write to 1 to set the PERR interrupt flag.

TXUF 0 Write to 1 to set the TXUF interrupt flag.

TXOF 0 Write to 1 to set the TXOF interrupt flag.

RXUF 0 Write to 1 to set the RXUF interrupt flag.

RXOF 0 Write to 1 to set the RXOF interrupt flag.

W1 W1 W1 W1 W1 W1 W1 W1 W1

Set Collision Check Fail Interrupt Flag Set Slave-Select in Master mode Interrupt Flag Set Multi-Processor Address Frame Interrupt Flag Set Framing Error Interrupt Flag Set Parity Error Interrupt Flag Set TX Underflow Interrupt Flag Set TX Overflow Interrupt Flag Set RX Underflow Interrupt Flag Set RX Overflow Interrupt Flag

RXFULL 0 Write to 1 to set the RXFULL interrupt flag.

Reserved

W1

Set RX Buffer Full Interrupt Flag

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXC 0 Write to 1 to set the TXC interrupt flag.

W1

Set TX Complete Interrupt Flag 16.5.19 USARTn_IFC - Interrupt Flag Clear Register Offset

0x048

Reset Access Bit Position Name

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

367

www.silabs.com

Bit

31:13

12 11 10 9 8 7 6 5 4 3

2:1

0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CCF 0 Write to 1 to clear the CCF interrupt flag.

SSM 0 Write to 1 to clear the SSM interrupt flag.

MPAF 0 Write to 1 to clear the MPAF interrupt flag.

FERR 0 Write to 1 to clear the FERR interrupt flag.

PERR 0 Write to 1 to clear the PERR interrupt flag.

TXUF 0 Write to 1 to clear the TXUF interrupt flag.

TXOF 0 Write to 1 to clear the TXOF interrupt flag.

W1 W1 W1 W1 W1 W1 W1

Clear Collision Check Fail Interrupt Flag Clear Slave-Select In Master Mode Interrupt Flag Clear Multi-Processor Address Frame Interrupt Flag Clear Framing Error Interrupt Flag Clear Parity Error Interrupt Flag Clear TX Underflow Interrupt Flag Clear TX Overflow Interrupt Flag

RXUF 0 Write to 1 to clear the RXUF interrupt flag.

RXOF 0 Write to 1 to clear the RXOF interrupt flag.

W1 W1

Clear RX Underflow Interrupt Flag Clear RX Overflow Interrupt Flag

RXFULL 0 Write to 1 to clear the RXFULL interrupt flag.

Reserved

W1

Clear RX Buffer Full Interrupt Flag

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXC 0 Write to 1 to clear the TXC interrupt flag.

W1

Clear TX Complete Interrupt Flag 16.5.20 USARTn_IEN - Interrupt Enable Register Offset

0x04C

Reset Access Bit Position Name Bit

31:13

12 11 10 9

Name Reset Access Description

Reserved

CCF

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 RW Enable interrupt on collision check error detected.

SSM 0 RW Enable interrupt on slave-select in master mode.

MPAF 0 RW Enable interrupt on multi-processor address frame.

FERR 0 Enable interrupt on framing error.

RW

Collision Check Fail Interrupt Enable Slave-Select In Master Mode Interrupt Enable Multi-Processor Address Frame Interrupt Enable Framing Error Interrupt Enable

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

368

www.silabs.com

6 5 4 3 2 1 0

Bit

8 7

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access

PERR 0 RW Enable interrupt on parity error (asynchronous mode only).

TXUF 0 Enable interrupt on TX underflow.

RW RW TXOF 0 Enable interrupt on TX overflow.

RXUF 0 Enable interrupt on RX underflow.

RXOF 0 Enable interrupt on RX overflow.

RW RW RW RXFULL 0 Enable interrupt on RX Buffer full.

RXDATAV Enable interrupt on RX data.

0 TXBL 0 Enable interrupt on TX buffer level.

TXC 0 Enable interrupt on TX complete.

RW RW RW

Description Parity Error Interrupt Enable TX Underflow Interrupt Enable TX Overflow Interrupt Enable RX Underflow Interrupt Enable RX Overflow Interrupt Enable RX Buffer Full Interrupt Enable RX Data Valid Interrupt Enable TX Buffer Level Interrupt Enable TX Complete Interrupt Enable 16.5.21 USARTn_IRCTRL - IrDA Control Register Offset

0x050

Reset Access Bit Position Name Bit

31:8

7 6:4 3

Name

Reserved

IRPRSEN 0 RW

IrDA PRS Channel Enable

Enable the PRS channel selected by IRPRSSEL as input to IrDA module instead of TX.

IRPRSSEL 0x0 RW

IrDA PRS Channel Select

A PRS can be used as input to the pulse modulator instead of TX. This value selects the channel to use.

3 4 5 Value 0 1 2 Mode PRSCH0 PRSCH1 PRSCH2 PRSCH3 PRSCH4 PRSCH5

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

Description PRS Channel 0 selected PRS Channel 1 selected PRS Channel 2 selected PRS Channel 3 selected PRS Channel 4 selected PRS Channel 5 selected RW

IrDA RX Filter

IRFILT 0 Set to enable filter on IrDA demodulator.

Value 0 Description No filter enabled 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

369

www.silabs.com

Bit

2:1 0

Preliminary

...the world's most energy friendly microcontrollers

Name

Value 1

Reset Access Description

Description Filter enabled. IrDA pulse must be high for at least 4 consecutive clock cycles to be detected IRPW 0x0 RW

IrDA TX Pulse Width

Configure the pulse width generated by the IrDA modulator as a fraction of the configured USART bit period.

Value 0 1 2 3 Mode ONE TWO THREE FOUR Description IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 IREN 0 RW Enable IrDA module and rout USART signals through it.

Enable IrDA Module 16.5.22 USARTn_ROUTE - I/O Routing Register Offset

0x054

Reset Access Bit Position Name Bit

31:11

10:8

7:4

3 2 1

Name Reset Access Description

Reserved

LOCATION

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 Decides the location of the USART I/O pins.

RW

I/O Location

2 3 4 Value 0 1 5 6

Reserved

CLKPEN

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 RW When set, the CLK pin of the USART is enabled.

CLK Pin Enable

Value 0 1 Mode LOC0 LOC1 LOC2 LOC3 LOC4 LOC5 LOC6 Description The USn_CLK pin is disabled The USn_CLK pin is enabled Description Location 0 Location 1 Location 2 Location 3 Location 4 Location 5 Location 6

CS Pin Enable

CSPEN 0 When set, the CS pin of the USART is enabled.

RW Value 0 1 Description The USn_CS pin is disabled The USn_CS pin is enabled TXPEN 0 RW When set, the TX/MOSI pin of the USART is enabled

TX Pin Enable

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

370

www.silabs.com

0

Bit Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Value 0 1 Value 0 1 Description The U(S)n_TX (MOSI) pin is disabled The U(S)n_TX (MOSI) pin is enabled RXPEN 0 RW When set, the RX/MISO pin of the USART is enabled.

Description The U(S)n_RX (MISO) pin is disabled The U(S)n_RX (MISO) pin is enabled

RX Pin Enable 16.5.23 USARTn_INPUT - USART Input Register Offset

0x058

Reset Access Bit Position Name Bit

31:5

4

3

2:0

Name

Reserved

RXPRS 0 RW When set, the PRS channel selected as input to RX.

Reserved

PRS RX Enable

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXPRSSEL 0x0 Select PRS channel as input to RX.

RW

RX PRS Channel Select

2 3 4 5 Value 0 1 Mode PRSCH0 PRSCH1 PRSCH2 PRSCH3 PRSCH4 PRSCH5

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

Description PRS Channel 0 selected PRS Channel 1 selected PRS Channel 2 selected PRS Channel 3 selected PRS Channel 4 selected PRS Channel 5 selected

16.5.24 USARTn_I2SCTRL - I2S Control Register Offset

0x05C

Reset Access Bit Position Name Bit

31:11

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

371

www.silabs.com

1 0

7:5

4 3 2

Bit

10:8

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access

FORMAT 0x0 RW Configure the data-width used internally for I2S data

Description I2S Word Format

4 5 6 7 Value 0 1 2 3 Mode W32D32 W32D24M W32D24 W32D16 W32D8 W16D16 W16D8 W8D8 Description 32-bit word, 32-bit data 32-bit word, 32-bit data with 8 lsb masked 32-bit word, 24-bit data 32-bit word, 16-bit data 32-bit word, 8-bit data 16-bit word, 16-bit data 16-bit word, 8-bit data 8-bit word, 8-bit data

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DELAY 0 RW

Delay on I2S data

Set to add a one-cycle delay between a transition on the word-clock and the start of the I2S word. Should be set for standard I2S format DMASPLIT 0 RW

Separate DMA Request For Left/Right Data

When set DMA requests for right-channel data are put on the TXBLRIGHT and RXDATAVRIGHT DMA requests.

JUSTIFY 0 RW Determines whether the I2S data is left or right justified

Justification of I2S Data

Value 0 1 Mode LEFT RIGHT MONO 0 RW Switch between stereo and mono mode. Set for mono EN 0 Set the U(S)ART in I2S mode.

RW Description Data is left-justified Data is right-justified

Stero or Mono Enable I2S Mode

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

372

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

17 LEUART - Low Energy Universal Asynchronous Receiver/Transmitter

0 1 2 3 4

DMA cont roller RAM

Quick Facts What?

The LEUART provides full UART communication using a low frequency 32.768

kHz clock, and has special features for communication without CPU intervention.

Why?

It allows UART communication to be performed in low energy modes, using only a few µA during active communication and only 150 nA when waiting for incoming data.

How?

LEUART RX TX A low frequency clock signal allows communication with less energy. Using DMA, the LEUART can transmit and receive data with minimal CPU intervention. Special UART-frames can be configured to help control the data flow, further automating data transmission.

17.1 Introduction

The unique LEUART TM , the Low Energy UART, is a UART that allows two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication at baud rates up to 9600.

Even when the EFM is in low energy mode EM2 (with most core functionality turned off), the LEUART can wait for an incoming UART frame while having an extremely low energy consumption. When a UART frame is completely received, the CPU can quickly be woken up. Alternatively, multiple frames can be transferred via the Direct Memory Access (DMA) module into RAM memory before waking up the CPU.

Received data can optionally be blocked until a configurable start frame is detected. A signal frame can be configured to generate an interrupt to indicate e.g. the end of a data transmission. The start frame and signal frame can be used in combination for instance to handle higher level communication protocols.

Similarly, data can be transmitted in EM2 either on a frame-by-frame basis with data from the CPU or through use of the DMA.

The LEUART includes all necessary hardware support to make asynchronous serial communication possible with minimum of software intervention and energy consumption.

17.2 Features

• Low energy asynchronous serial communications • Full/half duplex communication • Separate TX / RX enable • Separate double buffered transmit buffer and receive buffer • Programmable baud rate, generated as a fractional division of the LFBCLK • Supports baud rates from 300 baud/s to 9600 baud/s 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

373

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

• Can use a high frequency clock source for even higher baud rates • Configurable number of data bits: 8 or 9 (plus parity bit, if enabled) • Configurable parity: off, even or odd • HW parity bit generation and check • Configurable number of stop bits, 1 or 2 • Capable of sleep-mode wake-up on received frame • Either wake-up on any received byte or • Wake up only on specified start and signal frames • Supports transmission and reception in EM0, EM1 and EM2 with • Full DMA support • Specified start-byte can start reception automatically • IrDA modulator (pulse generator, pulse extender) • Multi-processor mode • Loopback mode • Half duplex communication • Communication debugging • PRS RX input

17.3 Functional Description

An overview of the LEUART module is shown in Figure 17.1 (p. 374) .

Figure 17.1. LEUART Overview

Peripheral Bus LEUn_TX LEUn_RX PRS Input TX Buffer Pulse gen TX Shift Regist er TX Baud rat e generat or UART Cont rol and st at us St art fram e (STARTFRAME) Signal fram e (SIGFRAME) RX Buffer = = !RXBLOCK

St art fram e int errupt Signal fram e int errupt RX Shift Regist er RX Wakeup SYNC Pulse ex t end RX Baud rat e generat or

17.3.1 Frame Format

The frame format used by the LEUART consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking. A frame starts with one start-bit (S), where the line is driven 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

374

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

low for one bit-period. This signals the start of a frame, and is used for synchronization. Following the start bit are 8 or 9 data bits and an optional parity bit. The data is transmitted with the least significant bit first. Finally, a number of stop-bits, where the line is driven high, end the frame. The frame format

is shown in Figure 17.2 (p. 375) .

Figure 17.2. LEUART Asynchronous Frame Format

Fram e St op or idle S 0 1 2 3 4 5 6 7 [8] [P] St op St art or idle The number of data bits in a frame is set by DATABITS in LEUARTn_CTRL, and the number of stop-bits is set by STOPBITS in LEUARTn_CTRL. Whether or not a parity bit should be included, and whether it should be even or odd is defined by PARITY in LEUARTn_CTRL. For communication to be possible, all parties of an asynchronous transfer must agree on the frame format being used.

The frame format used by the LEUART can be inverted by setting INV in LEUARTn_CTRL. This affects the entire frame, resulting in a low idle state, a high start-bit, inverted data and parity bits, and low stop bits. INV should only be changed while the receiver is disabled.

17.3.1.1 Parity Bit Calculation and Handling

Hardware automatically inserts parity bits into outgoing frames and checks the parity bits of incoming

frames. The possible parity modes are defined in Table 17.1 (p. 375) . When even parity is chosen,

a parity bit is inserted to make the number of high bits (data + parity) even. If odd parity is chosen, the parity bit makes the total number of high bits odd. When parity bits are disabled, which is the default configuration, the parity bit is omitted.

Table 17.1. LEUART Parity Bit

PARITY [1:0]

00 01 10 11 No parity (default) Reserved Even parity Odd parity

Description

See Section 17.3.5.4 (p. 380) for more information on parity bit handling.

17.3.2 Clock Source

The LEUART clock source is selected by the LFB bit field the CMU_LFCLKSEL register. The clock is prescaled by the LEUARTn bitfield in the CMU_LFBPRESC0 register and enabled by the LEUARTn bit in the CMU_LFBCLKEN0.

To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to the module clock.

17.3.3 Clock Generation

The LEUART clock defines the transmission and reception data rate. The clock generator employs a fractional clock divider to allow baud rates that are not attainable by integral division of the 32.768 kHz clock that drives the LEUART.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

375

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

The clock divider used in the LEUART is a 12-bit value, with a 7-bit integral part and a 5-bit fractional part. The baud rate of the LEUART is given by :

LEUART Baud Rate Equation

br = fLEUARTn/(1 + LEUARTn_CLKDIV/256) (17.1) where fLEUARTn is the clock frequency supplied to the LEUART. The value of LEUARTn_CLKDIV thus defines the baud rate of the LEUART. The integral part of the divider is right-aligned in the upper 24 bits of LEUARTn_CLKDIV and the fractional part is left-aligned in the lower 8 bits. The divider is thus a 256th of LEUARTn_CLKDIV as seen in the equation.

For a desired baud rate br DESIRED , LEUARTn_CLKDIV can be calculated by using:

LEUART CLKDIV Equation

LEUARTn_CLKDIV = 256 x (fLEUARTn/br DESIRED - 1) (17.2)

Table 17.2 (p. 376) lists a set of desired baud rates and the closest baud rates reachable by the

LEUART with a 32.768 kHz clock source. It also shows the average baud rate error.

Table 17.2. LEUART Baud Rates

Desired baud rate [baud/s]

300 600 1200 2400 4800 9600

LEUARTn_CLKDIV

27704 13728 6736 3240 1488 616

LEUARTn_CLKDIV/256

108,21875 53,625 26,3125 12,65625 5,8125 2,40625

Actual baud rate [baud/s]

300,0217 599,8719 1199,744 2399,487 4809,982 9619,963

Error [%]

0,01 -0,02 -0,02 -0,02 0,21 0,21

17.3.4 Data Transmission

Data transmission is initiated by writing data to the transmit buffer using one of the methods described

in Section 17.3.4.1 (p. 376) . When the transmission shift register is empty and ready for new data,

a frame from the transmit buffer is loaded into the shift register, and if the transmitter is enabled, transmission begins. When the frame has been transmitted, a new frame is loaded into the shift register if available, and transmission continues. If the transmit buffer is empty, the transmitter goes to an idle state, waiting for a new frame to become available. Transmission is enabled through the command register LEUARTn_CMD by setting TXEN, and disabled by setting TXDIS. When the transmitter is disabled using TXDIS, any ongoing transmission is aborted, and any frame currently being transmitted is discarded. When disabled, the TX output goes to an idle state, which by default is a high value. Whether or not the transmitter is enabled at a given time can be read from TXENS in LEUARTn_STATUS.

After a transmission, when there is no more data in the shift register or transmit buffer, the TXC flag in LEUARTn_STATUS and the TXC interrupt flag in LEUARTn_IF are set, signaling that the transmitter is idle. The TXC status flag is cleared when a new byte becomes available for transmission, but the TXC interrupt flag must be cleared by software.

17.3.4.1 Transmit Buffer Operation

A frame can be loaded into the transmit buffer by writing to LEUARTn_TXDATA or LEUARTn_TXDATAX.

Using LEUARTn_TXDATA allows 8 bits to be written to the buffer. If 9 bit frames are used, the 9th bit will in that case be set to the value of BIT8DV in LEUARTn_CTRL. To set the 9th bit directly and/or use transmission control, LEUARTn_TXDATAX must be used. When writing data to the transmit buffer using LEUARTn_TXDATAX, the 9th bit written to LEUARTn_TXDATAX overrides the value in BIT8DV, and alone defines the 9th bit that is transmitted if 9-bit frames are used.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

376

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

If a write is attempted to the transmit buffer when it is not empty, the TXOF interrupt flag in LEUARTn_IF is set, indicating the overflow. The data already in the buffer is in that case preserved, and no data is written.

In addition to the interrupt flag TXC in LEUARTn_IF and the status flag TXC in LEUARTn_STATUS which are set when the transmitter becomes idle, TXBL in LEUARTn_STATUS and the TXBL interrupt flag in LEUARTn_IF are used to indicate the level of the transmit buffer. Whenever the transmit buffer becomes empty, these flags are set high. Both the TXBL status flag and the TXBL interrupt flag are cleared automatically when data is written to the transmit buffer.

The transmit buffer, including the TX shift register can be cleared by setting command bit CLEARTX in LEUARTn_CMD. This will prevent the LEUART from transmitting the data in the buffer and shift register, and will make them available for new data. Any frame currently being transmitted will not be aborted.

Transmission of this frame will be completed. An overview of the operation of the transmitter is shown

in Figure 17.3 (p. 377) .

Figure 17.3. LEUART Transmitter Overview

LEUn_TX TXENS Transm it shift regist er d0- d8 cont rol TXDATA BIT8DV 0 d0 d1 d2 d3 d4 d5 d6 d7 d8 cont rol Transm it buffer TXDATAX

17.3.4.2 Frame Transmission Control

The transmission control bits, which can be written using LEUARTn_TXDATAX, affect the transmission of the written frame. The following options are available: • Generate break: By setting WBREAK, the output will be held low during the first stop-bit period to generate a framing error. A receiver that supports break detection detects this state, allowing it to be used e.g. for framing of larger data packets. The line is driven high for one baud period before the next frame is transmitted so the next start condition can be identified correctly by the recipient. Continuous breaks lasting longer than an UART frame are thus not supported by the LEUART. GPIO can be used for this. Note that when AUTOTRI in LEUARTn_CTRL is used, the transmitter is not tristated before the high-bit after the break has been transmitted.

• Disable transmitter after transmission: If TXDISAT is set, the transmitter is disabled after the frame has been fully transmitted.

• Enable receiver after transmission: If RXENAT is set, the receiver is enabled after the frame has been fully transmitted. It is enabled in time to detect a start-bit directly after the last stop-bit has been transmitted.

The transmission control bits in the LEUART cannot tristate the transmitter. This is performed

automatically by hardware however, if AUTOTRI in LEUARTn_CTRL is set. See Section 17.3.7 (p. 382)

for more information on half duplex operation.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

377

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

17.3.4.3 Jitter in Transmitted Data

Internally the LEUART module uses only the positive edges of the 32.768 kHz clock (LFBCLK) for transmission and reception. Transmitted data will thus have jitter equal to the difference between the optimal data set-up location and the closest positive edge on the 32.768 kHz clock. The jitter in on the location data is set up by the transmitter will thus be no more than half a clock period according to the optimal set-up location. The jitter in the period of a single baud output by the transmitter will never be more than one clock period.

17.3.5 Data Reception

Data reception is enabled by setting RXEN in LEUARTn_CMD. When the receiver is enabled, it actively samples the input looking for a transition from high to low indicating the start baud of a new frame. When a start baud is found, reception of the new frame begins if the receive shift register is empty and ready for new data. When the frame has been received, it is pushed into the receive buffer, making the shift register ready for another frame of data, and the receiver starts looking for another start baud. If the receive buffer is full, the received frame remains in the shift register until more space in the receive buffer is available.

If an incoming frame is detected while both the receive buffer and the receive shift register are full, the data in the receive shift register is overwritten, and the RXOF interrupt flag in LEUARTn_IF is set to indicate the buffer overflow.

The receiver can be disabled by setting the command bit RXDIS in LEUARTn_CMD. Any frame currently being received when the receiver is disabled is discarded. Whether or not the receiver is enabled at a given time can be read out from RXENS in LEUARTn_STATUS.

17.3.5.1 Receive Buffer Operation

When data becomes available in the receive buffer, the RXDATAV flag in LEUARTn_STATUS and the RXDATAV interrupt flag in LEUARTn_IF are set. Both the RXDATAV status flag and the RXDATAV interrupt flag are cleared by hardware when data is no longer available, i.e. when data has been read out of the buffer.

Data can be read from receive buffer using either LEUARTn_RXDATA or LEUARTn_RXDATAX.

LEUARTn_RXDATA gives access to the 8 least significant bits of the received frame, while LEUARTn_RXDATAX must be used to get access to the 9th, most significant bit. The latter register also contains status information regarding the frame.

When a frame is read from the receive buffer using LEUARTn_RXDATA or LEUARTn_RXDATAX, the frame is removed from the buffer, making room for a new one. If an attempt is done to read more frames from the buffer than what is available, the RXUF interrupt flag in LEUARTn_IF is set to signal the underflow, and the data read from the buffer is undefined.

Frames can also be read from the receive buffer without removing the data by using LEUARTn_RXDATAXP, which gives access to the frame in the buffer including control bits. Data read from this register when the receive buffer is empty is undefined. No underflow interrupt is generated by a read using LEUARTn_RXDATAXP, i.e. the RXUF interrupt flag is never set as a result of reading from LEUARTn_RXDATAXP.

An overview of the operation of the receiver is shown in Figure 17.4 (p. 379) .

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

378

www.silabs.com

Preliminary

Figure 17.4. LEUART Receiver Overview ...the world's most energy friendly microcontrollers

LEUn_RX RXENS RXDATA Receive shift regist er d0- d8 st at us !RXBLOCK

d0 d1 d2 d3 d4 d5 d6 d7 d8 st at us Receive buffer RXDATAX (RXDATAXP)

17.3.5.2 Blocking Incoming Data

When using hardware frame recognition, as detailed in Section 17.3.5.6 (p. 380) , Section 17.3.5.7 (p.

381) , and Section 17.3.5.8 (p. 381) , it is necessary to be able to let the receiver sample

incoming frames without passing the frames to software by loading them into the receive buffer. This is accomplished by blocking incoming data.

Incoming data is blocked as long as RXBLOCK in LEUARTn_STATUS is set. When blocked, frames received by the receiver will not be loaded into the receive buffer, and software is not notified by the RXDATAV bit in LEUARTn_STATUS or the RXDATAV interrupt flag in LEUARTn_IF at their arrival.

For data to be loaded into the receive buffer, RXBLOCK must be cleared in the instant a frame is fully received by the receiver. RXBLOCK is set by setting RXBLOCKEN in LEUARTn_CMD and disabled by setting RXBLOCKDIS also in LEUARTn_CMD. There are two exceptions where data is loaded into the receive buffer even when RXBLOCK is set. The first is when an address frame is received when

in operating in multi-processor mode as shown in Section 17.3.5.8 (p. 381) . The other case is when

receiving a start-frame when SFUBRX in LEUARTn_CTRL is set; see Section 17.3.5.6 (p. 380)

Frames received containing framing or parity errors will not result in the FERR and PERR interrupt flags in LEUARTn_IF being set while RXBLOCK is set. Hardware recognition is not applied to these erroneous frames, and they are silently discarded.

Note

If a frame is received while RXBLOCK in LEUARTn_STATUS is cleared, but stays in the receive shift register because the receive buffer is full, the received frame will be loaded into the receive buffer when space becomes available even if RXBLOCK is set at that time.

The overflow interrupt flag RXOF in LEUARTn_IF will be set if a frame in the receive shift register, waiting to be loaded into the receive buffer is overwritten by an incoming frame even though RXBLOCK is set.

17.3.5.3 Data Sampling

The receiver samples each incoming baud as close as possible to the middle of the baud-period. Except for the start-bit, only a single sample is taken of each of the incoming bauds.

The length of a baud-period is given by 1 + LEUARTn_CLKDIV/256, as a number of 32.768 kHz clock periods. Let the clock cycle where a start-bit is first detected be given the index 0. The optimal sampling point for each baud in the UART frame is then given by the following equation: 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

379

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers LEUART Optimal Sampling Point

S opt (n) = n (1 + LEUARTn_CLKDIV/256) + CLKDIV/512 (17.3) where n is the bit-index.

Since samples are only done on the positive edges of the 32.768 kHz clock, the actual samples are performed on the closest positive edge, i.e. the edge given by the following equation:

LEUART Actual Sampling Point

S(n) = floor(n x (1 + LEUARTn_CLKDIV/256) + LEUARTn_CLKDIV/512) (17.4) The sampling location will thus have jitter according to difference between S opt and S. The start-bit is found at n=0, then follows the data bits, any parity bit, and the stop bits.

If the value of the start-bit is found to be high, then the start-bit is discarded, and the receiver waits for a new start-bit.

17.3.5.4 Parity Error

When the parity bit is enabled, a parity check is automatically performed on incoming frames. When a parity error is detected in a frame, the data parity error bit PERR in the frame is set, as well as the interrupt flag PERR. Frames with parity errors are loaded into the receive buffer like regular frames.

PERR can be accessed by reading the frame from the receive buffer using the LEUARTn_RXDATAX register.

17.3.5.5 Framing Error and Break Detection

A framing error is the result of a received frame where the stop bit was sampled to a value of 0. This can be the result of noise and baud rate errors, but can also be the result of a break generated by the transmitter on purpose.

When a framing error is detected, the framing error bit FERR in the received frame is set. The interrupt flag FERR in LEUARTn_IF is also set. Frames with framing errors are loaded into the receive buffer like regular frames.

FERR can be accessed by reading the frame from the receive buffer using the LEUARTn_RXDATAX or LEUARTn_RXDATAXP registers.

17.3.5.6 Programmable Start Frame

The LEUART can be configured to start receiving data when a special start frame is detected on the input.

This can be useful when operating in low energy modes, allowing other devices to gain the attention of the LEUART by transmitting a given frame.

When SFUBRX in LEUARTn_CTRL is set, an incoming frame matching the frame defined in LEUARTn_STARTFRAME will result in RXBLOCK in LEUARTn_STATUS being cleared. This can be used to enable reception when a specified start frame is detected. If the receiver is enabled and blocked, i.e. RXENS and RXBLOCK in LEUARTn_STATUS are set, the receiver will receive all incoming frames, but unless an incoming frame is a start frame it will be discarded and not loaded into the receive buffer.

When a start frame is detected, the block is cleared, and frames received from that point, including the start frame, are loaded into the receive buffer.

An incoming start frame results in the STARTF interrupt flag in LEUARTn_IF being set, regardless of the value of SFUBRX in LEUARTn_CTRL. This allows an interrupt to be made when the start frame is detected.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

380

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

When 8 data-bit frame formats are used, only the 8 least significant bits of LEUARTn_STARTFRAME are compared to incoming frames. The full length of LEUARTn_STARTFRAME is used when operating with frames consisting of 9 data bits.

Note

The receiver must be enabled for start frames to be detected. In addition, a start frame with a parity error or framing error is not detected as a start frame.

17.3.5.7 Programmable Signal Frame

As well as the configurable start frame, a special signal frame can be specified. When a frame matching the frame defined in LEUARTn_SIGFRAME is detected by the receiver, the SIGF interrupt flag in LEUARTn_IF is set. As for start frame detection, the receiver must be enabled for signal frames to be detected.

One use of the programmable signal frame is to signal the end of a multi-frame message transmitted to the LEUART. An interrupt will then be triggered when the packet has been completely received, allowing software to process it. Used in conjunction with the programmable start frame and DMA, this makes it possible for the LEUART to automatically begin the reception of a packet on a specified start frame, load the entire packet into memory, and give an interrupt when reception of a packet has completed.

The device can thus wait for data packets in EM2, and only be woken up when a packet has been completely received.

A signal frame with a parity error or framing error is not detected as a signal frame.

17.3.5.8 Multi-Processor Mode

To simplify communication between multiple processors and maintain compatibility with the USART, the LEUART supports a multi-processor mode. In this mode the 9th data bit in each frame is used to indicate whether the content of the remaining 8 bits is data or an address.

When multi-processor mode is enabled, an incoming 9-bit frame with the 9th bit equal to the value of MPAB in LEUARTn_CTRL is identified as an address frame. When an address frame is detected, the MPAF interrupt flag in LEUARTn_IF is set, and the address frame is loaded into the receive register.

This happens regardless of the value of RXBLOCK in LEUARTn_STATUS.

Multi-processor mode is enabled by setting MPM in LEUARTn_CTRL. The mode can be used in buses with multiple slaves, allowing the slaves to be addressed using the special address frames. An addressed slave, which was previously blocking reception using RXBLOCK, would then unblock reception, receive a message from the bus master, and then block reception again, waiting for the next message. See the USART for a more detailed example.

Note

The programmable start frame functionality can be used for automatic address matching, enabling reception on a correctly configured incoming frame.

An address frame with a parity error or a framing error is not detected as an address frame.

17.3.6 Loopback

The LEUART receiver samples LEUn_RX by default, and the transmitter drives LEUn_TX by default.

This is not the only configuration however. When LOOPBK in LEUARTn_CTRL is set, the receiver is

connected to the LEUn_TX pin as shown in Figure 17.5 (p. 382) . This is useful for debugging, as the

LEUART can receive the data it transmits, but it is also used to allow the LEUART to read and write to the same pin, which is required for some half duplex communication modes. In this mode, the LEUn_TX pin must be enabled as an output in the GPIO.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

381

www.silabs.com

Preliminary

Figure 17.5. LEUART Local Loopback ...the world's most energy friendly microcontrollers

LOOPBK = 0 µC LEUART TX RX LEUn_TX LEUn_RX LOOPBK = 1 µC LEUART TX RX LEUn_TX LEUn_RX

17.3.7 Half Duplex Communication

When doing full duplex communication, two data links are provided, making it possible for data to be sent and received at the same time. In half duplex mode, data is only sent in one direction at a time.

There are several possible half duplex setups, as described in the following sections.

17.3.7.1 Single Data-link

In this setup, the LEUART both receives and transmits data on the same pin. This is enabled by setting LOOPBK in LEUARTn_CTRL, which connects the receiver to the transmitter output. Because they are both connected to the same line, it is important that the LEUART transmitter does not drive the line when receiving data, as this would corrupt the data on the line.

When communicating over a single data-link, the transmitter must thus be tristated whenever not transmitting data. If AUTOTRI in LEUARTn_CTRL is set, the LEUART automatically tristates LEUn_TX whenever the transmitter is inactive. It is then the responsibility of the software protocol to make sure the transmitter is not transmitting data whenever incoming data is expected.

The transmitter can also be tristated from software by configuring the GPIO pin as an input and disabling the LEUART output on LEUn_TX.

Note

Another way to tristate the transmitter is to enable wired-and or wired-or mode in GPIO.

For wired-and mode, outputting a 1 will be the same as tristating the output, and for wired or mode, outputting a 0 will be the same as tristating the output. This can only be done on buses with a pull-up or pull-down resistor respectively.

17.3.7.2 Single Data-link with External Driver

Some communication schemes, such as RS-485 rely on an external driver. Here, the driver has an extra input which enables it, and instead of Tristating the transmitter when receiving data, the external driver must be disabled. The USART has hardware support for automatically turning the driver on and off.

When using the LEUART in such a setup, the driver must be controlled by a GPIO. Figure 17.6 (p. 382)

shows an example configuration using an external driver.

Figure 17.6. LEUART Half Duplex Communication with External Driver

µC GPIO LEUART TX RX 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

382

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

17.3.7.3 Two Data-links

Some limited devices only support half duplex communication even though two data links are available.

In this case software is responsible for making sure data is not transmitted when incoming data is expected.

17.3.8 Transmission Delay

By configuring TXDELAY in LEUARTn_CTRL, the transmitter can be forced to wait a number of bit periods from it is ready to transmit data, to it actually transmits the data. This delay is only applied to the first frame transmitted after the transmitter has been idle. When transmitting frames back-to-back the delay is not introduced between the transmitted frames.

This is useful on half duplex buses, because the receiver always returns received frames to software during the first stop-bit. The bus may still be driven for up to 3 baud periods, depending on the current frame format. Using the transmission delay, a transmission can be started when a frame is received, and it is possible to make sure that the transmitter does not begin driving the output before the frame on the bus is completely transmitted.

17.3.9 PRS RX Input

The LEUART can be configured to receive data directly from the PRS channel by setting RX_PRS in LEUARTn_INPUT. The PRS channel used can be selected using RX_PRS_SEL in LEUARTn_INPUT.

17.3.10 DMA Support

The LEUART has full DMA support in energy modes EM0 – EM2. The DMA controller can write to the transmit buffer using the registers LEUARTn_TXDATA and LEUARTn_TXDATAX, and it can read from receive buffer using the registers LEUARTn_RXDATA and LEUARTn_RXDATAX. This enables single byte transfers and 9 bit data + control/status bits transfers both to and from the LEUART. The DMA will start up the HFRCO and run from this when it is waken by the LEUART in EM2. The HFRCO is disabled once the transaction is done.

A request for the DMA controller to read from the receive buffer can come from one of the following sources: • Receive buffer full A write request can come from one of the following sources: • Transmit buffer and shift register empty. No data to send.

• Transmit buffer empty In some cases, it may be sensible to temporarily stop DMA access to the LEUART when a parity or framing error has occurred. This is enabled by setting ERRSDMA in LEUARTn_CTRL. When this bit is set, the DMA controller will not get requests from the receive buffer if a framing error or parity error is detected in the received byte. The ERRSDMA bit applies only to the RX DMA.

When operating in EM2, the DMA controller must be powered up in order to perform the transfer. This is automatically performed for read operations if RXDMAWU in LEUARTn_CTRL is set and for write operations if TXDMAWU in LEUARTn_CTRL is set. To make sure the DMA controller still transfers bits to and from the LEUART in low energy modes, these bits must thus be configured accordingly.

Note

When RXDMAWU or TXDMAWU is set, the system will not be able to go to EM2/EM3 before all related LEUART DMA requests have been processed. This means that if RXDMAWU is set and the LEUART receives a frame, the system will not be able to go to 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

383

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

EM2/EM3 before the frame has been read from the LEUART. In order for the system to go to EM2 during the last byte transmission, LEUART_CTRL_TXDMAWU must be cleared in the DMA interrupt service routine. This is because TXBL will be high during that last byte transfer.

17.3.11 Pulse Generator/ Pulse Extender

The LEUART has an optional pulse generator for the transmitter output, and a pulse extender on the receiver input. These are enabled by setting PULSEEN in LEUARTn_PULSECTRL, and with INV in LEUARTn_CTRL set, they will change the output/input format of the LEUART from NRZ to RZI as shown

in Figure 17.7 (p. 384) .

Figure 17.7. LEUART - NRZ vs. RZI

Idle Idle NRZ RZI S 0 1 2 3 4 5 6 7 P St op If PULSEEN in LEUARTn_PULSECTRL is set while INV in LEUARTn_CTRL is cleared, the output

waveform will like RZI shown in Figure 17.7 (p. 384) , only inverted.

The width of the pulses from the pulse generator can be configured using PULSEW in LEUARTn_PULSECTRL. The generated pulse width is PULSEW + 1 cycles of the 32.768 kHz clock, which makes pulse width from 31.25µs to 500µs possible.

Since the incoming signal is only sampled on positive clock edges, the width of the incoming pulses must be at least two 32.768 kHz clock periods wide for reliable detection by the LEUART receiver. They must also be shorter than half a UART baud period.

At 2400 baud/s or lower, the pulse generator is able to generate RZI pulses compatible with the IrDA physical layer specification. The external IrDA device must generate pulses of sufficient length for successful two-way communication.

17.3.11.1 Interrupts

The interrupts generated by the LEUART are combined into one interrupt vector. If LEUART interrupts are enabled, an interrupt will be made if one or more of the interrupt flags in LEUARTn_IF and their corresponding bits in LEUART_IEN are set.

17.3.12 Register access

Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to the HFCORECLK, special considerations must be taken when accessing registers. Please refer to

Section 5.3 (p. 18) for a description on how to perform register accesses to Low Energy Peripherals.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

384

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

17.4 Register Map

The offset register address is relative to the registers base address.

Offset

0x000

0x004

0x008 0x00C

0x010 0x014

0x018 0x01C

0x020 0x024

0x028 0x02C

0x030

0x034

0x038 0x03C

0x040 0x044

0x054

0x0AC

Name

LEUARTn_CTRL

LEUARTn_CMD

LEUARTn_STATUS LEUARTn_CLKDIV

LEUARTn_STARTFRAME LEUARTn_SIGFRAME

LEUARTn_RXDATAX LEUARTn_RXDATA

LEUARTn_RXDATAXP LEUARTn_TXDATAX

LEUARTn_TXDATA LEUARTn_IF

LEUARTn_IFS

LEUARTn_IFC

LEUARTn_IEN LEUARTn_PULSECTRL

LEUARTn_FREEZE LEUARTn_SYNCBUSY

LEUARTn_ROUTE

LEUARTn_INPUT

Type

RW RW RW R RW RW RW W1 R RW RW RW R R R W W R W1 W1

Description

Control Register

Command Register

Status Register Clock Control Register

Start Frame Register Signal Frame Register

Receive Buffer Data Extended Register Receive Buffer Data Register

Receive Buffer Data Extended Peek Register Transmit Buffer Data Extended Register

Transmit Buffer Data Register Interrupt Flag Register

Interrupt Flag Set Register

Interrupt Flag Clear Register

Interrupt Enable Register Pulse Control Register

Freeze Register Synchronization Busy Register

I/O Routing Register

LEUART Input Register

17.5 Register Description 17.5.1 LEUARTn_CTRL - Control Register (Async Reg)

For more information about Asynchronous Registers please see Section 5.3 (p. 18) .

Offset

0x000

Reset Access Bit Position Name Bit

31:16

15:14

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXDELAY 0x0 RW

TX Delay Transmission

Configurable delay before new transfers. Frames sent back-to-back are not delayed.

Value 0 1 2 Mode NONE SINGLE DOUBLE Description Frames are transmitted immediately Transmission of new frames are delayed by a single baud period Transmission of new frames are delayed by two baud periods 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

385

www.silabs.com

Bit

13 12 11 10 9 8 7 6 5 4

Preliminary

...the world's most energy friendly microcontrollers

Name

Value 3 Value 0 1 Mode TRIPLE

Reset Access Description

Description Transmission of new frames are delayed by three baud periods TXDMAWU 0 RW

TX DMA Wakeup

Set to wake the DMA controller up when in EM2 and space is available in the transmit buffer.

Description While in EM2, the DMA controller will not get requests about space being available in the transmit buffer DMA is available in EM2 for the request about space available in the transmit buffer RXDMAWU 0 RW

RX DMA Wakeup

Set to wake the DMA controller up when in EM2 and data is available in the receive buffer.

Value 0 1 Description While in EM2, the DMA controller will not get requests about data being available in the receive buffer DMA is available in EM2 for the request about data in the receive buffer BIT8DV 0 RW

Bit 8 Default Value

When 9-bit frames are transmitted, the default value of the 9th bit is given by BIT8DV. If TXDATA is used to write a frame, then the value of BIT8DV is assigned to the 9th bit of the outgoing frame. If a frame is written with TXDATAX however, the default value is overridden by the written value.

MPAB 0 RW

Multi-Processor Address-Bit

Defines the value of the multi-processor address bit. An incoming frame with its 9th bit equal to the value of this bit marks the frame as a multi-processor address frame.

MPM 0 Set to enable multi-processor mode.

RW

Multi-Processor Mode

Value 0 1 Description The 9th bit of incoming frames have no special function An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set SFUBRX 0 RW

Start-Frame UnBlock RX

Clears RXBLOCK when the start-frame is found in the incoming data. The start-frame is loaded into the receive buffer.

Value 0 1 LOOPBK Description Detected start-frames have no effect on RXBLOCK When a start-frame is detected, RXBLOCK is cleared and the start-frame is loaded into the receive buffer 0 RW Set to connect receiver to LEUn_TX instead of LEUn_RX.

Loopback Enable

Value 0 1 Value 0 1 Description The receiver is connected to and receives data from LEUn_RX The receiver is connected to and receives data from LEUn_TX ERRSDMA 0 RW

Clear RX DMA On Error

When set,RX DMA requests will be cleared on framing and parity errors.

Description Framing and parity errors have no effect on DMA requests from the LEUART RX DMA requests from the LEUART are disabled if a framing error or parity error occurs.

INV 0 RW Set to invert the output on LEUn_TX and input on LEUn_RX.

Invert Input And Output

Value 0 1 Description A high value on the input/output is 1, and a low value is 0.

A low value on the input/output is 1, and a high value is 0.

STOPBITS 0 RW

Stop-Bit Mode

Determines the number of stop-bits used. Only used when transmitting data. The receiver only verifies that one stop bit is present.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

386

www.silabs.com

Bit

3:2 1 0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Value 0 1 Mode ONE TWO Description One stop-bit is transmitted with every frame Two stop-bits are transmitted with every frame PARITY 0x0 RW

Parity-Bit Mode

Determines whether parity bits are enabled, and whether even or odd parity should be used.

Value 0 2 3 Mode NONE EVEN ODD RW Description Parity bits are not used Even parity are used. Parity bits are automatically generated and checked by hardware.

Odd parity is used. Parity bits are automatically generated and checked by hardware.

Data-Bit Mode

DATABITS 0 This register sets the number of data bits.

Value 0 1 Mode EIGHT NINE Description Each frame contains 8 data bits Each frame contains 9 data bits AUTOTRI 0 RW

Automatic Transmitter Tristate

When set, LEUn_TX is tristated whenever the transmitter is inactive.

Value 0 1 Description LEUn_TX is held high when the transmitter is inactive. INV inverts the inactive state.

LEUn_TX is tristated when the transmitter is inactive

17.5.2 LEUARTn_CMD - Command Register (Async Reg)

For more information about Asynchronous Registers please see Section 5.3 (p. 18) .

Offset

0x004

Reset Access Bit Position Name

6 5 4 3 2

Bit

31:8

7

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CLEARRX 0 W1 Set to clear receive buffer and the RX shift register.

CLEARTX 0 W1 Set to clear transmit buffer and the TX shift register.

Clear RX Clear TX

RXBLOCKDIS 0 W1

Receiver Block Disable

Set to clear RXBLOCK, resulting in all incoming frames being loaded into the receive buffer.

RXBLOCKEN 0 W1

Receiver Block Enable

Set to set RXBLOCK, resulting in all incoming frames being discarded.

TXDIS Set to disable transmission.

0 W1

Transmitter Disable

TXEN 0 Set to enable data transmission.

W1

Transmitter Enable

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

387

www.silabs.com

Bit

1 0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

RXDIS 0 W1

Receiver Disable

Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.

RXEN 0 Set to activate data reception on LEUn_RX.

W1

Receiver Enable 17.5.3 LEUARTn_STATUS - Status Register Bit Position Offset

0x008

Reset Access Name

1 0 4 3 2

Bit

31:6

5

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXDATAV 0 R

RX Data Valid

Set when data is available in the receive buffer. Cleared when the receive buffer is empty.

TXBL 1 R

TX Buffer Level

Indicates the level of the transmit buffer. Set when the transmit buffer is empty, and cleared when it is full.

TXC 0 R

TX Complete

Set when a transmission has completed and no more data is available in the transmit buffer. Cleared when a new transmission starts.

RXBLOCK 0 R

Block Incoming Data

When set, the receiver discards incoming frames. An incoming frame will not be loaded into the receive buffer if this bit is set at the instant the frame has been completely received.

TXENS 0 Set when the transmitter is enabled.

R

Transmitter Enable Status

RXENS 0 R

Receiver Enable Status

Set when the receiver is enabled. The receiver must be enabled for start frames, signal frames, and multi-processor address bit detection.

17.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg)

For more information about Asynchronous Registers please see Section 5.3 (p. 18) .

Offset

0x00C

Bit Position Reset Access Name

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

388

www.silabs.com

Bit

31:15

14:3

2:0

Preliminary

...the world's most energy friendly microcontrollers

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DIV 0x000 RW Specifies the fractional clock divider for the LEUART.

Reserved

Fractional Clock Divider

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

17.5.5 LEUARTn_STARTFRAME - Start Frame Register (Async Reg)

For more information about Asynchronous Registers please see Section 5.3 (p. 18) .

Bit Position Offset

0x010

Reset Access Name Bit

31:9

8:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

STARTFRAME 0x000 RW

Start Frame

When a frame matching STARTFRAME is detected by the receiver, STARTF interrupt flag is set, and if SFUBRX is set, RXBLOCK is cleared. The start-frame is be loaded into the RX buffer.

17.5.6 LEUARTn_SIGFRAME - Signal Frame Register (Async Reg)

For more information about Asynchronous Registers please see Section 5.3 (p. 18) .

Bit Position Offset

0x014

Reset Access Name Bit

31:9

8:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SIGFRAME 0x000 RW

Signal Frame

When a frame matching SIGFRAME is detected by the receiver, SIGF interrupt flag is set.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

389

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

17.5.7 LEUARTn_RXDATAX - Receive Buffer Data Extended Register Bit Position Offset

0x018

Reset Access Name Bit

31:16

15 14

13:9

8:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

FERR 0 R

Receive Data Framing Error

Set if data in buffer has a framing error. Can be the result of a break condition.

PERR 0 Set if data in buffer has a parity error.

Reserved

R

Receive Data Parity Error

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXDATA 0x000 R

RX Data

Use this register to access data read from the LEUART. Buffer is cleared on read access.

17.5.8 LEUARTn_RXDATA - Receive Buffer Data Register Bit Position Offset

0x01C

Reset Access Name Bit

31:8

7:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXDATA 0x00 R

RX Data

Use this register to access data read from LEUART. Buffer is cleared on read access. Only the 8 LSB can be read using this register.

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

390

www.silabs.com

Preliminary

...the world's most energy friendly microcontrollers

17.5.9 LEUARTn_RXDATAXP - Receive Buffer Data Extended Peek Register Offset

0x020

Bit Position Reset Access Name Bit

31:16

15 14

13:9

8:0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

FERRP 0 R

Receive Data Framing Error Peek

Set if data in buffer has a framing error. Can be the result of a break condition.

PERRP 0 Set if data in buffer has a parity error.

R

Receive Data Parity Error Peek

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXDATAP 0x000 R Use this register to access data read from the LEUART.

RX Data Peek 17.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register (Async Reg)

For more information about Asynchronous Registers please see Section 5.3 (p. 18) .

Offset

0x024

Bit Position Reset Access Name Bit

31:16

15 14

Name Reset Access Description

Reserved

RXENAT

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Set to enable reception after transmission.

W

Enable RX After Transmission

Value 0 1 TXDISAT 0 W

Disable TX After Transmission

Set to disable transmitter directly after transmission has competed.

Value 0 Description The receiver is enabled, setting RXENS after the frame has been transmitted Description 2015-03-16 - Happy Gecko Family - d0321_Rev0.91

391

www.silabs.com

Bit

13

12:9

8:0

Preliminary

...the world's most energy friendly microcontrollers

Name

Value 1

Reset Access Description

Description The transmitter is disabled, clearing TXENS after the frame has been transmitted TXBREAK 0 W

Transmit Data As Break

Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value of TXDATA.

Value 0 1 Description The specified number of stop-bits are transmitted Instead of the ordinary stop-bits, 0 is transmitted to generate a break. A single stop-bit is generated after the break to allow the receiver to detect the start of the next frame

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXDATA 0x000 W

TX Data

Use this register to write data to the LEUART. If the transmitter is enabled, a transfer will be initiated at the first opportunity.

17.5.11 LEUARTn_TXDATA - Transmit Buffer Data Register (Async Reg)

For more information about Asynchronous Registers please see Section 5.3 (p. 18) .

Offset

0x028

Bit Position Reset Access Name Bit

31:8

7:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXDATA 0x00 W

TX Data

This frame will be added to the transmit buffer. Only 8 LSB can be written using this register. 9th bit and control bits will be cleared.

17.5.12 LEUARTn_IF - Interrupt Flag Register Offset

0x02C

Reset Access Bit Position Name Bit

31:11

10 9 8

Name

Reserved

SIGF

Reset

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Set when a signal frame is detected.

STARTF 0 Set when a start frame is detected.

MPAF 0

Access

R R R

Description Signal Frame Interrupt Flag Start Frame Interrupt Flag Multi-Processor Address Frame Interrupt Flag

2015-03-16 - Happy Gecko Family - d0321_Rev0.91

392

www.silabs.com

Bit

7 6 5 4 3 2 1 0</