Silicon Labs Si5380 Revision D Reference Manual

Silicon Labs Si5380 Revision D  Reference Manual
RELATED DOCUMENTS
D
This Reference Manual is intended to provide system, PCB design, signal integrity, and
software engineers the necessary technical information to successfully use the Si5380
devices in end applications. The official device specifications can be found in the Si5380
datasheet.
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Si5380 Revision D Reference Manual
• Si5380 Data Sheet
• Si5380 Device Errata
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• Si5380-EVB User Guide
• Si5380-EVB Schematics, BOM & Layout
• IBIS models
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• To download evaluation board design and
support files, go to: Si534x/8x Evaluation
Kit
silabs.com | Building a more connected world.
Rev. 1.3
Table of Contents
1. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
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1.2 Si5380 LTE Frequency Configuration .
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. 5
1.3 Si5380 Configuration for JESD204B subclass 1 Clock Generation.
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. 7
1.4 DSPLL Loop Bandwidth . . .
1.4.1 Fastlock . . . . . . .
1.4.2 Holdover Exit Bandwidth .
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1.5 Dividers Overview .
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1.1 DSPLL.
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2.2 Free Run Mode .
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.14
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2.3 Lock Acquisition Mode .
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2.4 Locked Mode
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2.5 Holdover Mode .
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3. Clock Inputs (IN0, IN1, IN2, IN3)
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2.1 Reset and Initialization . . . . . . . . .
2.1.1 Updating Registers During Device Operation
2.1.2 Revision D . . . . . . . . . . . .
2.1.3 NVM Programming . . . . . . . . .
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2. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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.18
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3.2 Types of Inputs . . . . . . . . . . . .
3.2.1 Hitless Input Switching with Phase Buildout .
3.2.2 Ramped Input Switching . . . . . . .
3.2.3 Glitchless Input Switching . . . . . . .
3.2.4 Unused Inputs. . . . . . . . . . .
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3.1 Input Source Selection . . .
3.1.1 Manual Input Selection . .
3.1.2 Automatic Input Switching .
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3.3 Fault Monitoring . . . . . . . . . . . . . . . . . . . .
3.3.1 Input LOS (Loss-of-Signal) Detection . . . . . . . . . . . .
3.3.2 Reference Input LOSXAXB (Loss-of-Signal) Detection . . . . . .
3.3.3 Input OOF (Out-of-Frequency) Detection . . . . . . . . . . .
3.3.4 DSPLL LOL (Loss-of-Lock) Detection and the LOLb Output Indicator Pin
3.3.5 Device Status Monitoring . . . . . . . . . . . . . . . .
3.3.6 INTRb Interrupt Configuration . . . . . . . . . . . . . .
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4. Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1 Output Crosspoint Switch . . . . .
4.1.1 Output R Divider Synchronization .
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4.2 Performance Guidelines for Outputs .
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.37
4.3 Output Signal Format .
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.38
4.4 Output Driver Supply Select
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.39
silabs.com | Building a more connected world.
Rev. 1.3 | 2
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4.6 LVCMOS Outputs . . . . . . . . . . . . . . . .
4.6.1 LVCMOS Output Terminations . . . . . . . . . .
4.6.2 LVCMOS Output Impedance and Drive Strength Selection.
4.6.3 LVCMOS Output Signal Swing . . . . . . . . . .
4.6.4 LVCMOS Output Polarity . . . . . . . . . . . .
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4.7 Output Enable/Disable . . . . . . . . .
4.7.1 Output Driver State When Disabled . . .
4.7.2 Synchronous Output Enable/Disable Feature
4.7.3 Automatic Output Disable During LOL. . .
4.7.4 Automatic Output Disable During LOSXAXB
4.7.5 Output Driver Disable Source Summary . .
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4.8 Output Delay Control (Δt0 – Δt4) .
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4.5 Differential Outputs . . . . . . . . . . . . . . . . . . . .
4.5.1 Differential Output Terminations . . . . . . . . . . . . . . .
4.5.2 Differential Output Amplitude Controls. . . . . . . . . . . . .
4.5.3 Differential Output Common Mode Voltage Selection. . . . . . . .
4.5.4 Recommended Settings for Differential LVPECL, LVDS, HCSL, and CML
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5. Zero Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1 I2C Interface .
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6.2 SPI Interface.
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.59
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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7. Field Programming
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6. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8. XAXB External References
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8.1 Performance of External References
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8.2 Recommended Crystals and External Oscillators
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8.3 XAXB Control Register Settings . . . . . . . . . . .
8.3.1 XAXB_EXTCLK_EN Reference Clock Selection Register .
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9. Crystal and Device Circuit Layout Recommendations
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9.2 Si5381/82 64-Pin QFN with External XO Layout Recommendations .
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9.1 Si5380 Crystal Layout Guidelines.
10. Power Management
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. . . . . . . . . . . . . . . 67
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. . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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10.2 Power Supply Recommendations .
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10.3 Power Supply Sequencing
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10.4 Grounding Vias .
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10.1 Power Management Features
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11. Base vs. Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . 75
11.1 "Base" Devices (a.k.a. "Blank" Devices) .
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11.2 "Factory Preprogrammed" (Custom OPN) Devices .
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11.3 Part Numbering Summary.
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silabs.com | Building a more connected world.
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Rev. 1.3 | 3
12. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
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.76
12.2 Page 1 Registers.
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12.3 Page 2 Registers.
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12.4 Page 3 Registers .
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12.5 Page 4 Registers .
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. 104
12.6 Page 5 Registers .
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. 105
12.7 Page 9 Registers .
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. 113
12.8 Page A Registers
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12.9 Page B Registers
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D
13. Appendix—Custom Differential Amplitude Controls
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12.1 Page 0 Registers.
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14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
silabs.com | Building a more connected world.
Rev. 1.3 | 4
Si5380 Revision D Reference Manual
Functional Description
1. Functional Description
1.1 DSPLL
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The DSPLL provides the synthesis for generating the output clock frequencies which are synchronous to the selected input clock frequency or freerun from the XTAL. It consists of a phase detector, a programmable digital loop filter, a high-performance ultra-lowphase-noise analog 14.7456 GHz VCO, and a user configurable feedback divider. An internal oscillator (OSC) provides the DSPLL with
a stable low-noise clock source for frequency synthesis and for maintaining frequency accuracy in the Freerun or Holdover modes. The
oscillator simply requires an external, low cost 54 MHz fundamental mode crystal to operate. No other external components are required for oscillation. A key feature of DSPLL is providing immunity to external noise coupling from power supplies and other uncontrolled noise sources that normally exist on printed circuit boards.
The frequency configuration of the DSPLL is programmable through the SPI or I2C serial interface and can also be stored in non-volatile memory (NVM) or RAM. The combination of integer input dividers (P0-P3), Integer frequency multiplication (M), Integer output division (N), and integer output division (R0A-R9A) allows the generation of a wide range of frequencies on any of the outputs. All divider
values for a specific frequency plan are easily determined using the ClockBuilder Pro software.
D
1.2 Si5380 LTE Frequency Configuration
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The device’s frequency configuration is fully programmable through the serial interface and can also be stored in non-volatile memory.
The flexible combination of integer dividers and a high frequency VCO allows the device to generate multiple output clock frequencies
for applications that require ultra-low phase-noise and spurious performance. At the core of the device are the N dividers which determine the number of unique frequencies that can be generated from the device. The table below shows a list of possible output frequencies for LTE applications. The Si5380’s DSPLL core can generate up to five unique frequencies. These frequencies are distributed to
the output dividers using a configurable crosspoint mux. The R dividers allow further division for up to 10 unique integer related frequencies on the Si5380. The ClockBuilder Pro software utility provides a simple means of automatically calculating the optimum divider
values (P, M, N and R) for the frequencies listed below.
Table 1.1. Example List of Possible LTE Clock Frequencies
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Fin (MHz)1
15.36
19.20
19.20
30.72
30.72
38.40
38.40
61.44
61.44
76.80
76.80
122.88
122.88
153.60
153.60
184.32
184.32
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15.36
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LTE Device Clock Fout (MHz)2
245.76
245.76
307.20
307.20
368.64
368.64
491.52
491.52
614.40
614.40
737.28
737.28
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983.04
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1228.80
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1474.56
silabs.com | Building a more connected world.
Rev. 1.3 | 5
Si5380 Revision D Reference Manual
Functional Description
Fin (MHz)1
LTE Device Clock Fout (MHz)2
Notes:
1. The Si5380 locks to any one of the frequencies listed in the Fin column and generates LTE device clock frequencies.
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2. R output dividers allow other frequencies to be generated. These are useful for applications like JESD204B SYSREF clocks.
silabs.com | Building a more connected world.
Rev. 1.3 | 6
Si5380 Revision D Reference Manual
Functional Description
1.3 Si5380 Configuration for JESD204B subclass 1 Clock Generation
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The Si5380 can be used as a high-performance, fully-integrated JEDEC JESD204B jitter cleaner while eliminating the need for discrete
VCXO and loop filter components. The Si5380 supports JESD204B subclass 0 and subclass 1 clocking by providing both device clocks
(DCLK) and system reference clocks (SYSREF). The 12 clock outputs can be independently configured as device clocks or SYSREF
clocks to drive JESD204B ADCs, DACs, FPGAs, or other logic devices. The Si5380 will clock up to six JESD204B subclass 1 targets,
using six DCLK/SYSREF pairs. If SYSREF clocking is implemented in external logic, then the Si5380 can clock up to 12 JESD204B
targets. Not limited to JESD204B applications, each of the 12 outputs is individually configurable as a high performance output for traditional clocking applications.
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D
For applications which require adjustable static delay between the DCLK and SYSREF signals, the Si5380 supports up to four DCLK/
SYSREF pairs, each with independently adjustable delay. An example of an adjustable delay JESD204B frequency configuration is
shown in the following figure. In this case, the N0 divider determines the device clock frequencies while the N1-N4 dividers generate the
divided SYSREF used as the lower frequency frame clock. Each output N divider also includes a configurable delay (Δt) for controlling
deterministic latency. This example shows a configuration where all the device clocks are controlled by a single delay (Δt0) while the
SYSREF clocks each have their own independent delay (Δt1 – Δt4), though other combinations are also possible. The bidirectional
delay is programmable over ±8.6 ns in 68 ps steps. See 4.8 Output Delay Control (Δt0 – Δt4) for more information on delay control. The
SYSREF clock is always periodic and can be controlled (on/off) without glitches by enabling or disabling its output through register
writes.
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Functional Description
Si5380
IN_SEL[1:0]
IN1
IN1b
IN2
IN2b
IN3/FB_IN
IN3b/FB_INb
÷P0
DSPLL
÷P1
PD
÷P2
÷P3
LPF
÷M
÷5
VDDO0
÷R0
OUT0
OUT0b
÷R5
VDDO5
OUT5
OUT5b
÷R6
VDDO6
OUT6
OUT6b
÷R7
VDDO7
OUT7
OUT7b
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t0
÷R8
VDDO8
OUT8
OUT8b
÷R9
OUT9
OUT9b
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÷R9A
Device
Clocks
OUT9A
OUT9Ab
VDDO9
÷N1
t1
÷R1
VDDO1
OUT1
OUT1b
÷N2
t2
÷R2
VDDO2
OUT2
OUT2b
÷N3
t3
÷R3
VDDO3
OUT3
OUT3b
÷N4
t4
÷R4
VDDO4
OUT4
OUT4b
SYSREF
Clocks
Figure 1.1. Si5380 Block Diagram
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OUT0A
OUT0Ab
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÷N0
÷R0A
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IN0
IN0b
1.4 DSPLL Loop Bandwidth
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The DSPLL loop bandwidth determines the amount of input clock jitter attenuation and wander filtering. Register configurable DSPLL
loop bandwidth settings in the range of 0.1 Hz to 100 Hz are available for selection. Since the loop bandwidth is controlled digitally, the
DSPLL will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection. The DSPLL loop bandwidth register values are determined using ClockBuilder Pro. Note that after manually changing bandwidth parameters, the BW_UPDATE bit must be set high to latch the new values into operation. Note that this update bit will latch the new values for Loop, Fastlock,
and Holdover Exit bandwidths simultaneously.
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Si5380 Revision D Reference Manual
Functional Description
Table 1.2. DSPLL Loop Bandwidth Registers
Register Name
Hex Address
Function
[Bit Field]
0x0508[7:0]-0x050D[7:0]
Determines the loop BW for the DSPLL.
Parameters are generated by ClockBuilder
Pro.
BW_UPDATE
0x0514[0]
Writing a 1 to this register bit will latch
Loop, Fastlock, and Holdover Exit BW parameter registers.
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BW_PLL
1.4.1 Fastlock
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Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The Fastlock feature allows setting
a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process to reduce lock time. Higher Fastlock loop bandwidth settings will enable the DSPLLs to lock faster. Fastlock Bandwidth settings in the range from 100 Hz up to 4 kHz are available for
selection. Once lock acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth
setting. The Fastlock feature can be enabled or disabled independently by register control. If enabled, when LOL is asserted Fastlock
will be automatically enabled. When LOL is no longer asserted, Fastlock will be automatically disabled. Note that this update bit will
latch new values for Loop, Fastlock, and Holdover Exit bandwidths simultaneously.
Register Name
Hex Address
[Bit Field]
FASTLOCK_AUTO_EN
0x052B[0]
0x052B[1]
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FASTLOCK_MAN
0x050E[7:0]-0x0513[7:0]
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FASTLOCK_BW_PLL
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Table 1.3. DSPLL Fastlock Bandwidth Registers
Function
Determines the Fastlock BW for the DSPLL. Parameters
are generated by ClockBuilder Pro.
Auto Fastlock Enable/Disable.
0: Disable Auto Fastlock (default)
1: Enable Auto Fastlock
Force Fastlock.
0: Normal Operation (default)
1: Force Fastlock
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The loss of lock (LOL) feature is a fault monitoring mechanism. Details of the LOL feature can be found in 3.3.4 DSPLL LOL (Loss-ofLock) Detection and the LOLb Output Indicator Pin.
1.4.2 Holdover Exit Bandwidth
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In additional to the Loop and Fastlock bandwidths, a user-selectable bandwidth is available when exiting holdover and locking or relocking to an input clock when ramping is disabled (HOLD_RAMP_BYP = 1). CBPro sets this value equal to the Loop bandwidth by default.
Note that the BW_UPDATE bit will latch new values for Loop, Fastlock, and Holdover bandwidths simultaneously.
Table 1.4. DSPLL Holdover Exit Bandwidth Registers
Register Name
HOLDEXIT_BW
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Hex Address
Function
[Bit Field]
0x059D[7:0]–0x05A2
Determines the Holdover Exit BW for the
DSPLL. Parameters are generated by
ClockBuilder Pro.
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Si5380 Revision D Reference Manual
Functional Description
1.5 Dividers Overview
There are four divider classes within the Si5380. Figure 1.1 Si5380 Block Diagram on page 8 shows all of these dividers. All divider
values for the Si5380 are Integer-only.
• P0-P3: Input clock wide range dividers (0x0208–0x022F)
• 48-bit numerator, 32-bit denominator
• Min. value is 1; Max. value is 224.
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• Practical range limited by phase detector and VCO range
• Each divider has an update bit that must be written to cause a newly written divider value to take effect.
• M: DSPLL feedback divider (0x0515–0x051F)
• 56-bit numerator, 32-bit denominator
• Min. value is 5, Max. value is 224
Practical range limited by phase detector and VCO range
The M divider has an update bit that must be written to cause a newly written divider value to take effect.
Soft Reset will also update M divider values.
The DSPLL includes an additional divide-by-5 in the feedback path. Manually calculated M divider register values must be adjusted accordingly.
• N: Output divider (0x0302-0x0338)
• 44-bit numerator, 32-bit denominator
• Min. value is 10, Max. value is 224
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•
•
•
•
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• Each N divider has an update bit that must be written to cause a newly written divider value to take effect.
• Soft Reset will also update N divider values.
• R: Final output divider (0x0247-0x026A)
• 24-bit field
• Min. value is 2, Max. value is 225-2
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• Only even integer divide values: 2,4,6, etc.
• R Divisor=2 x (Field +1). For example, Field=3 gives an R divisor of 8.
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Si5380 Revision D Reference Manual
Modes of Operation
2. Modes of Operation
After initialization, the DSPLL will operate in one of the following modes: Free-run, Lock-Acquisition, Locked, or Holdover. These modes
are described further in the sections below.
No valid
input clocks
selected
Free-run
Valid input clock
selected
Phase lock on
selected input
clock is achieved
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Locked
Mode
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Selected input
clock fails
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Holdover
Mode
No
Is holdover
history valid?
Lock Acquisition
(Fast Lock)
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An input is qualified
and available for
selection
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Reset and
Initialization
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Power-Up
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Figure 2.1. Modes of Operation
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Si5380 Revision D Reference Manual
Modes of Operation
2.1 Reset and Initialization
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from
NVM and performs other initialization tasks. Communicating with the device through the SPI or I2C serial interface is possible once this
initialization period is complete. No clocks will be generated until the initialization is complete.
Table 2.1. Reset Registers
Register Name
Hex Address
Function
[Bit Field]
SOFT_RST
0x001C[0]
Hard Reset bit
asserted
Writing a 1 to this register bit performs a
Soft Reset of the device. Initiates register
configuration changes without reloading
NVM.
RSTb
pin asserted
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Power-Up
Writing a 1 to this register bit performs the
same function as power cycling the device.
All registers will be restored to their NVM
values.
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0x001E[1]
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HARD_RST
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There are two types of resets available. A Hard Reset is functionally similar to a device power-up. All registers will be restored to the
values stored in NVM, and all circuits including the serial interface, will be restored to their initial state. A Hard Reset is initiated using
the RSTb pin or by asserting the Hard Reset bit. A Soft Reset bypasses the NVM download and is used to initiate register configuration
changes. The table below lists the reset and control registers.
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NVM download
Soft Reset bit
asserted
Initialization
Serial interface ready
Figure 2.2. Initialization from Hard Reset and Soft Reset
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The Si5380 is fully configurable using the serial interface (I2C or SPI). At power up the device downloads its default register values from
internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate
specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply
voltages applied to its VDD and VDDA pins.
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Si5380 Revision D Reference Manual
Modes of Operation
2.1.1 Updating Registers During Device Operation
If certain registers are changed while the device is in operation, it is possible for the PLL to become unresponsive (i.e. lose lock indefinitely). The following are the affected registers:
Register(s)
P0_NUM / P0_DEN
0x0208 – 0x0211
P1_NUM / P1_DEN
0x0212 – 0x021B
P2_NUM / P2_DEN
0x021C – 0x0225
P3_NUM / P3_DEN
0x0226 – 0x022F
MXAXB_NUM / MXAXB_DEN
0x0235 – 0x023E
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Control
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PLL lockup can easily be avoided by using following the preamble and postamble write sequence when one of these registers is modified during device operation. ClockBuilder Pro software adds these writes to the output file by default when Exporting Register Files.
1. First, the preamble.
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Write 0x0B24 = 0xD8
Write 0x0B25 = 0x00
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Write 0x0540 = 0x01 (NOTE: for all new designs it is recommend that this register be written as part of the preamble. In some rare
cases, omitting this write may result in a one-time LOL occurrence. However, if this issue has not occurred with your current frequency plan it is not likely to occur)
2. Wait 625 ms.
3. Then perform the desired register modifications.
4. Write SOFT_RST 0x001C[0] = 1.
5. Write the post-amble.
Write 0x0B24 = 0xDB
Write 0x0B25 = 0x02
2.1.2 Revision D
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Write 0x0540 = 0x00 (NOTE: for all new designs it is recommend that this register be written as part of the post-amble. In some
rare cases, omitting this write may result in a one-time LOL occurrence. However, if this issue has not occurred with your current
frequency plan it is not likely to occur)
The revision D preamble and postamble values for updating certain registers during device operation have changed after revision B.
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Either the new or old values below may be written to revision D or later devices without issue. No system software changes are necessary for legacy systems. When writing old values, note that reading back these registers will not give the written old values, but will
reflect the new values. Silicon Labs recommends using the new values for all revision D and later designs, since the write and read
values will match.
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The device revision can be determined in the setting DEVICE_REV, register 0x0005.
DEVICE_REV = 0x02 or higher: New Values
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Revision D Preamble: 0x0B24 = 0xC0, 0x0B25 = 0x00
Revision D Postamble: 0x0B24 = 0xC3, 0x0B25 = 0x02
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Note that revision B and earlier devices must continue to use the original values for these registers:
DEVICE_REV = 0x00 or 0x01: Old Values
Revision B Preamble: 0x0B24 = 0xD8, 0x0B25 = 0x00
Revision B Postamble: 0x0B24 = 0xDB, 0x0B25 = 0x02
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Modes of Operation
2.1.3 NVM Programming
The NVM is two-time writable for a base part (no set frequency plan) and one-time writable for a part with a factory pre-programmed
frequency plan. Once a new configuration has been written to NVM, the old configuration is no longer accessible.
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While polling DEVICE_READY during the procedure below, the following conditions must be met in order to ensure that the correct
values are written into the NVM:
• VDD and VDDA power must both be stable throughout the process.
• No additional registers may be written during the polling. This includes the page register at address 0x01. DEVICE_READY is available on every register page, so no page change is needed to read it.
• Only the DEVICE_READY register (0xFE) may be read during this time.
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The procedure for writing registers into NVM is as follows:
1. Write all registers as needed. Verify device operation before writing registers to NVM.
2. You may write to the user scratch space (registers 0x026B to 0x0272) to identify the contents of the NVM bank.
3. Write 0xC7 to NVM_WRITE register.
4. Poll DEVICE_READY until DEVICE_READY=0x0F.
5. Set NVM_READ_BANK 0x00E4[0]=1.
6. Poll DEVICE_READY until DEVICE_READY=0x0F.
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Alternatively, Steps 5 and 6 can be replaced with a Hard Reset, either by RSTb pin, HARD_RST register bit, or power cycling the device to generate a POR. All of these actions will load the new NVM contents back into the device registers.
Table 2.2. NVM Programming Registers
Hex Address
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Register Name
Function
[Bit Field]
NVM_WRITE
0x00E2[7:0]
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ACTIVE_NVM_BANK
0x00E3[7:0]
Identifies the active NVM bank.
Initiates an NVM write when written with
value 0xC7.
NVM_READ_BANK
0x00E4[0]
Download register values with content stored in NVM.
DEVICE_READY
0x00FE[7:0]
Indicates that the device is ready to accept
commands when value = 0x0F.
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WARNING: Any attempt to read or write any register other than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt
the NVM programming. This includes writes to the PAGE register.
2.2 Free Run Mode
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Once power is applied and initialization is complete, the DSPLL will automatically enter Freerun mode, generating the output frequencies determined by the NVM. The frequency accuracy of the generated output clocks in Freerun mode is entirely dependent on the
frequency accuracy of the external crystal or reference clock on the XAXB pins. For example, if the crystal frequency is ±100 ppm, then
all the output clocks will be generated at their configured frequency ±100 ppm in Freerun mode. Any drift of the crystal frequency will be
tracked at the output clock frequencies. A TCXO or OCXO is recommended for applications that need better frequency accuracy and
stability while in Freerun or Holdover modes. Because there is little or no jitter attenuation from the XAXB pins to the clock outputs, a
low-jitter XAXB source is needed for low-jitter clock outputs.
2.3 Lock Acquisition Mode
The device monitors all inputs for a valid clock. If at least one valid clock is available for synchronization, the DSPLL will automatically
start the lock acquisition process. If the Fastlock feature is enabled, the DSPLL will acquire lock using the Fastlock Loop Bandwidth
setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs
will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency.
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Modes of Operation
2.4 Locked Mode
Once locked, the DSPLL will generate output clocks that are both frequency and phase locked to its selected input clock. At this point
any XTAL frequency drift will typically not affect the output frequency. A loss of lock pin (LOLb) and status bit indicate when lock is
achieved. See 3.3.4 DSPLL LOL (Loss-of-Lock) Detection and the LOLb Output Indicator Pin for more details on the operation of the
loss of lock circuit.
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2.5 Holdover Mode
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The DSPLL will automatically enter Holdover mode when the selected input clock becomes invalid and no other valid input clocks are
available for selection. It uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit stores up to 120 seconds of historical frequency
data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window within
the stored historical frequency data. Both the window size and the delay are programmable as shown in the figure below. The window
size determines the amount of holdover frequency averaging. This delay value allows recent frequency information to be ignored for
Holdover in cases where the input clock source frequency changes as it is removed.
Clock Failure
and Entry into
Holdover
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Historical Frequency Data Collected
Programmable historical data window
used to determine the final holdover value
120s
Programmable delay
30ms, 60ms, 1s,10s, 30s, 60s
0s
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1s,10s, 30s, 60s
time
Figure 2.3. Programmable Holdover Window
When entering Holdover, the DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in Holdover, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XAXB pins. If
the clock input becomes valid, the DSPLL will automatically exit the Holdover mode and re-acquire lock to the new input clock. This
process involves pulling the output clock frequency to achieve frequency and phase lock with the input clock. This pull-in process is
Glitchless and its rate is controlled by the DSPLL bandwidth or the Fastlock bandwidth, if Fastlock is enabled. These options are register programmable.
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The recommended mode of exit from holdover is a ramp in frequency. Just before the exit begins, the frequency difference between the
output frequency while in holdover and the desired, new output frequency is measured. It is quite possible (even likely) that the new
output clock frequency will not be the same as the holdover output frequency because the new input clock frequency might have
changed and the holdover history circuit may have changed the holdover output frequency. The ramp logic calculates the difference in
frequency between the holdover frequency and the new, desired output frequency. Using the user selected ramp rate, the correct ramp
time is calculated. The output ramp rate is then applied for the correct amount of time so that when the ramp ends, the output frequency
will be the desired new frequency. Using the ramp, the transition between the two frequencies is smooth and linear. The ramp rate can
be selected to be very slow (0.2 ppm/sec), very fast (40,000 ppm/sec) or any of approximately 40 values that are in between. The loop
BW values do not limit or affect the ramp rate selections and vice versa. CBPro defaults to ramped exit from holdover. Ramped exit
from holdover is also used for ramped input clock switching. See 3.2.2 Ramped Input Switching for more information.
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As shown in Figure 2.1 Modes of Operation on page 11 the Holdover and Freerun modes are closely related. The device will only enter
Holdover if a valid clock has been selected long enough for the holdover history to become valid, i.e., HOLD_HIST_VALID = 1. If the
clock fails before the combined HOLD_HIST_LEN + HOLD_HIST_DELAY time has been met, HOLD_HIST_VALID = 0 and the device
will enter Freerun mode instead. Reducing the HOLD_HIST_LEN and HOLD_HIST_DELAY times will allow Holdover in less time, limited by the source clock failure and wander characteristics. Note that the Holdover history accumulation is suspended when the input
clock is removed and resumes accumulating when a valid input clock is again presented to the DSPLL.
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Modes of Operation
Table 2.3. Holdover Mode Control Registers
Register Name
Hex Address
Function
[Bit Field]
HOLD
0x000E[5]
DSPLL Holdover status indicator.
0: Normal Operation
1: In Holdover/Freerun Mode:
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Holdover Status
HOLD_HIST_VALID = 0 ≥ Freerun Mode
HOLD_HIST_VALID = 1 ≥ Holdover Mode
0x0013[5]
Holdover indicator sticky flag bit. Remains asserted after the indicator bit shows a fault until cleared by the user. Writing a 0 to the
flag bit will clear it if the indicator bit is no longer asserted.
HOLD_INTR_MSK
0x0019[5]
Masks Holdover/Freerun from generating INTRb interrupt.
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HOLD_FLG
0: Allow Holdover/Freerun interrupt (default)
1: Mask (ignore) Holdover/Freerun for interrupt
0x053F[1]
Holdover historical frequency data valid.
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HOLD_HIST_VALID
0: Incomplete Holdover history, Freerun mode available
1: Valid Holdover history, Holdover mode available
HOLD_HIST_LEN
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Holdover Control and Settings
0x052E[4:0]
Window Length time for historical average frequency used in
Holdover mode. Window Length in seconds (s):
Window Length = (2HOLD_HIST_LEN - 1) x 8 / 3 x 10-7
HOLD_HIST_DELAY
0x052F[4:0]
Delay Time to ignore data for historical average frequency in
Holdover mode. Delay Time in seconds (s):
Delay Time = 2HOLD_HIST_DELAY x 2 / 3 x 10-7
0x0535[0]
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FORCE_HOLD
0: Normal Operation
1: Force Holdover/Freerun Mode:
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Force the device into Holdover mode. Used to hold the device
output clocks while retraining an upstream input clock.
HOLD_HIST_VALID = 0 =>Freerun Mode
HOLD_HIST_VALID = 1 =>Holdover Mode
Holdover Exit Control
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HOLD_RAMP_BYP
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0x052C[3]
Holdover Exit Ramp Bypass
0: Use Ramp when exiting from Holdover (default)
1: Use Holdover/Fastlock/Loop bandwidth when exiting from Holdover
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Si5380 Revision D Reference Manual
Modes of Operation
Register Name
Hex Address
Function
[Bit Field]
HOLDEXIT_BW_SEL0
0x059B[6]
Select the exit bandwidth from Holdover when ramped exit is not
selected (HOLD_RAMP_BYP = 1).
00: Use Fastlock bandwidth on Holdover exit
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01: Use Holdover Exit bandwidth on Holdover exit (default)
10, 11: Use Normal Loop bandwidth on Holdover exit
HOLDEXIT_BW_SEL1
0x052C[4]
Select the exit bandwidth from Holdover when ramped exit is not
selected (HOLD_RAMP_BYP = 1).
00: Use Fastlock bandwidth on Holdover exit
01: Use Holdover Exit bandwidth on Holdover exit (default)
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10, 11: Use Normal Loop bandwidth on Holdover exit
0x052C[7:5]
Time Interval of the frequency ramp steps when ramping between
inputs or exiting holdover.
RAMP_STEP_SIZE
0x05A6[2:0]
Size of the frequency ramp steps when ramping between inputs
or exiting holdover.
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RAMP_STEP_INTERVAL
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Clock Inputs (IN0, IN1, IN2, IN3)
3. Clock Inputs (IN0, IN1, IN2, IN3)
3.1 Input Source Selection
Table 3.1. Input Selection Control Registers
Register Name
Hex Address
Function
[Bit Field]
0x0536[1:0]
Selects manual or automatic switching
modes. Automatic mode can be Revertive
or Non-revertive.
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CLK_SWITCH_MODE
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The inputs accept both standard format inputs and low-duty-cycle Pulsed CMOS clocks. Input selection from CLK_SWITCH_MODE
can be manual (pin or register controlled) or automatic with user definable priorities. Register 0x052A is used to select manual pin or
register control, and to configure the input as shown in the table below.
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0: Manual (default), 1: Automatic Non-revertive,
2: Automatic Revertive, 3: Reserved
IN_SEL_REGCTRL
0x052A[0]
Manual Input Select control source.
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0: Pin controlled input clock selection (default)
.
3.1.1 Manual Input Selection
0x052A[3:1]
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IN_SEL
1: IN_SEL register input clock selection
Manual Input Select selection register.
0: IN0 (default), 1: IN1, 2: IN2, 3: IN3/
FB_IN, 4-7: Reserved
In manual mode, CLK_SWITCH_MODE=0x00.
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Input switching can be done manually using the IN_SEL[1:0] device pins from the package or through register 0x052A IN_SEL[2:1]. Bit
0 of register 0x052A determines if the input selection is pin selectable or register selectable. The default is pin selectable. The following
table describes the input selection on the pins. Note that when Zero Delay Mode is enabled, the FB_IN pins will become the feedback
input and IN3 therefore is not available as a clock input. If there is not a valid clock signal on the selected input, the device will automatically enter Freerun or Holdover mode. See 5. Zero Delay Mode for further information.
Table 3.2. Manual Input Selection using IN_SEL[1:0] Pins
DSPLL Input Source
00
IN0
01
IN1
10
IN2
11
IN31
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IN_SEL[1:0] PINS
Note:
1. IN3 not available as a DSPLL source in ZDM.
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Clock Inputs (IN0, IN1, IN2, IN3)
3.1.2 Automatic Input Switching
In automatic mode CLK_SWITCH_MODE = 0x01 (Non-revertive) or 0x02 (Revertive).
Table 3.3. Automatic Input Switching Registers
Register Name
Hex Address
Function
0x0536[1:0]
Selects manual or automatic switching
modes. Automatic mode can be Revertive
or Non-revertive. Selections are the following:
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CLK_SWITCH_MODE
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[Bit Field]
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Automatic input switching is available in addition to the manual selection described previously in 3.1.1 Manual Input Selection . In automatic mode, the switching criteria is based on input clock qualification, input priority and the revertive option. The IN_SEL[1:0] pins and
IN_SEL 0x052A[3:1] register bits are not used in automatic input switching. Also, only input clocks that are valid (i.e., with no active fault
indicators) can be selected by the automatic clock switching. If there are no valid input clocks available, the DSPLL will enter Holdover
or Freerun mode. With Revertive switching enabled, the highest priority input with a valid input clock is always selected. If an input with
a higher priority becomes valid then an automatic switchover to that input will be initiated. With Non-revertive switching, the active input
will always remain selected while it is valid. If it becomes invalid, an automatic switchover to the highest priority valid input will be initiated. Note that automatic input switching is not available in Zero Delay Mode. See section 5. Zero Delay Mode for further information.
00: Manual (default), 01: Automatic Non-revertive,
02: Automatic Revertive, 03: Reserved
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IN_OOF_MSK
0x0537[3:0]
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IN_LOS_MSK
0x0537[7:4]
Enables the use of IN3 - IN0 LOS status in
determining a valid clock for automatic input selection.
0: Use LOS in automatic clock switching
logic (default)
1: Mask (ignore) LOS from the automatic
clock switching logic
Determines the OOF status for IN3 - IN0
and is used in determining a valid clock for
the automatic input selection.
0: Use OOF in the automatic clock switching logic (default)
1: Mask (ignore) OOF from the automatic
clock switching logic
0x0538[2:0]
IN1_PRIORITY
0x0538[6:4]
IN0 - IN3 priority assignment for the automatic switching state machine. Priority assignments in descending importance are:
IN2_PRIORITY
0x0539[2:0]
1, 2, 3, 4, or 0 for never selected
IN3_PRIORITY
0x0539[6:4]
5-7: Reserved
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IN0_PRIORITY
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Clock Inputs (IN0, IN1, IN2, IN3)
3.2 Types of Inputs
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Each of the four different inputs IN0-IN3/FB_IN can be configured as standard LVDS, LVPECL, HCL, CML, and single-ended LVCMOS
formats, or as a low duty cycle pulsed CMOS format. The standard format inputs have a nominal 50% duty cycle, must be ac-coupled
and use the “Standard” Input Buffer selection as these pins are internally dc biased to approximately 0.83 V. The pulsed CMOS input
format allows pulse-based inputs, such as frame-sync and other synchronization signals, having a duty cycle much less than 50%.
These pulsed CMOS signals are dc-coupled and use the “Pulsed CMOS” Input Buffer selection. In all cases, the inputs should be terminated near the device input pins as shown in the figure below. The resistor divider values given below will work with up to 1 MHz pulsed
inputs. In general, following the “Standard AC Coupled Single Ended” arrangement shown below will give superior jitter performance
over Pulsed CMOS.
Standard AC Coupled Differential LVDS
50
100
3.3V, 2.5V
LVDS or
CML
INx
Si5380 Rev D
Standard
INxb
D
50
N
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Pulsed CMOS
Standard AC Coupled Differential LVPECL
50
INx
100
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INxb
50
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3.3V, 2.5V
LVPECL
Si5380 Rev D
Standard
Pulsed CMOS
Standard AC Coupled Single Ended
50
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3.3V, 2.5V, 1.8V
LVCMOS
INx
Si5380 Rev D
Standard
INxb
Pulsed CMOS
Pulsed CMOS DC Coupled Single Ended
Si5380 Rev D
R1
INx
50
R2
3.3V, 2.5V, 1.8V
LVCMOS
VDD
Resistor values for
fIN_PULSED < 1MHz
1.8V
2.5V
3.3V
R1 (W)
324
511
634
R2 (W)
665
475
365
Standard
INxb
Pulsed CMOS
Figure 3.1. Input Termination for Standard and Pulsed CMOS Inputs
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Clock Inputs (IN0, IN1, IN2, IN3)
Input clock buffers are enabled by setting the IN_EN 0x0949[3:0] bits appropriately for IN3 through IN0. Unused clock inputs may be
powered down and left unconnected at the system level. For standard mode inputs, both input pins must be properly connected as
shown in the figure above, including the “Standard AC Coupled Single Ended” case. In Pulsed CMOS mode, it is not necessary to
connect the inverting INb input pin. To place the input buffer into Pulsed CMOS mode, the corresponding bit must be set in
IN_PULSED_CMOS_EN 0x0949[7:4] for IN3 through IN0.
Table 3.4. Input Clock Configuration Registers
Hex Address
Function
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Register Name
[Bit Field]
IN_EN
0x0949[3:0]
Enable (or powerdown) the IN3 – IN0 input buffers.
0: Powerdown input buffer
1: Enable and Power-up input buffer
0x0949[7:4]
Select Pulsed CMOS input buffer for IN3 – IN0.
0: Standard Input Format
D
IN_PULSED_CMOS_EN
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1: Pulsed CMOS Input Format
3.2.1 Hitless Input Switching with Phase Buildout
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Phase buildout is a feature that prevents the phase of an output clock from changing when switching to a new input clock that does not
have the same phase as the original input clock. It only makes sense to enable phase buildout when switching between two clocks that
are exactly the same frequency (i.e. are frequency locked). When hitless switching phase buildout is enabled (register 0x0536[2] = 1),
the DSPLL absorbs the phase difference between the current input clock and the new input clock. When disabled (register 0x0536[2] =
0), the phase difference between the two input clocks will propagate to the output at a rate that is determined by the DSPLL loop bandwidth. Phase buildout hitless switching supports clock frequencies down to the minimum input frequency. Note that Hitless switching is
not available in Zero Delay Mode.
Table 3.5. Input Hitless Switching
Register Name
Hex Address
Function
[Bit Field]
HSW_EN
0x0536[2]
Enable Hitless Switching.
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0: Disable Hitless switching
0x05A6[3]
Enable Ramped Input Switching when HOLD_RAMP_BYP = 0.
0: Disable Ramped Input switching
1: Enable Ramped Input switching (default)
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RAMP_SWITCH_EN
1: Enable Hitless switching (phase buildout enabled) (default)
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Clock Inputs (IN0, IN1, IN2, IN3)
3.2.2 Ramped Input Switching
The DSPLL has the ability to switch between two input clock frequencies that are up to ±20 ppm apart. When switching between input
clocks that are not exactly the same frequency (i.e. are plesiochronous), ramped switching should be enabled to ensure a smooth transition between the two input frequencies. In this situation, it is also advisable to enable hitless switching phase buildout to minimize the
input-to-output clock skew after the clock switch ramp has completed.
Register Name
Hex Address
Function
HOLD_RAMP_BYP
0x052C[3]
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[Bit Field]
D
Table 3.6. Ramped Switching Controls
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When ramped clock switching is enabled, the DSPLL will very briefly go into holdover and then immediately exit from holdover. This
means that ramped switching will behave the same as an exit from holdover. This is particularly important when switching between two
input clocks that are not the same frequency because the transition between the two frequencies will be smooth and linear. Ramped
switching should be turned off when switching between input clocks that are always frequency locked (i.e. are the same exact frequency). Because ramped switching avoids frequency transients and over shoot when switching between clocks that are not the same frequency, CBPro defaults to ramped clock switching. The same ramp rate settings are used for both exit from holdover and clock switching. For more information on ramped exit from holdover, see 2.5 Holdover Mode.
Holdover Exit Ramp Bypass
0: Use Ramp when exiting from Holdover (default)
1: Use Holdover/Fastlock/Loop bandwidth when exiting from Holdover
RAMP_STEP_SIZE
0x05A6[2:0]
Time Interval of the frequency ramp steps when ramping between
inputs or exiting holdover. Set by CBPro.
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0x052C[7:5]
Size of the frequency ramp steps when ramping between inputs
or exiting holdover. Set by CBPro.
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RAMP_STEP_INTERVAL
3.2.3 Glitchless Input Switching
The DSPLL glitchlessly switches between two input clock frequencies that are up to ±20 ppm apart. The DSPLL will pull-in to the new
frequency at a rate determined by either DSPLL loop bandwidth or, if enabled, the Fastlock bandwidth. Depending on the LOL configuration settings, the loss of lock (LOL) indicator may assert while the DSPLL is pulling-in to the new clock frequency. However, there will
never be abnormally shortened “runt” pulses generated at the output during this transition.
3.2.4 Unused Inputs
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Unused inputs can be disabled and left unconnected when not in use. Register 0x0949[3:0] defaults the input clocks to being enabled.
Clearing the bits for unused inputs will power down those inputs. For inputs that are enabled but have an inactive clock source, a weak
pullup or pulldown resistor may be added to minimize noise pickup.
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Si5380 Revision D Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)
3.3 Fault Monitoring
The four input clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF). Note that the reference at the XAXB pins is also monitored for LOS since it provides a critical reference clock for the DSPLL. There is also a Loss of Lock
(LOL) indicator asserted when the DSPLL loses synchronization within the feedback loop. The figure below shows the fault monitors for
each input path going into the DSPLL, which includes the crystal input as well as IN0-3.
XA XB
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Si5380
OSC
IN1
IN1b
IN2
IN2b
IN3/FB_IN
Precision
Fast
÷P1
LOS
OOF
Precision
Fast
÷P2
LOS
Precision
OOF
Fast
÷P3
LOS
OOF
LOS
XAXB
D
OOF
DSPLL
LOL
PD
Feedback
Clock
Precision
Fast
LPF
÷M
÷5
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IN3b/FB_INb
LOS
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IN0b
÷P0
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IN0
Figure 3.2. Si5380 Fault Monitors
3.3.1 Input LOS (Loss-of-Signal) Detection
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The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of
the input LOS circuits has its own programmable sensitivity that allows missing edges or intermittent errors to be ignored. LOS sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading its status register
bit. The live LOS register always displays the current LOS state. Also, there is a sticky flag register which stays asserted until cleared
by the user.
Sticky
LOS
LOS
LOS
en
Live
Figure 3.3. LOS Status Indicator
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Monitor
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Clock Inputs (IN0, IN1, IN2, IN3)
3.3.2 Reference Input LOSXAXB (Loss-of-Signal) Detection
A LOS monitor is also available to ensure that the external crystal or reference clock is valid. By default the output clocks are disabled
when LOSXAXB is detected. This feature can be disabled such that the device will continue to produce output clocks even when LOSXAXB is detected. Single-ended inputs must be connected to the XA input pin with the XB pin terminated properly for LOSXAXB to
function correctly. The table below lists the loss of signal status indicators and fault monitoring control registers.
Register Name
Hex Address
Function
[Bit Field]
LOS Status and Controls
LOS
0x000D[3:0]
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Table 3.7. LOS Monitoring and Control Registers
LOS status indicators for IN3 - IN0.
D
0: Input signal detected or input buffer disabled or LOS disabled
1: Insufficient Input signal detected (LOS)
LOS_INTR_MSK
0x0018[3:0]
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LOS_VAL_TIME
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LOS_EN
0x002C[3:0]
0x002D[7:0]
0x002E[7:0]-0x0035[7:0]
LOS_CLR_THR
0x0036[7:0]-0x003D[7:0]
LOS_EN
0x002C[3:0]
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LOS_TRIG_THR
R
LOS indicator sticky flag bits for IN3 - IN0.
Remains asserted after the indicator bit
shows a fault until cleared by the user.
Writing a 0 to the flag bit will clear it if the
indicator bit is no longer asserted.
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0x0012[3:0]
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LOS_FLG
Masks LOS from generating INTRb interrupt for IN3 - IN0.
0: Allow LOS interrupt (default)
1: Mask (ignore) LOS for interrupt
LOS enable bits for IN3 - IN0. Allows disabling LOS monitors on unused inputs.
0: Disable input LOS
1: Enable input LOS
LOS clear validation time for IN3 - IN0. This
sets the time that an input must have a valid clock before the LOS condition is
cleared. 0: 2 ms, 1: 100 ms, 2: 200 ms, and
3: 1 s
Sets the LOS trigger threshold and clear
sensitivity for IN3 - IN0. These values are
determined by ClockBuilder Pro.
Enable LOS detection on IN3 - IN0. 0: Disable LOS Detection 1: Enable LOS Detection (default)
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LOSXAXB Status and Controls
LOSXAXB
LOSXAXB_FLG
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0x000C[1]
LOS indicator for XAXB input signal
0: XAXB input signal detected
1: Insufficient XAXB input signal detected
0x0011[1]
LOSXAXB status indicator sticky flag bit.
Remains asserted after the indicator bit
shows a fault until cleared by the user.
Writing a 0 to the flag bit will clear it if the
indicator bit is no longer asserted.
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Si5380 Revision D Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)
Register Name
Hex Address
Function
[Bit Field]
LOSXAXB_INTR_MSK
0x0017[1]
Masks LOSXAXB from generating INTRb
interrupt.
0: Allow LOSXAXB interrupt (default)
LOSXAXB_DIS
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1: Mask (ignore) LOSXAXB for interrupt
0x002C[4]
Enable LOS detection on the XAXB inputs.
0: Enable LOS Detection (default).
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D
1: Disable LOS Detection
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Si5380 Revision D Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)
3.3.3 Input OOF (Out-of-Frequency) Detection
Each input clock is monitored for frequency accuracy with respect to an OOF reference which it considers as its 0 ppm reference. This
OOF reference can be selected as either:
• XAXB signal
• IN0, IN1, IN2, IN3
Monitor
Sticky
en
Precision
LOS
OOF
Fast
Live
en
N
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Figure 3.4. OOF Status Indicator
D
OOF
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The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in the figure
below. An option to disable either monitor is also available. The live OOF register always displays the current OOF state and its sticky
flag register bit stays asserted until cleared. Note that IN3 is only available as an OOF reference when the device is not in ZDM.
OOF Declared
Hysteresis
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OOF Cleared
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The Precision OOF monitor circuit measures the frequency of all input clocks to within up to ±1 ppm accuracy with respect to the selected OOF frequency reference. A valid input clock frequency is one that remains within the register-programmable OOF frequency range
of up to ±500 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling
at the failure boundary. An example is shown in the figure below. In this case, the OOF monitor is configured with a valid frequency
range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0–IN3) as the 0 ppm OOF reference instead of
the XAXB pins is available. These options are all register configurable.
-6 ppm
(Set)
-4 ppm
(Clear)
0 ppm
OOF
Reference
fIN
Hysteresis
+4 ppm
(Clear)
+6 ppm
(Set)
Figure 3.5. Example of Precision OOF Status Monitor Set and Clear Thresholds
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The table below lists the OOF monitoring and control registers. Because the precision OOF monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored input clock frequencies over a relatively long period of time. However,
this may be too slow to detect an input clock that is quickly ramping in frequency. An additional level of OOF monitoring called the Fast
OOF monitor runs in parallel with the precision OOF monitors to quickly detect a ramping input frequency. The Fast OOF responds
more quickly, and has larger thresholds.
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Table 3.8. OOF Status Monitoring and Control Registers
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Register Name
OOF
Hex Address
Function
[Bit Field]
OOF Status and Controls
0x000D[7:4]
OOF status indicators for IN3 - IN0.
0: Input signal detected or input buffer disabled or OOF disabled
1: Insufficient Input signal detected (OOF)
OOF_FLG
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0x0012[7:4]
OOF indicator sticky flag bits for IN3 - IN0.
Remains asserted after the indicator bit
shows a fault until cleared by the user.
Writing a 0 to the flag bit will clear it if the
indicator bit is no longer asserted.
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Clock Inputs (IN0, IN1, IN2, IN3)
Register Name
Hex Address
Function
[Bit Field]
OOF_INTR_MSK
0x0018[7:4]
Masks OOF from generating INTRb interrupt for IN3 - IN0.
0: Allow OOF interrupt (default)
Precision OOF Controls
OOF_EN
0x003F[3:0]
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1: Mask (ignore) OOF for interrupt
Enable Precision OOF for IN3 - IN0.
0: Disable Precision OOF
1: Enable Precision OOF
0x0040[2:0]
Selects clock used for OOF as the 0 ppm
reference. Selections are: XAXB, IN0, IN1,
IN2, IN3. Default is XAXB. Note that IN3
may not be used when the device is in
ZDM.
OOF_SET_THR
0x0046[7:0]-0x0049[7:0]
OOF Set threshold for IN3 – IN0. Range is
up to ±500 ppm in steps of 1/16 ppm.
OOF_CLR_THR
0x004A[7:0]-0x004D[7:0]
OOF Clear threshold for each input. Range
is up to ±500 ppm in steps of 1/16 ppm.
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OOF_REF_SEL
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Fast OOF Controls
0x003F[7:4]
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FAST_OOF_EN
Enable Fast OOF for IN3 - IN0.
0: Disable Precision OOF
1: Enable Precision OOF
0x0051[7:0]-0x0054[7:0]
Fast OOF Set threshold for IN3 - IN0.
Range is from ±1,000 ppm to ±16,000 ppm
in 1000 ppm steps.
FAST_OOF_CLR_THR
0x0055[7:0]-0x0058[7:0]
OOF Clear threshold for each input. Range
is from ±1,000 ppm to ±16,000 ppm in
1,000 ppm steps.
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FAST_OOF_SET_THR
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Clock Inputs (IN0, IN1, IN2, IN3)
3.3.4 DSPLL LOL (Loss-of-Lock) Detection and the LOLb Output Indicator Pin
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The Loss of Lock (LOL) monitor asserts a LOL register bit when the DSPLL has lost synchronization with its selected input clock. There
is also a dedicated loss of lock pin that reflects the loss of lock condition. The LOL monitor functions by measuring the frequency difference between the input and feedback clocks at the phase detector. There are four parameters to the LOL monitor.
1. Assert to set the LOL.
a. User sets the threshold in ppm in CBPro.
2. Fast assert to set the LOL.
a. CBPro sets this to ~100 times the assert threshold.
b. A very large ppm error in a short time will assert the LOL.
3. De-assert to clear the LOL.
a. User sets the threshold in ppm in CBPro.
4. Clear delay.
a. CBPro sets this based upon the project plan.
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A block diagram of the LOL monitor is shown in the figure below. The live LOL register always displays the current LOL state and a
sticky register always stays asserted until cleared. The LOLb pin reflects the current state of the LOL monitor.
LOL
Clear
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LOL Monitor
Timer
LOS
LOL
LOL
Set
Feedback
Clock
LOLb
LPF
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Live
DSPLL
fIN
Sticky
÷M
Si5380
Figure 3.6. LOL Status Indicator
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The LOL frequency monitor has an adjustable sensitivity which is register-configurable from ±1 ppm to ±10,000 ppm. Having two separate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is indicated when there is less than 0.1 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there's more
than 10 ppm frequency difference is shown in the figure below.
LOL Declared
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Locked
Loss of
Lock
Hysteresis
-10 ppm
(Set)
Lock
Acquisition
-0.1 ppm
(Clear)
0 ppm
fDIFF
Hysteresis
+0.1 ppm
(Clear)
+10 ppm
(Set)
Loss of
Lock
Phase Detector Frequency Difference
Figure 3.7. Example of LOL Set and Clear Thresholds
An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the inpujt
clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The
configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using
the ClockBuilder Pro utility. It is important to know that, in addition to being a status bit, LOL automatically enables Fastlock by default.
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Clock Inputs (IN0, IN1, IN2, IN3)
Table 3.9. LOL Status Monitor and Control Registers
Register Name
Hex Address
Function
[Bit Field]
0x000E[1]
LOL status indicator for the DSPLL.
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LOL
0: DSPLL Locked to input clock
1: DSPLL Not locked to an input clock
0x0013[1]
LOL indicator sticky flag bit. Remains asserted after the indicator bit shows a fault
until cleared by the user. Writing a 0 to the
flag bit will clear it if the indicator bit is no
longer asserted.
LOL_INTR_MSK
0x0019[1]
Masks LOL from generating INTRb interrupt.
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LOL_FLG
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0: Allow LOL interrupt (default)
1: Mask (ignore) LOL for interrupt
0x009E[7:4]
LOL_SLW_CLR_THR
0x00A0[7:4]
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LOL_SLW_SET_THR
0x00A9[7:0]-0x00AC[4:0]
LOL_TIMER_EN
0x00A2[1]
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LOL_CLR_DELAY_DIV256
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LOL_FST_EN
Configures the loss of lock set thresholds.
Selectable as
1,3,10,30,100,300,1000,3000,10000. Values are in ppm.
Configures the loss of lock set thresholds.
Selectable as
0.1,0.3,1,3,10,30,100,300,1000,3000,1000
0. Values are in ppm.
This is a 29-bit register that configures the
delay value for the LOL Clear delay. Selectable from 4 ns to over 500 seconds.
This value depends on the DSPLL frequency configuration and loop bandwidth. It is
calculated using the ClockBuilder Pro utility.
Enable for the LOL Clear Timer.
0: Disable LOL clear timer
1: Enable LOL clear timer
0x0092[1]
Fast LOL Enable. Large input frequency errors will quickly assert LOL when enabled.
0: Disable Fast LOL
1: Enable Fast LOL (default)
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The settings in the above table are handled by ClockBuilder Pro. Manual settings should be avoided.
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Clock Inputs (IN0, IN1, IN2, IN3)
3.3.5 Device Status Monitoring
In addition to the input-driven LOS, LOSXAXB, OOF, LOL, and HOLD fault monitors discussed previously, there are several additional
status monitors which may be useful in determining the device operating state. While some of these indicators may seem redundant,
they are either taken from different locations in the device or are active in different operating modes. These indicators can provide further insight into the operating state of the device.
Register Name
Hex Address
Function
[Bit Field]
SYSINCAL
0x000C[0]
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Table 3.10. Device Status Monitoring and Control Registers
Device in Calibration status indicator.
0: Normal Operation
LOSREF
D
1: Device in Calibration
0x000C[2]
LOS status indicator for XAXB reference
signal.
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0: XAXB input signal detected
1: Insufficient XAXB input signal detected
XAXB_ERR
0x000C[3]
XAXB input locking status indicator.
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0: XAXB Input Locked
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SYSINCAL_FLG
0x000C[5]
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SMBUS_TMOUT
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LOSREF_FLG
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XAXB_ERR_FLG
SMBUS_TMOUT_FLG
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0x000F[5]
1: XAXB Input Not locked
SMB Bus Timeout Indicator.
0: SMB Bus Timeout has Not occurred
1: SMB Bus Timeout Has occurred
DSPLL in Calibration status indicator.
0: Normal Operation
1: DSPLL in Calibration
0x0011[0]
SYSINCAL indicator sticky flag bit. Remains asserted after the indicator bit shows
a fault until cleared by the user. Writing a 0
to the flag bit will clear it if the indicator bit
is no longer asserted.
0x0011[2]
LOSREF indicator sticky flag bit. Remains
asserted after the indicator bit shows a fault
until cleared by the user. Writing a 0 to the
flag bit will clear it if the indicator bit is no
longer asserted.
0x0011[3]
XAXB_ERR indicator sticky flag bit. Remains asserted after the indicator bit shows
a fault until cleared by the user. Writing a 0
to the flag bit will clear it if the indicator bit
is no longer asserted.
0x0011[5]
SMBUS_TMOUT indicator sticky flag bit.
Remains asserted after the indicator bit
shows a fault until cleared by the user.
Writing a 0 to the flag bit will clear it if the
indicator bit is no longer asserted.
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Clock Inputs (IN0, IN1, IN2, IN3)
Register Name
Hex Address
Function
[Bit Field]
0x0014[5]
CAL indicator sticky flag bit. Remains asserted after the indicator bit shows a fault
until cleared by the user. Writing a 0 to the
flag bit will clear it if the indicator bit is no
longer asserted.
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ew
D
es
ig
ns
CAL_FLG
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Clock Inputs (IN0, IN1, IN2, IN3)
3.3.6 INTRb Interrupt Configuration
The INTRb interrupt output pin is a convenient way to monitor a change in state of one or more status indicator flags, though direct
polling may also be used to monitor device status. Each of the status indicator flags is maskable to avoid unwanted assertion of the
interrupt pin. The state of the INTRb pin is reset by clearing the unmasked status flag register bit(s) that caused the interrupt. Note that
the status flag register bits cannot be cleared if the corresponding status indicator is still showing a fault. Also notate that under certain
conditions while the RSTb input is held low, the INTRb output may oscillate at a low frequency of approximately 5 MHz.
LOS_INTR_MSK[3-0]
es
ig
ns
LOS_FLG[3-0]
OOF_INTR_MSK[3-0]
OOF_FLG[3-0]
D
LOL_INTR_MSK
N
ew
LOL_FLG
INTRb
HOLD_INTR_MSK
HOLD_FLG
fo
r
CAL_INTR_MSK
CAL_FLG
SYSINCAL_FLG
m
en
de
d
SYSINCAL_INTR_MSK
LOSXAXB_INTR_MSK
LOSXAXB_FLG
LOSREF_INTR_MSK
LOSREF_FLG
XAXB_ERR_INTR_MSK
om
XAXB_ERR_FLG
SMB_TMOUT_INTR_MSK
Figure 3.8. Interrupt Pin Source Masking Options
N
ot
R
ec
SMB_TMOUT_FLG
Register Name
LOS_INTR_MSK
Table 3.11. INTRb Pin Interrupt Mask Registers
Hex Address
Function
[Bit Field]
0x0018[3:0]
Masks LOS from generating INTRb interrupt for IN3 - IN0.
0: Allow LOS interrupt (default)
1: Mask (ignore) LOS for interrupt
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Clock Inputs (IN0, IN1, IN2, IN3)
Register Name
Hex Address
Function
[Bit Field]
OOF_INTR_MSK
0x0018[7:4]
Masks OOF from generating INTRb interrupt for IN3 - IN0.
0: Allow OOF interrupt (default)
LOL_INTR_MSK
es
ig
ns
1: Mask (ignore) OOF for interrupt
0x0019[1]
Masks LOL from generating INTRb interrupt.
0: Allow LOL interrupt (default)
1: Mask (ignore) LOL for interrupt
0x0019[5]
Masks Holdover/Freerun from generating
INTRb interrupt.
D
HOLD_INTR_MSK
N
ew
0: Allow Holdover/Freerun interrupt (default)
1: Mask (ignore) Holdover/Freerun for interrupt
CAL_INTR_MSK
0x001A[5]
Masks CAL from generating INTRb interrupt.
0x0017[0]
m
en
de
d
SYSINCAL_INTR_MSK
fo
r
0: Allow CAL interrupt (default)
LOSXAXB_INTR_MSK
0x0017[2]
ec
om
LOSREF_INTR_MSK
0x0017[1]
N
ot
SMB_TMOUT_INTR_MSK
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Masks SYSINCAL from generating INTRb
interrupt.
0: Allow SYSINCAL interrupt (default)
1: Mask (ignore) SYSINCAL for interrupt
Masks LOSXAXB from generating INTRb
interrupt.
0: Allow LOSXAXB interrupt (default)
1: Mask (ignore) LOSXAXB for interrupt
Masks LOSREF from generating INTRb interrupt.
0: Allow LOSREF interrupt (default)
1: Mask (ignore) LOSREF for interrupt
0x0017[3]
Masks XAXB_ERR from generating INTRb
interrupt.
0: Allow XAXB_ERR interrupt (default)
R
XAXB_ERR_INTR_MSK
1: Mask (ignore) CAL for interrupt
1: Mask (ignore) XAXB_ERR for interrupt
0x0017[5]
Masks SMB_TMOUT from generating
INTRb interrupt.
0: Allow SMB_TMOUT interrupt (default)
1: Mask (ignore) SMB_TMOUT for interrupt
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Output Clocks
4. Output Clocks
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D
es
ig
ns
Each output driver has configurable output amplitude and common mode voltage, covering a wide variety of differential signal output
formats including LVPECL, LVDS, HCSL, and CML. In addition to supporting differential signals, any of the outputs can be configured
as single-ended LVCMOS (3.3, 2.5, or 1.8V) providing up to 20 single-ended outputs or any combination of differential and singleended outputs. Unused outputs may be left unconnected.
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Output Clocks
4.1 Output Crosspoint Switch
A crosspoint switch allows any of the output drivers to connect with any of the Output N dividers as shown in the figure below. The
crosspoint configuration is programmable and can be stored in NVM so that the desired output configuration is ready at power up. Any
N divider can source multiple, or even all, output drivers.
VDDO0
t2
÷N3
t3
÷N4
t4
÷R1
VDDO1
OUT1
OUT1b
÷R2
VDDO2
OUT2
OUT2b
÷R3
es
ig
ns
OUT0
OUT0b
÷R4
÷R5
VDDO5
OUT5
OUT5b
÷R6
VDDO6
OUT6
OUT6b
÷R7
VDDO7
OUT7
OUT7b
÷R8
VDDO8
OUT8
OUT8b
÷R9
OUT9
OUT9b
m
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om
ec
÷R9A
R
N
ot
VDDO3
OUT3
OUT3b
VDDO4
OUT4
OUT4b
fo
r
÷N2
÷R0
D
t1
÷N1
OUT0A
OUT0Ab
N
ew
t0
÷N0
÷R0A
OUT9A
OUT9Ab
VDDO9
Figure 4.1. N Divider to Output Driver Crosspoint
The following table is used to set up the routing from the N divider frequency selection to the output.
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Output Clocks
Table 4.1. Output Crosspoint Configuration Registers
Register Name
Hex Address
Function
[Bit Field]
OUT1_MUX_SEL
0x0110[2:0]
OUT2_MUX_SEL
0x0115[2:0]
OUT3_MUX_SEL
0x011A[2:0]
OUT4_MUX_SEL
0x011F[2:0]
OUT5_MUX_SEL
0x0124[2:0]
OUT6_MUX_SEL
0x0129[2:0]
OUT7_MUX_SEL
0x012E[2:0]
OUT8_MUX_SEL
0x0133[2:0]
OUT9_MUX_SEL
0x0138[2:0]
OUT9A_MUX_SEL
0x013D[2:0]
4.1.1 Output R Divider Synchronization
0: N0
1: N1
2: N2
3: N3
4: N4
es
ig
ns
0x010B[2:0]
D
OUT0_MUX_SEL
Connects the output drivers to one of the N
divider sources. Selections are:
5-7: Reserved
N
ew
0x0106[2:0]
fo
r
OUT0A_MUX_SEL
m
en
de
d
All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable
output phase alignment. Resetting the device using the RSTb pin or asserting the Hard Reset bit 0x001E[1] will give the same result.
Also, the output R dividers can be reset by driving the SYNCb input pin low or by setting the SYNC register bit (0x001E[2]) high.
N
ot
R
ec
om
Soft Reset does not affect the output synchronization, though it will load any updated Nx_DELAY values to adjust the relative delays
between outputs. See 4.8 Output Delay Control (Δt0 – Δt4) for more information.
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Output Clocks
4.2 Performance Guidelines for Outputs
Whenever a number of high frequency, fast rise time, large amplitude signals are located close to one another, the laws of physics
dictate that there will be some amount of crosstalk. The Integer-divider nature of the Si5380 greatly reduces the chances for crosstalk,
as all clock output frequencies are divided from the same VCO frequency. However, the phase noise of the Si5380 is so low that crosstalk may still be detected in certain cases. Crosstalk occurs at both the device level, as well as the PCB level. It is difficult (and possibly
irrelevant) to allocate the crosstalk contributions between these two sources since it can only be measured, while the Si5380 is mounted on a PCB.
es
ig
ns
In addition to following the PCB layout guidelines given in 9. Crystal and Device Circuit Layout Recommendations, crosstalk can be
minimized by modifying the placements of the different output clock frequencies. For example, consider the following lineups of output
clocks in the table below. The “Clock Placement Wizard ...” button on the “Define Output Frequencies” page of ClockBuilder Pro provides an easy way to change the frequency placements by either Manual or Automatic means.
Table 4.2. Comparison of Output Clock Frequency Placement Choices
Not Recommended (Frequency MHz)
0A
122.88
0
122.88
1
7.68
2
7.68
3
7.68
4
7.68
5
491.52
491.52
6
92.16
7.68
7
76.8
76.8
61.44
7.68
256.76
256.76
256.76
256.76
9
9A
122.88
N
ew
122.88
fo
r
m
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8
Recommended (Frequency MHz)
D
Output
61.44
7.68
92.16
7.68
N
ot
R
ec
om
Using this example, a few guidelines are illustrated:
1. Avoid adjacent frequency values that are close. A 76.8 MHz clock should not be next to a 92.16 MHz clock as crosstalk will be
observed at 15.36 MHz from each frequency. If the jitter integration bandwidth or spur range goes up to 20 MHz then keep adjacent frequencies at least 20 MHz apart.
2. Frequency values that are integer multiples of one another should be grouped together. Noting that because 61.44 x 2 = 122.88
and 7.68 = 61.44 / 8 = 92.16 / 12 = 491.52 / 64 = 76.8 / 10 = 245.76 / 32, it is okay to place each of these frequency values next to
one another.
3. Unused outputs can also be placed to separate clock outputs that might otherwise show crosstalk.
4. If some outputs have tighter spur requirements while others are relatively loose, rearrange the clock outputs so that the critical
outputs are the least susceptible to crosstalk.
5. Because CMOS outputs have large pk-pk swings, are single ended, and do not present a balanced load to the VDDO supplies,
CMOS outputs generate much more crosstalk than differential outputs. For this reason, CMOS outputs should be avoided whenever possible. When CMOS is unavoidable, even greater care must be taken with respect to the above guidelines. For more information on these issues, see AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems.
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Output Clocks
4.3 Output Signal Format
Table 4.3. Output Signal Format Registers
Register Name
Hex Address
Function
OUT0_FORMAT
0x0109[2:0]
OUT1_ FORMAT
0x010E[2:0]
OUT2_ FORMAT
0x0113[2:0]
OUT3_ FORMAT
0x0118[2:0]
OUT4_ FORMAT
0x011D[2:0]
OUT5_ FORMAT
0x0122[2:0]
OUT6_ FORMAT
0x0127[2:0]
OUT7_ FORMAT
0x012C[2:0]
OUT9_ FORMAT
1: Normal Differential
2: Low-Power Differential
3: Reserved
4: LVCMOS
5-7: Reserved
0x0131[2:0]
0x0136[2:0]
0x013B[2:0]
N
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om
OUT9A_FORMAT
0: Reserved
m
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OUT8_ FORMAT
Selects the output signal format as differential or LVCMOS mode.
N
ew
0x0104[2:0]
fo
r
OUT0A_FORMAT
D
[Bit Field]
es
ig
ns
The differential output amplitude and common mode voltage are both fully programmable covering a wide variety of signal formats including LVDS, LVPECL, HCSL. For CML applications, see 13. Appendix—Custom Differential Amplitude Controls. The standard formats can be either Normal or Low-Power. Low-Power format uses less power for the same amplitude but has the drawback of slower
rise/fall times. The source impedance in the Low-Power format is higher than 100 Ω. See 13. Appendix—Custom Differential Amplitude
Controls for register settings to implement variable amplitude differential outputs. In addition to supporting differential signals, any of the
outputs can be configured as LVCMOS (3.3, 2.5, or 1.8 V) drivers providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs. Note also that CMOS output can create much more crosstalk than differential outputs so extra care
must be taken in their pin replacement so that other clocks that need best spur performance are not on nearby pins. See AN862:
Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems.
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Output Clocks
4.4 Output Driver Supply Select
The VDDO output driver voltage may be selected separately for each driver. The selected voltage must match the voltage supplied to
that VDDO pin in the end system. VDDO pins for unused (unconnected) outputs can be left unconnected, or may be connected to a
convenient 1.8 V–3.3 V system supply without increasing power dissipation.
Hex Address
Register Name
Function
[Bit Field]
OUT0A_VDD_SEL_EN
es
ig
ns
Table 4.4. Output Driver Supply Select
Output Driver VDD Select Enable.
0x0106[3]
Set to 1 for normal operation.
Output Driver VDD Select
OUT0A_VDD_SEL
D
0: 1.8 V
1: 2.5 V
0x0106[5:4]
N
ew
2: 3.3 V
3: Reserved
0x010B[3]
OUT0_VDD_SEL
0x010B[5:4]
OUT1_VDD_SEL_EN
0x0110[3]
OUT1_VDD_SEL
0x0110[5:4]
OUT2_VDD_SEL_EN
0x0115[3]
OUT2_VDD_SEL
0x0115[5:4]
m
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fo
r
OUT0_VDD_SEL_EN
OUT3_VDD_SEL_EN
0x011A[3]
OUT3_VDD_SEL
0x011A[5:4]
OUT4_VDD_SEL_EN
0x011F[3]
OUT4_VDD_SEL
0x011F[5:4]
0x0124[3]
OUT5_VDD_SEL
0x0124[5:4]
0x0129[3]
OUT6_VDD_SEL
0x0129[5:4]
OUT7_VDD_SEL_EN
0x012E[3]
OUT7_VDD_SEL
0x012E[5:4]
OUT8_VDD_SEL_EN
0x0133[3]
OUT8_VDD_SEL
0x0133[5:4]
N
ot
R
OUT6_VDD_SEL_EN
ec
om
OUT5_VDD_SEL_EN
OUT9_VDD_SEL_EN
0x0138[3]
OUT9_VDD_SEL
0x0138[5:4]
OUT9A_VDD_SEL_EN
0x013D[3]
OUT9A_VDD_SEL
0x013D[5:4]
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Similar to OUT0A settings
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Output Clocks
4.5 Differential Outputs
4.5.1 Differential Output Terminations
The differential output drivers support both ac and dc-coupled terminations as shown in the following figure.
VDDO = 3.3V, 2.5V, 1.8V
VDDO = 3.3V, 2.5V, 1.8V
50
OUTx
OUTx
50
100
50
Si5380
Internally
self-biased
D
Si5380
50
OUTxb
100
OUTxb
es
ig
ns
AC Coupled LVDS/LVPECL
DC Coupled LVDS
AC Coupled LVPECL / CML
DC Coupled LVCMOS
3.3V, 2.5V, 1.8V
LVCMOS
VDD – 1.3V
N
ew
VDDO = 3.3V, 2.5V, 1.8V
VDDO = 3.3V, 2.5V
50
Rs
OUTx
OUTx
OUTxb
50
50
50
OUTxb
50
50
Rs
Si5380
AC Coupled HCSL
VDDO = 3.3V, 2.5V, 1.8V
R1
OUTx
R1
50
OUTxb
Standard
HCSL
Receiver
50
Si5380
Note: An external bias is required when the
receiver does not have an internal bias.
m
en
de
d
VDDRX
fo
r
Si5380
R2
R2
For VCM = 0.35V
R1
R2
om
VDDRX
442
56.2
2.5V
332
59
1.8V
243
63.4
Figure 4.2. Termination of Differential and LVCMOS Input Signals
N
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3.3V
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Output Clocks
4.5.2 Differential Output Amplitude Controls
The differential amplitude of each output can be controlled with the following registers. See Table 4.7 Recommended Settings for Differential LVPECL, LVDS, HCSL, and CML on page 43 for recommended OUTx_AMPL settings for common signal formats. See
13. Appendix—Custom Differential Amplitude Controls for register settings for non-standard amplitudes.
Register Name
Hex Address
Function
[Bit Field]
0x010A[6:4]
OUT1_ AMPL
0x010F[6:4]
OUT2_ AMPL
0x0114[6:4]
OUT3_ AMPL
0x0119[6:4]
OUT4_ AMPL
0x011E[6:4]
OUT5_ AMPL
0x0123[6:4]
OUT6_ AMPL
0x0128[6:4]
OUT7_ AMPL
0x012D[6:4]
OUT8_ AMPL
0x0132[6:4]
OUT9_ AMPL
0x0137[6:4]
OUT9A_ AMPL
0x013C[6:4]
D
OUT0_AMPL
Sets the voltage swing for the differential
output drivers for both Normal and LowPower modes. This field only applies when
OUTx_FORMAT = 1 or 2.
N
ew
0x0105[6:4]
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OUT0A_AMPL
es
ig
ns
Table 4.5. Differential Output Voltage Swing Registers
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Output Clocks
4.5.3 Differential Output Common Mode Voltage Selection
The common mode voltage (VCM) for differential output Normal and Low-Power modes is selectable depending on the supply voltage
provided at the output’s VDDO pin. See the table below for recommended OUTx_CM settings for common signal formats. See
13. Appendix—Custom Differential Amplitude Controls " for recommended OUTx_CM settings when using custom output amplitude.
Register Name
Hex Address
Function
[Bit Field]
0x010A[3:0]
OUT1_ CM
0x010F[3:0]
OUT2_ CM
0x0114[3:0]
OUT3_ CM
0x0119[3:0]
OUT4_ CM
0x011E[3:0]
OUT5_ CM
0x0123[3:0]
OUT6_ CM
0x0128[3:0]
OUT7_ CM
0x012D[3:0]
OUT8_ CM
0x0132[3:0]
OUT9_ CM
0x0137[3:0]
OUT9A_ CM
0x013C[3:0]
D
OUT0_CM
Sets the common mode voltage for the differential output driver. This field only applies when OUTx_FORMAT = 1 or 2.
N
ew
0x0105[3:0]
N
ot
R
ec
om
m
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d
fo
r
OUT0A_CM
es
ig
ns
Table 4.6. Differential Output Common Mode Voltage Selection Registers
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Output Clocks
4.5.4 Recommended Settings for Differential LVPECL, LVDS, HCSL, and CML
Each differential output has four settings for control:
1. Normal or Low-Power Format
2. Amplitude (sometimes called Swing)
3. Common Mode Voltage
4. Stop High or Stop Low (See 4.7.1 Output Driver State When Disabled for details.)
es
ig
ns
The Normal mode setting includes an internal 100 Ω resistor between the OUT and OUTb pins. In Low-Power mode, this resistor is
removed, resulting in a higher output impedance. The increased impedance creates larger amplitudes for the same power while reducing edge rates, which may increase jitter or phase noise. In either mode, the differential receiver must be properly terminated to the
PCB trace impedance for good system signal integrity. Note that ClockBuilder Pro does not provide Low-Power mode settings. Contact
Silicon Labs Technical Support for assistance with Low-Power mode use.
Amplitude controls are as described in the previous section and also in more detail in 13. Appendix—Custom Differential Amplitude
Controls ". Common mode voltage selection is also described in more detail in this appendix.
VDDO
Mode
OUTx_FORMAT
OUTx_CM
OUTx_AMPL
(Dec)
(Dec)
(Dec)
1
11
6
1
11
6
2
11
3
2
11
3
1
3
3
N
ew
Standard
D
Table 4.7. Recommended Settings for Differential LVPECL, LVDS, HCSL, and CML
3.3
Normal
LVPECL
2.5
Normal
LVPECL
3.3
Low-Power
LVPECL
2.5
Low-Power
LVDS
3.3
Normal
LVDS
2.5
Normal
1
11
3
1.8
Normal
1
13
3
3.3
Low-Power
2
3
1
2.5
Low-Power
2
11
1
1.8
Low-Power
2
13
1
3.3
Low-Power
2
11
3
2.5
Low-Power
2
11
3
1.8
Low-Power
2
13
3
Sub-LVDS1
LVDS
LVDS
Sub-LVDS1
HCSL2
HCSL2
om
HCSL2
fo
r
LVPECL
m
en
de
d
(V)
R
ec
Note:
1. The Sub-LVDS common mode voltage is not compliant with LVDS standards. Therefore, AC coupling the driver to an LVDS receiver is highly recommended in this case.
2. Creates HCSL compatible signals, see HCSL receiver biasing network in Figure 4.2 Termination of Differential and LVCMOS Input Signals on page 40.
N
ot
The output differential driver can also produce a wide range of CML compatible output amplitudes. See 13. Appendix—Custom Differential Amplitude Controls for additional information.
4.6 LVCMOS Outputs
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Output Clocks
4.6.1 LVCMOS Output Terminations
LVCMOS outputs are dc-coupled as shown in the following figure.
DC Coupled LVCMOS
OUTx
50
Rs
OUTxb
50
Rs
D
VDDO = 3.3V, 2.5V, 1.8V
es
ig
ns
3.3V, 2.5V, 1.8V
LVCMOS
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
Figure 4.3. LVCMOS Output Terminations
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Output Clocks
4.6.2 LVCMOS Output Impedance and Drive Strength Selection
Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A series
source termination resistor (Rs) is recommended close to the output to match the selected output impedance to the trace impedance
(i.e. Rs = Trace Impedance – Zs). There are multiple programmable output impedance selections for each VDDO option as shown in
the following table. Generally, the lowest impedance for a given supply voltage is preferable, since it will give the fastest edge rates.
OUTx_CMOS_DRV
Driver Impedance (Zs)
0x1
38 Ω
0x2
30 Ω
0x31
22 Ω
0x1
43 Ω
0x2
35 Ω
0x31
24 Ω
2.5 V
0x31
1.8 V
10 mA
12 mA
17 mA
6 mA
D
3.3 V
Drive Strength (Iol/Ioh)
N
ew
VDDO
es
ig
ns
Table 4.8. LVCMOS Output Impedance and Drive Strength Selections
31 Ω
8 mA
11 mA
5 mA
fo
r
Note:
1. Use of the lowest impedance setting is recommended for all supply voltages.
Table 4.9. LVCMOS Drive Strength Registers
Hex Address
m
en
de
d
Register Name
[Bit Field]
0x0104[7:6]
OUT0_CMOS_DRV
0x0109[7:6]
OUT1_ CMOS_DRV
0x010E[7:6]
OUT2_ CMOS_DRV
0x0113[7:6]
OUT3_ CMOS_DRV
0x0118[7:6]
OUT4_ CMOS_DRV
0x011D[7:6]
OUT5_ CMOS_DRV
0x0122[7:6]
OUT6_ CMOS_DRV
0x0127[7:6]
OUT7_ CMOS_DRV
0x012C[7:6]
OUT8_ CMOS_DRV
0x0131[7:6]
R
ec
om
OUT0A_CMOS_DRV
0x0136[7:6]
OUT9A_ CMOS_DRV
0x013B[7:6]
LVCMOS output impedance. See the table
above for settings.
N
ot
OUT9_ CMOS_DRV
Function
4.6.3 LVCMOS Output Signal Swing
The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own
VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. Each output driver automatically detects the voltage
on the VDDO pin to properly determine the correct output voltage.
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Output Clocks
4.6.4 LVCMOS Output Polarity
When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUT and OUTb). By default the clock on
the OUTb pin is generated with the same polarity (in phase) with the clock on the OUT pin. The polarity of these clocks is configurable
enabling complimentary clock generation and/or inverted polarity with respect to other output drivers. Note that these settings have no
effect on the differential-mode output driver.
Register Name
Hex Address
Function
[Bit Field]
0x010B[7:6]
OUT1_INV
0x0110[7:6]
OUT2_INV
0x0115[7:6]
OUT3_INV
0x011A[7:6]
OUT4_INV
0x011F[7:6]
OUT5_INV
0x0124[7:6]
OUT6_INV
0x0129[7:6]
OUT7_INV
0x012E[7:6]
OUT8_INV
0x0133[7:6]
OUT9_INV
0x0138[7:6]
OUT9A_INV
0x013D[7:6]
D
OUT0_INV
Controls the output polarity of the OUT and
OUT pins when in LVCMOS mode. Selections are shown below in the table below.
N
ew
0x0106[7:6]
m
en
de
d
fo
r
OUT0A_INV
es
ig
ns
Table 4.10. LVCMOS Output Polarity Registers
Table 4.11. LVCMOS Output Polarity of OUT and OUTb Pins
OUTx_INV
Register Settings
0x00
0x02
OUTb
Comment
CLK
CLK
Both in phase (default)
CLK
CLKb
Complementary
CLKb
CLKb
Both Inverted
CLKb
CLK
Inverted Complementary
N
ot
R
ec
0x03
om
0x01
OUT
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Output Clocks
4.7 Output Enable/Disable
es
ig
ns
Each output driver may be individually placed in one of three operating states:
• “Enabled” state is the normal state for output clock operation. The output clock is toggling and the differential common mode voltage
will be generated, if selected by the output format.
• “Disabled” state gates off clock operation and places the output into a static, user-selectable, logic state. Differential output common
mode voltage is maintained, if selected by the output format, allowing a quick transition back to Enabled state operation with minimal
common mode disruption.
• “Powerdown” state removes power from the output driver and leaves the output pins high-impedance. In this state, regardless of
output format, the output common mode voltage is not generated and the output pin voltages are not well defined. Powerdown is
recommended for unused outputs as well as startup or long-term power reduction, where differential common voltage generation
restart will not introduce issues in the system. See 10.1 Power Management Features for more information on powerdown.
D
The OEb pin provides a convenient method of enabling or disabling all of the output drivers at the same time. Holding the OEb pin low
enables all of the outputs, while driving it high disables all outputs. In addition to pin control, flexible register controls described in the
following sections allow further customization for each application. Note that any one disable control can disable the corresponding
output(s) even if all other sources controls are enabled. See the sections below, especially 4.7.5 Output Driver Disable Source Summary , for more information on manual and automatic disable controls.
Register Name
Hex Address
[Bit Field]
0x0102[0]
OUT0A_OE
OUT0_OE
OUT1_OE
OUT2_OE
OUT3_OE
OUT4_OE
om
OUT5_OE
m
en
de
d
fo
r
OUTALL_DISABLE_LOW
N
ew
Table 4.12. Output Enable/Disable Manual Control Registers
0x0103[1]
0x0108[1]
0x010D[1]
0: Disable All outputs (default)
1: Enable All outputs
Enable/Disable individual outputs. Note
that the OEb pin must be held low and
OUTALL_DISABLE_LOW = 1 in order to
enable an output.
0: Disable Output (default)
0x0117[1]
1: Enable Output
0x011C[1]
0x0121[1]
0x0126[1]
OUT7_OE
0x012B[1]
OUT8_OE
0x0130[1]
OUT9_OE
0x0135[1]
OUT9A_OE
0x013A[1]
ec
Enable/Disable all output drivers. If the
OEb pin is held high, then all outputs will
be disabled regardless of the state of this
or the OUTx_OE register bits.
0x0112[1]
OUT6_OE
N
ot
R
Function
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Output Clocks
4.7.1 Output Driver State When Disabled
The disabled state of an output driver is configurable as: disable logic low or disable logic high.
Table 4.13. Output Driver Disable State Registers
Register Name
Hex Address
Function
0x0109[5:4]
OUT1_ DIS_STATE
0x010E[5:4]
OUT2_ DIS_STATE
0x0113[5:4]
OUT3_ DIS_STATE
0x0118[5:4]
OUT4_ DIS_STATE
0x011D[5:4]
OUT5_ DIS_STATE
0x0122[5:4]
OUT6_ DIS_STATE
0x0127[5:4]
OUT7_ DIS_STATE
0x012C[5:4]
OUT8_ DIS_STATE
0x0131[5:4]
OUT9_ DIS_STATE
0x0136[5:4]
OUT9A_ DIS_STATE
0x013B[5:4]
m
en
de
d
4.7.2 Synchronous Output Enable/Disable Feature
0: Disable logic low
1: Disable logic high
2-3: Reserved
D
OUT0_DIS_STATE
Determines the static state of an output
driver when disabled.
N
ew
0x0104[5:4]
fo
r
OUT0A_DIS_STATE
es
ig
ns
[Bit Field]
Each of the output drivers has individually selectable synchronous or asynchronous enable/disable behavior. Output drivers with Synchronous enable/disable will wait until a clock period has completed before changing the enable state. This prevents unwanted shortened “runt” pulses from occurring. Output drivers with Asynchronous enable/disable will change the enable state immediately, without
waiting for the entire clock period to complete. This selection affects both manual as well as automatic output enables and disables.
Table 4.14. Synchronous Enable/Disable Control Registers
om
Register Name
Hex Address
[Bit Field]
0x0104[3]
OUT0_SYNC_EN
0x0109[3]
OUT1_ SYNC_EN
OUT2_ SYNC_EN
0x0113[3]
0x010E[3]
OUT3_ SYNC_EN
0x0118[3]
OUT4_ SYNC_EN
0x011D[3]
N
ot
R
ec
OUT0A_SYNC_EN
OUT5_ SYNC_EN
0x0122[3]
OUT6_ SYNC_EN
0x0127[3]
OUT7_ SYNC_EN
0x012C[3]
OUT8_ SYNC_EN
0x0131[3]
OUT9_ SYNC_EN
0x0136[3]
OUT9A_SYNC_EN
0x013B[3]
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Function
Synchronous output Enable/Disable selection.
0: Asynchronous Enable/Disable (default)
1: Synchronous Enable/Disable
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Output Clocks
4.7.3 Automatic Output Disable During LOL
By default, a DSPLL that is out of lock will generate an output clock. There is an option to disable the outputs when the DSPLL is out of
lock (LOL). This option can be useful to force a downstream PLL into Holdover.
4.7.4 Automatic Output Disable During LOSXAXB
es
ig
ns
The internal oscillator circuit, in combination with the external crystal, provides a critical function for the operation of the DSPLLs. In the
event of a crystal failure the device will assert an LOSXAXB fault. By default all outputs will be disabled during assertion of the LOSXAXB fault.
Table 4.15. Output Automatic Disable on LOL and LOSXAXB Registers
Register Name
Hex Address
Function
[Bit Filed]
0x0142[1]
Determines if the outputs are disabled during an LOL condition.
D
OUT_DIS_MSK_LOL
N
ew
0: Disable all outputs on LOL (default)
1: Normal Operation during LOL
0x0141[6]
Determines if outputs are disabled during
an LOSXAXB condition.
0: Disable all outputs on LOSXAXB (default)
1: All outputs remain enabled during LOSXAXB
N
ot
R
ec
om
m
en
de
d
fo
r
OUT_DIS_MSK_LOSXAXB
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Output Clocks
4.7.5 Output Driver Disable Source Summary
There are a number of conditions that may cause the outputs to be automatically disabled. The user may mask out unnecessary disable sources to match system requirements. Any one of the unmasked sources may cause the output(s) to be disabled; this is more
powerful, but similar in concept, to common “wired-OR” configurations. The table below summarizes the output disable sources with
additional information for each source.
Output Driver Disable Source
es
ig
ns
Table 4.16. Output Driver Summary of Disable Sources
Disable Output(s)
when Source...
Outputs Individually Assignable?
User Maskable?
Related Registers
OUTALL_DISABLE_LOW
Low
N
N
0x0102[0]
User Controllable
OUT0A_OE
Low
Y
N
0x0103[1]
User Controllable
[bits]
0x0108[1]
OUT1_OE
0x010D[1]
OUT2_OE
0x0112[1]
N
ew
D
OUT0_OE
0x0117[1]
OUT3_OE
0x011C[1]
OUT4_OE
0x0121[1]
OUT5_OE
fo
r
OUT6_OE
OUT7_OE
m
en
de
d
OUT8_OE
OUT9_OE
OUT9A_OE
OEb (pin)
High
OE (register)
Low
High
om
LOL
High
ec
LOSXAXB
Comments
High
N
N
0x012B[1]
0x0130[1]
0x0135[1]
0x013A[1]
N
0x0022[1:0],
User Controllable
0x0023[7:0],
0x0024[3:0]
Y
0x000D[1],
Maskable
0x0142[1]
Y
0x000C[1],
Maskable
0x0141[6]
N
N
0x000C[0]
Automatic, not user
controllable or maskable
N
ot
R
SYSINCAL
Y
0x0126[1]
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Output Clocks
4.8 Output Delay Control (Δt0 – Δt4)
The Si5380 uses independently adjustable output N dividers (N0 - N4) to generate up to 5 unique top frequencies to its 12 outputs
through the output crosspoint switch. By default all output clocks are aligned. Each N divider has an independently adjustable delay
path (Δt0 – Δt4) associated with it. Each of these dividers is available for applications that require deterministic output delay configuration. This is useful for PCB trace length mismatch compensation or for applications that require quadrature clock generation. Delay adjustments are bidirectional over ±8.6 ns in 68 ps steps and are programmed through registers. An example of generating two frequencies with unique configurable path delays of Δt2 and Δt3 is shown in the figure below.
÷R0
OUT0
OUT0b
÷R1
VDDO1
OUT1
OUT1b
t0
t1
t2
÷N3
t3
÷N4
t4
N
ot
R
ec
om
m
en
de
d
÷N2
D
OUT0A
OUT0Ab
N
ew
÷N1
÷R0A
÷R2
VDDO2
OUT2
OUT2b
÷R3
VDDO3
OUT3
OUT3b
÷R4
VDDO4
OUT4
OUT4b
÷R5
VDDO5
OUT5
OUT5b
÷R6
VDDO6
OUT6
OUT6b
÷R7
VDDO7
OUT7
OUT7b
÷R8
VDDO8
OUT8
OUT8b
÷R9
OUT9
OUT9b
fo
r
÷N0
es
ig
ns
VDDO0
÷R9A
OUT9A
OUT9Ab
VDDO9
Figure 4.4. Example of Independently-Configurable Path Delays
A Soft Reset of the device, SOFT_RST (0x001C[0] = 1), is required to latch in the new bidirectional delay value(s). All delay values are
restored to their NVM values after POR, RSTb, or HARD_RST. Delay default values can be written to NVM, allowing a custom delay
offset configuration at power-up or after a Hard Reset.
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Output Clocks
Table 4.17. Output Delay Adjustment Registers
Hex Address [Bit Field]
Function
N0_DELAY
0x0359[7:0] - 0x035A[7:0]
N1_DELAY
0x035B[7:0] - 0x035C[7:0]
8-bit 2s-complement delay values. Nx_Delay values range between -128 and +127
VCO periods, inclusive.
N2_DELAY
0x035D[7:0] - 0x035E[7:0]
N3_DELAY
0x035F[7:0] - 0x0360[7:0]
N4_DELAY
0x0361[7:0] - 0x0362[7:0]
es
ig
ns
Register Name
tDLY = Nx_DELAY / 256 * 67.8 ps
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
fvco=14.7456 GHz, 1/fvco=67.8 ps
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Zero Delay Mode
5. Zero Delay Mode
es
ig
ns
Zero Delay Mode (ZDM) is available for applications requiring consistent minimum fixed delay between the selected input and outputs.
ZDM is configured by opening the internal DSPLL feedback loop through software configuration and then closing the loop externally as
shown in the figure below. This helps to cancel out internal delay introduced by the dividers, the crosspoint, the input, and the output
drivers. The OUT9A output and FB_IN input should be used for the external feedback connection in the Si5380 to minimize the overall
distance and delay. In this case the pairs of pins are adjacent and polarized in such a way that no PCB vias are required to make this
connection. The FB_IN input pins must be terminated and ac-coupled as shown below when Zero Delay Mode is used. A differential
external feedback path connection is necessary for best performance. Note that ZDM delay performance may degrade when using a
loop bandwidths <10 Hz. ClockBuilder Pro will issue a warning if this condition occurs.
When the DSPLL is set for Zero-Delay Mode (ZDM), a hard reset request from either the RSTb pin or RST_REG register bit will have a
delay of ~750 ms before executing. Any subsequent register writes to the device should be made after this time expires or they will be
overwritten with the NVM values. Please contact Silicon Labs technical support for information on reducing this ZDM hard reset time.
IN0
Si5380
DSPLL
÷P1
IN2
PD
÷P2
IN2b
÷M
IN3/FB_IN
÷P3
÷R0A
OUT0A
OUT0Ab
÷N0
t0
÷R0
OUT0
OUT0b
÷N1
t1
÷R2
VDDO2
OUT2
OUT2b
÷N2
t2
÷N3
t3
÷R8
÷N4
t4
VDDO8
OUT8
OUT8b
÷R9
OUT9
OUT9b
m
en
de
d
om
VDDO0
÷R9A
OUT9A
OUT9Ab
VDDO9
N
ot
R
ec
÷5
fo
r
100
IN3b/FB_INb
LPF
N
ew
IN1
IN1b
D
÷P0
IN0b
External Feedback Path
Figure 5.1. Zero Delay Mode (ZDM) Setup
To enable Zero Delay Mode (ZDM), set ZDM_EN = 1. In ZDM, the input clock source is selected manually by using either the
ZDM_IN_SEL register bits or the IN_SEL1 and IN_SEL0 device input pins. IN_SEL_REGCTRL determines the choice of register or pin
control to select the desired input clock. When register control is selected in ZDM, the ZDN_IN_SEL control bits determine the input to
be used and the non-ZDM IN_SEL bits will be ignored. Note that in ZDM, the DSPLL will not use Hitless switching.
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Zero Delay Mode
Table 5.1. Zero Delay Mode Registers
Hex Address [Bit Field]
Function
OUTX_ALWAYS_ON
0x013F[7:0]
Force ZDM output always on.
0x0140[3:0]
0x000: Do not force output on (default)
es
ig
ns
Register Name
0x800: Force OUT9A always on for ZDM
ZDM_EN
0x0487[0]
Enable ZDM operation.
0: Disable ZDM (default)
1: Enable ZDM operation
0x0487[2:1]
ZDM Manual Input Select when both
ZDM_EN = 1 and IN_SEL_REGCTRL
(0x052A[0]) = 1.
D
ZDM_IN_SEL
N
ew
0: IN0 (default)
1: IN1
2: IN2
3: Reserved (IN3 already used by ZDM)
0x052A[0]
ZDM Manual Input Select control source.
m
en
de
d
fo
r
IN_SEL_REGCTRL
0: Pin controlled input clock selection (default)
1: ZDM_IN_SEL register input clock selection
Table 5.2. Input Clock Selection in Zero Delay Mode
ZDM_AUTO_SW_EN
0
0
0
IN_SEL_REGCTRL
Input Clock Selection Governed by:
0
0
IN_SEL[1:0] Pins
0
1
IN_SEL Register
1
0
IN_SEL[1:0] Pins (ZDM)
1
1
ZDM_IN_SEL Register (ZDM)
X
X
Input clock selection governed
by automatic input switching engine (see 3.1.2 Automatic Input
Switching)
N
ot
R
ec
1
om
0
ZDM_EN
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Serial Interface
6. Serial Interface
SPI 4-Wire
I2C_SEL pin = High
I2C_SEL pin = Low
SPI_3WIRE = 0
IO_VDD_SEL = 0
IO_VDD_SEL = 0
1.8V
1.8V
Host = 1.8V
1.8V
3.3V
1.8V
VDDA VDD
I2C SDA
HOST
SCLK
SDA
SPI
HOST
SCLK Si5380
CSb
SDO
SDI
SCLK
IO_VDD_SEL = 1
3.3V
3.3V
1.8V
VDDA VDD
I2C SDA
HOST
SCLK
IO_VDD_SEL = 0
3.3V
1.8V
VDDA
VDD
CSb
1.8V
SPI
HOST
SDIO
SDO
SCLK
3.3V
SDA
VDDA
SPI
HOST
CSb
Si5380
SDIO
SDI
SDO
SCLK
1.8V
SCLK
CSb
SDIO
SCLK
3.3V
SPI
HOST
Si5380
3.3V
1.8V
VDDA
VDD
CSb
SDIO
SCLK
Si5380
IO_VDD_SEL = 1
VDD
CSb
SDO
m
en
de
d
SCLK Si5380
fo
r
3.3V
I2C_SEL pin = Low
SPI_3WIRE = 1
IO_VDD_SEL = 1
3.3V
Host = 3.3V
SPI 3-Wire
D
I2C
N
ew
Serial
Interface
Configuration
es
ig
ns
Configuration and operation of the Si5380 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL pin
selects I2C or SPI operation. The Si5380 supports communication with a 3.3 V or 1.8 V host by setting the IO_VDD_SEL (0x0943[0])
configuration bit. The SPI interface supports both 4-wire or 3-wire modes by setting the SPI_3WIRE (0x002B[3]) configuration bit. See
the figure below for supported modes of operation and settings. All digital I/O pins are 3.3 V-tolerant, even when operating at 1.8 V.
Additionally, the pins with internal pull-ups, I2C_SEL and A0/CS are pulled-up to 3.3 V through a high impedance pull-up, regardless of
IO_VDD_SEL setting.
CSb
SDIO
SCLK
3.3V
1.8V
VDDA
VDD
CSb
SDIO
SCLK
Si5380
Figure 6.1. I2C/SPI Device Connectivity Configurations
om
In some cases it is not known prior to the design, what the serial interface type and I/O voltage will be. Setting the device to 1.8 V
(IO_VDD_SEL = 0) digital I/O in the NVM allows the host to reliably write the device, regardless of its operating voltage. Once the serial
interface type has been chosen using the I2C_SEL pin, the device may be written successfully regardless of the host interface type.
This is true for both 3-wire and 4-wire SPI modes as well as I2C. The SPI serial data is written to the same SDA/SDIO input pin in all
cases. At this point, the device can be configured to adjust IO_VDD_SEL for optimum 3.3 V operation and to select SPI_3WIRE between 3-/4-wire SPI modes. These mode changes are made immediately and no delays or wait times are needed for subsequent serial
interface operations, including read operations.
ec
Note that the registers are organized into multiple pages to allow a larger register set, given the limitations of the I2C/SPI interface
standards. First, the correct page must be selected with the initial write. Then the register location within that page can be read/written.
See "AN926: Reading and Writing Registers with SPI and I2C for Si534x/8x Devices" for more information on register paging.
N
ot
R
If neither serial interface is used, the SDA/SDIO, A1/SDO, and SCLK pins must be pulled either high or low externally since they are not
pulled internally. I2C_SEL and A0/CSb have internal pull-ups and may be left unconnected in this case. Note that the Si5380 is not I2C
failsafe upon loss of power. Applications that require failsafe operation should isolate the device from a shared I2C bus.
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Serial Interface
The following table lists register settings of interest for the I2C/SPI serial interface operation.
Table 6.1. I2C/SPI Configuration Registers
Register Name
Hex Address [Bit Field]
IO_VDD_SEL
0x0943[0]
Function
Select digital I/O operating voltage.
es
ig
ns
0: 1.8 V digital I/O connections (default)
1: 3.3 V digital I/O connections
SPI_3WIRE
0x002B[3]
Selects operating mode for SPI interface:
0: 4-wire SPI (default)
1: 3-wire SPI
0x000B[6:0]
D
7-bit I2C Address. See 6.1 I2C Interface for
more information.
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
I2C_ADDR
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Serial Interface
6.1 I2C Interface
I2C
VDD
VDD/I2C
Si5380
I2C_SEL
SDA
To I2C Bus
or Host
D
SCLK
es
ig
ns
When in I2C mode, the serial interface operates in slave mode with 7-bit addressing and operates in either Standard-Mode (100 kbps)
or Fast-Mode (400 kbps) while supporting burst data transfer with auto address increments. The I2C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in the figure below. Both the SDA and SCL pins must be connected to a
supply via an external pull-up (4.7 kΩ) as recommended by the I2C specification. Two address select pins, A1 and A0, are provided,
allowing up to four Si5380 devices to communicate on the same bus. This also allows four choices in the I2C address for systems that
may have other overlapping addresses for other I2C devices.
N
ew
A0
LSBs of I2C
Address
A1
Figure 6.2. I2C Configuration
fo
r
The 7-bit I2C slave device address of the Si5380 consists of a 5-bit fixed address plus two bit determined by the voltages on the A1 and
A0 input pins, as shown in the figure below.
5
4
3
2
1
1
0
1
0
m
en
de
d
Slave Address
6
1
0
A1 A0
Figure 6.3. 7-bit I2C Slave Address Bit-Configuration
The I2C bus supports SDA timeout for compatibility with SMB Bus interfaces. The error indicator and flag are listed in the registers
listed in the table below. See 3.3 Fault Monitoringfor more information.
Table 6.2. SMB Bus Timeout Error Registers
om
Register Name
R
N
ot
SMBUS_TIMEOUT_FLG
Function
SMB Bus Timeout Indicator.
0x000C[5]
0: SMB Bus Timeout has Not occurred
1: SMB Bus Timeout Has occurred
ec
SMBUS_TIMEOUT
Hex Address [Bit Field]
0x0011[5]
SMB_TMOUT indicator sticky flag bit. Remains asserted after the indicator bit shows
a fault until cleared by the user. Writing a 0
to the flag bit will clear it if the indicator bit
is no longer asserted.
Data is transferred MSB first in 8-bit words as specified by the I2C specification. A write command consists of a 7-bit device (slave)
address + a write bit, an 8-bit register address, and 8 bits of data as shown in the figure below. A write burst operation is also shown
where subsequent data words are written using to an auto-incremented address.
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Serial Interface
Write Operation – Single Byte
S
Slv Addr [6:0]
0
A Reg Addr [7:0] A
Data [7:0]
A
P
A
Data [7:0]
Write Operation - Burst (Auto Address Increment)
Slv Addr [6:0]
0
A Reg Addr [7:0] A
Data [7:0]
A
P
es
ig
ns
S
Reg Addr +1
Si5380
Host
Si5380
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
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Figure 6.4. I2C Write Operation
A read operation is performed in two stages. A data write is used to set the register address, then a data read is performed to retrieve
the data from the set address. A read burst operation is also supported. This is shown in the following figure.
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Read Operation – Single Byte
S
Slv Addr [6:0]
0
A Reg Addr [7:0] A
S
Slv Addr [6:0]
1
A
N P
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Data [7:0]
P
Read Operation - Burst (Auto Address Increment)
Slv Addr [6:0]
0
A Reg Addr [7:0] A
S
Slv Addr [6:0]
1
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S
Si5380
Host
Si5380
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Data [7:0]
A
P
Data [7:0]
N P
Reg Addr +1
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
Figure 6.5. I2C Read Operation
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Serial Interface
6.2 SPI Interface
When in SPI mode, the serial interface operates in 4-wire or 3-wire depending on the state of the SPI_3WIRE configuration bit,
0x000B[3]. The 4-wire interface consists of a clock input (SCLK), a chip select input (CSb), serial data input (SDI), and serial data output (SDO). The 3-wire interface combines the SDI and SDO signals into a single bidirectional data pin (SDIO). Both 4-wire and 3-wire
interface connections are shown in the following figure.
I2C_SEL
I2C_SEL
CSb
To SPI
Host
SDO
SCLK
Si5380
SDIO
SCLK
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To SPI
Host
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CSb
SDI
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SPI 3-Wire
SPI_3WIRE = 1
SPI 4-Wire
SPI_3WIRE = 0
Si5380
Figure 6.6. SPI Interface Connections
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Table 6.3. SPI Command Formats
Ist Byte1
2nd Byte
3rd Byte
Nth Byte2,3
Set Address
000x xxxx
8-bit Address
-
-
Write Data
010x xxxx
8-bit Data
-
-
100x xxxx
8-bit Data
-
-
011x xxxx
8-bit Data
-
-
101x xxxx
8-bit Data
-
-
1110 0000
8-bit Address
8-bit Data
8-bit Data
Read Data
Write Data + Address Increment
Read Data + Address Increment
Burst Write Data
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Instruction
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Note:
1. X = don't care (1 or 0)
2. The Burst Write Command is terminated by de-asserting CSb (CSb = high)
3. There is no limit to the number of data bytes that follow the Burst Write Command, but the address will wrap around to zero in the
byte after address 255 is written.
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Writing or reading data consist of sending a “Set Address” command followed by a “Write Data” or “Read Data” command. The 'Write
Data + Address Increment' or “Read Data + Address Increment” commands are available for cases where multiple byte operations in
sequential address locations is necessary. The “Burst Write Data” instruction provides a compact command format for writing data
since it uses a single instruction to define starting address and subsequent data bytes. The first figure below shows an example of writing three bytes of data using the write commands. This demonstrates that the “Write Burst Data” command is the most efficient method
for writing data to sequential address locations. Figure 6.8 Example of Reading Three Data Bytes Using the SPI Read Commands on
page 60 provides a similar comparison for reading data with the read commands. Note that there is no burst read, only read increment.
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Serial Interface
‘Set Addr’
Addr [7:0]
‘Write Data’
Data [7:0]
‘Set Addr’
Addr [7:0]
‘Write Data’
Data [7:0]
‘Set Addr’
Addr [7:0]
‘Write Data’
Data [7:0]
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‘Set Address’ and ‘Write Data’
‘Set Address’ and ‘Write Data + Address Increment’
‘Write Data + Addr Inc’
‘Write Data + Addr Inc’
Data [7:0]
‘Write Data + Addr Inc’
Data [7:0]
‘Burst Write Data’
Host
Addr [7:0]
Si5380
Data [7:0]
Data [7:0]
Data [7:0]
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‘Burst Write Data’
Data [7:0]
D
Addr [7:0]
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‘Set Addr’
Host
Si5380
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Figure 6.7. Example Writing Three Data Bytes Using the SPI Write Commands
‘Set Address’ and ‘Read Data’
Addr [7:0]
‘Read Data’ Data [7:0]
‘Set Addr’
Addr [7:0]
‘Read Data’ Data [7:0]
‘Set Addr’
Addr [7:0]
‘Read Data’ Data [7:0]
om
‘Set Addr’
‘Set Address’ and ‘Read Data + Address Increment’
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‘Set Addr’
Addr [7:0]
‘Read Data + Addr Inc’
‘Read Data + Addr Inc’
Data [7:0]
‘Read Data + Addr Inc’
Data [7:0]
Host
Si5380
Host
Data [7:0]
Si5380
Figure 6.8. Example of Reading Three Data Bytes Using the SPI Read Commands
The timing diagrams for the SPI commands are shown in the following figures.
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Serial Interface
Previous
Command
Next
Command
‘Set Address’ Command
>1.9
SCLK
Periods
2 Cycle
Wait
Base Address
SCLK
4-Wire
0
7
6
5
4
3
2
1
0
7
6
1
0
7
6
5
4
3
2
1
0
7
6
SDO
SDIO
Si5380
Host
3
2
Si5380
1
0
5
4
3
2
Don’t Care
1
0
7
6
7
6
High Impedance
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4
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3-Wire
5
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1
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SDI
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Set Address Instruction
CSb
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Figure 6.9. SPI "Set Address" Command Timing
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Serial Interface
Previous
Command
Next
Command
‘Write Data’
2 Cycle
Wait
SCLK
4-Wire
0
7
6
5
4
3
2
1
0
7
6
1
0
7
6
5
4
3
2
1
0
7
6
SDO
SDIO
Host
Host
Si5380
Si5380
4
5
4
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3-Wire
5
3
2
1
0
D
1
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SDI
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Data byte @ base address
or
Data byte @ base address + 1
Write Data instruction
CSb
>1.9
SCLK
Periods
3
Don’t Care
2
1
0
7
6
7
6
High Impedance
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Figure 6.10. SPI "Write Data" and "Write Data + Address Increment" Instruction Timing
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Serial Interface
Previous
Command
Next
Command
‘Read Data’
2 Cycle
Wait
Read byte @ base address
or
Read byte @ base address + 1
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Read Data instruction
CSb
SCLK
4-Wire
0
SDO
1
0
1
0
7
6
5
4
3
2
1
0
D
1
7
6
7
6
3-Wire
6
5
4
3
Host
Si5380
2
1
Si5380
0
3
2
1
0
7
6
5
4
3
2
1
0
7
6
High Impedance
Don’t Care
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Host
7
6
4
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SDIO
7
5
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SDI
>1.9
SCLK
Periods
Figure 6.11. SPI "Read Data" and "Read Data + Address Increment" Instruction Timing
Previous
Command
2 Cycle
Wait
Burst Write Instruction
CSb
SCLK
1
7
R
3-Wire
1
0
N
ot
SDIO
6
5
4
nth data byte @ base address +n
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
ec
SDO
0
>1.9
SCLK
Periods
1st data byte @ base address
Base address
om
4-Wire
SDI
Next
Command
‘Burst Data Write’ Command
Host
Si5380
7
6
5
4
Host
Si5380
Don’t Care
High Impedance
Figure 6.12. SPI "Burst Data Write" Instruction Timing
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Field Programming
7. Field Programming
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To simplify design and software development of systems using the Si5380, a field programmer is available. The ClockBuilder Pro Field
Programmer supports both “in-system” programming for devices already mounted on a PCB, as well as “in-socket” programming of
Si5380 sample devices. Refer to http://www.silabs.com/CBProgrammer for information about this kit.
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XAXB External References
8. XAXB External References
8.1 Performance of External References
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An external standard non-pullable crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra low phase
noise reference clock for the DSPLL, as well as providing a stable reference for the Freerun and Holdover modes. Simplified connection
diagrams are shown below. The device includes internal 8 pF crystal loading capacitors which eliminates the need for external capacitors and also has the benefit of reduced noise coupling from external sources. In most applications, using the internal OSC with an
external crystal provides the best phase noise performance. See "AN905: Si534x External References; Optimizing Performance" for
more information on the performance of various XOs with these devices. The recommended crystal suppliers are listed in Si534x/8x
Jitter Attenuators Recommended Crystal, TCXO and OCXOs Reference Manual with crystal PCB layout recommendations in
9.1 Si5380 Crystal Layout Guidelines
Differential Connection
0. 1 uf
D
nc X1
nc X2
Note: 2. 0 Vpp_ se max
2xCL
0. 1 uf
XA
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0. 1 uf
Single-ended XO Connection
nc X1
nc X2
2xCL
0. 1 uf
Si5380
Note: 2. 5 Vpp diff max
Single-ended Connection
Note: 2. 0 Vpp_ se max
R1
3.3 V
2.5 V
1.8 V
R1
R2
523
475
158
442
649
866
0. 1 uf
R2
0. 1 uf
OSC
0. 1 uf
OSC
Si5380
Crystal Connection
X1
2xCL
XA
2xCL
2xCL
XA
XTAL
OSC
XB
2xCL
Si5380
XB
X2
2xCL
Si5380
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XO VDD
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nc X1
nc X2
CMOS/ XO Output
XA
XO with Clipped Sine Wave
XB
0. 1 uf
Output
XB
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50
OSC
2xCL
Figure 8.1. XAXB Crystal Resonator and External Reference Clock Connection Options
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In addition to crystal operations, the Si5380 accepts a Clipped Sine wave, CMOS, or Differential reference clock on the XAXB interface.
Most clipped sine wave and CMOS TCXOs have insufficient drive strength to drive a 50 Ω or 100 Ω load. For this reason, place the
TCXO as close to the Si5380 as possible to minimize PCB trace length. In addition, connect both the Si5380 and the TCXO directly to
the same ground plane. The figure above shows the recommended method of connecting a clipped sine wave TCXO to the Si5380.
Because the Si5380 provides dc bias at the XA and XB pins, the ~800 mV peak-peak swing can be input directly into XA after accoupling. Single-ended inputs must be connected to the XA pin with proper termination on the XB pin. Because the signal is singleended in this case, the XB input is ac-coupled to ground. The figure above also illustrates the recommended method of connecting a
single-ended CMOS rail-to-rail output to the XAXB inputs of the Si5380. The resistor network attenuates the swing to ensure that the
maximum input voltage swing at the XA pin remains below the datasheet specification. The signal is ac-coupled before connecting it to
the Si5380 XA input. For applications with loop bandwidth values less than 10 Hz that require low wander output clocks, using a TCXO
as the XAXB reference source should be considered to avoid the wander of a crystal.
8.2 Recommended Crystals and External Oscillators
Please refer to the Si534x/8x Jitter Attenuators Recommended Crystal, TCXO and OCXOs Reference Manual for more information.
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XAXB External References
8.3 XAXB Control Register Settings
The following registers can be used to control and make adjustments for the external reference source used.
8.3.1 XAXB_EXTCLK_EN Reference Clock Selection Register
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Table 8.1. XAXB External Clock Selection Register
Register Name
Hex Address [Bit Field]
Function
XAXB_EXTCLK_EN
090E[0]
This bit selects between the Crystal or External reference clock on the XAXB pins.
0: Crystal on XAXB, enable internal XO
(default)
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1: External XAXB signal, internal XO disabled
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Crystal and Device Circuit Layout Recommendations
9. Crystal and Device Circuit Layout Recommendations
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The main layout issues that should be carefully considered for optimum phase noise include the following:
• Number and size of the ground vias for the Epad (see 10.4 Grounding Vias)
• Output clock trace routing
• Input clock trace routing
• Control and Status signals to input or output clock trace coupling
• Xtal signal coupling
• Xtal layout (see 9.1 Si5380 Crystal Layout Guidelinesbelow for important crystal layout guidelines)
If the application uses a crystal for the XAXB inputs, a shield should be placed underneath the crystal connected to the X1 and X2 pins
(7 and 10) to provide the best possible performance. The shield should not be connected to the ground plane and the planes underneath should overlap under the shield as little as possible. It may be difficult to do this for all the layers, but it is important to do this for
the layers that are closest to the shield.
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Go to http://www.silabs.com/Si538x-4x-EVB to obtain Si5380-EVB schematics, layouts, and component BOM files.
9.1 Si5380 Crystal Layout Guidelines
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The following are five recommended crystal guidelines:
1. Place the crystal as close as possible to the XAXB pins.
2. DO NOT connect the crystal's GND pins to the PCB gnd.
3. Connect the crystal's "GND" pins to the devices X1 and X2 pins via a local crystal shield placed around and under the crystal. See
the bottom right diagram of Figure 9.1 External XO: Si5381/82 Device and XO Layout Recommendations, Top Layer (Layer 1) on
page 68for an illustration of how to connect the crystal shield by placing vias connecting the top layer traces to the shield layer
underneath. The second layer of the ground shield is shown in Figure 9.2 External XO: Input Clocks and Ground Fill, Below the
Top Layer (Layer 2) on page 69.
4. Minimize traces adjacent to the crystal/oscillator area especially if they are clocks or frequent toggling digital signals, such as serial
interface lines.
5. In general, do not route GND, power planes/traces, or locate components on the other side of the PCB, below the crystal GND
shield. As an exception, if it is absolutely necessary to use the area on the other side of the board for layout or routing, then place
the next reference plane in the stack-up at least two layers away or on a layer at least 50 mils (0.05") away. The crystal should
have all layers underneath the ground shield removed.
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Crystal and Device Circuit Layout Recommendations
9.2 Si5381/82 64-Pin QFN with External XO Layout Recommendations
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This section details the recommended guidelines for the layout of the 64-pin QFN Si5381/82 with external XO using the 8-layer
Si5381A-E-EB PCB. The following are the descriptions of each of the eight layers.
• Layer 1: device layer, with low speed CMOS control/status signals, ground flooded
• Layer 2: input clocks, ground flooded
• Layer 3: ground plane
• Layer 4: power distribution, ground flooded
• Layer 5: power routing layer
• Layer 6: ground input clocks, ground flooded
• Layer 7: output clocks layer
• Layer 8: ground layer
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External XO: The figure below shows the top layer layout of the Si5381/82 device mounted on the PCB. The XO is outlined with the
white box around it. The top layer is flooded with ground. Both the XA and XB pins are capacitively coupled, with XB ac connected to
XO ground for single-ended output XO's. Notice the 5x5 array of thermal vias in the center of the device. See Grounding Vias for more
information on thermal/ground via layout.
Figure 9.1. External XO: Si5381/82 Device and XO Layout Recommendations, Top Layer (Layer 1)
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External XO: The following figure shows the layer that implements the ground shield underneath the XO. This layer also has the clock
input pins. The clock input pins go to layer 2 using vias to avoid crosstalk. As soon as the clock inputs are on layer 2, they have a
ground shield above, below, and on the sides for maximum protection.
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Crystal and Device Circuit Layout Recommendations
Figure 9.2. External XO: Input Clocks and Ground Fill, Below the Top Layer (Layer 2)
Figure 9.3. External XO: Internal Ground Plane (Layer 3)
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External XO: The figure below shows one of the ground planes. Figure 9.4 External XO: Internal Power Plane (Layer 4) on page 70 is
a power plane and shows the clock output power supply traces.
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Crystal and Device Circuit Layout Recommendations
Figure 9.4. External XO: Internal Power Plane (Layer 4)
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External XO: The figure below shows layer 5, which is the power plane routed to the clock output power pins.
Figure 9.5. External XO: Internal Power Plane (Layer 5)
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External XO: The figure below shows layer 6, another ground plane similar to layer 3.
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Crystal and Device Circuit Layout Recommendations
Figure 9.6. External XO: Internal Ground Plane (Layer 6)
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External XO: The figure below shows the output clocks. Similar to the input clocks, the output clocks have vias that immediately go to a
buried layer with a ground plane above them and a ground flooded bottom layer. There is ground flooding between the clock output
pairs to reduce crosstalk. There should be a line of vias through the ground flood on either side of the output clocks to ensure that the
ground flood immediately next to the differential pairs has a low inductance path to the ground plane on layers 3 and 6.
Figure 9.7. External XO: Output Clocks (Layer 7)
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External XO: The bottom layer shown in the figure below displays the location of the decoupling capacitors close to the device.
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Crystal and Device Circuit Layout Recommendations
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Figure 9.8. External XO: Bottom Layer Ground Flooded (Layer 8)
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Power Management
10. Power Management
10.1 Power Management Features
Table 10.1. Powerdown Registers
Register Name
Hex Address [Bit Field]
PDN
0x001E[0]
Function
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A number of unused functions can be powered down to minimize power consumption. The registers listed in the table below are used
for powering down different features of the device.
Place the device into a low current Powerdown state. Note that the serial interface
and registers remain active in this state.
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0: Normal Operation (default)
1: Powerdown Device
OUT0_PDN
0x0108[0]
OUT1_PDN
0x010D[0]
OUT2_PDN
0x0112[0]
OUT3_PDN
0x0117[0]
OUT4_PDN
0x011C[0]
OUT5_PDN
0x0121[0]
OUT6_PDN
0x0126[0]
OUT8_PDN
OUT9_PDN
OUT9A_PDN
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OUT7_PDN
1: Powerdown output driver
When powered down, output pins will be
high impedance with a light pull down effect.
0x0130[0]
0x0135[0]
0x013A[0]
0x0145[0]
Powers down all output drivers.
0: Normal Operation (default)
1: Powerdown All output drivers
0x090E[1]
Powers down the built-in low noise crystal
oscillator when using an external reference
input.
0: Powerdown Internal Oscillator
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IN_EN
0: Power-up output driver (default)
0x012B[0]
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XAXB_XO_EN
Powers down unused output drivers.
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OUT0A_PDN
1: Internal Oscillator Powered (default) - required when using a crystal with the XAXB
oscillator.
0x0949[3:0]
Enable (or powerdown) the IN3 - IN0 input
buffers.
0: Powerdown input buffer
1: Enable and Power-up input buffer
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Power Management
10.2 Power Supply Recommendations
Power supply filtering is generally important for optimal timing performance. The Si5380 devices have multiple stages of on-chip regulation to minimize the impact of board level noise on clock jitter. Following conventional power supply filtering and layout techniques will
minimize signal degradation from power supply noise.
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It is recommended to use a 0402-size 1 mF ceramic capacitor on each power supply pin for optimal performance. If the supply voltage
is extremely noisy, it might require a ferrite bead in series between the voltage supply voltage and the device power supply pin.
10.3 Power Supply Sequencing
Four classes of supply voltages exist on the Si5380:
1. VDD = 1.8 V (Core digital supply)
2. VDDA = 3.3 V (Analog supply)
3. VDDO = 1.8/2.5/3.3 V (Output Clock supplies)
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There is no general requirement for power supply sequencing on this device unless the output clocks are required to be phase
aligned with each other. In this case, the VDDO of each clock which needs to be aligned must be powered up before VDD and
VDDA.
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If output-to-output alignment is required for applications where it is not possible to properly sequence the power supplies, then the
output clocks can be aligned by asserting Hard Reset 0x001E[1] register bits or driving the RSTb pin. Note that using a Hard Reset
will reload the register with the contents of the NVM and any unsaved register changes will be lost.
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When powering up the VDD = 1.8V rail first, it can be observed that the VDDA = 3.3 V rail will initially follow the 1.8 V rail. Likewise,
if the VDDA rail is powered down first then it will not drop far below VDD until VDD itself is powered down. This is due to the pad
I/O circuits, which have large MOSFET switches to select the local supply from either the VDD or VDDA rails. These devices are
relatively large and yield a parasitic diode between VDD and VDDA. Allow for both VDD and VDDA to power-up and power-down
before measuring their respective voltages.
10.4 Grounding Vias
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The "Epad" on the bottom of the device functions as both the sole electrical ground and as the primary heat transfer path. Hence it is
important to minimize the inductance and maximize the heat transfer from this pad to the internal ground plane of the PCB. Use no
fewer than 25 vias from the center pad to a ground plane under the device. In general, more vias will perform better. Having the ground
plane near the top layer will also help to minimize the via inductance from the device to ground and maximize the heat transfer away
from the device.
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Base vs. Factory Preprogrammed Devices
11. Base vs. Factory Preprogrammed Devices
The Si5380 devices can be ordered as "base" or "factory-preprogrammed" (also known as "custom OPN") versions.
11.1 "Base" Devices (a.k.a. "Blank" Devices)
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• Example "base" orderable part numbers (OPNs) are of the form "Si5380A-D-GM."
• Base devices are available for applications where volatile reads and writes are used to program and configure the device for a particular application.
• Base devices do not power up in a usable state (all output clocks are disabled).
• Base devices are, however, configured by default to use a 48 MHz crystal on the XAXB reference and a 1.8 V compatible I/O voltage setting for the host I2C/SPI interface.
• Additional programming of a base device is mandatory to achieve a usable configuration.
• See the on-line lookup utility at www.silabs.com/products/clocksoscillators/pages/clockbuilderlookup.aspx to access the default configuration plan and register settings for any base OPN.
11.2 "Factory Preprogrammed" (Custom OPN) Devices
m
en
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r
N
ew
• Factory preprogammed devices use a “custom OPN”, such as Si5380A-Dxxxxx-GM, where “xxxxx” is a sequence of characters assigned by Silicon Labs for each customer-specific configuration. These characters are referred to as the “OPN ID”. Customers must
initiate custom OPN creation using the ClockBuilder Pro software.
• Many customers prefer to order devices which are factory preprogrammed for a particular application that includes specifying the
XAXB reference frequency/type, the clock input frequencies, the clock output frequencies, as well as the other options, such as automatic clock selection, loop bandwidth, etc. The ClockBuilder software is required to select among all of these options and to produce a project file which Silicon Labs uses to preprogram all devices with custom orderable part number (“custom OPN”).
• Custom OPN devices contain all of the initialization information in their non-volatile memory (NVM) so that it powers up fully configured and ready to go.
• Because preprogrammed device applications are inherently quite different from one another, the default power up values of the register settings can be determined using the custom OPN utility at: http://www.silabs.com/products/clocksoscillators/pages/clockbuilderlookup.aspx
• Custom OPN devices include a device top mark which includes the unique OPN ID. Refer to the device data sheet's Ordering Guide
and Top Mark sections for more details.
Both "base" and "factory preprogrammed" devices can have their operating configurations changed at any time using volatile reads and
writes to the registers. Both types of devices can also have their current register configuration written to the NVM by executing an NVM
bank burn sequence (see 2.1.3 NVM Programming).
11.3 Part Numbering Summary
Part numbers are of the form:
om
Si<Part Num Type><Grade>-<Device Revision><OPN ID>-<Temp Grade><Package ID>
N
ot
R
ec
For example:
• Si5380A-D12345-GM: Applies to a factory preprogrammed OPN (Ordering Part Number) device. These devices are programmed at
the factory with the frequency plan and all other operating characteristics defined by the user's ClockBuilder Pro project file.
• Si5380A-D-GM: Applies to a "base" device. Base devices are factory programmed to a specific base part type (e.g., Si5380) but
exclude any user-defined frequency plan or other operating characteristics which would be selected in ClockBuilder Pro.
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Register Map
12. Register Map
12.1 Page 0 Registers
Table 12.1. Register 0x0000 Die Rev
Bit Field
Type
Name
Default
0x0000
3:0
R
DIE_REV
0
Description
es
ig
ns
Reg Address
4-bit die revision number
Table 12.2. Register 0x0001 Page
Bit Field
Type
Name
Default
0x0001
7:0
R/W
PAGE
0
Description
Select one of 256 possible
pages.
D
Reg Address
N
ew
This is the “Page Register” which is located at address 0x01 on every page. When read, it will indicate the current page. When written,
it will change the page to the value entered. There is a page register at address 0x0001, 0x0101, 0x0201, 0x0301, … etc. See "AN926:
Reading and Writing Registers with SPI and I2C for Si534x/8x Devices" for more information on register paging.
Table 12.3. Register 0x0002-0x0003 Base Part Number
Type
0x0002
7:0
R
0x0003
15:8
R
Name
Default
Description
PN_BASE
0x80
PN_BASE
0x53
Four-digit ,"base" part number, one nibble per digit. Example: Si53280A-D-GM. The
base part number is 5380,
which is stored in this register.
fo
r
Bit Field
m
en
de
d
Reg Address
See 11.3 Part Numbering Summary for more information on part numbers.
Table 12.4. Register 0x0004 Device Grade
Reg Address
Type
Name
Description
7:0
R
GRADE
One ASCII character indicating the
device speed grade. For example
Si5380A-D12345-GM would be 0,
grade A:
om
0x0004
Bit Field
ec
0 = A, 1 = B, 2 = C, 3 = D, etc.
R
See 11.3 Part Numbering Summary for more information on part numbers. Refer to the device data sheet Ordering Guide section for
more information about device grades.
Table 12.5. Register 0x0005 Device Revision
Bit Field
Type
Name
Description
0x0005
7:0
R
DEVICE_REV
One ASCII character indicating the
device revision level.
N
ot
Reg Address
0 = A; 1 = B; 2 = C, 3 = D, etc.
For example: Si5380A-D12345GM, the device revision is D.
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Register Map
See 11.3 Part Numbering Summary for more information on part numbers. Refer to the device data sheet Ordering Guide section for
more information about device grades.
Table 12.6. Register 0x0009 Temperature Grade
Bit Field
Type
Name
Description
0x0009
7:0
R
TEMP_GRADE
Device temperature grade:
es
ig
ns
Reg Address
0: Industrial (-40 to 85 °C
See 11.3 Part Numbering Summary for more information on part numbers.
Table 12.7. Register 0x000A Package ID
Bit Field
Type
Name
0x000A
7:0
R
PKG_ID
Description
D
Reg Address
Package Identifier:
See 11.3 Part Numbering Summary for more information on part numbers.
N
ew
0: 9x9 mm 64 QFN
Table 12.8. Register 0x000B I2C Address
Bit Field
0x000B
6:0
Type
fo
r
Reg Address
R
Name
Description
I2C_ADDR
7-bit I2C Address
m
en
de
d
Note that the 2 least significant bits, [1:0], are determined by the voltages on the A1 and A0 input pins respectively.
Table 12.9. Register 0x000C Device Status
Reg Address
0x000C
0x000C
0x000C
ec
0x000C
Type
Name
Description
0
R
SYSINCAL
1 if the device is currently calibrating.
1
R
LOSXAXB
1 if there is currently no signal at
the XAXB pins.
2
R
LOSREF
1 if there is currently no signal detected on the XAXB input signal.
3
R
XAXB_ERR
1 if there is currently a problem
locking to the XAXB input signal.
5
R
SMBUS_TIMEOUT
1 if there is currently an SMB Bus
Timeout error.
om
0x000C
Bit Field
N
ot
R
See 3.3 Fault Monitoring for more information.
Table 12.10. Register 0x000D Out-of-Frequency (OOF) and Loss-of Signal (LOS) Status
Reg Address
Bit Field
Type
Name
Description
0x000D
3:0
R
LOS
1 if IN3 - IN0 is currently LOS
0x000D
7:4
R
OOF
1 if IN3 - IN0 is currently OOF
See 3.3 Fault Monitoring for more information.
• IN0: LOS 0x000D[0], OOF 0x000D[4]
• IN1: LOS 0x000D[1], OOF 0x000D[5]
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Register Map
• IN2: LOS 0x000D[2], OOF 0x000D[6]
• IN3/FB_IN: LOS 0x000D[3], OOF 0x000D[7]
Table 12.11. Register 0x000E Holdover (HOLD) and Loss-of-Lock (LOL) Status
Bit Field
Type
Name
0x000E
1
R
LOL
0x000E
5
R
HOLD
Description
1 if the DSPLL is currently out of
lock
1 if the DSPLL is currently in Holdover or Freerun
See 3.3 Fault Monitoring for more information.
Type
Name
0x000F
5
R
CAL
Description
1 if the DSPLL internal calibration
is currently busy
N
ew
Bit Field
D
Table 12.12. Register 0x000F DSPLL Calibration Status
Reg Address
es
ig
ns
Reg Address
See 3.3 Fault Monitoring for more information.
fo
r
Table 12.13. Register 0x0011 Device Status Flags
Bit Field
Type
Name
0x0011
0
R/W
SYSINCAL_FLG
Flag 1 if the device was in SYSINCAL
0x0011
1
R/W
LOSXAXB_FLG
Flag 1 if the XAXB input showed LOSXAXB
0x0011
2
R/W
LOSREF_FLG
0x0011
3
R/W
XAXB_ERR_FLG
0x0011
5
R/W
SMBUS_TIMEOUT_FLG
m
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Reg Address
Description
Flag 1 if the XAXB input LOSREF
Flag 1 if the XAXB input showed XAXB_ERR
Flag 1 if SMBUS_TMEOUT ws in error
These are sticky flag bits corresponding to the bits in register 0x000C. They are cleared by writing 0 to the bit that has been set. The
corresponding 0x000C register bit must be 0 to clear this sticky flag bit. See 3.3 Fault Monitoring for more information.
Reg Address
ec
0x0012
om
Table 12.14. Register 0x0012 OOF and LOS Status Flags
0x0012
Bit Field
Type
Name
Description
3:0
R/W
LOS_FLG
Flag 1 if IN3 - IN0 was or is LOS
7:4
R/W
OOF_FLG
Flag 1 if IN3 - IN0 was or is OOF
N
ot
R
These are sticky flag bits corresponding to the bits in register 0x000D. They are cleared by writing 0 to the bit that has been set. The
corresponding 0x000D register bit must be 0 to clear this sticky flag bit. See 3.3 Fault Monitoring for more information.
• IN0: LOS_FLG 0x0012[0], OOF_FLG 0x0012[4]
• IN1: LOS_FLG 0x0012[1], OOF_FLG 0x0012[5]
• IN2: LOS_FLG 0x0012[2], OOF_FLG 0x0012[6]
• IN3/FB_IN: LOS_FLG 0x0012[3], OOF_FLG 0x0012[7]
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Register Map
Table 12.15. Register 0x0013 HOLD and LOL Status Flags
Bit Field
Type
Name
0x0013
1
R/W
LOL_FLG
0x0013
5
R/W
HOLD_FLG
Description
Flag 1 if the DSPLL was or is LOL
Flag 1 if the DSPLL was or is in
Holdover or Freerun
es
ig
ns
Reg Address
These are sticky flag bits corresponding to the bits in register 0x000E. They are cleared by writing 0 to the bit that has been set. The
corresponding 0x000E register bit must be 0 to clear this sticky flag bit. See 3.3 Fault Monitoring for more information.
Table 12.16. Register 0x0014 DSPLL Calibration Status Flag
Type
Name
0x0014
5
R/W
CAL_FLG
Description
D
Bit Field
Flag 1 if the internal calibration was
or is busy
N
ew
Reg Address
These are sticky flag bits corresponding to the bits in register 0x000F. They are cleared by writing 0 to the bit that has been set. The
corresponding 0x000F register bit must be 0 to clear this sticky flag bit. See 3.3 Fault Monitoring for more information.
Table 12.17. Register 0x0017 Device Status Interrupt Masks
Type
0x0017
0
R/W
0x0017
1
R/W
0x0017
2
0x0017
3
0x0017
5
Name
fo
r
Bit Field
Description
SYSINCAL_INTR_MSK
1 to mask SYSINCAL_FLG from
causing an interrupt
LOSXAXB_FLG_MSK
1 to mask LOSXAXB_FLG from
causing an interrupt
m
en
de
d
Reg Address
R/W
LOSREF_INTR_MSK
1 to mask LOSREF_FLG from
causing an interrupt
R/W
XAXB_ERR_INTR_MSK
1 to mask LOL_FLG from causing
an interrupt
R/W
SMBUS_IMOUT_ FLG_MSK
1 to mask SMBUS_TMOUT_FLG
from causing an interrupt
om
These are interrupt mask bits corresponding to the bits in register 0x0011. See 3.3.6 INTRb Interrupt Configuration for more information.
ec
Table 12.18. Register 0x0018 OOF and LOS Interrupt Masks
Bit Field
Type
Name
Description
0x0018
3:0
R/W
LOS_INTR_MSK
1 to mask LOS_FLG from causing
an interrupt
7:4
R/W
OOF_INTR_MSK
1 to mask OOF_FLG from causing
an interrupt
R
Reg Address
N
ot
0x0018
These are interrupt mask bits corresponding to the bits in register 0x0012. See 3.3.6 INTRb Interrupt Configuration for more information.
• IN0: LOS_INTR_MSK 0x0018[0], OOF_INTR_MSK 0x0018[4]
• IN1: LOS_INTR_MSK 0x0018[1], OOF_INTR_MSK 0x0018[5]
• IN2: LOS_INTR_MSK 0x0018[2], OOF_INTR_MSK 0x0018[6]
• IN3/FB_IN: LOS_INTR_MSK 0x0018[3], OOF_INTR_MSK 0x0018[7]
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Register Map
Table 12.19. Register 0x0019 HOLD and LOL Interrupt Masks
Bit Field
Type
Name
Description
0x0019
1
R/W
LOL_INTR_MSK
1 to mask LOL_FLG from causing
an interrupt
0x0019
5
R/W
HOLD_INTR_MSK
1 to mask HOLD_FLG from causing an interrupt
es
ig
ns
Reg Address
These are interrupt mask bits corresponding to the bits in register 0x0013. See 3.3.6 INTRb Interrupt Configuration for more information.
Table 12.20. Register 0x001A PLL In Calibration Interrupt Mask
Type
Name
0x001A
5
R/W
CAL_INTR_MSK
Description
D
Bit Field
1 to mask CAL_FLG from causing
an interrupt
N
ew
Reg Address
These are interrupt mask bits corresponding to the bits in register 0x0014. See 3.3.6 INTRb Interrupt Configuration for more information.
Table 12.21. Register 0x001C Soft Reset and Calibration
Type
0x001C
0
S
Name
Description
SOFT_RST
1 Initialize and calibrate the device
fo
r
Bit Field
m
en
de
d
Reg Address
0 No effect
Soft Reset restarts the device using the existing register values without loading from NVM. Soft Reset also updates registers requiring a
separate update strobe, including the DSPLL bandwidth registers as well as the P, M, N, and R dividers.
Table 12.22. Register 0x001E Sync, Power Down and Hard Reset
Reg Address
Type
Name
Description
0
R/W
PDN
Place the device into a low current
Powerdown state. Note that the serial interface and registers remain
active in this state.
ec
om
0x001E
Bit Field
1
1: Powerdown Device
S
HARD_RST
N
ot
R
0x001E
0: Normal Operation (default)
0x001E
Perform Hard Reset with NVM
read.
0: Normal Operation
1: Hard Reset the device
2
S
SYNC
Resets all R dividers. Logically
equivalent to asserting the SYNCb
pin.
0: Normal Operation
1: Reset R Dividers
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Register Map
Table 12.23. Register 0x0022 Output Enable Group Controls
Reg Address
Bit Field
Type
Name
0x0022
0
R/W
OE_REG_SEL
Description
Selects between Pin and Register
control for output disable.
es
ig
ns
0: OEb Pin disable (default)
1: OE Register disable
0x0022
1
R/W
OE_REG_DIS
When OE_REG_SEL = 1:
0: Disable selected outputs
1: Enable selected outputs
N
ew
D
By default ClockBuilder Pro sets the OEb pin controlling all outputs. OUTALL_DISABLE_LOW (0x0102[0]) must be high (enabled) to
allow the OEb pin to enable outputs. Note that the OE_REG_DIS bit (active high) has inverted logic sense from the OEb pin (active
low). See 4.7.5 Output Driver Disable Source Summary for more information.
Table 12.24. Register 0x0023-0x0024 OE0 Output Disable Selection
Reg Address
Bit Field
Type
0x0023
0
R/W
1
Description
OE_OUT0A_SEL
Selects whether each output driver
is affected by the OEb pin or
OE_REG_DIS.
fo
r
OE_OUT0_SEL
2
OE_OUT1_SEL
3
m
en
de
d
OE_OUT2_SEL
4
OE_OUT3_SEL
5
OE_OUT4_SEL
6
OE_OUT5_SEL
7
OE_OUT6_SEL
0
R/W
0: Output Ignores OEb and
OE_REG_DIS
1: Output Disabled by OEb or
OE_REG_DIS
OE_OUT7_SEL
1
OE_OUT8_SEL
2
OE_OUT9_SEL
3
OE_OUT9A_SEL
om
0x0024
Name
R
ec
By default ClockBuilder Pro sets the OEb pin controlling all outputs. OUTALL_DISABLE_LOW (0x0102[0]) must be high (enabled) to
allow the OEb pin to enable outputs. See 4.7.5 Output Driver Disable Source Summary for more information.
N
ot
Reg Address
0x002B
Table 12.25. Register 0x002B SPI 3 vs 4 Wire
Bit Field
Type
Name
Description
3
R/W
SPI_3WIRE
Selects operating mode for SPI interface:
0: 4-wire SPI
1: 3-wire SPI
This bit is ignored for I2C bus operation, when I2C_SEL is high.
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Register Map
Table 12.26. Register 0x002C LOS Enables
Reg Address
Bit Field
Type
Name
Description
0x002C
3:0
R/W
LOS_EN
Enable LOS detection on IN3 - IN0.
es
ig
ns
0: Disable LOS Detection.
1: Enable LOS Detection.
0x002C
4
R/W
LOSXAXB_DIS
Enable LOS detection on the
XAXB inputs.
0: Enable LOS Detection (default).
1: Disable LOS Detection.
D
IN0: LOS_EN[0]
IN1: LOS_EN[1]
IN2: LOS_EN[2]
IN3/FB_IN: LOS_EN[3]
N
ew
•
•
•
•
Table 12.27. Register 0x002D LOS Clear Delays
Type
0x002D
1:0
R/W
Name
0x002D
0x002D
0x002D
LOS0_VAL_TIME
fo
r
Bit Field
m
en
de
d
Reg Address
Description
IN0 LOS Clear delay.
0: 2 ms
1: 100 ms
2: 200 ms
3: 1000 ms
3:2
R/W
LOS1_VAL_TIME
IN1, same as above
5:4
R/W
LOS2_VAL_TIME
IN2, same as above
7:6
R/W
LOS3_VAL_TIME
IN3/FB_IN, same as above
om
When a valid input clock is not present on the input, LOS will be asserted. When the clock returns, it must remain valid for this period of
time before that clock is considered to be qualified again.
Table 12.28. Register 0x002E-0x002F IN0 LOS Trigger Threshold
Bit Field
Type
Name
Description
0x002E
7:0
R/W
LOS0_TRG_THR
16-bit LOS Trigger Threshold value
0x002F
15:8
R/W
LOS0_TRG_THR
R
ec
Reg Address
N
ot
ClockBuilder Pro calculates the correct LOS register threshold trigger value for IN0, given a particular frequency plan.
Table 12.29. Register 0x0036-0x0037 LOS0 Clear Threshold
Reg Address
Bit Field
Type
Name
0x0036
7:0
R/W
LOS0_CLR_THR
0x0037
15:8
R/W
LOS0_CLR_THR
Description
16-bit LOS Clear Threshold value
ClockBuilder Pro calculates the correct LOS register clear threshold value for IN0, given a particular frequency plan.
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Register Map
All 4 input buffers are identical in terms of control. The single set of descriptions for IN0 above also apply to IN1-IN3.
Table 12.30. Output Registers Following the Same Definitions as IN0
Description
(Same as) Addresses
0x0030 - 0x0031
IN1 LOS Trigger Threshold
0x002E - 0x002F
0x0038 - 0x0039
IN1 LOS Clear Threshold
0x0036 - 0x0037
0x0032 - 0x0033
IN2 LOS Trigger Threshold
0x003A - 0x003B
IN2 LOS Clear Threshold
0x0034 - 0x0035
IN3/FB_IN LOS Trigger Threshold
0x003C - 0x003D
IN3/FB_IN LOS Clear Threshold
0x002E - 0x002F
0x0036 - 0x0037
Type
0x003F
3:0
R/W
0x0036 - 0x0037
Name
Description
OOF_EN
Enable Precision OOF for IN3 - IN0
N
ew
Bit Field
0x002E - 0x002F
D
Table 12.31. Register 0x003F OOF Enable
Reg Address
es
ig
ns
Register Addresses
0: Disable Precision OOF
1: Enable Precision OOF
R/W
FAST_OOF_EN
Enable Fast OOF for IN3 - IN0
0: Disable Fast OOF
1: Enable Fast OOF
IN0: OOF_EN[0], FAST_OOF_EN[4]
IN1: OOF_EN[1], FAST_OOF_EN[5]
IN2: OOF_EN[2], FAST_OOF_EN[6]
IN3/FB_IN: OOF_EN[3], FAST_OOF_EN[7]
m
en
de
d
•
•
•
•
7:4
fo
r
0x003F
Table 12.32. Register 0x0040 OOF Reference Select
Reg Address
Type
Name
2:0
R/W
OOF_REF_SEL
om
0x0040
Bit Field
Select reference 0 ppm
0: IN0
ec
1: IN1
2: IN2
3: IN3
4: XAXB
R
N
ot
Description
5-7: Reserved
Table 12.33. Register 0x0041 OOF0 Divider Select
Reg Address
Bit Field
Type
Name
0x0041
4:0
R/W
OOF0_DIV_SEL
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Description
Values calculated by CBPro.
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Si5380 Revision D Reference Manual
Register Map
Table 12.34. Register 0x0042 OOF1 Divider Select
Type
Name
0x0042
4:0
R/W
OOF1_DIV_SEL
Table 12.35. Register 0x0043 OOF2 Divider Select
Reg Address
Bit Field
Type
Name
0x0043
4:0
R/W
OOF2_DIV_SEL
Table 12.36. Register 0x0044 OOF3 Divider Select
Bit Field
Type
Name
0x0044
4:0
R/W
OOF3_DIV_SEL
Values calculated by CBPro.
Description
Values calculated by CBPro.
Description
Values calculated by CBPro.
N
ew
Reg Address
Description
es
ig
ns
Bit Field
D
Reg Address
Table 12.37. Register 0x0045 OOFXO Divider Select
Bit Field
Type
0x0045
4:0
R/W
Name
OOFXO_DIV_SEL
Description
Values calculated by CBPro.
fo
r
Reg Address
Table 12.38. Register 0x0046-0x0049 Precision OOF Set Thresholds
Bit Field
Type
Name
Description
7:0
R/W
OOF0_SET_THR
7:0
R/W
OOF1_SET_THR
Precision OOF Set Threshold. The
range is up to ±500 ppm in 1/16
ppm steps.
7:0
R/W
OOF2_SET_THR
7:0
R/W
OOF3_SET_THR
m
en
de
d
Reg Address
0x0046
0x0047
0x0048
0x0049
Set Threshold (ppm) =
OOFx_SET_THR x 1/16 ppm
OOF will be indicated if this is set
to 0.
Reg Address
om
Table 12.39. Register 0x004A-0x004D Precision OOF Clear Thresholds
Bit Field
Type
Name
7:0
R/W
OOF0_CLR_THR
0x004B
7:0
R/W
OOF1_CLR_THR
0x004C
7:0
R/W
OOF2_CLR_THR
0x004D
7:0
R/W
OOF3_CLR_THR
N
ot
R
ec
0x004A
silabs.com | Building a more connected world.
Description
Precision OOF Clear Threshold.
The range is up to ±500 ppm in
1/16 ppm steps.
Clear Threshold (ppm) =
OOFx_CLR_THR x ±1/16 ppm
Note that OOF will be indicated if
this is set to 0.
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Register Map
Table 12.40. Register 0x004E–0x04F OOF Detection Windows
Bit Field
Type
Name
0x004E
2:0
R/W
FAST_OOF0_DETWIN_SEL
0x004E
6:4
R/W
FAST_OOF1_DETWIN_SEL
0x004F
2:0
R/W
FAST_OOF2_DETWIN_SEL
0x004F
6:4
R/W
FAST_OOF3_DETWIN_SEL
Description
Values calculated by CBPro
Table 12.41. Register 0x0051-0x0054 Fast OOF Set Thresholds
Type
Name
0x0051
3:0
R/W
FAST_OOF0_SET_THR
0x0052
3:0
R/W
FAST_OOF1_SET_THR
0x0053
3:0
R/W
FAST_OOF2_SET_THR
0x0054
3:0
R/W
FAST_OOF3_SET_THR
Description
Fast OOF Set Threshold. The range
is from ±1,000 ppm to ±16,000 ppm
in 1000 ppm steps.
D
Bit Field
N
ew
Reg Address
es
ig
ns
Reg Address
Fast Set Threshold (ppm) =
(FAST_OOFx_SET_THR + 1) x
±1000 ppm
fo
r
Note that OOF will be indicated if
this is set to 0.
Table 12.42. Register 0x0055-0x0058 Fast OOF Clear Thresholds
Bit Field
0x0055
3:0
0x0056
3:0
0x0057
3:0
0x0058
3:0
Type
Name
m
en
de
d
Reg Address
R/W
FAST_OOF0_CLR_THR
R/W
FAST_OOF1_CLR_THR
R/W
FAST_OOF2_CLR_THR
R/W
FAST_OOF3_CLR_THR
Description
Fast OOF Clear Threshold. The
range is from ±1,000 ppm to
±16,000 ppm in 1000 ppm steps.
Fast Clear Threshold (ppm) =
(FAST_OOFx_CLR_THR + 1) *
±1000ppm
om
Note that OOF will be indicated if
this is set to 0.
Type
0x0059
1:0
R/W
FAST_OOF0_DETWIN_SEL
0x0059
3:2
R/W
FAST_OOF1_DETWIN_SEL
0x0059
5:4
R/W
FAST_OOF2_DETWIN_SEL
0x0059
7:6
R/W
FAST_OOF3_DETWIN_SEL
Table 12.43. Register 0x0059 Fast OOF Detection Window
Bit Field
N
ot
R
ec
Reg Address
silabs.com | Building a more connected world.
Name
Description
Values calculated by CBPro
Rev. 1.3 | 85
Si5380 Revision D Reference Manual
Register Map
Table 12.44. Register 0x005A–0x05D OOF0 Ratio for Reference
Bit Field
Type
Name
0x005A
7:0
R/W
OOF0_RATIO_REF
0x005B
15:8
R/W
OOF0_RATIO_REF
0x005C
23:16
R/W
OOF0_RATIO_REF
0x005D
25:24
R/W
OOF0_RATIO_REF
Description
Values calculated by CBPro
Table 12.45. Register 0x005E–0x061 OOF1 Ratio for Reference
Type
Name
0x005E
7:0
R/W
OOF1_RATIO_REF
0x005F
15:8
R/W
OOF1_RATIO_REF
0x0060
23:16
R/W
OOF1_RATIO_REF
0x0061
25:24
R/W
OOF1_RATIO_REF
Description
D
Bit Field
Values calculated by CBPro
N
ew
Reg Address
es
ig
ns
Reg Address
fo
r
Table 12.46. Register 0x0062–0x065 OOF2 Ratio for Reference
Reg Address
Bit Field
Type
Name
0x0062
7:0
R/W
0x0063
15:8
R/W
0x0064
23:16
R/W
OOF2_RATIO_REF
0x0065
25:24
R/W
OOF2_RATIO_REF
Description
OOF2_RATIO_REF
m
en
de
d
OOF2_RATIO_REF
Values calculated by CBPro
Table 12.47. Register 0x0066–0x069 OOF3 Ratio for Reference
Bit Field
Type
Name
0x0066
7:0
R/W
OOF3_RATIO_REF
0x0067
15:8
R/W
OOF3_RATIO_REF
23:16
R/W
OOF3_RATIO_REF
25:24
R/W
OOF3_RATIO_REF
0x0068
R
ec
0x0069
om
Reg Address
N
ot
Reg Address
0x0092
Bit Field
1
Description
Values calculated by CBPro
Table 12.48. Register 0x0092 Fast LOL Enable
Type
R/W
Name
LOL_FST_EN
Description
Fast LOL Enable. Large input frequency errors will quickly assert
LOL when enabled.
0: Disable Fast LOL
1: Enable Fast LOL (default)
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Si5380 Revision D Reference Manual
Register Map
Table 12.49. Register 0x0093 Fast LOL Detection Window
Bit Field
Type
Name
Description
0x0093
7:4
R/W
LOL_FST_DETWIN_SEL
Values calculated by CBPro
Table 12.50. Register 0x0095 Fast LOL Detection Value
Reg Address
Bit Field
Type
Name
0x0095
3:2
R/W
LOL_FST_VALWIN_SEL
es
ig
ns
Reg Address
Description
Values calculated by CBPro
Bit Field
Type
Name
Description
0x0096
7:4
R/W
LOL_FST_SET_THR_SEL
Values calculated by CBPro
N
ew
Reg Address
D
Table 12.51. Register 0x0096 Fast LOL Set Threshold
Table 12.52. Register 0x0098 Fast LOL Clear Threshold
Bit Field
Type
Name
0x0098
7:4
R/W
LOL_FST_CLR_THR_SEL
Description
Values calculated by CBPro
fo
r
Reg Address
Table 12.53. Register 0x009A LOL Enable
Bit Field
Type
1
R/W
m
en
de
d
Reg Address
0x009A
Name
Description
LOL_SLOW_EN_PLL Enable LOL detection.
0: LOL Disabled
1: LOL Enabled
Table 12.54. Register 0x009B LOL Detection Window
Bit Field
Type
Name
Description
0x009B
LOL_SLW_DETWIN_SEL
om
Reg Address
R/W
Reg Address
Bit Field
Type
Name
0x009D
3:2
R/W
LOL_SLW_VALWIN_SEL
7:4
Values calculated by CBPro
N
ot
R
ec
Table 12.55. Register 0x009D LOL Detection Window
Description
Values calculated by CBPro
Table 12.56. Register 0x009E LOL Set Threshold
Reg Address
Bit Field
Type
0x009E
7:4
R/W
Name
Description
LOL_SLW_SET_THR LOL Set Threshold.
See the list below for settings.
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Rev. 1.3 | 87
Si5380 Revision D Reference Manual
Register Map
Table 12.57. Register 0x00A0 LOL Clear Threshold
Reg Address
Bit Field
Type
0x00A0
7:4
R/W
Name
Description
LOL_SLW_CLR_THR LOL Clear Threshold.
es
ig
ns
See the list below for settings.
N
ew
D
LOL_SET_THR and LOL_CLR_THR Threshold settings:
• 0 = ±0.1 ppm
• 1 = ±0.3 ppm
• 2 = ±1 ppm
• 3 = ±3 ppm
• 4 = ±10 ppm
• 5 = ±30 ppm
• 6 = ±100 ppm
• 7 = ±300 ppm
• 8 = ±1000 ppm
• 9 = ±3000 ppm
• 10 = ±10000 ppm
• 11–15: Reserved
Bit Field
Type
0x00A2
1
R/W
Name
LOL_TIMER_EN
m
en
de
d
Reg Address
fo
r
Table 12.58. Register 0x00A2 LOL Timer Enable
Description
Enable Delay for LOL Clear.
0: Disable Delay for LOL Clear
1: Enable Delay for LOL Clear
Extends the time after a clock returns or stabilizes before LOL de-asserts.
Table 12.59. Register 0x00A8-0x00AC LOL Clear Delay
Bit Field
Type
Name
Description
0x00A9
7:0
R/W
LOL_CLR_DELAY_DIV256
29-bit value
0x00AA
0x00AB
15:8
23:16
28:24
ec
0x00AC
om
Reg Address
N
ot
R
The LOL Clear Delay value is set by ClockBuilder Pro based on each frequency plan.
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Rev. 1.3 | 88
Si5380 Revision D Reference Manual
Register Map
Table 12.60. Register 0x00E2 NVM Active Bank
Reg Address
Bit Field
Type
0x00E2
7:0
R
Name
Description
ACTIVE_NVM_BANK 0x03 when no NVM has been
burned
es
ig
ns
0x0F when 1 NVM bank has been
burned
0x3F when 2 NVM banks have
been burned
D
hen ACTIVE_NVM_BANK = 0x3F,
the last bank has already been
burned. See 2.1.3 NVM Programming for a detailed description of
how to program the NVM.
Reg Address
Bit Field
Type
0x00E3
7:0
R/W
Name
Description
NVM_WRITE
Write 0xC7 to initiate an NVM bank
burn.
fo
r
See 2.1.3 NVM Programming for more information.
N
ew
Table 12.61. Register 0x00E3 NVM Write Control
Reg Address
0x00E4
m
en
de
d
Table 12.62. Register 0x00E4 Read Active NVM Bank
Bit Field
Type
Name
0
S
NVM_READ_BANK
Description
Set to 1 to initiate NVM copy to
registers.
Table 12.63. Register 0x00E5 Fastlock Extend Enable
Bit Field
Type
Name
0x00E5
5
R/W
FASTLOCK_EXTEND_EN
R
ec
om
Reg Address
Description
Extend Fastlock bandwidth period
past LOL Clear
0: Do not extend Fastlock period
1: Extend Fastlock period (default)
Table 12.64. Register 0x009D Fastlock Extend Length
Bit Field
Type
Name
Description
0x00EA
7:0
R/W
FASTLOCK_EXTEND
0x00EB
15:8
R/W
FASTLOCK_EXTEND
0x00EC
23:16
R/W
FASTLOCK_EXTEND
Values calculated by CBPro to minimize transients when switching to
or from the Fastlock bandwidth.. 29bit value.
0x00ED
28:24
R/W
FASTLOCK_EXTEND
N
ot
Reg Address
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Rev. 1.3 | 89
Si5380 Revision D Reference Manual
Register Map
Table 12.65. Register 0x00FE Device Ready
Reg Address
Bit Field
Type
Name
0x00FE
7:0
R
DEVICE_READY
Description
Device Ready indicator.
es
ig
ns
0x0F: Device is Ready
0xF3: Device is Not ready
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
Read-only byte to indicate when the device is ready to accept serial bus writes. The user can poll this byte starting at power-up. When
reads from DEVICE_READY return 0x0F the user can safely read or write to all registers. This is generally only needed after POR, after
a Hard Reset by pin or register, or after initiating and NVM write. The “Device Ready” register is available on every page in the device
at the second to the last serial address, 0xFE. There is a device ready register at 0x00FE, 0x01FE, 0x02FE, … etc. Since this is on
every page, you should not write the page register when reading DEVICE_READY.
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Rev. 1.3 | 90
Si5380 Revision D Reference Manual
Register Map
12.2 Page 1 Registers
Table 12.66. Register 0x0102 Global Output Gating for all Clock Outputs
Bit Field
Type
Name
Description
0x0102
0
R/W
OUTALL_DISABLE_LOW
Enable/Disable All output drivers. If
the OEb pin is held high, then all
outputs will be disabled regardless
of this setting.
es
ig
ns
Reg Address
0: Disable All outputs (default)
1: Enable All outputs
D
Table 12.67. Register 0x0103 OUT0A Output Enable and R0A Divider Configuration
Bit Field
Type
Name
Description
0x0103
0
R/W
OUT0A_PDN
Powerdown output driver.
N
ew
Reg Address
0: Normal Operation (default)
1: Powerdown output driver
0x0103
2
R/W
fo
r
1
OUT0A_OE
Enable/Disable individual output.
0: Disable output (default)
m
en
de
d
0x0103
When powered down, outputs pins
will be high impedance with a light
pull down effect.
R/W
1: Enable output
OUT0A_RDIV_FORCE
Force R0A output divider divideby-2.
0: R0A_REG sets divide value (default)
1: Divide value forced to divide-by-2
om
Setting R0A_REG=0 will not set the divide value to divide-by-2 automatically. OUT0A_RDIV_FORCE must be set to a value of 1 to
force R0A to divide-by-2. Note that the R0A_REG value will be ignored while OUT0A_RDIV_FORCE=1. See R0A_REG registers,
0x0247-0x0249, for more information.
ec
Table 12.68. Register 0x0104 OUT0A Output Format and Configuration
Bit Field
Type
Name
0x0104
2:0
R/W
OUT0A_FORMAT
N
ot
R
Reg Address
Description
Select output format.
0: Reserved
1: Differential Normal
mode
2: Differential Low-Power
mode
3: Reserved
4: LVCMOS single ended
5–7: Reserved
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Si5380 Revision D Reference Manual
Register Map
Reg Address
Bit Field
Type
Name
Description
0x0104
3
R/W
OUT0A_SYNC_EN
Synchronous Enable/
Disable selection.
0: Asynchronous Enable/
Disable (default)
0x0104
5:4
es
ig
ns
1: Synchronous Enable/
Disable (Glitchless)
R/W
OUT0A_DIS_STATE
Determines the logic
state of the output driver
when disabled:
0: Disable logic Low
1: Disable logic High
7:6
R/W
OUT0A_CMOS_DRV
N
ew
0x0104
D
2-3: Reserved
LVCMOS output impedance selection. See Table 4.8 LVCMOS Output
Impedance and Drive
Strength Selections on
page 45for valid selections.
fo
r
Table 12.69. Register 0x0105 Output OUT0A Differential Amplitude and Common Mode
Bit Field
Type
Name
0x0105
3:0
R/W
OUT0A_CM
6:4
R/W
OUT0A_AMPL
m
en
de
d
Reg Address
0x0105
Description
OUT0A Common Mode
Voltage selection. Only
applies when
OUT0A_FORMAT=1 or
2.
OUT0A Differential Amplitude setting. Only applies when OUT0A_FORMAT=1 or 2.
om
ClockBuilder Pro is used to select the correct settings for this register. See Table 4.7 Recommended Settings for Differential LVPECL,
LVDS, HCSL, and CML on page 43 and 13. Appendix—Custom Differential Amplitude Controls for details of the settings.
ec
Table 12.70. Register 0x0106 Output OUT0A Source, VDD Select, and LVCMOS Inversion
Bit Field
Type
Name
0x0106
2:0
R/W
OUT0A_MUX_SEL
R
Reg Address
Description
OUT0A output source divider select.
0: N0 is the source for OUT0A
N
ot
1: N1 is the source for OUT0A
2: N2 is the source for OUT0A
3: N3 is the source for OUT0A
4: N4 is the source for OUT0A
5-7: Reserved
0x0106
3
R/W
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OUT0A_VDD_SEL_EN
Output Driver VDD Select Enable. Set to 1
for normal operation.
Rev. 1.3 | 92
Si5380 Revision D Reference Manual
Register Map
Reg Address
Bit Field
Type
Name
Description
0x0106
5:4
R/W
OUT0A_VDD_SEL
Output Driver VDD Select
0: 1.8 V
1: 2.5 V
0x0106
7:6
R/W
es
ig
ns
2, 3: 3.3 V
OUT0A_INV
OUT0A output LVCMOS inversion. Only
applies when OUT0A_FORMAT= 4. See
Table 4.10 LVCMOS Output Polarity Registers on page 46 for more information.
Each output can be independently configured to use one of the N0-N4 divider outputs as its source. Nx_NUM and Nx_DEN for each Ndivider are set in registers 0x0302-0x0337 for N0 to N4. Five different frequencies can be set in the N-dividers (N0-N4) and each of the
12 outputs can be configured to use any of the five different frequencies.
D
All 12 output drivers are identical in terms of control. The single set of descriptions above for OUT0A also applies to OUT0-OUT9A:
N
ew
Table 12.71. Output Registers Following the Same Definitions as OUT0A
Description
0x0108
OUT0 Powerdown, Output Enable,
and R0 Divide-by-2
0x0109
OUT0 Signal Format and Configuration
0x010A
OUT0 Differential Amplitude and
Common Mode
0x0105
0x010B
OUT0 Source Selection and
LVCMOS Inversion
0x0106
OUT1 Powerdown, Output Enable,
and R1 Divide-by-2
0x0103
OUT1 Signal Format and Configuration
0x0104
OUT1 Differential Amplitude and
Common Mode
0x0105
OUT1 Source Selection and
LVCMOS Inversion
0x0106
OUT2 Powerdown, Output Enable,
and R2 Divide-by-2
0x0103
0x0113
OUT2 Signal Format and Configuration
0x0104
0x0114
OUT2 Differential Amplitude and
Common Mode
0x0105
0x0115
OUT2 Source Selection and
LVCMOS Inversion
0x0106
0x0117
OUT3 Powerdown, Output Enable,
and R3 Divide-by-2
0x0103
0x0118
OUT3 Signal Format and Configuration
0x0104
0x0119
OUT3 Differential Amplitude and
Common Mode
0x0105
0x010E
0x010F
om
0x0110
m
en
de
d
0x010D
N
ot
R
ec
0x0112
(Same as) Address
fo
r
Register Address
silabs.com | Building a more connected world.
0x0103
0x0104
Rev. 1.3 | 93
Si5380 Revision D Reference Manual
Register Map
Description
(Same as) Address
0x011A
OUT3 Source Selection and
LVCMOS Inversion
0x0106
0x011C
OUT4 Powerdown, Output Enable,
and R4 Divide-by-2
0x0103
0x011D
OUT4 Signal Format and Configuration
0x0104
0x011E
OUT4 Differential Amplitude and
Common Mode
0x0105
0x011F
OUT4 Source Selection and
LVCMOS Inversion
0x0106
0x0121
OUT5 Powerdown, Output Enable,
and R5 Divide-by-2
0x0103
0x0122
OUT5 Signal Format and Configuration
0x0123
OUT5 Differential Amplitude and
Common Mode
0x0124
OUT5 Source Selection and
LVCMOS Inversion
0x0126
OUT6 Powerdown, Output Enable,
and R6 Divide-by-2
0x0127
OUT6 Signal Format and Configuration
0x0104
0x0128
OUT6 Differential Amplitude and
Common Mode
0x0105
OUT6 Source Selection and
LVCMOS Inversion
0x0106
OUT7 Powerdown, Output Enable,
and R7 Divide-by-2
0x0103
OUT7 Signal Format and Configuration
0x0104
OUT7 Differential Amplitude and
Common Mode
0x0105
0x012E
OUT7 Source Selection and
LVCMOS Inversion
0x0106
0x0130
OUT8 Powerdown, Output Enable,
and R8 Divide-by-2
0x0103
0x0131
OUT8 Signal Format and Configuration
0x0104
0x0132
OUT8 Differential Amplitude and
Common Mode
0x0105
0x0133
OUT8 Source Selection and
LVCMOS Inversion
0x0106
0x0135
OUT9 Powerdown, Output Enable,
and R9 Divide-by-2
0x0103
0x0136
OUT9 Signal Format and Configuration
0x0104
0x012B
0x012C
N
ot
R
ec
D
0x0104
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0x0105
N
ew
fo
r
om
0x012D
m
en
de
d
0x0129
es
ig
ns
Register Address
0x0106
0x0103
Rev. 1.3 | 94
Si5380 Revision D Reference Manual
Register Map
Description
(Same as) Address
0x0137
OUT9 Differential Amplitude and
Common Mode
0x0105
0x0138
OUT9 Source Selection and
LVCMOS Inversion
0x0106
0x013A
OUT9A Powerdown, Output Enable,
and R9A Divide-by-2
0x0103
0x013B
OUT9A Signal Format and Configuration
0x0104
0x013C
OUT9A Differential Amplitude and
Common Mode
0x0105
0x013D
OUT9A Source Selection and
LVCMOS Inversion
0x0106
D
es
ig
ns
Register Address
N
ew
Table 12.72. Register 0x013F-0x0140 Output Disable Mask for ZDM
Bit Field
Type
Name
Description
0x013F
7:0
R/W
OUTX_ALWAYS_ON
Force output driver to remain active, even
when fault conditions are present. Used
primarily for ZDM.
0x0140
3:0
m
en
de
d
fo
r
Reg Address
R/W
OUTX_ALWAYS_ON
0: Normal output driver enable/disable
(default)
1: Force driver always active (ZDM)
[OUT6, OUT5, ..., OUT0, OUT0A]
[OUT9A, OUT9, OUT8, OUT7]
Table 12.73. Register 0x0141 Output Disable Mask for LOSXAXB
Bit Field
Type
Name
0x0141
1
R/W
OUT_DIS_MSK
ec
om
Reg Address
6
N
ot
Mask alarms from disabling all output drivers.
0: Disable All output drivers on
alarm (default)
1: Ignore alarms for output driver
disable
R/W
OUT_DIS_LOSXAXB_MSK
R
0x0141
Description
Mask LOSXAXB from disabling all
output drivers.
0: Disable All output drivers on
LOSXAXB (default)
1: Ignore LOSXAXB for output driver disable
See 4.7.5 Output Driver Disable Source Summaryfor more information.
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Si5380 Revision D Reference Manual
Register Map
Table 12.74. Register 0x0142 Output Disable Mask for LOL
Reg Address
Bit Field
Type
0x0142
1
R/W
Name
Description
OUT_DIS_MASK_LOL Mask LOL from disabling all output
drivers.
es
ig
ns
0: Disable All output drivers on
LOL (default)
See 4.7.5 Output Driver Disable Source Summaryfor more information.
Table 12.75. Register 0x0145 Output Power Down All
Bit Field
Type
Name
0x0145
0
R/W
OUT_PDN_ALL
Description
Powerdown all output drivers.
N
ew
Reg Address
D
1: Ignore LOL for output driver disable
0: Normal Operation (default)
N
ot
R
ec
om
m
en
de
d
fo
r
1: Powerdown all output drivers
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Si5380 Revision D Reference Manual
Register Map
12.3 Page 2 Registers
Table 12.76. Register 0x0208-0x020D P0 Divider Numerator
Bit Field
Type
Name
0x0208
7:0
R/W
P0_NUM
0x0209
15:8
0x020A
23:16
0x020B
31:24
0x020C
39:32
0x020D
47:40
Description
48-bit Integer Number
D
es
ig
ns
Reg Address
Bit Field
Type
0x020E
7:0
R/W
0x020F
15:8
0x0210
23:16
0x0211
31:24
Name
P0_DEN
Description
32-bit Integer Number
fo
r
Reg Address
N
ew
Table 12.77. Register 0x020E-0x0211 P0 Divider Denominator
The P input divider values are calculated by ClockBuilder Pro for a particular frequency plan and are written into these registers. The
new register values for the P divider will not take effect until the appropriate Px_UPDATE strobe is set as described below.
m
en
de
d
Note: This ratio of Px_NUM/Px_DEN should be an integer for proper operation of the device.
Table 12.78. Registers that Follow the P0_NUM and P0_DEN Above
Register Address
Description
Size
Same as Address
P1 Divider Numerator
48-bit Integer Number
0x0208-0x020D
P1 Divider Denominator
32-bit Integer Number
0x020E-0x0211
P2 Divider Numerator
48-bit Integer Number
0x0208-0x020D
0x0222-0x0225
P2 Divider Denominator
32-bit Integer Number
0x020E-0x0211
0x0226-0x022B
P3 Divider Numerator
48-bit Integer Number
0x0208-0x020D
P3 Divider Denominator
32-bit Integer Number
0x020E-0x0211
0x0212-0x0217
0x0218-0x021B
ec
om
0x021C-0x0221
0x022C-0x022F
R
Table 12.79. Register 0x0230 Px_UPDATE
Bit Field
Type
Name
0x0230
0
S
P0_UPDATE
0x0230
1
S
P1_UPDATE
0x0230
2
S
P2_UPDATE
0x0230
3
S
P3_UPDATE
N
ot
Reg Address
Description
Set these bits for IN3 - IN0 to 1 to
latch in new P-divider values.
The Px_UPDATE bit must be asserted to update the internal P divider numerator and denominator values. These update bits are provided so that all of the P input dividers can be changed at the same time.
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Si5380 Revision D Reference Manual
Register Map
Table 12.80. Register 0x0235–0x023A MXAXB Divider Numerator
Bit Field
Type
Name
Description
0x0235
7:0
R/W
MXAXB_NUM
0x0236
15:8
R/W
MXAXB_NUM
0x0237
23:16
R/W
MXAXB_NUM
0x0238
31:24
R/W
MXAXB_NUM
0x0239
39:32
R/W
MXAXB_NUM
0x023A
47:40
R/W
MXAXB_NUM
es
ig
ns
Reg Address
44-bit Integer Number
D
Changing this register during operation may cause indefinite loss of lock unless the guidelines in 2.1.1 Updating Registers During Device Operation are followed. Either MXAXB_UPDATE or SOFT_RST must be set to cause these changes to take effect.
N
ew
Table 12.81. Register 0x0235–0x023A MXAXB Divider Denominator
Bit Field
Type
Name
0x023B
7:0
R/W
MXAXB_DEN
0x023C
15:8
R/W
MXAXB_DEN
0x023D
23:16
R/W
MXAXB_DEN
0x023E
31:24
R/W
Description
32-bit Integer Number
fo
r
Reg Address
MXAXB_DEN
m
en
de
d
Changing this register during operation may cause indefinite loss of lock unless the guidelines in 2.1.1 Updating Registers During Device Operation are followed. Either MXAXB_UPDATE or SOFT_RST must be set to cause these changes to take effect.
Table 12.82. Register 0x023F MXAXB Update
Reg Address
Bit Field
R/W
Name
MXAXB_UPDATE
Type
Name
0x0247
7:0
R/W
R0A_REG
0x0248
15:8
R
23:16
N
ot
0x0249
Description
Set to 1 to update the MXAXB_NUM
and MXAXB_DEN values. A
SOFT_RST may also be used to update these values.
Table 12.83. Register 0x0247-0x0249 R0 Divider
Bit Field
ec
Reg Address
1
om
0x023F
Type
Description
24-bit integer final R0A divider selection.
R Divisor = (R0A_REG+1) x 2
However, note that setting
R0A_REG = 0 will not set the output to divide-by-2. See notes below.
The final output R dividers are even dividers beginning with divide-by-2. While all other values follow the formula in the bit description
above, divide-by-2 requires an extra bit to be set. For divide-by-2, set OUT0_RDIV_FORCE=1. See the description for register bit
0x0103[2] in this register map.
The R0-R9A dividers follow the same format as the R0A divider description above.
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Register Map
Table 12.84. Registers that Follow the R0A_REG
Description
Size
Same as Address
0x024A-0x024C
R0_REG
24-bit Integer Number
0x0247-0x0249
0x024D-0x024F
R1_REG
24-bit Integer Number
0x0247-0x0249
0x0250-0x0252
R2_REG
24-bit Integer Number
0x0253-0x0255
R3_REG
24-bit Integer Number
0x0256-0x0258
R4_REG
24-bit Integer Number
0x0259-0x025B
R5_REG
24-bit Integer Number
0x025C-0x025E
R6_REG
24-bit Integer Number
0x025F-0x0261
R7_REG
24-bit Integer Number
0x0262-0x0264
R8_REG
24-bit Integer Number
0x0265-0x0267
R9_REG
24-bit Integer Number
0x0247-0x0249
0x0268-0x026A
R9A_REG
24-bit Integer Number
0x0247-0x0249
es
ig
ns
Register Address
0x0247-0x0249
0x0247-0x0249
0x0247-0x0249
0x0247-0x0249
0x0247-0x0249
D
0x0247-0x0249
N
ew
0x0247-0x0249
Table 12.85. Register 0x026B-0x0272 User Design Identifier
Bit Field
Type
0x026B
7:0
R/W
0x026C
15:8
R/W
0x026E
0x026F
0x0270
0x0271
DESIGN_ID0
23:16
R/W
DESIGN_ID2
31:24
R/W
DESIGN_ID3
39:32
R/W
DESIGN_ID4
47:40
R/W
DESIGN_ID5
DESIGN_ID0: 0x55
55:48
R/W
DESIGN_ID6
DESIGN_ID1: 0x4C
63:56
R/W
DESIGN_ID7
DESIGN_ID2: 0x54
DESIGN_ID1
DESIGN_ID3: 0x2E
DESIGN_ID4: 0x31
DESIGN_ID5: 0x41
DESIGN_ID6: 0x00
DESIGN_ID7: 0x00
N
ot
R
ec
om
0x0272
Description
ASCII encoded string defined by
the ClockBuilder Pro user, with
user defined space or null padding
of unused characters. A user will
normally include a configuration ID
+ revision ID. For example, "ULT.
1A" with null character padding
sets:
m
en
de
d
0x026D
Name
fo
r
Reg Address
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Register Map
Table 12.86. Register 0x0278–0x027C OPN Identifier
Bit Field
Type
Name
Description
0x0278
7:0
R/W
OPN_ID0
0x0279
15:8
R/W
OPN_ID1
OPN unique identifier. ASCII encoded. For example, with OPN:
0x027A
23:16
R/W
OPN_ID2
5380C-A12345-GM, 12345 is the
OPN unique identifier, which sets:
0x027B
31:24
R/W
OPN_ID3
OPN_ID0: 0x31
0x027C
39:32
R/W
OPN_ID4
OPN_ID1: 0x32
es
ig
ns
Reg Address
OPN_ID2: 0x33
D
OPN_ID3: 0x34
See 11.3 Part Numbering Summary for more information on part numbers.
N
ew
OPN_ID4: 0x35
Table 12.87. Register 0x0294 Fastlock Extend Scale
Bit Field
Type
Name
0x0294
7:4
R/W
FASTLOCK_EXTEND_SCL
fo
r
Reg Address
Description
Value calculated in CBPro based on parameter selected.
Reg Address
Bit Field
0x0296
1
m
en
de
d
Table 12.88. Register 0x0296 Fastlock Delay on Input Switch
Type
Name
R/W
LOL_SLW_VALWIN_SELX
Description
Value calculated in CBPro based on parameter selected.
Table 12.89. Register 0x0297 Fastlock Delay on Input Switch
Bit Field
0x0297
1
Type
Name
R/W
FASTLOCK_DLY_ONSW_EN
om
Reg Address
Description
Value calculated in CBPro based on parameter selected.
ec
Table 12.90. Register 0x0299 Fastlock Delay on LOL Enable
Bit Field
Type
Name
0x0299
1
R/W
FASTLOCK_DLY_ONLOL_EN
N
ot
R
Reg Address
Description
Value calculated in CBPro based on parameter selected.
Table 12.91. Register 0x029D–0x029F Fastlock Delay on LOL
Reg Address
Bit Field
Type
Name
0x029D
7:0
R/W
FASTLOCK_DLY_ONLOL
0x029E
15:8
R/W
FASTLOCK_DLY_ONLOL
0x029F
19:16
R/W
FASTLOCK_DLY_ONLOL
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Description
Value calculated in CBPro based on parameter selected.
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Register Map
Table 12.92. Register 0x02A9–0x02AB Fastlock Delay on Input Switch
Bit Field
Type
Name
Description
0x02A9
7:0
R/W
FASTLOCK_DLY_ONSW
0x02AA
15:8
R/W
FASTLOCK_DLY_ONSW
0x02AB
19:16
R/W
FASTLOCK_DLY_ONSW
Value calculated in CBPro based on parameter selected.
Table 12.93. Register 0x02B7 LOL Delay from LOS
Bit Field
Type
Name
Description
0x02B7
3:2
R/W
LOL_NOSIG_TIME
Value calculated in CBPro based on parameter selected.
N
ot
R
ec
om
m
en
de
d
fo
r
N
ew
D
Reg Address
es
ig
ns
Reg Address
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Register Map
12.4 Page 3 Registers
Table 12.94. Register 0x0302-0x0307 N0 Numerator
Bit Field
Type
Name
Description
0x0302
7:0
R/W
N0_NUM
0x0303
15:8
N Output Divider Numerator. 44-bit
Integer.
0x0304
23:16
0x0305
31:24
0x0306
39:32
0x0307
43:40
Bit Field
Type
0x0308
7:0
R/W
0x0309
15:8
0x030A
23:16
0x030B
31:24
Name
Description
N0_DEN
N Output Divider Denominator. 32bit Integer
fo
r
Reg Address
N
ew
Table 12.95. Register 0x0308-0x030B N0 Denominator
D
es
ig
ns
Reg Address
m
en
de
d
The N output divider values are calculated by ClockBuilder Pro for a particular frequency plan and are written into these registers. Note
that this ratio of Nx_NUM / Nx_DEN should be an integer for proper operation of the device. The N output dividers feed into the final
output R dividers through the output crosspoint.
Table 12.96. Register 0x030C N0 Update
Reg Address
0x030C
Bit Field
Type
Name
Description
0
S
N0_UPDATE
Set this bit to latch the N output divider registers into operation.
Setting this self-clearing bit to 1 latches the new N output divider register values into operation. A Soft Reset will have the same effect.
om
Table 12.97. Registers that Follow the N0_NUM and N0_DEN Definitions
Description
Size
Same as Address
0x030D-0x0312
N1_NUM
44-bit Integer
0x0302-0x0307
0x0313-0x0316
N1_DEN
32-bit Integer
0x0308-0x030B
0x0317
N1_UPDATE
one bit
0x030C
0x0318-0x031D
N2_NUM
44-bit Integer
0x0302-0x0307
0x031E-0x0321
N2_DEN
32-bit Integer
0x0308-0x030B
0x0322
N2_UPDATE
one bit
0x030C
0x0323-0x0328
N3_NUM
44-bit Integer
0x0302-0x0307
0x0329-0x032C
N3_DEN
32-bit Integer
0x0308-0x030B
0x032D
N3_UPDATE
one bit
0x030C
0x032E-0x0333
N4_NUM
44-bit Integer
0x0302-0x0307
N
ot
R
ec
Register Address
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Register Map
Register Address
Description
Size
Same as Address
0x0334-0x0337
N4_DEN
32-bit Integer
0x0308-0x030B
0x0338
N4_UPDATE
one bit
0x030C
Reg Address
Bit Field
Type
Name
0x0338
1
R/W
N_UPDATE_ALL
es
ig
ns
Table 12.98. Register 0x0338 Global N Divider Update
Description
Writing a 1 to this bit will update
the N output divider values. When
this bit is written to 1, all other bits
in this register must be written as
zeros.
Reg Address
Bit Field
Type
0x0359-0x035A
7:0
R/W
N
ew
Table 12.99. Register 0x0359-0x35A N0 Delay Control
D
This bit is provided so that all of the divider bits can be changed at the same time. First, write all of the new values to Nx_NUM and
Nx_DEN, then set the update bit to 1.
Name
N0_DELAY[15:8]
Description
8-bit, 2s-complement delay for N0
fo
r
N0_DELAY[7:0] is an 8-bit 2’s-complement number that sets the output delay of the N0 divider. ClockBuilder Pro calculates the correct
value for this register. A Soft Reset of the device, SOFT_RST (0x001C[0] = 1), required to latch in the new delay value(s). Note that the
least significant byte (0x0359) is ignored.
tDLY = Nx_DELAY / 256 x 67.8 ps
m
en
de
d
fVCO=14.7456 GHz, 1/fVCO=67.8 ps
Table 12.100. Register 0x035B-0x035C N1 Delay Control
Reg Address
Bit Field
Type
Name
0x035B-0x035C
7:0
R/W
N1_DELAY[15:8]
Description
8-bit, 2s-complement delay for N1
N1_DELAY behaves in the same manner as N0_DELAY.
Reg Address
om
Table 12.101. Register 0x035D-0x035E N2 Delay Control
Type
Name
7:0
R/W
N2_DELAY[15:8]
ec
0x035D-0x035E
Bit Field
Description
8-bit, 2s-complement delay for N2
R
N2_DELAY behaves in the same manner as N0_DELAY above.
Table 12.102. Register 0x035F-0x0360 N3 Delay Control
Bit Field
Type
Name
0x035F-0x0360
7:0
R/W
N3_DELAY[15:8]
N
ot
Reg Address
Description
8-bit, 2s-complement delay for N3
N3_DELAY behaves in the same manner as N0_DELAY above.
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Register Map
Table 12.103. Register 0x0361-0x0362 N4 Delay Control
Reg Address
Bit Field
Type
Name
Description
0x0361-0x0362
7:0
R/W
N4_DELAY[15:8]
8-bit, 2s-complement delay for N4
es
ig
ns
N4_DELAY behaves in the same manner as N0_DELAY above.
12.5 Page 4 Registers
Table 12.104. Register 0x0487 Zero Delay Mode Setup
Bit Field
Type
Name
0x0487
0
R/W
ZDM_EN
Description
Enable ZDM Operation.
D
Reg Address
N
ew
0: Disable Zero Delay Mode (default)
1: Enable Zero Delay Mode
0x0487
2:1
R/W
ZDM_IN_SEL
ZDM Manual Input Source Select when
both ZDM_EN = 1 and
IN_SEL_REGCTRL (0x052A[0]) = 1.
m
en
de
d
fo
r
0: IN0 (default)
0x0487
4
R/W
1: IN1
2: IN2
3: Reserved (IN3 already used by ZDM)
ZDM_AUTOSW_EN Enable ZDM automatic input switching.
0: Disable automatic switching for ZDM
(default)
1: Enable automatic input switching in
ZDM governed by automatic input switching engine
N
ot
R
ec
om
To enable ZDM, set ZDM_EN = 1. In ZDM, the input clock source must be selected manually by using either the ZDM_IN_SEL register
bits or the IN_SEL1 and IN_SEL0 device input pins. IN_SEL_REGCTRL determiens the choice of register or pin control to select the
desired input clock. When register control is selected in ZDM, the ZDM_IN_SEL control bits determine the input to be used and the
non-ZDM IN_SEL bits will be ignored. Note that in ZDM, the DSPLL does not use either Hitless switching or Automatic input source
switching.
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Register Map
12.6 Page 5 Registers
Table 12.105. Register 0x0507 DSPLL Active Input Indicator
Bit Field
Type
Name
Description
0x0507
7:6
R
IN_ACTV
Currently selected
DSPLL input clock.
es
ig
ns
Reg Address
0: IN0
1: IN1
2: IN2
3: IN3/FB_IN
N
ew
D
This register displays the currently selected input for the DSPLL. In manual select mode, this reflects either the voltages on the
IN_SEL1 and INSEL0 pins or the register value. In automatic switching mode, it reflects the input currently chosen by the automatic
algorithm. If there are no valid input clocks in the automatic mode, this value will retain its previous value until a valid input clock is
presented. Note that this value is not meaningful in Holdover or Freerun modes.
Table 12.106. Register 0x0508-0x050D DSPLL Loop Bandwidth
Reg Address
Bit Field
Type
Name
0x0508
7:0
R/W
0x0509
7:0
R/W
0x050A
7:0
R/W
0x050B
7:0
R/W
BW3_PLL
7:0
R/W
BW4_PLL
7:0
R/W
BW5_PLL
fo
r
BW0_PLL
BW1_PLL
BW2_PLL
m
en
de
d
0x050C
0x050D
Description
DSPLL loop bandwidth parameters.
This group of registers determines the DSPLL loop bandwidth. In ClockBuilder Pro it is selectable from 0.1 Hz to 100 Hz in factors of
roughly 2x each. Clock Builder Pro will then determine the values for each of these registers. The BW_UPDATE bit (0x0514[0]) must be
set to cause all of the BWx_PLL, FASTLOCK_BWx_PLL, and HOLDEXIT_BWx parameters to take effect.
Reg Address
om
Table 12.107. Register 0x050E-0x0513 DSPLL Fastlock Loop Bandwidth
Bit Field
Type
Name
7:0
R/W
FASTLOCK_BW0_PLL
7:0
R/W
FASTLOCK_BW1_PLL
0x0510
7:0
R/W
FASTLOCK_BW2_PLL
0x0511
7:0
R/W
FASTLOCK_BW3_PLL
0x0512
7:0
R/W
FASTLOCK_BW4_PLL
7:0
R/W
FASTLOCK_BW5_PLL
0x050E
N
ot
R
ec
0x050F
0x0513
Description
DSPLL Fastlock Bandwidth parameters.
This group of registers determines the DSPLL Fastlock bandwidth. In Clock Builder Pro, it is selectable from 100 Hz to 4 kHz in factors
of roughly 2x each. Clock Builder Pro will then determine the values for each of these registers. The BW_UPDATE bit (0x0514[0]) must
be set to cause all of the BWx_PLL, FASTLOCK_BWx_PLL, and HOLDEXIT_BWx parameters to take effect.
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Register Map
Table 12.108. Register 0x0514 DSPLL Bandwidth Update
Reg Address
Bit Field
Type
Name
Description
0x0514
0
S
BW_UPDATE
Set to 1 to latch updated bandwidth
registers into operation.
es
ig
ns
Setting this self-clearing bit high latches all of the new DSPLL bandwidth register values into operation. Asserting this strobe will update
all of the BWx_PLL, FASTLOCK_BWx_PLL, and HOLDEXIT_BWx bandwidths at the same time. A device Soft Reset (0x001C[0]) will
have the same effect, but individual DSPLL soft resets will not update these values.
Table 12.109. Register 0x0515-0x051B M Feedback Divider Numerator, 56-bits
7:0
0x0516
15:8
0x0517
23:16
0x0518
31:24
0x0519
39:32
0x051A
47:40
0x051B
55:48
Name
Description
D
0x0515
Type
N
ew
Bit Field
R/W
M_NUM
M feedback divider Numerator
56-bit Integer
fo
r
Reg Address
m
en
de
d
Note: Note that DSPLL B includes a divide-by-5 block in the PLL feedback path before the M divider. Register values for the DSPLL B
M divider must account for this additional divider. This divider is not present in DSPLLs A, C, or D.
Table 12.110. Register 0x051C-0x051F M Feedback Divider Denominator, 32-bits
Reg Address
Bit Field
0x051C
Name
R/W
M_DEN
Description
7:0
0x051D
15:8
23:16
M feedback divider Denominator
32-bit Integer
31:24
om
0x051E
0x051F
Type
R
ec
Note: Note that DSPLL B includes a divide-by-5 block in the PLL feedback path before the M divider. Register values for the DSPLL B
M divider must account for this additional divider. This divider is not present in DSPLLs A, C, or D.
Table 12.111. Register 0x0520 M Divider Update
Bit Field
Type
Name
Description
0x0520
0
S
M_UPDATE
Set this bit to latch the M feedback
divider registers into operation.
N
ot
Reg Address
Setting this self-clearing bit high latches the new M feedback divider register values into operation. A Soft Reset will have the same
effect.
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Register Map
Table 12.112. Register 0x052A Manual Input Clock Select
Reg Address
Bit Field
Type
Name
Description
0x052A
0
R/W
IN_SEL_REGCTRL
Manual Input Select control source.
es
ig
ns
0: Pin controlled input clock selection (default)
1: IN_SEL register input clock selection
(ZDM_IN_SEL in ZDM)
0x052A
3:1
R/W
IN_SEL
Manual Input Select selection register. (Non-ZDM)
D
0: IN0 (default), 1: IN1, 2: IN2, 3:
IN3/FB_IN
N
ew
4-7: Reserved
Note that in ZDM, the ZDM_IN_SEL (0x0487[2:1]) input source select control bits are used and IN_SEL is ignored. In both ZDM and
non-ZDM operation, IN_SEL_REGCTRL determines whether register-based or pin-based manual source selection is used.
Table 12.113. Register 0x052B Fastlock Control
Type
0x052B
0
R/W
0x052B
1
Name
Description
fo
r
Bit Field
FASTLOCK_AUTO_EN
Auto Fastlock Enable/Disable.
0: Disable Auto Fastlock
m
en
de
d
Reg Address
R/W
1: Enable Auto Fastlock (default)
FASTLOCK_MAN
Manually Force Fastlock.
0: Normal Operation (default)
1: Force Fastlock
om
When Fastlock is enabled by either manual or automatic means, the higher Fastlock bandwidth will be used to provide faster settling of
the DSPLL. With FASTLOCK_MAN=0 and FASTLOCK_AUTO_EN=1, the DSPLL will automatically revert to the loop bandwidth when
the loop has locked and LOL deasserts. See 1.4.1 Fastlock for more information on Fastlock behavior.
Table 12.114. Register 0x052C Holdover Exit Control
Bit Field
Type
Name
0x052C
0
R/W
HOLD_EN
N
ot
0x052C
Description
Holdover enable
0: Holdover Disabled
R
ec
Reg Address
1: Holdover Enabled (default)
3
R/W
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HOLD_RAMP_BYP
Must be set to 1 for Normal Operation.
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Register Map
Reg Address
Bit Field
Type
Name
Description
0x052C
4
R/W
HOLDEXIT_BW_SEL1
Holdover Exit Bandwidth select. Selects
the exit bandwidth from Holdover when
ramped exit is disabled
(HOLD_RAMP_BYP = 1).
es
ig
ns
0: Exit Holdover using Holdover Exit or
Fastlock bandwidths (default). See HOLDEXIT_BW_SEL0 (0x059B[6]) for additional information.
1: Exit Holdover using the Normal loop
bandwidth
7:5
R/W
RAMP_STEP_INTERVAL
Time Interval of the frequency ramp steps
when ramping between inputs or when
exiting holdover. Calculated by CBPro
based on selection.
D
0x052C
Bit Field
Type
0x052E
4:0
R/W
Name
Description
HOLD_HIST_LEN
Window Length time for historical
average frequency used in Holdover mode. Window Length in seconds:
fo
r
Reg Address
N
ew
Table 12.115. Register 0x052E Holdover History Average Length
Window Length = (2HOLD_HIST_LEN
- 1) x 8 / 3 x 10-7
m
en
de
d
The holdover logic averages the input frequency over a period of time whose duration is determined by the history average length. The
average frequency is then used as the holdover frequency. See 2.5 Holdover Mode to calculate the window length from the register
value.
Table 12.116. Register 0x052F Holdover History Delay
Reg Address
Type
Name
Description
4:0
R/W
HOLD_HIST_DELAY
Delay Time to ignore data for historical average frequency in Holdover mode. Delay Time in seconds
(s):
om
0x052F
Bit Field
ec
Delay Time = 2HOLD_HIST_DELAY x
2 / 3 x 10-7
N
ot
R
The most recent input frequency perturbations can be ignored during entry into holdover. The holdover logic pushes back into the past.
The amount the average window is delayed is the holdover history delay. See 2.5 Holdover Mode to calculate the ignore delay time
from the register value.
Table 12.117. Register 0x0532 Holdover Cycle Count
Reg Address
Bit Field
Type
Name
0x0532
7:0
R/W
HOLD_15M_CYC_COUNT
0x0533
15:8
R/W
HOLD_15M_CYC_COUNT
0x0534
23:16
R/W
HOLD_15M_CYC_COUNT
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Description
Value calculated in CBPro.
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Register Map
Table 12.118. Register 0x0535 Force Holdover
Bit Field
Type
Name
Description
0x0535
0
R/W
FORCE_HOLD
Force the device into Holdover
mode. Used to hold the device output clocks while retraining an upstream input clock.
es
ig
ns
Reg Address
0: Normal Operation
1: Force Holdover/Freerun Mode:
HOLD_HIST_VALID = 0 =>Freerun
Mode
D
HOLD_HIST_VALID = 1 =>Holdover Mode
Bit Field
Type
0x0536
1:0
R/W
Name
m
en
de
d
0x0536
2
R/W
Description
CLK_SWITCH_MODE Selects manual or automatic
switching modes. Automatic mode
can be Revertive or Non-revertive.
fo
r
Reg Address
N
ew
Table 12.119. Register 0x0536 Input Clock Switching Control
HSW_EN
00: Manual (default), 01: Automatic
Non-revertive,
02: Automatic Revertive, 03: Reserved
Enable Hitless Switching.
0: Disable Hitless switching
1: Enable Hitless switching (phase
buildout enabled) (default)
Table 12.120. Register 0x0537 Input Fault Masks
Type
Name
3:0
R/W
IN_LOS_MSK
ec
0x0537
Bit Field
om
Reg Address
Enables the use of IN3 - IN0 LOS
status in determining a valid clock
for automatic input selection.
0: Use LOS in automatic clock
switching logic (default)
R
N
ot
0x0537
Description
1: Mask (ignore) LOS from automatic clock switching logic
7:4
R/W
IN_OOF_MSK
Determines the OOF status for IN3
- IN0 and is used in determining a
valid clock for the automatic input
selection.
0: Use OOF in the automatic clock
switching logic (default)
1: Mask (ignore) OOF from automatic clock switching logic
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Register Map
This register is for the input clock fault masks. For each of the four clock inputs, the OOF and/or the LOS fault can be used for the clock
selection logic or they can be masked from it.
Note: The clock selection logic can affect entry into Holdover.
Table 12.121. Register 0x0538-0x0539 Clock Input Priorities
Bit Field
Type
Name
0x0538
2:0
R/W
IN0_PRIORITY
0x0538
6:4
R/W
IN1_PRIORITY
0x0539
2:0
R/W
IN2_PRIORITY
0x0539
6:4
R/W
IN3_PRIORITY
Description
es
ig
ns
Reg Address
IN0 - IN3 priority assignment for
the automatic switching state machine. Priority assignments in descending importance are:
1, 2, 3, 4, or 0 for never selected
D
5-7: Reserved
N
ew
These registers are used to assign priority to each input clock for automatic clock input switching. The available clock with the highest
priority will be selected. Priority 1 is first and most likely to be selected, followed by priorities 2–4. Priority 0 prevents the clock input from
being automatically selected, though it may still be manually selected. When two valid input clocks are assigned the same priority, the
lowest numbered input will be selected. In other words, IN0 has priority over IN1-IN3, IN1 has priority over IN2-IN3, etc, when the priorities are the same.
Table 12.122. Register 0x053A Hitless Switching Mode
Type
0x053A
1:0
R/W
0x053A
3:2
Name
fo
r
Bit Field
HSW_MODE
m
en
de
d
Reg Address
R/W
HSW_PHMEAS_CTRL
Description
2: Default setting, do not modify
0, 1, 3: Reserved
2: Default setting, do not modify
0, 2, 3: Reserved
Table 12.123. Register 0x053B–0x053C Hitless Switching Phase Threshold
Bit Field
Type
Name
0x053B
7:0
R/W
HSW_PHMEAS_THR
0x053C
9:8
R/W
HSW_PHMEAS_THR
om
Reg Address
Description
Value calculated in CBPro.
ec
Table 12.124. Register 0x053D Hitless Switching Length
Bit Field
Type
Name
0x053D
4:0
R/W
HSW_COARSE_PM_LEN
N
ot
R
Reg Address
Description
Value calculated in CBPro.
Table 12.125. Register 0x053E Hitless Switching Length
Reg Address
Bit Field
Type
Name
0x053E
4:0
R/W
HSW_COARSE_PM_DLY
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Description
Value calculated in CBPro.
Rev. 1.3 | 110
Si5380 Revision D Reference Manual
Register Map
Table 12.126. Register 0x053F DSPLL Hold Valid and Fastlock Status
Reg Address
Bit Field
Type
Name
Description
0x053F
1
R
HOLD_HIST_VALID
Holdover Valid historical frequency
data indicator.
es
ig
ns
0: Invalid Holdover History - Freerun on input fail
1: Valid Holdover History - Holdover on input fail
0x053F
2
R
FASTLOCK_STATUS Fastlock engaged indicator.
0: DSPLL Loop bandwidth is active
D
1: Fastlock DSPLL bandwidth currently being used
N
ew
Table 12.127. Register 0x0588 Hitless Switching Length
Reg Address
Bit Field
Type
Name
0x0588
3:0
R/W
HSW_FINE_PM_LEN
Description
Value calculated in CBPro.
fo
r
Table 12.128. Register 0x0589–0x058A PFD Enable Delay
Bit Field
Type
Name
0x0589
7:0
R/W
PFD_EN_DLY
0x058A
12:8
R/W
PFD_EN_DLY
m
en
de
d
Reg Address
Description
Value calculated in CBPro.
Table 12.129. Register 0x059B Holdover Exit
6
ec
0x059B
Bit Field
om
Reg Address
7
R/W
Name
HOLDEXIT_BW_SEL0
Description
Holdover Exit Bandwidth select. Only
valid when both HOLDEXIT_BW_SEL0 = 0 and
HOLD_RAMP_BYP = 1.
0: Use Fastlock Bandwidth on Holdover exit
1: Use Holdover Exit Bandwidth on
Holdover Exit (default)
R/W
HOLDEXIT_STD_BO
1: Default setting, do not modify
0: Reserved
N
ot
R
0x059B
Type
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Si5380 Revision D Reference Manual
Register Map
Table 12.130. Register 0x059D-0x05A2 DSPLL Holdover Exit Bandwidth
Bit Field
Type
Name
Description
0x059D
7:0
R/W
HOLDEXIT_BW0
0x059E
7:0
R/W
HOLDEXIT_BW1
0x059F
7:0
R/W
HOLDEXIT_BW2
0x05A0
7:0
R/W
HOLDEXIT_BW3
0x05A1
7:0
R/W
HOLDEXIT_BW4
0x05A2
7:0
R/W
HOLDEXIT_BW5
DSPLL Holdover Exit bandwidth
parameters calculated by CBPro
when ramp switching is disabled.
es
ig
ns
Reg Address
D
These registers determine the DSPLL bandwidth to be used when exiting Holdover mode if not using ramped exit. In ClockBuilder Pro
this defaults to being equal to the Loop bandwidth, and can be selected by the user. This bandwidth must be equal to, or greater than,
the Loop bandwidth. Clock Builder Pro will determine the values for each of these registers. The BW_UPDATE_PLL bit (register bit
0x0514[0]) must be set to 1 to cause the all of the BWx_PLL, FASTLOCK_BWx_PLL, and HOLDEXIT_BWx parameters to take effect.
N
ew
When the input fails or is switched and the DSPLL switches to Holdover or Freerun mode, HOLD_HIST_VALID accumulation will stop.
When a valid input clock is presented to the DSPLL, the holdover frequency history measurements will be cleared and will begin to
accumulate once again.
Table 12.131. Register 0x05A6 Hitless Switching Control
Type
0x05A6
2:0
R/W
0x05A6
3
Name
fo
r
Bit Field
RAMP_STEP_SIZE
m
en
de
d
Reg Address
RAMP_SWITCH_EN
Size of the frequency ramp steps when
ramping between inputs or when exiting
holdover. Calculated by CBPro based on
selection.
Ramp Switching Enable
0: Disable Ramp Switching
1: Enable Ramp Switching (default)
N
ot
R
ec
om
R/W
Description
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Register Map
12.7 Page 9 Registers
Table 12.132. Register 0x090E XAXB Configuration
Bit Field
Type
Name
Description
0x090E
0
R/W
XAXB_EXTCLK_EN
This bit selects between the Crystal or External reference clock on
the XAXB pins.
es
ig
ns
Reg Address
0: Crystal on XAXB, enable internal
XO (default)
1: External XAXB signal, internal
XO disabled
Bit Field
Type
0x0943
0
R/W
Name
N
ew
Reg Address
D
Table 12.133. Register 0x0943 Control I/O Voltage Select
IO_VDD_SEL
Description
Select digital I/O operating voltage.
0: 1.8 V digital I/O connections
1: 3.3 V digital I/O connections
fo
r
The IO_VDD_SEL configuration bit selects between 1.8V and 3.3V digital I/O. All digital I/O pins, including the serial interface pins, are
3.3V tolerant. Setting this to the default 1.8V is the safe default choice that allows writes to the device regardless of the serial interface
used or the host supply voltage. When the I2C or SPI host is operating at 3.3V and the Si5380 at VDD=1.8V, the host must write
IO_VDD_SEL=1. This will ensure that both the host and the serial interface are operating with the optimum signal thresholds.
m
en
de
d
Table 12.134. Register 0x0949 Clock Input Control and Configuration
Bit Field
Type
Name
0x0949
3:0
R/W
IN_EN
7:4
R/W
Description
Enable (or powerdown) the IN3 IN0 input buffers.
0: Powerdown input buffer
1: Enable and Power-up input buffer
IN_PULSED_CMOS_EN
Select Pulsed CMOS input buffer
for IN3-IN0. See 3.2 Types of Inputs
for more information.
0: Standard Input Format
ec
0x0949
om
Reg Address
R
1: Pulsed CMOS Input Format
N
ot
When a clock input is disabled, it is powered down as well.
• IN0: IN_EN 0x0949[0], IN_PULSED_CMOS_EN 0x0949[4]
• IN1: IN_EN 0x0949[1], IN_PULSED_CMOS_EN 0x0949[5]
• IN2: IN_EN 0x0949[2], IN_PULSED_CMOS_EN 0x0949[6]
• IN3/FB_IN: IN_EN 0x0949[3], IN_PULSED_CMOS_EN 0x0949[7]
Table 12.135. Register 0x094A Input Clock Enable to DSPLL
Reg Address
Bit Field
Type
Name
0x094A
3:0
R/W
INX_TO_PFD_EN
silabs.com | Building a more connected world.
Description
Value calculated in CBPro.
Rev. 1.3 | 113
Si5380 Revision D Reference Manual
Register Map
Table 12.136. Register 0x094E–0x094F Input Clock Buffer Hysteresis
Bit Field
Type
Name
Description
0x094E
7:0
R/W
REFCLK_HYS_SEL
0x094F
3:0
R/W
REFCLK_HYS_SEL
Value calculated in CBPro.
es
ig
ns
Reg Address
12.8 Page A Registers
Table 12.137. Register 0x094A Enable N-divider 0.5x
Bit Field
Type
Name
0x0A02
4:0
R/W
N_ADD_0P5
Description
Value calculated in CBPro.
D
Reg Address
N
ew
Table 12.138. Register 0x0A03 Output N Divider to Output Driver
Bit Field
Type
Name
0x0A03
4:0
R/W
N_CLK_TO_OUTX_EN
fo
r
Reg Address
Description
Enable the output N dividers. Must
be set to 1 to enable the dividers.
See related registers 0x0A05 and
0x0B4A[4:0].
Clock Builder Pro handles these bits when changing settings for the device.
m
en
de
d
Table 12.139. Register 0x0A04 Output N Divider Integer Divide Mode
Reg Address
0x0A04
Bit Field
Type
Name
Description
4:0
R/W
N_PIBYP
Must be set to 0x1F for Normal Operation. Note that a device Soft Reset (0x001C[0]0 = 1) must be issued after changing the settings in
this register.
om
Clock Builder Pro handles these bits when changing settings for the device.
Table 12.140. Register 0x0A05 Output N Divider Power Down
ec
Reg Address
Type
Name
4:0
R/W
N_PDNB
N
ot
R
0x0A05
Bit Field
Description
Powers down the output N4 - N0
dividers.
0: Powerdown unused N dividers
1: Power-up active N dividers
See related registers 0x0A03 and
0x0B4A[4:0].
Clock Builder Pro handles these bits when changing settings for the device.
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Register Map
12.9 Page B Registers
Table 12.141. Register 0x0B24 Reserved Control
Bit Field
Type
Name
Description
0x0B24
7:0
R/W
RESERVED
Reserved
es
ig
ns
Reg Address
This register is used when making certain changes to the device. See 2.1.1 Updating Registers During Device Operation for more information.
Table 12.142. Register 0x0B25 Reserved Control
Bit Field
Type
Name
Description
0x0B25
7:0
R/W
RESERVED
Reserved
D
Reg Address
N
ew
This register is used when making certain changes to the device. See 2.1.1 Updating Registers During Device Operation for more information.
Table 12.143. Register 0x0B46 Loss of Signal Clock Disables
Bit Field
Type
0x0B46
3:0
R/W
Name
Description
LOS_CLK_DIS
Disables LOS clock for
IN3 - IN0. Must be set to
0 to enable the LOS
function of the respective
inputs.
m
en
de
d
fo
r
Reg Address
Clock Builder Pro handles these bits when changing settings for all portions of the device.
Table 12.144. Register 0x0B47 Disable OOF Internal Clocks
Reg Address
Type
Name
4:0
R/W
OOF_CLK_DIS
om
0x0B47
Bit Field
Description
Set to 0 for normal operation. Bits
3:0 are for IN3,2,1,0, Bit 4 is for
OOF for the XAXB input.
Table 12.145. Register 0x0B48 Disable OOF Internal Divider Clocks
ec
Reg Address
Type
Name
4:0
R/W
OOF_DIV_CLK_DIS
N
ot
R
0x0B48
Bit Field
Description
Set to 0 for normal operation. Bits
3:0 are for IN3,2,1,0, Bit 4 is for
OOF for the XAXB input.
Table 12.146. Register 0x0B49 Reserved Control_2
Reg Address
Bit Field
Type
Name
Description
0x0B49
1:0
R/W
CAL_DIS
Must be 0 for normal operation.
0x0B49
3:2
R/W
CAL_FORCE
Must be 0 for normal operation.
Clock Builder Pro handles these bits when changing settings for the device.
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Register Map
Table 12.147. Register 0x0B4A Divider Clock Disables
Bit Field
Type
Name
Description
0x0B4A
4:0
R/W
N_CLK_DIS
Disable digital clocks to N dividers.
Must be set to 0 to use each N divider. See also related registers
0x0A03 and 0x0A05.
0x0B4A
5
R/W
M_CLK_DIS
Disable M divider. Must be set to 0
to enable the M divider.
0x0B4A
6
R/W
M_DIV_CAL_DIS
Disable M divider calibration. Must
be set to 0 to allow calibration.
Table 12.148. Register 0x0B57 VCO Calcode
Bit Field
Type
Name
0x0B57
7:0
R/W
VCO_RESET_CALCODE
0x0B58
3:0
R/W
VCO_RESET_CALCODE
N
ew
Reg Address
D
Clock Builder Pro handles these bits when changing settings for the device.
es
ig
ns
Reg Address
Description
N
ot
R
ec
om
m
en
de
d
fo
r
Value calculated in CBPro.
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Rev. 1.3 | 116
Si5380 Revision D Reference Manual
Appendix—Custom Differential Amplitude Controls
13. Appendix—Custom Differential Amplitude Controls
In some customer applications, it may be desirable to have larger or smaller differential amplitudes than those produced by the standard LVPECL and LVDS settings generated by ClockBuilder Pro. For example, "CML" format is sometimes desired for an application,
but CML is not a defined standard, and, hence, the input amplitude of CML signals may differ between receivers. In these cases, the
following information describes how to implement nonstandard differential amplitudes.
Table 13.1. Differential Output Amplitude Typical Values
Low-Power Mode
Normal Mode
OUTx_FORMAT = 1
OUTx_FORMAT = 2
(mVpp-SE)
(mVpp-SE)
D
OUTx_AMPL
es
ig
ns
The differential output driver has two basic modes of operation as well as variable output amplitude capability. The Normal mode has
an internal impedance of 100 Ω differential, while the Low Power mode has an internal impedance of >500 Ω differential. In both cases,
when properly terminated with 100 Ω differential externally, the typical amplitudes listed in the table below result.
130
200
1
230
2
350
3
450
4
575
5
700
1200
810
13501
920
16001
fo
r
N
ew
0
6
620
820
1010
m
en
de
d
7
400
Note:
1. In Low-Power mode with VDDO=1.8 V, OUTx_AMPL may not be set to 6 or 7.
2. These amplitudes are based upon 100 Ω differential termination.
For applications using a custom differential output amplitude, the common mode voltage should be selected as shown in the table below. These selections, along with the settings given in Table 4.7 Recommended Settings for Differential LVPECL, LVDS, HCSL, and
CML on page 43, have been verified to produce good signal integrity. Some extreme combinations of amplitude and common mode
may have impaired signal integrity.
om
Also, in cases where the receiver is dc-based, either internally or through an external network, the outputs of the device must be accoupled. Output driver performance is not guaranteed when dc-coupled to a biased-input receiver.
Differential Format
OUTx_FORMAT
Common Mode Voltage
(Volts)
OUTx_CM
3.3
Normal
0x1
2.0
0xB
3.3
Low-Power
0x2
1.6
0x7
2.5
Normal
0x1
1.3
0xC
2.5
Low-Power
0x2
1.1
0xA
1.8
Normal
0x1
0.8
0xD
1.8
Low-Power
0x2
0.8
0xD
N
ot
VDDO (Volts)
R
ec
Table 13.2. Differential Output Common Mode Voltage Selections
See also Table 4.7 Recommended Settings for Differential LVPECL, LVDS, HCSL, and CML on page 43 for additional information on
the OUTx_FORMAT_OUTx_AMPL, and OUTx_CM controls.
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Rev. 1.3 | 117
Si5380 Revision D Reference Manual
Revision History
14. Revision History
Revision 1.3
May 2019
es
ig
ns
• Updated Section 2.1.1 Updating Registers During Device Operation.
• Updated Section 2.1.3 NVM Programming.
Revision 1.0
July 28, 2016
N
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N
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D
• Initial release.
silabs.com | Building a more connected world.
Rev. 1.3 | 118
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One-click access to Timing tools,
documentation, software, source
code libraries & more. Available for
Windows and iOS (CBGo only).
www.silabs.com/CBPro
om
Timing Portfolio
www.silabs.com/timing
m
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ClockBuilder Pro
SW/HW
www.silabs.com/CBPro
Quality
www.silabs.com/quality
Support and Community
community.silabs.com
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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without
further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Without prior
notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or the performance
of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant any license to
design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA premarket approval is required
or Life Support Systems without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails,
can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. Silicon Labs
disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of a Silicon Labs product in such unauthorized applications.
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