Silicon Labs Si53154-EVB User's Guide

Silicon Labs Si53154-EVB  User's Guide

S i 5 3 1 5 4 - E V B S i 5 3 1 5 4 E V A L U A T I O N B O A R D U S E R ’ S G U I D E

Description EVB Features

The Si53154 is a four port PCIe clock buffer compliant to the PCIe Gen1, Gen2 and Gen3 standards. The Si53154 is a 24-pin QFN device that operates on a 3.3 V power supply and can be controlled using SMBus signals along with hardware control input pins. The device is spread aware and accepts a frequency spread differential clock frequency range from 100 to 210 MHz.

The connections are described in this document.    This document is intended to be used in conjunction with the Si53154 device and data sheet for the following tests:   PCIe Gen1, Gen2, Gen3 compliancy Power consumption test Jitter performance Testing out I 2 C code for signal tuning In-system validation where SMA connectors are present

Rev. 0.1 1/12

GND VDD = 3.3V power supply Power connectors Differential Clock Input DIFF3 Output Enable SDATA SCLK Si53154 DIFF1 Output Enable DIFF2 Output Enable DIFF0 Output Enable SRC0 connection for application SRC1 connection for application

Copyright © 2012 by Silicon Labs

SRC3 connection for application SRC2 connection for application

Si53154-EVB

2 S i 5 3 1 5 4 - E V B

1. Front Panel

Differential Buffer Input for on Si53154-EVB only 3.3V Power Supply Connector GND Connector VDD Connectors I2C connect -For I2C read and write. In sequence SData, Gnd, SCLK from left to right . OE_DIFF3 hardware input control for DIFF3 output DIFF3 Differential output OE1 hardware input control for DIFF1 output No Connect OE2 hardware input control for DIFF2 output OE0 hardware input control for DIFF0 output Si53154 device mount

Jumper Label

OE0 OE1 OE2 OE3 SDATA SCLK

Figure 1. Evaluation Module Front Panel Table 1. Input Jumper Settings

Type

I I I I I/O I

Description OE0, 3.3 V Input for Enabling DIFF0 Clock Output

.

1 = DIFF0 enabled, 0 = DIFF0 disabled.

OE1, 3.3 V Input for Enabling DIFF1 Clock Output

.

1 = DIFF1 enabled, 0 = DIFF1 disabled.

OE2, 3.3 V Input for Enabling DIFF2 Clock Output

.

1 = DIFF2 enabled, 0 = DIFF2 disabled.

OE3, 3.3 V Input for Enabling DIFF3 Clock Output

.

1 = DIFF3 enabled, 0 = DIFF3 disabled.

SMBus-Compatible SDATA

.

SMBus-Compatible SCLOCK

.

DIFF2 Differential output DIFF1 Differential output DIFF0 Differential output

Rev. 0.1

Si53154-EVB

1.1. Generating DIFF Outputs from the Si53154

Upon power-on of the device if the differential input is applied and input pins are left floating, by default all DIFF outputs DIFF[0:3] are ON. The input pin headers have clear indication of jumper settings for setting logic low (0) and high (1) as shown in the figure below, the jumper placed on middle and left pin will set input OE0 to low; and jumper placed on middle and right pin will set input OE0 to high.

The output enable pins can be changed on the fly to observe outputs stopped cleanly. Input functionality is explained in detail below.

1.1.1. OE [0:3] Inputs

The output enable pins can change on the fly when the device is on. Deasserting (valid low) results in corresponding DIFF output to be stopped after their next transition with final state low/low. Asserting (valid high) results in corresponding output that was stopped are to resume normal operation in a glitch-free manner. Each of the hardware OE [0:3] pins are mapped via I 2 C to control bit in Control register. The hardware pin and the Register Control Bit both need to be high to enable the output. Both of these form an “AND” function to disable or enable the DIFF output. Both of these form an “AND” function to disable or enable the DIFF output. The DIFF outputs and their corresponding I 2

C control bits and hardware pins are listed in Table 2.

Table 2. Output Enable Control

I 2 C Control Bit

Byte1 [bit 2] Byte1 [bit 0] Byte2 [bit 7] Byte2 [bit 6]

Output

DIFF0 DIFF1 DIFF2 DIFF3

Hardware Control Input

OE0 OE1 OE2 OE3

Rev. 0.1

3

4 S i 5 3 1 5 4 - E V B

2. Schematics

VDD1 VDD6 VDD12 VDD17 VDD21 For Si52144,R10 open For Si53154,R11 open VDD1 R11 NI SSON OE2 OE0 OE3 R10 0 OE1 SCLK SDATA C1 0.1uF

C2 0.1uF

C3 0.1uF

C4 0.1uF

C5 0.1uF

DUTGND DUTGND U1 5 OE2 7 OE0 18 OE3 2 OE1 3 VDD 19 SCLK 20 SDA 1 6 12 17 21 VDD1 VDD6 VDD12 VDD17 VDD21 4 24 25 VSS4 VSS24 EPAD XOUT/DIFFIN Si53154 XIN/DIFFIN# 23 DIFF0 DIFF0# 8 9 DIFF1 DIFF1# 10 11 DIFF2 DIFF2# DIFF3 DIFF3# 22 14 13 16 15 DIFF0 DIFF0# DIFF1 DIFF1# DIFF2 DIFF2# DIFF3 DIFF3#

Figure 2. QFN-24 Device Connection

R1 0 R2 NI Y1 NI R3 NI R4 0 XOUT_DIFFIN YC1 NI YC2 NI

XTL P/N: ECS-250-20-5PXDU-F-TR Use SMD footprint

DUTGND XIN_DIFFIN# VCC_3.3V

VCC_3.3V

L1 + C6 10uF VDD_3.3V1

1 HEADER 1x1 C7 0.1uF

1 GND1 HEADER 1x1 JP1 JUMPER L2 JP2 JUMPER L3 JP3 JUMPER L4 JP4 JUMPER L5 JP5 JUMPER L6 TP1 TP2 TP3 TP4 TP5 VDD1 VDD21 VDD6 VDD12 VDD17 R5 0 + C8 10uF C13 1uF R6 0 + C9 10uF C17 1uF R7 0 + C10 10uF C14 1uF R8 0 + C11 10uF C15 1uF R9 0 + C12 10uF C16 1uF

Figure 3. Device Power Supply

Rev. 0.1

OE2 HEADER 1x3 P2 3 2 1 GND VDD VDD_3.3V

DUTGND OE2 R16 10K OE0 HEADER 1x3 P3 VDD 3 2 1 GND OE0 VDD_3.3V

DUTGND R20 10K OE3 HEADER 1x3 P4 VDD 3 2 1 GND VDD_3.3V

OE3 DUTGND R23 10K OE1 HEADER 1x3 P5 3 2 1 GND VDD VDD_3.3V

DUTGND R24 10K OE1 SSON SSON HEADER 1x3 3 2 1 VDD P6 GND VDD_3.3V

DUTGND

SCLK/SDATA

VDD_3.3V

HEADER 1x3 3 2 1 P1 R15 10K DUTGND VDD_3.3V

R17 10K SCLK SDATA

Si53154-EVB

XIN_DIFFIN#1 SMA DUTGND XOUT_DIFFIN1 SMA DUTGND XIN_DIFFIN# XOUT_DIFFIN DIFF0 DIFF0# L1 SHOULD BE SHORT AS POSSIBLE DIFF1 DIFF1# L1 SHOULD BE SHORT AS POSSIBLE

Figure 4. Clock and Control Signals

DUTGND C27 2.0pF

DUTGND C29 2.0pF

DIFF0_1 SMA DUTGND DIFF0#_1 SMA DUTGND DIFF2 DIFF2# L1 SHOULD BE SHORT AS POSSIBLE C28 2.0pF

C30 2.0pF

DIFF2_1 SMA DUTGND DIFF2#_1 SMA DUTGND DUTGND C32 2.0pF

DUTGND C34 2.0pF

DIFF1_1 SMA DUTGND DIFF1#_1 SMA DIFF3 DIFF3# L1 SHOULD BE SHORT AS POSSIBLE

Figure 5. Differential Clock Signals

Rev. 0.1

DUTGND C31 2.0pF

DUTGND C33 2.0pF

DIFF3_1 SMA DUTGND DIFF3#_1 SMA DUTGND

5

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