Silicon Labs EZR32WG Reference Manual

Silicon Labs EZR32WG  Reference Manual

...the world's most energy friendly wireless MCUs

EZR32WG Reference Manual

• Silicon Labs’ first 32-bit Wireless MCUs • Based on ARM Cortex M4 CPU cores • 256KB of Flash and 32KB RAM • Best-in-class RF performance with EZradio and EZRadioPRO transceivers • Ultra-low power wireless MCU • Low transmit and receive currents • Ultra-low power standby and sleep modes • Fast wake-up time • Low Energy sensor interface (LESENSE) • Rich set of peripherals including 12-bit ADC and DAC, multiple communication interfaces (USB, UART, LEUART, SPI, I2C), GPIO and timers • AES Accelerator with 128/256-bit keys The EZR32WG Wireless MCUs are the latest in Silicon Labs family of wireless MCUs delivering a high performance, low energy wireless solution integrated into a small form factor package. By combining a high performance sub-GHz RF transceiver with an energy efficient 32-bit MCU, the EZR32WG family provides designers the ultimate in flexibility with a family of pin-compatible devices that scale with 64/128/256 kB of flash and support Silicon Labs EZRadio or EZRadioPRO transceivers. The ultra-low power operating modes and fast wake-up times of the Silicon Labs energy friendly 32-bit MCUs, combined with the low transmit and receive power consumption of the sub-GHz radio, result in a solution optimized for battery powered applications.

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1 Energy Friendly Wireless Microcontrollers

1.1 Typical Applications

The EZR32WG wireless microcontroller is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications. These devices are developed to minimize the energy consumption by lowering both the power and the active time, over all phases of MCU operation. This unique combination of ultra low energy consumption and the performance of the 32-bit ARM Cortex-M4 processor, help designers get more out of the available energy in a variety of applications.

Ultra low energy EZR32WG wireless microcontrollers are perfect for:

• Gas metering • Energy metering • Water metering • Smart metering • Alarm and security systems • Health and fitness applications • Industrial and home automation

0 1 2 3 4

1.2 EZR32WG Development

Because EZR32WG use the Cortex-M4 CPU, embedded designers benefit from the largest development ecosystem in the industry, the ARM ecosystem. The development suite spans the whole design process and includes powerful debug tools, and some of the world’s top brand compilers. Libraries with documentation and user examples shorten time from idea to market.

The range of EZR32WG devices ensure easy migration and feature upgrade possibilities.

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2 About This Document

This document contains reference material for the EZR32WG series of wireless microcontrollers. All modules and peripherals in the EZR32WG series devices are described in general terms. Not all modules are present in all devices, and the feature set for each device might vary. Such differences, including pin-out, are covered in the device-specific datasheets.

2.1 Conventions Register Names

Register names are given as a module name prefix followed by the short register name: TIMERn_CTRL - Control Register The "n" denotes the numeric instance for modules that might have more than one instance.

Some registers are grouped which leads to a group name following the module prefix: GPIO_Px_DOUT - Port Data Out Register, where x denotes the port instance (A,B,...).

Bit Fields

Registers contain one or more bit fields which can be 1 to 32 bits wide. Multi-bit fields are denoted with (x:y), where x is the start bit and y is the end bit.

Address

The address for each register can be found by adding the base address of the module (found in the Memory Map), and the offset address for the register (found in module Register Map).

Access Type

The register access types used in the register descriptions are explained in Table 2.1 (p. 3) .

Table 2.1. Register Access Types

Access Type

R RW RW1 RW1H W1 W RWH

Description

Read only. Writes are ignored.

Readable and writable.

Readable and writable. Only writes to 1 have effect.

Readable, writable and updated by hardware. Only writes to 1 have effect.

Read value undefined. Only writes to 1 have effect.

Write only. Read value undefined.

Readable, writable and updated by hardware.

Number format

0x prefix is used for hexadecimal numbers.

0b prefix is used for binary numbers.

Numbers without prefix are in decimal representation.

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Reserved

Registers and bit fields marked with reserved are reserved for future use. These should be written to 0 unless otherwise stated in the Register Description. Reserved bits might be read as 1 in future devices.

Reset Value

The reset value denotes the value after reset.

Registers denoted with X have an unknown reset value and need to be initialized before use. Note that, before these registers are initialized, read-modify-write operations might result in undefined register values.

Pin Connections

Pin connections are given as a module prefix followed by a short pin name: USn_TX (USARTn TX pin) The pin locations referenced in this document are given in the device-specific datasheet.

2.2 Related Documentation

Further documentation on the EZR32WG family and the ARM Cortex-M4 can be found at the Silicon Laboratories and ARM web pages: www.silabs.com

www.arm.com

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3 System Overview

3.1 Introduction

The EZR32WG Wireless MCUs are the latest in Silicon Labs family of wireless MCUs delivering a high performance, low energy wireless solution integrated into a small form factor package. By combining a high performance sub-1 GHz RF transceiver with an energy efficient 32-bit MCU, the EZR32WG family provides designers the ultimate in flexibility with a family of pin-compatible devices that scale with 64/128/256 kB of flash and support Silicon Labs EZRadio or EZRadioPRO transceivers. The ultra low power operating modes and fast wake-up times of the Silicon Labs energy friendly 32-bit MCUs, combined with the low transmit and receive power consumption of the sub-1 GHz radio, result in a

solution optimized for battery powered applications, see Figure 3.1 (p. 5) .

3.2 Block Diagram

Figure 3.1 (p. 5) shows the block diagram of EZR32WG. The color indicates peripheral availability

in the different energy modes, described in Section 3.4 (p. 8) .

Figure 3.1. Block Diagram of EZR32WG

ARM Cort ex ™ M4 processor wit h DSP ex t ensions and FPU Flash Program Mem ory TX 18 m A @ 20 dBm Core and Mem ory RAM Mem ory Transceiver 142- 1050 MHz ASK, OOK, (G)FSK, 4(G)FSK SPI RX 10 m A Pream ble Sense 5.4 m A 133 dBm sensit ivit y Debug Int erface w/ ETM 32- bit bus Peripheral Reflex Syst em Serial Int erfaces I/ O Port s USART SPI USB Mem ory Prot ect ion Unit EZR32WG Clock Managem ent Aux High Freq RC Oscillat or High Freq RC Oscillat or High Freq Cryst al Oscillat or Low Freq RC Oscillat or DMA Cont roller Low Freq Cryst al Oscillat or Ult ra Low Freq RC Oscillat or Energy Managem ent Volt age Regulat or Volt age Com parat or Brown- out Det ect or Back- up Power Dom ain Power- on Reset Low Energy UART I 2 C Ex t ernal Int errupt s Pin Reset General Purpose I/ O Pin Wakeup Tim ers and Triggers Tim er/ Count er LESENSE Low Energy Tim er Real Tim e Count er Pulse Count er Wat chdog Tim er Back- up RTC Analog Int erfaces ADC DAC Securit y Hardware AES Analog Com parat or Operat ional Am plifier Ant enna Diversit y 1 Mbps

Figure 3.2. Energy Mode Indicator 0 1 2 3 4

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In the energy mode indicator, the numbers indicates Energy Mode, i.e EM0-EM4.

3.3 Features

3.3.1 MCU Features

ARM Cortex-M4 CPU platform • High Performance 32-bit processor @ up to 48 MHz MHz • DSP instruction support and floating-point unit • Memory Protection Unit • Wake-up Interrupt Controller • Flexible Energy Management System • 20 nA @ 3 V Shutoff Mode • 0.4 µA @ 3 V Shutoff Mode with RTC • 0.65 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention • 0.95 µA @ 3 V Deep Sleep Mode, including RTC with 32768 Hz oscillator, Power-on Reset, Brown-out Detector, RAM and CPU retention • 63 µA/MHz @ 3 V Sleep Mode • 225 µA/MHz @ 3 V Run Mode, with code executed from flash • 256/128/64 KB Flash32 KB RAMUp to 41 General Purpose I/O pins • Configurable push-pull, open-drain, pull-up/down, input filter, drive strength • Configurable peripheral I/O locations • 16 asynchronous external interrupts • Output state retention and wake-up from Shutoff Mode • 12 Channel DMA Controller • Alternate/primary descriptors with scatter-gather/ping-pong operation • 12 Channel Peripheral Reflex System • Autonomous inter-peripheral signaling enables smart operation in low energy modes • Universal Serial Bus (USB) • Fully USB 2.0 compliant • On-chip PHY and embedded 5V to 3.3V regulator • Hardware AES with 128/256-bit Keys in 54/75 cyclesCommunication interfaces • 2× Universal Synchronous/Asynchronous Receiver/Transmitter • UART/SPI/SmartCard (ISO 7816)/IrDA (USART0)/I2S (USART1+USART2) • Triple buffered full/half-duplex operation • 4-16 data bits • 2× Universal Asynchronous Receiver/Transmitter • Triple buffered full/half-duplex operation • 8-9 data bits • 2× Low Energy UART • Autonomous operation with DMA in Deep Sleep Mode • 2× I 2 C Interface with SMBus support • Address recognition in Stop Mode • Timers/Counters • 4× 16-bit Timer/Counter • 3 Compare/Capture/PWM channels • Dead-Time Insertion on TIMER0 • 16-bit Low Energy Timer 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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• 1× 24-bit and 1× 32-bit Real-Time Counter • 3× 8/16-bit Pulse Counter • Asynchronous pulse counting/quadrature decoding • Watchdog Timer with dedicated RC oscillator @ 50 nA • Backup Power Domain • RTC and retention registers in a separate power domain, available in all energy modes • Operation from backup battery when main power drains out • Ultra low power precision analog peripherals • 12-bit 1 Msamples/s Analog to Digital Converter • 8 input channels and on-chip temperature sensor • Single ended or differential operation • Conversion tailgating for predictable latency • 12-bit 500 ksamples/s Digital to Analog Converter • 2 single ended channels/1 differential channel • Up to 3 Operational Amplifiers • Supports rail-to-rail inputs and outputs • Programmable gain • 2× Analog Comparator • Programmable speed/current • Capacitive sensing with up to 8 inputs • Supply Voltage Comparator • Ultra low power sensor interface • Autonomous sensor monitoring in Deep Sleep Mode • Wide range of sensors supported, including LC sensors and capacitive buttons

3.3.2 RF Features

Frequency range = 142–1050 MHzReceive sensitivity = -133 dBmModulation • (G)FSK, 4(G)FSK, (G)MSK, OOK • Max output power • +20 dBm • +16 dBm • +13 dBm • PA support for +27 or +30 dBmLow active power consumption • 10/13 mA RX • 18 mA TX at +10 dBm • Preamble sense mode • 6 mA average RX current at 1.2 kbps • 10 µA average RX current at 50 kbps and 1 sec sleep interval • Fast preamble detection • 1 byte preamble detection • Data rate = 100 bps to 1 MbpsFast wake and hop timesPower supply = 1.8 to 3.8 VExcellent selectivity performance • 69 dB adjacent channel • 79 dB blocking at 1 MHz • Antenna diversity and T/R switch controlHighly configurable packet handler 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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TX and RX 64 byte FIFOs • 129 bytes dedicated Tx or Rx • Auto frequency control (AFC)Automatic gain control (AGC)Low battery detectorTemperature sensorIEEE 802.15.4g and WMBus compliantSuitable for FCC Part 90 Mask D, FCC part 15.247, 15,231, 15,249, ARIB T-108, T-96,

T-67, RCR STD-30, China regulatory

ETSI Category I Operation EN300 220

3.3.3 System Features

Ultra efficient Power-on Reset and Brown-Out DetectorDebug Interface • 2-pin Serial Wire Debug interface • 1-pin Serial Wire Viewer • Embedded Trace Module v3.5 (ETM) • Temperature range -40 - 85°CSingle power supply 1.98 - 3.8 VPackages • QFN64

3.4 Energy Modes

There are five different Energy Modes (EM0-EM4) in the EZR32WG, see Table 3.1 (p. 9) . The

EZR32WG is designed to achieve a high degree of autonomous operation in low energy modes. The intelligent combination of peripherals, RAM with data retention, DMA, low-power oscillators, and short wake-up time, makes it attractive to remain in low energy modes for long periods and thus saving energy consumption.

Tip

Throughout this document, the first figure in every module description contains an Energy Mode

Indicator showing which energy mode(s) the module can operate (see Table 3.1 (p. 9) ).

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Table 3.1. Energy Mode Description

Energy Mode Name Description

...the world's most energy friendly wireless MCUs 0 1 2 3 4

EM0 – Energy Mode 0 (Run mode) In EM0, the CPU is running and consuming as little as 225 µA/MHz, when running code from flash. All peripherals can be active.

0 1 2 3 4

EM1 – Energy Mode 1 (Sleep Mode) In EM1, the CPU is sleeping and the power consumption is only 63 µA/MHz.

All peripherals, including DMA, PRS and memory system, are still available.

0 1 2 3 4 0 1 2 3 4

EM2 – Energy Mode 2 (Deep Sleep Mode) In EM2 the high frequency oscillator is turned off, but with the 32.768 kHz oscillator running, selected low energy peripherals (RTC, LETIMER, PCNT, LEUART, I 2 C, LESENSE, OPAMP, USB, WDOG and ACMP) are still available. This gives a high degree of autonomous operation with a current consumption as low as 0.95 µA with RTC enabled. Power-on Reset, Brown out Detection and full RAM and CPU retention is also included.

EM3 - Energy Mode 3 (Stop Mode) In EM3, the low-frequency oscillator is disabled, but there is still full CPU and RAM retention, as well as Power-on Reset, Pin reset, EM4 wake-up and Brown-out Detection, with a consumption of only 0.65 µA. The low-power ACMP, asynchronous external interrupt, PCNT, and I 2 C can wake-up the device. Even in this mode, the wake-up time is a few microseconds.

0 1 2 3 4

EM4 – Energy Mode 4 (Shutoff Mode) In EM4, the current is down to 20 nA and all chip functionality is turned off except the pin reset, GPIO pin wake-up, GPIO pin retention, Backup RTC (including retention RAM) and the Power-On Reset. All pins are put into their reset state.

3.5 Product Overview

Table 3.2 (p. 9) shows a device overview of the EZR32WG Wireless Microcontroller Series,

including peripheral functionality. For more information, the reader is referred to the device specific datasheets.

Table 3.2. EZR32WG Wireless Microcontroller Series

230F64 230F128 230F256 330F64 64 128 256 32 32 32 41 41 41 64 32 37 Y 4 2 4 4 4 2 2 2 2 2 2 2 4 (12) 4 (12) 4 (12) 4 (12) 1 1 1 1 1 3 1 1 1 3 3 3 1 1 1 1 1 (8) 1 (8) 1 (8) 1 (8) 2 (2) 2 (16) 2 (2) 2 (16) 2 (2) 2 (16) 2 (2) 2 (12) Y Y Y Y Y 3 QFN64 Y Y Y 3 QFN64 3 QFN64 3 QFN64 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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330F128 330F256 128 32 37 Y 256 32 37 Y 4 2 4 2 2 2 4 (12) 4 (12) 1 1 1 3 1 3 1 1 1 (8) 1 (8) 2 (2) 2 (12) 2 (2) 2 (12) Y Y Y 3 QFN64 Y 3 QFN64

3.6 Device Revision

The device revision number is read from the ROM Table. The major revision number and the chip family number is read from PID0 and PID1 registers. The minor revision number is extracted from the PID2 and

PID3 registers, as illustrated in Figure 3.3 (p. 10) . The Fam[5:2] and Fam[1:0] must be combined

to complete the chip family number, while the Minor Rev[7:4] and Minor Rev[3:0] must be combined to form the complete revision number.

Figure 3.3. Revision Number Extraction

31:8 PID2 (0 xE0 0 FFFE8 ) 7:4 Minor Rev[7:4] 3:0 31:8 PID0 (0 xE0 0 FFFE0 ) 7:6 Fam [1:0] 5:0 Major Rev[5:0] 31:8 PID3 (0 xE0 0 FFFEC) 7:4 Minor Rev[3:0] 3:0 PID1 (0 xE0 0 FFFE4 ) 31:4 3:0 Fam [5:2] For the latest revision of the EZR32WG family, the chip family number is 0x03 and the major revision

number is 0x01. The minor revision number is to be interpreted according to Table 3.3 (p. 10) .

Table 3.3. Minor Revision Number Interpretation

Minor Rev[7:0]

0x00

Revision

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4 Radio Overview

The EZR32WG family of devices is built using high-performance, low-current EZRadio and EZRadioPRO RF transceivers covering the sub-GHz frequency bands from 142 to 1050 MHz. These devices offer outstanding sensitivity of upto -133 dBm (using EZRadioPRO) while achieving extremely low active and standby current consumption. The EZR32WG devices using the EZRadioPRO transceiver offer frequency coverage in all major bands and include optimal phase noise, blocking, and selectivity performance for narrow band and licensed band applications, such as FCC Part 90 and 169 MHz wireless M-Bus. The 69 dB adjacent channel selectivity with 12.5 kHz channel spacing ensures robust receive operation in harsh RF conditions, which is particularly important for narrow band operation. The active mode TX current consumption of 18 mA at +10 dBm and RX current of 10 mA coupled with extremely low standby current and fast wake times is optimized for extended battery life in the most demanding applications. The EZR32WG devices can achieve up to +27 dBm output power with built in ramping control of a low-cost external FET. The devices can meet worldwide regulatory standards: FCC, ETSI, and ARIB. All devices are designed to be compliant with 802.15.4g and Wireless M-Bus smart metering standards. The devices are highly flexible and can be programmed and configured via Simplicity Studio, available at www.silabs.com.

4.1 EZRadioPRO Overview

4.1.1 Introduction

Silicon Laboratories' EZRadioPRO devices are high-performance, low-current RF transceivers covering the sub-GHz frequency bands from 142 to 1050 MHz. All parts offer outstanding sensitivity of -129 dBm while achieving extremely low active and standby current consumption. EZRadioPRO devices offers frequency coverage in all major bands. The EZRadioPRO devices includes optimal phase noise, blocking, and selectivity performance for narrow band and wireless M-Bus licensed band applications, such as FCC Part90 and 169 MHz wireless M-Bus. The 69 dB adjacent channel selectivity with 12.5 kHz channel spacing ensures robust receive operation in harsh RF conditions, which is particularly important for narrow band operation. The EZRadioPRO devices offers exceptional output power of up to +20 dBm with outstanding TX efficiency. The high output power and sensitivity results in an industry-leading link budget of 146 dB allowing extended ranges and highly robust communication links. The EZRadioPRO active mode TX current consumption of 18 mA at +10 dBm and RX current of 10 mA coupled with extremely low standby current and fast wake times ensure extended battery life in the most demanding applications. The EZRadioPRO devices can achieve up to +27 dBm output power with built-in ramping control of a low-cost external FET. The devices can meet worldwide regulatory standards: FCC, ETSI, wireless M-Bus, and ARIB. All devices are designed to be compliant with 802.15.4g and Wireless M Bus smart metering standards.

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...the world's most energy friendly wireless MCUs Figure 4.1. EZRadioPRO Block Diagram

SDN RXP RXN TX GPIO3 GPIO2 VCO FBDIV TX DIV LO Gen Loop Filt er RF PKDET

LNA PA

PowerRam p Cnt l PA LDO TXRAMP PFD / CP XIN XOUT Frac- N Div 30 MHz XO Boot up OSC IF PKDET PGA ADC MODEM FIFO Packet Handler LDOs POR LBD 32K LP OSC VDD Digit al Logic GPIO0 GPIO1 nSEL SDI SDO SCLK nIRQ

4.1.2 Functional Description

The EZRadioPRO devices are high-performance, low-current, wireless ISM transceivers that cover the sub-GHz bands. The wide operating voltage range of 1.8-3.8 V and low current consumption make the EZRadioPRO an ideal solution for battery powered applications. The EZRadioPRO operates as a time division duplexing (TDD) transceiver where the device alternately transmits and receives data packets. The device uses a single-conversion mixer to downconvert the 2/4-level FSK/GFSK or OOK modulated receive signal to a low IF frequency. Following a programmable gain amplifier (PGA) the signal is converted to the digital domain by a high performance ∆Σ ADC allowing filtering, demodulation, slicing, and packet handling to be performed in the built-in DSP increasing the receiver’s performance and flexibility versus analog based architectures. The demodulated signal is output to the system MCU through a programmable GPIO or via the standard SPI bus by reading the 64-byte RX FIFO.

A single high precision local oscillator (LO) is used for both transmit and receive modes since the transmitter and receiver do not operate at the same time. The LO is generated by an integrated VCO and ∆Σ Fractional-N PLL synthesizer. The synthesizer is designed to support configurable data rates from 100 bps to 1 Mbps. The EZRadioPRO devices operate in the frequency bands of 142-175, 283-350, 350-525, and 850-1050 MHz with a maximum frequency accuracy step size of 28.6 Hz. The transmit FSK data is modulated directly into the ∆Σ data stream and can be shaped by a Gaussian low-pass filter to reduce unwanted spectral content.

The EZRadioPRO contains a power amplifier (PA) that supports output power up to +20 dBm with very high efficiency, consuming only 70 mA at 169 MHz and 85 mA at 915 MHz. The integrated +20 dBm power amplifier can also be used to compensate for the reduced performance of a lower cost, lower performance antenna or antenna with size constraints due to a small form-factor. Competing solutions require large and expensive external PAs to achieve comparable performance. EZRadioPRO is designed to support single coin cell operation with current consumption below 18 mA for +10 dBm output power. Two match topologies are available for the EZRadioPRO, class-E and switched-current. Class 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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E matching provides optimal current consumption, while switched-current matching demonstrates the best performance over varying battery voltage and temperature with slightly higher current consumption.

The PA is single-ended to allow for easy antenna matching and low BOM cost. The PA incorporates automatic ramp-up and ramp-down control to reduce unwanted spectral spreading. The EZRadioPRO family supports frequency hopping, TX/RX switch control, and antenna diversity switch control to extend the link range and improve performance. Built-in antenna diversity and support for frequency hopping can be used to further extend range and enhance performance. Antenna diversity is completely integrated into the EZRadioPRO and can improve the system link budget by 8-10 dB, resulting in substantial range increases under adverse environmental conditions. A highly configurable packet handler allows for autonomous encoding/decoding of nearly any packet structure. Additional system features, such as an automatic wake-up timer, low battery detector, 64 byte TX/RX FIFOs, and preamble detection, reduce overall current consumption and allows for the use of lower-cost system MCUs. An integrated temperature sensor, power-on-reset (POR), and GPIOs further reduce overall system cost and size.

4.1.3 Controller Interface

4.1.3.1 Serial Peripheral Interface (SPI)

The EZRadioPRO communicates with the EFM32WG MCU over a standard 4-wire serial peripheral interface (SPI): SCLK, SDI, SDO, and nSEL. The SPI interface is designed to operate at a maximum

of 10 MHz. The SPI timing parameters are demonstrated in Table 4.1 (p. 13) . The host MCU writes data over the SDI pin and can read data from the device on the SDO output pin. Table 4.1 (p. 13)

demonstrates an SPI write command. The nSEL pin should go low to initiate the SPI command. The first byte of SDI data will be one of the firmware commands followed by n bytes of parameter data which will be variable depending on the specific command. The rising edges of SCLK should be aligned with the center of the SDI data. For details regarding pin setup, see datasheet for the specific part.

Table 4.1. Serial Interface Timing Parameters

Symbol

tCH tCL tDS tDH tDD tDE tSS tSH tSW

Parameter

Clock high time Clock low time Data setup time Data hold time Output data delay time Output disable time Select setup time Select hold time Select high period 20 20

Min (ns)

40 40 20 50 80 43 45

Max (ns)

Note

CL = 10 pF; VDD = 1.8 V; SDO Drive strength setting = 10.

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Figure 4.2. Serial Interface Timing ...the world's most energy friendly wireless MCUs Figure 4.3. SPI Write Command

nSEL SDO SDI SCLK FW Command Param Byte 0 Param Byte n The EZRadioPRO contains an internal MCU which controls all the internal functions of the radio. For SPI read commands a typical MCU flow of checking clear-to-send (CTS) is used to make sure the internal

MCU has executed the command and prepared the data to be output over the SDO pin. Figure 4.4 (p.

15) demonstrates the general flow of an SPI read command. Once the CTS value reads FFh then

the read data is ready to be clocked out to the host MCU. The typical time for a valid FFh CTS reading is

20 µs. Figure 4.5 (p. 15) demonstrates the remaining read cycle after CTS is set to FFh. The internal

MCU will clock out the SDO data on the negative edge so the host MCU should process the SDO data on the rising edge of SCLK.

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...the world's most energy friendly wireless MCUs Figure 4.4. SPI Read Command - Check CTS Value

Firm ware Flow

Send Com m and Read CTS CTS Value

0x FF 0x 00

Ret rieve Response

NSEL SDO SDI SCK ReadCm dBuff CTS

Figure 4.5. SPI Read Command - Clock Out Read Data

NSEL SDO SDI SCK Response Byt e 0 Response Byt e n

The fast response registers are registers that can be read immediately without the requirement to monitor and check CTS. There are four fast response registers that can be programmed for a specific function.

The fast response registers can be read through API commands, 0x50 for Fast Response A, 0x51 for Fast Response B, 0x53 for Fast Response C, and 0x57 for Fast Response D. The fast response registers can be configured by the “FRR_CTL_X_MODE” properties.

4.1.3.2 Fast Response Registers

The fast response registers are registers that can be read immediately without the requirement to monitor and check CTS. There are four fast response registers that can be programmed for a specific function.

The fast response registers can be read through API commands, 0x50 for Fast Response A, 0x51 for Fast Response B, 0x53 for Fast Response C, and 0x57 for Fast Response D. The fast response registers can be configured by the “FRR_CTL_X_MODE” properties.

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4.1.3.3 Operating Modes and Timing

The primary states of the EZRadioPRO are shown in Figure 4.6 (p. 16) . The shutdown state

completely shuts down the radio to minimize current consumption. Standby/Sleep, SPI Active, Ready, TX Tune, and RX tune are available to optimize the current consumption and response time to RX/ TX for a given application. API commands START_RX, START_TX, and CHANGE_STATE control the

operating state with the exception of shutdown which is controlled by SDN, pin 1. Table 4.2 (p. 16)

shows each of the operating modes with the time required to reach either RX or TX mode as well as the

current consumption of each mode. The times in Table 4.1 (p. 13) are measured from the rising edge

of nSEL until the chip is in the desired state. Note that these times are indicative of state transition timing but are not guaranteed and should only be used as a reference data point. An automatic sequencer will put the chip into RX or TX from any state. It is not necessary to manually step through the states. To simplify the diagram it is not shown but any of the lower power states can be returned to automatically after RX or TX.

Figure 4.6. State Machine Diagram Table 4.2. Operating State Response Time and Current Consumption

State/Mode

Shutdown State Standby State Sleep State SPI Active State Ready State TX Tune State RX Tune State TX State RX State

TX

15 ms 440 µs 440 µs 340 µs 100 µs 58 µs 100 µs

Response Time to RX

15 ms 440 µs 440 µs 340 µs 100 µs 60 µs 100 µs 75 µs

Current in State /Mode

30 nA 40 nA 740 nA 1.35 mA 1.8 mA 7.8 mA 7.6 mA 18 mA @ +10 dBm 10.9 or 13.7 mA

Note

TX → RX and RX → TX state transition timing can be reduced to 70 µs if using Zero-IF mode.

Figure 4.7 (p. 17) shows the POR timing and voltage requirements. The power consumption (battery

life) depends on the duty cycle of the application or how often the part is in either Rx or Tx state. In most applications the utilization of the standby state will be most advantageous for battery life but for very low duty cycle applications shutdown will have an advantage. For the fastest timing the next state can be selected in the START_RX or START_TX API commands to minimize SPI transactions and internal MCU processing.

4.1.3.3.1 Power on Reset (POR)

A Power On Reset (POR) sequence is used to boot the device up from a fully off or shutdown state. To execute this process, VDD must ramp within 1ms and must remain applied to the device for at least 10 ms. If VDD is removed, then it must stay below 0.15 V for at least 10 ms before being applied again.

See Figure 4.7 (p. 17) and Table 4.3 (p. 17) for details.

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Figure 4.7. POR Timing Diagram ...the world's most energy friendly wireless MCUs Table 4.3. POR Timing

Variable

tPORH tPORL VRRH VRRL tSR

Description

High time for VDD to fully settle POR circuit Low time for VDD to enable POR Voltage for successful POR Starting Voltage for successful POR Slew rate of VDD for successful POR 0

Min

10 10 90% x Vdd

Typ Max

150 1

Units

ms ms V mV ms

4.1.3.3.2 Shutdown State

The shutdown state is the lowest current consumption state of the device with nominally less than 30 nA of current consumption. The shutdown state may be entered by driving the SDN pin (Pin 1) high.

The SDN pin should be held low in all states except the shutdown state. In the shutdown state, the contents of the registers are lost and there is no SPI access. When coming out of the shutdown state a power on reset (POR) will be initiated along with the internal calibrations. After the POR the POWER_UP command is required to initialize the radio. The SDN pin needs to be held high for at least 10us before driving low again so that internal capacitors can discharge. Not holding the SDN high for this period of time may cause the POR to be missed and the device to boot up incorrectly. If POR timing and voltage requirements cannot be met, it is highly recommended that SDN be controlled using the host processor rather than tying it to GND on the board.

4.1.3.3.3 Standby State

Standby state has the lowest current consumption with the exception of shutdown but has much faster response time to RX or TX mode. In most cases standby should be used as the low power state. In this state the register values are maintained with all other blocks disabled. The SPI is accessible during this mode but any SPI event, including FIFO R/W, will enable an internal boot oscillator and automatically move the part to SPI active state. After an SPI event the host will need to re-command the device back to standby through the “Change State” API command to achieve the 40 nA current consumption. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption of this mode.

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4.1.3.3.4 Sleep State

Sleep state is the same as standby state but the wake-up-timer and a 32 kHz clock source are enabled.

The source of the 32 kHz clock can either be an internal 32 kHz RC oscillator which is periodically calibrated or a 32 kHz oscillator using an external XTAL.The SPI is accessible during this mode but an SPI event will enable an internal boot oscillator and automatically move the part to SPI active mode. After an SPI event the host will need to re-command the device back to sleep. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption of this mode.

4.1.3.3.5 SPI Active State

In SPI active state the SPI and a boot up oscillator are enabled. After SPI transactions during either standby or sleep the device will not automatically return to these states. A “Change State” API command will be required to return to either the standby or sleep modes.

4.1.3.3.6 Ready State

Ready state is designed to give a fast transition time to TX or RX state with reasonable current consumption. In this mode the Crystal oscillator remains enabled reducing the time required to switch to TX or RX mode by eliminating the crystal start-up time.

4.1.3.3.7 TX State

The TX state may be entered from any of the state with the “Start TX” or “Change State” API commands.

A built-in sequencer takes care of all the actions required to transition between states from enabling the crystal oscillator to ramping up the PA. The following sequence of events will occur automatically when going from standby to TX state.

• Enable internal LDOs.

• Start up crystal oscillator and wait until ready (controlled by an internal timer).

• Enable PLL.

• Calibrate VCO/PLL.

• Wait until PLL settles to required transmit frequency (controlled by an internal timer).

• Activate power amplifier and wait until power ramping is completed (controlled by an internal timer).

• Transmit packet.

Steps in this sequence may be eliminated depending on which state the chip is configured to prior to commanding to TX. By default, the VCO and PLL are calibrated every time the PLL is enabled. When the START_TX API command is utilized the next state may be defined to ensure optimal timing and turnaround.

Figure 4.8 (p. 19) shows an example of the commands and timing for the START_TX command. CTS

will go high as soon as the sequencer puts the part into TX state. As the sequencer is stepping through the events listed above, CTS will be low and no new commands or property changes are allowed. If the Fast Response (FRR) or nIRQ is used to monitor the current state there will be slight delay caused by the internal hardware from when the event actually occurs to when the transition occurs on the FRR or nIRQ. The time from entering TX state to when the FRR will update is 5 µs and the time to when the nIRQ will transition is 13 µs. If a GPIO is programmed for TX state or used as control for a transmit/ receive switch (TR switch) there is no delay.

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Figure 4.8. Start_TX Commands and Timing ...the world's most energy friendly wireless MCUs

CTS NSEL SDI Current St at e FRR nIRQ GPIOx – TX st at e START_TX YYY St at e YYY St at e Tx St at e Tx St at e TXCOMPLETE_STATE TXCOMPLETE_STATE

4.1.3.3.8 RX State

The RX state may be entered from any of the other states by using the “Start RX” or “Change State” API command. A built-in sequencer takes care of all the actions required to transition between states.

The following sequence of events will occur automatically to get the chip into RX mode when going from standby to RX state: • Enable the digital LDO and the analog LDOs.

• Start up crystal oscillator and wait until ready (controlled by an internal timer).

• Enable PLL.

• Calibrate VCO.

• Wait until PLL settles to required receive frequency (controlled by an internal timer).

• Enable receiver circuits: LNA, mixers, and ADC.

• Enable receive mode in the digital modem.

Depending on the configuration of the radio, all or some of the following functions will be performed automatically by the digital modem: AGC, AFC (optional), update status registers, bit synchronization, packet handling (optional) including sync word, header check, and CRC. Similar to the TX state, the next state after RX may be defined in the “Start RX” API command. The START_RX commands and timing

will be equivalent to the timing shown in Figure 4.8 (p. 19) .

4.1.3.4 Application Programming Interface (API)

An application programming interface (API), which the host MCU will communicate with, is embedded inside the device. The API is divided into two sections, commands and properties. The commands are used to control the chip and retrieve its status. The properties are general configurations which will change infrequently. The API descriptions can be found on the Silicon Labs website.

4.1.3.5 Interrupts

The EZRadioPRO is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0.

This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Registers. The nIRQ output signal will then be reset until the next change in status is detected.

The interrupts sources are grouped into three groups: packet handler, chip status, and modem. The individual interrupts in these groups can be enabled/disabled in the interrupt property registers. An interrupt must be enabled for it to trigger an event on the nIRQ pin. The interrupt group must be enabled as well as the individual interrupts in API properties described in the API documentation.

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Once an interrupt event occurs and the nIRQ pin is low there are two ways to read and clear the interrupts.

All of the interrupts may be read and cleared in the “GET_INT_STATUS” API command. By default all interrupts will be cleared once read. If only specific interrupts want to be read in the fastest possible method the individual interrupt groups (Packet Handler, Chip Status, Modem) may be read and cleared by the “GET_MODEM_STATUS”, “GET_PH_STATUS” (packet handler), and “GET_CHIP_STATUS” API commands.

The instantaneous status of a specific function maybe read if the specific interrupt is enabled or disabled.

The status results are provided after the interrupts and can be read with the same commands as the interrupts. The status bits will give the current state of the function whether the interrupt is enabled or not.

The fast response registers can also give information about the interrupt groups but reading the fast response registers will not clear the interrupt and reset the nIRQ pin.

4.1.3.6 GPIO

Four general purpose IO pins are available to utilize in the application. The GPIO are configured by the GPIO_PIN_CFG command in address 13h. For a complete list of the GPIO options please see the API guide. GPIO pins 0 and 1 should be used for active signals such as data or clock. GPIO pins 2 and 3 have more susceptibility to generating spurious in the synthesizer than pins 0 and 1. The drive strength of the GPIOs can be adjusted with the GEN_CONFIG parameter in the GPIO_PIN_CFG command.

By default the drive strength is set to minimum. The default configuration for the GPIOs and the state

during SDN is shown below in Table 4.4 (p. 20) .The state of the IO during shutdown is also shown in Table 4.4 (p. 20) .

Table 4.4. Energy Mode Description

Pin

GPIO0 GPIO1 GPIO2 GPIO3 nIRQ SDO SDI SCLK NSEL 0 0

SDN State

0 0 resistive VDD pull-up resistive VDD pull-up High Z High Z High Z

POR Default

POR CTS POR POR nIRQ SDO SDI SCLK NSEL

4.1.4 Modulation and Hardware Configuration Options

The EZRadioPRO supports different modulation options and can be used in various configurations to tailor the device to any specific application or legacy system for drop in replacement. The modulation and configuration options are set in API property, MODEM_MOD_TYPE. Refer to the API documentation for details on modem related properties.

4.1.4.1 Modulation Types

The EZRadioPRO supports five different modulation options: Gaussian frequency shift keying (GFSK), frequency-shift keying (FSK), four-level GFSK (4GFSK), four-level FSK (4FSK), and on-off keying (OOK). Minimum shift keying (MSK) can also be created by using GFSK with the appropriate modulation index (h = 0.5). GFSK is the recommended modulation type as it provides the best performance and cleanest modulation spectrum. The modulation type is set by the “MOD_TYPE[2:0]” field in the “MODEM_MOD_TYPE” API property. A continuous-wave (CW) carrier may also be selected for RF 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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evaluation purposes. The modulation source may also be selected to be a pseudo-random source for evaluation purposes.

4.1.4.2 Hardware Configuration Options

There are different receive demodulator options to optimize the performance and mutually-exclusive options for how the RX/TX data is transferred from the host MCU to the RF device.

4.1.4.2.1 Receive Demodulator Options

There are multiple demodulators integrated into the device to optimize the performance for different applications, modulation formats, and packet structures. The calculator built into Simplicity Studio will choose the optimal demodulator based on the input criteria.

4.1.4.2.2 Synchronous Demodulator

The synchronous demodulator's internal frequency error estimator acquires the frequency error based on a 101010 preamble structure. The bit clock recovery circuit locks to the incoming data stream within four transactions of a “10” or “01” bit stream. The synchronous demodulator gives optimal performance for 2- or 4-level (G)FSK modulation that has a modulation index less than 2.

4.1.4.2.3 Asynchronous Demodulator

The asynchronous demodulator should be used for OOK modulation and for (G)FSK modulation under one or more of the following conditions: • Modulation index ≥ 2 • Non-standard preamble (not 1010101... pattern) When the modulation index exceeds 2, the asynchronous demodulator has better sensitivity compared to the synchronous demodulator. An internal deglitch circuit provides a glitch-free data output and a data clock signal to simplify the interface to the host. There is no requirement to perform deglitching in the host MCU. The asynchronous demodulator will typically be utilized for legacy systems and will have many performance benefits over devices used in legacy designs. There is no requirement to perform deglitching on the data in the host MCU. Glitch-free data is output from EZRadioPRO devices, and a sample clock for the asynchronous data can also be supplied to the host MCU; so, oversampling or bit clock recovery is not required by the host MCU. There are multiple detector options in the asynchronous demodulator block, which will be selected based upon the options entered into the SS calculator. The asynchronous demodulator's internal frequency error estimator is able to acquire the frequency error based on any preamble structure.

4.1.4.2.4 RX/TX Data Interface With MCU

There are two different options for transferring the data from the RF device to the host MCU. FIFO mode uses the SPI interface to transfer the data, while direct mode transfers the data in real time over a GPIO pin.

4.1.4.2.4.1 FIFO Mode

In FIFO mode, the transmit and receive data is stored in integrated FIFO register memory. The TX FIFO is accessed by writing command 66h followed directly by the data/clk that the host wants to write into the TX FIFO. The RX FIFO is accessed by writing command 77h followed by the number of clock cycles of data the host would like to read out of the RX FIFO. The RX data will be clocked out onto the SDO pin.

In TX FIFO mode, the data bytes stored in FIFO memory are “packaged” together with other fields and bytes of information to construct the final transmit packet structure. These other potential fields include the Preamble, Sync word, and CRC checksum. In TX mode, the packet structure may be 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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highly customized by enabling or disabling individual fields; for example, it is possible to disable both the Preamble and Sync Word fields and to load the entire packet structure into FIFO memory. For further information on the configuration of the FIFOs for a specific application or packet size, see

Section 4.1.6 (p. 33) . In RX mode, the Packet Handler must be enabled to allow storage of

received data bytes into RX FIFO memory. The Packet Handler is required to detect the Sync Word, and proper detection of the Sync Word is required to determine the start of the Payload. All bytes after the Sync Word are stored in RX FIFO memory except the CRC checksum and (optionally) the variable packet length byte(s). When the FIFO is being used in RX mode, all of the received data may still be observed directly (in realtime) by properly programming a GPIO pin as the RXDATA output pin; this can be quite useful during application development. When in FIFO mode, the chip will automatically exit the TX or RX State when either the PACKET_SENT or PACKET_RX interrupt occurs.

The chip will return to the state programmed in the argument of the “START TX” or “START RX” API command, TXCOMPLETE_STATE[3:0] or RXVALID_STATE[3:0]. For example, the chip may be placed into READY mode after a TX packet by sending the “START TX” command and by writing 30h to the TXCOMPLETE_STATE[3:0] argument. The chip will transmit all of the contents of the FIFO, and the PACKET_SENT interrupt will occur. When this event occurs, the chip will return to the READY state as defined by TXCOMPLETE_STATE[3:0] = 30h.

4.1.4.2.4.2 FIFO Direct Mode (Infinite Receive)

In some applications, there is a need to receive extremely long packets (greater than 40 kB) while relying on preamble and sync word detection from the on-chip packet handler. In these cases, the packet length is unknown, and the device will load the bits after the sync word into the RX FIFO forever. Other features, such as Data Whitening, CRC, Manchester, etc., are supported in this mode, but CRC calculation is not because the end of packet is unknown to the device. The RX data and clock are also available on GPIO pins. The host MCU will need to reset the packet handler by issuing a START_RX to begin searching for a new packet.

4.1.4.2.4.3 Automatic TX Packet Repeat

In TX mode, there is an option to send the FIFO contents repeatedly with a user-defined number of times to repeat. This is limited to the FIFO size, and the entire contents of the packet including preamble and sync word need to be loaded into the TX FIFO. This is selectable via the START_TX API, and packets will be sent without any gaps between them.

4.1.4.2.4.4 Direct Mode

For legacy systems that perform packet handling within the host MCU or other baseband chip, it may not be desirable to use the FIFO. For this scenario, a Direct mode is provided, which bypasses the FIFOs entirely. In TX Direct mode, the TX modulation data is applied to an input pin of the chip and processed in “real time” (i.e., not stored in a register for transmission at a later time). Any of the GPIOs may be configured for use as the TX Data input function. Furthermore, an additional pin may be required for a TX Clock output function if GFSK modulation is desired (only the TX Data input pin is required for FSK or OOK). To achieve direct mode, the desired GPIO pin must be configured as a digital input by setting the GPIO_PIN_CFG API command = enumeration 0x04 in addition to setting the MODEM_MOD_TYPE API property to source the TXDATA stream from that same GPIO pin. For GFSK, “TX_DIRECT_MODE_TYPE” must be set to synchronous. For 2FSK or OOK, the type can be set to asynchronous or synchronous. The MOD_SOURCE[1:0] field within the MODEM_MOD_TYPE property should be set = 0x01h for all Direct mode configurations. In RX Direct mode, the RX Data and RX Clock can be programmed for direct (real-time) output to GPIO pins. The microcontroller may then process the RX data without using the FIFO or packet handler functions of the RFIC.

4.1.4.3 Preamble Length 4.1.4.3.1 Digital Signal Arrival Detector (DSA)

Traditional preamble detection requires 20 bits to detect preamble. This device introduces a new approach to signal detection that can detect a preamble pattern in as little as one byte. If AFC is enabled, 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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a preamble length of two bytes is sufficient to reliably detect signal arrival and settle a one-shot AFC. The impact of this is significant for low-power solutions as it reduces the amount of time the receiver has to

stay active to detect the preamble. This feature is used with Preamble Sense Mode (Section 4.1.8.6 (p.

37) ) and the latest Wireless M-Bus N modes as well as with features, such as frequency hopping,

which may use signal arrival as a condition to hop. The traditional preamble detector is also available to maintain backward compatibility. Note that the DSA is using the RSSI jump detector. When used for collision detection, the RSSI jump detector may need to be reconfigured after preamble detection. Refer to the API documentation for details on how to configure the device to use the signal arrival detector.

4.1.4.3.2 Traditional Preamble Detection

Optimal performance of the chip is obtained by qualifying reception of a valid Preamble pattern prior to continuing with reception of the remainder of the packet (e.g., Sync Word and Payload). Reception of the Preamble is considered valid when a minimum number of consecutive bits of 101010... pattern have been received; the required threshold for preamble detection is specified by the RX_THRESH[6:0] field in the PREAMBLE_CONFIG_STD_1 property. The appropriate value of the detection threshold depends upon the system application and typically trades off speed of acquisition against the probability of false detection. If the detection threshold is set too low, the chip may readily detect the short pattern within noise; the chip then proceeds to attempt to detect the remainder of the non-existent packet, with the result that the arrival of an actual valid packet may be missed. If the detection threshold is set too high, the required number of transmitted Preamble bits must be increased accordingly, leading to longer packet lengths and shorter battery life. A preamble detection threshold value of 20 bits is suitable for most applications. The total length of the transmitted Preamble field must be at least equal to the receive preamble detection threshold, plus an additional number of bits to allow for acquisition of bit timing and settling of the AFC algorithm. The recommended preamble detection thresholds and preamble lengths

for a variety of operational modes are listed in Table 4.5 (p. 23) .

Configuration of the preamble detection threshold in the RX_THRESH[6:0] field is only required for reception of a standard Preamble pattern (i.e., 101010... pattern). Reception of a repetitive but non-standard Preamble pattern is also supported in the chip but is configured through the PREAMBLE_CONFIG_NSTD and PREAMBLE_PATTERN properties.

Table 4.5. Recommended Preamble Length

Mode AFC Antenna Diversity Preamble Type

(G)FSK (G)FSK (G)FSK (G)FSK (G)FSK (G)FSK 4(G)FSK 4(G)FSK 4(G)FSK OOK OOK OOK Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Disabled Enabled Disabled Disabled Disabled Enabled Enabled Disabled Disabled Disabled Disabled Standard Standard Non-standard Non-standard Standard Standard Standard Standard Non-standard Standard Non-standard

Recommended Preamble Length Recommended Preamble Detection Threshold

4 Bytes 5 Bytes 2 Bytes Not Supported 7 Bytes 8 Bytes 40 symbols 48 symbols Not Supported 4 Bytes 2 Bytes Not Supported 20 bits 20 bits 0 bits 24 bits 24 bits 16 symbols 16 symbols 20 bits 0 bits

Note

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• The recommended preamble length and preamble detection thresholds listed above are to achieve 0% PER. They may be shortened when occasional packet errors are tolerable.

• All recommended preamble lengths and detection thresholds include AGC and BCR settling times.

• “Standard” preamble type should be set for an alternating data sequence at the max data rate (…10101010…).

• “Non-standard” preamble type can be set for any preamble type including …10101010...

• When preamble detection threshold = 0, sync word needs to be 3 Bytes to avoid false syncs. When only a 2 Byte sync word is available the sync word detection can be extended by including the last preamble Byte into the RX sync word setting.

4.1.5 Internal Functional Blocks

The following sections provide an overview to the key internal blocks and features.

4.1.5.1 RX Chain

The internal low-noise amplifier (LNA) is designed to be a wide-band LNA that can be matched with three or four external discrete components to cover any common range of frequencies in the sub-GHz band. The LNA has extremely low noise to suppress the noise of the following stages and achieve optimal sensitivity; so, no external gain or front-end modules are necessary. The LNA has gain control, which is controlled by the internal automatic gain control (AGC) algorithm. The LNA is followed by an I-Q mixer, filter, programmable gain amplifier (PGA), and ADC. The I-Q mixers downconvert the signal to an intermediate frequency. The PGA then boosts the gain to be within dynamic range of the ADC. The ADC rejects out-of-band blockers and converts the signal to the digital domain where filtering, demodulation, and processing is performed. Peak detectors are integrated at the output of the LNA and PGA for use in the AGC algorithm.

The RX and TX pins may be directly tied externally for output powers less than +17 dBm in the higher frequency bands and can support +20 dBm in the lower bands, such as 169MHz. This reduces BOM cost by saving the expense of a switch for single antenna solutions. See the direct-tie reference designs on the Silicon Labs web site for more details.

4.1.5.1.1 RX Chain Architecture

It is possible to operate the RX chain in different architecture configurations: fixed-IF, zero-IF, and scaled-IF. There are trade-offs between the architectures in terms of sensitivity, selectivity, and image rejection. Fixed-IF is the default configuration and is recommended for most applications. With 35 dB native image rejection and autonomous image calibration to achieve 55 dB, the fixed-IF solution gives the best performance for most applications. Fixed-IF obtains the best sensitivity, but it has the effect of degraded selectivity at the image frequency. An autonomous image rejection calibration is included in

EZRadioPRO devices and described in more detail in Section 4.1.5.2.3 (p. 26) . For scaled-IF and

zero-IF, the sensitivity is degraded for data rates less than 100 kbps or bandwidths less than 200 kHz.

The reduction in sensitivity is caused by increased flicker noise as dc is approached. The benefit of zero-IF is that there is no image frequency; so, there is no degradation in the selectivity curve, but it has the worst sensitivity. Scaled-IF is a trade-off between fixed-IF and zero-IF. In the scaled-IF architecture, the image frequency is placed or hidden in the adjacent channel where it only slightly degrades the typical adjacent channel selectivity. The scaled-IF approach has better sensitivity than zero-IF but still some degradation in selectivity due to the image. In scaled-IF mode, the image frequency is directly

proportional to the channel bandwidth selected. Figure 4.8 (p. 19) demonstrates the trade-off in

sensitivity between the different architecture options.

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Figure 4.9. RX Architecture vs. Data Rate ...the world's most energy friendly wireless MCUs

4.1.5.2 RX Modem

Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed in the digital domain, which allows for flexibility in optimizing the device for particular applications. The digital modem performs the following functions: • Channel selection filter • TX modulation • RX demodulation • Automatic Gain Control (AGC) • Preamble detection • Invalid preamble detection • Radio signal strength indicator (RSSI) • Automatic frequency compensation (AFC) • Image Rejection Calibration • Packet handling • Cyclic redundancy check (CRC) The digital channel filter and demodulator are optimized for ultra-low-power consumption and are highly configurable. Supported modulation types are GFSK, FSK, 4GFSK, 4FSK, GMSK, and OOK. The channel filter can be configured to support bandwidths ranging from 850 kHz down to 1.1 kHz. A large variety of data rates are supported ranging from 100 bps up to 1 Mbps. The configurable preamble detector is used with the synchronous demodulator to improve the reliability of the sync-word detection.

Preamble detection can be skipped using only sync detection, which is a valuable feature in some applications. The received signal strength indicator (RSSI) provides a measure of the signal strength received on the tuned channel. The resolution of the RSSI is 0.5 dB. This high-resolution RSSI enables accurate channel power measurements for clear channel assessment (CCA), carrier sense (CS), and listen before talk (LBT) functionality. A comprehensive programmable packet handler is integrated to create a variety of communication topologies ranging from peer-to-peer networks to mesh networks.

The extensive programmability of the packet header allows for advanced packet filtering, which, in turn enables a mix of broadcast, group, and point-to-point communication. A wireless communication channel can be corrupted by noise and interference, so it is important to know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the presence of erroneous bits in each packet. A CRC is computed and appended at the end of each transmitted packet and verified 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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by the receiver to confirm that no errors have occurred. The packet handler and CRC can significantly reduce the load on the system microcontroller allowing for a simpler and cheaper microcontroller. The digital modem includes the TX modulator, which converts the TX data bits into the corresponding stream of digital modulation values to be summed with the fractional input to the sigma-delta modulator. This modulation approach results in highly accurate resolution of the frequency deviation. A Gaussian filter is implemented to support GFSK and 4GFSK, considerably reducing the energy in adjacent channels.

The default bandwidth-time product (BT) is 0.5 for all programmed data rates, but it may be adjusted to other values.

4.1.5.2.1 Automatic Gain Control (AGC)

The AGC algorithm is implemented digitally using an advanced control loop optimized for fast response time. The AGC occurs within a single bit or in less than 2 µs. Peak detectors at the output of the LNA and PGA allow for optimal adjustment of the LNA gain and PGA gain to optimize IM3, selectivity, and sensitivity performance.

4.1.5.2.2 Auto Frequency Correction (AFC)

Frequency mistuning caused by crystal inaccuracies can be compensated for by enabling the digital automatic frequency control (AFC) in receive mode. There are two types of integrated frequency compensation: modem frequency compensation and AFC by adjusting the PLL frequency. With AFC disabled, the modem compensation can correct for frequency offsets up to ±0.25 times the IF bandwidth.

When the AFC is enabled, the received signal is centered in the passband of the IF filter, providing optimal sensitivity and selectivity over a wider range of frequency offsets up to ±0.35 times the IF bandwidth. When AFC is enabled, the preamble length needs to be long enough to settle the AFC. As

shown in Table 4.5 (p. 23) , an additional byte of preamble is typically required to settle the AFC.

4.1.5.2.3 Image Rejection and Calibration

Since the receiver utilizes a low-IF architecture, the selectivity will be affected by the image frequency.

The IF frequency is 468.75 kHz (Fxtal/64), and the image frequency will be at 937.5 kHz (2 x Fxtal/64) below the RF frequency. The native image rejection of the EZRadioPRO family is 40 dB. Image rejection calibration is available in the EZRadioPRO to improve the image rejection to more than 55 dB. The calibration is initiated with the IRCAL API command. The calibration uses an internal signal source, so no external signal generator is required. The initial calibration takes 250 ms, and periodic re-calibration takes 100 ms. Recalibration should be initiated when the temperature has changed more than 30 °C.

4.1.5.2.4 Received Signal Strength Indicator

The received signal strength indicator (RSSI) is an estimate of the signal strength in the channel to which the receiver is tuned. The RSSI measurement is done after the channel filter, so it is only a measurement of the in-band signal power (desired or undesired). There are two methods for reading the RSSI value and several different options for configuring the returned RSSI value. The fastest method for reading the RSSI is to configure one of the four fast response registers (FRR) to return a latched RSSI value. The latched RSSI value is measured once per packet and is latched at a configurable amount of time after RX mode is entered. The fast response registers can be read in 16 SPI clock cycles with no requirement to wait for CTS. The RSSI value may also be read out of the GET_MODEM_STATUS command. In this command, both the current RSSI and the latched RSSI are available. The current RSSI value represents the signal strength at the instant in time the GET_MODEM_STATUS command is processed and may be read multiple times per packet. Reading the RSSI in the GET_MODEM_STATUS command takes longer than reading the RSSI out of the fast response register. After the initial command, it takes 33 µs for CTS to be set and then the four or five bytes of SPI clock cycles to read out the respective current or latched RSSI values.

The RSSI configuration options are set in the MODEM_RSSI_CONTROL API property. The latched RSSI value may be latched and stored based on the following events: preamble detection, sync detection, or a configurable number of bit times measured after the start of RX mode (minimum of 4 bit times). The requirement for a minimum of four bit times is determined by the processing delay and 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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settling through the modem and digital channel filter. In MODEM_RSSI_CONTROL, the RSSI may be defined to update every bit period or to be averaged and updated every four bit periods. If RSSI averaging over four bits is enabled, the latched RSSI value will be delayed to a minimum of seven bits after the start of RX mode to allow for the averaging. The latched RSSI values are cleared when entering RX mode so they may be read after the packet is received or after dropping back to standby mode. If the RSSI value has been cleared by the start of RX but not yet latched, a value of 0 will be returned if it is attempted to be read.

The RSSI value read by the API may be translated into dBm by the following linear equation: RF_Input_Level_dBm = (RSSI_value / 2) - MODEM_RSSI_COMP - 70 The MODEM_RSSI_COMP property provides for fine adjustment of the relationship between the actual RF input level (in dBm) and the returned RSSI value. That is, adjustment of this property allows the user to shift the RSSI vs RF Input Power curve up and down. This may be desirable to compensate for differences in front-end insertion loss between multiple designs (e.g., due to the presence of a SAW preselection filter, or an RF switch). A value of MODEM_RSSI_COMP = 0x40 = 64d is appropriate for most applications.

Clear channel assessment (CCA) or RSSI threshold detection is also available. An RSSI threshold may be set in the MODEM_RSSI_THRESH API property. If the Current RSSI value is above this threshold, an interrupt or GPIO may notify the host. Both the latched version and asynchronous version of this threshold are available on any of the GPIOs. Automatic fast hopping based on RSSI is available. See

Section 4.1.5.3.1.2 (p. 28) .

4.1.5.2.5 RSSI Jump Indicator (Collision Detection)

The chip is capable of detecting a jump in RSSI in either direction (i.e., either a signal increase or a signal decrease). Both polarities of jump detection may be enabled simultaneously, resulting in detection of a Jump-Up or Jump-Down event. This may be used to detect whether a secondary interfering signal (desired or undesired) has “collided” with reception of the current packet. An interrupt flag or GPIO pin may be configured to notify the host MCU of the Jump event. The change in RSSI level required to trigger the Jump event is programmable through the MODEM_RSSI_JUMP_THRESH API property.

The chip may be configured to reset the RX state machine upon detection of an RSSI Jump, and thus to automatically begin reacquisition of the packet. The chip may also be configured to generate an interrupt.

This functionality is intended to detect an abrupt change in RSSI level and to not respond to a slow, gradual change in RSSI level. This is accomplished by comparing the difference in RSSI level over a programmable time period. In this fashion, the chip effectively evaluates the slope of the change in RSSI level.

The arrival of a desired packet (i.e., the transition from receiving noise to receiving a valid signal) will likely be detected as an RSSI Jump event. For this reason, it is recommended to enable this feature in mid-packet (i.e., after signal qualification, such as PREAMBLE_VALID.) Refer to the API documentation for configuration options.

4.1.5.3 Synthesizer

An integrated Sigma Delta ( Σ∆ ) Fractional-N PLL synthesizer capable of operating over the bands from 142-175, 283-350, 350-525, and 850-1050 MHz. Using a Σ∆ synthesizer has many advantages; it provides flexibility in choosing data rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the loop in the digital domain through the fractional divider, which results in very precise accuracy and control over the transmit deviation. The frequency resolution in the 850-1050 MHz band is 28.6 Hz with finer resolution in the other bands. The nominal reference frequency to the PLL is 30 MHz, but any XTAL frequency from 25 to 32 MHz may be used. The modem configuration calculator in SS will automatically account for the XTAL frequency being used. The PLL utilizes a differential LC VCO with integrated on-chip inductors. The output of the VCO is followed by a configurable divider, which will divide the signal down to the desired output frequency band.

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4.1.5.3.1 Synthesizer Frequency Control

The frequency is set by changing the integer and fractional settings to the synthesizer. The SS calculator will automatically provide these settings, but the synthesizer equation is shown below for convenience.

The APIs for setting the frequency are FREQ_CONTROL_INTE, FREQ_CONTROL_FRAC2, FREQ_CONTROL_FRAC1, and FREQ_CONTROL_FRAC0.

RF Channel Equation

(fc_inte+fc_frac/2 19 )*(2*freq_xo/outdiv) (4.1)

Note

The fc_frac/2 19 value in the above formula has to be a number between 1 and 2.

Table 4.6. Output Divider (Outdiv) Values for the EZRadioPRO

Outdiv

24 12 10 8 4

Lower (MHz)

142 284 350 420 850

Upper (MHz)

175 350 420 525 1050

4.1.5.3.1.1 EZ Frequency Programming

In applications that utilize multiple frequencies or channels, it may not be desirable to write four API registers each time a frequency change is required. EZ frequency programming is provided so that only a single register write (channel number) is required to change frequency. A base frequency is first set by first programming the integer and fractional components of the synthesizer. This base frequency will correspond to channel 0. Next, a channel step size is programmed into the FREQ_CONTROL_CHANNEL_STEP_SIZE_1 and FREQ_CONTROL_CHANNEL_STEP_SIZE_0 API registers. The resulting frequency will be:

RF Frequency Equation

RF Frequency = Base Frequency + (Channel * Stepsize) (4.2) The second argument of the START_RX or START_TX is CHANNEL, which sets the channel number for EZ frequency programming. For example, if the channel step size is set to 1 MHz, the base frequency is set to 900 MHz with the FREQ_CONTROL_INTE and FREQ_CONTROL_FRAC API properties, and a CHANNEL number of 5 is programmed during the START_TX command, the resulting frequency will be 905 MHz. If no CHANNEL argument is written as part of the START_RX/TX command, it will default to the previously-programmed value. The initial value of CHANNEL is 0; so, if no CHANNEL value is written, it will result in the programmed base frequency.

4.1.5.3.1.2 Automatic RX Hopping and Hop Table

The transceiver supports an automatic RX hopping feature that can be fully configured through the API.

This functionality is useful in applications where it is desired to look for packets but to hop to the next channel if a packet is not found. The sequence of channel numbers that are visited are specified by entries in a hop table. If this feature is enabled, the device will automatically start hopping through the channels listed in the hop table as soon as the chip enters RX mode.

The transceiver supports an automatic RX hopping feature that can be fully configured through the API.

This functionality is useful in applications where it is desired to look for packets but to hop to the next channel if a packet is not found. The sequence of channel numbers that are visited are specified by entries in a hop table. If this feature is enabled, the device will automatically start hopping through the channels listed in the hop table as soon as the chip enters RX mode.

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The hop table can hold up to 64 entries and is maintained in firmware inside the RFIC. Each entry is a channel number, allowing construction of a frequency plan of up to 64 channels. The number of entries in the table is set by RX HOP TABLE_SIZE API. The specified channels correspond to the EZ frequency programming method for programming the frequency. The receiver starts at the base channel and hops in sequence from the top of the hop table to the bottom. The table will wrap around to the base channel once it reaches the end of the table. An entry of 0xFF in the table indicates that the entry should be skipped. The device will hop to the next entry in the table that contains a non-0xFF value.

There are three conditions that can be used to determine whether to continue hopping or to stay on a particular channel. These conditions are as follows: • RSSI threshold • Preamble timeout (invalid preamble pattern) • Sync word timeout (invalid or no sync word detected after preamble) These conditions can be used individually, or they can be enabled all together by configuring the RX_HOP_CONTROL API. However, the firmware will make a decision on whether or not to hop based on the first condition that is met.

The RSSI that is monitored is the current RSSI value. This is compared to the threshold value set in the MODEM_RSSI_THRESH API property, and, if it is above the threshold value, it will stay on the channel.

If the RSSI is below the threshold, it will continue hopping. There is no averaging of RSSI done during the automatic hopping from channel to channel. Since the preamble timeout and the sync word timeout are features that require packet handling, the RSSI threshold is the only condition that can be used if the user is in “direct” or “RAW” mode where packet handling features are not used.

The RSSI threshold value may be converted to an approximate equivalent RF input power level through

the equation shown in Section 4.1.5.2.4 (p. 26) . However, performance should be verified on the

bench to optimize the threshold setting for a given application.

The time spent in receive mode will be determined by the configuration of the hop conditions. Manual RX hopping will have the fastest turn-around time but will require more overhead and management by the host MCU.

The following are example steps for using Auto Hop: • Set the base frequency (inte + frac) and channel step size.

• Define the number of entries in the hop table (RX_HOP_TABLE_SIZE).

• Write the channels to the hop table (RX_HOP_TABLE_ENTRY_n) • Configure the hop condition and enable auto hopping- RSSI, preamble, or sync (RX_HOP_CONTROL).

• Set preamble and sync parameters if enabled.

• Program the RSSI threshold property in the modem using “MODEM_RSSI_THRESH”.

• Set the preamble threshold using “PREAMBLE_CONFIG_STD_1”.

• Program the preamble timeout property using “PREAMBLE_CONFIG_STD_2”.

• Set the sync detection parameters if enabled.

• If needed, use “GPIO_PIN_CFG” to configure a GPIO to toggle on hop and hop table wrap.

• Use the “START_RX” API with channel number set to the first valid entry in the hop table (i.e., the first non 0xFF entry).

• Device should now be in auto hop mode.

4.1.5.3.1.3 Manual RX Hopping

The RX_HOP command provides the fastest method for hopping from RX to RX but it requires more overhead and management by the host MCU. The timing is faster with this method than Start_RX or RX hopping because one of the calculations required for the synthesizer calibrations is offloaded to 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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the host and must be calculated/stored by the host, VCO_CNT0. For VCO_CNT values, download the EZRadioPRO RX_HOP PLL calculator spreadsheet from the EZRadioPRO product website.

4.1.5.4 Transmitter (TX)

The EZRadioPRO contains an integrated +20 dBm transmitter or power amplifier that is capable of transmitting from -20 to +20 dBm. The resolution of the programmable steps in output power is less than 0.25 dB when operated within 6 dB of the maximum power setting; the resolution of the steps in output power becomes coarser and more non-linear as the output power is reduced towards the minimum end of its control range. The EZRadioPRO PA is designed to provide the highest efficiency and lowest current consumption possible. The EZRadioPRO is designed to supply +13 dBm output power for less than 20 mA for applications that require operation from a single coin cell battery. The EZRadioPRO can operate with Class-E matching and output up to +13 dBm Tx power at a supply voltage of VDD = 3.3 V. All PA options are single-ended to allow for easy antenna matching and low BOM cost. Automatic ramp-up and ramp-down is automatically performed to reduce unwanted spectral spreading. Refer to “AN627: Si4460/61 Low-Power PA Matching” and “AN648: PA Matching” for details on TX matching options.

The chip’s TXRAMP pin is disabled by default to save current in cases where the on-chip PA provides sufficient output power to drive the antenna. In cases where on-chip PA will drive the external PA, and the external PA needs a ramping signal, TXRAMP is the signal to use. To enable TXRAMP, set the API Property PA_MODE[7] = 1. TXRAMP will start to ramp up, and ramp down at the SAME time as the internal on-chip PA ramps up/down.

However, the time constant of the TXRAMP signal for the external PA is programmed independently of the ramp time constant for the on-chip PA. The ramp time constant for TXRAMP is programmed by the TC[3:0] field in the PA_RAMP_EX API property and provides the following approximate ramp times as a function of TC[3:0] value.

Table 4.7. Ramp Times as a Function of TC[3:0] Value

1 2

TC

0 5 6 3 4 7 8 9 10 11 12 13 14 15 2.22

2.50

2.86

3.33

4.00

5.00

6.67

10.00

20.00

Ramp Time (µs)

1.25

1.33

1.43

1.54

1.67

1.82

2.00

The ramping profile is close to a linear ramping profile with smoothed out corner when approaching Vhi and Vlo. The TXRAMP pin can source up to 1 mA without voltage drooping. The TXRAMP pin’s sinking capability is equivalent to a 10 kOhm pull-down resistor.

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Vhi = 3 V when Vdd > 3.3 V. When Vdd < 3.3 V, the Vhi will be closely following the Vdd, and ramping time will be smaller also.

Vlo = 0 V when NO current needed to be sunk into TXRAMP pin. If 10uA need to be sunk into the chip, Vlo will be 10 µA x 10k = 100 mV.

Table 4.8. Command

Number

0x2200 0x2201 0x2202

Command

PA_MODE PA_PWR_LVL PA_BIAS_CLKDUTY 0x2203 PA_TC

Summary

Sets PA type.

Adjust TX power in fine steps.

Adjust TX power in coarse steps and optimizes for different match configurations.

Changes the ramp up/down time of the PA.

4.1.5.4.1 EZRadioPRO: +20 dBm PA

The +20 dBm configuration utilizes a class-E matching configuration for all frequency bands except 169 MHz where it uses a Square Wave match. Typical performance for the 915 MHz band for output power

steps, voltage, and temperature are shown in Figure 4.10 (p. 31) . The output power is changed in

128 steps through PA_PWR_LVL API. For detailed matching values, BOM, and performance at other frequencies, refer to “AN648: PA Matching”.

Figure 4.10. +20 dBm TX Power vs. PA_PWR_LVL

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Figure 4.11. +20 dBm TX Power vs. VDD ...the world's most energy friendly wireless MCUs Figure 4.12. +20 dBm TX Power vs. Temp

4.1.5.5 Crystal Oscillator

The EZRadioPRO includes an integrated crystal oscillator with a fast start-up time of less than 250 µs.

The design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components. By default, all that is required off-chip is the crystal. The default crystal is 30 MHz, but the circuit is designed to handle any XTAL from 25 to 32 MHz. If a crystal different than 30 MHz is used, the POWER_UP API boot command must be modified. The SS calculator crystal frequency field must also be changed to reflect the frequency being used. The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal load capacitance is programmed through the GLOBAL_XO_TUNE API property. The total internal capacitance is 11 pF and is adjustable in 127 steps (70 fF/step). The crystal frequency adjustment can be used to compensate for crystal production

tolerances. The frequency offset characteristics of the capacitor bank are demonstrated in Figure 4.13 (p.

33) .

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...the world's most energy friendly wireless MCUs Figure 4.13. Capacitor Bank Frequency Offset Characteristics

Utilizing the on-chip temperature sensor and suitable control software, the temperature dependency of the crystal can be canceled.

A TCXO or external signal source can easily be used in place of a conventional XTAL and should be connected to the XIN pin. The incoming clock signal is recommended to have a peak-to-peak swing in the range of 600 mV to 1.4 V and ac-coupled to the XIN pin. If the peak-to-peak swing of the TCXO exceeds 1.4 V peak-to-peak, then dc coupling to the XIN pin should be used. The maximum allowed swing on XIN is 1.8 V peak-to-peak.

The XO capacitor bank should be set to 0 whenever an external drive is used on the XIN pin. In addition, the POWER_UP command should be invoked with the TCXO option whenever external drive is used.

4.1.6 Data Handling and Packet Handler

4.1.6.1 RX and TX FIFOs

Two 64-byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 4.14 (p.

34) . For dedicated TX or RX, the FIFO size is up to 129 bytes. Writing to command Register 66h

loads data into the TX FIFO, and reading from command Register 77h reads data from the RX FIFO.

The TX FIFO has a threshold for when the FIFO is almost empty, which is set by the “TX_FIFO_EMPTY” property. An interrupt event occurs when the data in the TX FIFO reaches the almost empty threshold. If more data is not loaded into the FIFO, the chip automatically exits the TX state after the PACKET_SENT interrupt occurs. The RX FIFO has one programmable threshold, which is programmed by setting the “RX_FIFO_FULL” property. When the incoming RX data crosses the Almost Full Threshold, an interrupt will be generated to the microcontroller via the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO. The RX Almost Full Threshold indication implies that the host can read at least the threshold number of bytes from the RX FIFO at that time. Both the TX and RX FIFOs may be cleared or reset with the “FIFO_RESET” command.

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Figure 4.14. TX and RX FIFOs

TX FIFO

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RX FIFO

RX FIFO Alm ost Full Threshold TX FIFO Alm ost Em pt y Threshold

4.1.6.2 Packet Handler

When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both.

The usual fields for network communication, such as preamble, synchronization word, headers, packet length, and CRC, can be configured to be automatically added to the data payload. The fields needed for packet generation normally change infrequently and can therefore be stored in registers. Automatically adding these fields to the data payload in TX mode and automatically checking them in RX mode greatly reduces the amount of communication between the microcontroller and EZRadioPRO. It also greatly reduces the required computational power of the microcontroller. The general packet structure is shown

in Figure 4.15 (p. 34) . Any or all of the fields can be enabled and checked by the internal packet

handler.

Figure 4.15. Packet Handler Structure

The fields are highly programmable and can be used to check any kind of pattern in a packet structure.

The general functions of the packet handler include the following: • Detection/validation of Preamble quality in RX mode (PREAMBLE_VALID signal) • Detection of Sync word in RX mode (SYNC_OK signal) • Detection of valid packets in RX mode (PKT_VALID signal) • Detection of CRC errors in RX mode (CRC_ERR signal) • Data de-whitening and/or Manchester decoding (if enabled) in RX mode • Match/Header checking in RX mode • Storage of Data Field bytes into FIFO memory in RX mode • Construction of Preamble field in TX mode • Construction of Sync field in TX mode 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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• Construction of Data Field from FIFO memory in TX mode • Construction of CRC field (if enabled) in TX mode • Data whitening and/or Manchester encoding (if enabled) in TX mode For details on how to configure the packet handler, see “AN626: Packet Handler Operation for Si446x RFICs”.

4.1.7 RX Modem Configuration

The EZRadioPRO can easily be configured for different data rate, deviation, frequency, etc. by using the Radio Configuration Application (RCA) GUI which is part of Simplicity Studio (SS).

4.1.8 Auxiliary Blocks

4.1.8.1 Wake-up Timer and 32 kHz Clock Source

The chip contains an integrated wake-up timer that can be used to periodically wake the chip from sleep mode. The wake-up timer runs from either the internal 32 kHz RC Oscillator, or from an external 32 kHz XTAL.

The wake-up timer can be configured to run when in sleep mode. If WUT_EN = 1 in the GLOBAL_WUT_CONFIG property, prior to entering sleep mode, the wake-up timer will count for a time specified defined by the GLOBAL_WUT_R and GLOBAL_WUT_M properties. At the expiration of this period, an interrupt will be generated on the nIRQ pin if this interrupt is enabled in the INT_CTL_CHIP_ENABLE property. The microcontroller will then need to verify the interrupt by reading the chip interrupt status either via GET_INT_STATUS or a fast response register. The formula for calculating the Wake-Up Period is as follows:

Wake-up Time Equation

WUT = WUT_M *(4*2 WUT_R /32768 (4.3) The RC oscillator frequency will change with temperature; so, a periodic recalibration is required. The RC oscillator is automatically calibrated during the POWER_UP command and exits from the Shutdown state. To enable the recalibration feature, CAL_EN must be set in the GLOBAL_WUT_CONFIG property, and the desired calibration period should be selected via WUT_CAL_PERIOD[2:0] in the same API property. During the calibration, the 32 kHz RC oscillator frequency is compared to the 30 MHz XTAL and then adjusted accordingly. The calibration needs to start the 30 MHz XTAL, which increases the average current consumption; so, a longer CAL_PERIOD results in a lower average current consumption. The 32 kHz XTAL accuracy is comprised of both the XTAL parameters and the internal circuit. The XTAL accuracy can be defined as the XTAL initial error + XTAL aging + XTAL temperature drift + detuning from the internal oscillator circuit. The error caused by the internal circuit is typically less than 10 ppm.

Refer to API documentation for details on WUT related commands and properties.

4.1.8.2 Low Duty Cycle Mode (Auto RX Wake-Up)

The low duty cycle (LDC) mode is implemented to automatically wake-up the receiver to check if a valid signal is available or to enable the transmitter to send a packet. It allows low average current polling operation by the EZRadioPRO for which the wake-up timer (WUT) is used. RX and TX LDC operation must be set via the GLOBAL_WUT_CONFIG property when setting up the WUT. The LDC wake-up period is determined by the following formula:

LDC Wake-up Time Equation

LDC = WUT_LDC *(4*2 WUT_R /32768 (4.4) where the WUT_LDC parameter can be set by the GLOBAL_WUT_LDC property. The WUT period must be set in conjunction with the LDC mode duration; for the relevant API properties, see the wake up timer (WUT) section.

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Figure 4.16. RX and TX LDC Sequences ...the world's most energy friendly wireless MCUs

The basic operation of RX LDC mode is shown in Figure 4.17 (p. 36) . The receiver periodically wakes

itself up to work on RX_STATE during LDC mode duration. If a valid preamble is not detected, a receive error is detected, or an entire packet is not received, the receiver returns to the WUT state (i.e., ready or sleep) at the end of LDC mode duration and remains in that mode until the beginning of the next wake up period. If a valid preamble or sync word is detected, the receiver delays the LDC mode duration to receive the entire packet. If a packet is not received during two LDC mode durations, the receiver returns to the WUT state at the last LDC mode duration until the beginning of the next wake-up period.

Figure 4.17. Low Duty Cycle Mode for RX

In TX LDC mode, the transmitter periodically wakes itself up to transmit a packet that is in the data buffer. If a packet has been transmitted, nIRQ goes low if the option is set in the INT_CTL_ENABLE property. After transmitting, the transmitter immediately returns to the WUT state and stays there until the next wake-up time expires.

4.1.8.3 Temperature, Battery Voltage, and Auxiliary ADC

The EZRadioPRO family contains an integrated auxiliary ADC for measuring internal battery voltage, an internal temperature sensor, or an external component over a GPIO. The ADC utilizes a SAR architecture and achieves 11-bit resolution. The Effective Number of Bits (ENOB) is 9 bits. When measuring external components, the input voltage range is 1 V, and the conversion rate is between 300 Hz to 2.44 kHz. The ADC value is read by first sending the GET_ADC_READING command and enabling the inputs that are desired to be read: GPIO, battery, or temp. The temperature sensor accuracy at 25 °C is typically ±2 °C. Refer to API documentation for details on the command and reply stream.

4.1.8.4 Low Battery Detector

The low battery detector (LBD) is enabled and utilized as part of the wake-up-timer (WUT). The LBD function is not available unless the WUT is enabled, but the host MCU can manually check the battery voltage anytime with the auxiliary ADC. The LBD function is enabled in the GLOBAL_WUT_CONFIG API property. The battery voltage will be compared against the threshold each time the WUT expires.

The threshold for the LBD function is set in GLOBAL_LOW_BATT_THRESH. The threshold steps are in increments of 50 mV, ranging from a minimum of 1.5 V up to 3.05 V. The accuracy of the LBD is ±3%.

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The LBD notification can be configured as an interrupt on the nIRQ pin or enabled as a direct function on one of the GPIOs.

4.1.8.5 Antenna Diversity

To mitigate the problem of frequency-selective fading due to multipath propagation, some transceiver systems use a scheme known as antenna diversity. In this scheme, two antennas are used. Each time the transceiver enters RX mode the receive signal strength from each antenna is evaluated. This evaluation process takes place during the preamble portion of the packet. The antenna with the strongest received signal is then used for the remainder of that RX packet. The same antenna will also be used for the next corresponding TX packet. This chip fully supports antenna diversity with an integrated antenna diversity control algorithm. The required signals needed to control an external SPDT RF switch (such as a PIN diode or GaAs switch) are available on the GPIOx pins. The operation of these GPIO signals is programmable to allow for different antenna diversity architectures and configurations. The antdiv[2:0] bits are found in the MODEM_ANT_DIV_CONTROL API property descriptions and enable the antenna diversity mode. The GPIO pins are capable of sourcing up to 5 mA of current; so, it may be used directly to forward-bias a PIN diode if desired. The antenna diversity algorithm will automatically toggle back and forth between the antennas until the packet starts to arrive. The recommended preamble length for optimal antenna selection is 8 bytes.

4.1.8.6 Preamble Sense Mode

This mode of operation is suitable for extremely low power applications where power consumption is important. The preamble sense mode (PSM) takes advantage of the Digital Signal Arrival detector (DSA), which can detect a preamble within eight bit times with no sensitivity degradation. This fast detection of an incoming signal can be combined with duty cycling of the receiver during the time the device is searching or sniffing for packets over the air. The average receive current is lowered significantly when using this mode. In applications where the timing of the incoming signal is unknown, the amount of power savings is primarily dependent on the data rate and preamble length as the Rx inactive time is determined by these factors. In applications where the sleep time is fixed and the timing of the incoming signal is known, the average current also depends on the sleep time. The PSM mode is similar to the low duty cycle mode but has the benefit of faster signal detection and autonomous duty cycling of the receiver to achieve even lower average receive currents. This mode can be used with the low power mode (LP) which has an active RX current of 10 mA or with the high-performance (HP) mode which has an active RX current of 13 mA.

Figure 4.18. Preamble Sense Mode Table 4.9. Data Rates

PM length = 4 bytes PM length = 8 bytes

Note

Data Rate

1.2 kbps 6.48

3.83

9.6 kbps 6.84

3.96

Typical values. Active RX current is 13 mA.

50 kbps 8.44

4.57

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4.1.9 Wireless MBUS support

Wireless M-Bus is a widely accepted standard for smart meter communication in Europe. The radio supports all Wireless M-Bus modes per the latest draft specification of the EN13757-4 standard. This includes a much wider deviation error tolerance of ±30% and frequency error tolerance of ±4 kHz, short preamble support (16-bit preamble for 2 and 4 level FSK modes), 3-of-6 encoding and decoding and 169 MHz N modes including N2g.

In addition, Silicon Labs has a production ready Wireless M-Bus stack available at no additional cost which supports all modes and runs on the EZR32 (32-bit ARM) family of energy friendly microcontrollers.

This stack and complete documentation including PHY configuration and test results are available for download from the EZRadioPRO page on the Silicon Labs website.

4.1.10 ETSI EN300 220 Category 1

The radio is capable of supporting ETSI Category 1 applications (social alarms, healthcare applications, etc.) in the 169 MHz and 868 MHz bands. Blocking performance is improved at the 2 MHz and 10 MHz offsets allowing for additional margin from the regulatory limits. The radio complies with ACS limits at the 25 kHz offset in both, 169 MHz and 868 MHz bands. In the 169 MHz band, there is no need for an external SAW filter for 2 MHz and 10 MHz blocking resulting in a lower system cost. In the 868 MHz band, an external SAW filter is still required to meet the Cat 1 blocking limits. An RF Pico board is available for evaluation specifically for ETSI Cat 1 applications.

Test conditions for ETSI Cat 1 specifications are different from the typical conditions and are stated below.

• Data Rate: 3 kbps • Deviation: 2 kHz • Modulation: 2 GFSK • IF mode: Fixed and/or Scaled IF • RX bandwidth: 13 kHz • BER target: 0.1% • Blocker signal: CW

Table 4.10. Energy Mode Description

±25 kHz ACS ±2 MHz blocking ±10 MHz blocking RX sensitivity Spurious response

ETSI Cat 1 limits

54 dB 84 dB 84 dB -107 dB 35 dB

169 MHz band(no SAW)

62 dB 88 dB 90 dB -108 dB 40 dB

868 MHz band(no SAW)

58 dB 76 dB 82 dB -108 dB 40 dB For further details on configuring the radio for ETSI Cat 1 applications, refer to the application notes available on the Silicon Labs website

4.2 EZRadio Overview

4.2.1 Introduction

The EZRadio with its +13 dBm output power and excellent sensitivity of -116 dBm allows for a longer operating range, while the low current consumption of 18 mA TX (at 10 dBm), 10 mA RX, and 40 nA standby, provides for superior battery life. By fully integrating all components from the antenna to the GPIO or SPI interface to the MCU, the EZRadio makes it easy to realize this performance in an 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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application. The EZRadio is capable of supporting major worldwide regulatory standards, such as FCC, ETSI, ARIB, and China regulatory standards.

4.2.2 Functional Description

Figure 4.19. EZRadio Block Diagram

The EZRadio is an easy-to-use, size efficient, low current wireless ISM device that covers the sub-GHz bands. The wide operating voltage range of 1.8-3.6 V and low current consumption make the EZRadio an ideal solution for battery powered applications. The EZRadio operates as a time division duplexing (TDD) transceiver where the device alternately transmits and receives data packets. The device uses a single conversion mixer to downconvert the FSK/GFSK or OOK modulated receive signal to a low IF frequency.

Following a programmable gain amplifier (PGA), the signal is converted to the digital domain by a high performance ∆Σ ADC allowing filtering, demodulation, slicing, and packet handling to be performed in the built-in digital modem, increasing the receiver’s performance and flexibility versus analog based architectures. The demodulated signal is output to the system MCU through a programmable GPIO or via the standard SPI bus by reading the 64-byte Rx FIFO.

A single high-precision local oscillator (LO) is used for both transmit and receive modes since the transmitter and receiver do not operate at the same time. The LO signal is generated by an integrated VCO and ∆Σ Fractional-N PLL synthesizer. The synthesizer is designed to support configurable data rates up to 500 kbps. The EZRadio operates in the frequency bands of 283-350, 350-525, and 850-960 MHz. The transmit FSK data is modulated directly into the ∆Σ data stream and can be shaped by a Gaussian low-pass filter to reduce unwanted spectral content.

The device contains a power amplifier (PA) that supports output powers up to +13 dBm and is designed to support single coin cell operation with current consumption of 18 mA for +10 dBm output power.

The PA is single-ended to allow for easy antenna matching and low BOM cost. The PA incorporates automatic ramp-up and ramp-down control to reduce unwanted spectral spreading. Additional system features, such as 64-byte TX/RX FIFOs, preamble detection, sync word detector, and CRC, reduce overall current consumption and allow for the use of lower-cost system MCUs. Power-on-reset (POR) and GPIOs further reduce overall system cost and size. The EZRadio is designed to work with an MCU, crystal, and a few passives to create a very compact and low-cost system.

4.2.2.1 Receiver Chain

The internal low-noise amplifier (LNA) is designed to be a wideband LNA that can be matched with three external discrete components to cover any common range of frequencies in the sub-GHz band.

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sensitivity; therefore, no external gain or front-end modules are necessary. The LNA has gain control, which is controlled by the internal automatic gain control (AGC) algorithm. The LNA is followed by an I-Q mixer, filter, programmable gain amplifier (PGA), and ADC. The I-Q mixers downconvert the signal to an intermediate frequency. The PGA then boosts the gain to be within dynamic range of the ADC. The ADC rejects out-of-band blockers and converts the signal to the digital domain where filtering, demodulation, and processing is performed. Peak detectors are integrated at the output of the LNA and PGA for use in the AGC algorithm.

The RX and TX pins can be directly tied externally on the EZRadio transceiver.

4.2.2.2 Receiver Modem

Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed in the digital domain, which allows for flexibility in optimizing the device for particular applications. The digital modem performs the following functions: • Channel selection filter • Preamble detection • Invalid preamble detection • TX modulation • RX demodulation • Automatic Gain Control (AGC) • Automatic frequency compensation (AFC) • Radio signal strength indicator (RSSI) • Cyclic redundancy check (CRC) The digital channel filter and demodulator are optimized for ultra-low-power consumption and are highly configurable. Supported modulation types are GFSK, FSK, and OOK. The channel filter can be configured to support bandwidths ranging from 850 kHz down to 40 kHz. A large variety of data rates are supported ranging from 0.5 kbps up to 500 kbps. The configurable preamble detector is used with the synchronous demodulator to improve the reliability of the sync-word detection. Preamble detection can be skipped using only sync detection, which is a valuable feature of the asynchronous demodulator when very short preambles are used. The received signal strength indicator (RSSI) provides a measure of the signal strength received on the tuned channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel power measurements for clear channel assessment (CCA), carrier sense (CS), and listen before talk (LBT) functionality. A wireless communication channel can be corrupted by noise and interference, so it is important to know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the presence of erroneous bits in each packet. A CRC is computed and appended at the end of each transmitted packet and verified by the receiver to confirm that no errors have occurred. The packet handler and CRC can significantly reduce the load on the system microcontroller, allowing for a simpler and cheaper microcontroller. The digital modem includes the TX modulator, which converts the TX data bits into the corresponding stream of digital modulation values to be summed with the fractional input to the sigma-delta modulator. This modulation approach results in highly accurate resolution of the frequency deviation. A Gaussian filter is implemented to support GFSK, considerably reducing the energy in adjacent channels. The default bandwidth-time (BT) product is 0.5

for all programmed data rates.

4.2.2.3 Received Signal Strength Indicator

The received signal strength indicator (RSSI) is an estimate of the signal strength in the channel to which the receiver is tuned. The RSSI measurement is done after the channel filter, so it is only a measurement of the desired or undesired in-band signal power. The EZRadio uses a fast response register to read RSSI and so can complete the read in 16 SPI clock cycles with no requirement to wait for CTS. The RSSI value reported by this API command can be converted to dBm using the following equation:

RSSI Equation

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RSSI dBm = (RSSI_value\2) - 130 (4.5) The value of 130 in the above formula is based on bench characterization of the EZRadio RF Pico boards (evaluation boards). The RSSI value is latched at sync word detection and can be read via the fast response register. The latched value of RSSI is available until the device re-enters Rx mode. In addition, the current value of RSSI can be read out using the GET_MODEM_STATUS command. This can be used to implement CCA (clear channel assessment) functionality. The user can set up an RSSI threshold value using the SS Radio Configuration Application GUI.

4.2.2.4 Synthesizer

The EZRadio includes an integrated Sigma Delta ( Σ∆ ) Fractional-N PLL synthesizer capable of operating over the bands from 283-350, 350-525, and 850-960 MHz. The synthesizer has many advantages; it provides flexibility in choosing data rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the loop in the digital domain through the fractional divider, which results in very precise accuracy and control over the transmit deviation. The frequency resolution is (2/3)Freq_xo/(219) for 283-350 MHz, Freq_xo/(219) for 350-525 MHz, and Freq_xo/(218) for 850-960 MHz. The nominal reference frequency to the PLL is 30 MHz, but any XTAL frequency from 25 to 32 MHz may be used. The modem configuration calculator in SS will automatically account for the XTAL frequency being used. The PLL utilizes a differential LC VCO with integrated on-chip inductors. The output of the VCO is followed by a configurable divider, which will divide the signal down to the desired output frequency band.

4.2.2.4.1 Synthesizer Frequency Control

The frequency is set by changing the integer and fractional settings to the synthesizer. The SS calculator will automatically provide these settings, but the synthesizer equation is shown below for convenience.

Initial frequency settings are configured in the EZConfig setup and can also be modified using the API commands: FREQ_CONTROL_INTE, FREQ_CONTROL_FRAC2, FREQ_CONTROL_FRAC1, and FREQ_CONTROL_FRAC0.

RF Frequency Equation

RF Frequency = (fc_inte + fc_frac\2 19 ) * (4 * freq_xo\outdiv) (4.6)

Note

The fc_frac/2 19 value in the above formula must be a number between 1 and 2. The LSB of fc_frac must be "1".

Table 4.11. Output Divider (Outdiv) Values

Outdiv

12 10 8 4

Lower (MHz)

284 350 420 850

Upper (MHz)

350 420 525 960

4.2.2.4.1.1 EZ Frequency Programming

EZ frequency programming allows for easily changing radio frequency using a single API command. The base frequency is first set using the EZConfig setup. This base frequency will correspond to channel 0.

Next, a channel step size is also programmed within the EZConfig setup. The resulting frequency will be: 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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RR Frequency = Base Frequency + Channel * Step Size (4.7) The second argument of the START_RX or START_TX is CHANNEL, which sets the channel number for EZ frequency programming. For example, if the channel step size is set to 1 MHz, the base frequency is set to 900 MHz, and a CHANNEL number of 5 is programmed during the START_TX command, the resulting frequency will be 905 MHz. If no CHANNEL argument is written as part of the START_RX/TX command, it will default to the previous value. The initial value of CHANNEL is 0 and so will be set to the base frequency if this argument is never used.

4.2.2.5 Transmitter

The device contains a +13 dBm power amplifier that is capable of transmitting from -40 to +13 dBm. The

output power set size is dependent on the power level and can be seen in Figure 4.20 (p. 42) . The PA

power level is set using the API command: PA_PWR_LVL. The power amplifier is single-ended to allow for easy antenna matching and low BOM cost. For detailed matching values, BOM, and performance expectations, refer to "AN686: Antennas for the Si4455/4355 RF ICs". Power ramp-up and ramp-down is automatically performed to reduce unwanted spectral spreading.

Figure 4.20. Tx Power vs PA_PWR_LVL and VDD

4.2.2.6 Crystal Oscillator

The EZRadio includes an integrated crystal oscillator with a fast start-up time of less than 250 µs.

The design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components. By default, all that is required off-chip is the crystal. The default crystal is 30 MHz, but the circuit is designed to handle any XTAL from 25 to 32 MHz, set in the EZConfig setup. The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance and to adjust the frequency of the crystal oscillator. The tuning of the crystal load capacitance is programmed through the GLOBAL_XO_TUNE API property. The total internal capacitance is 11 pF and is adjustable in 127 steps (70 fF/step). The crystal frequency adjustment can be used to compensate for crystal production tolerances. The frequency offset characteristics of the

capacitor bank are demonstrated in Figure 4.21 (p. 43) .

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...the world's most energy friendly wireless MCUs Figure 4.21. Capacitor Bank Frequency Offset Characteristics

An external signal source can easily be used in lieu of a conventional XTAL and should be connected to the XIN pin. The incoming clock signal is recommended to be ac-coupled to the XIN pin since the dc bias is controlled by the internal crystal oscillator buffering circuitry. The input swing range should be between 600 mV-1.8 V peak-to-peak. If external drive is desired, the incoming signal amplitude should not go below 0 V or exceed 1.8 V. The best dc bias should be approximately 0.7 V. However, if the signal swing exceeds 1.4 Vpp, the dc bias can be set to 1/2 the peak-to-peak voltage swing. The XO capacitor bank should be set to 0 whenever an external drive is used on the XIN pin. In addition, the POWER_UP command should be invoked with the TCXO option whenever external drive is used.

4.2.2.7 Battery Voltage and Auxiliary ADC

The EZRadio contains an integrated auxiliary 11-bit ADC used for the internal battery voltage detector or an external component via GPIO. The Effective Number of Bits (ENOB) is 9 bits. When measuring external components, the input voltage range is 1 V, and the conversion rate is between 300 Hz to 2.44 kHz. The ADC value is read by first sending the GET_ADC_READING command and enabling the desired inputs. When the conversion is finished and all the data is ready, CTS will go high, and the data can be read out. For details on this command and the formulas needed to interpret the results, refer to the EZRadio API documentation zip file available from www.silabs.com.

4.2.3 Configuration Options and User Interface

4.2.3.1 Radio Configuration Application (RCA) GUI

The Radio Configuration Application (RCA) GUI is part of the Simplicity Studio (SS) program. This setup interface provides an easy path to quickly selecting and loading the desired configuration for the device.

The RCA allows for two different methods for device setup. One option is the configuration table, which provides a list of preloaded, common configurations. A second option allows for custom configurations to be loaded. After the desired configuration is selected, the RCA automatically creates the EZConfig configuration array that will be passed to the chip for setup. The program then gives the option to load a sample project with the selected configuration onto the evaluation board or launch IDE with the new configuration array preloaded into the user program. For more information on EZConfig usage, refer to application note, “AN692: Si4355/Si4455 Programming Guide”.

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4.2.3.1.1 Radio Configuration Application

The Radio Configuration Application provides an intuitive interface for directly modifying the device configuration. Using this control panel, the device parameters such as modulation type, data rate, frequency deviation, and any packet related settings can be set. The program then takes these parameters and automatically determines the appropriate device settings. This method allows the user to have complete flexibility in determining the configuration of the device without the need to translate the system requirements into device specific properties. The resulting configuration array is automatically generated and available for use in the user's program. The resulting configuration array is obfuscated; therefore, its content changes every time a new array is generated, even if the input parameters are the same.

4.2.3.2 Configuration Options 4.2.3.2.1 Frequency Band

The EZRadio can operate in the 283-350 MHz, 350-525 MHz, or 850-960 MHz bands. One of these three bands will be selected during the configuration setup and then the specific transmission frequency that will be used within this band can be selected.

4.2.3.2.2 Modulation Type

The EZRadio can operate using On/Off Keying (OOK), Frequency Shift Keying (FSK), or Gaussian Frequency Shift Keying (GFSK). OOK modulation is the most basic modulation type available. It is the most power-efficient method and does not require as high oscillator accuracy as FSK. FSK provides the best sensitivity and range performance, but generally requires more precision from the oscillator used.

GFSK is a version of FSK where the signal is passed through a Gaussian filter, limiting its spectral width.

As a result, the out-of-band components of the signal are reduced.

The EZRadio also has an option for Manchester coding. This method provides a state transition at each bit and so allows for more reliable clock recovery. Manchester code is available only when using the packet handler option and, if selected, will be applied to the entire packet (the preamble pattern is set to continuous “1” if the Manchester mode is enabled; therefore, the chip rate of the resulting preamble pattern is the same as for the rest of the packet). The polarity can be configured to a “10” or “01”.

Figure 4.22. Manchester Code Example

4.2.3.2.3 Frequency Deviation

If FSK or GFSK modulation is selected, then a frequency deviation will also need to be selected. The frequency deviation is the maximum instantaneous difference between the FM modulated frequency and the nominal carrier frequency. The EZRadio can operate across a wide range of data rates and frequency deviations. If a frequency deviation needs to be selected, the following guideline might be helpful to build a robust link. A proper frequency deviation is linked to the frequency error between transmitter and receiver. The frequency error can be calculated using the crystal tolerance parameters and the RF operating frequency: (ppm_tx+ppm_rx)*Frf/1E-6. For frequency errors below 50 kHz, the 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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deviation can be about the same as the frequency error. For frequency errors exceeding 50 kHz, the frequency deviation can be set to about 0.75 times the frequency error. It is advised to position the modulation index (= 2*freq_dev/data_rate) into a range between 1 and 100 for Packet Handling mode and 2 to 100 for direct mode (non-standard preamble). For example, when in Packet Handling mode and the frequency error is smaller than data_rate/2, the frequency deviation is set to about data_rate/2.

When the frequency error exceeds 100xdata_rate/2, the frequency deviation is preferred to be set to 100xdata_rate/2.

4.2.3.2.4 Channel Bandwidth

The channel bandwidth sets the bandwidth for the receiver. Since the receiver bandwidth is directly proportional to the noise allowed in the system, this will normally be set as low as possible. The specific channel bandwidth used will usually be determined based upon the precision of the oscillator and the frequency deviation of the transmitted signal.

4.2.3.2.5 Preamble Length

A preamble is a defined simple bit sequence used to notify the receiver that a data transmission is imminent. The length of this preamble will normally be set as short as possible to minimize power while insuring that it will be reliably detected given the receiver characteristics, such as duty cycling and packet error rate performance. The EZRadio allows the preamble length to be set between 0 to 255 bytes in length with a default length of 4 bytes. The preamble pattern for the EZRadio will always be 55h with a first bit of “0” if the packet handler capability is used.

4.2.3.2.6 Sync Word Length and Pattern

The sync word follows the preamble in the packet structure and is used to identify the start of the payload data and to synchronize the receiver to the transmitted bit stream. The EZRadio allows for sync word lengths of 1 to 4 bytes, where the default is a 2 byte length 2d d4 pattern.

4.2.3.2.7 Cyclic Redundancy Check

Cyclic Redundancy Check (CRC) is used to verify that no errors have occurred during transmission and the received packet has exactly the same data as it did when transmitted. If this function is enabled in the EZRadio, the last byte of transmitted data must include the CRC generated by the transmitter. The EZRadio then performs a CRC calculation on the received packet and compares that to the transmitted CRC. If these two values are the same, the EZRadio will set an interrupt indicating a valid packet has been received and is waiting in the Rx FIFO. If these two CRC values differ, the EZRadio will flag an interrupt indicating that a packet error occurred. The EZRadio uses CRC(16)-IBM: x16+x15+x2+1 with a seed of 0xFFFF as well as a 16-bit ITU-T CRC as specified in the IEEE 802.15.4g standard.

4.2.3.2.8 Preamble Sense Mode

This mode of operation is suitable for extremely low power applications where power consumption is important. The preamble sense mode (PSM) takes advantage of the Digital Signal Arrival detector (DSA), which can detect a preamble within eight bit times with no sensitivity degradation. This fast detection of an incoming signal can be combined with duty cycling of the receiver during the time the device is searching or sniffing for packets over the air. The average receive current is lowered significantly when using this mode. In applications where the timing of the incoming signal is unknown, the amount of power savings is primarily dependent on the data rate and preamble length as the Rx inactive time is determined by these factors. In applications where the sleep time is fixed and the timing of the incoming signal is known, the average current also depends on the sleep time. The PSM mode is similar to the low duty cycle mode but has the benefit of faster signal detection and autonomous duty cycling of the receiver to achieve even lower average receive currents.

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Figure 4.23. Preamble Sense Mode ...the world's most energy friendly wireless MCUs Table 4.12. Data Rates

1.2 kbps

5.8

3.6

9.6 kbps

6.1

3.7

Data Rate 50 kbps

7.6

4.3

100 kbps

9.3

5.0

mA mA

Note

Typical values. Active RX current is 10.9 mA.

4.2.4 Controller Interface

4.2.4.1 Serial Peripheral Interface

The EZRadio communicates with the host MCU over a standard 4-wire serial peripheral interface (SPI): SCLK, SDI, SDO, and nSEL. The SPI interface is designed to operate at a maximum of 10 MHz. The

SPI timing parameters are listed in Table 4.13 (p. 46) . The host MCU writes data over the SDI pin

and can read data from the device on the SDO output pin. Figure 4.25 (p. 47) shows an SPI write

command. The nSEL pin should go low to initiate the SPI command. The first byte of SDI data will be one of the API commands followed by n bytes of parameter data which will be variable depending on the specific command. The rising edges of SCLK should be aligned with the center of the SDI data. For details regarding pin setup, see datasheet for the specific part.

Table 4.13. Serial Interface Timing Parameters

Symbol

tCH tCL tDS tDH tDD tDE tSS tSH tSW

Parameter

Clock high time Clock low time Data setup time Data hold time Output data delay time Output disable time Select setup time Select hold time Select high period 20 20 50 80

Min (ns)

40 40 20 43 45

Max (ns)

Note

CL = 10 pF; VDD = 1.8 V; SDO Drive strength setting = 10.

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Figure 4.24. Serial Interface Timing ...the world's most energy friendly wireless MCUs Figure 4.25. SPI Write Command

nSEL SDO SDI SCLK FW Command Param Byte 0 Param Byte n The EZRadio contains an internal MCU which controls all the internal functions of the radio. For SPI read commands, a typical communication flow of checking clear-to-send (CTS) is used to make sure the internal MCU has executed the command and prepared the data to be output over the SDO pin.

Figure 4.26 (p. 48) demonstrates the general flow of an SPI read command. Once the CTS value

reads FFh, then the read data is ready to be clocked out to the host MCU. The typical time for a valid

FFh CTS reading is 20 µs. Figure 4.27 (p. 48) demonstrates the remaining read cycle after CTS is

set to FFh. The internal MCU will clock out the SDO data on the negative edge so the host MCU should process the SDO data on the rising edge of SCLK.

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...the world's most energy friendly wireless MCUs Figure 4.26. SPI Read Command-Check CTS Value

Firm ware Flow

Send Com m and Read CTS CTS Value

0x FF 0x 00

Ret rieve Response

NSEL SDO SDI SCK ReadCm dBuff CTS

Figure 4.27. SPI Read Command-Clock Out Read Data

NSEL SDO SDI SCK Response Byt e 0 Response Byt e n

4.2.4.2 Operating Modes and Timing

The primary states of the EZRadio are shown in Figure 4.28 (p. 48) . The shutdown state completely

shuts down the radio, minimizing current consumption and is controlled using the SDN (pin 2). All other states are controlled using the API commands START_RX, START_TX and CHANGE_STATE.

Table 4.14 (p. 49) shows each of the operating modes with the time required to reach either RX or TX state as well as the current consumption of each state. The times in Table 4.14 (p. 49) are

measured from the rising edge of nSEL until the chip is in the desired state. This information is included for reference only since an automatic sequencer moves the chip from one state to another and so

it is not necessary to manually step through each state. Figure 4.29 (p. 49) and Figure 4.30 (p.

49) demonstrate this timing and the current consumption for each radio state as the chip moves from

shutdown or standby to TX and back. Most applications will utilize the standby mode since this provides the fastest transition response time, maintains all register values, and results in nearly the same current consumption as shutdown.

Figure 4.28. State Machine Diagram

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...the world's most energy friendly wireless MCUs Table 4.14. Operating State Response Time and Current Consumption

State / Mode

Shutdown Standby SPI Active Ready Tx Tune Rx Tune Tx Rx

Tx

30 ms 504 µs 288 µs 108 µs 60 µs 120 µs

Response Time to Rx

30 ms 516 µs 296 µs 120 µs 84 µs 132 µs 108 µs

Current in State / Mode

30 nA 40 nA 1.5 mA 1.8 mA 6.8 mA 7.1 mA 18 mA @ +10 dBm 10.9 mA

Figure 4.29. Start-Up Timing and Current Consumption using Shutdown State Figure 4.30. Start-Up Timing and Current Consumption using Standby State

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4.2.4.2.1 Shutdown State

The shutdown state is the lowest current consumption state of the device and is entered by driving SDN (Pin 2) high. In this state, all register contents are lost and there is no SPI access. To exit this mode, drive SDN low. The device will then initiate a power on reset (POR) along with internal calibrations.

Once this POR period is complete, the POWER_UP command is required to initialize the radio and the configuration can then be loaded into the device. The SDN pin must be held high for at least 10 µs before driving it low again to insure the POR can be executed correctly. The shutdown state can be used to fully reset the part. If POR timing and voltage requirements cannot be met, it is highly recommended that SDN be controlled using the host processor rather than tying it to GND on the board.

4.2.4.2.2 Standby State

The standby state has similar current consumption to the shutdown state but retains all register values, allowing for a much faster response time. Because of these benefits, most applications will want to use standby mode rather than shutdown. The standby state is entered by using the CHANGE_STATE API command. While in this state, the SPI is accessible but any SPI event will automatically transition the chip to the SPI active state. After the SPI event, the host will need to re-command the device to standby mode.

4.2.4.2.3 SPI Active State

The SPI active state enables the device to process any SPI events, such as API commands. In this state, the SPI and boot up oscillator are enabled. The SPI active state is entered by using the CHANGE_STATE command or automatically through an SPI event while in standby mode. If the SPI active state was entered automatically from standby mode, a CHANGE_STATE command will be needed to return the device to standby mode.

4.2.4.2.4 Power on Reset

A Power On Reset (POR) sequence is used to boot the device up from a fully off or shutdown state. To execute this process, VDD must ramp within 1 ms and must remain applied to the device for at least 10 ms. If VDD is removed, then it must stay below 0.15 V for at least 10 ms before being applied again.

Refer to Figure 4.31 (p. 50) and Table 4.15 (p. 51) for details.

Figure 4.31. POR Timing Diagram

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...the world's most energy friendly wireless MCUs Table 4.15. POR Timing

Variable

tPORH tPORL VRRH VRRL tSR

Description

0

Min

10 10 90%*Vdd

Typ Max

150 1

Units

ms ms V mV ms

4.2.4.2.5 TX State

The TX state is used whenever the device is required to transmit data. It is entered using either the START_TX or CHANGE_STATE command. With the START_TX command, the next state can be defined to insure optimal timing. When either command is sent to enter TX state, an internal sequencer automatically takes care of all actions required to move between states with no additional

user commands needed. Examples of the timing of this transition can be seen in Figure 4.29 (p. 49) and Figure 4.30 (p. 49) . The specific sequencer controlled events that take place during this time can

include enable internal LDOs, start up crystal oscillator, enable PLL, calibrate VCO/PLL, active power amplifier, and transmit packet.

Figure 4.32 (p. 51) shows an example of the commands and timing for the START_TX command.

CTS will go high as soon as the sequencer puts the part into TX state. As the sequencer is stepping through the events listed above, CTS will be low and no new commands or property changes are allowed.

If the nIRQ is used to monitor the current state, there will be a slight delay caused by the internal hardware from when the event actually occurs to when the transition occurs on the nIRQ. The time from entering TX state to when the nIRQ will transition is 13 µs. If a GPIO is programmed for TX state or used as control for a transmit/receive switch (TR switch), there is no delay.

Figure 4.32. START_TX Commands and Timing

CTS NSEL SDI Current St at e FRR nIRQ GPIOx – TX st at e START_TX YYY St at e YYY St at e Tx St at e Tx St at e TXCOMPLETE_STATE TXCOMPLETE_STATE

4.2.4.2.6 RX State

The RX state is used whenever the device is required to receive data. It is entered using either the START_RX or CHANGE_STATE commands. With the START_RX command, the next state can be defined to insure optimal timing. When either command is sent to enter RX state, an internal sequencer automatically takes care of all actions required to move between states with no additional user commands needed. The sequencer controlled events can include enable the digital and analog LDOs, start up the crystal oscillator, enable PLL, calibrate VCO, enable receiver circuits, and enable receive mode. The device will also automatically set up all receiver features such as packet handling based upon the initial configuration of the device.

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4.2.4.3 Interrupts

The EZRadio is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Registers. The nIRQ output signal will then be reset until the next change in status is detected.

The interrupt sources are grouped into three categories: packet handler, chip status, and modem. The individual interrupts in these groups can be enabled/disabled in the interrupt property registers, 0x0101, 0x0102, and 0x0103. An interrupt must be enabled for it to trigger an event on the nIRQ pin. The interrupt group must be enabled as well as the individual interrupts in API property 0x0100.

• Chip status • Modem status • Packet handler status • Packet sent • Packet received • CRC error • Invalid preamble detected • Invalid sync detected • Preamble detected • Sync detected • State change • Command error • Chip ready • TX FIFO almost empty • RX FIFO almost full • RSSI interrupt

4.2.4.4 GPIO

Four General Purpose IO (GPIO) pins are available for use in the application. The GPIOs are configured using the GPIO_PIN_CFG command. GPIO pins 0 and 1 should be used for active signals such as data or clock. GPIO pins 2 and 3 have more susceptibility to generating spurious components in the synthesizer than pins 0 and 1. The drive strength of the GPIO's can be adjusted with the GEN_CONFIG parameter in the GPIO_PIN_CFG command. By default, the drive strength is set to the minimum. The

default configuration and the state of the GPIO during shutdown are shown in Table 4.16 (p. 53) . For

a complete list of the GPIO options, please refer to the EZRadio API documentation zip file available from www.silabs.com.

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...the world's most energy friendly wireless MCUs Table 4.16. GPIOs

Pin

GPIO0 GPIO1 GPIO2 GPIO3 nIRQ SDO SDI SCLK NSEL 0 0

SDN State

0 0 Resistive VDD pull-up Resistive VDD pull-up High Z High Z High Z

POR Default

POR CTS POR POR nIRQ SDO SDI SCLK NSEL

4.2.5 Data Handling and Packet Handler

4.2.5.1 RX and TX FIFOs

Two 64-byte FIFOs are integrated into the chip, one for RX and one for TX. Writing to command register 66h loads data into the TX FIFO and reading from command register 77h reads data from the RX FIFO.

For packet lengths greater than 64 bytes, RX_FIFO_ALMOST_FULL and TX_FIFO_ALMOST_EMPTY status bits and interrupts can be used to manage the FIFO. The maximum payload length supported in packet handler mode is 255 bytes.

The EZRadio includes integrated packet handler features such as preamble and sync word detection as well as CRC calculation. This allows the chip to qualify and synchronize with legitimate transmissions independent of the microcontroller. In this setup, the preamble and sync word length can be modified and the sync word pattern can be selected. If the preamble is greater than or equal to 4 bytes, the device uses the preamble detection circuit with a 2-byte detection threshold. If the preamble is less than 32 bits, then at least two bytes of sync word are required plus at least one byte of 0101 pattern (3 bytes total).

In this case, preamble detection is skipped, and only sync word detection is used. For any combination of preamble and sync word less than three bytes, the device will use direct mode. The general packet

structure is shown in Table 4.17 (p. 53) .

The EZConfig setup also provides the option to select a variable packet length. With this setting, the receiver is not required to know the packet length ahead of time. The transmitter sends the length of the packet immediately after the sync word. The packet structure for variable length packets is shown

in Table 4.16 (p. 53) .

Table 4.17. Packet Structure for Fixed Packet Length

Preamble

0 - 255 Bytes

Sync Word

1 - 4 Bytes

Data

1 - 255 Bytes

CRC

2 Bytes

4.2.5.2 Direct Mode

In direct mode, the packet handler (including FIFO) is bypassed, and the host MCU must feed the data stream to the device in TX mode and read out the data stream in RX mode via GPIOs. The host MCU will process the data and perform packet handler functions. This is commonly used to support legacy implementations where host MCU software exists or to support non-standard packet structures. Some examples are packets with non 1010 preamble pattern, no preamble or sync word, or sync word with no edge transitions.

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5 System Processor

0 1 2 3 4

CM4 Core 3 2 - bit ALU

Hardware divider Single cycle 32- bit m ult iplier Cont rol Logic Float ing- Point Unit Inst ruct ion Int erface NVIC Int erface DSP ex t ensions Thum b & Thum b- 2 Decode Dat a Int erface Mem ory Prot ect ion Unit

Quick Facts What?

The industry leading Cortex-M4 processor from ARM is the CPU in the EZR32WG wireless microcontrollers.

Why?

The ARM Cortex-M4 is designed for exceptional short response time, high code density, and high 32-bit throughput while maintaining a strict cost and power consumption budget.

How?

Combined with the ultra low energy peripherals available, the Cortex-M4 with Floating-Point Unit (FPU) makes the EZR32WG devices perfect for 8- to 32-bit applications. The processor is featuring a Harvard architecture, 3 stage pipeline, single cycle instructions, extended Thumb-2 instruction set support, and fast interrupt handling.

5.1 Introduction

The ARM Cortex-M4 32-bit RISC processor provides outstanding computational performance and exceptional system response to interrupts while meeting low cost requirements and low power consumption.

The ARM Cortex-M4 implemented is revision r0p1.

5.2 Features

• Digital Signal Processor • Enhances speed and reduces the active time with dedicated DSP instructions • Harvard Architecture • Separate data and program memory buses (No memory bottleneck as for a single-bus system) • 3-stage pipeline • Thumb-2 instruction set • Enhanced levels of performance, energy efficiency, and code density • Single-Precision Floating-Point Unit • Enables embedded system designers to take full advantage of floating-points • Extends the instruction set with 28 floating-point instructions • Single-cycle multiply and efficient divide instructions • 32-bit multiplication in a single cycle • Signed and unsigned divide operations between 2 and 12 cycles • Atomic bit manipulation with bit banding • Direct access to single bits of data • Two 1MB bit banding regions for memory and peripherals mapping to 32MB alias regions • Atomic operation which cannot be interrupted by other bus activities 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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• 1.25 DMIPS/MHz • Memory Protection Unit • Up to 8 protected memory regions • 24-bit System Tick Timer for Real-Time Operating System (RTOS) • Excellent 32-bit migration choice for 8/16 bit architecture based designs • Simplified stack-based programmer's model is compatible with traditional ARM architecture and retains the programming simplicity of legacy 8- and 16-bit architectures • Unaligned data storage and access • Continuous storage of data requiring different byte lengths • Data access in a single core clock cycle • Integrated power modes • Sleep Now mode for immediate transfer to low power state • Sleep on Exit mode for entry into low power state after the servicing of an interrupt • Ability to extend power savings to other system components • Optimized for low latency, nested interrupts

5.3 Functional Description

For a full functional description of the ARM Cortex-M4 (r0p1) implementation in the EZR32WG family, the reader is referred to the ARM Cortex-M4 Devices Generic User Guide.

5.3.1 Interrupt Operation

Figure 5.1. Interrupt Operation

Module IFS[n] Int errupt condit ion IFC[n] IEN[n] set clear IF[n] IRQ Cort ex - M4 NVIC SETENA[n]/ CLRENA[n] Act ive int errupt set clear SETPEND[n]/ CLRPEND[n] Soft ware generat ed int errupt Int errupt request The EZR32WG devices have up to interrupt request lines (IRQ) which are connected to the Cortex-M4.

Each of these lines (shown in Table 5.1 (p. 55) ) are connected to one or more interrupt flags in one

or more modules. The interrupt flags are set by hardware on an interrupt condition. It is also possible to set/clear the interrupt flags through the IFS/IFC registers. Each interrupt flag is then qualified with its own interrupt enable bit (IEN register), before being OR'ed with the other interrupt flags to generate the IRQ. A high IRQ line will set the corresponding pending bit (can also be set/cleared with the SETPEND/ CLRPEND bits in ISPR0/ICPR0) in the Cortex-M4 NVIC. The pending bit is then qualified with an enable bit (set/cleared with SETENA/CLRENA bits in ISER0/ICER0) before generating an interrupt request to

the core. Figure 5.1 (p. 55) illustrates the interrupt system. For more information on how the interrupts

are handled inside the Cortex-M4, the reader is referred to the ARM Cortex-M4 Devices Generic User Guide.

Table 5.1. Interrupt Request Lines (IRQ)

1 2

IRQ #

0 3

Source

DMA GPIO_EVEN TIMER0 USART0_RX 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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7 8 9 10 5 6

IRQ #

4 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

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Source

USART0_TX USB ACMP0/ACMP1 ADC0 DAC0 I2C0 I2C1 GPIO_ODD TIMER1 TIMER2 TIMER3 USART1_RX USART1_TX LESENSE USART2_RX USART2_TX UART0_RX UART0_TX UART1_RX UART1_TX LEUART0 LEUART1 LETIMER0 PCNT0 PCNT1 PCNT2 RTC BURTC CMU VCMP LCD MSC AES EBI EMU 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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6 Memory and Bus System

...the world's most energy friendly wireless MCUs 0 1 2 3 4

Quick Facts What?

A low latency memory system, including low energy flash and RAM with data retention, makes extended use of low-power energy modes possible.

Why?

RAM retention reduces the need for storing data in flash and enables frequent use of the ultra low energy modes EM2 and EM3 with as little as 0.65 µA current consumption.

How?

Low energy and non-volatile flash memory stores program and application data in all energy modes and can easily be reprogrammed in system. Low leakage RAM, with data retention in EM0 to EM3, removes the data restore time penalty, and the DMA ensures fast autonomous transfers with predictable response time.

6.1 Introduction

The EZR32WG contains an AMBA AHB Bus system allowing bus masters to access the memory mapped address space. A multilayer AHB bus matrix, using a Round-robin arbitration scheme, connects the

master bus interfaces to the AHB slaves (Figure 6.1 (p. 57) ). The bus matrix allows several AHB

slaves to be accessed simultaneously. An AMBA APB interface is used for the peripherals, which are accessed through an AHB-to-APB bridge connected to the AHB bus matrix. The AHB bus masters are: • Cortex-M4 ICode: Used for instruction fetches from Code memory (0x00000000 - 0x1FFFFFFF).

Cortex-M4 DCode: Used for debug and data access to Code memory (0x00000000 - 0x1FFFFFFF).

Cortex-M4 System: Used for instruction fetches, data and debug access to system space (0x20000000 - 0xDFFFFFFF).

DMA: Can access SRAM, Flash and peripherals (0x00000000 - 0xDFFFFFFF).

USB DMA: Can access SRAM and Flash (0x00000000 - 0x3FFFFFFF), and the AHB-peripherals: USB and AES.

Figure 6.1. EZR32WG Bus System

6.2 Functional Description

The memory segments are mapped together with the internal segments of the Cortex-M4 into the system

memory map shown by Figure 6.2 (p. 58)

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Figure 6.2. System Address Space ...the world's most energy friendly wireless MCUs

The embedded SRAM is located at address 0x20000000 in the memory map of the EZR32WG. When running code located in SRAM starting at this address, the Cortex-M4 uses the System bus to fetch instructions. This results in reduced performance as the Cortex-M4 accesses stack, other data in SRAM and peripherals using the System bus. To be able to run code from SRAM efficiently, the SRAM is also mapped in the code space at address 0x10000000. When running code from this space, the Cortex-M4 fetches instructions through the I/D-Code bus interface, leaving the System bus for data access. The SRAM mapped into the code space can however only be accessed by the CPU, i.e. not the DMA.

6.2.1 Bit-banding

The SRAM bit-band alias and peripheral bit-band alias regions are located at 0x22000000 and 0x42000000 respectively. Read and write operations to these regions are converted into masked single bit reads and atomic single-bit writes to the embedded SRAM and peripherals of the EZR32WG.

The standard approach to modify a single register or SRAM bit in the aliased regions, requires software to read the value of the byte, half-word or word containing the bit, modify the bit, and then write the byte, half-word or word back to the register or SRAM address. Using bit-banding, this read-modify-write can be done in a single atomic operation. As read-writeback, bit-masking and bit-shift operations are not necessary in software, code size is reduced and execution speed improved.

The bit-band regions allows addressing each individual bit in the SRAM and peripheral areas of the memory map. To set or clear a bit in the embedded SRAM, write a 1 or a 0 to the following address:

Memory SRAM Area Set/Clear Bit

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bit_address = 0x22000000 + (address – 0x20000000) × 32 + bit × 4, (6.1) where address is the address of the 32-bit word containing the bit to modify, and bit is the index of the bit in the 32-bit word.

To modify a bit in the Peripheral area, use the following address:

Memory Peripheral Area Bit Modification

bit_address = 0x42000000 + (address – 0x40000000) × 32 + bit × 4, (6.2) where address and bit are defined as above.

Note that the AHB-peripherals USB and AES does not support bit-banding.

6.2.2 Peripherals

The peripherals are mapped into the peripheral memory segment, each with a fixed size address range

according to Table 6.1 (p. 59) , Table 6.2 (p. 59) and Table 6.3 (p. 60) .

Table 6.1. Memory System Core Peripherals

Core peripherals Address Range

0xE0041000 - 0xE0081000 0x400E0000 - 0x400E0400 0x400CA000 - 0x400CA400 0x400C8000 - 0x400C8400 0x400C6000 - 0x400C6400 0x400C4000 - 0x400C4400 0x400C2000 - 0x400C4000 0x400C0000 - 0x400C0400

Module Name

ETM AES RMU CMU EMU USB DMA MSC

Table 6.2. Memory System Low Energy Peripherals

Low Energy peripherals Address Range

0x4008C000 - 0x4008C400 0x40088000 - 0x40088400 0x40086800 - 0x40086C00 0x40086400 - 0x40086800 0x40086000 - 0x40086400 0x40084400 - 0x40084800 0x40084000 - 0x40084400 0x40082000 - 0x40082400 0x40081000 - 0x40081400 0x40080000 - 0x40080400

Module Name

LESENSE WDOG PCNT2 PCNT1 PCNT0 LEUART1 LEUART0 LETIMER0 BURTC RTC 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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Peripherals Address Range

0x400CC000 - 0x400CC400 0x40010C00 - 0x40011000 0x40010800 - 0x40010C00 0x40010400 - 0x40010800 0x40010000 - 0x40010400 0x4000E400 - 0x4000E800 0x4000E000 - 0x4000E400 0x4000C800 - 0x4000CC00 0x4000C400 - 0x4000C800 0x4000C000 - 0x4000C400 0x4000A400 - 0x4000A800 0x4000A000 - 0x4000A400 0x40006000 - 0x40007000 0x40004000 - 0x40004400 0x40002000 - 0x40002400 0x40001400 - 0x40001800 0x40001000 - 0x40001400 0x40000000 - 0x40000400

6.2.3 Bus Matrix

The Bus Matrix connects the memory segments to the bus masters: • Code: CPU instruction or data fetches from the code space • System: CPU read and write to the SRAM and peripherals • DMA: Access to SRAM, Flash and peripherals • USB DMA: Access to SRAM and Flash

Module Name

PRS TIMER3 TIMER2 TIMER1 TIMER0 UART1 UART0 USART2 USART1 USARTRF0 I2C1 I2C0 GPIO DAC0 ADC0 ACMP1 ACMP0 VCMP

6.2.3.1 Arbitration

The Bus Matrix uses a round-robin arbitration algorithm which enables high throughput and low latency while starvation of simultaneous accesses to the same bus slave are eliminated. Round-robin does not assign a fixed priority to each bus master. The arbiter does not insert any bus wait-states.

6.2.3.2 Access Performance

The Bus Matrix is a multi-layer energy optimized AMBA AHB compliant bus with an internal bandwidth equal to 4 times a single AHB-bus.

The Bus Matrix accepts new transfers initiated by each master in every clock cycle without inserting any wait-states. The slaves, however, may insert wait-states depending on their internal throughput and the clock frequency.

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The Cortex-M4, the DMA Controller, and the peripherals run on clocks that can be prescaled separately.

When accessing a peripheral which runs on a frequency equal to or faster than the HFCORECLK, the number of wait cycles per access, in addition to master arbitration, is given by:

Memory Wait Cycles with Clock Equal or Faster than HFCORECLK

N cycles = 2 + N slave cycles , (6.3) where N slave cycles is the wait cycles introduced by the slave.

When accessing a peripheral running on a clock slower than the HFCORECLK, wait-cycles are introduced to allow the transfer to complete on the peripheral clock. The number of wait cycles per access, in addition to master arbitration, is given by:

Memory Wait Cycles with Clock Slower than CPU

N cycles = (2 + N slave cycles ) x f HFCORECLK /f HFPERCLK , (6.4) where N slave cycles is the number of wait cycles introduced by the slave.

For general register access, N slave cycles = 1.

More details on clocks and prescaling can be found in Chapter 12 (p. 166) .

6.3 Access to Low Energy Peripherals (Asynchronous Registers)

6.3.1 Introduction

The Low Energy Peripherals are capable of running when the high frequency oscillator and core system is powered off, i.e. in energy mode EM2 and in some cases also EM3. This enables the peripherals to perform tasks while the system energy consumption is minimal.

The Low Energy Peripherals are: • Low Energy Timer - LETIMER • Low Energy UART - LEUART • Pulse Counter - PCNT • Real Time Counter - RTC • Watchdog - WDOG • Low Energy Sensor Interface - LESENSE • Backup RTC - BURTC All Low Energy Peripherals are memory mapped, with automatic data synchronization. Because the Low Energy Peripherals are running on clocks asynchronous to the core clock, there are some constraints on how register accesses can be done, as described in the following sections.

6.3.1.1 Writing

Every Low Energy Peripheral has one or more registers with data that needs to be synchronized into the Low Energy clock domain to maintain data consistency and predictable operation. There are two different synchronization mechanisms on the EZR32WG; immediate synchronization, and delayed synchronization. Immediate synchronization is available for the RTC, LETIMER and LESENSE, and results in an immediate update of the target registers. Delayed synchronization is used for the other Low Energy Peripherals, and for these peripherals, a write operation requires 3 positive edges on the clock of the Low Energy Peripheral being accessed. Registers requiring synchronization are marked "Asynchronous" in their description header.

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6.3.1.1.1 Delayed synchronization

After writing data to a register which value is to be synchronized into the Low Energy Peripheral using delayed synchronization, a corresponding busy flag in the _SYNCBUSY register (e.g.

LEUART_SYNCBUSY) is set. This flag is set as long as synchronization is in progress and is cleared upon completion.

Note

Subsequent writes to the same register before the corresponding busy flag is cleared is not supported. Write before the busy flag is cleared may result in undefined behavior.

In general, the SYNCBUSY register only needs to be observed if there is a risk of multiple write access to a register (which must be prevented). It is not required to wait until the relevant flag in the SYNCBUSY register is cleared after writing a register. E.g EM2 can be entered immediately after writing a register.

See Figure 6.3 (p. 62) for a more detailed overview of the write operation.

Figure 6.3. Write operation to Low Energy Peripherals

Writ e[0:n] Set 0 Set 1 Set n Core Clock Dom ain Core Clock Regist er 0 Regist er 1 .

.

.

Regist er n Freeze Low Frequency Clock Dom ain Low Frequency Clock Synchronizer 0 Synchronizer 1 .

.

.

Synchronizer n Low Frequency Clock Regist er 0 Sync Regist er 1 Sync .

.

.

Regist er n Sync Synchronizat ion Done Syncbusy Regist er 0 Syncbusy Regist er 1 .

.

.

Syncbusy Regist er n Clear 0 Clear 1 Clear n

6.3.1.1.2 Immediate synchronization

Contrary to the peripherals with delayed synchronization, data written to peripherals with immediate synchronization, takes effect in the peripheral immediately. They are updated immediately on the peripheral write access. If a write is set up close to a peripheral clock edge, the write is delayed to after the clock edge. This will introduce wait-states on peripheral access. In the worst case, there can be three wait-state cycles of the HFCORECLK_LE and an additional wait-state equivalent of up to 315 ns.

For peripherals with immediate synchronization, the SYNCBUSY registers are still present and serve two purposes: (1) commands written to a peripheral with immediate synchronization are not executed before the first peripheral clock after the write. During this period, the SYNCBUSY flag in the command register is set, indicating that the command has not yet been executed; (2) to maintain backwards compatibility with the EFM32G series, SYNCBUSY registers are also present for other registers. These are however, always 0, indicating that register writes are always safe.

Note

If the application must be compatible with the EFM32G series, all Low Energy Peripherals should be accessed as if they only had delayed synchronization, i.e. using SYNCBUSY.

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6.3.1.2 Reading

When reading from Low Energy Peripherals, the data is synchronized regardless of the originating clock domain. Registers updated/maintained by the Low Energy Peripheral are read directly from the Low Energy clock domain. Registers residing in the core clock domain, are read from the core clock domain.

See Figure 6.4 (p. 63) for a more detailed overview of the read operation.

Note

Writing a register and then immediately reading back the value of the register may give the impression that the write operation is complete. This is not necessarily the case. Please refer to the SYNCBUSY register for correct status of the write operation to the Low Energy Peripheral.

Figure 6.4. Read operation from Low Energy Peripherals

Core Clock Dom ain

Core Clock Regist er 0 Regist er 1 .

.

.

Regist er n Freeze

Low Frequency Clock Dom ain

Low Frequency Clock Synchronizer 0 Synchronizer 1 .

.

.

Synchronizer n Low Frequency Clock Regist er 0 Sync Regist er 1 Sync .

.

.

Regist er n Sync Read Synchronizer Read Dat a HW St at us Regist er 0 HW St at us Regist er 1 .

.

.

HW St at us Regist er m Low Energy Peripheral Main Funct ion

6.3.2 FREEZE register

For Low Energy Peripherals with delayed synchronization there is a _FREEZE register (e.g. RTC_FREEZE), containing a bit named REGFREEZE. If precise control of the synchronization process is required, this bit may be utilized. When REGFREEZE is set, the synchronization process is halted, allowing the software to write multiple Low Energy registers before starting the synchronization process, thus providing precise control of the module update process. The synchronization process is started by clearing the REGFREEZE bit.

Note

The FREEZE register is also present on peripherals with immediate synchronization, but has no effect.

6.4 Flash

The Flash retains data in any state and typically stores the application code, special user data and security information. The Flash memory is typically programmed through the debug interface, but can also be erased and written to from software.

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• More than 10 years data retention at 85°C • Lock-bits for memory protection • Data retention in any state

6.5 SRAM

The primary task of the SRAM memory is to store application data. Additionally, it is possible to execute instructions from SRAM, and the DMA may used to transfer data between the SRAM, Flash and peripherals.

• Up to 32 kB memory • Bit-band access support • Data retention of the entire memory in EM0 to EM3

6.6 Device Information (DI) Page

The DI page contains calibration values, a unique identification number and other useful data. See the table below for a complete overview.

Table 6.4. Device Information Page Contents

DI Address

0x0FE08020 0x0FE08028 0x0FE08030 0x0FE08040 0x0FE08048 0x0FE08050 0x0FE08058 0x0FE08060 0x0FE08068 0x0FE08078 0x0FE080A0 0x0FE080A8 0x0FE080B0 0x0FE080B8 0x0FE080C0 0x0FE080C8 0x0FE081AA 0x0FE081AB 0x0FE081AC 0x0FE081AD 0x0FE081AE 0x0FE081B0

Register

CMU_LFRCOCTRL CMU_HFRCOCTRL CMU_AUXHFRCOCTRL ADC0_CAL ADC0_BIASPROG DAC0_CAL DAC0_BIASPROG ACMP0_CTRL ACMP1_CTRL CMU_LCDCTRL DAC0_OPACTRL DAC0_OPAOFFSET EMU_BUINACT EMU_BUACT EMU_BUBODBUVINCAL EMU_BUBODUNREGCAL MCM_REV_MIN MCM_REV_MAJ RADIO_REV_MIN RADIO_REV_MAJ RADIO_OPN DI_CRC

Description

Register reset value.

Register reset value.

Register reset value.

Register reset value.

Register reset value.

Register reset value.

Register reset value.

Register reset value.

Register reset value.

Register reset value.

Register reset value.

Register reset value.

Register reset value.

Register reset value.

Register reset value.

Register reset value.

MCM minor revision (0, 1, 2, …).

MCM major revision (A=1, B=2, C=3, …).

Radio minor revision. (0, 1, 2, ...).

Radio major revision. (A = 1, B = 2, C = 3, …).

4 digit part number for the radio die. Example: EZR32WG330F256R67 => 4467d.

[15:0]: DI extra data CRC-16,Y,[15:0]: DI data CRC-16.

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DI Address

0x0FE081B2 0x0FE081B4 0x0FE081B6 0x0FE081B8 0x0FE081BA 0x0FE081BC 0x0FE081BE 0x0FE081C8 0x0FE081CC 0x0FE081D0 0x0FE081D4 0x0FE081D5 0x0FE081D6 0x0FE081D7 0x0FE081D8 0x0FE081D9 0x0FE081DC 0x0FE081DD 0x0FE081DE 0x0FE081DF 0x0FE081E0 0x0FE081E1 0x0FE081E7 0x0FE081EE 0x0FE081F0 0x0FE081F4 0x0FE081F8 0x0FE081FA 0x0FE081FC

Register

CAL_TEMP_0 ADC0_CAL_1V25 ADC0_CAL_2V5 ADC0_CAL_VDD ADC0_CAL_5VDIFF ADC0_CAL_2XVDD ADC0_TEMP_0_READ_1V25 DAC0_CAL_1V25 DAC0_CAL_2V5 DAC0_CAL_VDD AUXHFRCO_CALIB_BAND_1 AUXHFRCO_CALIB_BAND_7 AUXHFRCO_CALIB_BAND_11 AUXHFRCO_CALIB_BAND_14 AUXHFRCO_CALIB_BAND_21 AUXHFRCO_CALIB_BAND_28 HFRCO_CALIB_BAND_1 HFRCO_CALIB_BAND_7 HFRCO_CALIB_BAND_11 HFRCO_CALIB_BAND_14 HFRCO_CALIB_BAND_21 HFRCO_CALIB_BAND_28 MEM_INFO_PAGE_SIZE RADIO_ID EUI64_0 EUI64_0 MEM_INFO_FLASH MEM_INFO_RAM PART_NUMBER

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Description

[7:0] Calibration temperature (°C).

[14:8]: Gain for 1V25 reference, [6:0]: Offset for 1V25 reference.

[14:8]: Gain for 2V5 reference, [6:0]: Offset for 2V5 reference.

[14:8]: Gain for VDD reference, [6:0]: Offset for VDD reference.

[14:8]: Gain for 5VDIFF reference, [6:0]: Offset for 5VDIFF reference.

[14:8]: Reserved (gain for this reference cannot be calibrated), [6:0]: Offset for 2XVDD reference.

[15:4] Temperature reading at 1V25 reference, [3:0] Reserved.

[22:16]: Gain for 1V25 reference, [13:8]: Channel 1 offset for 1V25 reference, [5:0]: Channel 0 offset for 1V25 reference.

[22:16]: Gain for 2V5 reference, [13:8]: Channel 1 offset for 2V5 reference, [5:0]: Channel 0 offset for 2V5 reference.

[22:16]: Reserved (gain for this reference cannot be calibrated), [13:8]: Channel 1 offset for VDD reference, [5:0]: Channel 0 offset for VDD reference.

[7:0]: Tuning for the 1.2 MHZ AUXHFRCO band.

[7:0]: Tuning for the 6.6 MHZ AUXHFRCO band.

[7:0]: Tuning for the 11 MHZ AUXHFRCO band.

[7:0]: Tuning for the 14 MHZ AUXHFRCO band.

[7:0]: Tuning for the 21 MHZ AUXHFRCO band.

[7:0]: Tuning for the 28 MHZ AUXHFRCO band.

[7:0]: Tuning for the 1.2 MHZ HFRCO band.

[7:0]: Tuning for the 6.6 MHZ HFRCO band.

[7:0]: Tuning for the 11 MHZ HFRCO band.

[7:0]: Tuning for the 14 MHZ HFRCO band.

[7:0]: Tuning for the 21 MHZ HFRCO band.

[7:0]: Tuning for the 28 MHZ HFRCO band.

[7:0] Flash page size in bytes coded as 2 ^ ((MEM_INFO_PAGE_SIZE + 10) & 0xFF). Ie. the value 0xFF = 512 bytes.

RADIO_ID[15:0]: EZR32WG/EZR32LG = 1d.

EUI64[31:0]: EUI64[63:40] = 0x000B57 (IEEE-MA-L for Silicon Labs). EUI64[39:0] = Unique number.

EUI64[63:32]: EUI64[63:40] = 0x000B57 (IEEE-MA-L for Silicon Labs). EUI64[39:0] = Unique number.

[15:0]: Flash size, kbyte count as unsigned integer (eg.

128).

[15:0]: Ram size, kbyte count as unsigned integer (eg. 16).

[15:0]: EZR32 part number as unsigned integer (eg. 230).

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DI Address

0x0FE081FE 0x0FE081FF

Register

PART_FAMILY PROD_REV

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Description

[7:0]: EZR32 part family number (Gecko = 71, Giant Gecko = 72, Tiny Gecko = 73, Leopard Gecko=74, Wonder Gecko=75, EZR32WG=120, EZR32LG=121).

[7:0]: EZR32 Production ID.

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7 DBG - Debug Interface

0 1 2 3 4

ARM Cortex- M4 DBG Debug Data Quick Facts What?

The DBG (Debug Interface) is used to program and debug EZR32WG devices.

Why?

The Debug Interface makes it easy to re program and update the system in the field, and allows debugging with minimal I/O pin usage.

How?

The Cortex-M4 supports advanced debugging features. EZR32WG devices only use two port pins for debugging or programming. The internal and external state of the system can be examined with debug extensions supporting instruction or data access break- and watch points.

7.1 Introduction

The EZR32WG devices include hardware debug support through a 2-pin serial-wire debug (SWD) interface and an Embedded Trace Module (ETM) for data/instruction tracing. In addition, there is also a Serial Wire Viewer pin which can be used to output profiling information, data trace and software generated messages.

For more technical information about the debug interface the reader is referred to: • ARM Cortex-M4 Technical Reference Manual • ARM CoreSight Components Technical Reference Manual • ARM Debug Interface v5 Architecture Specification

7.2 Features

• Flash Patch and Breakpoint (FPB) unit • Implement breakpoints and code patches • Data Watch point and Trace (DWT) unit • Implement watch points, trigger resources and system profiling • Instrumentation Trace Macrocell (ITM) • Application-driven trace source that supports printf style debugging • Embedded Trace Macrocell v3.5 (ETM) • Real time instruction and data trace information of the processor

7.3 Functional Description

There are three debug pins and four trace pins available on the device. Operation of these pins are described in the following section.

7.3.1 Debug Pins

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• Serial Wire Clock input (SWCLK): This pin is enabled after reset and has a built-in pull down.

• Serial Wire Data Input/Output (SWDIO): This pin is enabled after reset and has a built-in pull-up.

• Serial Wire Viewer (SWV): This pin is disabled after reset.

The debug pins can be enabled and disabled through GPIO_ROUTE, see Section 32.3.4.1 (p. 734)

. Please remeberer that upon disabling, debug contact with the device is lost. Also note that, because the debug pins have pull-down and pull-up enabled by default, leaving them enabled might increase the current consumption with up to 200 µA if left connected to supply or ground.

7.3.2 Embedded Trace Macrocell v3.5 (ETM)

The ETM makes it possible to trace both instruction and data from the processor in real time. The trace can be controlled through a set of triggering and filtering resources. The resources include 4 address comparators, 2 data value comparators, 2 counters, a context ID comparator and a sequencer.

Before enabling the ETM, the AUXHFRCO clock needs to be enabled by setting AUXHFRCOEN in CMU_OSCENCMD. The trace can be exported through a set of trace pins, which include: • Trace Clock (TCLK): Functions as a sample clock for the trace. This pin is disabled after reset.

• Trace Data 0 - Trace Data 3 (TD0-TD3): The data pins provide the compressed trace stream. These pins are disabled after reset.

For information on how to configure the ETM, see the ARM Embedded Trace Macrocell Architecture Specification. The Trace Clock and Trace Data pins can be enabled through the GPIO. For more

information on how to enable the ETM Trace pins, the reader is referred to Section 32.3.4.2 (p. 734) .

7.3.3 Debug and EM2/EM3

Leaving the debugger connected when issuing a WFI or WFE to enter EM2 or EM3 will make the system enter a special EM2. This mode differs from regular EM2 and EM3 in that the high frequency clocks are still enabled, and certain core functionality is still powered in order to maintain debug-functionality.

Because of this, the current consumption in this mode is closer to EM1 and it is therefore important to disconnect the debugger before doing current consumption measurements.

7.4 Debug Lock and Device Erase

The debug access to the Cortex-M4 is locked by clearing the Debug Lock Word (DLW) and resetting

the device, see Section 8.3.2 (p. 74) .

When debug access is locked, the debug interface remains accessible but the connection to the Cortex-

M4 core and the whole bus-system is blocked as shown in Figure 7.2 (p. 69) . This mechanism is

controlled by the Authentication Access Port (AAP) as illustrated by Figure 7.1 (p. 68) . The AAP is

only accessible from a debugger and not from the core.

Figure 7.1. AAP - Authentication Access Port

DEVICEERASE ERASEBUSY SerialWire debug int erface SW- DP Aut hent icat ion Access Port (AAP) DLW[3:0] = = 0x F

Cortex

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The debugger can access the AAP-registers, and only these registers just after reset, for the time of the

AAP-window outlined in Figure 7.2 (p. 69) . If the device is locked, access to the core and bus-system

is blocked even after code execution starts, and the debugger can only access the AAP-registers. If the device is not locked, the AAP is no longer accessible after code execution starts, and the debugger can access the core and bus-system normally.

Figure 7.2. Device Unlock

Reset Locked No access 150 us Unlocked No access AAP Program ex ecut ion Program ex ecut ion AAP Cort ex 47 us If the device is locked, it can be unlocked by writing a valid key to the AAP_CMDKEY register and then setting the DEVICEERASE bit of the AAP_CMD register via the debug interface. The commands are not executed before AAP_CMDKEY is invalidated, so this register should be cleared to to start the erase operation. This operation erases the main block of flash, all lock bits are reset and debug access through the AHB-AP is enabled. The operation takes 125 ms to complete. Note that the SRAM contents will also be deleted during a device erase, while the UD-page is not erased.

Even if the device is not locked, the can device can be erased through the AAP, using the above procedure during the AAP window. This can be useful if the device has been programmed with code that, e.g., disables the debug interface pins on start-up, or does something else that prevents communication with a debugger.

If the device is locked, the debugger may read the status from the AAP_STATUS register. When the ERASEBUSY bit is set low after DEVICEERASE of the AAP_CMD register is set, the debugger may set the SYSRESETREQ bit in the AAP_CMD register. After reset, the debugger may resume a normal debug session through the AHB-AP. If the device is not locked, the device erase starts when the AAP window closes, so it is not possible to poll the status.

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7.5 Register Map

The offset register address is relative to the registers base address.

Offset

0x000 0x004

0x008 0x0FC

Name

AAP_CMD AAP_CMDKEY

AAP_STATUS AAP_IDR

Type

W1 W1 R R

Description

Command Register Command Key Register

Status Register AAP Identification Register

7.6 Register Description

7.6.1 AAP_CMD - Command Register

Offset

0x000

Reset Access Bit Position Name Bit

31:2

1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SYSRESETREQ 0 W1

System Reset Request

A system reset request is generated when set to 1. This register is write enabled from the AAP_CMDKEY register.

DEVICEERASE 0 W1

Erase the Flash Main Block, SRAM and Lock Bits

When set, all data and program code in the main block is erased, the SRAM is cleared and then the Lock Bit (LB) page is erased.

This also includes the Debug Lock Word (DLW), causing debug access to be enabled after the next reset. The information block User Data page (UD) is left unchanged, but the User data page Lock Word (ULW) is erased. This register is write enabled from the AAP_CMDKEY register.

7.6.2 AAP_CMDKEY - Command Key Register

Offset

0x004

Bit Position Reset Access Name Bit

31:0

Name

WRITEKEY

Reset

0x00000000

Access

W1

Description CMD Key Register

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Bit

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Name Reset Access Description

The key value must be written to this register to write enable the AAP_CMD register. After AAP_CMD is written, this register should be cleared to excecute the command.

Value 0xCFACC118 Mode WRITEEN Description Enable write to AAP_CMD

7.6.3 AAP_STATUS - Status Register

Offset

0x008

Reset Access Bit Position Name Bit

31:1

0

Name

Reserved

ERASEBUSY

Reset

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 This bit is set when a device erase is executing.

Access

R

Description Device Erase Command Status

7.6.4 AAP_IDR - AAP Identification Register

Offset

0x0FC

Bit Position Reset Access Name Bit

31:0

Name Reset Access Description

ID 0x16E60001 R

AAP Identification Register

Access port identification register in compliance with the ARM ADI v5 specification (JEDEC Manufacturer ID) .

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8 MSC - Memory System Controller

0 1 2 3 4

01000101011011100110010101110010 01100111011110010010000001001101 01101001011000110111001001101111 00100000011100100111010101101100 01100101011100110010000001110100 01101000011001010010000001110111 01101111011100100110110001100100 00100000011011110110011000100000 01101100011011110111011100101101 01100101011011100110010101110010 01100111011110010010000001101101 01101001011000110111001001101111 01100011011011110110111001110100 01110010011011110110110001101100 01100101011100100010000001100100 01100101011100110110100101100111 01101110001000010100010101101110

Quick Facts What?

The user can perform Flash memory read, read configuration and write operations through the Memory System Controller (MSC) .

Why?

The MSC allows the application code, user data and flash lock bits to be stored in non volatile Flash memory. Certain memory system functions, such as program memory wait-states and bus faults are also configured from the MSC peripheral register interface, giving the developer the ability to dynamically customize the memory system performance, security level, energy consumption and error handling capabilities to the requirements at hand.

How?

The MSC integrates a low-energy Flash IP with a charge pump, enabling minimum energy consumption while eliminating the need for external programming voltage to erase the memory. An easy to use write and erase interface is supported by an internal, fixed-frequency oscillator and autonomous flash timing and control reduces software complexity while not using other timer resources.

Application code may dynamically scale between high energy optimization and high code execution performance through advanced read modes.

A highly efficient low energy instruction cache reduces the number of flash reads significantly, thus saving energy.

Performance is also improved when wait states are used, since many of the wait-states are eliminated. Built-in performance counters can be used to measure the efficiency of the instruction cache.

8.1 Introduction

The Memory System Controller (MSC) is the program memory unit of the EZR32WG microcontroller.

The flash memory is readable and writable from both the Cortex-M4 and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock bits.

There is also a read-only page in the information block containing system and device calibration data.

Read and write operations are supported in the energy modes EM0 and EM1.

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8.2 Features

• AHB read interface • Scalable access performance to optimize the Cortex-M4 code interface • Zero wait-state access up to 16 MHz and one wait-state for up to 32 MHz and two wait-states for up to 48 MHz MHz • Advanced energy optimization functionality • Conditional branch target prefetch suppression • Cortex-M4 disfolding of if-then (IT) blocks • Instruction Cache • DMA read support in EM0 and EM1 • Command and status interface • Flash write and erase • Accessible from Cortex-M4 in EM0 • DMA write support in EM0 and EM1 • Core clock independent Flash timing • Internal oscillator and internal timers for precise and autonomous Flash timing • General purpose timers are not occupied during Flash erase and write operations • Configurable interrupt erase abort • Improved interrupt predictability • Memory and bus fault control • Security features • Lockable debug access • Page lock bits • SW Mass erase Lock bits • User data lock bits • End-of-write and end-of-erase interrupts

8.3 Functional Description

The size of the main block is device dependent. The largest size available is 256 kB (128 pages).

The information block has 2048 bytes available for user data. The information block also contains chip configuration data located in a reserved area. The main block is mapped to address 0x00000000 and

the information block is mapped to address 0x0FE00000. Table 8.1 (p. 74) outlines how the Flash

is mapped in the memory space. All Flash memory is organized into 2048 byte pages.

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...the world's most energy friendly wireless MCUs Table 8.1. MSC Flash Memory Mapping

Block

Main 1 Reserved

Page

.

0 127

Base address

0x00000000

Write/Erase by

Software, debug Yes Software, debug

Software readable

Yes 0x0003F800 0x00040000 Software, debug Yes

Purpose/Name

User code and data

Size

64 kB - 256 kB ~24 MB Information Reserved 2 0 1 0x0FE00000 0x0FE00800 0x0FE04000 0x0FE04800 0x0FE08000 0x0FE08800 0x0FE10000 Software, debug Yes Write: Software, debug Yes Erase: Debug only Yes Reserved for flash expansion User Data (UD) Reserved Lock Bits (LB) Reserved Device Information (DI) Reserved Reserved for flash expansion 2 kB 2 kB 2 kB Rest of code space 1 Block/page erased by a device erase

8.3.1 User Data (UD) Page Description

This is the user data page in the information block. The page can be erased and written by software. The page is erased by the ERASEPAGE command of the MSC_WRITECMD register. Note that the page is

not erased by a device erase operation. The device erase operation is described in Section 7.4 (p. 68) .

8.3.2 Lock Bits (LB) Page Description

This page contains the following information: • Debug Lock Word (DLW) • User data page Lock Word (ULW) • Mass erase Lock Word (MLW) • Main block Page Lock Words (PLWs)

The words in this page are organized as shown in Table 8.2 (p. 74) :

Table 8.2. Lock Bits Page Structure

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Word 127 is the debug lock word (DLW). The four LSBs of this word are the debug lock bits. If these bits are 0xF, then debug access is enabled. If the bits are not 0xF, then debug access to the core is locked.

See Section 7.4 (p. 68) for details on how to unlock the debug access.

Word 126 is the user page lock word (ULW). Bit 0 of this word is the User Data Page lock bit. Bit 1 in this word locks the Lock Bits Page.

Word 125 is the mass erase lock word (MLW). Bit 0 locks the entire flash. The mass erase lock bits will not have any effect on device erases initiated from the Authentication Access Port (AAP) registers. The

AAP is described in more detail in Section 7.4 (p. 68) .

There are 32 page lock bits per page lock word (PLW). Bit 0 refers to the first page and bit 31 refers to the last page within a PLW. Thus, PLW[0] contains lock bits for page 0-31 in the main block. Similarly, PLW[1] contains lock bits for page 32-63 and so on. A page is locked when the bit is 0. A locked page cannot be erased or written.

The lock bits can be reset by a device erase operation initiated from the Authentication Access Port

(AAP) registers. The AAP is described in more detail in Section 7.4 (p. 68) . Note that the AAP is only

accessible from the debug interface, and cannot be accessed from the Cortex-M4 core.

8.3.3 Device Information (DI) Page

This read-only page holds the calibration data for the oscillator and other analog peripherals from the

production test as well as a unique device ID. The page is further described in Section 6.6 (p. 64) .

8.3.4 Post-reset Behavior

Calibration values are automatically written to registers by the MSC before application code startup. The values are also available to read from the DI page for later reference by software. Other information such as the device ID and production date is also stored in the DI page and is readable from software.

8.3.4.1 One Wait-state Access

After reset, the HFCORECLK is normally 14 MHz from the HFRCO and the MODE field of the MSC_READCTRL register is set to WS1 (one wait-state). The reset value must be WS1 as an uncalibrated HFRCO may produce a frequency higher than 16 MHz. Software must not select a zero wait-state mode unless the clock is guaranteed to be 16 MHz or below, otherwise the resulting behavior is undefined. If a HFCORECLK frequency above 16 MHz is to be set by software, the MODE field of the MSC_READCTRL register must be set to WS1 or WS1SCBTP before the core clock is switched to the higher frequency clock source.

When changing to a lower frequency, the MODE field of the MSC_READCTRL register can be set to WS0 or WS0SCBTP, but only after the frequency transition is completed. If the HFRCO is used, wait until the oscillator is stable on the new frequency. Otherwise, the behavior is unpredictable.

To run at a frequency higher than 32 MHz, WS2 or WS2SCBTP must be selected to insert two wait states for every flash access.

8.3.4.2 Zero Wait-state Access

At 16 MHz and below, read operations from flash may be performed without any wait-states. Zero wait state access greatly improves code execution performance at frequencies from 16 MHz and below.

By default, the Cortex-M4 uses speculative prefetching and If-Then block folding to maximize code execution performance at the cost of additional flash accesses and energy consumption.

8.3.4.3 Operation Above 32 MHz

To run at frequencies higher than 32 MHz, MODE in MSC_READCTRL must be set to WS2 or WS2SCBTP.

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8.3.4.4 Suppressed Conditional Branch Target Prefetch (SCBTP)

MSC offers a special instruction fetch mode which optimizes energy consumption by cancelling Cortex M4 conditional branch target prefetches. Normally, the Cortex-M4 core prefetches both the next sequential instruction and the instruction at the branch target address when a conditional branch instruction reaches the pipeline decode stage. This prefetch scheme improves performance while one extra instruction is fetched from memory at each conditional branch, regardless of whether the branch is taken or not. To optimize for low energy, the MSC can be configured to cancel these speculative branch target prefetches. With this configuration, energy consumption is more optimal, as the branch target instruction fetch is delayed until the branch condition is evaluated.

The performance penalty with this mode enabled is source code dependent, but is normally less than 1% for core frequencies from 16 MHz and below. To enable the mode at frequencies from 16 MHz and below write WS0SCBTP to the MODE field of the MSC_READCTRL register. For frequencies above 16 MHz, use the WS1SCBTP mode, and for frequencies above 32 MHz, use the WS2SCBTP mode. An increased performance penalty per clock cycle must be expected compared to WS0SCBTP mode. The performance penalty in WS1SCBTP/WS2SCBTP mode depends greatly on the density and organization of conditional branch instructions in the code.

8.3.4.5 Cortex-M4 If-Then Block Folding

The Cortex-M4 offers a mechanism known as if-then block folding. This is a form of speculative prefetching where small if-then blocks are collapsed in the prefetch buffer if the condition evaluates to false. The instructions in the block then appear to execute in zero cycles. With this scheme, performance is optimized at the cost of higher energy consumption as the processor fetches more instructions from memory than it actually executes. To disable the mode, write a 1 to the DISFOLD bit in the NVIC Auxiliary Control Register; see the Cortex-M4 Technical Reference Manual for details. Normally, it is expected that this feature is most efficient at core frequencies above 16 MHz. Folding is enabled by default.

8.3.4.6 Instruction Cache

The MSC includes an instruction cache. The instruction cache for the internal flash memory is enabled by default, but can be disabled by setting IFCDIS in MSC_READCTRL. When enabled, the instruction cache typically reduces the number of flash reads significantly, thus saving energy. In most cases a cache hit-rate of more than 70 % is achievable. When a 32-bit instruction fetch hits in the cache the data is returned to the processor in one clock cycle. Thus, performance is also improved when wait-states are used (i.e. running at frequencies above 16 MHz).

The instruction cache is connected directly to the Cortex-M4 and functions as a memory access filter

between the processor and the memory system, as illustrated in Figure 8.1 (p. 77) . The cache

consists of an access filter, lookup logic, a 128x32 SRAM (512 bytes) and two performance counters.

The access filter checks that the address for the access is of an instruction in the code space (instructions in RAM outside the code space are not cached). If the address matches, the cache lookup logic and SRAM is enabled. Otherwise, the cache is bypassed and the access is forwarded to the memory system.

The cache is then updated when the memory access completes. The access filter also disables cache updates for interrupt context accesses if caching in interrupt context is disabled. The performance counters, when enabled, keep track of the number of cache hits and misses. The cache consists of 16 8-word cachelines organized as 4 sets with 4 ways. The cachelines are filled up continuously one word at a time as the individual words are requested by the processor. Thus, not all words of a cacheline might be valid at a given time.

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...the world's most energy friendly wireless MCUs Figure 8.1. Instruction Cache

Cort ex ICODE AHB- Lit e Bus Inst ruct ion Cache Cache Look- up Logic Access Filt er 128x 32 SRAM Perform ance Count ers ICODE AHB- Lit e Bus IDCODE MUX IDCODE AHB- Lit e Bus CODE Mem ory Space DCODE AHB- Lit e Bus By default, the instruction cache is automatically invalidated when the contents of the flash is changed (i.e. written or erased). In many cases, however, the application only makes changes to data in the flash, not code. In this case, the automatic invalidate feature can be disabled by setting AIDIS in MSC_READCTRL. The cache can (independent of the AIDIS setting) be manually invalidated by writing 1 to INVCACHE in MSC_CMD.

In general it is highly recommended to keep the cache enabled all the time. However, for some sections of code with very low cache hit-rate more energy-efficient execution can be achieved by disabling the cache temporarily. To measure the hit-rate of a code-section, the built-in performance counters can be used. Before the section, start the performance counters by writing 1 to STARTPC in MSC_CMD.

This starts the performance counters, counting from 0. At the end of the section, stop the performance counters by writing 1 to STOPPC in MSC_CMD. The number of cache hits and cache misses for that section can then be read from MSC_CACHEHITS and MSC_CACHEMISSES respectively. The total number of 32-bit instruction fetches will be MSC_CACHEHITS + MSC_CACHEMISSES. Thus, the cache hit-ratio can be calculated as MSC_CACHEHITS / (MSC_CACHEHITS + MSC_CACHEMISSES).

When MSC_CACHEHITS overflows the CHOF interrupt flag is set. When MSC_CACHEMISSES overflows the CMOF interrupt flag is set. These flags must be cleared explicitly by software. The range of the performance counters can thus be extended by increasing a counter in the MSC interrupt routine. The performance counters only count when a cache lookup is performed. If the lookup fails, MSC_CACHEMISSES is increased. If the lookup is successful, MSC_CACHEHITS is increased. For example, a cache lookup is not performed if the cache is disabled or the code is executed from RAM outside the code space. When caching of vector fetches and instructions in interrupt routines is disabled (ICCDIS in MSC_READCTRL is set), the performance counters do not count when these types of fetches occur (i.e. while in interrupt context).

By default, interrupt vector fetches and instructions in interrupt routines are also cached. Some applications may get better cache utilization by not caching instructions in interrupt context. This is done by setting ICCDIS in MSC_READCTRL. You should only set this bit based on the results from a cache hit ratio measurement. In general, it is recommended to keep the ICCDIS bit cleared. Note that lookups in the cache are still performed, regardless of the ICCDIS setting - but instructions are not cached when cache misses occur inside the interrupt routine. So, for example, if a cached function is called from the interrupt routine, the instructions for that function will be taken from the cache.

The cache content is not retained in EM2, EM3 and EM4. The cache is therefore invalidated regardless of the setting of AIDIS in MSC_READCTRL when entering these energy modes. Applications that switch frequently between EM0 and EM2/3 and execute the very same non-looping code almost every time will most likely benefit from putting this code in RAM. The interrupt vectors can also be put in RAM to reduce current consumption even further.

The cache also supports caching of instruction fetches from the external bus interface (EBI) when accessing the EBI through code space. By default, this is enabled, but it can be disabled by setting EBICDIS in MSC_READCTRL.

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8.3.5 Erase and Write Operations

The AUXHFRCO is used for timing during flash write and erase operations. To achieve correct timing, the MSC_TIMEBASE register has to be configured according to the settings in CMU_AUXHFRCOCTRL.

BASE in MSC_TIMEBASE defines how many AUXCLK cycles - 1 there is in 1 us or 5 us, depending on the configuration of PERIOD. To ensure that timing of flash write and erase operations is within the specification of the flash, the value written to BASE should give at least a 10% margin with respect to the period, i.e. for the 1 us PERIOD, the number of cycles should at least span 1.1 us, and for the 5 us period they should span at least 5.5 us. For the 1 MHz band, PERIOD in MSC_TIMEBASE should be set to 5US, while it should be set to 1US for all other AUXHFRCO bands.

Both page erase and write operations require that the address is written into the MSC_ADDRB register.

For erase operations, the address may be any within the page to be erased. Load the address by writing 1 to the LADDRIM bit in the MSC_WRITECMD register. The LADDRIM bit only has to be written once when loading the first address. After each word is written the internal address register ADDR will be incremented automatically by 4. The INVADDR bit of the MSC_STATUS register is set if the loaded address is outside the flash and the LOCKED bit of the MSC_STATUS register is set if the page addressed is locked. Any attempts to command erase of or write to the page are ignored if INVADDR or the LOCKED bits of the MSC_STATUS register are set. To abort an ongoing erase, set the ERASEABORT bit in the MSC_WRITECMD register.

When a word is written to the MSC_WDATA register, the WDATAREADY bit of the MSC_STATUS register is cleared. When this status bit is set, software or DMA may write the next word.

A single word write is commanded by setting the WRITEONCE bit of the MSC_WRITECMD register.

The operation is complete when the BUSY bit of the MSC_STATUS register is cleared and control of the flash is handed back to the AHB interface, allowing application code to resume execution.

For a DMA write the software must write the first word to the MSC_WDATA register and then set the WRITETRIG bit of the MSC_WRITECMD register. DMA triggers when the WDATAREADY bit of the MSC_STATUS register is set.

It is possible to write words twice between each erase by keeping at 1 the bits that are not to be changed.

Let us take as an example writing two 16 bit values, 0xAAAA and 0x5555. To safely write them in the same flash word this method can be used: • Write 0xFFFFAAAA (word in flash becomes 0xFFFFAAAA) • Write 0x5555FFFF (word in flash becomes 0x5555AAAA) Note that there is a maximum of two writes to the same word between each erase due to a physical limitation of the flash.

Note

During a write or erase, flash read accesses will be stalled, effectively halting code execution from flash. Code execution continues upon write/erase completion. Code residing in RAM may be executed during a write/erase operation.

Note

The MSC_WDATA and MSC_ADDRB registers are not retained when entering EM2 or lower energy modes.

8.3.5.1 Mass erase

A mass erase can be initiated from software using ERASEMAIN0 in MSC_WRITECMD. This command will start a mass erase of the entire flash. Prior to initiating a mass erase, MSC_MASSLOCK must be unlocked by writing 0x631A to it. After a mass erase has been started, this register can be locked again to prevent runaway code from accidentally triggering a mass erase.

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The regular flash page lock bits will not prevent a mass erase. To prevent software from initiating mass erases, use the mass erase lock bits in the mass erase lock word (MLW).

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8.4 Register Map

The offset register address is relative to the registers base address.

Offset

0x000

0x004

0x008 0x00C

0x010 0x018

0x01C 0x02C

0x030 0x034

0x038 0x03C

0x040 0x044

0x048 0x050

0x054

Name

MSC_CTRL

MSC_READCTRL

MSC_WRITECTRL MSC_WRITECMD

MSC_ADDRB MSC_WDATA

MSC_STATUS MSC_IF

MSC_IFS MSC_IFC

MSC_IEN MSC_LOCK

MSC_CMD MSC_CACHEHITS

MSC_CACHEMISSES MSC_TIMEBASE

MSC_MASSLOCK

Type

R R RW RW RW RW RW W1 RW RW R R W1 W1 RW RW W1

Description

Memory System Control Register

Read Control Register

Write Control Register Write Command Register

Page Erase/Write Address Buffer Write Data Register

Status Register Interrupt Flag Register

Interrupt Flag Set Register Interrupt Flag Clear Register

Interrupt Enable Register Configuration Lock Register

Command Register Cache Hits Performance Counter

Cache Misses Performance Counter Flash Write and Erase Timebase

Mass Erase Lock Register

8.5 Register Description

8.5.1 MSC_CTRL - Memory System Control Register

Offset

0x000

Reset Access Bit Position Name Bit

31:1

0

Name Reset Access Description

Reserved

Value 0 1 Mode GENERATE IGNORE

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BUSFAULT 1 RW

Bus Fault Response Enable

When this bit is set, the memory system generates bus error response.

Description A bus fault is generated on access to unmapped code and system space.

Accesses to unmapped address space is ignored.

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8.5.2 MSC_READCTRL - Read Control Register

Offset

0x004

Reset Access Bit Position Name Bit

31:18

17:16

15:8

7 6 5 4 3 2:0

Name Reset Access Description

Reserved

BUSSTRATEGY

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 RW Specify which master has low latency to bus matrix.

Strategy for bus matrix

Value 0 1 2 3 Mode CPU DMA DMAEM1 NONE

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RAMCEN 0 RW Enable instruction caching for RAM in code-space.

EBICDIS 0 RW Disable instruction cache for external bus interface.

RAM Cache Enable External Bus Interface Cache Disable

ICCDIS 0 RW

Interrupt Context Cache Disable

Set this bit to automatically disable caching of vector fetches and instruction fetches in interrupt context. Cache lookup will still be performed in interrupt context. When set, the performance counters will not count when these types of fetches occur.

AIDIS 0 RW

Automatic Invalidate Disable

When this bit is set the cache is not automatically invalidated when a write or page erase is performed.

IFCDIS 0 RW Disable instruction cache for internal flash memory.

Internal Flash Cache Disable

MODE 0x1 RW

Read Mode

If software wants to set a core clock frequency above 16 MHz, this register must be set to WS1 or WS1SCBTP before the core clock is switched to the higher frequency. When changing to a lower frequency, this register can be set to WS0 or WS0SCBTP after the frequency transition has been completed. After reset, the core clock is 14 MHz from the HFRCO but the MODE field of MSC_READCTRL register is set to WS1. This is because the HFRCO may produce a frequency above 16 MHz before it is calibrated.

If the HFRCO is used as clock source, wait until the oscillator is stable on the new frequency to avoid unpredictable behavior.

Value 0 1 2 3 4 5 Mode WS0 WS1 WS0SCBTP WS1SCBTP WS2 WS2SCBTP Description Description Zero wait-states inserted in fetch or read transfers.

One wait-state inserted for each fetch or read transfer. This mode is required for a core frequency above 16 MHz.

Zero wait-states inserted with the Suppressed Conditional Branch Target Prefetch (SCBTP) function enabled. SCBTP saves energy by delaying the Cortex' conditional branch target prefetches until the conditional branch instruction is in the execute stage.

When the instruction reaches this stage, the evaluation of the branch condition is completed and the core does not perform a speculative prefetch of both the branch target address and the next sequential address. With the SCBTP function enabled, one instruction fetch is saved for each branch not taken, with a negligible performance penalty.

One wait-state access with SCBTP enabled.

Two wait-states inserted for each fetch or read transfer. This mode is required for a core frequency above 32 MHz.

Two wait-state access with SCBTP enabled.

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8.5.3 MSC_WRITECTRL - Write Control Register

Bit Position Offset

0x008

Reset Access Name Bit

31:2

1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

IRQERASEABORT 0 RW

Abort Page Erase on Interrupt

When this bit is set to 1, any Cortex interrupt aborts any current page erase operation.

WREN 0 RW

Enable Write/Erase Controller

When this bit is set, the MSC write and erase functionality is enabled.

8.5.4 MSC_WRITECMD - Write Command Register

Bit Position Offset

0x00C

Reset Access Name Bit

31:13

12

11:9

8

7:6

5 4 3

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CLEARWDATA 0 W1

Clear WDATA state

Will set WDATAREADY and DMA request. Should only be used when no write is active.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

ERASEMAIN0 0 W1

Mass erase region 0

Initiate mass erase of region 0. For devices supporting read-while-write, this is the lower half of the flash. For other devices it is the entire flash. Before use MSC_MASSLOCK must be unlocked. To completely prevent access from software, clear bit 0 in the mass erase lock-word (MLW).

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

ERASEABORT 0 W1 Writing to this bit will abort an ongoing erase sequence.

Abort erase sequence

WRITETRIG 0 W1

Word Write Sequence Trigger

Functions like MSC_CMD_WRITEONCE, but will set MSC_STATUS_WORDTIMEOUT if no new data is written to MSC_WDATA within the 30 µs timeout.

WRITEONCE 0 W1

Word Write-Once Trigger

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2 1 0

Bit

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Name Reset Access Description

Start write of the first word written to MSC_WDATA, then add 4 to ADDR and write the next word if available within a 30 µs timeout.

When ADDR is incremented past the page boundary, ADDR is set to the base of the page.

WRITEEND 0 W1

End Write Mode

Write 1 to end write mode when using the WRITETRIG command.

ERASEPAGE 0 W1

Erase Page

Erase any user defined page selected by the MSC_ADDRB register. The WREN bit in the MSC_WRITECTRL register must be set in order to use this command.

LADDRIM 0 W1

Load MSC_ADDRB into ADDR

Load the internal write address register ADDR from the MSC_ADDRB register. The internal address register ADDR is incremented automatically by 4 after each word is written. When ADDR is incremented past the page boundary, ADDR is set to the base of the page.

8.5.5 MSC_ADDRB - Page Erase/Write Address Buffer

Offset

0x010

Bit Position Reset Access Name Bit

31:0

Name Reset Access Description

ADDRB 0x00000000 RW

Page Erase or Write Address Buffer

This register holds the page address for the erase or write operation. This register is loaded into the internal MSC_ADDR register when the LADDRIM field in MSC_WRITECMD is set. The MSC_ADDR register is not readable. This register is not retained when entering EM2 or lower energy modes.

8.5.6 MSC_WDATA - Write Data Register

Offset

0x018

Bit Position Reset Access Name Bit

31:0

Name

WDATA

Reset

0x00000000

Access

RW

Description Write Data

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Bit

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Name Reset Access Description

The data to be written to the address in MSC_ADDR. This register must be written when the WDATAREADY bit of MSC_STATUS is set. This register is not retained when entering EM2 or lower energy modes.

8.5.7 MSC_STATUS - Status Register

Offset

0x01C

Reset Access Bit Position Name

2 1 0 5 4

Bit

31:7

6 3

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PCRUNNING 0 R

Performance Counters Running

This bit is set while the performance counters are running. When one performance counter reaches the maximum value, this bit is cleared.

ERASEABORTED 0 R

The Current Flash Erase Operation Aborted

When set, the current erase operation was aborted by interrupt.

WORDTIMEOUT 0 R

Flash Write Word Timeout

When this bit is set, MSC_WDATA was not written within the timeout. The flash write operation timed out and access to the flash is returned to the AHB interface. This bit is cleared when the ERASEPAGE, WRITETRIG or WRITEONCE commands in MSC_WRITECMD are triggered.

WDATAREADY 1 R

WDATA Write Ready

When this bit is set, the content of MSC_WDATA is read by MSC Flash Write Controller and the register may be updated with the next 32-bit word to be written to flash. This bit is cleared when writing to MSC_WDATA.

INVADDR 0 R

Invalid Write Address or Erase Page

Set when software attempts to load an invalid (unmapped) address into ADDR.

LOCKED 0 R

Access Locked

When set, the last erase or write is aborted due to erase/write access constraints.

BUSY 0 R

Erase/Write Busy

When set, an erase or write operation is in progress and new commands are ignored.

8.5.8 MSC_IF - Interrupt Flag Register

Offset

0x02C

Reset Access Bit Position Name Bit

31:4

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

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1 0

Bit

3 2

Name Reset

CMOF 0 Set when MSC_CACHEMISSES overflows.

CHOF 0 Set when MSC_CACHEHITS overflows.

WRITE Set when a write is done.

0 ERASE Set when erase is done.

0

Access

R R R R

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Description Cache Misses Overflow Interrupt Flag Cache Hits Overflow Interrupt Flag Write Done Interrupt Read Flag Erase Done Interrupt Read Flag

8.5.9 MSC_IFS - Interrupt Flag Set Register

Bit Position Offset

0x030

Reset Access Name

2 1 0

Bit

31:4

3

Name Reset Access Description

Reserved

CMOF

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Set the CMOF flag and generate interrupt.

CHOF 0 Set the CHOF flag and generate interrupt.

W1 W1

Cache Misses Overflow Interrupt Set Cache Hits Overflow Interrupt Set

WRITE 0 Set the write done bit and generate interrupt.

W1 ERASE 0 Set the erase done bit and generate interrupt.

W1

Write Done Interrupt Set Erase Done Interrupt Set

8.5.10 MSC_IFC - Interrupt Flag Clear Register

Bit Position Offset

0x034

Reset Access Name Bit

31:4

3

Name

Reserved

CMOF

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 W1

Cache Misses Overflow Interrupt Clear

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Bit

2 1 0

Name Reset

Clear the CMOF interrupt flag.

CHOF 0 Clear the CHOF interrupt flag.

WRITE Clear the write done bit.

0 ERASE Clear the erase done bit.

0

Access

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Description

W1 W1 W1

Cache Hits Overflow Interrupt Clear Write Done Interrupt Clear Erase Done Interrupt Clear

8.5.11 MSC_IEN - Interrupt Enable Register

Offset

0x038

Reset Access Bit Position Name

1 0

Bit

31:4

3 2

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CMOF 0 RW

Cache Misses Overflow Interrupt Enable

Enable the cache misses performance counter overflow interrupt.

CHOF 0 RW Enable the cache hits performance counter overflow interrupt.

Cache Hits Overflow Interrupt Enable

WRITE 0 Enable the write done interrupt.

RW

Write Done Interrupt Enable

ERASE 0 Enable the erase done interrupt.

RW

Erase Done Interrupt Enable

8.5.12 MSC_LOCK - Configuration Lock Register

Offset

0x03C

Bit Position Reset Access Name Bit

31:16

15:0

Name

Reserved

LOCKKEY

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0000 RW

Configuration Lock

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Bit

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Name Reset Access Description

Write any other value than the unlock code to lock access to MSC_CTRL, MSC_READCTRL, MSC_WRITECTRL and MSC_TIMEBASE. Write the unlock code to enable access. When reading the register, bit 0 is set when the lock is enabled.

Mode Read Operation UNLOCKED LOCKED Write Operation LOCK UNLOCK Value 0 1 0 0x1B71 Description MSC registers are unlocked.

MSC registers are locked.

Lock MSC registers.

Unlock MSC registers.

8.5.13 MSC_CMD - Command Register

Offset

0x040

Reset Access Bit Position Name Bit

31:3

2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

STOPPC 0 W1 Use this command bit to stop the performance counters.

INVCACHE 0 W1 Use this register to invalidate the instruction cache.

Stop Performance Counters

STARTPC 0 W1

Start Performance Counters

Use this command bit to start the performance counters. The performance counters always start counting from 0.

Invalidate Instruction Cache

8.5.14 MSC_CACHEHITS - Cache Hits Performance Counter

Offset

0x044

Bit Position Reset Access Name Bit

31:20

19:0

Name

Reserved

CACHEHITS

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x00000 R

Cache hits since last performance counter start command.

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Bit

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Name Reset Access Description

Use to measure cache performance for a particular code section.

8.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter

Offset

0x048

Bit Position Reset Access Name Bit

31:20

19:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CACHEMISSES 0x00000 R

Cache misses since last performance counter start command.

Use to measure cache performance for a particular code section.

8.5.16 MSC_TIMEBASE - Flash Write and Erase Timebase

Offset

0x050

Reset Access Bit Position Name Bit

31:17

16

15:6

5:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PERIOD 0 RW

Sets the timebase period

Decides whether TIMEBASE specifies the number of AUX cycles in 1 us or 5 us. 5 us should only be used with 1 MHz AUXHFRCO band.

Value 0 1 Mode 1US 5US Description TIMEBASE period is 1 us.

TIMEBASE period is 5 us.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BASE 0x10 RW

Timebase used by MSC to time flash writes and erases

Should be set to the number of full AUX clock cycles in the period given by MSC_TIMEBASE_PERIOD. I.e. 1.1 us or 5.5. us with PERIOD cleared or set, respectively. The resetvalue of the timebase matches a 14 MHz AUXHFRCO, which is the default frequency of the AUXHFRCO.

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8.5.17 MSC_MASSLOCK - Mass Erase Lock Register

Offset

0x054

Bit Position Reset Access Name Bit

31:16

15:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LOCKKEY 0x0001 RW

Mass Erase Lock

Write any other value than the unlock code to lock access the the ERASEMAIN0 and ERASEMAIN1 commands. Write the unlock code 631A to enable access. When reading the register, bit 0 is set when the lock is enabled. Locked by default.

Mode Read Operation UNLOCKED LOCKED Write Operation LOCK UNLOCK Value 0 1 0 0x631A Description Mass erase unlocked.

Mass erase locked.

Lock mass erase.

Unlock mass erase.

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9 DMA - DMA Controller

0 1 2 3 4

DMA cont roller Flash RAM Peripherals

Quick Facts What?

The DMA controller can move data without CPU intervention, effectively reducing the energy consumption for a data transfer.

Why?

The DMA can perform data transfers more energy efficiently than the CPU and allows autonomous operation in low energy modes.

The LEUART can for instance provide full UART communication in EM2, consuming only a few µA by using the DMA to move data between the LEUART and RAM.

How?

The DMA controller has multiple highly configurable, prioritized DMA channels.

Advanced transfer modes such as ping-pong and scatter-gather make it possible to tailor the controller to the specific needs of an application.

9.1 Introduction

The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.

This has the benefit of reducing the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes for example when moving data from the USART to RAM. The DMA controller uses the PL230 µDMA controller licensed from ARM 1 . Each of the PL230s channels on the EZR32 can be connected to any of the EZR32 peripherals.

9.2 Features

• The DMA controller is accessible as a memory mapped peripheral • Possible data transfers include • RAM/Flash to peripheral • RAM to Flash • Peripheral to RAM • RAM/Flash to RAM • The DMA controller has 12 independent channels • Each channel has one (primary) or two (primary and alternate) descriptors • The configuration for each channel includes • Transfer mode • Priority • Word-count • Word-size (8, 16, 32 bit) • The transfer modes include • Basic (using the primary or alternate DMA descriptor) 1 ARM PL230 homepage [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0417a/index.html] 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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• Ping-pong (switching between the primary or alternate DMA descriptors, for continuous data flow to/from peripherals) • Scatter-gather (using the primary descriptor to configure the alternate descriptor) • Each channel has a programmable transfer length • Channels 0 and 1 support looped transfers • Channel 0 supports 2D copy • A DMA channel can be triggered by any of several sources: • Communication modules (USART, UART, LEUART) • Timers (TIMER) • Analog modules (DAC, ACMP, ADC) • Software • Programmable mapping between channel number and peripherals - any DMA channel can be triggered by any of the available sources • Interrupts upon transfer completion • Data transfer to/from LEUART in EM2 is supported by the DMA, providing extremely low energy consumption while performing UART communications

9.3 Block Diagram

An overview of the DMA and the modules it interacts with is shown in Figure 9.1 (p. 91) .

Figure 9.1. DMA Block Diagram

Int errupt s Cort ex AHB Peripheral Peripheral AHB t o APB bridge Configurat ion cont rol APB block APB m em ory m apped regist ers Configurat ion Channel select REQ/ ACK DMA Core AHB block AHB- Lit e m ast er int erface DMA dat a t ransfer Error Channel done DMA cont rol block The DMA Controller consists of four main parts: • An APB block allowing software to configure the DMA controller • An AHB block allowing the DMA to read and write the DMA descriptors and the source and destination data for the DMA transfers • A DMA control block controlling the operation of the DMA, including request/acknowledge signals for the connected peripherals 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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• A channel select block routing the right peripheral request to each DMA channel

9.4 Functional Description

The DMA Controller is highly flexible. It is capable of transferring data between peripherals and memory without involvement from the processor core. This can be used to increase system performance by off-loading the processor from copying large amounts of data or avoiding frequent interrupts to service peripherals needing more data or having available data. It can also be used to reduce the system energy consumption by making the DMA work autonomously with the LEUART for data transfer in EM2 without having to wake up the processor core from sleep.

The DMA Controller contains 12 independent channels. Each of these channels can be connected to any

of the available peripheral trigger sources by writing to the configuration registers, see Section 9.4.1 (p.

92) . In addition, each channel can be triggered by software (for large memory transfers or for

debugging purposes).

What the DMA Controller should do (when one of its channels is triggered) is configured through channel descriptors residing in system memory. Before enabling a channel, the software must therefore take care to write this configuration to memory. When a channel is triggered, the DMA Controller will first read the channel descriptor from system memory, and then it will proceed to perform the memory transfers as specified by the descriptor. The descriptor contains the memory address to read from, the memory address to write to, the number of bytes to be transferred, etc. The channel descriptor is described in

detail in Section 9.4.3 (p. 103) .

In addition to the basic transfer mode, the DMA Controller also supports two advanced transfer modes; ping-pong and scatter-gather. Ping-pong transfers are ideally suited for streaming data for high-speed peripheral communication as the DMA will be ready to retrieve the next incoming data bytes immediately while the processor core is still processing the previous ones (and similarly for outgoing communication).

Scatter-gather involves executing a series of tasks from memory and allows sophisticated schemes to be implemented by software.

Using different priority levels for the channels and setting the number of bytes after which the DMA Controller re-arbitrates, it is possible to ensure that timing-critical transfers are serviced on time.

9.4.1 Channel Select Configuration

The channel select block allows selecting which peripheral's request lines (dma_req, dma_sreq) to connect to each DMA channel.

This configuration is done by software through the control registers DMA_CH0_CTRL DMA_CH11_CTRL, with SOURCESEL and SIGSEL components. SOURCESEL selects which peripheral to listen to and SIGSEL picks which output signals to use from the selected peripheral.

All peripherals are connected to dma_req. When this signal is triggered, the DMA performs a number of transfers as specified by the channel descriptor (2 R ). The USARTs are additionally connected to the dma_sreq line. When only dma_sreq is asserted but not dma_req, then the DMA will perform exactly one transfer only (given that dma_sreq is enabled by software).

Note

A DMA channel should not be active when the clock to the selected peripheral is off.

9.4.2 DMA control

9.4.2.1 DMA arbitration rate

You can configure when the controller arbitrates during a DMA transfer. This enables you to reduce the latency to service a higher priority channel.

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The controller provides four bits that configure how many AHB bus transfers occur before it re-arbitrates.

These bits are known as the R_power bits because the value you enter, R, is raised to the power of two and this determines the arbitration rate. For example, if R = 4 then the arbitration rate is 2 4 , that is, the controller arbitrates every 16 DMA transfers.

Table 9.1 (p. 93) lists the arbitration rates.

Table 9.1. AHB bus transfer arbitration interval

R_power b0000 b0001 b0010 b0011 b0100 b0101 b0110 b0111 b1000 b1001 Arbitrate after x DMA transfers x = 1 x = 2 x = 4 x = 8 x = 16 x = 32 x = 64 x = 128 x = 256 x = 512 b1010 - b1111 x = 1024

Note

You must take care not to assign a low-priority channel with a large R_power because this prevents the controller from servicing high-priority requests, until it re-arbitrates.

The number of dma transfers N that need to be done is specified by the user. When N > 2 R and is not an integer multiple of 2 R then the controller always performs sequences of 2 R transfers until N < 2 R remain to be transferred. The controller performs the remaining N transfers at the end of the DMA cycle.

You store the value of the R_power bits in the channel control data structure. See Section 9.4.3.3 (p.

106) for more information about the location of the R_power bits in the data structure.

9.4.2.2 Priority

When the controller arbitrates, it determines the next channel to service by using the following information: • the channel number • the priority level, default or high, that is assigned to the channel.

You can configure each channel to use either the default priority level or a high priority level by setting the DMA_CHPRIS register.

Channel number zero has the highest priority and as the channel number increases, the priority of a

channel decreases. Table 9.2 (p. 93) lists the DMA channel priority levels in descending order of

priority.

Table 9.2. DMA channel priority

Channel number 0 Priority level setting High Descending order of channel priority Highest-priority DMA channel 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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6 7 2 3 4 5 Channel number 1 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 High High High High Default Default Default Default Default Default Default Default Default Default Default Default Priority level setting High High High High High High High Descending order of channel priority Lowest-priority DMA channel

After a DMA transfer completes, the controller polls all the DMA channels that are available. Figure 9.2 (p.

95) shows the process it uses to determine which DMA transfer to perform next.

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...the world's most energy friendly wireless MCUs Figure 9.2. Polling flowchart

St art polling Is t here a channel request ?

No Yes Are any channel request s using a high priorit y level ?

No Yes Select channel t hat has t he lowest channel num ber and is set t o high priorit y- level Select channel t hat has t he lowest channel num ber St art DMA t ransfer

9.4.2.3 DMA cycle types

The cycle_ctrl bits control how the controller performs a DMA cycle. You can set the cycle_ctrl bits as

Table 9.3 (p. 95) lists.

Table 9.3. DMA cycle types

cycle_ctrl b000 b001 b010 b011 b100 b101 b110 b111 Description Channel control data structure is invalid Basic DMA transfer Auto-request Ping-pong Memory scatter-gather using the primary data structure Memory scatter-gather using the alternate data structure Peripheral scatter-gather using the primary data structure Peripheral scatter-gather using the alternate data structure

Note

The cycle_ctrl bits are located in the channel_cfg memory location that Section 9.4.3.3 (p.

106) describes.

For all cycle types, the controller arbitrates after 2 R DMA transfers. If you set a low-priority channel with a large 2 R value then it prevents all other channels from performing a DMA transfer, until the low-priority DMA transfer completes. Therefore, you must take care when setting the R_power, that you do not significantly increase the latency for high-priority channels.

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9.4.2.3.1 Invalid

After the controller completes a DMA cycle it sets the cycle type to invalid, to prevent it from repeating the same DMA cycle.

9.4.2.3.2 Basic

In this mode, you configure the controller to use either the primary or the alternate data structure. After you enable the channel C and the controller receives a request for this channel, then the flow for this DMA cycle is as follows: 1. The controller performs 2 R transfers. If the number of transfers remaining becomes zero, then the

flow continues at step 3 (p. 96) .

2. The controller arbitrates: • if a higher-priority channel is requesting service then the controller services that channel

• if the peripheral or software signals a request to the controller then it continues at step 1 (p. 96) .

3. The controller sets dma_done[C] HIGH for one HFCORECLK cycle. This indicates to the host processor that the DMA cycle is complete.

9.4.2.3.3 Auto-request

When the controller operates in this mode, it is only necessary for it to receive a single request to enable it to complete the entire DMA cycle. This enables a large data transfer to occur, without significantly increasing the latency for servicing higher priority requests, or requiring multiple requests from the processor or peripheral.

You can configure the controller to use either the primary or the alternate data structure. After you enable the channel C and the controller receives a request for this channel, then the flow for this DMA cycle is as follows: 1. The controller performs 2 R transfers for channel C. If the number of transfers remaining is zero the

flow continues at step 3 (p. 96) .

2. The controller arbitrates. When channel C has the highest priority then the DMA cycle continues at

step 1 (p. 96) .

3. The controller sets dma_done[C] HIGH for one HFCORECLK cycle. This indicates to the host processor that the DMA cycle is complete.

9.4.2.3.4 Ping-pong

In ping-pong mode, the controller performs a DMA cycle using one of the data structures (primary or alternate) and it then performs a DMA cycle using the other data structure. The controller continues to switch from primary to alternate to primary… until it reads a data structure that is invalid, or until the host processor disables the channel.

Figure 9.3 (p. 97) shows an example of a ping-pong DMA transaction.

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Figure 9.3. Ping-pong example

Task A: Prim ary, cycle_ct rl = b011, 2 R = 4, N = 6 Task A Request Request Task B: Alt ernat e, cycle_ct rl = b011, 2 R = 4, N = 12 Request Request Request Task B

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dma_done[C] dma_done[C]

Task C: Prim ary, cycle_ct rl = b011, 2 R = 2, N = 2 Task C Request Task D: Alt ernat e, cycle_ct rl = b011, 2 R = 4, N = 5 Request Request Task E: Prim ary, cycle_ct rl = b011, 2 R = 4, N = 7 Task E Request Request Task D

dma_done[C] dma_done[C] dma_done[C]

End: Alt ernat e, cycle_ct rl = b000 Invalid

In Figure 9.3 (p. 97) :

Task A 1. The host processor configures the primary data structure for task A.

2. The host processor configures the alternate data structure for task B. This enables the controller to immediately switch to task B after task A completes, provided that a higher priority channel does not require servicing.

3. The controller receives a request and performs four DMA transfers.

4. The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority.

5. The controller performs the remaining two DMA transfers.

6. The controller sets arbitration process.

dma_done[C] HIGH for one HFCORECLK cycle and enters the After task A completes, the host processor can configure the primary data structure for task C. This enables the controller to immediately switch to task C after task B completes, provided that a higher priority channel does not require servicing.

After the controller receives a new request for the channel and it has the highest priority then task B commences: Task B 7. The controller performs four DMA transfers.

8. The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority.

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9. The controller performs four DMA transfers.

10.The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority.

11.The controller performs the remaining four DMA transfers.

12.The controller sets dma_done[C] HIGH for one arbitration process.

HFCORECLK cycle and enters the After task B completes, the host processor can configure the alternate data structure for task D.

After the controller receives a new request for the channel and it has the highest priority then task C commences: Task C 13.The controller performs two DMA transfers.

14.The controller sets dma_done[C] HIGH for one arbitration process.

HFCORECLK cycle and enters the After task C completes, the host processor can configure the primary data structure for task E.

After the controller receives a new request for the channel and it has the highest priority then task D commences: Task D 15.The controller performs four DMA transfers.

16.The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority.

17.The controller performs the remaining DMA transfer.

18.The controller sets dma_done[C] HIGH for one arbitration process.

HFCORECLK cycle and enters the After the controller receives a new request for the channel and it has the highest priority then task E commences: Task E 19.The controller performs four DMA transfers.

20.The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority.

21.The controller performs the remaining three DMA transfers.

22.The controller sets dma_done[C] HIGH for one arbitration process.

HFCORECLK cycle and enters the If the controller receives a new request for the channel and it has the highest priority then it attempts to start the next task. However, because the host processor has not configured the alternate data structure, and on completion of task D the controller set the cycle_ctrl bits to b000, then the ping-pong DMA transaction completes.

Note

You can also terminate the ping-pong DMA cycle in Figure 9.3 (p. 97) , if you configure

task E to be a basic DMA cycle by setting the cycle_ctrl field to 3’b001.

9.4.2.3.5 Memory scatter-gather

In memory scatter-gather mode the controller receives an initial request and then performs four DMA transfers using the primary data structure. After this transfer completes, it starts a DMA cycle using the alternate data structure. After this cycle completes, the controller performs another four DMA transfers 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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using the primary data structure. The controller continues to switch from primary to alternate to primary… until either: • the host processor configures the alternate data structure for a basic cycle • it reads an invalid data structure.

Note

After the controller completes the N primary transfers it invalidates the primary data structure by setting the cycle_ctrl field to b000.

The controller only asserts dma_done[C] when the scatter-gather transaction completes using an auto request cycle.

In scatter-gather mode, the controller uses the primary data structure to program the alternate data

structure. Table 9.4 (p. 99) lists the fields of the channel_cfg memory location for the primary data

structure, that you must program with constant values and those that can be user defined.

Table 9.4. channel_cfg for a primary data structure, in memory scatter-gather mode

Bit Field Constant-value fields: [31:30} [29:28] dst_inc dst_size [27:26] [25:24] src_inc src_size Value b10 b10 b10 b10 Description Configures the controller to use word increments for the address Configures the controller to use word transfers Configures the controller to use word increments for the address Configures the controller to use word transfers [17:14] [3] [2:0] cycle_ctrl User defined values: [23:21] R_power next_useburst dst_prot_ctrl b0010 0 b100 Configures the controller to perform four DMA transfers For a memory scatter-gather DMA cycle, this bit must be set to zero Configures the controller to perform a memory scatter-gather DMA cycle Configures the state of HPROT 1 when the controller writes the destination data [20:18] src_prot_ctrl Configures the state of HPROT when the controller reads the source data [13:4] n_minus_1 N 2 Configures the controller to perform N DMA transfers, where N is a multiple of four 1 ARM PL230 homepage [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0417a/index.html] 2 Because the R_power field is set to four, you must set N to be a multiple of four. The value given by N/4 is the number of times that you must configure the alternate data structure.

See Section 9.4.3.3 (p. 106) for more information.

Figure 9.4 (p. 100) shows a memory scatter-gather example.

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...the world's most energy friendly wireless MCUs Figure 9.4. Memory scatter-gather example

Init ializat ion: 1. Configure prim ary t o enable t he copy A, B, C, and D operat ions: cycle_ct rl = b100, 2 R = 4, N = 16.

2. Writ e t he prim ary source dat a t o m em ory, using t he st ruct ure shown in t he following t able.

Dat a for Task A Dat a for Task B Dat a for Task C Dat a for Task D src_dat a_end_pt r 0x 0A000000 0x 0B000000 0x 0C000000 0x 0D000000 dst _dat a_end_pt r 0x 0AE00000 0x 0BE00000 0x 0CE00000 0x 0DE00000 channel_cfg cycle_ct rl = b101, 2 R = 4, N = 3 cycle_ct rl = b101, 2 R = 2, N = 8 cycle_ct rl = b101, 2 R = 8, N = 5 cycle_ct rl = b010, 2 R = 4, N = 4 Unused 0x XXXXXXXX 0x XXXXXXXX 0x XXXXXXXX 0x XXXXXXXX Mem ory scat t er- gat her t ransact ion:

Primary Alternate

Copy from A in m em ory, t o Alt ernat e Request Copy from B in m em ory, t o Alt ernat e Aut o request Aut o request Task A N = 3, 2 R = 4 Aut o request Aut o request Aut o request Aut o request Aut o request Copy from C in m em ory, t o Alt ernat e Task B N = 8, 2 R = 2 Copy from D in m em ory, t o Alt ernat e Aut o request Aut o request Aut o request Task C Task D N = 5, 2 R = 8 N = 4, 2 R = 4

dma_done[C]

In Figure 9.4 (p. 100) :

Initialization 1. The host processor configures the primary data structure to operate in memory scatter-gather mode by setting cycle_ctrl to b100. Because a data structure for a single channel consists of four words then you must set 2 R to 4. In this example, there are four tasks and therefore N is set to 16.

2. The host processor writes the data structure for tasks A, B, C, and D to the memory locations that the primary src_data_end_ptr specifies.

3. The host processor enables the channel.

The memory scatter-gather transaction commences when the controller receives a request on dma_req[ ] or a manual request from the host processor. The transaction continues as follows: Primary, copy A Task A Primary, copy B Task B Primary, copy C 1. After receiving a request, the controller performs four DMA transfers. These transfers write the alternate data structure for task A.

2. The controller generates an auto-request for the channel and then arbitrates.

3. The controller performs task A. After it completes the task, it generates an auto-request for the channel and then arbitrates.

4. The controller performs four DMA transfers. These transfers write the alternate data structure for task B.

5. The controller generates an auto-request for the channel and then arbitrates.

6. The controller performs task B. After it completes the task, it generates an auto-request for the channel and then arbitrates.

7. The controller performs four DMA transfers. These transfers write the alternate data structure for task C.

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Task C Primary, copy D Task D

9.4.2.3.6 Peripheral scatter-gather

In peripheral scatter-gather mode the controller receives an initial request from a peripheral and then it performs four DMA transfers using the primary data structure. It then immediately starts a DMA cycle using the alternate data structure, without re-arbitrating.

Note

These are the only circumstances, where the controller does not enter the arbitration process after completing a transfer using the primary data structure.

After this cycle completes, the controller re-arbitrates and if the controller receives a request from the peripheral that has the highest priority then it performs another four DMA transfers using the primary data structure. It then immediately starts a DMA cycle using the alternate data structure, without re arbitrating. The controller continues to switch from primary to alternate to primary… until either: • the host processor configures the alternate data structure for a basic cycle • it reads an invalid data structure.

Note ...the world's most energy friendly wireless MCUs

8. The controller generates an auto-request for the channel and then arbitrates.

9. The controller performs task C. After it completes the task, it generates an auto-request for the channel and then arbitrates.

10.The controller performs four DMA transfers. These transfers write the alternate data structure for task D.

11.The controller sets the cycle_ctrl bits of the primary data structure to b000, to indicate that this data structure is now invalid.

12.The controller generates an auto-request for the channel and then arbitrates.

13.The controller performs task D using an auto-request cycle.

14.The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process.

After the controller completes the N primary transfers it invalidates the primary data structure by setting the cycle_ctrl field to b000.

The controller asserts dma_done[C] when the scatter-gather transaction completes using a basic cycle.

In scatter-gather mode, the controller uses the primary data structure to program the alternate data

structure. Table 9.5 (p. 101) lists the fields of the channel_cfg memory location for the primary data

structure, that you must program with constant values and those that can be user defined.

Table 9.5. channel_cfg for a primary data structure, in peripheral scatter-gather mode

Bit Field Constant-value fields: [31:30] [29:28] dst_inc dst_size [27:26] [25:24] src_inc src_size [17:14] [2:0] R_power cycle_ctrl User defined values: [23:21] dst_prot_ctrl Value Description b10 b10 b10 b10 b0010 b110 Configures the controller to use word increments for the address Configures the controller to use word transfers Configures the controller to use word increments for the address Configures the controller to use word transfers Configures the controller to perform four DMA transfers Configures the controller to perform a peripheral scatter-gather DMA cycle Configures the state of HPROT when the controller writes the destination data 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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Bit [20:18] [13:4] Field src_prot_ctrl n_minus_1 Value N 1 Description Configures the state of HPROT when the controller reads the source data Configures the controller to perform N DMA transfers, where N is a multiple of four [3] next_useburst When set to 1, the controller sets the chnl_useburst_set [C] bit to 1 after the alternate transfer completes 1 Because the R_power field is set to four, you must set N to be a multiple of four. The value given by N/4 is the number of times that you must configure the alternate data structure.

See Section 9.4.3.3 (p. 106) for more information.

Figure 9.5 (p. 102) shows a peripheral scatter-gather example.

Figure 9.5. Peripheral scatter-gather example

Init ializat ion: 1. Configure prim ary t o enable t he copy A, B, C, and D operat ions: cycle_ct rl = b110, 2 R = 4, N = 16.

2. Writ e t he prim ary source dat a in m em ory, using t he st ruct ure shown in t he following t able.

Dat a for Task A Dat a for Task B Dat a for Task C Dat a for Task D src_dat a_end_pt r 0x 0A000000 0x 0B000000 0x 0C000000 0x 0D000000 dst _dat a_end_pt r 0x 0AE00000 0x 0BE00000 0x 0CE00000 0x 0DE00000 channel_cfg cycle_ct rl = b111, 2 R = 4, N = 3 cycle_ct rl = b111, 2 R = 2, N = 8 cycle_ct rl = b111, 2 R = 8, N = 5 cycle_ct rl = b001, 2 R = 4, N = 4 Unused 0x XXXXXXXX 0x XXXXXXXX 0x XXXXXXXX 0x XXXXXXXX Peripheral scat t er- gat her t ransact ion:

Primary Alternate

Request Copy from A in m em ory, t o Alt ernat e For all prim ary t o alt ernat e t ransit ions, t he cont roller does not ent er t he arbit rat ion process and im m ediat ely perform s t he DMA t ransfer t hat t he alt ernat e channel cont rol dat a st ruct ure specifies.

Task A N = 3, 2 R = 4 Request Copy from B in m em ory, t o Alt ernat e Task B Copy from C in m em ory, t o Alt ernat e Request Request Request Request N = 8, 2 R = 2 Task C N = 5, 2 R = 8 Copy from D in m em ory, t o Alt ernat e Request Task D N = 4, 2 R = 4

dma_done[C]

In Figure 9.5 (p. 102) :

Initialization 1. The host processor configures the primary data structure to operate in peripheral scatter-gather mode by setting cycle_ctrl to b110. Because a data structure for a single channel consists of four words then you must set 2 R to 4. In this example, there are four tasks and therefore N is set to 16.

2. The host processor writes the data structure for tasks A, B, C, and D to the memory locations that the primary src_data_end_ptr specifies.

3. The host processor enables the channel.

The peripheral scatter-gather transaction commences when the controller receives a request on dma_req[ ] . The transaction continues as follows: 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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Primary, copy A Task A

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1. After receiving a request, the controller performs four DMA transfers. These transfers write the alternate data structure for task A.

2. The controller performs task A.

3. After the controller completes the task it enters the arbitration process.

After the peripheral issues a new request and it has the highest priority then the process continues with: Primary, copy B Task B 4. The controller performs four DMA transfers. These transfers write the alternate data structure for task B.

5. The controller performs task B. To enable the controller to complete the task, the peripheral must issue a further three requests.

6. After the controller completes the task it enters the arbitration process.

After the peripheral issues a new request and it has the highest priority then the process continues with: Primary, copy C Task C 7. The controller performs four DMA transfers. These transfers write the alternate data structure for task C.

8. The controller performs task C.

9. After the controller completes the task it enters the arbitration process.

After the peripheral issues a new request and it has the highest priority then the process continues with: Primary, copy D Task D 10.The controller performs four DMA transfers. These transfers write the alternate data structure for task D.

11.The controller sets the cycle_ctrl bits of the primary data structure to b000, to indicate that this data structure is now invalid.

12.The controller performs task D using a basic cycle.

13.The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process.

9.4.2.4 Error signaling

If the controller detects an ERROR response on the AHB-Lite master interface, it: • disables the channel that corresponds to the ERROR • sets dma_err HIGH.

After the host processor detects that dma_err is HIGH, it must check which channel was active when the ERROR occurred. It can do this by: 1. Reading the DMA_CHENS register to create a list of disabled channels.

When a channel asserts dma_done[ ] then the controller disables the channel. The program running on the host processor must always keep a record of which channels have recently asserted their dma_done[ ] outputs.

2. It must compare the disabled channels list from step 1 (p. 103) , with the record of the channels that

have recently set their dma_done[ ] outputs. The channel with no record of dma_done[C] being set is the channel that the ERROR occurred on.

9.4.3 Channel control data structure

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• have a base address that is an integer multiple of the total size of the channel control data structure.

Figure 9.6 (p. 104) shows the memory that the controller requires for the channel control data structure,

when all 12 channels and the optional alternate data structure are in use.

Figure 9.6. Memory map for 12 channels, including the alternate data structure

Alt ernat e dat a st ruct ure Alt ernat e_Ch_11 Alt ernat e_Ch_10 Alt ernat e_Ch_9 Alt ernat e_Ch_8 Alt ernat e_Ch_7 Alt ernat e_Ch_6 Alt ernat e_Ch_5 Alt ernat e_Ch_4 Alt ernat e_Ch_3 Alt ernat e_Ch_2 Alt ernat e_Ch_1 Alt ernat e_Ch_0 0x 1C0 0x 1B0 0x 1A0 0x 190 0x 180 0x 170 0x 160 0x 150 0x 140 0x 130 0x 120 0x 110 0x 100 Prim ary dat a st ruct ure Prim ary_Ch_11 Prim ary_Ch_10 Prim ary_Ch_9 Prim ary_Ch_8 Prim ary_Ch_7 Prim ary_Ch_6 Prim ary_Ch_5 Prim ary_Ch_4 Prim ary_Ch_3 Prim ary_Ch_2 Prim ary_Ch_1 Prim ary_Ch_0 0x 0C0 0x 0B0 0x 0A0 0x 090 0x 080 0x 070 0x 060 0x 050 0x 040 0x 030 0x 020 0x 010 0x 000 User Cont rol Dest inat ion End Point er Source End Point er 0x 00C 0x 008 0x 004 0x 000

This structure in Figure 9.6 (p. 104) uses 384 bytes of system memory. The controller uses the lower

8 address bits to enable it to access all of the elements in the structure and therefore the base address must be at 0xXXXXXX00 .

You can configure the base address for the primary data structure by writing the appropriate value in the DMA_CTRLBASE register.

You do not need to set aside the full 384 bytes if all dma channels are not used or if all alternate descriptors are not used. If, for example, only 4 channels are used and they only need the primary descriptors, then only 64 bytes need to be set aside.

Table 9.6 (p. 104) lists the address bits that the controller uses when it accesses the elements of the

channel control data structure.

Table 9.6. Address bit settings for the channel control data structure

Address bits [8] A [7] C[3] [6] C[2] [5] C[1] [4] C[0] [3:0] 0x0, 0x4, or 0x8 Where: A C[3:0] Address[3:0] Selects one of the channel control data structures: A = 0 A = 1 Selects the primary data structure.

Selects the alternate data structure.

Selects the DMA channel.

Selects one of the control elements: 0x0 Selects the source data end pointer.

0x4 0x8 0xC Selects the destination data end pointer.

Selects the control data configuration.

The controller does not access this address location. If required, you can enable the host processor to use this memory location as system memory.

Note

It is not necessary for you to calculate the base address of the alternate data structure because the DMA_ALTCTRLBASE register provides this information.

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Figure 9.7 (p. 105) shows a detailed memory map of the descriptor structure.

Figure 9.7. Detailed memory map for the 12 channels, including the alternate data structure

Alt ernat e for channel 11 Alt ernat e for channel 1 Alt ernat e for channel 0 Prim ary for channel 11 Prim ary for channel 1 Prim ary for channel 0 Unused Cont rol Dest inat ion End Point er Source End Point er 0x 1BC 0x 1B8 0x 1B4 0x 1B0 Unused Cont rol Dest inat ion End Point er Source End Point er Unused Cont rol Dest inat ion End Point er Source End Point er Unused Cont rol Dest inat ion End Point er Source End Point er 0x 11C 0x 118 0x 114 0x 110 0x 10C 0x 108 0x 104 0x 100 0x 0BC 0x 0B8 0x 0B4 0x 0B0 Alt ernat e dat a st ruct ure Unused Cont rol Dest inat ion End Point er Source End Point er Unused Cont rol Dest inat ion End Point er Source End Point er 0x 01C 0x 018 0x 014 0x 010 0x 00C 0x 008 0x 004 0x 000 Prim ary dat a st ruct ure The controller uses the system memory to enable it to access two pointers and the control information that it requires for each channel. The following subsections will describe these 32-bit memory locations and how the controller calculates the DMA transfer address.

9.4.3.1 Source data end pointer

The src_data_end_ptr memory location contains a pointer to the end address of the source data.

Figure 9.7 (p. 105) lists the bit assignments for this memory location.

Table 9.7. src_data_end_ptr bit assignments

Bit [31:0] Name src_data_end_ptr Description Pointer to the end address of the source data Before the controller can perform a DMA transfer, you must program this memory location with the end address of the source data. The controller reads this memory location when it starts a 2 R DMA transfer.

Note

The controller does not write to this memory location.

9.4.3.2 Destination data end pointer

The dst_data_end_ptr memory location contains a pointer to the end address of the destination data.

Table 9.8 (p. 106) lists the bit assignments for this memory location.

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...the world's most energy friendly wireless MCUs Table 9.8. dst_data_end_ptr bit assignments

Bit [31:0] Name dst_data_end_ptr Description Pointer to the end address of the destination data Before the controller can perform a DMA transfer, you must program this memory location with the end address of the destination data. The controller reads this memory location when it starts a 2 R DMA transfer.

Note

The controller does not write to this memory location.

9.4.3.3 Control data configuration

For each DMA transfer, the channel_cfg memory location provides the control information for the

controller. Figure 9.8 (p. 106) shows the bit assignments for this memory location.

Figure 9.8. channel_cfg bit assignments

31 30 29 28 27 26 25 24 23 21 20 18 17 14 R_power 13 dst _inc src_inc dst _size src_size src_prot _ct rl dst _prot _ct rl n_m inus_1 4 3 2 0 cycle_ct rl nex t _useburst

Table 9.9 (p. 106) lists the bit assignments for this memory location.

Table 9.9. channel_cfg bit assignments

Bit [31:30] Name dst_inc Description Destination address increment.

The address increment depends on the source data width as follows: Source data width = byte b00 = byte.

b01 = halfword.

b10 = word.

b11 = no increment. Address remains set to the value that the dst_data_end_ptr memory location contains.

Source data width = halfword Source data width = word b00 = reserved.

b01 = halfword.

b10 = word.

b11 = no increment. Address remains set to the value that the dst_data_end_ptr memory location contains.

b00 = reserved.

b01 = reserved.

b10 = word.

b11 = no increment. Address remains set to the value that the dst_data_end_ptr memory location contains.

[29:28] dst_size Destination data size.

Note

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Bit [27:26] [25:24] [23:21] dst_prot_ctrl [20:18] [17:14] Name src_inc src_size src_prot_ctrl R_power Description You must set dst_size to contain the same value that src_size contains.

Set the bits to control the source address increment. The address increment depends on the source data width as follows: Source data width = byte b00 = byte.

b01 = halfword.

Source data width = halfword Source data width = word b10 = word.

b11 = no increment. Address remains set to the value that the src_data_end_ptr memory location contains.

b00 = reserved.

b01 = halfword.

b10 = word.

b11 = no increment. Address remains set to the value that the src_data_end_ptr memory location contains.

b00 = reserved.

b01 = reserved.

b10 = word.

b11 = no increment. Address remains set to the value that the src_data_end_ptr memory location contains.

Set the bits to match the size of the source data: b00 = byte b01 = halfword b10 = word b11 = reserved.

Set the bits to control the state of HPROT when the controller writes the destination data.

Bit [23] Bit [22] Bit [21] This bit has no effect on the DMA.

This bit has no effect on the DMA.

Controls the state of HPROT as follows: 0 = HPROT is LOW and the access is non-privileged.

1 = HPROT is HIGH and the access is privileged.

Set the bits to control the state of HPROT when the controller reads the source data.

Bit [20] Bit [19] Bit [18] This bit has no effect on the DMA.

This bit has no effect on the DMA.

Controls the state of HPROT as follows: 0 = HPROT is LOW and the access is non-privileged.

1 = HPROT is HIGH and the access is privileged.

Set these bits to control how many DMA transfers can occur before the controller re-arbitrates.

The possible arbitration rate settings are: b0000 b0001 b0010 b0011 b0100 b0101 b0110 b0111 b1000 b1001 b1010 - b1111 Arbitrates after each DMA transfer.

Arbitrates after 2 DMA transfers.

Arbitrates after 4 DMA transfers.

Arbitrates after 8 DMA transfers.

Arbitrates after 16 DMA transfers.

Arbitrates after 32 DMA transfers.

Arbitrates after 64 DMA transfers.

Arbitrates after 128 DMA transfers.

Arbitrates after 256 DMA transfers.

Arbitrates after 512 DMA transfers.

Arbitrates after 1024 DMA transfers. This means that no arbitration occurs during the DMA transfer because the maximum transfer size is 1024.

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Bit [13:4] [3] [2:0]

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Name n_minus_1 next_useburst cycle_ctrl Description Prior to the DMA cycle commencing, these bits represent the total number of DMA transfers that the DMA cycle contains. You must set these bits according to the size of DMA cycle that you require.

The 10-bit value indicates the number of DMA transfers, minus one. The possible values are: b000000000 = 1 DMA transfer b000000001 = 2 DMA transfers b000000010 = 3 DMA transfers b000000011 = 4 DMA transfers b000000100 = 5 DMA transfers .

.

.

b111111111 = 1024 DMA transfers.

The controller updates this field immediately prior to it entering the arbitration process. This enables the controller to store the number of outstanding DMA transfers that are necessary to complete the DMA cycle.

Controls if the chnl_useburst_set [C] bit is set to a 1, when the controller is performing a peripheral scatter-gather and is completing a DMA cycle that uses the alternate data structure.

Note

Immediately prior to completion of the DMA cycle that the alternate data structure specifies, the controller sets the chnl_useburst_set [C] bit to 0 if the number of remaining transfers is less than 2 R . The setting of the next_useburst bit controls if the controller performs an additional modification of the chnl_useburst_set [C] bit.

In peripheral scatter-gather DMA cycle then after the DMA cycle that uses the alternate data structure completes , either: 0 = the controller does not change the value of the chnl_useburst_set [C] bit. If the chnl_useburst_set [C] bit is 0 then for all the remaining DMA cycles in the peripheral scatter gather transaction, the controller responds to requests on dma_req[ ] and dma_sreq[ ] , when it performs a DMA cycle that uses an alternate data structure.

1 = the controller sets the chnl_useburst_set [C] bit to a 1. Therefore, for the remaining DMA cycles in the peripheral scatter-gather transaction, the controller only responds to requests on dma_req[ ] , when it performs a DMA cycle that uses an alternate data structure.

The operating mode of the DMA cycle. The modes are: b000 b001 b010 b011 b100 Stop. Indicates that the data structure is invalid.

Basic. The controller must receive a new request, prior to it entering the arbitration process, to enable the DMA cycle to complete.

Auto-request. The controller automatically inserts a request for the appropriate channel during the arbitration process. This means that the initial request is sufficient to enable the DMA cycle to complete.

Ping-pong. The controller performs a DMA cycle using one of the data structures. After the DMA cycle completes, it performs a DMA cycle using the other data structure. After the DMA cycle completes and provided that the host processor has updated the original data structure, it performs a DMA cycle using the original data structure. The controller continues to perform DMA cycles until it either reads an invalid data structure or the

host processor changes the cycle_ctrl bits to b001 or b010. See Section 9.4.2.3.4 (p.

96) .

Memory scatter/gather. See Section 9.4.2.3.5 (p. 98) .

b101 When the controller operates in memory scatter-gather mode, you must only use this value in the primary data structure.

Memory scatter/gather. See Section 9.4.2.3.5 (p. 98) .

b110 When the controller operates in memory scatter-gather mode, you must only use this value in the alternate data structure.

Peripheral scatter/gather. See Section 9.4.2.3.6 (p. 101) .

b111 When the controller operates in peripheral scatter-gather mode, you must only use this value in the primary data structure.

Peripheral scatter/gather. See Section 9.4.2.3.6 (p. 101) .

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Bit Name

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Description When the controller operates in peripheral scatter-gather mode, you must only use this value in the alternate data structure.

At the start of a DMA cycle, or 2 R DMA transfer, the controller fetches the channel_cfg from system memory. After it performs 2 R , or N, transfers it stores the updated channel_cfg in system memory.

The controller does not support a dst_size value that is different to the src_size value. If it detects a mismatch in these values, it uses the src_size value for source and destination and when it next updates the n_minus_1 field, it also sets the dst_size field to the same as the src_size field.

After the controller completes the N transfers it sets the cycle_ctrl field to b000, to indicate that the channel_cfg data is invalid. This prevents it from repeating the same DMA transfer.

9.4.3.4 Address calculation

To calculate the source address of a DMA transfer, the controller performs a left shift operation on the n_minus_1 value by a shift amount that src_inc specifies, and then subtracts the resulting value from the source data end pointer. Similarly, to calculate the destination address of a DMA transfer, it performs a left shift operation on the n_minus_1 value by a shift amount that dst_inc specifies, and then subtracts the resulting value from the destination end pointer.

Depending on the value of src_inc and dst_inc, the source address and destination address can be calculated using the equations: src_inc = b00 and dst_inc = b00 src_inc = b01 and dst_inc = b01 src_inc = b10 and dst_inc = b10 src_inc = b11 and dst_inc = b11 • source address = src_data_end_ptr - n_minus_1 • destination address = dst_data_end_ptr - n_minus_1.

• source address = src_data_end_ptr - (n_minus_1 << 1) • destination address = dst_data_end_ptr - (n_minus_1 << 1).

• source address = src_data_end_ptr - (n_minus_1 << 2) • destination address = dst_data_end_ptr - (n_minus_1 << 2).

• source address = src_data_end_ptr • destination address = dst_data_end_ptr.

Table 9.10 (p. 109) lists the destination addresses for a DMA cycle of six words.

Table 9.10. DMA cycle of six words using a word increment

Initial values of channel_cfg, prior to the DMA cycle src_size = b10, dst_inc = b10, n_minus_1 = b101, cycle_ctrl = 1 End Pointer Count Difference 1 0x2AC 0x2AC 5 4 0x14 0x10 Address 0x298 0x29C DMA transfers 0x2AC 0x2AC 0x2AC 0x2AC 1 0 3 2 Final values of channel_cfg, after the DMA cycle 0xC 0x8 0x4 0x0 0x2A0 0x2A4 0x2A8 0x2AC src_size = b10, dst_inc = b10, n_minus_1 = 0, cycle_ctrl = 0 1 This value is the result of count being shifted left by the value of dst_inc.

Table 9.11 (p. 110) lists the destination addresses for a DMA transfer of 12 bytes using a halfword

increment.

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...the world's most energy friendly wireless MCUs Table 9.11. DMA cycle of 12 bytes using a halfword increment

Initial values of channel_cfg, prior to the DMA cycle src_size = b00, dst_inc = b01, n_minus_1 = b1011, cycle_ctrl = 1, R_power = b11 End Pointer Count Difference 1 Address 0x5E7 0x5E7 0x5E7 11 10 9 0x16 0x14 0x12 0x5D1 0x5D3 0x5D5 DMA transfers 0x5E7 0x5E7 0x5E7 0x5E7 8 7 6 5 0x10 0xE 0xC 0xA 0x5D7 0x5D9 0x5DB 0x5DD 0x5E7 Values of channel_cfg after 2 R DMA transfers 4 0x8 0x5DF src_size = b00, dst_inc = b01, n_minus_1 = b011, cycle_ctrl = 1, R_power = b11 DMA transfers End Pointer 0x5E7 0x5E7 0x5E7 0x5E7 2 1 Count 3 0 Difference 0x6 0x4 0x2 0x0 Address 0x5E1 0x5E3 0x5E5 0x5E7 Final values of channel_cfg, after the DMA cycle src_size = b00, dst_inc = b01, n_minus_1 = 0, cycle_ctrl = 0 2 , R_power = b11 1 This value is the result of count being shifted left by the value of dst_inc.

2 After the controller completes the DMA cycle it invalidates the channel_cfg memory location by clearing the cycle_ctrl field.

9.4.4 Looped Transfers

A regular DMA channel is done when it has performed the number of transfers given by the channel descriptor. If an application wants a continuous flow of data, one option is to use ping-pong mode, alternating between two descriptors and having software update one descriptor while the other is being used. Another way is to use looped transfers.

For DMA channels 0 and 1, looping can be enabled by setting EN in DMA_LOOP0 and DMA_LOOP1 respectively. A looping DMA channel will on completion set the respective DONE interrupt flag, but then reload n_minus_1 in the channel descriptor with the loop width defined by WIDTH in DMA_LOOPx and continue transmitting data.

The total length of the transfer is given by the original value of n_minus_1 in the channel descriptor and WIDTH in DMA_LOOPx times the number of loops taken. The loop feature can for instance be used to implement a ring buffer, contiguously overwriting old data when new data is available. To end the loop clear EN in DMA_LOOPx. The channel will then complete the last loop before stopping.

9.4.5 2D Copy

In addition to looped transfers, DMA channel 0 has the ability to do rectangle transfers, or 2D copy. For an application working with graphics, this would mean the ability to copy a rectangle of a given width and height from one picture to another. The DMA also has the ability to copy from linear data to a rectangle, and from a rectangle to linear data.

To set up rectangle copy for DMA channel 0, configure WIDTH in DMA_LOOP0 to one less than the rectangle width, and HEIGHT in DMA_RECT0 to one less than the rectangle height. Then 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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set SRCSTRIDE in DMA_RECT0 to the outer rectangle width of the source, and DSTSTRIDE in DMA_RECT0 to the outer rectangle width of the destination rectangle. Finally, the channel descriptor for channel 0 has to be configured. The source and destination end pointers should be set to the last element of the first line of the source data and destination data respectively. The number of elements to be transferred, n_minus_1 should be set equal to WIDTH in DMA_LOOP0. The parameters are visualized

in Figure 9.9 (p. 111) .

Figure 9.9. 2D copy

Source buffer WIDTH Source end point er Dest inat ion buffer WIDTH Dest inat ion end point er SRCSTRIDE DSTSTRIDE

When doing a rectangle copy, the source and destination address of the channel descriptor will be incremented line for line as the DMA works its way through the rectangle. The operation is done when the number of lines specified by HEIGHT in DMA_RECT0 has been copied. The source and destination addresses in the channel descriptor will then point at the last element of the source and destination rectangles.

On completion, the DONE interrupt flag of channel 0 is set. Looping is not supported for rectangle copy.

In some cases, e.g. when performing graphics operations, it is desirable to create a list of copy operations and have them executed automatically. This can be done using 2D copy together with the scatter gather mode of the DMA controller. Set DESCRECT in DMA_CTRL to override SCRSTRIDE and HEIGHT in DMA_RECT0 and WIDTH in DMA_LOOP0 by the values in the user part of the DMA descriptor as

shown in Table 9.12 (p. 111) . In this way every copy command in the list can specify these parameters

individually.

Table 9.12. User data assignments when DESCRECT is set

Bit [30:20] [19:10] [9:0] Field SRCSTRIDE HEIGHT WIDTH Description Stride in source buffer Height - 1 of data to be copied Width - 1 of data to be copied With regular 2D copy, the DMA descriptor will be updated as the copy operation proceeds. To be able to reuse the 2D copy scatter gather list without rewriting source and destination end addresses, set PRDU 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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in DMA_CTRL. This will prevent the address in the descriptor from being updated. In this case RDSCH0 in DMA_RDS must be set and all other bits in DMA_RDS must be cleared. The bits in DMA_RDS make individual DMA channels remember the source and destination end pointers while active, speeding up their transfers.

9.4.6 Interaction with the EMU

The DMA interacts with the Energy Management Unit (EMU) to allow transfers from , e.g., the LEUART to occur in EM2. The EMU can wake up the DMA sufficiently long to allow data transfers to occur. See section "DMA Support" in the LEUART documentation.

9.4.7 Interrupts

The PL230 dma_done[n:0] signals (one for each channel) as well as the dma_err signal, are available as interrupts to the Cortex-M4 core. They are combined into one interrupt vector, DMA_INT. If the interrupt for the DMA is enabled in the ARM Cortex-M4 core, an interrupt will be made if one or more of the interrupt flags in DMA_IF and their corresponding bits in DMA_IEN are set.

9.5 Examples

A basic example of how to program the DMA for transferring 42 bytes from the USART1 to memory location 0x20003420. Assumes that the channel 0 is currently disabled, and that the DMA_ALTCTRLBASE register has already been configured.

Example 9.1. DMA Transfer

1. Configure the channel select for using USART1 with DMA channel 0 a. Write SOURCESEL=0b001101 and SIGSEL=XX to DMA_CHCTRL0 2. Configure the primary channel descriptor for DMA channel 0 a. Write XX (read address of USART1) to src_data_end_ptr b. Write 0x20003420 + 40 to dst_data_end_ptr c c. Write these values to channel_cfg for channel 0: i. dst_inc=b01 (destination halfword address increment) ii. dst_size=b01 (halfword transfer size) iii. src_inc=b11 (no address increment for source) iv. src_size=01 (halfword transfer size) v. dst_prot_ctrl=000 (no cache/buffer/privilege) vi. src_prot_ctrl=000 (no cache/buffer/privilege) vii.R_power=b0000 (arbitrate after each DMA transfer) viii.n_minus_1=d20 (transfer 21 halfwords) ix. next_useburst=b0 (not applicable) x. cycle_ctrl=b001 (basic operating mode) 3. Enable the DMA a. Write EN=1 to DMA_CONFIG 4. Disable the single requests for channel 0 (i.e., do not react to data available, wait for buffer full) a. Write DMA_CHUSEBURSTS[0]=1 5. Enable buffer-full requests for channel 0 a. Write DMA_CHREQMASKC[0]=1 6. Use the primary data structure for channel 0 a. Write DMA_CHALTC[0]=1 7. Enable channel 0 a. Write DMA_CHENS[0]=1 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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9.6 Register Map

The offset register address is relative to the registers base address.

Offset

0x000 0x004

0x008 0x00C

0x010

0x014

0x018

0x01C

0x020

0x024

0x028 0x02C

0x030

0x034

0x038

0x03C

0x04C 0xE10

0xE18

0x1000

0x1004

0x1008

0x100C

0x1010 0x1014

0x1020

0x1024 0x1060

0x1100

...

0x112C

Name

DMA_STATUS DMA_CONFIG

DMA_CTRLBASE DMA_ALTCTRLBASE

DMA_CHWAITSTATUS

DMA_CHSWREQ

DMA_CHUSEBURSTS

DMA_CHUSEBURSTC

DMA_CHREQMASKS

DMA_CHREQMASKC

DMA_CHENS DMA_CHENC

DMA_CHALTS

DMA_CHALTC

DMA_CHPRIS

DMA_CHPRIC

DMA_ERRORC DMA_CHREQSTATUS

DMA_CHSREQSTATUS

DMA_IF

DMA_IFS

DMA_IFC

DMA_IEN

DMA_CTRL DMA_RDS

DMA_LOOP0

DMA_LOOP1 DMA_RECT0

DMA_CH0_CTRL DMA_CHx_CTRL DMA_CH11_CTRL

Type

RWH RW RWH RW RW RW R W RW R R W1 RW1H W1 RW1 W1 RW1 W1 RW1 W1 RW1 W1 RW R R R W1 W1 RW RW RW

Description

DMA Status Registers DMA Configuration Register

Channel Control Data Base Pointer Register Channel Alternate Control Data Base Pointer Register

Channel Wait on Request Status Register

Channel Software Request Register

Channel Useburst Set Register

Channel Useburst Clear Register

Channel Request Mask Set Register

Channel Request Mask Clear Register

Channel Enable Set Register Channel Enable Clear Register

Channel Alternate Set Register

Channel Alternate Clear Register

Channel Priority Set Register

Channel Priority Clear Register

Bus Error Clear Register Channel Request Status

Channel Single Request Status

Interrupt Flag Register

Interrupt Flag Set Register

Interrupt Flag Clear Register

Interrupt Enable register

DMA Control Register DMA Retain Descriptor State

Channel 0 Loop Register

Channel 1 Loop Register Channel 0 Rectangle Register

Channel Control Register Channel Control Register Channel Control Register

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9.7 Register Description

9.7.1 DMA_STATUS - DMA Status Registers

Offset

0x000

Reset Access Bit Position Name Bit

31:21

20:16

15:8

7:4

3:1

0

Name

Reserved

5 6 7 8 9 10 Value 0 1 2 3 4

Reset

Mode IDLE RDCHCTRLDATA RDSRCENDPTR RDDSTENDPTR RDSRCDATA WRDSTDATA WAITREQCLR WRCHCTRLDATA STALLED DONE PERSCATTRANS

Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CHNUM 0x0B Number of available DMA channels minus one.

R

Reserved

Channel Number

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

STATE 0x0 R

Control Current State

State can be one of the following. Higher values (11-15) are undefined.

Description Idle Reading channel controller data Reading source data end pointer Reading destination data end pointer Reading source data Writing destination data Waiting for DMA request to clear Writing channel controller data Stalled Done Peripheral scatter-gather transition

Reserved

EN

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 When this bit is 1, the DMA is enabled.

R

DMA Enable Status

9.7.2 DMA_CONFIG - DMA Configuration Register

Offset

0x004

Reset Access Bit Position Name Bit

31:6

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

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Bit

5

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Name Reset Access Description

CHPROT 0 W

Channel Protection Control

Control whether accesses done by the DMA controller are privileged or not. When CHPROT = 1 then HPROT is HIGH and the access is privileged. When CHPROT = 0 then HPROT is LOW and the access is non-privileged.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

EN 0 Set this bit to enable the DMA controller.

W

Enable DMA

9.7.3 DMA_CTRLBASE - Channel Control Data Base Pointer Register

Offset

0x008

Bit Position Reset Access Name Bit

31:0

Name Reset Access Description

CTRLBASE 0x00000000 RW

Channel Control Data Base Pointer

The base pointer for a location in system memory that holds the channel control data structure. This register must be written to point to a location in system memory with the channel control data structure before the DMA can be used. Note that ctrl_base_ptr[8:0] must be 0.

9.7.4 DMA_ALTCTRLBASE - Channel Alternate Control Data Base Pointer Register

Offset

0x00C

Bit Position Reset Access Name Bit

31:0

Name

ALTCTRLBASE

Reset

0x00000100

Access

R

Description Channel Alternate Control Data Base Pointer

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Name Reset Access Description

The base address of the alternate data structure. This register will read as DMA_CTRLBASE + 0x100.

9.7.5 DMA_CHWAITSTATUS - Channel Wait on Request Status Register

Bit Position Offset

0x010

Reset Access Name Bit

31:12

11 10 9 8 7 6 5 4 3 2 1 0

Name Reset Access Description

Reserved

CH11WAITSTATUS

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

1 Status for wait on request for channel 11.

CH10WAITSTATUS 1 Status for wait on request for channel 10.

R R

Channel 11 Wait on Request Status Channel 10 Wait on Request Status

R

Channel 9 Wait on Request Status

CH9WAITSTATUS 1 Status for wait on request for channel 9.

CH8WAITSTATUS 1 Status for wait on request for channel 8.

CH7WAITSTATUS 1 Status for wait on request for channel 7.

CH6WAITSTATUS 1 Status for wait on request for channel 6.

CH5WAITSTATUS 1 Status for wait on request for channel 5.

CH4WAITSTATUS 1 Status for wait on request for channel 4.

CH3WAITSTATUS 1 Status for wait on request for channel 3.

CH2WAITSTATUS 1 Status for wait on request for channel 2.

CH1WAITSTATUS 1 Status for wait on request for channel 1.

CH0WAITSTATUS 1 Status for wait on request for channel 0.

R R R R R R R R R

Channel 8 Wait on Request Status Channel 7 Wait on Request Status Channel 6 Wait on Request Status Channel 5 Wait on Request Status Channel 4 Wait on Request Status Channel 3 Wait on Request Status Channel 2 Wait on Request Status Channel 1 Wait on Request Status Channel 0 Wait on Request Status

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9.7.6 DMA_CHSWREQ - Channel Software Request Register

Offset

0x014

Reset Access Bit Position Name Bit

31:12

11 10 9 8 7 6 5 4 3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH11SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 11 Software Request

CH10SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 10 Software Request

CH9SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 9 Software Request

CH8SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 8 Software Request

CH7SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 7 Software Request

CH6SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 6 Software Request

CH5SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 5 Software Request

CH4SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 4 Software Request

CH3SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 3 Software Request

CH2SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 2 Software Request

CH1SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 1 Software Request

CH0SWREQ 0 W1 Write 1 to this bit to generate a DMA request for this channel.

Channel 0 Software Request

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9.7.7 DMA_CHUSEBURSTS - Channel Useburst Set Register

Bit Position Offset

0x018

Reset Access Name Bit

31:12

11 10 9 8 7 6 5 4 3 2 1 0

Name

Reserved

Value 0 1

Reset

Mode SINGLEANDBURST BURSTONLY

Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH11USEBURSTS 0 See description for channel 0.

CH10USEBURSTS 0 See description for channel 0.

CH9USEBURSTS 0 See description for channel 0.

CH8USEBURSTS 0 See description for channel 0.

CH7USEBURSTS 0 See description for channel 0.

CH6USEBURSTS 0 See description for channel 0.

CH5USEBURSTS 0 See description for channel 0.

CH4USEBURSTS 0 See description for channel 0.

CH3USEBURSTS 0 See description for channel 0.

CH2USEBURSTS 0 See description for channel 0.

CH1USEBURSTS 0 See description for channel 0.

RW1H RW1H RW1H RW1H RW1H RW1H RW1H RW1H RW1H RW1H RW1H

Channel 11 Useburst Set Channel 10 Useburst Set Channel 9 Useburst Set Channel 8 Useburst Set Channel 7 Useburst Set Channel 6 Useburst Set Channel 5 Useburst Set Channel 4 Useburst Set Channel 3 Useburst Set Channel 2 Useburst Set Channel 1 Useburst Set

CH0USEBURSTS 0 RW1H

Channel 0 Useburst Set

Write to 1 to enable the useburst setting for this channel. Reading returns the useburst status. After the penultimate 2^R transfer completes, if the number of remaining transfers, N, is less than 2^R then the controller resets the chnl_useburst_set bit to 0.

This enables you to complete the remaining transfers using dma_req[] or dma_sreq[]. In peripheral scatter-gather mode, if the next_useburst bit is set in channel_cfg then the controller sets the chnl_useburst_set[C] bit to a 1, when it completes the DMA cycle that uses the alternate data structure.

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9.7.8 DMA_CHUSEBURSTC - Channel Useburst Clear Register

Offset

0x01C

Reset Access Bit Position Name Bit

31:12

11 10 9 8 7 6 5 4 3 2 1 0

Name Reset Access Description

Reserved

CH11USEBURSTC

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 W1 Write to 1 to disable useburst setting for this channel.

CH10USEBURSTC 0 W1 Write to 1 to disable useburst setting for this channel.

CH9USEBURSTC 0 W1 Write to 1 to disable useburst setting for this channel.

CH08USEBURSTC 0 W1 Write to 1 to disable useburst setting for this channel.

CH7USEBURSTC 0 W1 Write to 1 to disable useburst setting for this channel.

CH6USEBURSTC 0 W1 Write to 1 to disable useburst setting for this channel.

CH5USEBURSTC 0 W1 Write to 1 to disable useburst setting for this channel.

CH4USEBURSTC 0 W1 Write to 1 to disable useburst setting for this channel.

CH3USEBURSTC 0 W1 Write to 1 to disable useburst setting for this channel.

CH2USEBURSTC 0 W1 Write to 1 to disable useburst setting for this channel.

CH1USEBURSTC 0 W1 Write to 1 to disable useburst setting for this channel.

CH0USEBURSTC 0 W1 Write to 1 to disable useburst setting for this channel.

Channel 11 Useburst Clear Channel 10 Useburst Clear Channel 9 Useburst Clear Channel 8 Useburst Clear Channel 7 Useburst Clear Channel 6 Useburst Clear Channel 5 Useburst Clear Channel 4 Useburst Clear Channel 3 Useburst Clear Channel 2 Useburst Clear Channel 1 Useburst Clear Channel 0 Useburst Clear

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9.7.9 DMA_CHREQMASKS - Channel Request Mask Set Register

Offset

0x020

Reset Access Bit Position Name Bit

31:12

11 10 9 8 7 6 5 4 3 2 1 0

Name Reset Access Description

Reserved

CH11REQMASKS

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 RW1 Write to 1 to disable peripheral requests for this channel.

CH10REQMASKS 0 RW1 Write to 1 to disable peripheral requests for this channel.

CH9REQMASKS 0 RW1 Write to 1 to disable peripheral requests for this channel.

CH8REQMASKS 0 RW1 Write to 1 to disable peripheral requests for this channel.

CH7REQMASKS 0 RW1 Write to 1 to disable peripheral requests for this channel.

CH6REQMASKS 0 RW1 Write to 1 to disable peripheral requests for this channel.

CH5REQMASKS 0 RW1 Write to 1 to disable peripheral requests for this channel.

CH4REQMASKS 0 RW1 Write to 1 to disable peripheral requests for this channel.

CH3REQMASKS 0 RW1 Write to 1 to disable peripheral requests for this channel.

CH2REQMASKS 0 RW1 Write to 1 to disable peripheral requests for this channel.

CH1REQMASKS 0 RW1 Write to 1 to disable peripheral requests for this channel.

CH0REQMASKS 0 RW1 Write to 1 to disable peripheral requests for this channel.

Channel 11 Request Mask Set Channel 10 Request Mask Set Channel 9 Request Mask Set Channel 8 Request Mask Set Channel 7 Request Mask Set Channel 6 Request Mask Set Channel 5 Request Mask Set Channel 4 Request Mask Set Channel 3 Request Mask Set Channel 2 Request Mask Set Channel 1 Request Mask Set Channel 0 Request Mask Set

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9.7.10 DMA_CHREQMASKC - Channel Request Mask Clear Register

Offset

0x024

Reset Access Bit Position Name Bit

31:12

11 10 9 8 7 6 5 4 3 2 1 0

Name Reset Access Description

Reserved

CH11REQMASKC

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 W1 Write to 1 to enable peripheral requests for this channel.

CH10REQMASKC 0 W1 Write to 1 to enable peripheral requests for this channel.

CH9REQMASKC 0 W1 Write to 1 to enable peripheral requests for this channel.

CH8REQMASKC 0 W1 Write to 1 to enable peripheral requests for this channel.

Channel 11 Request Mask Clear Channel 10 Request Mask Clear Channel 9 Request Mask Clear Channel 8 Request Mask Clear Channel 7 Request Mask Clear

CH7REQMASKC 0 W1 Write to 1 to enable peripheral requests for this channel.

CH6REQMASKC 0 W1 Write to 1 to enable peripheral requests for this channel.

CH5REQMASKC 0 W1 Write to 1 to enable peripheral requests for this channel.

CH4REQMASKC 0 W1 Write to 1 to enable peripheral requests for this channel.

CH3REQMASKC 0 W1 Write to 1 to enable peripheral requests for this channel.

CH2REQMASKC 0 W1 Write to 1 to enable peripheral requests for this channel.

CH1REQMASKC 0 W1 Write to 1 to enable peripheral requests for this channel.

CH0REQMASKC 0 W1 Write to 1 to enable peripheral requests for this channel.

Channel 6 Request Mask Clear Channel 5 Request Mask Clear Channel 4 Request Mask Clear Channel 3 Request Mask Clear Channel 2 Request Mask Clear Channel 1 Request Mask Clear Channel 0 Request Mask Clear

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9.7.11 DMA_CHENS - Channel Enable Set Register

Offset

0x028

Reset Bit Position Access Name Bit

31:12

11 10 9 8 7 6 5 4 3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH11ENS 0 RW1

Channel 11 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

CH10ENS 0 RW1

Channel 10 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

CH9ENS 0 RW1

Channel 9 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

CH8ENS 0 RW1

Channel 8 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

CH7ENS 0 RW1

Channel 7 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

CH6ENS 0 RW1

Channel 6 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

CH5ENS 0 RW1

Channel 5 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

CH4ENS 0 RW1

Channel 4 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

CH3ENS 0 RW1

Channel 3 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

CH2ENS 0 RW1

Channel 2 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

CH1ENS 0 RW1

Channel 1 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

CH0ENS 0 RW1

Channel 0 Enable Set

Write to 1 to enable this channel. Reading returns the enable status of the channel.

9.7.12 DMA_CHENC - Channel Enable Clear Register

Offset

0x02C

Reset Access Bit Position Name

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Bit

31:12

11 10 9 8 7 6 5 4 3 2 1 0

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Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH11ENC 0 W1

Channel 11 Enable Clear

Write to 1 to disable this channel. See also description for channel 0.

CH10ENC 0 W1

Channel 10 Enable Clear

Write to 1 to disable this channel. See also description for channel 0.

CH9ENC 0 W1

Channel 9 Enable Clear

Write to 1 to disable this channel. See also description for channel 0.

CH8ENC 0 W1

Channel 8 Enable Clear

Write to 1 to disable this channel. See also description for channel 0.

CH7ENC 0 W1

Channel 7 Enable Clear

Write to 1 to disable this channel. See also description for channel 0.

CH6ENC 0 W1

Channel 6 Enable Clear

Write to 1 to disable this channel. See also description for channel 0.

CH5ENC 0 W1

Channel 5 Enable Clear

Write to 1 to disable this channel. See also description for channel 0.

CH4ENC 0 W1

Channel 4 Enable Clear

Write to 1 to disable this channel. See also description for channel 0.

CH3ENC 0 W1

Channel 3 Enable Clear

Write to 1 to disable this channel. See also description for channel 0.

CH2ENC 0 W1

Channel 2 Enable Clear

Write to 1 to disable this channel. See also description for channel 0.

CH1ENC 0 W1

Channel 1 Enable Clear

Write to 1 to disable this channel. See also description for channel 0.

CH0ENC 0 W1

Channel 0 Enable Clear

Write to 1 to disable this channel. Note that the controller disables a channel, by setting the appropriate bit, when either it completes the DMA cycle, or it reads a channel_cfg memory location which has cycle_ctrl = b000, or an ERROR occurs on the AHB-Lite bus.

A read from this field returns the value of CH0ENS from the DMA_CHENS register.

9.7.13 DMA_CHALTS - Channel Alternate Set Register

Offset

0x030

Reset Access Bit Position Name Bit

31:12

11 10 9

Name

Reserved

CH11ALTS Write to 1 to select the alternate structure for this channel.

CH10ALTS 0 RW1 Write to 1 to select the alternate structure for this channel.

CH9ALTS

Reset

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 0

Access

RW1 RW1

Description Channel 11 Alternate Structure Set Channel 10 Alternate Structure Set Channel 9 Alternate Structure Set

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Bit

8 7 6 5 4 3 2 1 0

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Name Reset Access

Write to 1 to select the alternate structure for this channel.

CH8ALTS 0 RW1 Write to 1 to select the alternate structure for this channel.

CH7ALTS 0 RW1 Write to 1 to select the alternate structure for this channel.

CH6ALTS 0 RW1 Write to 1 to select the alternate structure for this channel.

CH5ALTS 0 RW1 Write to 1 to select the alternate structure for this channel.

CH4ALTS 0 RW1 Write to 1 to select the alternate structure for this channel.

CH3ALTS 0 RW1 Write to 1 to select the alternate structure for this channel.

CH2ALTS 0 RW1 Write to 1 to select the alternate structure for this channel.

CH1ALTS 0 RW1 Write to 1 to select the alternate structure for this channel.

CH0ALTS 0 RW1 Write to 1 to select the alternate structure for this channel.

Description Channel 8 Alternate Structure Set Channel 7 Alternate Structure Set Channel 6 Alternate Structure Set Channel 5 Alternate Structure Set Channel 4 Alternate Structure Set Channel 3 Alternate Structure Set Channel 2 Alternate Structure Set Channel 1 Alternate Structure Set Channel 0 Alternate Structure Set

9.7.14 DMA_CHALTC - Channel Alternate Clear Register

Bit Position Offset

0x034

Reset Access Name Bit

31:12

11 10 9 8 7 6

Name Reset Access Description

Reserved

CH11ALTC

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 W1 Write to 1 to select the primary structure for this channel.

CH10ALTC 0 W1 Write to 1 to select the primary structure for this channel.

CH9ALTC 0 W1 Write to 1 to select the primary structure for this channel.

CH8ALTC 0 W1 Write to 1 to select the primary structure for this channel.

CH7ALTC 0 W1 Write to 1 to select the primary structure for this channel.

CH6ALTC 0 W1 Write to 1 to select the primary structure for this channel.

Channel 11 Alternate Clear Channel 10 Alternate Clear Channel 9 Alternate Clear Channel 8 Alternate Clear Channel 7 Alternate Clear Channel 6 Alternate Clear

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3 2 1 0

Bit

5 4

Name Reset Access

CH5ALTC 0 W1 Write to 1 to select the primary structure for this channel.

CH4ALTC 0 W1 Write to 1 to select the primary structure for this channel.

CH3ALTC 0 W1 Write to 1 to select the primary structure for this channel.

CH2ALTC 0 W1 Write to 1 to select the primary structure for this channel.

CH1ALTC 0 W1 Write to 1 to select the primary structure for this channel.

CH0ALTC 0 W1 Write to 1 to select the primary structure for this channel.

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Description Channel 5 Alternate Clear Channel 4 Alternate Clear Channel 3 Alternate Clear Channel 2 Alternate Clear Channel 1 Alternate Clear Channel 0 Alternate Clear

9.7.15 DMA_CHPRIS - Channel Priority Set Register

Bit Position Offset

0x038

Reset Access Name Bit

31:12

11 10 9 8 7 6 5 4 3 2

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH11PRIS 0 RW1

Channel 11 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

CH10PRIS 0 RW1

Channel 10 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

CH9PRIS 0 RW1

Channel 9 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

CH8PRIS 0 RW1

Channel 8 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

CH7PRIS 0 RW1

Channel 7 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

CH6PRIS 0 RW1

Channel 6 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

CH5PRIS 0 RW1

Channel 5 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

CH4PRIS 0 RW1

Channel 4 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

CH3PRIS 0 RW1

Channel 3 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

CH2PRIS 0 RW1

Channel 2 High Priority Set

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Bit

1 0

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Name Reset Access Description

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

CH1PRIS 0 RW1

Channel 1 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

CH0PRIS 0 RW1

Channel 0 High Priority Set

Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.

9.7.16 DMA_CHPRIC - Channel Priority Clear Register

Bit Position Offset

0x03C

Reset Access Name Bit

31:12

11 10 9 8 7 6 5 4 3 2 1 0

Name Reset Access Description

Reserved

CH11PRIC

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Write to 1 to clear high priority for this channel.

W1 CH10PRIC 0 Write to 1 to clear high priority for this channel.

W1 CH9PRIC 0 Write to 1 to clear high priority for this channel.

W1 CH8PRIC 0 Write to 1 to clear high priority for this channel.

W1 CH7PRIC 0 Write to 1 to clear high priority for this channel.

W1 CH6PRIC 0 Write to 1 to clear high priority for this channel.

W1 CH5PRIC 0 Write to 1 to clear high priority for this channel.

W1 CH4PRIC 0 Write to 1 to clear high priority for this channel.

W1 CH3PRIC 0 Write to 1 to clear high priority for this channel.

W1 CH2PRIC 0 Write to 1 to clear high priority for this channel.

W1 CH1PRIC 0 Write to 1 to clear high priority for this channel.

W1 CH0PRIC 0 Write to 1 to clear high priority for this channel.

W1

Channel 11 High Priority Clear Channel 10 High Priority Clear Channel 9 High Priority Clear Channel 8 High Priority Clear Channel 7 High Priority Clear Channel 6 High Priority Clear Channel 5 High Priority Clear Channel 4 High Priority Clear Channel 3 High Priority Clear Channel 2 High Priority Clear Channel 1 High Priority Clear Channel 0 High Priority Clear

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9.7.17 DMA_ERRORC - Bus Error Clear Register

Offset

0x04C

Reset Access Bit Position Name Bit

31:1

0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

ERRORC 0 RW

Bus Error Clear

This bit is set high if an AHB bus error has occurred. Writing a 1 to this bit will clear the bit. If the error is deasserted at the same time as an error occurs on the bus, the error condition takes precedence and ERRORC remains asserted.

9.7.18 DMA_CHREQSTATUS - Channel Request Status

Bit Position Offset

0xE10

Reset Access Name Bit

31:12

11 10 9 8 7 6

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH11REQSTATUS 0 R

Channel 11 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

CH10REQSTATUS 0 R

Channel 10 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

CH9REQSTATUS 0 R

Channel 9 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

CH8REQSTATUS 0 R

Channel 8 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

CH7REQSTATUS 0 R

Channel 7 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

CH6REQSTATUS 0 R

Channel 6 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

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Bit

5 4 3 2 1 0

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Name Reset Access Description

CH5REQSTATUS 0 R

Channel 5 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

CH4REQSTATUS 0 R

Channel 4 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

CH3REQSTATUS 0 R

Channel 3 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

CH2REQSTATUS 0 R

Channel 2 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

CH1REQSTATUS 0 R

Channel 1 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

CH0REQSTATUS 0 R

Channel 0 Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 R DMA transfers.

9.7.19 DMA_CHSREQSTATUS - Channel Single Request Status

Bit Position Offset

0xE18

Reset Access Name Bit

31:12

11 10 9 8 7 6

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH11SREQSTATUS 0 R

Channel 11 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

CH10SREQSTATUS 0 R

Channel 10 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

CH9SREQSTATUS 0 R

Channel 9 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

CH8SREQSTATUS 0 R

Channel 8 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

CH7SREQSTATUS 0 R

Channel 7 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

CH6SREQSTATUS 0 R

Channel 6 Single Request Status

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5 4 3 2 1 0

Bit

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Name Reset Access Description

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

CH5SREQSTATUS 0 R

Channel 5 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

CH4SREQSTATUS 0 R

Channel 4 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

CH3SREQSTATUS 0 R

Channel 3 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

CH2SREQSTATUS 0 R

Channel 2 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

CH1SREQSTATUS 0 R

Channel 1 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

CH0SREQSTATUS 0 R

Channel 0 Single Request Status

When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.

9.7.20 DMA_IF - Interrupt Flag Register

Offset

0x1000

Reset Access Bit Position Name Bit

31

30:12

11 10 9 8 7 6 5

Name Reset Access Description

ERR 0 R This flag is set when an error has occurred on the AHB bus.

DMA Error Interrupt Flag

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH11DONE 0 R

DMA Channel 11 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

CH10DONE 0 R

DMA Channel 10 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

CH9DONE 0 R

DMA Channel 9 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

CH8DONE 0 R

DMA Channel 8 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

CH7DONE 0 R

DMA Channel 7 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

CH6DONE 0 R

DMA Channel 6 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

CH5DONE 0 R

DMA Channel 5 Complete Interrupt Flag

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Bit

4 3 2 1 0

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Name Reset Access Description

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

CH4DONE 0 R

DMA Channel 4 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

CH3DONE 0 R

DMA Channel 3 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

CH2DONE 0 R

DMA Channel 2 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

CH1DONE 0 R

DMA Channel 1 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

CH0DONE 0 R

DMA Channel 0 Complete Interrupt Flag

Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.

9.7.21 DMA_IFS - Interrupt Flag Set Register

Offset

0x1004

Reset Access Bit Position Name Bit

31

30:12

11 10 9 8 7 6 5 4 3 2

Name Reset Access Description

ERR 0 Set to 1 to set DMA error interrupt flag.

Reserved

W1

DMA Error Interrupt Flag Set

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH11DONE 0 W1

DMA Channel 11 Complete Interrupt Flag Set

Write to 1 to set the corresponding DMA channel complete interrupt flag.

CH10DONE 0 W1

DMA Channel 10 Complete Interrupt Flag Set

Write to 1 to set the corresponding DMA channel complete interrupt flag.

CH9DONE 0 W1

DMA Channel 9 Complete Interrupt Flag Set

Write to 1 to set the corresponding DMA channel complete interrupt flag.

CH8DONE 0 W1

DMA Channel 8 Complete Interrupt Flag Set

Write to 1 to set the corresponding DMA channel complete interrupt flag.

CH7DONE 0 W1

DMA Channel 7 Complete Interrupt Flag Set

Write to 1 to set the corresponding DMA channel complete interrupt flag.

CH6DONE 0 W1

DMA Channel 6 Complete Interrupt Flag Set

Write to 1 to set the corresponding DMA channel complete interrupt flag.

CH5DONE 0 W1

DMA Channel 5 Complete Interrupt Flag Set

Write to 1 to set the corresponding DMA channel complete interrupt flag.

CH4DONE 0 W1

DMA Channel 4 Complete Interrupt Flag Set

Write to 1 to set the corresponding DMA channel complete interrupt flag.

CH3DONE 0 W1

DMA Channel 3 Complete Interrupt Flag Set

Write to 1 to set the corresponding DMA channel complete interrupt flag.

CH2DONE 0 W1

DMA Channel 2 Complete Interrupt Flag Set

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Bit

1 0

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Name Reset Access Description

Write to 1 to set the corresponding DMA channel complete interrupt flag.

CH1DONE 0 W1

DMA Channel 1 Complete Interrupt Flag Set

Write to 1 to set the corresponding DMA channel complete interrupt flag.

CH0DONE 0 W1

DMA Channel 0 Complete Interrupt Flag Set

Write to 1 to set the corresponding DMA channel complete interrupt flag.

9.7.22 DMA_IFC - Interrupt Flag Clear Register

Offset

0x1008

Reset Access Bit Position Name Bit

31

30:12

11 10 9 8 7 6 5 4 3 2 1 0

Name Reset Access Description

ERR 0 W1

DMA Error Interrupt Flag Clear

Set to 1 to clear DMA error interrupt flag. Note that if an error happened, the Bus Error Clear Register must be used to clear the DMA.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH11DONE 0 W1

DMA Channel 11 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

CH10DONE 0 W1

DMA Channel 10 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

CH9DONE 0 W1

DMA Channel 9 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

CH8DONE 0 W1

DMA Channel 8 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

CH7DONE 0 W1

DMA Channel 7 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

CH6DONE 0 W1

DMA Channel 6 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

CH5DONE 0 W1

DMA Channel 5 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

CH4DONE 0 W1

DMA Channel 4 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

CH3DONE 0 W1

DMA Channel 3 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

CH2DONE 0 W1

DMA Channel 2 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

CH1DONE 0 W1

DMA Channel 1 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

CH0DONE 0 W1

DMA Channel 0 Complete Interrupt Flag Clear

Write to 1 to clear the corresponding DMA channel complete interrupt flag.

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9.7.23 DMA_IEN - Interrupt Enable register

Offset

0x100C

Reset Access Bit Position Name Bit

31

30:12

11 10 9 8 7 6 5 4 3 2 1 0

Name Reset Access Description

ERR 0 Set this bit to enable interrupt on AHB bus error.

RW

Reserved

DMA Error Interrupt Flag Enable

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH11DONE 0 RW

DMA Channel 11 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

CH10DONE 0 RW

DMA Channel 10 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

CH9DONE 0 RW

DMA Channel 9 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

CH8DONE 0 RW

DMA Channel 8 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

CH7DONE 0 RW

DMA Channel 7 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

CH6DONE 0 RW

DMA Channel 6 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

CH5DONE 0 RW

DMA Channel 5 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

CH4DONE 0 RW

DMA Channel 4 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

CH3DONE 0 RW

DMA Channel 3 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

CH2DONE 0 RW

DMA Channel 2 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

CH1DONE 0 RW

DMA Channel 1 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

CH0DONE 0 RW

DMA Channel 0 Complete Interrupt Enable

Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.

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9.7.24 DMA_CTRL - DMA Control Register

Offset

0x1010

Reset Access Bit Position Name Bit

31:2

1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PRDU 0 RW

Prevent Rect Descriptor Update

Allows the reuse of a rect descriptor. When active CH0 and no others can have RDS set DESCRECT 0 RW

Descriptor Specifies Rectangle

Word 4 (user data) in dma descriptor specifies WIDTH, HEIGHT and SRCSTRIDE for rectangle copies. WIDTH is given by bits 9:0, HEIGHT is given by bits 19:10, and SRCSTRIDE is given by bits 30:20

9.7.25 DMA_RDS - DMA Retain Descriptor State

Offset

0x1014

Reset Access Bit Position Name Bit

31:12

11 10 9 8 7 6

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RDSCH11 0 RW

Retain Descriptor State

Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration cycle if the next channel is the same as the previous RDSCH10 0 RW

Retain Descriptor State

Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration cycle if the next channel is the same as the previous RDSCH9 0 RW

Retain Descriptor State

Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration cycle if the next channel is the same as the previous RDSCH8 0 RW

Retain Descriptor State

Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration cycle if the next channel is the same as the previous RDSCH7 0 RW

Retain Descriptor State

Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration cycle if the next channel is the same as the previous RDSCH6 0 RW

Retain Descriptor State

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Bit

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Name Reset Access Description

RDSCH5 0 RW

Retain Descriptor State

Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration cycle if the next channel is the same as the previous RDSCH4 0 RW

Retain Descriptor State

Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration cycle if the next channel is the same as the previous RDSCH3 0 RW

Retain Descriptor State

Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration cycle if the next channel is the same as the previous RDSCH2 0 RW

Retain Descriptor State

Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration cycle if the next channel is the same as the previous RDSCH1 0 RW

Retain Descriptor State

Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration cycle if the next channel is the same as the previous RDSCH0 0 RW

Retain Descriptor State

Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration cycle if the next channel is the same as the previous

9.7.26 DMA_LOOP0 - Channel 0 Loop Register

Bit Position Offset

0x1020

Reset Access Name Bit

31:17

16

15:10

9:0

Name Reset Access Description

Reserved

EN Loop enable for channel 0

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 RW

DMA Channel 0 Loop Enable

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

WIDTH 0x000 RWH Reload value for N_MINUS_1 when loop is enabled

Loop Width

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9.7.27 DMA_LOOP1 - Channel 1 Loop Register

Bit Position Offset

0x1024

Reset Access Name Bit

31:17

16

15:10

9:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

EN Loop enable for channel 1

Reserved

0 RW

DMA Channel 1 Loop Enable

WIDTH

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x000 RW Reload value for N_MINUS_1 when loop is enabled

DMA Channel 1 Loop Width

9.7.28 DMA_RECT0 - Channel 0 Rectangle Register

Bit Position Offset

0x1060

Reset Access Name Bit

31:21 20:10 9:0

Name Reset Access Description

DSTSTRIDE 0x000 RW Space between start of lines in destination rectangle

DMA Channel 0 Destination Stride

SRCSTRIDE 0x000 Space between start of lines in source rectangle RWH

DMA Channel 0 Source Stride

HEIGHT 0x000 RWH

DMA Channel 0 Rectangle Height

Number of lines when doing rectangle copy. Set to the number of lines - 1.

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9.7.29 DMA_CHx_CTRL - Channel Control Register

Offset

0x1100

Bit Position Reset Access Name Bit

31:22

21:16

15:4

3:0

Name Reset Access Description

Reserved

SOURCESEL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x00 Select input source to DMA channel.

RW

Source Select

Value 0b000000 0b001000 0b001010 0b001100 0b001101 0b001110 0b010000 0b010001 0b010100 0b010101 0b011000 0b011001 0b011010 0b011011 0b101100 0b101101 0b110000 0b110001 0b110010 Mode NONE ADC0 DAC0 USARTRF0 USART1 USART2 LEUART0 LEUART1 I2C0 I2C1 TIMER0 TIMER1 TIMER2 TIMER3 UART0 UART1 MSC AES LESENSE Value SOURCESEL = 0b000000 (NONE) 0bxxxx Mode OFF SOURCESEL = 0b001000 (ADC0) 0b0000 0b0001 SOURCESEL = 0b001010 (DAC0) 0b0000 0b0001 SOURCESEL (USARTRF0) = 0b001100 ADC0SINGLE ADC0SCAN DAC0CH0 DAC0CH1 0b0000 0b0001 0b0010 SOURCESEL (USART1) = 0b001101 USARTRF0RXDATAV USARTRF0TXBL USARTRF0TXEMPTY Description No source selected Analog to Digital Converter 0 Digital to Analog Converter 0 Universal Synchronous/Asynchronous Receiver/Transmitter 0 Universal Synchronous/Asynchronous Receiver/Transmitter 1 Universal Synchronous/Asynchronous Receiver/Transmitter 2 Low Energy UART 0 Low Energy UART 1 I2C 0 I2C 1 Timer 0 Timer 1 Timer 2 Timer 3 Universal Asynchronous Receiver/Transmitter 0 Universal Asynchronous Receiver/Transmitter 1 Advanced Encryption Standard Accelerator Low Energy Sensor Interface

Reserved

SIGSEL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 Select input signal to DMA channel.

RW

Signal Select

Description Channel input selection is turned off ADC0SINGLE ADC0SCAN DAC0CH0 DAC0CH1 USARTRF0RXDATAV REQ/SREQ USARTRF0TXBL REQ/SREQ USARTRF0TXEMPTY 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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Bit Name Reset Access

Value 0b0000 0b0001 0b0010 0b0011 0b0100 SOURCESEL (USART2) = 0b001110 Mode USART1RXDATAV USART1TXBL USART1TXEMPTY USART1RXDATAVRIGHT USART1TXBLRIGHT 0b0000 0b0001 0b0010 0b0011 0b0100 SOURCESEL (LEUART0) 0b0000 = 0b010000 USART2RXDATAV USART2TXBL USART2TXEMPTY USART2RXDATAVRIGHT USART2TXBLRIGHT 0b0001 0b0010 SOURCESEL (LEUART1) 0b0000 0b0000 0b0001 SOURCESEL (TIMER0) 0b0000 = 0b010001 0b0001 0b0010 SOURCESEL = 0b010100 (I2C0) 0b0000 0b0001 SOURCESEL = 0b010101 (I2C1) = 0b011000 0b0001 0b0010 0b0011 SOURCESEL (TIMER1) = 0b011001 LEUART0RXDATAV LEUART0TXBL LEUART0TXEMPTY LEUART1RXDATAV LEUART1TXBL LEUART1TXEMPTY I2C0RXDATAV I2C0TXBL I2C1RXDATAV I2C1TXBL TIMER0UFOF TIMER0CC0 TIMER0CC1 TIMER0CC2 0b0000 0b0001 0b0010 TIMER1UFOF TIMER1CC0 TIMER1CC1 TIMER1CC2 0b0011 SOURCESEL (TIMER2) 0b0000 0b0001 0b0010 0b0011 SOURCESEL (TIMER3) 0b0000 = = 0b011010 0b011011 TIMER2UFOF TIMER2CC0 TIMER2CC1 TIMER2CC2 0b0001 0b0010 0b0011 TIMER3UFOF TIMER3CC0 TIMER3CC1 TIMER3CC2 SOURCESEL = 0b101100 (UART0) 0b0000 UART0RXDATAV 0b0001 UART0TXBL 0b0010 SOURCESEL = 0b101101 (UART1) UART0TXEMPTY

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Description

Description USART1RXDATAV REQ/SREQ USART1TXBL REQ/SREQ USART1TXEMPTY USART1RXDATAVRIGHT REQ/SREQ USART1TXBLRIGHT REQ/SREQ USART2RXDATAV REQ/SREQ USART2TXBL REQ/SREQ USART2TXEMPTY USART2RXDATAVRIGHT REQ/SREQ USART2TXBLRIGHT REQ/SREQ LEUART0RXDATAV LEUART0TXBL LEUART0TXEMPTY LEUART1RXDATAV LEUART1TXBL LEUART1TXEMPTY I2C0RXDATAV I2C0TXBL I2C1RXDATAV I2C1TXBL TIMER0UFOF TIMER0CC0 TIMER0CC1 TIMER0CC2 TIMER1UFOF TIMER1CC0 TIMER1CC1 TIMER1CC2 TIMER2UFOF TIMER2CC0 TIMER2CC1 TIMER2CC2 TIMER3UFOF TIMER3CC0 TIMER3CC1 TIMER3CC2 UART0RXDATAV REQ/SREQ UART0TXBL REQ/SREQ UART0TXEMPTY 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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Bit Name Reset Access

Value 0b0000 0b0001 0b0010 SOURCESEL = 0b110000 (MSC) 0b0000 SOURCESEL = 0b110001 (AES) 0b0000 0b0001 0b0010 0b0011 SOURCESEL (LESENSE) 0b0000 = 0b110010 Mode UART1RXDATAV UART1TXBL UART1TXEMPTY MSCWDATA AESDATAWR AESXORDATAWR AESDATARD AESKEYWR LESENSEBUFDATAV

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Description

Description UART1RXDATAV REQ/SREQ UART1TXBL REQ/SREQ UART1TXEMPTY MSCWDATA AESDATAWR AESXORDATAWR AESDATARD AESKEYWR LESENSEBUFDATAV REQ/SREQ 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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10 RMU - Reset Management Unit

0 1 2 3 4

RESETn POWERON BROWNOUT LOCKUP SYSRESETREQ WATCHDOG Reset Managem ent Unit RESET

Quick Facts What?

The RMU ensures correct reset operation.

It is responsible for connecting the different reset sources to the reset lines of the EZR32WG.

Why?

A correct reset sequence is needed to ensure safe and synchronous startup of the EZR32WG. In the case of error situations such as power supply glitches or software crash, the RMU provides proper reset and startup of the EZR32WG.

How?

The Power-on Reset and Brown-out Detector of the EZR32WG provides power line monitoring with exceptionally low power consumption. The cause of the reset may be read from a register, thus providing software with information about the cause of the reset.

10.1 Introduction

The RMU is responsible for handling the reset functionality of the EZR32WG.

10.2 Features

• Reset sources • Power-on Reset (POR) • Brown-out Detection (BOD) on the following power domains: • Regulated domain • Unregulated domain • Analog Power Domain 0 (AVDD0) • Analog Power Domain 1 (AVDD1) • RESETn pin reset • Watchdog reset • EM4 wakeup reset from pin • EM4 wakeup reset from Backup RTC interrupt • Wakeup from Backup Mode • Software triggered reset (SYSRESETREQ) • Core LOCKUP condition • EM4 Detection • A software readable register indicates the cause of the last reset

10.3 Functional Description

The RMU monitors each of the reset sources of the EZR32WG. If one or more reset sources go active, the RMU applies reset to the EZR32WG. When the reset sources go inactive the EZR32WG starts 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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up. At startup the EZR32WG loads the stack pointer and program entry point from memory, and starts execution.

As seen in Figure 10.1 (p. 140) the Power-on Reset, Brown-out Detectors, Watchdog timeout and

RESETn pin all reset the whole system including the Debug Interface. A Core Lockup condition or a System reset request from software resets the whole system except the Debug Interface.

Whenever a reset source is active, the corresponding bit in the RMU_RSTCAUSE register is set. At startup the program code may investigate this register in order to determine the cause of the reset. The register must be cleared by software.

Figure 10.1. RMU Reset Input Sources and Connections.

POR V DD BOD V DD_REGULATED BOD AVDD0 BOD AVDD1 RESETn BOD Filt er EM4 wakeup Backup m ode ex it Reset Managem ent Unit BROWNOUT_UNREGn BROWNOUT_REGn BROWNOUT_AVDD0 BROWNOUT_AVDD1 POWERONn WDOG em 4 Backup m ode RCCLR LOCKUP RMU_RSTCAUSE Edge- t o- pulse filt er LOCKUPRDIS SYSREQRST PORESETn SYSRESETn Cort ex Debug Int erface Core Peripherals

10.3.1 RMU_RSTCAUSE Register

The RMU_RSTCAUSE register indicates the reason for the last reset. The register should be cleared after the value has been read at startup. Otherwise the register may indicate multiple causes for the reset at next startup.

The following procedure must be done to clear RMU_RSTCAUSE: 1. Write a 1 to RCCLR in RMU_CMD 2. Write a 1 to bit 0 in EMU_AUXCTRL 3. Write a 0 to bit 0 in EMU_AUXCTRL

RMU_RSTCAUSE should be interpreted according to Table 10.1 (p. 141) . X bits are don't care. Notice

that it is possible to have multiple reset causes. For example, an external reset and a watchdog reset may happen simultaneously.

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...the world's most energy friendly wireless MCUs Table 10.1. RMU Reset Cause Register Interpretation

Register Value

0bXXXX XXXX XXXX XXX1 0bXXXX XXXX 0XXX XX10 0bXXXX XXXX XXX0 0100 0bXXXX XXXX XXXX 1X00 0bXXXX XXXX XXX1 XX00 0bXXXX X000 0010 0000 0bXXXX X000 01X0 0000 0bXXXX X000 1XX0 0XX0 0bXXXX X001 1XX0 0XX0 0bXXXX X01X XXX0 0000 0bXXXX X10X XXX0 0000 0bXXXX 1XXX XXXX 0XX0 0bXXX1 XXXX XXXX 0XX0 0bXX1X XXXX XXXX 0XX0 0bX1XX XXXX XXXX 0XX0 0b1XXX XXXX XXXX XXX0

Cause

A Power-on Reset has been performed. X bits are don't care.

A Brown-out has been detected on the unregulated power.

A Brown-out has been detected on the regulated power.

An external reset has been applied.

A watchdog reset has occurred.

A lockup reset has occurred.

A system request reset has occurred.

The system has woken up from EM4.

The system has woken up from EM4 on an EM4 wakeup reset request from pin.

A Brown-out has been detected on Analog Power Domain 0 (AVDD0).

A Brown-out has been detected on Analog Power Domain 1 (AVDD1).

A Brown-out has been detected by the Backup BOD on VDD_DREG.

A Brown-out has been detected by the Backup BOD on BU_VIN.

A Brown-out has been detected by the Backup BOD on unregulated power A Brown-out has been detected by the Backup BOD on regulated power.

The system has been in Backup mode.

Note

When exiting EM4 with external reset, both the BODREGRST and BODUNREGRST in RSTCAUSE might be set (i.e. are invalid)

10.3.2 Power-On Reset (POR)

The POR ensures that the EZR32WG does not start up before the supply voltage V DD has reached the threshold voltage VPORthr (see Device Datasheet Electrical Characteristics for details). Before the threshold voltage is reached, the EZR32WG is kept in reset state. The operation of the POR is illustrated

in Figure 10.2 (p. 141) , with the active low POWERONn reset signal. The reason for the “unknown”

region is that the corresponding supply voltage is too low for any reliable operation.

Figure 10.2. RMU Power-on Reset Operation

V V DD VPORt hr POWERONn Unknown

10.3.3 Brown-Out Detector Reset (BOD)

The EZR32WG has 4 brownout detectors, one for the unregulated 3.0 V power, one for the regulated internal power, one for Analog Power Domain 0 (AVDD0), and one for Analog Power Domain 1 (AVDD1).

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The BODs are constantly monitoring the voltages. Whenever the unregulated or regulated power drops below the VBODthr value (see Electrical Characteristics for details), or if the AVDD0 or AVDD1 drops below the voltage at the decouple pin (DEC), the corresponding active low BROWNOUTn line is held low. The BODs also include hysteresis, which prevents instability in the corresponding BROWNOUTn line when the supply is crossing the VBODthr limit or the AVDD bods drops below decouple pin (DEC).

The operation of the BOD is illustrated in Figure 10.3 (p. 142) . The “unknown” regions are handled

by the POR module.

Figure 10.3. RMU Brown-out Detector Operation

V VBODt hr V DD BROWNOUTn Unknown VBODhyst VBODhyst Unknown t im e

10.3.4 RESETn pin Reset

Forcing the RESETn pin low generates a reset of the EZR32WG. The RESETn pin includes an on chip pull-up resistor, and can therefore be left unconnected if no external reset source is needed. Also connected to the RESETn line is a filter which prevents glitches from resetting the EZR32WG.

10.3.5 Watchdog Reset

The Watchdog circuit is a timer which (when enabled) must be cleared by software regularly. If software does not clear it, a Watchdog reset is activated. This functionality provides recovery from a software stalemate. Refer to the Watchdog section for specifications and description.

10.3.6 Lockup Reset

A Cortex-M4 lockup is the result of the core being locked up because of an unrecoverable exception following the activation of the processor’s built-in system state protection hardware.

For more information about the Cortex-M4 lockup conditions see the ARMv7-M Architecture Reference Manual. The Lockup reset does not reset the Debug Interface. Set the LOCKUPRDIS bit in the RMU_CTRL register in order to disable this reset source.

10.3.7 System Reset Request

Software may initiate a reset (e.g. if it finds itself in a non-recoverable state). By writing to the SYSRESETREQ bit in the Application Interrupt and Reset Control Register (see the Cortex-M4 reference manual), a reset is issued. The SYSRESETREQ does not reset the Debug Interface.

10.3.8 EM4 Reset

Whenever EM4 is entered, the EM4RST bit is set. This bit enables the user to identify that the device has been in EM4. Upon wake-up this bit should be cleared by software.

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10.3.9 EM4 Wakeup Reset

Whenever the system is woken up from EM4 on a pin wake-up request, the EM4WURST bit is set. This bit enables the user to identify that the device was woken up from EM4 using a pin wake-up request.

Upon wake-up this bit should be cleared by software.

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10.4 Register Map

The offset register address is relative to the registers base address.

Offset

0x000 0x004

0x008

Name

RMU_CTRL RMU_RSTCAUSE

RMU_CMD

Type

RW R W1

Description

Control Register Reset Cause Register

Command Register

10.5 Register Description

10.5.1 RMU_CTRL - Control Register

Offset

0x000

Reset Access Bit Position Name Bit

31:2

1 0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BURSTEN 1 RW

Backup domain reset enable

This bit has to be cleared before accessing the registers in the BURTC.

LOCKUPRDIS 0 RW

Lockup Reset Disable

Set this bit to disable the LOCKUP signal (from the Cortex) from resetting the device.

10.5.2 RMU_RSTCAUSE - Reset Cause Register

Offset

0x004

Reset Access Bit Position Name Bit

31:16

15 14 13

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BUMODERST 0 R

Backup mode reset

Set if the system has been in Backup mode. Must be cleared by software. Please see Section 11.3.4 (p. 153) for details on how

to interpret this bit.

BUBODREG 0 R

Backup Brown Out Detector Regulated Domain

Set if the Backup BOD sensing on regulated power triggers. Must be cleared by software. Please see Section 11.3.4.2 (p. 154)

for details on how to interpret this bit.

BUBODUNREG 0 R

Backup Brown Out Detector Unregulated Domain

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7 6

Bit

12 11 10 9 8 5 4 3 2 1 0

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Name Reset Access Description

Set if the Backup BOD sensing on unregulated power triggers. Must be cleared by software. Please see Section 11.3.4.2 (p. 154)

for details on how to interpret this bit.

BUBODBUVIN 0 R

Backup Brown Out Detector, BU_VIN

Set if the Backup BOD sensing on BU_VIN triggers. Must be cleared by software. Please see Section 11.3.4.2 (p. 154) for details

on how to interpret this bit.

BUBODVDDDREG 0 R

Backup Brown Out Detector, VDD_DREG

Set if the Backup BOD sensing on VDDD_REG triggers. Must be cleared by software. Please see Section 11.3.4.2 (p. 154) for

details on how to interpret this bit.

BODAVDD1 0 R

AVDD1 Bod Reset

Set if analog power domain 1 brown out detector reset has been performed. Must be cleared by software. Please see Table 10.1 (p.

141) for details on how to interpret this bit.

BODAVDD0 0 R

AVDD0 Bod Reset

Set if analog power domain 0 brown out detector reset has been performed. Must be cleared by software. Please see Table 10.1 (p.

141) for details on how to interpret this bit.

EM4WURST 0 R

EM4 Wake-up Reset

Set if the system has been woken up from EM4 from a reset request from pin. Must be cleared by software. Please see Table 10.1 (p.

141) for details on how to interpret this bit.

EM4RST 0 R

EM4 Reset

Set if the system has been in EM4. Must be cleared by software. Please see Table 10.1 (p. 141) for details on how to interpret this bit.

SYSREQRST 0 R

System Request Reset

Set if a system request reset has been performed. Must be cleared by software. Please see Table 10.1 (p. 141) for details on how

to interpret this bit.

LOCKUPRST 0 R

LOCKUP Reset

Set if a LOCKUP reset has been requested. Must be cleared by software. Please see Table 10.1 (p. 141) for details on how to

interpret this bit.

WDOGRST 0 R

Watchdog Reset

Set if a watchdog reset has been performed. Must be cleared by software. Please see Table 10.1 (p. 141) for details on how to

interpret this bit.

EXTRST 0 R

External Pin Reset

Set if an external pin reset has been performed. Must be cleared by software. Please see Table 10.1 (p. 141) for details on how

to interpret this bit.

BODREGRST 0 R

Brown Out Detector Regulated Domain Reset

Set if a regulated domain brown out detector reset has been performed. Must be cleared by software. Please see Table 10.1 (p.

141) for details on how to interpret this bit.

BODUNREGRST 0 R

Brown Out Detector Unregulated Domain Reset

Set if a unregulated domain brown out detector reset has been performed. Must be cleared by software. Please see Table 10.1 (p.

141) for details on how to interpret this bit.

PORST 0 R

Power On Reset

Set if a power on reset has been performed. Must be cleared by software. Please see Table 10.1 (p. 141) for details on how to

interpret this bit.

10.5.3 RMU_CMD - Command Register

Offset

0x008

Reset Access Bit Position Name

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Bit

31:1

0

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Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RCCLR 0 W1

Reset Cause Clear

Set this bit to clear the LOCKUPRST and SYSREQRST bits in the RMU_RSTCAUSE register. Use the HRCCLR bit in the EMU_AUXCTRL register to clear the remaining bits.

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11 EMU - Energy Management Unit

0 1 2 3 4

Quick Facts What?

The EMU (Energy Management Unit) handles the different low energy modes in the EZR32WG microcontrollers.

Why?

The need for performance and peripheral functions varies over time in most applications. By efficiently scaling the available resources in real-time to match the demands of the application, the energy consumption can be kept at a minimum.

How?

With a broad selection of energy modes, a high number of low-energy peripherals available even in EM2, and short wake up time (2 µs from EM2 and EM3), applications can dynamically minimize energy consumption during program execution.

11.1 Introduction

The Energy Management Unit (EMU) manages all the low energy modes (EM) in EZR32WG microcontrollers. Each energy mode manages if the CPU and the various peripherals are available. The energy modes range from EM0 to EM4, where EM0, also called run mode, enables the CPU and all peripherals. The lowest recoverable energy mode, EM3, disables the CPU and most peripherals while maintaining wake-up and RAM functionality. EM4 disables everything except the POR, pin reset and optionally Backup RTC, 512 byte data retention, GPIO state retention, and EM4 reset wakeup request.

The various energy modes differ in: • Energy consumption • CPU activity • Reaction time • Wake-up triggers • Active peripherals • Available clock sources Low energy modes EM1 to EM4 are enabled through the application software. In EM1-EM3, a range of wake-up triggers return the microcontroller back to EM0. EM4 can only return to EM0 by power on reset, external pin reset, EM4 GPIO wakeup request, or Backup RTC interrupt.

11.2 Features

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11.3 Functional Description

The Energy Management Unit (EMU) is responsible for managing the wide range of energy modes

available in EZR32WG. An overview of the EMU module is shown in Figure 11.1 (p. 148) .

Figure 11.1. EMU Overview

Peripheral bus Cont rol and st at us regist ers Energy Managem ent St at e Machine Cort ex Volt age regulat or syst em Oscillat or syst em Reset syst em Mem ory syst em Int errupt cont roller The EMU is available as a peripheral on the peripheral bus. The energy management state machine is triggered from the Cortex-M4 and controls the internal voltage regulators, oscillators, memories and interrupt systems in the low energy modes. Events from the interrupt or reset systems can in turn cause the energy management state machine to return to its active state. This is further described in the following sections.

11.3.1 Energy Modes

There are five main energy modes available in EZR32WG, called Energy Mode 0 (EM0) through Energy Mode 4 (EM4). EM0, also called the active mode, is the energy mode in which any peripheral function can be enabled and the Cortex-M4 core is executing instructions. EM1 through EM4, also called low energy modes, provide a selection of reduced peripheral functionality that also lead to reduced energy consumption, as described below.

Figure 11.2 (p. 149) shows the transitions between different energy modes. After reset the EMU will

always start in EM0. A transition from EM0 to another energy mode is always initiated by software. EM0 is the highest activity mode, in which all functionality is available. EM0 is therefore also the mode with highest energy consumption.

The low energy modes EM1 through EM4 result in less functionality being available, and therefore also reduced energy consumption. The Cortex-M4 is not executing instructions in any low energy mode.

Each low energy mode provides different energy consumptions associated with it, for example because a different set of peripherals are enabled or because these peripherals are configured differently.

A transition from EM0 to a low energy mode can only be triggered by software.

A transition from EM1 – EM3 to EM0 can be triggered by an enabled interrupt or event. In addition, a chip reset will return the device to EM0. A transition from EM4 can be triggered by a pin reset, power on reset, EM4 GPIO wakeup, or Backup RTC interrupt.

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Figure 11.2. EMU Energy Mode Transitions ...the world's most energy friendly wireless MCUs

Act ive m ode

EM0 EM1

Low energy m odes

EM2 EM3 EM4

No direct transitions between EM1, EM2 or EM3 are available, as can also be seen from Figure 11.2 (p.

149) . Instead, a wakeup will transition back to EM0, in which software can enter any other low energy

mode. An overview of the supported energy modes and the functionality available in each mode is shown

in Table 11.1 (p. 150) . Most peripheral functionality indicated as "On" in a particular energy mode can

also be turned off from software in order to save further energy.

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...the world's most energy friendly wireless MCUs Table 11.1. EMU Energy Mode Overview

EM0

1 Wakeup time to EM0 MCU clock tree High frequency peripheral clock trees Core voltage regulator High frequency oscillator I 2 C full functionality Low frequency peripheral clock trees Low frequency oscillator Real Time Counter LEUART LETIMER LESENSE PCNT ACMP I 2 C receive address recognition Watchdog Pin interrupts RAM voltage regulator/RAM retention Brown Out Reset Power On Reset Pin Reset GPIO state retention EM4 Reset Wakeup Request Backup RTC Backup retention registers 1 Energy Mode 0/Active Mode 2 Energy Mode 1/2/3/4 3 When the 1 kHz ULFRCO is selected 4 Not available in Backup mode On On On On On On On On On On On On On On On On On On On On On On On The different Energy Modes are summarized in the following sections.

On On On On On On On On On On -

EM2

2 2 µs On On On On On On On On On On On On On On On On On On On On On -

EM1

2 On On On On On On On On On On On On On -

EM3

2 2 µs On 3 On 3 On 3 On On On On On On On On 3 On On On 4 On 4 On On -

EM4

2 160 µs -

11.3.1.1 EM0

• The high frequency oscillator is active • High frequency clock trees are active • All peripheral functionality is available

11.3.1.2 EM1

• The high frequency oscillator is active • MCU clock tree is inactive 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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• High frequency peripheral clock trees are active • All peripheral functionality is available

11.3.1.3 EM2

• The high frequency oscillator is inactive • The high frequency peripheral and MCU clock trees are inactive • The low frequency oscillator and clock trees are active • Low frequency peripheral functionality is available • Wakeup through peripheral interrupt or asynchronous pin interrupt • RAM and register values are preserved • DAC and OPAMPs are available

11.3.1.4 EM3

• Both high and low frequency oscillators and clock trees are inactive • Wakeup through asynchronous pin interrupts, I 2 C address recognition or ACMP edge interrupt • Watchdog and some low frequency peripherals available when ULFRCO (1 kHz clock) has been selected • BURTC is available.

• All other peripheral functionality is disabled • RAM and register values are preserved • DAC and OPAMPs are available

11.3.1.5 EM4

• All oscillators and regulators are inactive, if Backup RTC is not enabled.

• RAM and register values are not preserved, except for the ones located in the Backup RTC.

• Optional GPIO state retention • Wakeup from Backup RTC interrupt, external pin reset or pins that support EM4 wakeup

11.3.2 Entering a Low Energy Mode

A low energy mode is entered by first configuring the desired Energy Mode through the EMU_CTRL

register and the SLEEPDEEP bit in the Cortex-M4 System Control Register, see Table 11.2 (p. 152) .

A Wait For Interrupt (WFI) or Wait For Event (WFE) instruction from the Cortex-M4 triggers the transition into a low energy mode.

The transition into a low energy mode can optionally be delayed until the lowest priority Interrupt Service Routine (ISR) is exited, if the SLEEPONEXIT bit in the Cortex-M4 System Control Register is set.

Entering the lowest energy mode, EM4, is done by writing a sequence to the EM4CTRL bitfield in the EMU_CTRL register. Writing a zero to the EM4CTRL bitfield will restart the power sequence.

EM2BLOCK prevents the EMU to enter EM2 or lower, and it will instead enter EM1.

EM3 is equal to EM2, except that the LFACLK/LFBCLK are disabled in EM3. The LFACLK/LFBCLK must be disabled by the user before entering low energy mode.

The EMVREG bit in EMU_CTRL can be used to prevent the voltage regulator from being turned off in low energy modes. The device will then essentially stay in EM1 (with HF oscillators disabled) when entering a low energy mode. Note that if a DMA transfer is initiated in this mode, the HF-oscillators will start and remain enabled until the device is woken up from an EM2 interrupt.

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Table 11.2. EMU Entering a Low Energy Mode ...the world's most energy friendly wireless MCUs

Low Energy Mode

EM1 EM2 EM4

EM4CTRL EMVREG

0 0 Write sequence: 2, 3, 2, 3, 2, 3, 2, 3, 2 x 0 x

EM2BLOCK

x 0 x

SLEEPDEEP

0 1 x

Cortex-M4 Instruction

WFI or WFE WFI or WFE x (‘x’ means don’t care)

11.3.3 Leaving a Low Energy Mode

In each low energy mode a selection of peripheral units are available, and software can either enable or disable the functionality. Enabled interrupts that can cause wakeup from a low energy mode are shown

in Table 11.3 (p. 153) . The wakeup triggers always return the EZR32 to EM0. Additionally, any reset

source will return to EM0.

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...the world's most energy friendly wireless MCUs Table 11.3. EMU Wakeup Triggers from Low Energy Modes

Peripheral

RTC USART UART LEUART LESENSE I 2 C I 2 C TIMER LETIMER CMU DMA MSC DAC ADC AES PCNT ACMP

Wakeup Trigger

Any enabled interrupt Receive / transmit Receive / transmit Receive / transmit Any enabled interrupt Any enabled interrupt Receive address recognition Any enabled interrupt Any enabled interrupt Any enabled interrupt Any enabled interrupt Any enabled interrupt Any enabled interrupt Any enabled interrupt Any enabled interrupt Any enabled interrupt Any enabled edge interrupt VCMP Pin interrupts Any enabled edge interrupt Asynchronous Pin EM4 wakeup on supported pins Backup RTC Reset Asynchronous Any enabled interrupt Power Cycle Off/On 1 Energy Mode 0/Active Mode 2 Energy mode 1/2/3/4 3 When the 1 kHz ULFRCO is selected 4 When using an external clock -

EM0

1 Yes

EM1

2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes -

EM3

2 Yes 3 Yes 3 Yes Yes 3 Yes 4 -

EM2

2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes -

EM4

2 Yes Yes

11.3.4 Backup power domain

11.3.4.1 Introduction

The EZR32WG has the possibility to be partly powered by a backup battery. The backup power input, BU_VIN, is connected to a power domain in the EZR32WG containing the Backup RTC and 512 bytes

of data retention, available in all energy modes. Figure 11.3 (p. 154) shows an overview of the backup

powering scheme. During normal operation, the entire chip is powered by the main power supply. If the main power supply drains out and the Backup mode functionality is enabled, the system enters a low energy mode, equivalent to EM4, and automatically switches over to the backup power supply.

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Figure 11.3. Backup power domain overview ...the world's most energy friendly wireless MCUs

BUCTRL_STATEN BUCTRL_EN Main power BOD BU_STAT BUINACT_PWRCON / BUACT_PWRCON PWRCONF_PWRRES VDD_DREG Main power supply + Main power Main dom ain BUBODVDDDREG BUBODUNREG Backup regulat or BUBODREG SW reset reset BOD POR WDOG EXT RESETn Wake- up cont roller BURTC Wake- Up Main power OK EM4 pin Wake- Up Backup dom ain BURTC 512 byt e ret ent ion BUBODBUVIN Backup power BU_VIN + Backup power supply STRONG MEDIUM WEAK PWRCONF_VOUTx x x BU_VOUT When in backup mode, available functionality is the same as the functionality available in EM4. Refer

to Section 11.3.4.10 (p. 157) for further details.

11.3.4.2 Brown out detectors

The backup power domain functionality utilizes four brown-out detectors, BODs. One senses the main power supply, one senses the backup power supply, one senses the unregulated selected power supply (main or backup, depending on mode), and one BOD senses the regulated power supply. The bits BUBODVDDDREG ,BUBODBUVIN, BUBODUNREG, and BUBODREG in the RSTCAUSE register in the RMU are set when the associated BOD triggers. The locations of the Backup BODs are indicated in

Figure 11.3 (p. 154) . A brown out on the main power supply will trigger a switch to the backup power

supply if the backup functionality is enabled and the BOD sensing on the backup power supply has not triggered. The two other BODs are used for error indication and will only set the bits in RMU_RSTCAUSE if they are triggered.

11.3.4.3 Entering backup mode

To be able to enter backup mode, the EN bit in EMU_BUCTRL has to be set. The BURDY interrupt flag will be set as soon as the backup sensing module is operational. Status of the backup functionality is also available in the BURDY flag in the EMU_STATUS register. The BU_VIN pin also needs to be enabled. This is done by setting the BUVINPEN bit in EMU_ROUTE. To enter backup mode, the voltage on VDD_DREG has to drop below the programmable threshold of the BOD sensing on this power. This threshold is programmed using BUENRANGE and BUENTHRES in EMU_BUINACT. BUENRANGE decides the voltage range for the BOD, while BUENTHRES is used for tuning of the BOD threshold.

Refer to Section 11.3.4.5 (p. 155) for details regarding BOD calibration.

Note

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BUVINPEN in EMU_ROUTE is by default set. If Backup mode is not to be used, this bit should be cleared.

Note

The voltage on BU_VIN has to be above the threshold for the BOD sensing on BU_VIN to enter backup mode.

The BU_STAT pin can be used to indicate whether or not the system is in backup mode. To enable exporting of the backup mode status, set STATEN in EMU_BUCTRL and enable the GPIO clock. The BU_STAT pin is driven to BU_VIN when backup mode is active and to ground otherwise.

11.3.4.4 Leaving backup mode

To exit backup mode, the voltage on VDD_DREG has to be above the threshold programmed in EMU_BUACT. BUEXRANGE decides the voltage range for backup mode exit, while BUEXTHRES is used for tuning. When leaving backup mode, a system reset is triggered, resetting everything except the backup domain. When backup mode has been active, the BURST bit in RMU_RSTCAUSE is set.

Figure 11.4. Entering and leaving backup mode

EMU_BUACT_BUEXRANGE / EMU_BUACT_BUEXTHRES EMU_BUINACT_BUENRANGE / EMU_BUINACT_BUENTHRES VDDREG Backup m ode act ive Tim e

Figure 11.4 (p. 155) illustrates how the BOD sensing on VDD_DREG can be programmed to

implement hysteresis on entering and exiting backup mode.

11.3.4.5 Threshold calibration

The thresholds for entering and exiting backup mode are configured in the EMU_BUINACT and EMU_BUACT registers, respectively. Calibration of these thresholds is performed during production test, but may also be performed using the DAC. The calibration values for the BODs sensing on unregulated power and BU_VIN, BUBODUNREG and BUBODBUVIN respectively, are available in EMU_BUBODVINCAL and EMU_BUBODUNREGCAL. These registers are written during production test and should not be modified except for calibrating the Backup BOD sensing on VDD_DREG, as described in the following section.

Setting BODCAL in EMU_BUCTRL will enable a mode where the BOD is sensing the DAC output, as

depicted in Figure 11.5 (p. 156) . For the BODCAL bit to take effect, the backup power enable bit, EN

in EMU_BUCTRL, has to be cleared. The procedure for BOD calibration is as follows: • Clear EN and set BODCAL in EMU_BUCTRL.

• Store the values in EMU_BUBODVINCAL and EMU_BUBODUNREGCAL before clearing these registers.

• Configure the DAC to output to the maximum level and wait for 500 us before configuring the DAC output to the wanted BOD trigger voltage level.

• Step through the BOD calibration values (RANGE and THRES in EMU_BUINACT) with 500 us delay in between steps until the BUBODVDDDREG flag in RMU_RSTCAUSE is set. The RANGE and THRES 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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values in EMU_BUINACT can now be written to EMU_BUINACT for configuration of threshold for entering backup mode, or EMU_BUACT for configuration of the threshold for leaving backup mode.

• Restore the values in EMU_BUBODVINCAL and EMU_BUBODUNREGCAL.

Figure 11.5. BOD calibration using DAC

BOD t rigger + 1.8V

BUCTRL_BODCAL 0 1 VDD_DREG DAC alt ernat ive out put EMU_BUINACT_BUENRANGE / EMU_BUINACT_BUENTHRES

11.3.4.6 Backup battery charging

The EZR32WG includes functionality for charging of the backup battery. This is done by connecting the main power and the backup power through a resistor, and optionally a diode. The connection is configured individually for when in backup mode and when in normal mode. When in normal mode, the connection is configured in PWRCON in EMU_BUINACT. PWRCON in EMU_BUACT configures the connection when in backup mode. The series resistance between the two power domains is configured in PWRRES in EMU_PWRCONF, this configuration applies both to backup mode and normal mode.

11.3.4.7 Supply voltage output

To be able to power external devices, the supply voltage for the backup domain is available as an output.

Three switches connect the backup supply voltage to the BU_VOUT pin. To be able to control the series resistance, the switches have different strengths: weak, medium, and strong. The switches are controlled using the VOUTWEAK, VOUTMED, and VOUTSTRONG bits in EMU_PWRCONF. For resistor values, refer to Device Datasheet Electrical Characteristics.

11.3.4.8 Voltage probing

It is possible to probe the voltage levels at VDD_DREG, BU_VIN, and BU_VOUT. This is done by configuring the ADC to measure a tristated channel, for instance a disabled DAC channel. The PROBE bitfield in EMU_BUCTRL configures which voltage to be probed. The voltage measured by the ADC will be 1/8 of the actual probed voltage, meaning that the result needs to be multiplied by 8 for the correct result. Voltage probing does not work when BODCAL in the EMU_BUCTRL register is set.

11.3.4.9 Configuration lock

Configurations used in Backup mode and EM4, like BOD calibration, and Backup RTC settings need to be locked before entering EM4, this is done by setting the LOCKCONF bit in EMU_EM4CONF. This bit should also be set before a potential entry to backup mode. Setting this bit will lock following the configuration: • LFXOMODE, LFXOBUFCUR, and LFXOBOOST in CMU_CTRL • TUNING in CMU_LFRCOCTRL • BURSTEN in RMU_CTRL • BURTCWU and VREGEN in EMU_EM4CONF • EMU_BUCTRL • EMU_PWRCONF • EMU_BUINACT • EMU_BUACT 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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• EMU_ROUTE

Note

For registers residing in the CMU and EMU_AUXCTRL, the reset value will be read after exit from EM4 or Backup mode, but if LOCKCONF in EMU_EM4CONF has been set, the locked configuration will be used until LOCKCONF is cleared. This also applies for the LOCKCONF bit itself.

The LOCKCONF bit does not lock the PROBE bitfield in EMU_BUCTRL.

11.3.4.10 EM4 with RTC and data retention

The backup power domain can also be powered by the main power. This provides possibility for Backup RTC operation and data retention in EM4. Available functionality in EM4 is configured in EMU_EM4CONF. Setting the VREGEN bit will keep the voltage regulator for the Backup domain enabled when in EM4. This allows the Backup RTC to keep running. To enable the Backup RTC to wake up the system from EM4, BURTCWU in EMU_EM4CONF needs to be set. When BURTCWU is set, any enabled Backup RTC interrupt will wake up the system. For further details regarding the Backup RTC

and EM4 data retention, refer to Chapter 22 (p. 542) .

The voltage regulator can also be used to power the Backup RTC during a watchdog reset from any energy mode. Set EMU_EM4CONF_VREGEN to enable the Backup RTC to be powered from the regulator, making sure it survives a watchdog reset.

11.3.4.10.1 Oscillators in EM4

When the system is in EM4 or backup mode with the voltage regulator enabled, the ULFRCO is by default enabled. If the LFXO or LFRCO is used by the Backup RTC, the ULFRCO can be shut down to reduce power consumption. To do this, configure the OSC bitfield in EMU_EM4CONF.

Note

If OSC in EMU_EM4CONF is not set to ULFRCO, PRESC and LPCOMP in BURTC_CTRL has to be configured in the following manner: • 4 < (PRESC + LPCOMP) < 8, PRESC = 0,5,6,7

Refer to Chapter 22 (p. 542) for details on how to configure the Backup RTC.

11.3.4.10.2 Brown-out detector in EM4

To enable Brown-out detection in EM4, the Backup BODs have to be enabled, by setting EN in EMU_BUCTRL. When BURDY in EMU_STATUS is set, the Brown-out detectors are ready and able to issue a reset from EM4 if a Brown-out is detected on either regulated or unregulated power. The Backup BOD' ability to issue reset from EM4 can be disabled by setting BUBODRSTDIS in EMU_EM4CONF.

Note

The Backup BODs can be enabled without allowing entrance to backup mode. This is done by setting EN in EMU_BUCTRL, and clearing BUVINPEN in EMU_ROUTE.

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11.4 Register Map

The offset register address is relative to the registers base address.

Offset

0x000

0x008 0x024

0x02C 0x030

0x034 0x038

0x03C

0x040 0x044 0x048

0x04C 0x050 0x054

0x058 0x05C

Name

EMU_CTRL

EMU_LOCK EMU_AUXCTRL

EMU_EM4CONF EMU_BUCTRL

EMU_PWRCONF EMU_BUINACT

EMU_BUACT

EMU_STATUS EMU_ROUTE EMU_IF

EMU_IFS EMU_IFC EMU_IEN

EMU_BUBODBUVINCAL EMU_BUBODUNREGCAL

Type

R W1 W1 RW RW RW RW RW RW RW RW RW RW RW R RW

Description

Control Register

Configuration Lock Register Auxiliary Control Register

Energy mode 4 configuration register Backup Power configuration register

Power connection configuration register Backup mode inactive configuration register

Backup mode active configuration register

Status register I/O Routing Register Interrupt Flag Register

Interrupt Flag Set Register Interrupt Flag Clear Register Interrupt Enable Register

BU_VIN Backup BOD calibration Unregulated power Backup BOD calibration

11.5 Register Description

11.5.1 EMU_CTRL - Control Register

Offset

0x000

Reset Access Bit Position Name

1 0

Bit

31:4

3:2

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

EM4CTRL 0x0 RW

Energy Mode 4 Control

This register is used to enter Energy Mode 4, in which the device only wakes up from an external pin reset, from a power cycle, Backup RTC interrupt, or EM4 wakeup reset request. Energy Mode 4 is entered when the EM4 sequence is written to this bitfield.

EM2BLOCK 0 RW

Energy Mode 2 Block

This bit is used to prevent the MCU to enter Energy Mode 2 or lower.

EMVREG 0 RW Control the voltage regulator in low energy modes 2 and 3.

Energy Mode Voltage Regulator Control

Value 0 1 Mode REDUCED FULL Description Reduced voltage regulator drive strength in EM2 and EM3.

Full voltage regulator drive strength in EM2 and EM3.

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11.5.2 EMU_LOCK - Configuration Lock Register

Offset

0x008

Bit Position Reset Access Name Bit

31:16

15:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LOCKKEY 0x0000 RW

Configuration Lock Key

Write any other value than the unlock code to lock all EMU registers, except the interrupt registers, from editing. Write the unlock code to unlock. When reading the register, bit 0 is set when the lock is enabled.

Mode Read Operation UNLOCKED LOCKED Write Operation LOCK UNLOCK Value 0 1 0 0xADE8 Description EMU registers are unlocked.

EMU registers are locked.

Lock EMU registers.

Unlock EMU registers.

11.5.3 EMU_AUXCTRL - Auxiliary Control Register

Bit Position Offset

0x024

Reset Access Name Bit

31:1

0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

HRCCLR 0 RW

Hard Reset Cause Clear

Write to 1 and then 0 to clear the POR, BOD and WDOG reset cause register bits. See also the Reset Management Unit (RMU).

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11.5.4 EMU_EM4CONF - Energy mode 4 configuration register

Offset

0x02C

Reset Access Bit Position Name

1 0

Bit

31:17

16

15:5

4 3:2

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LOCKCONF 0 RW

EM4 configuration lock enable

Lock regulator, BOD and oscillator configuration. This is necessary before going to EM4 if the regulator is to be used in EM4, and must also be done before a potential entry to backup mode.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BUBODRSTDIS 0 RW

Disable reset from Backup BOD in EM4

When set, no reset will be asserted due to Brownout when in EM4.

OSC 0x0 RW

Select EM4 duty oscillator

Value 0 1 2 Mode ULFRCO LFRCO LFXO Description ULFRCO is available.

LFRCO is available. Can only be set if LFRCO is running before EM4/backup entry.

LFXO is available. Can only be set if LFXO is available before EM4/backup entry.

BURTCWU 0 Exit EM4 on Backup RTC interrupt.

RW

Backup RTC EM4 wakeup enable

VREGEN 0 RW

EM4 voltage regulator enable

When set, the voltage regulator is enabled in EM4, enabling operation of the Backup RTC and retention registers.

11.5.5 EMU_BUCTRL - Backup Power configuration register

Offset

0x030

Reset Access Bit Position Name Bit

31:7

6:5

Name Reset Access Description

Reserved

PROBE

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 Configure which voltage to export to ADC.

RW

Voltage probe select

Value 0 1 2 Mode DISABLE VDDDREG BUIN Description Disable voltage probe.

Connect probe to VDD_DREG.

Connect probe to BU_IN.

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1 0

4:3

2

Bit

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Name

Value 3 Mode BUOUT

Reset Access Description

Description Connect probe to BU_OUT.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BODCAL 0 RW

Enable BOD calibration mode

When set, the Backup BOD sensing on VDD_DREG will be sensing the DAC output.

STATEN 0 RW

Enable backup mode status export

When enabled, BU_STAT will indicate when backup mode is active.

EN 0 RW

Enable backup mode

Backup mode will be entered when main power browns out and backup battery is present.

11.5.6 EMU_PWRCONF - Power connection configuration register

Offset

0x034

Reset Access Bit Position Name

2 1 0

Bit

31:5

4:3

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PWRRES 0x0 RW

Power domain resistor select

Select value of series resistor between main power domain and backup power domain.

Value 0 1 2 3 Mode RES0 RES1 RES2 RES3 Description Main power and backup power connected with RES0 series resistance.

Main power and backup power connected with RES1 series resistance.

Main power and backup power connected with RES2 series resistance.

Main power and backup power connected with RES3 series resistance.

VOUTSTRONG 0 RW

BU_VOUT strong enable

Enable strong switch between backup domain power supply and BU_VOUT.

VOUTMED 0 RW

BU_VOUT medium enable

Enable medium switch between backup domain power supply and BU_VOUT.

VOUTWEAK 0 RW

BU_VOUT weak enable

Enable weak switch between backup domain power supply and BU_VOUT.

11.5.7 EMU_BUINACT - Backup mode inactive configuration register

Offset

0x038

Reset Access Bit Position Name

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Bit

31:7

6:5 4:3 2:0

Name

Reserved

PWRCON

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Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 RW

Power connection configuration when not in Backup mode

Value 0 1 2 3 Mode NONE BUMAIN MAINBU NODIODE Description No connection.

Main power and backup power are connected through a diode, allowing current to flow from backup power source to main power source, but not the other way.

Main power and backup power are connected through a diode, allowing current to flow from main power source to backup power source, but not the other way.

Main power and backup power are connected without diode.

BUENRANGE 0x1 RW Threshold range for Backup BOD sensing on VDD_DREG when not in backup mode. This field is set to the threshold range calibrated during production, hence the reset value might differ from device to device.

BUENTHRES 0x3 RW Threshold for Backup BOD sensing on VDD_DREG when not in backup mode. This field is set to the threshold value calibrated during production, hence the reset value might differ from device to device.

11.5.8 EMU_BUACT - Backup mode active configuration register

Bit Position Offset

0x03C

Reset Access Name Bit

31:7

6:5 4:3 2:0

Name

Reserved

PWRCON

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 RW

Power connection configuration when in Backup mode

Value 0 1 2 3 Mode NONE BUMAIN MAINBU NODIODE Description No connection.

Main power and backup power are connected through a diode, allowing current to flow from backup power source to main power source, but not the other way.

Main power and backup power are connected through a diode, allowing current to flow from main power source to backup power source, but not the other way.

Main power and backup power are connected without diode.

BUEXRANGE 0x1 RW Threshold range for Backup BOD sensing on VDD_DREG when in backup mode. This field is set to the threshold range calibrated during production, hence the reset value might differ from device to device.

BUEXTHRES 0x3 RW Threshold for Backup BOD sensing on VDD_DREG when in backup mode. This field is set to the threshold value calibrated during production, hence the reset value might differ from device to device.

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11.5.9 EMU_STATUS - Status register

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Offset

0x040

Reset Access Bit Position Name Bit

31:1

0

Name Reset Access Description

Reserved

BURDY

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 R Set when the Backup power functionality is ready.

Backup mode ready

11.5.10 EMU_ROUTE - I/O Routing Register

Offset

0x044

Reset Access Bit Position Name Bit

31:1

0

Name

Reserved

BUVINPEN

Reset

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

1 When set, the BU_VIN pin is enabled.

Access

RW

Description BU_VIN Pin Enable

11.5.11 EMU_IF - Interrupt Flag Register

Offset

0x048

Reset Access Bit Position Name Bit

31:1

0

Name

Reserved

BURDY

Reset

0

Access

R Set when the Backup functionality is ready for use.

Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

Backup functionality ready Interrupt Flag

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11.5.12 EMU_IFS - Interrupt Flag Set Register

Offset

0x04C

Reset Access Bit Position Name Bit

31:1

0

Name Reset Access Description

Reserved

BURDY

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Write to 1 to set the BURDY interrupt flag.

W1

Set Backup functionality ready Interrupt Flag

11.5.13 EMU_IFC - Interrupt Flag Clear Register

Offset

0x050

Reset Access Bit Position Name Bit

31:1

0

Name Reset Access Description

Reserved

BURDY

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Write to 1 to clear the BURDY interrupt flag.

W1

Clear Backup functionality ready Interrupt Flag

11.5.14 EMU_IEN - Interrupt Enable Register

Offset

0x054

Reset Access Bit Position Name Bit

31:1

0

Name Reset Access Description

Reserved

BURDY

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 RW Enable interrupt when Backup functionality is ready.

Backup functionality ready Interrupt Enable

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11.5.15 EMU_BUBODBUVINCAL - BU_VIN Backup BOD calibration

Offset

0x058

Reset Access Bit Position Name Bit

31:5

4:3 2:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RANGE 0x1 RW Threshold range for Backup BOD sensing on BU_VIN. This field is set to the threshold range calibrated during production, hence the reset value might differ from device to device.

THRES 0x3 RW Threshold for Backup BOD sensing on BU_VIN. This field is set to the threshold value calibrated during production, hence the reset value might differ from device to device.

11.5.16 EMU_BUBODUNREGCAL - Unregulated power Backup BOD calibration

Bit Position Offset

0x05C

Reset Access Name Bit

31:5

4:3 2:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RANGE 0x1 RW Threshold range for Backup BOD sensing on unregulated power. This field is set to the threshold range calibrated during production, hence the reset value might differ from device to device.

THRES 0x3 RW Threshold for Backup BOD sensing on unregulated power. This field is set to the threshold value calibrated during production, hence the reset value might differ from device to device.

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12 CMU - Clock Management Unit

0 1 2 3 4

Oscillat ors CMU WDOG clock LETIMER clock Peripheral A clock Peripheral B clock Peripheral C clock Peripheral D clock CPU clock

Quick Facts What?

The CMU controls oscillators and clocks.

EZR32WG supports five different oscillators with minimized power consumption and short start-up time. An additional separate RC oscillator is used for flash programming and debug trace. The CMU also has HW support for calibration of RC oscillators.

Why?

Oscillators and clocks contribute significantly to the power consumption of the MCU. With the low power oscillators combined with the flexible clock control scheme, it is possible to minimize the energy consumption in any given application.

How?

The CMU can configure different clock sources, enable/disable clocks to peripherals on an individual basis and set the prescaler for the different clocks. The short oscillator start-up times makes duty-cycling between active mode and the different low energy modes (EM2-EM4) very efficient. The calibration feature ensures high accuracy RC oscillators. Several interrupts are available to avoid CPU polling of flags.

12.1 Introduction

The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EZR32WG. The CMU provides the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not wasting power on peripherals and oscillators that are inactive.

12.2 Features

• Multiple clock sources available: • 1-28 MHz High Frequency RC Oscillator (HFRCO) • 4-48 MHz MHz High Frequency Crystal Oscillator (HFXO) • 32768 Hz Low Frequency RC Oscillator (LFRCO) • 32768 Hz Low Frequency Crystal Oscillator (LFXO) • 1000 Hz Ultra Low Frequency RC Oscillator (ULFRCO) • • Low power oscillators • Low start-up times • Separate prescaler for High Frequency Core Clocks (HFCORECLK) and Peripheral Clocks (HFPERCLK) 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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• Individual clock prescaler selection for each Low Energy Peripheral • Clock Gating on an individual basis to core modules and all peripherals • Selectable clocks can be output on two pins for use externally.

• Auxiliary 1-28 MHz RC oscillator (AUXHFRCO) for flash programming, and debug trace, and LESENSE timing.

12.3 Functional Description

An overview of the CMU is shown in Figure 12.1 (p. 168) . The number of peripheral modules that are

connected to the different clocks varies from device to device.

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...the world's most energy friendly wireless MCUs Figure 12.1. CMU Overview

AUXHFRCO HFXO HFRCO LFXO LFRCO LESENSE (High frequency t im ing) MSC (Flash Program m ing) Tim eout AUXCLK Tim eout Tim eout Tim eout Tim eout Debug Trace CMU_CTRL_DBGCLK clock swit ch CMU_HFPERCLKEN0.TIMER0

Clock Gat e HFPERCLK TIMER0 CMU_HFPERCLKDIV.HFPERCLKEN

prescaler HFPERCLK CMU_HFPERCLKEN0.I2C0

CMU_HFPERCLKDIV.HFPERCLKDIV

clock swit ch CMU_CTRL.HFCLKDIV

HFCLK DIV HFCLK EM0 CMU_CMD.HFCLKSEL

CMU_HFCORECLKDIV prescaler HFCORECLK CMU_CMD.USBCCLKSEL

CMU_HFCORECLKEN0.USBC

clock swit ch HFCORECLK USBC / 2 or / 4 CMU_HFCORECLKEN0.DMA

CMU_HFCORECLKEN0.LE

clock swit ch LFACLK CMU_LFCLKSEL.LFA / LFAE CMU_HFPERCLKEN0.TIMER1

CMU_LFACLKEN0.LESENSE

prescaler CMU_LFAPRESC0.LESENSE

CMU_LFACLKEN0.RTC

prescaler CMU_LFAPRESC0.RTC

CMU_LFACLKEN0.LETIMER0

prescaler CMU_LFAPRESC0.LETIMER0

CMU_LFACLKEN0.LCD

prescaler LFACLK LCDpre Fram e Rat e Cont rol CMU_LCDCTRL.FDIV

CMU_LFAPRESC0.LCD

Clock Gat e .

.

.

Clock Gat e Clock Gat e HFCORECLK CM4 Clock Gat e .

.

.

Clock Gat e Clock Gat e Clock Gat e Clock Gat e Clock Gat e HFPERCLK TIMER1 .

.

.

HFPERCLK I2C0 HFCORECLK DMA .

.

.

HFCORECLK LE LFACLK LFACLK LFACLK LFACLK LESENSE RTC LETIMER0 LCD PCNTn_S0 PCNTnCLK CMU_PCNTCTRL.PCNTnCLKSEL

CMU_LFCLKSEL.LFB / LFBE clock swit ch LFBCLK CMU_LFBPRESC0.LEUART0

prescaler CMU_LFBCLKEN0.LEUART0

CMU_LFBCLKEN0.LEUART1

Clock Gat e LFBCLK LEUART0 Clock Gat e LFBCLK LEUART1 prescaler CMU_LFBPRESC0.LEUART1

ULFRCO WDOGCLK WDOG_CTRL.CLKSEL

WDOG BURTC

12.3.1 System Clocks

12.3.1.1 HFCLK - High Frequency Clock

HFCLK is the selected High Frequency Clock. This clock is used by the CMU and drives the two prescalers that generate HFCORECLK and HFPERCLK. The HFCLK can be driven by a high-frequency oscillator (HFRCO or HFXO) or one of the low-frequency oscillators (LFRCO or LFXO). By default the HFRCO is selected. In most applications, one of the high frequency oscillators will be the preferred 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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choice. To change the selected HFCLK write to HFCLKSEL in CMU_CMD. The HFCLK is running in EM0 and EM1.

HFCLK can optionally be divided down by setting HFCLKDIV in CMU_CTRL to a nonzero value. This divides down HFCLK to all high frequency components except the USB Core and is typically used to save energy in USB applications where the system is not required to run at 48 MHz. Combined with the HFCORECLK and HFPERCLK prescalers the HFCLK divider also allows for more flexible clock division.

12.3.1.2 HFCORECLK - High Frequency Core Clock

HFCORECLK is a prescaled version of HFCLK. This clock drives the Core Modules, which consists of the CPU and modules that are tightly coupled to the CPU, e.g. MSC, DMA etc. This also includes the interface to the Low Energy Peripherals. Some of the modules that are driven by this clock can be clock gated completely when not in use. This is done by clearing the clock enable bit for the specific module in CMU_HFCORECLKEN0. The frequency of HFCORECLK is set using the CMU_HFCORECLKDIV register. The setting can be changed dynamically and the new setting takes effect immediately.

The USB Core runs on HFCORECLK USBC . Selectable clock sources are LFXO, LFRCO , HFCLK . If HFCLK is selected, it will always be undivided, regardless of the HFCLKDIV setting. When the USB Core is active this clock must be switched to a 32 kHz clock (LFRCO or LFXO) when entering EM2.

The USB Core uses this clock for monitoring the USB bus. The switch is done by writing USBCCLKSEL in CMU_CMD. The currently active clock can be checked by reading CMU_STATUS. The clock switch can take up to 1.5 32 kHz cycle (45 us). To avoid polling the clock selection status when switching from 32 kHz to HFCLK when coming up from EM2 the USBCHFCLKSEL interrupt can be used. EM3 is not supported when the USB is active.

Note

Note that if HFPERCLK runs faster than HFCORECLK, the number of clock cycles for each bus-access to peripheral modules will increase with the ratio between the clocks. Please

refer to Section 6.2.3.2 (p. 60) for more details.

12.3.1.3 HFPERCLK - High Frequency Peripheral Clock

Like HFCORECLK, HFPERCLK can also be a prescaled version of HFCLK. This clock drives the High-Frequency Peripherals. All the peripherals that are driven by this clock can be clock gated completely when not in use. This is done by clearing the clock enable bit for the specific peripheral in CMU_HFPERCLKEN0. The frequency of HFPERCLK is set using the CMU_HFPERCLKDIV register.

The setting can be changed dynamically and the new setting takes effect immediately.

Note

Note that if HFPERCLK runs faster than HFCORECLK, the number of clock cycles for each bus-access to peripheral modules will increase with the ratio between the clocks. E.g. if a bus-access normally takes three cycles, it will take 9 cycles if HFPERCLK runs three times as fast as the HFCORECLK.

12.3.1.4 LFACLK - Low Frequency A Clock

LFACLK is the selected clock for the Low Energy A Peripherals. There are four selectable sources for LFACLK: LFRCO, LFXO, HFCORECLK/2 and ULFRCO. In addition, the LFACLK can be disabled. From reset, the LFACLK source is set to LFRCO. However, note that the LFRCO is disabled from reset. The selection is configured using the LFA field in CMU_LFCLKSEL. The HFCORECLK/2 setting allows the Low Energy A Peripherals to be used as high-frequency peripherals.

Note

If HFCORECLK/2 is selected as LFACLK, the clock will stop in EM2/3.

Each Low Energy Peripheral that is clocked by LFACLK has its own prescaler setting and enable bit. The prescaler settings are configured using CMU_LFAPRESC0 and the clock enable bits can be found in CMU_LFACLKEN0. When operating in oversampling mode, the pulse counters are clocked by LFACLK.

This is configured for each pulse counter (n) individually by setting PCNTnCLKSEL in CMU_PCNTCTRL.

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12.3.1.5 LFBCLK - Low Frequency B Clock

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LFBCLK is the selected clock for the Low Energy B Peripherals. There are four selectable sources for LFBCLK: LFRCO, LFXO, HFCORECLK/2 and ULFRCO. In addition, the LFBCLK can be disabled. From reset, the LFBCLK source is set to LFRCO. However, note that the LFRCO is disabled from reset. The selection is configured using the LFB field in CMU_LFCLKSEL. The HFCORECLK/2 setting allows the Low Energy B Peripherals to be used as high-frequency peripherals.

Note

If HFCORECLK/2 is selected as LFBCLK, the clock will stop in EM2/3.

Each Low Energy Peripheral that is clocked by LFBCLK has its own prescaler setting and enable bit.

The prescaler settings are configured using CMU_LFBPRESC0 and the clock enable bits can be found in CMU_LFBCLKEN0.

12.3.1.6 PCNTnCLK - Pulse Counter n Clock

Each available pulse counter is driven by its own clock, PCNTnCLK where n is the pulse counter instance number. Each pulse counter can be configured to use an external pin (PCNTn_S0) or LFACLK as PCNTnCLK.

12.3.1.7 WDOGCLK - Watchdog Timer Clock

The Watchdog Timer (WDOG) can be configured to use one of three different clock sources: LFRCO, LFXO or ULFRCO. ULFRCO (Ultra Low Frequency RC Oscillator) is a separate 1 kHz RC oscillator that also runs in EM3.

12.3.1.8 AUXCLK - Auxiliary Clock

AUXCLK is a 1-28 MHz clock driven by a separate RC oscillator, AUXHFRCO. This clock is used for flash programming , and Serial Wire Output (SWO) , and LESENSE operation. During flash programming , or if needed by LESENSE, this clock will be active. If the AUXHFRCO has not been enabled explicitly by software, the MSC or LESENSE module will automatically start and stop it. The AUXHFRCO is enabled by writing a 1 to AUXHFRCOEN in CMU_OSCENCMD. This explicit enabling is required when SWO is used.

12.3.2 Oscillator Selection

12.3.2.1 Start-up Time

The different oscillators have different start-up times. For the RC oscillators, the start-up time is fixed, but both the LFXO and the HFXO have configurable start-up time. At the end of the start-up time a ready flag is set to indicated that the start-up time has exceeded and that the clock is available. The low start up time values can be used for an external clock source of already high quality, while the higher start-up times should be used when the clock signal is coming directly from a crystal. The startup time for HFXO and LFXO can be set by configuring the HFXOTIMEOUT and LFXOTIMEOUT bitfields, respectively.

Both bitfields are located in CMU_CTRL. For HFXO it is also possible to enable a glitch detection filter by setting HFXOGLITCHDETEN in CMU_CTRL. The glitch detector will reset the start-up counter if a glitch is detected, making the start-up process start over again.

There are individual bits for each oscillator indicating the status of the oscillator: • ENABLED - Indicates that the oscillator is enabled • READY - Start-up time is exceeded • SELECTED - Start-up time is exceeded and oscillator is chosen as clock source These status bits are located in the CMU_STATUS register.

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12.3.2.2 Switching Clock Source

The HFRCO oscillator is a low energy oscillator with extremely short wake-up time. Therefore, this oscillator is always chosen by hardware as the clock source for HFCLK when the device starts up (e.g.

after reset and after waking up from EM2 and EM3). After reset, the HFRCO frequency is 14 MHz.

Software can switch between the different clock sources at run-time. E.g., when the HFRCO is the clock source, software can switch to HFXO by writing the field HFCLKSEL in the CMU_CMD command

register. See Figure 12.2 (p. 171) for a description of the sequence of events for this specific operation.

Note

It is important first to enable the HFXO since switching to a disabled oscillator will effectively stop HFCLK and only a reset can recover the system.

During the start-up period HFCLK will stop since the oscillator driving it is not ready. This effectively stalls the Core Modules and the High-Frequency Peripherals. It is possible to avoid this by first enabling the HFXO and then wait for the oscillator to become ready before switching the clock source. This way, the system continues to run on the HFRCO until the HFXO has timed out and provides a reliable clock.

This sequence of events is shown in Figure 12.3 (p. 172) .

A separate flag is set when the oscillator is ready. This flag can also be configured to generate an interrupt.

Figure 12.2. CMU Switching from HFRCO to HFXO before HFXO is ready

CMU_CMD.HFCLKSEL

CMU_OSCENCMD.HFRCOEN

CMU_OSCENCMD.HFRCODIS

CMU_OSCENCMD.HFXOEN

CMU_OSCENCMD.HFXODIS

CMU_STATUS.HFRCORDY

CMU_STATUS.HFRCOENS

CMU_STATUS.HFRCOSEL

CMU_STATUS..HFXORDY

CMU_STATUS.HFXOENS

CMU_STATUS.HFXOSEL

HFCLK HFRCO HFXO 00 02 00 HFXO t im e- out period 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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...the world's most energy friendly wireless MCUs Figure 12.3. CMU Switching from HFRCO to HFXO after HFXO is ready

00 02 00 CMU_CMD.HFCLKSEL

CMU_OSCENCMD.HFRCOEN

CMU_OSCENCMD.HFRCODIS

CMU_OSCENCMD.HFXOEN

CMU_OSCENCMD.HFXODIS

CMU_STATUS.HFRCORDY

CMU_STATUS.HFRCOENS

CMU_STATUS.HFRCOSEL

CMU_STATUS.HFXORDY

CMU_STATUS.HFXOENS

CMU_STATUS.HFXOSEL

HFCLK HFRCO HFXO HFXO t im e- out period Switching clock source for LFACLK and LFBCLK is done by setting the LFA and LFB fields in CMU_LFCLKSEL. To ensure no stalls in the Low Energy Peripherals, the clock source should be ready before switching to it.

Note

To save energy, remember to turn off all oscillators not in use.

12.3.3 Oscillator Configuration

12.3.3.1 HFXO and LFXO

The crystal oscillators are by default configured to ensure safe startup and operation of the most common crystals. In order to optimize startup margin, startup time and power consumption for a given crystal, it is possible to adjust the gain in the oscillator. HFXO gain can be increased by setting HFXOBOOST field in CMU_CTRL, LFXO gain can be increased by setting LFXOBOOST field in CMU_CTRL. It is important that the boost settings, along with the crystal load capacitors are matched to the crystals in use. Correct values for these parameters can be found using the energyAware Designer.

The HFXO crystal is connected to the HFXTAL_N/HFXTAL_P pins as shown in Figure 12.4 (p. 172)

Figure 12.4. HFXO Pin Connection

Similarly, the LFXO crystal is connected to the LFXTAL_N/LFXTAL_P pins as shown in Figure 12.5 (p.

173)

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...the world's most energy friendly wireless MCUs Figure 12.5. LFXO Pin Connection

C L1 32.768kHz

C L2 LFXTAL_N LFXTAL_P EZR32 It is possible to connect an external clock source to HFXTAL_N/LFXTAL_N pin of the HFXO or LFXO oscillator. By configuring the HFXOMODE/LFXOMODE fields in CMU_CTRL, the HFXO/LFXO can be bypassed.

12.3.3.2 HFRCO, LFRCO and AUXHFRCO

It is possible to calibrate the HFRCO, LFRCO and AUXHFRCO to achieve higher accuracy (see the device datasheets for details on accuracy). The frequency is adjusted by changing the TUNING fields in CMU_HFRCOCTRL/CMU_LFRCOCTRL/CMU_AUXHFRCOCTRL. Changing to a higher value will result in a higher frequency. Please refer to the datasheet for stepsize details.

The HFRCO and AUXHFRCO can be set to one of several different frequency bands from 1 MHz to 28 MHz by setting the BAND field in CMU_HFRCOCTRL and CMU_AUXHFRCOCTRL.The HFRCO and AUXHFRCO frequency bands are calibrated during production test, and the production tested calibration values can be read from the Device Information (DI) page. The DI page contains a separate tuning value for each frequency band. During reset, HFRCO and AUXHFRCO tuning values are set to the production calibrated values for the 14 MHz band, which is the default frequency band. When changing to a different HFRCO or AUXHFRCO band, make sure to also update the tuning value.

The LFRCO and is also calibrated in production and its TUNING value is set to the correct value during reset.

The CMU has built-in HW support to efficiently calibrate the RC oscillators at run-time, see Figure 12.6 (p.

174) The concept is to select a reference and compare the RC frequency with the reference frequency.

When the calibration circuit is started, one down-counter running on a selectable clock (DOWNSEL in CMU_CALCTRL) and one up-counter running on a selectable clock (UPSEL in CMU_CALCTRL) are started simultaneously. The top value for the down-counter must be written to CMU_CALCNT before calibration is started. The smallest value that can be written to the CMU_CALCNT is 1. The down-counter counts for CMU_CALCNT+1 cycles. When the down-counter has reached 0, the up-counter is sampled and the CALRDY interrupt flag is set. If CONT in CMU_CALCTRL is cleared, the counters are stopped at this point. If continuous mode is selected by setting CONT in CMU_CALCTRL the down-counter reloads the top value and continues counting and the up-counter restarts from 0. Software can then read out the sampled up-counter value from CMU_CALCNT. Then it is easy to find the ratio between the reference and the oscillator subject to the calibration. Overflows of the up-counter will not occur. If the up-counter reaches its top value before the down counter reaches 0, the top counter stays at its top value. Calibration can be stopped by writing CALSTOP in CMU_CMD. With this HW support, it is simple to write efficient calibration algorithms in software.

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...the world's most energy friendly wireless MCUs Figure 12.6. HW-support for RC Oscillator Calibration

DOWNCLK Dom ain AUXHFRCO HFRCO LFRCO HFXO LFXO (Default ) HFCLK CMU_CALCTRL.DOWNSEL

DOWNCLK 20- bit down- count er = 0 ?

UPCLK Dom ain AUXHFRCO HFRCO LFRCO CMU_CALCTRL.REFSEL

UPCLK HFXO LFXO SYNC 20- bit up- count er Reload down- count er wit h t op value in cont inouous m ode.

TOP Take snapshot of up- count er in up- count er bufffer. If in cont inouous m ode, rest art up- count er from 0.

20- bit up- count er buffer HFCLK Dom ain Writ e t op- value using CMU_CALCNT before st art ing calibrat ion.

SYNC CMU_CALCNT SYNC Set CMU_IF.CALRDY

The counter operation for single and continuous mode are shown in Figure 12.7 (p. 174) and Figure 12.8 (p. 174) respectively.

Figure 12.7. Single Calibration (CONT=0)

Up- count er sam pled and CALRDY int errupt flag set .

Sam pled value available in CMU_CALCNT.

Up- count er 0 TOP Down- count er 0 Calibrat ion St art ed Calibrat ion St opped (count ers st opped)

Figure 12.8. Continuous Calibration (CONT=1)

Up- count er sam pled and CALRDY int errupt flag set .

Sam pled value available in CMU_CALCNT.

Up- count er sam pled and CALRDY int errupt flag set .

Sam pled value available in CMU_CALCNT.

Up- count er 0 TOP Down- count er 0 Calibrat ion St art ed 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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12.3.4 Configuration For Operating Frequencies

The HFXO is capable of driving crystals up to 48 MHz, which allows the EZR32 to run at up to this

frequency. Different frequencies have different requirements as shown in Table 12.1 (p. 175) . Before

going to a high frequency, make sure the registers in the table have the correct values. When going down in frequency, make sure to keep the registers at the values required by the higher frequency until after the switch has been done.

Table 12.1. Configuration For Operating Frequencies

Maximum Frequency MODE in MSC_READCTRL HFLE in CMU_CTRL

16 MHz -

HFXOBUFCUR in CMU_CTRL

BOOSTUPTO32MHZ (default value) 24 MHz 32 MHz 48 MHz WS0 / WS0SCBTP / WS1 / WS1SCBTP / WS2 / WS2SCBTP WS1 / WS1SCBTP / WS2 / WS2SCBTP WS1 / WS1SCBTP / WS2 / WS2SCBTP WS2 / WS2SCBTP 1 1 BOOSTUPTO32MHZ (default value) BOOSTUPTO32MHZ (default value) BOOSTABOVE32MHZ MODE in MSC_READCTRL makes sure the flash is able to operate at the given frequencies by inserting waitstates for flash accesses. HFXOBUFCUR in CMU_CTRL should be set to BOOSTABOVE32MHZ when operating above 32 MHz. When operating at 32 MHz or below, the default value (BOOSTUPTO32MHZ) should be used. HFLE in CMU_CTRL is only required for frequencies above 24 MHz, and ensures correct operation of LE peripherals. The CMU_CTRL_HFLE is or'ed with HFCORECLKLEDIV in CMU_HFCORECLKDIV, so setting either of this bits will reduce the the frequency of CMU_HFCORECLKLEDIV2.

12.3.5 Output Clock on a Pin

It is possible to configure the CMU to output clocks on two pins. This clock selection is done using CLKOUTSEL0 and CLKOUTSEL1 fields in CMU_CTRL. The output pins must be configured in the CMU_ROUTE register.

• LFRCO, LFXO, HFCLK or the qualified clock from any of the oscillators can be output on one pin (CMU_OUT1). A qualified clock will not have any glitches or skewed duty-cycle during startup. For LFXO and HFXO you need to configure LFXOTIMEOUT and HFXOTIMEOUT in CMU_CTRL correctly to guarantee a qualified clock.

• HFRCO, HFXO, HFCLK/2, HFCLK/4, HFCLK/8, HFCLK/16, ULFRCO or AUXHFRCO can be output on another pin (CMU_OUT0) Note that HFXO and HFRCO clock outputs to pin can be unstable after startup and should not be output on a pin before HFXORDY/HFRCORDY is set high in CMU_STATUS.

12.3.6 Protection

It is possible to lock the control- and command registers to prevent unintended software writes to critical clock settings. This is controlled by the CMU_LOCK register.

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12.4 Register Map

The offset register address is relative to the registers base address.

Offset

0x000

0x004 0x008

0x00C

0x010 0x014

0x018 0x01C

0x020

0x024 0x028

0x02C

0x030

0x034

0x038 0x03C

0x040

0x044

0x050

0x054 0x058

0x060 0x068

0x070

0x078

0x080 0x084

Name

CMU_CTRL

CMU_HFCORECLKDIV CMU_HFPERCLKDIV

CMU_HFRCOCTRL

CMU_LFRCOCTRL CMU_AUXHFRCOCTRL

CMU_CALCTRL CMU_CALCNT

CMU_OSCENCMD

CMU_CMD CMU_LFCLKSEL

CMU_STATUS

CMU_IF

CMU_IFS

CMU_IFC CMU_IEN

CMU_HFCORECLKEN0

CMU_HFPERCLKEN0

CMU_SYNCBUSY

CMU_FREEZE CMU_LFACLKEN0

CMU_LFBCLKEN0 CMU_LFAPRESC0

CMU_LFBPRESC0

CMU_PCNTCTRL

CMU_ROUTE CMU_LOCK

Type

RW RW RW RW RW RW RW RW RW RW RW RW RWH W1 W1 RW R R W1 W1 RW RW RW R RW RW RW

Description

CMU Control Register

High Frequency Core Clock Division Register High Frequency Peripheral Clock Division Register

HFRCO Control Register

LFRCO Control Register AUXHFRCO Control Register

Calibration Control Register Calibration Counter Register

Oscillator Enable/Disable Command Register

Command Register Low Frequency Clock Select Register

Status Register

Interrupt Flag Register

Interrupt Flag Set Register

Interrupt Flag Clear Register Interrupt Enable Register

High Frequency Core Clock Enable Register 0

High Frequency Peripheral Clock Enable Register 0

Synchronization Busy Register

Freeze Register Low Frequency A Clock Enable Register 0 (Async Reg)

Low Frequency B Clock Enable Register 0 (Async Reg) Low Frequency A Prescaler Register 0 (Async Reg)

Low Frequency B Prescaler Register 0 (Async Reg)

PCNT Control Register

I/O Routing Register Configuration Lock Register

12.5 Register Description

12.5.1 CMU_CTRL - CMU Control Register

Offset

0x000

Reset Access Bit Position Name

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Bit

31

30

29

28

27

26:23 22:20 19:18 17 16:14 13

...the world's most energy friendly wireless MCUs

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

HFLE 0 RW

High-Frequency LE Interface

Set to allow access to LE peripherals when running at frequencies higher than 24 MHz. Or'ed with CMU_HFCORECLKDIV_HFCORECLKLEDIV to reduce the frequency of CMU_HFCORECLKLEDIV2.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DBGCLK 0 Select clock used for the debug system.

RW

Debug Clock

Value 0 1 Mode AUXHFRCO HFCLK Description AUXHFRCO is the debug clock.

The system clock is the debug clock.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CLKOUTSEL1 0x0 RW

Clock Output Select 1

Controls the clock output multiplexer. To actually output on the pin, set CLKOUT1PEN in CMU_ROUTE.

3 4 5 6 7 Value 0 1 2 Mode LFRCO LFXO HFCLK LFXOQ HFXOQ LFRCOQ HFRCOQ AUXHFRCOQ Description LFRCO (directly from oscillator).

LFXO (directly from oscillator).

HFCLK (undivided).

LFXO (qualified).

HFXO (qualified).

LFRCO (qualified).

HFRCO (qualified).

AUXHFRCO (qualified).

CLKOUTSEL0 0x0 RW

Clock Output Select 0

Controls the clock output multiplexer. To actually output on the pin, set CLKOUT0PEN in CMU_ROUTE.

3 4 5 6 7 Value 0 1 2 Mode HFRCO HFXO HFCLK2 HFCLK4 HFCLK8 HFCLK16 ULFRCO AUXHFRCO RW Description HFRCO (directly from oscillator).

HFXO (directly from oscillator).

HFCLK/2.

HFCLK/4.

HFCLK/8.

HFCLK/16.

ULFRCO (directly from oscillator).

AUXHFRCO (directly from oscillator).

LFXO Timeout

LFXOTIMEOUT 0x3 Configures the start-up delay for LFXO.

Value 0 1 2 3 Mode 8CYCLES 1KCYCLES 16KCYCLES 32KCYCLES Description Timeout period of 8 cycles.

Timeout period of 1024 cycles.

Timeout period of 16384 cycles.

Timeout period of 32768 cycles.

LFXOBUFCUR 0 RW

LFXO Boost Buffer Current

This value has been updated to the correct level during calibration and should not be changed.

HFCLKDIV 0x0 RW Use to divide HFCLK frequency by (HFCLKDIV + 1).

HFCLK Division

LFXOBOOST 1 Adjusts start-up boost current for LFXO.

RW

LFXO Start-up Boost Current

Value 0 1 Mode 70PCENT 100PCENT Description 70 %.

100 %.

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7

Bit

12:11 10:9 6:5

4

3:2 1:0

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Name Reset Access Description

LFXOMODE 0x0 RW

LFXO Mode

Set this to configure the external source for the LFXO. The oscillator setting takes effect when 1 is written to LFXOEN in CMU_OSCENCMD. The oscillator setting is reset to default when 1 is written to LFXODIS in CMU_OSCENCMD.

Value 0 1 Mode XTAL BUFEXTCLK 2 Value 0 1 2 3 DIGEXTCLK HFXOTIMEOUT 0x3 Configures the start-up delay for HFXO.

Mode 8CYCLES 256CYCLES 1KCYCLES 16KCYCLES RW Description 32.768 kHz crystal oscillator.

An AC coupled buffer is coupled in series with LFXTAL_N pin, suitable for external sinus wave (32.768 kHz).

Digital external clock on LFXTAL_N pin. Oscillator is effectively bypassed.

HFXO Timeout

Description Timeout period of 8 cycles.

Timeout period of 256 cycles.

Timeout period of 1024 cycles.

Timeout period of 16384 cycles.

Reserved

Value 1 3

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

HFXOGLITCHDETEN 0 RW

HFXO Glitch Detector Enable

This bit enables the glitch detector which is active as long as the start-up ripple-counter is counting. A detected glitch will reset the ripple-counter effectively increasing the start-up time. Once the ripple-counter has timed-out, glitches will not be detected.

HFXOBUFCUR 0x1 RW

HFXO Boost Buffer Current

The current level in the HFXO buffer should be set to default value when operating on 32 MHz or below. When operating on frequencies above 32 MHz, the buffer current level should be set to 3.

Mode BOOSTUPTO32MHZ BOOSTABOVE32MHZ Description Boost Buffer Current level when HFXO is below or equal to 32 MHz.

Boost Buffer Current Level when HFXO is above 32 MHz.

Reserved

HFXOBOOST

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x3 Used to adjust start-up boost current for HFXO.

RW

HFXO Start-up Boost Current

Value 0 1 2 3 Mode 50PCENT 70PCENT 80PCENT 100PCENT Description 50 %.

70 %.

80 %.

100 % (default).

HFXOMODE 0x0 RW

HFXO Mode

Set this to configure the external source for the HFXO. The oscillator setting takes effect when 1 is written to HFXOEN in CMU_OSCENCMD. The oscillator setting is reset to default when 1 is written to HFXODIS in CMU_OSCENCMD.

Value 0 1 2 Mode XTAL BUFEXTCLK DIGEXTCLK Description 4-48 MHz crystal oscillator.

An AC coupled buffer is coupled in series with HFXTAL_N, suitable for external sine wave (4-48 MHz). The sine wave should have a minimum of 200 mV peak to peak.

Digital external clock on HFXTAL_N pin. Oscillator is effectively bypassed.

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12.5.2 CMU_HFCORECLKDIV - High Frequency Core Clock Division Register

Bit Position Offset

0x004

Reset Access Name Bit

31:9

8

7:4

3:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

HFCORECLKLEDIV 0 RW

Additional Division Factor For HFCORECLKLE

Additional division factor for HFCORECLKLE. When running at frequencies higher than 24 MHz, this must be set to DIV4.

Value 0 1 4 5 6 7 8 9 Value 0 1 2 3 Mode DIV2 DIV4 Description Valid for frequencies 24 MHz and lower.

Must be used when HFCORECLK may go above 24 MHz.

Reserved

HFCORECLKDIV

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 Specifies the clock divider for HFCORECLK.

RW

HFCORECLK Divider

Mode HFCLK HFCLK2 HFCLK4 HFCLK8 HFCLK16 HFCLK32 HFCLK64 HFCLK128 HFCLK256 HFCLK512 Description HFCORECLK = HFCLK.

HFCORECLK = HFCLK/2.

HFCORECLK = HFCLK/4.

HFCORECLK = HFCLK/8.

HFCORECLK = HFCLK/16.

HFCORECLK = HFCLK/32.

HFCORECLK = HFCLK/64.

HFCORECLK = HFCLK/128.

HFCORECLK = HFCLK/256.

HFCORECLK = HFCLK/512.

12.5.3 CMU_HFPERCLKDIV - High Frequency Peripheral Clock Division Register

Bit Position Offset

0x008

Reset Access Name Bit

31:9

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

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Bit

8

7:4

3:0

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Name Reset Access Description

HFPERCLKEN 1 Set to enable the HFPERCLK.

Reserved

RW

HFPERCLK Enable

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

HFPERCLKDIV 0x0 Specifies the clock divider for the HFPERCLK.

RW

HFPERCLK Divider

2 3 4 5 6 7 8 9 Value 0 1 Mode HFCLK HFCLK2 HFCLK4 HFCLK8 HFCLK16 HFCLK32 HFCLK64 HFCLK128 HFCLK256 HFCLK512 Description HFPERCLK = HFCLK.

HFPERCLK = HFCLK/2.

HFPERCLK = HFCLK/4.

HFPERCLK = HFCLK/8.

HFPERCLK = HFCLK/16.

HFPERCLK = HFCLK/32.

HFPERCLK = HFCLK/64.

HFPERCLK = HFCLK/128.

HFPERCLK = HFCLK/256.

HFPERCLK = HFCLK/512.

12.5.4 CMU_HFRCOCTRL - HFRCO Control Register

Bit Position Offset

0x00C

Reset Access Name Bit

31:17

16:12

11

10:8 7:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SUDELAY Always write this field to 0.

0x00

Reserved

RW

HFRCO Start-up Delay

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BAND 0x3 RW

HFRCO Band Select

Write this field to set the frequency band in which the HFRCO is to operate. When changing this setting there will be no glitches on the HFRCO output, hence it is safe to change this setting even while the system is running on the HFRCO. To ensure an accurate frequency, the HFTUNING value should also be written when changing the frequency band. The calibrated tuning value for the different bands can be read from the Device Information page.

3 4 5 Value 0 1 2 Mode 1MHZ 7MHZ 11MHZ 14MHZ 21MHZ 28MHZ Description 1 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

7 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

11 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

14 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

21 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

28 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

TUNING 0x80 RW

HFRCO Tuning Value

Writing this field adjusts the HFRCO frequency (the higher value, the higher frequency). This field is updated with the production calibrated value for the 14 MHz band during reset, and the reset value might therefore vary between devices.

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12.5.5 CMU_LFRCOCTRL - LFRCO Control Register

Offset

0x010

Reset Access Bit Position Name Bit

31:7

6:0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TUNING 0x40 RW

LFRCO Tuning Value

Writing this field adjusts the LFRCO frequency (the higher value, the higher frequency). This field is updated with the production calibrated value during reset, and the reset value might therefore vary between devices.

12.5.6 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register

Bit Position Offset

0x014

Reset Access Name Bit

31:11

10:8 7:0

Name

Reserved

BAND 0x0 RW

AUXHFRCO Band Select

Write this field to set the frequency band in which the AUXHFRCO is to operate. When changing this setting there will be no glitches on the AUXHFRCO output, hence it is safe to change this setting even while the system is using the AUXHFRCO. To ensure an accurate frequency, the AUXTUNING value should also be written when changing the frequency band. The calibrated tuning value for the different bands can be read from the Device Information page. Flash erase and write use this clock. If it is changed to another value than the default, MSC_TIMEBASE must also be configured to ensure correct flash erase and write operation.

3 6 7 Value 0 1 2 Mode 14MHZ 11MHZ 7MHZ 1MHZ 28MHZ 21MHZ

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

Description 14 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

11 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

7 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

1 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

28 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

21 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

TUNING 0x80 RW

AUXHFRCO Tuning Value

Writing this field adjusts the AUXHFRCO frequency (the higher value, the higher frequency).This field is updated with the production calibrated value during reset, and the reset value might therefore vary between devices.

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12.5.7 CMU_CALCTRL - Calibration Control Register

Offset

0x018

Reset Access Bit Position Name Bit

31:7

6 5:3 2:0

Name Reset Access Description

Reserved

CONT

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Set this bit to enable continuous calibration.

RW DOWNSEL 0x0 RW Selects clock source for the calibration down-counter.

Continuous Calibration Calibration Down-counter Select

3 4 5 Value 0 1 2 UPSEL 0x0 RW Selects clock source for the calibration up-counter.

2 3 4 Value 0 1 Mode HFCLK HFXO LFXO HFRCO LFRCO AUXHFRCO Mode HFXO LFXO HFRCO LFRCO AUXHFRCO Description Select HFCLK for down-counter.

Select HFXO for down-counter.

Select LFXO for down-counter.

Select HFRCO for down-counter.

Select LFRCO for down-counter.

Select AUXHFRCO for down-counter.

Calibration Up-counter Select

Description Select HFXO as up-counter.

Select LFXO as up-counter.

Select HFRCO as up-counter.

Select LFRCO as up-counter.

Select AUXHFRCO as up-counter.

12.5.8 CMU_CALCNT - Calibration Counter Register

Offset

0x01C

Bit Position Reset Access Name Bit

31:20

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

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Bit

19:0

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Name Reset Access Description

CALCNT 0x00000 RWH

Calibration Counter

Write top value before calibration. Read calibration result from this register when Calibration Ready flag has been set.

12.5.9 CMU_OSCENCMD - Oscillator Enable/Disable Command Register

Bit Position Offset

0x020

Reset Access Name Bit

31:10

9 8 7 6 5 4 3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LFXODIS 0 W1

LFXO Disable

Disables the LFXO. LFXOEN has higher priority if written simultaneously.

LFXOEN Enables the LFXO.

0 W1

LFXO Enable

LFRCODIS 0 W1

LFRCO Disable

Disables the LFRCO. LFRCOEN has higher priority if written simultaneously.

LFRCOEN Enables the LFRCO.

0 W1

LFRCO Enable

AUXHFRCODIS 0 W1

AUXHFRCO Disable

Disables the AUXHFRCO. AUXHFRCOEN has higher priority if written simultaneously. WARNING: Do not disable this clock during a flash erase/write operation.

AUXHFRCOEN Enables the AUXHFRCO.

HFXOEN Enables the HFXO.

0 0 W1 W1

AUXHFRCO Enable

HFXODIS 0 W1

HFXO Disable

Disables the HFXO. HFXOEN has higher priority if written simultaneously. WARNING: Do not disable the HFRXO if this oscillator is selected as the source for HFCLK.

HFXO Enable

HFRCODIS 0 W1

HFRCO Disable

Disables the HFRCO. HFRCOEN has higher priority if written simultaneously. WARNING: Do not disable the HFRCO if this oscillator is selected as the source for HFCLK.

HFRCOEN Enables the HFRCO.

0 W1

HFRCO Enable

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12.5.10 CMU_CMD - Command Register

Offset

0x024

Reset Access Bit Position Name

4 3 2:0

Bit

31:8

7:5

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USBCCLKSEL 0x0 W1

USB Core Clock Select

Selects the clock for HFCORECLK USBC . The status register is updated when the clock switch has taken effect.

Value 1 2 3 CALSTOP 0 Stops the calibration counters.

W1

Calibration Stop

CALSTART 0 W1

Calibration Start

Starts the calibration, effectively loading the CMU_CALCNT into the down-counter and start decrementing.

HFCLKSEL 0x0 W1

HFCLK Select

Selects the clock source for HFCLK. Note that selecting an oscillator that is disabled will cause the system clock to stop. Check the status register and confirm that oscillator is ready before switching.

Value 1 2 3 4 Mode HFCLKNODIV LFXO LFRCO Mode HFRCO HFXO LFRCO LFXO Description Select HFCLK (undivided) as HFCORECLK USBC .

Select LFXO as HFCORECLK USBC .

Select LFRCO as HFCORECLK USBC .

Description Select HFRCO as HFCLK.

Select HFXO as HFCLK.

Select LFRCO as HFCLK.

Select LFXO as HFCLK.

12.5.11 CMU_LFCLKSEL - Low Frequency Clock Select Register

Offset

0x028

Reset Access Bit Position Name Bit

31:21

20

Name Reset Access Description

Reserved

LFBE

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 This bit redefines the meaning of the LFB field.

RW

Clock Select for LFB Extended

Value 0 Mode DISABLED Description LFBCLK is disabled (when LFB = DISABLED).

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Bit

19:17

16

15:4

3:2 1:0

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Name

Value 1 Value 0 1 Mode ULFRCO Mode DISABLED ULFRCO

Reset Access Description

Description ULFRCO selected as LFBCLK (when LFB = DISABLED).

Reserved

LFAE

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 This bit redefines the meaning of the LFA field.

RW

Clock Select for LFA Extended

Description LFACLK is disabled (when LFA = DISABLED).

ULFRCO selected as LFACLK (when LFA = DISABLED).

Reserved

LFB

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x1 Selects the clock source for LFBCLK.

RW

Clock Select for LFB

LFB 0 1 2 3 0 LFBE 0 0 0 0 1 Mode Disabled LFRCO LFXO HFCORECLKLEDIV2 ULFRCO Description LFBCLK is disabled LFRCO selected as LFBCLK LFXO selected as LFBCLK HFCORECLK LE divided by two is selected as LFBCLK ULFRCO selected as LFBCLK RW

Clock Select for LFA

LFA 0x1 Selects the clock source for LFACLK.

LFA 0 1 2 3 LFAE 0 0 0 0 0 1 Mode Disabled LFRCO LFXO HFCORECLKLEDIV2 ULFRCO Description LFACLK is disabled LFRCO selected as LFACLK LFXO selected as LFACLK HFCORECLK LE divided by two is selected as LFACLK ULFRCO selected as LFACLK

12.5.12 CMU_STATUS - Status Register

Offset

0x02C

Reset Access Bit Position Name Bit

31:18

17 16 15

Name Reset Access Description

Reserved

USBCLFRCOSEL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 R LFRCO is selected (and active) as HFCORECLK USBC .

USBCLFXOSEL 0 R LFXO is selected (and active) as HFCORECLK USBC .

USBCHFCLKSEL 0 R HFCLK is selected (and active) as HFCORECLK USBC .

USBC LFRCO Selected USBC LFXO Selected USBC HFCLK Selected

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12 11 10 9 8 7 6 1 0 5 4 3 2

Bit

14 13

Name Reset Access

CALBSY Calibration is on-going.

0 LFXOSEL 0 LFXO is selected as HFCLK clock source.

LFRCOSEL 0 LFRCO is selected as HFCLK clock source.

HFXOSEL 0 HFXO is selected as HFCLK clock source.

HFRCOSEL 1 HFRCO is selected as HFCLK clock source.

R R R R R LFXORDY 0 R LFXO is enabled and start-up time has exceeded.

LFXOENS LFXO is enabled.

0 R LFRCORDY 0 R LFRCO is enabled and start-up time has exceeded.

LFRCOENS LFRCO is enabled.

0 R AUXHFRCORDY 0 R AUXHFRCO is enabled and start-up time has exceeded.

AUXHFRCOENS AUXHFRCO is enabled.

0 R HFXORDY 0 R HFXO is enabled and start-up time has exceeded.

HFXOENS HFXO is enabled.

0 R HFRCORDY 1 R HFRCO is enabled and start-up time has exceeded.

HFRCOENS HFRCO is enabled.

1 R

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Description Calibration Busy LFXO Selected LFRCO Selected HFXO Selected HFRCO Selected LFXO Ready LFXO Enable Status LFRCO Ready LFRCO Enable Status AUXHFRCO Ready AUXHFRCO Enable Status HFXO Ready HFXO Enable Status HFRCO Ready HFRCO Enable Status

12.5.13 CMU_IF - Interrupt Flag Register

Bit Position Offset

0x030

Reset Access Name Bit

31:8

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

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1 0 5 4 3 2

Bit

7 6

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Name Reset Access

USBCHFCLKSEL 0 R Set when HFCLK is selected as HFCORECLK USBC .

CALOF 0 R Set when calibration overflow has occurred CALRDY 0 Set when calibration is completed.

R AUXHFRCORDY 0 R Set when AUXHFRCO is ready (start-up time exceeded).

LFXORDY 0 R Set when LFXO is ready (start-up time exceeded).

LFRCORDY 0 R Set when LFRCO is ready (start-up time exceeded).

HFXORDY 0 R Set when HFXO is ready (start-up time exceeded).

HFRCORDY 1 R Set when HFRCO is ready (start-up time exceeded).

Description USBC HFCLK Selected Interrupt Flag Calibration Overflow Interrupt Flag Calibration Ready Interrupt Flag AUXHFRCO Ready Interrupt Flag LFXO Ready Interrupt Flag LFRCO Ready Interrupt Flag HFXO Ready Interrupt Flag HFRCO Ready Interrupt Flag

12.5.14 CMU_IFS - Interrupt Flag Set Register

Bit Position Offset

0x034

Reset Access Name

2 1 6 5 4 3

Bit

31:8

7

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USBCHFCLKSEL 0 W1 Write to 1 to set the USBC HFCLK Selected Interrupt Flag.

CALOF 0 W1 Write to 1 to set the Calibration Overflow Interrupt Flag.

USBC HFCLK Selected Interrupt Flag Set Calibration Overflow Interrupt Flag Set

CALRDY 0 W1

Calibration Ready Interrupt Flag Set

Write to 1 to set the Calibration Ready(completed) Interrupt Flag.

AUXHFRCORDY 0 W1 Write to 1 to set the AUXHFRCO Ready Interrupt Flag.

AUXHFRCO Ready Interrupt Flag Set LFXO Ready Interrupt Flag Set

LFXORDY 0 Write to 1 to set the LFXO Ready Interrupt Flag.

W1 LFRCORDY 0 W1 Write to 1 to set the LFRCO Ready Interrupt Flag.

LFRCO Ready Interrupt Flag Set

HFXORDY 0 W1 Write to 1 to set the HFXO Ready Interrupt Flag.

HFXO Ready Interrupt Flag Set

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Bit

0

Name Reset Access

HFRCORDY 0 W1 Write to 1 to set the HFRCO Ready Interrupt Flag.

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Description HFRCO Ready Interrupt Flag Set

12.5.15 CMU_IFC - Interrupt Flag Clear Register

Offset

0x038

Reset Access Bit Position Name

5 4 3 2 1 0

Bit

31:8

7 6

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USBCHFCLKSEL 0 W1 Write to 1 to clear the USBC HFCLK Selected Interrupt Flag.

USBC HFCLK Selected Interrupt Flag Clear

CALOF 0 W1 Write to 1 to clear the Calibration Overflow Interrupt Flag.

Calibration Overflow Interrupt Flag Clear Calibration Ready Interrupt Flag Clear

CALRDY 0 W1 Write to 1 to clear the Calibration Ready Interrupt Flag.

AUXHFRCORDY 0 W1 Write to 1 to clear the AUXHFRCO Ready Interrupt Flag.

LFXORDY 0 W1 Write to 1 to clear the LFXO Ready Interrupt Flag.

AUXHFRCO Ready Interrupt Flag Clear LFXO Ready Interrupt Flag Clear LFRCO Ready Interrupt Flag Clear

LFRCORDY 0 W1 Write to 1 to clear the LFRCO Ready Interrupt Flag.

HFXORDY 0 W1 Write to 1 to clear the HFXO Ready Interrupt Flag.

HFRCORDY 0 W1 Write to 1 to clear the HFRCO Ready Interrupt Flag.

HFXO Ready Interrupt Flag Clear HFRCO Ready Interrupt Flag Clear

12.5.16 CMU_IEN - Interrupt Enable Register

Offset

0x03C

Reset Access Bit Position Name

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5 4 3 2 1 0

Bit

31:8

7 6

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Name Reset Access Description

Reserved

USBCHFCLKSEL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 RW Set to enable the USBC HFCLK Selected Interrupt.

CALOF 0 Set to enable the Calibration Overflow Interrupt.

RW CALRDY 0 Set to enable the Calibration Ready Interrupt.

RW AUXHFRCORDY 0 Set to enable the AUXHFRCO Ready Interrupt.

RW LFXORDY 0 Set to enable the LFXO Ready Interrupt.

RW LFRCORDY 0 Set to enable the LFRCO Ready Interrupt.

HFXORDY 0 Set to enable the HFXO Ready Interrupt.

HFRCORDY 0 Set to enable the HFRCO Ready Interrupt.

RW RW RW

USBC HFCLK Selected Interrupt Enable Calibration Overflow Interrupt Enable Calibration Ready Interrupt Enable AUXHFRCO Ready Interrupt Enable LFXO Ready Interrupt Enable LFRCO Ready Interrupt Enable HFXO Ready Interrupt Enable HFRCO Ready Interrupt Enable

12.5.17 CMU_HFCORECLKEN0 - High Frequency Core Clock Enable Register 0

Bit Position Offset

0x040

Reset Access Name

2 1 0

Bit

31:5

4 3

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LE 0 RW

Low Energy Peripheral Interface Clock Enable

Set to enable the clock for LE. Interface used for bus access to Low Energy peripherals.

USB 0 Set to enable the clock for USB.

RW

Universal Serial Bus Interface Clock Enable

RW

Universal Serial Bus Interface Core Clock Enable

USBC 0 Set to enable the clock for USBC.

AES 0 Set to enable the clock for AES.

DMA 0 Set to enable the clock for DMA.

RW RW

Advanced Encryption Standard Accelerator Clock Enable Direct Memory Access Controller Clock Enable

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12.5.18 CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0

Offset

0x044

Reset Access Bit Position Name Bit

31:18

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

Name Reset Access Description

Reserved

DAC0

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Set to enable the clock for DAC0.

ADC0 0 Set to enable the clock for ADC0.

PRS 0 Set to enable the clock for PRS.

VCMP 0 Set to enable the clock for VCMP.

GPIO 0 Set to enable the clock for GPIO.

I2C1 0 Set to enable the clock for I2C1.

I2C0 0 Set to enable the clock for I2C0.

ACMP1 0 Set to enable the clock for ACMP1.

ACMP0 0 Set to enable the clock for ACMP0.

TIMER3 0 Set to enable the clock for TIMER3.

TIMER2 0 Set to enable the clock for TIMER2.

TIMER1 0 Set to enable the clock for TIMER1.

TIMER0 0 Set to enable the clock for TIMER0.

UART1 0 Set to enable the clock for UART1.

UART0 0 Set to enable the clock for UART0.

USART2 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Digital to Analog Converter 0 Clock Enable Analog to Digital Converter 0 Clock Enable Peripheral Reflex System Clock Enable Voltage Comparator Clock Enable General purpose Input/Output Clock Enable I2C 1 Clock Enable I2C 0 Clock Enable Analog Comparator 1 Clock Enable Analog Comparator 0 Clock Enable Timer 3 Clock Enable Timer 2 Clock Enable Timer 1 Clock Enable Timer 0 Clock Enable Universal Asynchronous Receiver/Transmitter 1 Clock Enable Universal Asynchronous Receiver/Transmitter 0 Clock Enable Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable

Set to enable the clock for USART2.

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Bit

1 0

Name

USART1

Reset

0 Set to enable the clock for USART1.

USARTRF0 0 Set to enable the clock for USARTRF0.

Access

RW

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Description Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable

RW

Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable

12.5.19 CMU_SYNCBUSY - Synchronization Busy Register

Bit Position Offset

0x050

Reset Access Name

1

0

3

2

5

4

Bit

31:7

6

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LFBPRESC0 0 R

Low Frequency B Prescaler 0 Busy

Used to check the synchronization status of CMU_LFBPRESC0.

Value 1 Description CMU_LFBPRESC0 is busy synchronizing new value.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LFBCLKEN0 0 R

Low Frequency B Clock Enable 0 Busy

Used to check the synchronization status of CMU_LFBCLKEN0.

Value 0 1 Description CMU_LFBCLKEN0 is ready for update.

CMU_LFBCLKEN0 is busy synchronizing new value.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LFAPRESC0 0 R

Low Frequency A Prescaler 0 Busy

Used to check the synchronization status of CMU_LFAPRESC0.

Value 0 1 Description CMU_LFAPRESC0 is ready for update.

CMU_LFAPRESC0 is busy synchronizing new value.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LFACLKEN0 0 R

Low Frequency A Clock Enable 0 Busy

Used to check the synchronization status of CMU_LFACLKEN0.

Value 0 1 Description CMU_LFACLKEN0 is ready for update.

CMU_LFACLKEN0 is busy synchronizing new value.

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12.5.20 CMU_FREEZE - Freeze Register

Offset

0x054

Reset Access Bit Position Name Bit

31:1

0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

REGFREEZE 0 RW

Register Update Freeze

When set, the update of the Low Frequency clock control registers is postponed until this bit is cleared. Use this bit to update several registers simultaneously.

Value 0 1 Mode UPDATE FREEZE Description Each write access to a Low Frequency clock control register is updated into the Low Frequency domain as soon as possible.

The LE Clock Control registers are not updated with the new written value.

12.5.21 CMU_LFACLKEN0 - Low Frequency A Clock Enable Register 0 (Async Reg)

Bit Position Offset

0x058

Reset Access Name Bit

31:3

2 1 0

Name Reset Access Description

Reserved

LETIMER0

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Set to enable the clock for LETIMER0.

RTC 0 Set to enable the clock for RTC.

LESENSE 0 Set to enable the clock for LESENSE.

RW RW RW

Low Energy Timer 0 Clock Enable Real-Time Counter Clock Enable Low Energy Sensor Interface Clock Enable

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12.5.22 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg)

Offset

0x060

Reset Access Bit Position Name Bit

31:2

1 0

Name Reset Access Description

Reserved

LEUART1

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Set to enable the clock for LEUART1.

LEUART0 0 Set to enable the clock for LEUART0.

RW RW

Low Energy UART 1 Clock Enable Low Energy UART 0 Clock Enable

12.5.23 CMU_LFAPRESC0 - Low Frequency A Prescaler Register 0 (Async Reg)

Bit Position Offset

0x068

Reset Access Name Bit

31:12

11:8

Name Reset Access Description

Reserved

LETIMER0

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 Configure Low Energy Timer 0 prescaler RW

Low Energy Timer 0 Prescaler

4 5 6 7 8 9 Value 0 1 2 3 10 11 12 Mode DIV1 DIV2 DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 DIV256 DIV512 DIV1024 DIV2048 DIV4096 Description LFACLK LETIMER0 = LFACLK LFACLK LETIMER0 = LFACLK/2 LFACLK LETIMER0 = LFACLK/4 LFACLK LETIMER0 = LFACLK/8 LFACLK LETIMER0 = LFACLK/16 LFACLK LETIMER0 = LFACLK/32 LFACLK LETIMER0 = LFACLK/64 LFACLK LETIMER0 = LFACLK/128 LFACLK LETIMER0 = LFACLK/256 LFACLK LETIMER0 = LFACLK/512 LFACLK LETIMER0 = LFACLK/1024 LFACLK LETIMER0 = LFACLK/2048 LFACLK LETIMER0 = LFACLK/4096 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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Bit

7:4

3:2

1:0

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Name

Value 13 14 15 RTC 0x0 Configure Real-Time Counter prescaler 10 11 12 13 14 15 4 5 6 7 8 9 Value 0 1 2 3 Value 0 1 2 3 Mode DIV8192 DIV16384 DIV32768 Mode DIV1 DIV2 DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 DIV256 DIV512 DIV1024 DIV2048 DIV4096 DIV8192 DIV16384 DIV32768

Reserved

LESENSE

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 RW Configure Low Energy Sensor Interface prescaler

Low Energy Sensor Interface Prescaler

Mode DIV1 DIV2 DIV4 DIV8

Reset Access

RW

Description

Description LFACLK LETIMER0 = LFACLK/8192 LFACLK LETIMER0 = LFACLK/16384 LFACLK LETIMER0 = LFACLK/32768

Real-Time Counter Prescaler

Description LFACLK RTC = LFACLK LFACLK RTC = LFACLK/2 LFACLK RTC = LFACLK/4 LFACLK RTC = LFACLK/8 LFACLK RTC = LFACLK/16 LFACLK RTC = LFACLK/32 LFACLK RTC = LFACLK/64 LFACLK RTC = LFACLK/128 LFACLK RTC = LFACLK/256 LFACLK RTC = LFACLK/512 LFACLK RTC = LFACLK/1024 LFACLK RTC = LFACLK/2048 LFACLK RTC = LFACLK/4096 LFACLK RTC = LFACLK/8192 LFACLK RTC = LFACLK/16384 LFACLK RTC = LFACLK/32768 Description LFACLK LESENSE = LFACLK LFACLK LESENSE = LFACLK/2 LFACLK LESENSE = LFACLK/4 LFACLK LESENSE = LFACLK/8

12.5.24 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg)

Bit Position Offset

0x070

Reset Access Name Bit

31:6

5:4

Name Reset Access Description

Reserved

LEUART1

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 Configure Low Energy UART 1 prescaler RW

Low Energy UART 1 Prescaler

Value 0 Mode DIV1 Description LFBCLK LEUART1 = LFBCLK 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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Bit

3:2

1:0

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Name

Value 1 2 3 Value 0 1 2 3 Mode DIV2 DIV4 DIV8 Mode DIV1 DIV2 DIV4 DIV8

Reset Access Description

Description LFBCLK LEUART1 = LFBCLK/2 LFBCLK LEUART1 = LFBCLK/4 LFBCLK LEUART1 = LFBCLK/8

Reserved

LEUART0

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 Configure Low Energy UART 0 prescaler RW

Low Energy UART 0 Prescaler

Description LFBCLK LEUART0 = LFBCLK LFBCLK LEUART0 = LFBCLK/2 LFBCLK LEUART0 = LFBCLK/4 LFBCLK LEUART0 = LFBCLK/8

12.5.25 CMU_PCNTCTRL - PCNT Control Register

Offset

0x078

Reset Access Bit Position Name Bit

31:6

5 4 3 2 1

Name Reset Access Description

Reserved

PCNT2CLKSEL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 RW This bit controls which clock that is used for the PCNT.

PCNT2 Clock Select

Value 0 1 Value 0 1 Mode LFACLK PCNT2S0 PCNT2CLKEN 0 This bit enables/disables the clock to the PCNT.

RW Description PCNT2 is disabled.

PCNT2 is enabled.

Value 0 1 PCNT0CLKSEL Description PCNT1 is disabled.

PCNT1 is enabled.

0 RW Description LFACLK is clocking PCNT2.

External pin PCNT2_S0 is clocking PCNT0.

PCNT2 Clock Enable

PCNT1CLKSEL 0 RW This bit controls which clock that is used for the PCNT.

Value 0 1 Mode LFACLK PCNT1S0 PCNT1CLKEN 0 This bit enables/disables the clock to the PCNT.

RW

PCNT1 Clock Select

Description LFACLK is clocking PCNT0.

External pin PCNT1_S0 is clocking PCNT0.

PCNT1 Clock Enable PCNT0 Clock Select

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0

Bit

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Name Reset Access Description

This bit controls which clock that is used for the PCNT.

Value 0 1 Mode LFACLK PCNT0S0 Description LFACLK is clocking PCNT0.

External pin PCNT0_S0 is clocking PCNT0.

PCNT0CLKEN 0 This bit enables/disables the clock to the PCNT.

RW Value 0 1 Description PCNT0 is disabled.

PCNT0 is enabled.

PCNT0 Clock Enable

12.5.26 CMU_ROUTE - I/O Routing Register

Offset

0x080

Reset Access Bit Position Name

1 0

Bit

31:5

4:2

Name Reset Access Description

Reserved

LOCATION

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 Decides the location of the CMU I/O pins.

RW

I/O Location

Value 0 1 2 Mode LOC0 LOC1 LOC2 CLKOUT1PEN 0 When set, the CLKOUT1 pin is enabled.

CLKOUT0PEN 0 When set, the CLKOUT0 pin is enabled.

RW RW Description Location 0 Location 1 Location 2

CLKOUT1 Pin Enable CLKOUT0 Pin Enable

12.5.27 CMU_LOCK - Configuration Lock Register

Offset

0x084

Bit Position Reset Access Name

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Bit

31:16

15:0

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Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

LOCKKEY 0x0000 RW

Configuration Lock Key

Write any other value than the unlock code to lock CMU_CTRL, CMU_HFCORECLKDIV, CMU_HFPERCLKDIV, CMU_HFRCOCTRL, CMU_LFRCOCTRL, CMU_AUXHFRCOCTRL, CMU_OSCENCMD, CMU_CMD, CMU_LFCLKSEL, CMU_HFCORECLKEN0, CMU_HFPERCLKEN0, CMU_LFACLKEN0, CMU_LFBCLKEN0, CMU_LFAPRESC0, CMU_LFBPRESC0, and CMU_PCNTCTRL from editing. Write the unlock code to unlock. When reading the register, bit 0 is set when the lock is enabled.

Mode Read Operation UNLOCKED LOCKED Write Operation LOCK UNLOCK Value 0 1 0 0x580E Description CMU registers are unlocked.

CMU registers are locked.

Lock CMU registers.

Unlock CMU registers.

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13 WDOG - Watchdog Timer

0 1 2 3 4

Count er value Wat chdog clear Tim eout period Syst em reset Tim e

Quick Facts What?

The WDOG (Watchdog Timer) resets the system in case of a fault condition, and can be enabled in all energy modes as long as the low frequency clock source is available.

Why?

If a software failure or external event renders the MCU unresponsive, a Watchdog timeout will reset the system to a known, safe state.

How?

An enabled Watchdog Timer implements a configurable timeout period. If the CPU fails to re-start the Watchdog Timer before it times out, a full system reset will be triggered. The Watchdog consumes insignificant power, and allows the device to remain safely in low energy modes for up to 256 seconds at a time.

13.1 Introduction

The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a software failure.

13.2 Features

• Clock input from selectable oscillators • Internal 32.768 Hz RC oscillator • Internal 1 kHz RC oscillator • External 32.768 Hz XTAL oscillator • Configurable timeout period from 9 to 256k watchdog clock cycles • Individual selection to keep running or freeze when entering EM2 or EM3 • Selection to keep running or freeze when entering debug mode • Selection to block the CPU from entering Energy Mode 4 • Selection to block the CMU from disabling the selected watchdog clock

13.3 Functional Description

The watchdog is enabled by setting the EN bit in WDOG_CTRL. When enabled, the watchdog counts up to the period value configured through the PERSEL field in WDOG_CTRL. If the watchdog timer is not cleared to 0 (by writing a 1 to the CLEAR bit in WDOG_CMD) before the period is reached, the chip is reset. If a timely clear command is issued, the timer starts counting up from 0 again. The watchdog can optionally be locked by writing the LOCK bit in WDOG_CTRL. Once locked, it cannot be disabled or reconfigured by software.

The watchdog counter is reset when EN is reset.

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13.3.1 Clock Source

Three clock sources are available for use with the watchdog, through the CLKSEL field in WDOG_CTRL.

The corresponding clocks must be enabled in the CMU. The SWOSCBLOCK bit in WDOG_CTRL can be written to prevent accidental disabling of the selected clocks. Also, setting this bit will automatically start the selected oscillator source when the watchdog is enabled. The PERSEL field in WDOG_CTRL is used to divide the selected watchdog clock, and the timeout for the watchdog timer can be calculated like this:

WDOG Timeout Equation

T TIMEOUT = (2 3+PERSEL + 1)/f, (13.1) where f is the frequency of the selected clock.

It is recommended to clear the watchdog first, if PERSEL is changed while the watchdog is enabled.

To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to the module clock.

Note

When changing the clock source for WDOG, the EN bit in WDOG_CTRL should be cleared.

In addition to this, the WDOG_SYNCBUSY value should be zero.

13.3.2 Debug Functionality

The watchdog timer can either keep running or be frozen when the device is halted by a debugger. This configuration is done through the DEBUGRUN bit in WDOG_CTRL. When code execution is resumed, the watchdog will continue counting where it left off.

13.3.3 Energy Mode Handling

The watchdog timer can be configured to either keep on running or freeze when entering EM2 or EM3.

The configuration is done individually for each energy mode in the EM2RUN and EM3RUN bits in WDOG_CTRL. When the watchdog has been frozen and is re-entering an energy mode where it is running, the watchdog timer will continue counting where it left off. For the watchdog there is no difference between EM0 and EM1. The watchdog does not run in EM4, and if EM4BLOCK in WDOG_CTRL is set, the CPU is prevented from entering EM4.

Note

If the WDOG is clocked by the LFXO or LFRCO, writing the SWOSCBLOCK bit will effectively prevent the CPU from entering EM3. When running from the ULFRCO, writing the SWOSCBLOCK bit will prevent the CPU from entering EM4.

13.3.4 Register access

Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to the HFCORECLK, special considerations must be taken when accessing registers. Please refer to

Section 6.3 (p. 61) for a description on how to perform register accesses to Low Energy Peripherals.

note that clearing the EN bit in WDOG_CTRL will reset the WDOG module, which will halt any ongoing register synchronization.

Note

Never write to the WDOG registers when it is disabled, except to enable it by setting WDOG_CTRL_EN or when changing the clock source using WDOG_CTRL_CLKSEL.

Make sure that the enable is registered (i.e. WDOG_SYNCBUSY_CTRL goes low), before writing other registers.

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13.4 Register Map

The offset register address is relative to the registers base address.

Offset

0x000

0x004

0x008

Name

WDOG_CTRL

WDOG_CMD

WDOG_SYNCBUSY

Type

RW W1 R

Description

Control Register

Command Register

Synchronization Busy Register

13.5 Register Description

13.5.1 WDOG_CTRL - Control Register (Async Reg)

For more information about Asynchronous Registers please see Section 6.3 (p. 61) .

Offset

0x000

Reset Access Bit Position Name Bit

31:14

13:12 11:8

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CLKSEL 0x0 RW

Watchdog Clock Select

Selects the WDOG oscillator, i.e. the clock on which the watchdog will run.

Value 0 1 2 Mode ULFRCO LFRCO LFXO Description ULFRCO LFRCO LFXO RW

Watchdog Timeout Period Select

PERSEL 0xF Select watchdog timeout period.

10 11 12 13 14 15 4 5 6 7 8 9 Value 0 1 2 3 Description Timeout period of 9 watchdog clock cycles.

Timeout period of 17 watchdog clock cycles.

Timeout period of 33 watchdog clock cycles.

Timeout period of 65 watchdog clock cycles.

Timeout period of 129 watchdog clock cycles.

Timeout period of 257 watchdog clock cycles.

Timeout period of 513 watchdog clock cycles.

Timeout period of 1k watchdog clock cycles.

Timeout period of 2k watchdog clock cycles.

Timeout period of 4k watchdog clock cycles.

Timeout period of 8k watchdog clock cycles.

Timeout period of 16k watchdog clock cycles.

Timeout period of 32k watchdog clock cycles.

Timeout period of 64k watchdog clock cycles.

Timeout period of 128k watchdog clock cycles.

Timeout period of 256k watchdog clock cycles.

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Bit

7

6 5 4 3 2 1 0

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Name Reset Access Description

Reserved

SWOSCBLOCK 0 RW

Software Oscillator Disable Block

Set to disallow disabling of the selected WDOG oscillator. Writing this bit to 1 will turn on the selected WDOG oscillator if it is not already running.

Value 0 1

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

Description Software is allowed to disable the selected WDOG oscillator. See CMU for detailed description. Note that also CMU registers are lockable.

Software is not allowed to disable the selected WDOG oscillator.

EM4BLOCK 0 Set to prevent the EMU from entering EM4.

Value 0 1 RW

Energy Mode 4 Block

Description EM4 can be entered. See EMU for detailed description.

EM4 cannot be entered.

LOCK 0 RW

Configuration lock

Set to lock the watchdog configuration. This bit can only be cleared by reset.

Value 0 1 EM3RUN Description Watchdog configuration can be changed.

Watchdog configuration cannot be changed.

0 Set to keep watchdog running in EM3.

RW

Energy Mode 3 Run Enable

Value 0 1 EM2RUN Description Watchdog timer is frozen in EM3.

Watchdog timer is running in EM3.

0 Set to keep watchdog running in EM2.

RW

Energy Mode 2 Run Enable

Value 0 1 Description Watchdog timer is frozen in EM2.

Watchdog timer is running in EM2.

DEBUGRUN 0 Set to keep watchdog running in debug mode.

RW Value 0 1

Debug Mode Run Enable

Description Watchdog timer is frozen in debug mode.

Watchdog timer is running in debug mode.

EN 0 Set to enabled watchdog timer.

RW

Watchdog Timer Enable

13.5.2 WDOG_CMD - Command Register (Async Reg)

For more information about Asynchronous Registers please see Section 6.3 (p. 61) .

Offset

0x004

Reset Access Bit Position Name

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Bit

31:1

0

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Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CLEAR 0 W1

Watchdog Timer Clear

Clear watchdog timer. The bit must be written 4 watchdog cycles before the timeout.

Value 0 1 Mode UNCHANGED CLEARED Description Watchdog timer is unchanged.

Watchdog timer is cleared to 0.

13.5.3 WDOG_SYNCBUSY - Synchronization Busy Register

Offset

0x008

Reset Access Bit Position Name Bit

31:2

1 0

Name Reset Access Description

Reserved

CMD

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 R Set when the value written to CMD is being synchronized.

CTRL 0 R Set when the value written to CTRL is being synchronized.

CMD Register Busy CTRL Register Busy

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14 PRS - Peripheral Reflex System

0 1 2 3 4

Tim er ADC DMA PRS Ch PRS Ch

Quick Facts What?

The PRS (Peripheral Reflex System) allows configurable, fast and autonomous communication between the peripherals.

Why?

Events and signals from one peripheral can be used as input signals or triggers by other peripherals and ensure timing-critical operation and reduced software overhead.

How?

Without CPU intervention the peripherals can send reflex signals (both pulses and level) to each other in single- or chained steps. The peripherals can be set up to perform actions based on the incoming reflex signals. This results in improved system performance and reduced energy consumption.

14.1 Introduction

The Peripheral Reflex System (PRS) system is a network which allows the different peripheral modules to communicate directly with each other without involving the CPU. Peripheral modules which send out reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which apply actions depending on the reflex signals received. The format for the reflex signals is not given, but edge triggers and other functionality can be applied by the PRS.

14.2 Features

• 12 configurable interconnect channels • Each channel can be connected to any producing peripheral • Consumers can choose which channel to listen to • Selectable edge detector (rising, falling and both edges) • Software controlled channel output • Configurable level • Triggered pulses

14.3 Functional Description

An overview of the PRS module is shown in Figure 14.1 (p. 204) . The PRS contains 12 interconnect

channels, and each of these can select between all the output reflex signals offered by the producers.

The consumers can then choose which PRS channel to listen to and perform actions based on the reflex signals routed through that channel. The reflex signals can be both pulse signals and level signals.

Synchronous PRS pulses are one HFPERCLK cycle long, and can either be sent out by a producer (e.g., ADC conversion complete) or be generated from the edge detector in the PRS channel. Level signals can have an arbitrary waveform (e.g., Timer PWM output).

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14.3.1 Asynchronous Mode

Many reflex signals can operate in two modes, synchronous or asynchronous. A synchronous reflex is clocked on HFPERCLK, and can be used as an input to all reflex consumers, but since they require HFPERCLK, they will not work in EM2/EM3.

Asynchronous reflexes are not clocked on HFPERCLK, and can be used even in EM2/EM3. There is a limitation to reflexes operating in asynchronous mode though: they can only be used by a subset of

the reflex consumers, the ones marked with async support in Table 14.2 (p. 206) . Peripherals that

can produce asynchronous reflexes are marked with async support in Table 14.1 (p. 205) . To use

these reflexes asynchronously, set ASYNC in the CHCTRL register for the PRS channel selecting the reflex signal.

Note

If a peripheral channel with ASYNC set is used in a consumer not supporting asynchronous reflexes, the behaviour is undefined.

14.3.2 Channel Functions

Different functions can be applied to a reflex signal within the PRS. Each channel includes an edge detector to enable generation of pulse signals from level signals. It is also possible to generate output reflex signals by configuring the SWPULSE and SWLEVEL bits. SWLEVEL is a programmable level for each channel and holds the value it is programmed to. The SWPULSE will give out a one-cycle high pulse if it is written to 1, otherwise a 0 is asserted. The SWLEVEL and SWPULSE signals are then XOR'ed with the selected input from the producers to form the output signal sent to the consumers listening to the channel.

Note

The edge detector controlled by EDSEL should only be used when working with synchronous reflexes, i.e., ASYNC in CHCTRL is cleared.

Figure 14.1. PRS Overview

SIGSEL[2:0] SOURCESEL[5:0] ASYNC[n] EDSEL[1:0] SWPULSE[n] SWLEVEL[n] APB bus Signals from producer peripherals Reg Signals t o consum er peripherals

14.3.3 Producers

Each PRS channel can choose between signals from several producers, which is configured in SOURCESEL in PRS_CHx_CTRL. Each of these producers outputs one or more signals which can be selected by setting the SIGSEL field in PRS_CHx_CTRL. Setting the SOURCESEL bits to 0 (Off) leads to a constant 0 output from the input mux. An overview of the available producers is given in

Table 14.1 (p. 205) .

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Table 14.1. Reflex Producers

Module

ACMP ADC DAC GPIO RTC TIMER LETIMER UART

Reflex Output

Comparator Output Single Conversion Done Scan Conversion Done Channel 0 Conversion Done Channel 1 Conversion Done Pin 0 Input Pin 1 Input Pin 2 Input Pin 3 Input Pin 4 Input Pin 5 Input Pin 6 Input Pin 7 Input Pin 8 Input Pin 9 Input Pin 10 Input Pin 11 Input Pin 12 Input Pin 13 Input Pin 14 Input Pin 15 Input Overflow Compare Match 0 Compare Match 1 Underflow Overflow CC0 Output CC1 Output CC2 Output CH0 CH1 TX Complete RX Data Received

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Output Format

Level Pulse Pulse Pulse Pulse Level Level Level Level Level Level Level Level Level Level Level Level Level Level Level Level Pulse Pulse Pulse Pulse Pulse Level Level Level Level Level Pulse Pulse Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

Async Support

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Module

USART VCMP LESENSE BURTC USB

Reflex Output

TX Complete RX Data Received IrDA Decoder Output Comparator Output SCANRES register Decoder Output Overflow Compare match 0 Start of Frame Start of Fram Sent/ Received

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Output Format

Pulse Pulse Level Level Level Level/Pulse Pulse Pulse Yes Yes Yes Yes Yes

Async Support

Yes Yes

14.3.4 Consumers

Consumer peripherals (listed in Table 14.2 (p. 206) ) can be set to listen to a PRS channel and perform

an action based on the signal received on that channel. Most consumers expect pulse input, while some can handle level inputs as well.

Table 14.2. Reflex Consumers

Module

ADC DAC TIMER UART USART LEUART PCNT

Reflex Input

Single Mode Trigger Scan Mode Trigger Channel 0 Trigger Channel 1 Trigger CC0 Input CC1 Input CC2 Input DTI Fault Source 0 (TIMER0 only) DTI Fault Source 1 (TIMER0 only) DTI Input (TIMER0 only) TX/RX Enable RX Input TX/RX Enable IrDA Encoder Input RX Input RX Input S0 input

Input Format

Pulse Pulse Pulse Pulse Pulse/Level Pulse/Level Pulse/Level Pulse Pulse Pulse/Level Pulse Pulse/Level Pulse Pulse Pulse/Level Pulse/Level Level Yes Yes Yes Yes

Async Support

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Module

LESENSE

Reflex Input

S1 input Start scan Decoder Bit 0 Decoder Bit 1 Decoder Bit 2 Decoder Bit 3

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Input Format

Level Pulse/Level Level Level Level Level

Async Support

Yes Yes Yes Yes Yes Yes

Note

It is possible to output prs channel 0 - channel 3 onto the GPIO by setting CH0PEN, CH1PEN, CH2PEN, or CH3PEN in the PRS_ROUTE register.

14.3.5 Example

The example below (illustrated in Figure 14.2 (p. 207) ) shows how to set up ADC0 to start single

conversions every time TIMER0 overflows (one HFPERCLK cycle high pulse), using PRS channel 5: • Set SOURCESEL in PRS_CH5_CTRL to 0b011100 to select TIMER0 as input to PRS channel 5.

• Set SIGSEL in PRS_CH5_CTRL to 0b001 to select the overflow signal (from TIMER0).

• Configure ADC0 with the desired conversion set-up.

• Set SINGLEPRSEN in ADC0_SINGLECTRL to 1 to enable single conversions to be started by a high PRS input signal.

• Set SINGLEPRSSEL in ADC0_SINGLECTRL to 0x5 to select PRS channel 5 as input to start the single conversion.

• Start TIMER0 with the desired TOP value, an overflow PRS signal is output automatically on overflow.

Note that the ADC results needs to be fetched either by the CPU or DMA.

Figure 14.2. TIMER0 overflow starting ADC0 single conversions through PRS channel 5.

TIMER0

Overflow

ADC0

St art single conv.

PRS

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14.4 Register Map

The offset register address is relative to the registers base address.

Offset

0x000

0x004

0x008 0x010

...

0x03C

Name

PRS_SWPULSE

PRS_SWLEVEL

PRS_ROUTE PRS_CH0_CTRL PRS_CHx_CTRL PRS_CH11_CTRL

Type

W1 RW RW RW RW RW

Description

Software Pulse Register

Software Level Register

I/O Routing Register Channel Control Register Channel Control Register Channel Control Register

14.5 Register Description

14.5.1 PRS_SWPULSE - Software Pulse Register

Offset

0x000

Reset Access Bit Position Name Bit

31:12

11 10 9 8 7 6 5 4 3 2

Name

Reserved

CH11PULSE See bit 0.

CH10PULSE See bit 0.

CH9PULSE See bit 0.

CH8PULSE See bit 0.

CH7PULSE See bit 0.

CH6PULSE See bit 0.

CH5PULSE See bit 0.

CH4PULSE See bit 0.

CH3PULSE See bit 0.

CH2PULSE See bit 0.

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0 0 0 0 0 0 0 0 0

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 W1

Channel 11 Pulse Generation

W1 W1 W1 W1 W1 W1 W1 W1 W1

Channel 10 Pulse Generation Channel 9 Pulse Generation Channel 8 Pulse Generation Channel 7 Pulse Generation Channel 6 Pulse Generation Channel 5 Pulse Generation Channel 4 Pulse Generation Channel 3 Pulse Generation Channel 2 Pulse Generation

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Bit

1 0

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Name Reset Access Description

CH1PULSE See bit 0.

0 W1

Channel 1 Pulse Generation

CH0PULSE 0 W1

Channel 0 Pulse Generation

Write to 1 to generate one HFPERCLK cycle high pulse. This pulse is XOR'ed with the corresponding bit in the SWLEVEL register and the selected PRS input signal to generate the channel output.

14.5.2 PRS_SWLEVEL - Software Level Register

Bit Position Offset

0x004

Reset Access Name Bit

31:12

11 10 9 8 7 6 5 4 3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CH11LEVEL See bit 0.

CH10LEVEL See bit 0.

CH9LEVEL See bit 0.

CH8LEVEL See bit 0.

CH7LEVEL See bit 0.

CH6LEVEL See bit 0.

CH5LEVEL See bit 0.

CH4LEVEL See bit 0.

CH3LEVEL See bit 0.

CH2LEVEL See bit 0.

0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW

Channel 11 Software Level Channel 10 Software Level Channel 9 Software Level Channel 8 Software Level Channel 7 Software Level Channel 6 Software Level Channel 5 Software Level Channel 4 Software Level Channel 3 Software Level Channel 2 Software Level

CH1LEVEL See bit 0.

0 RW

Channel 1 Software Level

CH0LEVEL 0 RW

Channel 0 Software Level

The value in this register is XOR'ed with the corresponding bit in the SWPULSE register and the selected PRS input signal to generate the channel output.

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14.5.3 PRS_ROUTE - I/O Routing Register

Offset

0x008

Reset Access Bit Position Name Bit

31:11

10:8

7:4

3 2 1 0

Name

Reserved

LOCATION

Reset

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 Decides the location of the PRS I/O pins.

Access

RW

Description I/O Location

Value 0 1 Mode LOC0 LOC1 Description Location 0 Location 1

Reserved

CH3PEN

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 RW When set, GPIO output from PRS channel 3 is enabled CH2PEN 0 RW When set, GPIO output from PRS channel 2 is enabled CH1PEN 0 RW When set, GPIO output from PRS channel 1 is enabled CH0PEN 0 RW When set, GPIO output from PRS channel 0 is enabled

CH3 Pin Enable CH2 Pin Enable CH1 Pin Enable CH0 Pin Enable

14.5.4 PRS_CHx_CTRL - Channel Control Register

Offset

0x010

Bit Position Reset Access Name Bit

31:29

28

27:26

25:24

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

ASYNC 0 RW Set to disable synchronization of this reflex signal

Reserved

Asynchronous reflex

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

EDSEL Select edge detection.

0x0 RW

Edge Detect Select

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Bit

23:22

21:16

15:3

2:0

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Name

Value 1 2 Mode POSEDGE NEGEDGE

Reset Access Description

Description A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal 3 Value 0b000000 0b000001 0b000010 0b000011 0b000110 0b001000 0b010000 0b010001 0b010010 0b011100 0b011101 0b011110 0b011111 0b100100 0b101000 0b101001 0b101010 0b110000 0b110001 0b110100 0b110111 0b111001 0b111010 0b111011 BOTHEDGES

Reserved

SOURCESEL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x00 Select input source to PRS channel.

RW

Source Select

Mode NONE VCMP ACMP0 ACMP1 DAC0 ADC0 USARTRF0 USART1 USART2 TIMER0 TIMER1 TIMER2 TIMER3 USB RTC UART0 UART1 GPIOL GPIOH LETIMER0 BURTC LESENSEL LESENSEH LESENSED Description No source selected Voltage Comparator Analog Comparator 0 Analog Comparator 1 Digital to Analog Converter 0 Analog to Digital Converter 0 Universal Synchronous/Asynchronous Receiver/Transmitter 0 Universal Synchronous/Asynchronous Receiver/Transmitter 1 Universal Synchronous/Asynchronous Receiver/Transmitter 2 Timer 0 Timer 1 Timer 2 Timer 3 Universal Serial Bus Interface Real-Time Counter Universal Asynchronous Receiver/Transmitter 0 Universal Asynchronous Receiver/Transmitter 1 General purpose Input/Output General purpose Input/Output Low Energy Timer 0 Backup RTC Low Energy Sensor Interface Low Energy Sensor Interface Low Energy Sensor Interface

Reserved

SIGSEL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 Select signal input to PRS channel.

RW

Signal Select

Value SOURCESEL (NONE) 0bxxx SOURCESEL (VCMP) = = 0b000000 0b000001 Mode OFF 0b000 SOURCESEL (ACMP0) 0b000 SOURCESEL (ACMP1) 0b000 = = 0b000010 0b000011 VCMPOUT ACMP0OUT ACMP1OUT SOURCESEL = 0b000110 (DAC0) 0b000 DAC0CH0 0b001 DAC0CH1 SOURCESEL = 0b001000 (ADC0) 0b000 ADC0SINGLE Description Channel input selection is turned off Voltage comparator output VCMPOUT Analog comparator output ACMP0OUT Analog comparator output ACMP1OUT DAC ch0 conversion done DAC0CH0 DAC ch1 conversion done DAC0CH1 ADC single conversion done ADC0SINGLE 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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Bit Name Reset Access

Value 0b001 SOURCESEL (USARTRF0) 0b000 0b001 0b010 SOURCESEL (USART1) 0b001 0b010 SOURCESEL (USART2) = = = 0b010000 0b010001 0b010010 Mode ADC0SCAN USARTRF0IRTX USARTRF0TXC USARTRF0RXDATAV USART1TXC USART1RXDATAV 0b001 0b010 SOURCESEL (TIMER0) 0b000 0b001 0b010 0b011 = 0b011100 USART2TXC USART2RXDATAV TIMER0UF TIMER0OF TIMER0CC0 TIMER0CC1 TIMER0CC2 0b100 SOURCESEL (TIMER1) 0b000 0b001 0b010 0b011 0b100 SOURCESEL (TIMER2) 0b000 0b001 = = 0b011101 0b011110 TIMER1UF TIMER1OF TIMER1CC0 TIMER1CC1 TIMER1CC2 0b010 0b011 0b100 SOURCESEL (TIMER3) = 0b011111 0b000 0b001 0b010 0b011 0b100 SOURCESEL = 0b100100 (USB) TIMER2UF TIMER2OF TIMER2CC0 TIMER2CC1 TIMER2CC2 TIMER3UF TIMER3OF TIMER3CC0 TIMER3CC1 TIMER3CC2 0b000 0b001 SOURCESEL = 0b101000 (RTC) 0b000 0b001 0b010 SOURCESEL (UART0) = 0b101001 USBSOF USBSOFSR RTCOF RTCCOMP0 RTCCOMP1 0b001 0b010 SOURCESEL (UART1) 0b001 = 0b101010 UART0TXC UART0RXDATAV UART1TXC 0b010 SOURCESEL = 0b110000 (GPIO) UART1RXDATAV

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Description

Description ADC scan conversion done ADC0SCAN USART 0 IRDA out USARTRF0IRTX USART 0 TX complete USARTRF0TXC USART 0 RX Data Valid USARTRF0RXDATAV USART 1 TX complete USART1TXC USART 1 RX Data Valid USART1RXDATAV USART 2 TX complete USART2TXC USART 2 RX Data Valid USART2RXDATAV Timer 0 Underflow TIMER0UF Timer 0 Overflow TIMER0OF Timer 0 Compare/Capture 0 TIMER0CC0 Timer 0 Compare/Capture 1 TIMER0CC1 Timer 0 Compare/Capture 2 TIMER0CC2 Timer 1 Underflow TIMER1UF Timer 1 Overflow TIMER1OF Timer 1 Compare/Capture 0 TIMER1CC0 Timer 1 Compare/Capture 1 TIMER1CC1 Timer 1 Compare/Capture 2 TIMER1CC2 Timer 2 Underflow TIMER2UF Timer 2 Overflow TIMER2OF Timer 2 Compare/Capture 0 TIMER2CC0 Timer 2 Compare/Capture 1 TIMER2CC1 Timer 2 Compare/Capture 2 TIMER2CC2 Timer 3 Underflow TIMER3UF Timer 3 Overflow TIMER3OF Timer 3 Compare/Capture 0 TIMER3CC0 Timer 3 Compare/Capture 1 TIMER3CC1 Timer 3 Compare/Capture 2 TIMER3CC2 USB Start of Frame USBSOF USB Start of Frame Sent/Received USBSOFSR RTC Overflow RTCOF RTC Compare 0 RTCCOMP0 RTC Compare 1 RTCCOMP1 USART 0 TX complete UART0TXC USART 0 RX Data Valid UART0RXDATAV USART 0 TX complete UART1TXC USART 0 RX Data Valid UART1RXDATAV 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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Bit Name Reset Access

Value 0b000 0b001 0b010 0b011 0b100 0b101 0b110 0b111 SOURCESEL = 0b110001 (GPIO) 0b000 GPIOPIN8 0b001 GPIOPIN9 0b010 0b011 0b100 GPIOPIN10 GPIOPIN11 GPIOPIN12 0b101 0b110 0b111 SOURCESEL (LETIMER0) = 0b110100 GPIOPIN13 GPIOPIN14 GPIOPIN15 0b000 0b001 SOURCESEL (BURTC) 0b000 0b001 SOURCESEL (LESENSE) 0b000 0b001 = = 0b110111 0b111001 Mode GPIOPIN0 GPIOPIN1 GPIOPIN2 GPIOPIN3 GPIOPIN4 GPIOPIN5 GPIOPIN6 GPIOPIN7 LETIMER0CH0 LETIMER0CH1 BURTCOF BURTCCOMP0 0b010 0b011 0b100 0b101 0b110 0b111 SOURCESEL (LESENSE) 0b000 0b001 0b010 = 0b111010 LESENSESCANRES0 LESENSESCANRES1 LESENSESCANRES2 LESENSESCANRES3 LESENSESCANRES4 LESENSESCANRES5 LESENSESCANRES6 LESENSESCANRES7 LESENSESCANRES8 LESENSESCANRES9 LESENSESCANRES10 0b011 0b100 0b101 0b110 LESENSESCANRES11 LESENSESCANRES12 LESENSESCANRES13 LESENSESCANRES14 0b111 LESENSESCANRES15 SOURCESEL (LESENSE) 0b000 0b001 0b010 = 0b111011 LESENSEDEC0 LESENSEDEC1 LESENSEDEC2

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Description

Description GPIO pin 0 GPIOPIN0 GPIO pin 1 GPIOPIN1 GPIO pin 2 GPIOPIN2 GPIO pin 3 GPIOPIN3 GPIO pin 4 GPIOPIN4 GPIO pin 5 GPIOPIN5 GPIO pin 6 GPIOPIN6 GPIO pin 7 GPIOPIN7 GPIO pin 8 GPIOPIN8 GPIO pin 9 GPIOPIN9 GPIO pin 10 GPIOPIN10 GPIO pin 11 GPIOPIN11 GPIO pin 12 GPIOPIN12 GPIO pin 13 GPIOPIN13 GPIO pin 14 GPIOPIN14 GPIO pin 15 GPIOPIN15 LETIMER CH0 Out LETIMER0CH0 LETIMER CH1 Out LETIMER0CH1 BURTC Overflow BURTCOF BURTC Compare 0 BURTCCOMP0 LESENSE SCANRES register, bit 0 LESENSESCANRES0 LESENSE SCANRES register, bit 1 LESENSESCANRES1 LESENSE SCANRES register, bit 2 LESENSESCANRES2 LESENSE SCANRES register, bit 3 LESENSESCANRES3 LESENSE SCANRES register, bit 4 LESENSESCANRES4 LESENSE SCANRES register, bit 5 LESENSESCANRES5 LESENSE SCANRES register, bit 6 LESENSESCANRES6 LESENSE SCANRES register, bit 7 LESENSESCANRES7 LESENSE SCANRES register, bit 8 LESENSESCANRES8 LESENSE SCANRES register, bit 9 LESENSESCANRES9 LESENSE SCANRES LESENSESCANRES10 LESENSE SCANRES LESENSESCANRES11 register, register, bit bit 10 11 register, bit 12 LESENSE SCANRES LESENSESCANRES12 LESENSE SCANRES LESENSESCANRES13 LESENSE SCANRES LESENSESCANRES14 LESENSE SCANRES LESENSESCANRES15 register, register, register, bit bit bit 13 14 15 LESENSE Decoder PRS out 0 LESENSEDEC0 LESENSE Decoder PRS out 1 LESENSEDEC1 LESENSE Decoder PRS out 2 LESENSEDEC2 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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15 USB - Universal Serial Bus Controller

0 1 2 3 4

Quick Facts What?

The USB is a full-speed/low-speed USB 2.0

compliant USB Controller that can be used in various OTG Dual Role Device, Host and Device configurations. The on-chip 3.3V

regulator delivers up to 50 mA and can also be used to power external components, eliminating the need for an external LDO. The on-chip regulator allows the system to run from a battery utilizing the full voltage range of the EZR32 still being compliant with the 3.3V +/- 10% USB voltage range.

Why?

USB provides a robust, industry-standard way to interface PCs and other portable devices.

How?

The flexible and highly software-configurable architecture of the USB Controller makes it easy to implement both device- and host capable solutions. The on-chip OTG PHY with software controllable pull-up and pull down resistors, VBUS comparators and ID-line detection reduces the number of external components to a minimum. Third party USB software stacks are also available, reducing the development time substantially.

By utilizing the very low energy consumption in EM2, the USB device will be able to wake up and perform tasks several times a second without violating the 2.5 mA maximum average current during suspend.

15.1 Introduction

The USB is a full-speed/low-speed USB 2.0 compliant OTG host/device controller. The architecture is very flexible and allows the USB to be used in various On-the-go (OTG) Dual-Role Device, Host- and Device-only configurations. The USB supports HNP and SRP protocols and both OTG Revisions 1.3

and 2.0 are supported A switchable external 5V supply or step-up regulator is needed for OTG Dual Role Device and Host configurations. The on-chip voltage regulator and PHY reduces the number of external components to a minimum.

15.2 Features

• Fully compliant with Universal Serial Bus Specification, Revision 2.0

• Supports full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) host and device • Dedicated Internal DMA Controller • 12 software-configurable endpoints (6 IN, 6 OUT) in addition to endpoint 0 • 2 KB endpoint memory 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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• Resume/Reset detection in EM2 (during suspend) • SRP detection in EM2 (during host session off) • Soft connect/disconnect • Full OTG support • Compliant with On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification, Revision 2.0

• Compliant with USB On-The-Go Supplement, Revision 1.3

• Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) • On-chip PHY • Internal pull-up and pull-down resistors • Voltage comparators for monitoring VBUS voltage • A/B Device identification using ID line • Charge/discharge of VBUS for VBUS-pulsing • Internal 3.3V Regulator • Output voltage: 3.3V

• Output current: 50 mA • Input voltage range: 4.0 - 5.5V

• Enabled automatically when input voltage applied • Low quiescent current: 100 uA • Dedicated input pin allows regulator to be used in OTG and host configurations • Output pin can be used to power the EZR32 itself as well as external components • Regulator voltage output sense feature for detecting USB plug/unplug events (also available in EM2/3)

15.3 USB System Description

A block diagram of the USB is shown in Figure 15.1 (p. 215) .

Figure 15.1. USB Block Diagram

The USB consists of a digital logic part, an endpoint RAM, PHY and a voltage regulator with output voltage sensor. The voltage regulator provides a stable 3.3 V supply for the PHY, but can also be used to power the EZR32 itself as well as external components.

The digital logic of the USB is split into two parts: system and core.

The system part is accessed using USB registers from offset 0x000 to 0x018 and controls the voltage regulator and enabling/disabling of the PHY and USB pins. This part is clocked by HFCORECLK USB and is accessed using an APB slave interface. The system part can thus be accessed independently of the core part, without HFCORECLK USBC running.

The core part is clocked by HFCORECLK USBC and is accessed using an AHB slave interface. This interface is used for accessing the FIFO contents and the registers in the core part starting at offset 0x3C000. An additional master interface is used by the internal DMA controller of the core. The core part takes care of all the USB protocol related functionality. The clock to the system part must not be disabled when the core part is active.

There are several pins associated with the USB. USB_DP and USB_DM are the USB D+ and D- pins.

These are the USB data signaling pins. USB_VBUS should be connected to the VBUS (5V) pin on the USB receptacle. It is connected to the voltage comparators and current sink/source in the PHY.

USB_ID is the OTG ID pin used to detect the device type (A or B). This pin can be left unconnected when not used. USB_VBUSEN is used to turn on and off VBUS power when operating as host-only or OTG A-Device. USB_VREGI is the input to the voltage regulator and USB_VREGO is the regulated output. USB_DMPU is used to enable/disable an external D- pull-up resistor. This is needed for low 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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speed device only. USB_VBUSEN and USB_DMPU will be high-impedance until enabled from software.

Thus, if a defined level is required during start-up an external pull-up/pull-down can be used.

15.3.1 USB Clocks

The USB requires the device to run a 48 MHz crystal (2500 ppm or better). The core part of the USB will always run from HFCORECLK USBC , which is 48 MHz. The current consumption for the rest of the device can be reduced by dividing down HFCORECLK using the CMU_HFCORECLKDIV register.

Bandwidth requirements for the specific USB application must be taken into account when dividing down HFCORECLK.

15.3.2 USB Initialization

Follow these steps to enable the USB: 1. Enable the clock to the system part by setting USB in CMU_HFCORECLKEN0.

2. If the internal USB regulator is bypassed (by applying 3.3V on USB_VREGI and USB_VREGO externally), disable the regulator by setting VREGDIS in USB_CTRL.

3. If the PHY is powered from VBUS using the internal regulator, the VREGO sense circuit should be enabled by setting VREGOSEN in USB_CTRL.

4. Enable the USB PHY pins by setting PHYPEN in USB_ROUTE.

5. If host or OTG dual-role device, set VBUSENAP in USB_CTRL to the desired value and then enable the USB_VBUSEN pin in USB_ROUTE. Set the MODE for the pin to PUSHPULL.

6. If low-speed device, set DMPUAP in USB_CTRL to the desired value and then enable the USB_DMPU pin in USB_ROUTE. Set the MODE for the pin to PUSHPULL.

7. Make sure the oscillator is ready and selected in CMU_CMD_USBCCLKSEL.

8. Enable the clock to the core part by setting USBC in CMU_HFCORECLKEN0.

9. Wait for the core to come out of reset. This is easiest done by polling a core register with non-zero reset value until it reads a non-zero value. This takes approximately 20 48-MHz cycles.

10.Start initializing the USB core as described in USB Core Description.

15.3.3 Configurations

The USB can be used as Device, OTG Dual Role Device or Host. The sections below describe the different configurations. External ESD protection and series resistors for impedance matching are required. The voltage regulator requires a 4.7 uF external decoupling capacitor on the input and a 1 uF external decoupling capacitor on the output. Decoupling not related to USB is not shown in the figures.

15.3.3.1 Bus-powered Device

A bus-powered device configuration is shown in Figure 15.2 (p. 217) . In this configuration the voltage

regulator powers the PHY and the EZR32 at 3.3 V. The voltage regulator output (USB_VREGO) can also be used to power other components of the system.

In this configuration, the VREGO sense circuit should be left disabled.

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...the world's most energy friendly wireless MCUs Figure 15.2. Bus-powered Device

VDD MCU USB_VREGO USB_VREGI USB_VBUS USB_DP USB_DM VBUS D+ D GND

15.3.3.2 Self-powered Device

A self-powered device configuration is shown in Figure 15.3 (p. 217) . When the USB is configured as

a self-powered device, the voltage regulator is typically used to power the PHY only, although it may also be used to power other 3.3 V components. When the USB is connected to a host, the voltage regulator is activated. Software can detect this event by enabling the VREGO Sense High (VREGOSH) interrupt. The PHY pins can then be enabled and USB traffic can start. The VREGO Sense Low (VREGOSL) interrupt can be used to detect when VBUS voltage disappears (for example if the USB cable is unplugged).

In this configuration, the VREGO sense circuit must be enabled.

Figure 15.3. Self-powered Device

1.8V – 3.6V

VDD MCU USB_VREGO USB_VREGI USB_VBUS USB_DP USB_DM VBUS D+ D GND

15.3.3.3 Self-powered Device (with bus-power switch)

A self-powered device (with bus-power switch) may switch power supply to VBUS when connected to a host. This is typically useful for extending the life of battery-powered devices and enables the use of coin-cell driven systems with low maximum peak current. The external components required typically include 2 transistors, 2 diodes and a few resistors. See application note for details. This allows seamless power supply switching between a battery and the voltage regulator output.

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The VREGO Sense High interrupt is used to detect when VBUS becomes present. Software can then enable the external transistor connected to USB_VREGO, effectively switching the power source. A regular GPIO pin is used to control this transistor. If necessary, the application may have to reduce the current consumption before switching to the USB power source. If VBUS voltage is removed, the circuit switches automatically back to the battery power supply. If necessary software must react quickly to this event and reduce the current consumption (for example by reducing the clock frequency) to avoid

excessive voltage drop. This configuration is shown in Figure 15.4 (p. 218) .

In this configuration, the VREGO sense circuit must be enabled.

Figure 15.4. Self-powered Device (with bus-power switch)

1.8V – 3.6V

Dual- Power Circuit VDD (enable) GPIO USB_VREGO USB_VREGI MCU USB_VBUS USB_DP USB_DM VBUS D+ D GND

15.3.3.4 OTG Dual Role Device (5V)

An OTG Dual Role Device (5V) configuration is shown in Figure 15.5 (p. 219) . When 5V is available,

the internal regulator can be used to power the EZR32. An external power switch is needed to control VBUS power. For over-current detection a regular GPIO input pin with interrupt is used. The application should turn off or limit VBUS power when over-current is detected. In OTG mode, the maximum VBUS decoupling capacitance is 6.5 uF.

In this configuration, the VREGO sense circuit should be left disabled.

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...the world's most energy friendly wireless MCUs Figure 15.5. OTG Dual Role Device (5V)

MCU VDD 5V USB_VREGO USB_VREGI GPIO (over- current ) USB_VBUSEN USB_VBUS USB_DP USB_DM USB_ID OC EN V in V out Power swit ch + over- current det ect ion VBUS D+ D ID GND

15.3.3.5 OTG Dual Role Device (5V step-up regulator)

An OTG Dual Role Device (5V step-up regulator) configuration is shown in Figure 15.6 (p. 219) . When

5V is not available, an external 5V step-up regulator is needed. In this configuration, the voltage for the EZR32 must be in the range 3.0V - 3.6V. In this mode the voltage regulator is bypassed by connecting both the input and output to the external supply. This effectively causes the PHY to be powered directly from the external 3.0 - 3.6 V supply. The voltage regulator should be disabled when operating in this mode. For over-current detection a regular GPIO input pin with interrupt is used. The application should turn off or limit VBUS power when over-current is detected. In OTG mode, the maximum VBUS decoupling capacitance is 6.5 uF.

In this configuration, the VREGO sense circuit should be left disabled.

Figure 15.6. OTG Dual Role Device (5V step-up regulator)

3.0V – 3.6V

MCU VDD USB_VREGI USB_VREGO GPIO (over- current ) USB_VBUSEN OC EN V in V out 5V st ep- up USB_VBUS USB_DP USB_DM USB_ID VBUS D+ D ID GND

15.3.3.6 Host

A host configuration is shown in Figure 15.7 (p. 220) . In this example a 5V step-up regulator is used.

If 5V is available, a power switch can be used instead, as shown in Figure 15.5 (p. 219) . The host

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USB connector which is a USB Standard-A Connector. In host mode, the minimum VBUS decoupling capacitance is 96 uF.

In this configuration, the VREGO sense circuit should be left disabled.

Figure 15.7. Host

3.0V – 3.6V

MCU VDD USB_VREGI USB_VREGO GPIO (over- current ) USB_VBUSEN OC EN V in V out 5V st ep- up USB_VBUS USB_DP USB_DM VBUS D+ D GND

15.3.4 PHY

The USB includes an internal full-speed/low-speed PHY with built-in pull-up/pull-down resistors, VBUS comparators and ID line state sensing. During suspend, the PHY enters a low-power state where only the single-ended receivers are active. The PHY is disabled by default and should be enabled by setting PHYPEN in USB_ROUTE before the USB core clock is enabled.

The PHY is powered by the internal voltage regulator output (USB_VREGO). To power the PHY directly from an external source (for example an external 3.3 V LDO), connect both USB_VREGO and USB_VREGI to the external 3.3 V supply voltage. To stop the quiescent current present with the voltage regulator enabled in this configuration, disable the the regulator by setting VREGDIS in USB_CTRL after power up. Then the regulator is effectively bypassed.

When VREGO Sense is enabled, the PHY is automatically disabled internally when the VREGO Sense output is low. This will happen if VBUS-power disappears. The application can detect this by keeping the VREGO Sense Low Interrupt enabled. Note that PHYPEN in USB_ROUTE will not be set to 0 in this case. Also, the PHY must always be disabled manually when there is no voltage applied to VREGO.

15.3.5 Voltage Regulator

The voltage regulator is used to regulate the 5 V VBUS voltage down to 3.3 V which is the operating voltage for the PHY.

A decoupling capacitor is required on USB_VREGI and USB_VREGO. Note that the USB standard requires the total capacitance on VBUS to be 1 uF minimum and 10 uF maximum for regular devices.

OTG devices can have maximum 6.5 uF capacitance on VBUS.

The voltage regulator is enabled by default and can thus be used to power the EZR32 itself. Systems not using the USB should disable the regulator by setting VREGDIS in USB_CTRL. A voltage sense circuit monitors the output voltage and can be used to detect when the voltage regulator becomes active. This sense circuit can also be used to detect when the voltage drops (typically due to the USB cable being unplugged). If regulator voltage monitoring is not required (i.e. it is known that the VREGO voltage is always present), the sense circuit should be left disabled.

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During suspend, the bias current for the regulator can be reduced if the current requirements in EM2/3 are low. The bias current in EM2/3 is controlled by BIASPROGEM23 in USB_CTRL. When EM2/3 is entered, the bias current for the regulator switches to what is specified in BIASPROGEM23 in USB_CTRL. When entering EM0 again (due to USB resume/reset signaling or any other wake-up interrupt) the regulator switches back to using the value specified in BIASPROGEM01 in USB_CTRL.

15.3.6 Interrupts and PRS

Interrupts from the core and system part share a common USB interrupt line to the CPU. The interrupt flags for the system part are grouped together in the USB_IF register. The interrupt events from the core are controlled by several core interrupt flag registers.

There are two PRS outputs from the USB: SOF and SOFSR. In Host mode, SOF toggles every time an SOF is generated and SOFSR toggles every time an SOF is successfully transmitted. In Device mode, SOF toggles every time an SOF token is received from the USB host or when an SOF token is missed at the start of frame, while SOFSR toggles only when a valid SOF token is received from the USB host.

Both PRS outputs must be synchronized in the PRS when used (i.e. it is an asynchronous PRS output).

The edge-to-pulse converter in the PRS can be used to convert the edges into pulses if needed. The PRS outputs go to 0 in EM2/3.

15.3.7 USB in EM2

During suspend and session-off EM2 should be used to save power and meet the average current requirements dictated by the USB standard. Before entering EM2, HFCORECLK USBC must be switched from 48 MHz to 32 kHz (LFXO or LFRCO). This is done using the CMU_CMD and CMU_STATUS registers. Upon EM2 wake-up, HFCORECLK USBC must be switched back to 48 MHz before accessing the core registers. The device always starts up from HFRCO so software must restart HFXO and switch from HFRCO to HFXO. The USB system clock, HFCORECLK USB , must be kept enabled during EM2. The USB system registers can be accessed immediately upon EM2 wake-up, while running from HFRCO.

Follow the steps outlined the USB Core Description when entering EM2 during suspend and session-off.

The FIFO content is lost when entering EM2. In addition, most of the USB core registers are reset and therefore need to be backed up in RAM.

EM3 cannot be used when the USB is active. However, EM3 can be used while waiting for the internal voltage regulator to be activated (i.e. VBUS becomes 5V).

15.4 USB Core Description

This section describes the programming requirements for the USB Corein Host and Device modes.

Important features/parameters for the core are: • HNP- and SRP-Capable OTG (Device and Host) • Internal DMA (Buffer Pointer Based) • Dedicated TX FIFOS for each endpoint in device mode • 6 IN/OUT endpoints in addition to endpoint 0 (in device mode) • 14 host channels (in host mode) > • Dynamic FIFO sizing • Non-Periodic Request Queue Depth: 8 • Host Mode Periodic Request Queue Depth: 8 The core has the following limitations: • Link Power Management (LPM) is not supported • ADP is not supported 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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Portions Copyright © 2010 Synopsys, Inc. Used with permission. Synopsys and DesignWare are registered trademarks of Synopsys, Inc.

15.4.1 Overview: Programming the Core

Each significant programming feature of the core is discussed in a separate section.

This chapter uses abbreviations for register names and their fields. For detailed information on registers,

see Section 15.6 (p. 325) .

The application must perform a core initialization sequence. If the cable is connected during power-up, the Current Mode of Operation bit in the Core Interrupt register (USB_GINTSTS.CURMOD) reflects the mode. The core enters Host mode when an “A” plug is connected, or Device mode when a “B” plug is connected.

This section explains the initialization of the core after power-on. The application must follow the initialization sequence irrespective of Host or Device mode operation. All core global registers are initialized according to the core’s configuration.

1. Program the following fields in the Global AHB Configuration (USB_GAHBCFG) register.

• DMA Mode bit • AHB Burst Length field • Global Interrupt Mask bit = 1 • Non-periodic TxFIFO Empty Level (can be enabled only when the core is operating in Slave mode as a host.) • Periodic TxFIFO Empty Level (can be enabled only when the core is operating in Slave mode) 2. Program the following field in the Global Interrupt Mask (USB_GINTMSK) register: • USB_GINTMSK.RXFLVLMSK = 0 3. Program the following fields in USB_GUSBCFG register.

• HNP Capable bit • SRP Capable bit • External HS PHY or Internal FS Serial PHY Selection bit • Time-Out Calibration field • USB Turnaround Time field 4. The software must unmask the following bits in the USB_GINTMSK register.

• OTG Interrupt Mask • Mode Mismatch Interrupt Mask 5. The software can read the USB_GINTSTS.CURMOD bit to determine whether the core is operating

in Host or Device mode. The software the follows either the Section 15.4.1.1 (p. 222) or Device Initialization (p. 223) sequence.

Note

The core is designed to be interrupt-driven. Polling interrupt mechanism is not recommended: this may result in undefined resolutions.

Note

In device mode, just after Power On Reset or a Soft Reset, the USB_GINTSTS.SOF bit is set to 1 for debug purposes. This status must be cleared and can be ignored.

15.4.1.1 Host Initialization

To initialize the core as host, the application must perform the following steps.

1. Program USB_GINTMSK.PRTINT to unmask.

2. Program the USB_HCFG register to select full-speed host.

3. Program the USB_HPRT.PRTPWR bit to 1. This drives VBUS on the USB.

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4. Wait for the USB_HPRT.PRTCONNDET interrupt. This indicates that a device is connect to the port.

5. Program the USB_HPRT.PRTRST bit to 1. This starts the reset process.

6. Wait at least 10 ms for the reset process to complete.

7. Program the USB_HPRT.PRTRST bit to 0.

8. Wait for the USB_HPRT.PRTENCHNG interrupt.

9. Read the USB_HPRT.PRTSPD field to get the enumerated speed.

10.Program the USB_HFIR register with a value corresponding to the selected PHY clock. At this point, the host is up and running and the port register begins to report device disconnects, etc. The port is active with SOFs occurring down the enabled port.

11.Program the RXFSIZE register to select the size of the receive FIFO.

12.Program the NPTXFSIZE register to select the size and the start address of the Non-periodic Transmit FIFO for non-periodic transactions.

13.Program the USB_HPTXFSIZ register to select the size and start address of the Periodic Transmit FIFO for periodic transactions.

To communicate with devices, the system software must initialize and enable at least one channel as

described in Device Initialization (p. 223) .

15.4.1.1.1 Host Connection

The following steps explain the host connection flow: 1. When the USB Cable is plugged to the Host port, the core triggers USB_GINTSTS.CONIDSTSCHNG

interrupt.

2. When the Host application detects USB_GINTSTS.CONIDSTSCHNG interrupt, the application can perform one of the following actions: • Turn on VBUS by setting USB_HPRT.PRTPWR = 1 or • Wait for SRP Signaling from Device to turn on VBUS.

3. The PHY indicates VBUS power-on by detecting a VBUS valid voltage level.

4. When the Host Core detects the device connection, it triggers the Host Port Interrupt (USB_GINTSTS.PRTINT) to the application.

5. When USB_GINTSTS.PRTINT is triggered, the application reads the USB_HPRT register to check if the Port Connect Detected (USB_HPRT.PRTCONNDET) bit is set or not.

15.4.1.1.2 Host Disconnection

The following steps explain the host disconnection flow: 1. When the Device is disconnected from the USB Cable (but the cable is still connected to the USB host), the Core triggers USB_GINTSTS.DISCONNINT (Disconnect Detected) interrupt.

Note

If the USB cable is disconnected from the Host port without removing the device, the core generates an additional interrupt - USB_GINTSTS.CONIDSTSCHNG (Connector ID Status Change).

2. The Host application can choose to turn off the VBUS by programming USB_HPRT.PRTPWR = 0.

15.4.1.2 Device Initialization

The application must perform the following steps to initialize the core at device on, power on, or after a mode change from Host to Device.

1. Program the following fields in USB_DCFG register.

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• Periodic Frame Interval 2. Program the USB_GINTMSK register to unmask the following interrupts.

• USB Reset • Enumeration Done • Early Suspend • USB Suspend 3. Wait for the USB_GINTSTS.USBRST interrupt, which indicates a reset has been detected on the USB and lasts for about 10 ms. On receiving this interrupt, the application must perform the steps

listed in Initialization on USB Reset (p. 257)

4. Wait for the USB_GINTSTS.ENUMDONE interrupt. This interrupt indicates the end of reset on the USB. On receiving this interrupt, the application must read the USB_DSTS register to determine the

enumeration speed and perform the steps listed in Initialization on Enumeration Completion (p. 257)

At this point, the device is ready to accept SOF packets and perform control transfers on control endpoint 0.

15.4.1.2.1 Device Connection

The device connect process varies depending on the if the VBUS is on or off when the device is connected to the USB cable.

When VBUS is on When the Device is Connected

If VBUS is on when the device is connected to the USB cable, there is no SRP from the device. The device connection flow is as follows: 1. The device triggers the USB_GINTSTS.SESSREQINT [bit 30] interrupt bit.

2. When the device application detects the USB_GINTSTS.SESSREQINT interrupt, it programs the required bits in the USB_DCFG register.

3. When the Host drives Reset, the Device triggers USB_GINTSTS.USBRST [bit 12] on detecting the Reset. The host then follows the USB 2.0 Enumeration sequence.

When VBUS is off When the Device is Connected

If VBUS is off when the device is connected to the USB cable, the device initiates SRP in OTG Revision 1.3 mode. The device connection flow is as follows: 1. The application initiates SRP by writing the Session Request bit in the OTG Control and Status register. The core perform data-line pulsing followed by VBUS pulsing.

2. The host starts a new session by turning on VBUS, indicating SRP success. The core interrupts the application by setting the Session Request Success Status Change bit in the OTG Interrupt Status register.

3. The application reads the Session Request Success bit in the OTG Control and Status register and programs the required bits in USB_DCFG register.

4. When Host drives Reset, the Device triggers USB_GINTSTS.USBRST on detecting the Reset. The host then follows the USB 2.0 Enumeration sequence.

15.4.1.2.2 Device Disconnection

The device session ends when the USB cable is disconnected or if the VBUS is switched off by the Host.

The device disconnect flow is as follows: 1. When the USB cable is unplugged or when the VBUS is switched off by the Host, the Device core trigger USB_GINTSTS.OTGINT [bit 2] interrupt bit.

2. When the device application detects USB_GINTSTS.OTGINT interrupt, it checks that the USB_GOTGINT.SESENDDET (Session End Detected) bit is set to 1.

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15.4.1.2.3 Device Soft Disconnection

The application can perform a soft disconnect by setting the Soft disconnect bit (SFTDISCON) in Device Control Register (USB_DCTL).

Send/Receive USB Transfers -> Soft disconnect->Soft reset->USB Device Enumeration

Sequence of operations: 1. The application configures the device to send or receive transfers.

2. The application sets the Soft disconnect bit (SFTDISCON) in the Device Control Register (USB_DCTL).

3. The application sets the Soft Reset bit (CSFTRST) in the Reset Register (USB_GRSTCTL).

4. Poll the USB_GRSTCTL register until the core clears the soft reset bit, which ensures the soft reset is completed properly.

5. Initialize the core according to the instructions in Device Initialization (p. 223) .

Suspend-> Soft disconnect->Soft reset->USB Device Enumeration

Sequence of operations: 1. The core detects a USB suspend and generates a Suspend Detected interrupt.

2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register, the core puts the PHY in suspend mode, and the PHY clock stops.

3. The application clears the Stop PHY Clock bit in the Power and Clock Gating Control register, and waits for the PHY clock to come back. The core takes the PHY back to normal mode, and the PHY clock comes back.

4. The application sets the Soft disconnect bit (SFTDISCON) in Device Control Register (USB_DCTL).

5. The application sets the Soft Reset bit (CSFTRST) in the Reset Register (USB_GRSTCTL).

6. Poll the USB_GRSTCTL register until the core clears the soft reset bit, which ensures the soft reset is completed properly.

7. Initialize the core according to the instructions in Device Initialization (p. 223) .

15.4.2 Modes of operation

• Overview: DMA/Slave modes (p. 225) • DMA Mode (p. 225)

• Slave Mode (p. 226)

15.4.2.1 Overview: DMA/Slave modes

The application can operate the core in either of two modes:

• In DMA Mode (p. 225) - The core fetches the data to be transmitted or updates the received data

on the AHB.

• In Slave Mode (p. 226) — The application initiates the data transfers for data fetch and store.

15.4.2.2 DMA Mode

In DMA Mode, the OTG host uses the AHB master Interface for transmit packet data fetch (AHB to USB) and receive data update (USB to AHB). The AHB master uses the programmed DMA address (USB_HCx_DMAADDR register in host mode and USB_DIEPx_DMAADDR/USB_DOEPx_DMAADDR register in device mode) to access the data buffers.

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15.4.2.2.1 Transfer-Level Operation

In DMA mode, the application is interrupted only after the programmed transfer size is transmitted or received (provided the core detects no NAK/Timeout/Error response in Host mode, or Timeout/CRC Error in Device mode). The application must handle all transaction errors. In Device mode, all the USB errors are handled by the core itself.

15.4.2.2.2 Transaction-Level Operation

This mode is similar to transfer-level operation with the programmed transfer size equal to one packet size (either maximum packet size, or a short packet size).

15.4.2.3 Slave Mode

In Slave mode, the application can operate the core either in transaction-level (packet-level) operation or in pipelined transaction-level operation.

15.4.2.3.1 Transaction-Level Operation

The application handles one data packet at a time per channel/endpoint in transaction-level operations.

Based on the handshake response received on the USB, the application determines whether to retry the transaction or proceed with the next, until the end of the transfer. The application is interrupted on completion of every packet. The application performs transaction-level operations for a channel/endpoint

for a transmission (host: OUT/device: IN) or reception (host: IN/device: OUT) as shown in Figure 15.8 (p.

227) and Figure 15.9 (p. 227) .

Host Mode

For an OUT transaction, the application enables the channel and writes the data packet into the corresponding (Periodic or Non-periodic) transmit FIFO. The core automatically writes the channel number into the corresponding (Periodic or Non-periodic) Request Queue, along with the last DWORD write of the packet. For an IN transaction, the application enables the channel and the core automatically writes the channel number into the corresponding Request queue. The application must wait for the packet received interrupt, then empty the packet from the receive FIFO.

Device Mode

For an IN transaction, the application enables the endpoint, writes the data packet into the corresponding transmit FIFO, and waits for the packet completion interrupt from the core. For an OUT transaction, the application enables the endpoint, waits for the packet received interrupt from the core, then empties the packet from the receive FIFO.

Note

The application has to finish writing one complete packet before switching to a different channel/endpoint FIFO. Violating this rule results in an error.

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Start Set up the channel/endpoint Write 1 packet to the Transmit FIFO Rewrite packet to the Transmit FIFO Get interrupt?

Yes Get channel/endpoint interrupt status No No Yes Retry required?

No Transfer complete?

Yes Done

Figure 15.9. Receive Transaction-Level Operation in Slave Mode

St art Set up t he Channel / endpoint Yes RXFLVL or Ch/EP int errupt ?

No Yes Read Receive St at us Queue No Ret ry required ?

No Read t he packet from t he Receive FIFO Transfer com plet e?

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15.4.2.3.2 Pipelined Transaction-Level Operation

The application can pipeline more than one transaction (IN or OUT) with pipelined transaction-level operation, which is analogous to Transfer mode in DMA mode. In pipelined transaction-level operation, the application can program the core to perform multiple transactions. The advantage of this mode compared to transaction-level operation is that the application is not interrupted on a packet basis.

15.4.2.3.2.1 Host mode

For an OUT transaction, the application sets up a transfer and enables the channel. The application can write multiple packets back-to-back for the same channel into the transmit FIFO, based on the space availability. It can also pipeline OUT transactions for multiple channels by writing into the HCHARn register, followed by a packet write to that channel. The core writes the channel number, along with the last DWORD write for the packet, into the Request queue and schedules transactions on the USB in the same order.

For an IN transaction, the application sets up a transfer and enables the channel, and the core writes the channel number into the Request queue. The application can schedule IN transactions on multiple channels, provided space is available in the Request queue. The core initiates an IN token on the USB only when there is enough space to receive at least of one maximum-packet-size packet of the channel in the top of the Request queue.

15.4.2.3.2.2 Device mode

For an IN transaction, the application sets up a transfer and enables the endpoint. The application can write multiple packets back-to-back for the same endpoint into the transmit FIFO, based on available space. It can also pipeline IN transactions for multiple channels by writing into the USB_DIEPx_CTL register followed by a packet write to that endpoint. The core writes the endpoint number, along with the last DWORD write for the packet into the Request queue. The core transmits the data in the transmit FIFO when an IN token is received on the USB.

For an OUT transaction, the application sets up a transfer and enables the endpoint. The core receives the OUT data into the receive FIFO, when it has available space. As the packets are received into the FIFO, the application must empty data from it.

From this point on in this chapter, the terms “Pipelined Transaction mode” and “Transfer mode” are used interchangeably.

15.4.3 Host Programming Model

Before you program the Host, read Overview: Programming the Core (p. 222) and Modes of operation (p. 225) .

This section discusses the following topics:

• Channel Initialization (p. 228)

• Halting a Channel (p. 229)

• Zero-Length Packets (p. 230) • Handling Babble Conditions (p. 230) • Handling Disconnects (p. 230) • Host Programming Operations (p. 230)

• Writing the Transmit FIFO in Slave Mode (p. 231)

• Reading the Receive FIFO in Slave Mode (p. 232)

15.4.3.1 Channel Initialization

The application must initialize one or more channels before it can communicate with connected devices.

To initialize and enable a channel, the application must perform the following steps.

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1. Program the USB_GINTMSK register to unmask the following: 2. Channel Interrupt • Non-periodic Transmit FIFO Empty for OUT transactions (applicable for Slave mode that operates in pipelined transaction-level with the Packet Count field programmed with more than one).

• Non-periodic Transmit FIFO Half-Empty for OUT transactions (applicable for Slave mode that operates in pipelined transaction-level with the Packet Count field programmed with more than one).

3. Program the USB_USB_HAINTMSK register to unmask the selected channels’ interrupts.

4. Program the HCINTMSK register to unmask the transaction-related interrupts of interest given in the Host Channel Interrupt register.

5. Program the selected channel’s USB_HCx_TSIZ register.

Program the register with the total transfer size, in bytes, and the expected number of packets, including short packets. The application must program the PID field with the initial data PID (to be used on the first OUT transaction or to be expected from the first IN transaction).

6. Program the selected channels’ USB_HCx_DMAADDR register(s) with the buffer start address (DMA mode only).

7. Program the USB_HCx_CHAR register of the selected channel with the device’s endpoint characteristics, such as type, speed, direction, and so forth. (The channel can be enabled by setting the Channel Enable bit to 1 only when the application is ready to transmit or receive any packet).

Repeat the above steps for other channels.

Note

De-allocate channel means after the transfer has completed, the channel is disabled. When the application is ready to start the next transfer, the application re-initializes the channel by following these steps.

15.4.3.2 Halting a Channel

The application can disable any channel by programming the USB_HCx_CHAR register with the USB_HCx_CHAR.CHDIS and USB_HCx_CHAR.CHENA bits set to 1. This enables the host to flush the posted requests (if any) and generates a Channel Halted interrupt. The application must wait for the USB_HCx_INT.CHHLTD interrupt before reallocating the channel for other transactions. The host does not interrupt the transaction that has been already started on USB.

In Slave mode operation, before disabling a channel, the application must ensure that there is at least one free space available in the Non-periodic Request Queue (when disabling a non-periodic channel) or the Periodic Request Queue (when disabling a periodic channel). The application can simply flush the posted requests when the Request queue is full (before disabling the channel), by programming the USB_HCx_CHAR register with the USB_HCx_CHAR.CHDIS bit set to 1, and the USB_HCx_CHAR.CHENA bit reset to 0.

The core generates a RXFLVL interrupt when there is an entry in the queue. The application must read/ pop the USB_GRXSTSP register to generate the Channel Halted interrupt.

To disable a channel in DMA mode operation, the application need not check for space in the Request queue. The host checks for space in which to write the Disable request on the disabled channel’s turn during arbitration. Meanwhile, all posted requests are dropped from the Request queue when the USB_HCx_CHAR.CHDIS bit is set to 1.

The application is expected to disable a channel under any of the following conditions: 1. When a USB_HCx_INT.XFERCOMPL interrupt is received during a non-periodic IN transfer or high bandwidth interrupt IN transfer (Slave mode only) 2. When a USB_HCx_INT.STALL, USB_HCx_INT.XACTERR, USB_HCx_INT.BBLERR, or USB_HCx_INT.DATATGLERR interrupt is received for an IN or OUT channel (Slave mode only).

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For high-bandwidth interrupt INs in Slave mode, once the application has received a DATATGLERR interrupt it must disable the channel and wait for a Channel Halted interrupt. The application must be able to receive other interrupts (DATATGLERR, NAK, Data, XACTERR, BBLERR) for the same channel before receiving the halt.

3. When a USB_GINTSTS.DISCONNINT (Disconnect Device) interrupt is received. The application must check for the USB_HPRT.PRTCONNSTS, because when the device directly connected to the host is disconnected, USB_HPRT.PRTCONNSTS is reset. The software must issue a soft reset to ensure that all channels are cleared. When the device is reconnected, the host must issue a USB Reset.

4. When the application aborts a transfer before normal completion (Slave and DMA modes).

Note

In DMA mode, keep the following guideline in mind: • Channel disable must not be programmed for periodic channels. At the end of the next frame (in the worst case), the core generates a channel halted and disables the channel automatically.

15.4.3.3 Sending a Zero-Length Packet in Slave/DMA Modes

To send a zero-length data packet, the application must initialize an OUT channel as follows.

1. Program the USB_HCx_TSIZ register of the selected channel with a correct PID, XFERSIZE = 0, and PKTCNT = 1.

2. Program the USB_HCx_CHAR register of the selected channel with CHENA = 1 and the device’s endpoint characteristics, such as type, speed, and direction.

The application must treat a zero-length data packet as a separate transfer, and cannot combine it with a non-zero-length transfer.

15.4.3.4 Handling Babble Conditions

The core handles two cases of babble: packet babble and port babble. Packet babble occurs if the device sends more data than the maximum packet size for the channel. Port babble occurs if the core continues to receive data from the device at EOF2 (the end of frame 2, which is very close to SOF).

When the core detects a packet babble, it stops writing data into the Rx buffer and waits for the end of packet (EOP). When it detects an EOP, it flushes already-written data in the Rx buffer and generates a Babble interrupt to the application.

When detects a port babble, it flushes the RxFIFO and disables the port. The core then generates a Port Disabled Interrupt (USB_GINTSTS.PRTINT, USB_HPRT.PRTENCHNG). On receiving this interrupt, the application must determine that this is not due to an overcurrent condition (another cause of the Port Disabled interrupt) by checking USB_HPRT.PRTOVRCURRACT, then perform a soft reset. The core does not send any more tokens after it has detected a port babble condition.

15.4.3.5 Handling Disconnects

If the device is disconnected suddenly, a USB_GINTSTS.DISCONNINT interrupt is generated.

When the application receives this interrupt, it must issue a soft reset by programming the USB_GRSTCTL.CSFTRST bit.

15.4.3.6 Host Programming Operations

Table 15.1 (p. 231) provides links to the programming sequence for the different types of USB

transactions.

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Mode Control Slave IN DMA

Bulk and Control IN Transactions in Slave Mode (p. 235)

Bulk and Control IN Transactions in DMA Mode (p. 241)

Bulk Slave DMA

Bulk and Control IN Transactions in Slave Mode (p. 235)

Bulk and Control IN Transactions in DMA Mode (p. 241)

Interrupt Slave DMA

Interrupt IN Transactions in Slave Mode (p. 245)

Interrupt IN Transactions in DMA Mode (p. 249)

Isochronous Slave DMA OUT/SETUP

Bulk and Control OUT/SETUP Transactions in Slave Mode (p. 233)

Bulk and Control OUT/SETUP Transactions in DMA Mode (p. 237)

Bulk and Control OUT/SETUP Transactions in Slave Mode (p. 233)

Bulk and Control OUT/SETUP Transactions in DMA Mode (p. 237)

Interrupt OUT Transactions in Slave Mode (p. 243)

Interrupt OUT Transactions in DMA Mode (p. 247)

Isochronous IN Transactions in Slave Mode (p. 253)

Isochronous IN Transactions in DMA Mode (p. 255)

Isochronous OUT Transactions in Slave Mode (p. 251)

Isochronous OUT Transactions in DMA Mode (p. 254)

15.4.3.6.1 Writing the Transmit FIFO in Slave Mode

Figure 15.10 (p. 232) shows the flow diagram for writing to the transmit FIFO in Slave mode. The host

automatically writes an entry (OUT request) to the Periodic/Non-periodic Request Queue, along with the last DWORD write of a packet. The application must ensure that at least one free space is available in the Periodic/Non-periodic Request Queue before starting to write to the transmit FIFO. The application must always write to the transmit FIFO in DWORDs. If the packet size is non-DWORD aligned, the application must use padding. The host determines the actual packet size based on the programmed maximum packet size and transfer size.

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...the world's most energy friendly wireless MCUs Figure 15.10. Transmit FIFO Write Task in Slave Mode

St art Read USB_GNPTXSTS / USB_HPTXFSIZ regist ers for available FIFO and Queue spaces USB_GAHBCFG Wait for .

NPTXFEMPLVL or USB_GAHBCFG .

PTXFEMPLVL int errupt No 1 or LPS FIFO space available?

Yes Writ e dat a t o Transm it FIFO Yes More packet s t o send?

No Done MPS : Last Packet Size

15.4.3.6.2 Reading the Receive FIFO in Slave Mode

Figure 15.11 (p. 232) shows the flow diagram for reading the receive FIFO in Slave mode. The

application must ignore all packet statuses other than IN Data Packet (0b0010).

Figure 15.11. Receive FIFO Read Task in Slave Mode

St art Unm ask RXFLVL int errupt Read t he received packet from t he Receive FIFO No RXFLVL Int errupt ?

Yes Mask RXFLVL int errupt Read USB_GRXSTSP PKTSTS = 0b0010?

Yes Yes No Unm ask RXFLVL int errupt No

15.4.3.6.3 Control Transactions in Slave Mode

Setup, Data, and Status stages of a control transfer must be performed as three separate transfers.

Setup- Data- or Status-stage OUT transactions are performed similarly to the bulk OUT transactions

explained in Bulk and Control OUT/SETUP Transactions in Slave Mode (p. 233) . Data- or Status-

stage IN transactions are performed similarly to the bulk IN transactions explained in Bulk and Control IN Transactions in Slave Mode (p. 235) For all three stages, the application is expected to set the

USB_HC1_CHAR.EPTYPE field to Control. During the Setup stage, the application is expected to set the USB_HC1_TSIZ.PID field to SETUP.

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15.4.3.6.4 Bulk and Control OUT/SETUP Transactions in Slave Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the connected device, it must

initialize a channel as described in Channel Initialization (p. 228) . See Figure 15.10 (p. 232) and Figure 15.11 (p. 232) for Read or Write data to and from the FIFO in Slave mode.

A typical bulk or control OUT/SETUP pipelined transaction-level operation in Slave mode is shown in

Figure 15.12 (p. 234) . See channel 1 (ch_1). Two bulk OUT packets are transmitted. A control SETUP

transaction operates the same way but has only one packet. The assumptions are: • The application is attempting to send two maximum-packet-size packets (transfer size = 1,024 bytes).

• The Non-periodic Transmit FIFO can hold two packets (128 bytes for FS).

• The Non-periodic Request Queue depth = 4.

15.4.3.6.4.1 Normal Bulk and Control OUT/SETUP Operations

The sequence of operations in Figure 15.12 (p. 234) (channel 1) is as follows:

1. Initialize channel 1 as explained in Channel Initialization (p. 228) .

2. Write the first packet for channel 1.

3. Along with the last DWORD write, the core writes an entry to the Non-periodic Request Queue.

4. As soon as the non-periodic queue becomes non-empty, the core attempts to send an OUT token in the current frame.

5. Write the second (last) packet for channel 1.

6. The core generates the XFERCOMPL interrupt as soon as the last transaction is completed successfully.

7. In response to the XFERCOMPL interrupt, de-allocate the channel for other transfers.

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...the world's most energy friendly wireless MCUs Figure 15.12. Normal Bulk/Control OUT/SETUP and Bulk/Control IN Transactions in Slave Mode

AHB Host USB Device

init_ reg( ch_2) set_ch_en (ch_2) set_ch_en (ch_2)

1 1 2 2 5 Application

init_ reg(ch_1) writ e_t x_fifo ( ch_1) writ e_t x_fifo ( ch_1) 1 MPS 1 MPS

3

ch_1 ch_2 ch_1 ch_2

4 Non- Periodic Request Queue

Assum e t hat t his queue can hold 4 ent ries.

OUT D AT A0 MPS

3

set_ch_en (ch_2) ACK IN

4

D AT A0

5

read_rx_st s read_rx_fifo set_ch_en (ch_2) RXFLVL int errupt 1 MPS ch_1 ch_2 ch_2 ch_2 ACK O UT D AT A1 MPS

7

De- allocat e ( ch_1) XFERCOMPL int errupt

6

ACK IN D AT A1 read_rx_st sre ad_rx_fifo read_rx_st s Disable (ch_2) read_rx_st s De- allocat e (ch_2)

7 9 1 1 1 3

RXFLVL int errupt 1 MPS RXFLVL int errupt XFERCOMPL int errupt RXFLVL int errupt CHHLTD int errupt

6 8

ch_2

1 0 1 2

ACK

15.4.3.6.4.2 Handling Interrupts

The channel-specific interrupt service routine for bulk and control OUT/SETUP transactions in Slave mode is shown in the following code samples.

Interrupt Service Routine for Bulk/Control OUT/SETUP Transactions in Slave Mode Bulk/Control OUT/SETUP

Unmask (NAK/XACTERR/STALL/XFERCOMPL) if (XFERCOMPL) { Reset Error Count Mask ACK De-allocate Channel } else if (STALL) 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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{ Transfer Done = 1 Unmask CHHLTD Disable Channel } else if (NAK or XACTERR) { Rewind Buffer Pointers Unmask CHHLTD Disable Channel if (XACTERR) { Increment Error Count Unmask ACK } else { Reset Error Count } } else if (CHHLTD) { Mask CHHLTD if (Transfer Done or (Error_count == 3)) { De-allocate Channel } else { Re-initialize Channel } } else if (ACK) { Reset Error Count Mask ACK } The application is expected to write the data packets into the transmit FIFO when space is available in the transmit FIFO and the Request queue. The application can make use of USB_GINTSTS.NPTXFEMP

interrupt to find the transmit FIFO space.

The application is expected to write the requests as and when the Request queue space is available and until the XFERCOMPL interrupt is received.

15.4.3.6.5 Bulk and Control IN Transactions in Slave Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the connected device, it must

initialize a channel as described in Channel Initialization (p. 228) . See Figure 15.10 (p. 232) and Figure 15.11 (p. 232) for read or write data to and from the FIFO in Slave mode.

A typical bulk or control IN pipelined transaction-level operation in Slave mode is shown in

Figure 15.12 (p. 234) . See channel 2 (ch_2). The assumptions are:

1. The application is attempting to receive two maximum-sized packets (transfer size = 1,024 bytes).

2. The receive FIFO can contain at least one maximum-packet-size packet and two status DWORDs per packet (72 bytes for FS).

3. The Non-periodic Request Queue depth = 4.

15.4.3.6.5.1 Normal Bulk and Control IN Operations

The sequence of operations in Figure 15.12 (p. 234) is as follows:

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1. Initialize channel 2 as explained in Channel Initialization (p. 228) .

2. Set the USB_HC2_CHAR.CHENA bit to write an IN request to the Non-periodic Request Queue.

3. The core attempts to send an IN token after completing the current OUT transaction.

4. The core generates an RXFLVL interrupt as soon as the received packet is written to the receive FIFO.

5. In response to the RXFLVL interrupt, mask the RXFLVL interrupt and read the received packet status to determine the number of bytes received, then read the receive FIFO accordingly. Following this, unmask the RXFLVL interrupt.

6. The core generates the RXFLVL interrupt for the transfer completion status entry in the receive FIFO.

7. The application must read and ignore the receive packet status when the receive packet status is not an IN data packet (USB_GRXSTSR.PKTSTS != 0b0010).

8. The core generates the XFERCOMPL interrupt as soon as the receive packet status is read.

9. In response to the XFERCOMPL interrupt, disable the channel (see Halting a Channel (p. 229) )

and stop writing the USB_HC2_CHAR register for further requests. The core writes a channel disable request to the non-periodic request queue as soon as the USB_HC2_CHAR register is written.

10.The core generates the RXFLVL interrupt as soon as the halt status is written to the receive FIFO.

11.Read and ignore the receive packet status.

12.The core generates a CHHLTD interrupt as soon as the halt status is popped from the receive FIFO.

13.In response to the CHHLTD interrupt, de-allocate the channel for other transfers.

Note

For Bulk/Control IN transfers, the application must write the requests when the Request queue space is available, and until the XFERCOMPL interrupt is received.

15.4.3.6.5.2 Handling Interrupts

The channel-specific interrupt service routine for bulk and control IN transactions in Slave mode is shown in the following code samples.

Interrupt Service Routine for Bulk/Control IN Transactions in Slave Mode

Unmask (XACTERR/XFERCOMPL/BBLERR/STALL/DATATGLERR) if (XFERCOMPL) { Reset Error Count Unmask CHHLTD Disable Channel Reset Error Count Mask ACK } else if (XACTERR or BBLERR or STALL) { Unmask CHHLTD Disable Channel if (XACTERR) { Increment Error Count Unmask ACK } } else if (CHHLTD) { Mask CHHLTD if (Transfer Done or (Error_count == 3)) { De-allocate Channel } else { Re-initialize Channel } 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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} else if (ACK) { Reset Error Count Mask ACK } else if (DATATGLERR) { Reset Error Count }

15.4.3.6.6 Control Transactions in DMA Mode

Setup, Data, and Status stages of a control transfer must be performed as three separate transfers.

Setup- and Data- or Status-stage OUT transactions are performed similarly to the bulk OUT transactions

explained in Bulk and Control OUT/SETUP Transactions in DMA Mode (p. 237) . Data- or Status-

stage IN transactions are performed similarly to the bulk IN transactions explained in Bulk and Control IN Transactions in DMA Mode (p. 241) . For all three stages, the application is expected to set the

USB_HC1_CHAR.EPTYPE field to Control. During the Setup stage, the application is expected to set the USB_HC1_TSIZ.PID field to SETUP.

15.4.3.6.7 Bulk and Control OUT/SETUP Transactions in DMA Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 228) .

This section discusses the following topics:

• Overview (p. 237) • Normal Bulk and Control OUT/SETUP Operations (p. 237) • NAK Handling with DMA (p. 237)

• Handling Interrupts (p. 239)

15.4.3.6.7.1 Overview

• The application is attempting to send two maximum-packet-size packets (transfer size = 1,024 bytes).

• The Non-periodic Transmit FIFO can hold two packets (128 bytes for FS).

• The Non-periodic Request Queue depth = 4.

15.4.3.6.7.2 Normal Bulk and Control OUT/SETUP Operations

The sequence of operations in Figure 15.12 (p. 234) is as follows:

1. Initialize and enable channel 1 as explained in Channel Initialization (p. 228) .

2. The host starts fetching the first packet as soon as the channel is enabled. For DMA mode, the host uses the programmed DMA address to fetch the packet.

3. After fetching the last DWORD of the second (last) packet, the host masks channel 1 internally for further arbitration.

4. The host generates a CHHLTD interrupt as soon as the last packet is sent.

5. In response to the CHHLTD interrupt, de-allocate the channel for other transfers.

The channel-specific interrupt service routine for bulk and control OUT/SETUP transactions in DMA

mode is shown in Handling Interrupts (p. 239) .

15.4.3.6.7.3 NAK Handling with DMA

1. The Host sends a Bulk OUT Transaction.

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2. The Device responds with NAK.

3. If the application has unmasked NAK, the core generates the corresponding interrupt(s) to the application.

The application is not required to service these interrupts, since the core takes care of rewinding of buffer pointers and re-initializing the Channel without application intervention.

4. When the Device returns an ACK, the core continues with the transfer.

Optionally, the application can utilize these interrupts. If utilized by the application: • The NAK interrupt is masked by the application.

• The core does not generate a separate interrupt when NAK is received by the Host functionality.

Application Programming Flow

1. The application programs a channel to do a bulk transfer for a particular data size in each transaction.

• Packet Data size can be up to 512 KBytes • Zero-length data must be programmed as a separate transaction.

2. Program the transfer size register with: • Transfer size • Packet Count 3. Program the DMA address.

4. Program the USB_HCx_CHAR to enable the channel.

5. The Interrupt handling by the application is as depicted in the flow diagram.

Note

The NAK interrupts are still generated internally. The application can mask off these interrupts from reaching it. The application can use these interrupts optionally.

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...the world's most energy friendly wireless MCUs Figure 15.13. Normal Bulk/Control OUT/SETUP and Bulk/Control IN Transactions in DMA Mode

AHB Host USB Device

init_ reg( ch_2)

1 1 Application

init_ reg( ch_1) 1 MPS

2 Non- Periodic Request Queue

Assum e t hat t his queue can hold 4 ent ries.

1 MPS

2

ch_1 ch_2 ch_1 ch_2 OUT D ATA0 M PS

3

ACK IN

5

De- allocat e (ch_1) 1 MPS CHHLTD int errupt

3 5

ch_1 ch_2 ch_2 ch_2

4

D ATA0 ACK OUT D ATA1 M PS ACK IN D ATA1

4

1 MPS ACK ch_2

6 7

CHHLTD int errupt De- allocat e (ch_2)

8 15.4.3.6.7.4 Handling Interrupts

The channel-specific interrupt service routine for bulk and control OUT/SETUP transactions in DMA mode is shown in the following code samples.

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...the world's most energy friendly wireless MCUs Figure 15.14. Interrupt Service Routine for Bulk/Control OUT Transaction in DMA Mode

St art Unm asked t he required USB_HAINTMSK and USB_HCx _INTMSK st at us bit s Int errupt ?

No yes Read USB_HAINT t o det erm ine t he channel which caused t he Int errupt and read t he corresponding USB_HCx _INT No Service based on t he ot her int errupt st at us bit s nam ely: AHBERR, FRMOVRERR, BBLERR and DATATGLERR USB_HCx _INT.

CHHLTD = 1 ?

No USB_HCx _INT.

ACK = 1?

Yes, USB_HCx _INT.STALL = 1 or USB_HCx _INT.XFERCOMPL = 1 Yes , USB_HCx _INT.XACTERR = 1 Yes Reset Err_cnt No USB_HCx _INT.NAK = 1 / USB_HCx _INT.ACK = 1 Err_cnt = Err_cnt + 1 Yes 1. Err_cnt = 1 2. Re- init ialize channel 3. Reprogram Buffer point ers 1. Reset Err_cnt 2. Deallocat e channel 1. Reprogram Buffer point ers 2. Re- init ialize Channel No Err_cnt = = 3 ?

Yes Deallocat e Channel

In Figure 15.14 (p. 240) that the Interrupt Service Routine is not required to handle NAK responses.

This is the difference of proposed flow with respect to current flow. Similar flow is applicable for Control flow also.

The NAK status bits in USB_HCx_INT registers are updated. The application can unmask these interrupts when it requires the core to generate an interrupt for NAK. The NAK status is updated because during Xact_err scenarios, this status provides a means for the application to determine whether the Xact_err occurred three times consecutively or there were NAK responses in between two Xact_err.

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must read the NAK/ACK along with the xact_err. If NAK/ACK is not set, the Xact_err count must be incremented otherwise application must initialize the Xact_err count to 1.

Bulk/Control OUT/SETUP

Unmask (CHHLTD) if (CHHLTD) { if (XFERCOMPL or STALL) { Reset Error Count (Error_count=1) Mask ACK De-allocate Channel } else if (XACTERR) { if (NAK/ACK) { Error_count = 1 Re-initialize Channel Rewind Buffer Pointers } else { Error_count = Error_count + 1 if (Error_count == 3) { De allocate channel } else { Re-initialize Channel Rewind Buffer Pointers } } } } else if (ACK) { Reset Error Count (Error_count=1) Mask ACK } As soon as the channel is enabled, the core attempts to fetch and write data packets, in multiples of the maximum packet size, to the transmit FIFO when space is available in the transmit FIFO and the Request queue. The core stops fetching as soon as the last packet is fetched.

15.4.3.6.8 Bulk and Control IN Transactions in DMA Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 228) .

A typical bulk or control IN operation in DMA mode is shown in Figure 15.13 (p. 239) . See channel

2 (ch_2).

The assumptions are:

1. The application is attempting to receive two maximum-packet-size packets (transfer size = 1,024 bytes).

2. The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDs per packet (72 bytes for FS).

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3. The Non-periodic Request Queue depth = 4.

15.4.3.6.8.1 Normal Bulk and Control IN Operations

The sequence of operations in Figure 15.13 (p. 239) is as follows:

1. Initialize and enable channel 2 as explained in Channel Initialization (p. 228) .

2. The host writes an IN request to the Request queue as soon as channel 2 receives the grant from the arbiter. (Arbitration is performed in a round-robin fashion, with fairness.).

3. The host starts writing the received data to the system memory as soon as the last byte is received with no errors.

4. When the last packet is received, the host sets an internal flag to remove any extra IN requests from the Request queue.

5. The host flushes the extra requests.

6. The final request to disable channel 2 is written to the Request queue. At this point, channel 2 is internally masked for further arbitration.

7. The host generates the CHHLTD interrupt as soon as the disable request comes to the top of the queue.

8. In response to the CHHLTD interrupt, de-allocate the channel for other transfers.

15.4.3.6.8.2 Handling Interrupts

The channel-specific interrupt service routine for bulk and control IN transactions in DMA mode is shown in the following flow:

Interrupt Service Routines for Bulk/Control Bulk/Control IN Transactions in DMA Mode Bulk/Control IN

Unmask (CHHLTD) if (CHHLTD) { if (XFERCOMPL or STALL or BBLERR) { Reset Error Count Mask ACK De-allocate Channel } else if (XACTERR) { if (Error_count == 2) { De-allocate Channel } else { Unmask ACK Unmask NAK Unmask DATATGLERR Increment Error Count Re-initialize Channel } } } else if (ACK or NAK or DATATGLERR) { Reset Error Count Mask ACK Mask NAK Mask DATATGLERR } 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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15.4.3.6.9 Interrupt OUT Transactions in Slave Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the connected device, it must

initialize a channel as described in Channel Initialization (p. 228) . See Figure 15.10 (p. 232) and Figure 15.11 (p. 232) for read or write data to and from the FIFO in Slave mode.

A typical interrupt OUT operation in Slave mode is shown in Figure 15.15 (p. 244) . See channel 1

(ch_1). The assumptions are: • The application is attempting to send one packet in every frame (up to 1 maximum packet size), starting with the odd frame (transfer size = 1,024 bytes).

• The Periodic Transmit FIFO can hold one packet.

• Periodic Request Queue depth = 4.

15.4.3.6.9.1 Normal Interrupt OUT Operation

The sequence of operations in Figure 15.15 (p. 244) is as follows:

1. Initialize and enable channel 1 as explained in Channel Initialization (p. 228) . The application must

set the USB_HC1_CHAR.ODDFRM bit.

2. Write the first packet for channel 1. For a high-bandwidth interrupt transfer, the application must write the subsequent packets up to MC (maximum number of packets to be transmitted in the next frame times before switching to another channel).

3. Along with the last DWORD write of each packet, the host writes an entry to the Periodic Request Queue.

4. The host attempts to send an OUT token in the next (odd) frame.

5. The host generates an XFERCOMPL interrupt as soon as the last packet is transmitted successfully.

6. In response to the XFERCOMPL interrupt, reinitialize the channel for the next transfer.

15.4.3.6.9.2 Handling Interrupts

The channel-specific interrupt service routine for Interrupt OUT transactions in Slave mode is shown in the following flow: 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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...the world's most energy friendly wireless MCUs Figure 15.15. Normal Interrupt OUT/IN Transactions in Slave Mode

AHB Host USB Device

init_ reg(ch_2) set_ch_en ( ch_2)

1 1 2 2 Application

init_ reg( ch_1) writ e_t x_fifo (ch_1) 1 MPS

3

ch_1 ch_2

4

Periodic Request Queue Assum e t hat t his queue can hold

3

OUT D ATA0 M PS Odd fram e

5 6

init_ reg( ch_1) writ e_t x_fifo (ch_1) XFERCOMPL int errupt

5 4

ACK IN read_rx_st s read_rx_fifo read_rx_st s

7 6

1 MPS RXFLVL int errupt 1 MPS RXFLVL int errupt XFERCOMPL int errupt

8

ch_1 ch_2 D ATA0 ACK init_ reg(ch_2) set_ch_en ( ch_2)

9

Even fram e init_ reg( ch_1) writ e_t x_fifo (ch_1) XFERCOMPL int errupt 1 MPS OUT D ATA1 MPS ACK IN D ATA1

Interrupt Service Routine for Interrupt OUT Transactions in Slave Mode Interrupt OUT

Unmask (NAK/XACTERR/STALL/XFERCOMPL/FRMOVRUN) if (XFERCOMPL) { Reset Error Count Mask ACK De-allocate Channel } else if (STALL or FRMOVRUN) { Mask ACK Unmask CHHLTD Disable Channel if (STALL) { Transfer Done = 1 } 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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} else if (NAK or XACTERR) { Rewind Buffer Pointers Reset Error Count Mask ACK Unmask CHHLTD Disable Channel } else if (CHHLTD) { Mask CHHLTD if (Transfer Done or (Error_count == 3)) { De-allocate Channel } else { Re-initialize Channel (in next b_interval - 1 Frame) } } else if (ACK) { Reset Error Count Mask ACK } The application is expected to write the data packets into the transmit FIFO when the space is available in the transmit FIFO and the Request queue up to the count specified in the MC field before switching to another channel. The application uses the USB_GINTSTS.NPTXFEMP interrupt to find the transmit FIFO space.

15.4.3.6.10 Interrupt IN Transactions in Slave Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 228) . See Transmit FIFO Write Task in Slave Mode

and Receive FIFO Read Task in Slave Mode for read or write data to and from the FIFO in Slave mode.

A typical interrupt-IN operation in Slave mode is shown in Figure 15.15 (p. 244) . See channel 2 (ch_2).

The assumptions are: 1. The application is attempting to receive one packet (up to 1 maximum packet size) in every frame, starting with odd. (transfer size = 1,024 bytes).

2. The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDs per packet (1,031 bytes for FS).

3. Periodic Request Queue depth = 4.

15.4.3.6.10.1 Normal Interrupt IN Operation

The sequence of operations in Figure 15.15 (p. 244) (channel 2) is as follows:

1. Initialize channel 2 as explained in Channel Initialization (p. 228) . The application must set the

USB_HC2_CHAR.ODDFRM bit.

2. Set the USB_HC2_CHAR.CHENA bit to write an IN request to the Periodic Request Queue. For a high-bandwidth interrupt transfer, the application must write the USB_HC2_CHAR register MC (maximum number of expected packets in the next frame) times before switching to another channel.

3. The host writes an IN request to the Periodic Request Queue for each USB_HC2_CHAR register write with a CHENA bit set.

4. The host attempts to send an IN token in the next (odd) frame.

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5. As soon as the IN packet is received and written to the receive FIFO, the host generates an RXFLVL interrupt.

6. In response to the RXFLVL interrupt, read the received packet status to determine the number of bytes received, then read the receive FIFO accordingly. The application must mask the RXFLVL interrupt before reading the receive FIFO, and unmask after reading the entire packet.

7. The core generates the RXFLVL interrupt for the transfer completion status entry in the receive FIFO.

The application must read and ignore the receive packet status when the receive packet status is not an IN data packet (USB_GRXSTSR.PKTSTS != 0b0010).

8. The core generates an XFERCOMPL interrupt as soon as the receive packet status is read.

9. In response to the XFERCOMPL interrupt, read the USB_HC2_TSIZ.PKTCNT field. If

USB_HC2_TSIZ.PKTCNT != 0, disable the channel (as explained in Halting a Channel (p. 229)

) before re-initializing the channel for the next transfer, if any). If USB_HC2_TSIZ.PKTCNT == 0, reinitialize the channel for the next transfer. This time, the application must reset the USB_HC2_CHAR.ODDFRM bit.

15.4.3.6.10.2 Handling Interrupts

The channel-specific interrupt service routine for an interrupt IN transaction in Slave mode is a follows.

Interrupt IN

Unmask (NAK/XACTERR/XFERCOMPL/BBLERR/STALL/FRMOVRUN/DATATGLERR) if (XFERCOMPL) { Reset Error Count Mask ACK if (USB_HCx_TSIZ.PKTCNT == 0) { De-allocate Channel } else { Transfer Done = 1 Unmask CHHLTD Disable Channel } } else if (STALL or FRMOVRUN or NAK or DATATGLERR or BBLERR) { Mask ACK Unmask CHHLTD Disable Channel if (STALL or BBLERR) { Reset Error Count Transfer Done = 1 } else if (!FRMOVRUN) { Reset Error Count } } else if (XACTERR) { Increment Error Count Unmask ACK Unmask CHHLTD Disable Channel } else if (CHHLTD) { Mask CHHLTD 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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if (Transfer Done or (Error_count == 3)) { De-allocate Channel } else { Re-initialize Channel (in next b_interval - 1 Frame) } } else if (ACK) { Reset Error Count Mask ACK } The application is expected to write the requests for the same channel when the Request queue space is available up to the count specified in the MC field before switching to another channel (if any).

15.4.3.6.11 Interrupt OUT Transactions in DMA Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 228) .

A typical interrupt OUT operation in DMA mode is shown in Figure 15.16 (p. 248) . See channel 1

(ch_1). The assumptions are: • The application is attempting to transmit one packet in every frame (up to 1 maximum packet size of 1,024 bytes).

• The Periodic Transmit FIFO can hold one packet (1 KB for FS).

• Periodic Request Queue depth = 4.

15.4.3.6.11.1 Normal Interrupt OUT Operation

1. Initialize and enable channel 1 as explained in Channel Initialization (p. 228) .

2. The host starts fetching the first packet as soon the channel is enabled and writes the OUT request along with the last DWORD fetch. In high-bandwidth transfers, the host continues fetching the next packet (up to the value specified in the MC field) before switching to the next channel.

3. The host attempts to send the OUT token in the beginning of the next odd frame.

4. After successfully transmitting the packet, the host generates a CHHLTD interrupt.

5. In response to the CHHLTD interrupt, reinitialize the channel for the next transfer.

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...the world's most energy friendly wireless MCUs Figure 15.16. Normal Interrupt OUT/IN Transactions in DMA Mode

init_ reg( ch_2)

1 1 Application

init_ reg( ch_1)

AHB

1 MPS

2 Host USB Periodic Request Queue

Assum e t hat t his queue can hold 4 ent ries.

Device

ch_1 ch_2

3 2

OUT DATA0 MPS Odd fram e

4 5

CHHLTD int errupt init_ reg( ch_1)

3

A CK IN 1 MPS DATA0 ACK 1 MPS CHHLTD int errupt

4

ch_1 ch_2 init_ reg( ch_2)

5

Even fram e init_ reg( ch_1) CHHLTD int errupt 1 MPS OUT D ATA1 MPS ACK IN DATA1

15.4.3.6.11.2 Handling Interrupts

The following code sample shows the channel-specific ISR for an interrupt OUT transaction in DMA mode.

Interrupt OUT

Unmask (CHHLTD) if (CHHLTD) { if (XFERCOMPL) { Reset Error Count Mask ACK if (Transfer Done) { De-allocate Channel } else { 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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Re-initialize Channel (in next b_interval - 1 Frame) } } else if (STALL) { Transfer Done = 1 Reset Error Count Mask ACK De-allocate Channel } else if (NAK or FRMOVRUN) { Mask ACK Rewind Buffer Pointers Re-initialize Channel (in next b_interval - 1 Frame) if (NAK) { Reset Error Count } } else if (XACTERR) { if (Error_count == 2) { De-allocate Channel } else { Increment Error Count Rewind Buffer Pointers Unmask ACK Re-initialize Channel (in next b_interval - 1 Frame) } } } else if (ACK) { Reset Error Count Mask ACK } As soon as the channel is enabled, the core attempts to fetch and write data packets, in maximum packet size multiples, to the transmit FIFO when the space is available in the transmit FIFO and the Request queue. The core stops fetching as soon as the last packet is fetched (the number of packets is determined by the MC field of the USB_HCx_CHAR register).

15.4.3.6.12 Interrupt IN Transactions in DMA Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 228) .

A typical interrupt IN operation in DMA mode is shown in Figure 15.16 (p. 248) . See channel 2 (ch_2).

The assumptions are: • The application is attempting to receive one packet in every frame (up to 1 maximum packet size of 1,024 bytes).

• The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDs per packet (1,032 bytes for FS).

• Periodic Request Queue depth = 4.

15.4.3.6.12.1 Normal Interrupt IN Operation

The sequence of operations in Figure 15.16 (p. 248) (channel 2) is as follows:

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1. Initialize and enable channel 2 as explained in Channel Initialization (p. 228) .

2. The host writes an IN request to the Request queue as soon as the channel 2 gets the grant from the arbiter (round-robin with fairness). In high-bandwidth transfers, the host writes consecutive writes up to MC times.

3. The host attempts to send an IN token at the beginning of the next (odd) frame.

4. As soon the packet is received and written to the receive FIFO, the host generates a CHHLTD interrupt.

5. In response to the CHHLTD interrupt, reinitialize the channel for the next transfer.

15.4.3.6.12.2 Handling Interrupts

The channel-specific interrupt service routine for Interrupt IN transactions in DMA mode is as follows.

Interrupt Service Routine for Interrupt IN Transactions in DMA Mode Unmask (CHHLTD) if (CHHLTD) { if (XFERCOMPL) { Reset Error Count Mask ACK if (Transfer Done) { De-allocate Channel } else { Re-initialize Channel (in next b_interval - 1 Frame) } } else if (STALL or BBLERR) { Reset Error Count Mask ACK De-allocate Channel } else if (NAK or DATATGLERR or FRMOVRUN) { Mask ACK Re-initialize Channel (in next b_interval - 1 Frame) if (DATATGLERR or NAK) { Reset Error Count } } else if (XACTERR) { if (Error_count == 2) { De-allocate Channel } else { Increment Error Count Unmask ACK Re-initialize Channel (in next b_interval - 1 Frame) } } } else if (ACK) { Reset Error Count Mask ACK 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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} As soon as the channel is enabled, the core attempts to write the requests into the Request queue when the space is available up to the count specified in the MC field.

15.4.3.6.13 Isochronous OUT Transactions in Slave Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the connected device, it must

initialize a channel as described in Channel Initialization (p. 228) . See TFigure 15.10 (p. 232) and Figure 15.11 (p. 232) for read or write data to and from the FIFO in Slave mode.

A typical isochronous OUT operation in Slave mode is shown in Figure 15.17 (p. 252) . See channel

1 (ch_1). The assumptions are: • The application is attempting to send one packet every frame (up to 1 maximum packet size), starting with an odd frame. (transfer size = 1,024 bytes).

• The Periodic Transmit FIFO can hold one packet (1 KB).

• Periodic Request Queue depth = 4.

15.4.3.6.13.1 Normal Isochronous OUT Operation

The sequence of operations in Figure 15.17 (p. 252) (channel 1) is as follows:

1. Initialize and enable channel 1 as explained in Channel Initialization (p. 228) . The application must

set the USB_HC1_CHAR.ODDFRM bit.

2. Write the first packet for channel 1. For a high-bandwidth isochronous transfer, the application must write the subsequent packets up to MC (maximum number of packets to be transmitted in the next frame) times before switching to another channel.

3. Along with the last DWORD write of each packet, the host writes an entry to the Periodic Request Queue.

4. The host attempts to send the OUT token in the next frame (odd).

5. The host generates the XFERCOMPL interrupt as soon as the last packet is transmitted successfully.

6. In response to the XFERCOMPL interrupt, reinitialize the channel for the next transfer.

15.4.3.6.13.2 Handling Interrupts

The channel-specific interrupt service routine for isochronous OUT transactions in Slave mode is shown in the following flow: 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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...the world's most energy friendly wireless MCUs Figure 15.17. Normal Isochronous OUT/IN Transactions in Slave Mode

AHB Host USB Device

init_ reg( ch_2) set_ch_en ( ch_2)

1 1 2 2 Application

init_reg(ch_1) writ e_t x_fifo ( ch_1) 1 MPS

3

ch_1 ch_2

4 Periodic Requests Queue

Asum e t hat t his queue can hold 4 ent ries.

3 5

OUT DAT A0 MPS Odd fram e

6

XFERCOMPL int errupt init_reg(ch_1) writ e_t x_fifo ( ch_1)

4

IN read_rx_st s read_rx_fifo

6

1 MPS RXFLVL int errupt 1 MPS RXFLVL int errupt

5

DAT A0 read_rx_st s

7

XFERCOMPL int errupt

8

ch_1 ch_2 init_ reg( ch_2) set_ch_en (ch_2)

9

Even fram e OUT DAT A0 MPS XFERCOMPL int errupt init_reg(ch_1) writ e_t x_fifo ( ch_1) 1 MPS IN DATA 0

Interrupt Service Routine for Isochronous OUT Transactions in Slave Mode Isochronous OUT

Unmask (FRMOVRUN/XFERCOMPL) if (XFERCOMPL) { De-allocate Channel } else if (FRMOVRUN) { Unmask CHHLTD Disable Channel } else if (CHHLTD) { Mask CHHLTD De-allocate Channel } 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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15.4.3.6.14 Isochronous IN Transactions in Slave Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the connected device, it must

initialize a channel as described in Channel Initialization (p. 228) . See Figure 15.10 (p. 232) and Figure 15.11 (p. 232) for read or write data to and from the FIFO in Slave mode.

A typical isochronous IN operation in Slave mode is shown in Figure 15.17 (p. 252) . See channel 2

(ch_2). The assumptions are: • The application is attempting to receive one packet (up to 1 maximum packet size) in every frame starting with the next odd frame. (transfer size = 1,024 bytes).

• The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDs per packet (1,031 bytes for FS).

• Periodic Request Queue depth = 4.

15.4.3.6.14.1 Normal Isochronous IN Operation

The sequence of operations in Figure 15.17 (p. 252) (channel 2) is as follows:

1. Initialize channel 2 as explained in Channel Initialization (p. 228) . The application must set the

USB_HC2_CHAR.ODDFRM bit.

2. Set the USB_HC2_CHAR.CHENA bit to write an IN request to the Periodic Request Queue. For a high-bandwidth isochronous transfer, the application must write the USB_HC2_CHAR register MC (maximum number of expected packets in the next frame) times before switching to another channel.

3. The host writes an IN request to the Periodic Request Queue for each USB_HC2_CHAR register write with the CHENA bit set.

4. The host attempts to send an IN token in the next odd frame.

5. As soon as the IN packet is received and written to the receive FIFO, the host generates an RXFLVL interrupt.

6. In response to the RXFLVL interrupt, read the received packet status to determine the number of bytes received, then read the receive FIFO accordingly. The application must mask the RXFLVL interrupt before reading the receive FIFO, and unmask it after reading the entire packet.

7. The core generates an RXFLVL interrupt for the transfer completion status entry in the receive FIFO.

This time, the application must read and ignore the receive packet status when the receive packet status is not an IN data packet (USB_GRXSTSR.PKTSTS != 0b0010).

8. The core generates an XFERCOMPL interrupt as soon as the receive packet status is read.

9. In response to the XFERCOMPL interrupt, read the USB_HC2_TSIZ.PKTCNT field. If

USB_HC2_TSIZ.PKTCNT != 0, disable the channel (as explained in Halting a Channel (p. 229)

) before re-initializing the channel for the next transfer, if any. If USB_HC2_TSIZ.PKTCNT == 0, reinitialize the channel for the next transfer. This time, the application must reset the USB_HC2_CHAR.ODDFRM bit.

15.4.3.6.14.2 Handling Interrupts

The channel-specific interrupt service routine for an isochronous IN transaction in Slave mode is as follows.

Isochronous IN

Unmask (XACTERR/XFERCOMPL/FRMOVRUN/BBLERR) if (XFERCOMPL or FRMOVRUN) { if (XFERCOMPL and (USB_HCx_TSIZ.PKTCNT == 0)) 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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{ Reset Error Count De-allocate Channel } else { Unmask CHHLTD Disable Channel } } else if (XACTERR or BBLERR) { Increment Error Count Unmask CHHLTD Disable Channel } else if (CHHLTD) { Mask CHHLTD if (Transfer Done or (Error_count == 3)) { De-allocate Channel } else { Re-initialize Channel } }

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15.4.3.6.15 Isochronous OUT Transactions in DMA Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 228) .

A typical isochronous OUT operation in DMA mode is shown in Figure 15.18 (p. 255) . See channel

1 (ch_1). The assumptions are: • The application is attempting to transmit one packet every frame (up to 1 maximum packet size of 1,024 bytes).

• The Periodic Transmit FIFO can hold one packet (1 KB).

• Periodic Request Queue depth = 4.

15.4.3.6.15.1 Normal Isochronous OUT Operation

1. Initialize and enable channel 1 as explained in Channel Initialization (p. 228) .

2. The host starts fetching the first packet as soon as the channel is enabled, and writes the OUT request along with the last DWORD fetch. In high-bandwidth transfers, the host continues fetching the next packet (up to the value specified in the MC field) before switching to the next channel.

3. The host attempts to send an OUT token in the beginning of the next (odd) frame.

4. After successfully transmitting the packet, the host generates a CHHLTD interrupt.

5. In response to the CHHLTD interrupt, reinitialize the channel for the next transfer.

15.4.3.6.15.2 Handling Interrupts

The channel-specific interrupt service routine for Isochronous OUT transactions in DMA mode is shown in the following flow: 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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...the world's most energy friendly wireless MCUs Figure 15.18. Normal Isochronous OUT/IN Transactions in DMA Mode

init_ reg( ch_2)

1 1 Application

init_reg(ch_1)

AHB

1 MPS

2 Host USB Periodic Request Queue

Assum e t hat t his queue can hold 4 ent ries.

Device

ch_1 ch_2

3 2 4

OUT D ATA0 M PS Odd fram e

5

CHHLTD int errupt init_reg(ch_1)

3

IN 1 MPS D ATA0 1 MPS CHHLTD int errupt

4

ch_1 ch_2 init_ reg( ch_2)

5

Even fram e init_reg(ch_1) CHHLTD int errupt 1 MPS OUT D ATA0 M PS IN D ATA0

Interrupt Service Routine for Isochronous OUT Transactions in DMA Mode Isochronous OUT

Unmask (CHHLTD) if (CHHLTD) { if (XFERCOMPL or FRMOVRUN) { De-allocate Channel } }

15.4.3.6.16 Isochronous IN Transactions in DMA Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the connected device, it must initialize

a channel as described in Channel Initialization (p. 228) .

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A typical isochronous IN operation in DMA mode is shown in Figure 15.18 (p. 255) . See channel 2

(ch_2). The assumptions are: • The application is attempting to receive one packet in every frame (up to 1 maximum packet size of 1,024 bytes).

• The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDS per packet (1,031 bytes).

• Periodic Request Queue depth = 4.

15.4.3.6.16.1 Normal Isochronous IN Operation

The sequence of operations in Figure 15.18 (p. 255) (channel 2) is as follows:

1. Initialize and enable channel 2 as explained in Channel Initialization (p. 228) .

2. The host writes an IN request to the Request queue as soon as the channel 2 gets the grant from the arbiter (round-robin with fairness). In high-bandwidth transfers, the host performs consecutive writes up to MC times.

3. The host attempts to send an IN token at the beginning of the next (odd) frame.

4. As soon the packet is received and written to the receive FIFO, the host generates a CHHLTD interrupt.

5. In response to the CHHLTD interrupt, reinitialize the channel for the next transfer.

15.4.3.6.16.2 Handling Interrupts

The channel-specific interrupt service routine for an isochronous IN transaction in DMA mode is as follows.

Isochronous IN

Unmask (CHHLTD) if (CHHLTD) { if (XFERCOMPL or FRMOVRUN) { if (XFERCOMPL and (USB_HCx_TSIZ.PKTCNT == 0)) { Reset Error Count De-allocate Channel } else { De-allocate Channel } } else if (XACTERR or BBLERR) { if (Error_count == 2) { De-allocate Channel } else { Increment Error Count Re-enable Channel (in next b_interval - 1 Frame) } } } 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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15.4.4 Device Programming Model

Before you program the Device, be sure to read Overview: Programming the Core (p. 222) and Modes of operation (p. 225)

15.4.4.1 Endpoint Initialization

This section addresses the following topics:

• Initialization on USB Reset (p. 257) • Initialization on Enumeration Completion (p. 257)

• Initialization on SetAddress Command (p. 258) • Initialization on SetConfiguration/SetInterface Command (p. 258) • Endpoint Activation (p. 258) • Endpoint Deactivation (p. 258)

• Device DMA/Slave Mode Initialization (p. 259)

15.4.4.1.1 Initialization on USB Reset

1. Set the NAK bit for all OUT endpoints • USB_DOEPx_CTL.SNAK = 1 (for all OUT endpoints) 2. Unmask the following interrupt bits: • USB_USB_DAINTMSK.INEP0 = 1 (control 0 IN endpoint) • USB_USB_DAINTMSK.OUTEP0 = 1 (control 0 OUT endpoint) • USB_DOEPMSK.SETUP = 1 • USB_DOEPMSK.XFERCOMPL = 1 • USB_DIEPMSK.XFERCOMPL = 1 • USB_DIEPMSK.TIMEOUTMSK = 1

3. To transmit or receive data, the device must initialize more registers as specified in Device DMA/ Slave Mode Initialization (p. 259) .

4. Set up the Data FIFO RAM for each of the FIFOs • Program the USB_GRXFSIZ Register, to be able to receive control OUT data and setup data. At a minimum, this must be equal to 1 max packet size of control endpoint 0 + 2 DWORDs (for the status of the control OUT data packet) + 10 DWORDs (for setup packets).

• Program the Device IN Endpoint Transmit FIFO size register (depending on the FIFO number chosen), to be able to transmit control IN data. At a minimum, this must be equal to 1 max packet size of control endpoint 0.

5. Program the following fields in the endpoint-specific registers for control OUT endpoint 0 to receive a SETUP packet • USB_DOEP0TSIZ.SUPCNT = 3 (to receive up to 3 back-to-back SETUP packets) • In DMA mode, USB_DOEP0DMAADDR register with a memory address to store any SETUP packets received At this point, all initialization required to receive SETUP packets is done, except for enabling control OUT endpoint 0 in DMA mode.

15.4.4.1.2 Initialization on Enumeration Completion

1. On the Enumeration Done interrupt (USB_GINTSTS.ENUMDONE, read the USB_DSTS register to determine the enumeration speed.

2. Program the USB_DIEP0CTL.MPS field to set the maximum packet size. This step configures control endpoint 0. The maximum packet size for a control endpoint depends on the enumeration speed.

3. In DMA mode, program the USB_DOEP0CTL register to enable control OUT endpoint 0, to receive a SETUP packet.

• USB_DOEP0CTL.EPENA = 1 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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At this point, the device is ready to receive SOF packets and is configured to perform control transfers on control endpoint 0.

15.4.4.1.3 Initialization on SetAddress Command

This section describes what the application must do when it receives a SetAddress command in a SETUP packet.

1. Program the USB_DCFG register with the device address received in the SetAddress command 2. Program the core to send out a status IN packet.

15.4.4.1.4 Initialization on SetConfiguration/SetInterface Command

This section describes what the application must do when it receives a SetConfiguration or SetInterface command in a SETUP packet.

1. When a SetConfiguration command is received, the application must program the endpoint registers to configure them with the characteristics of the valid endpoints in the new configuration.

2. When a SetInterface command is received, the application must program the endpoint registers of the endpoints affected by this command.

3. Some endpoints that were active in the prior configuration or alternate setting are not valid in the new configuration or alternate setting. These invalid endpoints must be deactivated.

4. For details on a particular endpoint’s activation or deactivation, see Endpoint Activation (p. 258) and Endpoint Deactivation (p. 258) .

5. Unmask the interrupt for each active endpoint and mask the interrupts for all inactive endpoints in the USB_USB_DAINTMSK register.

6. Set up the Data FIFO RAM for each FIFO. See Data FIFO RAM Allocation (p. 303) for more detail.

7. After all required endpoints are configured, the application must program the core to send a status IN packet.

At this point, the device core is configured to receive and transmit any type of data packet.

15.4.4.1.5 Endpoint Activation

This section describes the steps required to activate a device endpoint or to configure an existing device endpoint to a new type.

1. Program the characteristics of the required endpoint into the following fields of the USB_DIEPx_CTL register (for IN or bidirectional endpoints) or the USB_DOEPx_CTL register (for OUT or bidirectional endpoints).

• Maximum Packet Size • USB Active Endpoint = 1 • Endpoint Start Data Toggle (for interrupt and bulk endpoints) • Endpoint Type • TxFIFO Number 2. Once the endpoint is activated, the core starts decoding the tokens addressed to that endpoint and sends out a valid handshake for each valid token received for the endpoint.

15.4.4.1.6 Endpoint Deactivation

This section describes the steps required to deactivate an existing endpoint.

1. In the endpoint to be deactivated, clear the USB Active Endpoint bit in the USB_DIEPx_CTL register (for IN or bidirectional endpoints) or the USB_DOEPx_CTL register (for OUT or bidirectional endpoints).

2. Once the endpoint is deactivated, the core ignores tokens addressed to that endpoint, resulting in a timeout on the USB.

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15.4.4.1.7 Device DMA/Slave Mode Initialization

The application must meed the following conditions to set up the device core to handle traffic.

• In Slave mode, USB_GINTMSK.NPTXFEMPMSK, and USB_GINTMSK.RXFLVLMSK must be unset.

• In DMA mode, the aforementioned interrupts must be masked.

15.4.4.1.8 Transfer Stop Process

When the core is operating as a device, use the following programing sequence if you want to stop any transfers (because of an interrupt from the host, typically a reset).

15.4.4.1.8.1 Transfer Stop Programming Flow for IN Endpoints

Sequence of operations: 1. Disable the IN endpoint by programming USB_DIEP0CTL/USB_DIEPx_CTL.EPDIS = 1.

2. Wait for the USB_DIEPx_INT.EPDISBLD interrupt, which indicates that the IN endpoint is completely disabled. When the EPDISBLD interrupt is asserted, the core clears the following bits: • USB_DIEP0CTL/USB_DIEPx_CTL.EPDIS = 0 • USB_DIEP0CTL/USB_DIEPx_CTL.EPENA = 0 3. Flush the TX FIFO by programming the following bits: • USB_GRSTCTL.TXFFLSH = 1 • USB_GRSTCTL.TXFNUM = FIFO number specific to endpoint 4. The application can start polling till USB_GRSTCTL.TXFFLSH is cleared. When this bit is cleared, it ensures that there is no data left in the TX FIFO.

15.4.4.1.8.2 Transfer Stop Programming Flow for OUT Endpoints

Sequence of operations: 1. Enable all OUT endpoints by setting USB_DOEP0CTL/USB_DOEPx_CTL.EPENA = 1.

2. Before disabling any OUT endpoint, the application must enable Global OUT NAK mode in the core,

according to the instructions in Setting the Global OUT NAK (p. 267) . This ensures that data in the

RX FIFO is sent to the application successfully. Set USB_DCTL.USB_DCTL.SGOUTNAK = 1.

3. Wait for the USB_GINTSTS.GOUTNAKEFF interrupt.

4. Disable all active OUT endpoints by programming the following register bits: • USB_DOEP0CTL/USB_DOEPx_CTL.EPENA = 1 • USB_DOEP0CTL/USB_DOEPx_CTL.EPDIS = 1 • USB_DOEP0CTL/USB_DOEPx_CTL.SNAK = 1 5. Wait for the USB_DOEP0INT/USB_DOEPx_INT.EPDISBLD interrupt for each OUT endpoint programmed in the previous step. The USB_DOEP0INT/USB_DOEPx_INT.EPDISBLD interrupt indicates that the corresponding OUT endpoint is completely disabled. When the EPDISBLD interrupt is asserted, the core clears the following bits: • USB_DOEP0CTL/USB_DOEPx_CTL.EPENA = 0 • USB_DOEP0CTL/USB_DOEPx_CTL.EPDIS = 0

Note

The application must not flush the Rx FIFO, as the Global OUT NAK effective interrupt earlier ensures that there is no data left in the Rx FIFO.

15.4.4.2 Device Programming Operations

Table 15.2 (p. 260) provides links to the programming sequence for different USB transaction types.

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Device Mode Control Slave IN SETUP DMA

Generic Non-Periodic (Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode (p. 284) Generic Non-Periodic (Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode (p. 284)

OUT Data Transfers in Slave and DMA Modes (p. 261) OUT Data Transfers in Slave and DMA Modes (p. 261)

Bulk Slave DMA

Generic Non-Periodic (Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode (p. 284) Generic Non-Periodic (Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode (p. 284)

Interrupt Slave DMA

Generic Periodic IN (Interrupt and Isochronous) Data Transfers Without Thresholding (p. 289)

and Generic Periodic IN Data Transfers Without Thresholding Using the Periodic Transfer Interrupt Feature (p.

291)

Generic Periodic IN (Interrupt and Isochronous) Data Transfers Without Thresholding (p. 289)

and Generic Periodic IN Data Transfers Without Thresholding Using the Periodic Transfer Interrupt Feature (p.

291)

Isochronous Slave

Generic Periodic IN (Interrupt and Isochronous) Data Transfers Without Thresholding (p. 289)

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OUT

Generic Non-Isochronous OUT Data Transfers Without Thresholding in DMA and Slave Modes (p. 269) Generic Non-Isochronous OUT Data Transfers Without Thresholding in DMA and Slave Modes (p. 269) Generic Non-Isochronous OUT Data Transfers Without Thresholding in DMA and Slave Modes (p. 269) Generic Non-Isochronous OUT Data Transfers Without Thresholding in DMA and Slave Modes (p. 269) Generic Non-Isochronous OUT Data Transfers Without Thresholding in DMA and Slave Modes (p. 269)

and Generic Interrupt OUT Data Transfers Without Thresholding Using Periodic Transfer Interrupt Feature (p.

273)

Generic Non-Isochronous OUT Data Transfers Without Thresholding in DMA and Slave Modes (p. 269)

and Generic Interrupt OUT Data Transfers Without Thresholding Using Periodic Transfer Interrupt Feature (p.

273)

Control Read Transfers (SETUP, Data IN, Status OUT) (p. 264) and

Incomplete Isochronous OUT Data Transfers

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DMA

Generic Periodic IN (Interrupt and Isochronous) Data Transfers Without Thresholding (p. 289)

and Generic Periodic IN Data Transfers Without Thresholding Using the Periodic Transfer Interrupt Feature (p.

291)

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in DMA and Slave Modes (p. 277)

Control Read Transfers (SETUP, Data IN, Status OUT) (p. 264) and

Incomplete Isochronous OUT Data Transfers in DMA and Slave Modes (p. 277)

15.4.4.2.1 OUT Data Transfers in Slave and DMA Modes

This section describes the internal data flow and application-level operations during data OUT transfers and setup transactions.

15.4.4.2.1.1 Control Setup Transactions

This section describes how the core handles SETUP packets and the application’s sequence for handling setup transactions. To initialize the core after power-on reset, the application must follow the sequence

in Overview: Programming the Core (p. 222) . Before it can communicate with the host, it must initialize

an endpoint as described in Endpoint Initialization (p. 257) . See Packet Read from FIFO in Slave Mode (p. 266) .

Application Requirements

1. To receive a SETUP packet, the USB_DOEPx_TSIZ.SUPCNT field in a control OUT endpoint must be programmed to a non-zero value. When the application programs the SUPCNT field to a non zero value, the core receives SETUP packets and writes them to the receive FIFO, irrespective of the USB_DOEPx_CTL.NAK status and USB_DOEPx_CTL.EPENA bit setting. The SUPCNT field is decremented every time the control endpoint receives a SETUP packet. If the SUPCNT field is not programmed to a proper value before receiving a SETUP packet, the core still receives the SETUP packet and decrements the SUPCNT field, but the application possibly is not be able to determine the correct number of SETUP packets received in the Setup stage of a control transfer.

• USB_DOEPx_TSIZ.SUPCNT = 3 2. In DMA mode, the OUT endpoint must also be enabled, to transfer the received SETUP packet data from the internal receive FIFO to the external memory.

• USB_DOEPx_CTL.EPENA = 1 3. The application must always allocate some extra space in the Receive Data FIFO, to be able to receive up to three SETUP packets on a control endpoint.

• The space to be Reserved is (4 * n) + 6 DWORDs, where n is the number of control endpoints supported by the device. Three DWORDs are required for the first SETUP packet, 1 DWORD is required for the Setup Stage Done DWORD, and 6 DWORDs are required to store two extra SETUP packets among all control endpoints.

• 3 DWORDs per SETUP packet are required to store 8 bytes of SETUP data and 4 bytes of SETUP status (Setup Packet Pattern). The core reserves this space in the receive data • FIFO to write SETUP data only, and never uses this space for data packets.

4. In Slave mode, the application must read the 2 DWORDs of the SETUP packet from the receive FIFO.

In DMA mode, the core writes the 2 DWORDs of SETUP data to the memory.

5. The application must read and discard the Setup Stage Done DWORD from the receive FIFO.

Internal Data Flow

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1. When a SETUP packet is received, the core writes the received data to the receive FIFO, without checking for available space in the receive FIFO and irrespective of the endpoint’s NAK and Stall bit settings.

• The core internally sets the IN NAK and OUT NAK bits for the control IN/OUT endpoints on which the SETUP packet was received.

2. For every SETUP packet received on the USB, 3 DWORDs of data is written to the receive FIFO, and the SUPCNT field is decremented by 1.

• The first DWORD contains control information used internally by the core • The second DWORD contains the first 4 bytes of the SETUP command • The third DWORD contains the last 4 bytes of the SETUP command 3. When the Setup stage changes to a Data IN/OUT stage, the core writes an entry (Setup Stage Done DWORD) to the receive FIFO, indicating the completion of the Setup stage.

4. On the AHB side, SETUP packets are emptied either by the DMA or the application. In DMA mode, the SETUP packets (2 DWORDs) are written to the memory location programmed in the USB_DOEPx_DMAADDR register, only if the endpoint is enabled. If the endpoint is not enabled, the data remains in the receive FIFO until the enable bit is set.

5. When either the DMA or the application pops the Setup Stage Done DWORD from the receive FIFO, the core interrupts the application with a USB_DOEPx_INT.SETUP interrupt, indicating it can process the received SETUP packet.

• The core clears the endpoint enable bit for control OUT endpoints.

Application Programming Sequence

1. Program the USB_DOEPx_TSIZ register.

• USB_DOEPx_TSIZ.SUPCNT = 3 2. In DMA mode, program the USB_DOEPx_DMAADDR register and USB_DOEPx_CTL register with the endpoint characteristics and set the Endpoint Enable bit (USB_DOEPx_CTL.EPENA).

• Endpoint Enable = 1 3. In Slave mode, wait for the USB_GINTSTS.RXFLVL interrupt and empty the data packets from the

receive FIFO, as explained in Packet Read from FIFO in Slave Mode (p. 266) . This step can be

repeated many times.

4. Assertion of the USB_DOEPx_INT.SETUP interrupt marks a successful completion of the SETUP Data Transfer.

• On this interrupt, the application must read the USB_DOEPx_TSIZ register to determine the number of SETUP packets received and process the last received SETUP packet.

• In DMA mode, the application must also determine if the interrupt bit USB_DOEPx_INT.BACK2BACKSETUP is set. This bit is set if the core has received more than three back-to-back SETUP packets. If this is the case, the application must ignore the USB_DOEPx_TSIZ.SUPCNT value and use the USB_DOEPx_DMAADDR directly to read out the last SETUP packet received. USB_DOEPx_DMAADDR-8 provides the pointer to the last valid SETUP data.

Note

If the application has not enabled EP0 before the host sends the SETUP packet, the core ACKs the SETUP packet and stores it in the FIFO, but does not write to the memory until EP0 is enabled. When the application enables the EP0 (first enable) and clears the NAK bit at the same time the Host sends DATA OUT, the DATA OUT is stored in the RxFIFO.

The OTG core then writes the setup data to the memory and disables the endpoint. Though the application expects a Transfer Complete interrupt for the Data OUT phase, this does not occur, because the SETUP packet, rather than the DATA OUT packet, enables EP0 the first time. Thus, the DATA OUT packet is still in the RxFIFO until the application re-enables EP0. The application must enable EP0 one more time for the core to process the DATA OUT packet.

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Figure 15.19 (p. 263) charts this flow.

Figure 15.19. Processing a SETUP Packet

Wait for USB_DOEPx _INT.SETUP

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No Back2Back Set up Int errupt bit set ?

Yes rem _supcnt = Rd_Reg(USB_DOEPx _TSIZ) Set up_addr = Rd_Reg(USB_DOEPx _DMA set up_cm d[31:0] = m em [4- 2 * rem _supcnt ] set up_cm d[63:32] = m em [5- 2 * rem _supcnt ] set up_cm d[31:0] = m em [set up_addr- 8] set up_cm d[63:32] = m em [set up_addr- 4] Find set up cm d t ype Read ct r- rd/ wr/ 2 st age Writ e set up_np_in_pkt Dat a IN phase 2- st age set up_np_in_pkt Sat a IN phase rcv_out _pkt Dat a OUT phase

15.4.4.2.1.2 Handling More Than Three Back-to-Back SETUP Packets

Per the USB 2.0 specification, normally, during a SETUP packet error, a host does not send more than three back-to-back SETUP packets to the same endpoint. However, the USB 2.0 specification does not limit the number of back-to-back SETUP packets a host can send to the same endpoint.

When this condition occurs, the core generates an interrupt (USB_DOEPx_INT.BACK2BACKSETUP).

In DMA mode, the core also rewinds the DMA address for that endpoint (USB_DOEPx_DMAADDR) and overwrites the first SETUP packet in system memory with the fourth, second with the fifth, and so on. If the BACK2BACKSETUP interrupt is asserted, the application must read the OUT endpoint DMA register (USB_DOEPx_DMAADDR) to determine the final SETUP data in system memory.

In DMA mode, the application can mask the BACK2BACKSETUP interrupt, but after receiving the DOEPINT.SETUP interrupt, the application can read the DOEPINT.BACK2BACKSETUP interrupt bit.

In Slave mode, the application can use the USB_GINTSTS.RXFLVL interrupt to read out the SETUP packets from the FIFO whenever the core receives the SETUP packet.

15.4.4.2.2 Control Transfers

This section describes the various types of control transfers.

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15.4.4.2.2.1 Control Write Transfers (SETUP, Data OUT, Status IN)

This section describes control write transfers.

Application Programming Sequence 1. Assertion of the USB_DOEPx_INT.SETUP Packet interrupt indicates that a valid SETUP packet

has been transferred to the application. See OUT Data Transfers in Slave and DMA Modes (p.

261) for more details. At the end of the Setup stage, the application must reprogram the

USB_DOEPx_TSIZ.SUPCNT field to 3 to receive the next SETUP packet.

2. If the last SETUP packet received before the assertion of the SETUP interrupt indicates a data OUT

phase, program the core to perform a control OUT transfer as explained in Generic Non-Isochronous OUT Data Transfers Without Thresholding in DMA and Slave Modes (p. 269) .

In DMA mode, the application must reprogram the USB_DOEPx_DMAADDR register to receive a control OUT data packet to a different memory location.

3. In a single OUT data transfer on control endpoint 0, the application can receive up to 64 bytes. If the application is expecting more than 64 bytes in the Data OUT stage, the application must re-enable the endpoint to receive another 64 bytes, and must continue to do so until it has received all the data in the Data stage.

4. Assertion of the USB_DOEPx_INT.Transfer Completed interrupt on the last data OUT transfer indicates the completion of the data OUT phase of the control transfer.

5. On completion of the data OUT phase, the application must do the following.

• To transfer a new SETUP packet in DMA mode, the application must re-enable the control OUT

endpoint as explained in OUT Data Transfers in Slave and DMA Modes (p. 261) .

• USB_DOEPx_CTL.EPENA = 1 • To execute the received Setup command, the application must program the required registers in the core. This step is optional, based on the type of Setup command received.

6. For the status IN phase, the application must program the core as described in Generic Non-Periodic

perform a data IN transfer.

7. Assertion of the USB_DIEPx_INT.XFERCOMPL interrupt indicates completion of the status IN phase of the control transfer.

8. The previous step must be repeated until the USB_DIEPx_INT.XFERCOMPL interrupt is detected on the endpoint, marking the completion of the control write transfer.

15.4.4.2.2.2 Control Read Transfers (SETUP, Data IN, Status OUT)

This section describes control read transfers.

Application Programming Sequence

1. Assertion of the USB_DOEPx_INT.SETUP Packet interrupt indicates that a valid SETUP packet

has been transferred to the application. See OUT Data Transfers in Slave and DMA Modes (p.

261) for more details. At the end of the Setup stage, the application must reprogram the

USB_DOEPx_TSIZ.SUPCNT field to 3 to receive the next SETUP packet.

2. If the last SETUP packet received before the assertion of the SETUP interrupt indicates a data IN

phase, program the core to perform a control IN transfer as explained in Generic Non-Periodic (Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode (p. 284) .

3. On a single IN data transfer on control endpoint 0, the application can transmit up to 64 bytes. To transmit more than 64 bytes in the Data IN stage, the application must re-enable the endpoint to transmit another 64 bytes, and must continue to do so, until it has transmitted all the data in the Data stage.

4. The previous step must be repeated until the USB_DIEPx_INT.XFERCOMPL interrupt is detected for every IN transfer on the endpoint.

5. The USB_DIEPx_INT.XFERCOMPL interrupt on the last IN data transfer marks the completion of the control transfer’s Data stage.

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6. To perform a data OUT transfer in the status OUT phase, the application must program the core as

described in OUT Data Transfers in Slave and DMA Modes (p. 261) .

• The application must program the USB_DCFG.NZSTSOUTHSHK handshake field to a proper setting before transmitting an data OUT transfer for the Status stage.

• In DMA mode, the application must reprogram the USB_DOEPx_DMAADDR register to receive the control OUT data packet to a different memory location.

7. Assertion of the USB_DOEPx_INT.XFERCOMPL interrupt indicates completion of the status OUT phase of the control transfer. This marks the successful completion of the control read transfer.

• To transfer a new SETUP packet in DMA mode, the application must re-enable the control OUT

endpoint as explained in OUT Data Transfers in Slave and DMA Modes (p. 261) .

• USB_DOEPx_CTL.EPENA = 1

15.4.4.2.2.3 Two-Stage Control Transfers (SETUP/Status IN)

This section describes two-stage control transfers.

Application Programming Sequence

1. Assertion of the USB_DOEPx_INT.SETUP interrupt indicates that a valid SETUP packet has

been transferred to the application. See OUT Data Transfers in Slave and DMA Modes (p.

261) for more detail. To receive the next SETUP packet, the application must reprogram the

USB_DOEPx_TSIZ.SUPCNT field to 3 at the end of the Setup stage.

2. Decode the last SETUP packet received before the assertion of the SETUP interrupt. If the packet indicates a two-stage control command, the application must do the following.

• To transfer a new SETUP packet in DMA mode, the application must re-enable the control OUT

endpoint. See OUT Data Transfers in Slave and DMA Modes (p. 261) for details.

• USB_DOEPx_CTL.EPENA = 1 • Depending on the type of Setup command received, the application can be required to program registers in the core to execute the received Setup command.

3. For the status IN phase, the application must program the core described in Generic Non-Periodic

perform a data IN transfer.

4. Assertion of the USB_DIEPx_INT.XFERCOMPL interrupt indicates the completion of the status IN phase of the control transfer.

5. The previous step must be repeated until the USB_DIEPx_INT.XFERCOMPL interrupt is detected on the endpoint, marking the completion of the two-stage control transfer.

Example: Two-Stage Control Transfer

These notes refer to Figure 15.20 (p. 266) .

1. SETUP packet #1 is received on the USB and is written to the receive FIFO, and the core responds with an ACK handshake. This handshake is lost and the host detects a timeout.

2. The SETUP packet in the receive FIFO results in a USB_GINTSTS.RXFLVL interrupt to the application, causing the application to empty the receive FIFO.

3. SETUP packet #2 on the USB is written to the receive FIFO, and the core responds with an ACK handshake.

4. The SETUP packet in the receive FIFO sends the application the USB_GINTSTS.RXFLVL interrupt and the application empties the receive FIFO.

5. After the second SETUP packet, the host sends a control IN token for the status phase. The core issues a NAK response to this token, and writes a Setup Stage Done entry to the receive FIFO. This entry results in a USB_GINTSTS.RXFLVL interrupt to the application, which empties the receive FIFO.

After reading out the Setup Stage Done DWORD, the core asserts the USB_DOEPx_INT.SETUP

packet interrupt to the application.

6. On this interrupt, the application processes SETUP Packet #2, decodes it to be a two-stage control command, and clears the control IN NAK bit.

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• USB_DIEPx_CTL.CNAK = 1 7. When the application clears the IN NAK bit, the core interrupts the application with a USB_DIEPx_INT.INTKNTXFEMP. On this interrupt, the application enables the control IN endpoint with a USB_DIEPx_TSIZ.XFERSIZE of 0 and a USB_DIEPx_TSIZ.PKTCNT of 1. This results in a zero-length data packet for the status IN token on the USB.

8. At the end of the status IN phase, the core interrupts the application with a USB_DIEPx_INT.XFERCOMPL interrupt.

Figure 15.20. Two-Stage Control Transfer

Host USB Device Application 1

set up_ x act_1

3

set up_ x act_2 st at us_ x act_2 st at us_ x act_2 SETUP A CK Lo st S ETUP ACK IN NA K IN NAK IN(STATUS) .

ACK Ct l- IN NAK 1 1 RXFLVL INTR idle unt il int r rcv_out_ dat a RXF INTR LVL set up done idle unt il int r RX FLV L IN

4

TR

5

rcv_out_ dat a idle unt il int r rcv_out_ dat a SETUP Intr idle unt il int r INTKNTXFEM P Clear IN NAK INTR sts data rdy proc_ set up_pkt # 2 set up_ in_ np_ pkt XFERCOMP INTR L

8 7

idle unt il int r

6

XFERSIZE = 0 byt es PKTCNT = 1 EPENA = 1

15.4.4.2.2.4 Packet Read from FIFO in Slave Mode

This section describes how to read packets (OUT data and SETUP packets) from the receive FIFO in Slave mode.

1. On catching a USB_GINTSTS.RXFLVL interrupt, the application must read the Receive Status Pop register (USB_GRXSTSP).

2. The application can mask the USB_GINTSTS.RXFLVL interrupt USB_GINTMSK.RXFLVL = 0, until it has read the packet from the receive FIFO.

by writing to 3. If the received packet’s byte count is not 0, the byte count amount of data is popped from the receive Data FIFO and stored in memory. If the received packet byte count is 0, no data is popped from the Receive Data FIFO.

4. The receive FIFO’s packet status readout indicates one of the following.

5. Global OUT NAK Pattern: PKTSTS = Global OUT NAK, BCNT = 0x000, EPNUM = Dont Care (0x0), DPID = Dont Care (0b00). This data indicates that the global OUT NAK bit has taken effect.

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a. SETUP Packet Pattern: PKTSTS = SETUP, BCNT = 0x008, EPNUM = Control EP Num, DPID = D0. This data indicates that a SETUP packet for the specified endpoint is now available for reading from the receive FIFO.

b. Setup Stage Done Pattern: PKTSTS = Setup Stage Done, BCNT = 0x0, EPNUM = Control EP Num, DPID = Don’t Care (0b00). This data indicates that the Setup stage for the specified endpoint has completed and the Data stage has started. After this entry is popped from the receive FIFO, the core asserts a Setup interrupt on the specified control OUT endpoint.

c. Data OUT Packet Pattern: PKTSTS = DataOUT, BCNT = size of the Received data OUT packet, EPNUM = EPNum on which the packet was received, DPID = Actual Data PID.

d. Data Transfer Completed Pattern: PKTSTS = Data OUT Transfer Done, BCNT = 0x0, EPNUM = OUT EP Num on which the data transfer is complete, DPID = Dont Care (0b00). This data indicates that a OUT data transfer for the specified OUT endpoint has completed. After this entry is popped from the receive FIFO, the core asserts a Transfer Completed interrupt on the specified OUT endpoint.

The encoding for the PKTSTS is listed in Section 15.6 (p. 325) .

6. After the data payload is popped from the receive FIFO, the USB_GINTSTS.RXFLVL interrupt must be unmasked.

7. Steps 1–5 are repeated every time the application detects assertion of the interrupt line due to USB_GINTSTS.RXFLVL. Reading an empty receive FIFO can result in undefined core behavior.

Figure 15.21 (p. 267) provides a flow chart of this procedure.

Figure 15.21. Receive FIFO Packet Read in Slave Mode

wait unt il USB_GINTSTS.RXFLVL

rd_dat a = rd_reg(USB_RXSTSP) packet st ore in m em ory Y rd_dat a.BCNT = 0 N m em [0:dword_cnt - 1] = rd_rx fifo(rd_dat a.EPNUM, dword_cnt ) dword_cnt = BCNT[11:2] + (BCNT[1] | BCNT[0]) rcv_out _pkt ()

15.4.4.2.2.5 Setting the Global OUT NAK

Internal Data Flow 1. When the application sets the Global OUT NAK (USB_DCTL.SGOUTNAK), the core stops writing data, except SETUP packets, to the receive FIFO. Irrespective of the space availability in the receive FIFO, non-isochronous OUT tokens receive a NAK handshake response, and the core ignores isochronous OUT data packets 2. The core writes the Global OUT NAK pattern to the receive FIFO. The application must reserve

enough receive FIFO space to write this data pattern. See Data FIFO RAM Allocation (p. 303) .

3. When either the core (in DMA mode) or the application (in Slave mode) pops the Global OUT NAK pattern DWORD from the receive FIFO, the core sets the USB_GINTSTS.GOUTNAKEFF interrupt.

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4. Once the application detects this interrupt, it can assume that the core is in Global OUT NAK mode.

The application can clear this interrupt by clearing the USB_DCTL.SGOUTNAK bit.

Application Programming Sequence

1. To stop receiving any kind of data in the receive FIFO, the application must set the Global OUT NAK bit by programming the following field.

• USB_DCTL.SGOUTNAK = 1 2. Wait for the assertion of the interrupt USB_GINTSTS.GOUTNAKEFF. When asserted, this interrupt indicates that the core has stopped receiving any type of data except SETUP packets.

3. The application can receive valid OUT packets after it has set USB_DCTL.SGOUTNAK and before the core asserts the USB_GINTSTS.GOUTNAKEFF interrupt.

4. The application can temporarily USB_GINTMSK.GOUTNAKEFFMSK bit.

mask this interrupt by writing to the • USB_GINTMSK.GINNAKEFFMSK = 0 5. Whenever the application is ready to exit the Global OUT NAK mode, it must clear the USB_DCTL.SGOUTNAK bit. This also clears the USB_GINTSTS.GOUTNAKEFF interrupt.

• USB_DCTL.CGOUTNAK = 1 6. If the application has masked this interrupt earlier, it must be unmasked as follows: • USB_GINTMSK.GOUTNAKEFFMSK = 1

15.4.4.2.2.6 Disabling an OUT Endpoint

The application must use this sequence to disable an OUT endpoint that it has enabled.

Application Programming Sequence

1. Before disabling any OUT endpoint, the application must enable Global OUT NAK mode in the core,

as described in Setting the Global OUT NAK (p. 267) .

• USB_DCTL.SGOUTNAK = 1 • Wait for the USB_GINTSTS.GOUTNAKEFF interrupt 2. Disable the required OUT endpoint by programming the following fields.

• USB_DOEPx_CTL.EPDIS = 1 • USB_DOEPx_CTL.SNAK = 1 3. Wait for the USB_DOEPx_INT.EPDISBLD interrupt, which indicates that the OUT endpoint is completely disabled. When the EPDISBLD interrupt is asserted, the core also clears the following bits.

• USB_DOEPx_CTL.EPDIS = 0 • USB_DOEPx_CTL.EPENA = 0 4. The application must clear the Global OUT NAK bit to start receiving data from other non-disabled OUT endpoints.

• USB_DCTL.SGOUTNAK = 0

15.4.4.2.2.7 Stalling a Non-Isochronous OUT Endpoint

This section describes how the application can stall a non-isochronous endpoint.

1. Put the core in the Global OUT NAK mode, as described in Setting the Global OUT NAK (p. 267) .

2. Disable the required endpoint, as described in Section 15.4.4.2.2.6 (p. 268) .

• When disabling the endpoint, instead of setting the USB_DOEPx_CTL.SNAK bit, set USB_DOEPx_CTL.STALL = 1.

• The Stall bit always takes precedence over the NAK bit.

3. When the application is ready to end the STALL handshake for the endpoint, the USB_DOEPx_CTL.STALL bit must be cleared.

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4. If the application is setting or clearing a STALL for an endpoint due to a SetFeature.Endpoint Halt or ClearFeature.Endpoint Halt command, the Stall bit must be set or cleared before the application sets up the Status stage transfer on the control endpoint.

15.4.4.2.2.8 Generic Non-Isochronous OUT Data Transfers in DMA and Slave Modes

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the host, it must initialize an endpoint

as described in Endpoint Initialization (p. 257) . See Packet Read from FIFO in Slave Mode (p. 266) .

This section describes a regular non-isochronous OUT data transfer (control, bulk, or interrupt).

Application Requirements

1. Before setting up an OUT transfer, the application must allocate a buffer in the memory to accommodate all data to be received as part of the OUT transfer, then program that buffer’s size and start address (in DMA mode) in the endpoint-specific registers.

1. For OUT transfers, the Transfer Size field in the endpoint’s Transfer Size register must be a multiple of the maximum packet size of the endpoint, adjusted to the DWORD boundary.

if (mps[epnum] mod 4) == 0 transfer size[epnum] = n * (mps[epnum]) //Dword Aligned else transfer size[epnum] = n * (mps[epnum] + 4 - (mps[epnum] mod 4)) //Non Dword Aligned packet count[epnum] = n n > 0 2. In DMA mode, the core stores a received data packet in the memory, always starting on a DWORD boundary. If the maximum packet size of the endpoint is not a multiple of 4, the core inserts byte pads at end of a maximum-packet-size packet up to the end of the DWORD.

3. On any OUT endpoint interrupt, the application must read the endpoint’s Transfer Size register to calculate the size of the payload in the memory. The received payload size can be less than the programmed transfer size.

• Payload size in memory = application-programmed initial transfer size – core updated final transfer size • Number of USB packets in which this payload was received = application-programmed initial packet count – core updated final packet count

Internal Data Flow

1. The application must set the Transfer Size and Packet Count fields in the endpoint-specific registers, clear the NAK bit, and enable the endpoint to receive the data.

2. Once the NAK bit is cleared, the core starts receiving data and writes it to the receive FIFO, as long as there is space in the receive FIFO. For every data packet received on the USB, the data packet and its status are written to the receive FIFO. Every packet (maximum packet size or short packet) written to the receive FIFO decrements the Packet Count field for that endpoint by 1.

• OUT data packets received with Bad Data CRC are flushed from the receive FIFO automatically.

• After sending an ACK for the packet on the USB, the core discards non-isochronous OUT data packets that the host, which cannot detect the ACK, re-sends. The application does not detect multiple back-to-back data OUT packets on the same endpoint with the same data PID. In this case the packet count is not decremented.

• If there is no space in the receive FIFO, isochronous or non-isochronous data packets are ignored and not written to the receive FIFO. Additionally, non-isochronous OUT tokens receive a NAK handshake reply.

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• In all the above three cases, the packet count is not decremented because no data is written to the receive FIFO.

3. When the packet count becomes 0 or when a short packet is received on the endpoint, the NAK bit for that endpoint is set. Once the NAK bit is set, the isochronous or non-isochronous data packets are ignored and not written to the receive FIFO, and non-isochronous OUT tokens receive a NAK handshake reply.

4. After the data is written to the receive FIFO, either the application (in Slave mode) or the core’s DMA engine (in DMA mode), reads the data from the receive FIFO and writes it to external memory, one packet at a time per endpoint.

5. At the end of every packet write on the AHB to external memory, the transfer size for the endpoint is decremented by the size of the written packet.

6. The OUT Data Transfer Completed pattern for an OUT endpoint is written to the receive FIFO on one of the following conditions.

• The transfer size is 0 and the packet count is 0 • The last OUT data packet written to the receive FIFO is a short packet (0 <= packet size < maximum packet size) 7. When either the application or the DMA pops this entry (OUT Data Transfer Completed), a Transfer Completed interrupt is generated for the endpoint and the endpoint enable is cleared.

Application Programming Sequence

1. Program the USB_DOEPx_TSIZ register for the transfer size and the corresponding packet count.

Additionally, in DMA mode, program the USB_DOEPx_DMAADDR register.

2. Program the USB_DOEPx_CTL register with the endpoint characteristics, and set the Endpoint Enable and ClearNAK bits.

• USB_DOEPx_CTL.EPENA = 1 • USB_DOEPx_CTL.CNAK = 1 3. In Slave mode, wait for the USB_GINTSTS.RXFLVL level interrupt and empty the data packets from

the receive FIFO as explained in Packet Read from FIFO in Slave Mode (p. 266) .

• This step can be repeated many times, depending on the transfer size.

4. Asserting the USB_DOEPx_INT.XFERCOMPL interrupt marks a successful completion of the non isochronous OUT data transfer.

5. Read the USB_DOEPx_TSIZ register to determine the size of the received data payload.

Note

The XFERSIZE is not decremented for the last packet. This is as per design behavior.

Slave Mode Bulk OUT Transaction

Figure 15.22 (p. 271) depicts the reception of a single bulk OUT data packet from the USB to the AHB

and describes the events involved in the process.

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...the world's most energy friendly wireless MCUs Figure 15.22. Slave Mode Bulk OUT Transaction

Host USB Device Applicatio n init_ out_ ep 1 2

OUT wr_reg(USB_DOEPx _TSIZ) wr_reg(USB_DOEPx _CTL)

3

EPENA = = ACK

5 4

x act_1 U S B PKTCNT = T NAK=1 0 RXFLVL INTR

6

idle unt il int r OUT NAK

7

XFERSIZE= 0 XFER CO R MP

8

rcv_out_pkt() idle unt il int r On new x fer or Rx FIFO not em pt y After a SetConfiguration/SetInterface command, the application initializes all OUT endpoints by setting USB_DOEPx_CTL.CNAK = 1 and USB_DOEPx_CTL.EPENA = 1, and setting a suitable XFERSIZE and PKTCNT in the USB_DOEPx_TSIZ register.

1. Host attempts to send data (OUT token) to an endpoint.

2. When the core receives the OUT token on the USB, it stores the packet in the RxFIFO because space is available there.

3. After writing the complete packet in the RxFIFO, the core then asserts the USB_GINTSTS.RXFLVL

interrupt.

4. On receiving the PKTCNT number of USB packets, the core sets the NAK bit for this endpoint internally to prevent it from receiving any more packets.

5. The application processes the interrupt and reads the data from the RxFIFO.

6. When the application has read all the data (equivalent to XFERSIZE), the core generates a USB_DOEPx_INT.XFERCOMPL interrupt.

7. The application processes the interrupt and uses the setting of the USB_DOEPx_INT.XFERCOMPL

interrupt bit to determine that the intended transfer is complete.

15.4.4.2.2.9 Generic Isochronous OUT Data Transfer in DMA and Slave Modes

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the host, it must initialize an endpoint

as described in Endpoint Initialization (p. 257) . See Packet Read from FIFO in Slave Mode (p. 266) .

This section describes a regular isochronous OUT data transfer.

Application Requirements:

1. All the application requirements for non-isochronous OUT data transfers also apply to isochronous OUT data transfers 2. For isochronous OUT data transfers, the Transfer Size and Packet Count fields must always be set to the number of maximum-packet-size packets that can be received in a single frame and no more.

Isochronous OUT data transfers cannot span more than 1 frame.

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3. In Slave mode, when isochronous OUT endpoints are supported in the device, the application must read all isochronous OUT data packets from the receive FIFO (data and status) before the end of the periodic frame (USB_GINTSTS.EOPF interrupt). In DMA mode, the application must guarantee enough bandwidth to allow emptying the isochronous OUT data packet from the receive FIFO before the end of each periodic frame.

4. To receive data in the following frame, an isochronous OUT endpoint must be enabled after the USB_GINTSTS.EOPF and before the USB_GINTSTS.SOF.

Internal Data Flow

1. The internal data flow for isochronous OUT endpoints is the same as that for non-isochronous OUT endpoints, but for a few differences.

2. When an isochronous OUT endpoint is enabled by setting the Endpoint Enable and clearing the NAK bits, the Even/Odd frame bit must also be set appropriately. The core receives data on a isochronous OUT endpoint in a particular frame only if the following condition is met.

• USB_DOEPx_CTL.DPIDEOF (Even/Odd frame) = USB_DSTS.SOFFN[0] 3. When either the application or the internal DMA completely reads an isochronous OUT data packet (data and status) from the receive FIFO, the core updates the USB_DOEPx_TSIZ.RXDPIDSUPCNT

(Received DPID) field with the data PID of the last isochronous OUT data packet read from the receive FIFO.

Application Programming Sequence

1. Program the USB_DOEPx_TSIZ register for the transfer size and the corresponding packet count.

When in DMA mode, also program the USB_DOEPx_DMAADDR register.

2. Program the USB_DOEPx_CTL register with the endpoint characteristics and set the Endpoint Enable, ClearNAK, and Even/Odd frame bits.

• Endpoint Enable = 1 • CNAK = 1 • Even/Odd frame = (0: Even/1: Odd) 1. In Slave mode, wait for the USB_GINTSTS.Rx StsQ level interrupt and empty the data packets from

the receive FIFO as explained in Packet Read from FIFO in Slave Mode (p. 266) .

• This step can be repeated many times, depending on the transfer size.

1. The assertion of the USB_DOEPx_INT.XFERCOMPL interrupt marks the completion of the isochronous OUT data transfer. This interrupt does not necessarily mean that the data in memory is good.

2. This interrupt can not always be detected for isochronous OUT transfers. Instead, the application can

detect the USB_GINTSTS.INCOMPLP (Incomplete Isochronous OUT data) interrupt. See Incomplete Isochronous OUT Data Transfers in DMA and Slave Modes (p. 277) , for more details

3. Read the USB_DOEPx_TSIZ register to determine the size of the received transfer and to determine the validity of the data received in the frame. The application must treat the data received in memory as valid only if one of the following conditions is met.

• USB_DOEPx_TSIZ.RXDPID = D0 and the number of USB packets in which this payload was received = 1 • USB_DOEPx_TSIZ.RXDPID = D1 and the number of USB packets in which this payload was received = 2 • USB_DOEPx_TSIZ.RXDPID = D2 and the number of USB packets in which this payload was received = 3 • The number of USB packets in which this payload was received = App Programmed Initial Packet Count – Core Updated Final Packet Count The application can discard invalid data packets.

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15.4.4.2.2.10 Generic Interrupt OUT Data Transfers Using Periodic Transfer Interrupt Feature

This section describes a regular INTR OUT data transfer with the Periodic Transfer Interrupt feature.

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the host, it must initialize an endpoint

as described in Endpoint Initialization (p. 257) . See Packet Read from FIFO in Slave Mode (p. 266) .

Application Requirements 1. Before setting up a periodic OUT transfer, the application must allocate a buffer in the memory to accommodate all data to be received as part of the OUT transfer, then program that buffer’s size and start address in the endpoint-specific registers.

2. For Interrupt OUT transfers, the Transfer Size field in the endpoint’s Transfer Size register must be a multiple of the maximum packet size of the endpoint, adjusted to the DWORD boundary. The Transfer Size programmed can span across multiple frames based on the periodicity after which the application want to receive the USB_DOEPx_INT.XFERCOMPL interrupt • transfer size[epnum] = n * (mps[epnum] + 4 - (mps[epnum] mod 4)) • packet count[epnum] = n • n > 0 (Higher value of n reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt) • 1 < packet count[epnum] < n (Higher value of n reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt) 3. In DMA mode, the core stores a received data packet in the memory, always starting on a DWORD boundary. If the maximum packet size of the endpoint is not a multiple of 4, the core inserts byte pads at end of a maximum-packet-size packet up to the end of the DWORD. The application will not be informed about the frame number on which a specific packet has been received.

4. On USB_DOEPx_INT.XFERCOMPL interrupt, the application must read the endpoint’s Transfer Size register to calculate the size of the payload in the memory. The received payload size can be less than the programmed transfer size.

• Payload size in memory = application-programmed initial transfer size – core updated final transfer size • Number of USB packets in which this payload was received = application-programmed initial packet count – core updated final packet count.

• If for some reason, the host stops sending tokens, there are no interrupts to the application, and the application must timeout on its own.

5. The assertion of the USB_DOEPx_INT.XFERCOMPL interrupt marks the completion of the interrupt OUT data transfer. This interrupt does not necessarily mean that the data in memory is good.

6. Read the USB_DOEPx_TSIZ register to determine the size of the received transfer and to determine the validity of the data received in the frame.

Internal Data Flow

1. The application must set the Transfer Size and Packet Count fields in the endpoint-specific registers, clear the NAK bit, and enable the endpoint to receive the data.

• The application must enable the USB_DCTL.IGNRFRMNUM

2. When an interrupt OUT endpoint is enabled by setting the Endpoint Enable and clearing the NAK bits, the Even/Odd frame will be ignored by the core.

1. Once the NAK bit is cleared, the core starts receiving data and writes it to the receive FIFO, as long as there is space in the receive FIFO. For every data packet received on the USB, the data packet and its status are written to the receive FIFO. Every packet (maximum packet size or short packet) written to the receive FIFO decrements the Packet Count field for that endpoint by 1.

• OUT data packets received with Bad Data CRC or any packet error are flushed from the receive FIFO automatically.

• Interrupt packets with PID errors are not passed to application. Core discards the packet, sends ACK and does not decrement packet count.

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• If there is no space in the receive FIFO, interrupt data packets are ignored and not written to the receive FIFO. Additionally, interrupt OUT tokens receive a NAK handshake reply.

2. When the packet count becomes 0 or when a short packet is received on the endpoint, the NAK bit for that endpoint is set. Once the NAK bit is set, the isochronous or interrupt data packets are ignored and not written to the receive FIFO, and interrupt OUT tokens receive a NAK handshake reply.

3. After the data is written to the receive FIFO, the core’s DMA engine reads the data from the receive FIFO and writes it to external memory, one packet at a time per endpoint.

4. At the end of every packet write on the AHB to external memory, the transfer size for the endpoint is decremented by the size of the written packet.

5. The OUT Data Transfer Completed pattern for an OUT endpoint is written to the receive FIFO on one of the following conditions.

• The transfer size is 0 and the packet count is 0.

• The last OUT data packet written to the receive FIFO is a short packet (0 < packet size < maximum packet size) 6. When either the application or the DMA pops this entry (OUT Data Transfer Completed), a Transfer Completed interrupt is generated for the endpoint and the endpoint enable is cleared.

15.4.4.2.2.11 Generic Isochronous OUT Data Transfers Using Periodic Transfer Interrupt Feature

This section describes a regular isochronous OUT data transfer with the Periodic Transfer Interrupt feature.

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the host, it must initialize an endpoint

as described in Endpoint Initialization (p. 257) . For packet writes in Slave mode, see: Packet Read from FIFO in Slave Mode (p. 266) .

Application Requirements

1. Before setting up ISOC OUT transfers spanned across multiple frames, the application must allocate buffer in the memory to accommodate all data to be received as part of the OUT transfers, then program that buffer’s size and start address in the endpoint-specific registers.

• The application must mask the USB_GINTSTS.INCOMPLP (Incomplete ISO OUT).

• The application must enable the USB_DCTL.IGNRFRMNUM

2. For ISOC transfers, the Transfer Size field in the USB_DOEPx_TSIZ.XFERSIZE register must be a multiple of the maximum packet size of the endpoint, adjusted to the DWORD boundary. The Transfer Size programmed can span across multiple frames based on the periodicity after which the application wants to receive the USB_DOEPx_INT.XFERCOMPL interrupt • transfer size[epnum] = n * (mps[epnum] + 4 - (mps[epnum] mod 4)) • packet count[epnum] = n • n > 0 (Higher value of n reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt) • 1 =< packet count[epnum] =< n (Higher value of n reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt).

3. In DMA mode, the core stores a received data packet in the memory, always starting on a DWORD boundary. If the maximum packet size of the endpoint is not a multiple of 4, the core inserts byte pads at end of a maximum-packet-size packet up to the end of the DWORD. The application will not be informed about the frame number and the PID value on which a specific OUT packet has been received.

4. The assertion of the USB_DOEPx_INT.XFERCOMPL interrupt marks the completion of the isochronous OUT data transfer. This interrupt does not necessarily mean that the data in memory is good.

• On USB_DOEPx_INT.XFERCOMPL, the application must read the endpoint’s Transfer Size register to calculate the size of the payload in the memory.

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• Number of USB packets in which this payload was received = application-programmed initial packet count – core updated final packet count.

• If for some reason, the host stop sending tokens, there will be no interrupt to the application, and the application must timeout on its own.

5. The assertion of the USB_DOEPx_INT.XFERCOMPL can also mark a packet drop on USB due to unavailability of space in the RxFifo or due to any packet errors.

• The application must read the USB_DOEPx_INT.PKTDRPSTS (USB_DOEPx_INT.Bit[11] is now used as the USB_DOEPx_INT.PKTDRPSTS) register to differentiate whether the USB_DOEPx_INT.XFERCOMPL was generated due to the normal end of transfer or due to dropped packets. In case of packets being dropped on the USB due to unavailability of space in the RxFifo or due to any packet errors the endpoint enable bit is cleared.

• In case of packet drop on the USB application must re-enable the endpoint after recalculating the values USB_DOEPx_TSIZ.XFERSIZE and USB_DOEPx_TSIZ.PKTCNT.

• Payload size in memory = application-programmed initial transfer size - core updated final transfer size • Number of USB packets in which this payload was received = application-programmed initial packet count - core updated final packet count.

Note

Due to application latencies it is possible that DOEPINT.XFERCOMPL interrupt is generated without DOEPINT.PKTDRPSTS being set, This scenario is possible only if back to-back packets are dropped for consecutive frames and the PKTDRPSTS is merged, but the XFERSIZE and PktCnt values for the endpoint are nonzero. In this case, the application must proceed further by programming the PKTCNT and XFERSIZE register for the next frame, as it would if PKTDRPSTS were being set.

Figure 15.23 (p. 276) gives the application flow for Isochronous OUT Periodic Transfer Interrupt

feature.

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...the world's most energy friendly wireless MCUs Figure 15.23. ISOC OUT Application Flow for Periodic Transfer Interrupt Feature Note: 1 . ( micro-) frame number and PID field are not updated for Periodic OUT packets 2 . In Periodic OUT transfers . The application must reenable the endpoint with recalculated values of XferSize and PktCnt 3 . The application must reenable the endpoint after dropped packets for ISOC OU

START Int ialize variables Program t he DMA address USB_DOEPx _DMA =

START Address of the Data Memory

Program Xfer _ size regist er USB_DOEPx _TSIZ.XFERSIZE

XferSize Spanning across multiple Xfers

USB_DOEPx _TSIZ.

.PKTCNT Program t he Global INT STS

Program PktCnt for multiple Xfers

INCOMPLPMSK = 0

/ / Mask IncompISOCOUT Interrupt

Program EP Ct rl regist er t o st art t he x fer USB_DOEPx _CTL . CNAK = USB_DOEPx _CTL .EPENA

USB_DOEPx _CTL . SNAK USB_DOEPx _CTL .EPDIS

= = = Wait for USB_DOEPx _INT. XFERCOMPL int errupt and report error if t im eout ex pires Re - com put e XFERSIZE and PKTCNT NO Received Short Packet If USB_DOEPx _TSIZ. PKTCNT= =0 YES NO If USB_DOEPx _INT. PKTDRPSTS = =1 YES ISOC OUT Pkt Drop YES End of Transfer Ret urn NO YES Received Short Packet NO ERROR

Internal Data Flow

1. The application must set the Transfer Size, Packets to be received in a frame and Packet Count Fields in the endpoint-specific registers, clear the NAK bit, and enable the endpoint to receive the data.

2. When an isochronous OUT endpoint is enabled by setting the Endpoint Enable and clearing the NAK bits, the Even/Odd frame will be ignored by the core.

3. Once the NAK bit is cleared, the core starts receiving data and writes it to the receive FIFO, as long as there is space in the receive FIFO. For every data packet received on the USB, the data packet and its status are written to the receive FIFO. Every packet (maximum packet size or short packet) written to the receive FIFO decrements the Packet Count field for that endpoint by 1.

4. When the packet count becomes 0 or when a short packet is received on the endpoint, the NAK bit for that endpoint is set. Once the NAK bit is set, the ISOC packets are ignored and not written to the receive FIFO.

5. After the data is written to the receive FIFO, the core’s DMA engine, reads the data from the receive FIFO and writes it to external memory, one packet at a time per endpoint.

6. At the end of every packet write on the AHB to external memory, the transfer size for the endpoint is decremented by the size of the written packet.

7. The OUT Data Transfer Completed pattern for an OUT endpoint is written to the receive FIFO on one of the following conditions.

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• The last OUT data packet written to the receive FIFO is a short packet (0 < packet size < maximum packet size).

8. When the DMA pops this entry (OUT Data Transfer Completed), a Transfer Completed interrupt is generated for the endpoint or the endpoint enable is cleared.

9. OUT data packets received with Bad Data CRC or any packet error are flushed from the receive FIFO automatically.

• In these two cases, the packet count and transfer size registers are not decremented because no data is written to the receive FIFO.

Figure 15.24. Isochronous OUT Core Internal Flow for Periodic Transfer Interrupt Feature

START

A

NO

If (USB_DOEPx _CTL.CNAK = 0b1) && (USB_DOEPx _CTL.EPENA = 0b1) && (DCTL.IGNRFRMNUM = 0b1) &&

NO

OUT Token From Host

YES

Check RXFifo Space Available

YES

NOTE 1 . 2 . 3 . Any Short Packet 4 . 5 . Core will write data to only DWORD Aligned addresses including zero length packet PacketDrop due to unAvailability of Space in RxFifo will generate XferComplete Immediately PktDrop due to EndPoint being disabled will generate XferComplete at End of periodic Frame interval

Disable endpoint YES Receive Pkt and St ore in RXFifo Pkt Cnt -1 NO Received Short Packet Pkt Cnt - 1 DMA Pop Rx Fifo XferSize Max Pkt Size USB_DOEPx _INT.XFERCOMPL = 1 DMA Pop Rx Fifo XferSize Act Pkt Size YES NO

A

NO YES ret urn

Received will generate XferComplete Interrupt

NO

If End Of PerFrInt ISOC Out Packet Naked

YES Disable endpoint

15.4.4.2.2.12 Incomplete Isochronous OUT Data Transfers in DMA and Slave Modes

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the host, it must initialize an endpoint

as described in Endpoint Initialization (p. 257) . See Packet Read from FIFO in Slave Mode (p. 266) .

This section describes the application programming sequence when isochronous OUT data packets are dropped inside the core.

Internal Data Flow

1. For isochronous OUT endpoints, the USB_DOEPx_INT.XFERCOMPL interrupt possibly is not always asserted. If the core drops isochronous OUT data packets, the application could fail to detect the USB_DOEPx_INT.XFERCOMPL interrupt under the following circumstances.

• When the receive FIFO cannot accommodate the complete ISO OUT data packet, the core drops the received ISO OUT data.

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2. When the core detects an end of periodic frame before transfer completion to all isochronous OUT endpoints, it asserts the USB_GINTSTS.INCOMPLP (Incomplete Isochronous OUT data) interrupt, indicating that a USB_DOEPx_INT.XFERCOMPL interrupt is not asserted on at least one of the isochronous OUT endpoints. At this point, the endpoint with the incomplete transfer remains enabled, but no active transfers remains in progress on this endpoint on the USB.

3. This step is applicable only if the core is operating in slave mode. Application Programming Sequence 4. This step is applicable only if the core is operating in slave mode. Asserting the USB_GINTSTS.INCOMPLP (Incomplete Isochronous OUT data) interrupt indicates that in the current frame, at least one isochronous OUT endpoint has an incomplete transfer.

5. If this occurs because isochronous OUT data is not completely emptied from the endpoint, the application must ensure that the DMA or the application empties all isochronous OUT data (data and status) from the receive FIFO before proceeding.

• When all data is emptied from the receive FIFO, the application can detect the USB_DOEPx_INT.XFERCOMPL interrupt. In this case, the application must re-enable the endpoint

to receive isochronous OUT data in the next frame, as described in Control Read Transfers (SETUP, Data IN, Status OUT) (p. 264) .

6. When it receives a USB_GINTSTS.incomplete Isochronous OUT data interrupt, the application must read the control registers of all isochronous OUT endpoints (USB_DOEPx_CTL) to determine which endpoints had an incomplete transfer in the current frame. An endpoint transfer is incomplete if both the following conditions are met.

• USB_DOEPx_CTL.DPIDEOF (Even/Odd frame) = USB_DSTS.SOFFN[0] • USB_DOEPx_CTL.EPENA (Endpoint Enable) = 1 7. The previous step must be performed before the USB_GINTSTS.SOF interrupt is detected, to ensure that the current frame number is not changed.

8. For isochronous OUT endpoints with incomplete transfers, the application must discard the data in the memory and disable the endpoint by setting the USB_DOEPx_CTL.EPDIS (Endpoint Disable) bit.

9. Wait for the USB_DOEPx_INT.EPDIS (Endpoint Disabled) interrupt and enable the endpoint to

receive new data in the next frame as explained in Control Read Transfers (SETUP, Data IN, Status OUT) (p. 264) .

• Because the core can take some time to disable the endpoint, the application possibly is not able to receive the data in the next frame after receiving bad isochronous data.

15.4.4.2.3 IN Data Transfers in Slave and DMA Modes

This section describes the internal data flow and application-level operations during IN data transfers.

• Packet Write in Slave Mode (p. 279) • Setting Global Non-Periodic IN Endpoint NAK (p. 279) • Setting IN Endpoint NAK (p. 279)

• IN Endpoint Disable (p. 280)

• Bulk IN Stall (p. 281) • Incomplete Isochronous IN Data Transfers (p. 281)

• Stalling Non-Isochronous IN Endpoints (p. 282)

• Worst-Case Response Time (p. 283) • Choosing the Value of USB_GUSBCFG.USBTRDTIM (p. 283)

• Handling Babble Conditions (p. 284) • Generic Non-Periodic (Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode (p. 284)

• Examples (p. 286)

• Generic Periodic IN Data Transfers Without Thresholding Using the Periodic Transfer Interrupt Feature (p. 291)

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15.4.4.2.3.1 Packet Write in Slave Mode

This section describes how the application writes data packets to the endpoint FIFO in Slave mode.

1. The application can either choose polling or interrupt mode.

• In polling mode, application monitors the status of the endpoint transmit data FIFO, by reading the USB_DIEPx_TXFSTS register, to determine, if there is enough space in the data FIFO.

• In interrupt mode, application waits for the USB_DIEPx_INT.TXFEMP interrupt and then reads the USB_DIEPx_TXFSTS register, to determine, if there is enough space in the data FIFO.

• To write a single non-zero length data packet, there must be space to write the entire packet is the data FIFO.

• For writing zero length packet, application must not look for FIFO space.

2. Using one of the above mentioned methods, when the application determines that there is enough space to write a transmit packet, the application must first write into the endpoint control register, before writing the data into the data FIFO. The application, typically must do a read modify write on the USB_DIEPx_CTL, to avoid modifying the contents of the register, except for setting the Endpoint Enable bit.

The application can write multiple packets for the same endpoint, into the transmit FIFO, if space is available. For periodic IN endpoints, application must write packets only for one frame. It can write packets for the next periodic transaction, only after getting transfer complete for the previous transaction.

15.4.4.2.3.2 Setting Global Non-Periodic IN Endpoint NAK Internal Data Flow

1. When the application sets the Global Non-periodic IN NAK bit (USB_DCTL.SGNPINNAK), the core stops transmitting data on the non-periodic endpoint, irrespective of data availability in the Non periodic Transmit FIFO.

2. Non-isochronous IN tokens receive a NAK handshake reply 3. The core asserts the USB_DCTL.SGNPINNAK bit.

USB_GINTSTS.GINNAKEFF interrupt in response to the 4. Once the application detects this interrupt, it can assume that the core is in the Global Non-periodic IN NAK mode. The application can clear this interrupt by clearing the USB_DCTL.SGNPINNAK bit.

Application Programming Sequence

1. To stop transmitting any data on non-periodic IN endpoints, the application must set the USB_DCTL.SGNPINNAK bit. To set this bit, the following field must be programmed • USB_DCTL.SGNPINNAK = 1 2. Wait for the assertion of the USB_GINTSTS.GINNAKEFF interrupt. This interrupt indicates the core has stopped transmitting data on the non-periodic endpoints.

3. The core can transmit valid non-periodic IN data after the application has set the USB_DCTL.SGNPINNAK bit, but before the assertion of the USB_GINTSTS.GINNAKEFF interrupt.

4. The application can optionally mask this interrupt temporarily by writing to the USB_GINTMSK.GINNAKEFFMSK bit.

• USB_GINTMSK.GINNAKEFFMSK = 0 5. To exit Global Non-periodic IN NAK mode, the application must clear the USB_DCTL.SGNPINNAK.

This also clears the USB_GINTSTS.GINNAKEFF interrupt.

• USB_DCTL.SGNPINNAK = 1 6. If the application has masked this interrupt earlier, it must be unmasked as follows: • USB_GINTMSK.GINNAKEFFMSK = 1

15.4.4.2.3.3 Setting IN Endpoint NAK Internal Data Flow

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1. When the application sets the IN NAK for a particular endpoint, the core stops transmitting data on the endpoint, irrespective of data availability in the endpoint’s transmit FIFO.

2. Non-isochronous IN tokens receive a NAK handshake reply • Isochronous IN tokens receive a zero-data-length packet reply 3. The core asserts the USB_DIEPx_INT.INEPNAKEFF (IN NAK Effective) interrupt in response to the USB_DIEPx_CTL.SNAK (Set NAK) bit.

4. Once this interrupt is seen by the application, the application can assume that the endpoint is in IN NAK mode. This interrupt can be cleared by the application by setting the USB_DIEPx_CTL. Clear NAK bit.

Application Programming Sequence

1. To stop transmitting any data on a particular IN endpoint, the application must set the IN NAK bit. To set this bit, the following field must be programmed.

• USB_DIEPx_CTL.SNAK = 1 2. Wait for assertion of the USB_DIEPx_INT.INEPNAKEFF (NAK Effective) interrupt. This interrupt indicates the core has stopped transmitting data on the endpoint.

3. The core can transmit valid IN data on the endpoint after the application has set the NAK bit, but before the assertion of the NAK Effective interrupt.

4. The application can mask this interrupt USB_DIEPMSK.INEPNAKEFFMSK (NAK Effective) bit.

temporarily by writing to the • USB_DIEPMSK.INEPNAKEFFMSK (NAK Effective) = 0 5. To exit Endpoint NAK mode, the application must clear the USB_DIEPx_CTL.NAK status. This also clears the USB_DIEPx_INT.INEPNAKEFF (NAK Effective) interrupt.

• USB_DIEPx_CTL.CNAK = 1 6. If the application masked this interrupt earlier, it must be unmasked as follows: • USB_DIEPMSK.INEPNAKEFFMSK (NAK Effective) = 1

15.4.4.2.3.4 IN Endpoint Disable

Use the following sequence to disable a specific IN endpoint (periodic/non-periodic) that has been previously enabled.

Application Programming Sequence:

1. In Slave mode, the application must stop writing data on the AHB, for the IN endpoint to be disabled.

2. The application must set the endpoint in NAK mode. See Setting IN Endpoint NAK (p. 279) .

• USB_DIEPx_CTL.SNAK = 1 3. Wait for USB_DIEPx_INT.INEPNAKEFF (NAK Effective) interrupt.

4. Set the following bits in the USB_DIEPx_CTL register for the endpoint that must be disabled.

• USB_DIEPx_CTL.EPDIS (Endpoint Disable) = 1 • USB_DIEPx_CTL.SNAK = 1 5. Assertion of USB_DIEPx_INT.EPDISBLD (Endpoint Disabled) interrupt indicates that the core has completely disabled the specified endpoint. Along with the assertion of the interrupt, the core also clears the following bits.

• USB_DIEPx_CTL.EPENA = 0 • USB_DIEPx_CTL.EPDIS = 0 6. The application must read the USB_DIEPx_TSIZ register for the periodic IN EP, to calculate how much data on the endpoint was transmitted on the USB.

7. The application must flush the data in the Endpoint transmit FIFO, by setting the following fields in the USB_GRSTCTL register.

• USB_GRSTCTL.TXFNUM = Endpoint Transmit FIFO Number • USB_GRSTCTL.TXFFLSH = 1 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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The application must poll the USB_GRSTCTL register, until the TXFFLSH bit is cleared by the core, which indicates the end of flush operation. To transmit new data on this endpoint, the application can re-enable the endpoint at a later point.

15.4.4.2.3.5 Bulk IN Stall

These notes refer to Figure 15.25 (p. 281)

1. The application has scheduled an IN transfer on receiving the USB_DIEPx_INT.INTKNTXFEMP (IN Token Received When TxFIFO Empty) interrupt.

2. When the transfer is in progress, the application must force a STALL on the endpoint. This could be because the application has received a SetFeature.Endpoint Halt command. The application sets the Stall bit, disables the endpoint and waits for the USB_DIEPx_INT.EPDISBLD (Endpoint Disabled) interrupt. This generates STALL handshakes for the endpoint on the USB.

3. On receiving the interrupt, the application flushes the Non-periodic Transmit FIFO and clears the USB_DCTL.SGNPINNAK (Global IN NP NAK) bit.

4. On receiving the ClearFeature.Endpoint Halt command, the application clears the Stall bit.

5. The endpoint behaves normally and the application can re-enable the endpoint for new transfers

Figure 15.25. Bulk IN Stall

Host USB Device Application

IN NAK IN ACK IN STAL L INTKNTXFEMP INTR EPDisabled int r idle( wait_int r) set up_ np_in_ pkt x act_ 1 dat a rdy NPTXFEMP INT set up_ np_in_ pkt set_ st all ep_ disable; flush_ nper_ t x_ fifo; Clr Global IN NP Nak

1

do_in_ x fer

2 3 4

IN STAL L wait_for_ host/ app t o clr st all

5

clr_ st all IN NAK IN INTKNT XFEMP do_ in_ x fer new x act A CK

15.4.4.2.3.6 Incomplete Isochronous IN Data Transfers

This section describes what the application must do on an incomplete isochronous IN data transfer.

Internal Data Flow 1. An isochronous IN transfer is treated as incomplete in one of the following conditions.

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a. The core receives a corrupted isochronous IN token on at least one isochronous IN endpoint. In this case, the application detects a USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt.

b. The application or DMA is slow to write the complete data payload to the transmit FIFO and an IN token is received before the complete data payload is written to the FIFO. In this case, the application detects a USB_DIEPx_INT.INTKNTXFEMP (IN Token Received When TxFIFO Empty) interrupt. The application can ignore this interrupt, as it eventually results in a USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt at the end of periodic frame.

i. The core transmits a zero-length data packet on the USB in response to the received IN token.

2. In either of the aforementioned cases, in Slave mode, the application must stop writing the data payload to the transmit FIFO as soon as possible.

3. The application must set the NAK bit and the disable bit for the endpoint. In DMA mode, the core automatically stops fetching the data payload when the endpoint disable bit is set.

4. The core disables the endpoint, clears the disable bit, and asserts the Endpoint Disable interrupt for the endpoint.

Application Programming Sequence

1. The application can ignore the USB_DIEPx_INT.INTKNTXFEMP (IN Token Received When TxFIFO empty) interrupt on any isochronous IN endpoint, as it eventually results in a USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt.

2. Assertion of the USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt indicates an incomplete isochronous IN transfer on at least one of the isochronous IN endpoints.

3. The application must read the Endpoint Control register for all isochronous IN endpoints to detect endpoints with incomplete IN data transfers.

4. In Slave mode, the application must stop writing data to the Periodic Transmit FIFOs associated with these endpoints on the AHB.

5. In both modes of operation, program the following fields in the USB_DIEPx_CTL register to disable the endpoint.

• USB_DIEPx_CTL.SNAK = 1 • USB_DIEPx_CTL.EPDIS (Endpoint Disable) = 1 6. The USB_DIEPx_INT.EPDISBLD (Endpoint Disabled) interrupt’s assertion indicates that the core has disabled the endpoint.

• At this point, the application must flush the data in the associated transmit FIFO or overwrite the existing data in the FIFO by enabling the endpoint for a new transfer in the next frame. To flush the data, the application must use the USB_GRSTCTL register.

15.4.4.2.3.7 Stalling Non-Isochronous IN Endpoints

This section describes how the application can stall a non-isochronous endpoint.

Application Programming Sequence

1. Disable the IN endpoint to be stalled. Set the Stall bit as well.

2. USB_DIEPx_CTL.EPDIS (Endpoint Disable) = 1, when the endpoint is already enabled • USB_DIEPx_CTL.STALL = 1 • The Stall bit always takes precedence over the NAK bit 3. Assertion of the USB_DIEPx_INT.EPDISBLD (Endpoint Disabled) interrupt indicates to the application that the core has disabled the specified endpoint.

4. The application must flush the Non-periodic or Periodic Transmit FIFO, depending on the endpoint type. In case of a non-periodic endpoint, the application must re-enable the other non-periodic endpoints, which do not need to be stalled, to transmit data.

5. Whenever the application is ready to end the STALL handshake for the endpoint, the USB_DIEPx_CTL.STALL bit must be cleared.

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6. If the application sets or clears a STALL for an endpoint due to a SetFeature.Endpoint Halt command or ClearFeature.Endpoint Halt command, the Stall bit must be set or cleared before the application sets up the Status stage transfer on the control endpoint.

Special Case: Stalling the Control IN/OUT Endpoint

The core must stall IN/OUT tokens if, during the Data stage of a control transfer, the host sends more IN/OUT tokens than are specified in the SETUP packet. In this case, the application must to enable USB_DIEPx_INT.INTKNTXFEMP and USB_DOEPx_INT.OUTTKNEPDIS interrupts during the Data stage of the control transfer, after the core has transferred the amount of data specified in the SETUP packet. Then, when the application receives this interrupt, it must set the STALL bit in the corresponding endpoint control register, and clear this interrupt.

15.4.4.2.3.8 Worst-Case Response Time

When the acts as a device, there is a worst case response time for any tokens that follow an isochronous OUT. This worst case response time depends on the AHB clock frequency.

The core registers are in the AHB domain, and the core does not accept another token before updating these register values. The worst case is for any token following an isochronous OUT, because for an isochronous transaction, there is no handshake and the next token could come sooner. This worst case value is 7 PHY clocks in FS mode.

If this worst case condition occurs, the core responds to bulk/interrupt tokens with a NAK and drops isochronous and SETUP tokens. The host interprets this as a timeout condition for SETUP and retries the SETUP packet. For isochronous transfers, the INCOMPISOIN and INCOMPLP interrupts inform the application that isochronous IN/OUT packets were dropped.

15.4.4.2.3.9 Choosing the Value of USB_GUSBCFG.USBTRDTIM

The value in USB_GUSBCFG.USBTRDTIM is the time it takes for the MAC, in terms of PHY clocks after it has received an IN token, to get the FIFO status, and thus the first data from PFC (Packet FIFO Controller) block. This time involves the synchronization delay between the PHY and AHB clocks. This delay is 5 clocks.

Once the MAC receives an IN token, this information (token received) is synchronized to the AHB clock by the PFC (the PFC runs on the AHB clock). The PFC then reads the data from the SPRAM and writes it into the dual clock source buffer. The MAC then reads the data out of the source buffer (4 deep).

If the AHB is running at a higher frequency than the PHY (in Low-speed mode), the application can use

a smaller value for USB_GUSBCFG.USBTRDTIM. Figure 15.26 (p. 284) explains the 5-clock delay.

This diagram has the following signals: • tkn_rcvd: Token received information from MAC to PFC • dynced_tkn_rcvd: Doubled sync tkn_rcvd, from pclk to hclk domain • spr_read: Read to SPRAM • spr_addr: Address to SPRAM • spr_rdata: Read data from SPRAM • srcbuf_push: Push to the source buffer • srcbuf_rdata: Read data from the source buffer. Data seen by MAC The application can use the following formula to calculate the value of USB_GUSBCFG.USBTRDTIM: 4 * AHB Clock + 1 PHY Clock = (2 clock sync + 1 clock memory address + 1 clock memory data from sync RAM) + (1 PHY Clock (next PHY clock MAC can sample the 2-clock FIFO output) 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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Host USB Device Application

IN NAK INTKNTXFEMP INTR idle( wait_int r) IN ACK IN STAL L x act_ 1 dat a rdy set up_ np_in_ pkt NPTXFEMP INT set up_ np_in_ pkt EPDisabled int r set_ st all ep_ disable; flush_ nper_ t x_ fifo; Clr Global IN NP Nak

1

do_in_ x fer

2 3 4

IN STAL L wait_for_ host/ app t o clr st all

5

clr_ st all IN NAK IN INTKNT XFEMP do_ in_ x fer new x act A CK

15.4.4.2.3.10 Handling Babble Conditions

If receives a packet that is larger than the maximum packet size for that endpoint, the core stops writing data to the Rx buffer and waits for the end of packet (EOP). When the core detects the EOP, it flushes the packet in the Rx buffer and does not send any response to the host.

If the core continues to receive data at the EOF2 (the end of frame 2, which is very close to SOF), the core generates an early_suspend interrupt (USB_GINTSTS.ERLYSUSP). On receiving this interrupt, the application must check the erratic_error status bit (USB_DSTS.ERRTICERR). If this bit is set, the application must take it as a long babble and perform a soft reset.

15.4.4.2.3.11 Generic Non-Periodic (Bulk and Control) IN Data Transfers in DMA and Slave Mode

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the host, it must initialize an endpoint

as described in Endpoint Initialization (p. 257) . For packet writes in Slave mode, see: Packet Write in Slave Mode (p. 279) .

Application Requirements

1. Before setting up an IN transfer, the application must ensure that all data to be transmitted as part of the IN transfer is part of a single buffer, and must program the size of that buffer and its start address (in DMA mode) to the endpoint-specific registers.

2. For IN transfers, the Transfer Size field in the Endpoint Transfer Size register denotes a payload that constitutes multiple maximum-packet-size packets and a single short packet. This short packet is transmitted at the end of the transfer.

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• To transmit a few maximum-packet-size packets and a short packet at the end of the transfer: • Transfer size[epnum] = n * mps[epnum] + sp (where n is an integer >= 0, and 0 <= sp < mps[epnum]) • If (sp > 0), then packet count[epnum] = n + 1. Otherwise, packet count[epnum] = n a. To transmit a single zero-length data packet: • Transfer size[epnum] = 0 • Packet count[epnum] = 1 b. To transmit a few maximum-packet-size packets and a zero-length data packet at the end of the transfer, the application must split the transfer in two parts. The first sends maximum-packet-size data packets and the second sends the zero-length data packet alone.

c. First transfer: transfer size[epnum] = n * mps[epnum]; packet count = n; d. Second transfer: transfer size[epnum] = 0; packet count = 1; 3. In DMA mode, the core fetches an IN data packet from the memory, always starting at a DWORD boundary. If the maximum packet size of the IN endpoint is not a multiple of 4, the application must arrange the data in the memory with pads inserted at the end of a maximum-packet-size packet so that a new packet always starts on a DWORD boundary.

4. Once an endpoint is enabled for data transfers, the core updates the Transfer Size register. At the end of IN transfer, which ended with a Endpoint Disabled interrupt, the application must read the Transfer Size register to determine how much data posted in the transmit FIFO was already sent on the USB.

5. Data fetched into transmit FIFO = Application-programmed initial transfer size – core-updated final transfer size • Data transmitted on USB = (application-programmed initial packet count – Core updated final packet count) * mps[epnum] • Data yet to be transmitted on USB = (Application-programmed initial transfer size – data transmitted on USB)

Internal Data Flow

1. The application must set the Transfer Size and Packet Count fields in the endpoint-specific registers and enable the endpoint to transmit the data.

2. In Slave mode, the application must also write the required data to the transmit FIFO for the endpoint.

In DMA mode, the core fetches the data from memory according to the application setting for the endpoint.

3. Every time a packet is written into the transmit FIFO, either by the core’s internal DMA (in DMA mode) or the application (in Slave Mode), the transfer size for that endpoint is decremented by the packet size. The data is fetched from the memory (DMA/Application), until the transfer size for the endpoint becomes 0. After writing the data into the FIFO, the “number of packets in FIFO” count is incremented (this is a 3-bit count, internally maintained by the core for each IN endpoint transmit FIFO. The maximum number of packets maintained by the core at any time in an IN endpoint FIFO is eight). For zero-length packets, a separate flag is set for each FIFO, without any data in the FIFO.

4. Once the data is written to the transmit FIFO, the core reads it out upon receiving an IN token. For every non-isochronous IN data packet transmitted with an ACK handshake, the packet count for the endpoint is decremented by one, until the packet count is zero. The packet count is not decremented on a TIMEOUT.

5. For zero length packets (indicated by an internal zero length flag), the core sends out a zero-length packet for the IN token and decrements the Packet Count field.

6. If there is no data in the FIFO for a received IN token and the packet count field for that endpoint is zero, the core generates a IN Tkn Rcvd When FIFO Empty Interrupt for the endpoint, provided the endpoint NAK bit is not set. The core responds with a NAK handshake for non-isochronous endpoints on the USB.

7. For Control IN endpoint, if there is a TIMEOUT condition, the USB_DIEPx_INT.TIMEOUT interrupt is generated.

8. When the transfer size is 0 and the packet count is 0, the transfer complete interrupt for the endpoint is generated and the endpoint enable is cleared.

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Application Programming Sequence

1. Program the USB_DIEPx_TSIZ register with the transfer size and corresponding packet count. In DMA mode, also program the USB_DIEPx_DMAADDR register.

2. Program the USB_DIEPx_CTL register with the endpoint characteristics and set the CNAK and Endpoint Enable bits.

3. In slave mode when transmitting non-zero length data packet, the application must poll the USB_DIEPx_TXFSTS register (where x is the FIFO number associated with that endpoint) to determine whether there is enough space in the data FIFO. The application can optionally use USB_DIEPx_INT.TXFEMP before writing the data.

15.4.4.2.3.12 Examples Slave Mode Bulk IN Transaction

These notes refer to Figure 15.27 (p. 286) .

1. The host attempts to read data (IN token) from an endpoint.

2. On receiving the IN token on the USB, the core returns a NAK handshake, because no data is available in the transmit FIFO.

3. To indicate to the application that there was no data to send, the core generates a USB_DIEPx_INT.INTKNTXFEMP (IN Token Received When TxFIFO Empty) interrupt.

4. When data is ready, the application sets up the USB_DIEPx_TSIZ register with the Transfer Size and Packet Count fields.

5. The application writes one maximum packet size or less of data to the Non-periodic TxFIFO.

6. The host reattempts the IN token.

7. Because data is now ready in the FIFO, the core now responds with the data and the host ACKs it.

8. Because the XFERSIZE is now zero, the intended transfer is complete. The device core generates a USB_DIEPx_INT.XFERCOMPL interrupt.

9. The application processes the interrupt and uses the setting of the USB_DIEPx_INT.XFERCOMPL

interrupt bit to determine that the intended transfer is complete.

Figure 15.27. Slave Mode Bulk IN Transaction

Host 1 USB

IN NAK IN NAK

Device 3 2

IN

5 Application

INTKNTXFEMP INTR wait for x fer idle unt il int r new x fer rdy?

4

Yes wr_reg(ep. DIEPTSIZn ) x act_1 set up_np_ in_pkt()

6

IN

7 8 9

Tim eout = ACK XFERCOMPL INTR idle unt il int r 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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Slave Mode Bulk IN Transfer (Pipelined Transaction)

These notes refer to Figure 15.28 (p. 288)

1. The host attempts to read data (IN token) from an endpoint.

2. On receiving the IN token on the USB, the core returns a NAK handshake, because no data is available in the transmit FIFO.

3. To indicate that there was no data to send, the core generates an USB_DIEPx_INT.INTKNTXFEMP

(In Token Received When TxFIFO Empty) interrupt.

4. When data is ready, the application sets up the USB_DIEPx_TSIZ register with the transfer size and packet count.

5. The application writes one maximum packet size or less of data to the Non-periodic TxFIFO.

6. The host reattempts the IN token.

7. Because data is now ready in the FIFO, the core responds with the data, and the host ACKs it.

8. When the TxFIFO level falls below the halfway mark, the core generates a USB_GINTSTS.NPTXFEMP (NonPeriodic TxFIFO Empty) interrupt. This triggers the application to start writing additional data packets to the FIFO.

9. A data packet for the second transaction is ready in the TxFIFO.

10.A data packet for third transaction is ready in the TxFIFO while the data for the second packet is being sent on the bus.

11.The second data packet is sent to the host.

12.The last short packet is sent to the host.

13.Because the last packet is sent and XFERSIZE is now zero, the intended transfer is complete. The core generates a USB_DIEPx_INT.XFERCOMPL interrupt.

14.The application processes the interrupt and uses the setting of the USB_DIEPx_INT.XFERCOMPL

interrupt bit to determine that the intended transfer is complete 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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...the world's most energy friendly wireless MCUs Figure 15.28. Slave Mode Bulk IN Transfer (Pipelined Transaction)

Host USB Device Application 2 1

IN NAK

3

INTKNTXFEMP INTR

4

idle unt il int r wr_reg( x fer_ size_reg) pkt_ cnt = 1

6

x act_ 1 of 3 IN

5 7

x act_ 1 set up_ np_in_pkt NPTX FEMP

8

x act_2 3 ACK IN

9

x act_ 2

2 1 1

x act_3 x act_2

1 0

set up_ np_in_pkt set up_ np_in_pkt ACK x act_3 3 IN 1 byt e ACK

1 2 1 3 1 4

XFERCOMPL INTR idle unt il int r

Slave Mode Bulk IN Two-Endpoint Transfer

These notes refer to Figure 15.29 (p. 289)

1. The host attempts to read data (IN token) from endpoint 1.

2. On receiving the IN token on the USB, the core returns a NAK handshake, because no data is available in the transmit FIFO for endpoint 1, and generates a USB_DIEP1_INT.INTKNTXFEMP (In Token Received When TxFIFO Empty) interrupt.

3. The application processes the interrupt and initializes USB_DIEP1_TSIZ register with the Transfer Size and Packet Count fields. The application starts writing the transaction data to the transmit FIFO.

4. The application writes one maximum packet size or less of data for endpoint 1 to the Non-periodic TxFIFO.

5. Meanwhile, the host attempts to read data (IN token) from endpoint 2.

6. On receiving the IN token on the USB, the core returns a NAK handshake, because no data is available in the transmit FIFO for endpoint 2, and the core generates a USB_DIEP2_INT.INTKNTXFEMP (In Token Received When TxFIFO Empty) interrupt.

7. Because the application has completed writing the packet for endpoint 1, it initializes the USB_DIEP2_TSIZ register with the Transfer Size and Packet Count fields. The application starts writing the transaction data into the transmit FIFO for endpoint 2.

8. The host repeats its attempt to read data (IN token) from endpoint 1.

9. Because data is now ready in the TxFIFO, the core returns the data, which the host ACKs.

10.Meanwhile, the application has initialized the data for the next two packets in the TxFIFO (ep2.xact1

and ep1.xact2, in order).

11.The host repeats its attempt to read data (IN token) from endpoint 2.

12.Because endpoint 2’s data is ready, the core responds with the data (ep2.xact_1), which the host ACKs.

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13.Meanwhile, the application has initialized the data for the next two packets in the TxFIFO (ep2.xact2

and ep1.xact3, in order). The application has finished initializing data for the two endpoints involved in this scenario.

14.The host repeats its attempt to read data (IN token) from endpoint 1.

15.Because data is now ready in the FIFO, the core responds with the data, which the host ACKs.

16.The host repeats its attempt to read data (IN token) from endpoint 2.

17.With data now ready in the FIFO, the core responds with the data, which the host ACKs.

18.With the last packet for endpoint 2 sent and its XFERSIZE now zero, the intended transfer is complete.

The core generates a USB_DIEP2_INT.XFERCOMPL interrupt for this endpoint.

19.The application processes the interrupt and uses the setting of the USB_DIEP2_INT.XFERCOMPL

interrupt bit to determine that the intended transfer on endpoint 2 is complete.

20.The host repeats its attempt to read data (IN token) from endpoint 1 (last transaction).

21.With data now ready in the FIFO, the core responds with the data, which the host ACKs.

22.Because the last endpoint one packet has been sent and XFERSIZE is now zero, the intended transfer is complete. The core generates a USB_DIEP1_INT.XFERCOMPL interrupt for this endpoint.

23.The application processes the interrupt and uses the setting of the USB_DIEP1_INT.XFERCOMPL

interrupt bit to determine that the intended transfer on endpoint 1 is complete.

Figure 15.29. Slave Mode Bulk IN Two-Endpoint Transfer

Host 1 8 5 11 USB

IN, ep1 NAK

6 2 Device

IN, ep2 NA K IN,ep1 ep1.xact_1

9

512 bytes .

ACK IN, ep2 512 bytes

12

ep1.xact_2

ep2.xact_1

13 10 Application

EP_NUM 1 register set XferSize = 1025 bytes PktCnt = 3 EPEna = 1 ep1.InTkn

TxF Emp intr

3

idle until intr ep2.InTknTxF

Emp intr

7

EP_NUM 2 registers XferSize = 522 bytes PktCnt = 2 EPEna = 1

ep2 drvr

idle until intr

4

ep1.setup_np_in_pkt

ep1.setup_np_in_pkt

ep2.setup_np_in_pkt

14

ep2.setup_np_in_pkt

ACK IN, ep1

15

ep2.xact_2

ep1.xact_2

512 bytes ep1.xact_3

ep1.xact_2

ep1.setup_np_in_pkt

16 20

ACK IN, ep2 10 bytes

17 18 19

idle until intr xfer_complete =1 IN,ep1 1 byte ACK

21 22

ep1.Xfer

Comp intr ep2.XferCompl intr xfer_complete = 1 idle until intr

23 15.4.4.2.3.13 Generic Periodic IN (Interrupt and Isochronous) Data Transfers

To initialize the core after power-on reset, the application must follow the sequence in Overview: Programming the Core (p. 222) . Before it can communicate with the host, it must initialize an endpoint

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as described in Endpoint Initialization (p. 257) . For packet writes in Slave mode, see: Packet Write in Slave Mode (p. 279) .

Application Requirements

1. Application requirements 1, 2, 3, and 4 of Generic Non-Periodic (Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode (p. 284) also apply to periodic IN data transfers,

except for a slight modification of Requirement 2.

• The application can only transmit multiples of maximum-packet-size data packets or multiples of maximum-packet-size packets, plus a short packet at the end. To transmit a few maximum-packet size packets and a short packet at the end of the transfer, the following conditions must be met.

• transfer size[epnum] = n * mps[epnum] + sp(where n is an integer # 0, and 0 >= sp < mps[epnum]) • If (sp > 0), packet count[epnum] = n + 1Otherwise, packet count[epnum] = n; • mc[epnum] = packet count[epnum] • The application cannot transmit a zero-length data packet at the end of transfer. It can transmit a single zero-length data packet by it self. To transmit a single zero-length data packet, • transfer size[epnum] = 0 • packet count[epnum] = 1 • mc[epnum] = packet count[epnum] 2. The application can only schedule data transfers 1 frame at a time.

• (USB_DIEPx_TSIZ.MC – 1) * USB_DIEPx_CTL.MPS =< USB_DIEPx_TSIZ.XFERSIZE =< USB_DIEPx_TSIZ.MC * USB_DIEPx_CTL.MPS

• USB_DIEPx_TSIZ.PKTCNT = USB_DIEPx_TSIZ.MC

• If USB_DIEPx_TSIZ.XFERSIZE < USB_DIEPx_TSIZ.MC * USB_DIEPx_CTL.MPS, the last data packet of the transfer is a short packet.

3. This step is not applicable for isochronous data transfers, only for interrupt transfers.

The application can schedule data transfers for multiple frames, only if multiples of max packet sizes (up to 3 packets), must be transmitted every frame. This is can be done, only when the core is operating in DMA mode. This is not a recommended mode though.

• ((n*USB_DIEPx_TSIZ.MC) - 1)*USB_DIEPx_CTL.MPS <= USB_DIEPx_TSIZ.XFERSIZE <= n*USB_DIEPx_TSIZ.MC*USB_DIEPx_CTL.MPS

• USB_DIEPx_TSIZ.PKTCNT = n*USB_DIEPx_TSIZ.MC

• n is the number of frames for which the data transfers are scheduled Data Transmitted per frame in this case would be USB_DIEPx_TSIZ.MC*USB_DIEPx_CTL.MPS, in all the frames except the last one. In the frame “n”, the data transmitted would be (USB_DIEPx_TSIZ.XFERSIZE - (n-1)*USB_DIEPx_TSIZ.MC*USB_DIEPx_CTL.MPS) 4. For Periodic IN endpoints, the data must always be prefetched 1 frame ahead for transmission in the next frame. This can be done, by enabling the Periodic IN endpoint 1 frame ahead of the frame in which the data transfer is scheduled.

5. The complete data to be transmitted in the frame must be written into the transmit FIFO (either by the application or the DMA), before the Periodic IN token is received. Even when 1 DWORD of the data to be transmitted per frame is missing in the transmit FIFO when the Periodic IN token is received, the core behaves as when the FIFO was empty. When the transmit FIFO is empty, 6. A zero data length packet would be transmitted on the USB for ISO IN endpoints • A NAK handshake would be transmitted on the USB for INTR IN endpoints 7. For a High Bandwidth IN endpoint with three packets in a frame, the application can program the endpoint FIFO size to be 2*max_pkt_size and have the third packet load in after the first packet has been transmitted on the USB.

Internal Data Flow

1. The application must set the Transfer Size and Packet Count fields in the endpoint-specific registers and enable the endpoint to transmit the data.

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2. In Slave mode, the application must also write the required data to the associated transmit FIFO for the endpoint. In DMA mode, the core fetches the data for the endpoint from memory, according to the application setting.

3. Every time either the core’s internal DMA (in DMA mode) or the application (in Slave mode) writes a packet to the transmit FIFO, the transfer size for that endpoint is decremented by the packet size. The data is fetched from DMA or application memory until the transfer size for the endpoint becomes 0.

4. When an IN token is received for an periodic endpoint, the core transmits the data in the FIFO, if available. If the complete data payload (complete packet) for the frame is not present in the FIFO, then the core generates an IN Token Received When TxFIFO Empty Interrupt for the endpoint.

• A zero-length data packet is transmitted on the USB for isochronous IN endpoints • A NAK handshake is transmitted on the USB for interrupt IN endpoints 5. The packet count for the endpoint is decremented by 1 under the following conditions: • For isochronous endpoints, when a zero- or non-zero-length data packet is transmitted • For interrupt endpoints, when an ACK handshake is transmitted • When the transfer size and packet count are both 0, the Transfer Completed interrupt for the endpoint is generated and the endpoint enable is cleared.

6. At the “Periodic frame Interval” (controlled by USB_DCFG.PERFRINT), when the core finds non empty any of the isochronous IN endpoint FIFOs scheduled for the current frame non-empty, the core generates a USB_GINTSTS.INCOMPISOIN interrupt.

Application Programming Sequence (Transfer Per Frame)

1. Program the USB_DIEPx_TSIZ register. In DMA mode, also program the USB_DIEPx_DMAADDR register.

2. Program the USB_DIEPx_CTL register with the endpoint characteristics and set the CNAK and Endpoint Enable bits.

3. In Slave mode, write the data to be transmitted in the next frame to the transmit FIFO.

4. Asserting the USB_DIEPx_INT.INTKNTXFEMP (In Token Received When TxFifo Empty) interrupt indicates that either the DMA or application has not yet written all data to be transmitted to the transmit FIFO.

5. If the interrupt endpoint is already enabled when this interrupt is detected, ignore the interrupt. If it is not enabled, enable the endpoint so that the data can be transmitted on the next IN token attempt.

• If the isochronous endpoint is already enabled when this interrupt is detected, see Incomplete Isochronous IN Data Transfers (p. 281) for more details.

6. The core handles timeouts internally on interrupt IN endpoints programmed as periodic endpoints without application intervention. The application, thus, never detects a USB_DIEPx_INT.TIMEOUT

interrupt for periodic interrupt IN endpoints.

7. Asserting the USB_DIEPx_INT.XFERCOMPL interrupt with no USB_DIEPx_INT.INTKNTXFEMP (In Token Received When TxFifo Empty) interrupt indicates the successful completion of an isochronous IN transfer. A read to the USB_DIEPx_TSIZ register must indicate transfer size = 0 and packet count = 0, indicating all data is transmitted on the USB.

8. Asserting the USB_DIEPx_INT.XFERCOMPL interrupt, with or without indicate transfer size = 0 and packet count = 0, indicating all data is transmitted on the USB.

the USB_DIEPx_INT.INTKNTXFEMP (In Token Received When TxFifo Empty) interrupt, indicates the successful completion of an interrupt IN transfer. A read to the USB_DIEPx_TSIZ register must 9. Asserting the USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt with none of the aforementioned interrupts indicates the core did not receive at least 1 periodic IN token in the current frame.

10.For isochronous IN endpoints, see Incomplete Isochronous IN Data Transfers (p. 281) , for more

details.

15.4.4.2.3.14 Generic Periodic IN Data Transfers Using the Periodic Transfer Interrupt Feature

This section describes a typical Periodic IN (ISOC / INTR) data transfer with the Periodic Transfer Interrupt feature.

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1. Before setting up an IN transfer, the application must ensure that all data to be transmitted as part of the IN transfer is part of a single buffer, and must program the size of that buffer and its start address (in DMA mode) to the endpoint-specific registers.

2. For IN transfers, the Transfer Size field in the Endpoint Transfer Size register denotes a payload that constitutes multiple maximum-packet-size packets and a single short packet. This short packet is transmitted at the end of the transfer.

a. To transmit a few maximum-packet-size packets and a short packet at the end of the transfer: • Transfer size[epnum] = n * mps[epnum] + sp (where n is an integer > 0, and 0 < sp < mps[epnum]. A higher value of n reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt) • If (sp > 0), then packet count[epnum] = n + 1. Otherwise, packet count[epnum] = n b. To transmit a single zero-length data packet: • Transfer size[epnum] = 0 • Packet count[epnum] = 1 c. To transmit a few maximum-packet-size packets and a zero-length data packet at the end of the transfer, the application must split the transfer in two parts. The first sends maximum-packet-size data packets and the second sends the zero-length data packet alone.

• First transfer: transfer size[epnum] = n * mps[epnum]; packet count = n; • Second transfer: transfer size[epnum] = 0; packet count = 1; d. The application can only transmit multiples of maximum-packet-size data packets or multiples of maximum-packet-size packets, plus a short packet at the end. To transmit a few maximum-packet size packets and a short packet at the end of the transfer, the following conditions must be met.

• transfer size[epnum] = n * mps[epnum] + sp (where n is an integer > 0, and 0 < sp < mps[epnum]) • If (sp > 0), packet count[epnum] = n + 1 Otherwise, packet count[epnum] = n; • mc[epnum] = number of packets to be sent out in a frame.

e. The application cannot transmit a zero-length data packet at the end of transfer. It can transmit a single zero-length data packet by itself. To transmit a single zero-length data packet, • transfer size[epnum] = 0 • packet count[epnum] = 1 • mc[epnum] = packet count[epnum] 3. In DMA mode, the core fetches an IN data packet from the memory, always starting at a DWORD boundary. If the maximum packet size of the IN endpoint is not a multiple of 4, the application must arrange the data in the memory with pads inserted at the end of a maximum-packet-size packet so that a new packet always starts on a DWORD boundary.

4. Once an endpoint is enabled for data transfers, the core updates the Transfer Size register. At the end of IN transfer, which ended with a Endpoint Disabled interrupt, the application must read the Transfer Size register to determine how much data posted in the transmit FIFO was already sent on the USB.

• Data fetched into transmit FIFO = Application-programmed initial transfer size - core-updated final transfer size • Data transmitted on USB = (application-programmed initial packet count - Core updated final packet count) * mps[epnum] • Data yet to be transmitted on USB = (Application-programmed initial transfer size - data transmitted on USB) 5. The application can schedule data transfers for multiple frames, only if multiples of max packet sizes (up to 3 packets), must be transmitted every frame. This is can be done, only when the core is operating in DMA mode.

• ((n*USB_DIEPx_TSIZ.MC) - 1)*USB_DIEPx_CTL.MPS <= USB_DIEPx_TSIZ.XFERSIZE <= n*USB_DIEPx_TSIZ.MC*USB_DIEPx_CTL.MPS

• USB_DIEPx_TSIZ.PKTCNT = n*USB_DIEPx_TSIZ.MC

• n is the number of frames for which the data transfers are scheduled. Data Transmitted per frame in this case is USB_DIEPx_TSIZ.MC*USB_DIEPx_CTL.MPS in all frames except the last one. In frame n, the data transmitted is (USB_DIEPx_TSIZ.XFERSIZE – (n – 1) * USB_DIEPx_TSIZ.MC

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6. For Periodic IN endpoints, the data must always be prefetched 1 frame ahead for transmission in the next frame. This can be done, by enabling the Periodic IN endpoint 1 frame ahead of the frame in which the data transfer is scheduled.

7. The complete data to be transmitted in the frame must be written into the transmit FIFO, before the Periodic IN token is received. Even when 1 DWORD of the data to be transmitted per frame is missing in the transmit FIFO when the Periodic IN token is received, the core behaves as when the FIFO was empty. When the transmit FIFO is empty, • A zero data length packet would be transmitted on the USB for ISOC IN endpoints • A NAK handshake would be transmitted on the USB for INTR IN endpoints • USB_DIEPx_TSIZ.PKTCNT is not decremented in this case.

8. For a High Bandwidth IN endpoint with three packets in a frame, the application can program the endpoint FIFO size to be 2 * max_pkt_size and have the third packet load in after the first packet has been transmitted on the USB.

Figure 15.30. Periodic IN Application Flow for Periodic Transfer Interrupt Feature

START

NOTE Requirements For XferSize and PktCnt programming 1 . 2 . Short Packets are not allowed in between Xfers 5 . Core will read packets from System Memory only from DWORD aligned addresses 6 . If MaxPktSize is not DWORD aligned .

7 . Thresholding in not supported for the Periodic Transfer Interrupt enhancement

· · Int ialize variables · Program t he DMA address DIEPDMA

START Address of the Data Memory

· Program Xfer USB_DIEPx _TSIZ XFERSIZE = USB_DIEPx _TSIZ PKTCNT =

XferSize Spanning across multiple Xfers Program PktCnt for multiple Xfers

USB_DIEPx _TSIZ.MC

= Max Number of Packets in a

· Program t he Global INT STS USB_GINTMSK. INCOMPLSOCINMSK = 0b0

/ / Mask IncompISOCIN Interrupt

· Program EP Ct rl regist er t o st art t he x fer USB_DIEPx _CTL.CNAK = t x_fifo_ num; USB_DIEPx _CTL.EPENA

= 0b0 USB_DIEPx _CTL.EPDIS = If USB_DIEPx _TSIZ XFERSIZE != 0 or USB_DIEPx _TSIZ PKTCNT != 0 no De- a llo ca t e Da t a Ra m Mem o r y · Yes ret urn

Internal Data Flow

1. The application must set the Transfer Size and Packet Count fields in the endpoint-specific registers and enable the endpoint to transmit the data.

• The application must enable the USB_DCTL.IGNRFRMNUM

2. When an isochronous OUT endpoint is enabled by setting the Endpoint Enable and clearing the NAK bits, the Even/Odd frame will be ignored by the core.

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3. Every time either the core’s internal DMA writes a packet to the transmit FIFO, the transfer size for that endpoint is decremented by the packet size. The data is fetched from DMA or application memory until the transfer size for the endpoint becomes 0.

4. When an IN token is received for a periodic endpoint, the core transmits the data in the FIFO, if available. If the complete data payload (complete packet) for the frame is not present in the FIFO, then the core generates an IN Token Received When TxFifo Empty Interrupt for the endpoint.

• A zero-length data packet is transmitted on the USB for isochronous IN endpoints • A NAK handshake is transmitted on the USB for interrupt IN endpoints 5. If an IN token comes for an endpoint on the bus, and if the corresponding TxFIFO for that endpoint has at least 1 packet available, and if the USB_DIEPx_CTL.NAK bit is not set, and if the internally maintained even/odd bit match with the bit 0 of the current frame number, then the core will send this data out on the USB. The core will also decrement the packet count. Core also toggles the MultCount in USB_DIEPx_CTL register and based on the value of MultCount the next PID value is sent.

• If the IN token results in a timeout (core did not receive the handshake or handshake error), core rewind the FIFO pointers. Core does not decrement packet count. It does not toggle PID.

USB_DIEPx_INT.TIMEOUT interrupt will be set which the application could check.

• At the end of periodic frame interval (Based on the value programmed in the USB_DCFG.PERFRINT register, core will internally set the even/odd internal bit to match the next frame.

6. The packet count for the endpoint is decremented by 1 under the following conditions: • For isochronous endpoints, when a zero- or non-zero-length data packet is transmitted • For interrupt endpoints, when an ACK handshake is transmitted 7. The data PID of the transmitted data packet is based on the value of USB_DIEPx_TSIZ.MC

programmed by the application. In case the USB_DIEPx_TSIZ.MC value is set to 3 then, for a particular frame the core expects to receive 3 Isochronous IN token for the respective endpoint. The data PIDs transmitted will be D2 followed by D1 and D0 respectively for the tokens.

• If any of the tokens responded with a zero-length packet due to non-availability of data in the TxFIFO, the packet is sent in the next frame with the pending data PID. For example, in a frame, the first received token is responded to with data and data PID value D2. If the second token is responded to with a zero-length packet, the host is expected not to send any more tokens for the respective endpoint in the current frame. When a token arrives in the next frame it will be responded to with the pending data PID value of D1.

• Similarly the second token of the current frame gets responded with D0 PID. The host is expected to send only two tokens for this frame as the first token got responded with D1 PID.

8. When the transfer size and packet count are both 0, the Transfer Completed interrupt for the endpoint is generated and the endpoint enable is cleared.

9. The USB_GINTSTS.INCOMPISOIN will be masked by the application hence at the Periodic Frame interval (controlled by USB_DCFG.PERFRINT), even though the core finds non-empty any of the isochronous IN endpoint FIFOs, USB_GINTSTS.INCOMPISOIN interrupt will not be generated.

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...the world's most energy friendly wireless MCUs Figure 15.31. Periodic IN Core Internal Flow for Periodic Transfer Interrupt Feature

START

If (USB_DIEPx _CTL.CNAK = 0b1) && (USB_DIEPx CTL.EPENA = 0b1) && (USB_DCTL.IGNRFRMNUM = 0b1)

NOTE 1 . 2 . 3 . Core will fetch data only from DWORD Aligned addresses 4 . The DATA PID of the packet which was not sent in the previous ( micro) frame will remain the same 5 . Short Packets are not allowed in between transfers can have a Short Packet

IN Token From Host

YES

Check Data Available

NO · · Int errupt IN Xm it NAK Packet WAIT YES · · ·

not change

· · · · Transm it Dat a Packet

If 0 If PktCnt 0 && XferSize

YES NO USB_DIEPx _INT.XFERCOMPL = 1 ret urn

15.4.5 OTG Revision 1.3 Programming Model

This section describes the OTG programming model when the core is configured to support OTG Revision 1.3 of the specification.

The core is an OTG device supporting HNP and SRP. When the core is connected to an “A” plug, it is referred to as an A-device. When the core is connected to a “B” plug it is referred to as a B-device. In Host mode, the core turns off Vbus to conserve power. SRP is a method by which the B-device signals the A-device to turn on Vbus power. A device must perform both data-line pulsing and Vbus pulsing, but a host can detect either data-line pulsing or Vbus pulsing for SRP. HNP is a method by which the B-device negotiates and switches to host role. In Negotiated mode after HNP, the B-device suspends the bus and reverts to the device role.

15.4.5.1 A-Device Session Request Protocol

The application must set the SRP-Capable bit in the Core USB Configuration register. This enables the core to detect SRP as an A-device.

1. To save power, the application suspends and turns off port power when the bus is idle by writing the Port Suspend and Port Power bits in the Host Port Control and Status register.

2. PHY indicates port power off by detecting that VBUS voltage level is no longer valid.

3. The device must detect SE0 for at least 2 ms to start SRP when Vbus power is off.

4. To initiate SRP, the device turns on its data line pull-up resistor for 5 to 10 ms. The core detects data-line pulsing.

5. The device drives Vbus above the A-device session valid (2.0 V minimum) for Vbus pulsing.

The core interrupts the application on detecting SRP. The Session Request Detected bit is set in Global Interrupt Status register (USB_GINTSTS.SESSREQINT).

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6. The application must service the Session Request Detected interrupt and turn on the Port Power bit by writing the Port Power bit in the Host Port Control and Status register. The PHY indicates port power-on by detecting a valid VBUS level.

7. When the USB is powered, the device connects, completing the SRP process.

15.4.5.2 B-Device Session Request Protocol

The application must set the SRP-Capable bit in the Core USB Configuration register. This enables the core to initiate SRP as a B-device. SRP is a means by which the core can request a new session from the host.

1. To save power, the host suspends and turns off port power when the bus is idle. PHY indicates port power off by detecting a not valid VBUS level.

The core sets the Early Suspend bit in the Core Interrupt register after 3 ms of bus idleness. Following this, the core sets the USB Suspend bit in the Core Interrupt register.

The PHY indicates the end of the B-device session by detecting a VBUS level below session valid.

2. PHY to enables the VBUS discharge function to speed up Vbus discharge.

3. The PHY indicates the session’s end by detecting a session end voltage level on VBUS. This is the initial condition for SRP. The core requires 2 ms of SE0 before initiating SRP.

The application must wait until Vbus discharges to 0.2 V after USB_GOTGCTL.BSESVLD is deasserted. This discharge time can be obtained from the datasheet.

4. The application initiates SRP by writing the Session Request bit in the OTG Control and Status register. The core perform data-line pulsing followed by Vbus pulsing.

5. The host detects SRP from either the data-line or Vbus pulsing, and turns on Vbus. The PHY indicates Vbus power-on by detecting a valid VBUS level.

6. The core performs Vbus pulsing.

The host starts a new session by turning on Vbus, indicating SRP success. The core interrupts the application by setting the Session Request Success Status Change bit in the OTG Interrupt Status register. The application reads the Session Request Success bit in the OTG Control and Status register.

7. When the USB is powered, the core connects, completing the SRP process.

15.4.5.3 A-Device Host Negotiation Protocol

HNP switches the USB host role from the A-device to the B-device. The application must set the HNP Capable bit in the Core USB Configuration register to enable the core to perform HNP as an A#device.

1. The core sends the B-device a SetFeature b_hnp_enable descriptor to enable HNP support. The B-device’s ACK response indicates that the B-device supports HNP. The application must set Host Set HNP Enable bit in the OTG Control and Status register to indicate to the core that the B-device supports HNP.

2. When it has finished using the bus, the application suspends by writing the Port Suspend bit in the Host Port Control and Status register.

3. When the B-device observes a USB suspend, it disconnects, indicating the initial condition for HNP.

The B-device initiates HNP only when it must switch to the host role; otherwise, the bus continues to be suspended.

The core sets the Host Negotiation Detected interrupt in the OTG Interrupt Status register, indicating the start of HNP.

The PHY turns off the D+ and D- pulldown resistors to indicate a device role. The PHY enable the D + pull-up resistor indicates a connect for B-device.

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The application must read the Current Mode bit in the OTG Control and Status register to determine Device mode operation.

4. The B-device detects the connection, issues a USB reset, and enumerates the core for data traffic.

5. The B-device continues the host role, initiating traffic, and suspends the bus when done.

The core sets the Early Suspend bit in the Core Interrupt register after 3 ms of bus idleness. Following this, the core sets the USB Suspend bit in the Core Interrupt register.

6. In Negotiated mode, the core detects the suspend, disconnects, and switches back to the host role.

The core turns on the D+ and D- pulldown resistors to indicate its assumption of the host role.

7. The core sets the Connector ID Status Change interrupt in the OTG Interrupt Status register. The application must read the connector ID status in the OTG Control and Status register to determine the core’s operation as an A-device. This indicates the completion of HNP to the application. The application must read the Current Mode bit in the OTG Control and Status register to determine Host mode operation.

8. The B-device connects, completing the HNP process.

15.4.5.4 B-Device Host Negotiation Protocol

HNP switches the USB host role from B-device to A-device. The application must set the HNP-Capable bit in the Core USB Configuration register to enable the core to perform HNP as a B-device.

1. The A-device sends the SetFeature b_hnp_enable descriptor to enable HNP support. The core’s ACK response indicates that it supports HNP. The application must set the Device HNP Enable bit in the OTG Control and Status register to indicate HNP support.

The application sets the HNP Request bit in the OTG Control and Status register to indicate to the core to initiate HNP.

2. When it has finished using the bus, the A-device suspends by writing the Port Suspend bit in the Host Port Control and Status register.

The core sets the Early Suspend bit in the Core Interrupt register after 3 ms of bus idleness. Following this, the core sets the USB Suspend bit in the Core Interrupt register.

The core disconnects and the A-device detects SE0 on the bus, indicating HNP. The core enables the D+ and D- pulldown resistors to indicate its assumption of the host role.

The A-device responds by activating its D+ pull-up resistor within 3 ms of detecting SE0. The core detects this as a connect.

The core sets the Host Negotiation Success Status Change interrupt in the OTG Interrupt Status register, indicating the HNP status. The application must read the Host Negotiation Success bit in the OTG Control and Status register to determine host negotiation success. The application must read the Current Mode bit in the Core Interrupt register (USB_GINTSTS) to determine Host mode operation.

3. The application sets the reset bit (USB_HPRT.PRTRST) and the core issues a USB reset and enumerates the A-device for data traffic 4. The core continues the host role of initiating traffic, and when done, suspends the bus by writing the Port Suspend bit in the Host Port Control and Status register.

5. In Negotiated mode, when the A-device detects a suspend, it disconnects and switches back to the host role. The core disables the D+ and D- pulldown resistors to indicate the assumption of the device role.

6. The application must read the Current Mode bit in the Core Interrupt (USB_GINTSTS) register to determine the Host mode operation.

7. The core connects, completing the HNP process.

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15.4.6 OTG Revision 2.0 Programming Model

OTG Revision 2.0 supports the new Attach Detection Protocol (ADP). This protocol enables a local device (an OTG device or Embedded Host) to detect when a remote device is attached or detached.

Note

ADP is not supported by the core.

In addition to ADP, OTG Revision 2.0 also supports enhanced SRP and HNP, which are described in the following sections:

• OTG Revision 2.0 Session Request Protocol (p. 298)

• OTG Revision 2.0 Host Negotiation Protocol (p. 300)

Note

VBUS pulsing is not supported in OTG Revision 2.0 mode.

15.4.6.1 OTG Revision 2.0 Session Request Protocol

When the core is behaving as an A-device, it can power off VBUS when no session is active until the B-device initiates a SRP. The SRP detection is handled by the core.

Figure 15.32 (p. 299) illustrates the programming steps that need to be performed by A-device’s

application (core as A-device) when B-device initiates a SRP to establish a connection.

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Host m ode (PHY not driving VBUS) Program USB_GINTMSK.

(Unm ask OTGINT, MODEMIS, SESSREQINT) No If host ’ s applicat ion decides t o t urn on VBUS volunt arily, t hen t he applicat ion need not wait for SRP from device No Int errupt?

Yes Read USB_GINTSTS GINTSTS.

SESSREQINT = 1 ?

Yes Host Init ializat ion St eps. Refer t o t he Host Init ializat ion sect ion of t his chapt er for m ore inform at ion.

(In t his st ep t he OTG FSM is in a_host st at e.) Not e: If MODEMIS int errupt is det ect ed during t his process, connect or has been plugged out or int erchanged. confirm ed by reading USB_GINTSTS.CONIDSTSCHNG

Host Transact ions

Figure 15.33 (p. 300) illustrates the steps that need to be performed by B-device’s application (core

as B-device) in order to establishing a connection with A-device by signaling a SRP.

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...the world's most energy friendly wireless MCUs Figure 15.33. SRP Initiation by the Core When Acting as a B-Device

Device (OTG FSM in b_idle st at e) 1. Program USB_GINTMSK (unm ask OTGINT) 2. Read USB_GOTGCTL Yes VBUS is already being driven and hence t here is no need for a SRP ) USB_GOTGCTL.

BSESVLD = 1 ?

No Device Init ializat ion St eps . inform at ion Device Init ializat ion sect ion of t his chapt er.

Set USB_GOTGCTL.

SESREQ = 1 Int errupt ?

No Yes No Read USB_GINTSTS No USB_GINTSTS.

OTGINT = 1?

Yes Read USB_GOTGINT No Device Transact ions USB_GOTGINT .

SESREQSUCS TSCHNG = Yes 1. Read USB_GOTGCTL 2. Clear USB_GOTGINT .SESREQSU

CSTSCHNG by writ ing a USB_GOTGCTL .

SESREQSCS = Yes Device Init ializat ion St eps. inform at ion Device Init ializat ion sect ion of t his .

Note

The programming flow illustrated in Figure 15.33 (p. 300) is similar to OTG revision 1.3.

This is because the presence or absence of VBUS pulsing is transparent to the application.

15.4.6.2 OTG Revision 2.0 Host Negotiation Protocol

When the core is operating as A-device, the application must execute a GetStatus() operation to the B device with a frequency of THOST_REQ_POLL to determine the state of the host request flag in the B-device. If the host request flag is set in B-device it must program the core to change its role within THOST_REQ_SUSP.

Figure 15.34 (p. 301) shows the programming steps that need to be performed by A-device’s application (core as A-device) in order to change its role to device. In Figure 15.34 (p. 301) , the A-

device performs a role change, becomes a B-device and then reverts back to host (A-device) mode of operation.

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...the world's most energy friendly wireless MCUs Figure 15.34. HNP When the Core is an A-Device

Host t o Device t o Host Host m ode (Send Set Feat ure Com m and t o enable b_hnp_enable feat ure in HNP capable devices. HNP polling m echanism is also involved. This is done when OTG FSM is in a_host st at e) Program Unm ask USB_GINTSTS. OTGINT Int errupt ?

No No Yes Read USB_GINTSTS Yes C1 1. Unm ask USB_GINTSTS.ERLYSUSP

of t his chapt er , see Device Init ializat ion sect ion St art of Device t ransact ions End of Device t ransact ions Int errupt ?

No Read USB_GINTSTS Check t hat CURMOD = 0 Yes Host Init ializat ion St eps . inform at ion Init ializat ion sect ion .

Host Mode Transact ions No No Read USB_GINTSTS No USB_GINTSTS.

OTGINT Yes Int errupt ?

No Yes USB_GOTGINT.

HSTNEGDET =1?

Yes Read USB_GINTSTS.CURMOD

USB_GINTSTS.

ERLYSUSP = 1 ?

Yes Int errupt ?

No No Read USB_GINTSTS USB_GINTSTS.

USBSUSP = 1 ?

Yes Applicat ion st art s 200 Rem ain as Host applicat ion can t o swit ch off VBUS or not ) No USB_GINTSTS.

CURMOD = 0?

Yes C1 No Int errupt wit hin 200 m s yes Read USB_GINTSTS USB_GINTSTS.WKUPINT = 1 or USB_GINTSTS.RESETDET ?

Figure 15.35 (p. 302) shows the programming steps that need to be performed by B-device’s application (core as B-device) in order to change its role to Host. In Figure 15.35 (p. 302) , the B-

device performs a role change, becomes a Host and then reverts back to Device mode of operation.

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C1 Device m ode (Receive Set Feat ure Com m and and OTG FSM is in b_peripheral st at e) 1. Program USB_GOTGCTL.DEVSETHNPEN = 1 2. Program USB_GOTGCTL.HNPREQ = 1 Int errupt ?

No No Read USB_GINTSTS USB_GINTSTS.

ERLYSUSP = 1?

Yes No Int errupt ?

No Read USB_GINTSTS No USB_GINTSTS.

USBSUSP = 1?

Yes Int errupt ?

No Yes No Read USB_GINTSTS USB_GINTSTS.

OTGINT = 1?

Yes C1 Read USB_GOTGINT USB_GOTGINT.

HSTNEGSUCSTSCHNG = 1 ?

Yes Clear USB_GOTGINT.

HSTNEGSUCSTSCHNG Read USB_GOTGCTL USB_GOTGCTL.

HSTNEGSUCS = 1 ?

Yes Read USB_GINTSTS. Check t hat CURMOD = 1.

No Rem ain as Device Host Init ializat ion St eps (USB_HPRT.PRTPWR should not be program m ed). For m ore inform at ion, see Host Init ializat ion sect ion in t his chapt er.

St art of Host t ransact ions End of Host t ransact ions Set USB_HPRT.PRTSUSP = 1.

Unm ask GINTSTS.OTGINT.

(USB_HPRT.PRTPWR should not be program m ed) Does B device want t o rem ain host?

No No Yes Program USB_HPRT.PRTRES = 1 for a predefined t im e.

The applicat ion should ensure t hat t his process happens wit hin m s Int errupt ?

No Read USB_GINTSTS USB_GINTSTS.

DISCONNINT = 1 ?

Yes Read USB_GINTSTS.CURMOD

and ensure it is 0. Device Init ializat ion St eps Device Init ializat ion Device Mode Transact ions

Note

During HNP process where the B-device is going to assume the role of a host, the B-device application needs to ensure that a USB reset process is programmed (in USB_HPRT 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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register) within 150 ms (TB_ACON_BSE0) of getting a USB_HPRT.PRTCONNDET

interrupt.

15.4.7 FIFO RAM Allocation

15.4.7.1 Data FIFO RAM Allocation

External RAM must be allocated among different FIFOs in the core before any transactions can start.

The application must follow this procedure every time it changes core FIFO RAM allocation.

The application must allocate data RAM per FIFO based on the AHB’s operating frequency, the PHY Clock frequency, the available AHB bandwidth, and the performance required on the USB. Based on the above mentioned criteria, the application must provide a table as described below with RAM sizes for each FIFO in each mode.

The core shares a single FIFO RAM between transmit FIFO(s) and receive FIFO.

In DMA mode—The FIFO RAM is also used for storing the some register information.

The Device mode Endpoint DMA address registers (USB_DIEP0DMAADDR, USB_DOEP0DMAADDR, USB_DIEPx_DMAADDR, USB_DOEPx_DMAADDR) and Host mode Channel DMA registers (USB_HCx_DMAADDR) are stored in the FIFO RAM.

• These register information are stored at the end of the FIFO RAM after the space allocated for receive and Transmit FIFO. These register space must also be taken into account when calculating the total FIFO depth of the core as explained in the following sections.

The registers USB_DIEPx_DMAADDR/USB_DOEPx_DMAADDR are maintained in RAM.

The following rules apply while calculating how much RAM space must be allocated to store these registers.

Host Mode:

• Slave mode only: No space needed.

• DMA mode: One location per channel.

Device Mode:

• Slave mode only: No space needed.

• DMA mode: One location per end point direction.

15.4.7.1.1 Device Mode 15.4.7.1.1.1 Tx FIFO Operation

When allocating data RAM for FIFOs in Device mode keep in mind these factors: 1. Receive FIFO RAM allocation: • RAM for SETUP Packets: 4 * n + 6 locations must be Reserved in the receive FIFO to receive up to n SETUP packets on control endpoints, where n is the number of control endpoints the device core supports. The core does not use these locations, which are Reserved for SETUP packets, to write any other data.

• One location for Global OUT NAK • Status information is written to the FIFO along with each received packet. Therefore, a minimum space of (Largest Packet Size / 4) + 1 must be allotted to receive packets. If a high-bandwidth endpoint is enabled, or multiple isochronous endpoints are enabled, then at least two (Largest 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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Packet Size / 4) + 1 spaces must be allotted to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1 spaces are recommended so that when the previous packet is being transferred to AHB, the USB can receive the subsequent packet. If AHB latency is high, you must allocate enough space to receive multiple packets. This is critical to prevent dropping any isochronous packets.

• Along with each endpoint's last packet, transfer complete status information is also pushed to the FIFO. Typically, one location for each OUT endpoint is recommended.

2. Transmit FIFO RAM Allocation: The minimum RAM space required for each IN Endpoint Transmit FIFO is the maximum packet size for that particular IN endpoint.

More space allocated in the transmit IN Endpoint FIFO results in a better performance on the USB and can hide latencies on the AHB.

Table 15.3.

FIFO Name

Receive data FIFO Transmit FIFO 0 Transmit FIFO 1 Transmit FIFO 2 ...

Transmit FIFO i

Data RAM Size

rx_fifo_size. This must include RAM for setup packets, OUT endpoint control information and data OUT packets, as mentioned earlier.

tx_fifo_size[0] tx_fifo_size[1] tx_fifo_size[2] ...

tx_fifo_size[i] With this information, the following registers must be programmed as follows: 1. Receive FIFO Size Register (USB_GRXFSIZ) USB_GRXFSIZ.Receive FIFO Depth = rx_fifo_size; 2. Device IN Endpoint Transmit FIFO0 Size Register (USB_GNPTXFSIZ) USB_GNPTXFSIZ.non-periodic Transmit FIFO Depth = tx_fifo_size[0]; USB_GNPTXFSIZ.non-periodic Transmit RAM Start Address = rx_fifo_size; 3. Device IN Endpoint Transmit FIFO#1 Size Register (USB_DIEPTXF1) USB_DIEPTXF1. Transmit RAM Start Address = USB_GNPTXFSIZ.FIFO0 Transmit RAM Start Address + tx_fifo_size[0]; 4. Device IN Endpoint Transmit FIFO#2 Size Register (USB_DIEPTXF2) USB_DIEPTXF2.Transmit RAM Start Address = USB_DIEPTXF1.Transmit RAM Start Address + tx_fifo_size[1]; 5. Device IN Endpoint Transmit FIFO#i Size Register (USB_DIEPTXFi) USB_DIEPTXFm.Transmit RAM Start Address = USB_DIEPTXFi-1.Transmit RAM Start Address + tx_fifo_size[i-1]; 6. The transmit FIFOs and receive FIFO must be flushed after the RAM allocation is done, for the proper functioning of the FIFOs.

• USB_GRSTCTL.TXFNUM = 0x10 • USB_GRSTCTL.TXFFLSH = 1 • USB_GRSTCTL.RXFFLSH = 1 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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The application must wait until the TXFFLSH bit and the RXFFLSH bits are cleared before performing any operation on the core.

15.4.7.1.2 Host Mode

Considerations for allocating data RAM for Host Mode FIFOs are listed here:

Receive FIFO RAM allocation:

Status information is written to the FIFO along with each received packet. Therefore, a minimum space of (Largest Packet Size / 4) + 2 must be allotted to receive packets. If a high-bandwidth channel is enabled, or multiple isochronous channels are enabled, then at least two (Largest Packet Size / 4) + 2 spaces must be allotted to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 2 spaces are recommended so that when the previous packet is being transferred to AHB, the USB can receive the subsequent packet. If AHB latency is high, you must allocate enough space to receive multiple packets.

Along with each host channel’s last packet, information on transfer complete status and channel halted is also pushed to the FIFO. So two locations must be allocated for this.

For handling NAK in DMA mode, the application must determine the number of Control/Bulk OUT endpoint data that must fit into the TX_FIFO at the same instant. Based on this, one location each is required for Control/Bulk OUT endpoints.

For example, when the host addresses one Control OUT endpoint and three Bulk OUT endpoints, and all these must fit into the non-periodic TX_FIFO at the same time, then four extra locations are required in the RX FIFO to store the rewind status information for each of these endpoints.

Transmit FIFO RAM allocation

The minimum amount of RAM required for the Host Non-periodic Transmit FIFO is the largest maximum packet size among all supported non-periodic OUT channels.

More space allocated in the Transmit Non-periodic FIFO results in better performance on the USB and can hide AHB latencies. Typically, two Largest Packet Sizes’ worth of space is recommended, so that when the current packet is under transfer to the USB, the AHB can get the next packet. If the AHB latency is large, then you must allocate enough space to buffer multiple packets.

The minimum amount of RAM required for Host periodic Transmit FIFO is the largest maximum packet size among all supported periodic OUT channels. If there is at lease one High Bandwidth Isochronous OUT endpoint, then the space must be at least two times the maximum packet size of that channel.

15.4.7.1.2.1 Internal Register Storage Space Allocation

When operating in DMA mode, the DMA address register for each host channel (USB_HCx_DMAADDR) is stored in the FIFO RAM. One location for each channel must be reserved for this.

Table 15.4.

FIFO Name

Receive Data FIFO Non-periodic Transmit FIFO IN Endpoint Transmit FIFO

Data RAM Size

rx_fifo_size tx_fifo_size[0] tx_fifo_size[1] With this information, the following registers must be programmed: 1. Receive FIFO Size Register (USB_GRXFSIZ) • USB_GRXFSIZ.RXFDEP = rx_fifo_size; 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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2. Non-periodic Transmit FIFO Size Register (USB_GNPTXFSIZ) • USB_GNPTXFSIZ.NPTXFDEP = tx_fifo_size[0]; • USB_GNPTXFSIZ.NPTXFSTADDR = rx_fifo_size; 3. Host Periodic Transmit FIFO Size Register (USB_HPTXFSIZ) • USB_HPTXFSIZ.PTXFSIZE = tx_fifo_size[1]; • USB_HPTXFSIZ.PTXFSTADDR = USB_GNPTXFSIZ.NPTXFSTADDR + tx_fifo_size[0]; 4. The transmit FIFOs and receive FIFO must be flushed after RAM allocation for proper FIFO function.

• USB_GRSTCTL.TXFNUM = 0x10 • USB_GRSTCTL.TXFFLSH = 1 • USB_GRSTCTL.RXFFLSH = 1 • The application must wait until the TXFFLSH bit and the RXFFLSH bits are cleared before performing any operation on the core.

15.4.7.1.3 Summary of Guidelines for Choosing Data FIFO RAM Depth in Host Mode 15.4.7.1.3.1 RX FIFO size

The RX FIFO size must be equal to at least twice the largest value of MPS size used. The recommended minimum RXFIFO depth = ((largest packet size/4)*2)+2. (+2) is required by the core for the status quadlets internally.

15.4.7.1.3.2 Non periodic TX FIFO size

This should be equal to at least twice the largest value of MPS size used. The recommended minimum non-periodic TXFIFO depth = ((largest packet size/4)*2).

15.4.7.1.3.3 Periodic TX FIFO size

The recommended size for Periodic TXFIFO is sum total of (MPS*MC)/4 for all the channels.

Note

Note: In the above recommendations, always round off the MPS value to the nearest multiple of 4. For example, if the largest value of MPS=125, use the rounded-off value, which is 128.

15.4.7.1.4 Calculating the Total FIFO Size

The RxFIFO is shared between the host and device. The Host TxFIFOs are also shared with Device IN endpoint TxFIFOs 0 through n.

There are three ways to calculate the total FIFO size.

Method 1

Use this method if you are using the following conditions: • Minimum FIFO depth allocation • The FIFO must equal at least one MaxPacketSize (MPS).

Device RxFIFO = • (4 * number of control endpoints + 6) + ((largest USB packet used / 4) + 1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK

Note

Include the Control OUT endpoint in the number of OUT endpoints.

Host RxFIFO = 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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• Slave mode Minimum requirement: (largest USB packet used / 4) + 1 for status information + 1 transfer complete • DMA mode (largest USB packet used / 4) + 1 for status information + 1 transfer complete + 1 location each bulk/ control out endpoint for handling NAK scenario Host Non-Periodic TxFIFO = • largest non-periodic USB packet used / 4 Host Periodic TxFIFO = • Sum total of (MPS*MC)/4 of all periodic channels or 1500 locations, whichever is lower.

Device IN Endpoint TxFIFOs (a separate FIFO is allocated to each IN endpoint) = • IN Endpoints Max packet Size / 4

Method 2

Use this method if you are using the recommended minimum FIFO depth allocation with support for high-bandwidth endpoints. This FIFO allocation enables the core to transfer a packet on the USB while the previous (next) packet is simultaneously transferred to the AHB. This FIFO allocation improves the core’s performance.

Device RxFIFO = • (4 * number of control endpoints + 6) + 2 * ((largest USB packet used / 4) + 1) +(2 * number of OUT endpoints) + 1 Host RxFIFO = • Slave mode 2 * ((largest USB packet used / 4) + 1 + 1) • DMA mode 2 * ((largest USB packet used / 4) + 1 + 1) + 1 location each bulk/control out endpoint for handling NAK scenario Host Non-Periodic TxFIFO = • 2 * (largest non-periodic USB packet used / 4) Host Periodic TxFIFO = • Sum total of (MPS*MC)/4 for all periodic channels or 1500 location, whichever is lower.

Device IN Endpoint-Specific TxFIFOs (a separate FIFO is allocated to each endpoint) = • 2 * (max_pkt_size for the endpoint) / 4.

//DMA mode OTG Total RAM = (Device RxFIFO or Host RxFIFO; choose the largest one) + 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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((Host Non-Periodic TxFIFO + Host peiodic TxFIFO) or (Device IN Endpoint TxFIFO #0 + #1 + #2 + #n)); choose the largest one + (1 location per Host channel or 1 location per Device Endpoint direction; choose the largest one) //Slave mode OTG Total RAM = (Device RxFIFO or Host RxFIFO; choose the largest one) + ((Host Non-Periodic TxFIFO + Host peiodic TxFIFO) or (Device IN Endpoint TxFIFO #0 + #1 + #2 + #n)); choose the largest one

Method 3

Use this method if you are using the recommended FIFO depth allocation that supports high-bandwidth endpoints and high AHB latency.

Note

• x = (AHB latency + time to transfer largest packet on AHB) / time to transfer largest packet on USB.

• The value of x is an integer. Any fractional value is rounded to the nearest integer. For example: x = 20 ms / 17,039 ms = 1.17 ms = 2 ms.

Device RxFIFO = • (4 * number of control endpoints + 6) + (x + 1) * ((largest USB packet used / 4) + 1)+ (2 * number of OUT endpoints) + 1

Note

Include the Control OUT endpoint in the number of OUT endpoints.

Host RxFIFO = • Slave mode (x + 1) * ((largest USB packet used / 4) + 1 + 1) • DMA mode (x + 1) * ((largest USB packet used / 4) + 1 + 1) + 1 location each bulk/control out endpoint for handling NAK scenario Host Non-Periodic TxFIFO = • (x + 1) * (largest non-periodic USB packet used / 4) Host Periodic TxFIFO = • (x+1) * (Sum total of (MPS*MC)/4 of all periodic channels or 1500 locations, whichever is lower).

Device IN Endpoint-Specific TxFIFOs (a separate FIFO is allocated to each endpoint) = • (x+1)*(max_pkt_size for the endpoint)/4 //DMA mode OTG Total RAM = (Device RxFIFO or Host RxFIFO; choose the largest one) + ((Host Non-Periodic TxFIFO + Host periodic TxFIFO) OR (Device IN Endpoint TxFIFO #0 + #1 + #2 + #n); choose the largest one) + (1 location per Host channel or 1 location per Device Endpoint direction; choose 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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the largest one) //Slave mode OTG Total RAM = (Device RxFIFO or Host RxFIFO; choose the largest one) + ((Host Non-Periodic TxFIFO + Host periodic TxFIFO) OR (Device IN Endpoint TxFIFO #0 + #1 + #2 + #n); choose the largest one)

15.4.7.2 Dynamic FIFO Allocation

The application can change the RAM allocation for each FIFO during the operation of the core.

15.4.7.2.1 Host Mode

In Host mode, before changing FIFO data RAM allocation, the application must determine the following.

All channels are disabled • All FIFOs are empty

Once these conditions are met, the application can reallocate FIFO data RAM as explained in Data FIFO RAM Allocation (p. 303) .

After reallocating the FIFO data RAM, the application must flush all FIFOs in the core using the USB_GRSTCTL.TXFFLSH (TxFIFO Flush) and USB_GRSTCTL.RXFFLSH (RxFIFO Flush) fields.

Flushing is required to reset the pointers in the FIFOs for proper FIFO operation after reallocation. For

more information on flushing FIFOs, see Flushing TxFIFOs in the Core (p. 309) and Flushing RxFIFOs in the Core (p. 310) .

15.4.7.2.2 Device Mode

In Device mode, before changing FIFO data RAM allocation, the application must determine the following.

• All IN and OUT endpoints are disabled • NAK mode is enabled in the core on all IN endpoints • Global OUT NAK mode is enabled in the core • All FIFOs are empty

Once these conditions are met, the application can reallocate FIFO data RAM as explained in Data FIFO RAM Allocation (p. 303) . When NAK mode is enabled in the core, the core responds with a NAK

handshake on all tokens received on the USB, except for SETUP packets.

After the reallocating the FIFO data RAM, the application must flush all FIFOs in the core using the USB_GRSTCTL.TXFFLSH (TxFIFO Flush) and USB_GRSTCTL.RXFFLSH (RxFIFO Flush) fields.

Flushing is required to reset the pointers in the FIFOs for proper FIFO operation after reallocation. For

more information on flushing FIFOs, see Flushing TxFIFOs in the Core (p. 309) and Flushing RxFIFOs in the Core (p. 310) .

15.4.7.2.3 Flushing TxFIFOs in the Core

The application can flush all TxFIFOs in the core using USB_GRSTCTL.TXFFLSH as follows: 1. Check that USB_GINTSTS.GINNAKEFF=0. If this bit is cleared then set USB_DCTL.SGNPINNAK=1.

2. Wait for USB_GINTSTS.GINNAKEFF=1, which indicates the NAK setting has taken effect to all IN endpoints.

3. Poll USB_GRSTCTL.AHBIDLE until it is 1.

AHBIdle = H indicates that the core is not writing anything to the FIFO.

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4. Check that USB_GRSTCTL.TXFFLSH =0. If it is 0, then write the TxFIFO number you want to flush to USB_GRSTCTL.TXFNUM.

5. Set USB_GRSTCTL.TXFFLSH=1and wait for it to clear.

6. Set the USB_DCTL.GCNPINNAK bit.

15.4.7.2.4 Flushing RxFIFOs in the Core

The application can flush all RxFIFOs in the core using USB_GRSTCTL.RXFFLSH as follows: 1. Check the status of the USB_GINTSTS.GOUTNAKEFF bit. If it has been cleared, then set USB_DCTL.SGOUTNAK=1. Else, clear USB_GINTSTS.GOUTNAKEFF.

NAK Effective interrupt = 1 indicates that the core is not writing to FIFO.

2. Wait for USB_GINTSTS.GOUTNAKEFF=1, which indicates the NAK setting has taken effect to all OUT endpoints.

3. Poll the USB_GRSTCTL.AHBIDLE until it is 1.

AHBIDLE = 1 indicates that the core is not reading anything from the FIFO.

4. Set USB_GRSTCTL.RXFFLSH=1 and wait for it to clear.

5. Set the USB_DCTL.GCOUTNAK bit.

The Core Interrupt Handler

Figure 15.36. Core Interrupt Handler

ot g_int r_ handler Wait for int errupt Clear int errupt Generat e host global soft ware int errupt Yes Read USB_HPRT Generat e port specific soft ware Yes int errupt.

Read USB_GINTSTS OTG int errupt?

Yes Read Generat e OTG soft ware int errupt No Host global int errupt?

No Host Port Int errupt?

No Read USB_HAINT No Host/ Device com m on int errupt?

No RTL in Device m ode?

Yes Device global int errupt?

No Read USB_DAINT Yes IN endpoint int errupt?

Yes Generat e gobal soft ware int errupt Generat e device global soft ware int errupt Yes Read USB_DIEPx _INT Generat e IN endpoint- specific Clear int errupt Read USB_HCx _INT Generat e channel specific soft ware int errupt.

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15.4.8 Suspend/Resume and SRP

This chapter describes different methods of saving power when the USB is suspended. This chapter discusses the following topics:

• Placing PHY in Low Power Mode Without Entering Suspend (p. 311) • When the Core is in Host Mode (p. 311)

• When the Core is in Device Mode (p. 312) • Suspend (p. 312) • Using EM2 (p. 312) • Overview of the EM2 Programming Model (p. 312) • Using EM2 when the Core is in Host Mode (p. 312)

• EM2 when the Core is in Device Mode (p. 315)

• Clock Gating (EM0 and EM1) (p. 317) • Internal Clock Gating when the Core is in Host Mode (p. 317)

• Internal Clock Gating when the Core is in Device Mode (p. 318)

15.4.8.1 Placing PHY in Low Power Mode Without Entering Suspend

The core can place the PHY in low power mode (the differential receiver is disabled) without entering suspend.

15.4.8.1.1 When the Core is in Host Mode Programming flow for the Host Core to put PHY in low power mode

1. To turn off port power, perform write operation to set the following bits in the USB_HPRT register: • USB_HPRT.PRTPWR = 0; • USB_HPRT.PRTENA = 0; 2. To put PHY in low power mode, perform read-modify-write operation to set the following bits in the USB_PCGCCTL register: • USB_PCGCCTL.STOPPCLK = 1 • USB_PCGCCTL.GATEHCLK = 0

Programming flow for the Host Core to make PHY exit low power mode

If your device is non-SRP capable, the host must implement polling to detect the device connection by turning on the port and exiting PHY low power mode periodically and checking for connect.

1. To turn on port power, perform write operation to set the following bits in the USB_HPRT register: • USB_HPRT.PRTPWR = 1 • USB_HPRT.PRTENA = 0 2. To exit PHY low power mode, perform read-modify-write operation to set the following bits in the USB_PCGCCTL register: • USB_PCGCCTL.STOPPCLK = 0 • USB_PCGCCTL.STOPHCLK = 0 3. Wait for the USB_HPRT Port Connect Detected (PRTCONNDET) bit to be set and do the enumeration of the device.

If your device is SRP-capable, when the device initiates SRP request, the Host core asynchronously detects SRP and the PHY exits low power mode.

1. Wait for Session Request from the device, or New Session Detected Interrupt (SESSREQINT) in the USB_GINTSTS register.

2. To turn on port power, perform write operation to set the following bits in the USB_HPRT register: 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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• USB_HPRT.PRTPWR = 1 • USB_HPRT.PRTENA = 0 3. Wait for the USB_HPRT Port Connect Detected (PRTCONNDET) bit to be set and do the enumeration of Device.

15.4.8.1.2 When the Core is in Device Mode

To make PHY enter low power mode, complete the following steps: 1. Ensure that the following signals are set as follows: • VBUS voltage level must be below the session valid level (VBUS is not active) • DP/DM must be SE0 2. From the application, perform read-modify-write operation to set USB_PCGCCTL.STOPPCLK = 1.

15.4.8.2 Suspend

When the core is in Suspend, the following power conservation options are available to use:

• Using EM2 (p. 312) : You can enter EM2, turning off power (and reseting) parts of the core

• Clock Gating (EM0 and EM1) (p. 317) : You can choose gate the AHB clock to some parts of the core Internal Clock Gating when the Core is in Host Mode (p. 317)

This section discusses methods of conserving power by using one of the above methods.

15.4.8.2.1 Using EM2 15.4.8.2.1.1 Overview of the EM2 Programming Model

When the USB is suspended or the session is not valid, the PHY is driven into Suspend mode, stopping the PHY clock to reduce power consumption in the PHY and the core. To further reduce power consumption, the core also supports AHB clock gating and using EM2.

The following sections show the procedures you must follow to use EM2 while in suspend/session-off.

During EM2, the clock to the core must be switched to one of the 32 kHz sources (LFRCO or LFXO).

This core needs this clock to detect Resume and SRP events.

15.4.8.2.1.2 EM2 when the Core is in Host Mode Host Mode Suspend in EM2

Sequence of operations: 1. Back up the essential registers of the core. Read and store the following core registers: • USB_GINTMSK • USB_GOTGCTL • USB_GAHBCFG • USB_GUSBCFG • USB_GRXFSIZ • USB_GNPTXFSIZ • USB_DCFG • USB_DCTL • USB_DAINTMSK • USB_DIEPMSK • USB_DOEPMSK • USB_DIEPx_CTL • USB_DIEPx_TSIZ • USB_DIEPx_DMAADDR • USB_PCGCCTL • USB_DIEPTXFn 2. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend.

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3. The application sets the Power Clamp bit in the Power and Clock Gating Control register.

4. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control register.

5. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register, the core suspends the PHY and the PHY clock stops. If USB_HCFG.ENA32KHZS is set, switch the USBC clock to 32 kHz.

6. Enter EM2.

Host Mode Resume in EM2

Sequence of operations: 1. The resume event starts by the application waking up from EM2 (on an interrupt) 2. Switch USBC clock back to 48 MHz.

3. The application clears the Stop PHY Clock bit and the core takes the PHY back to normal mode.

The PHY clock starts up.

4. The application clears the Power Clamp bit. The core starts driving Resume signaling on the USB.

5. The application clears the Reset to Power-Down Modules bit.

6. The application programs registers in the CSR and sets the Port Resume bit in Host Port CSR (Setting the Port Resume bit is required by the core, although Resume signaling starts earlier).

7. The application clears the Port Resume bit and the core stops driving Resume signaling.

The core is in normal operating mode.

Note

The application must insert delays of at least 2 PHY clocks between all steps in this sequence. This requirement applies to all USB EM2 programming sequences.

Host Mode Remote Wakeup in EM2

Sequence of operations: 1. The core detects Remote Wakeup signaling on the USB. The PHY exits suspend mode and the PHY clock restarts.

2. The core generates a Remote Wakeup Detected interrupt. The Remote Wakeup interrupt is generated using the 32 kHz clock depending on the USB_HCFG.RESVALID (ResumeValidPeriod) programmed.

The Host Core starts resume signaling at this stage.

3. The USBC clock is switched back to normal 48 MHz clock.

4. The application clears the Stop PHY Clock bit.

5. The application clears the Power Clamp bit.

6. The application clears the Reset to Power-Down Modules bit 7. The application programs CSRs and sets the Port Resume bit. The core continues to drive Resume signaling on the USB.

8. The application clears the Port Resume bit and the core stops driving Resume signaling.

The core enters normal operating mode.

Host Mode Session End in EM2

Sequence of operations: 1. Back up the essential registers of the core. Read and store the following core registers: • USB_GINTMSK • USB_GOTGCTL • USB_DCTL • USB_DAINTMSK 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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• USB_GAHBCFG • USB_GUSBCFG • USB_GRXFSIZ • USB_GNPTXFSIZ • USB_DCFG • USB_DIEPMSK • USB_DOEPMSK • USB_DIEPx_CTL • USB_DIEPx_TSIZ • USB_DIEPx_DMAADDR • USB_PCGCCTL • USB_DIEPTXFn 2. The application sets the Port Suspend bit in the Host Port CSR and the core drives a USB suspend.

3. The application clears the Port Power bit.

4. The application sets the Power Clamp bit in the Power and Clock Gating Control register, and the core clamps the signals between the internal modules on different power rails.

5. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control register.

6. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register, and the core suspends the PHY, stopping the PHY clock.

7. Switch USBC clock to 32 kHz.

8. Enter EM2.

Host Mode Session Start (EM2 -> EM0)

Sequence of operations: 1. Exit EM2/Enter EM0).

2. Switch USBC clock back to 48 MHz.

3. The application clears the Stop PHY Clock bit.

4. The application clears the Power Clamp bit. The application clears the Reset to Power-Down Modules bit.

5. The application programs CSRs and sets the Port Power bit to turn on VBUS.

6. The core detects the connection and drives the USB reset.

The core enters normal operating mode.

Host Mode Session End (EM0 -> EM2)

Sequence of operations: 1. Back up the essential registers of the core. Read and store the following core registers: • USB_GINTMSK • USB_GOTGCTL • USB_GAHBCFG • USB_GUSBCFG • USB_GRXFSIZ • USB_GNPTXFSIZ • USB_DCFG • USB_DCTL • USB_DAINTMSK • USB_DIEPMSK • USB_DOEPMSK • USB_DIEPx_CTL • USB_DIEPx_TSIZ • USB_DIEPx_DMAADDR • USB_PCGCCTL • USB_DIEPTXFn 2. The application sets the Port Suspend bit in the Host Port CSR and the core drives a USB suspend.

3. The application clears the Port Power bit.

4. The application sets the Power Clamp bit in the Power and Clock Gating Control register, and the core clamps the signals between the internal modules on different power rails.

5. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control register.

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6. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register.

7. Enter EM2.

Host Mode Sessions Start (SRP) (EM2 -> EM0)

Sequence of operations: 1. The core detects SRP (data line pulsing) on the bus. The core de-asserts the suspend_n signal to the PHY, generating the PHY clock. The SRP Detected interrupt is generated.

2. The application clears the Stop PHY Clock bit, the core deasserts the suspend_n signal to the PHY to generate the PHY clock.

3. The power (VDD_DN) is turned on and stabilizes.

4. The application clears the Power Clamp bit.

5. The application clears the Reset to Power-Down Modules bit.

6. The application programs the CSRs, and sets the Port Power bit to turn on VBUS.

7. The core detects device connection and drives a USB reset.

The core enters normal operating mode.

15.4.8.2.1.3 EM2 when the Core is in Device Mode Device Mode Suspend With EM2

In Device mode, the device validates the host-driven Resume signal for a period of 1.5 µs (75 clock cycles at 48 MHz). With a 32-KHz clock, 2.34 ms is required (75 clock cycles at 32 KHz) to detect the resume. Hence, the application programs USB_DCFG.RESVALID with a value of 4 clock cycles (125 µs). If the core is in Suspend mode, the device thus detects the resume and the host signals a resume for a minimum of 125 µs.

If the device is being reset from suspend, it begins a high-speed detection handshake after detecting SE0 for no fewer than 2.5 µs. With a 48-MHz clock, detection occurs after 120 clock cycles (2.5 µs).

With a 32-kHz clock, 120 clock cycles signifies 3.75 msec. Hence, a programmable value of 4 clock cycles (125 µs) is used to detect reset.

The 32-KHz Suspend feature incorporates switching to the 32-KHz clock during suspend and resume/ remote wakeup until the system comes up and starts driving 48 MHz.

Sequence of operations: 1. Detect Suspend state. Wait for an interrupt from the device core and check that USB_GINTSTS.USBSUSP is set to 1.

2. Back up the essential registers of the core. Read and store the following core registers: • USB_GINTMSK • USB_GOTGCTL • USB_GAHBCFG • USB_GUSBCFG • USB_GRXFSIZ • USB_GNPTXFSIZ • USB_DCFG • USB_DCTL • USB_DAINTMSK • USB_DIEPMSK • USB_DOEPMSK • USB_DIEPx_CTL • USB_DIEPx_TSIZ • USB_DIEPx_DMAADDR • USB_PCGCCTL • USB_DIEPTXFn 3. The application sets the PWRCLMP bit in the Power and Clock Gating Control (USB_PCGCCTL) register.

4. The application sets the USB_PCGCCTL.RSTPDWNMODULE bit.

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5. The application sets the USB_PCGCCTL.STOPPCLK bit.

6. Switch USB Core Clock (USBC) to 32 kHz.

7. Enter EM2.

Device Mode Resume (EM2 -> EM0)

Sequence if operations: 1. The core detects Resume signaling on the USB. The core generates a Resume Detected interrupt.

2. Switch USB Core Clock (USBC) back to 48 MHz.

3. The application clears the STOPPCLK bit.

4. The application clears the USB_PCGCCTL.PWRCLMP and USB_PCGCCTL.RSTPDWNMODULE

bits.

5. Restore the USB_GUSBCFG and USB_DCFG registers with the values stored during the Save operation before entering EM2.

6. Restore the following core registers with the values stored during the Save operation before entering EM2: • USB_GINTMSK • USB_GOTGCTL • USB_GUSBCFG • USB_GRXFSIZ • USB_GNPTXFSIZ • USB_DAINTMSK • USB_DIEPMSK • USB_DOEPMSK • USB_DIEPx_CTL • USB_DIEPx_TSIZ • USB_DIEPx_DMAADDR • USB_DIEPTXFn 7. The application programs CSRs, then sets the Power-On Programming Done bit in the Device Control register.

Device Mode Remote Wakeup (EM2 -> EM0)

Sequence if operations: 1. An interrupt wakes up the device from EM2.

2. Switch USB Core Clock (USBC) back to 48 MHz.

3. The application clears the STOPPCLK and GATEHCLK bits in the USB_PCGCCTL register.

4. The application clears the USB_PCGCCTL.PWRCLMP and USB_PCGCCTL.RSTPDWNMODULE

bits.

5. Restore the USB_GUSBCFG and USB_DCFG registers with the values stored during the Save operation before entering EM2 .

6. Drive remote wakeup from the core. Program USB_DCTL by performing write-only operation with the following values: • USB_DCTL.RMTWKUPSIG = 1 • Other Bits = Value stored during the Save operation before entering EM2 7. Clear all interrupt status. Wait for at least 1 millisecond of remote wakeup time and then program GINSTS register with 0xFFFFFFFF to clear all the status register fields.

8. Restore the following core registers with the values stored during the Save operation before entering EM2: • USB_GINTMSK • USB_GOTGCTL • USB_GUSBCFG • USB_GRXFSIZ • USB_GNPTXFSIZ • USB_DAINTMSK 2015-01-15 - EZR32WG Family - d0334_Rev0.50

316 • USB_DIEPMSK • USB_DOEPMSK • USB_DIEPx_CTL • USB_DIEPx_TSIZ • USB_DIEPx_DMAADDR • USB_DIEPTXFn

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9. Wait for remote wakeup time (1-15ms) and then program USB_DCTL by performing read-modify write to set USB_DCTL.RMTWKUPSIG = 0.

Device Mode Session End (EM0 -> EM2)

Sequence of operations: 1. The core detects a USB suspend and generates a Suspend Detected interrupt. The host turns off VBUS.

2. The application sets the Power Clamp bit in the Power and Clock Gating Control register.

3. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control register.

4. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register.

5. Switch USB Core clock (USBC) to 32 kHz.

6. Enter EM2.

Device Mode Session Start (EM2 -> EM0)

Sequence of operations: 1. The core detects VBUS on (voltage level within session-valid). A New Session Detected interrupt is generated.

2. Switch USB Core clock (USBC) back to 48 MHz.

3. The application clears the Stop PHY Clock bit.

4. The application clears the Power Clamp bit.

5. The application clears the Reset to Power-Down Modules bit.

6. The application programs CSRs.

7. The cores detects a USB reset.

The core enters normal operating mode.

15.4.8.2.2 Using Clock Gating in EM0/EM1

The core supports HCLK gating to reduce dynamic power to internal modules to the core during Suspend/ session-off state in EM0 and EM1.

15.4.8.2.2.1 Internal Clock Gating when the Core is in Host Mode

The following sections show the procedures you must follow to use the clock gating feature.

Host Mode Suspend and Resume With Clock Gating

Sequence of operations: 1. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend.

2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, the core gates the hclk internally.

3. The core remains in Suspend mode.

4. The application clears the Gate hclk and Stop PHY Clock bits, and the PHY clock is generated.

5. The application sets the Port Resume bit, and the core starts driving Resume signaling.

6. The application clears the Port Resume bit after at least 20 ms.

7. The core is in normal operating mode.

Host Mode Suspend and Remote Wakeup With Clock Gating

Sequence of operations: 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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1. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend.

2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, and the core gates hclk internally.

3. The core remains in Suspend mode 4. The Remote Wakeup signaling from the device is detected. The core generates a Remote Wakeup Detected interrupt.

5. The application clears the Gate hclk and Stop PHY Clock bits. The core sets the Port Resume bit.

6. The application clears the Port Resume bit after at least 20 ms.

7. The core is in normal operating mode.

Host Mode Session End and Start With Clock Gating

Sequence of operations: 1. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend.

2. The application clears the Port Power bit. The core turns off VBUS.

3. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, and the core gates hclk internally.

4. The core remains in Low-Power mode.

5. The application clears the Gate hclk bit and the application clears the Stop PHY Clock bit to start the PHY clock.

6. The application sets the Port Power bit to turn on VBUS.

7. The core detects device connection and drives a USB reset.

8. The core is in normal operating mode.

Host Mode Session End and SRP With Clock Gating

Sequence of operations: 1. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend.

2. The application clears the Port Power bit. The core turns off VBUS.

3. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, and the core gates hclk internally.

4. The core remains in Low-Power mode.

5. SRP (data line pulsing) from the device is detected. An SRP Request Detected interrupt is generated.

6. The application clears the Gate hclk bit and the Stop PHY Clock bit.

7. The core sets the Port Power bit to turn on VBUS.

8. The core detects device connection and drives a USB reset.

9. The core is in normal operating mode.

15.4.8.2.2.2 Internal Clock Gating when the Core is in Device Mode

The following sections show the procedures you must follow to use the clock gating feature.

Device Mode Suspend and Resume With Clock Gating

Sequence of operations: 1. The core detects a USB suspend and generates a Suspend Detected interrupt.

2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, and the core gates hclk.

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3. The core remains in Suspend mode.

4. The Resume signaling from the host is detected. A Resume Detected interrupt is generated.

5. The application clears the Gate hclk bit and the Stop PHY Clock bit.

6. The host finishes Resume signaling.

7. The core is in normal operating mode.

Device Mode Suspend and Remote Wakeup With Clock Gating

Sequence of operations: 1. The core detects a USB suspend and generates a Suspend Detected interrupt.

2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, the core gates hclk.

3. The core remains in Suspend mode.

4. The application clears the Gate hclk bit and the Stop PHY Clock bit.

5. The application sets the Remote Wakeup bit in the Device Control register, the core starts driving Remote Wakeup signaling.

6. The host drives Resume signaling.

7. The core is in normal operating mode.

Device Mode Session End and Start With Clock Gating

Sequence of operations: 1. The core detects a USB suspend, and generates a Suspend Detected interrupt. The host turns off VBUS.

2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, and the core gates hclk.

3. The core remains in Low-Power mode.

4. The new session is detected (A session-valid voltage is detected). A New Session Detected interrupt is generated.

5. The application clears the Gate hclk and Stop PHY Clock bits.

6. The core detects USB reset.

7. The core is in normal operating mode

Device Mode Session End and SRP With Clock Gating

Sequence of operations: 1. The core detects a USB suspend, and generates a Suspend Detected interrupt. The host turns off VBUS.

2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit in the Power and Clock Gating Control register, and the core gates hclk.

3. The core remains in Low-Power mode.

4. The application clears the Gate hclk and Stop PHY Clock bits.

5. The application sets the SRP Request bit, and the core drives data line and VBUS pulsing.

6. The host turns on VBUS, detects device connection, and drives a USB reset.

7. The core is in normal operating mode.

15.4.9 Register Usage

Only the Core Global, Power and Clock Gating, Data FIFO Access, and Host Port registers can be accessed in both Host and Device modes. When the core is operating in one mode, either Device or 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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Host, the application must not access registers from the other mode. If an illegal access occurs, a Mode Mismatch interrupt is generated and reflected in the Core Interrupt register (USB_GINTSTS.MODEMIS).

When the core switches from one mode to another, the registers in the new mode must be reprogrammed as they would be after a power-on reset.

The memory map for the core is as follows: • Core Global Registers are located in the address offset-range [0x3C000, 0x3C3FF] and typically start with first letter G.

• Host Mode Registers are located in the address offset-range [0x3C400, 0x3C7FF] and start with first letter H.

• Device Mode Registers are located in the address offset-range [0x3C800, 0x3CDFF] and start with first letter D.

• The Power and Clock Gating register is located at offset 0x3CE00.

• The Device EP/Host Channel FIFOs start at address offset 0x3D000 with 4K spacing. These registers, available in both Host and Device modes, are used to read or write the FIFO space for a specific endpoint or a channel, in a given direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the channel.

• The Direct RAM Access area start at address offset 0x5C000.

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15.5 Register Map Name

USB_CTRL

USB_STATUS USB_IF USB_IFS

USB_IFC USB_IEN

USB_ROUTE USB_GOTGCTL

USB_GOTGINT

USB_GAHBCFG

USB_GUSBCFG

USB_GRSTCTL

USB_GINTSTS

USB_GINTMSK

USB_GRXSTSR

USB_GRXSTSP

USB_GRXFSIZ

USB_GNPTXFSIZ USB_GNPTXSTS

USB_GDFIFOCFG USB_HPTXFSIZ

USB_DIEPTXF1 USB_DIEPTXF2

USB_DIEPTXF3 USB_DIEPTXF4

USB_DIEPTXF5 USB_DIEPTXF6

USB_HCFG

USB_HFIR USB_HFNUM

USB_HPTXSTS USB_HAINT

USB_HAINTMSK USB_HPRT

USB_HC0_CHAR

USB_HC0_INT

USB_HC0_INTMSK

USB_HC0_TSIZ USB_HC0_DMAADDR

USB_HCx_CHAR

The offset register address is relative to the registers base address.

Offset

0x3C114 0x3C118

0x3C400

0x3C404 0x3C408

0x3C410 0x3C414

0x3C418 0x3C440

0x3C500

0x3C508

0x3C50C

0x3C510 0x3C514

...

0x000

0x004 0x008 0x00C

0x010 0x014

0x018 0x3C000

0x3C004

0x3C008

0x3C00C

0x3C010

0x3C014

0x3C018

0x3C01C

0x3C020

0x3C024

0x3C028 0x3C02C

0x3C05C 0x3C100

0x3C104 0x3C108

0x3C10C 0x3C110

Type

RW RW RW RW R R R RW RWH RWH RW1H RW RW RW RWH RW R R W1 W1 RW RW RWH RW1H RW RWH RWH RWH RW R R RW RW R RW RW RW RW RW RW

Description

System Control Register

System Status Register Interrupt Flag Register Interrupt Flag Set Register

Interrupt Flag Clear Register Interrupt Enable Register

I/O Routing Register OTG Control and Status Register

OTG Interrupt Register

AHB Configuration Register

USB Configuration Register

Reset Register

Interrupt Register

Interrupt Mask Register

Receive Status Debug Read Register

Receive Status Read and Pop Register

Receive FIFO Size Register

Non-periodic Transmit FIFO Size Register Non-periodic Transmit FIFO/Queue Status Register

Global DFIFO Configuration Register Host Periodic Transmit FIFO Size Register

Device IN Endpoint Transmit FIFO 1 Size Register Device IN Endpoint Transmit FIFO 2 Size Register

Device IN Endpoint Transmit FIFO 3 Size Register Device IN Endpoint Transmit FIFO 4 Size Register

Device IN Endpoint Transmit FIFO 5 Size Register Device IN Endpoint Transmit FIFO 6 Size Register

Host Configuration Register

Host Frame Interval Register Host Frame Number/Frame Time Remaining Register

Host Periodic Transmit FIFO/Queue Status Register Host All Channels Interrupt Register

Host All Channels Interrupt Mask Register Host Port Control and Status Register

Host Channel x Characteristics Register

Host Channel x Interrupt Register

Host Channel x Interrupt Mask Register

Host Channel x Transfer Size Register Host Channel x DMA Address Register

Host Channel x Characteristics Register

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Offset

...

...

...

...

0x3C6A0

0x3C6A8

0x3C6AC

0x3C6B0 0x3C6B4

0x3C800

0x3C804

0x3C808

0x3C810

0x3C814

0x3C818

0x3C81C

0x3C828 0x3C82C 0x3C834

0x3C900

0x3C908

0x3C910

0x3C914 0x3C918

0x3C920

0x3C928

0x3C930

0x3C934 0x3C938

0x3C940

0x3C948

0x3C950

0x3C954 0x3C958

0x3C960

0x3C968

0x3C970

0x3C974 0x3C978

0x3C980

0x3C988

0x3C990

Name

USB_HCx_INT

USB_HCx_INTMSK

USB_HCx_TSIZ USB_HCx_DMAADDR

USB_HC13_CHAR

USB_HC13_INT

USB_HC13_INTMSK

USB_HC13_TSIZ USB_HC13_DMAADDR

USB_DCFG

USB_DCTL

USB_DSTS

USB_DIEPMSK

USB_DOEPMSK

USB_DAINT

USB_DAINTMSK

USB_DVBUSDIS USB_DVBUSPULSE USB_DIEPEMPMSK

USB_DIEP0CTL

USB_DIEP0INT

USB_DIEP0TSIZ

USB_DIEP0DMAADDR USB_DIEP0TXFSTS

USB_DIEP0_CTL

USB_DIEP0_INT

USB_DIEP0_TSIZ

USB_DIEP0_DMAADDR USB_DIEP0_TXFSTS

USB_DIEP1_CTL

USB_DIEP1_INT

USB_DIEP1_TSIZ

USB_DIEP1_DMAADDR USB_DIEP1_TXFSTS

USB_DIEP2_CTL

USB_DIEP2_INT

USB_DIEP2_TSIZ

USB_DIEP2_DMAADDR USB_DIEP2_TXFSTS

USB_DIEP3_CTL

USB_DIEP3_INT

USB_DIEP3_TSIZ

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Type

RW1H RW RW RW RWH RW1H RW RW RW RW RWH R RW RW R RW RW RW RW RWH RWH RW RW R RWH RWH RW RW R RWH RWH RW RW R RWH RWH RW RW R RWH RWH RW

Description

Host Channel x Interrupt Register

Host Channel x Interrupt Mask Register

Host Channel x Transfer Size Register Host Channel x DMA Address Register

Host Channel x Characteristics Register

Host Channel x Interrupt Register

Host Channel x Interrupt Mask Register

Host Channel x Transfer Size Register Host Channel x DMA Address Register

Device Configuration Register

Device Control Register

Device Status Register

Device IN Endpoint Common Interrupt Mask Register

Device OUT Endpoint Common Interrupt Mask Register

Device All Endpoints Interrupt Register

Device All Endpoints Interrupt Mask Register

Device VBUS Discharge Time Register Device VBUS Pulsing Time Register Device IN Endpoint FIFO Empty Interrupt Mask Register

Device IN Endpoint 0 Control Register

Device IN Endpoint 0 Interrupt Register

Device IN Endpoint 0 Transfer Size Register

Device IN Endpoint 0 DMA Address Register Device IN Endpoint 0 Transmit FIFO Status Register

Device IN Endpoint x+1 Control Register

Device IN Endpoint x+1 Interrupt Register

Device IN Endpoint x+1 Transfer Size Register

Device IN Endpoint x+1 DMA Address Register Device IN Endpoint x+1 Transmit FIFO Status Register

Device IN Endpoint x+1 Control Register

Device IN Endpoint x+1 Interrupt Register

Device IN Endpoint x+1 Transfer Size Register

Device IN Endpoint x+1 DMA Address Register Device IN Endpoint x+1 Transmit FIFO Status Register

Device IN Endpoint x+1 Control Register

Device IN Endpoint x+1 Interrupt Register

Device IN Endpoint x+1 Transfer Size Register

Device IN Endpoint x+1 DMA Address Register Device IN Endpoint x+1 Transmit FIFO Status Register

Device IN Endpoint x+1 Control Register

Device IN Endpoint x+1 Interrupt Register

Device IN Endpoint x+1 Transfer Size Register

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Offset

0x3C994 0x3C998

0x3C9A0

0x3C9A8

0x3C9B0

0x3C9B4 0x3C9B8

0x3C9C0

0x3C9C8

0x3C9D0

0x3C9D4 0x3C9D8

0x3CB00

0x3CB08

0x3CB10

0x3CB14 0x3CB20

0x3CB28

0x3CB30

0x3CB34

0x3CB40

0x3CB48

0x3CB50

0x3CB54

0x3CB60

0x3CB68

0x3CB70

0x3CB74

0x3CB80

0x3CB88

0x3CB90

0x3CB94

0x3CBA0

0x3CBA8

0x3CBB0

0x3CBB4

0x3CBC0

0x3CBC8

0x3CBD0

0x3CBD4 0x3CE00

0x3D000

Name

USB_DIEP3_DMAADDR USB_DIEP3_TXFSTS

USB_DIEP4_CTL

USB_DIEP4_INT

USB_DIEP4_TSIZ

USB_DIEP4_DMAADDR USB_DIEP4_TXFSTS

USB_DIEP5_CTL

USB_DIEP5_INT

USB_DIEP5_TSIZ

USB_DIEP5_DMAADDR USB_DIEP5_TXFSTS

USB_DOEP0CTL

USB_DOEP0INT

USB_DOEP0TSIZ

USB_DOEP0DMAADDR USB_DOEP0_CTL

USB_DOEP0_INT

USB_DOEP0_TSIZ

USB_DOEP0_DMAADDR

USB_DOEP1_CTL

USB_DOEP1_INT

USB_DOEP1_TSIZ

USB_DOEP1_DMAADDR

USB_DOEP2_CTL

USB_DOEP2_INT

USB_DOEP2_TSIZ

USB_DOEP2_DMAADDR

USB_DOEP3_CTL

USB_DOEP3_INT

USB_DOEP3_TSIZ

USB_DOEP3_DMAADDR

USB_DOEP4_CTL

USB_DOEP4_INT

USB_DOEP4_TSIZ

USB_DOEP4_DMAADDR

USB_DOEP5_CTL

USB_DOEP5_INT

USB_DOEP5_TSIZ

USB_DOEP5_DMAADDR USB_PCGCCTL

USB_FIFO0D0

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Type

RW R RWH RWH RW RW R RWH RWH RW RW R RWH RWH RW RW RWH RWH RWH RW RWH RWH RWH RW RWH RWH RWH RW RWH RWH RWH RW RWH RWH RWH RW RWH RWH RWH RW RWH RW

Description

Device IN Endpoint x+1 DMA Address Register Device IN Endpoint x+1 Transmit FIFO Status Register

Device IN Endpoint x+1 Control Register

Device IN Endpoint x+1 Interrupt Register

Device IN Endpoint x+1 Transfer Size Register

Device IN Endpoint x+1 DMA Address Register Device IN Endpoint x+1 Transmit FIFO Status Register

Device IN Endpoint x+1 Control Register

Device IN Endpoint x+1 Interrupt Register

Device IN Endpoint x+1 Transfer Size Register

Device IN Endpoint x+1 DMA Address Register Device IN Endpoint x+1 Transmit FIFO Status Register

Device OUT Endpoint 0 Control Register

Device OUT Endpoint 0 Interrupt Register

Device OUT Endpoint 0 Transfer Size Register

Device OUT Endpoint 0 DMA Address Register Device OUT Endpoint x+1 Control Register

Device OUT Endpoint x+1 Interrupt Register

Device OUT Endpoint x+1 Transfer Size Register

Device OUT Endpoint x+1 DMA Address Register

Device OUT Endpoint x+1 Control Register

Device OUT Endpoint x+1 Interrupt Register

Device OUT Endpoint x+1 Transfer Size Register

Device OUT Endpoint x+1 DMA Address Register

Device OUT Endpoint x+1 Control Register

Device OUT Endpoint x+1 Interrupt Register

Device OUT Endpoint x+1 Transfer Size Register

Device OUT Endpoint x+1 DMA Address Register

Device OUT Endpoint x+1 Control Register

Device OUT Endpoint x+1 Interrupt Register

Device OUT Endpoint x+1 Transfer Size Register

Device OUT Endpoint x+1 DMA Address Register

Device OUT Endpoint x+1 Control Register

Device OUT Endpoint x+1 Interrupt Register

Device OUT Endpoint x+1 Transfer Size Register

Device OUT Endpoint x+1 DMA Address Register

Device OUT Endpoint x+1 Control Register

Device OUT Endpoint x+1 Interrupt Register

Device OUT Endpoint x+1 Transfer Size Register

Device OUT Endpoint x+1 DMA Address Register Power and Clock Gating Control Register

Device EP 0/Host Channel 0 FIFO

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Offset

...

0x3D7FC 0x3E000

...

0x3E7FC

0x3F000

...

0x3F7FC 0x40000

...

0x407FC

0x41000

...

0x417FC 0x42000

...

0x427FC

0x43000

...

0x437FC 0x44000

...

0x447FC 0x45000

...

0x457FC

0x46000

...

0x467FC 0x47000

...

0x477FC

0x48000

...

0x487FC 0x49000

...

0x497FC

0x4A000

...

0x4A7FC

0x5C000

Name

USB_FIFO0Dx USB_FIFO0D511 USB_FIFO1D0 USB_FIFO1Dx USB_FIFO1D511

USB_FIFO2D0 USB_FIFO2Dx USB_FIFO2D511 USB_FIFO3D0 USB_FIFO3Dx USB_FIFO3D511

USB_FIFO4D0 USB_FIFO4Dx USB_FIFO4D511 USB_FIFO5D0 USB_FIFO5Dx USB_FIFO5D511

USB_FIFO6D0 USB_FIFO6Dx USB_FIFO6D511 USB_FIFO7D0 USB_FIFO7Dx USB_FIFO7D511 USB_FIFO8D0 USB_FIFO8Dx USB_FIFO8D511

USB_FIFO9D0 USB_FIFO9Dx USB_FIFO9D511 USB_FIFO10D0 USB_FIFO10Dx USB_FIFO10D511

USB_FIFO11D0 USB_FIFO11Dx USB_FIFO11D511 USB_FIFO12D0 USB_FIFO12Dx USB_FIFO12D511

USB_FIFO13D0 USB_FIFO13Dx USB_FIFO13D511

USB_FIFORAM0

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Type

RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Description

Device EP 0/Host Channel 0 FIFO Device EP 0/Host Channel 0 FIFO Device EP 1/Host Channel 1 FIFO Device EP 1/Host Channel 1 FIFO Device EP 1/Host Channel 1 FIFO

Device EP 2/Host Channel 2 FIFO Device EP 2/Host Channel 2 FIFO Device EP 2/Host Channel 2 FIFO Device EP 3/Host Channel 3 FIFO Device EP 3/Host Channel 3 FIFO Device EP 3/Host Channel 3 FIFO

Device EP 4/Host Channel 4 FIFO Device EP 4/Host Channel 4 FIFO Device EP 4/Host Channel 4 FIFO Device EP 5/Host Channel 5 FIFO Device EP 5/Host Channel 5 FIFO Device EP 5/Host Channel 5 FIFO

Device EP 6/Host Channel 6 FIFO Device EP 6/Host Channel 6 FIFO Device EP 6/Host Channel 6 FIFO Host Channel 7 FIFO Host Channel 7 FIFO Host Channel 7 FIFO Host Channel 8 FIFO Host Channel 8 FIFO Host Channel 8 FIFO

Host Channel 9 FIFO Host Channel 9 FIFO Host Channel 9 FIFO Host Channel 10 FIFO Host Channel 10 FIFO Host Channel 10 FIFO

Host Channel 11 FIFO Host Channel 11 FIFO Host Channel 11 FIFO Host Channel 12 FIFO Host Channel 12 FIFO Host Channel 12 FIFO

Host Channel 13 FIFO Host Channel 13 FIFO Host Channel 13 FIFO

Direct Access to Data FIFO RAM for Debugging (2 KB)

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Offset

...

0x5C7FC

Name

USB_FIFORAMx USB_FIFORAM511

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Type

RW RW

Description

Direct Access to Data FIFO RAM for Debugging (2 KB) Direct Access to Data FIFO RAM for Debugging (2 KB)

15.6 Register Description

15.6.1 USB_CTRL - System Control Register

Offset

0x000

Reset Access Bit Position Name Bit

31:26

25:24

23:22

21:20

19:18

17 16

15:2

1 0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BIASPROGEM23 0x0 RW

Regulator Bias Programming Value in EM2/3

Regulator bias current setting in EM2/3 (i.e. while USB in suspend).

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BIASPROGEM01 0x0 RW Regulator bias current setting in EM0/1 (i.e. while USB active).

Regulator Bias Programming Value in EM0/1

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

VREGOSEN 0 RW Set this bit to enable USB_VREGO voltage level sensing.

VREGO Sense Enable

VREGDIS 0 Set this bit to disable the voltage regulator.

Reserved

RW

Voltage Regulator Disable

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DMPUAP 0 RW Use this bit to select the active polarity of the USB_DMPU pin.

DMPU Active Polarity

Value 0 1 Mode LOW HIGH Description USB_DMPU is active low.

USB_DMPU is active high.

VBUSENAP 0 RW

VBUSEN Active Polarity

Use this bit to select the active polarity of the USB_VBUSEN pin.

Value 0 1 Mode LOW HIGH Description USB_VBUSEN is active low.

USB_VBUSEN is active high.

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15.6.2 USB_STATUS - System Status Register

Offset

0x004

Reset Access Bit Position Name Bit

31:1

0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

VREGOS 0 R

VREGO Sense Output

USB_VREGO Voltage Sense output. 0 when no USB_VREGO voltage, 1 when USB_VREGO above approximately 1.8 V. Always 0 when VREGOSEN in USB_CTRL is 0.

15.6.3 USB_IF - Interrupt Flag Register

Offset

0x008

Reset Access Bit Position Name Bit

31:2

1 0

Name Reset Access Description

Reserved

VREGOSL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

1 R Set when USB_VREGO drops below approximately 1.8 V.

VREGOSH 1 R Set when USB_VREGO goes above approximately 1.8 V.

VREGO Sense Low Interrupt Flag VREGO Sense High Interrupt Flag

15.6.4 USB_IFS - Interrupt Flag Set Register

Offset

0x00C

Reset Access Bit Position Name Bit

31:2

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

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Bit

1 0

Name Reset Access

VREGOSL 0 W1 Write to 1 to set the VREGO Sense Low Interrupt Flag.

VREGOSH 0 W1 Write to 1 to set the VREGO Sense High Interrupt Flag.

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Description Set VREGO Sense Low Interrupt Flag Set VREGO Sense High Interrupt Flag

15.6.5 USB_IFC - Interrupt Flag Clear Register

Bit Position Offset

0x010

Reset Access Name Bit

31:2

1 0

Name

Reserved

VREGOSL

Reset

0

Access

W1 Write to 1 to clear the VREGO Sense Low Interrupt Flag.

VREGOSH 0 W1 Write to 1 to clear the VREGO Sense High Interrupt Flag.

Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

Clear VREGO Sense Low Interrupt Flag Clear VREGO Sense High Interrupt Flag

15.6.6 USB_IEN - Interrupt Enable Register

Bit Position Offset

0x014

Reset Access Name Bit

31:2

1 0

Name Reset Access Description

Reserved

VREGOSL

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Enable interrupt on VREGO Sense Low.

VREGOSH 0 Enable interrupt on VREGO Sense High.

RW RW

VREGO Sense Low Interrupt Enable VREGO Sense High Interrupt Enable

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15.6.7 USB_ROUTE - I/O Routing Register

Offset

0x018

Reset Access Bit Position Name Bit

31:3

2 1 0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DMPUPEN 0 When set, the USB_DMPU pin is enabled.

VBUSENPEN 0 When set, the USB_VBUSEN pin is enabled.

RW RW

DMPU Pin Enable VBUSEN Pin Enable

PHYPEN 0 RW

USB PHY Pin Enable

When set, the USB PHY and USB pins are enabled. The USB_DP and USB_DM are changed from regular GPIO pins to USB pins.

15.6.8 USB_GOTGCTL - OTG Control and Status Register

The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the core.

Offset

0x3C000

Reset Access Bit Position Name Bit

31:21

20 19 18

Name Reset Access Description

Reserved

OTGVER Indicates the OTG revision.

0

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RW

OTG Version

Value 0 1 Mode OTG13 OTG20 Description OTG Version 1.3. In this version the core supports data line pulsing and VBus pulsing for SRP.

OTG Version 2.0. In this version the core supports only data line pulsing for SRP.

BSESVLD 0 R

B-Session Valid device only

Indicates the Device mode transceiver status for B-session valid. In OTG mode, you can use this bit to determine if the device is connected or disconnected.

ASESVLD 0 R Indicates the Host mode transceiver status for A-session valid.

A-Session Valid host only

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Bit

17 16

15:12

11 10 9 8 7 6 5 4 3 2 1 0

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Name Reset Access

DBNCTIME 0 R Indicates the debounce time of a detected connection.

Value 0 1 Mode LONG SHORT

Description Long/Short Debounce Time host only

Description Long debounce time, used for physical connections (100 ms + 2.5 us).

Short debounce time, used for soft connections (2.5 us).

CONIDSTS 1 R Indicates the connector ID status on a connect event.

Value 0 1 Mode A B

Connector ID Status host and device

Description The core is in A-Device mode.

The core is in B-Device mode.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DEVHNPEN 0 RW

Device HNP Enabled device only

The application sets this bit when it successfully receives a SetFeature.SetHNPEnable command from the connected USB host.

HSTSETHNPEN 0 RW

Host Set HNP Enable host only

The application sets this bit when it has successfully enabled HNP (using the SetFeature.SetHNPEnable command) on the connected device.

HNPREQ 0 RW

HNP Request device only

The application sets this bit to initiate an HNP request to the connected USB host. The application can clear this bit by writing a 0 when the Host Negotiation Success Status Change bit in the OTG Interrupt register (USB_GOTGINT.HSTNEGSUCSTSCHNG) is set. The core clears this bit when the HSTNEGSUCSTSCHNG bit is cleared.

HSTNEGSCS 0 R

Host Negotiation Success device only

The core sets this bit when host negotiation is successful. The core clears this bit when the HNP Request (HNPREQ) bit in this register is set.

AVALIDOVVAL 0 RW

Avalid Override Value

This bit is used to set Override value for Avalid signal when USB_GOTGCTL.AVALIDOVEN is set.

AVALIDOVEN 0 RW

AValid Override Enable

This bit is used to enable/disable the software to override the Avalid signal using the USB_GOTGCTL.AVALIDOVVAL. When set Avalid received from the PHY is overridden with USB_GOTGCTL.AVALIDOVVAL.

BVALIDOVVAL 0 RW

Bvalid Override Value

This bit is used to set Override value for Bvalid signal when USB_GOTGCTL.BVALIDOVEN is set.

BVALIDOVEN 0 RW

BValid Override Enable

This bit is used to enable/disable the software to override the Bvalid signal using the USB_GOTGCTL.BVALIDOVVAL. When set Bvalid received from the PHY is overridden with USB_GOTGCTL.BVALIDOVVAL.

VBVALIDOVVAL 0 RW

VBUS Valid Override Value

This bit is used to set Override value for vbusvalid signal when USB_GOTGCTL.VBVALIDOVEN is set.

VBVALIDOVEN 0 RW

VBUS-Valid Override Enable

This bit is used to enable/disable the software to override the vbusvalid signal using the USB_GOTGCTL.VBVALIDOVVAL. When set, vbusvalid received from the PHY is overridden with USB_GOTGCTL.VBVALIDOVVAL.

SESREQ 0 RW

Session Request device only

The application sets this bit to initiate a session request on the USB. The application can clear this bit by writing a 0 when the Host Negotiation Success Status Change bit in the OTG Interrupt register (USB_GOTGINT.HSTNEGSUCSTSCHNG) is set. The core clears this bit when the HSTNEGSUCSTSCHNG bit is cleared. The application must wait until the VBUS discharges to 0.2 V, after the B-Session Valid bit in this register (USB_GOTGCTL.BSESVLD) is cleared. This discharge time can be obtained from the datasheet.

SESREQSCS 0 R

Session Request Success device only

The core sets this bit when a session request initiation is successful.

15.6.9 USB_GOTGINT - OTG Interrupt Register

The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.

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Offset

0x3C004

Reset Access Name

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Bit Position Bit

31:20

19 18 17

16:10

9 8

7:3

2

1:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DBNCEDONE 0 RW1H

Debounce Done host only

The core sets this bit when the debounce is completed after the device connect. The application can start driving USB reset after seeing this interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is set in the Core USB Configuration register (USB_GUSBCFG.HNPCAP or USB_GUSBCFG.SRPCAP, respectively). This bit can be set only by the core and the application should write 1 to clear it.

ADEVTOUTCHG 0 RW1H

A-Device Timeout Change host and device

The core sets this bit to indicate that the A-device has timed out while waiting for the B-device to connect. This bit can be set only by the core and the application should write 1 to clear it.

HSTNEGDET 0 RW1H

Host Negotiation Detected host and device

The core sets this bit when it detects a host negotiation request on the USB. This bit can be set only by the core and the application should write 1 to clear it.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

HSTNEGSUCSTSCHNG 0 RW1H

Host Negotiation Success Status Change host and device

The core sets this bit on the success or failure of a USB host negotiation request. The application must read the Host Negotiation Success bit of the OTG Control and Status register (USB_GOTGCTL.HSTNEGSCS) to check for success or failure. This bit can be set only by the core and the application should write 1 to clear it.

SESREQSUCSTSCHNG 0 RW1H

Session Request Success Status Change host and device

The core sets this bit on the success or failure of a session request. The application must read the Session Request Success bit in the OTG Control and Status register (USB_GOTGCTL.SESREQSCS) to check for success or failure. This bit can be set only by the core and the application should write 1 to clear it.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SESENDDET 0 RW1H

Session End Detected host and device

The core sets this bit when VBUS is in the range 0.8V - 2.0V. This bit can be set only by the core and the application should write 1 to clear it.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

15.6.10 USB_GAHBCFG - AHB Configuration Register

This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.

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Offset

0x3C008

Reset Access Name

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Bit Position

6

5

Bit

31:23

22 21

20:9

8 7 4:1

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NOTIALLDMAWRIT 0 RW

Notify All DMA Writes

This bit is programmed to enable the System DMA Done functionality for all the DMA write Transactions corresponding to the Channel/ Endpoint. This bit is valid only when USB_GAHBCFG.REMMEMSUPP is set to 1. When set, the core asserts int_dma_req for all the DMA write transactions on the AHB interface along with int_dma_done, chep_last_transact and chep_number signal informations.

The core waits for sys_dma_done signal for all the DMA write transactions in order to complete the transfer of a particular Channel/ Endpoint. When cleared, the core asserts int_dma_req signal only for the last transaction of DMA write transfer corresponding to a particular Channel/Endpoint. Similarly, the core waits for sys_dma_done signal only for that transaction of DMA write to complete the transfer of a particular Channel/Endpoint.

REMMEMSUPP 0 RW

Remote Memory Support

This bit is programmed to enable the functionality to wait for the system DMA Done Signal for the DMA Write Transfers. When set, the int_dma_req output signal is asserted when HSOTG DMA starts write transfer to the external memory. When the core is done with the Transfers it asserts int_dma_done signal to flag the completion of DMA writes from HSOTG. The core then waits for sys_dma_done signal from the system to proceed further and complete the Data Transfer corresponding to a particular Channel/Endpoint. When cleared, the int_dma_req and int_dma_done signals are not asserted and the core proceeds with the assertion of the XferComp interrupt as soon as the DMA write transfer is done at the HSOTG Core Boundary and it doesn't wait for the sys_dma_done signal to complete the DATA.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PTXFEMPLVL 0 RW

Periodic TxFIFO Empty Level host only

Indicates when the Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (USB_GINTSTS.PTXFEMP) is triggered. This bit is used only in Slave mode.

Value 0 1 Mode HALFEMPTY EMPTY Description USB_GINTSTS.PTXFEMP interrupt indicates that the Periodic TxFIFO is half empty.

USB_GINTSTS.PTXFEMP interrupt indicates that the Periodic TxFIFO is completely empty.

NPTXFEMPLVL 0 RW

Non-Periodic TxFIFO Empty Level host and device

This bit is used only in Slave mode. In host mode this bit indicates when the Non-Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (USB_GINTSTS.NPTXFEMP) is triggered. In device mode, this bit indicates when IN endpoint Transmit FIFO empty interrupt (USB_DIEP0INT/USB_DIEPx_INT.TXFEMP) is triggered.

Value 0 1 Mode HALFEMPTY EMPTY Description Host Mode: USB_GINTSTS.NPTXFEMP interrupt indicates that the Non-Periodic TxFIFO is half empty.

Device Mode: USB_DIEP0INT/USB_DIEPx_INT.TXFEMP interrupt indicates that the IN Endpoint TxFIFO is half empty.

Host Mode: USB_GINTSTS.NPTXFEMP interrupt indicates that the Non-Periodic TxFIFO is completely empty.

Device Mode: USB_DIEP0INT/USB_DIEPx_INT.TXFEMP interrupt indicates that the IN Endpoint TxFIFO is completely empty.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DMAEN 0 RW

DMA Enable host and device

When set to 0 the core operates in Slave mode. When set to 1 the core operates in a DMA mode.

HBSTLEN 0x0 This field is used in DMA mode.

RW

Burst Length/Type host and device

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0

Bit

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Name Reset Access Description

Value 0 1 3 5 7 Mode SINGLE INCR INCR4 INCR8 INCR16 Description Single transfer.

Incrementing burst of unspecified length.

4-beat incrementing burst.

8-beat incrementing burst.

16-beat incrementing burst.

GLBLINTRMSK 0 RW

Global Interrupt Mask host and device

The application uses this bit to mask or unmask the interrupt line assertion to itself. Irrespective of this bit's setting, the interrupt status registers are updated by the core. Set to unmask.

15.6.11 USB_GUSBCFG - USB Configuration Register

This register can be used to configure the core after power-on or a changing to Host mode or Device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.

Bit Position Offset

0x3C00C

Reset Access Name Bit

31 30 29 28

27:23

22

21:14

13:10

Name Reset Access Description

CORRUPTTXPKT 0 W1

Corrupt Tx packet host and device

This bit is for debug purposes only. Never Set this bit to 1. The application should always write 0 to this bit.

FORCEDEVMODE 0 RW

Force Device Mode host and device

Writing a 1 to this bit forces the core to device mode irrespective of the state of the ID pin. After setting the force bit, the application must wait at least 25 ms before the change to take effect.

FORCEHSTMODE 0 RW

Force Host Mode host and device

Writing a 1 to this bit forces the core to host mode irrespective of the state of the ID pin. After setting the force bit, the application must wait at least 65 ms before the change to take effect.

TXENDDELAY 0 RW

Tx End Delay device only

Writing 1 to this bit enables the core to follow the TxEndDelay timings as per UTMI+ specification 1.05 section 4.1.5 for opmode signal during remote wakeup.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TERMSELDLPULSE 0 RW

TermSel DLine Pulsing Selection device only

This bit selects utmi_termselect to drive data line pulse during SRP.

Value 0 1 Mode TXVALID TERMSEL Description Data line pulsing using utmi_txvalid.

Data line pulsing using utmi_termsel.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USBTRDTIM 0x5 RW

USB Turnaround Time device only

Sets the turnaround time in PHY clocks. Specifies the response time For a MAC request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). Always write this field to 5.

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7:6

5

4:3

2:0

Bit

9 8

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Name Reset Access Description

HNPCAP 0 RW

HNP-Capable host and device

The application uses this bit to control the core's HNP capabilities. Set to enable HNP capability.

SRPCAP 0 RW

SRP-Capable host and device

The application uses this bit to control the core's SRP capabilities. If the core operates as a non-SRP-capable B-device, it cannot request the connected A-device (host) to activate VBUS and start a session. Set to enable SRP capability.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 RW

Full-Speed Serial Interface Select host and device

FSINTF Always write this bit to 0.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TOUTCAL Always write this field to 0.

0x0 RW

Timeout Calibration host and device

15.6.12 USB_GRSTCTL - Reset Register

The application uses this register to reset various hardware features inside the core.

Offset

0x3C010

Bit Position Reset Access Name Bit

31 30

29:11

10:6 5

Name Reset Access Description

AHBIDLE 1 R

AHB Master Idle host and device

Indicates that the AHB Master State Machine is in the IDLE condition.

DMAREQ 0 R Indicates that the DMA request is in progress. Used for debug.

DMA Request Signal host and device

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXFNUM 0x00 RW

TxFIFO Number host and device

This is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not be changed until the core clears the TxFIFO Flush bit.

Value 0 1 2 3 4 5 6 16 Mode F0 F1 F2 F3 F4 F5 F6 FALL Description Host mode: Non-periodic TxFIFO flush.

Device: Tx FIFO 0 flush Host mode: Periodic TxFIFO flush.

Device: TXFIFO 1 flush.

Device mode: TXFIFO 2 flush.

Device mode: TXFIFO 3 flush.

Device mode: TXFIFO 4 flush.

Device mode: TXFIFO 5 flush.

Device mode: TXFIFO 6 flush.

Flush all the transmit FIFOs in device or host mode.

TXFFLSH 0 RW1H

TxFIFO Flush host and device

This bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the midst of a transaction. The application must write this bit only after checking that the core is neither writing to the TxFIFO nor reading from the TxFIFO. NAK Effective 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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Bit

4

1

0

3

2

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Name Reset Access Description

Interrupt ensures the core is not reading from the FIFO. USB_GRSTCTL.AHBIDLE ensures the core is not writing anything to the FIFO. Flushing is normally recommended when FIFOs are reconfigured. FIFO flushing is also recommended during device endpoint disable. The application must wait until the core clears this bit before performing any operations. This bit takes eight clocks to clear.

RXFFLSH 0 RW1H

RxFIFO Flush host and device

The application can flush the entire RxFIFO using this bit, but must first ensure that the core is not in the middle of a transaction. The application must only write to this bit after checking that the core is neither reading from the RxFIFO nor writing to the RxFIFO. The application must wait until the bit is cleared before performing any other operations. This bit requires 8 clocks to clear.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

FRMCNTRRST 0 RW1H

Host Frame Counter Reset host only

The application writes this bit to reset the frame number counter inside the core. When the frame counter is reset, the subsequent SOF sent out by the core has a frame number of 0. When application writes 1 to the bit, it might not be able to read back the value as it will get cleared by the core in a few clock cycles.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

CSFTRST 0 RW1H

Core Soft Reset host and device

Resets the core by clearing the interrupts and all the CSR registers except the following register bits: USB_PCGCCTL.RSTPDWNMODULE, USB_PCGCCTL.GATEHCLK, USB_PCGCCTL.PWRCLMP, USB_GUSBCFG.FSINTF, USB_HCFG.FSLSPCLKSEL, USB_DCFG.DEVSPD.

All module state machines (except the AHB Slave Unit) are reset to the IDLE state, and all the transmit FIFOs and the receive FIFO are flushed. Any transactions on the AHB Master are terminated as soon as possible, after gracefully completing the last data phase of an AHB transfer. Any transactions on the USB are terminated immediately. The application can write to this bit any time it wants to reset the core. This is a self-clearing bit and the core clears this bit after all the necessary logic is reset in the core, which can take several clocks, depending on the current state of the core. Once this bit is cleared software must wait at least 3 clock cycles before doing any access to the core. Software must also must check that bit 31 of this register is 1 (AHB Master is IDLE) before starting any operation.

15.6.13 USB_GINTSTS - Interrupt Register

This register interrupts the application for system-level events in the current mode (Device mode or Host mode). Some of the bits in this register are valid only in Host mode, while others are valid in Device mode only. This register also indicates the current mode. To clear the interrupt status bits of type RW1H, the application must write 1 into the bit.

The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically.

The application must clear the USB_GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.

Offset Bit Position

0x3C014

Reset Access Name Bit

31 30

Name Reset Access Description

WKUPINT 0 RW1H

Resume/Remote Wakeup Detected Interrupt host and device

Wakeup Interrupt during Suspend state. In Device mode this interrupt is asserted only when Host Initiated Resume is detected on USB. In Host mode this interrupt is asserted only when Device Initiated Remote Wakeup is detected on USB. This bit can be set only by the core and the application should write 1 to clear.

SESSREQINT 0 RW1H

Session Request/New Session Detected Interrupt host and device

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Bit

29 28

27

26 25 24 23 22 21 20 19 18

17:16

15

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Name Reset Access Description

In Host mode, this interrupt is asserted when a session request is detected from the device. In Device mode, this interrupt is asserted when the VBUS voltage reaches the session-valid level. This bit can be set only by the core and the application should write 1 to clear.

DISCONNINT 0 RW1H

Disconnect Detected Interrupt host only

Asserted when a device disconnect is detected. This bit can be set only by the core and the application should write 1 to clear it.

CONIDSTSCHNG 1 RW1H

Connector ID Status Change host and device

The core sets this bit when there is a change in connector ID status. This bit can be set only by the core and the application should write 1 to clear it.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PTXFEMP 1 R

Periodic TxFIFO Empty host only

This interrupt is asserted when the Periodic Transmit FIFO is either half or completely empty and there is space for at least one entry to be written in the Periodic Request Queue. The half or completely empty status is determined by the Periodic TxFIFO Empty Level bit in the Core AHB Configuration register (USB_GAHBCFG.PTXFEMPLVL).

HCHINT 0 R

Host Channels Interrupt host only

The core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in Host mode). The application must read the Host All Channels Interrupt (USB_HAINT) register to determine the exact number of the channel on which the interrupt occurred, and then read the corresponding Host Channel-x Interrupt (USB_HCx_INT) register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the USB_HCx_INT register to clear this bit.

PRTINT 0 R

Host Port Interrupt host only

The core sets this bit to indicate a change in port status in Host mode. The application must read the Host Port Control and Status (USB_HPRT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the Host Port Control and Status register to clear this bit.

RESETDET 0 RW1H

Reset detected Interrupt device only

In Device mode, this interrupt is asserted when a reset is detected on the USB in EM2 when the device is in Suspend.

In Host mode, this interrupt is not asserted.

FETSUSP 0 RW1H

Data Fetch Suspended device only

This interrupt is valid only in DMA mode. This interrupt indicates that the core has stopped fetching data for IN endpoints due to the unavailability of TxFIFO space or Request Queue space. This interrupt is used by the application for an endpoint mismatch algorithm.

For example, after detecting an endpoint mismatch, the application: Sets a Global non-periodic IN NAK handshake, Disables In endpoints, Flushes the FIFO, Determines the token sequence from the IN Token Sequence, Re-enables the endpoints, Clears the Global non-periodic IN NAK handshake.

If the Global non-periodic IN NAK is cleared, the core has not yet fetched data for the IN endpoint, and the IN token is received: the core generates an IN Token Received when FIFO Empty interrupt. The OTG then sends the host a NAK response. To avoid this scenario, the application can check the USB_GINTSTS.FETSUSP interrupt, which ensures that the FIFO is full before clearing a Global NAK handshake. Alternatively, the application can mask the IN Token Received when FIFO Empty interrupt when clearing a Global IN NAK handshake.

INCOMPLP 0 RW1H

Incomplete Periodic Transfer host and device

In Host mode, the core sets this interrupt bit when there are incomplete periodic transactions still pending which are scheduled for the current frame. In Device mode, the core sets this interrupt to indicate that there is at least one isochronous OUT endpoint on which the transfer is not completed in the current frame. This bit can be set only by the core and the application should write 1 to clear it.

INCOMPISOIN 0 RW1H

Incomplete Isochronous IN Transfer device only

The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in the current frame.

OEPINT 0 R

OUT Endpoints Interrupt device only

The core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of the core (in Device mode). The application must read the Device All Endpoints Interrupt (USB_DAINT) register to determine the exact number of the OUT endpoint on which the interrupt occurred, and then read the corresponding Device OUT Endpoint-x Interrupt (USB_DOEP0INT/USB_DOEPx_INT) register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding USB_DOEP0INT/USB_DOEPx_INT register to clear this bit.

IEPINT 0 R

IN Endpoints Interrupt device only

The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the core (in Device mode). The application must read the Device All Endpoints Interrupt (USB_DAINT) register to determine the exact number of the IN endpoint on Device IN Endpoint-x Interrupt (USB_DIEP0INT/USB_DIEPx_INT) register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding USB_DIEP0INT/USB_DIEPx_INT register to clear this bit.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

EOPF 0 RW

End of Periodic Frame Interrupt

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7

Bit

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Name Reset Access Description

Indicates that the period specified in the Periodic Frame Interval field of the Device Configuration register (DCFG_PERFRINT) has been reached in the current microframe.

ISOOUTDROP 0 RW1H

Isochronous OUT Packet Dropped Interrupt device only

The core sets this bit when it fails to write an isochronous OUT packet into the RxFIFO because the RxFIFO does not have enough space to accommodate a maximum packet size packet for the isochronous OUT endpoint.

ENUMDONE 0 RW1H

Enumeration Done device only

The core sets this bit to indicate that speed enumeration is complete. The application must read the Device Status (USB_DSTS) register to obtain the enumerated speed.

USBRST 0 RW1H

USB Reset device only

The core sets this bit to indicate that a reset is detected on the USB.

USBSUSP 0 RW1H

USB Suspend device only

The core sets this bit to indicate that a suspend was detected on the USB. The core enters the Suspended state when there is no activity on the bus for an extended period of time.

ERLYSUSP 0 RW1H

Early Suspend device only

The core sets this bit to indicate that an Idle state has been detected on the USB for 3 ms.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

GOUTNAKEFF 0 R

Global OUT NAK Effective device only

Indicates that the Set Global OUT NAK bit in the Device Control register (USB_DCTL.SGOUTNAK), set by the application, has taken effect in the core. This bit can be cleared by writing the Clear Global OUT NAK bit in the Device Control register (USB_DCTL.CGOUTNAK).

GINNAKEFF 0 R

Global IN Non-periodic NAK Effective device only

Indicates that the Set Global Non-periodic IN NAK bit in the Device Control register (USB_DCTL.SGNPINNAK), set by the application, has taken effect in the core. That is, the core has sampled the Global IN NAK bit set by the application. This bit can be cleared by clearing the Clear Global Non-periodic IN NAK bit in the Device Control register (USB_DCTL.CGNPINNAK). This interrupt does not necessarily mean that a NAK handshake is sent out on the USB. The STALL bit takes precedence over the NAK bit.

NPTXFEMP 1 R

Non-Periodic TxFIFO Empty host only

This interrupt is asserted when the Non-periodic TxFIFO is either half or completely empty, and there is space for at least one entry to be written to the Non-periodic Transmit Request Queue. The half or completely empty status is determined by the Non-periodic TxFIFO Empty Level bit in the Core AHB Configuration register (USB_GAHBCFG.NPTXFEMPLVL).

RXFLVL 0 R

RxFIFO Non-Empty host and device

Indicates that there is at least one packet pending to be read from the RxFIFO.

SOF 0 RW1H

Start of Frame host and device

In Host mode, the core sets this bit to indicate that an SOF (FS) or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to this bit to clear the interrupt.

In Device mode, in the core sets this bit to indicate that an SOF token has been received on the USB. The application can read the Device Status register to get the current frame number. This interrupt is seen only when the core is operating at full-speed (FS). This bit can be set only by the core and the application should write 1 to clear it.

OTGINT 0 R

OTG Interrupt host and device

The core sets this bit to indicate an OTG protocol event. The application must read the OTG Interrupt Status (USB_GOTGINT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the USB_GOTGINT register to clear this bit.

MODEMIS 0 RW1H

Mode Mismatch Interrupt host and device

The core sets this bit when the application is trying to access a Host mode register, when the core is operating in Device mode or when the application accesses a Device mode register, when the core is operating in Host mode. The register access is ignored by the core internally and does not affect the operation of the core. This bit can be set only by the core and the application should write 1 to clear it.

CURMOD Indicates the current mode.

0 R

Current Mode of Operation host and device

Value 0 1 Mode DEVICE HOST Description Device mode.

Host mode.

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15.6.14 USB_GINTMSK - Interrupt Mask Register

This register works with the Interrupt Register (USB_GINTSTS) to interrupt the application. When an interrupt bit is masked (bit is 0), the interrupt associated with that bit is not generated. However, the USB_GINTSTS register bit corresponding to that interrupt is still set.

Offset

0x3C018

Reset Access Bit Position Name Bit

31 30 29 28

27

26 25 24 23 22 21 20 19 18

17:16

Name Reset Access Description

WKUPINTMSK 0 RW

Resume/Remote Wakeup Detected Interrupt Mask host and device

Set to 1 to unmask WKUPINT interrupt.

SESSREQINTMSK 0 RW

Session Request/New Session Detected Interrupt Mask host and device

Set to 1 to unmask SESSREQINT interrupt.

DISCONNINTMSK 0 RW

Disconnect Detected Interrupt Mask host and device

Set to 1 to unmask DISCONNINT interrupt.

CONIDSTSCHNGMSK 0 Set to 1 to unmask CONIDSTSCHNG interrupt.

RW

Reserved

Connector ID Status Change Mask host and device

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RW

Periodic TxFIFO Empty Mask host only

PTXFEMPMSK 0 Set to 1 to unmask PTXFEMP interrupt.

HCHINTMSK 0 Set to 1 to unmask HCHINT interrupt.

PRTINTMSK 0 Set to 1 to unmask PRTINT interrupt.

RESETDETMSK 0 Set to 1 to unmask RESETDET interrupt.

RW RW RW

Host Channels Interrupt Mask host only Host Port Interrupt Mask host only Reset detected Interrupt Mask device only

FETSUSPMSK 0 Set to 1 to unmask FETSUSP interrupt.

INCOMPLPMSK 0 Set to 1 to unmask INCOMPLP interrupt.

INCOMPISOINMSK 0 Set to 1 to unmask INCOMPISOIN interrupt.

RW RW RW

Data Fetch Suspended Mask device only Incomplete Periodic Transfer Mask host and device Incomplete Isochronous IN Transfer Mask device only

OEPINTMSK 0 Set to 1 to unmask OEPINT interrupt.

RW

OUT Endpoints Interrupt Mask device only

IEPINTMSK 0 Set to 1 to unmask IEPINT interrupt.

Reserved

RW

IN Endpoints Interrupt Mask device only

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

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2 1

0

13 12 11 10

9:8

7 6 5 4 3

Bit

15 14

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Name Reset Access Description

EOPFMSK 0 Set to 1 to unmask EOPF interrupt.

ISOOUTDROPMSK 0 Set to 1 to unmask ISOOUTDROP interrupt.

ENUMDONEMSK 0 Set to 1 to unmask ENUMDONE interrupt.

USBRSTMSK 0 Set to 1 to unmask USBRST interrupt.

USBSUSPMSK 0 Set to 1 to unmask USBSUSP interrupt.

RW RW RW RW RW

End of Periodic Frame Interrupt Mask device only Isochronous OUT Packet Dropped Interrupt Mask device only Enumeration Done Mask device only USB Reset Mask device only USB Suspend Mask device only

ERLYSUSPMSK 0 Set to 1 to unmask ERLYSUSP interrupt.

Reserved

RW

Early Suspend Mask device only

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

GOUTNAKEFFMSK 0 Set to 1 to unmask GOUTNAKEFF interrupt.

RW

Global OUT NAK Effective Mask device only

GINNAKEFFMSK 0 Set to 1 to unmask GINNAKEFF interrupt.

NPTXFEMPMSK 0 Set to 1 to unmask NPTXFEMP interrupt.

RXFLVLMSK 0 Set to 1 to unmask RXFLVL interrupt.

SOFMSK 0 Set to 1 to unmask SOF interrupt.

OTGINTMSK 0 Set to 1 to unmask OTGINT interrupt.

RW RW RW RW RW

Global Non-periodic IN NAK Effective Mask device only Non-Periodic TxFIFO Empty Mask host only Receive FIFO Non-Empty Mask host and device Start of Frame Mask host and device OTG Interrupt Mask host and device

MODEMISMSK 0 Set to 1 to unmask MODEMIS interrupt.

Reserved

RW

Mode Mismatch Interrupt Mask host and device

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

15.6.15 USB_GRXSTSR - Receive Status Debug Read Register

A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO.

The receive status contents must be interpreted differently in Host and Device modes. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core Interrupt register (USB_GINTSTS.RXFLVL) is asserted.

Bit Position Offset

0x3C01C

Reset Access Name

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Bit

31:28

27:24

23:21

20:17 16:15 14:4 3:0

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Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

FN 0x0 R

Frame Number device only

This is the least significant 4 bits of the Frame number in which the packet is received on the USB.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PKTSTS 0x0 Indicates the status of the received packet.

R

Packet Status (host or device)

4 5 6 7 Value 1 2 3 Mode GOUTNAK PKTRCV XFERCOMPL SETUPCOMPL TGLERR SETUPRCV CHLT Description Device mode: Global OUT NAK (triggers an interrupt).

Host mode: IN data packet received.

Device mode: OUT data packet received.

Host mode: IN transfer completed (triggers an interrupt).

Device mode: OUT transfer completed (triggers an interrupt).

Device mode: SETUP transaction completed (triggers an interrupt).

Host mode: Data toggle error (triggers an interrupt).

Device mode: SETUP data packet received.

Host mode: Channel halted (triggers an interrupt).

DPID 0x0 R

Data PID (host or device)

Host mode: Indicates the Data PID of the received packet. Device mode: Indicates the Data PID of the received OUT data packet.

Value 0 1 2 3 Mode DATA0 DATA1 DATA2 MDATA Description DATA0 PID.

DATA1 PID.

DATA2 PID.

MDATA PID.

BCNT 0x000 R

Byte Count (host or device)

Host mode: Indicates the byte count of the received IN data packet.

Device mode: Indicates the byte count of the received data packet.

CHEPNUM 0x0 R

Channel Number host only / Endpoint Number device only

Host mode: Indicates the channel number to which the current received packet belongs.

Device mode: Indicates the endpoint number to which the current received packet belongs.

15.6.16 USB_GRXSTSP - Receive Status Read and Pop Register

A read to the Receive Status Read and Pop register returns the contents of the top of the Receive FIFO and pops the top data entry out of the RxFIFO. The receive status contents must be interpreted differently in Host and Device modes. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core Interrupt register (USB_GINTSTS.RXFLVL) is asserted.

Bit Position Offset

0x3C020

Reset Access Name

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Bit

31:25

24:21 20:17 16:15 14:4 3:0

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Name Reset Access Description

Reserved

3 4 5 6 7

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

FN 0x0 R

Frame Number device only

This is the least significant 4 bits of the Frame number in which the packet is received on the USB.

PKTSTS 0x0 Indicates the status of the received packet.

R

Packet Status (host or device)

Value 1 2 Mode GOUTNAK PKTRCV XFERCOMPL SETUPCOMPL TGLERR SETUPRCV CHLT Description Device mode: Global OUT NAK (triggers an interrupt).

Host mode: IN data packet received.

Device mode: OUT data packet received.

Host mode: IN transfer completed (triggers an interrupt).

Device mode: OUT transfer completed (triggers an interrupt).

Device mode: SETUP transaction completed (triggers an interrupt).

Host mode: Data toggle error (triggers an interrupt).

Device mode: SETUP data packet received.

Host mode: Channel halted (triggers an interrupt).

DPID 0x0 R Host mode: Indicates the Data PID of the received packet.

Data PID (host or device)

Device mode: Indicates the Data PID of the received OUT data packet.

Value 0 1 2 3 Mode DATA0 DATA1 DATA2 MDATA Description DATA0 PID.

DATA1 PID.

DATA2 PID.

MDATA PID.

BCNT 0x000 R

Byte Count (host or device)

Host mode: Indicates the byte count of the received IN data packet.

Device mode: Indicates the byte count of the received data packet.

CHEPNUM 0x0 R

Channel Number host only / Endpoint Number device only

Host mode: Indicates the channel number to which the current received packet belongs.

Device mode: Indicates the endpoint number to which the current received packet belongs.

15.6.17 USB_GRXFSIZ - Receive FIFO Size Register

The application can program the RAM size that must be allocated to the RxFIFO.

Offset

0x3C024

Bit Position Reset Access Name Bit

31:10

9:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXFDEP 0x200 RW

RxFIFO Depth

This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.

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15.6.18 USB_GNPTXFSIZ - Non-periodic Transmit FIFO Size Register

The application can program the RAM size and the memory start address for the Non-periodic TxFIFO.

Offset

0x3C028

Bit Position Reset Access Name Bit

31:16

15:10

9:0

Name Reset Access Description

NPTXFINEPTXF0DEP 0x0200 RW

Non-periodic TxFIFO Depth host only / IN Endpoint TxFIFO 0 Depth device only

This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NPTXFSTADDR 0x200 RW

Non-periodic Transmit RAM Start Address host only

This field contains the memory start address for Non-periodic Transmit FIFO RAM. Programmed values must not exceed the reset value.

15.6.19 USB_GNPTXSTS - Non-periodic Transmit FIFO/Queue Status Register

This register is used in host mode only. This read-only register contains the free space information for the Non-periodic TxFIFO and the Nonperiodic Transmit Request Queue.

Offset

0x3C02C

Bit Position Reset Access Name Bit

31

30:24

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NPTXQTOP 0x00 R

Top of the Non-periodic Transmit Request Queue

Entry in the Non-periodic Tx Request Queue that is currently being processed by the MAC.

Bits [6:3]: Channel/endpoint number.

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Bit

23:16 15:0

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Name Reset Access Description

Bits [2:1]: 00: IN/OUT token, 01: Zero-length transmit packet (device IN/host OUT), 10: Unused, 11: Channel halt command.

Bit [0]: Terminate (last Entry for selected channel/endpoint).

NPTXQSPCAVAIL 0x08 R

Non-periodic Transmit Request Queue Space Available

Indicates the amount of free space (locations) available in the Non-periodic Transmit Request Queue. This queue holds both IN and OUT requests in Host mode. Device mode has only IN requests.

NPTXFSPCAVAIL 0x0200 R

Non-periodic TxFIFO Space Available

Indicates the amount of free space available in the Non-periodic TxFIFO. Values are in terms of 32-bit words.

15.6.20 USB_GDFIFOCFG - Global DFIFO Configuration Register

Offset

0x3C05C

Bit Position Reset Access Name Bit

31:16 15:0

Name Reset Access Description

EPINFOBASEADDR 0x01F2 RW This field provides the start address of the EP info controller.

Endpoint Info Base Address

GDFIFOCFG 0x0200 RW

DFIFO Config

This field is for dynamic programming of the DFIFO Size. This value takes effect only when the application programs a non zero value to this register. The core does not have any corrective logic if the FIFO sizes are programmed incorrectly.

15.6.21 USB_HPTXFSIZ - Host Periodic Transmit FIFO Size Register

This register holds the size and the memory start address of the Periodic TxFIFO.

Offset

0x3C100

Bit Position Reset Access Name Bit

31:26

25:16

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PTXFSIZE 0x200 RW

Host Periodic TxFIFO Depth

This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.

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Bit

15:11

10:0

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Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PTXFSTADDR 0x400 RW

Host Periodic TxFIFO Start Address

This field contains the memory start address for Host Periodic TxFIFO.

15.6.22 USB_DIEPTXF1 - Device IN Endpoint Transmit FIFO 1 Size Register

This register holds the size and memory start address of IN endpoint TxFIFO 1 in Device mode. For IN endpoint FIFO 0 use USB_GNPTXFSIZ register for programming the size and memory start address.

Offset

0x3C104

Bit Position Reset Access Name Bit

31:26

25:16

15:11

10:0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNTXFDEP 0x200 RW

IN Endpoint TxFIFO Depth

This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNTXFSTADDR 0x400 RW

IN Endpoint FIFO 1 Transmit RAM Start Address

This field contains the memory start address for IN endpoint Transmit FIFO 1.

15.6.23 USB_DIEPTXF2 - Device IN Endpoint Transmit FIFO 2 Size Register

This register holds the size and memory start address of IN endpoint TxFIFO 2 in Device mode. For IN endpoint FIFO 0 use USB_GNPTXFSIZ register for programming the size and memory start address.

Offset

0x3C108

Bit Position Reset Access Name Bit

31:26

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

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Bit

25:16

15:11

10:0

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Name Reset Access Description

INEPNTXFDEP 0x200 RW

IN Endpoint TxFIFO Depth

This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNTXFSTADDR 0x600 RW

IN Endpoint FIFO 2 Transmit RAM Start Address

This field contains the memory start address for IN endpoint Transmit FIFO 2.

15.6.24 USB_DIEPTXF3 - Device IN Endpoint Transmit FIFO 3 Size Register

This register holds the size and memory start address of IN endpoint TxFIFO 3 in Device mode. For IN endpoint FIFO 0 use USB_GNPTXFSIZ register for programming the size and memory start address.

Offset

0x3C10C

Bit Position Reset Access Name Bit

31:26

25:16

15:12

11:0

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNTXFDEP 0x200 RW

IN Endpoint TxFIFO Depth

This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNTXFSTADDR 0x800 RW

IN Endpoint FIFO 3 Transmit RAM Start Address

This field contains the memory start address for IN endpoint Transmit FIFO 3.

15.6.25 USB_DIEPTXF4 - Device IN Endpoint Transmit FIFO 4 Size Register

This register holds the size and memory start address of IN endpoint TxFIFO 4 in Device mode. For IN endpoint FIFO 0 use USB_GNPTXFSIZ register for programming the size and memory start address.

Offset

0x3C110

Bit Position Reset Access Name

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Bit

31:26

25:16

15:12

11:0

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Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNTXFDEP 0x200 RW

IN Endpoint TxFIFO Depth

This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNTXFSTADDR 0xA00 RW

IN Endpoint FIFO 4 Transmit RAM Start Address

This field contains the memory start address for IN endpoint Transmit FIFO 4.

15.6.26 USB_DIEPTXF5 - Device IN Endpoint Transmit FIFO 5 Size Register

This register holds the size and memory start address of IN endpoint TxFIFO 5 in Device mode. For IN endpoint FIFO 0 use USB_GNPTXFSIZ register for programming the size and memory start address.

Offset

0x3C114

Bit Position Reset Access Name Bit

31:26

25:16

15:12

11:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNTXFDEP 0x200 RW

IN Endpoint TxFIFO Depth

This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNTXFSTADDR 0xC00 RW

IN Endpoint FIFO 5 Transmit RAM Start Address

This field contains the memory start address for IN endpoint Transmit FIFO 5.

15.6.27 USB_DIEPTXF6 - Device IN Endpoint Transmit FIFO 6 Size Register

This register holds the size and memory start address of IN endpoint TxFIFO 6 in Device mode. For IN endpoint FIFO 0 use USB_GNPTXFSIZ register for programming the size and memory start address.

Offset

0x3C118

Bit Position Reset Access Name

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Bit

31:26

25:16

15:12

11:0

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Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNTXFDEP 0x200 RW

IN Endpoint TxFIFO Depth

This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNTXFSTADDR 0xE00 RW

IN Endpoint FIFO 6 Transmit RAM Start Address

This field contains the memory start address for IN endpoint Transmit FIFO 6.

15.6.28 USB_HCFG - Host Configuration Register

This register configures the core after power-on. Do not make changes to this register after initializing the host.

Offset

0x3C400

Reset Access Bit Position Name Bit

31

30:16

15:8 7

6:3

2 1:0

Name Reset Access Description

MODECHTIMEN This bit is used to enable/disable the Host core to wait 200 clock cycles at the end of Resume before changing the PHY opmode to normal operation. When set to 0 the Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the end of resume to the change the PHY opmode to normal operation. When set to 1 the Host core waits only for a linstate of SE0 at the end of resume to change the PHY opmode to normal operation.

Reserved

0 RW

Mode Change Time

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RESVALID 0x00 RW

Resume Validation Period

This field is effective only when USB_HCFG.ENA32KHZS is set. It will control the resume period when the core resumes from suspend. The core counts for RESVALID number of clock cycles to detect a valid resume when USB_HCFG.ENA32KHZS is set.

ENA32KHZS 0 RW

Enable 32 KHz Suspend mode

When this bit is set the core expects that the clock to the core during Suspend is switched from 48 MHz to 32 KHz.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

FSLSSUPP 0 RW

FS- and LS-Only Support

The application uses this bit to control the core's enumeration speed. Using this bit, the application can make the core enumerate as a FS host, even If the connected device supports HS traffic. Do not make changes to this field after initial programming.

Value 0 1 Mode HSFSLS FSLS Description HS/FS/LS, based on the maximum speed supported by the connected device.

FS/LS-only, even If the connected device can support HS.

FSLSPCLKSEL 0x0 RW

FS/LS PHY Clock Select

Use this field to set the internal PHY clock frequency. Set to 48 MHz in FS Host mode and 6 MHz in LS Host mode. When you select a 6 MHz clock during LS mode, you must do a soft reset.

Value 1 2 Mode DIV1 DIV8 Description Internal PHY clock is running at 48 MHz (undivided).

Internal PHY clock is running at 6 MHz (48 MHz divided by 8).

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15.6.29 USB_HFIR - Host Frame Interval Register

This register stores the frame interval information for the current speed to which the core has enumerated.

Offset

0x3C404

Bit Position Reset Access Name Bit

31:17

16 15:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

HFIRRLDCTRL 0 RW

Reload Control

This bit allows dynamic reloading of the HFIR register during run time. This bit needs to be programmed during initial configuration and its value should not be changed during runtime.

Value 0 1 Mode STATIC DYNAMIC Description The HFIR cannot be reloaded dynamically.

The HFIR can be dynamically reloaded during runtime.

FRINT 0x17D7 RW

Frame Interval

The value that the application programs to this field specifies the interval between two consecutive SOFs (FS) or Keep-Alive tokens (LS). This field contains the number of PHY clocks that constitute the required frame interval. The application can write a value to this register only after the Port Enable bit of the Host Port Control and Status register (USB_HPRT.PRTENA) has been set. If no value is programmed, the core calculates the value based on the PHY clock specified in the FS/LS PHY Clock Select field of the Host Configuration register (USB_HCFG.FSLSPCLKSEL). Do not change the value of this field after the initial configuration. Set to 48000 (1 ms at 48 MHz) for FS and 6000 (1 ms at 6 MHz) for LS.

15.6.30 USB_HFNUM - Host Frame Number/Frame Time Remaining Register

This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame.

Offset

0x3C408

Bit Position Reset Access Name Bit

31:16

Name

FRREM

Reset

0x0000

Access

R

Description Frame Time Remaining

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Bit

15:0

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Name Reset Access Description

Indicates the amount of time remaining in the current Frame, in terms of PHY clocks. This field decrements on each PHY clock. When it reaches zero, this field is reloaded with the value in the Frame Interval register and a new SOF is transmitted on the USB.

FRNUM 0x3FFF R

Frame Number

This field increments when a new SOF is transmitted on the USB, and is reset to 0 when it reaches 0x3FFF.

15.6.31 USB_HPTXSTS - Host Periodic Transmit FIFO/Queue Status Register

This read-only register contains the free space information for the Periodic TxFIFO and the Periodic Transmit Request Queue.

Offset

0x3C410

Bit Position Reset Access Name Bit

31:24 23:16 15:0

Name Reset Access Description

PTXQTOP 0x00 R

Top of the Periodic Transmit Request Queue

This indicates the Entry in the Periodic Tx Request Queue that is currently being processes by the MAC. This register is used for debugging.

Bit [7]: Odd/Even Frame. 0: send in even Frame, 1: send in odd Frame.

Bits [6:3]: Channel/endpoint number.

Bits [2:1]: Type. 00: IN/OUT, 01: Zero-length packet, 10: Unused, 11: Disable channel command.

Bit [0]: Terminate (last Entry for the selected channel/endpoint).

PTXQSPCAVAIL 0x08 R

Periodic Transmit Request Queue Space Available

Indicates the number of free locations available to be written in the Periodic Transmit Request Queue. This queue holds both IN and OUT requests.

PTXFSPCAVAIL 0x0200 R

Periodic Transmit Data FIFO Space Available

Indicates the number of free locations available to be written to in the Periodic TxFIFO. Values are in terms of 32-bit words.

15.6.32 USB_HAINT - Host All Channels Interrupt Register

When a significant event occurs on a channel, the Host All Channels Interrupt register interrupts the application using the Host Channels Interrupt bit of the Core Interrupt register (USB_GINTSTS.HCHINT).

There is one interrupt bit per channel. Bits in this register are set and cleared when the application sets and clears bits in the corresponding Host Channel x Interrupt register.

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Offset

0x3C414

Reset Access Name

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Bit Position Bit

31:14

13:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

HAINT 0x0000 R

Channel Interrupt for channel 0 - 13.

When the interrupt bit for a channel x set, one or more of the interrupt flags in the USB_HCx_INT are set.

15.6.33 USB_HAINTMSK - Host All Channels Interrupt Mask Register

The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel. Set bits to unmask.

Offset

0x3C418

Bit Position Reset Access Name Bit

31:14

13:0

Name Reset Access Description

Reserved

HAINTMSK

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0000 Set bit n to unmask channel n interrupts.

RW

Channel Interrupt Mask for channel 0 - 13

15.6.34 USB_HPRT - Host Port Control and Status Register

This register is available only in Host mode. This register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for the port. Some bits in this register can trigger an interrupt to the application through the Host Port Interrupt bit of the Core Interrupt register (USB_GINTSTS.PRTINT). On a Port Interrupt, the application must read this register and clear the bit that caused the interrupt. For the RW1H bits, the application must write a 1 to the bit to clear the interrupt.

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Offset

0x3C440

Reset Access Name

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Bit Position

9

8

Bit

31:19

18:17 16:13 12 11:10 7 6

Name Reset Access Description

Reserved

PRTSPD

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x0 R Indicates the speed of the device attached to this port.

Port Speed

Value 0 1 2 Mode HS FS LS Description High speed.

Full speed.

Low speed.

PRTTSTCTL 0x0 RW

Port Test Control

The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is signaled on the port.

3 4 5 Value 0 1 2 Mode DISABLE J K SE0NAK PACKET FORCE Description Test mode disabled.

Test_J mode.

Test_K mode.

Test_SE0_NAK mode.

Test_Packet mode.

Test_Force_Enable.

PRTPWR 0 RW

Port Power

The application uses this field to control power to this port. The core can clear this bit on an over current condition.

Value 0 1 Mode OFF ON Description Power off.

Power on.

PRTLNSTS 0x0 R

Port Line Status

Indicates the current logic level USB data lines. Bit [0]: Logic level of D+. Bit [1]: Logic level of D-.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PRTRST 0 RW

Port Reset

When the application sets this bit, a reset sequence is started on this port. The application must time the reset period and clear this bit after the reset sequence is complete. The application must leave this bit set for at least 10 ms to start a reset on the port. The application can leave it set for another 10 ms in addition to the required minimum duration, before clearing the bit, even though there is no maximum limit set by the USB standard.

PRTSUSP 0 RW1H

Port Suspend

The application sets this bit to put this port in Suspend mode. The core only stops sending SOFs when this is set. To stop the PHY clock, the application must set USB_PCGCCTL.STOPPCLK, which puts the PHY into suspend mode. The read value of this bit reflects the current suspend status of the port. This bit is cleared by the core after a remote wakeup signal is detected or the application sets the Port Reset bit or Port Resume bit in this register or the Resume/Remote Wakeup Detected Interrupt bit or Disconnect Detected Interrupt bit in the Core Interrupt register (USB_GINTSTS.WKUPINT or USB_GINTSTS.DISCONNINT respectively). This bit is cleared by the core even if there is no device connected to the Host.

PRTRES 0 RW

Port Resume

The application sets this bit to drive resume signaling on the port. The core continues to drive the resume signal until the application clears this bit. If the core detects a USB remote wakeup sequence, as indicated by the Port Resume/Remote Wakeup Detected 2015-01-15 - EZR32WG Family - d0334_Rev0.50

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5 4 3 2 1 0

Bit

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Name Reset Access Description

Interrupt bit of the Core Interrupt register (USB_GINTSTS.WKUPINT), the core starts driving resume signaling without application intervention and clears this bit when it detects a disconnect condition. The read value of this bit indicates whether the core is currently driving resume signaling.

PRTOVRCURRCHNG 0 RW1H

Port Overcurrent Change

The core sets this bit when the status of the Port Overcurrent Active bit (bit 4) in this register changes. This bit can be set only by the core and the application should write 1 to clear it.

PRTOVRCURRACT 0 R

Port Overcurrent Active

Indicates the overcurrent condition of the port. When there is an overcurrent condition this bit is 1.

PRTENCHNG 0 RW1H

Port Enable/Disable Change

The core sets this bit when the status of the Port Enable bit[2] of this register changes. This bit can be set only by the core and the application should write 1 to clear it.

PRTENA 0 RW1H

Port Enable

A port is enabled only by the core after a reset sequence, and is disabled by an overcurrent condition, a disconnect condition, or by the application clearing this bit. The application cannot set this bit by a register write. It can only clear it to disable the port by writing 1. This bit does not trigger any interrupt to the application.

PRTCONNDET 0 RW1H

Port Connect Detected

The core sets this bit when a device connection is detected to trigger an interrupt to the application using the Host Port Interrupt bit of the Core Interrupt register (USB_GINTSTS.PRTINT). This bit can be set only by the core and the application should write 1 to clear it. The application must write a 1 to this bit to clear the interrupt.

PRTCONNSTS 0 R When this bit is 1 a device is attached to the port.

Port Connect Status

15.6.35 USB_HCx_CHAR - Host Channel x Characteristics Register

Bit Position Offset

0x3C500

Reset Access Name Bit

31 30 29 28:22 21:20

Name Reset Access Description

CHENA 0 RW1H

Channel Enable

This field is set by the application and cleared by the core. The state of this bit reflects the channel enable status.

CHDIS 0 RW1H

Channel Disable

The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete.

The application must wait for the Channel Disabled interrupt before treating the channel as disabled.

ODDFRM 0 RW

Odd Frame

This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions.

DEVADDR 0x00 RW

Device Address

This field selects the specific device serving as the data source or sink.

MC 0x0 RW

Multi Count

For periodic transfers this field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is used only in DMA mode, and specifies the number packets to be fetched for this channel before the internal DMA engine changes arbitration.

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Bit

19:18 17

16

15 14:11 10:0

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Name Reset

EPTYPE 0x0 Indicates the transfer type selected.

Access

RW

Description Endpoint Type

Value 0 1 2 3 Mode CONTROL ISO BULK INT Description Control endpoint.

Isochronous endpoint.

Bulk endpoint.

Interrupt endpoint.

LSPDDEV 0 RW

Low-Speed Device

This field is set by the application to indicate that this channel is communicating to a low-speed device.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

EPDIR 0 Indicates whether the transaction is IN or OUT.

RW

Endpoint Direction

Value 0 1 Mode OUT IN Description Direction is OUT.

Direction is IN.

EPNUM 0x0 RW

Endpoint Number

Indicates the endpoint number on the device serving as the data source or sink.

MPS 0x000 RW Indicates the maximum packet size of the associated endpoint.

Maximum Packet Size

15.6.36 USB_HCx_INT - Host Channel x Interrupt Register

This register indicates the status of a channel with respect to USB- and AHB-related events. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (USB_GINTSTS.HCHINT) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (USB_HAINT) register to get the exact channel number for the Host Channel x Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the USB_HAINT and USB_GINTSTS registers.

Bit Position Offset

0x3C508

Reset Access Name Bit

31:11

10 9 8

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DATATGLERR 0 RW1H

Data Toggle Error

This bit can be set only by the core and the application should write 1 to clear it.

FRMOVRUN 0 RW1H

Frame Overrun

This bit can be set only by the core and the application should write 1 to clear it.

BBLERR 0 RW1H

Babble Error

This bit can be set only by the core and the application should write 1 to clear it.

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3 2

6

5 4

Bit

7 1 0

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Name Reset Access Description

XACTERR 0 RW1H

Transaction Error

Indicates one of the following errors occurred on the USB: CRC check failure, Timeout, Bit stuff error or False EOP. This bit can be set only by the core and the application should write 1 to clear it.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

ACK 0 RW1H

ACK Response Received/Transmitted Interrupt

This bit can be set only by the core and the application should write 1 to clear it.

NAK 0 RW1H

NAK Response Received Interrupt

This bit can be set only by the core and the application should write 1 to clear it.

STALL 0 RW1H

STALL Response Received Interrupt

This bit can be set only by the core and the application should write 1 to clear it.

AHBERR 0 RW1H

AHB Error

This is generated only in DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

CHHLTD 0 RW1H

Channel Halted

In DMA mode this bit indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.

XFERCOMPL 0 RW1H

Transfer Completed

Transfer completed normally without any errors. This bit can be set only by the core and the application should write 1 to clear it.

15.6.37 USB_HCx_INTMSK - Host Channel x Interrupt Mask Register

This register reflects the mask for each channel status described in the USB_CHx_INT.

Offset

0x3C50C

Reset Access Bit Position Name

6

5

Bit

31:11

10 9 8 7

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DATATGLERRMSK 0 Set to unmask DATATGLERR interrupt.

FRMOVRUNMSK 0 Set to unmask FRMOVRUN interrupt.

RW RW

Data Toggle Error Mask Frame Overrun Mask

BBLERRMSK 0 Set to unmask BBLERR interrupt.

RW

Babble Error Mask

XACTERRMSK 0 Set to unmask XACTERR interrupt.

Reserved

RW

Transaction Error Mask

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

ACKMSK Set to unmask ACK interrupt.

0 RW

ACK Response Received/Transmitted Interrupt Mask

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2 1 0

Bit

4 3

Name Reset

NAKMSK Set to unmask NAK interrupt.

0 STALLMSK 0 Set to unmask STALL interrupt.

AHBERRMSK 0 Set to unmask AHBERR interrupt.

CHHLTDMSK 0 Set to unmask CHHLTD interrupt.

XFERCOMPLMSK 0 Set to unmask XFERCOMPL interrupt.

RW RW RW

Access

RW

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Description NAK Response Received Interrupt Mask

RW

STALL Response Received Interrupt Mask AHB Error Mask Channel Halted Mask Transfer Completed Mask

15.6.38 USB_HCx_TSIZ - Host Channel x Transfer Size Register

Offset

0x3C510

Bit Position Reset Access Name Bit

31

30:29 28:19 18:0

Name Reset Access Description

Reserved

Value 0 1 2 3 Mode DATA0 DATA2 DATA1 MDATA

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PID 0x0 RW

Packet ID

The application programs this field with the packet ID type to use for the initial transaction. The host maintains this field for the rest of the transfer.

Description DATA0 PID.

DATA2 PID.

DATA1 PID.

MDATA (non-control) / SETUP (control) PID.

PKTCNT 0x000 RW

Packet Count

This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.

XFERSIZE 0x00000 RW

Transfer Size

For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).

15.6.39 USB_HCx_DMAADDR - Host Channel x DMA Address Register

This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

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Offset

0x3C514

Reset

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Bit Position Access Name Bit

31:0

Name Reset Access Description

DMAADDR 0xXXXXXXXX RW

DMA Address

This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. The data for this register field is stored in RAM. Thus, the reset value is undefined (X).

15.6.40 USB_DCFG - Device Configuration Register

This register configures the core in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.

Bit Position Offset

0x3C800

Reset Access Name Bit

31:26

25:13

12:11 10:4 3

Name Reset Access Description

RESVALID 0x02 RW

Resume Validation Period

This field is effective only when USB_DCFG.ENA32KHZSUSP is set. It will control the resume period when the core resumes from suspend. The core counts for RESVALID number of clock cycles to detect a valid resume when USB_DCFG.ENA32KHZSUSP is set.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PERFRINT 0x0 RW

Periodic Frame Interval

Indicates the time within a frame at which the application must be notified using the End Of Periodic Frame Interrupt. This can be used to determine if all the isochronous traffic for that frame is complete.

Value 0 1 2 3 Mode 80PCNT 85PCNT 90PCNT 95PCNT Description 80% of the frame interval.

85% of the frame interval.

90% of the frame interval.

95% of the frame interval.

DEVADDR 0x00 RW

Device Address

The application must program this field after every SetAddress control command.

ENA32KHZSUSP 0 RW

Enable 32 KHz Suspend mode

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Bit

2 1:0

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Name Reset Access Description

When this bit is set, the core expects that the PHY clock during Suspend is switched from 48 MHz to 32 KHz.

NZSTSOUTHSHK 0 RW

Non-Zero-Length Status OUT Handshake

The application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the OUT transaction of a control transfer's Status stage. When set to 1 send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application. When set to 0 send the received OUT packet to the application (zerolength or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register.

DEVSPD 0x0 RW

Device Speed

Indicates the speed at which the application requires the core to enumerate, or the maximum speed the application can support.

However, the actual bus speed is determined only after the chirp sequence is completed, and is based on the speed of the USB host to which the core is connected.

Value 2 3 Mode LS FS Description Low speed (PHY clock is 6 MHz). If you select 6 MHz LS mode, you must do a soft reset.

Full speed (PHY clock is 48 MHz).

15.6.41 USB_DCTL - Device Control Register

Offset

0x3C804

Reset Access Bit Position Name Bit

31:17

16 15

14:12

11 10 9 8 7 6:4

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NAKONBBLE 0 RW

NAK on Babble Error

Set NAK automatically on babble. The core sets NAK automatically for the endpoint on which babble is received.

IGNRFRMNUM 0 RW

Ignore Frame number For Isochronous End points

When set to 0 the core transmits the packets only in the frame number in which they are intended to be transmitted. When set to 1 the core ignores the frame number, sending packets immediately as the packets are ready.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PWRONPRGDONE 0 RW

Power-On Programming Done

The application uses this bit to indicate that register programming is completed after a wake-up from Power Down mode.

CGOUTNAK 0 A write to this field clears the Global OUT NAK.

W1

Clear Global OUT NAK

SGOUTNAK A write to this field sets the Global OUT NAK. The application uses this bit to send a NAK handshake on all OUT endpoints.

The application must set this bit only after making sure that the Global OUT NAK Effective bit in the Core Interrupt Register (USB_GINTSTS.GOUTNAKEFF) is cleared.

CGNPINNAK 0 0 W1 W1 A write to this field clears the Global Non-periodic IN NAK.

Set Global OUT NAK Clear Global Non-periodic IN NAK

SGNPINNAK TSTCTL 0 0x0 W1 RW

Set Global Non-periodic IN NAK

A write to this field sets the Global Non-periodic IN NAK. The application uses this bit to send a NAK handshake on all non-periodic IN endpoints. The application must set this bit only after making sure that the Global IN NAK Effective bit in the Core Interrupt Register (USB_GINTSTS.GINNAKEFF) is cleared.

Test Control

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3 2 1 0

Bit

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Name Reset

Set to a non-zero value to enable test control.

3 4 5 Value 0 1 2 Mode DISABLE J K SE0NAK PACKET FORCE

Access Description

Description Test mode disabled.

Test_J mode.

Test_K mode.

Test_SE0_NAK mode.

Test_Packet mode.

Test_Force_Enable.

GOUTNAKSTS 0 R

Global OUT NAK Status

When this bit is 0 a handshake is sent based on the FIFO Status and the NAK and STALL bit settings. When this bit is 1 no data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions.

All isochronous OUT packets are dropped.

GNPINNAKSTS 0 R

Global Non-periodic IN NAK Status

When this bit is 0 a handshake is sent out based on the data availability in the transmit FIFO. When this bit is 1 a NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO.

SFTDISCON 0 RW

Soft Disconnect

The application uses this bit to signal the core to do a soft disconnect. As long as this bit is set, the host does not see that the device is connected, and the device does not receive signals on the USB. The core stays in the disconnected state until the application clears this bit. When suspended, the minimum duration for which the core must keep this bit set is 1 ms + 2.5 us. When IDLE or performing transactions, the minimum duration for which the core must keep this bit set is 2.5 us.

RMTWKUPSIG 0 RW

Remote Wakeup Signaling

When the application sets this bit, the core initiates remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the Suspend state. As specified in the USB 2.0 specification, the application must clear this bit 1-15 ms after setting it.

15.6.42 USB_DSTS - Device Status Register

This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from Device All Interrupts (USB_DAINT) register.

Offset

0x3C808

Bit Position Reset Access Name Bit

31:22

21:8

7:4

3

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SOFFN 0x0000 R

Frame Number of the Received SOF

This field contains a Frame number. This field may return a non zero value if read immediately after power on reset. In case the register bits reads non zero immediately after power on reset it does not indicate that SOF has been received from the host. The read value of this interrupt is valid only after a valid connection between host and device is established.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

ERRTICERR 0 R

Erratic Error

The core sets this bit to report any erratic errors (PHY error) Due to erratic errors, the core goes into Suspended state and an interrupt is generated to the application with Early Suspend bit of the Core Interrupt register (USB_GINTSTS.ERLYSUSP). If the early suspend is asserted due to an erratic error, the application can only perform a soft disconnect recover.

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Bit

2:1 0

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Name Reset Access Description

ENUMSPD 0x1 R

Enumerated Speed

Indicates the speed at which the core has come up after speed detection through a chirp sequence.

Value 2 3 Mode LS FS Description Low speed (PHY clock is running at 6 MHz).

Full speed (PHY clock is running at 48 MHz).

SUSPSTS 0 R

Suspend Status

In Device mode, this bit is set as long as a Suspend condition is detected on the USB. The core enters the Suspended state when there is no activity on the bus for an extended period of time. The core comes out of the suspend when there is any activity on the bus or when the application writes to the Remote Wakeup Signaling bit in the Device Control register (USB_DCTL.RMTWKUPSIG).

15.6.43 USB_DIEPMSK - Device IN Endpoint Common Interrupt Mask Register

This register works with each of the Device IN Endpoint Interrupt (USB_DIEP0INT/USB_DIEPx_INT) registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the USB_DIEP0INT/USB_DIEPx_INT register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.

Offset

0x3C810

Reset Access Bit Position Name

5

4

7

6

Bit

31:14

13

12:9

8 3 2 1

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NAKMSK 0 Set to 1 to unmask NAK Interrupt.

Reserved

RW

NAK interrupt Mask

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXFIFOUNDRNMSK 0 Set to 1 to unmask TXFIFOUNDRN Interrupt.

RW

Reserved

Fifo Underrun Mask

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPNAKEFFMSK 0 Set to 1 to unmask INEPNAKEFF Interrupt.

Reserved

RW

IN Endpoint NAK Effective Mask

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INTKNTXFEMPMSK 0 Set to 1 to unmask INTKNTXFEMP Interrupt.

RW

IN Token Received When TxFIFO Empty Mask

TIMEOUTMSK 0 RW

Timeout Condition Mask

Set to 1 to unmask Interrupt TIMEOUT. Applies to Non-isochronous endpoints.

RW

AHB Error Mask

AHBERRMSK 0 Set to 1 to unmask AHBERR Interrupt.

EPDISBLDMSK 0 RW

Endpoint Disabled Interrupt Mask

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Bit

0

Name Reset

Set to 1 to unmask EPDISBLD Interrupt.

XFERCOMPLMSK 0 Set to 1 to unmask XFERCOMPL Interrupt.

Access

RW

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Description Transfer Completed Interrupt Mask

15.6.44 USB_DOEPMSK - Device OUT Endpoint Common Interrupt Mask Register

This register works with each of the Device OUT Endpoint Interrupt (USB_DOEP0INT/ USB_DOEPx_INT) registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the USB_DOEP0INT/USB_DOEPx_INT register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.

Bit Position Offset

0x3C814

Reset Access Name

12

7

6

5

4

Bit

31:14

13

11:9

8 3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NAKMSK 0 Set to 1 to unmask NAK Interrupt.

RW

NAK interrupt Mask

BBLEERRMSK 0 Set to 1 to unmask BBLEERR Interrupt.

Reserved

RW

Babble Error interrupt Mask

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

OUTPKTERRMSK 0 Set to 1 to unmask OUTPKTERR Interrupt.

Reserved

RW

OUT Packet Error Mask

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BACK2BACKSETUP 0 RW

Back-to-Back SETUP Packets Received Mask

Set to 1 to unmask BACK2BACKSETUP Interrupt. Applies to control OUT endpoints only.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

OUTTKNEPDISMSK 0 RW

OUT Token Received when Endpoint Disabled Mask

Set to 1 to unmask OUTTKNEPDIS Interrupt. Applies to control OUT endpoints only.

SETUPMSK 0 RW

SETUP Phase Done Mask

Set to 1 to unmask SETUP Interrupt. Applies to control endpoints only.

AHBERRMSK 0 Set to 1 to unmask AHBERR Interrupt.

RW

AHB Error

RW

Endpoint Disabled Interrupt Mask

EPDISBLDMSK 0 Set to 1 to unmask EPDISBLD Interrupt.

XFERCOMPLMSK 0 Set to 1 to unmask XFERCOMPL Interrupt.

RW

Transfer Completed Interrupt Mask

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15.6.45 USB_DAINT - Device All Endpoints Interrupt Register

When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register interrupts the application using the Device OUT Endpoints Interrupt bit or Device IN Endpoints Interrupt bit of the Core Interrupt register (USB_GINTSTS.OEPINT or USB_GINTSTS.IEPINT, respectively). There is one interrupt bit per endpoint. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding Device Endpoint Interrupt register (USB_DIEP0INT/USB_DIEPx_INT, USB_DOEP0INT/ USB_DOEPx_INT).

Offset

0x3C818

Reset Access Bit Position Name Bit

31:23

22 21 20 19 18 17 16

15:7

6 5 4 3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

OUTEPINT6 0 R

OUT Endpoint 6 Interrupt Bit

This bit is set when on or more of the interrupt flags in USB_DOEP5_INT are set.

OUTEPINT5 0 R

OUT Endpoint 5 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DOEP4_INT are set.

OUTEPINT4 0 R

OUT Endpoint 4 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DOEP3_INT are set.

OUTEPINT3 0 R

OUT Endpoint 3 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DOEP2_INT are set.

OUTEPINT2 0 R

OUT Endpoint 2 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DOEP1_INT are set.

OUTEPINT1 0 R

OUT Endpoint 1 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DOEP0_INT are set.

OUTEPINT0 0 R

OUT Endpoint 0 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DOEP0INT are set.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INEPINT6 0 R

IN Endpoint 6 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DIEP5_INT are set.

INEPINT5 0 R

IN Endpoint 5 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DIEP4_INT are set.

INEPINT4 0 R

IN Endpoint 4 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DIEP3_INT are set.

INEPINT3 0 R

IN Endpoint 3 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DIEP2_INT are set.

INEPINT2 0 R

IN Endpoint 2 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DIEP1_INT are set.

INEPINT1 0 R

IN Endpoint 1 Interrupt Bit

This bit is set when one or more of the interrupt flags in USB_DIEP0_INT are set.

INEPINT0 0 R

IN Endpoint 0 Interrupt Bit

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Bit

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Name Reset Access Description

This bit is set when one or more of the interrupt flags in USB_DIEP0INT are set.

15.6.46 USB_DAINTMSK - Device All Endpoints Interrupt Mask Register

The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register to interrupt the application when an event occurs on a device endpoint. However, the Device All Endpoints Interrupt (USB_DAINT) register bit corresponding to that interrupt is still set.

Bit Position Offset

0x3C81C

Reset Access Name Bit

31:23

22 21 20 19 18 17 16

15:7

6 5 4 3 2 1 0

Name Reset Access Description

Reserved

OUTEPMSK6

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0 Set to 1 to unmask USB_DAINT.OUTEPINT6.

RW OUTEPMSK5 0 Set to 1 to unmask USB_DAINT.OUTEPINT5.

RW

OUT Endpoint 6 Interrupt mask Bit OUT Endpoint 5 Interrupt mask Bit

OUTEPMSK4 0 Set to 1 to unmask USB_DAINT.OUTEPINT4.

RW OUTEPMSK3 0 Set to 1 to unmask USB_DAINT.OUTEPINT3.

RW OUTEPMSK2 0 Set to 1 to unmask USB_DAINT.OUTEPINT2.

RW OUTEPMSK1 0 Set to 1 to unmask USB_DAINT.OUTEPINT1.

RW

OUT Endpoint 2 Interrupt mask Bit OUT Endpoint 1 Interrupt mask Bit

OUTEPMSK0 0 Set to 1 to unmask USB_DAINT.OUTEPINT0.

RW

Reserved

OUT Endpoint 0 Interrupt mask Bit

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RW

OUT Endpoint 4 Interrupt mask Bit OUT Endpoint 3 Interrupt mask Bit IN Endpoint 6 Interrupt mask Bit

INEPMSK6 0 Set to 1 to unmask USB_DAINT.INEPINT6.

INEPMSK5 0 Set to 1 to unmask USB_DAINT.INEPINT5.

INEPMSK4 0 Set to 1 to unmask USB_DAINT.INEPINT4.

INEPMSK3 0 Set to 1 to unmask USB_DAINT.INEPINT3.

RW RW RW

IN Endpoint 5 Interrupt mask Bit IN Endpoint 4 Interrupt mask Bit IN Endpoint 3 Interrupt mask Bit

INEPMSK2 0 Set to 1 to unmask USB_DAINT.INEPINT2.

INEPMSK1 0 Set to 1 to unmask USB_DAINT.INEPINT1.

INEPMSK0 0 RW RW RW

IN Endpoint 2 Interrupt mask Bit IN Endpoint 1 Interrupt mask Bit IN Endpoint 0 Interrupt mask Bit

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Bit Name Reset

Set to 1 to unmask USB_DAINT.INEPINT0.

Access

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Description

15.6.47 USB_DVBUSDIS - Device VBUS Discharge Time Register

This register specifies the VBUS discharge time after VBUS pulsing during SRP.

Offset

0x3C828

Bit Position Reset Access Name Bit

31:16

15:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DVBUSDIS 0x17D7 RW

Device VBUS Discharge Time

Specifies the VBUS discharge time after VBUS pulsing during SRP. This value equals VBUS discharge time in PHY clocks / 1024.

Depending on your VBUS load, this value can need adjustment.

15.6.48 USB_DVBUSPULSE - Device VBUS Pulsing Time Register

This register specifies the VBUS pulsing time during SRP.

Offset

0x3C82C

Bit Position Reset Access Name Bit

31:12

11:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DVBUSPULSE 0x5B8 RW

Device VBUS Pulsing Time

Specifies the VBUS pulsing time during SRP. This value equals VBUS pulsing time in PHY clocks / 1024.

15.6.49 USB_DIEPEMPMSK - Device IN Endpoint FIFO Empty Interrupt Mask Register

This register is used to control the IN endpoint FIFO empty interrupt generation (USB_DIEP0INT/ USB_DIEPx_INT.TXFEMP).

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Offset

0x3C834

Reset Access Name

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Bit Position Bit

31:16

15:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

DIEPEMPMSK 0x0000 RW

IN EP Tx FIFO Empty Interrupt Mask Bits

These bits acts as mask bits for USB_DIEP0INT.TXFEMP/USB_DIEPx_INT.TXFEMP interrupt. One bit per IN Endpoint: Bit 0 for IN EP 0, bit 6 for IN EP 6.

15.6.50 USB_DIEP0CTL - Device IN Endpoint 0 Control Register

This section describes the Control IN Endpoint 0 Control register. Nonzero control endpoints use registers for endpoints 1 - 6.

Bit Position Offset

0x3C900

Reset Access Name Bit

31 30

29:28

27 26 25:22 21

Name Reset Access Description

EPENA 0 RW1H

Endpoint Enable

In DMA mode this bit indicates that data is ready to be transmitted on the endpoint. The core clears this bit before setting the following interrupts on this endpoint: Endpoint Disabled, Transfer Completed.

EPDIS 0 RW1H

Endpoint Disable

The application sets this bit to stop transmitting data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint Disabled Interrupt. The application must set this bit only if Endpoint Enable is already set for this endpoint.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SNAK 0 W1

Set NAK

A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint.

CNAK 0 W1 A write to this bit clears the NAK bit for the endpoint.

STALL 0 RW1H

Clear NAK

TXFNUM 0x0 RW

TxFIFO Number

This value is set to the FIFO number that is assigned to IN Endpoint 0.

Handshake

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Bit

20

19:18 17

16

15

14:2

1:0

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Name Reset Access Description

The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global Nonperiodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

EPTYPE 0x0 R Hardcoded to 0. Endpoint 0 is always a control endpoint.

Endpoint Type

NAKSTS 0 R

NAK Status

When this bit is 0 the core is transmitting non-NAK handshakes based on the FIFO status. When this bit is 1 the core is transmitting NAK handshakes on this endpoint. When this bit is set, either by the application or core, the core stops transmitting data, even if there is data available in the TxFIFO. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USBACTEP 1 R

USB Active Endpoint

This bit is always 1, indicating that control endpoint 0 is always active in all configurations and interfaces.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

MPS 0x0 RW

Maximum Packet Size

The application must program this field with the maximum packet size for the current logical endpoint.

Value 0 1 2 3 Mode 64B 32B 16B 8B Description 64 bytes.

32 bytes.

16 bytes.

8 bytes.

15.6.51 USB_DIEP0INT - Device IN Endpoint 0 Interrupt Register

This register indicates the status of endpoint 0 with respect to USB- and AHB-related events. The application must read this register when the IN Endpoints Interrupt bit of the Core Interrupt register (USB_GINTSTS.IEPINT) is set. Before the application can read this register, it must first read the Device All Endpoints Interrupt (USB_DAINT) register to get the exact endpoint number for the Device Endpoint Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the USB_DAINT and USB_GINTSTS registers.

Bit Position Offset

0x3C908

Reset Access Name Bit

31:14

13 12

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NAKINTRPT 0 RW1H

NAK Interrupt

The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo.

BBLEERR 0 RW1H

NAK Interrupt

The core generates this interrupt when babble is received for the endpoint.

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1 0 3 2

5

4

Bit

11

10:8

7 6

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Name Reset Access Description

PKTDRPSTS 0 RW1H

Packet Drop Status

This bit indicates to the application that an ISO OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXFEMP 1 R

Transmit FIFO Empty

This interrupt is asserted when the TxFIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the TxFIFO Empty Level bit in the Core AHB Configuration register (USB_GAHBCFG.NPTXFEMPLVL).

INEPNAKEFF 0 RW1H

IN Endpoint NAK Effective

Applies to periodic IN endpoints only. This bit can be cleared when the application clears the IN endpoint NAK by writing to USB_DIEP0CTL.CNAK. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core).

The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INTKNTXFEMP 0 RW1H

IN Token Received When TxFIFO is Empty

Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

TIMEOUT 0 RW1H

Timeout Condition

Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

AHBERR 0 RW1H

AHB Error

This is generated in DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address.

EPDISBLD 0 RW1H

Endpoint Disabled Interrupt

This bit indicates that the endpoint is disabled per the application's request.

XFERCOMPL 0 RW1H

Transfer Completed Interrupt

This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

15.6.52 USB_DIEP0TSIZ - Device IN Endpoint 0 Transfer Size Register

The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using Endpoint Enable bit of the Device Control Endpoint 0 Control register (USB_DIEP0CTL.EPENA), the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit. Nonzero endpoints use the registers for endpoints 1-6.

Offset

0x3C910

Reset Access Bit Position Name Bit

31:21

20:19

18:7

6:0

Name Reset Access Description

Reserved

XFERSIZE

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PKTCNT 0x0 RW

Packet Count

Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0. This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

0x00 RW

Transfer Size

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Bit

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Name Reset Access Description

Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet.

The core decrements this field every time a packet from the external memory is written to the TxFIFO.

15.6.53 USB_DIEP0DMAADDR - Device IN Endpoint 0 DMA Address Register

Offset

0x3C914

Bit Position Reset Access Name Bit

31:0

Name Reset Access Description

DIEP0DMAADDR 0xXXXXXXXX RW

DMA Address

Holds the start address of the external memory for fetching endpoint data. For control endpoints, this field stores control OUT data packets as well as SETUP transaction data packets. When more than three SETUP packets are received back-to-back, the SETUP data packet in the memory is overwritten. This register is incremented on every AHB transaction. The application can give only a DWORD-aligned address. The data for this register field is stored in RAM. Thus, the reset value is undefined (X).

15.6.54 USB_DIEP0TXFSTS - Device IN Endpoint 0 Transmit FIFO Status Register

This read-only register contains the free space information for the Device IN endpoint 0 TxFIFO.

Offset

0x3C918

Bit Position Reset Access Name Bit

31:16

15:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SPCAVAIL 0x0200 R

TxFIFO Space Available

Indicates the amount of free space available in the Endpoint TxFIFO. Values are in terms of 32-bit words.

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15.6.55 USB_DIEPx_CTL - Device IN Endpoint x+1 Control Register

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset

0x3C920

Bit Position Reset Access Name Bit

31 30 29 28 27 26 25:22 21

20

19:18

Name Reset Access Description

EPENA 0 RW1H

Endpoint Enable

In DMA mode for IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP Phase Done, Endpoint Disabled, Transfer Completed. For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.

EPDIS 0 RW1H

Endpoint Disable

The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete.

The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint Disabled interrupt. The application must set this bit only if Endpoint Enable is already set for this endpoint.

SETD1PIDOF 0 W1

Set DATA1 PID / Odd Frame

For bulk and interrupt endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field in this register to DATA1ODD.

For isochronous endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field to odd (DATA1ODD).

SETD0PIDEF 0 W1

Set DATA0 PID / Even Frame

For bulk and interrupt endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field in this register to DATA0EVEN.

For isochronous endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field to odd (DATA0EVEN).

SNAK 0 W1

Set NAK

A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint.

CNAK 0 W1 A write to this bit clears the NAK bit for the endpoint.

Clear NAK

TXFNUM 0x0 RW

TxFIFO Number

These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints.

STALL 0 RW1H

Handshake

For bulk and interrupt endpoints: The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. In this case only the application can clear this bit, never the core.

When control endpoint: The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint.

If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

EPTYPE 0x0 RW This is the transfer type supported by this logical endpoint.

Endpoint Type

Value 0 Mode CONTROL Description Control Endpoint.

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Bit

17 16 15

14:11

10:0

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Name

Value 1 2 3 Mode ISO BULK INT

Reset Access Description

Description Isochronous Endpoint.

Bulk Endpoint.

Interrupt Endpoint.

NAKSTS 0 R

NAK Status

When this bit is 0 the core is transmitting non-NAK handshakes based on the FIFO status. When this bit is 1 the core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit the core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet. For non-isochronous IN endpoints the core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO. For isochronous IN endpoints the core sends out a zero-length data packet, even if there data is available in the TxFIFO. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

DPIDEOF 0 R

Endpoint Data PID / Even or Odd Frame

For interrupt/bulk endpoints this field contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The applications use the SETD1PIDOF and SETD0PIDEF fields of this register to program either DATA0 or DATA1 PID. For isochronous endpoints, this field indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SETD0PIDEF and SETD1PIDOF fields in this register.

Value 0 1 Mode DATA0EVEN DATA1ODD Description DATA0 PID / Even Frame.

DATA1 PID / Odd Frame.

USBACTEP 0 RW

USB Active Endpoint

Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

MPS 0x000 RW

Maximum Packet Size

The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

15.6.56 USB_DIEPx_INT - Device IN Endpoint x+1 Interrupt Register

This register indicates the status of an endpoint with respect to USB- and AHB-related events. The application must read this register when the IN Endpoints Interrupt bit of the Core Interrupt register (USB_GINTSTS.IEPINT) is set. Before the application can read this register, it must first read the Device All Endpoints Interrupt (USB_DAINT) register to get the exact endpoint number for the Device Endpoint x+1 Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the USB_DAINT and USB_GINTSTS registers.

Bit Position Offset

0x3C928

Reset Access Name Bit

31:14

13

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NAKINTRPT 0 RW1H

NAK Interrupt

The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo.

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1 0

5

4

Bit

12 11

10:8

7 6 3 2

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Name Reset Access Description

BBLEERR 0 RW1H

NAK Interrupt

The core generates this interrupt when babble is received for the endpoint.

PKTDRPSTS 0 RW1H

Packet Drop Status

This bit indicates to the application that an ISO OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

TXFEMP 1 R

Transmit FIFO Empty

This interrupt is asserted when the TxFIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the TxFIFO Empty Level bit in the Core AHB Configuration register (USB_GAHBCFG.NPTXFEMPLVL).

INEPNAKEFF Applies to periodic IN endpoints only. This bit can be cleared when the application clears the IN endpoint NAK by writing to USB_DIEPx_CTL.CNAK. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Reserved

0 RW1H

IN Endpoint NAK Effective

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

INTKNTXFEMP 0 RW1H

IN Token Received When TxFIFO is Empty

Applies to non-periodic IN endpoints only. Indicates that an IN token was received when the associated TxFIFO (periodic/non periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

TIMEOUT 0 RW1H

Timeout Condition

Applies only to Control IN endpoints. Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

AHBERR 0 RW1H

AHB Error

This is generated only in DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address.

EPDISBLD 0 RW1H

Endpoint Disabled Interrupt

This bit indicates that the endpoint is disabled per the application's request.

XFERCOMPL 0 RW1H

Transfer Completed Interrupt

This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

15.6.57 USB_DIEPx_TSIZ - Device IN Endpoint x+1 Transfer Size Register

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint x+1 Control register (USB_DIEPx_CTL.EPENA), the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit.

Offset

0x3C930

Bit Position Reset Access Name Bit

31

Name

Reserved

Reset Access Description

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

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Bit

30:29 28:19 18:0

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Name Reset Access Description

MC 0x0 RW

Multi Count

For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.

PKTCNT 0x000 RW

Packet Count

Indicates the total number of USB packets that constitute the Transfer Size amount of data. This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

XFERSIZE 0x00000 RW

Transfer Size

Indicates the transfer size in bytes. The core interrupts the application only after it has exhausted the transfer size amount of data.

The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the TxFIFO.

15.6.58 USB_DIEPx_DMAADDR - Device IN Endpoint x+1 DMA Address Register

Offset

0x3C934

Bit Position Reset Access Name Bit

31:0

Name Reset Access Description

DMAADDR 0xXXXXXXXX RW

DMA Address

Holds the start address of the external memory for fetching endpoint data. For control endpoints, this field stores control OUT data packets as well as SETUP transaction data packets. When more than three SETUP packets are received back-to-back, the SETUP data packet in the memory is overwritten. This register is incremented on every AHB transaction. The application can give only a DWORD-aligned address. The data for this register field is stored in RAM. Thus, the reset value is undefined (X).

15.6.59 USB_DIEPx_TXFSTS - Device IN Endpoint x+1 Transmit FIFO Status Register

This read-only register contains the free space information for the Device IN endpoint TxFIFO.

Offset

0x3C938

Bit Position Reset Access Name

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Bit

31:16

15:0

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Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SPCAVAIL 0x0200 R

TxFIFO Space Available

Indicates the amount of free space available in the Endpoint TxFIFO. Values are in terms of 32-bit words.

15.6.60 USB_DOEP0CTL - Device OUT Endpoint 0 Control Register

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Bit Position Offset

0x3CB00

Reset Access Name Bit

31 30

29:28

27 26

25:22

21 20 19:18 17

16

15

Name Reset Access Description

EPENA 0 RW1H

Endpoint Enable

In DMA mode this bit indicates that the application has allocated the memory to start receiving data from the USB. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP Phase Done, Endpoint Disabled, Transfer Completed.

In DMA mode, this bit must be set for the core to transfer SETUP data packets into memory.

EPDIS 0 R

Endpoint Disable

This bit is always 0. The application cannot disable control OUT endpoint 0.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SNAK 0 W1

Set NAK

A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set bit on a Transfer Completed interrupt, or after a SETUP is received on the endpoint.

CNAK 0 W1 A write to this bit clears the NAK bit for the endpoint.

Clear NAK

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

STALL 0 RW1H

Handshake

The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

SNP 0 RW

Snoop Mode

This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory.

EPTYPE 0x0 R Hardcoded to 0. Endpoint 0 is always a control endpoint.

Endpoint Type

NAKSTS 0 R

NAK Status

When this bit is 0 the core is transmitting non-NAK handshakes based on the FIFO status. When this bit is 1 the core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit, the core stops receiving data, even if there is space in the RxFIFO to accommodate the incoming packet. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

USBACTEP 1 R

USB Active Endpoint

This bit is always 1, indicating that a control endpoint 0 is always active in all configurations and interfaces.

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Bit

14:2

1:0

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Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

MPS 0x0 R

Maximum Packet Size

The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN Endpoint 0.

Value 0 1 2 3 Mode 64B 32B 16B 8B Description 64 bytes.

32 bytes.

16 bytes.

8 bytes.

15.6.61 USB_DOEP0INT - Device OUT Endpoint 0 Interrupt Register

This register indicates the status of endpoint 0 with respect to USB- and AHB-related events. The application must read this register when the OUT Endpoints Interrupt bit of the Core Interrupt register (USB_GINTSTS.OEPINT) is set. Before the application can read this register, it must first read the Device All Endpoints Interrupt (USB_DAINT) register to get the exact endpoint number for the Device Endpoint Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the USB_DAINT and USB_GINTSTS registers.

Bit Position Offset

0x3CB08

Reset Access Name

5

4

Bit

31:14

13 12 11

10:7

6 3

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NAKINTRPT 0 RW1H

NAK Interrupt

The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo.

BBLEERR 0 RW1H

NAK Interrupt

The core generates this interrupt when babble is received for the endpoint.

PKTDRPSTS 0 RW1H

Packet Drop Status

This bit indicates to the application that an ISO OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BACK2BACKSETUP 0 RW1H

Back-to-Back SETUP Packets Received

This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

OUTTKNEPDIS 0 RW1H

OUT Token Received When Endpoint Disabled

Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

SETUP 0 RW1H

Setup Phase Done

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Bit

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Name Reset Access Description

Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet.

AHBERR 0 RW1H

AHB Error

This is generated only in DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address.

EPDISBLD 0 RW1H

Endpoint Disabled Interrupt

This bit indicates that the endpoint is disabled per the application's request.

XFERCOMPL 0 RW1H

Transfer Completed Interrupt

This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

15.6.62 USB_DOEP0TSIZ - Device OUT Endpoint 0 Transfer Size Register

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint x+1 Control register (USB_DOEPx_CTL.EPENA), the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit.

Offset

0x3CB10

Reset Access Bit Position Name Bit

31

30:29

28:20

19

18:7

6:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

SUPCNT 0x0 RW

SETUP Packet Count

This field specifies the number of back-to-back SETUP data packets the endpoint can receive.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PKTCNT 0 RW

Packet Count

This field is decremented to zero after a packet is written into the RxFIFO.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

XFERSIZE 0x00 RW

Transfer Size

Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet.

The core decrements this field every time a packet is read from the RxFIFO and written to the external memory.

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15.6.63 USB_DOEP0DMAADDR - Device OUT Endpoint 0 DMA Address Register

Offset

0x3CB14

Bit Position Reset Access Name Bit

31:0

Name Reset Access Description

DOEP0DMAADDR 0xXXXXXXXX RW

DMA Address

Holds the start address of the external memory for storing endpoint data. For control endpoints, this field stores control OUT data packets as well as SETUP transaction data packets. When more than three SETUP packets are received back-to-back, the SETUP data packet in the memory is overwritten. This register is incremented on every AHB transaction. The application can give only a DWORD-aligned address. The data for this register field is stored in RAM. Thus, the reset value is undefined (X).

15.6.64 USB_DOEPx_CTL - Device OUT Endpoint x+1 Control Register

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset

0x3CB20

Bit Position Reset Access Name Bit

31 30 29

Name Reset Access Description

EPENA 0 RW1H

Endpoint Enable

In DMA mode this bit indicates that the application has allocated the memory to start receiving data from the USB. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP Phase Done, Endpoint Disabled, Transfer Completed.

For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.

EPDIS SETD1PIDOF 0 0 RW1H W1

Endpoint Disable

The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete.

The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint Disabled interrupt. The application must set this bit only if Endpoint Enable is already set for this endpoint.

Set DATA1 PID / Odd Frame

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Bit

28 27 26

25:22

21 20 19:18 17 16 15

14:11

10:0

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Name Reset Access Description

For bulk and interrupt endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field in this register to DATA1ODD. For isochronous endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field to odd (DATA1ODD).

SETD0PIDEF 0 W1

Set DATA0 PID / Even Frame

For bulk and interrupt endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field in this register to DATA0EVEN. For isochronous endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field to odd (DATA0EVEN).

SNAK 0 W1

Set NAK

A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint.

CNAK 0 W1 A write to this bit clears the NAK bit for the endpoint.

Reserved

Clear NAK

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

STALL 0 RW1H

STALL Handshake

For non-control, non-isochronous endpoints: The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core.

For control endpoints: The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint.

If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

SNP 0 RW

Snoop Mode

This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory.

EPTYPE 0x0 RW This is the transfer type supported by this logical endpoint.

Endpoint Type

Value 0 1 2 3 Mode CONTROL ISO BULK INT Description Control Endpoint.

Isochronous Endpoint.

Bulk Endpoint.

Interrupt Endpoint.

NAKSTS 0 R

NAK Status

When this bit is 0 the core is transmitting non-NAK handshakes based on the FIFO status. When this bit is 1 the core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit the core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

DPIDEOF 0 R

Endpoint Data PID / Even-odd Frame

For interrupt/bulk endpoints: Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application use the SETD1PIDOF and SETD0PIDEF fields of this register to program either DATA0 or DATA1 PID.

For isochronous endpoints: Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SETD1PIDOF and SETD0PIDEF fields in this register.

Value 0 1 Mode DATA0EVEN DATA1ODD Description DATA0 PID / Even Frame.

DATA1 PID / Odd Frame.

USBACTEP Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit.

Reserved

0 RW

USB Active Endpoint

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

MPS 0x000 RW

Maximum Packet Size

The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

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15.6.65 USB_DOEPx_INT - Device OUT Endpoint x+1 Interrupt Register

This register indicates the status of an endpoint with respect to USB- and AHB-related events. The application must read this register when the OUT Endpoints Interrupt bit of the Core Interrupt register (USB_GINTSTS.OEPINT) is set. Before the application can read this register, it must first read the Device All Endpoints Interrupt (USB_DAINT) register to get the exact endpoint number for the Device Endpoint Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the USB_DAINT and USB_GINTSTS registers.

Bit Position Offset

0x3CB28

Reset Access Name

5

4

Bit

31:14

13 12 11

10:7

6 3 2 1 0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

NAKINTRPT 0 RW1H

NAK Interrupt

The core generates this interrupt when a NAK is transmitted or received by the device.

BBLEERR 0 RW1H

Babble Error

The core generates this interrupt when babble is received for the endpoint.

PKTDRPSTS 0 RW1H

Packet Drop Status

This bit indicates to the application that an ISO OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

BACK2BACKSETUP 0 RW1H

Back-to-Back SETUP Packets Received

Applies to Control OUT endpoints only. This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

OUTTKNEPDIS 0 RW1H

OUT Token Received When Endpoint Disabled

Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

SETUP 0 RW1H

Setup Phase Done

Applies to control OUT endpoints only. Indicates that the SETUP phase for the control endpoint is complete and no more back to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet.

AHBERR 0 RW1H

AHB Error

This is generated only in DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address.

EPDISBLD 0 RW1H

Endpoint Disabled Interrupt

This bit indicates that the endpoint is disabled per the application's request.

XFERCOMPL 0 RW1H

Transfer Completed Interrupt

This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

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15.6.66 USB_DOEPx_TSIZ - Device OUT Endpoint x+1 Transfer Size Register

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint x+1 Control register (USB_DOEPx_CTL.EPENA), the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit.

Offset

0x3CB30

Bit Position Reset Access Name Bit

31

30:29 28:19 18:0

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RXDPIDSUPCNT 0x0 R

Receive Data PID / SETUP Packet Count

For isochronous OUT endpoints: This is the data PID received in the last packet for this endpoint.

For control OUT Endpoints: This field specifies the number of back-to-back SETUP data packets the endpoint can receive.

Value 0 1 2 3 Mode DATA0 DATA2 DATA1 MDATA Description DATA0 PID.

DATA2 PID / 1 Packet.

DATA1 PID / 2 Packets.

MDATA PID / 3 Packets.

PKTCNT 0x000 RW

Packet Count

This field is decremented to zero after a packet is written into the RxFIFO.

XFERSIZE 0x00000 RW

Transfer Size

Indicates the transfer size in bytes. The core interrupts the application only after it has exhausted the transfer size amount of data.

The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the RxFIFO and written to the external memory.

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15.6.67 USB_DOEPx_DMAADDR - Device OUT Endpoint x+1 DMA Address Register

Offset

0x3CB34

Bit Position Reset Access Name Bit

31:0

Name Reset Access Description

DMAADDR 0xXXXXXXXX RW

DMA Address

Holds the start address of the external memory for storing endpoint data. For control endpoints, this field stores control OUT data packets as well as SETUP transaction data packets. When more than three SETUP packets are received back-to-back, the SETUP data packet in the memory is overwritten. This register is incremented on every AHB transaction. The application can give only a DWORD-aligned address. The data for this register field is stored in RAM. Thus, the reset value is undefined (X).

15.6.68 USB_PCGCCTL - Power and Clock Gating Control Register

This register is available in Host and Device modes. The application use this register to control the core's power-down and clock gating features.

Bit Position Offset

0x3CE00

Reset Access Name

7

6

5:4

3

Bit

31:9

8

Name Reset Access Description

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RESETAFTERSUSP 0 R

Reset after suspend

When exiting EM2, this bit needs to be set in host mode before clamp is removed if the host needs to issue reset after suspend. If this bit is not set, then the host issues resume after suspend. This bit is not applicable in device mode and when EM2 is not used.

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

PHYSLEEP 0 Indicates that the PHY is in Sleep State.

Reserved

R

PHY In Sleep

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

RSTPDWNMODULE 0 RW

Reset Power-Down Modules

The application sets this bit to reset the part of the USB that is powered down during EM2. The application clears this bit to release reset after an waking up from EM2 when the PHY clock is back at 48/6 MHz. Accessing core registers is possible only when this bit is set to 0.

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Bit

2 1 0

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Name Reset Access Description

PWRCLMP 0 RW

Power Clamp

The application sets this bit before the power is turned off to clamp the signals between the power-on modules and the power-off modules of the USB core. The application clears the bit to disable the clamping.

GATEHCLK 0 RW

Gate HCLK

The application sets this bit to gate the clock (HCLK) to modules other than the AHB Slave and Master and wakeup logic when the USB is suspended or the session is not valid. The application clears this bit when the USB is resumed or a new session starts.

STOPPCLK 0 RW

Stop PHY clock

The application sets this bit to stop the PHY clock when the USB is suspended, the session is not valid, or the device is disconnected.

The application clears this bit when the USB is resumed or a new session starts.

15.6.69 USB_FIFO0Dx - Device EP 0/Host Channel 0 FIFO

This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 0 or channel 0, in a given direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the channel.

Offset

0x3D000

Bit Position Reset Access Name Bit

31:0

Name Reset Access

FIFO0D 0xXXXXXXXX FIFO 0 push/pop region. Used in slave mode.

RW

Description Device EP 0/Host Channel 0 FIFO

15.6.70 USB_FIFO1Dx - Device EP 1/Host Channel 1 FIFO

This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 1 or channel 1, in a given direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the channel.

Offset

0x3E000

Bit Position Reset Access Name

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Bit

31:0

Name Reset Access

FIFO1D 0xXXXXXXXX FIFO 1 push/pop region. Used in slave mode.

RW

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Description Device EP 1/Host Channel 1 FIFO

15.6.71 USB_FIFO2Dx - Device EP 2/Host Channel 2 FIFO

This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 2 or channel 2, in a given direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the channel.

Offset

0x3F000

Bit Position Reset Access Name Bit

31:0

Name Reset Access

FIFO2D 0xXXXXXXXX FIFO 2 push/pop region. Used in slave mode.

RW

Description Device EP 2/Host Channel 2 FIFO

15.6.72 USB_FIFO3Dx - Device EP 3/Host Channel 3 FIFO

This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 3 or channel 3, in a given direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the channel.

Offset

0x40000

Bit Position Reset Access Name Bit

31:0

Name

FIFO3D

Reset

0xXXXXXXXX

Access

RW

Description Device EP 3/Host Channel 3 FIFO

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Bit Name Reset

FIFO 3 push/pop region. Used in slave mode.

Access

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Description

15.6.73 USB_FIFO4Dx - Device EP 4/Host Channel 4 FIFO

This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 4 or channel 4, in a given direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the channel.

Offset

0x41000

Bit Position Reset Access Name Bit

31:0

Name Reset Access

FIFO4D 0xXXXXXXXX FIFO 4 push/pop region. Used in slave mode.

RW

Description Device EP 4/Host Channel 4 FIFO

15.6.74 USB_FIFO5Dx - Device EP 5/Host Channel 5 FIFO

This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 5 or channel 5, in a given direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the channel.

Offset

0x42000

Bit Position Reset Access Name Bit

31:0

Name Reset Access

FIFO5D 0xXXXXXXXX FIFO 5 push/pop region. Used in slave mode.

RW

Description Device EP 5/Host Channel 5 FIFO

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15.6.75 USB_FIFO6Dx - Device EP 6/Host Channel 6 FIFO

This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 6 or channel 6, in a given direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the channel.

Offset

0x43000

Bit Position Reset Access Name Bit

31:0

Name Reset Access

FIFO6D 0xXXXXXXXX FIFO 6 push/pop region. Used in slave mode.

RW

Description Device EP 6/Host Channel 6 FIFO

15.6.76 USB_FIFO7Dx - Host Channel 7 FIFO

This register, available in Host mode, is used to read or write the FIFO space for channel 7, in a given direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the channel.

Offset

0x44000

Bit Position Reset Access Name Bit

31:0

Name Reset Access

FIFO7D 0xXXXXXXXX FIFO 7 push/pop region. Used in slave mode.

RW

Description Host Channel 7 FIFO

15.6.77 USB_FIFO8Dx - Host Channel 8 FIFO

This register, available in Host mode, is used to read or write the FIFO space for channel 8, in a given direction. If a host channel is