AMS AS5850A, AS585x EvalBoard User guide

AMS AS5850A, AS585x EvalBoard User guide
User Guide
UG000439
AS585X
Standard Board
AS585X-CB-EK-ST
v1-00 • 2020-Apr-21
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AS585X
Content Guide
Content Guide
1
Introduction.................................... 3
1.1
1.2
1.3
AS585X Eval Kit ........................................... 3
Eval Kit Content............................................ 5
Ordering Information .................................... 6
2
Getting Started ............................... 7
2.1
2.2
System Requirement .................................... 7
Eval Kit Assembly......................................... 7
3
Hardware Description.................... 9
3.1
3.2
3.3
3.4
3.5
3.6
AS585X Eval Kit Base Board ..................... 10
AS585X Eval Kit Power Module ................. 10
AS585X Eval Kit DAC Module ................... 11
AS585X Eval Kit COB Sample Board ........ 12
AS585X Eval Kit COF Sample Board ........ 13
FPGA Board ............................................... 14
4
Software Description ................... 15
4.1
4.2
4.3
4.4
Software Download .................................... 15
Software Installation ................................... 15
Getting Started ........................................... 15
GUI Description .......................................... 16
5
AS585X Operation ....................... 25
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5.1
5.2
5.3
Introduction ................................................ 25
CSA Operation Overview ........................... 26
Timing ........................................................ 29
6
Evaluation Modes ........................ 45
6.1
6.2
6.3
6.4
6.5
No Charge Generation ............................... 45
Internal Charge Generation (holes) ........... 46
Internal Charge Generation (electrons) ..... 54
External Charge Generation (holes) .......... 61
External Charge Generation (electrons) .... 68
7
Other Operation Modes ............... 70
8
Table of Abbreviations ................ 71
9
Troubleshooting .......................... 72
9.1
9.2
9.3
Connection Issue ....................................... 72
Screen Limitation Issue.............................. 72
CRC Fail ..................................................... 73
10
Revision Information ................... 74
11
Legal Information ........................ 75
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1
AS585X
Introduction
Introduction
The AS585X product family (AS5850, AS5851 and AS5852) is a 16-bit, 256-channel low-noise
charge-to-digital converter designed for digital X-ray systems. It enables a wide range of applications
for digital X-ray including static and dynamic flat panel detectors (FPDs) used in radiographic imaging,
digital mammography and high-speed fluoroscopy.
Each of the devices consists of 256 analog charge sensitive amplifiers (CSA) with a programmable
full-scale range, a correlated double sampler (CDS) for offset compensation with programmable time
constant and 128 multiplexed analog-to-digital converters (ADC) for the digital readout of each pixel.
The device can be configured for electron and hole polarity and includes a voltage reference and a
temperature sensor. Built-in diagnostic modes enable error detection in the signal chain.
The converted channels are output on a single LVDS interface with a data rate up to 320 Mbps for
optimized line time. The serial SPI interface allows the configuration of the analog frontend including
timing and different power modes for low stand-by power consumptions and fast startup times.
AS5850 is a high-speed design, optimized for line times down to 19 μs for dynamic flat panel detectors
in fluoroscopy applications. The AS5851 and AS5852, optimized for line times down to 38 μs, 76 μs
respectively, are its low-power versions for static, portable, and battery supplied flat panels with
minimum power dissipations down to 1.4 mW per channel.
All devices are delivered per default on a Chip on Flex package to minimize sidewall distances and
allow direct assembly on the X-ray panel. The Flex design can be customized according to customer
requirements. Alternatively, all devices can be delivered as dice on foil.
1.1
AS585X Eval Kit
The AS585X Eval Kit (Eval Kit) is a stand-alone system, which allows the AS585X complete
configuration, the measurement of all the relevant parameter (like noise and input linearity) and the
connection to an X-Ray photodetector panel.
Two different AS585X samples are included in the Eval Kit in order to perform the complete
evaluation:
1.
AS585X Chip-on-Board (COB) sample: The AS585X die is directly bonded to the AS585X
sample board, which is equipped with the signal generator circuitry. Such circuitry allows the
generation of the input signals that emulate the photodetector as on the final application.
2.
AS585X Chip-on-Flex (COF) sample: The default package type of the AS585X, where the die is
bonded on a flex substrate. Such package allows the direct connection to an X-Ray
photodetector panel.
In order to connect the COF to the Base Board, an adapter board is included with the COF preassembled.
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AS585X
Introduction
In the COF the signal generator circuitry is not implemented, therefore it is not possible to stimulate
the input channels externally.
An FPGA Module controls the AS585X SPI interface to read and write register values, the AS585X
Low-Voltage Differential Signaling (LVDS) interface to transfer the data off-chip, as well as the Eval Kit
input signal generator. The FPGA Module is controlled through the AS585X Eval Kit software.
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1.2
AS585X
Introduction
Eval Kit Content
Figure 1:
Included Components (part 1)
1
2
3
4
1
2
3
4
5
6
7
8
1x AS585X Chip-on-Board (COB) Sample
Board
1x AS585X Chip-on-Flex (COF) Sample
with adapter board
AS585X Eval Kit Base Board
Metallic shield cover
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5
DAC Module
6
Power Module
7
8
FPGA Board
1x FPGA Adaptor Board
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AS585X
Introduction
Figure 2:
Included Components (part 2)
9
10
11
13
9
10
11
1.3
1x FPGA Power Supply
1x USB 3.0 Cable
1x USB memory stick with AS585X Eval Kit
Software
12
14
12
13
14
1x ams neckband
1x ams pen
1x Eval Kit User Guide
Ordering Information
Ordering Code
Description
AS585X-CB-EK-ST
AS585X Standard Board
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2
Getting Started
2.1
System Requirement
AS585X
Getting Started
The AS585X Eval Kit software requires Windows 7 SP1 or later and a port USB 3.0.
2.2
Eval Kit Assembly
Attach the Base Board to the FPGA Adapter Board. The FPGA Module is already pre-mounted on the
FGPA Adapter Board. The AS585X COB Sample Board is already pre-mounted on the AS585X Eval
Kit underneath the shield box. The AS585X COF Sample can be exchanged to the COB one
according to the type of measurement to be performed.
Connect the FPGA Module to its 5 V power supply and to a USB 3.0 port with the supplied cable.
The Eval Kit baseboard requires a voltage supply of +5 V provided to the connector “VDD +5 V” as
well as a voltage of +8 V and -8 V provided to the connectors “VSS -7 V”, “VDD +7 V”, as shown in
Figure 3.
The ±8 V must be provided by an external power supply, while the +5 V voltage can be provided either
from an external power supply leaving the jumper on the FPGA adapter open as shown in Figure 3, or
directly from the FPGA power supply by simply closing the jumper, as shown in Figure 4. It is
important to set the jumper correctly to avoid damages to the Eval Kit.
Figure 3:
Eval Kit Powered by +5 V and ±8 V External Power Supplies
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AS585X
Getting Started
Figure 4:
Eval Kit Powered by ±8 V External Power Supplies and 5 V FPGA Power Supply
The Eval Kit is shipped with the jumper configured to supply the +5 V from the FPGA Adapter Board.
In the default case, where the Eval Kit power is supplied from the FPGA power supply, the connectors
VDD +5 V and its correspondent GND must be left unconnected as shown in Figure 4.
Supply the Eval Kit with +5 V (optional), +8 V and -8 V on the 2 mm banana connectors. Use a current
limit of 800 mA and switch on all supplies at the same time. Under normal conditions +5 V consumes
around 220 mA, +8 V around 70 mA and -8 V around 20 mA.
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3
AS585X
Hardware Description
Hardware Description
The Eval Kit is composed of five boards: The Base Board on which an AS585X sample is mounted, an
FPGA board and its adapter, a Power Module and a DAC Module.
Figure 5:
AS585X Eval Kit Hardware
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3.1
AS585X
Hardware Description
AS585X Eval Kit Base Board
Figure 6:
AS585X Eval Kit Base Board
The Base Board is an interface between the Power Module, DAC Module, the FPGA Module and the
Sample Board. It features a VDDA Step Generator and a Charge Pulse Generator circuit, which are
used to generate the input signal for the different evaluation modes. Please refer to the detailed
description in chapter 6 Evaluation Modes.
3.2
AS585X Eval Kit Power Module
Figure 7:
AS585X Eval Kit Power Module
The Power Module is an adjustable voltage power module with 4 outputs, namely VDD1, VDD2, VDD3
and VDD4. VDD1 is used to supply power to the analog AS585X circuitry while VDD2 is used to
supply the digital one. VDD1 delivers 1A of load current while other outputs are limited to 0.5 A of load
current.
Two on-board shunt resistors are used to measure the VDD1 and VDD2 current consumption of the
Power Module, using 16-bit ΔΣ ADCs. The current consumption values in the Eval Kit Software are
acquired from the Power Module during power offset calibration and power measurements.
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AS585X
Hardware Description
The module performances (voltage drop versus load current, measured at the Power Module output)
are shown on the graphs below on a module where both output voltages are trimmed to 3.5 V. The
noticeable voltage drop is due to the on-board shunt resistor for the measurement of the current
consumption and to the connection to the Base Board, which adds further series resistance.
When the AS585X device is used at maximum power mode (load current = 600 mA), this implies a
50 mV analog voltage supply drop, please refer to the example of the AS585X working point in
Figure 8 shown below (red line).
Figure 8:
AS585X Eval Kit Power Module Output Dynamic
VDD2: Digital supply
3,50
3,50
3,48
3,48
3,46
3,46
VDD [V]
VDD [V]
VDD1: Analog supply
3,44
3,42
3,42
3,40
3,40
0,00
0,50
1,00
load current [A]
3.3
3,44
0,00
0,10
0,20
0,30
0,40
0,50
load current [A]
AS585X Eval Kit DAC Module
Figure 9:
AS585X Eval Kit DAC Module
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AS585X
Hardware Description
The DAC module is used to generate the input signals for the evaluation of the AS585X.
The DAC Module uses a 20-bit DAC, with an output non-linearity verified to be below ±15 µV over its
entire 0 to 5 V range. The non-linearity of the DAC itself is not taken into account and not corrected
during the linearity measurement of the AS585X.
3.4
AS585X Eval Kit COB Sample Board
Figure 10:
AS585X Eval Kit COB Sample Board
The AS585X Sample Board is a chip carrier where an AS585X die is bonded.
In the sample board, the channels "41-48, 73-80, 187-194, 219-226" are bonded to 30 pF line
capacitors and 3 pF charge capacitors for external charge injection.
In the sample board, the channels “116-123, 148-155” are bonded to 30 pF line capacitors.
The channels "0-40, 49-72, 81-115, 124-147, 156-186, 195-218, 227-255" are not bonded.
A detailed description of the charge generation is explained in chapter 6.4 External Charge Generation
(holes)
Figure 11:
AS585X Eval Kit Sample Board Detector Input Schematic Example with Line Capacitor Only
(channel 116)
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AS585X
Hardware Description
Figure 12:
AS585X Eval Kit Sample Board Detector Input Schematic Example with Both Line Capacitor
and Charge Capacitor for Charge Injection (channel 187)
3.5
AS585X Eval Kit COF Sample Board
Figure 13:
AS585X Eval Kit COF Sample with Adapter Board
The Chip-on-Flex is the default package type of the AS585X, where the die is bonded on a flex
substrate. Such package allows the direct connection to an X-Ray photodetector panel.
The input channels of the COF package are unconnected; therefore, the external charge generation
cannot be performed on this package.
Only the measurement in no charge conditions or with internal charge generation can be performed.
Detailed descriptions of such measurements are explained in chapters 6.1 No Charge Generation, 6.2
Internal Charge Generation (holes) and 6.3 Internal Charge Generation (electrons)
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3.6
AS585X
Hardware Description
FPGA Board
Figure 14:
OpalKelly XEM6310-LX45
The FPGA used in the AS585X Eval Kit is an Opal Kelly XEM6310-LX45. The AS585X software loads
into the FPGA a dedicated firmware, through which the FPGA manages the AS585X digital signals
(SPI interface, the LVDS readout, clock generation) and the baseboard circuitry (DAC, Charge Step
Generator, PSRR VDDA Step Generation)
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4
Software Description
4.1
Software Download
AS585X
Software Description
The main software package is distributed upon request from your ams representative.
Please contact your ams representative and once downloaded the software package, the
“AS5850_Eval_SW_v1-0-0.exe” setup wizard needs to be executed.
4.2
Software Installation
Follow the instructions of the wizard to unpack and install the user interface and all required software
packages to run the Eval Kit.
The software does not run if no AS585X Eval Kit hardware is connected.
4.3
Getting Started
Start the AS585X Eval Kit software using the shortcut (
) on the desktop. The software should be
started with administrator privileges in order to save configuration settings. The windows firewall
message can be canceled, as the software does not need access to the internet.
The FPGA’s firmware upload starts automatically.
Figure 15:
Start-Up Window
By default, the configuration “No-Charge-Generation_XX_us” is loaded into the device. To check if the
software is running correctly press the Take Single Frame button and the following images and plot
should be shown on the GUI.
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AS585X
Software Description
Figure 16:
AS585X Eval Kit Software GUI
4.4
GUI Description
The AS585X GUI is composed of one information panel at the bottom and three tabs at the top:
4.4.1
1.
“Single Frame” tab: Is used to acquire images (or single frames) and to evaluate its related
noise level.
2.
“Sweep” tab: Is used to perform linearity and uniformity measurement. During the sweep
measurement, the input signal is swept to evaluate a certain AS585X input range.
3.
“Configuration & Setting” tab: Is used to set the measurements parameters, of both “Single
Frame” and “Sweep”, and configure the AS585X register map.
Information Panel
The information panel is located at the bottom of the GUI and contains information about the LVDS
reading status, the configuration loaded on the AS585X and the exit button.
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AS585X
Software Description
Figure 17:
Information Panel
Figure 18:
Description of the Information Panel
4.4.2
Control/Indicator
Description
CRC Error
Indicates when a CRC error is detected during an LVDS reading. It is
usually green; it becomes red only when CRC error is detected.
LVDS Timeout
Indicates if LVDS reading fails. It is usually green; it becomes red only
when the LVDS reading fails.
Current Configuration
Indicates the configuration stored on the AS585X.
Exit
Stop button
“Single Frame” Tab
Figure 19:
Single Frame Tab
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AS585X
Software Description
Figure 20:
Description of the Single Frame Tab
Control/Indicator
Description
Take Single Frame
Capture an image
Readings
AS585X LVDS output (counts) in LSB vs. number of samples
(consecutive) for all selected channels.
2D Reading
AS585X LVDS output (counts) in LSB represented as intensity (grey
scale) for all selected channels (x-axis) and acquired samples (y-axis).
Differential Image
AS585X LVDS output (counts) with baseline subtracted represented as
intensity (grey scale) for all selected channels (x-axis) and acquired
samples (y-axis).
The baseline is subtracted by dividing the acquisition in two halves (split
the image in 2 images, first half of the lines and second half the lines) and
then the first half is subtracted to the second (first image subtracted to the
second image), as described in Equation 1. Without the baseline, the
resulting image gives an indication on the correlated noise between the
different channels and different lines.
Channel noise
calculated on the
differential image
Noise in LSB vs. channel number represented by the standard deviation
of each channel calculated on the lines of the differential image
Channel average
calculated on the
differential image
Mean value in LSB vs. channel number represented of each channel
calculated on the lines of the differential image
Image Noise [LSB]
Image noise in LSB represented by the standard deviation of the pixels of
the differential image
Line Correlated Noise
[LSB]
Line correlated noise in LSB represented by the standard deviation on
each line of the differential image
Channel Correlated
Noise [LSB]
Channel correlated noise in LSB represented by the standard deviation on
each channel of the differential image
Average Uncorrelated
Noise [LSB]
Square root of the square difference of the Image Noise, Line Correlated
Noise, Channel Correlated Noise as described in Equation 2.
Equation 1:
𝐷𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑡𝑖𝑎𝑙 𝑖𝑚𝑎𝑔𝑒 = 𝐼𝑚𝑎𝑔𝑒 1 − 𝐼𝑚𝑎𝑔𝑒 2
Equation 2:
𝐴𝑣𝑒𝑟𝑎𝑔𝑒 𝑢𝑛𝑐𝑜𝑟𝑟𝑒𝑙𝑎𝑡𝑒𝑑 𝑛𝑜𝑖𝑠𝑒 = √𝐼𝑚𝑎𝑔𝑒 𝑛𝑜𝑖𝑠𝑒 2 − 𝐿𝑖𝑛𝑒 𝑐𝑜𝑟. 𝑛𝑜𝑖𝑠𝑒 2 − 𝐶ℎ𝑎𝑛𝑛𝑒𝑙 𝑐𝑜𝑟. 𝑛𝑜𝑖𝑠𝑒 2
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4.4.3
AS585X
Software Description
Sweep Tab
Figure 21:
Sweep Tab
Figure 22:
Description of the Sweep Tab
Control/Indicator
Description/Note
Start Measurement
Start a sweep as defined in the measurement settings.
Stop Measurement
Stop an ongoing sweep.
Readings with
capacitors 'A'
AS585X LVDS output from “capacitors A” in LSB vs. DAC voltage.
Related input charge can be calculated as described in chapter 5.2 CSA
Operation Overview and chapter 6 Evaluation Modes
INL with capacitors 'A'
INL of AS585X for output from “capacitors A” in LSB calculated with fixed
point method
Average INL with
capacitors 'A'
Maximum INL averaged over selected channels from “capacitors A”
Worst INL with
capacitors 'A'
Maximum INL of worst channel from “capacitors A”
Readings with
capacitors 'B'
AS585X LVDS output from “capacitors B” in LSB vs. DAC voltage.
Related input charge can be calculated as described in chapter 5.2 CSA
Operation Overview and chapter 6 Evaluation Modes
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4.4.4
AS585X
Software Description
Control/Indicator
Description/Note
INL with capacitors 'B'
INL of AS585X for output from “capacitors B” in LSB calculated with fixed
point method
Average INL with
capacitors 'B'
Maximum INL averaged over selected channels from “capacitors B”
Worst INL with
capacitors 'B'
Maximum INL of worst channel from “capacitors B”
Configuration & Setting
Figure 23:
Advanced Settings Window
Configuration Selection
From the “Configuration selection”, it is possible to select the saved configuration. As soon as the
configuration is selected, the register map gets loaded on the AS585X.
All the fields on the measurement setting as well as the AS585X register map can be edited.
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AS585X
Software Description
Save Configuration
If needed, it is possible to save changes into a new configuration, by pressing on the “Save
configuration” button. A window will pop up, asking to type the name of the new configuration
Figure 24:
Configuration Saving Window
In order to prevent the overwriting of the preinstalled configuration, a default configuration protection is
enabled; therefore, it is required to choose a configuration name different from the preinstalled
configuration ones.
Figure 25:
Preinstalled Protection Window
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AS585X
Software Description
Disable Standard Configuration Protection
If it is required to edit the preinstalled configurations, it is possible to disable this function by ticking the
option “Disable Standard Configuration Protection”, and then typing the same name of the
configuration to be edited.
Charge Generation Notes, Channel Selection Notes and ACLK Frequency Note
In this section, some quick explanation notes about the setting can be found.
Single Frame Settings
In this section, settings related to the single frame measurement are located.
Figure 26:
Description of the Single Frame Settings
Function/Control
Description
Vdac [V]
DAC voltage
Number of Samples [#]
Number of samples to acquire in the single frame
Remove # Samples [#]
Number of samples to be ignored before the image acquisition
Sweep Settings
In this section, settings related to the single frame measurement are located.
Figure 27:
Description of the Sweep Settings
Function/Control
Description
Vdac Start [V]
DAC voltage sweep starting value
Vdac Stop [V]
DAC voltage sweep stop value
OCP [V]
Offset correction point for INL calculation with fixed point
method
CGP [V]
Gain correction point for INL calculation with fixed point method
Number of Steps [#]
Sweep number of steps
Number of Samples per Step [#]
Number of samples per step
Remove # Samples per Step [#]
Number of samples to be discarded before the acquisition per
each step
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AS585X
Software Description
External Charge Pulse Generation Settings
In this section, settings related to the External Charge Pulse Generation are located.
Figure 28:
Description of the Single Frame Settings
Function/Control
Description
Charge Pulse Start [# ACLK
cycles after SYNC]
Number of clock cycles after which the charge step starts, with
respect to the start of acquisition (Sync pulse)
Charge Pulse Stop [# ACLK
cycles after SYNC]
Number of clock cycles after which the charge step ends, with
respect to the start of acquisition (Sync pulse)
View Settings
In this section, settings related to the “Channel Selector” are located. Refer to the note section on the
GUI left hand side or to the schematic for a detailed description about the AS585X Sample channels.
Input Digital Signals Settings (from FPGA)
In this section, settings related to the Input Digital Signals Settings (from FPGA) are located.
Figure 29:
Description of the Input Digital Signals Settings (from FPGA)
Function/Control
Description
ACLK Frequency Divider (n)[#]
The FPGA has an internal clock generator at 160 MHz. In order
to generate an appropriate ACLK for the AS585X, the FPGA
clock frequency is divided. To have an ACLK frequency of 8 MHz,
a division factor of 20 is used.
ACLK Frequency [MHz]
ACLK frequency indicator, this value is related to the ACLK
Frequency Divider
Number of ACLK Cycles
Between SYNC Pulses [#]
Defines the SYNC period. The default value is 500 ACLK cycles,
which gives an acquisition time of 62.5 μs at 8 MHz ACLK
frequency.
The SYNC period must be not less than the acquisition time
defined in the AS585X TIME Registers 0x33. Refer to 5.3 Timing
section for the complete explanation.
SYNC Period (Acquisition
Time) [μs]
Sync frequency indicator, this value is related to the ACLK
Frequency Divider and to Number of ACLK Cycles Between
SYNC Pulses
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AS585X
Software Description
AS585X Configuration
In this section, settings related to the “AS585X Configuration” are located, where it is possible to edit
the AS585X register map. Refer to Chapter 8 Register Description of the datasheet for the complete
description.
Raw Data Save
In this section, settings related to the Raw Data Saving are located. Raw data can be saved in CSV
format.
Figure 30:
Description of the Raw Data Save
Function/Control
Description
File Name
Output file name; set the Save Raw Data to File first
File Path
Output file path; set the Save Raw Data to File first
Save Raw Data to File
It enables the data save
As an alternative to the function in the Advanced Setting Window, measurement data can be exported
from all of the Eval Kit’s interface graphs to the clipboard and/or to MS Excel.
Right click on a graph, and then select Clipboard or Excel from the Export menu.
Figure 31:
Export Graphs
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5
AS585X Operation
5.1
Introduction
AS585X
AS585X Operation
In order to evaluate the AS585X performance figures, with the Eval Kit it is possible to emulate the
operating condition of the device as if it was connected to an X-ray flat panel detector.
The charge signal from an X-ray flat panel detector can be emulated by generating charge on
capacitors connected to AS585X inputs. A charge is generated on a capacitor by applying a voltage
step to the capacitor itself.
The charge generated on a capacitor is then transferred to the AS585X and converted into a digital
output. Being the charge generated externally to the AS585X, it is called external charge generation
(or injection).
The circuitry for the external charge implementation is implemented only in the COB sample.
As described in the Chapter 7.6 Low-Noise Charge-Sensitive Amplifier (CSA) in the datasheet,
additional charge can be generated on the internal charge capacitors by the voltages applied to
Vcharge and VchargeAux and injected on the CSA. Being the charge generated internally to the
AS585X, it is called internal charge generation (or injection).
Internal charge injection is used for:
1.
Injecting charge during the offset phase in order to exploit the full input range of AS585X
2.
Generating test charge to evaluate the performance of the AS585X in the same way as with the
external charge, but without unwanted contributions from external components.
In the Eval Kit, the pin Vcharge is connected to the DAC voltage and the pin VchargeAux is connected
to GND.
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5.2
AS585X
AS585X Operation
CSA Operation Overview
The CSA operation is divided in 3 main phases, namely the reset phase, the offset phase and the
signal phase:
1.
Reset phase: During this phase, the output voltage of the CSA has the same value as on the
CSA_VREF_IN pin (typically 1.75V).
2.
Offset phase: A charge (with opposite polarity with respect to the charge which is intended to be
converted during the signal phase) is injected at the CSA input to generate a suitable offset
voltage for an optimal use of the CSA dynamic range with both charge polarities
3.
Signal phase: In this phase, the signal charge is injected to be converted.
Refer to the Chapter 7.6 Low-Noise Charge-Sensitive Amplifier (CSA) in the datasheet for a more
complete description.
5.2.1
CSA Dynamic Range
The CSA dynamic input range is defined by
Equation 3:
|𝑄𝑆𝐼𝐺𝑁𝐴𝐿 | <
𝑄𝐹𝑈𝐿𝐿_𝑆𝐶𝐴𝐿𝐸
+ |𝑄𝑂𝐹𝐹𝑆𝐸𝑇 |
2
If no charge is injected during the offset phase, only half of the dynamic range can be exploited. That
is the reason why a suitable charge needs to be internally generated and injected during this phase.
The CSA voltage decreases when a positive charge (holes) is injected and vice versa, it increases
when a negative charge (electrons) is injected.
Information
In order to have a correct offset correction the polarity of the offset charge must be opposite with
respect to the signal one.
5.2.2
Internal Charge Injection
The charge injection from the internal charge generation circuit 1 is described in Equation 4 the same
equation applies for the charge generation 2 and 3 as well.
Equation 4:
𝑄𝐼𝑁𝐽1 = 𝐶𝐶𝐺1 ∙ (𝑉𝑉𝑐ℎ𝑎𝑟𝑔𝑒 𝑜𝑟 𝑉𝑐ℎ𝑎𝑟𝑔𝑒𝐴𝑢𝑥 − 𝑉𝐶𝑆𝐴_𝑉𝑅𝐸𝐹_𝐼𝑁 ) ∙ 𝑁𝑄_𝑇𝑅𝐴𝑁𝑆1
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AS585X Operation
Where
●
●
●
●
●
5.2.3
QINJ1 is the charge injected
CCG1 are the capacitors used for the charge injection and defined in the Charge Injection
Register A (Address 0x06) cap_q_trans1
VVchargeAux or VVchargeAux are the voltages on pins Vcharge or VchargeAux. Charge can be injected
from one or the other pin and it is defined in Charge Injection Register A (Address 0x06)
pol_q_trans1
VCSA_VREF_IN is 1.75V
NQTRANS1 is the number of charge pulses and it is defined in the Charge Injection Register A
(Address 0x06) n_q_trans1
CSA Output Voltage Offset Phase
The CSA output voltage during the offset phase is described in:
Equation 5:
𝑉𝐶𝑆𝐴_𝑂𝐹𝐹𝑆𝐸𝑇 = 𝑉𝐶𝑆𝐴_𝑉𝑅𝐸𝐹_𝐼𝑁 − (
𝑄𝑂𝐹𝐹𝑆𝐸𝑇
)
𝐶𝐹𝐵
Where
●
●
●
VCSA_VREF_IN is 1.75 V
CFB is the Feedback capacitance of the CSA and it is defined in the Control Register A (Address
0x02) csa_gain
QOFFEST is the charge injected during the offset phase, which is internally generated, (from
charge generation 1) therefore
𝑄𝑂𝐹𝐹𝑆𝐸𝑇 = 𝑄𝐼𝑁𝐽1
During the offset phase, only half of the full range charge can be injected as described in Equation 6.
A frontend saturation will result if a higher charge is injected.
Equation 6:
|𝑄𝑂𝐹𝐹𝑆𝐸𝑇 | <
5.2.4
𝑄𝐹𝑈𝐿𝐿_𝑆𝐶𝐴𝐿𝐸
2
CSA Output Voltage Signal Phase
The CSA output voltage during the signal phase is described in:
Equation 7:
𝑉𝐶𝑆𝐴_𝑆𝐼𝐺𝑁𝐴𝐿 = 𝑉𝐶𝑆𝐴_𝑂𝐹𝐹𝑆𝐸𝑇 − (
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)
𝐶𝐹𝐵
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AS585X Operation
Where
●
●
●
VCSA_OFFSET the CSA output voltage during the offset phase
CFB is the Feedback capacitance of the CSA and defined in the Control Register A (Address
0x02) csa_gain
QSIGNAL is the charge injected during the signal phase, which can be internally or externally
generated
During the signal phase, the charge that can be injected is described in Equation 8.
A frontend saturation will result if a higher charge is injected.
Equation 8:
|𝑄𝑆𝐼𝐺𝑁𝐴𝐿 | <
5.2.5
𝑄𝐹𝑈𝐿𝐿_𝑆𝐶𝐴𝐿𝐸
+ |𝑄𝑂𝐹𝐹𝑆𝐸𝑇 |
2
ADC Digital Output
The charge is now integrated and converted into digital signal as defined in:
Equation 9:
𝑂𝑢𝑡𝑝𝑢𝑡 𝐶𝑜𝑢𝑛𝑡𝑠 = 𝑏𝑎𝑠𝑒𝑙𝑖𝑛𝑒 + (
𝑉𝐶𝑆𝐴_𝑂𝐹𝐹𝑆𝐸𝑇 − 𝑉𝐶𝑆𝐴_𝑆𝐼𝐺𝑁𝐴𝐿
) ∙ 𝐶𝑆𝐴 𝑃𝑜𝑙𝑎𝑟𝑖𝑡𝑦
𝐴𝐷𝐶 𝑟𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛
Where
●
●
●
●
●
VCSA_SIGNAL is the CSA output voltage during the signal phase
VCSA_OFFSET is the CSA output voltage during the offset phase
baseline is ~-29300 LSB
ADC resolution is ~40μV/LSB
CSA Polarity is the polarity selection (electrons or holes) and defined in the Control Register B
(Address 0x03) csa_pol. It is +1 for positive charge (holes) and -1 for negative charge:
●
●
csa_pol=0: Positive charge (holes) → CSA Polarity= +1
csa_pol=1: Negative charge (electrons) → CSA Polarity= -1
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5.3
AS585X
AS585X Operation
Timing
As described in Chapter 7.10.4 Readout Mode 4 – All Parallel of the datasheet, in the AS585X the
CSA charge acquisition of row n, the ADC signal conversion of the previous row n-1 and LVDS data
output of row n-2 are done in parallel. The user needs to make sure that the LVDS readout of row n- 2
is completed before the ADC conversion of row n-1 is finished.
As the block times (the charge acquisition time, the ADC conversion time and the data output time)
may be all different form each other; it is important for a correct operation that the time between SYNC
pulses is greater than the slowest AS585X block time.
Equation 10:
𝑆𝑌𝑁𝐶 𝑝𝑒𝑟𝑖𝑜𝑑 ≥ 𝑀𝑎𝑥 [𝑐ℎ𝑎𝑟𝑔𝑒 𝑎𝑐𝑞𝑢𝑖𝑠𝑖𝑡𝑖𝑜𝑛 𝑡𝑖𝑚𝑒, 𝐴𝐷𝐶 𝑐𝑜𝑛𝑣𝑒𝑟𝑠𝑖𝑜𝑛 𝑡𝑖𝑚𝑒, 𝑑𝑎𝑡𝑎 𝑜𝑢𝑡𝑝𝑢𝑡 𝑡𝑖𝑚𝑒]
Figure 32:
AS585X Timing Diagram
SYNC
CSA
CSA Charge Acquisition (Row n)
Charge ac quisi tion tim e
ADC
ADC Signal Conversion (Row n-1)
A DC conv ersi on ti me
LVDS
LVDS data output (Row n-2)
Data output t ime
SYNC period
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5.3.1
AS585X
AS585X Operation
Charge Acquisition Time and the ADC Conversion Time
The Charge Acquisition Time and the ADC Conversion Time can be chosen according to time and
power requirements of the application from the
●
●
●
Control Register A (Address 0x02) csa_pwr
Control Register A (Address 0x02) adc_pwr
Control Register A (Address 0x02) adc_osr
as summarized in Figure 33
Figure 33:
AS585X Minimum Charge Acquisition Time and Minimum ADC Conversion Time
AS585X
Version
AS5852
AS5851
AS5850
CSA Power
Option
<csa_pwr>
Minimum Charge
Acquisition Time
ADC Power
Option
<adc_pwr>
OSR
<adc_osr>
Minimum ADC
Conversion Time
00
76 μs
0
0
38 μs
00
76 μs
0
1
45 μs
00
76 μs
0
0
38 μs
00
76 μs
0
1
45 μs
01
38 μs
0
0
38 μs
01
38 μs
0
1
45 μs
00
76 μs
0
0
38 μs
00
76 μs
0
1
45 μs
01
38 μs
0
0
38 μs
01
38 μs
0
1
45 μs
10
28.5 μs
1
0
19 μs
10
28.5 μs
1
1
22.5 μs
11
19 μs
1
0
19 μs
11
19 μs
1
1
22.5 μs
Information
In this document only the AS5850 and AS5851 time settings are covered.
The AS5852 time register settings can be calculated by doubling the values of the AS5851 ones.
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5.3.2
AS585X
AS585X Operation
Data Output Time
The Data Output Time depends only on the input LVDS clock frequency and it can be chosen
according to time and power requirements of the application.
The maximum allowed LVDS clock frequency is 160 MHz.
Since the minimum value of the Charge Acquisition Time and the ADC Conversion Time is 19 μs at an
ACLK frequency of 8 MHz, an LVDS frequency of 115 MHz is sufficient in all possible configuration.
Equation 11:
𝐷𝑎𝑡𝑎 𝑂𝑢𝑡𝑝𝑢𝑡 𝑇𝑖𝑚𝑒 =
4144
2 ∙ 𝐿𝑉𝐷𝑆 𝐶𝑙𝑜𝑐𝑘 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦
Where
●
●
4144 = 259 words (start word + temperature word +256 channels + end word) * 16-bit per word
Factor 2 because of the dual data rate
Figure 34:
AS585X Data Output Time
LVDS Clock Frequency
Data Output Time
160 MHz
12.95 μs
140 MHz
14.8 μs
115 MHz
18.1 μs
80 MHz
25.9 μs
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5.3.3
AS585X
AS585X Operation
AS585X TIME Registers (Address 0x20 – 0x33)
The timing management on the AS585X is defined in the Time Registers.
The content of such registers is expressed in number of ACLK cycles after the SYNC.
Information
When the ADC is in low power mode (<adc_pwr>=0), only even values are allowed in the time
registers!
Figure 35:
AS585X Allowed Time Registers Values
AS585X Version
ADC Power
Option
<adc_pwr>
Minimum ADC Conversion
Time
Allowed Time Register
Values
AS5851 and
AS5852
0
38 μs
Even
AS5850
1
19 μs
Odd and Even
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Figure 36:
Example: TIME Registers (Address 0x20 – 0x33) Content of the Configuration “Internal-ChargeGeneration-Holes_20_us”
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AS585X Operation
Acquisition Time
Information
The minimum acquisition time is to be considered an absolute minimum and it is not recommended
to be used as typical case, unless explicitly required by the application.
When possible it is recommended to use typical timing setting.
By using typical timing settings an AS5850 configuration is optimized for 20 μs line time and it is
used as use case for this document.
A detailed description of the acquisition time setting is described in “Minimum Acquisition Time” and
“Recommended Acquisition Time” in page 42.
The acquisition time or line time is defined in
●
Time Register A (Address 0x33) t_acquisition
The minimum line time of 19 μs at an ACLK frequency of 8 MHz, which corresponds to 152 ACLK
cycles, which can only be achieved when both CSA and ADC are configured in high power mode
(<csa_pwr>=11, <adc_pwr>=1).
In general, the acquisition time needs to fulfil the following condition
Equation 12:
𝐴𝑐𝑞𝑢𝑖𝑠𝑖𝑡𝑖𝑜𝑛 𝑡𝑖𝑚𝑒 ≥ 𝑀𝑎𝑥 [𝐶ℎ𝑎𝑟𝑔𝑒 𝑎𝑐𝑞𝑢𝑖𝑠𝑖𝑡𝑖𝑜𝑛 𝑡𝑖𝑚𝑒, 𝐴𝐷𝐶 𝑐𝑜𝑛𝑣𝑒𝑟𝑠𝑖𝑜𝑛 𝑡𝑖𝑚𝑒]
Figure 37:
AS585X Acquisition Time
ADC Power
Option
<adc_pwr>
Minimum ADC
Conversion
Time
Min
Acquisition
Time
Typ
Acquisition
Time
AS5851
0
38 μs
304 ACLK
cycles
320 ACLK
cycles
AS5850
1
19 μs
152 ACLK
cycles
160 ACLK
cycles
AS585x
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Acquisition
Time
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AS585X
AS585X Operation
Main CSA Phases
Figure 38:
AS585X CSA Phases
SYNC
Reset phase
Offset phase
Signal phase
VCSA_MAX
VCSA_OFFSET
VCSA_OUT
VCSA_RESET
VCSA_SIGNAL
VCSA_MIN
Charge acquisition time
The timings of the 3 main CSA phases are defined in
●
●
●
●
●
●
Time Register D (Address 0x23) t_csareset_start
Time Register E (Address 0x24) t_csareset_end
Time Register F (Address 0x25) t_offset_start
Time Register G (Address 0x26) t_offset_end
Time Register H (Address 0x27) t_signal_start
Time Register I (Address 0x28) t_signal_end
It is important that the CSA reset start at least after 1 ACLK cycle and to leave 1 ACLK cycle between
each phase when the ADC is in high power mode (<adc_pwr>=1). These values must be doubled
when the ADC is in low power mode (<adc_pwr>=0).
Figure 39:
AS585X CSA Reset Start
<adc_pwr>
Minimum
ADC
Conversion
Time
Min CSA
Reset Start
Typ CSA
Reset Start
Max CSA
Reset Start
AS5851
0
38 μs
2 ACLK
cycles
2 ACLK
cycles
2 ACLK
cycles
AS5850
1
19 μs
1 ACLK
cycles
1 ACLK
cycles
1 ACLK
cycles
AS585X
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AS585X Operation
Figure 40:
AS585X Time Between CSA Phases
AS585X
Version
ADC Power
Option
<adc_pwr>
Minimum ADC
Conversion Time
Min Time
Between
Phases
Typ Time
Between
Phases
Max Time
Between
Phases
AS5851
0
38 μs
2 ACLK
cycles
2 ACLK
cycles
2 ACLK cycles
AS5850
1
19 μs
1 ACLK
cycles
1 ACLK
cycles
1 ACLK cycles
Figure 41:
Example: Register Map of the Configuration “Internal-Charge-Generation-Holes_20_us”
Parameter
Register
Value
Start CSA reset
t_csareset_start
1 ACLK Cycles
End CSA reset
t_csareset_end
26 ACLK Cycles
Start CSA offset phase
t_offset_start
27 ACLK Cycles
End CSA offset phase
t_offset_end
92 ACLK Cycles
Start CSA signal phase
t_signal_start
93 ACLK Cycles
End CSA signal phase
t_signal_end
158 ACLK Cycles
Internal Charge Injection
The charge injection timings of the 3 circuits are defined in
●
●
●
Time Register A (Address 0x20) t_qtrans_start1
Time Register B (Address 0x21) t_qtrans_start2
Time Register C (Address 0x22) t_qtrans_start3
It is recommended to inject the charge 1 ACLK cycle after the start of the phase where the charge is
intended to be injected when the ADC is in high power mode (<adc_pwr>=1). These values must be
doubled when the ADC is in low power mode (<adc_pwr>=0).
In the example below, the Charge Injection A is used on the offset phase, the Charge Injection B is
used on the signal phase and the Charge Injection C is not used.
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AS585X Operation
Figure 42:
AS585X CSA Phases with Internal Charge Injection
SYNC
Reset phase
Offset phase
Signal phase
Pcharge1
Pcharge2
Pcharge3
VCSA_MAX
VCSA_OFFSET
VCSA_OUT
VCSA_RESET
VCSA_SIGNAL
VCSA_MIN
Charge acquisition time
Figure 43:
Example: Register Map of the Configuration “Internal-Charge-Generation-Holes_20_us”
Parameter
Register
Value
Start 1st charge injection
t_qtrans_start1
28 ACLK Cycles
Start 2nd charge injection
t_qtrans_start2
94 ACLK Cycles
Start 3rd charge injection
t_qtrans_start3
0 ACLK Cycles
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AS585X
AS585X Operation
Filter Acceleration
VSSA
VDDA
Figure 44:
AS585X Functional Diagram
csa_antibloom
Anti
blooming
CSA_VREF_LN
pd_enable
Reset
x4
CFB
LPF caps
Signal
lpf_tc
csa_gain
DETECTOR
+
x4
pol_q_
trans
CCG
Offset
lpf_acc
LNA
csa_cg
Charge
Injection
CCDS
Cboff set
VCHARGE_AUX
CLINE
2
2
CSA_VREF_IN
VCHARGE
PTFT
CPIX
RCDS
In the AS585X, the CSA output is fed into the low-pass filter. The filter time constant can be configured
by changing the resistor value on bits <lpf_tc>. For fast settling, a filter acceleration circuit, which
shortens the resistor by setting <lpf_acc> to logic 1 is implemented.
The filter acceleration circuit can be activated 3 times; one for each of the main CSA phases, and it is
defined in
●
●
●
●
●
●
Time Register J (Address 0x29) t_filtacc_start1
Time Register K (Address 0x2A) t_filtacc_end1
Time Register L (Address 0x2B) t_filtacc_start2
Time Register M (Address 0x2C) t_filtacc_end2
Time Register N (Address 0x2D) t_filtacc_start3
Time Register O (Address 0x2E) t_filtacc_end3
It is recommended to start the filter acceleration simultaneously with the corresponding phase and let
it last around 10-20 ACLK cycles, when the ADC is in high power mode (<adc_pwr>=1). These values
must be doubled when the ADC is in low power mode (<adc_pwr>=0).
In case of longer acceleration phases, it is anyhow recommended to leave several ACLK cycles
between the end of the acceleration and the end of its correspondent phase.
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AS585X Operation
Figure 45:
AS585X Delay between CSA Phase Start and Filter Acceleration
<adc_pwr>
Min Delay Between
CSA Phase Start
and Filter
Acceleration
Typ Delay Between
CSA Phase Start
and Filter
Acceleration
Max Delay Between
CSA Phase Start
and Filter
Acceleration
AS5851
0
0 ACLK cycles
0 ACLK cycles
0 ACLK cycles
AS5850
1
0 ACLK cycles
0 ACLK cycles
0 ACLK cycles
AS585X
Version
ADC Power
Option
Figure 46:
AS585X Filter Acceleration Duration
AS585X Version
ADC Power
Option
<adc_pwr>
Min Filter
Acceleration
Duration
Typ Filter
Acceleration
Duration
AS5851
0
20-40 ACLK cycles
AS5850
1
10-20 ACLK cycles
Max Filter
Acceleration
Duration
Figure 47:
Example: Register Map of the Configuration “Internal-Charge-Generation-Holes_20_us”
Parameter
Register
Value
Start 1st filter acceleration
t_filtacc_start1
1 ACLK Cycle
Stop 1st filter acceleration
t_filtacc_end1
10 ACLK Cycles
Start 2nd filter acceleration
t_filtacc_start2
27 ACLK Cycles
Stop 2nd filter acceleration
t_filtacc_end2
47 ACLK Cycles
Start 3rd filter acceleration
t_filtacc_start1
93 ACLK Cycles
Stop 3rd filter acceleration
t_filtacc_end1
113 ACLK Cycles
CDS Reset Duration
The CDS reset duration is defined in
●
Time Register P (Address 0x2F) t_adcreset_dur
The absolute minimum duration is 1 ACLK cycle but 2 ACLK cycles are recommended when the ADC
is in high power mode (<adc_pwr>=1). These values must be doubled when the ADC is in low power
mode (<adc_pwr>=0).
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AS585X Operation
The CDS reset phases start at the same time as the ADC reset phases, as defined in
●
●
Time Register R (Address 0x31) t_adcreset_start1
Time Register S (Address 0x32) t_adcreset_start2
As described in paragraph 5.3.3 ADC/CDS Reset Start and Stop.
Figure 48:
AS585X CDS Reset Duration
ADC Power
Option
AS585X
Version
<adc_pwr>
Min CDS Reset
Duration
Typ CDS Reset
Duration
AS5851
0
2 ACLK cycles
4 ACLK cycles
AS5850
1
1 ACLK cycles
2 ACLK cycles
Max CDS Reset
Duration
Figure 49:
Example: Register Map of the Configuration “Internal-Charge-Generation-Holes_20_us”
Parameter
Register
Value
CDS reset duration
t_adcreset_dur
2 ACLK Cycle
ADC Reset and Conversion
Figure 50:
AS585X ADC Phases
SYNC
ADC Reset 1
ADC Conversion 1
ADC Reset 2
ADC Conversion 2
ADC conversion time
Each AS585X ADC does the sequential acquisition of two channels; therefore, during the conversion
time two reset phases and two conversion phases take place.
As described in the Chapter 7.8 Analog to Digital Converter (ADC) of the datasheet, the ADC
conversion phase is defined by the oversampling ratio (OSR) in:
●
Control Register A (Address 0x02) adc_osr
and it can be chosen between two discrete values, 74 and 88. This corresponds to 74 or 88 ACLK
cycles when <adc_pwr>=1 and 148 or 176 ACLK cycles respectively when <adc_pwr>=0.
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AS585X Operation
Figure 51:
AS585X ADC Conversion Time
ADC Power Option
OSR
<adc_pwr>
<adc_osr>
AS585X
0
0
148 ACLK cycles
AS585X
0
1
176 ACLK cycles
AS5850
1
0
74 ACLK cycles
AS5850
1
1
88 ACLK cycles
AS585x Version
ADC Conversion
Concerning the ADC reset phase, when the ADC is in high power mode (<adc_pwr>=1) its absolute
minimum duration is at least 1 ACLK cycle longer than CDS reset duration. The recommended
duration is 6 ACLK cycles. These values must be doubled when the ADC is in low power mode
(<adc_pwr>=0).
Equation 13:
𝐴𝐷𝐶 𝑟𝑒𝑠𝑒𝑡 𝑑𝑢𝑟𝑎𝑡𝑖𝑜𝑛 ≥ 𝐶𝐷𝑆 𝑟𝑒𝑠𝑒𝑡 𝑑𝑢𝑟𝑎𝑡𝑖𝑜𝑛 + 1
Figure 52:
AS585X ADC Reset Duration
AS585x
Version
ADC Power
Option
<adc_pwr>
Min ADC Reset
Duration
Typ ADC Reset
Duration
AS585X
0
4 ACLK cycles
12 ACLK cycles
AS5850
1
2 ACLK cycles
6 ACLK cycles
Max ADC Reset
Duration
ADC/CDS Reset Start and Stop
The ADC reset phases start are defined in
●
●
Time Register R (Address 0x31) t_adcreset_start1
Time Register S (Address 0x32) t_adcreset_start2
These registers control the CDS reset start as well.
The ADC reset 1 should start at the beginning of the acquisition and the ADC reset 2 should start right
after the first conversion is finished
Equation 14:
𝐴𝐷𝐶 𝑟𝑒𝑠𝑒𝑡 𝑠𝑡𝑎𝑟𝑡 2≥𝐴𝐷𝐶 𝑟𝑒𝑠𝑒𝑡 𝑠𝑡𝑎𝑟𝑡 1+𝐴𝐷𝐶 𝑟𝑒𝑠𝑒𝑡 𝑑𝑢𝑟𝑎𝑡𝑖𝑜𝑛+𝐴𝐷𝐶 𝑐𝑜𝑛𝑣𝑒𝑟𝑠𝑖𝑜𝑛 (From Figure 51)
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AS585X Operation
Figure 53:
Example: Register Map of the Configuration “Internal-Charge-Generation-Holes_20_us”
Parameter
Register
Value
ADC reset duration
t_adcreset_dur
6 ACLK Cycle
ADC reset start 1
t_adcreset_start1
0 ACLK Cycle
ADC reset start 2
t_adcreset_start2
80 ACLK Cycle
Minimum Acquisition Time
If the minimum line time is desired, the ADC reset duration needs to be set at its minimum of 2 ACLK
cycles and the OSR at 74 ACLK cycle (<adc_osr>=0).
In this case the ADC conversion time is
Equation 15:
𝑀𝑖𝑛𝑖𝑚𝑢𝑚 𝐴𝐷𝐶 𝑐𝑜𝑛𝑣𝑒𝑟𝑠𝑖𝑜𝑛 𝑡𝑖𝑚𝑒 = 2 ∙
𝑂𝑆𝑅 + 𝐴𝐷𝐶 𝑟𝑒𝑠𝑒𝑡 𝑑𝑢𝑟𝑎𝑡𝑖𝑜𝑛 152 𝐴𝐶𝐿𝐾 𝑐𝑦𝑐𝑙𝑒𝑠
=
= 19μ𝑠
𝐴𝐶𝐿𝐾 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦
8𝑀𝐻𝑧
In this case, the ADC reset phases 1 and 2 start as soon as possible, which means
●
●
Time Register R (Address 0x31) t_adcreset_start1=0
Time Register S (Address 0x32) t_adcreset_start2=76
Moreover, also the CDS reset duration must be set to its minimum value of 1 ACLK cycle, in order to
fulfil the condition in Equation 13:
𝐴𝐷𝐶 𝑟𝑒𝑠𝑒𝑡 𝑑𝑢𝑟𝑎𝑡𝑖𝑜𝑛 ≥ 𝐶𝐷𝑆 𝑟𝑒𝑠𝑒𝑡 𝑑𝑢𝑟𝑎𝑡𝑖𝑜𝑛 + 1
Recommended Acquisition Time
In the recommended line time condition, the ADC reset duration should be set to 6 ACLK cycles. With
an OSR of 74 ACLK cycles (<adc_osr>=0), the ADC conversion time is
Equation 16:
𝑅𝑒𝑐𝑜𝑚𝑚𝑒𝑛𝑑𝑒𝑑 𝐴𝐷𝐶 𝑐𝑜𝑛𝑣𝑒𝑟𝑠𝑖𝑜𝑛 𝑡𝑖𝑚𝑒 = 2 ∙
𝑂𝑆𝑅 + 𝑟𝑒𝑠𝑒𝑡 𝑑𝑢𝑟𝑎𝑡𝑖𝑜𝑛 160 𝐴𝐶𝐿𝐾 𝑐𝑦𝑐𝑙𝑒𝑠
=
= 20μ𝑠
𝐴𝐶𝐿𝐾 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦
8𝑀𝐻𝑧
In this case, it is important that the ADC reset phases 1 and 2 start as soon as possible, which means
●
●
Time Register R (Address 0x31) t_adcreset_start1=0
Time Register S (Address 0x32) t_adcreset_start2=80
The recommended CDS reset duration is 2 ACLK cycles, which fulfils the condition in Equation 13:
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AS585X Operation
𝐴𝐷𝐶 𝑟𝑒𝑠𝑒𝑡 𝑑𝑢𝑟𝑎𝑡𝑖𝑜𝑛 ≥ 𝐶𝐷𝑆 𝑟𝑒𝑠𝑒𝑡 𝑑𝑢𝑟𝑎𝑡𝑖𝑜𝑛 + 1
Line Driver Timing
Figure 54:
Functional Diagram of Flat Panel and AS585X Front-End
In the AS585X operation, the CSA receive charge from a TFT panel and the timing is controlled by a
line driver. Refer to Chapter 7.3 of the datasheet for the complete description.
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AS585X Operation
Figure 55:
Main CSA Phases During AS585X Operation
Reset phase
Offset phase
Signal phase
Pcharge1
Pcharge2
Pinjection
PTFT (Line driver)
VCSA_MAX
VCSA_OFFSET
VCSA_OUT
VCSA_RESET
VCSA_SIGNAL
VCSA_MIN
As shown in Figure 55, the line driver needs to close slightly after the signal phase starts and needs to
open slightly after the signal phase ends.
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6
Evaluation Modes
6.1
No Charge Generation
AS585X
Evaluation Modes
In “No charge generation” mode, no charge is injected on the AS585X. Therefore, it is possible to
evaluate the AS585X noise and the output in no signal condition (baseline).
It can be evaluated with both the COB and COF samples.
A typical “Single Frame” taken in this mode is shown in Figure 56
Figure 56:
Typical No Charge Generation Single Frame
The baseline counts is ~ -29300 LSB.
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6.2
AS585X
Evaluation Modes
Internal Charge Generation (holes)
In the “Internal-Charge-Generation-Holes” mode, negative charge (electrons) is injected during the
offset phase for CSA voltage offset adjustment and a positive charge (holes) is injected during the
signal phase. The offset charge is injected from the pin VchargeAux that is connected to GND while
the signal charge is injected from the pin Vcharge that is driven by the DAC.
It can be evaluated with both the COB and COF samples.
256x
DETECTOR
0 - 255
DCLK_P
DCLK_N
VADC
VCHARGE
DAC Module
VCHARGE_AUX
Figure 57:
AS585X Eval Kit Hardware Architecture
128x
CSA
M
U
X
LPF
caps
DOUT_P
CDS
ampl
ADC
ADC
16
M
U
X
LVDS
DOUT_N
Temperature
sensor
Power
Module
3.5 V
3V
VDDA
VDDA_ADC
VDDD
VDDL
Power supply
& reset
Readout control
Voltage
reference
SPI
CVREF
SCLK
SDI
SDO
CS_N
DATA_START
SYNC
CONV_DONE
ACLK
CSA_VREF_IN
CSA_VREF_OUT
VSSA_VCHARGE
RESET_N
AS585x
Base Board
FPGA
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Evaluation Modes
Figure 58:
Control Register A (Address 0x02) and B (Address 0x03) Content of the Configuration
“Internal-Charge-Generation-Holes_20_us”
Figure 59:
Charge Injection Register A (Address 0x06), B (Address 0x07) and C (Address 0x08) Content of
the Configuration “Internal-Charge-Generation-Holes_20_us”
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Evaluation Modes
Figure 60:
TIME Registers (Address 0x20 – 0x33) Content of the Configuration “Internal-ChargeGeneration-Holes_20_us”
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6.2.1
AS585X
Evaluation Modes
Electrons Internal Charge Injection during the Offset Phase from VchargeAux
As shown in the “Internal-Charge-Generation-Holes_20_us” register map, the offset phase starts at 27
and ends at 92 as
●
●
TIME Registers (Address 0x25) t_offset_start=27
TIME Registers (Address 0x26) t_offset_end=92
The offset charge is generated by the internal charge generation circuit 1. The charge is injected
during the offset phase as
●
TIME Registers (Address 0x20) t_qtrans_start1=28
The offset charge is injected from the pin VchargeAux as
●
Charge Injection Register A (Address 0x06) pol_q_trans1=0
The amount of charge injected from VchargeAux is calculated as:
Equation 17:
𝑄𝑂𝐹𝐹𝑆𝐸𝑇 = 𝐶𝐶𝐺1 ∙ (𝑉𝑉𝑐ℎ𝑎𝑟𝑔𝑒𝐴𝑢𝑥 − 𝑉𝐶𝑆𝐴_𝑉𝑅𝐸𝐹_𝐼𝑁 ) ∙ 𝑁𝑄_𝑇𝑅𝐴𝑁𝑆1
Since the pin VchargeAux is connected to GND in the Eval Kit, the equation becomes
𝑄𝑂𝐹𝐹𝑆𝐸𝑇 = 𝐶𝐶𝐺1 ∙ (−𝑉𝐶𝑆𝐴_𝑉𝑅𝐸𝐹_𝐼𝑁 ) ∙ 𝑁𝑄_𝑇𝑅𝐴𝑁𝑆1
Where
●
●
●
VCSA_VREF_IN=1.75 V
Charge Injection Register A (Address 0x06) cap_q_trans1=0010: CCG1=200 fF
Charge Injection Register A (Address 0x06) n_q_trans1=1: NQTRANS1=1
Substituting the values, the equation becomes
𝑄𝑂𝐹𝐹𝑆𝐸𝑇 = 200𝑓𝐹 ∙ (−1.75𝑉) ∙ 1 = −0.35𝑝𝐶
As the CSA full scale range is defined in the
●
Control Register A (Address 0x02) csa_gain= 00011
●
●
CFB=0.84pF
Full scale range=2pC
The condition in Equation 6:
|𝑄𝑂𝐹𝐹𝑆𝐸𝑇 | <
𝑄𝐹𝑈𝐿𝐿_𝑆𝐶𝐴𝐿𝐸
2
is fulfilled.
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Evaluation Modes
If a positive charge is to be injected during the signal phase, a negative charge is required during the
offset phase in order to exploit the full input range.
The Eval Kit does not allow control on the voltage applied to the pin VchargeAux (shorted to GND),
therefore only discrete values of negative charge can be injected, according to the available
combinations allowed by cap_q_trans1 and n_q_trans1.
6.2.2
CSA Output Voltage Offset Phase
The CSA output voltage at the end of the offset phase is:
𝑉𝐶𝑆𝐴_𝑂𝐹𝐹𝑆𝐸𝑇 = 𝑉𝐶𝑆𝐴_𝑉𝑅𝐸𝐹_𝐼𝑁 − (
𝑄𝑂𝐹𝐹𝑆𝐸𝑇
−0.35𝑝𝐶
) = 1.75𝑉 − (
) = 2.17𝑉
𝐶𝐹𝐵
0.84𝑝𝐹
Where CFB is the CSA feedback capacitance defined in
●
Control Register A (Address 0x02) csa_gain= 00011: CFB=0.84 pF
Figure 61:
Charge Injection Timing Diagram During the Offset Phase(1)
Reset phase
Offset phase
Pcharge1
Pcharge2
Pinjection
PTFT (Line driver)
VCSA_MAX
VCSA_OFFSET
VCSA_OUT
VCSA_RESET
VCSA_MIN
(1)
After the negative offset internal charge injection of -0.35 pC, the CSA output voltage Increases
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6.2.3
AS585X
Evaluation Modes
Holes Internal Charge Injection During the Signal Phase from Vcharge
As shown in the “Internal-Charge-Generation-Holes_20_us” register map, the signal phase starts at 93
and ends at 158
●
●
TIME Registers (Address 0x27) t_signal_start=93
TIME Registers (Address 0x28) t_signal_end=158
The signal charge is generated by the internal charge generation circuit 2, as the charge is injected
during the signal phase as
●
TIME Registers (Address 0x21) t_qtrans_start2=94
The signal charge is injected from the pin Vcharge as
●
Charge Injection Register B (Address 0x06) pol_q_trans2=1
The amount of charge injected from Vcharge is calculated as:
𝑄𝑆𝐼𝐺𝑁𝐴𝐿 = 𝐶𝐶𝐺2 ∙ (𝑉𝑉𝑐ℎ𝑎𝑟𝑔𝑒 − 𝑉𝐶𝑆𝐴_𝑉𝑅𝐸𝐹_𝐼𝑁 ) ∙ 𝑁𝑄_𝑇𝑅𝐴𝑁𝑆2
Where VVcharge is driven by the DAC and its voltage can be adjusted from the “Configuration and
Settings” tab in the Eval Kit software
Figure 62:
Measurement Settings
Substituting the values
●
●
Charge Injection Register B (Address 0x07) cap_q_trans2=1000: CCG2=800fF
Charge Injection Register B (Address 0x07) n_q_trans2=1: NQTRANS2=1
It becomes
𝑄𝑆𝐼𝐺𝑁𝐴𝐿 = 800𝑓𝐹 ∙ (2.5 − 1.75𝑉) ∙ 1 = 0.6𝑝𝐶
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AS585X
Evaluation Modes
With an offset charge of -0.35 pC, the condition described in Equation 8 is fulfilled
|𝑄𝑆𝐼𝐺𝑁𝐴𝐿 | <
6.2.4
𝑄𝐹𝑈𝐿𝐿𝑆𝐶𝐴𝐿𝐸
2𝑝𝐶
+ |𝑄𝑂𝐹𝐹𝑆𝐸𝑇 | → 0.6𝑝𝐶 <
+ 0.35𝑝𝐶
2
2
CSA Output Voltage Signal Phase
The CSA output voltage at the end of the signal phase is:
𝑉𝐶𝑆𝐴_𝑆𝐼𝐺𝑁𝐴𝐿 = 𝑉𝐶𝑆𝐴_𝑂𝐹𝐹𝑆𝐸𝑇 − (
𝑄𝑆𝐼𝐺𝑁𝐴𝐿
0.6𝑝𝐶
) = 2.17𝑉 − (
) = 1.46𝑉
𝐶𝐹𝐵
0.84𝑝𝐹
Where CFB is the CSA feedback capacitance, defined as
●
Control Register A (Address 0x02) csa_gain= 00011: CFB=0.84pF
Figure 63:
Charge Injection Timing Diagram During the 3 CSA Phases.
Reset phase
Offset phase
Signal phase
Pcharge1
Pcharge2
Pinjection
PTFT (Line driver)
VCSA_MAX
VCSA_OFFSET
VCSA_OUT
VCSA_RESET
VCSA_SIGNAL
VCSA_MIN
6.2.5
ADC Digital Output
The expected ADC output is calculated as
Equation 18:
𝑂𝑢𝑡𝑝𝑢𝑡 = 𝑏𝑎𝑠𝑒𝑙𝑖𝑛𝑒 + (
𝑉𝐶𝑆𝐴_𝑂𝐹𝐹𝑆𝐸𝑇 − 𝑉𝐶𝑆𝐴_𝑆𝐼𝐺𝑁𝐴𝐿
) ∙ 𝐶𝑆𝐴 𝑃𝑜𝑙𝑎𝑟𝑖𝑡𝑦
𝐴𝐷𝐶 𝑟𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛
Where
●
VCSA_SIGNAL is the CSA output voltage during the signal phase
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●
●
●
●
AS585X
Evaluation Modes
VCSA_OFFSET is the CSA output voltage during the offset phase
baseline is ~-29300 LSB
ADC resolution is ~40µV/LSB
CSA Polarity is the polarity selection (electrons or holes) and defined in the Control Register B
(Address 0x03) csa_pol=0: Positive charge (holes) → CSA Polarity= +1
Therefore:
𝑂𝑢𝑡𝑝𝑢𝑡 = −29300 + (
2.17 − 1.46
) ∙ +1 = −11550 𝐿𝑆𝐵
40 ∙ 10−6
Figure 64:
Typical Internal-Charge-Generation-Holes Single Frame
Figure 64 shows an example of a single frame acquired in the “Internal-Charge-GenerationHoles_20_us” configuration. From the “Readings” plot, it is possible to see that the output is very
stable over many consecutive measurements and from the “Differential Image” no correlated noise is
visible.
The measurement output is very close to calculated values. The user needs anyhow to calibrate the
system with detector (offset and gain calibration).
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6.3
AS585X
Evaluation Modes
Internal Charge Generation (electrons)
In the “Internal-Charge-Generation-Electrons” mode, a negative charge (electrons) is injected during
the signal phase from the pin Vcharge that is driven by the DAC.
In this mode, a positive charge should be injected during the offset phase for CSA voltage offset
adjustment, but due to the limited capabilities of the setup, it is not possible. Therefore, the offset
adjustment is skipped allowing the exploitation of only half of the input range.
More precisely, the injection of a positive charge from the pin VchargeAux would require a voltage
higher than 1.75V on such pin. Being the VchargeAux pin tied to GND and not being able to be driven
to an arbitrary voltage, this operation is not possible.
It can be evaluated with both the COB and COF samples.
256x
DETECTOR
0 - 255
DCLK_N
DCLK_P
VADC
VCHARGE
DAC Module
VCHARGE_AUX
Figure 65:
AS585X Eval Kit Hardware Architecture
128x
CSA
M
U
X
LPF
caps
DOUT_P
CDS
ampl
ADC
ADC
16
M
U
X
LVDS
DOUT_N
Temperature
sensor
Power
Module
3.5 V
3V
VDDA
VDDA_ADC
VDDD
VDDL
Power supply
& reset
Readout control
Voltage
reference
SPI
CVREF
SCLK
SDI
SDO
CS_N
DATA_START
SYNC
CONV_DONE
ACLK
CSA_VREF_IN
CSA_VREF_OUT
VSSA_VCHARGE
RESET_N
AS585x
Base Board
FPGA
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Figure 66:
Control Register A (Address 0x02) and B (Address 0x03) Content of the Configuration
“Internal-Charge-Generation-Electrons_20_us”
Figure 67:
Charge Injection Register A (Address 0x06), B (Address 0x07) and C (Address 0x08) Content of
the Configuration “Internal-Charge-Generation-Electrons_20_us”
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Evaluation Modes
Figure 68:
TIME Registers (Address 0x20 – 0x33) Content of the Configuration “Internal-ChargeGeneration-Electrons_20_us”
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6.3.1
AS585X
Evaluation Modes
No Charge Injection during the Offset Phase from VchargeAux
As it is not possible to inject a suitable positive charge during the offset phase for CSA voltage offset
adjustment, the internal charge generation circuit 1 is disabled
●
●
●
TIME Register (Address 0x20) t_qtrans_start1=0
Charge Injection Register A (Address 0x06) cap_q_trans1=0000
Charge Injection Register A (Address 0x06) n_q_trans1=0
Therefore
𝑄𝑂𝐹𝐹𝑆𝐸𝑇 = 0𝑝𝐶
And the voltage at the end of the offset phase is:
𝑉𝐶𝑆𝐴_𝑂𝐹𝐹𝑆𝐸𝑇 = 𝑉𝐶𝑆𝐴_𝑉𝑅𝐸𝐹_𝐼𝑁 = 1.75𝑉
6.3.2
Electrons Internal Charge Injection during the Signal Phase from Vcharge
As shown in the “Internal-Charge-Generation-Electrons_20_us” register table, the signal phase starts
at 93 and ends at 158
●
●
TIME Register (Address 0x27) t_signal_start=93
TIME Register (Address 0x28) t_signal_end=158
The signal charge is generated by the internal charge generation circuit 2, as the charge is injected
during the signal phase as
●
TIME Register (Address 0x21) t_qtrans_start1=94
The signal charge is injected from the pin Vcharge as
●
Charge Injection Register B (Address 0x06) pol_q_trans2=1
The amount of charge injected from Vcharge is described as:
𝑄𝑆𝐼𝐺𝑁𝐴𝐿 = 𝐶𝐶𝐺2 ∙ (𝑉𝑉𝑐ℎ𝑎𝑟𝑔𝑒 − 𝑉𝐶𝑆𝐴_𝑉𝑅𝐸𝐹_𝐼𝑁 ) ∙ 𝑁𝑄_𝑇𝑅𝐴𝑁𝑆2
Where VVcharge is driven by the DAC, and its voltage can be adjusted from the “Configuration and
Settings” tab in the Eval Kit software
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Evaluation Modes
Figure 69:
Measurement Settings
Substituting the values
●
●
Charge Injection Register B (Address 0x07) cap_q_trans2=1000: CCG2=800fF
Charge Injection Register B (Address 0x07) n_q_trans2=1: NQTRANS2=1
It becomes
𝑄𝑆𝐼𝐺𝑁𝐴𝐿 = 800𝑓𝐹 ∙ (1.5 − 1.75𝑉) ∙ 1 = −0.2𝑝𝐶
Without an offset charge, only half of the full-scale charge can be injected during the signal phase.
The condition described in Equation 8: is fulfilled
|𝑄𝑆𝐼𝐺𝑁𝐴𝐿 | <
6.3.3
𝑄𝐹𝑈𝐿𝐿𝑆𝐶𝐴𝐿𝐸
2𝑝𝐶
− |𝑄𝑂𝐹𝐹𝑆𝐸𝑇 | → 0.2𝑝𝐶 <
+ 0𝑝𝐶
2
2
CSA Output Voltage Signal Phase
The CSA output voltage at the end of the signal phase is:
𝑉𝐶𝑆𝐴_𝑆𝐼𝐺𝑁𝐴𝐿 = 𝑉𝐶𝑆𝐴_𝑂𝐹𝐹𝑆𝐸𝑇 − (
𝑄𝑆𝐼𝐺𝑁𝐴𝐿
−0.2𝑝𝐶
) = 1.75𝑉 − (
) = 1.99𝑉
𝐶𝐹𝐵
0.84𝑝𝐹
As CFB is Feedback capacitance of CSA and defined in the
●
Control Register A (Address 0x02) csa_gain= 00011: CFB=0.84pF
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Figure 70:
Charge Injection Timing Diagram During the 3 CSA Phases
Reset phase
Offset phase
Signal phase
Pcharge1
Pcharge2
Pinjection
PTFT (Line driver)
VCSA_MAX
VCSA_SIGNAL
VCSA_OUT
VCSA_RESET
VCSA_OFFSET
VCSA_MIN
6.3.4
ADC Digital Output
The expected ADC output is calculated as
Equation 19:
𝑂𝑢𝑡𝑝𝑢𝑡 = 𝑏𝑎𝑠𝑒𝑙𝑖𝑛𝑒 + (
𝑉𝐶𝑆𝐴_𝑂𝐹𝐹𝑆𝐸𝑇 − 𝑉𝐶𝑆𝐴_𝑆𝐼𝐺𝑁𝐴𝐿
) ∙ 𝐶𝑆𝐴 𝑃𝑜𝑙𝑎𝑟𝑖𝑡𝑦
𝐴𝐷𝐶 𝑟𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛
Where
●
●
●
●
●
VCSA_SIGNAL is the CSA output voltage during the signal phase
VCSA_OFFSET is the CSA output voltage during the offset phase
baseline is ~-29300 LSB
ADC resolution is ~40 μV/LSB
CSA Polarity is the polarity selection (electrons or holes) and defined in the Control Register B
(Address 0x03) csa_pol=1: Negative charge (electrons) → CSA Polarity= -1
Therefore:
𝑂𝑢𝑡𝑝𝑢𝑡 𝐶𝑜𝑢𝑛𝑡𝑠 = −29300 + (
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1.75 − 1.99
) ∙ −1 = −23300 𝐿𝑆𝐵
40 ∙ 10−6
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Evaluation Modes
Figure 71:
Typical Internal-Charge-Generation-Electrons Single Frame
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6.4
AS585X
Evaluation Modes
External Charge Generation (holes)
In the “External Charge Generation-XX” mode, the charge signal is generated externally by applying a
voltage step to a set of capacitors connected to the AS585X frontend inputs, thus emulating the
charge signal from an X-ray flat panel detector.
It can be evaluated only with the COB sample.
The required voltage step is generated by the charge pulse generator, which generates a signal that
toggles between the DAC voltage and GND. Such signal is applied to the charge capacitor, thus
generating the charge, which is then transferred to the AS585X frontend.
The step timing is controlled by the FPGA.
For the linearity evaluation, the DAC voltage can be swept in order to exploit a certain input charge
range of the AS585X.
The amount of charge, which is injected in the front-end, is expressed in Equation 15:
Equation 20:
𝑄𝐸𝑋𝑇 = 𝐶𝐶𝐻𝐴𝑅𝐺𝐸 ∙ (𝑉𝑆𝑇𝐸𝑃𝐻𝐼𝐺𝐻 − 𝑉𝑆𝑇𝐸𝑃𝐿𝑂𝑊 ) = 𝐶𝐶𝐻𝐴𝑅𝐺𝐸 ∙ (𝑉𝐷𝐴𝐶 − 0)
In the “External Charge Generation-Holes” mode, negative charge (electrons) is injected during the
offsef phase for CSA voltage offset adjustment and a positive charge (holes) is injected during the
signal phase. The offset charge is injected from the pin VchargeAux that is connected to GND while
the signal charge is injected in the frontend from the charge pulse generator.
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Evaluation Modes
DCLK_P
DCLK_N
VADC
VCHARGE
VCHARGE_AUX
Figure 72:
AS585X Eval Kit Hardware Architecture
DAC Module
Ccharge
DETECTORS
41-48,
73-80,
187-194,
219-226
256x
128x
CSA
M
U
X
LPF
caps
DOUT_P
CDS
ampl
ADC
ADC
16
M
U
X
LVDS
DOUT_N
Cline
Temperature
sensor
Power
Module
3.5 V
3V
VDDA
VDDA_ADC
VDDD
VDDL
Power supply
& reset
Readout control
Voltage
reference
SPI
SCLK
SDI
SDO
CS_N
DATA_START
SYNC
CONV_DONE
ACLK
CSA_VREF_IN
CSA_VREF_OUT
VSSA_VCHARGE
RESET_N
AS585x
CVREF
Base Board
FPGA
Figure 73:
Control Register A (Address 0x02) and B (Address 0x03) Content of the Configuration
“External-Charge-Generation-Holes_20_us”
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Evaluation Modes
Figure 74:
Charge Injection Register A (Address 0x06), B (Address 0x07) and C (Address 0x08) Content of
the Configuration “External-Charge-Generation-Holes_20_us”
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Evaluation Modes
Figure 75:
TIME Registers (Address 0x20 – 0x33) Content of the Configuration “External-ChargeGeneration-Holes_20_us”
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6.4.1
AS585X
Evaluation Modes
Electrons Internal Charge Injection during the Offset Phase from VchargeAux
As in “Internal-Charge-Generation-Holes_20_us”, an offset charge of 0.35 pC is injected for CSA
voltage adjustment
𝑄𝑂𝐹𝐹𝑆𝐸𝑇 = 200𝑓𝐹 ∙ (−1.75𝑉) ∙ 1 = −0.35𝑝𝐶
Therefore, the CSA output voltage at the end of the offset phase is:
Equation 21:
𝑉𝐶𝑆𝐴_𝑂𝐹𝐹𝑆𝐸𝑇 = 𝑉𝐶𝑆𝐴_𝑉𝑅𝐸𝐹_𝐼𝑁 − (
6.4.2
𝑄𝑂𝐹𝐹𝑆𝐸𝑇
−0.35𝑝𝐶
) = 1.75𝑉 − (
) = 2.17𝑉
𝐶𝐹𝐵
0.84𝑝𝐹
Holes External Charge Injection during the Signal Phase
As described in Equation 15: the external charge generation is defined as
𝑄𝑆𝐼𝐺𝑁𝐴𝐿 = 𝐶𝐶𝐻𝐴𝑅𝐺𝐸 ∙ (𝑉𝐷𝐴𝐶 − 0)
Where:
●
●
CCHARGE is 3 pF
VDAC is defined from the “Configuration and Settings” tab in the Eval Kit software
Figure 76:
Measurement Settings
Substituting the values
𝑄𝑆𝐼𝐺𝑁𝐴𝐿 = 3𝑝𝐹 ∙ (0.2𝑉 − 0𝑉) = 0.6𝑝𝐶
The CSA output voltage at the end of the signal phase is:
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𝑉𝐶𝑆𝐴_𝑆𝐼𝐺𝑁𝐴𝐿 = 𝑉𝐶𝑆𝐴_𝑂𝐹𝐹𝑆𝐸𝑇 − (
AS585X
Evaluation Modes
𝑄𝑆𝐼𝐺𝑁𝐴𝐿
0.6𝑝𝐶
) = 2.17𝑉 − (
) = 1.46𝑉
𝐶𝐹𝐵
0.84𝑝𝐹
Figure 77:
Charge Injection Timing Diagram During the 3 CSA Phases.
Reset phase
Offset phase
Signal phase
Pcharge1
Pcharge2
Pinjection
PTFT (Line driver)
VCSA_MAX
VCSA_OFFSET
VCSA_OUT
VCSA_RESET
VCSA_SIGNAL
VCSA_MIN
6.4.3
Timing
As described in section 5.3.3 Line Driver Timing, the external charge injection needs to start slightly
after the start of the signal phase and it needs to end slightly after the signal phase.
The charge injection timing is defined in the Eval Kit software
Figure 78:
Example of External Charge Pulse Generation Settings for 20 μs Line Time
As shown in the “External-Charge-Generation-Holes_20_us” register map, the signal phase starts at
93 and ends at 158
●
●
TIME Registers (Address 0x27) t_signal_start=93
TIME Registers (Address 0x28) t_signal_end=158
So the charge injection in this case starts 2 ACLK cycles after the start of signal phase and it ends 2
ACLK cycles after the end of the signal phase.
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6.4.4
AS585X
Evaluation Modes
ADC Digital Output
The expected ADC output is calculated as
Equation 22:
𝑂𝑢𝑡𝑝𝑢𝑡 = 𝑏𝑎𝑠𝑒𝑙𝑖𝑛𝑒 + (
= −29300 + (
𝑉𝐶𝑆𝐴𝑂𝐹𝐹𝑆𝐸𝑇 − 𝑉𝐶𝑆𝐴𝑆𝐼𝐺𝑁𝐴𝐿
) ∙ 𝐶𝑆𝐴 𝑃𝑜𝑙𝑎𝑟𝑖𝑡𝑦 =
𝐴𝐷𝐶 𝑟𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛
2.17 − 1.46
) ∙ +1 = −11550 𝐿𝑆𝐵
40 ∙ 10−6
Figure 79:
Typical External-Charge-Generation-Holes Single Frame
External charge injection is possible only on the channels connected to the Charge Capacitors, which
are 32 on the AS585X sample boards.
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6.5
AS585X
Evaluation Modes
External Charge Generation (electrons)
The “External Charge Generation (electrons)” mode can be evaluated only with the COB sample.
The amount of charge externally injected with the Eval Kit charge generation circuitry is expressed in
Equation 15
𝑄𝐸𝑋𝑇 = 𝐶𝐶𝐻𝐴𝑅𝐺𝐸 ∙ (𝑉𝑆𝑇𝐸𝑃_𝐻𝐼𝐺𝐻 − 𝑉𝑆𝑇𝐸𝑃_𝐿𝑂𝑊 ) = 𝐶𝐶𝐻𝐴𝑅𝐺𝐸 ∙ (𝑉𝐷𝐴𝐶 − 0)
Its polarity can be inverted by inverting the step function as shown in Figure 80
Figure 80:
Charge Injection Timing Diagram During the 3 CSA Phases.
Reset phase
Offset phase
Signal phase
Pcharge1
Pcharge2
Pinjection
PTFT (Line driver)
VCSA_MAX
VCSA_SIGNAL
VCSA_OUT
VCSA_RESET
VCSA_OFFSET
VCSA_MIN
Thus, the charge will be negative, as only positive voltages are allowed for VDAC
Equation 23:
𝑄𝐸𝑋𝑇 = 𝐶𝐶𝐻𝐴𝑅𝐺𝐸 ∙ (𝑉𝑆𝑇𝐸𝑃_𝐿𝑂𝑊 − 𝑉𝑆𝑇𝐸𝑃_𝐻𝐼𝐺𝐻 ) = 𝐶𝐶𝐻𝐴𝑅𝐺𝐸 ∙ (0 − 𝑉𝐷𝐴𝐶 )
A negative charge is injected during the signal phase and no charge is injected during the offset
phase, as it is not possible to inject holes during the offset phase, because VchargeAux is connected
to GND as described in chapter 6.3.1.
Only half of the CSA dynamic range can be exploited with the Eval Kit in this case.
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6.5.1
AS585X
Evaluation Modes
Timing
The step function can be inverted by adjusting the timing: rise the level of the step during the reset
phase and then let it fall back to the low level slightly after the start of the signal phase, leaving it to the
low level for the rest of the acquisition, as described in paragraph 5.3.3 Line Driver Timing.
For example, in the case the signal phase starts at 93 and ends at 158, the charge pulse could start at
20 and end at 95, as shown in Figure 81
Figure 81:
External Charge Pulse Generation Settings
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7
AS585X
Other Operation Modes
Other Operation Modes
In order to enable a wide range of applications, the AS585X is highly configurable and it has several
other operation modes with respect to those treated in this manual, such as:
●
●
●
Binning mode
240 channels mode
Readout modes:
●
●
●
●
Readout Mode 1 – All Serial
Readout Mode 2 – Charge Acquisition and Signal Conversion Parallel
Readout Mode 3 – Signal Conversion and Data Output Parallel
Readout Mode 4 – All Parallel
However, a detailed description of all of them is out of the scope of this manual; therefore please get
in contact with ams AG to request engineering support to best address a specific solution for your
application.
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8
AS585X
Table of Abbreviations
Table of Abbreviations
Figure 82:
Table of Abbreviations
Abbreviation
Explanation
ADC
Analog-to-Digital Converter
CDS
Correlated Double Sampling
CSA
Charge Sensing Amplifier
INL
Integral Nonlinearity
LPF
Low-Pass Filter
LSB
Least Significant Bit
LVDS
Low-Voltage Differential Signaling
SPI
Serial Peripheral Interface
Abbreviation Explanation
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9
Troubleshooting
9.1
Connection Issue
AS585X
Troubleshooting
Please check the correct driver installation in the Device Manager.
To start the Device Manager click the Start button and type in the Start Search box device manager
and then press enter.
Figure 83:
Device Manager Connection
XEM6310 FPGA Board
If the XEM6310 does not appear under “FrontPanel devices”, drivers are not correctly installed. Please
disconnect the board, uninstall and re-install the software. Then re-connect the board and verify the
system is fully functional.
9.2
Screen Limitation Issue
The software front panel’s size cannot be reduced below 1366x768 pixels. This corresponds to the
minimum supported screen resolution. In case the screen resolution is below this value and the
software interface is not entirely visible, reduce Windows’ font size to Smaller - 100%. The
corresponding menu is accessible via Control Panel - Display.
Moreover, always make sure the resolution is set to the native resolution of the screen in the same
menu.
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9.3
AS585X
Troubleshooting
CRC Fail
Figure 84:
CRC Fail
If this dialog message pops up, please check the power supply on the board. If the power supply is
connected properly and the problem persists, please use another external power supply instead of the
supplied one, as described in section 2.2. If the problem persist, please contact the technical support.
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10
AS585X
Revision Information
Revision Information
Changes from previous version to current revision v1-00
Page
Initial version
●
●
Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
Correction of typographical errors is not explicitly mentioned.
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11
AS585X
Legal Information
Legal Information
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved.
The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the
copyright owner.
Demo Kits, Evaluation Kits and Reference Designs are provided to recipient on an “as is” basis for demonstration and
evaluation purposes only and are not considered to be finished end-products intended and fit for general consumer use,
commercial applications and applications with special requirements such as but not limited to medical equipment or automotive
applications. Demo Kits, Evaluation Kits and Reference Designs have not been tested for compliance with electromagnetic
compatibility (EMC) standards and directives, unless otherwise specified. Demo Kits, Evaluation Kits and Reference Designs
shall be used by qualified personnel only.
ams AG reserves the right to change functionality and price of Demo Kits, Evaluation Kits and Reference Designs at any time
and without notice.
Any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a
particular purpose are disclaimed. Any claims and demands and any direct, indirect, incidental, special, exemplary or
consequential damages arising from the inadequacy of the provided Demo Kits, Evaluation Kits and Reference Designs or
incurred losses of any kind (e.g. loss of use, data or profits or business interruption however caused) as a consequence of their
use are excluded.
ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability
to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.
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RoHS Compliant: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our
semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories (per
amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where
designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br/Cl): ams Green defines that in addition to RoHS compliance, our products are free
of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material).
Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that
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has taken and continues to take reasonable steps to provide representative and accurate information but may not have
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consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
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Please visit our website at www.ams.com
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Buy our products or get free samples online at www.ams.com/Products
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Technical Support is available at www.ams.com/Technical-Support
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Tel: +43 (0) 3136 500 0
For further information and requests, e-mail us at [email protected]
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