EVB-LAN9730-MII Evaluation Board User Manual

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SMSC LAN9730 Revision 1.0 (10-14-11)

USER MANUAL

EVB-LAN9730-MII Evaluation Board User Manual

1 Introduction

The LAN9730 is a high-performance, small form factor solution for USB to 10/100 Ethernet port bridging. With applications ranging from embedded systems, set-top boxes, and PVR’s, to USB port replicators and test instrumentation, the LAN9730 is targeted as a high-performance, low-cost

USB/Ethernet connectivity solution.

The LAN9730 contains an integrated 10/100 Ethernet PHY, HSIC interface, Hi-Speed USB 2.0 device controller, 10/100 Ethernet MAC, TAP controller, EEPROM controller, and a FIFO controller with a total of 30 kB of internal packet buffering. The LAN9730 complies with the IEEE 802.3 (full/half-duplex

10BASE-T and 100BASE-TX) Ethernet protocol and USB 2.0 specification, enabling compatibility with industry standard Fast Ethernet and USB 2.0 applications. The HSIC interface is compliant with the

High-Speed Interchip USB Electrical Specification 1.0. High-Speed Inter-Chip (HSIC) is a digital interconnect bus that enables the use of USB technology as a low-power chip-to-chip interconnect at speeds up to 480 Mb/s.

The EVB-LAN9730-MII is an Evaluation Board (EVB) that utilizes the LAN9730 to provide a fully functional, self-powered HSIC to Ethernet interface. The EVB-LAN9730-MII provides fully integrated

Ethernet and HSIC interfaces via the onboard RJ45 and HSIC Data/Strobe coaxial connectors. The

EVB-LAN9730-MII supports internal and external PHY modes. An external PHY may be connected via the onboard 40-pin female MII connector. The onboard 256x8 EEPROM is used to load the EVB-

LAN9730-MII’s USB configuration parameters and MAC address.

EVB-LAN9730-MII software drivers are available for Windows

®

XP, Windows Vista, Mac

®

OS X,

Linux

®

, and Windows CE. Additional manufacturing and diagnostic tools are available for debugging and external EEPROM configuration.

A simplified block diagram of the EVB-LAN9730-MII can be seen in

Figure 1.1

.

JTAG Header

2 x 10

External PHY

40-Pin MII Connector

(Female)

Data

Strobe

256 x 8

µ

Wire

EEPROM

SMSC

LAN9730

10/100

Ethernet

Magnetics

& RJ45

HSIC_DATA

HSIC_STROBE

HSIC Coax

Connectors

EVB-LAN9730-MII

Figure 1.1 EVB-LAN9730-MII Block Diagram

Ethernet

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EVB-LAN9730-MII Evaluation Board User Manual

The EVB-LAN9730-MII kit includes two U.FL coaxial cables (Hirose part number U.FL-2LP-068N2-A-

(100)) used for connection of the HSIC Data and Strobe signals to a USB HSIC Host. A U.FL RF coaxial cable extraction tool (Hirose part number U.FL-LP-N-2) is provided for properly removing the coaxial cables from the HSIC interconnects. The HSIC coaxial cables and extraction tool can be seen in

Figure 1.2

.

Note:

To avoid inadvertent damage, do not use the extraction tool while the EVB-LAN9730-MII is powered.

Figure 1.2 EVB-LAN9730-MII Coaxial Cables and Extraction Tool

1.1

References

Concepts and material available in the following documents may be helpful when using the EVB-

LAN9730-MII.

Table 1.1 References

DOCUMENT

SMSC LAN9730 Datasheet

AN8-13 Suggested Magnetics

SMSC EVB-LAN9730-MII Evaluation Board Schematic

LOCATION

http://www.smsc.com/lan9730 http://www.smsc.com/lan9730 http://www.smsc.com/lan9730

SMSC LAN9730 3

USER MANUAL

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EVB-LAN9730-MII Evaluation Board User Manual

2 Board Details

This section includes the following EVB-LAN9730-MII board details:

„

Configuration

„

Mechanicals

2.1

Configuration

The following sub-sections describe the various board features including jumpers, LEDs, test points,

and system connections. A top view of the EVB-LAN9730-MII is shown in Figure 2.1

.

JTAG

Header

JP10, JP11,

JP13, JP14

J2, JP1 LAN9730

Reset

Switch

HSIC

Interface

JP6

LED2

Female MII

Connector

MII

Testpoints

JP10, JP11,

JP13, JP14

JP2,

JP9

Ethernet Port

(integrated LEDs)

LED1

+5V Power

Input

Figure 2.1 EVB-LAN9730-MII Top View

Note:

The EVB-LAN9730-MII includes a 2 A fuse (F1) to protect from overcurrent conditions. If this fuse becomes damaged, it can be replaced with a 2 A Littlefuse 154002.DR.

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EVB-LAN9730-MII Evaluation Board User Manual

2.1.1

JP1

JP2

JP4

JP5

JP6

JP7

JP8

Jumpers

The following table details the jumper definitions and default settings for the EVB-LAN9730-MII.

Jumper settings may be changed as needed. However, any deviation from the default settings should be approached with care and knowledge of the schematics and datasheet. An incorrect jumper setting may disable the board.

Note:

A dashed line in the

Settings

column indicates an installed jumper. All jumper settings are shown in their default state (self-powered, internal Ethernet PHY operation).

Table 2.1 Jumpers

JUMPER DESCRIPTION

External Host Reset Connect

+1.2 V Power Supply Select

( Note 2.1

)

Ethernet PHY Select

External Reset Connect

LED Connects

( Note 2.2

)

EEPROM Chip Select

Connect

HSIC Slew Tune Boost Select

1 2

1 2

(DNP)

1 2

2---3

1 2

1---2

3---4

5---6

1---2

1 2

2---3

SETTINGS

IN:

Connects J2 (external host reset input) to JP5 for input to nRESET

OUT:

Disconnects J2 (external host reset input) to JP5 for input to nRESET

Note:

JP5 must also be installed to utilize an external host reset input on J2.

IN:

+1.2 V power supplied by an external

+1.2 V power source

OUT:

+1.2 V power supplied by the

LAN9730’s internal regulator

Selects external Ethernet PHY

Selects internal LAN9730 Ethernet PHY

IN:

Connects external reset events

(S1, J1, J2) to nRESET

OUT:

Disconnects external reset events

(S1, J1, J2) to nRESET

IN:

Connects Ethernet Speed LED indicator (T1 - Yellow)

OUT:

Disconnects Ethernet Speed LED indicator (T1 - Yellow)

IN:

Connects Ethernet Link/Activity LED indicator (T1 - Green)

OUT:

Disconnects Ethernet Link/Activity

LED indicator (T1 - Green)

IN:

Connects Ethernet Full Duplex LED indicator (LED2)

OUT:

Disconnects Ethernet Full Duplex

LED indicator (LED2)

IN:

Connects the LAN9730’s EECS pin to the CS pin of the on-board EEPROM

OUT:

Disconnects the LAN9730’s EECS pin from the CS pin of the on-board

EEPROM

Selects 30% HSIC_DATA and

HSIC_STROBE slew rate boost

Selects no HSIC_DATA and

HSIC_STROBE slew rate boost

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EVB-LAN9730-MII Evaluation Board User Manual

JUMPER

JP9

JP10

JP11

JP12

JP13

JP14

JP15

Table 2.1 Jumpers (continued)

DESCRIPTION

+1.2 V Internal Regulator

Select (

Note 2.1

EEPROM Select

)

HSIC Driver Output

Impedance Select

Self/Bus Power Select

Remote Wakeup Select

Port Swap Select

Auto-MDIX Select

1---2

2 3

1---2

2 3

1 2

2---3

1---2

2 3

1 2

2---3

1 2

2---3

1---2

2 3

SETTINGS

+1.2 V power supplied by the LAN9730’s internal regulator

+1.2 V power supplied by an external

+1.2 V power source

Selects 50 Ohm output impedance on

HSIC_DATA and HSIC_STROBE

Selects 40 Ohm output impedance on

HSIC_DATA and HSIC_STROBE

Disables EEPROM usage

Enables EEPROM usage

Self-powered device

Bus-powered device

Remote wakeup is supported

Remote wakeup is not supported

HSIC_DATA and HSIC_STROBE pin functionality is swapped

HSIC_DATA and HSIC_STROBE pin functionality is not swapped

Auto-MDIX is enabled

Auto-MDIX is disabled

Note 2.1

The EVB-LAN9730-MII is configured to utilize the LAN9730’s +1.2 V internal regulator by default (JP2 depopulated and JP9 populated in the 1-2 position). To utilize an external

+1.2 V power source, JP2 must be populated and JP9 must be populated in the 2-3 position. Incorrect JP2 and JP9 jumper settings may disable the board.

Note 2.2

Refer to

Table 2.2, "LEDs"

for descriptions of the various LED functions.

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2.1.2

LEDs

REFERENCE

LED1

LED2

T1

COLOR

Green

Table 2.2 LEDs

Green

Green

Yellow

INDICATION

+3.3 V Power Active

Ethernet Full Duplex

ON:

Full duplex

OFF:

Half duplex

Note:

This LED can be disabled by removing the jumper from the 5-6 position of JP6.

Ethernet Link/Activity

Solid:

Link established

Blinking:

Link activity

OFF:

No link

Note:

This LED can be disabled by removing the jumper from the 3-4 position of JP6.

Ethernet Speed

ON:

100BASE-TX

OFF:

10BASE-T

Note:

This LED can be disabled by removing the jumper from the 1-2 position of JP6.

2.1.3

TEST POINT

TP1

TP2

TP3

TP4

TP5

TP6

TP7

TP8

TP9

TP10

Test Points

Table 2.3 Test Points

DESCRIPTION

nRESET White Test Point

Ground Gold Post Test Point

+5.0 V Red Test Point

Ground Test Point (DNP)

Ground Gold Post Test Point

+3.3 V Orange Test Point

Ground Gold Post Test Point

Ground Gold Post Test Point

+1.2 V Green Test Point

Ground Gold Post Test Point

CONNECTION

nRESET (LAN9730)

GND

+5.0 V

GND

GND

+3.3 V

GND

GND

+1.2 V

GND

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EVB-LAN9730-MII Evaluation Board User Manual

2.1.4

T1

J1

J2

J3

J4

J5

J6

J7

TP11

TP13

System Connections

PLUG/HEADER

P1

Table 2.4 System Connections

DESCRIPTION PART

+5 V Power Supply Barrel Connector

RJ45 Ethernet Port with Integrated

Magnetics & LEDs

1x2 External Reset Button Header

PIN 1:

GND

PIN 2:

Reset Generator Input

Note:

JP5 must be installed to utilize J1.

1x2 External Host Reset Header

PIN 1:

nRESET

PIN 2:

GND

Note:

JP1 and JP5 must be installed to

utilize J2. ( Note 2.3

)

HSIC DATA Coaxial Connector

HSIC STROBE Coaxial Connector

40-pin Female MII Connector

Note:

This connector follows the standardized MII pinout. Refer to the EVB-LAN9730-MII schematic for additional information.

CUI PJ-102AH

Pulse J0011D01BNL

Adam Tech PH1-2-U-A

Adam Tech PH1-2-U-A

Hirose U.FL-R-SMT-1(01)

Hirose U.FL-R-SMT-1(01)

AMP 5787170-4

2x10 JTAG Header for IEEE 1149.1

Compliant TAP Controller

Note:

Refer

Table 2.5

to for a full pin list.

Adam Tech PH2-20-U-A

2x11 MII Test Point Header

Note:

Refer

Table 2.6

to for a full pin list.

Adam Tech PH2-22-U-A

1x2 nPHY_INT Header

PIN 1:

nPHY_INT

PIN 2:

Ground

Note:

In internal PHY mode, nPHY_INT is a configurable output. In external

PHY mode, nPHY_INT is an input.

Adam Tech PH1-2-U-A

1x2 TDO/nPHY_RST Header

PIN 1:

TDO/nPHY_RST

PIN 2:

Ground

Note:

In internal PHY mode, TDO output is enabled. In external PHY mode, nPHY_RST output is enabled for use as an external PHY reset.

Adam Tech PH1-2-U-A

Note 2.3

External host resets must be of the push-pull type. If the external host reset is open drain,

R7 must be removed from the PCB, or the external host reset must be wired directly to

JP1.2.

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EVB-LAN9730-MII Evaluation Board User Manual

.

HEADER PIN

6

7

4

5

1

2

3

8

9

10 nTRST

Ground

TDO

Ground

TDI

Ground

TMS

Ground

TCK

Ground

Table 2.5 2x10 JTAG Header Pinout

DESCRIPTION HEADER PIN

14

15

16

17

11

12

13

18

19

20

No Connect

Ground

No Connect

Ground

No Connect

Ground

No Connect

Ground

No Connect

+3.3 V

DESCRIPTION

.

Table 2.6 2x11 MII Header Pinout

HEADER PIN

6

7

4

5

1

2

3

10

11

8

9

DESCRIPTION

Ground

Ground

MDIO/GPIO1

MDC/GPIO2

TDI/RXD3

TMS/RXD2

TCK/RXD1 nTRST/RXD0

RXDV

RXCLK

RXER

HEADER PIN

15

16

17

18

12

13

14

19

20

21

22

DESCRIPTION

TXER

TXCLK

TXEN

TXD0/GPIO4/EEP_DISABLE

TXD1/GPIO5/RMT_WKP

TXD2/GPIO6/PORT_SWAP

TXD3/GPIO7/50DRIVER_EN

COL/GPIO0

CRS/GPIO3

Ground

Ground

SMSC LAN9730 9

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EVB-LAN9730-MII Evaluation Board User Manual

2.1.5

S1

Switches

SWITCH

Reset switch

Table 2.7 Switches

DESCRIPTION FUNCTION

When pressed, triggers a board reset.

Note:

JP5 must be installed to utilize the on-board reset switch. Refer to

Table 2.1, "Jumpers" for additional

JP5 information.

2.2

Mechanicals

Figure 2.2

details the EVB-LAN9730-MII mechanical dimensions.

0.175

0.175

Ø0.125 Ø0.125

0.175

0.175

TOP VIEW

0.175

0.175

Ø0.125

3.700

Figure 2.2 EVB-LAN9730-MII Mechanicals

Ø0.125

0.175

0.175

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EVB-LAN9730-MII Evaluation Board User Manual

3 User Manual Revision History

Table 3.1 Revision History

REVISION LEVEL & DATE SECTION/FIGURE/ENTRY

Rev. 1.0 (10-14-11) Initial Release

CORRECTION

SMSC LAN9730 11

USER MANUAL

Revision 1.0 (10-14-11)

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

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:

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