Motorola DragonBall MC9328MX1 Reference guide

Motorola DragonBall MC9328MX1 Reference guide

DragonBall MC9328MX1 Integrated

Portable System Processor

Reference Manual

MC9328MX1RM/D

Rev. 2, 02/2003

HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:

Motorola Literature Distribution;

P.O. Box 5405, Denver, Colorado 80217

1-303-675-2140 or 1-800-441-2447

JAPAN:

Motorola Japan Ltd.; SPS, Technical Information Center,

3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan

81-3-3440-3569

ASIA/PACIFIC:

Motorola Semiconductors H.K. Ltd.; Silicon Harbour

Centre, 2 Dai King Street, Tai Po Industrial Estate,

Tai Po, N.T., Hong Kong

852-26668334

TECHNICAL INFORMATION CENTER:

1-800-521-6274

HOME PAGE:

http://www.motorola.com/semiconductors

Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein.

Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in

Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. All other product or service names are the property of their respective owners.

The Bluetooth trademarks are owned by their proprietor and used by Motorola, Inc. under license.

The ARM POWERED logo and ARM7TDMI are the registered trademarks of ARM

Limited. ARM9, ARM920T, and ARM9TDMI are the trademarks of ARM Limited.

Portions of Chapters 4 and 7 of this document are reprinted with permission from

ARM Ltd. and are

©

ARM 2001.

Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

© Motorola, Inc. 2003

About This Book

Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . li

Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . li

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . liv

Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . liv

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lv

Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lv

Chapter 1

Introduction

1.1

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.3

ARM920T Microprocessor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.4

AHB to IP Bus Interfaces (AIPIs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.5

External Interface Module (EIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.6

SDRAM Controller (SDRAMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.7

Clock Generation Module (CGM) and Power Control Module . . . . . . . . . . . . . . . . . . . 1-4

1.8

Two Universal Asynchronous Receiver/Transmitters

(UART 1 and UART 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.9

Two Serial Peripheral Interfaces (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.10

Two General-Purpose 32-Bit Counters/Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.11

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.12

Real-Time Clock/Sampling Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.13

LCD Controller (LCDC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.14

Pulse-Width Modulation (PWM) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.15

Universal Serial Bus (USB) Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.16

Multimedia Card and Secure Digital (MMC/SD) Host Controller. . . . . . . . . . . . . . . . . 1-7

1.17

Memory Stick® Host Controller (MSHC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.18

SmartCard Interface Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.19

Direct Memory Access Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.20

Synchronous Serial Interface and Inter-IC Sound (SSI/I

2

S) Module . . . . . . . . . . . . . . . 1-9

1.21

Inter-IC (I

2

C) Bus Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.22

Video Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.23

General-Purpose I/O (GPIO) Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.24

Bootstrap Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.25

Analog Signal Processing (ASP) Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.26

Bluetooth Accelerator (BTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.27

Multimedia Accelerator (MMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.28

Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

MOTOROLA

Contents

iii

1.29

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.30

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

Chapter 2

Signal Descriptions and Pin Assignments

2.1

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2

I/O Pads Power Supply and Signal Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . 2-8

Chapter 3

Memory Map

3.1

Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.1

Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.2

3.1.3

On-Chip MCU Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Internal Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.1.4

3.1.5

External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Double Map Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.2

Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Chapter 4

ARM920T Processor

4.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2

ARM920T Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.2.1

4.2.2

Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Cache Lock-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2.3

4.2.4

4.2.5

4.2.6

Write Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

PATAG RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

MMUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2.7

Control Coprocessor (CP15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3

ARMv4T Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3.1

4.3.2

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Modes and Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3.3

4.3.4

Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Exception Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.3.5

Conditional Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.4

Four Classes of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.4.1

4.4.2

4.4.2.1

4.4.2.2

Data Processing Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Block Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.4.3

4.4.3.1

Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Branch with Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.4.4

Coprocessor Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.5

The ARM9 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.6

The ARM Thumb Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 iv

MC9328MX1 Reference Manual

MOTOROLA

4.6.1

ARM920T Modes and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Chapter 5

Embedded Trace Macrocell (ETM)

5.1

Introduction to the ETM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2

Programming and Reading ETM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.3

Pin Configuration for ETM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Chapter 6

Reset Module

6.1

Functional Description of the Reset Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1.1

Global Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1.2

ARM920T Processor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.2

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.2.1

Reset Source Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Chapter 7

AHB to IP Bus Interface (AIPI)

7.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.1.2

General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

7.2.1

7.2.1.1

7.2.1.2

7.2.2

Peripheral Size Registers[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12

AIPI1 Peripheral Size Register 0 and AIPI2 Peripheral Size Register 0 . . . . . 7-12

AIPI1 Peripheral Size Register 1 and AIPI2 Peripheral Size Register 1 . . . . . 7-13

Peripheral Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14

7.2.3

7.2.4

Peripheral Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15

Time-Out Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

7.3

Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17

7.3.1

Data Access to 8-Bit Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17

7.3.2

7.3.3

7.3.4

Data Access to 16-Bit Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18

Data Access to 32-Bit Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19

Special Consideration for Non-Natural Size Access . . . . . . . . . . . . . . . . . . . . . . . 7-20

Chapter 8

System Control

8.1

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1.1

Silicon ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8.1.2

8.1.3

Function Multiplexing Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

Global Peripheral Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.1.4

Global Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

8.2

System Boot Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

MOTOROLA

Contents

v

Chapter 9

Bootstrap Mode Operation

9.1

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.1.1

Entering Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.1.2

9.1.3

Bootstrap Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

Registers Used in Bootloader Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.1.4

9.1.5

Setting Up the RS-232 Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

Changing the Speed of Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.2

B-Record Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.3

Instruction Buffer Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.4

Simple Read/Write Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.5

Bootloader Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

9.6

Special Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

Chapter 10

Interrupt Controller (AITC)

10.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.2

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.3

AITC Interrupt Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

10.4

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.4.1

10.4.2

10.4.3

10.4.4

Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

Normal Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

Interrupt Enable Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10

Interrupt Disable Number Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

10.4.5

10.4.5.1

10.4.5.2

10.4.6

10.4.6.1

10.4.6.2

10.4.7

10.4.7.1

Interrupt Enable Register High and Interrupt Enable Register Low . . . . . . . . . . 10-12

Interrupt Enable Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12

Interrupt Enable Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13

Interrupt Type Register High and Interrupt Type Register Low . . . . . . . . . . . . . 10-14

Interrupt Type Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14

Interrupt Type Register Low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15

Normal Interrupt Priority Level Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15

Normal Interrupt Priority Level Register 7. . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16

10.4.7.2

10.4.7.3

10.4.7.4

10.4.7.5

10.4.7.6

10.4.7.7

10.4.7.8

10.4.8

Normal Interrupt Priority Level Register 6. . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17

Normal Interrupt Priority Level Register 5. . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18

Normal Interrupt Priority Level Register 4. . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19

Normal Interrupt Priority Level Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20

Normal Interrupt Priority Level Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21

Normal Interrupt Priority Level Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22

Normal Interrupt Priority Level Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23

Normal Interrupt Vector and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24

10.4.9

Fast Interrupt Vector and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25

10.4.10

Interrupt Source Register High and Interrupt Source Register Low . . . . . . . . . . 10-26

10.4.10.1

10.4.10.2

Interrupt Source Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26

Interrupt Source Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27

10.4.11

Interrupt Force Register High and Interrupt Force Register Low . . . . . . . . . . . . 10-28

10.4.11.1

Interrupt Force Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28 vi

MC9328MX1 Reference Manual

MOTOROLA

10.4.11.2

Interrupt Force Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29

10.4.12

Normal Interrupt Pending Register High

10.4.12.1

10.4.12.2

and Normal Interrupt Pending Register Low . . . . . . . . . . . . . . . . . . . . . . . . . 10-30

Normal Interrupt Pending Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30

Normal Interrupt Pending Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31

10.4.13

Fast Interrupt Pending Register High and Fast Interrupt Pending Register Low . 10-32

10.4.13.1

10.4.13.2

Fast Interrupt Pending Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32

Fast Interrupt Pending Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33

10.5

ARM920T Processor Interrupt Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . 10-34

10.5.1

ARM920T Processor Prioritization of Exception Sources . . . . . . . . . . . . . . . . . . 10-34

10.5.2

10.5.3

10.5.4

10.5.5

10.5.6

AITC Prioritization of Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34

Assigning and Enabling Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34

Enabling Interrupts Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34

Typical Interrupt Entry Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35

Writing Reentrant Normal Interrupt Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-36

Chapter 11

External Interface Module (EIM)

11.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.2

EIM I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.2.1

11.2.2

Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.2.3

11.2.4

11.2.4.1

11.2.4.2

Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

OE—Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

EB [3:0]—Enable Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.2.4.3

11.2.5

11.2.5.1

11.2.5.2

11.2.6

11.2.6.1

11.2.6.2

11.2.6.3

DTACK—Data Transfer Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

Chip Select Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

Chip Select 0 (CS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

Chip Select 1–Chip Select 5 (CS1–CS5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

Burst Mode Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

BCLK—Burst Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

LBA—Load Burst Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

ECB—End Current Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.3

Pin Configuration for EIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.4

Typical EIM System Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6

11.5

EIM Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8

11.5.1

Configurable Bus Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8

11.5.2

11.5.3

11.5.4

11.5.5

Programmable Output Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8

Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8

Burst Clock Divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8

Burst Clock Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9

11.5.6

11.5.7

Page Mode Emulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9

Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9

11.6

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10

11.6.1

Chip Select 0 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11

11.6.1.1

Chip Select 0 Upper Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11

MOTOROLA

Contents

vii

11.6.1.2

11.6.2

11.6.2.1

11.6.2.2

11.6.3

Chip Select 0 Lower Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11

Chip Select 1–Chip Select 5 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12

Chip Select 1–Chip Select 5 Upper Control Registers . . . . . . . . . . . . . . . . . . 11-12

Chip Select 1–Chip Select 5 Lower Control Registers. . . . . . . . . . . . . . . . . . 11-13

EIM Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21

Chapter 12

Phase-Locked Loop and Clock Controller

12.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

12.2

Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

12.2.1

12.2.2

Low Frequency Clock Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

High Frequency Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.3

DPLL Output Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3

12.3.1

DPLL Phase and Frequency Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3

12.4

MC9328MX1 Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

12.4.1

PLL Operation at Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

12.4.2

12.4.3

12.4.4

12.4.5

PLL Operation at Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

ARM920T Processor Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

SDRAM Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

Power Management in the Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

12.5

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5

12.5.1

Clock Source Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5

12.5.2

12.5.3

Peripheral Clock Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

Programming Digital Phase Locked Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9

12.5.3.1

12.5.3.2

12.5.4

12.5.4.1

12.5.4.2

MCU PLL Control Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9

MCU PLL and System Clock Control Register 1. . . . . . . . . . . . . . . . . . . . . . 12-11

Generation of 48 MHz Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11

System PLL Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

System PLL Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13

Chapter 13

DMA Controller

13.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1

13.2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

13.3

Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3

13.3.1

Big Endian and Little Endian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4

13.4

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4

13.4.1

General Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8

13.4.1.1

13.4.1.2

DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8

DMA Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9

13.4.1.3

13.4.1.4

13.4.1.5

13.4.1.6

13.4.1.7

13.4.1.8

DMA Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10

DMA Burst Time-Out Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11

DMA Request Time-Out Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12

DMA Transfer Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13

DMA Buffer Overflow Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14

DMA Burst Time-Out Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 viii

MC9328MX1 Reference Manual

MOTOROLA

13.4.2

13.4.2.1

13.4.2.2

13.4.2.3

13.4.3

13.4.3.1

13.4.3.2

13.4.3.3

2D Memory Registers (A and B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16

W-Size Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16

X-Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17

Y-Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18

Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18

Channel Source Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19

Destination Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20

Channel Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21

13.4.3.4

13.4.3.5

13.4.3.6

13.4.3.7

Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22

Channel Request Source Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25

Channel Burst Length Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26

Channel Request Time-Out Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-27

13.4.3.8

Channel 0 Bus Utilization Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28

13.5

DMA Request Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30

Chapter 14

Watchdog Timer Module

14.1

General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

14.2

Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

14.2.1

14.2.2

Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

Watchdog During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

14.2.2.1

14.2.2.2

Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

14.3

Watchdog After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

14.3.1

Initial Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

14.3.2

14.3.3

14.3.4

14.3.5

Countdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

Reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

Time-Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

Halting the Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

14.4

Watchdog Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

14.4.1

Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

14.4.2

Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

14.5

State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

14.6

Watchdog Timer I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5

14.7

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6

14.7.1

14.7.2

14.7.3

Watchdog Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6

Watchdog Service Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7

Watchdog Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8

Chapter 15

Analog Signal Processor (ASP)

15.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1

15.2

ASP Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1

15.3

Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3

15.4

Pen ADC (PADC) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3

15.4.1

Current-Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

MOTOROLA

Contents

ix

15.4.2

15.4.3

15.4.4

15.4.5

Sample Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5

Auto-Zero Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7

Pen-Down Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7

Pen-Up Detection (Method 1 – Compare Value) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7

15.4.6

15.4.7

Pen-Up Detection (Method 2 – Detect Rising Edge) . . . . . . . . . . . . . . . . . . . . . . . 15-7

Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7

15.5

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8

15.5.1

ASP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9

15.5.2

15.5.3

15.5.4

15.5.5

15.5.6

15.5.7

15.5.8

Pen A/D Sample Rate Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11

Compare Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12

Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13

Interrupt/Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14

Pen Sample FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15

Clock Divide Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16

ASP FIFO Pointer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17

Chapter 16

Bluetooth Accelerator (BTA)

16.1

Bluetooth Primer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1

16.2

BTA Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

16.3

Module Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3

16.3.1

Bluetooth Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3

16.3.1.1

16.3.1.2

16.3.1.2.1

16.3.1.2.2

IP Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4

Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5

Bluetooth Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5

Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6

16.3.1.3

16.3.1.3.1

16.3.1.3.2

16.3.1.3.3

16.3.1.3.4

16.3.1.4

16.3.1.5

16.3.1.6

Bluetooth Pipeline Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7

HEC/CRC Generator and Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8

Encryption and Decryption Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10

Whitening/De-Whitening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11

FEC Coding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11

Bit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11

Correlator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12

Bluetooth Application Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13

16.3.1.7

16.3.1.8

16.3.1.8.1

16.3.1.8.2

Hop Selection Co-Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13

Radio Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13

Frequency Synthesizer and Timing Control . . . . . . . . . . . . . . . . . . . . . . . 16-14

Pulse Width Modulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14

16.3.1.8.3

16.3.2

Radio Module Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14

Wake-Up Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18

16.4

Pin Configuration for BTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19

16.5

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20

16.5.1

16.5.1.1

16.5.1.2

16.5.1.3

16.5.1.4

Sequencer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-26

Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-26

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-27

Packet Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-29

Payload Header Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30 x

MC9328MX1 Reference Manual

MOTOROLA

16.5.4.2

16.5.4.3

16.5.4.4

16.5.4.5

16.5.4.6

16.5.4.7

16.5.4.8

16.5.4.9

16.5.4.10

16.5.4.11

16.5.5

16.5.5.1

16.5.6

16.5.6.1

16.5.6.2

16.5.6.3

16.5.2

16.5.2.1

16.5.2.2

16.5.2.3

16.5.2.4

16.5.2.5

16.5.2.6

16.5.2.7

16.5.2.8

16.5.2.9

16.5.3

16.5.3.1

16.5.3.2

16.5.3.3

16.5.4

16.5.4.1

16.5.6.4

16.5.6.5

16.5.6.6

16.5.7

16.5.7.1

16.5.8

16.5.8.1

16.5.8.2

16.5.8.3

16.5.8.4

16.5.8.5

16.5.8.6

16.5.8.7

16.5.9

16.5.9.1

Bluetooth Clocks Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-31

Native Count Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-31

Estimated Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32

Offset Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-33

Native Clock Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-34

Native Clock High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-35

Estimated Clock Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-36

Estimated Clock High Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-37

Offset Clock Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-38

Offset Clock High Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-39

Bluetooth Pipeline Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-40

HECCRC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-40

White Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-41

Encryption Control X13 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-42

Radio Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-43

Correlation Time Setup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-43

Correlation Time Stamp Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-44

RF GPO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-45

PWM Received Signal Strength Indicator Register . . . . . . . . . . . . . . . . . . . . 16-46

Time A & B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-47

Time C & D Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-48

PWM TX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-49

RF Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-50

RF Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-52

RX Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-54

TX Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-55

Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-56

Bluetooth Application Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-56

Correlator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-57

Threshold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-57

Correlation Max Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-59

Synch Word 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-60

Synch Word 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-61

Synch Word 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-62

Synch Word 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-62

Bit Buffer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-63

Buffer Word Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-63

Wake-Up Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-65

Wake-Up 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-65

Wake-Up 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-66

Wake-Up Delta4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-67

Wake-Up 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-68

WakeUp Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-69

Wake-Up Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-70

Wake-Up Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-71

System Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-72

Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-72

MOTOROLA

Contents

xi

16.5.10

SPI Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-73

16.5.10.1

SPI Word0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-73

16.5.10.2

16.5.10.3

SPI Word1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-74

SPI Word2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-75

16.5.10.4

16.5.10.5

16.5.10.6

16.5.10.7

SPI Word3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-76

SPI Write Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-77

SPI Read Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-78

SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-79

16.5.10.8

SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-81

16.5.11

Frequency Hopping Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-81

16.5.11.1

16.5.11.2

Hop 0 (Frequency In) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-82

Hop 1 (Frequency In) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-82

16.5.11.3

16.5.11.4

16.5.11.5

16.5.11.6

Hop 2 (Frequency In) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-83

Hop 3 (Frequency In) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-84

Hop 4 (Frequency In) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-84

Hop Frequency Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-85

16.5.12

Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-86

16.5.12.1

Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-86

16.5.13

Joint Detect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-87

16.5.13.1

Synchronization Metric Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-87

16.5.13.2

Synchronize Frequency Carrier Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-88

16.5.14

Bit Reverse Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-88

16.5.14.1

16.5.14.2

Word Reverse Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-88

Byte Reverse Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-89

Chapter 17

Multimedia Accelerator (MMA)

17.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1

17.2

MMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1

17.2.1

17.2.2

Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1

MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

17.2.2.1

17.2.2.2

17.2.2.3

17.2.3

Basic MAC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

Data Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3

DCT/iDCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

17.3

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5

17.3.1

MMA MAC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6

17.3.1.1

17.3.1.2

MMA MAC Module Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6

MMA MAC Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7

17.3.1.3

17.3.1.4

17.3.1.5

17.3.1.6

MMA MAC Multiply Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9

MMA MAC Accumulate Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10

MMA MAC Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10

MMA MAC Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11

17.3.1.7

17.3.1.8

17.3.1.9

17.3.1.10

MMA MAC FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12

MMA MAC FIFO Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13

MMA MAC Burst Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14

MMA MAC Bit Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 xii

MC9328MX1 Reference Manual

MOTOROLA

17.3.5.1

17.3.5.2

17.3.5.3

17.3.5.4

17.3.5.5

17.3.5.6

17.3.5.7

17.3.5.8

17.3.5.9

17.3.5.10

17.3.5.11

17.3.2

17.3.3

17.3.3.1

17.3.3.2

17.3.3.3

17.3.3.4

17.3.3.5

17.3.3.6

17.3.4

17.3.4.1

17.3.4.2

17.3.4.3

17.3.4.4

17.3.4.5

17.3.4.6

17.3.5

MMA MAC XY Count Accumulate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15

MMA MAC X Register Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15

MMA MAC X Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16

MMA MAC X Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16

MMA MAC X Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17

MMA MAC X Modify Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18

MMA MAC X Increment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18

MMA MAC X Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19

MMA MAC Y Register Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19

MMA MAC Y Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20

MMA MAC Y Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20

MMA MAC Y Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21

MMA MAC Y Modify Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22

MMA MAC Y Increment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22

MMA MAC Y Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23

MMA DCT/iDCT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24

DCT/iDCT Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24

DCT/iDCT Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25

DCT/iDCT IRQ Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26

DCT/iDCT IRQ Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27

DCT/iDCT Source Data Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-28

DCT/iDCT Destination Data Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-28

DCT/iDCT X-Offset Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29

DCT/iDCT Y-Offset Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29

DCT/iDCT XY Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30

DCT/iDCT Skip Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-31

DCT/iDCT Data FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32

Chapter 18

Serial Peripheral Interface Modules

(SPI 1 and SPI 2)

18.1

SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1

18.2

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2

18.2.1

18.2.2

Phase and Polarity Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2

Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3

18.2.3

Pin Configuration for SPI 1 and SPI 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3

18.3

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5

18.3.1

18.3.2

Receive (RX) Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6

Transmit (TX) Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7

18.3.3

18.3.4

18.3.5

18.3.6

18.3.7

18.3.8

Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8

Interrupt Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10

Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12

Sample Period Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13

DMA Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14

Soft Reset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15

MOTOROLA

Contents

xiii

Chapter 19

LCD Controller

19.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1

19.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1

19.3

LCDC Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.3.1

LCD Screen Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.3.2

19.3.3

19.3.4

19.3.5

Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3

Display Data Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3

Black-and-White Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7

Gray-Scale Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7

19.3.6

19.3.7

19.3.8

19.3.8.1

19.3.8.2

19.3.8.3

19.3.9

19.3.9.1

Color Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8

Frame Rate Modulation Control (FRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10

Panel Interface Signals and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10

Pin Configuration for LCDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11

Passive Matrix Panel Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12

Passive Panel Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13

8 bpp Mode Color STN Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14

Active Matrix Panel Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14

19.3.9.2

Active Panel Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16

19.4

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18

19.4.1

19.4.2

Screen Start Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20

Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20

19.4.3

19.4.4

19.4.5

19.4.6

Virtual Page Width Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21

Panel Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22

Horizontal Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24

Vertical Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25

19.4.7

19.4.8

Panning Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26

LCD Cursor Position Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27

19.4.9

LCD Cursor Width Height and Blink Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28

19.4.10

LCD Color Cursor Mapping Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28

19.4.11

Sharp Configuration 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-30

19.4.12

PWM Contrast Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-32

19.4.13

Refresh Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-33

19.4.14

DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-34

19.4.15

Interrupt Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-35

19.4.16

Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-36

19.4.17

Mapping RAM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-37

19.4.17.1

One Bit/Pixel Monochrome Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-37

19.4.17.2

19.4.17.3

19.4.17.4

19.4.17.5

19.4.17.6

19.4.17.7

Four Bits/Pixel Gray-Scale Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-37

Four Bits/Pixel Passive Matrix Color Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 19-37

Eight Bits/Pixel Passive Matrix Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . 19-38

Four Bits/Pixel Active Matrix Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 19-38

Eight Bits/Pixel Active Matrix Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 19-39

Twelve Bits/Pixel and Sixteen Bits/Pixel Active Matrix Color Mode . . . . . . 19-39 xiv

MC9328MX1 Reference Manual

MOTOROLA

Chapter 20

Multimedia Card/Secure Digital Host Controller Module (MMC/SD)

20.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1

20.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1

20.3

MMC/SD Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2

20.4

MMC/SD Module and Card Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3

20.4.1

20.4.2

20.4.3

20.4.4

MMC and SD Card Pin Assignments and Registers . . . . . . . . . . . . . . . . . . . . . . . 20-3

Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4

Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5

Pin Configuration for the MMC/SD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5

20.5

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5

20.5.1

DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6

20.5.1.1

20.5.1.2

DMA Burst Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7

Write-Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8

20.5.2

20.5.2.1

20.5.2.2

20.5.2.3

Memory Controller (Register Handler) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8

SD I/O—IRQ and ReadWait Service Handling . . . . . . . . . . . . . . . . . . . . . . . . 20-9

Card Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9

MMC/SD Module Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10

20.5.3

20.5.4

Logic and Command Interpreters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10

System Clock Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12

20.5.4.1

Card Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13

20.6

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13

20.6.1

20.6.2

20.6.3

20.6.4

MMC/SD Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14

MMC/SD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16

MMC/SD Clock Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19

MMC/SD Command and Data Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 20-20

20.6.5

20.6.6

20.6.7

20.6.8

MMC/SD Response Time-Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21

MMC/SD Read Time-Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22

MMC/SD Block Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-23

MMC/SD Number of Blocks Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24

20.6.9

MMC/SD Revision Number Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-25

20.6.10

MMC/SD Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26

20.6.11

Commands and Arguments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-28

20.6.11.1

MMC/SD Command Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29

20.6.11.2

20.6.11.3

MMC/SD Higher Argument Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29

MMC/SD Lower Argument Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-30

20.6.12

MMC/SD Response FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-31

20.6.13

MMC/SD Buffer Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-32

20.7

Functional Example for the MMC/SD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-32

20.7.1

Basic Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-33

20.7.2

20.7.2.1

Card Identification State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-33

Card Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-33

20.7.2.2

20.7.2.3

20.7.2.4

20.7.3

20.7.3.1

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-34

Voltage Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-34

Card Registry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-35

Card Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-37

Block Access—Block Write and Block Read . . . . . . . . . . . . . . . . . . . . . . . . 20-37

MOTOROLA

Contents

xv

20.7.5

20.7.6

20.7.7

20.7.7.1

20.7.7.2

20.7.7.3

20.7.8

20.7.8.1

20.7.8.2

20.7.8.3

20.7.8.4

20.7.8.5

20.7.8.5.1

20.7.8.5.2

20.7.8.5.3

20.7.8.5.4

20.7.8.5.5

20.7.8.5.6

20.7.8.5.7

20.7.8.5.8

20.7.3.1.1

20.7.3.1.2

20.7.3.2

20.7.3.2.1

20.7.3.2.2

20.7.3.3

20.7.3.4

20.7.4

20.7.4.1

20.7.4.2

20.7.4.3

20.7.4.3.1

20.7.4.3.2

20.7.4.3.3

20.7.4.3.4

20.7.4.3.5

Block Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-37

Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-39

Stream Access—Stream Write and Stream Read (MMC Only). . . . . . . . . . . 20-42

Stream Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-42

Stream Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-43

Erase—Group Erase and Sector Erase (MMC Only) . . . . . . . . . . . . . . . . . . . 20-44

Wide Bus Selection or Deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-45

Protection Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-45

Card Internal Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-45

Mechanical Write Protect Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-46

Password Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-46

Setting the Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-47

Resetting the Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-47

Locking a Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-47

Unlocking the Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-48

Forcing Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-48

Card Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-49

SD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-51

SD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-52

SD I/O Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-52

SD I/O Suspend and Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-53

SD I/O ReadWait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-53

Commands and Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-54

Application-Specific and General Commands . . . . . . . . . . . . . . . . . . . . . . . . 20-55

Command Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-55

Command Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-55

Commands for the MMC/SD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-56

Response Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-60

R1—Normal Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-60

R1b—Normal Response with Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-61

R2—CID, CSD Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-61

R3—OCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-61

R4—Fast I/O for MMC Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-61

R4b—SD I/O Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-62

R5—Interrupt Request (for MMC Only) . . . . . . . . . . . . . . . . . . . . . . . . . 20-62

R6—SD I/O Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-62

Chapter 21

Memory Stick Host Controller (MSHC) Module

21.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1

21.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1

21.3

Block Diagram and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1

21.4

Memory Stick Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2

21.4.1

21.4.2

Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3

Pin Configuration for the MSHC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3

21.5

Memory Stick Host Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4

21.5.1

Data FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 xvi

MC9328MX1 Reference Manual

MOTOROLA

21.5.2

21.5.3

21.5.3.1

21.5.3.2

21.5.4

21.5.5

21.5.5.1

21.5.5.2

Bus State Control Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5

MSHC Module Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5

Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5

SDIO Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6

Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7

Power Save Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8

Register Access During Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9

Register Access When MSHC Module is Disabled . . . . . . . . . . . . . . . . . . . . . 21-9

21.5.6

21.5.7

Auto Command Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9

Serial Clock Divider Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11

21.5.8

System-Level DMA Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11

21.6

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12

21.7

Memory Stick Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13

21.7.1

Memory Stick Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14

21.7.2

21.7.3

Memory Stick Transmit FIFO Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15

Memory Stick Receive FIFO Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16

21.7.4

21.7.5

21.7.6

21.7.7

Memory Stick Interrupt Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 21-17

Memory Stick Parallel Port Control/Data Register . . . . . . . . . . . . . . . . . . . . . . . 21-19

Memory Stick Control 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-20

Memory Stick Auto Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21

21.7.8

21.7.9

Memory Stick FIFO Access Error Control/Status Register . . . . . . . . . . . . . . . . . 21-21

Memory Stick Serial Clock Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22

21.7.10

Memory Stick DMA Request Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23

21.8

Programmer’s Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-24

21.8.1

21.8.2

21.8.2.1

21.8.2.2

21.8.3

21.8.4

21.8.4.1

21.8.4.2

21.8.5

21.8.5.1

21.8.5.2

21.8.5.3

Memory Stick Serial Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-24

Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26

Write Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26

Read Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26

Transfer Protocol Command (TPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27

Protocol Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-28

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-28

Two State Access Mode Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30

Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30

Bus State Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31

Data Transfer Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31

Chapter 22

Pulse-Width Modulator (PWM)

22.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1

22.2

PWM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1

22.2.1

22.2.2

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1

Pin Configuration for PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2

22.3

PWM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2

22.3.1

Playback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2

22.3.2

22.3.3

Tone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3

Digital-to-Analog Converter (D/A) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3

MOTOROLA

Contents

xvii

22.4

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3

22.4.1

PWM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3

22.4.1.1

22.4.2

HCTR and BCTR Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5

PWM Sample Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6

22.4.3

22.4.4

PWM Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7

PWM Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8

Chapter 23

Real-Time Clock (RTC)

23.1

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2

23.1.1

Prescaler and Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2

23.1.2

23.1.3

Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3

Sampling Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3

23.1.4

Minute Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3

23.2

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4

23.2.1

23.2.2

RTC Days Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4

RTC Hours and Minutes Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5

23.2.3

23.2.4

23.2.5

23.2.6

RTC Seconds Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6

RTC Day Alarm Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7

RTC Hours and Minutes Alarm Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8

RTC Seconds Alarm Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9

23.2.7

23.2.8

RTC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10

RTC Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10

23.2.9

RTC Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13

23.2.10

Stopwatch Minutes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-15

Chapter 24

SDRAM Memory Controller

24.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1

24.2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2

24.3

Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3

24.3.1

SDRAM Command Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3

24.3.2

24.3.3

24.3.4

24.3.5

Page and Bank Address Comparators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3

Row and Column Address Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3

Data Aligner and Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3

Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3

24.3.6

24.3.7

Refresh Request Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3

Powerdown Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4

24.3.8

DMA Operation with the SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4

24.4

External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4

24.4.1

24.4.2

24.4.3

24.4.4

24.4.5

24.4.6

SDCLK—SDRAM Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5

SDCKE0, SDCKE1—SDRAM Clock Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5

CSD0, CSD1—SDRAM Chip-Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5

DQ [31:0]—Data Bus (Internal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6

MA [11:0]—Multiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6

SDBA [4:0], SDIBA [3:0]—Non-Multiplexed Address Bus . . . . . . . . . . . . . . . . . 24-6 xviii

MC9328MX1 Reference Manual

MOTOROLA

24.4.7

24.4.8

DQM3, DQM2, DQM1, DQM0—Data Qualifier Mask . . . . . . . . . . . . . . . . . . . . 24-6

SDWE—Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6

24.4.9

RAS—Row Address Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6

24.4.10

CAS—Column Address Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7

24.4.11

RESET_SF—Reset or Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7

24.4.12

Pin Configuration for SDRAMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7

24.5

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8

24.5.1

SDRAM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9

24.5.2

24.5.3

SDRAM Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16

Miscellaneous Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-17

24.6

Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18

24.6.1

SDRAM and SyncFlash Command Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18

24.6.2

24.6.3

24.6.4

24.6.5

Normal Read/Write Mode (SMODE = 000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19

Precharge Command Mode (SMODE = 001). . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23

Auto-Refresh Mode (SMODE = 010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24

Set Mode Register Mode (SMODE = 011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-25

24.6.6

24.6.7

SyncFlash Load Command Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26

SyncFlash Program Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27

24.7

General Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28

24.7.1

Address Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-29

24.7.1.1

24.7.1.2

24.7.1.3

24.7.2

Multiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-29

Non-Multiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-31

Bank Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-32

Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-32

24.7.3

24.7.3.1

24.7.3.2

24.7.3.3

24.7.4

24.7.4.1

24.7.4.2

24.7.4.3

Self-Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33

Self-Refresh During RESET_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33

Self-Refresh During Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33

Powerdown Operation During Reset and Low-Power Modes . . . . . . . . . . . . 24-33

Clock Suspend Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-35

Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-35

Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-36

Refresh During Powerdown or Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . 24-36

24.8

SDRAM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-37

24.8.1

SDRAM Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-37

24.8.2

24.8.2.1

Configuring Controller for SDRAM Memory Array . . . . . . . . . . . . . . . . . . . . . . 24-37

CAS Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-38

24.8.2.2

24.8.2.3

24.8.2.4

24.8.2.5

Row Precharge Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-38

Row-to-Column Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-38

Row Cycle Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-38

Refresh Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-38

24.8.2.6

24.8.3

24.8.4

24.8.5

24.8.5.1

24.8.5.2

24.8.6

Memory Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-39

SDRAM Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-56

Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-58

Mode Register Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-61

Example 1—256 Mbit SDRAM Mode Register. . . . . . . . . . . . . . . . . . . . . . . 24-61

Example 2—64 Mbit SDRAM Mode Register. . . . . . . . . . . . . . . . . . . . . . . . 24-63

SDRAM Memory Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-65

MOTOROLA

Contents

xix

24.9

SyncFlash Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-65

24.9.1

SyncFlash Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-65

24.9.2

24.9.3

SyncFlash Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-66

Booting From SyncFlash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-66

24.9.4

24.9.5

24.9.6

24.9.7

SyncFlash Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-66

SyncFlash Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-68

Clock Suspend Timer Use with SyncFlash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-69

Powerdown Operation with SyncFlash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-70

24.10 Deep Powerdown Operation with SyncFlash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-70

Chapter 25

SmartCard Interface Module (SIM)

25.1

Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1

25.2

IP Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1

25.2.1

25.2.2

SIM Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2

SIM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2

25.2.3

25.2.4

25.2.5

25.2.6

SIM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2

SIM Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3

SIM General Purpose Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3

SIM LRC and CRC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3

25.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4

25.3.1

SIM Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4

25.3.1.1

25.3.1.2

Baud Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4

Transmitter Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

25.3.1.3

25.3.1.4

25.3.2

25.3.2.1

Receiver Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

Port Controller Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

SIM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

Transmit State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

25.3.2.2

25.3.2.3

25.3.2.4

25.3.2.5

25.3.2.6

25.3.3

25.3.3.1

25.3.3.2

25.3.3.3

25.3.3.4

25.3.3.5

25.3.3.6

25.3.3.7

25.3.4

25.3.4.1

25.3.5

Transmit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7

Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7

Transmit Guard Time Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7

Transmit NACK Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8

Transmit Data Convention Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9

SIM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9

Receive State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9

Data Sampling / Voting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11

Start Bit Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11

Parity Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11

Framing Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12

NACK Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12

Initial Character Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13

Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13

Overrun Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14

Character Wait Time Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14

25.4

SIM Port Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14

25.4.1

SmartCard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14

25.4.2

SmartCard Presence Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15 xx

MC9328MX1 Reference Manual

MOTOROLA

25.6.2

25.6.3

25.6.4

25.6.5

25.6.6

25.6.7

25.6.8

25.6.9

25.4.3

25.4.4

25.4.5

25.4.6

SmartCard Automatic Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15

SIM General Purpose Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16

SIM LRC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16

SIM CRC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17

25.4.7

SIM Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18

25.5

Pin Configuration for SIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18

25.6

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19

25.6.1

Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22

Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23

Receive Threshold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25

Transmit/Receive Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-26

Transmit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27

Receive Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-29

Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-31

Port Transmit Buffer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-32

Receive Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-33

25.6.10

Port Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-34

25.6.11

Transmit Threshold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-35

25.6.12

Transmit Guard Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-36

25.6.13

Open-Drain Configuration Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-37

25.6.14

Reset Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-38

25.6.15

Character Wait Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-39

25.6.16

General Purpose Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-40

25.6.17

Divisor Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-41

25.7

Functional Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-41

25.7.1

Configuring the SIM for Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-41

25.7.2

25.7.3

Configuring the SIM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-42

Configuring the SIM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-43

25.7.4

25.7.5

Configuring the SIM General Purpose Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 25-44

Configuring the SIM Linear Redundancy Check Block. . . . . . . . . . . . . . . . . . . . 25-44

25.7.6

Configuring the SIM Cyclic Redundancy Check Block. . . . . . . . . . . . . . . . . . . . 25-45

25.8

Using the SIM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-45

25.8.1

25.8.2

25.8.3

25.8.4

Receive Parity Errors and Parity NACK Generation . . . . . . . . . . . . . . . . . . . . . . 25-46

Receive Frame Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46

Receive Overrun Errors and Overrun NACK Generation . . . . . . . . . . . . . . . . . . 25-46

Using Initial Character Mode and Resulting Receive Data Formats . . . . . . . . . . 25-47

25.8.5

25.8.6

Initial Character Mode Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-47

Automatic Receiver Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-48

25.8.7

Using the SIM Receiver with T = 1 SmartCards . . . . . . . . . . . . . . . . . . . . . . . . . 25-48

25.9

Using the SIM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-48

25.9.1

25.9.2

25.9.3

25.9.4

Transmit Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-49

Transmit NACKs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-49

Transmit Guard Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-50

Using the SIM Transmit with T = 1 SmartCards . . . . . . . . . . . . . . . . . . . . . . . . . 25-50

25.10 Suggested Programming Models for Specific SmartCards . . . . . . . . . . . . . . . . . . . . 25-51

25.10.1

Answer To Reset (ATR) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-51

25.10.2

Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-52

MOTOROLA

Contents

xxi

25.10.2.1

25.10.2.2

25.10.2.3

Geldkate Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-53

T = 0 SmartCards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-53

T = 1 SmartCards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-54

Chapter 26

General-Purpose Timers

26.1

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2

26.1.1

Pin Configuration for General-Purpose Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2

26.2

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3

26.2.1

Timer Control Registers 1 and 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3

26.2.2

26.2.3

26.2.4

26.2.5

26.2.6

Timer Prescaler Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5

Timer Compare Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6

Timer Capture Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7

Timer Counter Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8

Timer Status Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9

Chapter 27

Universal Asynchronous Receiver/Transmitters (UART) Modules

27.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1

27.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1

27.2.1

27.2.2

Module Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2

Pin Configuration for UART1 and UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3

27.3

Interrupts and DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4

27.4

General UART Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5

27.4.1

27.4.2

RTS—UART Request To Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6

RTS Edge Triggered Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6

27.4.3

27.4.4

27.4.5

27.4.6

DTR—Data Terminal Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7

DTR Edge Triggered Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7

DSR—Data Set Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8

DCD—Data Carrier Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8

27.4.7

27.4.8

RI—Ring Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8

CTS—Clear To Send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8

27.4.9

Programmable CTS Deassertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8

27.4.10

TXD—UART Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8

27.4.11

RXD—UART Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8

27.5

Sub-Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9

27.5.1

27.5.2

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10

Transmitter FIFO Empty Interrupt Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10

27.5.3

27.5.4

27.5.4.1

27.5.5

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-11

Idle Line Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12

Idle Condition Detect Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12

Receiver Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13

27.5.6

27.5.7

27.5.8

27.5.9

Receiving a BREAK Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13

Vote Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13

Binary Rate Multiplier (BRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-14

Baud Rate Automatic Detection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-16 xxii

MC9328MX1 Reference Manual

MOTOROLA

27.5.9.1

Baud Rate Automatic Detection Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-17

27.5.10

Escape Sequence Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-18

27.6

Infrared Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-19

27.7

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-19

27.7.1

27.7.2

27.7.3

27.7.4

UART Receiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-22

UART Transmitter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-24

UART Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-25

UART Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-28

27.7.5

27.7.5.1

27.7.5.2

27.7.6

UART Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-31

UART1 Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-31

UART2 Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-33

UART Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-35

27.7.7

27.7.8

UART FIFO Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-37

UART Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-39

27.7.9

UART Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-41

27.7.10

UART Escape Character Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-43

27.7.11

UART Escape Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-44

27.7.12

UART BRM Incremental Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-45

27.7.13

UART BRM Modulator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-46

27.7.14

UART Baud Rate Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-47

27.7.15

UART BRM Incremental Preset Registers 1–4 . . . . . . . . . . . . . . . . . . . . . . . . . . 27-48

27.7.16

UART BRM Modulator Preset Registers 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-49

27.7.17

UART Test Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-50

27.8

UART Operation in Low-Power System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-51

Chapter 28

USB Device Port

28.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1

28.1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1

28.2

Module Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3

28.2.1

Universal Serial Bus Device Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3

28.2.2

28.2.3

28.2.4

28.2.5

Synchronization and Transaction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4

Endpoint FIFO Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4

Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5

USB Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5

28.2.6

28.2.7

Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5

Pin Configuration for USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6

28.3

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7

28.3.1

USB Frame Number and Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8

28.3.2

28.3.3

28.3.4

28.3.5

USB Specification and Release Number Register . . . . . . . . . . . . . . . . . . . . . . . . . 28-9

USB Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10

USB Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-11

USB Descriptor RAM Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-13

28.3.6

28.3.7

28.3.8

28.3.9

USB Descriptor RAM/Endpoint Buffer Data Register. . . . . . . . . . . . . . . . . . . . . 28-14

USB Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-15

USB Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-17

USB Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-18

MOTOROLA

Contents

xxiii

28.3.10

Endpoint n Status/Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-19

28.3.11

Endpoint n Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-20

28.3.12

Endpoint n Interrupt Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-23

28.3.13

Endpoint n FIFO Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-25

28.3.14

Endpoint n FIFO Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-26

28.3.15

Endpoint n FIFO Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-28

28.3.16

Endpoint n Last Read Frame Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 28-30

28.3.17

Endpoint n Last Write Frame Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 28-31

28.3.18

Endpoint n FIFO Alarm Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-32

28.3.19

Endpoint n FIFO Read Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-33

28.3.20

Endpoint n FIFO Write Pointer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-33

28.4

Programmer’s Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-34

28.5

Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-34

28.5.1

Configuration Download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-35

28.5.1.1

28.5.1.2

USB Endpoint to FIFO Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-37

USB Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-37

28.5.1.3

28.5.1.4

Endpoint Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-37

Enable the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-37

28.6

Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-38

28.6.1

Unable to Complete Device Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-38

28.6.2

28.6.3

Aborted Device Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-38

Unable to Fill or Empty FIFO Due to Temporary Problem . . . . . . . . . . . . . . . . . 28-38

28.6.4

Catastrophic Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-39

28.7

Data Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-39

28.7.1

28.7.1.1

28.7.1.2

28.7.1.3

28.7.1.4

28.7.2

28.7.2.1

28.7.2.2

USB Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-39

Short Packets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-39

Sending Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-39

Receiving Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-40

Programming the FIFO Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-40

USB Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-41

Data Transfers to the Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-41

Data Transfers to the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-41

28.7.3

28.7.4

28.7.4.1

28.7.4.2

28.7.5

28.7.6

28.7.6.1

28.7.6.2

Control Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-42

Bulk Traffic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-42

Bulk OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-42

Bulk IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-42

Interrupt Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-43

Isochronous Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-43

Isochronous Transfers in a Nutshell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-43

The SYNCH_FRAME Standard Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-44

28.8

Interrupt Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-44

28.8.1

USB General Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-44

28.8.1.1

28.8.1.2

MSOF—Missed Start-of-Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-44

SOF—Start-of-Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-44

28.8.1.3

28.8.1.4

28.8.1.5

RESET_STOP—End of USB Reset Signaling. . . . . . . . . . . . . . . . . . . . . . . . 28-44

RESET_START—Start of USB Reset Signaling. . . . . . . . . . . . . . . . . . . . . . 28-44

WAKEUP—Resume (Wake-Up) Signaling Detected . . . . . . . . . . . . . . . . . . 28-45 xxiv

MC9328MX1 Reference Manual

MOTOROLA

28.8.1.6

28.8.1.7

28.8.1.8

28.8.2

28.8.2.1

28.8.2.2

28.8.2.3

28.8.2.4

28.8.2.5

28.8.2.6

28.8.2.7

28.8.2.8

28.8.2.9

28.8.3

28.8.3.1

28.8.3.2

SUSP—USB Suspended. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-45

FRAME_MATCH—Match Detected in USB_FRAME Register . . . . . . . . . 28-45

CFG_CHG—Host Changed USB Device Configuration . . . . . . . . . . . . . . . . 28-45

Endpoint Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-45

FIFO_FULL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-45

FIFO_EMPTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-45

FIFO_ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-45

FIFO_HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-45

FIFO_LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-46

EOT—End of Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-46

DEVREQ—Device Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-46

MDEVREQ—Multiple Device Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-46

EOF—End of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-46

Interrupts, Missed Interrupts and the USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-46

SOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-46

CFG_CHG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-47

28.8.3.3

28.8.3.4

EOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-47

DEVREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-47

28.9

Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-47

28.9.1

Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-47

28.9.2

28.9.3

28.9.4

USB Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-47

UDC Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-47

USB Reset Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-48

I

Chapter 29

2

C Module

29.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1

29.2

Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1

29.3

29.4

I

I

2

2

C System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2

C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3

29.4.1

29.4.2

Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4

Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5

29.4.3

Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5

29.4.4

Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5

29.5

Pin Configuration for I

2

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5

29.6

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6

29.6.1

29.6.2

29.6.3

I

I

I

I

2

2

2

2

C Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7

C Frequency Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8

C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10

29.6.4

29.6.5

29.7

I

2

I

2

C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-12

C Data I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14

C Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14

29.7.1

29.7.2

Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-15

Generation of START. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-15

29.7.3

29.7.4

29.7.5

Post-Transfer Software Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-15

Generation of STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-16

Generation of Repeated START. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-16

MOTOROLA

Contents

xxv

29.7.6

29.7.7

Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-16

Arbitration Lost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-16

Chapter 30

Synchronous Serial Interface (SSI)

30.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1

30.2

SSI Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1

30.2.1

30.2.1.1

SSI Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4

Normal Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4

30.2.1.2

30.2.2

30.2.3

30.2.3.1

Master / Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4

SSI Clock and Frame Sync Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4

Pin Configuration for SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5

Pin Configuration Example Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7

30.3

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7

30.3.1

SSI Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8

30.3.2

30.3.3

SSI Transmit FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9

SSI Transmit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9

30.3.4

30.3.5

30.3.6

30.3.7

SSI Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-12

SSI Receive FIFO Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-12

SSI Receive Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-13

SSI Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-15

30.3.7.1

30.3.8

I2S Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19

SSI Transmit Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-20

30.3.9

SSI Receive Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-23

30.3.10

SSI Transmit Clock Control Register and SSI Receive Clock Control Register . 30-27

30.3.10.1

Calculating the SSI Bit Clock from the Input Clock Value . . . . . . . . . . . . . . 30-28

30.3.11

SSI Time Slot Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-30

30.3.12

SSI FIFO Control/Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-31

30.3.13

SSI Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-34

30.4

SSI Data and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-35

30.4.1

SSI_TXDAT, Serial Transmit Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-35

30.4.2

30.4.3

SSI_RXDAT, Serial Receive Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-35

SSI_TXCLK, Serial Transmit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-35

30.4.4

30.4.5

SSI_RXCLK, Serial Receive Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-35

SSI_TXFS, Serial Transmit Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-36

30.4.6

SSI_RXFS, Serial Receive Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-36

30.5

SSI Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-38

30.5.1

30.5.1.1

30.5.1.2

30.5.2

Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-39

Normal Mode Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-39

Normal Mode Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-39

Network Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-41

30.5.2.1

30.5.2.2

Network Mode Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-41

Network Mode Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-42

30.6

Gated Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-43

30.7

External Frame and Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-44

30.8

SSI Reset and Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-44 xxvi

MC9328MX1 Reference Manual

MOTOROLA

Chapter 31

CMOS Sensor Interface Module

31.6.2

31.6.3

31.6.4

31.6.5

31.6.6

31.6.6.1

31.6.6.2

31.6.7

31.6.7.1

31.6.7.2

31.6.7.3

31.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1

31.2

CSI Module Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1

31.3

CSI Module Interface Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2

31.3.1

Pin Configuration for CSI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3

31.4

CSI Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3

31.4.1

Data FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3

31.4.2

31.4.3

CSI Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4

Register Access When CSI Module is Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4

31.5

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4

31.5.1

CSI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5

31.5.2

31.5.3

CSI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8

CSI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-10

31.5.4

31.5.5

CSI Statistic FIFO Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-11

CSI RxFIFO Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12

31.6

Statistic Data Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-13

31.6.1

Statistic Block Diagram and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-13

Auto Exposure and Auto White Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-13

Auto Focus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-15

Packing of Statistic Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-15

Sensor Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16

Statistic Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16

Start of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16

Auto Focus Spread . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16

Statistic Output and DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16

Statistic Data Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16

Statistic FIFO Full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16

Statistic Data Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16

Chapter 32

GPIO Module and I/O Multiplexer (IOMUX)

32.1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1

32.2

GPIO Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2

32.2.1

32.2.2

GPIO Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3

32.2.3

GPIO Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3

32.3

GPIO Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4

32.4

Pin Configuration for GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4

32.5

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-7

32.5.1

32.5.2

32.5.2.1

32.5.2.2

32.5.3

32.5.3.1

Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9

Output Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-10

Output Configuration Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-10

Output Configuration Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-11

Input Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-12

Input Configuration Register A1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-12

MOTOROLA

Contents

xxvii

32.5.3.2

32.5.3.3

32.5.3.4

32.5.4

32.5.5

32.5.6

32.5.7

32.5.7.1

Input Configuration Register A2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-13

Input Configuration Register B1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-14

Input Configuration Register B2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-15

Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-16

GPIO In Use Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-17

Sample Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-18

Interrupt Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-19

Interrupt Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-19

32.5.7.2

32.5.8

Interrupt Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-20

Interrupt Mask Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-21

32.5.9

Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-22

32.5.10

General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-23

32.5.11

Software Reset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-24

32.5.12

Pull_Up Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-25 xxviii

MC9328MX1 Reference Manual

MOTOROLA

List of Figures

Figure 1-1 MC9328MX1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Figure 3-1 MC9328MX1 MCU Physical Memory Map (4 Gbyte) . . . . . . . . . . . . . . . . . . . 3-2

Figure 4-1 ARM920T Core Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Figure 5-1 ETM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Figure 6-1 Reset Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

Figure 6-2 DRAM and Internal Reset Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Figure 7-1 AIPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

Figure 7-2 Block Diagram of the AIPI Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

Figure 9-1 Bootloader Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

Figure 10-1 AITC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

Figure 11-1 Example of EIM Interface to Memory and Peripherals . . . . . . . . . . . . . . . . . . 11-6

Figure 11-2 Example of EIM Interface to Burst Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7

Figure 12-1 Clock Controller Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

Figure 13-1 DMAC in MC9328MX1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

Figure 13-2 DMAC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

Figure 13-3 DMA Request and Acknowledge Timing Diagram . . . . . . . . . . . . . . . . . . . . . 13-3

Figure 13-4 2D Memory Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3

Figure 14-1 Watchdog Timer Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

Figure 14-2 Counter State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

Figure 15-1 ASP System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1

Figure 15-2 Simplified ASP Signal Path Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2

Figure 15-3 Pen Input Sampling Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5

Figure 16-1 Functional Blocks in a Bluetooth System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

Figure 16-2 Functional Blocks in the Bluetooth Accelerator. . . . . . . . . . . . . . . . . . . . . . . . 16-3

Figure 16-3 Bluetooth Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8

Figure 16-4 BitBuf Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12

Figure 16-5 Programming Interfaces for the MC13180 Radio . . . . . . . . . . . . . . . . . . . . . 16-15

Figure 16-6 Timing of the RF Module Control Signals for the MC13180 Radio . . . . . . . 16-16

Figure 16-7 Programming Interface for the SiWave Radio . . . . . . . . . . . . . . . . . . . . . . . . 16-17

Figure 16-8 Timing of RF Module Control Signals for the SiWave Radio . . . . . . . . . . . . 16-17

Figure 16-9 Block Diagram of the Wake-Up Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18

Figure 16-10 Timing of the Wake-Up Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19

Figure 16-11 SPI Clock Dividers Determine Duty Cycle of SPI Clock . . . . . . . . . . . . . . . 16-80

Figure 17-1 MMA Data Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

MOTOROLA

List of Figures

xxix

Figure 17-2 Circular Buffering Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3

Figure 17-3 DCT/iDCT Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

Figure 17-4 Data Formatting for DCT and iDCT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

Figure 18-1 SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2

Figure 18-2 SPI Generic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3

Figure 19-1 LCDC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

Figure 19-2 LCD Screen Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3

Figure 19-3 Pixel Location on Display Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4

Figure 19-4 Display Data Mapping, 1/2/4/8 bpp Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5

Figure 19-5 Display Data Mapping, 16 bpp Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7

Figure 19-6 Gray-Scale Pixel Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8

Figure 19-7 Passive Matrix Color Pixel Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9

Figure 19-8 Active Matrix Color Pixel Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9

Figure 19-9 LCDC Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11

Figure 19-10 LCDC Interface Timing for 4-bit Data Width Gray-Scale Panels . . . . . . . . . 19-12

Figure 19-11 LCDC Interface Timing for 8-bit Data Passive Matrix Color Panels. . . . . . . 19-13

Figure 19-12 Horizontal Sync Pulse Timing in Passive Mode . . . . . . . . . . . . . . . . . . . . . . 19-14

Figure 19-13 Vertical Sync Pulse Timing Passive, Color, (Non-TFT) Mode . . . . . . . . . . . 19-14

Figure 19-14 LCDC Interface Timing for Active Matrix Color Panels . . . . . . . . . . . . . . . . 19-16

Figure 19-15 Horizontal Sync Pulse Timing in TFT Mode . . . . . . . . . . . . . . . . . . . . . . . . . 19-17

Figure 19-16 Vertical Sync Pulse Timing TFT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17

Figure 19-17 Register Memory Mapping Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19

Figure 19-18 Horizontal Timing in MC9328MX1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31

Figure 20-1 MMC/SD Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2

Figure 20-2 System Interconnection with MMC/SD Module . . . . . . . . . . . . . . . . . . . . . . . 20-2

Figure 20-3 DMAC Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6

Figure 20-4 FIFO Usage for Different Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8

Figure 20-5 Memory Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9

Figure 20-6 Card Detection Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10

Figure 20-7 Block Diagram for Logic and Command Interpreters . . . . . . . . . . . . . . . . . . 20-11

Figure 20-8 Command CRC Shift Register (SD_DAT Has a Similar Structure) . . . . . . . 20-12

Figure 20-9 Clock Tree for the MMC/SD Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12

Figure 20-10 System Clock Control Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13

Figure 21-1 Memory Stick Host Controller Simplified Block Diagram . . . . . . . . . . . . . . . 21-2

Figure 21-2 Memory Stick Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3

Figure 21-3 Memory Stick Interrupt Transfer State (BS0) Operation . . . . . . . . . . . . . . . . . 21-6

Figure 21-4 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8

Figure 21-5 Auto Command Function Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10

Figure 21-6 MSHC Module Serial Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11 xxx

MC9328MX1 Reference Manual

MOTOROLA

Figure 21-7 Memory Stick Bus Four State Access Protocol . . . . . . . . . . . . . . . . . . . . . . . 21-25

Figure 21-8 Write Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26

Figure 21-9 Read Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26

Figure 21-10 Two State Access Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-28

Figure 21-11 Write Packet Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29

Figure 21-12 Read Packet Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29

Figure 21-13 Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30

Figure 21-14 Bus State Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31

Figure 21-15 SCLK Extension for Data Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31

Figure 22-1 Pulse-Width Modulator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1

Figure 22-2 Audio Waveform Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2

Figure 23-1 Real-Time Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2

Figure 24-1 SDRAM Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2

Figure 24-2 Memory Bank Interleaving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13

Figure 24-3 CAS Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14

Figure 24-4 Precharge Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15

Figure 24-5 Row-to-Column Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15

Figure 24-6 Row Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16

Figure 24-7 Off-Page Single Read Timing Diagram (32-Bit Memory) . . . . . . . . . . . . . . . 24-20

Figure 24-8 On-Page Single Read Timing Diagram (32-Bit Memory) . . . . . . . . . . . . . . . 24-20

Figure 24-9 Off-Page Burst Read Timing Diagram (32-Bit Memory) . . . . . . . . . . . . . . . 24-21

Figure 24-10 On-Page Burst Read Timing Diagram (32-Bit Memory) . . . . . . . . . . . . . . . . 24-21

Figure 24-11 Off-Page Write Followed by On-Page Write Timing Diagram . . . . . . . . . . . 24-21

Figure 24-12 Off-Page Burst Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22

Figure 24-13 On-Page Burst Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22

Figure 24-14 Single Write Followed by On-Page Read Timing Diagram . . . . . . . . . . . . . . 24-22

Figure 24-15 Burst Write Followed by On-Page Read Timing Diagram. . . . . . . . . . . . . . . 24-23

Figure 24-16 Single Read Followed by On-Page Write Timing Diagram . . . . . . . . . . . . . . 24-23

Figure 24-17 Burst Read Followed by On-Page Write Timing Diagram. . . . . . . . . . . . . . . 24-23

Figure 24-18 Precharge Bank Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24

Figure 24-19 Precharge All Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24

Figure 24-20 Software Initiated Auto-Refresh Timing Diagram . . . . . . . . . . . . . . . . . . . . . 24-25

Figure 24-21 Set Mode Register State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26

Figure 24-22 Set Mode Register Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26

Figure 24-23 Load Command Register Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27

Figure 24-24 SyncFlash Program Mode State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27

Figure 24-25 SyncFlash Program Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28

Figure 24-26 SyncFlash Read Status Register Timing Diagram . . . . . . . . . . . . . . . . . . . . . 24-28

Figure 24-27 Hardware Refresh Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-32

MOTOROLA

List of Figures

xxxi

Figure 24-28 Hardware Refresh With Pending Bus Cycle Timing Diagram. . . . . . . . . . . . 24-33

Figure 24-29 Self-Refresh Entry Due to Low-Power Mode Timing Diagram. . . . . . . . . . . 24-34

Figure 24-30 Low-Power Mode Self-Refresh Exit Timing Diagram. . . . . . . . . . . . . . . . . . 24-34

Figure 24-31 Powerdown Mode Resulting From Reset with Refresh Disabled . . . . . . . . . 24-35

Figure 24-32 Powerdown Mode Entry Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-36

Figure 24-33 Powerdown Exit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-36

Figure 24-34 Clock Suspend Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-37

Figure 24-35 Single 64 Mbit (4M x 16) Connection Diagram (IAM = 1) . . . . . . . . . . . . . . 24-39

Figure 24-36 Single 64 Mbit (4M x 16 x 1) Connection Diagram (IAM = 0) . . . . . . . . . . . 24-40

Figure 24-37 Single 128 Mbit (8M x 16) Connection Diagram (IAM = 1) . . . . . . . . . . . . . 24-41

Figure 24-38 Single 128 Mbit (8M x 16) Connection Diagram (IAM = 0) . . . . . . . . . . . . . 24-42

Figure 24-39 Single 256 Mbit (16M x 16) Connection Diagram (IAM = 1) . . . . . . . . . . . . 24-43

Figure 24-40 Single 256 Mbit (16M x 16) Connection Diagram (IAM = 1) . . . . . . . . . . . . 24-44

Figure 24-41 Dual 64 Mbit (4M x 16 x 2) Connection Diagram (IAM = 1) . . . . . . . . . . . . 24-45

Figure 24-42 Dual 64 Mbit (4M x 16 x 2) Connection Diagram (IAM = 0) . . . . . . . . . . . . 24-46

Figure 24-43 Dual 128 Mbit (8M x 16 x 2) Connection Diagram (IAM = 1) . . . . . . . . . . . 24-47

Figure 24-44 Dual 128 Mbit (8M x 16 x 2) Connection Diagram (IAM = 0) . . . . . . . . . . . 24-48

Figure 24-45 Dual 256 Mbit (16M x 16 x 2) Connection Diagram (IAM = 1) . . . . . . . . . . 24-49

Figure 24-46 Dual 256 Mbit (16M x 16 x 2) Connection Diagram (IAM = 0) . . . . . . . . . . 24-50

Figure 24-47 Single 64 Mbit (2M x 32) Connection Diagram (IAM = 1) . . . . . . . . . . . . . . 24-51

Figure 24-48 Single 64 Mbit (2M x 32) Connection Diagram (IAM = 0) . . . . . . . . . . . . . . 24-52

Figure 24-49 Single 128 Mbit (4M x 32) Connection Diagram (IAM = 1) . . . . . . . . . . . . . 24-53

Figure 24-50 Single 128 Mbit (4M x 32) Connection Diagram (IAM = 0) . . . . . . . . . . . . . 24-54

Figure 24-51 Single 256 Mbit (8M x 32) Connection Diagram (IAM = 1) . . . . . . . . . . . . . 24-55

Figure 24-52 Single 256 Mbit (8M x 32) Connection Diagram (IAM = 0) . . . . . . . . . . . . . 24-56

Figure 24-53 SDRAM Power-On Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 24-57

Figure 24-54 Sync Flash Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-66

Figure 24-55 Single 64 Mbit SyncFlash Connection Diagram (IAM = 0). . . . . . . . . . . . . . 24-67

Figure 24-56 Dual 64 Mbit SyncFlash Connection Diagram (IAM = 0) . . . . . . . . . . . . . . . 24-68

Figure 24-57 SyncFlash Clock Suspend Timer Operation Timing Diagram . . . . . . . . . . . . 24-70

Figure 24-58 SyncFlash Powerdown Operation Timing Diagram . . . . . . . . . . . . . . . . . . . . 24-70

Figure 24-59 SyncFlash Deep Powerdown Operation Timing Diagram . . . . . . . . . . . . . . . 24-71

Figure 25-1 SIM Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1

Figure 25-2 SIM Clock Generator Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4

Figure 25-3 Transmit State Machine Operation Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6

Figure 25-4 Transmit Guard Time Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8

Figure 25-5 Transmit NACK Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8

Figure 25-6 SIM Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9

Figure 25-7 Receive State Machine Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11 xxxii

MC9328MX1 Reference Manual

MOTOROLA

Figure 25-8 Start Bit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11

Figure 25-9 Parity Bit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12

Figure 25-10 Framing Error Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12

Figure 25-11 Valid Initial Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13

Figure 25-12 Inverse Convention vs. Direct Convention. . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13

Figure 25-13 Two Methods of SmartCard Hookup to MC9328MX1 SIM Port . . . . . . . . . 25-15

Figure 25-14 Automatic Powerdown Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16

Figure 25-15 Cyclic Redundancy Check Circuit Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 25-17

Figure 25-16 Suggested T = 1, EMV, and Geldkate Compliant SIM Initialization. . . . . . . 25-53

Figure 26-1 General-Purpose Timers Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1

Figure 27-1 General Connections for a UART with a Modem . . . . . . . . . . . . . . . . . . . . . . 27-6

Figure 27-2 UART Block Diagram and Clock Generation Diagram . . . . . . . . . . . . . . . . . . 27-9

Figure 27-3 Transmitter FIFO Empty Interrupt Suppression Flow Chart . . . . . . . . . . . . . 27-11

Figure 27-4 Baud Rate Detection Protocol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-16

Figure 27-5 Majority Vote Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-52

Figure 27-6 Baud Rate Detection of Divisor = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-52

Figure 28-1 USB Device Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3

Figure 28-2 USB Module Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5

Figure 29-1 I

2

C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2

Figure 29-2 I

2

C Standard Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3

Figure 29-3 Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4

Figure 29-4 Synchronized Clock SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4

Figure 29-5 Flow Chart of Typical I

2

C Interrupt Routine . . . . . . . . . . . . . . . . . . . . . . . . . 29-17

Figure 30-1 MC9328MX1 Input/Output Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2

Figure 30-2 SSI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3

Figure 30-3 SSI Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4

Figure 30-4 SSI Transmit Clock Generator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 30-5

Figure 30-5 SSI Transmit Frame Sync Generator Block Diagram . . . . . . . . . . . . . . . . . . . 30-5

Figure 30-6 Transmit Data Path (TXBIT0 = 0, TSHFD = 0). . . . . . . . . . . . . . . . . . . . . . . 30-10

Figure 30-7 Transmit Data Path (TXBIT0 = 0, TSHFD = 1). . . . . . . . . . . . . . . . . . . . . . . 30-11

Figure 30-8 Transmit Data Path (TXBIT0 = 1, TSHFD = 0). . . . . . . . . . . . . . . . . . . . . . . 30-11

Figure 30-9 Transmit Data Path (TXBIT0 = 1, TSHFD = 1). . . . . . . . . . . . . . . . . . . . . . . 30-11

Figure 30-10 Receive Data Path (RXBIT0 = 0, RSHFD = 0) . . . . . . . . . . . . . . . . . . . . . . . 30-14

Figure 30-11 Receive Data Path (RXBIT0 = 0, RSHFD = 1) . . . . . . . . . . . . . . . . . . . . . . . 30-14

Figure 30-12 Receive Data Path (RXBIT0 = 1, RSHFD = 0) . . . . . . . . . . . . . . . . . . . . . . . 30-14

Figure 30-13 Receive Data Path (RXBIT0 = 1, RSHFD = 1) . . . . . . . . . . . . . . . . . . . . . . . 30-15

Figure 30-14 Asynchronous (SYN = 0) SSI Configurations—Continuous Clock. . . . . . . . 30-36

Figure 30-15 Synchronous SSI Configurations—Continuous and Gated Clock . . . . . . . . . 30-37

Figure 30-16 Serial Clock and Frame Sync Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-37

MOTOROLA

List of Figures

xxxiii

Figure 30-17 Normal Mode Timing—Continuous Clock . . . . . . . . . . . . . . . . . . . . . . . . . . 30-40

Figure 30-18 Normal Mode Timing—Gated Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-40

Figure 30-19 Network Mode Timing—Continuous Clock . . . . . . . . . . . . . . . . . . . . . . . . . 30-43

Figure 30-20 Rising Edge Clocking with Falling Edge Latching . . . . . . . . . . . . . . . . . . . . 30-44

Figure 30-21 Falling Edge Clocking with Rising Edge Latching . . . . . . . . . . . . . . . . . . . . 30-44

Figure 31-1 CSI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2

Figure 31-2 Statistic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-13

Figure 31-3 Statistic Blocks Example for 288 x 216 Pixels Image Size . . . . . . . . . . . . . . 31-14

Figure 31-4 Full Resolution Statistic Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-15

Figure 31-5 Auto Focus Spread . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16

Figure 32-1 Top Level of Circuitry for Port X, Pin [i]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2

Figure 32-2 GPIO Module Block Diagram for Port X, Pin [i]. . . . . . . . . . . . . . . . . . . . . . . 32-4 xxxiv

MC9328MX1 Reference Manual

MOTOROLA

Table 1-1

Table 2-1

Table 2-2

Table 3-1

Table 3-2

Table 4-1

Table 4-2

Table 4-3

Table 5-1

Table 6-1

Table 6-2

Table 6-3

Table 7-1

Table 7-2

Table 7-3

Table 7-4

Table 7-5

Table 7-6

Table 7-7

MC9328MX1 Reference Manual Revision History Rev. 1 . . . . . . . . . . . . . . . . . liv

Endpoint Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

MC9328MX1 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

MC9328MX1 Signal Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

MCU Memory Space (Physical Addresses) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

MC9328MX1 Internal Registers Sorted by Address . . . . . . . . . . . . . . . . . . . . . 3-6

ARM920T Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

ARM Thumb Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Register Availability by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

ETM Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Reset Module Pin and Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

RSR Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Hardware Reset Source Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

R-AHB to IP Bus Interface Operation (Big Endian—Read Operation) . . . . . . . 7-4

R-AHB to IP Bus Interface Operation (Big Endian—Write Operation) . . . . . . 7-5

Table 7-8

R-AHB to IP Bus Interface Operation (Little Endian—Read Operation) . . . . . 7-7

R-AHB to IP Bus Interface Operation (Little Endian—Write Operation) . . . . . 7-8

AIPI Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

Peripheral Address MODULE_EN Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

AIPI1 Peripheral Size Register 0 and AIPI2 Peripheral Size Register 0 Description . . . . . . . . . . . . . . . . . . . 7-12

AIPI1 Peripheral Size Register 1 and AIPI2 Peripheral Size Register 1 Description . . . . . . . . . . . . . . . . . . . 7-13

Table 7-9 PSR Data Bus Size Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14

Table 7-10 Peripheral Access Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15

Table 7-11 Peripheral Control Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

Table 7-12 Time-Out Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17

Table 7-13 Core and 8-Bit Peripheral Register Content After Code Execution . . . . . . . . . 7-18

Table 7-14 Core and 16-Bit Peripheral Register Content (Little Endian). . . . . . . . . . . . . . 7-18

Table 7-15 Core and 16-Bit Peripheral Register Content (Big Endian) . . . . . . . . . . . . . . . 7-19

Table 7-16 Core and 32-bit Peripheral Register Content (Little Endian) . . . . . . . . . . . . . . 7-20

Table 7-17 Core and 32-bit Peripheral Register Content (Big Endian) . . . . . . . . . . . . . . . 7-20

Table 8-1 System Control Module Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . 8-1

Table 8-2 Silicon ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

MOTOROLA

List of Tables

xxxv

Table 8-3

Table 8-4

Table 8-5

Table 8-6

Table 9-1

Table 9-2

Table 9-3

Function Multiplexing Control Register Description . . . . . . . . . . . . . . . . . . . . . 8-3

Global Peripheral Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

Global Clock Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

System Boot Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

Bootstrap Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

Definition of COUNT/MODE Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

Program Breakdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

Table 9-4

Table 9-5

Resulting B-Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

Read/Write Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

Table 10-1 Interrupt Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

Table 10-2 AITC Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

Table 10-3 Register Field Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

Table 10-4 Interrupt Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

Table 10-5 Normal Interrupt Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

Table 10-6 Interrupt Enable Number Register Description . . . . . . . . . . . . . . . . . . . . . . . 10-10

Table 10-7 Interrupt Disable Number Register Description . . . . . . . . . . . . . . . . . . . . . . . 10-11

Table 10-8 Interrupt Enable Register High Description . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12

Table 10-9 Interrupt Enable Register Low Description . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13

Table 10-10 Interrupt Type Register High Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14

Table 10-11 Interrupt Type Register Low Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15

Table 10-12 Normal Interrupt Priority Level Register 7 Description . . . . . . . . . . . . . . . . . 10-16

Table 10-13 Normal Interrupt Priority Level Register 6 Description . . . . . . . . . . . . . . . . . 10-17

Table 10-14 Normal Interrupt Priority Level Register 5 Description . . . . . . . . . . . . . . . . . 10-18

Table 10-15 Normal Interrupt Priority Level Register 4 Description . . . . . . . . . . . . . . . . . 10-19

Table 10-16 Normal Interrupt Priority Level Register 3 Description . . . . . . . . . . . . . . . . . 10-20

Table 10-17 Normal Interrupt Priority Level Register 2 Description . . . . . . . . . . . . . . . . . 10-21

Table 10-18 Normal Interrupt Priority Level Register 1 Description . . . . . . . . . . . . . . . . . 10-22

Table 10-19 Normal Interrupt Priority Level Register 0 Description . . . . . . . . . . . . . . . . . 10-23

Table 10-20 Normal Interrupt Vector and Status Register Description . . . . . . . . . . . . . . . 10-24

Table 10-21 Fast Interrupt Vector and Status Register Description . . . . . . . . . . . . . . . . . . 10-25

Table 10-22 Interrupt Source Register High Description . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26

Table 10-23 Interrupt Source Register Low Description . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27

Table 10-24 Interrupt Force Register High Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28

Table 10-25 Interrupt Force Register Low Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29

Table 10-26 Normal Interrupt Pending Register High Description . . . . . . . . . . . . . . . . . . 10-30

Table 10-27 Normal Interrupt Pending Register Low Description. . . . . . . . . . . . . . . . . . . 10-31

Table 10-28 Fast Interrupt Pending Register High Description . . . . . . . . . . . . . . . . . . . . . 10-32

Table 10-29 Fast Interrupt Pending Register Low Description . . . . . . . . . . . . . . . . . . . . . 10-33

Table 10-30 Typical Hardware Accelerated Normal Interrupt Entry Sequence . . . . . . . . . 10-35 xxxvi

MC9328MX1 Reference Manual

MOTOROLA

Table 10-31 Typical Fast Interrupt Entry Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35

Table 11-1 Chip Select Address Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

Table 11-2 EIM Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

Table 11-3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

Table 11-4 EIM Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10

Table 11-5 Chip Select Control Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13

Table 11-6 Chip Select Wait State and Burst Delay Encoding. . . . . . . . . . . . . . . . . . . . . 11-18

Table 11-7 EIM Configuration Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21

Table 12-1 Clock Controller Module Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

Table 12-2 SDRAM/SyncFlash Operation During Power Modes . . . . . . . . . . . . . . . . . . . 12-4

Table 12-3 Power Management in the Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5

Table 12-4 PLL and Clock Controller Module Register Memory Map . . . . . . . . . . . . . . . 12-5

Table 12-5 Clock Source Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6

Table 12-6 Clock Sources for Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

Table 12-7 Peripheral Clock Divider Register Description . . . . . . . . . . . . . . . . . . . . . . . . 12-8

Table 12-8 Sample Frequency Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9

Table 12-9 MCU PLL Control Register 0 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

Table 12-10 MCU PLL and System Clock Control Register 1 Description . . . . . . . . . . . . 12-11

Table 12-11 System PLL Multiplier Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11

Table 12-12 System PLL Control Register 0 Description . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

Table 12-13 System PLL Control Register 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . 12-13

Table 13-1 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3

Table 13-2 DMA Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4

Table 13-3 DMA Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8

Table 13-4 DMA Interrupt Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9

Table 13-5 DMA Interrupt Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10

Table 13-6 DMA Burst Time-Out Status Register Description . . . . . . . . . . . . . . . . . . . . 13-11

Table 13-7 DMA Request Time-Out Status Register Description . . . . . . . . . . . . . . . . . . 13-12

Table 13-8 DMA Transfer Error Status Register Description . . . . . . . . . . . . . . . . . . . . . 13-13

Table 13-9 DMA Buffer Overflow Status Register Description. . . . . . . . . . . . . . . . . . . . 13-14

Table 13-10 DMA Burst Time-Out Control Register Description . . . . . . . . . . . . . . . . . . . 13-15

Table 13-11 W-Size Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16

Table 13-12 X-Size Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17

Table 13-13 Y-Size Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18

Table 13-14 Channel Source Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . 13-19

Table 13-15 Channel Destination Address Registers Description . . . . . . . . . . . . . . . . . . . 13-20

Table 13-16 Channel Count Registers Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21

Table 13-17 Channel Control Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23

Table 13-18 DMA_EOBO_CNT and DMA_EOBI_CNT Settings . . . . . . . . . . . . . . . . . . 13-24

MOTOROLA

List of Tables

xxxvii

Table 13-19 Channel Request Source Select Registers Description. . . . . . . . . . . . . . . . . . 13-25

Table 13-20 Channel Burst Length Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . 13-26

Table 13-21 Channel Request Time-Out Registers Description . . . . . . . . . . . . . . . . . . . . . 13-28

Table 13-22 Channel 0 Bus Utilization Control Registers Description . . . . . . . . . . . . . . . 13-29

Table 13-23 DMA Request Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30

Table 14-1 Watchdog Timer I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5

Table 14-2 Watchdog Control Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6

Table 14-3 Watchdog Service Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8

Table 14-4 Watchdog Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8

Table 15-1 ASP Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2

Table 15-2 Simplified ASP Signal Path Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3

Table 15-3 Pen ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

Table 15-4 Pen ADC Maximum Sample Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5

Table 15-5 Output Data Rate Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6

Table 15-6 ASP Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8

Table 15-7 Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9

Table 15-8 Pen A/D Sample Rate Control Register Description . . . . . . . . . . . . . . . . . . . 15-11

Table 15-9 Compare Control Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12

Table 15-10 Interrupt Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13

Table 15-11 Interrupt/Error Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14

Table 15-12 Pen Sample FIFO Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16

Table 15-13 Clock Divide Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16

Table 15-14 ASP FIFO Pointer Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17

Table 16-1 CLK_CONTROL Register Settings for Synchronization . . . . . . . . . . . . . . . . 16-4

Table 16-2 Bluetooth Clocks and Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5

Table 16-3 Bluetooth Core Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7

Table 16-4 Packet Types and FEC/CRC Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9

Table 16-5 Writing Sequence for Encryption Engine Initialization . . . . . . . . . . . . . . . . . 16-10

Table 16-6 Functions Using the Bit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12

Table 16-7 Hop Selection Co-Processor Writing Sequence . . . . . . . . . . . . . . . . . . . . . . . 16-13

Table 16-8 Bluetooth Pin Mapping for Various Radio Interfaces . . . . . . . . . . . . . . . . . . 16-14

Table 16-9 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20

Table 16-10 BTA Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21

Table 16-11 BTA Module Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23

Table 16-12 Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-26

Table 16-13 Status Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28

Table 16-14 Packet Header Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-29

Table 16-15 Payload Header Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30

Table 16-16 Native Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-31 xxxviii

MC9328MX1 Reference Manual

MOTOROLA

Table 16-17 Estimated Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32

Table 16-18 Offset Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-33

Table 16-19 Native Clock Low Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-34

Table 16-20 Native Clock High Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-35

Table 16-21 Estimated Clock Low Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 16-36

Table 16-22 Estimated Clock High Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 16-37

Table 16-23 Offset Clock Low Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-38

Table 16-24 Offset Clock High Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-39

Table 16-25 HECCRC Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-40

Table 16-26 White Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-41

Table 16-27 Encryption Control X13 Register Description . . . . . . . . . . . . . . . . . . . . . . . . 16-42

Table 16-28 Correlation Time Setup Register Description. . . . . . . . . . . . . . . . . . . . . . . . . 16-43

Table 16-29 Correlation Time Stamp Register Description . . . . . . . . . . . . . . . . . . . . . . . . 16-44

Table 16-30 RF GPO Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-45

Table 16-31 PWM Received Signal Strength Indicator Register Description (MC13180) 16-46

Table 16-32 Time A & B Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-47

Table 16-33 Time C & D Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-48

Table 16-34 PWM TX Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-49

Table 16-35 RF Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-50

Table 16-36 RF Status Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-52

Table 16-37 RX Time Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-54

Table 16-38 TX Time Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-55

Table 16-39 Bluetooth Application Timer Register Description . . . . . . . . . . . . . . . . . . . . 16-56

Table 16-40 Threshold Register Description (MC13180) . . . . . . . . . . . . . . . . . . . . . . . . . 16-57

Table 16-41 Threshold Register Description (SiliconWave) . . . . . . . . . . . . . . . . . . . . . . . 16-58

Table 16-42 Signal Energy Levels and Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . 16-58

Table 16-43 Correlation Max Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-59

Table 16-44 Synch Word 0 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-60

Table 16-45 Synch Word 1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-61

Table 16-46 Synch Word 2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-62

Table 16-47 Synch Word 3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-63

Table 16-48 Buf Word 0 (LW0) Register to Buf Word 31 (LW7) Register Description . . 16-63

Table 16-49 Bit Buffer Registers Numbers and Addresses . . . . . . . . . . . . . . . . . . . . . . . . 16-64

Table 16-50 Wake-Up 1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-65

Table 16-51 Wake-Up 2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-66

Table 16-52 Wake-Up Delta4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-67

Table 16-53 Wake-Up 4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-68

Table 16-54 WakeUp Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-69

Table 16-55 Wake-Up Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-70

MOTOROLA

List of Tables

xxxix

Table 16-56 Wake-Up Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-71

Table 16-57 Clock Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-72

Table 16-58 SPI Word0 Register Description (MC13180). . . . . . . . . . . . . . . . . . . . . . . . . 16-73

Table 16-59 SPI Word0 Register Description (SiliconWave) . . . . . . . . . . . . . . . . . . . . . . 16-74

Table 16-60 SPI Word1 Register Description (MC13180). . . . . . . . . . . . . . . . . . . . . . . . . 16-74

Table 16-61 SPI Word1 Register Description (SiliconWave) . . . . . . . . . . . . . . . . . . . . . . 16-75

Table 16-62 SPI Word2 Register Description (MC13180). . . . . . . . . . . . . . . . . . . . . . . . . 16-75

Table 16-63 SPI Word2 Register Description (SiliconWave) . . . . . . . . . . . . . . . . . . . . . . 16-75

Table 16-64 SPI Word3 Register Description (MC13180). . . . . . . . . . . . . . . . . . . . . . . . . 16-76

Table 16-65 SPI Word3 Register Description (SiliconWave) . . . . . . . . . . . . . . . . . . . . . . 16-76

Table 16-66 SPI Write Address Register Description (MC13180). . . . . . . . . . . . . . . . . . . 16-77

Table 16-67 SPI Write Address Register Description (SiliconWave) . . . . . . . . . . . . . . . . 16-78

Table 16-68 SPI Read Address Register Description (MC13180) . . . . . . . . . . . . . . . . . . . 16-78

Table 16-69 SPI Read Address Register Description (SiliconWave) . . . . . . . . . . . . . . . . . 16-79

Table 16-70 SPI Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-80

Table 16-71 SPI Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-81

Table 16-72 Hop 0 (Frequency In) Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 16-82

Table 16-73 Hop 1 (Frequency In) Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 16-83

Table 16-74 Hop 2 (Frequency In) Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 16-83

Table 16-75 Hop 3 (Frequency In) Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 16-84

Table 16-76 Hop 4 (Frequency In) Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 16-85

Table 16-77 Hop Frequency Out Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-85

Table 16-78 Interrupt Vector Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-86

Table 16-79 Synchronization Metric Register Description. . . . . . . . . . . . . . . . . . . . . . . . . 16-87

Table 16-80 Synchronize Frequency Carrier Register Description . . . . . . . . . . . . . . . . . . 16-88

Table 16-81 Word Reverse Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-89

Table 16-82 Byte Reverse Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-90

Table 17-1 MMA Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5

Table 17-2 MMA MAC Module Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6

Table 17-3 MMA MAC Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7

Table 17-4 MMA MAC Multiply Counter Register Description . . . . . . . . . . . . . . . . . . . . 17-9

Table 17-5 MMA MAC Accumulate Counter Register Description . . . . . . . . . . . . . . . . 17-10

Table 17-6 MMA MAC Interrupt Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11

Table 17-7 MMA MAC Interrupt Mask Register Description . . . . . . . . . . . . . . . . . . . . . 17-11

Table 17-8 MMA MAC FIFO Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12

Table 17-9 MMA MAC FIFO Status Register Description . . . . . . . . . . . . . . . . . . . . . . . 17-13

Table 17-10 MMA MAC Burst Count Register Description . . . . . . . . . . . . . . . . . . . . . . . 17-14

Table 17-11 MMA MAC Bit Select Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 17-15

Table 17-12 MMA MAC X Base Address Register Description . . . . . . . . . . . . . . . . . . . . 17-16 xl

MC9328MX1 Reference Manual

MOTOROLA

Table 17-13 MMA MAC X Index Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16

Table 17-14 MMA MAC X Length Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 17-17

Table 17-15 MMA MAC X Modify Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 17-18

Table 17-16 MMA MAC X Increment Register Description . . . . . . . . . . . . . . . . . . . . . . . 17-19

Table 17-17 MMA MAC X Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19

Table 17-18 MMA MAC Y Base Address Register Description . . . . . . . . . . . . . . . . . . . . 17-20

Table 17-19 MMA MAC Y Index Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20

Table 17-20 MMA MAC Y Length Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 17-21

Table 17-21 MMA MAC Y Modify Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 17-22

Table 17-22 MMA MAC Y Increment Register Description . . . . . . . . . . . . . . . . . . . . . . . 17-23

Table 17-23 MMA MAC Y Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23

Table 17-24 DCT/iDCT Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24

Table 17-25 DCT/iDCT Version Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25

Table 17-26 DCT/iDCT IRQ Enable Register Description . . . . . . . . . . . . . . . . . . . . . . . . 17-26

Table 17-27 DCT/iDCT IRQ Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 17-27

Table 17-28 DCT/iDCT Source Data Address Register Description . . . . . . . . . . . . . . . . . 17-28

Table 17-29 DCT/iDCT Destination Data Address Register Description . . . . . . . . . . . . . 17-28

Table 17-30 DCT/iDCT X-Offset Address Register Description . . . . . . . . . . . . . . . . . . . . 17-29

Table 17-31 DCT/iDCT Y-Offset Address Register Description . . . . . . . . . . . . . . . . . . . . 17-30

Table 17-32 DCT/iDCT XY Count Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . 17-30

Table 17-33 DCT/iDCT Skip Address Register Description . . . . . . . . . . . . . . . . . . . . . . . 17-31

Table 17-34 DCT/iDCT Data FIFO Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 17-32

Table 18-1 SPI 1 and SPI 2 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1

Table 18-2 SPI Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4

Table 18-3 SPI Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5

Table 18-4 SPI 1 Rx Data Register and SPI 2 Rx Data Register Description . . . . . . . . . . 18-6

Table 18-5 SPI 1 Tx Data Register and SPI 2 Tx Data Register Description. . . . . . . . . . . 18-7

Table 18-6 SPI 1 Control Register and SPI 2 Control Register Description . . . . . . . . . . . 18-8

Table 18-7 SPI 1 Interrupt Control/Status Register and SPI 2 Interrupt Control/Status Register Description . . . . . . . . . . . . . 18-10

Table 18-8 SPI 1 Test Register and SPI 2 Test Register Description . . . . . . . . . . . . . . . . 18-12

Table 18-9 SPI 1 Sample Period Control Register and SPI 2 Sample Period Control Register Description . . . . . . . . . . . . . . 18-13

Table 18-10 SPI 1 DMA Control Register and SPI 2 DMA Control Register Description . . . . . . . . . . . . . . . . . . . . . 18-14

Table 18-11 SPI 1 Soft Reset Register and SPI 2 Soft Reset Register Description . . . . . . 18-15

Table 19-1 Supported Panel Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1

Table 19-2 Display Mapping in 12 bpp, CSTN Panel, Little Endian . . . . . . . . . . . . . . . . . 19-6

Table 19-3 Display Mapping in 12 bpp, CSTN Panel, Little Endian . . . . . . . . . . . . . . . . . 19-6

Table 19-4 Display Mapping in 12 bpp, CSTN Panel, Big Endian . . . . . . . . . . . . . . . . . . 19-7

MOTOROLA

List of Tables

xli

Table 19-5 Gray Palette Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10

Table 19-6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11

Table 19-7 TFT Color Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15

Table 19-8 LCDC Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18

Table 19-9 Screen Start Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20

Table 19-11 Virtual Page Width Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21

Table 19-10 Size Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21

Table 19-12 Panel Configuration Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22

Table 19-13 Horizontal Configuration Register Description . . . . . . . . . . . . . . . . . . . . . . . 19-24

Table 19-14 Vertical Configuration Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 19-25

Table 19-15 Panning Offset Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26

Table 19-16 LCD Cursor X Position Register Description. . . . . . . . . . . . . . . . . . . . . . . . . 19-27

Table 19-17 LCD Cursor Width Height and Blink Register Description . . . . . . . . . . . . . . 19-28

Table 19-18 LCD Color Cursor Mapping Register Description . . . . . . . . . . . . . . . . . . . . . 19-29

Table 19-19 Sharp Configuration 1 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . 19-30

Table 19-20 PWM Contrast Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 19-32

Table 19-21 Refresh Mode Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 19-33

Table 19-22 DMA Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-34

Table 19-23 Interrupt Configuration Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 19-35

Table 19-24 Interrupt Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-36

Table 19-25 Four Bits/Pixel Gray-Scale Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-37

Table 19-26 Four Bits/Pixel Passive Matrix Color Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 19-38

Table 19-27 Eight Bits/Pixel Passive Matrix Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . 19-38

Table 19-28 Four Bits/Pixel Active Matrix Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 19-39

Table 19-29 Eight Bits/Pixel Active Matrix Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 19-39

Table 20-1 MMC/SD Card Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3

Table 20-2 MMC/SD Card Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3

Table 20-3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5

Table 20-4 Multimedia Controller Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . 20-13

Table 20-5 MMC/SD Clock Control Register Description. . . . . . . . . . . . . . . . . . . . . . . . 20-15

Table 20-6 MMC/SD Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16

Table 20-7 MMC/SD Clock Rate Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19

Table 20-8 MMC/SD Command and Data Control Register Description . . . . . . . . . . . . 20-20

Table 20-9 MMC/SD Response Time-Out Register Description . . . . . . . . . . . . . . . . . . . 20-22

Table 20-10 MMC/SD Read Time-Out Register Description . . . . . . . . . . . . . . . . . . . . . . 20-22

Table 20-11 MMC/SD Block Length Register Description . . . . . . . . . . . . . . . . . . . . . . . . 20-23

Table 20-12 MMC/SD Number of Blocks Register Description . . . . . . . . . . . . . . . . . . . . 20-24

Table 20-13 MMC/SD Revision Number Register Description . . . . . . . . . . . . . . . . . . . . . 20-25

Table 20-14 MMC/SD Interrupt Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . 20-26 xlii

MC9328MX1 Reference Manual

MOTOROLA

Table 20-15 Interrupt Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-27

Table 20-16 MMC/SD Command Number Register Description. . . . . . . . . . . . . . . . . . . . 20-29

Table 20-17 MMC/SD Higher Argument Register Description . . . . . . . . . . . . . . . . . . . . . 20-30

Table 20-18 MMC/SD Lower Argument Register Description . . . . . . . . . . . . . . . . . . . . . 20-30

Table 20-19 MMC/SD Response FIFO Register Description . . . . . . . . . . . . . . . . . . . . . . 20-31

Table 20-20 MMC/SD Buffer Access Register Description. . . . . . . . . . . . . . . . . . . . . . . . 20-32

Table 20-21 Structure of Command Data Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-46

Table 20-22 Card Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-49

Table 20-23 SD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-52

Table 20-24 Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-56

Table 20-25 Commands for MMC/SD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-56

Table 20-26 R1 Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-61

Table 20-27 R2 Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-61

Table 20-28 R3 Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-61

Table 20-29 R4 Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-62

Table 20-30 R4b Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-62

Table 20-31 R5 Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-62

Table 20-32 R6 Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-63

Table 21-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4

Table 21-2 MSHC Module Interrupt Sources Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5

Table 21-3 Interrupt Detect Capability on Power Save Mode . . . . . . . . . . . . . . . . . . . . . . 21-8

Table 21-4 Serial Clock Divider Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11

Table 21-5 MSHC Module DMA Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . 21-12

Table 21-6 MSHC Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12

Table 21-7 Memory Stick Command Register Description . . . . . . . . . . . . . . . . . . . . . . . 21-13

Table 21-8 Memory Stick Control/Status Register Description . . . . . . . . . . . . . . . . . . . . 21-14

Table 21-9 Memory Stick Transmit FIFO Data Register Description . . . . . . . . . . . . . . . 21-16

Table 21-10 Memory Stick Receive FIFO Data Register Description . . . . . . . . . . . . . . . . 21-17

Table 21-11 Memory Stick Interrupt Control/Status Register Description . . . . . . . . . . . . 21-17

Table 21-12 Memory Stick Parallel Port Control/Data Register Description. . . . . . . . . . . 21-19

Table 21-13 Memory Stick Control 2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . 21-20

Table 21-14 Memory Stick Auto Command Register Description. . . . . . . . . . . . . . . . . . . 21-21

Table 21-15 Memory Stick FIFO Access Error Control/Status Register Description . . . . 21-22

Table 21-16 Memory Stick Serial Clock Divider Register Description . . . . . . . . . . . . . . . 21-23

Table 21-17 Memory Stick DMA Request Control Register Description . . . . . . . . . . . . . 21-24

Table 21-18 Serial Interface Signal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-25

Table 21-19 Four State Access Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-25

Table 21-20 Write Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26

Table 21-21 Read Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27

MOTOROLA

List of Tables

xliii

Table 21-22 TPC Code Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27

Table 21-23 Bus State in Two State Access Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29

Table 21-24 Two State Access Mode Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30

Table 22-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2

Table 22-2 PWM Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3

Table 22-3 PWM Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4

Table 22-4 HCTR and BCTR Bit Swapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6

Table 22-5 PWM Sample Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6

Table 22-6 PWM Period Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7

Table 22-7 PWM Counter Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8

Table 23-1 Sampling Timer Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3

Table 23-2 RTC Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4

Table 23-3 RTC Days Counter Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5

Table 23-4 RTC Hours and Minutes Counter Register Description . . . . . . . . . . . . . . . . . . 23-5

Table 23-5 RTC Seconds Counter Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6

Table 23-6 RTC Day Alarm Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7

Table 23-7 RTC Hours and Minutes Alarm Register Description . . . . . . . . . . . . . . . . . . . 23-8

Table 23-8 RTC Seconds Alarm Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9

Table 23-9 RTC Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10

Table 23-10 RTC Interrupt Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11

Table 23-11 RTC Interrupt Enable Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13

Table 23-12 Stopwatch Minutes Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-15

Table 24-1 AHB Bus and Internal Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4

Table 24-2 SDRAM Interface Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4

Table 24-3 SDRAM Interface Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5

Table 24-4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7

Table 24-5 SDRAM Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8

Table 24-6 SDRAM Array Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8

Table 24-7 SDRAM 0 Control Register and SDRAM 1 Control Register Description . . . 24-9

Table 24-8 Settings for SREFR Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13

Table 24-9 SDRAM Reset Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16

Table 24-10 Miscellaneous Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-17

Table 24-11 SDRAM and SyncFlash Command Encoding . . . . . . . . . . . . . . . . . . . . . . . . 24-18

Table 24-12 JEDEC Standard Single Data Rate SDRAMs . . . . . . . . . . . . . . . . . . . . . . . . 24-29

Table 24-13 Address Multiplexing by Column Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-30

Table 24-14 MC9328MX1 to SDRAM Interface Connections . . . . . . . . . . . . . . . . . . . . . 24-30

Table 24-15 Single 4M x 16 Control Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-39

Table 24-16 Single 4M x 16 Control Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-40

Table 24-17 Single 8M x 16 Control Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-41 xliv

MC9328MX1 Reference Manual

MOTOROLA

Table 24-18 Single 8M x 16 Control Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-42

Table 24-19 Single 16M x16 Control Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-43

Table 24-20 Single 16M x16 Control Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-44

Table 24-21 Dual 64 Mbit (4M x 16 x 2) Control Register Values (IAM = 1) . . . . . . . . . 24-45

Table 24-22 Dual 64 Mbit (4M x 16 x 2) Control Register Values (IAM = 0) . . . . . . . . . 24-46

Table 24-23 Dual 128 Mbit (8M x 16 x 2) Control Register Values (IAM = 1) . . . . . . . . 24-47

Table 24-24 Dual 128 Mbit (8M x 16 x 2) Control Register Values (IAM = 0) . . . . . . . . 24-48

Table 24-25 Dual 256 Mbit (16M x 16 x 2) Control Register Values (IAM = 1) . . . . . . . 24-49

Table 24-26 Dual 256 Mbit (16M x 16 x 2) Control Register Values (IAM = 0) . . . . . . . 24-50

Table 24-27 Single 64 Mbit (2M x 32) Control Register Values (IAM = 1) . . . . . . . . . . . 24-51

Table 24-28 Single 64 Mbit (2M x 32) Control Register Values . . . . . . . . . . . . . . . . . . . . 24-52

Table 24-29 Single 128 Mbit (4M x 32) Control Register Values (IAM = 1) . . . . . . . . . . 24-53

Table 24-30 Single 128 Mbit (4M x 32) Control Register Values (IAM = 0) . . . . . . . . . . 24-54

Table 24-31 Single 256 Mbit (8M x 32) Control Register Values (IAM = 1) . . . . . . . . . . 24-55

Table 24-32 Single 256 Mbit (8M x 32) Control Register Values (IAM = 0) . . . . . . . . . . 24-56

Table 24-33 4M x 16 Memory Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-58

Table 24-34 8M x 16 Memory Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-59

Table 24-35 16M x 16 Memory Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-59

Table 24-36 2M x 32 Memory Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-59

Table 24-37 4M x 32 Memory Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-59

Table 24-38 8M x 32 Memory Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-59

Table 24-39 MC9328MX1 SDRAM Memory Configuration . . . . . . . . . . . . . . . . . . . . . . 24-60

Table 24-40 256 Mbit SDRAM Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-61

Table 24-41 256 Mbit SDRAM Mode Register Description . . . . . . . . . . . . . . . . . . . . . . . 24-61

Table 24-42 256 Mbit SDRAM Mode Register with Values . . . . . . . . . . . . . . . . . . . . . . . 24-62

Table 24-43 MC9328MX1 Address Calculation for Given Mode Register Values . . . . . . 24-62

Table 24-44 64 Mbit SDRAM Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-63

Table 24-45 64 Mbit SDRAM Mode Register Description . . . . . . . . . . . . . . . . . . . . . . . . 24-63

Table 24-46 64 Mbit SDRAM Mode Register with Values . . . . . . . . . . . . . . . . . . . . . . . . 24-64

Table 24-47 MC9328MX1 Address Calculation for Given Mode Register Value. . . . . . . 24-64

Table 24-48 SDRAM Memory Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-65

Table 24-49 Single 4M x 16 SyncFlash Control Register Values . . . . . . . . . . . . . . . . . . . 24-67

Table 24-50 Dual 4M x 16 SyncFlash Control Register Values (IAM = 0) . . . . . . . . . . . . 24-67

Table 24-51 SyncFlash Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-69

Table 25-1 SIM Transmitter Interrupt Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2

Table 25-2 SIM Receiver Interrupt Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3

Table 25-3 SIM Port Control Interrupt Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3

Table 25-4 SIM Port Control Interrupt Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3

Table 25-5 SIM Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18

MOTOROLA

List of Tables

xlv

Table 25-6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19

Table 25-7 SSI Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19

Table 25-8 Register Field Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20

Table 25-9 Port Control Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22

Table 25-10 Control Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23

Table 25-11 Receive Threshold Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-26

Table 25-12 Transmit/Receive Enable Register Description . . . . . . . . . . . . . . . . . . . . . . . 25-26

Table 25-13 Transmit Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27

Table 25-14 Receive Status Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-29

Table 25-15 Interrupt Mask Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-31

Table 25-16 Port Transmit Buffer Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-32

Table 25-17 Receive Buffer Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-33

Table 25-18 Port Detect Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-34

Table 25-19 Transmit Threshold Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-35

Table 25-20 Transmit Guard Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . 25-36

Table 25-21 Open-Drain Configuration Control Register Description. . . . . . . . . . . . . . . . 25-37

Table 25-22 Reset Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-38

Table 25-23 Character Wait Timer Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 25-39

Table 25-24 General Purpose Counter Register Description . . . . . . . . . . . . . . . . . . . . . . . 25-40

Table 25-25 Divisor Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-41

Table 25-26 Configuring the SIM for Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-41

Table 25-27 Configuring the SIM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-42

Table 25-28 Configuring the SIM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-43

Table 25-29 Configuring the SIM General Purpose Counter . . . . . . . . . . . . . . . . . . . . . . . 25-44

Table 25-30 Configuring the SIM Linear Redundancy Check Block. . . . . . . . . . . . . . . . . 25-44

Table 25-31 Configuring the SIM Cyclic Redundancy Check Block. . . . . . . . . . . . . . . . . 25-45

Table 26-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2

Table 26-2 GP Timers Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3

Table 26-3 Timer 1 and 2 Control Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4

Table 26-4 Timer 1 and 2 Prescaler Registers Description. . . . . . . . . . . . . . . . . . . . . . . . . 26-5

Table 26-5 Timer 1 and 2 Compare Registers Description. . . . . . . . . . . . . . . . . . . . . . . . . 26-6

Table 26-6 Timer 1 and 2 Capture Registers Description. . . . . . . . . . . . . . . . . . . . . . . . . . 26-7

Table 26-7 Timer 1 and 2 Counter Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . 26-8

Table 26-8 Timer 1 and 2 Status Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9

Table 27-1 UART Module Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2

Table 27-2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3

Table 27-3 Interrupts and DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4

Table 27-4 RTS Edge Triggered Interrupt Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6

Table 27-5 DTR Edge Triggered Interrupt Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 xlvi

MC9328MX1 Reference Manual

MOTOROLA

Table 27-6 IDLE Detection Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12

Table 27-7 Majority Vote Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-14

Table 27-8 Baud Rate Automatic Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-16

Table 27-9 Highest Baud Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-17

Table 27-10 Escape Timer Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-18

Table 27-11 UART Module Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-19

Table 27-12 UART1 Receiver Register n and UART2 Receiver Register n Description . . . . . . . . . . . . . . . . . . . . . 27-22

Table 27-13 UART1 Transmitter Register n and UART2 Transmitter Register n Description . . . . . . . . . . . . . . . . . . . 27-24

Table 27-14 UART1 Control Register 1 and UART2 Control Register 1 Description . . . 27-25

Table 27-15 UART1 Control Register 2 and UART2 Control Register 2 Description . . . 27-28

Table 27-16 UART1 Control Register 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-31

Table 27-17 UART1 Control Register 3 and UART2 Control Register 3 Description . . . 27-33

Table 27-18 UART1 Control Register 4 and UART2 Control Register 4 Description . . . 27-35

Table 27-19 UART1 FIFO Control Register and UART2 FIFO Control Register Description . . . . . . . . . . . . . . . . . . . 27-37

Table 27-20 UART1 Status Register 1 and UART2 Status Register 1 Description . . . . . . 27-39

Table 27-21 UART1 Status Register 2 and UART2 Status Register 2 Description . . . . . . 27-41

Table 27-22 UART1 Escape Character Register and UART2 Escape Character Register Description . . . . . . . . . . . . . . . . 27-43

Table 27-23 UART1 Escape Timer Register and UART2 Escape Timer Register Description . . . . . . . . . . . . . . . . . . . 27-44

Table 27-24 UART1 BRM Incremental Register and UART2 BRM Incremental Register Description. . . . . . . . . . . . . . . . 27-45

Table 27-25 UART1 BRM Modulator Register and UART2 BRM Modulator Register Description . . . . . . . . . . . . . . . . . 27-46

Table 27-26 UART1 Baud Rate Count Register and UART2 Baud Rate Count Register Description . . . . . . . . . . . . . . . . 27-47

Table 27-27 UART BRM Incremental Preset Registers 1–4 Description . . . . . . . . . . . . . 27-48

Table 27-28 UART BRM Modulator Preset Registers 1–4 Description . . . . . . . . . . . . . . 27-49

Table 27-29 UART1 Test Register 1 and UART2 Test Register 1 Description. . . . . . . . . 27-50

Table 28-1 Endpoint Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2

Table 28-2 Pin Configuration for USB Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6

Table 28-3 USB Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7

Table 28-4 USB Frame Number and Match Register Description . . . . . . . . . . . . . . . . . . . 28-8

Table 28-5 USB Specification and Release Number Register Description . . . . . . . . . . . . 28-9

Table 28-6 USB Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10

Table 28-7 USB Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-11

Table 28-8 Device Request Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-12

MOTOROLA

List of Tables

xlvii

Table 28-9 USB Descriptor RAM Address Register Description. . . . . . . . . . . . . . . . . . . 28-13

Table 28-10 USB Descriptor RAM/Endpoint Buffer Data Register Description . . . . . . . . 28-14

Table 28-11 USB Interrupt Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-15

Table 28-12 USB Interrupt Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-17

Table 28-13 USB Enable Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-18

Table 28-14 Endpoint n Status/Control Registers Description . . . . . . . . . . . . . . . . . . . . . . 28-19

Table 28-15 Endpoint n Interrupt Status Registers Description . . . . . . . . . . . . . . . . . . . . . 28-21

Table 28-16 Endpoint n Interrupt Mask Registers Description . . . . . . . . . . . . . . . . . . . . . 28-23

Table 28-17 Endpoint n FIFO Data Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . 28-25

Table 28-18 Endpoint n FIFO Status Registers Description. . . . . . . . . . . . . . . . . . . . . . . . 28-26

Table 28-19 Endpoint n FIFO Control Registers Description . . . . . . . . . . . . . . . . . . . . . . 28-28

Table 28-20 Endpoint n Last Read Frame Pointer Registers Description . . . . . . . . . . . . . 28-30

Table 28-21 Endpoint n Last Write Frame Pointer Registers Description . . . . . . . . . . . . . 28-31

Table 28-22 Endpoint n FIFO Alarm Registers Description . . . . . . . . . . . . . . . . . . . . . . . 28-32

Table 28-23 Endpoint n FIFO Read Pointer Registers Description . . . . . . . . . . . . . . . . . . 28-33

Table 28-24 Endpoint n FIFO Write Pointer Registers Description . . . . . . . . . . . . . . . . . . 28-34

Table 28-25 ENDPTBUF—UDC Endpoint Buffers Format . . . . . . . . . . . . . . . . . . . . . . . 28-36

Table 29-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5

Table 29-2 I

2

C Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6

Table 29-3 I

2

C Address Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7

Table 29-4 IFDR Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8

Table 29-5 HCLK Dividers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9

Table 29-6 I

2

C Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10

Table 29-7 I2SR Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-12

Table 29-8 I2DR Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14

Table 30-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6

Table 30-2 SSI Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7

Table 30-3 SSI Transmit Data Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9

Table 30-4 Data Bit Shifting Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-10

Table 30-5 SSI Receive Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-12

Table 30-6 Data Bit Shifting Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-13

Table 30-7 SSI Control/Status Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-15

Table 30-8 I2S Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19

Table 30-9 I2S Master or I2S Slave Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19

Table 30-10 SSI Transmit Configuration Register Description . . . . . . . . . . . . . . . . . . . . . 30-21

Table 30-11 SSI Transmit Data Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-23

Table 30-12 SSI Receive Configuration Register Description . . . . . . . . . . . . . . . . . . . . . . 30-24

Table 30-13 SSI Receive Data Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-26

Table 30-14 Clock Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-26 xlviii

MC9328MX1 Reference Manual

MOTOROLA

Table 30-15 SSI Transmit Clock Control Register and SSI Receive Clock Control Register Description . . . . . . . . . . . . . . . 30-27

Table 30-16 SSI Bit and Frame Clock as a Function of PSR and PM in Normal Mode . . 30-29

Table 30-17 SSI Sys, Bit and Frame Clock in Master Mode . . . . . . . . . . . . . . . . . . . . . . . 30-29

Table 30-18 SSI Time Slot Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-30

Table 30-19 SSI FIFO Control/Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . 30-31

Table 30-20 Value of Transmit FIFO Empty (TFE) and Receive FIFO Full (RFF) . . . . . 30-33

Table 30-21 SSI Option Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-34

Table 30-22 SSI Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-35

Table 30-23 SSI Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-38

Table 30-24 SSI Control Bits Requiring Reset Before Change . . . . . . . . . . . . . . . . . . . . . 30-45

Table 31-1 CSI Module Interface Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2

Table 31-2 CMOS Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3

Table 31-3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3

Table 31-4 CSI Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4

Table 31-5 CSI Control Register 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5

Table 31-6 CSI Control Register 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8

Table 31-7 CSI Status Register 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-10

Table 31-8 CSI Statistic FIFO Register 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-11

Table 31-9 CSI Module FIFO Register Storage Scheme . . . . . . . . . . . . . . . . . . . . . . . . . 31-12

Table 31-10 CSI RxFIFO Register 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12

Table 31-11 Block Size for Live View LCD Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-14

Table 32-1 GPIO External Pins Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3

Table 32-2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5

Table 32-3 GPIO Multiplexing Table with AIN, BIN, CIN, AOUT, and BOUT . . . . . . . 32-6

Table 32-4 GPIO Module Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-8

Table 32-5 Data Direction Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9

Table 32-6 Output Configuration Register 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . 32-10

Table 32-7 Output Configuration Register 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . 32-11

Table 32-8 Input Configuration Register A1 Description. . . . . . . . . . . . . . . . . . . . . . . . . 32-12

Table 32-9 Input Configuration Register A2 Description. . . . . . . . . . . . . . . . . . . . . . . . . 32-13

Table 32-10 Input Configuration Register B1 Description . . . . . . . . . . . . . . . . . . . . . . . . . 32-14

Table 32-11 Input Configuration Register B2 Description . . . . . . . . . . . . . . . . . . . . . . . . . 32-15

Table 32-12 Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-16

Table 32-13 GPIO In Use Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-17

Table 32-14 Sample Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-18

Table 32-15 Interrupt Configuration Register 1 Description . . . . . . . . . . . . . . . . . . . . . . . 32-19

Table 32-16 Interrupt Configuration Register 2 Description . . . . . . . . . . . . . . . . . . . . . . . 32-20

Table 32-17 Interrupt Mask Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-21

MOTOROLA

List of Tables

xlix

Table 32-18 Interrupt Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-22

Table 32-19 General Purpose Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-23

Table 32-20 Software Reset Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-24

Table 32-21 Pull_Up Enable Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-25 l

MC9328MX1 Reference Manual

MOTOROLA

About This Book

This reference manual describes the features and operation of the MC9328MX1 (DragonBall™ MX1) microprocessor, the fifth generation of the DragonBall family of products. It provides the details of how to initialize, configure, and program the MC9328MX1. The manual presumes basic knowledge of

ARM920T™ architecture.

Audience

The MC9328MX1 Reference Manual is intended to provide a design engineer with the necessary data to successfully integrate the MC9328MX1 into a wide variety of applications. It is assumed that the reader has a good working knowledge of the ARM920T processor. For programming information about the

ARM920T processor, see the documents listed in the Suggested Reading section of this preface.

Organization

The MC9328MX1 Reference Manual is organized into 31 chapters that cover the operation and programming of the DragonBall MX1 device. Summaries of the chapters follow.

Chapter 1

Chapter 2

Chapter 3

Chapter 4

Chapter 5

Chapter 6

Chapter 7

Chapter 8

Chapter 9

Introduction:

This chapter contains a device feature list, overview of system modules, system block diagrams, and a feature comparison of the different generations of the DragonBall devices.

Signal Descriptions and Pin Assignments:

This chapter contains listings of the

MC9328MX1 input and output signals, organized into functional groups.

Memory Map:

This chapter summarizes the memory organization, programming information and a listing of all of the registers in the MC9328MX1.

ARM920T Processor:

This chapter provides a high-level overview of the

ARM920T processor including the ARM9 Thumb

instruction set.

Embedded Trace Macrocell (ETM):

This chapter provides a summary of the operation and features of the ARM Embedded Trace Macrocell™.

Reset Module:

The reset module processes of all of the system reset signals required by the MC9328MX1. This chapter gives a detailed description of the reset module and associated timing and signals.

AIPI Module (AIPI):

This chapter provides an overview of the R-AHB to IP bus interface. The AIPI module in the MC9328MX1 acts as an interface between the

R-AHB (Reduced ARM Advanced High-performance Bus) and lower bandwidth peripherals.

System Control:

This chapter describes the operation of and programming models for the system multiplex control, peripheral control, ID register, and I/O drive control registers.

Bootstrap Mode Operation:

The operation of bootstrap models is described in detail in this chapter. This chapter describes programming information necessary

MOTOROLA

About This Book

li

Chapter 10

Chapter 11

Chapter 12

Chapter 13

Chapter 14

Chapter 15

Chapter 16

Chapter 17

Chapter 18

Chapter 19

Chapter 20

Chapter 21 lii to allow a system to initialize a target system and download a program or data to the target system’s RAM using the UART controller.

Interrupt Controller (AITC):

This chapter provides a description and operational considerations for interrupt controller operation to perform interrupt masking, priority support, and hardware acceleration of normal interrupts.

External Interface Module (EIM):

This chapter describes the external interface module and shows how the module handles the interface to devices external to the MC9328MX1, including generation of chip selects for external peripherals and memory.

Phase-Locked Loop and Clock Controller:

This chapter provides detailed information about the operation and programming of the clock generation module as well as the recommended circuit schematics for external clock circuits.

It also describes and provides programming information about the operation of the power control module and the system power states.

DMA Controller (DMAC):

This chapter describes the operation of the direct memory access controller contained in the MC9328MX1. The DMA controller provides two memory channels and four I/O channels to support a wide variety of DMA operations.

Watchdog Timer Module:

The operation of the watchdog timer module is described in this chapter. It includes information of how the watchdog timer protects against system failures by providing a method of escaping from unexpected events or programming errors.

Analog Signal Processor (ASP):

This chapter describes the analog signal processing module of the MC9328MX1 which provides support and conversion capabilities for a variety of analog devices, including analog-to-digital controller

(ADC) for pen input. The ASP also includes embedded circuity to support a touch panel.

Bluetooth Accelerator (BTA):

This chapter describes the Bluetooth accelerator which, controlled by software running on the ARM920T processor, implements baseband protocols and other low-level link routines of the Bluetooth baseband.

Multimedia Accelerator (MMA):

This chapter describes the operation of the

MMA which is used in conjunction with the ARM920T processor to perform the iterative operations of a digital signal processor for applications such as MPEG or MP3 encoding/decoding and speech compression/decompression.

Serial Peripheral Interface Modules (SPI 1 and SPI 2)

: The programming and operation of the two identical serial peripheral interface modules (SPI 1 and

SPI 2) are described in this chapter.

LCD Controller (LCDC):

This chapter describes the operation and programming of the liquid crystal display controller, which provides display data for external LCD drivers or for an LCD panel.

Multimedia Card/Secure Digital Host Controller (MMC/SD):

T his chapter describes the Multimedia Card (MMC) host controller which controls

Flash-based mass storage products. This chapter also describes the Secure Digital feature of the MMC, its operation and programming information.

Memory Stick Host Controller (MSHC):

This chapter describes how data is transferred to a Memory Stick device. It also discusses how to configure and program the Memory Stick Host Controller.

MC9328MX1 Reference Manual

MOTOROLA

Chapter 22

Chapter 23

Chapter 24

Chapter 25

Chapter 26

Chapter 27

Chapter 28

Chapter 29

Chapter 30

Chapter 31

Chapter 32

Pulse-Width Modulator (PWM):

This chapter describes the operation and configuration of the pulse-width modulator. Programming information is also provided.

Real-Time Clock (RTC):

This chapter describes the operation of the real-time clock module, which is composed of a prescaler, time-of-day (TOD) clock, TOD alarm, programmable real-time interrupt, watchdog timer, and minute stopwatch as well as control registers and bus interface hardware.

SDRAM Memory Controller (SDRAMC):

The operation and programming of the SDRAM controller is described in this chapter. This module provides a glueless interface to 8-bit or 16-bit DRAM supporting EDO RAM, Fast Page

Mode, and synchronous DRAM.

SmartCard Interface Module:

This chapter details the features, operation, and programming interface of the SmartCard Interface Module (SIM).

General-Purpose Timers:

This chapter describes the two 16-bit timers that can be used as both watchdogs and alarms.

Universal Asynchronous Receiver/Transmitters (UART):

This chapter describes the capabilities and operation of the two UARTs. It also discusses how to configure and program the UART modules.

USB Device Port:

This chapter describes the features and programming model of the MC9328MX1’s USB device module.

I

2

C Module:

This chapter describes the I

2 including I

2

C module of the MC9328MX1

C protocol, clock synchronization, and the registers in the I

2

C programming mode.

Synchronous Serial Interface (SSI):

This chapter presents the Synchronous

Serial Interface and discusses the architecture, programming model, operating modes, and initialization of the SSI.

CMOS Sensor Interface (CSI):

The CSI module is a logic interface that enables the MC9328MX1 to connect directly to external CMOS image sensors. This chapter describes the CSI module, and discusses the architecture, the programming model, and the software initialization sequence.

GPIO and I/O Multiplexer (IOMUX):

This chapter covers all GPIO lines found in the MC9328MX1. Because each pin is individually configurable, a detailed description of the operation is provided.

MOTOROLA

About This Book

liii

Document Revision History

The following table provides the revision history for this manual. This history includes technical content revisions only and not stylistic or grammatical changes.

MC9328MX1 Reference Manual Revision History Rev. 1,

Revision Location

ASP, Signals, Memory Map and AITC chapters

EIM Chapter

All chapters

Revision

Removed all references to the voice CODEX

Expanded DTACK description and operation

Corrections to industry specifications to reflect newer versions.

Changes to the internal voltage ranges to reflect higher core speed.

Suggested Reading

The following documents are required for a complete description of the MC9328MX1 and are necessary to design properly with the device. Especially for those not familiar with the ARM920T processor or previous DragonBall products, the following documents will be helpful when used in conjunction with this manual.

ARM Architecture Reference Manual

(ARM Ltd., order number ARM DDI 0100)

ARM9DT1 Data Sheet Manual

(ARM Ltd., order number ARM DDI 0029)

ARM Technical Refines Manual (ARM Ltd., order number ARM DDI 0151C)

EMT9 Technical Reference Manual

(ARM Ltd., order number DDI O157E)

MC68EZ328 User’s Manual (order number MC68EZ328UM/D)

MC68EZ328 User’s Manual Addendum (order number MC68EZ328UMAD/D)

MC68VZ328 Product Brief

(order number MC68VZ328P/D)

MC68VZ328 User’s Manual

(order number MC68VZ328UM/D)

MC68VZ328 User’s Manual Addendum

(order number MC68VZ328UMAD/D)

MC68SZ328 Product Brief

(order number MC68SZ328P/D)

MC68SZ328 User’s Manual

(order number MC68SZ328UM/D)

The manuals may be found at the Motorola Semiconductors World Wide Web site at http://www.motorola.com/semiconductors. These documents may be downloaded directly from the World

Wide Web site, or printed versions may be ordered. The World Wide Web site also may have useful application notes.

Conventions

This reference manual uses the following conventions:

• OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.

Logic level one

is a voltage that corresponds to Boolean true (1) state.

Logic level zero

is a voltage that corresponds to Boolean false (0) state.

liv

MC9328MX1 Reference Manual

MOTOROLA

• To

set

a bit or bits means to establish logic level one.

• To

clear

a bit or bits means to establish logic level zero.

• A

signal

is an electronic construct whose state conveys or changes in state convey information.

• A

pin

is an external physical connection. The same pin can be used to connect a number of signals.

Asserted

means that a discrete signal is in active logic state.

Active low

signals change from logic level one to logic level zero.

Active high

signals change from logic level zero to logic level one.

Negated

means that an asserted discrete signal changes logic state.

Active low

signals change from logic level zero to logic level one.

Active high

signals change from logic level one to logic level zero.

• LSB means

least significant bit

or

bits

, and MSB means

most significant bit

or

bits

. References to low and high bytes or words are spelled out.

• Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or

0x

are hexadecimal.

Definitions, Acronyms, and Abbreviations

FEC

FIFO

GPIO

IAC

I/O

ICE

The following list defines acronyms and abbreviations used in this document.

ADC analog-to-digital converter

AFE

API

BCD analog front end application programming interface binary coded decimal

BER

CGM

CMOS

CRC bit error ratio clock generation module complimentary metal-oxide semiconductor cyclic redundancy check

CSIC

DAC

DAC

DDR RAM

DMA

DRAM

DSP

EDO RAM complex instruction set computer device access code: Bluetooth digital-to-analog converter double data rate RAM direct memory access dynamic random access memory digital signal processor extended data out DRAM forward error correction first in first out general purpose input/output inquiry access code: A predefined Bluetooth ID input/output in-circuit emulation

MOTOROLA

About This Book

lv

IrDa

JTAG

MAP

MAPBGA

MIPS

MMC

PADC

PLL

PWM

RTC

SIM

SD

SDRAM

SPI

SRAM

TQFP

UART

USB

XTAL infrared joint test action group mold array process mold array process ball grid array million instructions per second multimedia card

Pen analog-to-digital converter phase locked loop pulse-width modulator real-time clock system integration module secure digital synchronous dynamic random access memory serial peripheral interface static random access memory thin quad flat pack universal asynchronous receiver/transmitter universal serial bus crystal lvi

MC9328MX1 Reference Manual

MOTOROLA

Chapter 1

Introduction

Motorola’s DragonBall family of microprocessors has demonstrated leadership in the portable handheld market. Continuing this legacy, the DragonBall MX (Media Extensions) series provides a leap in performance with an ARM9™ microprocessor core and highly integrated system functions. DragonBall

MX products specifically address the requirements of the personal, portable product market by providing intelligent integrated peripherals, an advanced processor core, and power management capabilities.

The new MC9328MX1 features the advanced and power-efficient ARM920T™ core that operates at speeds up to 200 MHz. Integrated modules such as an LCD controller, static RAM, USB support, an A/D converter (with touch panel control), and an MMC/SD host controller offer a suite of peripherals to enhance any product seeking to provide a rich multimedia experience. In addition, the MC9328MX1 is the first Bluetooth™ technology-ready applications processor. It is packaged in a 256-pin Mold Array

Process-Ball Grid Array (MAPBGA).

The MC9328MX1 provides the following benefits:

• Represents the fifth generation of the industry-leading DragonBall family of microprocessors for the personal, portable product market

• Features a high level of on-chip integration

• Provides uncompromised performance in a very low-power system design

• Optimized for multimedia applications

• Optimized for Bluetooth applications with high-speed interfaces to external Bluetooth solutions

• Supports a wide variety of applications including the most popular PDA designs, smart phones, and next-generation wireless communicators

1.1 Block Diagram

Figure 1-1 on page 1-2 is a simplified functional block diagram of the MC9328MX1.

MOTOROLA

Introduction

1-1

Introduction

JTAG/ICE

System Control

Bootstrap

Power

Control

Connectivity

MMC/SD

Memory Stick®

Host Controller

SPI 1 and

SPI 2

UART 1

UART 2

SSI / I2S

I2C

USB Device

SmartCard I/F

Bluetooth

Accelerator

MC9328MX1

CPU Complex

ARM9TDMI™

I Cache

DPLL x2

D Cache

AIPI 1

AIPI 2

VMMU

DMAC

(11 Chnl)

Interrupt

Controller

Bus

Control

EIM &

SDRAMC

Standard

System I/O

GPIO

PWM

Timer 1 & 2

RTC

Watchdog

Multimedia

Multimedia

Accelerator

Video Port

Human Interface

Analog Signal

Processor

LCD Controller

Figure 1-1. MC9328MX1 Functional Block Diagram

1.2 Features

To support a wide variety of applications, the MC9328MX1 boasts a robust array of features, including the following:

• ARM920T Microprocessor Core

• AHB to IP Bus Interfaces (AIPIs)

• External Interface Module (EIM)

• SDRAM Controller (SDRAMC)

• Clock Generation Module (CGM) and Power Control Module

• Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2)

• Two Serial Peripheral Interfaces (SPI)

• Two General-Purpose 32-bit Counters/Timers

• Watchdog Timer

• Real-Time Clock/Sampling Timer (RTC)

• LCD Controller (LCDC)

• Pulse-Width Modulation (PWM) Module

• Universal Serial Bus (USB) Device

• Multimedia Card and Secure Digital (MMC/SD) Host Controller

1-2

MC9328MX1 Reference Manual

MOTOROLA

ARM920T Microprocessor Core

• Memory Stick® Host Controller (MSHC)

• SmartCard Interface Module (SIM)

• Direct Memory Access Controller (DMAC)

• Synchronous Serial Interface and Inter-IC Sound (SSI/I

2

S) Module

• Inter-IC (I

2

C) Bus Module

• Video Port

• General-Purpose I/O (GPIO) Ports

• Bootstrap Mode

• Analog Signal Processing (ASP) Module

• Bluetooth Accelerator (BTA)

• Multimedia Accelerator (MMA)

• Power Management Features

• Operating Voltage Range: I/O voltage 1.7 V to 3.3 V, core voltage 1.7 V to 2.0 V

• Packaging: 256-pin MAPBGA or 225-pin PBGA

The following sections detail the features of the MC9328MX1’s functional blocks.

1.3 ARM920T Microprocessor Core

The MC9328MX1 uses the ARM920T microprocessor core which has the following features:

• 200 MHz maximum processing speed

• 16K instruction cache and 16K data cache

• ARM9 high performance 32-bit RISC engine

• Thumb® 16-bit compressed instruction set for a leading level of code density

• EmbeddedICE™ JTAG software debug

• 100-percent user code binary compatibility with ARM7TDMI® processors

• ARM9TDMI® core, including integrated caches, write buffers, and bus interface units, provides

CPU-cache transparency

• Advanced Microcontroller Bus Architecture (AMBA™) system-on-chip multi-master bus interface

• Flexible CPU and bus clocking relationships including asynchronous, synchronous, and single-clock configurations

• Cache locking to support mixed loads of real-time and user applications

• Virtual Memory Management Unit (VMMU)

1.4 AHB to IP Bus Interfaces (AIPIs)

The MC9328MX1 AIPIs provide a communication interface between the high-speed AHB bus and a lower-speed IP bus for slow slave peripherals.

MOTOROLA

Introduction

1-3

Introduction

1.5 External Interface Module (EIM)

The MC9328MX1 EIM features:

• Up to six chip selects for external devices, each with 16 Mbyte of address space (chip selects for

ROM support a maximum of 32 Mbyte of address space)

• Programmable protection, port size, and wait states for each chip select

• Internal/external boot ROM selection

• Selectable bus watchdog counter

• Burst support for external AMD™ or Intel® flash with 32-bit data path

• Interrupt controller to handle a maximum of 63 interrupt sources

• Vectored interrupt capability with prioritization for 16 sources

1.6 SDRAM Controller (SDRAMC)

The MC9328MX1 SDRAMC features:

• Supports 4 banks of 64-, 128-, or 256-Mbit synchronous DRAMs

• Includes 2 independent chip-selects

— Up to 64 Mbyte per chip-select

— Up to four banks simultaneously active per chip-select

— JEDEC standard pinout and operation

• Supports Micron SyncFlash® SDRAM-interface burst flash memory

— Boot capability from CSD1

• Supports burst reads of word (32-bit) data types

• PC100 compliant interface

— 100 MHz system clock achievable with “-8” option PC100 compliant memories

— single and fixed-length (8-word) word access

— Typical access time of 8-1-1-1 at 100 MHz

• Software configurable bus width, row and column sizes, and delays for differing system requirements

• Built in auto-refresh timer and state machine

• Hardware supported self-refresh entry and exit which keeps data valid during system reset and low-power modes

• Auto-powerdown (clock suspend) timer

1.7 Clock Generation Module (CGM) and Power Control

Module

The MC9328MX1 CGM and Power Control Module features:

• Digital phase-locked loops (PLLs) and clock controller for all internal clocks generation

1-4

MC9328MX1 Reference Manual

MOTOROLA

Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2)

• MCUPLL generates FCLK to the CPU from either a 32 kHz, 32.768 kHz, or 38.4 kHz crystal

• SYSTEM PLL generates the system clock and the 48 MHz clock for the USB from a 16 MHz or either a 32 kHz, 32.768 kHz, or 38.4 kHz crystal

• Support for three power modes for different power consumption needs: run, doze, and stop

1.8 Two Universal Asynchronous Receiver/Transmitters

(UART 1 and UART 2)

The MC9328MX1 UARTs feature:

• Support for serial data transmit/receive operation: 7 or 8 data bits, 1 or 2 stop bits, and programmable parity (even, odd, or none)

• Programmable baud rates up to 1.00 MHz

• 32-byte FIFO on Tx and 32 half-word FIFO on Rx that support autobaud

• IrDA 1.0 support

1.9 Two Serial Peripheral Interfaces (SPI)

The MC9328MX1 SPIs feature:

• SPI 1is master/slave configurable, SPI 2 is master only

• Up to 16-bit programmable data transfer

• 8

×

16 FIFO for both Tx and Rx data

1.10 Two General-Purpose 32-Bit Counters/Timers

The MC9328MX1 General-Purpose Counters/Timers feature:

• Automatic interrupt generation

• Programmable timer input/output pins

• Input capture capability with programmable trigger edge

• Output compare with programmable mode

1.11 Watchdog Timer

The MC9328MX1 Watchdog Timer features:

• Programmable time out of 0.5 s to 64 s

• Resolution of 0.5 s

MOTOROLA

Introduction

1-5

Introduction

1.12 Real-Time Clock/Sampling Timer (RTC)

The MC9328MX1 RTC features:

• 32.768 kHz, 32 kHz, or 38.4 MHz operation

• Full clock features: seconds, minutes, hours, and days

• Capable of counting up to 512 days

• Minute countdown timer with interrupt

• Programmable daily alarm with interrupt

• Sampling timer with interrupt

• Once-per-second, once-per-minute, once-per-hour, and once-per-day interrupts

• Interrupt generation for digitizer sampling or keyboard debouncing

1.13 LCD Controller (LCDC)

The MC9328MX1 LCDC features:

• Software programmable screen size (a maximum of 640 monochrome, color STN panels, and color TFT panels

×

512 pixels) to support single (non-split)

• Support for 4 bpp (bits per pixel), 8 bpp and 12 bpp for passive color panels

• Support for 4 bpp, 8 bpp, 12 bpp and 16 bpp for TFT panels

— Up to 256 colors out of a palette of 4096 for 8 bpp

— True 64K color for 16 bpp

• In color STN mode, the maximum bit depth is 12 bpp

• In BW mode, the maximum bit depth is 4 bpp

• Up to 16 grey levels out of 16 palettes

• Capable of directly driving popular LCD drivers from manufacturers including Motorola, Sharp,

Hitachi, and Toshiba

• Support for data bus width for 12- or 16-bit TFT panels

• Panel interface of 8-, 4-, and 2-bits, and a 1-bit wide LCD panel data bus for monochrome panels

• Direct interface to Sharp® 320 × 240 HR-TFT panel

• Support for logical operation between color hardware cursor and background

• Uses system memory as display memory

• LCD contrast control using 8-bit PWM

• Support for self-refresh LCD modules

• Hardware panning (soft horizontal scrolling)

1.14 Pulse-Width Modulation (PWM) Module

The MC9328MX1 PWM Module features:

• 4

×

16 FIFO to minimize interrupt overhead

1-6

MC9328MX1 Reference Manual

MOTOROLA

Universal Serial Bus (USB) Device

• 16-bit resolution

• Sound and melody generation

1.15 Universal Serial Bus (USB) Device

The MC9328MX1 USB Device features:

• Compliant with

Universal Serial Bus Specification, revision 1.1

• Up to six logical endpoints—see Table 1-1 on page 1-7

• Support for isochronous communications pipes

— Frame match interrupt feature notifies the user when a specific USB frame occurs

— For DMA access, the maximum packet size for the isochronous endpoint is restricted by the

FIFO size of the endpoint

— For programmed I/O, isochronous data packets range from 0 bytes to 1023 bytes

• Support for control, bulk, and interrupt pipes

— Packet sizes are limited to 8, 16, 32, or 64 bytes

— Maximum packet size depends on the FIFO size of the endpoint

• Support (via a register bit) for a remote wake-up feature

• Full-speed (12 MHz) operation

• Programmable as self-powered

Table 1-1. Endpoint Configurations

Endpoint Direction

Physical FIFO

Size (Bytes)

Endpoint

Configuration

Maximum Packet Size

(Bytes)

0 IN and OUT 32 Control 32

1–5 IN or OUT

32 or 64

1 Control, interrupt, bulk, or isochronous

User configurable: 8, 16,

32, or 64 (depending on

FIFO size)

1.

FIFO1 and FIFO2 are 64 bytes each; FIFO3, FIFO4, and FIFO5 are 32 bytes each.

1.16 Multimedia Card and Secure Digital (MMC/SD) Host

Controller

The MC9328MX1 MMC/SD Host Controller features:

• Fully compatible with the

MMC System Specification version 3.1

• Fully compatible with the

SD Memory Card Specification 1.0

and

SD I/O Specification 1.0

with 1 or

4 channel(s)

• Up to ten MMC cards and one SD are supported by standard (maximum data rate with a maximum of ten cards)

• Support for hot swappable operation

• Support for data rates from 20 Mbps to 80 Mbps

MOTOROLA

Introduction

1-7

Introduction

1.17 Memory Stick® Host Controller (MSHC)

The MC9328MX1 MSHC features:

• Integrated 8-byte (4-word) FIFO buffer for transmit and receive

• Integrated CRC circuit

• Support for internal or external serial clock source

• Integrated Serial Clock Divider

• DMA support; DMA request condition is selectable based on FIFO status

• Automatic command execution when an interrupt from the Memory Stick is detected (can be toggled on/off)

• RDY time-out period set by the number of serial clock cycles

• Interrupt output to the ARM920T core when a time-out occurs

• Two integrated general-purpose input pins for detecting Memory Stick insertion/extraction

• 16-bit host bus access (byte access not supported)

1.18 SmartCard Interface Module (SIM)

The MC9328MX1 SIM features:

• ISO7816 smartcard interface

• 32 word deep receive FIFO

• SIM card presence detect with interrupt capability

1.19 Direct Memory Access Controller (DMAC)

The MC9328MX1 DMAC features:

• 11 channels to support linear memory, 2D memory, FIFO, and End-of-Burst Enable FIFO for both source and destination

• Support for 8-, 16-, or 32-bit FIFO port size and memory port size data transfer

• Support for big-endian and little-endian

• Configurable DMA burst length for each channel up to 16 words, 32 half-words, or 64 bytes

• Bus utilization control for a channel that is not triggered by DMA requests

• Bulk data transfer complete or transfer error interrupts provided to interrupt handler (and then to the core)

• DMA burst time-out error terminates the DMA cycle when the burst cannot be completed within a programmed timing period

• Acknowledge signal provided to peripheral after DMA burst is complete

1-8

MC9328MX1 Reference Manual

MOTOROLA

Synchronous Serial Interface and Inter-IC Sound (SSI/I

2

S) Module

1.20 Synchronous Serial Interface and Inter-IC Sound (SSI/I

2

S)

Module

The MC9328MX1 SSI/I

2

S Module features:

• Supports generic SSI interface for external audio chip or interprocessor communication

• Supports Philips standard Inter-IC Sound (I

2

S) bus for external digital audio chip interface

1.21 Inter-IC (I

2

C) Bus Module

The MC9328MX1 I

2

C Bus Module features:

• Support for Philips I

2

C-bus standard for external digital control

• Support for 3.3 V tolerant devices

• Multiple-master operation

• Software-programmable for 1 of 64 different serial clock frequencies

• Software-selectable acknowledge bit

• Interrupt-driven, byte-by-byte data transfer

• Arbitration-lost interrupt with automatic mode switching from master to slave

• Calling address identification interrupt

• Start and stop signal generation and detection

• Repeated START signal generation

• Acknowledge bit generation and detection

• Bus-busy detection

1.22 Video Port

The MC9328MX1 video port supports external CMOS sensor video data input.

1.23 General-Purpose I/O (GPIO) Ports

The MC9328MX1 GPIO ports feature:

• Interrupt capability

• 110 total I/O pins multiplexed with most dedicated functions for pin efficiency

1.24 Bootstrap Mode

The MC9328MX1 Bootstrap Mode features:

• Allows user to initialize system and download program or data to system memory through UART

• Accepts execution command to run program stored in system memory

• Supports memory/register read/write operation of selectable data size of byte, half-word, or word

MOTOROLA

Introduction

1-9

Introduction

• Provides a 32-byte instruction buffer for ARM920T core vector table storage, instruction storage and execution

1.25 Analog Signal Processing (ASP) Module

The MC9328MX1 ASP Module features:

• Pen ADC

— 9-bit Pen ADC (PADC) for touch panel and low voltage detection

— 12

×

16-bit FIFO for PADC sample

— Embedded touch panel circuitry

— Supports auto and manual sampling mode

— Programmable pen down and pen-up interrupt to interrupt handler

— Provides data-ready and FIFO-full interrupt to interrupt handler

— True differential input

1.26 Bluetooth Accelerator (BTA)

The MC9328MX1 Bluetooth Accelerator features:

• Low-level baseband processing engine

• Hop frequency selection co-processing module

• 32-word (16-bit) Rx and Tx buffer

• Programmable RF controller supports three front ends (including SPI /

µ

Wire controller)

• Support for external transceiver ICs from manufacturers such as Motorola (MC13180) and

Silicon Wave™

• Bluetooth application timer

• Wake-up timer for low-power support

• Low-power capabilities

1.27 Multimedia Accelerator (MMA)

The MC9328MX1 Multimedia Accelerator features:

• MAC for FIR and FFT operation—MP3 applications save 10% to 15% CPU MIPS

• DCT/iDCT hardware accelerator—MPEG4 decode applications save approximately 10% CPU

MIPS

1.28 Power Management Features

The MC9328MX1 provides the following power management features:

• Programmable clock synthesizer using either a 32 kHz, 32.768, or 38.4 kHz crystal for full frequency control

1-10

MC9328MX1 Reference Manual

MOTOROLA

Operating Voltage Range

• Low-power stop capabilities

• Modules that can be individually shut down

• Lowest power mode control

1.29 Operating Voltage Range

The MC9328MX1 operating voltages are as follows:

• I/O voltage - 1.70 V to 2.0 V or 2.7 V to 3.3 V

• Internal logic voltage - 1.70 V to 2.0 V

1.30 Packaging

The MC9328MX1 features two packages:

• 256-pin MAPBGA package with 14 mm × 14 mm × 1.3 mm, 0.8 mm ball pitch

• 225-pin PBGA package with 13 mm × 13 mm, 0.8 mm ball pitch

MOTOROLA

Introduction

1-11

Introduction

1-12

MC9328MX1 Reference Manual

MOTOROLA

Chapter 2

Signal Descriptions and Pin Assignments

This chapter identifies and describes the MC9328MX1 signals and their pin assignments.

A [24:0]

D [31:0]

EB0

EB1

EB2

EB3

OE

CS [5:0]

2.1 Signal Descriptions

MC9328MX1 signals are listed in Table 2-1.

Table 2-1. MC9328MX1 Signal Descriptions

Signal Name Function/Notes

ECB

LBA

BCLK

RW

External Bus/Chip Select (EIM)

Address bus signals

Data bus signals

MSB Byte Strobe—Active low external enable byte signal that controls D [31:24]

Byte Strobe—Active low external enable byte signal that controls D [23:16]

Byte Strobe—Active low external enable byte signal that controls D [15:8]

LSB Byte Strobe—Active low external enable byte signal that controls D [7:0]

Memory Output Enable—Active low output enables external data bus

Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.

Active low input signal sent by flash device to the EIM whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence.

Active low signal sent by flash device causing the external burst device to latch the starting burst address.

Clock signal sent to external synchronous memories (such as burst flash) during burst mode.

RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input signal by external DRAM.

MOTOROLA

Signal Descriptions and Pin Assignments

2-1

Signal Descriptions and Pin Assignments

Signal Name

Table 2-1. MC9328MX1 Signal Descriptions (Continued)

Function/Notes

BOOT [3:0]

SDBA [4:0]

SDIBA [3:0]

MA [11:10]

MA [9:0]

DQM [3:0]

CSD0

CSD1

RAS

CAS

SDWE

SDCKE0

SDCKE1

SDCLK

RESET_SF

EXTAL16M

XTAL16M

EXTAL32K

XTAL32K

Bootstrap

System Boot Mode Select—The operational system boot mode of the MC9328MX1 upon system reset is determined by the settings of these pins.

SDRAM Controller

SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals

A [15:11]. These signals are logically equivalent to core address p_addr [25:21] in

SDRAM/SyncFlash cycles.

SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address signals A [19:16]. These signals are logically equivalent to core address p_addr [12:9] in

SDRAM/SyncFlash cycles.

SDRAM address signals

SDRAM address signals which are multiplex with address signals A [10:1]. MA [9:0] are selected on SDRAM/SyncFlash cycles.

SDRAM data enable

SDRAM/SyncFlash Chip Select signal which is multiplexed with the CS2 signal. These two signals are selectable by programming the system control register.

SDRAM/SyncFlash Chip Select signal which is multiplex with CS3 signal. These two signals are selectable by programming the system control register. By default, CSD1 is selected, so it can be used as SyncFlash boot chip select by properly configuring BOOT

[3:0] input pins.

SDRAM/SyncFlash Row Address Select signal

SDRAM/SyncFlash Column Address Select signal

SDRAM/SyncFlash Write Enable signal

SDRAM/SyncFlash Clock Enable 0

SDRAM/SyncFlash Clock Enable 1

SDRAM/SyncFlash Clock

SyncFlash Reset

Clocks and Resets

Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when internal oscillator circuit is shut down.

Crystal output

32 kHz crystal input

32 kHz crystal output

2-2

MC9328MX1 Reference Manual

MOTOROLA

Signal Descriptions

Signal Name

CLKO

RESET_IN

RESET_OUT

POR

TRST

TDO

TDI

TCK

TMS

BIG_ENDIAN

ETMTRACESYNC

ETMTRACECLK

ETMPIPESTAT [2:0]

ETMTRACEPKT [7:0]

CSI_D [7:0]

CSI_MCLK

CSI_VSYNC

Table 2-1. MC9328MX1 Signal Descriptions (Continued)

Function/Notes

Clock Out signal selected from internal clock signals. Please refer to clock controller for internal clock selection.

Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all modules (except the reset module and the clock control module) are reset.

Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the following sources: Power-on reset, External reset (RESET_IN), and

Watchdog time-out.

Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally generated by an external RC circuit designed to detect a power-up event.

JTAG

Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.

Serial Output for test instructions and data. Changes on the falling edge of TCK.

Serial Input for test instructions and data. Sampled on the rising edge of TCK.

Test Clock to synchronize test logic and control register access through the JTAG port.

Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of TCK.

System

BIG_ENDIAN—This signal determines the memory endian configuration. BIG_ENDIAN is a static pin to inner module. If the pin is driven logic-high the memory system is configured into big endian. If it is driven logic-low the memory system is configured into little endian. The pin is not supposed to be changed on the fly.

ETM

ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.

ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.

ETM status signals which are multiplex with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM mode.

ETM packet signals which are multiplex with ECB, LBA, BCLK, PA17, A [19:16].

ETMTRACEPKT [7:0] are selected in ETM mode.

CMOS Sensor Interface

Sensor port data

Sensor port master clock

Sensor port vertical sync

MOTOROLA

Signal Descriptions and Pin Assignments

2-3

Signal Descriptions and Pin Assignments

Signal Name

CSI_HSYNC

CSI_PIXCLK

LD [15:0]

FLM/VSYNC

LP/HSYNC

LSCLK

ACD/OE

CONTRAST

SPL_SPR

PS

CLS

REV

SIM_CLK

SIM_RST

SIM_RX

SIM_TX

SIM_PD

SIM_SVEN

SPI1_MOSI

SPI1_MISO

SPI1_SS

SPI1_SCLK

SPI1_SPI_RDY

Table 2-1. MC9328MX1 Signal Descriptions (Continued)

Function/Notes

Sensor port horizontal sync

Sensor port data latch clock

LCD Controller

LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.

Frame Sync or Vsync—This signal also serves as the clock signal output for gate driver (dedicated signal SPS for Sharp panel HR-TFT).

Line Pulse or H Sync

Shift Clock

Alternate Crystal Direction/Output Enable

This signal is used to control the LCD bias voltage as contrast control.

Program horizontal scan direction (Sharp panel dedicated signal).

Control signal output for source driver (Sharp panel dedicated signal).

Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated signal).

Signal for common electrode driving signal preparation (Sharp panel dedicated signal).

SIM

SIM Clock

SIM Reset

Receive Data

Transmit Data

Presence Detect Schmitt trigger input

SIM Vdd Enable

SPI

Master Out/Slave In

Slave In/Master Out

Slave Select (Selectable polarity)

Serial Clock

Serial Data Ready

2-4

MC9328MX1 Reference Manual

MOTOROLA

Signal Name

SPI2_TXD

SPI2_RXD

SPI2_SS

SPI2_SCLK

TIN

TMR2OUT

USBD_VMO

USBD_VPO

USBD_VM

USBD_VP

USBD_SUSPND

USBD_RCV

USBD_OE

USBD_AFE

SD_CMD

SD_CLK

Signal Descriptions

Table 2-1. MC9328MX1 Signal Descriptions (Continued)

Function/Notes

SPI2 Master TxData Output—This signal is multiplexed with a GPI/O pin however it does show up as a primary or alternative signal in the signal multiplex scheme table. Refer to

Chapter 18, “Serial Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 32,

“GPIO Module and I/O Multiplexer (IOMUX),” for information on how to bring this signal to the assigned pin.

SPI2 master RxData input—This signal is multiplexed with a GPI/O pin however it does show up as a primary or alternative signal in the signal multiplex scheme table. Refer to

Chapter 18, “Serial Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 32,

“GPIO Module and I/O Multiplexer (IOMUX),” for information on how to bring this signal to the assigned pin.

SPI2 Slave Select—This signal is multiplexed with a GPI/O pin, however it does show up as a primary or alternative signal in the signal multiplex scheme table. Refer to

Chapter 18, “Serial Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 32,

“GPIO Module and I/O Multiplexer (IOMUX),” for information on how to bring this signal to the assigned pin.

SPI2 Serial Clock—This signal is multiplexed with a GPI/O pin however it does show up as a primary or alternative signal in the signal multiplex scheme table. Refer to

Chapter 18, “Serial Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 32,

“GPIO Module and I/O Multiplexer (IOMUX),” for information on how to bring this signal to the assigned pin.

General Purpose Timers

Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers simultaneously.

Timer 2 Output

USB Device

USB Minus Output

USB Plus Output

USB Minus Input

USB Plus Input

USB Suspend Output

USB RxD

USB OE

USB Analog Front End Enable

Secure Digital Interface

SD Command—If the system designer does not want to make use of the internal pull-up, via the Pull-up enable register, a 4.7K–69K external pull up resistor must be added.

MMC Output Clock

MOTOROLA

Signal Descriptions and Pin Assignments

2-5

Signal Name

SD_DAT [3:0]

UART1_RXD

UART1_TXD

UART1_RTS

UART1_CTS

UART2_RXD

UART2_TXD

UART2_RTS

UART2_CTS

UART2_DSR

UART2_RI

UART2_DCD

UART2_DTR

Signal Descriptions and Pin Assignments

MS_BS

MS_SDIO

MS_SCLKO

MS_SCLKI

MS_PI0

MS_PI1

SSI_TXDAT

SSI_RXDAT

SSI_TXCLK

SSI_RXCLK

SSI_TXFS

SSI_RXFS

Table 2-1. MC9328MX1 Signal Descriptions (Continued)

Function/Notes

Data—If the system designer does not want to make use of the internal pull-up, via the

Pull-up enable register, a 50 K–69K external pull up resistor must be added.

Memory Stick Interface

Memory Stick Bus State (Output)—Serial bus control signal

Memory Stick Serial Data (Input/Output)

Memory Stick External Clock (Input)—External clock source for SCLK Divider

Memory Stick Serial Clock (Output)—Serial Protocol clock signal

General purpose Input0—Can be used for Memory Stick Insertion/Extraction detect

General purpose Input1—Can be used for Memory Stick Insertion/Extraction detect

UARTs – IrDA/Auto-Bauding

Receive Data

Transmit Data

Request to Send

Clear to Send

Receive Data

Transmit Data

Request to Send

Clear to Send

Data Set Ready

Ring Indicator

Data Carrier Detect

Data Terminal Ready

Serial Audio Port – SSI (configurable to I2S protocol)

TxD

RxD

Transmit Serial Clock

Receive Serial Clock

Transmit Frame Sync

Receive Frame Sync

2-6

MC9328MX1 Reference Manual

MOTOROLA

BT1

BT2

BT3

BT4

BT5

BT6

BT7

R1B

R2A

R2B

RVP

RVM

AVDD

AGND

UIN

UIP

PX1

PY1

PX2

PY2

R1A

Signal Name

I2C_SCL

I2C_SDA

PWMO

Signal Descriptions

Table 2-1. MC9328MX1 Signal Descriptions (Continued)

Function/Notes

I

2

C

I

2

C Clock

I

2

C Data

PWM

PWM Output

ASP

Positive U analog input (for low voltage, temperature measurement)

Negative U analog input (for low voltage, temperature measurement)

Positive pen-X analog input

Positive pen-Y analog input

Negative pen-X analog input

Negative pen-Y analog input

Positive resistance input (a)

Positive resistance input (b)

Negative resistance input (a)

Negative resistance input (b)

Positive reference for pen ADC

Negative reference for pen ADC

Analog power supply

Analog ground

BlueTooth

I/O clock signal

Output

Input

Input

Output

Output

Output

MOTOROLA

Signal Descriptions and Pin Assignments

2-7

Signal Descriptions and Pin Assignments

Signal Name

BT8

BT9

BT10

BT11

BT12

BT13

TRISTATE

BTRF VDD

BTRF GND

NVDD

NVSS

AVDD

AVSS

QVDD

QVSS

SVDD

SGND

Table 2-1. MC9328MX1 Signal Descriptions (Continued)

Function/Notes

Output

Output

Output

Output

Output

Output

Sets all I/O pins to tristate; Can be used for flash loading and is pulled low for normal operations.

Power supply from external BT RFIC

Ground from external BT RFIC

Noisy Supply Pins

Noisy Supply for the I/O pins

Noisy Ground for the I/O pins

Supply Pins – Analog Modules

Supply for analog blocks

Quiet GND for analog blocks

Internal Power Supply

Power supply pins for silicon internal circuitry

GND pins for silicon internal circuitry

Substrate Supply Pins

Supply routed through substrate of package not to be bonded

Ground routed through substrate of package not to be bonded

2.2 I/O Pads Power Supply and Signal Multiplexing Scheme

This section describes detailed information about both the power supply for each I/O pin and its function multiplexing scheme. The user can reference information provided in Table 2-2 on page 2-9 to configure the power supply scheme for each device in the system (memory and external peripherals). The function multiplexing information also shown in Table 2-2 allows the user to select the function of each pin by configuring the appropriate GPIO registers when those pins are multiplexed to provide different functions.

2-8

MC9328MX1 Reference Manual

MOTOROLA

I/O Supply

Voltage

BGA

Pin

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

QVDD1

G5

H1

H4

T1

H9

H8

G4

G1

H2

H3

F3

G2

G3

F5

E4

A1

H5

F1

E3

E1

F2

F4

D2

D1

D3

E2

K8

B1

C2

C1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

I/O Pads Power Supply and Signal Multiplexing Scheme

Table 2-2. MC9328MX1 Signal Multiplexing Scheme

Primary Alternate

Signal

GPIO

Dir Mux Pull-up Signal

D21

A13

D20

VSS

QVDD1

VSS

D23

A15

D22

A14

D25

A17

D24

A16

D28

A20

D27

A19

D26

VSS

NVDD1

A18

NVDD1

A24

D31

A23

D30

A22

D29

A21

Dir

I/O

O

I/O

Static

Static

Static

I/O

O

I/O

O

I/O

O

I/O

O

I/O

Static

Static

O

I/O

O

I/O

O

I/O

O

I/O

O

Static

O

I/O

O

Pull-up

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

ETMTRACESYNC

ETMTRACECLK

ETMPIPESTAT2

ETMPIPESTAT1

ETMPIPESTAT0

ETMTRACEPKT3

ETMTRACEPKT2

ETMTRACEPKT1

ETMTRACEPKT0

O

O

O

O

O

O

O

O

O

PA0

PA31

PA30

PA29

PA28

PA27

PA26

PA25

PA24

69K

69K

69K

69K

69K

69K

69K

69K

69K

Default

A24

A23

A22

A21

A20

A19

A18

A17

A16

MOTOROLA

Signal Descriptions and Pin Assignments

2-9

Signal Descriptions and Pin Assignments

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

N2

P2

R1

M6

H6

T2

M3

P3

N3

P1

L3

M1

M2

N1

L5

K6

K5

M4

K2

L1

L4

L2

J3

K1

K4

K3

J5

J1

J4

J2

I/O Supply

Voltage

BGA

Pin

Table 2-2. MC9328MX1 Signal Multiplexing Scheme (Continued)

Primary Alternate GPIO

NVDD1

NVDD1

Signal

EB1

D9

EB2

VSS

NVDD1

A2

D11

EB0

D10

A3

D13

A5

D12

A4

D16

A8

D15

A7

D14

VSS

NVDD1

A6

NVDD1

A12

D19

A11

D18

A10

D17

A9

Dir

O

I/O

O

Static

Static

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

Static

Static

O

I/O

O

I/O

O

I/O

O

I/O

O

Static

O

I/O

O

Pull-up

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

Signal Dir Mux Pull-up

Default

2-10

MC9328MX1 Reference Manual

MOTOROLA

I/O Pads Power Supply and Signal Multiplexing Scheme

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

L6

N7

N8

M7

T8

M8

P8

R8

P7

J7

R6

P6

N6

R7

J6

M5

T6

T7

P4

P5

T5

H7

T4

N4

R4

N5

R2

R5

T3

R3

I/O Supply

Voltage

BGA

Pin

Table 2-2. MC9328MX1 Signal Multiplexing Scheme (Continued)

Primary Alternate GPIO

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

Dir

Static

O

O

O

O

I/O

O

Static

I/O

I

I/O

O

I/O

O

O

O

I/O

O

O

O

I/O

Signal

NVDD1

PA17

D1

RW

MA11

MA10

D3

BCLK

D2

VSS

D5

ECB

D4

LBA

CS3

D6

CS2

VSS

NVDD1

SDCLK

CS1

CS0

CS5

D7

CS4

A0

EB3

D8

OE

A1

I/O

Static

Static

I/O

O

O

Pull-up

69K

69K

69K

69K

69K

69K

69K

69K

Signal

CSD1

CSD0

ETMTRACEPKT7

ETMTRACEPKT6

ETMTRACEPKT5

ETMTRACEPKT4

Dir Mux

PA23

PA22

PA21

PA20

PA19

PA18

PA17

Pull-up

69K

69K

69K

69K

69K

69K

69K

Default

PA23

PA22

A0

CSD1

CSD0

ECB

LBA

BCLK

PA17

MOTOROLA

Signal Descriptions and Pin Assignments

2-11

Signal Descriptions and Pin Assignments

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

AVDD1

AVDD1

AVDD1

AVDD1

AVDD1

AVDD1

AVDD1

AVDD1

AVDD1

AVDD1

AVDD1

QVDD2

T13

P13

R15

T16

T14

T15

P11

N12

R13

P12

M10

N11

R12

M11

N10

T11

L7

T12

J8

T10

R11

P10

N9

R10

M9

L8

R9

K7

P9

T9

I/O Supply

Voltage

BGA

Pin

Table 2-2. MC9328MX1 Signal Multiplexing Scheme (Continued)

Primary Alternate GPIO

NVDD1

AVDD1

AVDD1

Signal

RESET_IN

RESET_OUT

POR

BIG_ENDIAN

BOOT3

BOOT2

BOOT1

BOOT0

TRISTATE

TRST

QVDD2

VSS

EXTAL16M

XTAL16M

NVDD1

SDWE

SDCKE0

SDCKE1

RESET_SF

CLKO

VSS

AVDD1

D0

VSS

DQM3

DQM2

DQM1

DQM0

RAS

CAS

Dir

I

I

Static

Static

I

O

I

I

I

I

I

I

I

O

O

O

Static

Static

Static

O

O

O

O

O

O

O

I/O

Static

O

O

Pull-up

69K

69K

69K

Signal Dir Mux Pull-up

Default

2-12

MC9328MX1 Reference Manual

MOTOROLA

I/O Pads Power Supply and Signal Multiplexing Scheme

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

QVDD3

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

AVDD1

AVDD1

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

K15

K16

K14

K13

K12

J15

L13

L12

L11

L10

M12

L16

L15

L14

N14

M15

M16

J10

P15

N13

M13

M14

N15

L9

N16

P14

R16

P16

K10

R14

I/O Supply

Voltage

BGA

Pin

Table 2-2. MC9328MX1 Signal Multiplexing Scheme (Continued)

Primary Alternate GPIO

Signal

CSI_D4

CSI_D3

CSI_D2

CSI_D1

CSI_D0

CSI_MCLK

PWMO

TIN

TMR2OUT

LD15

LD14

LD13

LD12

QVDD3

I2C_SDA

CSI_PIXCLK

CSI_HSYNC

CSI_VSYNC

CSI_D7

CSI_D6

CSI_D5

VSS

EXTAL32K

XTAL32K

NVDD2

TDO

TMS

TCK

TDI

I2C_SCL

Dir

O

O

O

O

O

Static

O

I

I

O

I

I

I

I

I

I

I

Static

I

I

I/O

I

I

O

I

I

I

O

Static

O

Pull-up

69K

69K

69K

Signal Dir Mux

PA12

PA11

PA10

PA9

PA16

PA15

PA14

PA13

Pull-up

PA4

PA3

PA2

PA1

PA8

PA7

PA6

PA5

PD31

PD30

PD29

PD28

PD27

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

Default

PA12

PA11

PA10

PA9

PA16

PA15

PA14

PA13

PA4

PA3

PA2

PA1

PA8

PA7

PA6

PA5

PD31

PD30

PD29

PD28

PD27

MOTOROLA

Signal Descriptions and Pin Assignments

2-13

Signal Descriptions and Pin Assignments

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

E16

D16

F14

F13

E15

E14

G11

F12

F15

J9

G13

G12

F16

H10

G16

H11

G15

G14

H14

H13

H16

H12

H15

J13

J12

J11

J16

K9

J14

K11

I/O Supply

Voltage

BGA

Pin

Table 2-2. MC9328MX1 Signal Multiplexing Scheme (Continued)

Primary Alternate GPIO

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

Signal

R2A

R2B

PX1

PY1

PX2

PY2

ACD/OE

CONTRAST

SPL_SPR

PS

CLS

REV

LSCLK

VSS

LD5

LD4

LD3

LD2

LD1

LD0

FLM/VSYNC

LP/HSYNC

VSS

NVDD2

LD11

LD10

LD9

LD8

LD7

LD6

Dir

I

I

I

I

I

I

O

O

O

Static

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

Static

Static

O

O

Pull-up Signal

UART2_DSR

UART2_RI

UART2_DCD

UART2_DTR

Dir

O

I

O

O

Mux Pull-up

PD14

PD13

PD12

PD11

PD18

PD17

PD16

PD15

PD10

PD9

PD8

PD7

PD6

PD22

PD21

PD20

PD19

PD26

PD25

PD24

PD23

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

Default

PD14

PD13

PD12

PD11

PD18

PD17

PD16

PD15

PD10

PD9

PD8

PD7

PD6

PD22

PD21

PD20

PD19

PD26

PD25

PD24

PD23

2-14

MC9328MX1 Reference Manual

MOTOROLA

I/O Pads Power Supply and Signal Multiplexing Scheme

D11

B11

C11

G10

F10

B10

F11

A12

E11

A11

A13

B13

C12

B12

D13

C13

E12

D12

E13

D14

B14

A14

B16

A16

B15

A15

D15

C16

C15

C14

I/O Supply

Voltage

BGA

Pin

Table 2-2. MC9328MX1 Signal Multiplexing Scheme (Continued)

Primary Alternate GPIO

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

QVDD4

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

BTRFVDD

BTRFVDD

BTRFVDD

BTRFVDD

BTRFVDD

BTRFVDD

BTRFVDD

BTRFVDD

BTRFVDD

BTRFVDD

BTRFVDD

BTRFVDD

Signal

BT6

BT7

BT8

BT9

BT10

BT11

QVDD4

VSS

BTRFVDD

BT1

BT2

BT3

BT4

BT5

NC

NC

NC

NC

NC

NC

RVM

RVP

R1A

R1B

VSS

AVDD2

NC

NC

UIN

UIP

I

I

O

O

O

O

O

O

O

I

I

I/O

Static

Static

Static

I

I

I

I

Dir

I

I

Static

Static

Pull-up Signal Dir Mux

PC27

PC26

PC25

PC24

PC31

PC30

PC29

PC28

PC23

PC22

PC21

Pull-up

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

Default

PC27

PC26

PC25

PC24

PC31

PC30

PC29

PC28

PC23

PC22

PC21

MOTOROLA

Signal Descriptions and Pin Assignments

2-15

Signal Descriptions and Pin Assignments

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

D7

D6

E6

B6

D5

C5

C7

F7

E7

C6

D8

B7

C8

A7

G8

B8

F8

E8

D9

A9

C9

A8

G9

F9

E9

B9

E10

D10

C10

A10

I/O Supply

Voltage

BGA

Pin

Table 2-2. MC9328MX1 Signal Multiplexing Scheme (Continued)

Primary Alternate GPIO

BTRFVDD

BTRFVDD

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

Signal

SSI_RXDAT

SSI_RXCLK

SSI_RXFS

VSS

UART2_RXD

UART2_TXD

UART2_RTS

UART2_CTS

USBD_VMO

USBD_VPO

USBD_VM

USBD_VP

USBD_SUSPND

USBD_RCV

BT12

BT13

BTRFGND

NVDD3

SPI1_MOSI

SPI1_MISO

SPI1_SS

SPI1_SCLK

SPI1_SPI_RDY

UART1_RXD

UART1_TXD

UART1_RTS

UART1_CTS

SSI_TXCLK

SSI_TXFS

SSI_TXDAT

Dir

I

I

O

O

O

I/O

I

O

I

O

I

I/O

I/O

Static

O

I/O

I/O

O

O

I

I

I

I/O

I/O

I/O

I/O

O

O

Static

Static

Pull-up Signal Dir Mux

PC20

PC19

Pull-up

69K

69K

PB27

PB26

PB25

PB24

PB31

PB30

PB29

PB28

PB23

PB22

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

PC9

PC8

PC7

PC6

PC5

PC4

PC3

PC13

PC12

PC11

PC10

PC17

PC16

PC15

PC14

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

Default

PC20

PC19

PB27

PB26

PB25

PB24

PB31

PB30

PB29

PB28

PB23

PB22

PC9

PC8

PC7

PC6

PC5

PC4

PC3

PC13

PC12

PC11

PC10

PC17

PC16

PC15

PC14

2-16

MC9328MX1 Reference Manual

MOTOROLA

I/O Pads Power Supply and Signal Multiplexing Scheme

G7

F6

G6

B4

B5

A5

A4

A6

C4

D4

B3

A3

A2

I/O Supply

Voltage

BGA

Pin

Table 2-2. MC9328MX1 Signal Multiplexing Scheme (Continued)

Primary Alternate GPIO

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

Signal

USBD_OE

USBD_AFE

VSS

NVDD4

SIM_CLK

SIM_RST

SIM_RX

SIM_TX

SIM_PD

SIM_SVEN

SD_CMD

SD_SCLK

SD_DAT3

Dir

O

O

I

I/O

O

O

Static

Static

I

O

I/O

O

I/O

Pull-up Signal

SSI_TXCLK

SSI_TXFS

SSI_TXDAT

SSI_RXDAT

SSI_RXCLK

SSI_RXFS

MS_BS

MS_SCLKO

MS_SDIO

PB15

PB14

PB13

PB12

PB11

PB19

PB18

PB17

PB16

I/O

I/O

O

O

I/O

I/O

I/O

O

I

Dir Mux

PB21

PB20

Pull-up

69K

69K

NVDD4

NVDD4

NVDD4

E5

B2

C3

SD_DAT2

SD_DAT1

SD_DAT0

I/O

I/O

I/O

MS_SCLKI

MS_PI1

MP_PI0

I

I

I

PB10

PB9

PB8

69K

69K

69K

69K

69K

(pull down)

69K

69K

69K

69K

69K

69K

69K

Default

PB21

PB20

PB10

PB9

PB8

PB15

PB14

PB13

PB12

PB11

PB19

PB18

PB17

PB16

MOTOROLA

Signal Descriptions and Pin Assignments

2-17

Signal Descriptions and Pin Assignments

2-18

MC9328MX1 Reference Manual

MOTOROLA

Chapter 3

Memory Map

This chapter describes the memory maps and the chip configuration registers of the MC9328MX1.

3.1 Memory Space

The ARM920T microprocessor implements a virtual addressing mechanism. Refer to the ARM920T

Memory Management Unit in the ARM9 technical reference manual for more information on this topic.

The ARM920T processor physical memory map can be divided according to the addresses shown in

Figure 3-1 on page 3-2.

3.1.1 Memory Map

The base address referred to in each peripheral register address is the address from this table. The exact address description of each of the peripherals is described in each peripheral section.

MOTOROLA

Memory Map

3-1

Memory Map

Base Address

$0000 0000

Double Map

Image

$000F FFFF

$0010 0000

Bootstrap

ROM

$001F FFFF

$0020 0000

Internal

Registers

$0022 6FFF

$0022 7000

Reserved

$002F FFFF

$0030 0000

$003F FFFF

$0040 0000

Embedded

SRAM

(128 KB Used)

1 MB

1 MB

156 KB

868 KB

1 MB

$0020 0000

AIPI1

$0020 FFFF

$0021 0000

AIPI2

$0021 FFFF

$0022 0000

$0022 0FFF

$0022 1000

$0022 1FFF

$0022 2000

$0022 2FFF

$0022 3000

$0022 3FFF

$0022 4000

$0022 4FFF

$0022 5000

$0022 5FFF

$0022 6000

$0022 6FFF

EIM

SDRAMC

MMA

AITC

CSI

Reserved

Reserved

64 KB

64 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

Reserved

$07FF FFFF

$0800 0000

External

(2x64 MB)

$0FFF FFFF

$1000 0000

$16FF FFFF

$1700 0000

External

(1x32 MB +

5x16 MB)

Reserved

$4FFF FFFF

$5000 0000

ARM9 Test

Registers

$5000 0FFF

$5000 1000

Reserved

$FFFF FFFF

124 MB

128 MB

112 MB

912 MB

4 KB

2815 MB

+

1020 KB

$0800 0000

CSD0

(SDRAM)

active low

$0BFF FFFF

$0C00 0000

CSD1

(SDRAM)

active low

$0FFF FFFF

$1000 0000

CS0

(Flash)

active low

$11FF FFFF

$1200 0000

$12FF FFFF

$1300 0000

$13FF FFFF

$1400 0000

$14FF FFFF

$1500 0000

$15FF FFFF

$1600 0000

$16FF FFFF

CS1

(Flash)

active low

CS2

(Ext SRAM)

active low

CS3

(Spare)

active low

CS4

(Spare)

active low

CS5

(Spare)

active low

64 MB

64 MB

32 MB

16 MB

16 MB

16 MB

16 MB

16 MB

Figure 3-1. MC9328MX1 MCU Physical Memory Map (4 Gbyte)

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

4 KB

$0020 0000

$0020 0FFF

$0020 1000

AIPI1

$0020 1FFF

$0020 2000

Watchdog

$0020 2FFF

$0020 3000

Timer1

$0020 3FFF

$0020 4000

Timer2

$0020 4FFF

$0020 5000

RTC

$0020 5FFF

$0020 6000

LCDC

$0020 6FFF

$0020 7000

UART1

$0020 7FFF

$0020 8000

UART2

$0020 8FFF

$0020 9000

PWM

$0020 9FFF

$0020 A000

DMAC

$0020 AFFF

$0020 B000

Reserved

$0020 BFFF

$0020 C000

Reserved

$0020 CFFF

$0020 D000

Reserved

$0020 DFFF

$0020 E000

Reserved

$0020 EFFF

$0020 F000

Reserved

$0020 FFFF

$0021 0000

Reserved

$0021 0FFF

$0021 1000

AIPI2

$0021 1FFF

$0021 2000

SIM

$0021 2FFF

$0021 3000

USBD

$0021 3FFF

$0021 4000

SPI 1

$0021 4FFF

$0021 5000

MMC/SDHC

$0021 5FFF

$0021 6000

ASP

$0021 6FFF

$0021 7000

BTA

$0021 7FFF

$0021 8000

I

2

C

$0021 8FFF

$0021 9000

SSI

SPI 2

$0021 9FFF

$0021 A000

MSHC

$0021 AFFF

$0021 B000

$0021 BFFF

$0021 C000

RESET/

CLOCK/CTRL

GPIO

$0021 CFFF

$0021 D000

Reserved

$0021 DFFF

$0021 E000

Reserved

$0021 EFFF

$0021 F000

$0021 FFFF

Reserved

3-2

MC9328MX1 Reference Manual

MOTOROLA

Memory Space

$0000 0000 - $000F FFFF

$0010 0000 - $001F FFFF

$0020 0000 - $0020 0FFF

$0020 1000 - $0020 1FFF

$0020 2000 - $0020 2FFF

$0020 3000 - $0020 3FFF

$0020 4000 - $0020 4FFF

$0020 5000 - $0020 5FFF

$0020 6000 - $0020 6FFF

$0020 7000 - $0020 7FFF

$0020 8000 - $0020 8FFF

$0020 9000 - $0020 9FFF

$0020 A000 - $0020 AFFF

$0020 B000 - $0020 BFFF

$0020 C000 - $0020 CFFF

$0020 D000 - $0020 DFFF

$0020 E000 - $0020 EFFF

$0020 F000 - $0020 FFFF

$0021 0000 - $0021 0FFF

$0021 1000 - $0021 1FFF

$0021 2000 - $0021 2FFF

$0021 3000 - $0021 3FFF

$0021 4000 - $0021 4FFF

$0021 5000 - $0021 5FFF

$0021 6000 - $0021 6FFF

$0021 7000 - $0021 7FFF

$0021 8000 - $0021 8FFF

$0021 9000 - $0021 9FFF

$0021 A000 - $0021 AFFF

Address

Table 3-1. MCU Memory Space (Physical Addresses)

Description

Reserved

Reserved

AIPI2

SIM

USBD

SPI 1

MMC/SDHC

ASP

BTA

I

2

C

SSI

SPI 2

MSHC

Bootstrap ROM

Reserved

AIPI1

WatchDog

TIMER1

TIMER2

RTC

LCDC

UART1

UART2

PWM

DMAC

Reserved

Reserved

Reserved

Reserved

Size

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

1 Mbyte

1 Mbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

MOTOROLA

Memory Map

3-3

Memory Map

Table 3-1. MCU Memory Space (Physical Addresses) (Continued)

Address Description Size

$0021 B000 - $0021 BFFF

$0021 C000 - $0021 CFFF

$0021 D000 - $0021 DFFF

$0021 E000 - $0021 EFFF

$0021 F000 - $0021 FFFF

$0022 0000 - $0022 0FFF

$0022 1000 - $0022 1FFF

$0022 2000 - $0022 2FFF

$0022 3000 - $0022 3FFF

$0022 4000 - $0022 4FFF

$0022 5000 - $0022 5FFF

$0022 6000 - $0022 6FFF

$0022 7000 - $002F FFFF

$0030 0000 - $003F FFFF

$0040 0000 - $07FF FFFF

$0800 0000 - $0BFF FFFF

$0C00 0000 - $0FFF FFFF

$1000 0000 - $11FF FFFF

$1200 0000 - $12FF FFFF

$1300 0000 - $13FF FFFF

$1400 0000 - $14FF FFFF

$1500 0000 - $15FF FFFF

$1600 0000 - $16FF FFFF

$1700 0000 - $4FFF FFFF

$5000 0000 - $5000 0FFF

$5000 1000 - $FFFF FFFF

RESET/CLOCK/CTRL

GPIO

Reserved

Reserved

Reserved

EIM

SDRAMC

MMA

AITC

CSI

Reserved

Reserved

Reserved

Internal SRAM (128 Kbyte used)

Reserved

External memory (CSD0)

External memory (CSD1)

External memory (CS0)

External memory (CS1)

External Memory (CS2)

External Memory (CS3)

External Memory (CS4)

External Memory (CS5)

Reserved

ARM920T Test Registers

Reserved

4 kbyte

4 kbyte

4 kbyte

4 kbyte

868 kbyte

1 Mbyte

124 Mbyte

64 Mbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

4 kbyte

64 Mbyte

32 Mbyte

16 Mbyte

16 Mbyte

16 Mbyte

16 Mbyte

16 Mbyte

912 Mbyte

4 kbyte

2815 Mbyte + 1020 kbyte

3-4

MC9328MX1 Reference Manual

MOTOROLA

Memory Space

3.1.2 On-Chip MCU Memory

One megabyte of address space is assigned to embedded SRAM, however only the first 128 Kbyte is physically populated, from address 0x00300000 to 0x0031FFFF. The last 32-bit word at 0x0031FFFC is an extending word. Reading a word at the rest of the 1 Mbyte (0x00320000

0x003FFFFC) boundary returns the same value as at the extending word.

3.1.3 Internal Register Space

Internal registers are located from 0x00200000 to 0x00224FFF. Some of the MC9328MX1 peripherals are each allocated 4 kbyte starting at address $00200000 and they are connected to the AIPI1 (AHB IP

Interface). Any ARM920T core write access to these modules will experience two wait states—that is, any write access will be a three cycle long access, and any ARM920T core read access from these modules will have one wait state—that is, any read access will be two cycle long access. The other MC9328MX1 peripherals are each allocated 4 kbyte starting at address $00210000 and they are connected to the AIPI2.

Any ARM920T core write access to these modules will have two wait states—that is, any write access will be a three cycle long access, and any ARM920T core read access from these modules will have one wait state—any read access will be two cycle long access.

4 kbyte address space beginning at 0x00220000 to 0x00220FFF is assigned for EIM internal registers.

4 kbyte address space beginning at 0x00221000 to 0x00221FFF is assigned for SDRAMC internal registers.

4 kbyte address space beginning at 0x00222000 to 0x00222FFF is assigned for MMA internal registers.

4 kbyte address space beginning at 0x00223000 to 0x00223FFF is assigned for AITC internal registers.

4 kbyte address space beginning at 0x00224000 to 0x00224FFF is assigned for CSI internal registers.

Within each 4 kbyte peripheral space, any number of architected registers may be defined (as outlined in the chapter for each peripheral), and software must explicitly address them making no assumptions regarding multiple mapping.

3.1.4 External Memory

There are 240 Mbytes of the memory map allocated for external chip access, beginning at address

$08000000. There are 8 external chip selects which are allocated 64 Mbyte each for CSD1–CSD0,

16 Mbyte each for CS5Q–CS1, and 32 Mbyte for CS0.

3.1.5 Double Map Image

The first 1 Mbyte system address space (starting at address $0) is defined as double map image space. This address space is mapped to the first 1 Mbyte of boot ROM upon power up. In MC9328MX1 the boot ROM can be either SyncFlash, CS0, or Bootstrap ROM. After system power up, reading or writing to the double map space ($0000,0000 to $000F,FFFF) is the same as reading or writing to the first 1 Mbyte of the selected boot ROM which is controlled by the configuration of BOOT [3:0] input pins.

MOTOROLA

Memory Map

3-5

Memory Map

3.2 Internal Registers

The internal registers in the MC9328MX1 are listed in Table 3-2.

Table 3-2. MC9328MX1 Internal Registers Sorted by Address

Module Name Address Name Description

RTC

RTC

RTC

RTC

Timer 2

Timer 2

Timer 2

Timer 2

RTC

RTC

RTC

Timer 1

Timer 1

Timer 1

Timer 1

Timer 1

Timer 1

Timer 2

Timer 2

AIPI1

AIPI1

AIPI1

AIPI1

AIPI1

Watchdog

Watchdog

Watchdog

0x00203008

0x0020300C

0x00203010

0x00203014

0x00204000

0x00204004

0x00204008

0x0020400C

0x00204010

0x00204014

0x00204018

0x00200000

0x00200004

0x00200008

0x0020000C

0x00200010

0x00201000

0x00201004

0x00201008

0x00202000

0x00202004

0x00202008

0x0020200C

0x00202010

0x00202014

0x00203000

0x00203004

TCMP2

TCR2

TCN2

TSTAT2

HOURMIN

SECONDS

ALRM_HM

ALRM_SEC

RCCTL

RTCISR

RTCIENR

TCTL1

TPRER1

TCMP1

TCR1

TCN1

TSTAT1

TCTL2

TPRER2

PSR0_1

PSR1_1

PAR_1

PCR_1

TSR_1

WCR

WSR

WSTR

AIPI1 Peripheral Size Register 0

AIPI1 Peripheral Size Register 1

AIPI1 Peripheral Access Register

AIPI1 Peripheral Control Register

AIPI1 Time-Out Status Register

Watchdog Control Register

Watchdog Service Register

Watchdog Status Register

Timer 1 Control Register

Timer 1 Prescaler Register

Timer 1 Compare Register

Timer 1 Capture Register

Timer 1 Counter Register

Timer 1 Status Register

Timer 2 Control Register

Timer 2 Prescaler Register

Timer 2 Compare Register

Timer 2 Capture Register

Timer 2 Counter Register

Timer 2 Status Register

RTC Hours and Minutes Counter Register

RTC Seconds Counter Register

RTC Hours and Minutes Alarm Register

RTC Seconds Alarm Register

RTC Control Register

RTC Interrupt Status Register

RTC Interrupt Enable Register

3-6

MC9328MX1 Reference Manual

MOTOROLA

Internal Registers

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

LCDC

LCDC

LCDC

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

RTC

RTC

RTC

LCDC

LCDC

LCDC

LCDC

LCDC

0x00205034

0x00205038

0x00205040

0x00206000

0x00206004

0x00206008

0x0020600C

0x00206010

0x00206014

0x00206018

0x0020601C

0x00206020

0x00206024

0x0020401C

0x00204020

0x00204024

0x00205000

0x00205004

0x00205008

0x0020500C

0x00205010

0x00205014

0x00205018

0x0020501C

0x00205020

0x00205024

0x00205028

0x0020502C

0x00205030

RMCR

LCDICR

LCDISR

URX0D_1

URX1D_1

URX2D_1

URX3D_1

URX4D_1

URX5D_1

URX6D_1

URX7D_1

URX8D_1

URX9D_1

LCHCC

PCR

HCR

VCR

POS

LGPMR

PWMR

DMACR

STPWCH

DAYR

DAYALARM

SSA

SIZE

VPW

CPOS

LCWHB

Stopwatch Minutes Register

RTC Days Counter Register

RTC Day Alarm Register

Screen Start Address Register

Size Register

Virtual Page Width Register

LCD Cursor Position Register

LCD Cursor Width Height and Blink Register

LCD Color Cursor Mapping Register

Panel Configuration Register

Horizontal Configuration Register

Vertical Configuration Register

Panning Offset Register

LCD Gray Palette Mapping Register

PWM Contrast Control Register

DMA Control Register

Refresh Mode Control Register

Interrupt Configuration Register

Interrupt Status Register

UART1 Receiver Register 0

UART1 Receiver Register 1

UART1 Receiver Register 2

UART1 Receiver Register 3

UART1 Receiver Register 4

UART1 Receiver Register 5

UART1 Receiver Register 6

UART1 Receiver Register 7

UART1 Receiver Register 8

UART1 Receiver Register 9

MOTOROLA

Memory Map

3-7

Memory Map

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

0x00206068

0x0020606C

0x00206070

0x00206074

0x00206078

0x0020607C

0x00206080

0x00206084

0x00206088

0x0020608C

0x00206090

0x00206094

0x00206098

0x00206028

0x0020602C

0x00206030

0x00206034

0x00206038

0x0020603C

0x00206040

0x00206044

0x00206048

0x0020604C

0x00206050

0x00206054

0x00206058

0x0020605C

0x00206060

0x00206064

UTX10D_1

UTX11D_1

UTX12D_1

UTX13D_1

UTX14D_1

UTX15D_1

UCR1_1

UCR2_1

UCR3_1

UCR4_1

UFCR_1

USR1_1

USR2_1

UTX2D_1

UTX3D_1

UTX4D_1

UTX5D_1

UTX6D_1

UTX7D_1

UTX8D_1

UTX9D_1

URX10D_1

URX11D_1

URX12D_1

URX13D_1

URX14D_1

URX15D_1

UTX0D_1

UTX1D_1

UART1 Receiver Register 10

UART1 Receiver Register 11

UART1 Receiver Register 12

UART1 Receiver Register 13

UART1 Receiver Register 14

UART1 Receiver Register 15

UART1 Transmitter Register 0

UART1 Transmitter Register 1

UART1 Transmitter Register 2

UART1 Transmitter Register 3

UART1 Transmitter Register 4

UART1 Transmitter Register 5

UART1 Transmitter Register 6

UART1 Transmitter Register 7

UART1 Transmitter Register 8

UART1 Transmitter Register 9

UART1 Transmitter Register 10

UART1 Transmitter Register 11

UART1 Transmitter Register 12

UART1 Transmitter Register 13

UART1 Transmitter Register 14

UART1 Transmitter Register 15

UART1 Control Register 1

UART1 Control Register 2

UART1 Control Register 3

UART1 Control Register 4

UART1 FIFO Control Register

UART1 Status Register 1

UART1 Status Register 2

3-8

MC9328MX1 Reference Manual

MOTOROLA

Internal Registers

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 2

UART 2

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

UART 1

0x00207008

0x0020700C

0x00207010

0x00207014

0x00207018

0x0020701C

0x00207020

0x00207024

0x00207028

0x0020702C

0x00207030

0x00207034

0x00207038

0x0020609C

0x002060A0

0x002060A4

0x002060A8

0x002060AC

0x002060B0

0x002060B4

0x002060B8

0x002060BC

0x002060C0

0x002060C4

0x002060C8

0x002060CC

0x002060D0

0x00207000

0x00207004

URX2D_2

URX3D_2

URX4D_2

URX5D_2

URX6D_2

URX7D_2

URX8D_2

URX9D_2

URX10D_2

URX11D_2

URX12D_2

URX13D_2

URX14D_2

BIPR4_1

BMPR1_1

BMPR2_1

BMPR3_1

BMPR4_1

UTS_1

URX0D_2

URX1D_2

UESC_1

UTIM_1

UBIR_1

UBMR_1

UBRC_1

BIPR1_1

BIPR2_1

BIPR3_1

UART1 Escape Character Register

UART1 Escape Timer Register

UART1 BRM Incremental Register

UART1 BRM Modulator Register

UART1 Baud Rate Count Register

UART1 BRM Incremental Preset Register 1

UART1 BRM Incremental Preset Register 2

UART1 BRM Incremental Preset Register 3

UART1 BRM Incremental Preset Register 4

UART1 BRM Modulator Preset Register 1

UART1 BRM Modulator Preset Register 2

UART1 BRM Modulator Preset Register 3

UART1 BRM Modulator Preset Register 4

UART1 Test Register 1

UART2 Receiver Register 0

UART2 Receiver Register 1

UART2 Receiver Register 2

UART2 Receiver Register 3

UART2 Receiver Register 4

UART2 Receiver Register 5

UART2 Receiver Register 6

UART2 Receiver Register 7

UART2 Receiver Register 8

UART2 Receiver Register 9

UART2 Receiver Register 10

UART2 Receiver Register 11

UART2 Receiver Register 12

UART2 Receiver Register 13

UART2 Receiver Register 14

MOTOROLA

Memory Map

3-9

Memory Map

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

0X0020707C

0x00207080

0x00207084

0x00207088

0x0020708C

0x00207090

0x00207094

0x00207098

0x0020709C

0x002070A0

0x002070A4

0x002070A8

0x002070AC

0x0020703C

0X00207040

0X00207044

0X00207048

0X0020704C

0X00207050

0X00207054

0X00207058

0X0020705C

0X00207060

0X00207064

0X00207068

0X0020706C

0X00207070

0X00207074

0X00207078

UTX15D_2

UCR1_2

UCR2_2

UCR3_2

UCR4_2

UFCR_2

USR1_2

USR2_2

UESC_2

UTIM_2

UBIR_2

UBMR_2

UBRC_2

UTX7D_2

UTX8D_2

UTX9D_2

UTX10D_2

UTX11D_2

UTX12D_2

UTX13D_2

UTX14D_2

URX15D_2

UTX0D_2

UTX1D_2

UTX2D_2

UTX3D_2

UTX4D_2

UTX5D_2

UTX6D_2

UART2 Receiver Register 15

UART2 Transmitter Register 0

UART2 Transmitter Register 1

UART2 Transmitter Register 2

UART2 Transmitter Register 3

UART2 Transmitter Register 4

UART2 Transmitter Register 5

UART2 Transmitter Register 6

UART2 Transmitter Register 7

UART2 Transmitter Register 8

UART2 Transmitter Register 9

UART2 Transmitter Register 10

UART2 Transmitter Register 11

UART2 Transmitter Register 12

UART2 Transmitter Register 13

UART2 Transmitter Register 14

UART2 Transmitter Register 15

UART2 Control Register 1

UART2 Control Register 2

UART2 Control Register 3

UART2 Control Register 4

UART2 FIFO Control Register

UART2 Status Register 1

UART2 Status Register 2

UART2 Escape Character Register

UART2 Escape Timer Register

UART2 BRM Incremental Register

UART2 BRM Modulator Register

UART2 Baud Rate Count Register

3-10

MC9328MX1 Reference Manual

MOTOROLA

Internal Registers

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

UART 2

PWM

PWM

PWM

PWM

DMAC

DMAC

DMAC

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

UART 2

0x0020900C

0x00209010

0x00209014

0x00209018

0x0020901C

0x00209040

0x00209044

0x00209048

0x0020904C

0x00209050

0x00209054

0x00209080

0x00209084

0x002070B0

0x002070B4

0x002070B8

0x002070BC

0x002070C0

0x002070C4

0x002070C8

0x002070CC

0x002070D0

0x00208000

0x00208004

0x00208008

0x0020800C

0x00209000

0x00209004

0x00209008

DBTOSR

DRTOSR

DSESR

DBOSR

DBTOCR

WSRA

XSRA

YSRA

WSRB

XSRB

YSRB

SAR0

DAR0

UTS_2

PWMC

PWMS

PWMP

PWMCNT

DCR

DISR

DIMR

BIPR1_2

BIPR2_2

BIPR3_2

BIPR4_2

BMPR1_2

BMPR2_2

BMPR3_2

BMPR4_2

UART2 BRM Incremental Preset Register 1

UART2 BRM Incremental Preset Register 2

UART2 BRM Incremental Preset Register 3

UART2 BRM Incremental Preset Register 4

UART2 BRM Modulator Preset Register 1

UART2 BRM Modulator Preset Register 2

UART2 BRM Modulator Preset Register 3

UART2 BRM Modulator Preset Register 4

UART2 Test Register 1

PWM Control Register

PWM Sample Register

PWM Period Register

PWM Counter Register

DMA Control Register

DMA Interrupt Status Register

DMA Interrupt Mask Register

DMA Burst Time-Out Status Register

DMA Request Time-Out Status Register

DMA Transfer Error Status Register

DMA Buffer Overflow Status Register

DMA Burst Time-Out Control Register

W-Size Register A

X-Size Register A

Y-Size Register A

W-Size Register B

X-Size Register B

Y-Size Register B

Channel 0 Source Address Register

Channel 0 Destination Address Register

MOTOROLA

Memory Map

3-11

Memory Map

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

0x00209088

0x0020908C

0x00209090

0x00209094

0x00209098

0x002090C0

0x002090C4

0x002090C8

0x002090CC

0x002090D0

0x002090D4

0x002090D8

0x00209100

0x00209104

0x00209108

0x0020910C

0x00209110

0x00209114

0x00209118

0x00209140

0x00209144

0x00209148

0x0020914C

0x00209150

0x00209154

0x00209158

0x00209180

RSSR2

BLR2

RTOR2

BUCR2

SAR3

DAR3

CNTR3

CCR3

RSSR3

BLR3

RTOR3

BUCR3

SAR4

RSSR1

BLR1

RTOR1

BUCR1

SAR2

DAR2

CNTR2

CCR2

CNTR0

CCR0

RSSR0

BLR0

RTOR0

BUCR0

SAR1

DAR1

CNTR1

CCR1

Channel 0 Count Register

Channel 0 Control Register

Channel 0 Request Source Select Register

Channel 0 Burst Length Register

Channel 0 Request Time-Out Register

Channel 0 Bus Utilization Control Register

Channel 1 Source Address Register

Channel 1 Destination Address Register

Channel 1 Count Register

Channel 1 Control Register

Channel 1 Request Source Select Register

Channel 1 Burst Length Register

Channel 1 Request Time-Out Register

Channel 1 Bus Utilization Control Register

Channel 2 Source Address Register

Channel 2 Destination Address Register

Channel 2 Count Register

Channel 2 Control Register

Channel 2 Request Source Select Register

Channel 2 Burst Length Register

Channel 2 Request Time-Out Register

Channel 2 Bus Utilization Control Register

Channel 3 Source Address Register

Channel 3 Destination Address Register

Channel 3 Count Register

Channel 3 Control Register

Channel 3 Request Source Select Register

Channel 3 Burst Length Register

Channel 3 Request Time-Out Register

Channel 3 Bus Utilization Control Register

Channel 4 Source Address Register

3-12

MC9328MX1 Reference Manual

MOTOROLA

Internal Registers

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

0x00209184

0x00209188

0x0020918C

0x00209190

0x00209194

0x00209198

0x002091C0

0x002091C4

0x002091C8

0x002091CC

0x002091D0

0x002091D4

0x002091D8

0x00209200

0x00209204

0x00209208

0x0020920C

0x00209210

0x00209214

0x00209218

0x00209240

0x00209244

0x00209248

0x0020924C

0x00209250

0x00209254

0x00209258

DAR7

CNTR7

CCR7

RSSR7

BLR7

RTOR7

BUCR7

DAR6

CNTR6

CCR6

RSSR6

BLR6

RTOR6

BUCR6

SAR7

DAR5

CNTR5

CCR5

RSSR5

BLR5

RTOR5

BUCR5

SAR6

DAR4

CNTR4

CCR4

RSSR4

BLR4

RTOR4

BUCR4

SAR5

Channel 4 Destination Address Register

Channel 4 Count Register

Channel 4 Control Register

Channel 4 Request Source Select Register

Channel 4 Burst Length Register

Channel 4 Request Time-Out Register

Channel 4 Bus Utilization Control Register

Channel 5 Source Address Register

Channel 5 Destination Address Register

Channel 5 Count Register

Channel 5 Control Register

Channel 5 Request Source Select Register

Channel 5 Burst Length Register

Channel 5 Request Time-Out Register

Channel 5 Bus Utilization Control Register

Channel 6 Source Address Register

Channel 6 Destination Address Register

Channel 6 Count Register

Channel 6 Control Register

Channel 6 Request Source Select Register

Channel 6 Burst Length Register

Channel 6 Request Time-Out Register

Channel 6 Bus Utilization Control Register

Channel 7 Source Address Register

Channel 7 Destination Address Register

Channel 7 Count Register

Channel 7 Control Register

Channel 7 Request Source Select Register

Channel 7 Burst Length Register

Channel 7 Request Time-Out Register

Channel 7 Bus Utilization Control Register

MOTOROLA

Memory Map

3-13

Memory Map

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

AIPI2

AIPI2

AIPI2

AIPI2

AIPI2

SIM

SIM

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

DMAC

0x00209280

0x00209284

0x00209288

0x0020928C

0x00209290

0x00209294

0x00209298

0x002092C0

0x002092C4

0x002092C8

0x002092CC

0x002092D0

0x002092D4

0x002092D8

0x00209300

0x00209304

0x00209308

0x0020930C

0x00209310

0x00209314

0x00209318

0x00210000

0x00210004

0x00210008

0x0021000C

0x00210010

0x00211000

0x00211004

SAR10

DAR10

CNTR10

CCR10

RSSR10

BLR10

RTOR10

BUCR10

PSR0_2

PSR1_2

PAR_2

PCR_2

TSR_2

PORT_CNTL

CNTL

SAR9

DAR9

CNTR9

CCR9

RSSR9

BLR9

RTOR9

BUCR9

SAR8

DAR8

CNTR8

CCR8

RSSR8

BLR8

RTOR8

BUCR8

Channel 8 Source Address Register

Channel 8 Destination Address Register

Channel 8 Count Register

Channel 8 Control Register

Channel 8 Request Source Select Register

Channel 8 Burst Length Register

Channel 8 Request Time-Out Register

Channel 8 Bus Utilization Control Register

Channel 9 Source Address Register

Channel 9 Destination Address Register

Channel 9 Count Register

Channel 9 Control Register

Channel 9 Request Source Select Register

Channel 9 Burst Length Register

Channel 9 Request Time-Out Register

Channel 9 Bus Utilization Control Register

Channel 10 Source Address Register

Channel 10 Destination Address Register

Channel 10 Count Register

Channel 10 Control Register

Channel 10 Request Source Select Register

Channel 10 Burst Length Register

Channel 10 Request Time-Out Register

Channel 10 Bus Utilization Control Register

AIPI2 Peripheral Size Register 0

AIPI2 Peripheral Size Register 1

AIPI2 Peripheral Access Register

AIPI2 Peripheral Control Register

AIPI2Time-Out Status Register

Port Control Register

Control Register

3-14

MC9328MX1 Reference Manual

MOTOROLA

Internal Registers

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

SIM

SIM

SIM

SIM

SIM

SIM

SIM

USBD

USBD

SIM

SIM

SIM

SIM

SIM

SIM

SIM

SIM

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

0x00211008

0x0021100C

0x00211010

0x00211014

0x00211018

0x0021101C

0x00211020

0x00211024

0x00211028

0x0021102C

0x00211030

0x00211034

0x00211038

0x0021103C

0x00211040

0x00212000

0x00212004

0x00212008

0x0021200C

0x00212010

0x00212014

0x00212018

0x0021201C

0x00212024

0x00212030

0x00212034

0x00212038

0x0021203C

RCV_THRESHOLD

ENABLE

XMT_STATUS

RCV_STATUS

INT_MASK

XMT_BUF

RCV_BUF

PORT_DETECT

XMT_THRESHOLD

GUARD_CNTL

OD_CONFIG

RESET_CNTL

CHAR_WAIT

GPCNT

DIVISOR

USB_FRAME

USB_SPEC

USB_STAT

USB_CTRL

USB_DADR

USB_DDAT

USB_INTR

USB_MASK

USB_ENAB

USB_EP0_STAT

USB_EP0_INTR

USB_EP0_MASK

USB_EP0_FDAT

Receive Threshold Register

Transmit/Receive Enable Register

Transmit Status Register

Receive Status Register

Interrupt Mask Register

Port Transmit Buffer Register

Receive Buffer Register

Detect Register

Transmit Threshold Register

Transmit Guard Control Register

Open-Drain Configuration Control Register

Reset Control Register

Character Wait Timer Register

General Purpose Counter Register

Divisor Register

USB Frame Number and Match Register

USB Specification and Release Number

Register

USB Status Register

USB Control Register

USB Descriptor RAM Address Register

USB Descriptor RAM/Endpoint Buffer Data

Register

USB Interrupt Status Register

USB Interrupt Mask Register

USB Enable Register

Endpoint 0 Status/Control Register

Endpoint 0 Interrupt Status Register

Endpoint 0 Interrupt Mask Register

Endpoint 0 FIFO Data Register

MOTOROLA

Memory Map

3-15

Memory Map

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

0x00212084

0x00212088

0x00212090

0x00212094

0x00212098

0x0021209C

0x002120A0

0x002120A4

0x002120A8

0x002120AC

0x002120B0

0x002120B4

0x002120B8

0x00212040

0x00212044

0x00212048

0x0021204C

0x00212050

0x00212054

0x00212058

0x00212060

0x00212064

0x00212068

0x0021206C

0x00212070

0x00212074

0x00212078

0x0021207C

0x00212080

USB_EP1_FRDP

USB_EP1_FWRP

USB_EP2_STAT

USB_EP2_INTR

USB_EP2_MASK

USB_EP2_FDAT

USB_EP2_FSTAT

USB_EP2_FCTRL

USB_EP2_LRFP

USB_EP2_LWFP

USB_EP2_FALRM

USB_EP2_FRDP

USB_EP2_FWRP

USB_EP0_FSTAT

USB_EP0_FCTRL

USB_EP0_LRFP

USB_EP0_LWFP

USB_EP0_FALRM

USB_EP0_FRDP

USB_EP0_FWRP

USB_EP1_STAT

USB_EP1_INTR

USB_EP1_MASK

USB_EP1_FDAT

USB_EP1_FSTAT

USB_EP1_FCTRL

USB_EP1_LRFP

USB_EP1_LWFP

USB_EP1_FALRM

Endpoint 0 FIFO Status Register

Endpoint 0 FIFO Control Register

Endpoint 0 Last Read Frame Pointer Register

Endpoint 0 Last Write Frame Pointer Register

Endpoint 0 FIFO Alarm Register

Endpoint 0 FIFO Read Pointer Register

Endpoint 0 FIFO Write Pointer Register

Endpoint 1 Status/Control Register

Endpoint 1 Interrupt Status Register

Endpoint 1 Interrupt Mask Register

Endpoint 1 FIFO Data Register

Endpoint 1 FIFO Status Register

Endpoint 1 FIFO Control Register

Endpoint 1 Last Read Frame Pointer Register

Endpoint 1 Last Write Frame Pointer Register

Endpoint 1 FIFO Alarm Register

Endpoint 1 FIFO Read Pointer Register

Endpoint 1 FIFO Write Pointer Register

Endpoint 2 Status/Control Register

Endpoint 2 Interrupt Status Register

Endpoint 2 Interrupt Mask Register

Endpoint 2 FIFO Data Register

Endpoint 2 FIFO Status Register

Endpoint 2 FIFO Control Register

Endpoint 2 Last Read Frame Pointer Register

Endpoint 2 Last Write Frame Pointer Register

Endpoint 2 FIFO Alarm Register

Endpoint 2 FIFO Read Pointer Register

Endpoint 2 FIFO Write Pointer Register

3-16

MC9328MX1 Reference Manual

MOTOROLA

Internal Registers

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

USBD

0x00212104

0x00212108

0x0021210C

0x00212110

0x00212114

0x00212118

0x00212120

0x00212124

0x00212128

0x0021212C

0x00212130

0x00212134

0x00212138

0x002120C0

0x002120C4

0x002120C8

0x002120CC

0x002120D0

0x002120D4

0x002120D8

0x002120DC

0x002120E0

0x002120E4

0x002120E8

0x002120F0

0x002120F4

0x002120F8

0x002120FC

0x00212100

USB_EP4_FCTRL

USB_EP4_LRFP

USB_EP4_LWFP

USB_EP4_FALRM

USB_EP4_FRDP

USB_EP4_FWRP

USB_EP5_STAT

USB_EP5_INTR

USB_EP5_MASK

USB_EP5_FDAT

USB_EP5_FSTAT

USB_EP5_FCTRL

USB_EP5_LRFP

USB_EP3_STAT

USB_EP3_INTR

USB_EP3_MASK

USB_EP3_FDAT

USB_EP3_FSTAT

USB_EP3_FCTRL

USB_EP3_LRFP

USB_EP3_LWFP

USB_EP3_FALRM

USB_EP3_FRDP

USB_EP3_FWRP

USB_EP4_STAT

USB_EP4_INTR

USB_EP4_MASK

USB_EP4_FDAT

USB_EP4_FSTAT

Endpoint 3 Status/Control Register

Endpoint 3 Interrupt Status Register

Endpoint 3 Interrupt Mask Register

Endpoint 3 FIFO Data Register

Endpoint 3 FIFO Status Register

Endpoint 3 FIFO Control Register

Endpoint 3 Last Read Frame Pointer Register

Endpoint 3 Last Write Frame Pointer Register

Endpoint 3 FIFO Alarm Register

Endpoint 3 FIFO Read Pointer Register

Endpoint 3 FIFO Write Pointer Register

Endpoint 4 Status/Control Register

Endpoint 4 Interrupt Status Register

Endpoint 4 Interrupt Mask Register

Endpoint 4 FIFO Data Register

Endpoint 4 FIFO Status Register

Endpoint 4 FIFO Control Register

Endpoint 4 Last Read Frame Pointer Register

Endpoint 4 Last Write Frame Pointer Register

Endpoint 4 FIFO Alarm Register

Endpoint 4 FIFO Read Pointer Register

Endpoint 4 FIFO Write Pointer Register

Endpoint 5 Status/Control Register

Endpoint 5 Interrupt Status Register

Endpoint 5 Interrupt Mask Register

Endpoint 5 FIFO Data Register

Endpoint 5 FIFO Status Register

Endpoint 5 FIFO Control Register

Endpoint 5 Last Read Frame Pointer Register

MOTOROLA

Memory Map

3-17

Memory Map

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

MMC/SDHC

MMC/SDHC

MMC/SDHC

MMC/SDHC

MMC/SDHC

MMC/SDHC

MMC/SDHC

MMC/SDHC

MMC/SDHC

MMC/SDHC

MMC/SDHC

ASP

ASP

USBD

USBD

USBD

USBD

SPI 1

SPI 1

SPI 1

SPI 1

SPI 1

SPI 1

SPI 1

SPI 1

MMC/SDHC

MMC/SDHC

MMC/SDHC

MMC/SDHC

0x00214010

0x00214014

0x00214018

0x0021401C

0x00214020

0x00214024

0x00214028

0x0021402C

0x00214030

0x00214034

0x00214038

0x00215000

0x00215004

0x0021213C

0x00212140

0x00212144

0x00212148

0x00213000

0x00213004

0x00213008

0x0021300C

0x00213010

0x00213014

0x00213018

0x0021301C

0x00214000

0x00214004

0x00214008

0x0021400C

RES_TO

READ_TO

BLK_LEN

NOB

REV_NO

INT_MASK

CMD

ARGH

ARGL

RES_FIFO

BUFFER_ACCESS

ASP_PADFIFO

ASP_VADFIFO

USB_EP5_LWFP

USB_EP5_FALRM

USB_EP5_FRDP

USB_EP5_FWRP

RXDATAREG1

TXDATAREG1

CONTROLREG1

INTREG1

TESTREG1

PERIODREG1

DMAREG1

RESETREG1

STR_STP_CLK

STATUS

CLK_RATE

CMD_DAT_CONT

Endpoint 5 Last Write Frame Pointer Register

Endpoint 5 FIFO Alarm Register

Endpoint 5 FIFO Read Pointer Register

Endpoint 5 FIFO Write Pointer Register

SPI 1 Rx Data Register

SPI 1 Tx Data Register

SPI 1 Control Register

SPI 1 Interrupt Control/Status Register

SPI 1 Test Register

SPI 1 Sample Period Control Register

SPI 1 DMA Control Register

SPI 1 Soft Reset Register

MMC/SD Clock Control Register

MMC/SD Status Register

MMC/SD Clock Rate Register

MMC/SD Command and Data Control Register

MMC/SD Response Time Out Register

MMC/SD Read Time Out Register

MMC/SD Block Length Register

MMC/SD Number of Blocks Register

MMC/SD Revision Number Register

MMC/SD Interrupt Mask Register

MMC/SD Command Number Register

MMC/SD Higher Argument Register

MMC/SD Lower Argument Register

MMC/SD Response FIFO Register

MMC/SD Buffer Access Register

Pen Sample FIFO

Voice ADC Register

3-18

MC9328MX1 Reference Manual

MOTOROLA

Internal Registers

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

ASP

ASP

ASP

ASP

ASP

ASP

ASP

ASP

ASP

ASP

ASP

BTA

BTA

0x00215008

0x0021500C

0x00215010

0x00215014

0x00215018

0x0021501C

0x00215020

0x00215024

0x00215028

0x0021502C

0x00215030

0x00216000

0x00216004

0x00216008

0x0021600C

0x00216010

0x00216014

0x00216018

0x0021601C

0x00216020

0x00216024

0x00216028

0x0021602C

0x00216030

0x00216034

0x00216038

0x00216040

0x00216048

ASP_VDAFIFO

ASP_VADCOEF

ASP_ACNTLCR

ASP_PSMPLRG

ASP_ICNTLR

ASP_ISTATR

ASP_VADGAIN

ASP_VDAGAIN

ASP_VDACOEF

ASP_CLKDIV

ASP_CMPCNTL

COMMAND

STATUS

PACKET_HEADER

Voice DAC Register

Voice ADC FIR Coefficients RAM

Control Register

Pen A/D Sample Rate Control Register

Interrupt Control Register

Interrupt/Error Status Register

Voice ADC Control Register

Voice DAC Control Register

Voice DAC FIR Coefficients RAM

Clock Divide Register

Compare Control Register

Command Register

Status Register

Packet Header Register

PAYLOAD_HEADER

NATIVE_COUNT

ESTIMATED_COUNT

OFFSET_COUNT

NATIVECLK_LOW

NATIVECLK_HIGH

ESTIMATED_CLK_LOW

ESTIMATED_CLK_HIGH

Payload Header Register

Native Count Register

Estimated Count Register

Offset Count Register

Native Clock Low Register

Native Clock High Register

Estimated Clock Low Register

Estimated Clock High Register

OFFSET_CLK_LOW

OFFSET_CLK_HIGH

HECCRC_CONTROL

WHITE_CONTROL

Offset Clock Low Register

Offset Clock High Register

HECCRC Control Register

White Control Register

ENCRYPTION_CONTROL_X13

CORRELATION_TIME_SETUP

CORRELATION_TIME_STAMP

RF_GPO

Encryption Control X13 Register

Correlation Time Setup Register

Correlation Time Stamp Register

RF GPO Register

MOTOROLA

Memory Map

3-19

Memory Map

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

0x0021604C

0x00216050

0x00216054

0x00216058

0x0021605C

0x00216060

0x00216064

0x00216068

0x0021606C

0x00216070

0x00216074

0x00216078

0x0021607C

0x00216080

0x00216084

0x00216088

0x0021608C

0x00216090

0x00216094

0x00216098

0x0021609C

0x002160A0

0x002160A4

0x002160A8

0x002160AC

0x002160B0

0x002160B4

0x002160B8

PWM_RSSI

TIME_A_B

TIME_C_D

PWM_TX

RF_CONTROL

RF_STATUS

RX_TIME

TX_TIME

BAT

THRESHOLD

CORRELATION_MAX

SYNCH_WORD_0

SYNCH_WORD_1

SYNCH_WORD_2

SYNCH_WORD_3

BUF_WORD_0 (LW0)

BUF_WORD_1 (LW0)

BUF_WORD_2 (LW0)

BUF_WORD_3 (LW0)

BUF_WORD_4 (LW0)

BUF_WORD_5 (LW0)

BUF_WORD_6 (LW0)

BUF_WORD_7 (LW0)

BUF_WORD_8 (LW0)

BUF_WORD_9 (LW0)

BUF_WORD_10 (LW0)

BUF_WORD_11 (LW0)

BUF_WORD_12 (LW0)

BUF_WORD_13 (LW0)

BUF_WORD_14 (LW0)

PWM Received Signal Strength Indicator

Register

Time A & B Register

Time C & D Register

PWM TX Register

RF Control Register

RF Status Register

RX Time Register

TX Time Register

Bluetooth Application Timer Register

Threshold Register

Correlation Max Register

Synch Word 0 Register

Synch Word 1 Register

Synch Word 2 Register

Synch Word 3 Register

Buf Word 0 (LW0) Register

Buf Word 1 (LW0) Register

Buf Word 2 (LW0) Register

Buf Word 3 (LW0) Register

Buf Word 4 (LW0) Register

Buf Word 5 (LW0) Register

Buf Word 6 (LW0) Register

Buf Word 7 (LW0) Register

Buf Word 8 (LW0) Register

Buf Word 9 (LW0) Register

Buf Word 10 (LW0) Register

Buf Word 11 (LW0) Register

Buf Word 12 (LW0) Register

Buf Word 13 (LW0) Register

Buf Word 14 (LW0) Register

3-20

MC9328MX1 Reference Manual

MOTOROLA

Internal Registers

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

0x002160BC

0x002160C0

0x002160C4

0x002160C8

0x002160CC

0x002160D0

0x002160D4

0x002160D8

0x002160DC

0x002160E0

0x002160E4

0x002160E8

0x002160EC

0x002160F0

0x002160F4

0x002160F8

0x002160FC

0x00216100

0x00216104

0x0021610C

0x00216110

0x00216114

0x00216118

0x00216120

0x00216124

0x00216128

0x0021612C

0x00216130

BUF_WORD_15 (LW0)

BUF_WORD_16 (LW0)

BUF_WORD_17 (LW0)

BUF_WORD_18 (LW0)

BUF_WORD_19 (LW0)

BUF_WORD_20 (LW0)

BUF_WORD_21 (LW0)

BUF_WORD_22 (LW0)

BUF_WORD_23 (LW0)

BUF_WORD_24 (LW0)

BUF_WORD_25 (LW0)

BUF_WORD_26 (LW0)

BUF_WORD_27 (LW0)

BUF_WORD_28 (LW0)

BUF_WORD_29 (LW7)

BUF_WORD_30 (LW7)

BUF_WORD_31 (LW7)

WAKEUP_1

WAKEUP_2

WAKEUP_DELTA4

WAKEUP_4

WU_CONTROL

WU_STATUS

WU_COUNT

CLK_CONTROL

SPI_WORD0

SPI_WORD1

SPI_WORD2

SPI_WORD3

SPI_WRITE_ADDR

Buf Word 15 (LW0) Register

Buf Word 16 (LW0) Register

Buf Word 17 (LW0) Register

Buf Word 18 (LW0) Register

Buf Word 19 (LW0) Register

Buf Word 20 (LW0) Register

Buf Word 21 (LW0) Register

Buf Word 22 (LW0) Register

Buf Word 23 (LW0) Register

Buf Word 24 (LW0) Register

Buf Word 25 (LW0) Register

Buf Word 26 (LW0) Register

Buf Word 27 (LW0) Register

Buf Word 28 (LW0) Register

Buf Word 29 (LW7) Register

Buf Word 30 (LW7) Register

Buf Word 31 (LW7) Register

WakeUp 1 Register

WakeUp 2 Register

WakeUp Delta4 Register

WakeUp 4 Register

WakeUp Control Register

WakeUp Status Register

WakeUp Count Register

Clock Control Register

SPI Word0 Register

SPI Word1 Register

SPI Word2 Register

SPI Word3 Register

SPI Write Address Register

MOTOROLA

Memory Map

3-21

Memory Map

SSI

SSI

SSI

SSI

SSI

SSI

SSI

SSI

SSI

SPI 2

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

BTA

I

2

C

I

2

C

I

2

C

I

2

C

I

2

C

SSI

0x00216144

0x00216148

0x0021614C

0x00216150

0x00216160

0x00216170

0x00216174

0x00216178

0x0021617C

0x00217000

0x00217004

0x00217008

0x0021700C

0x00217010

0x00218000

0x00218004

0x00218008

0x0021800C

0x00218010

0x00218014

0x00218018

0x0021801C

0x00218020

0x00218028

0x00219000

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

BTA

BTA

BTA

0x00216134

0x00216138

0x00216140

SPI_READ_ADDR

SPI_CONTROL

SPI_STATUS

HOP0

HOP_FREQ_OUT

HOP1

HOP2

HOP3

HOP4

INTERRUPT_VECTOR

SYNC_METRIC

SYNC_FC

WORD_REVERSE

BYTE_REVERSE

IADR

IFDR

I2CR

I2CSR

I2DR

STX

SRX

SCSR

STCR

SRCR

STCCR

SRCCR

STSR

SFCSR

SOR

RXDATAREG2

SPI Read Address Register

SPI Control Register

SPI Status Register

Hop 0 (Frequency In) Register

Hop Frequency Out Register

Hop 1 (Frequency In) Register

Hop 2 (Frequency In) Register

Hop 3 (Frequency In) Register

Hop 4 (Frequency In) Register

Interrupt Vector Register

Synchronization Metric Register

Synchronize Frequency Carrier Register

Word Reverse Register

Byte Reverse Register

I

2

C Address Register

I

2

C Frequency Divider Register

I

2

C Control Register

I

2

C Status Register

I

2

C Data I/O Register

SSI Transmit Data Register

SSI Receive Data Register

SSI Control/Status Register

SSI Transmit Configuration Register

SSI Receive Configuration Register

SSI Transmit Clock Control Register

SSI Receive Clock Control Register

SSI Time Slot Register

SSI FIFO Control/Status Register

SSI Option Register

SPI 2 Rx Data Register

3-22

MC9328MX1 Reference Manual

MOTOROLA

Internal Registers

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

SPI 2

SPI 2

SPI 2

SPI 2

SPI 2

SPI 2

SPI 2

MSHC

MSHC

MSHC

MSHC

MSHC

MSHC

MSHC

MSHC

MSHC

MSHC

MSHC

PLLCLK

PLLCLK

PLLCLK

PLLCLK

PLLCLK

PLLCLK

RESET

SYS CTRL

SYS CTRL

SYS CTRL

0x0021A00A

0x0021A00C

0x0021A00E

0x0021A010

0x0021A012

0x0021B000

0x0021B004

0x0021B0008

0x0021B00C

0x0021B010

0x0021B020

0x0021B800

0x0021B804

0x0021B808

0x0021B80C

0x00219004

0x00219008

0x0021900C

0x00219010

0x00219014

0x00219018

0x0021901C

0x0021A000

0x0021A002

0x0021A004

0x0021A004

0x0021A006

0x0021A008

MSCLKD

MSDRQC

CSCR

MPCTL0

MPCTL1

SPCTL0

SPCTL1

PCDR

RSR

SIDR

FMCR

GPCR

TXDATAREG2

CONTROLREG2

INTREG2

TESTREG2

PERIODREG2

DMAREG2

RESETREG2

MSCMD

MSCS

MSTDATA

MSRDATA

MSICS

MSPPCD

MSC2

MSACD

MSFAECS

SPI 2 Tx Data Register

SPI 2 Control Register

SPI 2 Interrupt Control/Status Register

SPI 2 Test Register

SPI 2 Sample Period Control Register

SPI 2 DMA Control Register

SPI 2 Soft Reset Register

Memory Stick Command Register

Memory Stick Control/Status Register

Memory Stick Transmit FIFO Data Register

Memory Stick Receive FIFO Data Register

Memory Stick Interrupt Control/Status Register

Memory Stick Parallel Port Control/Data

Register

Memory Stick Control 2 Register

Memory Stick Auto Command Register

Memory Stick FIFO Access Error

Control/Status Register

Memory Stick Serial Clock Divider Register

Memory Stick DMA Request Control Register

Clock Source Control Register

MCU PLL Control Register 0

MCU PLL and System Clock Control Register 1

System PLL Control Register 0

System PLL Control Register 1

Peripheral Clock Divider Register

Reset Source Register

Silicon ID Register

Function Multiplexing Control Register

Global Peripheral Control Register

MOTOROLA

Memory Map

3-23

Memory Map

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

GPIO A

GPIO B

GPIO B

GPIO B

GPIO B

GPIO B

GPIO B

GPIO B

GPIO B

GPIO B

GPIO B

GPIO B

GPIO B

GPIO A

GPIO A

GPIO A

GPIO A

GPIO A

GPIO A

GPIO A

GPIO A

GPIO A

GPIO A

GPIO A

GPIO A

GPIO A

GPIO A

GPIO A

GPIO A

0x0021C040

0x0021C100

0x0021C104

0x0021C108

0x0021C10C

0x0021C110

0x0021C114

0x0021C118

0x0021C11C

0x0021C120

0x0021C124

0x0021C128

0x0021C12C

0x0021C000

0x0021C004

0x0021C008

0x0021C00C

0x0021C010

0x0021C014

0x0021C018

0x0021C01C

0x0021C020

0x0021C024

0x0021C028

0x0021C02C

0x0021C030

0x0021C034

0x0021C038

0x0021C03C

PUEN_A

DDIR_B

OCR1_B

OCR2_B

ICONFA1_B

ICONFA2_B

ICONFB1_B

ICONFB2_B

DR_B

GIUS_B

SSR_B

ICR1_B

ICR2_B

GIUS_A

SSR_A

ICR1_A

ICR2_A

IMR_A

ISR_A

GPR_A

SWR_A

DDIR_A

OCR1_A

OCR2_A

ICONFA1_A

ICONFA2_A

ICONFB1_A

ICONFB2_A

DR_A

Port A Data Direction Register

Port A Output Configuration Register 1

Port A Output Configuration Register 2

Port A Input Configuration Register A1

Port A Input Configuration Register A2

Port A Input Configuration Register B1

Port A Input Configuration Register B2

Port A Data Register

Port A GPIO In Use Register

Port A Sample Status Register

Port A Interrupt Configuration Register 1

Port A Interrupt Configuration Register 2

Port A Interrupt Mask Register

Port A Interrupt Status Register

Port A General Purpose Register

Port A Software Reset Register

Port A Pull_Up Enable Register

Port B Data Direction Register

Port B Output Configuration Register 1

Port B Output Configuration Register 2

Port B Input Configuration Register A1

Port B Input Configuration Register A2

Port B Input Configuration Register B1

Port B Input Configuration Register B2

Port B Data Register

Port B GPIO In Use Register

Port B Sample Status Register

Port B Interrupt Configuration Register 1

Port B Interrupt Configuration Register 2

3-24

MC9328MX1 Reference Manual

MOTOROLA

Internal Registers

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

GPIO C

GPIO C

GPIO C

GPIO C

GPIO C

GPIO C

GPIO D

GPIO D

GPIO D

GPIO D

GPIO D

GPIO D

GPIO D

GPIO C

GPIO C

GPIO C

GPIO C

GPIO C

GPIO C

GPIO C

GPIO C

GPIO B

GPIO B

GPIO B

GPIO B

GPIO B

GPIO C

GPIO C

GPIO C

0x0021C22C

0x0021C230

0x0021C234

0x0021C238

0x0021C23C

0x0021C240

0x0021C300

0x0021C304

0x0021C308

0x0021C30C

0x0021C310

0x0021C314

0x0021C318

0x0021C130

0x0021C134

0x0021C138

0x0021C13C

0x0021C140

0x0021C200

0x0021C204

0x0021C208

0x0021C20C

0x0021C210

0x0021C214

0x0021C218

0x0021C21C

0x0021C220

0x0021C224

0x0021C228

ICR2_C

IMR_C

ISR_C

GPR_C

SWR_C

PUEN_C

DDIR_D

OCR1_D

OCR2_D

ICONFA1_D

ICONFA2_D

ICONFB1_D

ICONFB2_D

ICONFA1_C

ICONFA2_C

ICONFB1_C

ICONFB2_C

DR_C

GIUS_C

SSR_C

ICR1_C

IMR_B

ISR_B

GPR_B

SWR_B

PUEN_B

DDIR_C

OCR1_C

OCR2_C

Port B Interrupt Mask Register

Port B Interrupt Status Register

Port B General Purpose Register

Port B Software Reset Register

Port B Pull_Up Enable Register

Port C Data Direction Register

Port C Output Configuration Register 1

Port C Output Configuration Register 2

Port C Input Configuration Register A1

Port C Input Configuration Register A2

Port C Input Configuration Register B1

Port C Input Configuration Register B2

Port C Data Register

Port C GPIO In Use Register

Port C Sample Status Register

Port C Interrupt Configuration Register 1

Port C Interrupt Configuration Register 2

Port C Interrupt Mask Register

Port C Interrupt Status Register

Port C General Purpose Register

Port C Software Reset Register

Port C Pull_Up Enable Register

Port D Data Direction Register

Port D Output Configuration Register 1

Port D Output Configuration Register 2

Port D Input Configuration Register A1

Port D Input Configuration Register A2

Port D Input Configuration Register B1

Port D Input Configuration Register B2

MOTOROLA

Memory Map

3-25

Memory Map

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

EIM

EIM

EIM

EIM

EIM

EIM

EIM

SDRAMC

SDRAMC

SDRAMC

SDRAMC

MMA

MMA

EIM

EIM

EIM

EIM

GPIO D

GPIO D

EIM

EIM

GPIO D

GPIO D

GPIO D

GPIO D

GPIO D

GPIO D

GPIO D

GPIO D

0x00220018

0x0022001C

0x00220020

0x00220024

0x00220028

0x0022002C

0x00220030

0x00221000

0x00221004

0x00221014

0x00221018

0x00222000

0x00222004

0x0021C31C

0x0021C320

0x0021C324

0x0021C328

0x0021C32C

0x0021C330

0x0021C334

0x0021C338

0x0021C33C

0x0021C340

0x00220000

0x00220004

0x00220008

0x0022000C

0x00220010

0x00220014

CS3U

CS3L

CS4U

CS4L

CS5U

CS5L

EIM

SDCTL0

SDCTL1

MISCELLANEOUS

SDRST

MMA_MAC_MOD

MMA_MAC_CTRL

SWR_D

PUEN_D

CS0U

CS0L

CS1U

CS1L

CS2U

CS2L

DR_D

GIUS_D

SSR_D

ICR1_D

ICR2_D

IMR_D

ISR_D

GPR_D

Port D Data Register

Port D GPIO In Use Register

Port D Sample Status Register

Port D Interrupt Configuration Register 1

Port D Interrupt Configuration Register 2

Port D Interrupt Mask Register

Port D Interrupt Status Register

Port D General Purpose Register

Port D Software Reset Register

Port D Pull_Up Enable Register

Chip Select 0 Upper Control Register

Chip Select 0 Lower Control Register

Chip Select 1 Upper Control Register

Chip Select 1 Lower Control Register

Chip Select 2 Upper Control Register

Chip Select 2 Lower Control Register

Chip Select 3 Upper Control Register

Chip Select 3 Lower Control Register

Chip Select 4 Upper Control Register

Chip Select 4 Lower Control Register

Chip Select 5 Upper Control Register

Chip Select 5 Lower Control Register

EIM Configuration Register

SDRAM 0 Control Register

SDRAM 1 Control Register

Miscellaneous Register

SDRAM Reset Register

MMA MAC Module Register

MMA MAC Control Register

3-26

MC9328MX1 Reference Manual

MOTOROLA

Internal Registers

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

MMA

0x00222308

0x0022230C

0x00222310

0x00222314

0x00222400

0x00222404

0x00222408

0x0022240C

0x00222410

0x00222414

0x00222418

0x0022241C

0x00222420

0x00222008

0x0022200C

0x00222010

0x00222014

0x00222018

0x0022201C

0x00222020

0x00222024

0x00222200

0x00222204

0x00222208

0x0022220C

0x00222210

0x00222214

0x00222300

0x00222304

MMA_MAC_MULT

MMA_MAC_ACCU

MMA_MAC_INTR

MMA_MAC_INTR_MASK

MMA_MAC_FIFO

MMA_MAC_FIFO_STAT

MMA_MAC_BURST

MMA_MAC_BITSEL

MMA_MAC_XBASE

MMA_MAC_XINDEX

MMA_MAC_XLENGTH

MMA_MAC_XMODIFY

MMA_MAC_XINCR

MMA_MAC_XCOUNT

MMA_MAC_YBASE

MMA_MAC_YINDEX

MMA_MAC_YLENGTH

MMA_MAC_YMODIFY

MMA_MAC_YINCR

MMA_MAC_YCOUNT

MMA_DCTCTRL

MMA_DCTVERSION

MMA_DCTIRQENA

MMA_DCTIRQSTAT

DSA_DCTSRCDATA

MMA_DCTDESDATA

MMA_DCTXOFF

MMA_DCTYOFF

MMA_DCTXYCNT

MMA MAC Multiply Counter Register

MMA MAC Accumulate Counter Register

MMA MAC Interrupt Register

MMA MAC Interrupt Mask Register

MMA MAC FIFO Register

MMA MAC FIFO Status Register

MMA MAC Burst Count Register

MMA MAC Bit Select Register

MMA MAC X Base Address Register

MMA MAC X Index Register

MMA MAC X Length Register

MMA MAC X Modify Register

MMA MAC X Increment Register

MMA MAC X Count Register

MMA MAC Y Base Address Register

MMA MAC Y Index Register

MMA MAC Y Length Register

MMA MAC Y Modify Register

MMA MAC Y Increment Register

MMA MAC Y Count Register

DCT/iDCT Control Register

DCT/iDCT Version Register

DCT/iDCT IRQ Enable Register

DCT/iDCT IRQ Status Register

DCT/iDCT Source Data Address

DCT/iDCT Destination Data Address

DCT/iDCT X-Offset Address

DCT/iDCT Y-Offset Address

DCT/iDCT XY Count

MOTOROLA

Memory Map

3-27

Memory Map

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

AITC

MMA

MMA

AITC

AITC

0x00223038

0x0022303C

0x00223040

0x00223044

0x00223048

0x0022304C

0x00223050

0x00223054

0x00223058

0x0022305C

0x00223060

0x00223064

0x00222424

0x00222500

0x00223000

0x00223004

0x00223008

0x0022300C

0x00223010

0x00223014

0x00223018

0x0022301C

0x00223020

0x00223024

0x00223028

0x0022302C

0x00223030

0x00223034

NIPRIORITY1

NIPRIORITY0

NIVECSR

FIVECSR

INTSRCH

INTSRCL

INTFRCH

INTFRCL

NIPNDH

NIPNDL

FIPNDH

FIPNDL

MMA_DCTSKIP

MMA_DCTFIFO

INTCNTL

NIMASK

INTENNUM

INTDISNUM

INTENABLEH

INTENABLEL

INTTYPEH

INTTYPEL

NIPRIORITY7

NIPRIORITY6

NIPRIORITY5

NIPRIORITY4

NIPRIORITY3

NIPRIORITY2

DCT/iDCT Skip Address

DCT/iDCT Data FIFO

Interrupt Control Register

Normal Interrupt Mask Register

Interrupt Enable Number Register

Interrupt Disable Number Register

Interrupt Enable Register High

Interrupt Enable Register Low

Interrupt Type Register High

Interrupt Type Register Low

Normal Interrupt Priority Level Register 7

Normal Interrupt Priority Level Register 6

Normal Interrupt Priority Level Register 5

Normal Interrupt Priority Level Register 4

Normal Interrupt Priority Level Register 3

Normal Interrupt Priority Level Register 2

Normal Interrupt Priority Level Register 1

Normal Interrupt Priority Level Register 0

Normal Interrupt Vector and Status Register

Fast Interrupt Vector and Status Register

Interrupt Source Register High

Interrupt Source Register Low

Interrupt Force Register High

Interrupt Force Register Low

Normal Interrupt Pending Register High

Normal Interrupt Pending Register Low

Fast Interrupt Pending Register High

Fast Interrupt Pending Register Low

3-28

MC9328MX1 Reference Manual

MOTOROLA

Internal Registers

Table 3-2. MC9328MX1 Internal Registers Sorted by Address (Continued)

Module Name Address Name Description

CSI

CSI

CSI

CSI

CSI

0x00224000

0x00224004

0x00224008

0x0022400C

0x00224010

CSICR1

CSICR2

CSISR

CSISTATR

CSIRXR

CSI Control Register 1

CSI Control Register 2

CSI Status Register 1

CSI Statistic FIFO Register 1

CSI RxFIFO Register 1

MOTOROLA

Memory Map

3-29

Memory Map

3-30

MC9328MX1 Reference Manual

MOTOROLA

Chapter 4

ARM920T Processor

This chapter describes the operational features of the ARM920T™ high-performance processor that includes an overall summary of both the ARM920T processor core and the Thumb® instruction set as well as the operational modes. For detailed technical and programming information about the ARM920T processor refer to the

ARM920T Technical Reference Manual

(ARM Limited: 2001, order number

DDI 0151C).

4.1 Introduction

The ARM920T processor is a high-performance 32-bit RISC integer processor macrocell combining an

ARM9TDMI™ core with:

• 16 kbit instruction and 16 kbit data caches

• Instruction and data Memory Management Units (MMUs)

• Write buffer

• AMBA™ (Advanced Microprocessor Bus Architecture) bus interface

• Embedded Trace Macrocell (ETM) interface.

An enhanced ARM® architecture v4 MMU implementation provides translation and access permission checks for instruction and data addresses. The ARM920T high-performance processor solution gives considerable savings in chip complexity and area, chip system design, and power consumption. The

ARM920T processor is 100% user code binary compatible with ARM7TDMI

®

, and backwards compatible with the ARM7™ Thumb® Family and the StrongARM

®

processor families, giving designers software-compatible processors with a range of price/performance points from 60 MIPS to 200+ MIPS.

MOTOROLA

ARM920T Processor

4-1

ARM920T Processor

Figure 4-1. ARM920T Core Functional Block Diagram

4.2 ARM920T Macrocell

The ARM920T macrocell is based on the ARM9TDMI™ Harvard architecture processor core, with an efficient 5-stage pipeline. The architecture of the processor core or integer unit is described in more detail later in this chapter.

To reduce the effect of main memory bandwidth and latency on performance, the ARM920T processor includes:

• Instruction cache

• Data cache

• MMU

• TLBs

• Write buffer

• Physical address TAG RAM

4.2.1 Caches

Two 16 kbyte caches are implemented, one for instructions, the other for data, both with an 8-word line size. A 32-bit data bus connects each cache to the ARM9TDMI core allowing a 32-bit instruction to be fetched and fed into the instruction Decode stage of the pipeline at the same time as a 32-bit data access for the Memory stage of the pipeline.

4-2

MC9328MX1 Reference Manual

MOTOROLA

ARM920T Macrocell

4.2.2 Cache Lock-Down

Cache lock-down is provided to allow critical code sequences to be locked into the cache to ensure predictability for real-time code. The cache replacement algorithm can be selected by the operating system as either pseudo random or round-robin. Both caches are 64-way set associative. Lock-down operates on a per-set basis.

4.2.3 Write Buffer

The ARM920T processor also incorporates a 16-entry write buffer, to avoid stalling the processor when writes to external memory are performed.

4.2.4 PATAG RAM

The ARM920T processor implements PATAG RAM to perform write-backs from the data cache. The physical address of all the lines held in the data cache is stored by the PATAG memory, removing the need for address translation when evicting a line from the cache.

4.2.5 MMUs

The standard ARM920T processor implements an enhanced ARM v4 memory management unit (MMU) to provide translation and access permission checks for the instruction and data address ports of the

ARM9TDMI core.

The MMU features are:

• Standard ARM9 v4 MMU mapping sizes, domains, and access protection scheme

• Mapping sizes are 1 Mbyte sections, 64 kbyte large pages, 4 kbyte small pages, and new 1 kbyte tiny pages

• Access permissions for sections

• Access permissions for large pages and small pages can be specified separately for each quarter of the page (these quarters are called subpages)

• 16 domains implemented in hardware

• 64-entry instruction TLB and 64-entry data TLB

• Hardware page table walks

• Round-robin replacement algorithm (also called cyclic).

4.2.6 System Controller

The system controller oversees the interaction between the instruction and data caches and the Bus

Interface Unit. It controls internal arbitration between the blocks and stalls appropriate blocks when required.

The system controller arbitrates between instruction and data access to schedule single or simultaneous requests to the MMUs and the Bus Interface Unit. The system controller receives acknowledgement from each resource to allow execution to continue.

The physical address of all the lines held in the data cache is stored by the PATAG memory, removing the need for address translation when evicting a line from the cache.

MOTOROLA

ARM920T Processor

4-3

ARM920T Processor

4.2.7 Control Coprocessor (CP15)

The CP15 allows configuration of the caches, the write buffer, and other ARM920T processor options.

Several registers within CP15 are available for program control, providing access to features such as:

• Invalidate whole TLB using CP15

• Invalidate TLB entry, selected by modified virtual address, using CP15

• Independent lock-down of instruction TLB and data TLB using CP15 register 10

• Big or little-endian operation

• Low-power state

• Memory partitioning and protection

• Page table address

• Cache and TLB maintenance operations.

4.3 ARMv4T Architecture

The following sections summarize the registers and instruction sets of the ARMv4T architecture.

4.3.1 Registers

The ARM920T processor core consists of a 32-bit data path and associated control logic. This data path contains 31 general purpose registers, coupled to a full shifter, Arithmetic Logic Unit, and multiplier. At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing. Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention) as a stack pointer.

4.3.2 Modes and Exception Handling

All exceptions have banked registers for R14 and R13. After an exception, R14 holds the return address for exception processing. This address is used both to return after the exception is processed and to address the instruction that caused the exception.

R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without the need to save or restore these registers.

A seventh processing mode, System mode, does not have any banked registers. It uses the User mode registers. System mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions.

4.3.3 Status Registers

All other processor states are held in status registers. The current operating processor status is in the

Current Program Status Register (CPSR). The CPSR holds:

• Four ALU flags (Negative, Zero, Carry, and Overflow)

• Two interrupt disable bits (one for each type of interrupt)

4-4

MC9328MX1 Reference Manual

MOTOROLA

Four Classes of Instructions

• A bit to indicate ARM9 or Thumb execution

• Five bits to encode the current processor mode.

All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task immediately before the exception occurred.

4.3.4 Exception Types

ARM9TDMI core supports five types of exception, and a privileged processing mode for each type. The types of exceptions are:

• Fast interrupt (FIQ)

• Normal interrupt (IRQ)

• Memory aborts (used to implement memory protection or virtual memory)

• Attempted execution of an undefined instruction

• Software interrupts (SWIs).

4.3.5 Conditional Execution

All ARM9 instructions (with the exception of BLX) are conditionally executed. Instructions optionally update the four condition code flags (Negative, Zero, Carry, and Overflow) according to their result.

Subsequent instructions are conditionally executed according to the status of flags. Fifteen conditions are implemented.

4.4 Four Classes of Instructions

The ARM9 and Thumb instruction sets can be divided into four broad classes of instruction:

• Data processing instructions

• Load and store instructions

• Branch instructions

• Coprocessor instructions.

4.4.1 Data Processing Instructions

The data processing instructions operate on data held in general purpose registers. Of the two source operands, one is always a register. The other has two basic forms:

• An immediate value

• A register value optionally shifted

If the operand is a shifted register, the shift amount might have an immediate value or the value of another register. Four types of shift can be specified. Most data processing instructions can perform a shift followed by a logical or arithmetic operation. Multiply instructions come in two classes:

• Normal, 32-bit result

• Long, 32-bit result variants.

Both types of multiply instruction can optionally perform an accumulate operation.

MOTOROLA

ARM920T Processor

4-5

ARM920T Processor

4.4.2 Load and Store Instructions

The second class of instruction is load and store instructions. These instructions come in two main types:

• Load or store the value of a single register

• Load and store multiple register values.

Load and store single register instructions can transfer a 32-bit word, a 16-bit halfword and an 8-bit byte between memory and a register. Byte and halfword loads might be automatically zero extended or sign extended as they are loaded. Swap instructions perform an atomic load and store as a synchronization primitive.

4.4.2.1 Addressing Modes

Load and store instructions have three primary addressing modes:

• Offset

• Pre-indexed

• Post-indexed.

They are formed by adding or subtracting an immediate or register based offset to or from a base register.

Register-based offsets can also be scaled with shift operations. Pre-indexed and post-indexed addressing modes update the base register with the base plus offset calculation. As the PC is a general purpose register, a 32-bit value can be loaded directly into the PC to perform a jump to any address in the 4 Gbyte memory space.

4.4.2.2 Block Transfers

Load and store multiple instructions perform a block transfer of any number of the general purpose registers to or from memory. Four addressing modes are provided:

• Pre-increment addressing

• Post-increment addressing

• Pre-decrement addressing

• Post-decrement addressing.

The base address is specified by a register value (that can be optionally updated after the transfer). As the subroutine return address and the PC values are in general-purpose registers, very efficient subroutine calls can be constructed.

4.4.3 Branch Instructions

As well as allowing any data processing or load instruction to change control flow (by writing the PC) a standard branch instruction is provided with 24-bit signed offset, allowing forward and backward branches of up to 32 Mbyte.

4.4.3.1 Branch with Link

There is a Branch with Link (BL) that allows efficient subroutine calls. BL preserves the address of the instruction after the branch in R14 (the Link Register, or LR). This allows a move instruction to put the LR in to the PC and return to the instruction after the branch.

4-6

MC9328MX1 Reference Manual

MOTOROLA

The ARM9 Instruction Set

The third type of branch (BX and BLX) switches between ARM9 and Thumb instruction sets optionally with the return address preserving link option.

4.4.4 Coprocessor Instructions

There are three types of coprocessor instructions:

• Coprocessor data processing instructions invoke a coprocessor-specific internal operation

• Coprocessor register transfer instructions allow a coprocessor value to be transferred to or from an

ARM920T processor register

• Coprocessor data transfer instructions transfer coprocessor data to or from memory, where the

ARM920T calculates the address of the transfer.

4.5 The ARM9 Instruction Set

The instruction set used by the ARM920T processor is summarized in Table 4-1.

Table 4-1. ARM920T Instruction Set

Mnemonic

MOV

ADD

SUB

RSB

CMP

TST

AND

FOR

MUL

SMULL

Operation

Move

Add

Subtract

Reverse Subtract

Compare

Test

Logical AND

Logical Exclusive OR

Multiply

Sign Long Multiply

Mnemonic

MVN

ADC

SBC

RSC

CMN

TEQ

BIC

ORR

MLA

SMLAL

UMULL

CLZ

MRS

B

BL

BX

Unsigned Long Multiply

Count Leading Zeroes

Move From Status Register

Branch

Branch and Link

Branch and Exchange

UMLAL

BKPT

MSR

BLX

SWI

Operation

Move Not

Add with Carry

Subtract with Carry

Reverse Subtract with Carry

Compare Negated

Test Equivalence

Bit Clear

Logical (inclusive) OR

Multiply Accumulate

Signed Long Multiply

Accumulate

Unsigned Long Multiply

Accumulate

Breakpoint

Move to Status Register

Branch and Link and

Exchange

Software Interrupt

MOTOROLA

ARM920T Processor

4-7

ARM920T Processor

Mnemonic

LDR

LDRH

LDRB

LDRSH

LDMIA

SWP

CDP

MRC

LDC

Table 4-1. ARM920T Instruction Set (Continued)

Operation Mnemonic

Load Word

Load Halfword

Load Byte

Load Signed Halfword

Load Multiple

Swap Word

Coprocessor Data

Processing

Move From Coprocessor

Load To Coprocessor

STR

STRH

STRB

LDRSB

STMIA

SWPB

MCR

STC

Operation

Store Word

Store Halfword

Store Byte

Load Signed Byte

Store Multiple

Swap Byte

Move to Coprocessor

Store From Coprocessor

4.6 The ARM Thumb Instruction Set

The ARM Thumb instruction set is summarized in Table 4-2.

Table 4-2. ARM Thumb Instruction Set

Mnemonic Operation Mnemonic

CMP

TST

AND

FOR

MOV

ADD

SUB

RSB

LSL

ASR

MUL

B

BL

Move

Add

Subtract

Reverse Subtract

Compare

Test

Logical AND

Logical Exclusive OR

Logical Shift Left

Arithmetic Shift Right

Multiply

Unconditional Branch

Branch and Link

CMN

NEG

BIC

ORR

MVN

ADC

SBC

RSC

LSR

ROR

BKPT

Bcc

BLX

BX Branch and Exchange SWI

Operation

Move Not

Add with Carry

Subtract with Carry

Reverse Subtract with Carry

Compare Negated

Negate

Bit Clear

Logical (inclusive) OR

Logical Shift Right

Rotate Right

Breakpoint

Conditional Branch

Branch and Link and

Exchange

Software Interrupt

4-8

MC9328MX1 Reference Manual

MOTOROLA

Mnemonic

LDR

LDRH

LDRB

LDRSH

LDMIA

PUSH

The ARM Thumb Instruction Set

Table 4-2. ARM Thumb Instruction Set (Continued)

Operation Mnemonic

Load Word

Load Halfword

Load Byte

Load Signed Halfword

Load Multiple

Push Registers to stack

STR

STRH

STRB

LDRSB

STMIA

POP

Operation

Store Word

Store Halfword

Store Byte

Load Signed Byte

Store Multiple

Pop Registers from stack

4.6.1 ARM920T Modes and Registers

The modes and registers of the ARM920T processor are shown in Table 4-3.

Table 4-3. Register Availability by Mode

User and

System Modes

R8

R9

R10

R11

R12

R13

R14

PC

CPSR

R4

R5

R6

R7

R0

R1

R2

R3

Supervisor

Mode

Abort Mode

R8

R9

R10

R11

R12

R13_SVC

R14_SVC

PC

R4

R5

R6

R7

R0

R1

R2

R3

CPSR

SPSR_SVC

CPSR

SPSR_ABORT

= Mode-specific banked registers

R4

R5

R6

R7

R0

R1

R2

R3

R8

R9

R10

R11

R12

R13_ABORT

R14_ABORT

PC

Undefined

Mode

R8

R9

R10

R11

R12

R13_UNDEF

R14_UNDEF

PC

CPSR

SPSR_UNDEF

R4

R5

R6

R7

R0

R1

R2

R3

Interrupt Mode

R8

R9

R10

R11

R12

R13_IRQ

R14_IRQ

PC

CPSR

SPSR_IRQ

R4

R5

R6

R7

R0

R1

R2

R3

Fast Interrupt

Mode

R8_FIQ

R9_FIQ

R10_FIQ

R11_FIQ

R12_FIQ

R13_FIQ

R14_FIQ

PC

CPSR

SPSR_FIQ

R4

R5

R6

R7

R0

R1

R2

R3

MOTOROLA

ARM920T Processor

4-9

ARM920T Processor

4-10

MC9328MX1 Reference Manual

MOTOROLA

Chapter 5

Embedded Trace Macrocell (ETM)

The MC9328MX1 is equipped with an ARM9 Embedded Trace Macrocell

(ETM9) module for real time debugging which is a great help to a system designer because the MC9328MX1 is a highly integrated processor, a very limited number of pins are available for debug purposes. ETM signals in MC9328MX1 are multiplexed with other function pins. This chapter contains a brief summary of the ETM features, for details of ETM operation, please refer to the

ETM9 Technical Reference Manual

Rev.2a (ARM Limited:

2001, order number DDI0157E).

5.1 Introduction to the ETM

The ETM provides instruction and data trace for the ARM9™ family of microprocessors. This document describes the interface between an ARM Thumb® family processor and the ETM. For details of the interface between an ARM7™ processor and ETM7, refer to the

ETM7 Technical Reference Manual

Rev.1 (ARM Limited: 2001, order number DDI0158D).

The block diagram of the ETM is shown in

Figure 5-1.

MOTOROLA

Figure 5-1. ETM Block Diagram

Embedded Trace Macrocell (ETM)

5-1

Embedded Trace Macrocell (ETM)

5.2 Programming and Reading ETM Registers

All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the

ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit shift register comprising:

• 32-bit data field

• 7-bit address field

• A read/write bit

The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field, and 1 into the read/write bit.

A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.

For further details of ETM registers, see the Embedded Trace Macrocell specification.

5.3 Pin Configuration for ETM

The ETM module uses 13 pins on the MC9328MX1. These pins are multiplexed with other functions on the device, and must be configured for ETM operation. Table 5-1 identifies the pin configuration, however, only the 5 pins of the 13 that are multiplexed are shown.

NOTE:

The user must ensure that the data direction bits in the GPIO are set to the correct direction for proper operation. See Section 32.5.1, “Data Direction

Registers,” on page 32-9 for details.

Table 5-1. ETM Pin Configuration

Pin Setting Configuration Procedure

ETMTRACESYNC Alternate function of

GPIO Port A [0]

ETMTRACECLK

ETMPIPESTAT

[2:0]

ETMTRACEPKT

[7:4]

ETMTRACEPKT

[3:0]

Alternate function of

GPIO Port A [31]

Alternate function of

GPIO Port A [30:28]

Alternate function of

GPIO Port A [20:17]

Alternate function of

GPIO Port A [27:24]

1. Clear bit 0 of Port A GPIO In Use Register (GIUS_A)

2. Set bit 0 of Port A General Purpose Register (GPR_A)

1. Clear bit 31 of Port A GPIO In Use Register (GIUS_A)

2. Set bit 31 of Port A General Purpose Register (GPR_A)

1. Clear bits [30:28] of Port A GPIO In Use Register (GIUS_A)

2. Set bits [30:28] of Port A General Purpose Register (GPR_A)

1. Clear bits [20:17] of Port A GPIO In Use Register (GIUS_A)

2. Set bits [20:17] of Port A General Purpose Register (GPR_A)

1. Clear bits [27:24] of Port A GPIO In Use Register (GIUS_A)

2. Set bits [27:24] of Port A General Purpose Register (GPR_A)

5-2

MC9328MX1 Reference Manual

MOTOROLA

Chapter 6

Reset Module

The reset module controls or distributes all of the system reset signals used by the MC9328MX1. This chapter provides a detailed description of the operation of this module.

6.1 Functional Description of the Reset Module

A simplified block diagram of the reset module is shown in Figure 6-1. The reset module generates two distinct events—a global reset and an ARM920T processor reset.

TRST

POR

CLK32

300 ms

Counter

RESET_POR

CLK32

CLK32

CLK32

HCLK

RESET_IN

Watchdog

Timer

4-Cycle

Qualifier

WAT_RESET

Rising

Edge

Detector

CORE_TRST

7-Cycle

Stretcher

RESET_DRAM

14-Cycle

Stretcher

HRESET

Sync

Logic

HARD_ASYN_RESET

RSR

IP Bus

JTAG/ETM

DRAM

Controller

ARM9/

Watchdog

Timer

RESET_OUT

All Modules

Except

Watchdog

Timer

Figure 6-1. Reset Module Block Diagram

6.1.1 Global Reset

A global reset simultaneously asserts three reset signals: HRESET, RESET_DRAM, and CORE_TRST.

These signals remain asserted for 14 CLK32 cycles. The RESET_DRAM signal is deasserted 7 CLK32 cycles before HRESET and HARD_ASYN_RESET. This 7-cycle period provides the DRAM with time to execute any necessary self-refresh operations. The timing diagram in Figure 6-2 on page 6-2 shows the relationship of the reset signal timings. See Table 6-1 for reset module signal and pin definitions.

There is one source capable of generating a global reset: A high condition on the POR pin for at least

4

×

32 kHz clocks when the 32 kHz crystal oscillator is running.

MOTOROLA

Reset Module

6-1

Reset Module

The following signal conditions are not capable of generating a global reset, however they reset the

ARM920T core:

• An external qualified low condition on the RESET_IN pin

• A low condition on WAT_RESET

NOTE:

Due to the asynchronous nature of the RESET signal, the time period required to qualify the signal may vary, and the HRESET timing relative to the rising edge of RESET is also affected. A RESET signal shorter than

3 CLK32 cycles will not be qualified, a RESET signal equal to or longer than 4 CLK32 cycles will always be qualified, and any period length that is more than 3 and less than 4 CLK32 cycles is undefined.

IMPORTANT:

POR is the reset signal for all the reset module flip-flops. For this reason, an external reset signal is qualified if it lasts more than 4 CLK32 cycles when POR is deasserted.

POR

RESET_POR

RESET_DRAM

HRESET

(RESET_OUT)

CLK32

HCLK

300 ms

7 cycles @ CLK32

14 cycles @ CLK32

Figure 6-2. DRAM and Internal Reset Timing Diagram

6.1.2 ARM920T Processor Reset

Any qualified global reset signal resets the ARM920T processor and all related peripherals to their default state. After the internal reset is deasserted, the ARM920T processor begins fetching code from the internal bootstrap ROM, sync flash, or CS0 space. The memory location of the fetch depends on the configuration of the BOOT pins and the value of the TEST pin on the rising edge of HRESET (see Section 8.2, “System

Boot Mode Selection,” on page 8-7).

6-2

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Signal Name

CLK32

POR IN

RESET

TRST

WAT_RESET

CORE_TRST

HARD_ASYN_RESET

HRESET

RESET_DRAM

Table 6-1. Reset Module Pin and Signal Descriptions

Direction Signal Description

IN

IN

IN

IN

OUT

OUT

OUT

OUT

32 kHz Clock

—A 32 kHz clock signal derived from the input crystal oscillator circuit in the PLL.

Power-On Reset

—An internal active high Schmitt trigger signal from the

POR pin. The POR signal is normally generated by an external RC circuit designed to detect a power-up event.

Reset

—An external active low Schmitt trigger signal from the

RESET_IN pin. When this signal goes active, all modules (except the reset module and the clock control module) are reset.

Test Reset Pin

—An external active low signal from the TRST pin. The Test

Reset Pin is used to asynchronously initialize the JTAG controller.

Watchdog Timer Reset

—An active low signal generated by the watchdog timer when a time-out period has expired.

Core Test Reset

—An active low signal that resets the JTAG module and the ETM.

Hard Asynchronous Reset

—An active low signal that resets all peripheral modules except the watchdog timer module. The rising edge of this signal is synchronous with HCLK.

Hard Reset

—An active low signal that resets the ARM920T processor and the watchdog timer module.This signal is deasserted during the low phase of HCLK. This signal also appears on the RESET_OUT pin of the

MC9328MX1.

DRAM Reset

—An active low signal that resets the DRAM controller.

6.2 Programming Model

The Reset Source Register (RSR), the only register in the reset module, can be written to or read by the

ARM920T processor through the IP bus interface.

6.2.1 Reset Source Register (RSR)

The Reset Source Register is a 16-bit read-only register used by the ARM920T processor to determine the source of the last MC9328MX1. hardware reset. The source of the last hardware reset is defined in

Table 6-2 and Table 6-3 on page 6-4.

If several sources’ signals overlap and if the signals are released during the same CLK32 cycle (which also causes the assertion of the RESET_OUT signal), only the highest-priority event is registered by the RSR using the following priority order:

1. POR signal

2. Qualified external reset signal

3. Watchdog signal

Otherwise, the last signal that is released is honored.

MOTOROLA

Reset Module

6-3

Reset Module

RSR

BIT

Reset Source Register

30 29 28 27 26 25 24 23 22 21 20 19 18

Addr

0x0021B800

17 16

TYPE

RESET

31 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–2

WDR

Bit 1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0

Table 6-2. RSR Register Description

Description

Reserved—These bits are reserved and should read 0.

r

0 r

0 r

0

Settings

1

WDR rw

0

EXR

Bit 0

Watchdog Reset

—Indicates whether the last reset was caused by a Watchdog count expiration.

0 = Reset was NOT a Watchdog count expiration

1 = Reset WAS a Watchdog count expiration

External Reset

—Indicates whether the last reset was caused by a RESET_IN pin assertion.

0 = Reset was NOT a RESET_IN pin assertion

1 = Reset WAS a RESET_IN pin assertion

Table 6-3. Hardware Reset Source Matrix

Source WDR EXR

POR

Qualified external reset

Watchdog time-out

0

0

1

0

1

0

0

EXR rw

0

6-4

MC9328MX1 Reference Manual

MOTOROLA

Chapter 7

AHB to IP Bus Interface (AIPI)

7.1 Overview

This chapter provides an overview of the R-AHB to IP bus interface (AIPI). The AIPI module in the

MC9328MX1 acts as an interface between the R-AHB (Reduced ARM Advanced High-performance Bus) and lower bandwidth peripherals.

7.1.1 Features

The AIPI provides the following features:

• All peripheral read transactions require a minimum of two system clocks (R-AHB side) and all write transactions require a minimum of three system clocks (R-AHB side).

• Support of 8-bit, 16-bit, and 32-bit IP bus peripherals.

• Byte, half word, and word read and write are supported to and from each peripheral in both big and little endian mode.

• Support of multi-cycle accesses (16-bit operations to 8-bit peripherals, and 32-bit operations to

16-bit and 8-bit peripherals).

• Ability to restrict user to limit access to peripherals in their natural size only.

• Support of 15 external IP bus peripherals. Muxiplexers are incorporated to support the 15 separate read data buses, and the transfer wait and transfer error from peripherals.

• A watchdog timer is provided to time-out peripheral access if operation does not terminate with 512 clock cycles.

• Use of a single asynchronous reset and one global clock with both edges.

• The AIPI module is implemented using MUX-D scan methodology for testability.

7.1.2 General Information

The AIPI is the interface between the R-AHB and on-chip IP bus peripherals as shown in Figure 7-1 on page 7-2.

IP bus peripherals are modules that contain readable/writable control and status registers. The R-AHB master reads and writes these registers through the AIPI. The AIPI generates module enables, the module address, transfer attributes, byte enables and write data as inputs to the IP bus peripherals. The AIPI captures read data (qualified by IPS_XFR_WAIT) from the IP bus interface and drives it on the R-AHB.

The AIPI module terminates the transfer by asserting AIPI_HREADY_OUT.

MOTOROLA

AHB to IP Bus Interface (AIPI)

7-1

AHB to IP Bus Interface (AIPI)

The register maps of all IP bus peripherals are located on 4096 byte boundaries. Each IP bus peripheral is allocated one 4-kbyte block (minimum block size) of the memory map, configured as 1024 32-bit internal registers (or 2048 16-bit internal registers, or 4096 8-bit internal registers), activated by one of 15 module enables from the AIPI. Up to 15 IP bus peripherals may be implemented, occupying contiguous blocks of

4 kbytes, for a total of 60 kbytes. The exact address assignment for the IP bus peripherals is system dependent, and is defined in the system specification. Each IP bus peripheral will select its internal registers based on the address driven on the IPS_ADDR signals.

The AIPI is responsible for telling the IP bus peripherals if the access is in supervisor or user mode. The

AIPI may block user mode accesses to certain IP bus peripherals or it may allow the individual IP bus peripherals to determine if user mode accesses are allowed. Please see Section 7.2, “Programming Model,” for more information.

The AIPI supports multi-cycle accesses to IP bus peripherals when the R-AHB master requests data transfers that are larger than the targeted IP bus peripheral’s data bus width. Table 7-1 through Table 7-4 provides more information on both single-cycle and multi-cycle accesses. For data access that are larger than the target IP bus peripheral, the AIPI will duplicated the data across all the byte lanes on the AHB, i.e. for a word read from 8 bit peripheral, the same data read will appear on byte lanes [31:24, [23:16], [15:8] and [7:0]. Similarly for a byte write to the peripheral, the core will duplicate the same byte over the byte lanes of the AHB for the write operation.

haddr[16:0]

HWDATA[31:0]

HWDATA[31:0]

AIPI_HRDATA[31:0]

HPROTL

HTRANSL

HWRITE

HSIZE[1:0]

HREADY_IN

AIPI_HRESP[1:0]

AIPI_HREADY_OUT

HCLK

HCLK

HSEL_AIPI

HRESET

BIGEND_IN

AIPI

IPS_WDATA[31:0]

IPS_RDATA[15:1][31:

IPS_MODULE_EN[15:

IPS_ADDR1[11:1]

IPS_BYTE_7_0

IPS_BYTE_15_8

IPS_BYTE_23_16

IPS_BYTE_31_24

IPS_RWB

IPS_XFR_WAIT[15:1]

IPS_XFR_ERR[15:1]

IPS_SUPERVISOR_A

IPS_GATED_CLK_EN[1

Figure 7-1. AIPI Interface

7-2

MC9328MX1 Reference Manual

MOTOROLA

hwdata[31:0] dbmx_aipi_16 aipi aipi_core aipi_write_data_path aipi_current_state haddr[16:0] hsize[1:0] hready_in htransl hprot hwrite hsel hclk hclk hreset bigend_in aipi_control ips_rwb ips_supervisor_access ips_addr[11:0] ips_module_en[15:1] ips_byte_31_24 ips_byte_23_16 ips_byte_15_8 ips_byte_7_0 ips_gated_clk_en[15:1] aipi_hresp[1:0] aipi_hready_out ips_rdata[15:1][31:0] ips_wdata[31:0] aipi_read_data_path aipi_register_data aipi_par_en aipi_psr_err aipi_register_err aipi_registers aipi_register_wait

IP

IP bus_peripheral_size aipi_timeout ips_xfr_wait ips_xfr_err ips_rdata[31:0] aipi_watchdog aipi_start_transfer aipi_data_mux aipi_xfr_mux aipi_ip_decode mux_select

[3:0] ips_xfr_wait[15:1] ips_xfr_err[15:1]

Figure 7-2. Block Diagram of the AIPI Module

Overview

MOTOROLA

AHB to IP Bus Interface (AIPI)

7-3

AHB to IP Bus Interface (AIPI)

Transfer

Size

Table 7-1. R-AHB to IP Bus Interface Operation (Big Endian—Read Operation) haddr ips_addr Active Bus Section (IP Bus to R-AHB)

[1] [0]

IP

Bus

Size

[1] [0]

R-AHB

[31:24]

R-AHB

[23:16]

R-AHB

[15:8]

R-AHB

[7:0]

Byte

0

0

1

0

1

0

0

1

0

1

1

8-bit

16-bit

32-bit

1

1

0

1

Half Word 0 NA 8-bit

1

0

1

0

1

1

0

0

0

1

1

0

0

1

16-bit

32-bit

0

1

X

1

1

0

0

0

1

X

X

0

1

X

0

1

0

1 ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0]

X ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0]

X –

– ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0]

X

X ips_rdata

[31:24]

– – –

– ips_rdata

[23:16]

– ips_rdata[15:8]

– ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0]

0

1

0

1 ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0]

X ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0]

X ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0]

X – –

X ips_rdata

[31:24]

– ips_rdata

[23:16]

– ips_rdata[15:8] ips_rdata[7:0]

7-4

MC9328MX1 Reference Manual

MOTOROLA

Overview

Table 7-1. R-AHB to IP Bus Interface Operation (Big Endian—Read Operation) (Continued) haddr ips_addr Active Bus Section (IP Bus to R-AHB)

Transfer

Size

[1] [0]

IP

Bus

Size

[1] [0]

R-AHB

[31:24]

R-AHB

[23:16]

R-AHB

[15:8]

R-AHB

[7:0]

Word NA NA 8-bit

16-bit

32-bit

0

1

0

1

X

0

1

0

1 ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0]

X ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0]

X ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0]

X ips_rdata

[31:24] ips_rdata

[23:16] ips_rdata[15:8] ips_rdata[7:0]

Table 7-2. R-AHB to IP Bus Interface Operation (Big Endian—Write Operation) haddr

Transfer

Size

[1] [0]

Byte 0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

ips_addr Active Bus Section (R-AHB to IP Bus)

IP

Bus

Size

8-bit

16-bit

32-bit

0

0

1

1

0

[1]

1

X

X

[0]

R-AHB

[31:24]

R-AHB

[23:16]

R-AHB

[15:8]

R-AHB

[7:0]

1

X

0 ips_wdata[7:0]

1

0

– – ips_wdata[7:0]

– ips_wdata[7:0]

X

X

– ips_wdata

[15:8]

– ips_wdata

[31:24]

– ips_wdata[7:0]

– ips_wdata

[15:8]

X – ips_wdata

[23:16]

– – ips_wdata

[15:8]

– ips_wdata[7:0]

– ips_wdata[7:0]

– ips_wdata[7:0]

MOTOROLA

AHB to IP Bus Interface (AIPI)

7-5

AHB to IP Bus Interface (AIPI)

Table 7-2. R-AHB to IP Bus Interface Operation (Big Endian—Write Operation) (Continued) ips_addr Active Bus Section (R-AHB to IP Bus) haddr

Transfer

Size

[1] [0]

IP

Bus

Size

[1] [0]

R-AHB

[31:24]

R-AHB

[23:16]

R-AHB

[15:8]

R-AHB

[7:0]

Half

Word

Word

0 NA 8-bit

1

0

1

0

1

16-bit

32-bit

NA NA 8-bit

16-bit

32-bit

0

1

0

1

X

X

0

1

0

1

X

0

1

X

0

1

X

0 ips_wdata[7:0]

1 –

– ips_wdata[7:0]

– ips_wdata[7:0]

– ips_wdata[7:0]

– ips_wdata[7:0]

– –

X ips_wdata

[15:8]

– – ips_wdata[7:0]

X ips_wdata

[15:8]

– –

X ips_wdata

[31:24]

– ips_wdata

[23:16]

– ips_wdata[7:0]

0

1 ips_wdata[7:0]

– ips_wdata[7:0] ips_wdata

[15:8]

X

– ips_wdata

[15:8]

– ips_wdata[7:0] ips_wdata[7:0]

– ips_wdata[7:0]

– –

– ips_wdata[7:0]

X ips_wdata

[31:24] ips_wdata

[23:16] ips_wdata

[15:8] ips_wdata

[15:8] ips_wdata[7:0]

7-6

MC9328MX1 Reference Manual

MOTOROLA

Overview

Table 7-3. R-AHB to IP Bus Interface Operation (Little Endian—Read Operation) ips_addr Active Bus Section (IP Bus to R-AHB) haddr

Transfer

Size

[1] [0]

IP

Bus

Size

[1] [0]

R-AHB

[31:24]

R-AHB

[23:16]

R-AHB

[15:8]

R-AHB

[7:0]

Byte

Half

Word

1

0 NA

1

0

1

0

1

1

1

0

0

1

1

0

0

0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8-bit

16-bit

32-bit

8-bit

16-bit

32-bit X

X

0

1

1

1

0

0

0

1

X

X

0

1

X

X

0

1

0

1

X ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0]

X ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0]

X

– ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[15:8]

– ips_rdata[15:8] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0]

– ips_rdata[7:0]

X

0

1

0

1

– ips_rdata

[31:24] ips_rdata[7:0] ips_rdata[7:0] ips_rdata

[23:16]

– ips_rdata[7:0] ips_rdata[7:0]

– ips_rdata[7:0] ips_rdata[7:0]

– ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0]

X ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0]

X ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0]

– ips_rdata

[31:24]

– ips_rdata

[23:16] ips_rdata[15:8] ips_rdata[7:0]

– –

MOTOROLA

AHB to IP Bus Interface (AIPI)

7-7

AHB to IP Bus Interface (AIPI)

Table 7-3. R-AHB to IP Bus Interface Operation (Little Endian—Read Operation) (Continued) ips_addr Active Bus Section (IP Bus to R-AHB) haddr

Transfer

Size

[1] [0]

IP

Bus

Size

[1] [0]

R-AHB

[31:24]

R-AHB

[23:16]

R-AHB

[15:8]

R-AHB

[7:0]

Word NA NA 8-bit

16-bit

32-bit

0

1

0

1

X

0

1

0

1 ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0] ips_rdata[7:0]

X ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0]

X ips_rdata[15:8] ips_rdata[7:0] ips_rdata[15:8] ips_rdata[7:0]

X ips_rdata

[31:24] ips_rdata

[23:16] ips_rdata[15:8] ips_rdata[7:0]

Table 7-4. R-AHB to IP Bus Interface Operation (Little Endian—Write Operation) haddr

Transfer

Size

[1] [0] ips_addr

IP Bus

Size

[1] [0]

Byte 0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

8-bit

16-bit

32-bit

0

0

1

1

0

1

X

X

Active Bus Section (R-AHB to IP Bus)

R-AHB

[31:24]

R-AHB

[23:16]

R-AHB

[15:8]

R-AHB

[7:0]

0

1

0

1 ips_wdata[7:0]

X –

– –

– ips_wdata[7:0] ips_wdata[7:0]

– ips_wdata[7:0]

– ips_wdata

[15:8]

– ips_wdata[7:0]

X

X

X

– ips_wdata

[15:8]

– ips_wdata[7:0]

– ips_wdata

[15:8]

– ips_wdata[7:0]

– ips_wdata

[31:24] ips_wdata

[23:16]

– – –

7-8

MC9328MX1 Reference Manual

MOTOROLA

Overview

Table 7-4. R-AHB to IP Bus Interface Operation (Little Endian—Write Operation) (Continued)

Active Bus Section (R-AHB to IP Bus) haddr

Transfer

Size

[1] [0] ips_addr

IP Bus

Size

[1] [0]

R-AHB

[31:24]

R-AHB

[23:16]

R-AHB

[15:8]

R-AHB

[7:0]

Half

Word

Word

0 NA

1

0

1

0

1

NA NA

8-bit

16-bit

32-bit

8-bit

16-bit

32-bit

0

1

0

1

X

X

0

1

0

1

X

0

1

0 –

1 ips_wdata[7:0] ips_wdata[7:0]

X – –

– ips_wdata[7:0] ips_wdata[7:0]

– ips_wdata[7:0]

X ips_wdata[7:0] ips_wdata

[15:8]

– –

X ips_wdata

[15:8]

– – ips_wdata[7:0]

X ips_wdata

[31:24] ips_wdata

[23:16] ips_wdata

[15:8]

– –

0

1

0 –

1 ips_wdata[7:0] ips_wdata[7:0]

X – –

– ips_wdata[7:0] ips_wdata[7:0]

– ips_wdata[7:0]

X ips_wdata[7:0] ips_wdata

[15:8]

– –

X ips_wdata

[15:8] ips_wdata

[31:24] ips_wdata

[23:16] ips_wdata

[15:8] ips_wdata[7:0]

MOTOROLA

AHB to IP Bus Interface (AIPI)

7-9

AHB to IP Bus Interface (AIPI)

7.2 Programming Model

There are six registers that reside inside the AIPI module. Two system clocks are required for read accesses and three system clocks are required for write accesses to the AIPI registers. Table 7-5 is a summary of these registers and their addresses.

Table 7-5. AIPI Module Register Memory Map

Description Name Address

AIPI1

AIPI1 Peripheral Size Register 0

AIPI1 Peripheral Size Register 1

AIPI1 Peripheral Access Register

AIPI1 Peripheral Control Register

AIPI1 Time-Out Status Register

PSR0_1

PSR1_1

PAR_1

PCR_1

TSR_1

0x00200000

0x00200004

0x00200008

0x0020000C

0x00200010

AIPI2

AIPI2 Peripheral Size Register 0

AIPI2 Peripheral Size Register 1

AIPI2 Peripheral Access Register

AIPI2 Peripheral Control Register

AIPI2Time-Out Status Register

PSR0_2

PSR1_2

PAR_2

PCR_2

TSR_2

0x00210000

0x00210004

0x00210008

0x0021000C

0x00210010

Table 7-6 illustrates the peripheral address associated with the corresponding module_en number. Refer to

Chapter 3, “Memory Map,” to see the corresponding address assigned to each peripheral.

Table 7-6. Peripheral Address MODULE_EN Numbers

AIPI 1 AIPI 2

Address

0x0020 1000 – 0x0020 1FFF

0x0020 2000 – 0x0020 2FFF

0x0020 3000 – 0x0020 3FFF

0x0020 4000 – 0x0020 4FFF

0x0020 5000 – 0x0020 5FFF

0x0020 6000 – 0x0020 6FFF

0x0020 7000 – 0x0020 7FFF

0x0020 8000 – 0x0020 8FFF

MODULE_EN

7

8

5

6

3

4

1

2

Address

0x0021 1000 – 0x0021 1FFF

0x0021 2000 – 0x0021 2FFF

0x0021 3000 – 0x0021 3FFF

0x0021 4000 – 0x0021 4FFF

0x0021 5000 – 0x0021 5FFF

0x0021 6000 – 0x0021 6FFF

0x0021 7000 – 0x0021 7FFF

0x0021 8000 – 0x0021 8FFF

MODULE_EN

7

8

5

6

3

4

1

2

7-10

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Table 7-6. Peripheral Address MODULE_EN Numbers (Continued)

AIPI 1 AIPI 2

Address

0x0020 9000 – 0x0020 9FFF

0x0020 A000 – 0x0020 AFFF

0x0020 B000 – 0x0020 BFFF

0x0020 C000 – 0x0020 CFFF

0x0020 D000 – 0x0020 DFFF

0x0020 E000 – 0x0020 EFFF

0x0020 F000 – 0x0020 FFFF

MODULE_EN

12

13

14

15

9

10

11

Address

0x0021 9000 – 0x0021 9FFF

0x0021 A000 – 0x0021 AFFF

0x0021 B000 – 0x0021 BFFF

0x0021 C000 – 0x0021 CFFF

0x0021 D000 – 0x0021 DFFF

0x0021 E000 – 0x0021 EFFF

0x0021 F000 – 0x0021 FFFF

MODULE_EN

12

13

14

15

9

10

11

MOTOROLA

AHB to IP Bus Interface (AIPI)

7-11

AHB to IP Bus Interface (AIPI)

7.2.1 Peripheral Size Registers[1:0]

These registers control the size of the IP bus peripheral in each IP bus peripheral location. Peripheral locations that are not occupied must have their corresponding bits in the PSRs (Peripheral Size Registers) programmed to 1 in each register.

The least significant bit in the PSRs is a read only bit as it governs the AIPI registers themselves. They are set and cleared appropriately to indicate the registers are 32 bits. Bits 31 through 16 in both registers are preset to 1 and the fields are reserved and can only be read.

7.2.1.1 AIPI1 Peripheral Size Register 0 and AIPI2 Peripheral Size Register 0

PSR0_1

PSR0_2

BIT 31 30 29

AIPI1 Peripheral Size Register 0

AIPI2 Peripheral Size Register 0

28 27 26 25 24 23 22 21 20 19

Addr

0x00200000

0x00210000

18 17 16

TYPE

PSR0_1

RESET

PSR0_2

RESET

1

1

1 1 1

1 1 1

1 1

1 1

1

1

1

0xFFFF

1

1

0xFFFF

1

1 1

1 1

1

1

1 1 1 1

1 1 1 1

BIT

TYPE

PSR0_1

RESET rw

1

1

PSR0_2

RESET

Reserved

Bit 0

15

Table 7-7. AIPI1 Peripheral Size Register 0 and AIPI2 Peripheral Size Register 0 Description

Name Description Settings

Reserved

Bits 31–16

MOD_EN_L

Bits 15–1

14 rw

1

1

13 rw

1

0

12 rw

1

0

11 rw

1

0

10 rw

0

1 rw

0

9 8

MOD_EN_L

7 rw

0 rw

0

0

0xF800

0 0

0xC410 rw

0

Reserved—These bits are reserved and should read 1.

6

0

5 rw

0

0

4 rw

0

1

3 rw

0

0

2 rw

0

0

1 rw

0

0

Module_En (Lower)

—Each bit represents the lower bit of the 2-bit field (PSR1 + PSR0) that represents the

Module_En number.

Reserved—This bit is reserved and should read 0.

See Table 7-9 for bit settings

0 r

0

0

7-12

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

7.2.1.2 AIPI1 Peripheral Size Register 1 and AIPI2 Peripheral Size Register 1

PSR1_1

PSR1_2

BIT 31 30 29

AIPI1 Peripheral Size Register 1

AIPI2 Peripheral Size Register 1

28 27 26 25 24 23 22 21 20 19

Addr

0x00200004

0x00210004

18 17 16

TYPE

PSR_1

RESET

PSR_2

RESET

1

1

1 1 1

1 1 1

1 1

1 1

1

1

1

0xFFFF

1

1

0xFFFF

1

1 1

1 1

1

1

1 1 1 1

1 1 1 1

BIT

TYPE

PSR_1

RESET

PSR_2

RESET

Reserved

Bit 0

15 rw

1

1

Table 7-8. AIPI1 Peripheral Size Register 1 and AIPI2 Peripheral Size Register 1 Description

Name Description Settings

Reserved

Bits 31–16

MOD_EN_U

Bits 15–1

14 rw

1

1

13 rw

1

1

12 rw

1

1

11 rw

1

1

10 rw

1

0 rw

1

9 8

MOD_EN_U

7 rw

1 rw

1

1

0xFFFF

1 1

0xFBEF

6 rw

1

1

Reserved—These bits are reserved and should read 1.

5 rw

1

1

4 rw

1

0

3 rw

1

1

2 rw

1

1

1 rw

1

1

0 r

1

1

Module_En (Upper)

—Each bit represents the upper bit of the

2-bit field (PSR1 + PSR0) that represents the Module_En number.

Reserved—This bit is reserved and should read 0.

See Table 7-9 for bit settings

The PSRs work together to indicate the size of the IP bus peripheral occupying the corresponding

ips_module_en

location, or to indicate there is no IP bus peripheral occupying the corresponding

ips_module_en

location. A good example of how the PSRs work is the AIPI registers themselves. When haddr[16:12] is decoded to select the AIPI registers, {PSR1[bit0], PSR0[bit0]} returns a value of 10, indicating that the AIPI registers are word width registers. Table 7-9 shows how to program the PSR registers based on the size or availability of an IP bus peripheral.

MOTOROLA

AHB to IP Bus Interface (AIPI)

7-13

AHB to IP Bus Interface (AIPI)

Table 7-9. PSR Data Bus Size Encoding

PSR[1:0] Bits

IP Bus Peripheral Size [x]

(module_en [x])

PSR1[x] PSR0[x]

0

0

1

1

0

1

0

1

8-bit

16-bit

32-bit

Unoccupied

7.2.2 Peripheral Access Registers

These registers are used to tell the AIPI whether or not the IP bus peripheral corresponding to the bit location in the register may be accessed in user mode. If the peripheral may be accessed in supervisor mode only and a user mode access is attempted an abort will be generated and no IP bus activity occurs. If the peripheral can be accessed in user mode, then the IPS_SUPERVISOR_ACCESS bit reflects whether the attempted access is in supervisor or user mode and the peripheral itself can decide whether to accept a user access (if one is attempted) or issue an error response.

The least significant bit in the PAR is a read only bit as it governs the AIPI registers themselves. It is set to indicate supervisor access only. Bits 31 through 16 in both registers are preset to 1 and the fields are reserved and can only be read.

PAR_1

PAR_2

BIT 31 30 29

AIPI1 Peripheral Access Register

AIPI2 Peripheral Access Register

28 27 26 25 24 23 22 21 20 19

Addr

0x00200008

0x00210008

18 17 16

TYPE

PAR_1

RESET

PAR_2

RESET

1

1

1 1 1

1 1 1

1 1

1 1

1

1

1

0xFFFF

1

1

0xFFFF

1

1 1

1 1

1

1

1 1 1 1

1 1 1 1

BIT 15

TYPE

PAR_1

RESET

PAR_2

RESET rw

1

1

14 rw

1

1

13 rw

1

1

12 rw

1

1

11 rw

1

1

10 rw

1

1 rw

1

9 8

ACCESS

1 rw

1

7

0xFFFF

1 1

0xFFFF rw

1

6 rw

1 rw

1

1

5

1

4 rw

1

1

3 rw

1 rw

1 rw

1

1

2

1

1

1

0 r

1

1

7-14

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Name

Reserved

Bits 31–16

ACCESS

Bits 15–1

Table 7-10. Peripheral Access Register Description

Description

Reserved—These bits are reserved and should read 1.

Access Control

—Each bit controls the access mode of the corresponding peripheral.

Settings

0 = Assigned peripheral determines access mode.

1 = the corresponding peripheral is a supervisor access only peripheral.

Reserved

Bit 0

Reserved—This bit is reserved and should read 1.

7.2.3 Peripheral Control Register

These registers are to tell the AIPI whether or not the IP bus peripheral corresponding to the bit location in the register can be accessed in their natural size only. When set to 1, only byte access is allowed on an 8-bit peripheral, only halfword access is allowed on a 16-bit peripheral, and only word access is allowed on a

32-bit peripheral. When set to 1, any access other than natural size that is attempted on the peripheral results in an error response and no IP bus activity occurs.

The least significant bit in the PCR is a read-only bit and the AIPI registers are not governed by this bit.

Bits 31 through 16 in both registers are preset to 0 and the fields are reserved and can only be read.

PCR_1

PCR_2

BIT 31 30 29

AIPI1 Peripheral Control Register

AIPI2 Peripheral Control Register

28 27 26 25 24 23 22 21 20 19

Addr

0x0020000C

0x0021000C

18 17 16

TYPE

PCR_1

RESET

PCR_2

RESET

0

0

0 0 0

0 0 0

0 0

0 0

0

0

0

0x0000

0

0

0x0000

0

0 0

0 0

0

0

0 0 0 0

0 0 0 0

BIT 15

TYPE

PCR_1

RESET

PCR_2

RESET rw

0

0

14 rw

0

0

13 rw

0

0

12 rw

0

0

11 rw

0

0

10 rw

0

0

9 8 7

ACCESS_MODE rw

0 rw

0 rw

0

0

0x0000

0 0

0x0000

6 rw

0 rw

0

0

5

0

4 rw

0

0

3 rw

0 rw

0 rw

0

0

2

0

1

0

0 r

0

0

MOTOROLA

AHB to IP Bus Interface (AIPI)

7-15

AHB to IP Bus Interface (AIPI)

Name

Reserved

Bits 31–16

ACCESS_

MODE

Bits 15–1

Reserved

Bit 0

Table 7-11. Peripheral Control Register Description

Description

Reserved—These bits are reserved and should read zero.

Settings

Module Access Mode

—Each bit controls the method of access used by the corresponding peripheral assigned to the Module_en.

0 = sub-word and word access is allowed on the peripheral

1 = corresponding peripheral can only be accessed in the natural size. i.e. byte accesses on

8-bit peripherals, half-word accesses on 16-bit peripherals and word accesses on

32-bit peripherals.

Reserved—This bit is reserved and should read 1.

7.2.4 Time-Out Status Register

These registers contain status of the AIPI module prior to the occurrence of the time-out event. The

Time-Out registers are read-only and status is updated due to time-out operation and module_en must be active. The register is clear during initial reset.

TSR_1

TSR_2

BIT

TYPE

TSR_1

RESET

31

TO rw

0

0

TSR_2

RESET

30

RW r

0

29 r

0

0 0

28 r

0

0

AIPI1 Time-Out Status Register

AIPI2 Time-Out Status Register

27 r

0

0

26 r

0

0

25

ADDR

24 r

0 r

0

0

23

0x0000

0 0

0x0000 r

0

22 r

0

0

21 r

0

0 r

0

20

Addr

0x00200010

0x00210010

19 18 17 16

BE4 BE3 BE2 BE1 r

0 r

0 r

0 r

0

0 0 0 0 0

BIT

TYPE

TSR_1

RESET

TSR_2

RESET r

0

0

15 14 13 12 11 10 r

0

0 r

0

0 r

0

0 r

0

0 r

0

0 r

0

9 8

MODULE_EN

7 r

0 r

0

0

0x0000

0 0

0x0000

6 5 r

0 r

0

0 0

4 r

0

0

3 2 r

0

0 r

0

0

1 0 r

0 r

0

0 0

7-16

MC9328MX1 Reference Manual

MOTOROLA

Programming Example

Table 7-12. Time-Out Status Register Description

Description Name Settings

TO

Bit 31

Time-Out

—This bit when set to 1 indicates a time-out event and may be cleared by the user.

0 = No time-out event

1 = time-out event

This bit contains the ips_rwb status prior to time-out event.

RW

Bit 30

ADDR

Bits 29–20

BE4

Bit 19

BE3

Bit 18

Address

event.

—These bits contains the ips_addr[11:2] status prior to time-out

This bit contains the ips_byte_31_24 status prior to time-out event.

This bit contains the ips_byte_23_16 status prior to time-out event.

BE2

Bit 17

BE1

Bit 16

This bit contains the ips_byte_15_8 status prior to time-out event.

This bit contains the ips_byte_7_0 status prior to time-out event.

MODULE_EN

Bits 14–1

Reserved

Bit 0

Module Enable Status

—These bits contains the module_en[15:1] status prior to time-out event. Refer to Table 7-6 to determine which peripheral is assigned to which module_en number. assignment of

0= Corresponding module has not timed out

1 = Corresponding module has timed out

Reserved—This bit is reserved and should read 0.

7.3 Programming Example

This section covers programming examples written in assembly code to illustrate the data access through the AIPI module.

7.3.1 Data Access to 8-Bit Peripherals

The followings codes are executed with the ARM920T core set to big and little endian modes:

LDR

LDR r0, r1,

LDR r2,

STRB r0,

STRB r1,

STRH r0,

STR r1,

LDRB r3,

LDRB r4,

LDRH r5,

LDR r6,

=0x11223344

=0x55667788

=8BIT_PERIPHERAL_ADDRESS

[r2, #0x0]

[r2, #0x1]

[r2, #0x2]

[r2, #0x4]

[r2, #0x0]

[r2, #0x1]

[r2, #0x2]

[r2, #0x4]

The Table 7-13 on page 7-18 illustrates the difference in the 8-bit peripheral register content.

MOTOROLA

AHB to IP Bus Interface (AIPI)

7-17

AHB to IP Bus Interface (AIPI)

Table 7-13. Core and 8-Bit Peripheral Register Content After Code Execution

Address Peripheral Registers

6

7

4

5

2

3

0

1

88

77

66

55

44

88

44

33

Address

r3 r4 r5 r6

Core Registers

00 00 00 44

00 00 00 88

00 00 33 44

55 66 77 88

7.3.2 Data Access to 16-Bit Peripherals

The followings codes are executed with the ARM core set to big and little endian modes.

LDR

LDR r0, r1,

LDR r2,

STRB r0,

STRB r1,

STRH r0,

STR r1,

LDRB r3,

LDRB r4,

LDRH r5,

LDR r6,

=0x11223344

=0x55667788

=16BIT_PERIPHERAL_ADDRESS

[r2, #0x0]

[r2, #0x1]

[r2, #0x2]

[r2, #0x4]

[r2, #0x0]

[r2, #0x1]

[r2, #0x2]

[r2, #0x4]

The Table 7-14 and Table 7-15 illustrate the difference in the 16-bit peripheral register content.

Table 7-14. Core and 16-Bit Peripheral Register Content (Little Endian)

Address Peripheral Registers

0

2

4

6

88 44

33 44

77 88

55 66

7-18

MC9328MX1 Reference Manual

MOTOROLA

Programming Example

Table 7-14. Core and 16-Bit Peripheral Register Content (Little Endian) (Continued)

Address Peripheral Registers

Address

r3 r4 r5 r6

Core Registers

00 00 00 44

00 00 00 88

00 00 33 44

55 66 77 88

Table 7-15. Core and 16-Bit Peripheral Register Content (Big Endian)

Address Peripheral Registers

4

6

0

2

44 88

33 44

55 66

77 88

Address

r3 r4 r5 r6

Core Registers

00 00 00 44

00 00 00 88

00 00 33 44

55 66 77 88

7.3.3 Data Access to 32-Bit Peripherals

The followings codes are executed with the ARM core set to big and little endian modes.

LDR

LDR r0, r1,

LDR r2,

STRB r0,

STRB r1,

STRH r0,

STR r1,

LDRB r3,

LDRB r4,

LDRH r5,

LDR r6,

=0x11223344

=0x55667788

=32BIT_PERIPHERAL_ADDRESS

[r2, #0x0]

[r2, #0x1]

[r2, #0x2]

[r2, #0x4]

[r2, #0x0]

[r2, #0x1]

[r2, #0x2]

[r2, #0x4]

The Table 7-16 and Table 7-17 on page 7-20 illustrate the difference in the 32-bit peripheral register content.

MOTOROLA

AHB to IP Bus Interface (AIPI)

7-19

AHB to IP Bus Interface (AIPI)

Table 7-16. Core and 32-bit Peripheral Register Content (Little Endian)

Address Peripheral Registers

0

4

33 44 88 44

55 66 77 88

Address

r3 r4 r5 r6

Core Registers

00 00 00 44

00 00 00 88

00 00 33 44

55 66 77 88

Table 7-17. Core and 32-bit Peripheral Register Content (Big Endian)

Address Peripheral Registers

0

4

44 88 33 44

55 66 77 88

Address

r3 r4 r5 r6

Core Registers

00 00 00 44

00 00 00 88

00 00 33 44

55 66 77 88

7.3.4 Special Consideration for Non-Natural Size Access

A programmer must exercise care when accessing peripherals using access other than their natural size. An example of such access includes byte access to a 32-bits peripheral and word access to 8-bit peripheral.

The examples in the previous section clearly illustrate the difference in byte accessing a 32-bits peripheral in both big and little endian modes. An instruction such as:

STRB r1, [r2, #0x1] is accessing using byte lane[15:8] in little endian, while byte lane[23:16] is accessed using big endian mode. Therefore, if a programmer is using byte access to set up control information in 32-bit register, extreme care must be taken to ensure the desired byte is written during the desired endian mode.

7-20

MC9328MX1 Reference Manual

MOTOROLA

Chapter 8

System Control

This chapter describes the system control module of the MC9328MX1 microprocessor. The system control module enables system software to control, customize, or read the status of the following functions:

• Multiplexing of SSI and SIM signals

• Multiplexing of the SDRAM/SyncFlash chip select signal

• Chip ID

• System boot mode selection

8.1 Programming Model

The system control module includes four user-accessible 32-bit registers. Table 8-1 summarizes these registers and their addresses.

Table 8-1. System Control Module Register Memory Map

Description Name Address

Silicon ID Register SIDR 0x0021B804

Function Multiplexing Control Register FMCR 0x0021B808

Global Peripheral Control Register GPCR 0x0021B80C

Global Clock Control Register GCCR 0x0021B810

MOTOROLA

System Control

8-1

System Control

8.1.1 Silicon ID Register

This 32-bit read-only register shows the chip identification. The bit assignments for the register are shown in the following register display. The settings for the bits in the register are listed in Table 8-2.

SIDR

BIT

TYPE

RESET

31 r

0

30 29 28 r

0 r

0 r

0

Silicon ID Register

27 26 r

0 r

0 r

0

25 r

0

24

SID

23

0x0005 r

0

22 21 20 19 r

0 r

0 r

0 r

0

Addr

0x0021B804

18 17 16 r

1 r

0 r

1

BIT

TYPE

RESET

Name

SID

Bits 31–0 r

1

15 14 13 12 r

0 r

0 r

1

11 10 r

0 r

0

9 r

0

8

SID

7 r

0

0x901D r

0

6 r

0

5 r

0

Table 8-2. Silicon ID Register Description

Description

4 r

1

3 r

1

Silicon ID

—Contains the chip identification number of the MC9328MX1.

2 r

1

1 r

0

0 r

1

8-2

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

8.1.2 Function Multiplexing Control Register

The Function Multiplexing Control Register (FMCR) controls the multiplexing of the signal lines shared by the SSI and SIM modules. It also controls the SDRAM/SyncFlash chip select lines and masking of the external bus request. See Table 8-3 on page 8-3 for detailed description of bit settings.

FMCR

BIT 31 30

Function Multiplexing Control Register

29 28 27 26 25 24 23 22 21 20

Addr

0x0021B808

19 18 17 16

TYPE

RESET r

0

BIT r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0

15 14 13 12 11 10 9 8 7 6 r

0

5 r

0 r

0 r

0 r

0 r

0

4 3 2 1 0

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 rw

0 rw

0

0x0003 rw

0 rw

0 rw

0 rw rw rw

0 0 1 rw

1

Table 8-3. Function Multiplexing Control Register Description

Description Settings Name

Reserved

Bits 31–9

SPI2_RXD_SEL

Bit 8

SSI_RXFS_SEL

Bit 7

SSI_RXCLK_SEL

Bit 6

SSI_RXDAT_SEL

Bit 5

SSI_TXFS_SEL

Bit 4

SSI_TXCLK_SEL

Bit 3

Reserved—These bits are reserved and should read 0.

SPI2 Receive Data Input Select

SPI2 Receive data INput source

- Selects the 0 = Input from SPI2_RXD-0 pin (AOUT of

GPIO port A[1])

1 = Input from SPI2_RXD_1 pin (AOUT of

Port D[9])

SSI Receive Frame Sync Input

Select

—Selects the Receive Frame Sync input source.

SSI Receive Clock Select

—Selects the

Receive Clock input source.

0 = Input from Port C[3] SSI_RXFS pin

1 = Input from Port B[14] SIM_SVEN pin

0 = Input from Port C[4] SSI_RXCLK pin

1 = Input from Port B[15] SIM_PD pin

SSI Receive Data Select

—Selects the Receive

Data input source.

0 = Input from Port C[5] SSI_RXDAT pin

1 = Input from Port B[16] SIM_TX pin

SSI Transmit Frame Sync Select

—Selects the

Transmit Frame Sync input source.

0 = Input from Port C[7] SSI_TXFS pin

1 = Input from Port B[18] SIM_RST pin

SSI Transmit Clock Select

—Selects the

Transmit Clock input source.

0 = Input from Port C[8] SSI_TXCLK pin

1 = Input from Port B[19] SIM_CLK pin

MOTOROLA

System Control

8-3

System Control

Name

Table 8-3. Function Multiplexing Control Register Description (Continued)

Description Settings

EXT_BR_EN

Bit 2

SDCS1_SEL

Bit 1

SDCS0_SEL

Bit 0

External Bus Request Control

—Chooses whether the external bus request function is masked or enabled.

Note:

The external bus request is a test signal and the EXT_BR_EN bit must be clear during normal operation.

0 = External bus request masked

1 = External bus request enabled

SDRAM/SyncFlash Chip Select

—Selects the function of the CS3/CSD1 pin.

SDRAM/SyncFlash Chip Select

—Selects the function of the CS2/CSD0 pin.

0 = CS3 selected

1 = CSD1 selected

0 = CS2 selected

1 = CSD0 selected

8.1.3 Global Peripheral Control Register

The Global Peripheral Control Register (GPCR) controls the driving force parameters of the bus and several other functions in the MC9328MX1. Descriptions of the register settings appear in Table 8-4.

GPCR

BIT 31 30

Global Peripheral Control Register

29 28 27 26 25 24 23 22 21 20 19

Addr

0x0021B80C

18 17 16

TYPE

RESET

BIT r

0

15 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0

14 13 12 11 10 9 8 7 6 5 4 3 2 1 r

0

0

TYPE

RESET rw

0 r

0 r

0 rw

0 rw

0 rw

0 rw

1 rw

1

0x03FB rw

1 rw

1 rw

1 rw

1 r

1 r

0 rw

1 rw

1

8-4

MC9328MX1 Reference Manual

MOTOROLA

Reserved—These bits are reserved and should read 0.

Programming Model

Table 8-4. Global Peripheral Control Register Description

Description Settings Name

Reserved

Bits 31–16

TEST_EN_REG

Bit 15

Test Enable Register

- Active high of this bit switches the internal test signals from MEMC to GPIO for debug purposes.

0 = Normal

1 = Switches MEMC inner test signals to GPIO for debug purposes.

Reserved—These bits are reserved and should read 0.

Reserved

Bits 14–13

BTAEN

Bit 12

DS_SLOW

Bits 11–10

DS_CNTL

Bits 9–8

DS_ADDR

Bits 7–6

DS_DATA

Bits 5–4

CSI_PROT_EN

Bit 0

BTA Clock Input Control

—Controls the clock input signals to the BTA module. When the bit is clear, clock inputs to the BTA are stopped for power saving.

When this bit is set, clock inputs to the BTA are enabled.

0 = Clock inputs to BTA disabled

1 = Clock inputs to BTA enabled

Driving Strength Slow I/O

—Controls the driving strength of all slow I/O signals.

00 = 26 MHz/15 pF

01 = 26 MHz/30 pF

10 = 26 MHz/45 pF

11 = 26 MHz/greater than 45 pF

Driving Strength Bus Control Signal

—Controls the driving strength of bus control signals.

00 = 50 MHz/15 pF

01 = 50 MHz/30 pF

10 = 100 MHz/15 pF

11 = 100 MHz/30 pF

Driving Strength Address Bus

—Controls the driving strength of the address bus.

00 = 50 MHz/15 pF

01 = 50 MHz/30 pF

10 = 100 MHz/15 pF

11 = 100 MHz/30 pF

Driving Strength Data Bus

strength of the data bus.

—Controls the driving 00 = 50 MHz/15 pF

01 = 50 MHz/30 pF

10 = 100 MHz/15 pF

11 = 100 MHz/30 pF

Reserved—This bit must be set to 1 at all times for normal operation. Reserved

Bit 3

Reserved

Bit 2

MMA_PROT_EN

Bit 1

Reserved—This bit is reserved and should read 0.

MMA Privileged Mode Access

—Selects whether the

MMA can only be accessed in privileged mode or if it can be accessed in all modes.

0 = All access modes available

1 = Privileged mode access only

CMOS Sensor Interface Privileged Mode

Access

—Selects whether the CSI can only be accessed in privileged mode or if it can be accessed in all modes.

0 = All access modes available

1 = Privileged mode access only

MOTOROLA

System Control

8-5

System Control

8.1.4 Global Clock Control Register

The Global Clock Control Register (GCCR) provides additional power saving capabilities by controlling the clocks in the following MC9328MX1 modules: DMA, CSI, MMA and USB. It also controls the clock source for Bootstrap mode.

GCCR

BIT

Global Clock Control Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18

Addr

0x0021B810

17 16

TYPE

RESET r r r

0 0 0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0

DMA_

CLK_EN

Bit 3

CSI_

CLK_EN

Bit 2

MMA_

CLK_EN

Bit 2

USBD_

CLK_EN

Bit 2

BIT

TYPE

RESET

Name

Reserved

Bits 31–5

BROM_

CLK_EN

Bit 4

15 14 13 12 11 10 r r r

0 0 0 r

0 r

0 r

0

9 r

0

8 r

0

7 r

0

6 5 r

0

0x000F r

0

4 3 2 1 0

BROM_

CLK_EN

DMA_

CLK_EN

CSI_

CLK_EN

MMA_

CLK_EN

USBD_

CLK_EN rw

0 rw

1 rw

1 rw

1 rw

1

Table 8-5. Global Clock Control Register Description

Settings Description

Reserved—These bits are reserved and should read 0.

BROM Clock Enable

—Only available in Bootstrap mode. This bit enables/disables the operational system boot mode of the MC9328MX1 upon system reset. The boot mode is determined by the settings of these pins.

0 = Clock gating is controlled by setting of

BOOT[3:0] pins.

1 = Overrides the setting of the BOOT[3:0] pins and forces the HCLK to be used as clock.

DMA Clock Enable

—Enables/Disables clock input to the DMA module.

0 = DMA clock input is disabled.

1 = DMA clock input is enabled (default).

CMOS Sensor Interface Clock Enable

Enables/Disables clock input to the CSI module.

Multimedia Accelerator Clock Enable

Enables/Disables clock input to the MMA module.

USBD Clock Enable

—Enables/Disables clock input to the USB module.

0 = CSI clock input is disabled.

1 = CSI clock input is enabled (default).

0 = CSI clock input is disabled.

1 = CSI clock input is enabled (default).

0 = USB clock input is disabled.

1 = USB clock input is enabled (default).

8-6

MC9328MX1 Reference Manual

MOTOROLA

System Boot Mode Selection

8.2 System Boot Mode Selection

The operational system boot mode of the MC9328MX1 upon system reset is determined by the configuration of the four external input pins BOOT[3:0]. The settings of these pins control the following functions:

• CS0 boot function of the EIM module

• Control of the SyncFlash chip select (CSD1) boot function of the SDRAM controller

The settings of the system control module for the system boot mode selection are displayed in Table 8-6.

The MC9328MX1 always begins fetching instructions from address 0x00000000 after reset. The

BOOT[3:0] pins control the memory region that is mapped to address 0x0. The boot modes are defined in

Table 8-6. The BOOT[3:0] pins also control the initial configuration (for example bus width) for the external memory regions. When an external chip select is enabled by the BOOT[3:0] pins, the first

1 Mbyte range (0x0000000–0x000FFFFF) of the chip select's memory space is also mapped to address 0x0.

For example, by setting BOOT[3:0] to 0110, the MC9328MX1 will boot from the CS0 memory region using a 32-bit data bus width. The first 1 Mbyte of the CS0 memory space (0x10000000–0x100FFFFF) will be mapped to addresses 0x00000000–0x000FFFFF.

NOTE:

The BOOT pins must not change once the MC9328MX1 is out of reset.

Also BOOT[3] must always be tied to VSS.

NOTE:

If Bootstrap ROM is not selected for the boot mode, the internal ROM is not accessible.

Table 8-6. System Boot Mode Selection

Inputs

BOOT[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

Output Signals

Active Device

Bootstrap ROM

16-bit SyncFlash D[15:0]

32-bit SyncFlash

8-bit CS0 at D[7:0]

16-bit CS0 at D[31:16]

16-bit CS0 at D[15:0]

32-bit CS0 at D[31:0]

Reserved

MOTOROLA

System Control

8-7

System Control

8-8

MC9328MX1 Reference Manual

MOTOROLA

Chapter 9

Bootstrap Mode Operation

Bootstrap mode is designed to allow you to initialize a target system and download programs or data to the target system’s RAM using the UART 1 or UART 2 controller. After a program is downloaded, it can be executed, which gives you a simple debugging environment for failure analysis and a channel to update programs stored in flash memory. Bootstrap mode has the following capabilities:

• Allows you to initialize your system and download programs and data to system memory using

UART 1 or UART 2

• Accepts execution commands to run programs stored in system memory

• Supports memory and register read and write operations of selectable data size (byte, half-word, or word)

• Provides an 8-word instruction buffer for ARM920T vector table storage, instruction storage and execution

9.1 Operation

In bootstrap mode, the MC9328MX1’s UART 1 and UART 2 controllers are initialized to auto-baud detection mode, no parity, 8-bit character length, and 1 stop bit, and then they are ready to accept bootstrap data download. The first character received must be a

or

A

. This character determines the baud rate to be used and which UART port is being used for bootstrapping. The first character is not part of a program or data being downloaded. To download the data or program, the code must be converted to a bootstrap format file, which is a text file that contains bootstrap records. A DOS-executable program,

STOB.EXE

, can be downloaded from the DragonBall Web site to convert an S-record file to a bootstrap format file.

The MC9328MX1’s internal registers must be initialized as the target system before a program can be downloaded to system memory. Because these internal registers can be treated as a type of memory, each of them can be initialized by issuing a bootstrap record.

The bootstrap design provides an 8-word instruction buffer to which ARM920T core instructions can be downloaded. The buffers are word-access only. This feature enables the ARM920T core instructions to be run even if the memory systems are disabled or in a core stand-alone system. The instruction buffer starts at 0x00000004. Regardless of the operation (initializing internal registers, downloading a program to system RAM, or issuing a core instruction), bootstrap mode will only accept bootstrap record transfers that are made with the UART. The record type determines what action will occur.

The instruction buffer allows the user to download the vector table to the buffer without the use of external

ROM or Flash. The feature provides the user a fast and easy environment to use IRQ during program debugging.

MOTOROLA

Bootstrap Mode Operation

9-1

Bootstrap Mode Operation

9.1.1 Entering Bootstrap Mode

Bootstrap mode is the debug mode of the MC9328MX1. To enter bootstrap mode, the BOOT pins must be properly configured during system reset. After reset, the bootstrap ROM is selected for reset vector fetch cycles. Please refer to Section 8.2, “System Boot Mode Selection,” on page 8-7 for details about configuring bootstrap mode.

9.1.2 Bootstrap Record Format

Only bootstrap records (b-records) are accepted for data transfers in bootstrap mode. The b-record format is shown in Table 9-1, and Table 9-2 further defines the COUNT/MODE byte. All b-records are in uppercase. Each byte is represented by two ASCII characters during transfer (for example, a byte of value

0x12 will be represented by the characters

12

).

Table 9-1. Bootstrap Record Format

4 Bytes

Address

1 Byte

Count/mode

N (Count) Bytes

Data

Bit(s)

7–6

5

4–0

Table 9-2. Definition of COUNT/MODE Byte

Definition

Data size

Read/write flag

Data count in number of bytes

Settings

00 = Byte

01 = Half-word

10 = Reserved

11 = Word

0 = Write

1 = Read

Value from 0 to 31

NOTE:

1. A half-word is defined as 16 bits, while a word is defined as 32 bits.

2. The address specified must fall on a data size boundary: for word access, the last 2 bits of the address must be 0, while for half-word access, the last bit of the address must be 0. The data count in the COUNT/MODE byte must be a multiple of the data size: for word access, the data count must be a multiple of four, while for half-word access, the data count must be in multiple of two. If either the address or the data count is not on an appropriate data size boundary, the bootloader program will return a

*

character (asterisk) to indicate that an error has occurred, and the bootloader will then start waiting for a new b-record.

3. During a read operation, a

/

character (forward slash) is returned after the last data has been returned.

4. A data count of zero (disregard the value of data size and the status of the mode flag) has a special meaning: execute from the address specified. In this case, no data will follow the

COUNT/MODE byte.

Comments can be added to files of b-records. As described above, the shortest b-record consists of 10

ASCII characters (when the data count is 0) of 0 to 9 or A to F (hexadecimal digits). Comments included must not contain patterns to prevent the comments from being considered a b-record.

9-2

MC9328MX1 Reference Manual

MOTOROLA

B-Record Example

9.1.3 Registers Used in Bootloader Program

The bootloader program uses general-purpose registers r5 to r12 as well as r13 as the return register and r14 as the link register. All the other registers can be used by target programs.

9.1.4 Setting Up the RS-232 Terminal

To set up communication between your target system and the PC, set the communication specifications to the baud rate desired, no parity, 8-bit character length, and 1 stop bit. You may pause after each line

(b-record) is transferred to make sure each transferred ASCII character is echoed.

After setting up the hardware, powering up the system, and entering bootstrap mode, send an a

or

A character to the target system to initiate the link. Once the bootloader receives this character, it adjusts the baud rate. If the link is successful, the bootloader will return the special character

:

(colon) as an acknowledgment.

9.1.5 Changing the Speed of Communication

You can change the communication baud rate after communication is set up in the RS-232 terminal.

Simply issue a b-record to re-initialize the baud control register of the UART controller. After the last character of this b-record is sent, the echo of this last character will be transmitted at the new speed. The maximum speed recommended for Bootstrap is 57600 baud.

9.2 B-Record Example

Before you can download a program to system memory, the target system may need to be initialized using the internal registers. An init file can be built using a text editor. Code Example 9-1 initializes the eSRAM memory location0x00310000 to 0x12345678 in word access mode, the location0x00310006 to 0x7788 in half-word access mode, and the location0x00310009 to 0x55 in byte access mode.

Code Example 9-1. init.b Example

// init.b -- Initialization Example

00310000C412345678initialize 0x00310000 to 0x12345678

00310006427788

003100090155 initialize 0x00310006 to 0x7788 initialize 0x00310009 to 0x55

With b-records similar to those stated above, a target program can be downloaded to memory and executed from the address chosen with the following b-record:

1122334400 execute from 11223344

The target program may exit and return to the bootloader program by jumping to address 0x00000100, where the bootloader program starts.

9.3 Instruction Buffer Usage

An 8-word instruction buffer is provided for ARM920T core vector table storage, instruction and data storage. The buffer starts at 0x00000004. Up to eight instructions can be loaded to the instruction buffer for execution.Usually, the last instruction is an unconditional jump instruction (jmp) that jumps to the start of the bootloader program (0x00000100).

MOTOROLA

Bootstrap Mode Operation

9-3

Bootstrap Mode Operation

Code Example 9-2 fills memory locations starting from0x00310000 to 0x003100FF (the length of 0x100) with 0x12345678.

ldr ldr ldr ldr

Code Example 9-2. Instruction Buffer Sample

r1,=0x00310000 r2,=0x100 r3,=0x12345678 r4,=0x00000100

// starting address is 0x0031130100FF

// length is 0x100

// data to fill is 0x12345678

// bootloader program loop: str r3,[r1, r2] subs r2,r2, #4 bne mov loop pc, r4

// store data

// decrement address

// loop back till r2 down to 0x0

// return to bootloader program

Because the instruction buffer is of limited size, the programmer cannot do everything at the same time.

The program can be broken into five parts, as shown in Table 9-3.

Table 9-3. Program Breakdown

Part Code

1

2

3

4 ldr mov ldr mov ldr mov ldr mov r4,=0x00000100 pc, r4 r1,=0x00310000 pc, r4 r2,=0x00000100 pc, r4 r3,=0x12345678 pc, r4

// bootloader address 0x00000100

// return to bootloader program

// starting address is 0x00310000

// return to bootloader program

// length is 0x100

// return to bootloader program

// data to fill is 0x12345678

// return to bootloader program

5 loop str r3,[r1, r2] subs r2,r2, #4 bne mov loop pc, r4

// store data

// decrement address

// loop back till r2 down to 0x0

// return to bootloader program

Breaking down the register initialization into three parts is not mandatory, however it produces similar b-records and therefore is easier to manage.

The resulting b-records appear in Table 9-4.

Table 9-4. Resulting B-Records

B-Record Number B-Record

1

2

3

4

00000004 08E3A04F40E1A0F004

0000000400

00000004 08E3A019C4E1A0F004

0000000400

00000004 08E3A02F40E1A0F004

0000000400

00000004 0CE59F3000E1A0F00412345678

0000000400

9-4

MC9328MX1 Reference Manual

MOTOROLA

B-Record Number

5

Simple Read/Write Examples

Table 9-4. Resulting B-Records (Continued)

B-Record

00000004 0FE7813002E25220041AFFFFFCE1A0F004

0000000400

Note that all b-records start at the same address, 0x00000004, which is the starting address of the instruction buffer. B-records 1, 2, and 3 are very similar and can be used as prototype b-records for general-purpose register initialization.

Therefore, the resulting b-record file will be as follows:

Code Example 9-3. Bootloader B-Record

00000004 08E3A04F40E1A0F004

0000000400

00000004 08E3A019C4E1A0F004

0000000400 initialize r4 to 0x00000100 (bootloader start) execute and return to bootloader initialize r1 to 0x00310000 (start) execute and return to bootloader

00000004 08E3A02F40E1A0F004

0000000400 initialize r2 to 0x100 (length) execute and return to bootloader

00000004 0CE59F3000E1A0F00412345678

0000000400 initialize r3 to 0x12345678 (content) execute and return to bootloader

00000004 0FE7813002E25220041AFFFFFCE1A0F004

0000000400 memory fill execute and return to bootloader

9.4 Simple Read/Write Examples

Table 9-5 provides examples demonstrating how to perform memory and register reads/writes of various data sizes. Code Example 9-4 shows an example of the code used for Vector Tables

IRQ_Addr

FIQ_Addr

NOP

NOP

NOP

DCD

DCD

NOP

LDR

LDR

DCD

PC, IRQ_Addr

PC, FIQ_Addr

0

Code Example 9-4.

C_IRQ_Handler

C_FIQ_Handler

; 0x00

; 0x04 (programmable buffer)

; 0x08 (programmable buffer)

; 0x0C (programmable buffer)

; 0x10 (programmable buffer)

; 0x14 (programmable buffer)

; 0x18 (programmable buffer)

; 0x1C (programmable buffer)

; 0x20 (programmable buffer)

Example Type

Read 3 bytes starting from location

0x00310000

Read 3 half-words starting from location

0x00310000

Table 9-5. Read/Write Examples

B-Record

0031000023

Return Value

0031000003XXYYZZ/

(where XX, YY, and ZZ are data in byte)

0031000066

(6 bytes = 3 half-words)

0031000066XXXXYYYYZZZZ/

(where XXXX, YYYY, and ZZZZ are data in half-word)

MOTOROLA

Bootstrap Mode Operation

9-5

Bootstrap Mode Operation

Table 9-5. Read/Write Examples (Continued)

B-Record Return Value Example Type

Read 3 words starting from location

0x00310000

00310000EC

(12 bytes = 3 words)

00310000ECXXXXXXXXYYYYYYYYZZZZZZZZ/

(where XXXXXXXX, YYYYYYYY, and ZZZZZZZZ are data in word)

Write 3 bytes starting from location

0x00310000

Write 3 half-words starting from location

0x00310000

Write 3 words starting from location

0x00310000

0031000003112233

0031000046111122223333

(6 bytes = 3 half-words)

00310000CC111111112222

222233333333

(12 bytes = 3 words)

0031000003112233/

0031000046111122223333/

00310000CC111111112222222233333333/

9-6

MC9328MX1 Reference Manual

MOTOROLA

Bootloader Flowchart

9.5 Bootloader Flowchart

Figure 9-1 on page 9-7 illustrates how the bootloader program operates inside the MC9328MX1. The bootloader starts when the MC9328MX1 enters bootstrap mode.

START

Initialize

UART

Receive a Bootstrap

Record

Data COUNT = 0?

NO

YES

Run Program

Starting at ADDR

Data COUNT &

Data SIZE

Valid?

YES

NO

ECHO *

Read?

YES

NO

Store Data to

ADDR

Read Data From

ADDR

ECHO Data

Figure 9-1. Bootloader Program Operation

ECHO /

9.6 Special Notes

The following summary items may be helpful when working in bootstrap mode.

• A b-record is a string of uppercase hex characters with optional comments that follow.

• Comments in a b-record or b-record file must not contain any word or symbol that is longer than nine characters. However, the following characters can be used in a string of any length (all of these have an ASCII code value that is less than 0x30):

— space

MOTOROLA

Bootstrap Mode Operation

9-7

Bootstrap Mode Operation

— ! (exclamation point)

— “ (quotation mark)

— # (number sign)

— $ (dollar sign)

— % (percentage symbol)

— & (ampersand)

— ( (opening parenthesis)

— ) (closing parenthesis)

— * (asterisk)

— + (plus sign)

— - (minus sign)

— . (period)

— / (forward slash)

— , (comma)

• The bootloader program echoes all characters being received, however only those having an ASCII code value greater than or equal to 0x30 are kept for b-record assembling. Sending a character that is not a b-record (ASCII code value less than 0x30) will force the bootloader to start a new b-record.

• General-purpose registers r7–r14 and supervisor scratch registerss3 are used by the bootloader program. Writing to these registers may corrupt the bootloader program.

• Please visit the DragonBall Web site for bootstrap utility programs.

9-8

MC9328MX1 Reference Manual

MOTOROLA

Chapter 10

Interrupt Controller (AITC)

This chapter describes the ARM9 Interrupt Controller (AITC) that is used to control and prioritize up to 64 interrupts in the MC9328MX1. This chapter describes the registers and bit settings plus all other information necessary to write the software necessary to write interrupt service routines.

10.1 Introduction

The MC9328MX1 interrupt controller (AITC) is a 32-bit peripheral that collects interrupt requests from a maximum of 64 sources and provides an interface to the ARM920T processor.

AITC_FIQ

64

FIVECTOR

INTIN

INTENABLE

64

64

64

FIPEND

Priority

Encoder

6 FIAD

AITC_BLOCK_ARB

FORCE

64

INTTYPE

64

NIPEND

Software

Priority

Encoder

6

NIAD

64

AITC_IRQ

AITC_RDATA_OVR

NM

HADDR

32

Equals

0x00000018

Equals

0x0000001C

Opcode

Generator

32

AITC_RDATA

HREADY

FM

Figure 10-1. AITC Block Diagram

The AITC performs the following functions:

• Supports a maximum of 64 interrupt sources

• Supports fast and normal interrupts

• Selects normal or fast interrupt request for any interrupt source

• Indicates pending interrupt sources via a register for normal and fast interrupts

MOTOROLA

Interrupt Controller (AITC)

10-1

Interrupt Controller (AITC)

• Detects all pending interrupts and distinguishes by priority level

• Independently enables or disables any interrupt source

• Provides a mechanism for software to schedule an interrupt

• Supports a maximum of 16 software controlled priority levels for normal interrupts and priority masking

10.2 Operation

The interrupt controller consists of a set of control registers and associated logic to perform interrupt masking, priority support, and hardware acceleration of normal interrupts.

The interrupt source registers (INTSRCH and INTFRCL) are a pair of 32-bit status registers with a single interrupt source associated with each of the 64 bits. An interrupt line or set of interrupt lines is routed from each interrupt source to the INTSRCH or INTFRCL register. This configuration allows the ARM920T processor of the MC9328MX1 to monitor a maximum of 64 distinct interrupt sources.

Interrupt requests can be forcibly asserted through the interrupt force registers (INTFRCH and INTFRCL).

Each bit in these registers is logically ORed with the corresponding hardware request line prior to input to the INTSRCH or INTFRCL registers.

There is a corresponding set of interrupt enable registers (INTENABLEH and INTENABLEL), each

32 bits wide, that allow individual bit masking of the INTSRCH and INTFRCL registers. There is also a corresponding set of interrupt type registers (INTTYPEH and INTTYPEL) that selects whether an interrupt source generates a normal or fast interrupt to the ARM920T processor.

There is a corresponding set of normal interrupt pending registers (NIPNDH and NIPNDL) that indicate pending normal interrupt requests, and are equivalent to the logical AND of the interrupt source registers

(INTSRCH and INTSRCL), the interrupt enable registers (INTENABLEH and INTENABLEL), and the

NOT of the interrupt type registers (INTTYPEH and INTTYPEL). The NIPNDH and NIPNDL register bits are bit-wise NORed together to generate the nIRQ signal that is routed to the ARM920T processor.

This ARM920T processor input signal is maskable by the normal interrupt disable bit (I bit) in the program status register (CPSR). The normal interrupt vector register (NIVECSR) indicates the vector index of highest priority pending normal interrupt.

There is a corresponding set of fast interrupt pending registers (FIPNDH and FIPNDL) that indicate pending fast interrupt requests, and are equivalent to the logical AND of the interrupt source registers

(INTSRCH and INTSRCL), the interrupt enable registers (INTENABLEH and INTENABLEL), and the interrupt type registers (INTTYPEH and INTTYPEL). The FIPNDH and FIPNDL register bits are bit-wise

NORed together to generate the nFIQ signal that is routed to the ARM920T processor. This ARM920T processor input signal is maskable by the fast interrupt disable bit (F bit) in the CPSR. The fast interrupt vector register (FIVECSR) indicates the vector index of highest priority pending fast interrupt.

All interrupt controller registers are readable and writable in supervisor mode only. Writes attempted to read-only registers are ignored. These registers must be written with 32-bit stores only.

The INTFRCH and INTFRCL registers are provided for software generation of interrupts. By enabling interrupts for these bit positions, software can force an interrupt request. This register also provides an alternate method of interrupt assertion for debugging hardware interrupt service routines.

The interrupt requests are prioritized in the following order:

1. Fast interrupt requests, in order of highest number

2. Normal interrupt requests, in order of highest priority level, then highest source number with the same priority

10-2

MC9328MX1 Reference Manual

MOTOROLA

AITC Interrupt Controller Signals

The AITC provides 16 software controlled priority levels for normal interrupts and every interrupt can be placed in any priority level. The AITC also provides a normal interrupt priority level mask (NIMASK) that disables any interrupt with a priority level less than or equal to the mask. When a level 0 normal interrupt and a level 1 normal interrupt are asserted at the same time, the level 1 normal interrupt is selected unless

NIMASK has disabled level 1 normal interrupts. When two level 1 normal interrupts are asserted at the same time, the level 1 normal interrupt with the highest source number is selected unless NIMASK has disabled level 1 normal interrupts.

10.3 AITC Interrupt Controller Signals

The active-low INTIN [63:0] input signals indicate that a peripheral device is requesting an interrupt to the interrupt controller. The interrupt controller recognizes an interrupt is asserted on the rising edge of the clock and does not latch and hold the interrupt. The peripheral must keep the interrupt request asserted until the software acknowledges and clears the interrupt request.

The interrupt source assignment of INTIN [63:0] is shown Table 10-1. Interrupt sources in the table that are labeled ‘unused’ may be used by software to force an interrupt request for a specific source using either the INTFRCH or INTRFRCL registers.

Table 10-1. Interrupt Assignment

Bit # Name of Interrupt Bit # Name of Interrupt

12

13

14

15

10

11

8

9

16

17

6

7

4

5

2

3

0

1

Unused

Unused

Unused

Unused

Unused

PEN_UP_INT

CSI_INT

MMA_MAC_INT

MMA_INT

COMP_INT

MSIRQ

GPIO_INT_PORTA

GPIO_INT_PORTB

GPIO_INT_PORTC

LCDC_INT

SIM_IRQ

SIM_DATA

RTC_INT

44

45

46

47

40

41

42

43

48

49

36

37

38

39

32

33

34

35

Unused

PEN_DATA_INT

PWM_INT

MMC_IRQ

Unused

Unused

Unused

I2C_INT

SPI2_INT

SPI1_INT

SSI_TX_INT

SSI_TX_ERR_INT

SSI_RX_INT

SSI_RX_ERR_INT

TOUCH_INT

USBD_INT [0]

USBD_INT [1]

USBD_INT [2]

MOTOROLA

Interrupt Controller (AITC)

10-3

Interrupt Controller (AITC)

Bit #

Table 10-1. Interrupt Assignment (Continued)

Name of Interrupt Bit # Name of Interrupt

26

27

28

29

30

31

22

23

24

25

18

19

20

21

RTC_SAM_INT

UART2_MINT_PFERR

UART2_MINT_RTS

UART2_MINT_DTR

UART2_MINT_UARTC

UART2_MINT_TX

UART2_MINT_RX

UART1_MINT_PFERR

UART1_MINT_RTS

UART1_MINT_DTR

UART1_MINT_UARTC

UART1_MINT_TX

UART1_MINT_RX

Unused

58

59

60

61

62

63

54

55

56

57

50

51

52

53

USBD_INT [3]

USBD_INT [4]

USBD_INT [5]

USBD_INT [6]

Unused

BTSYS

BTTIM

BTWUI

TIMER2_INT

TIMER1_INT

DMA_ERR

DMA_INT

GPIO_INT_PORTD

WDT_INT

10.4 Programming Model

The AITC module includes 26 user-accessible 32-bit registers. All of these registers are single cycle access because the AITC sits on the native bus of the ARM920T processor. Table 10-2 summarizes these registers and their addresses. Table 10-3 provides an overview of the register fields.

Table 10-2. AITC Module Register Memory Map

Description

Interrupt Control Register

Normal Interrupt Mask Register

Interrupt Enable Number Register

Interrupt Disable Number Register

Interrupt Enable Register High

Interrupt Enable Register Low

Interrupt Type Register High

Interrupt Type Register Low

Normal Interrupt Priority Level Register 7

Name Address

INTCNTL

NIMASK

INTENNUM

0x00223000

0x00223004

0x00223008

INTDISNUM 0x0022300C

INTENABLEH 0x00223010

INTENABLEL 0x00223014

INTTYPEH 0x00223018

INTTYPEL 0x0022301C

NIPRIORITY7 0x00223020

10-4

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Table 10-2. AITC Module Register Memory Map (Continued)

Description Name Address

Normal Interrupt Priority Level Register 6

Normal Interrupt Priority Level Register 5

Normal Interrupt Priority Level Register 4

Normal Interrupt Priority Level Register 3

NIPRIORITY6 0x00223024

NIPRIORITY5 0x00223028

NIPRIORITY4 0x0022302C

NIPRIORITY3 0x00223030

Normal Interrupt Priority Level Register 2

Normal Interrupt Priority Level Register 1

NIPRIORITY2 0x00223034

NIPRIORITY1 0x00223038

Normal Interrupt Priority Level Register 0

Normal Interrupt Vector and Status Register

NIPRIORITY0 0x0022303C

NIVECSR 0x00223040

Fast Interrupt Vector and Status Register

Interrupt Source Register High

Interrupt Source Register Low

Interrupt Force Register High

Interrupt Force Register Low

Normal Interrupt Pending Register High

Normal Interrupt Pending Register Low

Fast Interrupt Pending Register High

Fast Interrupt Pending Register Low

FIVECSR

INTSRCH

INTSRCL

INTFRCH

INTFRCL

NIPNDH

NIPNDL

FIPNDH

FIPNDL

0x00223044

0x00223048

0x0022304C

0x00223050

0x00223054

0x00223058

0x0022305C

0x00223060

0x00223064

MOTOROLA

Interrupt Controller (AITC)

10-5

Interrupt Controller (AITC)

Table 10-3. Register Field Summary

R

NIPRIORITY5

W

R

NIPRIORITY4

W

R

NIPRIORITY3

W

R

NIPRIORITY2

W

R

NIPRIORITY1

W

R

NIPRIORITY0

W

NIVECSR

FIVECSR

INTSRCH

R

W

R

W

R

W

Name

INTCNTL

NIMASK

W

31 30 29 28 27 26 25 24 23 22 21

R 0 0 0 0 0 0 0 0 0 0 0

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NIAD FIAD

R 0

W

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NIMASK

0 0

INTENNUM

INTDISNUM

R 0 0 0 0 0 0 0 0 0 0 0

W

R 0 0 0 0 0 0 0 0 0 0 0

W

R

INTENABLEH

W

0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ENNUM

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISNUM

INTENABLE [63:32]

INTENABLEL

R

W

INTTYPEH

R

W

INTTYPEL

R

W

R

NIPRIORITY7

W

R

NIPRIORITY6

W

NIPR63

NIPR55

NIPR62

NIPR54

NIPR61

NIPR53

INTENABLE [31:0]

INTTYPE [63:32]

INTTYPE [31:0]

NIPR60

NIPR52

NIPR59

NIPR51

NIPR58

NIPR50

NIPR57 NIPR56

NIPR49 NIPR48

NIPR47

NIPR39

NIPR31

NIPR23

NIPR15

NIPR7

NIPR46

NIPR38

NIPR30

NIPR22

NIPR14

NIPR6

NIPR45

NIPR37

NIPR29

NIPR21

NIPR13

NIPR5

NIVECTOR

NIPR44

NIPR36

NIPR28

NIPR20

NIPR12

NIPR4

FIVECTOR

INTIN [63:32]

NIPR43

NIPR35

NIPR27

NIPR19

NIPR11

NIPR3

NIPR42

NIPR34

NIPR26

NIPR18

NIPR10

NIPR2

NIPR41 NIPR40

NIPR33 NIPR32

NIPR25 NIPR24

NIPR17 NIPR16

NIPRILVL

NIPR9

NIPR1

NIPR8

NIPR0

10-6

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Name

INTSRCL

INTFRCH

INTFRCL

NIPNDH

NIPNDL

FIPNDH

FIPNDL

R

W

R

W

R

W

R

W

R

W

R

W

R

W

Table 10-3. Register Field Summary (Continued)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INTIN [31:0]

FORCE [63:32]

FORCE [31:0]

NIPEND [63:32]

NIPEND [31:0]

FIPEND [63:32]

FIPEND [31:0]

10.4.1 Interrupt Control Register

The Interrupt Control Register (INTCNTL) is located on the ARM920T processor’s native bus, is accessible in 1 cycle, and can be accessed only in supervisor mode. This register must be accessed only on word (32-bit) boundaries.

INTCNTL

BIT

TYPE

RESET

31 r

0

30 r

0

29 r

0

28 r

0 r

0

27

Interrupt Control Register

26 r

0

25 r

0

24 23 r

0

0x0000 r

0

22 r

0

21 r

0

20 19

NIAD FIAD rw

0 rw

0

Addr

0x00223000

18 17 16 r

0 r

0 r

0

BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TYPE

RESET

Name

Reserved

Bits 31–21 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0

Table 10-4. Interrupt Control Register Description

Description

Reserved—These bits are reserved and should read 0.

r

0 r

0

Settings

r

0 r

0

MOTOROLA

Interrupt Controller (AITC)

10-7

Interrupt Controller (AITC)

Name

NIAD

Bit 20

Table 10-4. Interrupt Control Register Description (Continued)

Description Settings

Normal Interrupt Arbiter Disable

—Enables/Disables the assertion of a bus request to the ARM9 core when the normal interrupt signal (nIRQ) is asserted. When an alternate master has ownership of the bus when a normal interrupt occurs, the bus is given back to the ARM9 core after the DMA device has completed its accesses, so the IRQ_DIS bit does not affect alternate master accesses that are in progress.

0 = Disregard the normal interrupt flag when evaluating bus requests

1 = Normal interrupt flag prevents alternate masters from accessing the system bus

FIAD

Bit 19

Reserved

Bits 18–0

Note:

To prevent an alternate master from accessing the bus during an interrupt service routine, do not clear the interrupt flag until the end of the service routine.

Fast Interrupt Arbiter Disable

—Enables/Disables the assertion of a bus request to the ARM9 core when the fast interrupt signal (nFIQ) is asserted. When an alternate master has ownership of the bus when a fast interrupt occurs, the bus is given back to the ARM9 core after the DMA device has completed its accesses, so the IRQ_DIS bit does not affect alternate master accesses that are in progress.

0 = Disregard the fast interrupt flag when evaluating bus requests

1 = Fast interrupt flag prevents alternate masters from accessing the system bus

Note:

To prevent an alternate master from accessing the bus during an interrupt service routine, do not clear the interrupt flag until the end of the service routine.

Reserved—These bits are reserved and should read 0.

10-8

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

10.4.2 Normal Interrupt Mask Register

The Normal Interrupt Mask Register (NIMASK) controls the normal interrupt mask level. All normal interrupts with a priority level less than or equal to the NIMASK are disabled. The priority levels of normal interrupts are determined by the normal interrupt priority level registers (NIPRIORITY7, NIPRIORITY6,

NIPRIORITY5, NIPRIORITY4, NIPRIORITY3, NIPRIORITY2, NIPRIORITY1, and NIPRIORITY0).

The reset state of this register does not disable any normal interrupts.

Writing all 1’s, or

1, to the NIMASK sets the normal interrupt mask to

1 and does not disable any normal interrupt priority levels.

This hardware mechanism creates reentrant normal interrupt routines by disabling lower priority normal interrupts. Refer to Section 10.5.6, “Writing Reentrant Normal Interrupt Routines,” on page 10-36 for more details on the use of the NIMASK register.

This register is located on the ARM920T processor’s native bus, is accessible in 1 cycle, and can be accessed only in supervisor mode. This register must be accessed only on word (32-bit) boundaries.

NIMASK

BIT 31 30 29 28

Normal Interrupt Mask Register

27 26 25 24 23 22 21 20 19

Addr

0x00223004

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–5

NIMASK

Bits 4–0 r

0

15 14 13 12 11 10 9 8 7 6 5 4 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x001F r

0 r

0 r

0 rw

1

Table 10-5. Normal Interrupt Mask Register Description

Description Settings

Reserved—These bits are reserved and should read 0.

3 rw

1

2

NIMASK rw

1

1 rw

1

0 rw

1

Normal Interrupt Mask

—Controls normal interrupt mask level. All normal interrupts of priority level less than or equal to the

NIMASK are disabled. Settings are shown in decimal. Setting bit 4 disables all normal interrupts.

0 = Disable priority level 0 normal interrupts

1 = Disable priority level 1 and lower normal interrupts

...

16+ = Disable all normal interrupts.

MOTOROLA

Interrupt Controller (AITC)

10-9

Interrupt Controller (AITC)

10.4.3 Interrupt Enable Number Register

The Interrupt Enable Number Register (INTENNUM) provides hardware accelerated enabling of interrupts. Any write to INTENNUM enables one interrupt source. For example, when the 6 LSBs =

000000, interrupt source 0 is enabled; when the 6 LSBs = 000001, interrupt source 1 is enabled, and so forth. This register is decoded into a single hot mask that is logically ORed with the INTENABLEH and the INTENABLEL registers.

This hardware mechanism removes the requirement for an atomic read/modify/write sequence to enable an interrupt source. For example, to enable interrupts 10 and 20, the software performs two writes to the

AITC: first write 10, then write 20 to the INTENNUM register (the order of the writes is irrelevant to the

AITC).

This register is located on the ARM920T processor’s native bus, is accessible in 1 cycle, and can be accessed only in supervisor mode. This register must be accessed only on word (32-bit) boundaries. This register is self-clearing and therefore always reads back all 0s.

INTENNUM

BIT 31 30 29 28

Interrupt Enable Number Register

27 26 25 24 23 22 21 20 19

Addr

0x00223008

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7 r

0

0x0000 r

0

6 r

0

5 4 3 2

ENNUM

1 0 slfclr slfclr slfclr slfclr slfclr slfclr

0 0 0 0 0 0

Table 10-6. Interrupt Enable Number Register Description

Description Settings Name

Reserved

Bits 31–6

Reserved—These bits are reserved and should read 0.

ENNUM

Bits 5–0

Interrupt Enable Number

—Enables/Disables the interrupt source associated with this value.

0x00 = Enable interrupt source 0

0x01 = Enable interrupt source 1

...

0x3F = Enable interrupt source 63

10-10

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

10.4.4 Interrupt Disable Number Register

The Interrupt Disable Number Register (INTDISNUM) provides hardware accelerated disabling of interrupts. Any write to this register disables one interrupt source. When the 6 LSBs = 000000, then interrupt source 0 is disabled; when the 6 LSBs = 000001, then interrupt source 1 is disabled, and so forth.

This register is decoded into a single hot mask that is inverted and logically ANDed with the

INTENABLEH and the INTENABLEL registers.

This hardware mechanism removes the requirement for an atomic read/modify/write sequence to disable an interrupt source. To disable interrupts 10 and 20, the software performs two writes to the AITC: first write 10, then write 20 to INTDISNUM register (the order of the writes is irrelevant to the AITC).

This register is located on the ARM920T processor’s native bus, is accessible in 1 cycle, and can be accessed only in supervisor mode. This register must be accessed only on word (32-bit) boundaries. This register is self-clearing and therefore always reads back all 0s.

INTDISNUM

BIT 31 30 29 28

Interrupt Disable Number Register

27 26 25 24 23 22 21 20 19

Addr

0x0022300C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–6

DISNUM

Bits 5–0 r

0

15 14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7 r

0

0x0000 r

0

6 r

0

5 4 3 2

DISNUM

1 0 slfclr slfclr slfclr slfclr slfclr slfclr

0 0 0 0 0 0

Table 10-7. Interrupt Disable Number Register Description

Settings Description

Reserved—These bits are reserved and should read 0.

Interrupt Disable Number

—Enables/Disables the interrupt source associated with this value.

0x00 = Disable interrupt source 0

0x01 = Disable interrupt source 1

...

0x3F = Disable interrupt source 63

MOTOROLA

Interrupt Controller (AITC)

10-11

Interrupt Controller (AITC)

10.4.5 Interrupt Enable Register High and Interrupt Enable Register

Low

The Interrupt Enable Register High (INTENABLEH) and the Interrupt Enable Register Low

(INTENABLEL) registers enable pending interrupt requests to the ARM920T processor. Each bit in these registers corresponds to an interrupt source available in the system. The reset state of both registers is all interrupts masked.

These registers are updated by the following methods:

• Write directly to the INTENABLEH and INTENABLEL registers

• Set bits with the INTENNUM register

• Clear bits with the INTDISNUM register

These registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.

10.4.5.1 Interrupt Enable Register High

INTENABLEH

BIT 31 30 29

TYPE

RESET rw

0 rw

0 rw

0

28 rw

0

Interrupt Enable Register High

27 26 rw

0 rw

0

25 24 23

INTENABLE [63:48]

22 rw

0 rw

0 rw

0 rw

0

0x0000

21 rw

0

20 rw

0

19

Addr

0x00223010

18 17 16 rw

0 rw

0 rw

0 rw

0

BIT 15

TYPE

RESET rw

0

14 rw

0

13 12 rw

0 rw

0

11 10 rw

0 rw

0 rw

0

9 8 7

INTENABLE [47:32]

6 rw

0 rw

0 rw

0

0x0000

5 rw

0

4 rw

0

3 rw

0

2 1 rw

0 rw

0

Table 10-8. Interrupt Enable Register High Description

Name Description Settings

INTENABLE

Bits 31–0

Interrupt Enable

—Enables/Disables the individual bit interrupt sources to request a normal interrupt or a fast interrupt. When INTENABLE is set and the corresponding interrupt source is asserted, the interrupt controller asserts a normal or a fast interrupt request depending on the associated INTTYPEH and INTTYPEL setting.

0 = Interrupt disabled

1 = Interrupt enabled and generates a normal or fast interrupt upon assertion

0 rw

0

10-12

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

10.4.5.2 Interrupt Enable Register Low

INTENABLEL

BIT 31 30

TYPE

RESET rw

0 rw

0

29 rw

0

28 rw

0

Interrupt Enable Register Low

27 26 rw

0 rw

0

25 24 23

INTENABLE [31:16]

22 rw

0 rw

0 rw

0 rw

0

0x0000

21 rw

0

20 rw

0

19

Addr

0x00223014

18 17 16 rw

0 rw

0 rw

0 rw

0

BIT

TYPE

RESET

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0 rw

0

9 8 7

INTENABLE [15:0]

6 rw

0 rw

0 rw

0

0x0000

5 rw

0

4 rw

0

3 rw

0

2 rw

0

1 rw

0

Table 10-9. Interrupt Enable Register Low Description

Description Name Settings

INTENABLE

Bits 31–0

Interrupt Enable

—Enables/Disables the individual bit interrupt sources to request a normal interrupt or a fast interrupt. When INTENABLE is set and the corresponding interrupt source is asserted, the interrupt controller asserts a normal or a fast interrupt request depending on the associated INTTYPEH and INTTYPEL setting.

0 = Interrupt disabled

1 = Interrupt enabled and generates a normal or fast interrupt upon assertion

0 rw

0

MOTOROLA

Interrupt Controller (AITC)

10-13

Interrupt Controller (AITC)

10.4.6 Interrupt Type Register High and Interrupt Type Register Low

The Interrupt Type Register High (INTTYPEH) and the Interrupt Type Register Low (INTTYPEL) registers select whether a pending interrupt source, when enabled with the INTENABLEH and

INTENABLEL registers, creates a normal interrupt or a fast interrupt to the ARM920T processor. Each bit in this register corresponds to an interrupt source available in the system. The reset state of both registers is all interrupts generate a normal interrupt.

These registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.

10.4.6.1 Interrupt Type Register High

INTTYPEH

BIT 31

TYPE

RESET rw

0

30 29 28 rw

0 rw

0 rw

0

Interrupt Type Register High

27 26 rw

0 rw

0

25 24 23

INTTYPE [63:48]

22 rw

0 rw

0 rw

0 rw

0

0x0000

21 rw

0

20 rw

0

19

Addr

0x00223018

18 17 16 rw

0 rw

0 rw

0 rw

0

BIT

TYPE

RESET

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0 rw

0

9 8 7

INTTYPE [47:32] rw

0 rw

0

6 rw

0

0x0000

5 rw

0

4 rw

0

3 rw

0

2 rw

0

1 rw

0

Table 10-10. Interrupt Type Register High Description

Description Settings Name

INTTYPE

Bits 31–0

Interrupt Type

—Controls whether the individual interrupt sources request a normal interrupt or a fast interrupt.

When a INTTYPE bit is set and the corresponding interrupt source is asserted, the interrupt controller asserts a fast interrupt request.

0 = Interrupt source generates a normal interrupt (nIRQ)

1 = Interrupt source generates a fast interrupt (nFIQ)

0 rw

0

10-14

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

10.4.6.2 Interrupt Type Register Low

INTTYPEL

BIT 31

TYPE

RESET rw

0

30 29 28 rw

0 rw

0 rw

0

Interrupt Type Register Low

27 26 rw

0 rw

0

25 24 23

INTTYPE [31:16]

22 rw

0 rw

0 rw

0 rw

0

0x0000

21 rw

0

20 rw

0

19

Addr

0x0022301C

18 17 16 rw

0 rw

0 rw

0 rw

0

BIT

TYPE

RESET

Name

INTTYPE

Bits 31–0

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0 rw

0

9 8 7

INTTYPE [15:0] rw

0 rw

0

0x0000

6 rw

0

5 rw

0

4 rw

0

3 rw

0

2 rw

0

1 rw

0

0 rw

0

Table 10-11. Interrupt Type Register Low Description

Description

Interrupt Type

—Controls whether the individual interrupt sources request a normal interrupt or a fast interrupt.

When a bit is set in INTTYPE and the corresponding interrupt source is asserted, the interrupt controller asserts a fast interrupt request.

Settings

0 = Interrupt source generates a normal interrupt (nIRQ)

1 = Interrupt source generates a fast interrupt (nFIQ)

10.4.7 Normal Interrupt Priority Level Registers

The normal interrupt priority level registers (NIPRIORITY7, NIPRIORITY6, NIPRIORITY5,

NIPRIORITY4, NIPRIORITY3, NIPRIORITY2, NIPRIORITY1, and NIPRIORITY0) provide a software controllable prioritization of normal interrupts. Normal interrupts with a higher priority level preempt normal interrupts with a lower priority. The reset state of these registers forces all normal interrupts to the lowest priority level.

When a level 0 normal interrupt and a level 1 normal interrupt are asserted at the same time, the level 1 normal interrupt is selected assuming that NIMASK has not disabled level 1 normal interrupts. When two level 1 normal interrupts are asserted at the same time, the level 1 normal interrupt with the highest source number is selected, also assuming that NIMASK has not disabled level 1 normal interrupts.

These registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.

MOTOROLA

Interrupt Controller (AITC)

10-15

Interrupt Controller (AITC)

10.4.7.1 Normal Interrupt Priority Level Register 7

NIPRIORITY7

BIT 31

TYPE

RESET rw

0

30 29

NIPR63 rw

0 rw

0

Normal Interrupt Priority Level Register 7

28 rw

0

27 rw

0

26 25

NIPR62 rw

0 rw

0

24 23 rw

0

0x0000 rw

0

22 21

NIPR61 rw

0 rw

0

20 rw

0

19 rw

0

Addr

0x00223020

16 18 17

NIPR60 rw

0 rw

0 rw

0

BIT

TYPE

RESET

Name

NIPR63

Bits 31–28

NIPR62

Bits 27–24

NIPR61

Bits 23–20

NIPR60

Bits 19–16

NIPR59

Bits 15–12

NIPR58

Bits 11–8

NIPR57

Bits 7–4

NIPR56

Bits 3–0

15 rw

0

14 13

NIPR59 rw

0 rw

0

12 rw

0

11 rw

0

10 9

NIPR58 rw

0 rw

0

8 7 rw

0

0x0000 rw

0 rw

0

6 5

NIPR57 rw

0

4 rw

0

3 rw

0 rw

0

2 1

NIPR56 rw

0

Table 10-12. Normal Interrupt Priority Level Register 7 Description

Description Settings

Normal Interrupt Priority Level

—Selects the software controlled priority level for the associated normal interrupt source.

These registers do not affect the prioritization of fast interrupt priorities.

0000 = Lowest priority normal interrupt

...

1111 = Highest priority normal interrupt

0 rw

0

10-16

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

10.4.7.2 Normal Interrupt Priority Level Register 6

NIPRIORITY6

BIT 31

TYPE

RESET rw

0

30 29

NIPR55 rw

0 rw

0

Normal Interrupt Priority Level Register 6

28 rw

0

27 rw

0

26 25

NIPR54 rw

0 rw

0

24 23 rw

0

0x0000 rw

0

22 21

NIPR53 rw

0 rw

0

20 rw

0

19 rw

0

Addr

0x00223024

16 18 17

NIPR52 rw

0 rw

0 rw

0

BIT

TYPE

RESET

Name

NIPR55

Bits 31–28

NIPR54

Bits 27–24

NIPR53

Bits 23–20

NIPR52

Bits 19–16

NIPR51

Bits 15–12

NIPR50

Bits 11–8

NIPR49

Bits 7–4

NIPR48

Bits 3–0

15 rw

0

14 13

NIPR51 rw

0 rw

0

12 rw

0

11 rw

0

10 9

NIPR50 rw

0 rw

0

8 7 rw

0

0x0000 rw

0 l6 5

NIPR49 rw

0 rw

0

4 rw

0

3 rw

0 rw

0

2 1

NIPR48 rw

0

Table 10-13. Normal Interrupt Priority Level Register 6 Description

Description Settings

Normal Interrupt Priority Level

—Selects the software controlled priority level for the associated normal interrupt source.

These registers do not affect the prioritization of fast interrupt priorities.

0000 = Lowest priority normal interrupt

...

1111 = Highest priority normal interrupt

0 rw

0

MOTOROLA

Interrupt Controller (AITC)

10-17

Interrupt Controller (AITC)

10.4.7.3 Normal Interrupt Priority Level Register 5

NIPRIORITY5

BIT 31

TYPE

RESET rw

0

30 29

NIPR47 rw

0 rw

0

Normal Interrupt Priority Level Register 5

28 rw

0

27 rw

0

26 25

NIPR46 rw

0 rw

0

24 23 rw

0

0x0000 rw

0

22 21

NIPR45 rw

0 rw

0

20 rw

0

19 rw

0

Addr

0x00223028

16 18 17

NIPR44 rw

0 rw

0 rw

0

BIT

TYPE

RESET

Name

NIPR47

Bits 31–28

NIPR46

Bits 27–24

NIPR45

Bits 23–20

NIPR44

Bits 19–16

NIPR43

Bits 15–12

NIPR42

Bits 11–8

NIPR41

Bits 7–4

NIPR40

Bits 3–0

15 rw

0

14 13

NIPR43 rw

0 rw

0

12 rw

0

11 rw

0

10 9

NIPR42 rw

0 rw

0

8 7 rw

0

0x0000 rw

0 rw

0

6 5

NIPR41 rw

0

4 rw

0

3 rw

0 rw

0

2 1

NIPR40 rw

0

Table 10-14. Normal Interrupt Priority Level Register 5 Description

Description Settings

Normal Interrupt Priority Level

—Selects the software controlled priority level for the associated normal interrupt source.

These registers do not affect the prioritization of fast interrupt priorities.

0000 = Lowest priority normal interrupt

...

1111 = Highest priority normal interrupt

0 rw

0

10-18

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

10.4.7.4 Normal Interrupt Priority Level Register 4

NIPRIORITY4

BIT

TYPE

RESET

31 rw

0

30 29

NIPR39 rw

0 rw

0

Normal Interrupt Priority Level Register 4

28 rw

0

27 rw

0

26 25

NIPR38 rw

0 rw

0

24 23 rw

0

0x0000 rw

0

22 21

NIPR37 rw

0 rw

0

20 rw

0

19 rw

0

Addr

0x0022302C

16 18 17

NIPR36 rw

0 rw

0 rw

0

BIT

TYPE

RESET

Name

NIPR39

Bits 31–28

NIPR38

Bits 27–24

NIPR37

Bits 23–20

NIPR36

Bits 19–16

NIPR35

Bits 15–12

NIPR34

Bits 11–8

NIPR33

Bits 7–4

NIPR32

Bits 3–0

15 rw

0

14 13

NIPR35 rw

0 rw

0

12 rw

0

11 rw

0

10 9

NIPR34 rw

0 rw

0

8 7 rw

0

0x0000 rw

0 rw

0

6 5

NIPR33 rw

0

4 rw

0

3 rw

0 rw

0

2 1

NIPR32 rw

0

Table 10-15. Normal Interrupt Priority Level Register 4 Description

Description Settings

Normal Interrupt Priority Level

—Selects the software controlled priority level for the associated normal interrupt source.

These registers do not affect the prioritization of fast interrupt priorities.

0000 = Lowest priority normal interrupt

...

1111 = Highest priority normal interrupt

0 rw

0

MOTOROLA

Interrupt Controller (AITC)

10-19

Interrupt Controller (AITC)

10.4.7.5 Normal Interrupt Priority Level Register 3

NIPRIORITY3

BIT 31

TYPE

RESET rw

0

30 29

NIPR31 rw

0 rw

0

Normal Interrupt Priority Level Register 3

28 rw

0

27 rw

0

26 25

NIPR30 rw

0 rw

0

24 23 rw

0

0x0000 rw

0

22 21

NIPR29 rw

0 rw

0

20 rw

0

19 rw

0

Addr

0x00223030

16 18 17

NIPR28 rw

0 rw

0 rw

0

BIT

TYPE

RESET

Name

NIPR31

Bits 31–28

NIPR30

Bits 27–24

NIPR29

Bits 23–20

NIPR28

Bits 19–16

NIPR27

Bits 15–12

NIPR26

Bits 11–8

NIPR25

Bits 7–4

NIPR24

Bits 3–0

15 rw

0

14 13

NIPR27 rw

0 rw

0

12 rw

0

11 rw

0

10 9

NIPR26 rw

0 rw

0

8 7 rw

0

0x0000 rw

0 rw

0

6 5

NIPR25 rw

0

4 rw

0

3 rw

0 rw

0

2 1

NIPR24 rw

0

Table 10-16. Normal Interrupt Priority Level Register 3 Description

Description Settings

Normal Interrupt Priority Level

—Selects the software controlled priority level for the associated normal interrupt source.

These registers do not affect the prioritization of fast interrupt priorities.

0000 = Lowest priority normal interrupt

...

1111 = Highest priority normal interrupt

0 rw

0

10-20

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

10.4.7.6 Normal Interrupt Priority Level Register 2

NIPRIORITY2

BIT 31

TYPE

RESET rw

0

30 29

NIPR23 rw

0 rw

0

Normal Interrupt Priority Level Register 2

28 rw

0

27 rw

0

26 25

NIPR22 rw

0 rw

0

24 23 rw

0

0x0000 rw

0

22 21

NIPR21 rw

0 rw

0

20 rw

0

19 rw

0

Addr

0x00223034

16 18 17

NIPR20 rw

0 rw

0 rw

0

BIT

TYPE

RESET

Name

NIPR23

Bits 31–28

NIPR22

Bits 27–24

NIPR21

Bits 23–20

NIPR20

Bits 19–16

NIPR19

Bits 15–12

NIPR18

Bits 11–8

NIPR17

Bits 7–4

NIPR16

Bits 3–0

15 rw

0

14 13

NIPR19 rw

0 rw

0

12 rw

0

11 rw

0

10 9

NIPR18 rw

0 rw

0

8 7 rw

0

0x0000 rw

0 rw

0

6 5

NIPR17 rw

0

4 rw

0

3 rw

0 rw

0

2 1

NIPR16 rw

0

Table 10-17. Normal Interrupt Priority Level Register 2 Description

Description Settings

Normal Interrupt Priority Level

—Selects the software controlled priority level for the associated normal interrupt source.

These registers do not affect the prioritization of fast interrupt priorities.

0000 = Lowest priority normal interrupt

...

1111 = Highest priority normal interrupt

0 rw

0

MOTOROLA

Interrupt Controller (AITC)

10-21

Interrupt Controller (AITC)

10.4.7.7 Normal Interrupt Priority Level Register 1

NIPRIORITY1

BIT 31

TYPE

RESET rw

0

30 29

NIPR15 rw

0 rw

0

Normal Interrupt Priority Level Register 1

28 rw

0

27 rw

0

26 25

NIPR14 rw

0 rw

0

24 23 rw

0

0x0000 rw

0

22 21

NIPR13 rw

0 rw

0

20 rw

0

19 rw

0

Addr

0x00223038

16 18 17

NIPR12 rw

0 rw

0 rw

0

BIT

TYPE

RESET

Name

NIPR15

Bits 31–28

NIPR14

Bits 27–24

NIPR13

Bits 23–20

NIPR12

Bits 19–16

NIPR11

Bits 15–12

NIPR10

Bits 11–8

NIPR9

Bits 7–4

NIPR8

Bits 3–0

15 rw

0

14 13

NIPR11 rw

0 rw

0

12 rw

0

11 rw

0

10 9

NIPR10 rw

0 rw

0

8 7 rw

0

0x0000 rw

0 rw

0

6

NIPR9

5 rw

0

4 rw

0

3 rw

0 rw

0

2

NIPR8

1 rw

0

Table 10-18. Normal Interrupt Priority Level Register 1 Description

Description Settings

Normal Interrupt Priority Level

—Selects the software controlled priority level for the associated normal interrupt source.

These registers do not affect the prioritization of fast interrupt priorities.

0000 = Lowest priority normal interrupt

...

1111 = Highest priority normal interrupt

0 rw

0

10-22

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

10.4.7.8 Normal Interrupt Priority Level Register 0

NIPRIORITY0

BIT

TYPE

RESET

31 rw

0

30

NIPR7

29 rw

0 rw

0

Normal Interrupt Priority Level Register 0

28 rw

0

27 rw

0

26 25

NIPR6 rw

0 rw

0

24 23 rw

0

0x0000 rw

0

22 21

NIPR5 rw

0 rw

0

20 rw

0

19 rw

0

Addr

0x0022303C

16 18 17

NIPR4 rw

0 rw

0 rw

0

BIT

TYPE

RESET

Name

NIPR7

Bits 31–28

NIPR6

Bits 27–24

NIPR5

Bits 23–20

NIPR4

Bits 19–16

NIPR3

Bits 15–12

NIPR2

Bits 11–8

NIPR1

Bits 7–4

NIPR0

Bits 3–0

15 rw

0

14

NIPR3

13 rw

0 rw

0

12 rw

0

11 rw

0

10

NIPR2

9 rw

0 rw

0

8 7 rw

0

0x0000 rw

0 rw

0

6

NIPR1

5 rw

0

4 rw

0

3 rw

0 rw

0

2

NIPR0

1 rw

0

Table 10-19. Normal Interrupt Priority Level Register 0 Description

Description Settings

Normal Interrupt Priority Level

—Selects the software controlled priority level for the associated normal interrupt source.

These registers do not affect the prioritization of fast interrupt priorities.

0000 = Lowest priority normal interrupt

...

1111 = Highest priority normal interrupt

0 rw

0

MOTOROLA

Interrupt Controller (AITC)

10-23

Interrupt Controller (AITC)

10.4.8 Normal Interrupt Vector and Status Register

The Normal Interrupt Vector and Status Register (NIVECSR) specifies the priority of the highest pending normal interrupt and provides the vector index of the interrupt’s service routine. This hardware mechanism removes the requirement for ARM920T processor support of the FF1 command. This number can be directly used as an index into a vector table to select the highest pending normal interrupt source.

This read-only register is located on the ARM920T processor’s native bus, is accessible in 1 cycle, and can be accessed only in supervisor mode. This register must be accessed only on word (32-bit) boundaries.

NIVECSR

BIT

TYPE

RESET

31 r

1

30 r

1

29 r

1 r

1

28

Normal Interrupt Vector and Status

Register

27 26 25 22 21 20 r

1 r

1 r

1

24 23

NIVECTOR r

1

0xFFFF r

1 r

1 r

1 r

1

19 r

1

Addr

0x00223040

18 17 16 r

1 r

1 r

1

BIT

TYPE

RESET

15 r

1

14 r

1

13 r

1

12 r

1

11 r

1

10 r

1

9 r

1

8

NIPRILVL

7 r

1

0xFFFF r

1

6 r

1

5 r

1

4 r

1

3 r

1

2 r

1

1 r

1

0 r

1

Table 10-20. Normal Interrupt Vector and Status Register Description

Name Description Settings

NIVECTOR

Bits 31–16

NIPRILVL

Bits 15–0

Normal Interrupt Vector

—Indicates vector index for the highest pending normal interrupt. Settings are shown in decimal.

0 = Interrupt 0 highest priority pending normal interrupt

1 = Interrupt 1 highest priority pending normal interrupt

...

63 = Interrupt 63 highest priority pending normal interrupt

64+ = No normal interrupt request pending

Normal Interrupt Priority Level

—Indicates the priority level of the highest priority normal interrupt.

This number can be written to the NIMASK to disable the current priority normal interrupts to build a reentrant normal interrupt system. Settings are shown in decimal.

0 = Highest priority normal interrupt is level 0

1 = Highest priority normal interrupt is level 1

...

15 = Highest priority normal interrupt is level

15

16+ = No normal interrupt request pending

10-24

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

10.4.9 Fast Interrupt Vector and Status Register

The Fast Interrupt Vector and Status Register (FIVECSR) specifies the priority of the highest pending fast interrupt and provides the vector index for the interrupt’s service routine. This hardware mechanism removes the requirement for ARM920T processor support of the FF1 command. This number can be directly used as an index into a vector table to select the highest pending fast interrupt source.

This read-only register is located on the ARM920T processor’s native bus, is accessible in 1 cycle, and can be accessed only in supervisor mode. This register must be accessed only on word (32-bit) boundaries.

FIVECSR

BIT 31 30 29

Fast Interrupt Vector and Status Register

28 27 26 21 20 19

Addr

0x00223044

18 17 16

TYPE

RESET r

1 r

1 r

1 r

1 r

1 r

1

25 24 23

FIVECTOR [31:16]

22 r

1 r

1 r

1 r

1

0xFFFF r

1 r

1 r

1 r

1 r

1 r

1

BIT

TYPE

RESET

15 r

1

14 r

1

13 r

1

12 r

1

11 r

1

10 r

1 r

1

9 8 7

FIVECTOR [15:0] r

1 r

1

0xFFFF

6 r

1

5 r

1

4 r

1

3 r

1

2 r

1

1 r

1

0 r

1

Table 10-21. Fast Interrupt Vector and Status Register Description

Settings Name Description

FIVECTOR

Bits 31–0

Fast Interrupt Vector

—Indicates vector index for the highest pending fast interrupt.

0 = Interrupt 0 is highest pending fast interrupt

1 = Interrupt 1 is highest pending fast interrupt

...

63 = Interrupt 63 is highest pending fast interrupt

64+ = not used, does not occur

MOTOROLA

Interrupt Controller (AITC)

10-25

Interrupt Controller (AITC)

10.4.10 Interrupt Source Register High and Interrupt Source Register

Low

The Interrupt Source Register High (INTSRCH) and the Interrupt Source Register Low (INTSRCL) registers are each 32 bits wide. INTSRCH and INTSRCL reflect the status of all interrupt request inputs into the interrupt controller. Bit positions that are not used always read

0

(no request pending). The peripheral circuits generating the requests determine the state of this register out of reset; normally, the requests are inactive.

These read-only registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.

10.4.10.1 Interrupt Source Register High

INTSRCH

BIT 31

TYPE

RESET r

0

30 r

0

29 r

0 r

0

28

Interrupt Source Register High

27 26 r

0 r

0

25 24 23

INTIN [63:48] r

0 r

0 r

0

0x0000

22 r

0

21 r

0

20 r

0 r

0

19

Addr

0x00223048

18 17 16 r

0 r

0 r

0

BIT

TYPE

RESET

Name

INTIN

Bits 31–0 r

0

15 14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7

INTIN [47:32] r

0

0x0000 r

0

6 r

0

5 r

0

4 r

0

3 r

0

2 r

0

1 r

0

0 r

0

Table 10-22. Interrupt Source Register High Description

Description

Interrupt Source

—Indicates the state of the corresponding hardware interrupt source.

Settings

0 = Interrupt source negated

1 = Interrupt source asserted

NOTE:

The peripheral circuits generating the requests determine the state of this register out of reset; normally, the requests are inactive. This read-only register must be accessed only on word (32-bit) boundaries.

10-26

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

10.4.10.2 Interrupt Source Register Low

INTSRCL

BIT 31

TYPE

RESET r

0

30 r

0

29 r

0 r

0

28

Interrupt Source Register Low

27 26 r

0 r

0

25 24 23

INTIN [31:16] r

0 r

0 r

0

0x0000

22 r

0

21 r

0

20 r

0 r

0

19

Addr

0x0022304C

18 17 16 r

0 r

0 r

0

BIT

TYPE

RESET

Name

INTIN

Bits 31–0 r

0

15 14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7

INTIN [15:0] r

0

0x0000 r

0

6 r

0

5 r

0

4 r

0

3 r

0

2 r

0

1 r

0

0 r

0

Table 10-23. Interrupt Source Register Low Description

Description

Interrupt Source

—Indicates the state of the corresponding hardware interrupt source.

Settings

0 = Interrupt source negated

1 = Interrupt source asserted

NOTE:

The state of this register out of reset is determined by the peripheral circuits generating the requests; normally, the requests are inactive. This read-only register must be accessed only on word (32-bit) boundaries.

MOTOROLA

Interrupt Controller (AITC)

10-27

Interrupt Controller (AITC)

10.4.11 Interrupt Force Register High and Interrupt Force Register

Low

The Interrupt Force Register High (INTFRCH) and the Interrupt Force Register Low (INTFRCL) registers are each 32 bits wide. The interrupt forces registers allow for software generation of interrupts for each of the possible interrupt sources for functional or debugging purposes. The system level design can reserve one or more sources for software purposes to allow software to self-schedule interrupts by forcing one or more of these sources in the appropriate interrupt force register(s).

These registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.

10.4.11.1 Interrupt Force Register High

INTFRCH

BIT 31 30

TYPE

RESET rw

0 rw

0

29 28 rw

0 rw

0

Interrupt Force Register High

27 26 rw

0 rw

0

25 24 23

FORCE [63:48] rw

0 rw

0 rw

0

0x0000

22 rw

0

21 rw

0

20 rw

0

19

Addr

0x00223050

18 17 16 rw

0 rw

0 rw

0 rw

0

BIT

TYPE

RESET

Name

FORCE

Bits 31–0

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0 rw

0

9 8 7

FORCE [47:32] rw

0 rw

0

0x0000

6 rw

0

5 rw

0

4 rw

0

3 rw

0

2 rw

0

1 rw

0

0 rw

0

Table 10-24. Interrupt Force Register High Description

Description

Interrupt Source Force Request

—Forces a request for the corresponding interrupt source.

Settings

0 = Standard interrupt operation

1 = Interrupt forced asserted

10-28

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

10.4.11.2 Interrupt Force Register Low

INTFRCL

BIT 31

TYPE

RESET rw

0

30 29 28 rw

0 rw

0 rw

0

Interrupt Force Register Low

27 26 rw

0 rw

0

25 24 23

FORCE [31:16] rw

0 rw

0 rw

0

0x0000

22 rw

0

21 rw

0

20 rw

0

19

Addr

0x00223054

18 17 16 rw

0 rw

0 rw

0 rw

0

BIT

TYPE

RESET

Name

FORCE

Bits 31–0

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0 rw

0

9 8 7

FORCE [15:0] rw

0 rw

0

0x0000

6 rw

0

5 rw

0

4 rw

0

3 rw

0

2 rw

0

1 rw

0

0 rw

0

Table 10-25. Interrupt Force Register Low Description

Description

Interrupt Source Force Request

—Forces a request for the corresponding interrupt source.

Settings

0 = Standard interrupt operation

1 = Interrupt forced asserted

MOTOROLA

Interrupt Controller (AITC)

10-29

Interrupt Controller (AITC)

10.4.12 Normal Interrupt Pending Register High and Normal Interrupt

Pending Register Low

The Normal Interrupt Pending Register High (NIPNDH) and the Normal Interrupt Pending Register Low

(NIPNDL) registers are 32-bits wide and monitor the outputs of the enable and masking operations. These registers are actually only a set of buffers, so the reset state of these registers is determined by the normal interrupt enable registers, the interrupt mask register, and the interrupt source registers.

These read-only registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.

10.4.12.1 Normal Interrupt Pending Register High

NIPNDH

BIT

TYPE

RESET

31 r

0

30 r

0

29 r

0

Normal Interrupt Pending Register High

28 27 26 20 19

Addr

0x00223058

18 17 16 r

0 r

0 r

0

25 24 23

NIPEND [63:48] r

0 r

0 r

0

0x0000

22 r

0

21 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

NIPEND

Bits 31–0 r

0

15 14 r

0

13 r

0

12 r

0

11 r

0

10 r

0 r

0

9 8 7

NIPEND [47:32] r

0 r

0

0x0000

6 r

0

5 r

0

4 r

0

3 r

0

2 r

0

1 r

0

0 r

0

Table 10-26. Normal Interrupt Pending Register High Description

Description Settings

Normal Interrupt Pending Bit

—Indicates whether a normal interrupt is pending. When a normal interrupt enable bit is set and the corresponding interrupt source is asserted, the interrupt controller asserts a normal interrupt request. The normal interrupt pending bits reflect the interrupt input lines that are asserted and are currently enabled to generate a normal interrupt.

0 = No normal interrupt request

1 = Normal interrupt request pending

10-30

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

10.4.12.2 Normal Interrupt Pending Register Low

NIPNDL

BIT

TYPE

RESET

31 r

0

30 r

0

29 r

0

Normal Interrupt Pending Register Low

28 27 26 20 19

Addr

0x0022305C

18 17 16 r

0 r

0 r

0

25 24 23

NIPEND [31:16] r

0 r

0 r

0

0x0000

22 r

0

21 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

NIPEND

Bits 31–0 r

0

15 14 r

0

13 r

0

12 r

0

11 r

0

10 r

0 r

0

9 8 7

NIPEND [15:0] r

0 r

0

0x0000

6 r

0

5 r

0

4 r

0

3 r

0

2 r

0

Table 10-27. Normal Interrupt Pending Register Low Description

Description Settings

1 r

0

0 r

0

Normal Interrupt Pending Bit

—Indicates whether a normal interrupt is pending. When a normal interrupt enable bit is set and the corresponding interrupt source is asserted, the interrupt controller asserts a normal interrupt request. The normal interrupt pending bits reflect the interrupt input lines that are asserted and are currently enabled to generate a normal interrupt.

0 = No normal interrupt request

1 = Normal interrupt request pending

MOTOROLA

Interrupt Controller (AITC)

10-31

Interrupt Controller (AITC)

10.4.13 Fast Interrupt Pending Register High and Fast Interrupt

Pending Register Low

The Fast Interrupt Pending Register High (FIPNDH) and the Fast Interrupt Pending Register Low

(FIPNDL) registers are 32-bits wide and monitor the outputs of the enable and masking operations. These registers are actually only a set of buffers, so the reset state of these registers is determined by the fast interrupt enable registers, the interrupt mask register, and the interrupt source registers.

These read-only registers are located on the ARM920T processor’s native bus, are accessible in 1 cycle, and can be accessed only in supervisor mode. These registers must be accessed only on word (32-bit) boundaries.

10.4.13.1 Fast Interrupt Pending Register High

FIPNDH

BIT 31

TYPE

RESET r

0

30 29 r

0 r

0 r

0

28

Fast Interrupt Pending Register High

27 26 r

0 r

0

25 24 23

FIPEND [63:48] r

0 r

0 r

0

0x0000

22 r

0

21 r

0

20 r

0 r

0

19

Addr

0x00223060

18 17 16 r

0 r

0 r

0

BIT

TYPE

RESET

Name

FIPEND

Bits 31–0 r

0

15 14 r

0

13 r

0

12 r

0

11 r

0

10 r

0 r

0

9 8 7

FIPEND [47:32] r

0 r

0

0x0000

6 r

0

5 r

0

4 r

0

3 r

0

2 r

0

1 r

0

0 r

0

Table 10-28. Fast Interrupt Pending Register High Description

Description Settings

Fast Interrupt Pending Bit

—Indicates if a fast interrupt request is pending. When a fast interrupt enable bit is set and the corresponding interrupt source is asserted, the interrupt controller asserts a fast interrupt request. The fast interrupt pending bits reflect the interrupt input lines that are asserted and are currently enabled to generate a fast interrupt.

0 = No fast interrupt request pending

1 = Fast interrupt request pending

10-32

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

10.4.13.2 Fast Interrupt Pending Register Low

FIPNDL

BIT 31

TYPE

RESET r

0

30 29 r

0 r

0 r

0

28

Fast Interrupt Pending Register Low

27 26 r

0 r

0

25 24 23

FIPEND [31:16] r

0 r

0 r

0

0x0000

22 r

0

21 r

0

20 r

0 r

0

19

Addr

0x00223064

18 17 16 r

0 r

0 r

0

BIT

TYPE

RESET

Name

FIPEND

Bits 31–0 r

0

15 14 r

0

13 r

0

12 r

0

11 r

0

10 r

0 r

0

9 8 7

FIPEND [15:0] r

0 r

0

0x0000

6 r

0

5 r

0

4 r

0

3 r

0

2 r

0

1 r

0

0 r

0

Table 10-29. Fast Interrupt Pending Register Low Description

Description Settings

Fast Interrupt Pending Bit

—Indicates if a fast interrupt request is pending. When a fast interrupt enable bit is set and the corresponding interrupt source is asserted, the interrupt controller asserts a fast interrupt request. The fast interrupt pending bits reflect the interrupt input lines that are asserted and are currently enabled to generate a fast interrupt.

0 = No fast interrupt request pending

1 = Fast interrupt request pending

MOTOROLA

Interrupt Controller (AITC)

10-33

Interrupt Controller (AITC)

10.5 ARM920T Processor Interrupt Controller Operation

This section discusses the ARM920T processor prioritization of various exceptions and interrupt sources, two methods of enabling or disabling interrupts, and provides a typical pipeline sequence.

10.5.1 ARM920T Processor Prioritization of Exception Sources

The ARM920T processor prioritizes the various exceptions as follows:

• Reset (highest priority)

• Data Abort

• Fast Interrupt

• Normal Interrupt

• Prefetch Abort

• Undefined Instruction and SWI (lowest priority)

10.5.2 AITC Prioritization of Interrupt Sources

The AITC module prioritizes the various interrupt sources by source number. Higher source numbers have higher priority. Fast interrupts always have higher priority than normal interrupts.

Interrupt requests are prioritized as follows:

1. Fast interrupt requests, in order of highest source number

2. Normal interrupt requests, in order of highest priority level, then in order of highest source number with the same priority level

10.5.3 Assigning and Enabling Interrupt Sources

The interrupt controller provides flexible assignment of any interrupt source to either of the two ARM920T processor interrupt request inputs. This is done by setting the appropriate bits in the INTENABLEH and

INTENABLEL registers and the INTTYPEH and INTTYPEL registers. Interrupt assignment is usually done once during system initialization and does not affect interrupt latency.

Interrupt assignment is the first of three steps required to enable an interrupt source, and this is done by the

MC9328MX1 hardware. The second step is to program the source to generate interrupt requests. The final step is to enable the interrupt inputs in the ARM920T processor by clearing the normal interrupt disable (I) and/or the fast interrupt disable (F) bits in the processor status register (CPSR).

10.5.4 Enabling Interrupts Sources

There are two methods of enabling or disabling interrupts in the AITC. The first method is to directly read the INTENABLEH and INTENABLEL registers, logically OR or BIT CLEAR these registers with a generated mask, then write back to the INTENABLEH and INTENABLEL registers.

The second method is performing an atomic write to source number of the INTENNUM register. The

AITC decodes this 6-bit register and enables one of the 64 interrupt sources. The AITC automatically generates a single hot enable mask and logically ORs this mask to the correct INTENABLEH and

INTENABLEL register. To disable interrupts, the procedure is exactly the same except the source number is written to the INTDISNUM register.

10-34

MC9328MX1 Reference Manual

MOTOROLA

ARM920T Processor Interrupt Controller Operation

10.5.5 Typical Interrupt Entry Sequences

The Table 10-30 is a typical pipeline sequence for the ARM920T processor when a normal interrupt occurs. Assuming single cycle memories, it takes approximately 6 clocks from the acknowledgement of the normal interrupt within the ARM920T processor until the first opcode of the interrupt routine is fetched.

Table 10-30. Typical Hardware Accelerated Normal Interrupt Entry Sequence

Time

Address

2

1 0 1 2 3 4 5 6 7 8

Last ADDR before nIRQ

+4 / +2

+8 / +4

0x00000018

+4

+8

Vector Table

N/A nIRQ Routine

+4

+8 nIRQ

Assert

Fetch Dec nIRQ

ACK

Exec

Fetch Dec

Fetch

Link Adjust

Fetch Dec

Fetch

Exec

Dec

Fetch

Data

Vector

Wrbk

Fetch Dec

Fetch

Exec

Dec

Fetch

The Table 10-31 on page 10-35 is a typical pipeline sequence for the ARM920T processor when a fast interrupt occurs, assuming that the FIQ service routine begins at 0x0000001C and single cycle memories.

Table 10-31. Typical Fast Interrupt Entry Sequence

Time

Address

2

1 0 1 2 3

nFIQ

Assert

Last ADDR before nFIQ Fetch

+4 / +2

+8 / +4

0x0000001C nFIQ

ACK

Exec Dec

Fetch Dec

Fetch

Link

Fetch

Adjust

Dec Exec

MOTOROLA

Interrupt Controller (AITC)

10-35

Interrupt Controller (AITC)

+4

+8

Table 10-31. Typical Fast Interrupt Entry Sequence (Continued)

Time

Address

2

1 0 1 2 3

Fetch Dec

Fetch

10.5.6 Writing Reentrant Normal Interrupt Routines

The AITC can create a reentrant normal interrupt system. This enables preempting of lower priority level interrupts by higher priority level interrupts. This requires a small amount of software support and overhead. The following shows the steps necessary to accomplish this:

1. Push the link register (LR_IRQ) onto the stack (SP_IRQ).

2. Push the saved status register (SPSR_IRQ) onto the stack.

3. Read the current value of NIMASK and push this value onto the stack.

4. Read current priority level via NIVECSR.

5. Interrupts of the equal or lesser priority than the current priority level must be masked via the NIMASK register by writing value from NIVECSR.

6. Clear the I bit in the ARM920T processor via a MSR / MRS command sequence (a higher priority normal interrupt can preempt a lower priority one) and change the operating mode of the ARM920T processor to system mode from IRQ mode.

7. Push the System Mode Link Register (LR) onto the stack (SP_USER).

8. The traditional interrupt service routine is now included.

9. Pop the System Mode Link Register (LR) from the stack (SP_USER).

10. Set the I bit in the ARM920T processor via a MSR/MRS command sequence (disables all normal interrupts) and change the operating mode of the ARM920T processor to IRQ mode from system mode.

11. Pop the original value of the normal interrupt mask and write the value to the NIMASK register.

12. Pop the Saved Status Register from the stack (SP_IRQ).

13. Pop the link register from the stack into the PC.

14. Return from nIRQ.

NOTE:

These steps are still in development and are subject to change. Steps 1, 2,

13, and 14 are automatically done by most C compilers and are included for completeness.

10-36

MC9328MX1 Reference Manual

MOTOROLA

Chapter 11

External Interface Module (EIM)

11.1 Overview

The External Interface Module (EIM) handles the interface to devices external to the MC9328MX1, including generation of chip selects for external peripherals and memory, and provides the following features:

• Six chip selects for external devices: CS0, covering a range of 32 Mbyte, and CS1–CS5, covering a range of 16 Mbyte each

• Selectable protection for each chip select

• Reset programmable data port size for CS0

• Programmable data port size for each chip select

• Address suppression during burst mode operations

• Synchronous burst mode support for burst flash devices

• Programmable wait-state generator for each chip select

• Supports big endian and little endian modes of operation

• Programmable general output capability for unused chip select outputs

11.2 EIM I/O Signals

The EIM I/O signals provide communication and control pathways between external devices and the

MC9328MX1. A summary of the I/O signal pins is provided in Table 11-2 on page 11-4. Each signal is described in the following sections.

11.2.1 Address Bus

The A [24:0] signals are address bus outputs used to address external devices.

11.2.2 Data Bus

The D [31:0] signals are bidirectional data bus pins used to transfer data between the MC9328MX1 and an external device.

MOTOROLA

External Interface Module (EIM)

11-1

External Interface Module (EIM)

11.2.3 Read/Write

The R/W output signal indicates if the current bus access is in a read or write cycle. A high (logic one) level indicates a read cycle, and a low (logic zero) level indicates a write cycle.

11.2.4 Control Signals

The OE and EB [3:0] signals are used to control external device’s interface to the external data bus.

11.2.4.1 OE—Output Enable

This active-low output signal indicates the bus access is a read, and enable slave devices to drive the data bus with read data.

11.2.4.2 EB [3:0]—Enable Bytes

These active-low output pins indicate active data bytes for the current access. They may be configured to assert for read and write cycles or for write cycles only as programmed in the CS configuration registers.

EB [0] corresponds to D [31:24], EB [1] corresponds to D [23:16], EB [2] corresponds to D [15:8], and EB

[3] corresponds to D [7:0].

11.2.4.3 DTACK—Data Transfer Acknowledge

The DTACK signal is the external input data acknowledge signal that only supported by CS[5]. When the external DTACK signal is used as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 clocks counts have elapsed.

The maximum wait state supported by the DTACK signal at 96 MHz is 10.645us. This can be calculated by dividing the number of maximum wait state cycles (in this case 1022) by the system clock frequency

(HCLK). For designs requiring a longer wait state time greater than 10.645us, it is necessary to reduce the system clock frequency HCLK to an appropriate value that is less than 96 MHz. The system clock HCLK can be divided by setting the BLCK_DIV bits in the Clock Source Control Register to the desired value.

For more detailed information about setting the BCLK_DIV bits, see Chapter 12, “Phase-Locked Loop and Clock Controller.”

11.2.5 Chip Select Outputs

11.2.5.1 Chip Select 0 (CS0)

The CS0 output signal is active-low and is asserted based on a decode of internal address bus bits A[31:24] of the accessed address, and at reset is based on the value of the BOOTMOD [3:0] inputs. The port size is determined by the state of the BOOTMOD[3:0] inputs. See Section 8.2, “System Boot Mode Selection,” on page 8-7 for more information.

11.2.5.2 Chip Select 1–Chip Select 5 (CS1–CS5)

The CS1 through CS5 output signals are active-low and are asserted based on a decode of the internal address bus bits A [31:24] of the accessed address. When disabled, these pins can be used as programmable general-purpose outputs. Table 11-1 specifies the address range for each Chip Select output.

11-2

MC9328MX1 Reference Manual

MOTOROLA

Pin Configuration for EIM

Table 11-1. Chip Select Address Range

CSEN [x] A [31:24] Chip Select

set set set cleared set set set

-

0001000x

00010010

00010011

00010100

00010101

00010110 inactive

CS0

CS1

CS2

CS3

CS4

CS5

11.2.6 Burst Mode Signals

11.2.6.1 BCLK—Burst Clock

The BCLK output signal is used to clock external burst capable devices to synchronize the loading and incrementing of addresses, and delivery of burst read data to the EIM. Its behavior is affected by the BCM bit in the EIM configuration register and the SYNC, BCD, PME, and BCS bits in the EIM control registers.

11.2.6.2 LBA—Load Burst Address

The LBA active-low output signal is asserted during burst mode accesses to cause the external burst capable device to load a new starting burst address. Assertion of LBA indicates that a valid address is present on the address bus. Its behavior is affected by the SYNC, BCD, PME, and BCS bits in the EIM control registers.

11.2.6.3 ECB—End Current Burst

The ECB active-low input signal is asserted by external burst capable devices to indicate the end of the current (continuous) burst sequence. Following assertion, the EIM terminates the current burst sequence and initiates a new one.

11.3 Pin Configuration for EIM

Table 11-2 lists the pins used for the EIM module. Many of these pins are multiplexed with other functions on the device, and must be configured for EIM operation.

MOTOROLA

External Interface Module (EIM)

11-3

External Interface Module (EIM)

Table 11-2. EIM Pin List

Description Pin Name Direction

External I/O Signals

D [31:0]

A [24:0]

CS [5:0]

DTACK

EB [3:0]

OE

BCLK

LBA input/ output output output

Input output output output output

External 32-bit data bus

External address bus

Active low external chip selects

External input data acknowledge signal for CS5

Active low external enable bytes signals. EB [0] controls D [31:24]*

Active low output enable for external data bus

Clock for external synchronous memories (such as burst flash)

Active low signal sent to flash device causing the external device to latch the address.

Indicates whether external access is a read (high) or write (low) cycle RW output

ECB input input signal identifies when to end an external burst access

*EB [1] controls D [23:16], EB [2] controls D [15:8], EB [3] controls D [7:0]

NOTE:

The user must ensure that the data direction bits in the GPIO are set to the correct direction for proper operation. See Section 32.5.1, “Data Direction

Registers,” on page 32-9 for details.

Table 11-3. Pin Configuration

Setting Configuration Procedure Pins

D [31:0]

A [24]

Not Multiplexed

Primary function of GPIO Port

A [0]

1. Clear bit 0 of Port A GPIO In Use Register (GIUS_A)

2. Clear bit 0 of Port A General Purpose Register (GPR_A)

A [23:16] Primary function of GPIO Port

A [31:24]

1. Clear bits [31:24] of Port A GPIO In Use Register (GIUS_A)

2. Clear bits [31:24] of Port A General Purpose Register (GPR_A)

A [15:1] Not Multiplexed

A [0] Primary function of GPIO Port

A [21]

1. Clear bit 21 of Port A GPIO In Use Register (GIUS_A)

2. Clear bit 21 of Port A General Purpose Register (GPR_A)

CS [5:4] Primary function of GPIO Port

A [23:22]

1. Clear bits [23:22] of Port A GPIO In Use Register (GIUS_A)

2. Clear bits [23:22] of Port A General Purpose Register (GPR_A)

CS [3] Primary function of pin shared with SDRAM’s CSD1

1. Clear bit 1 (SDCS1_SEL) of Function Muxing Control Register

(FMCR)

11-4

MC9328MX1 Reference Manual

MOTOROLA

Pin Configuration for EIM

Setting

Table 11-3. Pin Configuration (Continued)

Configuration Procedure Pins

CS [2] Primary function of pin shared with SDRAM’s CSD0

1. Clear bit 0 (SDCS0_SEL) of Function Muxing Control Register

(FMCR)

CS [1:0] Not Multiplexed

DTACK Primary function of GPIO Port

A[17

1. Clear bit 17 of Port A GPIO In Use Register (GIUS_A)

2. Clear bit 17 of the Port A General Purpose Register (GPR_A

EB [3:0] Not Multiplexed

OE

BCLK

LBA

RW

ECB

Not Multiplexed

Primary function of GPIO Port

A [18]

1. Clear bit 18 of Port A GPIO In Use Register (GIUS_A)

2. Clear bit 18 of Port A General Purpose Register (GPR_A)

Primary function of GPIO Port

A [19]

1. Clear bit 19 of Port A GPIO In Use Register (GIUS_A)

2. Clear bit 19 of Port A General Purpose Register (GPR_A)

Not Multiplexed

Primary function of GPIO Port

A [20]

1. Clear bit 20 of Port A GPIO In Use Register (GIUS_A)

2. Clear bit 20 of Port A General Purpose Register (GPR_A)

MOTOROLA

External Interface Module (EIM)

11-5

External Interface Module (EIM)

11.4 Typical EIM System Connections

The following figures show example connections of the EIM with burst and asynchronous memories:

• Figure 11-1 illustrates a typical set of EIM interfaces to external memory and peripherals.

• Figure 11-2 illustrates the EIM interface to two supported external burst flash devices.

A [16:0]

A [31:0]

CS2

EB [0]

OE

D [31:0]

EB [0]

D [31:24]

Address [16:0]

CS

WE

OE

RAM

128Kx8

Data [7:0]

A [16:1]

EB [0]

EB [1]

EB [1]

CS1

RW

RW

OE

D [31:16]

Address [15:0]

UBS

LBS

CS

RAM

64Kx16

WE

OE

Data [15:0]

External

Interface

Module

CS0

EB [2]

A [19:1]

EB [2]

OE

D [15:0]

Address [18:0]

CS

WE

OE

Intel

Flash

512Kx16

Data [15:0]

A0

CS3

R’W

D [7:0]

RS

E

ACIA

R/W

Data [7:0]

ECB

LBA

BCLK

CS5

CS4

EB [3]

A0

RW

D [7:0]

RS

E

R/W

LCD

Control

Data [7:0]

Figure 11-1. Example of EIM Interface to Memory and Peripherals

11-6

MC9328MX1 Reference Manual

MOTOROLA

Typical EIM System Connections

A [31:0]

LBA

CS0

EB [0]

OE

BCLK

ECB

D [31:0]

External

Interface

Module

CS1

EB [1]

CS3

CS4

CS5

EB [2]

EB [3]

CS2

RW

EB [2]

EB [3]

RW

OE

A [20:1]

Address [19:0]

ADV#

EB [0]

CE#

OE

WE#

OE#

CLK

INTEL

BURST

FLASH

WAIT#

D [31:16]

DQ [15:0]

1Mx16

A [20:1]

Address [19:0]

ADV#

OE

BCLK

CE#

WE#

OE#

CLK

WAIT#

INTEL

BURST

FLASH

D [31:16]

DQ [15:0]

1Mx16

A [16:1]

Address [15:0]

UBS

LBS

CS

RAM

64Kx16

D [15:1]

WE

OE

Data [15:0]

Figure 11-2. Example of EIM Interface to Burst Memory

MOTOROLA

External Interface Module (EIM)

11-7

External Interface Module (EIM)

11.5 EIM Functionality

11.5.1 Configurable Bus Sizing

The EIM supports byte, halfword, and word operands, allowing access to 8-bit ports, 16-bit ports, and

32-bit ports. It does not support misaligned transfers.

The port size is programmable via the DSZ bits in the corresponding chip select control register. In addition, the portion of the data bus used for transfer to or from an 8-bit port or 16-bit port is programmable via the same bits. An 8-bit port can reside on external data bus bits D [31:24], D [23:16], D

[15:8] or D [7:0]. A 16-bit port can reside on external data bus bits D [31:16] or D [15:0].

Word access to or from an 8-bit port requires four external bus cycles to complete the transfer. Word access to or from a 16-bit port requires two external bus cycles to complete the transfer. Half-word access to or from an 8-bit port requires two external bus cycles to complete the transfer. In the case of a multi-cycle transfer, the lower two address bits, A [1:0], are incremented appropriately.

The EIM has a data multiplexer that routes the four bytes of the AHB interface data bus to the required positions to allow proper interfacing to memory and peripherals.

11.5.2 Programmable Output Generation

Unused chip select outputs can be configured to provide a programmable output signal. This functionality is not provided for the CS [0] output signal. When the CSEN bit is cleared, CS [0] is always inactive. To operate as a programmable output pin, the corresponding CSEN control bit must be cleared.

11.5.3 Burst Mode Operation

When burst mode is enabled, the EIM attempts to burst read data from as many sequential address locations as possible, limited only by the length of the burst flash internal page buffer, or the non-sequential nature of the ARM920T processor code or data stream. The EIM only displays the first address accessed in a burst sequence unless the page mode emulation (PME) bit is set.

For the first access in a burst sequence, the EIM asserts load burst address (LBA), causing the external burst device to latch the starting burst address, and then toggles the burst clock (BCLK) for a predefined number of cycles to latch the first unit of data. Subsequently read data units are burst from the external device in fewer clock cycles, realizing an overall increase in bus bandwidth.

Burst accesses is terminated by the EIM when it detects that the next ARM920T processor access is not sequential in nature, or when the external burst device needs additional cycles to retrieve the next requested memory location. In the latter case, the burst flash device provides an ECB signal to the EIM whenever it must terminate the on-going burst sequence and initiate a new (long first access) burst sequence.

11.5.4 Burst Clock Divisor

In some cases it is necessary to slow the external bus in relation to the internal bus to allow accesses to burst devices that have a maximum operating frequency that is lower than the operating frequency of the internal AHB bus. The internal bus frequency can be divided by 2, 3, or 4 for presentation on the external bus in burst mode operation.

11-8

MC9328MX1 Reference Manual

MOTOROLA

EIM Functionality

Programming the BCD bits to various values (see Table 11-5, "Chip Select Control Registers

Description") affects two signals on the external bus, LBA (load burst address) and BCLK. The LBA signal is asserted immediately and remains asserted until the first falling edge of the BCLK signal. The

BCLK signal runs with a 50% duty cycle until a non-sequential internal request is received or an external

ECB signal is recognized.

When programming these bits, ensure that the WSC and DOL fields are coordinated to provide the desired external bus waveforms. For example, when the BCD bits are programmed to 01, the DOL bits must be programmed to 0001, 0011, 0101, … . When the BCD bits are programmed to 10, the DOL must be programmed to 0010, 0101, 1000, … .

The BCM bit in the EIM configuration register has priority over the BCD bits. When BCM = 1, the BCLK runs at maximum frequency.

11.5.5 Burst Clock Start

To allow greater flexibility in achieving the minimum number of wait states on bursted accesses, the user can determine when they want the BCLK to start toggling. This allows the BCLK to be skewed from the point of data capture on the system clock by any number of system clock phases. Use caution when setting these bits in conjunction with the BCD, WSC, and DOL bits. See the external timing diagrams for some examples of how to use the BCS, BCD, WSC, and DOL bits together.

11.5.6 Page Mode Emulation

Setting the PME bit causes the EIM to perform bursted accesses by emulating page mode operation. The

LBA signal remains asserted for the entire access, the burst clock does not send a signal, and the external address asserts for each access made. The initial access timing is dictated by the WSC bits and the page mode access timing is dictated by the DOL bits.

The EIM can take advantage of improved page timing for sequential accesses only. Accesses that are on the page, however are not sequential in nature, have their timing dictated by the WSC bits. The page size can be set via the PSZ bits to 4, 8, 16, or 32 words (the word size is determined by the data width of the external memory, such as the DSZ bits).

11.5.7 Error Conditions

The following conditions cause an error condition to be asserted to the ARM920T processor:

• Access to a disabled chip select (access to a mapped chip select address space where the CSEN bit in the corresponding chip select control register is clear)

• Write access to a write-protected chip select address space (the WP bit in the corresponding chip select control register is set)

• User access to a supervisor-protected chip select address space (the SP bit in the corresponding chip select control register is set)

• User read or write access to a chip select control register or the EIM configuration register

• Byte or halfword access to a chip select control register or the EIM configuration register

MOTOROLA

External Interface Module (EIM)

11-9

External Interface Module (EIM)

11.6 Programming Model

The EIM module includes thirteen user-accessible 32-bit registers. There is a common register called the

EIM Configuration Register that contains control bits that configure the EIM for certain operation modes.

The other twelve registers are pairs of control registers for each chip select. The layout of the control register is slightly different for the CS0 register output because CS [0] does not support the programmable output function. These registers are accessible only in supervisor mode with word (32-bit) reads and writes.

Complete decoding is not performed, so shadowing can occur with these registers. The user must not attempt to address these registers at any other address location other than those listed in Table 11-4.

Table 11-4. EIM Module Register Memory Map

Description Name Address

Chip Select 0 Upper Control Register CS0U 0x00220000

Chip Select 0 Lower Control Register CS0L 0x00220004

Chip Select 1 Upper Control Register CS1U 0x00220008

Chip Select 1 Lower Control Register CS1L 0x0022000C

Chip Select 2 Upper Control Register CS2U 0x00220010

Chip Select 2 Lower Control Register CS2L 0x00220014

Chip Select 3 Upper Control Register CS3U 0x00220018

Chip Select 3 Lower Control Register CS3L 0x0022001C

Chip Select 4 Upper Control Register CS4U 0x00220020

Chip Select 4 Lower Control Register CS4L 0x00220024

Chip Select 5 Upper Control Register CS5U 0x00220028

Chip Select 5 Lower Control Register CS5L 0x0022002C

EIM Configuration Register EIM 0x00220030

11-10

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

11.6.1 Chip Select 0 Control Registers

The layout of the Chip Select 0 control registers are slightly different from the other Chip Select control registers because CS [0] does not support the programmable output function.

The 64 bits of control are divided into two registers, Chip Select 0 Upper Control Register and Chip Select

0 Lower Control Register.

• Bits [63:32] are located in Chip Select 0 Upper Control Register.

• Bits [31:0] are located in Chip Select 0 Lower Control Register.

11.6.1.1 Chip Select 0 Upper Control Register

CS0U

BIT 63

TYPE

RESET r

0

62 r

0

61

BCD

60 rw

0 rw

0

Chip Select 0 Upper Control Register

1

59 rw

0

58

BCS

57 rw

0 rw

0

56 55

PSZ

54 rw

0

0x0000 rw

0 rw

0

53 52

PME SYNC rw

0 rw

0

51 rw

0

Addr

0x00220000

50 49 48

DOL rw

0 rw

0 rw

0

BIT

TYPE

RESET

47

CNC

46 rw

0 rw

0

45 rw

1

44 rw

1

43

WSC

42 rw

1 rw

1

41 rw

1

40 rw

0

39

0x3E00

1

For bit descriptions, see Table 11-5 on page 11-13.

r

0

38 rw

0

37

WWS rw

0

36 rw

0

35 rw

0

34 33 rw

EDC rw

0 0

32 rw

0

11.6.1.2 Chip Select 0 Lower Control Register

CS0L

BIT 31

TYPE

RESET rw

0

30

OEA

29 rw

0 rw

0

28

Chip Select 0 Lower Control Register

1

27 24 23 20 rw

0 rw

0

26

OEN

25 rw

0 rw

0 rw

0

0x0000 rw

0

22

WEA

21 rw

0 rw

0 rw

0

19 rw

0

Addr

0x00220004

16 18

WEN

17 rw

0 rw

0 rw

0

BIT

TYPE

RESET

15 rw

0

14

CSA

13 rw

0 rw

0

12 rw

0

11

EBC rw

1

10 rw

*

9

DSZ rw

*

8 rw

*

7

0x0801

1

For bit descriptions, see Table 11-5 on page 11-13.

*Configurable on reset.

r

0

6

SP rw

0

5 r

0

4

WP rw

0

3 r

0

2 r

0

1 r

0

0

CSEN rw

1

MOTOROLA

External Interface Module (EIM)

11-11

External Interface Module (EIM)

11.6.2 Chip Select 1–Chip Select 5 Control Registers

The layout of the control registers for Chip Selects 1 through 5 are identical.

The 64 bits of control per chip select are divided into an Upper and a Lower register.

• Bits [63:32] are located in Chip Select x Upper Control Register.

• Bits [31:0] are located in Chip Select x Lower Control Register.

11.6.2.1 Chip Select 1

Chip Select 5 Upper Control Registers

For bit descriptions for all of these registers, see Table 11-5 on page 11-13.

CS1U

CS2U

CS3U

CS4U

CS5U

BIT

TYPE

63

DTACK_SEL r

0

62 61 60

BCD r rw rw

0 0 0

RESET

Chip Select 1 Upper Control Register

Chip Select 2 Upper Control Register

Chip Select 3 Upper Control Register

Chip Select 4 Upper Control Register

Chip Select 5 Upper Control Register

59 rw

0

58

BCS

57 rw

0 rw

0

56 rw

0

55

PSZ

54 rw

0

0x0000 rw

0

53

PME rw

0

52

SYNC rw

0

Addr

0x00220008

0x00220010

0x00220018

0x00220020

0x00220028

51 50

DOL

49 48 rw

0 rw

0 rw

0 rw

0

BIT

TYPE

RESET

47

CNC rw

0

46 45 44 rw rw rw

0 0 0

43 42

WSC rw

0 rw

0

41 rw

0

40 39 38 rw

0 r

0

0x0000 rw

0

37

WWS rw

0

36 rw

0

35 34

EDC

33 32 rw

0 rw

0 rw

0 rw

0

11-12

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

11.6.2.2 Chip Select 1

Chip Select 5 Lower Control Registers

For bit descriptions for Chip Select 1–Chip Select 5 registers, see Table 11-5.

CS1L

CS2L

CS3L

CS4L

CS5L

BIT 31

TYPE

RESET rw

0

30

OEA

29 rw

0 rw

0

28

Chip Select 1 Lower Control Register

Chip Select 2 Lower Control Register

Chip Select 3 Lower Control Register

Chip Select 4 Lower Control Register

Chip Select 5 Lower Control Register

27 24 23 20 rw

0 rw

0

26

OEN

25 rw

0 rw

0 rw

0

0x0000 rw

0

22

WEA

21 rw

0 rw

0 rw

0

19 rw

0

Addr

0x0022000C

0x00220014

0x0022001C

0x00220024

0x0022002C

16 18

WEN

17 rw

0 rw

0 rw

0

BIT 15

TYPE

RESET rw

0

14

CSA

13 rw

0 rw

0

12 rw

0

11

EBC rw

1

10 rw

0

9

DSZ rw

0

8 7 rw

0

0x0802 r

0

6

SP rw

0

5 r

0

4

WP rw

0

3 r

0

2 r

0

1 0

PA CSEN rw

1 rw

0

Name

DTACK_SEL

Bit 63

Table 11-5. Chip Select Control Registers Description

Description Settings

DTACK Select

This bit is used to select the functionality of the DTACK input signal for

CS5 to support either a generic DTACK signal or the Compact Flash/PCMCIA wait function. To select the DTACK functionality on CS5, the WSC bits for CS5 must be set to 111111.

0 = Generic DTACK function

1 = Compact Flash/PCMCIA wait function

Reserved—These bits are reserved and should read 0.

Reserved

Bit 62

BCD

Bits 61–60

Burst Clock Divisor

—Contains the value used to program the burst clock divisor. See

Section 11.5.4, “Burst Clock Divisor,” for more information on the burst clock divisors. When the

BCM bit is set (BCM = 1) in the EIM configuration register, BCD is ignored.

00 = Divisor is 1

01 = Divisor is 2

10 = Divisor is 3

11 = Divisor is 4

BCD is cleared by a hardware reset.

MOTOROLA

External Interface Module (EIM)

11-13

External Interface Module (EIM)

Name

BCS

Bits 59–56

PSZ

Bits 55–54

PME

Bit 53

SYNC

Bit 52

DOL

Bits 51–48

Table 11-5. Chip Select Control Registers Description (Continued)

Description Settings

Burst Clock Start

—Determines the number of half cycles after LBA assertion before the first rising edge of BCLK is seen. A value of 0 results in a half clock delay, not an immediate assertion.

When the BCM bit is set (BCM = 1) in the EIM configuration register, this overrides the BCS bits.

BCS is cleared by a hardware reset.

0000 = 1 half cycle before BCLK

0001 = 2 half cycles before BCLK

...

1111 = 16 half cycles before BCLK

Page Size

—Indicates the number of words

(where “word” is defined by the port size or DSZ bits) in a page in memory. This ensures that the

EIM does not burst past a page boundary when the PME bit is set.

00 = 4 words in a page

01 = 8 words in a page

10 = 16 words in a page

11 = 32 words in a page

PSZ is cleared by a hardware reset.

Page Mode Emulation

—Enables/Disables page mode emulation in burst mode. When PME is set, the external address asserts for each piece of data requested. Additionally, the LBA and BCLK signals behave as they do when an asynchronous access is performed.

0 = Disables page mode emulation

1 = Enables page mode emulation

PME is cleared by a hardware reset.

Synchronous Burst Mode

Enable

—Enables/Disables synchronous burst mode. When enabled, the EIM is capable of interfacing to burstable flash devices through additional burst control signals: BCLK, LBA, and

ECB. The sequencing of these additional I/Os is controlled by other EIM configuration register bit settings as defined below.

0 = Disables synchronous burst mode

1 = Enables synchronous burst mode

SYNC is cleared by a hardware reset.

Data Output Length

—Specifies the expected number of system clock cycles required for burst read data to be valid on the data bus before it is latched by the EIM. The reset value specifies that burst data is held for a single system clock period.

As system clock frequencies increase, it may become necessary to delay sampling the data for multiple system clock periods to meet burst flash max frequency specifications and/or EIM data setup time requirements. DOL has no effect on

EIM data latching when SYNC = 0.

0000 = 2 system clock delays

0001 = 2 system clock delays

0010 = 3 system clock delays

0011 = 4 system clock delays

...

1111 = 16 system clock delays

DOL is cleared by a hardware reset.

11-14

MC9328MX1 Reference Manual

MOTOROLA

Name

CNC

Bits 47–46

WSC

Bits 45–40

Reserved

Bit 39

WWS

Bits 38–36

Programming Model

Table 11-5. Chip Select Control Registers Description (Continued)

Description Settings

Chip Select Negation Clock Cycles

—Specifies the minimum number of clock cycles a chip select must remain negated after it is negated.

00 = Minimum negation is 0 clock cycles

01 = Minimum negation is 1 clock cycle

10 = Minimum negation is 2 clock cycles

11 = Minimum negation is 3 clock cycles

CNC has no effect on write accesses when any

CSA bit is set.

CNC is cleared by a hardware reset.

Wait State Control

For SYNC = 0:

WSC programs the number of wait-states for an access to the external device connected to the chip select. Table 11-6, "Chip Select Wait State and Burst Delay Encoding" shows the encoding of this field. When WWS is cleared, setting:

• WSC = 000000 results in 2 clock transfers

• WSC = 000001 results in 2 clock transfers

• WSC = 001110 results in 15 clock transfers

• WSC = 111110 results in 63 clock transfers

• WSC=111111 selects DTACK input functionality for CS5

See Table 11-6, "Chip Select Wait State and

Burst Delay Encoding"

For SYNC = 1:

WSC programs the number of system clock cycles required for the initial access of a burst sequence initiated by the EIM to an external burst device. See Table 11-6, "Chip Select Wait State and Burst Delay Encoding" and to the EIM synchronous burst read timing diagrams for further details.

to, the WSC

WSC is set to 111110 by a hardware reset for

CS0.

WSC is cleared by a hardware reset for

CS1–CS5.

Reserved—This bit is reserved and should read 0.

Write Wait State

—Determines whether additional wait-states are required for write cycles. This is useful for writing to memories that require additional data setup time.

See Table 11-6, "Chip Select Wait State and

Burst Delay Encoding"

WWS is cleared by a hardware reset.

MOTOROLA

External Interface Module (EIM)

11-15

External Interface Module (EIM)

Name

EDC

Bits 35–32

OEA

Bits 31–28

OEN

Bits 27–24

WEA

Bits 23–20

Table 11-5. Chip Select Control Registers Description (Continued)

Description Settings

Extra Dead Cycles

—Determines whether idle cycles are inserted after a read cycle for back-to-back external transfers to eliminate data bus contention. This is useful for slow memory and peripherals that use long CS or OE to output data three-state times. Idle cycles are not inserted for back-to-back external reads from the same chip select.

0000 = 0 Idle cycles inserted

0001 = 1 Idle cycle inserted

...

1111 = 15 Idle cycles inserted

EDC is cleared by a hardware reset.

OE Assert

—Determines when OE is asserted during read cycles.

For SYNC = 0:

OEA determines the number of half clocks before

OE asserts during a read cycle.

0000 = 0 half clocks before assertion

0001 = 1 half clock before assertion

...

1111 = 15 half clocks before assertion

For SYNC = 1:

After the initial burst access, OE is asserted continuously for subsequent burst accesses, and is not affected by OEA (see burst read timing diagrams for more detail). The behavior of OE on the initial burst access is the same as when

SYNC = 0.

When the EBC bit in the corresponding register is clear, the EB [3:0] outputs are similarly affected.

The OEA bits do not affect the cycle length.

OEA is cleared by a hardware reset.

OE Negate

—Determines when OE is negated during a read cycle. Setting the SYNC bit (SYNC

= 1) overrides OEN and OE negates at the end of a read access and no sooner. When EBC in the corresponding register is clear, the EB [3:0] outputs are similarly affected.

0000 = 0 half clocks before end of access

0001 = 1 half clock before end of access

...

1111 = 15 half clocks before end of access

OEN does not affect the cycle length.

OEN is cleared by a hardware reset.

EB [3:0] Assert

—Determines when EB [3:0] is asserted during write cycles. This is useful to meet data setup time requirements for slow memories.

WEA does not affect the cycle length.

WEA is cleared by a hardware reset.

0000 = 0 half clocks before assertion

0001 = 1 half clock before assertion

...

1111 = 15 half clocks before assertion

11-16

MC9328MX1 Reference Manual

MOTOROLA

Name

WEN

Bits 19–16

CSA

Bits 15–12

EBC

Bit 11

DSZ

Bits 10–8

Reserved

Bit 7

SP

Bit 6

Reserved

Bit 5

Programming Model

Table 11-5. Chip Select Control Registers Description (Continued)

Description Settings

EB [3:0] Negate During Write

—Determines when EB [3:0] outputs are negated during a write cycle. This is useful to meet data hold time requirements for slow memories.

0000 = 0 half clocks before end of access

0001 = 1 half clock before end of access

...

1111 = 15 half clocks before end of access

WEN does not affect the cycle length.

WEN is cleared by a hardware reset.

Chip Select Assert

—Determines when chip select is asserted and negated for devices that require additional address setup time and additional address/data hold times. CSA affects only external writes, and is ignored on external reads.

CSA does not affect the cycle length.

0000 = 0 clocks before assertion and 0

...

clocks following negation

0001 = 1 clock before assertion and 1 clock following negation

1111 = 15 clocks before assertion and 15 clocks after negation

CSA is cleared by a hardware reset.

Enable Byte Control

—Indicates the access types that assert the enable byte outputs (EB

[3:0]).

EBC is set by a hardware reset.

0 = Both read and write accesses assert the

EB [3:0] outputs, thus configuring the access as byte enables

1 = Only write accesses assert the EB [3:0] outputs, thus configuring the access as byte write enables; the EB [3:0] outputs are configured as byte write enables for accesses to dual x16 or quad x8 memories

Data Port Size

—Defines the width of the external device’s data port as shown in the table, DSZ Bit

Encoding, to the right. At hardware reset, the value of DSZ is 000 for CS1– CS5. For CS0, DSZ is mapped based on the value of the

EIM_BOOT_DSZ [2:0] bits. EIM_BOOT_DSZ [2] maps to DSZ [2], EIM_BOOT_DSZ [1] maps to

DSZ [1] and EIM_BOOT_DSZ [0] maps to DSZ

[0].

000 = 8-bit port, resides on D [31:24] pins

001 = 8-bit port, resides on D [23:16] pins

010 = 8-bit port, resides on D [15:8] pins

011 = 8-bit port, resides on D [7:0] pins

100 = 16-bit port, resides on D [31:16] pins

101 = 16-bit port, resides on D [15:0] pins

11x = 32-bit port

Reserved—This bit is reserved and should read 0.

Supervisor Protect

—Prevents accesses to the address range defined by the corresponding chip select when the access is attempted in the User mode of ARM9 core operation.

SPI is cleared by a hardware reset.

0 = User mode accesses are allowed in the range of chip select

1 = User mode accesses are prohibited; attempts to access an address mapped by this chip select in User mode results in a TEA to the ARM9 core and no assertion of the chip select output

Reserved—This bit is reserved and should read 0.

MOTOROLA

External Interface Module (EIM)

11-17

External Interface Module (EIM)

WP

Bit 4

Name

Reserved

Bits 3–2

PA

Bit 1

Table 11-5. Chip Select Control Registers Description (Continued)

Description Settings

Write Protect

—Prevents writes to the address range defined by the corresponding chip select.

WP is cleared by a hardware reset.

0 = Writes are allowed in the range of chip select

1 = Writes are prohibited; attempts to write to an address mapped by this chip select result in a TEA to the ARM9 core and no assertion of the chip select output

Reserved—These bits are reserved and should read 0.

CSEN

Bit 0

Pin Assert

—Controls the chip select pin when it is operating as a programmable output pin (when the CSEN bit is clear).

0 = Brings the chip select output to logic-low

1 = Brings the chip select output to logic-high

PA is not available (reserved) for CS0.

PA is set by a hardware reset for CS1–CS5.

Chip Select Enable

—Controls the operation of the chip select pin.

Except for CS0, CSEN is cleared by reset, disabling the chip select output pin. When enabled, the PA control bit is ignored. CSEN in the CS0 control register is set at reset to allow

CS0 to select from an external boot ROM.

CSEN is set by a hardware reset for CS0.

CSEN is cleared by a hardware reset for

CS1–CS5.

0 = Chip select function is disabled; attempts to access an address mapped by this chip select results in an error and no assertion of the chip select output

When disabled, the pin is a general purpose output controlled by the value of PA control bit. When CSEN in the

CS0 control register is clear, CS0 is inactive.

1 = Chip select is enabled, and is asserted when presented with a valid AHB access.

WSC [5:0]

000000

000001

000010

000011

000100

000101

000110

Table 11-6. Chip Select Wait State and Burst Delay Encoding

Number of Wait-States

WWS = 0 WWS = 1 WWS = 7

Read

Access

4

5

6

2

3

1

1

Write

Access

4

5

6

2

3

1

1

Read

Access

4

5

6

2

3

1

1

Write

Access

5

6

7

3

4

1

2

Read

Access

4

5

6

2

3

1

1

Write

Access

11

12

13

9

10

7

8

11-18

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

100000

001110

001111

010000

010001

010010

010011

010100

010101

000111

001000

001001

001010

001011

001100

001101

WSC [5:0]

Table 11-6. Chip Select Wait State and Burst Delay Encoding (Continued)

Number of Wait-States

Read

Access

26

27

28

29

22

23

24

25

30

31

32

18

19

20

21

14

15

16

17

10

11

12

13

7

8

9

WWS = 0

Write

Access

26

27

28

29

22

23

24

25

30

31

32

18

19

20

21

14

15

16

17

10

11

12

13

7

8

9

Read

Access

26

27

28

29

22

23

24

25

30

31

32

18

19

20

21

14

15

16

17

10

11

12

13

7

8

9

WWS = 1

Write

Access

27

28

29

30

23

24

25

26

31

32

33

19

20

21

22

15

16

17

18

11

12

13

14

8

9

10

Read

Access

26

27

28

29

22

23

24

25

30

31

32

18

19

20

21

14

15

16

17

10

11

12

13

7

8

9

WWS = 7

Write

Access

33

34

35

36

29

30

31

32

37

38

39

25

26

27

28

21

22

23

24

17

18

19

20

14

15

16

MOTOROLA

External Interface Module (EIM)

11-19

External Interface Module (EIM)

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

101000

101001

101010

101011

101100

101101

101110

101111

100001

100010

100011

100100

100101

100110

100111

WSC [5:0]

Table 11-6. Chip Select Wait State and Burst Delay Encoding (Continued)

Number of Wait-States

Read

Access

52

53

54

55

48

49

50

51

56

57

58

44

45

46

47

40

41

42

43

36

37

38

39

33

34

35

WWS = 0

Write

Access

52

53

54

55

48

49

50

51

56

57

58

44

45

46

47

40

41

42

43

36

37

38

39

33

34

35

Read

Access

52

53

54

55

48

49

50

51

56

57

58

44

45

46

47

40

41

42

43

36

37

38

39

33

34

35

WWS = 1

Write

Access

53

54

55

56

49

50

51

52

57

58

59

45

46

47

48

41

42

43

44

37

38

39

40

34

35

36

Read

Access

52

53

54

55

48

49

50

51

56

57

58

44

45

46

47

40

41

42

43

36

37

38

39

33

34

35

WWS = 7

Write

Access

59

60

61

62

55

56

57

58

63

63

63

51

52

53

54

47

48

49

50

43

44

45

46

40

41

42

11-20

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

WSC [5:0]

111011

111100

111101

111110

111111

Table 11-6. Chip Select Wait State and Burst Delay Encoding (Continued)

Number of Wait-States

WWS = 0

Read

Access

59

60

61

62

Reserved

Write

Access

59

60

61

62

Reserved

WWS = 1

Read

Access

59

60

61

62

Reserved

Write

Access

60

61

62

63

Reserved

WWS = 7

Read

Access

59

60

61

62

Reserved

Write

Access

63

63

63

63

Reserved

11.6.3 EIM Configuration Register

The EIM Configuration Register contains the bit that controls the operation of the burst clock.

EIM

BIT 31 30 29 28 27

EIM Configuration Register

26 25 24 23 22 21 20 19

Addr

0x00220030

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31– 3

15 r

0

14 13 12 11 10 9 8 7 6 5 4 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0

Table 11-7. EIM Configuration Register Description

Description Settings

Reserved—These bits are reserved and should read 0.

3 r

0

2

BCM rw

0

1 r

0

0 r

0

MOTOROLA

External Interface Module (EIM)

11-21

External Interface Module (EIM)

Name

BCM

Bit 2

Reserved

Bits 1–0

Table 11-7. EIM Configuration Register Description (Continued)

Description Settings

Burst Clock Mode

mode of operation.

—Selects the burst clock

BCM is cleared by a hardware reset.

0 = The burst clock runs only when accessing a chip select range with the SYNC bit set.

When the burst clock is not running, it remains in a logic 0 state; when the burst clock is running, it is configured by the BCD and BCS bits in the chip select control register.

1 = The burst clock runs all the time (independent of chip select accesses).

Reserved—These bits are reserved and should read 0.

11-22

MC9328MX1 Reference Manual

MOTOROLA

Chapter 12

Phase-Locked Loop and Clock Controller

12.1 Introduction

To produce the wide range of on-chip clock frequencies required by the MC9328MX1, the core clock generator uses a two-stage phase locked loop (PLL). The first stage is a premultiplier PLL. If the input crystal frequency is 32.768 kHz, the premultiplier multiplies it by a factor of 512 to 16.78 MHz. If the input crystal frequency is 32 kHz, the premultiplier multiplies it to 16.384 MHz. The second stage is a digital PLL (DPLL) that produces an output frequency determined by system requirements and used throughout the entire system. The two DPLLs (MCU PLL and System PLL) use digital and mixed analog/digital chips to provide clock generation for wireless communication and other applications. Power management of the MC9328MX1 is accomplished by controlling the operation of the premultiplier, MCU

PLL and System PLL units, as shown in Figure 12-1 on page 12-2.

12.2 Clock Sources

The distribution of clocks in the MC9328MX1 is shown in Figure 12-1 on page 12-2. Clock signal name definitions are provided in Table 12-1 on page 12-2. The use of bypass logic provides clock signals both for the ARMTDMI core and for the rest of the system by allowing the MC9328MX1 to select between one low-frequency and two high frequency clock sources:

• 32 kHz external crystal

• 16 MHz external source

• 16 MHz clock from an external Bluetooth RF module

12.2.1 Low Frequency Clock Source

The MC9328MX1 can use either a 32 kHz, 32.768 kHz or a 38.4 kHz crystal as the external low frequency source. Throughout this chapter, the low frequency crystal is referred to as the 32 kHz crystal. The signal from the external 32 kHz crystal is the source of the CLK32 signal that is sent to the real time clock (RTC).

The output of the 32 kHz crystal is also input to the premultiplier PLL to produce the 16.78 MHz signal that is input to the MCU PLL (it is 16.78 MHz if a 32.768 kHz crystal is used and 19.66 MHz if a 38.4 kHz crystal is used). The output of the MCU PLL is sent to the prescaler (PRESC) module to produce the fast clock (FCLK) signal for the ARMTDMI core.

The 16.384 MHz output of the premultiplier PLL also can be a source for the System PLL by setting the

System_SEL bit in the Clock Source Control Register to produce all of the system clocks from a single

32 kHz crystal oscillator. See Section 12.3.1, “DPLL Phase and Frequency Jitter,” for more detailed information on phase and frequency jitter specifications using this configuration.

MOTOROLA

Phase-Locked Loop and Clock Controller

12-1

Phase-Locked Loop and Clock Controller

12.2.2 High Frequency Clock Source

The System PLL produces the USBPLLCLK signal that is the source for the following clock signals:

• CLK48M—for the USB

• HCLK and BCLK—HCLK is the MC9328MX1 system clock and BCLK goes to the ARMTDMI core.

• Peripheral Clocks 1, 2, and 3—The peripheral clocks (PERCLK) provide clock signals to both integrated and external peripherals.

There are two possible external high frequency clock sources for the System PLL—an external 16 MHz oscillator or the Bluetooth reference clock signal. The source is selected by the CLK16_SEL bit in the

Clock Source Control Register.

OSC16

RFBTCLK16

CLK16_SEL

OSC_EN

0

1

CLK16M

1

0

System_SEL

OSC32

SYNC Logic

HCLK

System

PLL

System PLLCLK

USBDIV

CLK32

RTC

CLK48M

USB

OSC32

XTALOSC

PRE-

MULT

CLK32

MCU PLL

PLL Stop &

Wake-Up Logic

SPLLEN

MPLLEN

PRESC

BCLKDIV

PCLKDIV1

PCLKDIV2

PCLKDIV3

HCLK

CLK48M

CLK16M

PREMCLK

FCLK

CLK0SEL [2:0]

000

FCLK

BCLK

HCLK

PERCLK1

PERCLK2

PERCLK3

CPU

System

Internal

Peripherals

CLKO

CLKO

S

Signal Names

RFBTCLK16

CLK48M

FCLK

Figure 12-1. Clock Controller Module

Table 12-1. Clock Controller Module Signal Descriptions

I/O Description

I 16 MHz clock input from an external Bluetooth RF module through the internal BTA module.

O Continuous 48 MHz clock output when System PLL is enabled or when external 48 MHz clock is selected.

O Fast clock (FCLK) output to the CPU.

Default

Stop

Run

Run

12-2

MC9328MX1 Reference Manual

MOTOROLA

DPLL Output Frequency Calculation

Signal Names

Table 12-1. Clock Controller Module Signal Descriptions (Continued)

I/O Description

HCLK

CLKO

PERCLK1, 2, 3

O System clock (HCLK) output to the CPU (as BCLK) and to the system. This is a continuous clock (when the system is not in sleep mode) normally used for bus non-stop system logic (such as bus arbiter or interrupt controller) when the system is running.

O Output internal clock to the CLKO pin.

O Output clocks used by the peripheral modules.

Default

Run

Run

Run

12.3 DPLL Output Frequency Calculation

The DPLL (both the MCU PLL and System PLL) produce a high frequency clock that exhibits both a low frequency jitter and a low phase jitter. The DPLL output clock frequency (f dpll

Equation 12-1:

) is determined by the

f dpll

=

2f ref

• MFI + MFN / (MFD+1)

PD + 1

Eqn. 12-1

where:

• f ref

is the reference frequency

• MFI is an integer part of a multiplication factor (MF)

• MFN is the numerator and MFD is the denominator of the MF

• PD is the predivider factor

12.3.1 DPLL Phase and Frequency Jitter

Spectral purity of the DPLL output clock is characterized by both phase and frequency jitter. Phase jitter is a measure of clock phase fluctuations relative to an ideal clock phase. The output clock also can be skewed relative to the reference clock. Frequency jitter is a measure of clock period fluctuations relative to an ideal clock period. Frequency jitter is calculated as a difference of phase jitter values for adjacent clocks.

DPLL jitter requirements vary according to system configuration. For many stand-alone processors and asynchronous multiprocessor applications, only the frequency jitter value is important (slow phase jitter and clock skew do not affect system performance). In these systems, it is not necessary to adjust the output clock phase with an input clock phase. The clock generation mode in which slow phase fluctuations are permissible is called Frequency Only Lock (FOL) mode.

Phase error is sometimes important for synchronous applications and sampling analog-to-digital (A/D) and digital-to-analog (D/A) precision converters. The DPLL mode providing minimum phase jitter and skew elimination is Frequency and Phase Lock (FPL) mode. The DPLL mode is user selectable.

The DPLL communicates with the clock module. This block contains a control register and provides an interface between the DPLL and the ARMTDMI core.

MOTOROLA

Phase-Locked Loop and Clock Controller

12-3

Phase-Locked Loop and Clock Controller

12.4 MC9328MX1 Power Management

The operation of the PLL and clock controller at different stages of power management is described in the following sections.

12.4.1 PLL Operation at Power-Up

The crystal oscillator begins oscillating within several hundred milliseconds of initial power-up. While reset remains asserted, the PLL begins the lockup sequence and locks 1 ms after the crystal oscillator becomes stable. After lockup occurs, the system clock is available at the default System PLL output frequency of 96 MHz (when a 32 kHz crystal is used).

12.4.2 PLL Operation at Wake-Up

When the device is awakened from stop mode by a wake-up event, the DPLL locks within 300

µ s. The crystal oscillator is always on after initial power-up, so crystal startup time is not a factor. The PLL output clock starts operating as soon as it achieves lock.

12.4.3 ARM920T Processor Low-Power Modes

The MC9328MX1 provides two power saving modes, doze and stop:

• In stop mode, the MCU PLL and the System PLL are shut down and only the 32 kHz clock is running.

• In doze mode, the CPU executes a wait for interrupt instruction.

These modes are controlled by the clock control logic and a sequence of CPU instructions. Most of the peripheral modules can enable or disable the incoming clock signal (PERCLK 1, 2, or 3) through clock gating circuitry from the peripheral bus.

12.4.4 SDRAM Power Modes

When the SDRAM controller (SDRAMC) is enabled, the external SDRAM operates in distributed-refresh mode or in self-refresh mode (as shown in Table 12-2). The SDRAM wake-up latency is approximately 20 system clock cycles (HCLK). The SDRAMC can wake up from self-refresh mode when it is in a SDRAM cycle. In doze mode, the SDRAM enters self-refresh mode. When a bus cycle accesses the SDRAM or

SyncFlash, the controller wakes up and completes the bus cycle, then returns to self-refresh mode.

Table 12-2. SDRAM/SyncFlash Operation During Power Modes

SDRAM Run Doze Stop

SDRAM

SyncFlash

Distributed-refresh

Run

Self-refresh Self-refresh

Low-power mode Deep power-down mode

12.4.5 Power Management in the Clock Controller

Power management in the MC9328MX1 is achieved by controlling the duty cycles of the clock system efficiently. The clocking control scheme is shown in Table 12-3.

12-4

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Table 12-3. Power Management in the Clock Controller

Shut-Down Conditions Wake-Up Conditions Device/Signal

System PLL

MCU PLL

Premultiplier

CLK32

When 0 is written to the SPEN bit and the PLL shut-down count times out (for details see the SD_CNT settings in

Table 12-5 on page 12-6).

When IRQ or FIQ is asserted.

When 0 is written to the MPEN bit.

Same as System PLL.

When IRQ or FIQ is asserted, or 1 is written to the MPEN bit.

Same as System PLL.

Continuously running.

Continuously running.

12.5 Programming Model

The PLL and Clock Controller module includes six user-accessible 32-bit registers. Table 12-4 summarizes these registers and their addresses.

Table 12-4. PLL and Clock Controller Module Register Memory Map

Description Name Address

Clock Source Control Register

Peripheral Clock Divider Register

CSCR

PCDR

0x0021B000

0x0021B020

MCU PLL Control Register 0 MPCTL0 0x0021B004

MCU PLL and System Clock Control Register 1 MPCTL1 0x0021B008

System PLL Control Register 0

System PLL Control Register 1

SPCTL0 0x0021B00C

SPCTL1 0x0021B010

12.5.1 Clock Source Control Register

This register controls the various clock sources to the internal modules of the MC9328MX1. It allows the bypass of the 32 kHz derived clock source to the System PLL when the design requires clock signals with greater frequency and phase jitter performance than the internal PLL using the 32 kHz clock source provides.

MOTOROLA

Phase-Locked Loop and Clock Controller

12-5

Phase-Locked Loop and Clock Controller

CSCR

BIT

TYPE

RESET

31 rw

0

Clock Source Control Register

30 29 28 27 26

CLKO_SEL USB_DIV rw rw rw rw rw

0 0 0 1 1

25

SD_CNT rw

1

24 rw

1

23 22

SPLL_

RESTART r

0 rw

0

0x0F00

21

MPLL_

RESTART rw

0

20 19 r

0 r

0

Addr

0x0021B000

18

CLK16

_SEL rw

0

17

OSC

_EN rw

0

16

System

_SEL rw

0

BIT

TYPE

RESET

15

PRESC rw

1 r

0

14 13 12 11 10

BCLK_DIV rw

1 rw

0 rw

1 rw

1

Name

CLKO_SEL

Bits 31

29

USB_DIV

Bits 28

26

SD_CNT

Bits 25

24

Reserved

Bit 23

9 r

0

8 r

0

7 6 r

0

0xAC03 r

0

5 r

0

4 3 r

0 r

0

Table 12-5. Clock Source Control Register Description

Description Settings

2 r

0

1 0

SPEN MPEN rw

1 rw

1

CLKO Select

USB Divider

—Contains the integer divider value used to generate the CLK48M signal for the USB modules.

—Selects the clock signal source that is output on the CLKO pin.

000 = PERCLK1

001 = HCLK

010 = CLK48M

011 = CLK16M

100 = PREMCLK

101 = FCLK

.

.

000 = System PLL clock divide by 1

001 = System PLL clock divide by 2

.

111 = System PLL clock divide by 8

Shut-Down Control

—Contains the value that sets the duration of System PLL clock output after 0 is written to the SPEN bit. The power controller requests the bus before System PLL shutdown.

Any unmasked interrupt event enables the System

PLL.

00 = System PLL shuts down after next rising edge of CLK32 is detected and the current bus cycle is completed. A minimum of 16 HCLK cycles is guaranteed from writing “0” to SPEN bit.

01 = System PLL shuts down after the second rising edge of CLK32 is detected and the current bus cycle is completed.

10 = System PLL shuts down after the third rising edge of CLK32 is detected and the current bus cycle is completed.

11 = System PLL shuts down after forth rising edge of CLK32 is detected and the current bus cycle is completed.

Reserved—This bit is reserved and should read 0.

12-6

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Table 12-5. Clock Source Control Register Description (Continued)

Description Settings Name

SPLL_

RESTART

Bit 22

MPLL_

RESTART

Bit 21

SPLL Restart

—Restarts System PLL at new assigned frequency. SPLL_RESTART self-clears after 1 (min) or 2 (max) cycles of CLK32.

MPLL Restart

—Restarts the MCU PLL at a new assigned frequency. MPLL_RESTART self-clears after 1 (min) or 2 (max) cycles of CLK32.

Reserved—These bits are reserved and should read 0.

0 = No Effect

1 = Restarts System PLL at new frequency

0 = No Effect

1 = Restarts MCU PLL at new frequency

Reserved

Bits 20

19

CLK16_SEL

Bit 18

CLK16 Select

—Selects the clock source of the

16 MHz clock. When set, RFBTCLK16 is selected.

When cleared, the 16 MHz clock from OSC16 is selected.

0 = Selects the external 16 MHz oscillator source

1 = Selects the Bluetooth reference clock

RFBTCLK16

OSC_EN

Bit 17

System_SEL

Bit 16

Oscillator Enable

—Enables the 16 MHz oscillator circuit when set (available when using an external crystal input). When clear, the oscillator circuit control is disabled which bypasses the oscillator circuit when using external clock input.

0 = Disable the external 16 MHz oscillator circuit

1 = Enable the external 16 MHz oscillator circuit

System Select

—Selects the clock source of the

System PLL input. When set, the external high frequency clock input is selected.

0 = Clock source is the internal premultiplier

1 = Clock source is the external high frequency clock

PRESC

Bit 15

Reserved

Bit 14

BCLK_DIV

Bits 13

10

Prescaler

—Defines the MPU PLL clock prescaler.

0 = Prescaler divides by 1

1 = Prescaler divides by 2

Reserved—This bit is reserved and should read 0.

BClock Divider

—Contains the 4-bit integer divider values for the generation of the BCLK.

0000 = BCLK divided by 1

0001 = BCLK divided by 2

...

1111 = BCLK divided by 16

Reserved—These bits are reserved and should read 0.

Reserved

Bits 9–2

SPEN

Bit 1

MPEN

Bit 0

System PLL Enable

—Enables/Disables the

System PLL. When software writes 0 to SPEN, the

System PLL shuts down after SDCNT times out.

SPEN sets automatically when SPLLEN asserts, and on system reset.

0 = System PLL disabled

1 = System PLL enabled

MCU PLL Enable

—Enables/Disables the MCU

PLL. When cleared, the MCU PLL is disabled.

When software writes 0 to MPEN, the PLL shuts down immediately. MPEN sets automatically when

MPLLEN asserts, and on system reset.

0 = MCU PLL disabled

1 = MCU PLL enabled

MOTOROLA

Phase-Locked Loop and Clock Controller

12-7

Phase-Locked Loop and Clock Controller

12.5.2 Peripheral Clock Divider Register

Each peripheral module in the MC9328MX1 uses clock signals from one of the three clock sources shown in Table 12-6. The three peripheral clock dividers (PCLKDIV1, PCLKDIV2, PCLKDIV3) provide flexible clock configuration capability so that a minimum set of clock frequencies can satisfy a large group of modules to achieve better power efficiency.

Table 12-6. Clock Sources for Peripherals

Clock Source

PERCLK1

PERCLK2

PERCLK3

HCLK

Peripheral

UART1, UART2, Timer1, Timer2, PWM

ASP, LCD, SD, SIM, SPI 1, SPI 2

SSI

SDRAM, CSI, Memory Stick, I

2

C, DMA

PCDR

BIT 31

TYPE

RESET r

0

30 29 r

0 r

0 r

0

28

Peripheral Clock Divider Register

27 r

0

26 r

0

25 r

0

24 23 r

0

0x000B r

0

22 rw

0

21 rw

0

Addr

0x0021B020

17 16 20 19

PCLK_DIV3

18 rw

0 rw

1 rw

0 rw

1 rw

1

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7 r

0

0x00BB rw

1

6 5

PCLK_DIV2 rw

0 rw

1

4 rw

1

Table 12-7. Peripheral Clock Divider Register Description

3 rw

1

2 1

PCLK_DIV1 rw

0 rw

1

0 rw

1

Name Description

Reserved

Bits 31

23

PCLK_DIV3

Bits 22

16

Reserved—These bits are reserved and should read 0.

Peripheral Clock Divider 3

—Contains the 7-bit integer divider that produces the PERCLK3 clock signal for the peripherals. The input to the PCLK_DIV3 divider circuit is System PLLCLK.

Settings

0000000 = Divide by 1

0000001 = Divide by 2

1111111 = Divide by 128

Reserved

Bits 15

8

PCLK_DIV2

Bits 7

4

Reserved—These bits are reserved and should read 0.

Peripheral Clock Divider 2

—Contains the 4-bit integer divider that produces the PERCLK2 clock signal for the peripherals. The input to the PCLK_DIV2 divider circuit is System PLLCLK.

0000 = Divide by 1

0001 = Divide by 2

1111 = Divide by 16

12-8

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Table 12-7. Peripheral Clock Divider Register Description (Continued)

Description Settings Name

PCLK_DIV1

Bits 3

0

Peripheral Clock Divider 1

—Contains the 4-bit integer divider that produces the PERCLK1 clock signal for the peripherals. The input to the PCLK_DIV1 divider circuit is System PLLCLK.

0000 = Divide by 1

0001 = Divide by 2

1111 = Divide by 16

12.5.3 Programming Digital Phase Locked Loops

There are two DPLLs in the MC9328MX1—the MCU PLL and the System PLL. The MCU PLL primarily generates FCLK to the CPU, and the System PLL derives all system clocks to the entire MC9328MX1 and generates clocks that produce the programmable frequency range required by modules such as the USB,

UARTs, and SSI.

The MCU PLL derives the ARM920T processor’s CPU clock FCLK, and the System PLL derives the

ARM920T processor’s CPU clock BCLK, as well as the system clocks PERCLK 1, 2, and 3, and HCLK.

The MCU PLL frequency is determined by the speed requirement of the ARM920T processor. The recommended settings for both MCU PLL and System PLL, which produces the least amount of signal jitter, are shown in Table 12-8.

Table 12-8. Sample Frequency Table

PLL Input

Frequency

Premultiplier PD MFD MFI MFN

PLL Output

Frequency

32 kHz 16.384 MHz 0 63 5 55 192 MHz

12.5.3.1 MCU PLL Control Register 0

The MCU PLL Control Register 0 (MPCTL0) is a 32-bit register that controls the operation of the MCU

PLL. The MPCTL0 control bits are described in the following sections. A delay of 56 FCLK cycles (about

10–30 FCLK cycles for MCU PLL controller plus 2–26 FCLK cycles are necessary to get EDRAM_IDLE and SDRAM_IDLE signals) is required between two write accesses to MPCTL0 register. The following is a procedure for changing the MCU PLL settings:

1. Program the desired values of PD, MFD, MFI, and MFN into the MPCTL0.

2. Set the MPLL_RESTART bit in the CSCR (it will self-clear).

3. New PLL settings will take place.

MOTOROLA

Phase-Locked Loop and Clock Controller

12-9

Phase-Locked Loop and Clock Controller

MPCTL0

BIT 31

TYPE

RESET r

0

30 r

0

29 rw

0

28

PD

27 rw

0 rw

0

MCU PLL Control Register 0

26 25 rw

0 rw

0

24 23 rw

0

0x003F rw

0

22 rw

0

21

MFD

20 rw

1 rw

1

19

Addr

0x0021B004

18 17 16 rw

1 rw

1 rw

1 rw

1

BIT

TYPE

RESET r

0

Name

Reserved

Bits 31–30

PD

Bits 29–26

15 14 r

0

13 rw

0

12

MFI

11 rw

1 rw

0

10 rw

1

9 rw

0

8 7 rw

0

0x1437 rw

0

6 rw

0 rw

1

5

MFN

4 rw

1

Table 12-9. MCU PLL Control Register 0 Description

Description

Reserved—These bits are reserved and should read 0.

3 rw

0

2 1

Settings

0 rw

1 rw

1 rw

1

MFD

Bits 25–16

Predivider Factor

—Defines the predivider factor (PD) applied to the

PLL input frequency. PD is an integer between 0 and 15 (inclusive).

PD is chosen to ensure that the resulting output frequency remains within the specified range. When a new value is written into PD bits, the PLL loses its lock; after a time delay, the PLL re-locks. The output of the MCU PLL is determined by Equation 12-1.

0000 = 0

0001 = 1

1111 = 15

Multiplication Factor (Denominator Part)

—Defines the denominator part of the BRM value for the MF. When a new value is written into the

MFD bits, the PLL loses its lock; after a time delay, the PLL re-locks.

0x000 = Reserved

0x001 = 1

0x3FF = 1023

Reserved—These bits are reserved and should read 0.

Reserved

Bits 15–14

MFI

Bits 13–10

MFN

Bits 9–0

Multiplication Factor (Integer)

—Defines the integer part of the BRM value for the MF. The MFI is encoded so that MFI < 5 results in MFI =

5. When a new value is written into the MFI bits, the PLL loses its lock: after a time delay, the PLL re-locks. The VCO oscillates at a frequency determined by Equation 12-1. Where PD is the division factor of the predivider, MFI is the integer part of the total MF, MFN is the numerator of the fractional part of the MF, and MFD is its denominator part. The MF is chosen to ensure that the resulting VCO output frequency remains within the specified range.

0000–0101 = 5

0110 = 6

...

1111 = 15

Multiplication Factor (Numerator)

—Defines the numerator of the

BRM value for the MF. When a new value is written into the MFN bits, the PLL loses its lock; after a time delay, the PLL re-locks.

0x000 = 0

0x001 = 1

...

0x3FE = 1022

0x3FF = Reserved

12-10

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

12.5.3.2 MCU PLL and System Clock Control Register 1

The MCU PLL and System Clock Control Register 1 (MPCTL1) is a 32-bit register that directs the operation of the on-chip MCU PLL. The MPCTL1 control bits are described in Table 12-10.

MPCTL1

BIT

MCU PLL and System Clock Control Register 1

31 30 29 28 27 26 25 24 23 22 21

Addr

0x0021B008

20 19 18 17 16

TYPE

RESET r

0 r r

0 0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r r r

0 0 0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–7

BRMO

Bit 6

15 14 13 12 r

0 r r

0 0 r

0

11 r

0

10 r

0

9 r

0

8 r

0

7 r

0

6

BRMO rw

0

0x0000

5 r

0

4 r

0

3 2 1 r r r

0 0 0

Table 12-10. MCU PLL and System Clock Control Register 1 Description

Description Settings

Reserved—These bits are reserved and should read 0.

Reserved

Bits 5–0

BRM Order

—Controls the BRM order. The first order BRM is used if a

MF fractional part is both more than 1/10 and less than 9/10. In other cases, the second order BRM is used. The BRMO bit is cleared by a hardware reset. A delay of reference cycles is required between two write accesses to BRMO.

Reserved—These bits are reserved and should read 0.

0 = BRM contains first order

1 = BRM contains second order

0 r

0

12.5.4 Generation of 48 MHz Clocks

The USB interface clock (CLK48M) is used internally by the USB module. Its frequency is set to 48 MHz using the PLL control registers assuming a default input clock frequency 16.384 MHz. This input clock frequency assumes a 32 kHz crystal input.

The predivider/multiplier output depends on the input clock frequency as shown in Table 12-11.

Table 12-11. System PLL Multiplier Factor

PLL

Input

Frequency

Premultiplier PD MFD MFI MFN

PLL

Output

Frequency

USBDIV

USB

Clock

Frequency

32 kHz 16.384 MHz 1 63 5 55 96 MHz

The default setting exception is USB_DIV. The user must program this to 010.

2 48 MHz

MOTOROLA

Phase-Locked Loop and Clock Controller

12-11

Phase-Locked Loop and Clock Controller

12.5.4.1 System PLL Control Register 0

The System PLL Control Register 0 (SPCTL0) is a 32-bit register that controls the operation of the System

PLL. The SPCTL0 control bits are described in the following sections. A delay of 30 System PLLCLK cycles is required between two write accesses to SPCTL0 register. The following is a procedure for changing the System PLL settings:

1. Program the desired values of PD, MFD, MFI, and MFN into the SPCTL0.

2. Set the SPLL_RESTART bit in the CSCR (it will self-clear).

3. New PLL settings will take place.

SPCTL0

BIT 31 30 29

System PLL Control Register 0

26 25 24 23 22 19

Addr

0x0021B00C

18 17 16

TYPE

RESET r

0 r

0 rw

0

28

PD

27 rw

0 rw

0 rw

1 rw

0 rw

0

0x043F rw

0 rw

0

21

MFD

20 rw

1 rw

1 rw

1 rw

1 rw

1 rw

1

BIT

TYPE

RESET

15 r

0

14 r

0

13 rw

0

12

MFI

11 rw

1 rw

0

10 rw

1

9 rw

0

8 7 rw

0

0x1437 rw

0

6 rw

0 rw

1

5

MFN

4 rw

1

Table 12-12. System PLL Control Register 0 Description

3 rw

0

2 rw

1

1 rw

1

0 rw

1

Name Description Settings

Reserved

Bits 31–30

Reserved—These bits are reserved and should read 0.

PD

Bits 29–26

Predivider Factor

—Defines the predivider factor (PD) that is applied to the

PLL input frequency. PD is an integer between 0 and 15 (inclusive). The

System PLL oscillates at a frequency determined by Equation 12-1. The PD is chosen to ensure that the resulting VCO output frequency remains within the specified range. When a new value is written into the PD bits, the PLL loses its lock: after a time delay, the PLL re-locks.

0000 = 0

0001 = 1

1111 = 15

MFD

Bits 25–16

Multiplication Factor (Denominator Part)

—Defines the denominator part of the BRM value for the MF. When a new value is written into the MFD9–MFD0 bits, the PLL loses its lock: after a time delay, the PLL re-locks.

0x000 = Reserved

0x001 = 1

0x3FF = 1023

Reserved

Bits 15–14

Reserved—These bits are reserved and should read 0.

12-12

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Table 12-12. System PLL Control Register 0 Description (Continued)

Description Settings Name

MFI

Bits 13–10

Multiplication Factor (Integer Part)

—Defines the integer part of the BRM value for the MF. The MFI is decoded so that MFI < 5 results in MFI = 5.

The System PLL oscillates at a frequency determined by Equation 12-1.

Where PD is the division factor of the predivider, MFI is the integer part of the total MF, MFN is the numerator of the fractional part of the MF, and MFD is the denominator part of the MF. The MF is chosen to ensure that the resulting VCO output frequency remains within the specified range. When a new value is written into the MFI bits, the PLL loses its lock; after a time delay, the PLL re-locks.

0000–0101 = 5

0110 = 6

...

1111 = 15

MFN

Bits 9–0

Multiplication Factor (Numerator Part)

—Defines the numerator part of the

BRM value for the MF. When a new value is written into the MFN bits, the PLL loses its lock; after a time delay, the PLL re-locks.

0x000 = 0

0x001 = 1

...

0x3FE = 1022

0x3FF = Reserved

12.5.4.2 System PLL Control Register 1

The System PLL control register 1 (SPCTL1) is a 32-bit read/write register in the MCU memory map that directs the operation of the System PLL. The SPCTL1 control bits are described in this section.

SPCTL1

BIT 31

System PLL Control Register 1

30 29 28 27 26 25 24 23 22 21 20 19 18

Addr

0x0021B010

17 16

TYPE

RESET r

0 r r

0 0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–16

LF

Bit 15

Reserved

Bits 14–7

15

LF rw

0

14 13 12 11 10 9 r r

0 0 r

0 r

0 r

0 r

0

8 r

0

7 r

0

6

BRMO rw

0

0x0000

5 r

0

4 r

0

3 r

0

Table 12-13. System PLL Control Register 1 Description

2 r

0

1 r

0

Settings Description

Reserved—These bits are reserved and should read 0.

Lock Flag

—Indicates whether the System PLL is locked. When set, the System PLL clock output is valid. When cleared, the

System PLL clock output remains at logic high.

Reserved—These bits are reserved and should read 0.

0 r

0

0 = System PLL is not locked

1 = System PLL is locked

MOTOROLA

Phase-Locked Loop and Clock Controller

12-13

Phase-Locked Loop and Clock Controller

Name

BRMO

Bit 6

Reserved

Bits 5–0

Table 12-13. System PLL Control Register 1 Description (Continued)

Description Settings

BRM Order Bit—

Controls the BRM order. The first order BRM is used if a MF fractional part is both more than 1/10 and less than

9/10. In other cases, the second order BRM is used. The BRMO bit is cleared by a hardware reset.

0 = BRM has first order

1 = BRM has second order

Reserved—These bits are reserved and should read 0.

12-14

MC9328MX1 Reference Manual

MOTOROLA

Chapter 13

DMA Controller

The Direct Memory Access Controller (DMAC) of the MC9328MX1 provides eleven channels supporting linear memory, 2D memory, FIFO and end-of-burst enable FIFO transfers to provide support for a wide variety of DMA operations.

13.1 Features

The MC9328MX1 DMAC features are:

• Eleven channels support linear memory, FIFO, and end-of-burst enable FIFO for both source and destination.

• Any one of the eleven channels can be configured to support 2D memory.

• Increment, decrement, and no-change support for source and destination addresses.

• Each channel is configurable to response to any of the 32 DMA request signals.

• Supports 8, 16, or 32-bit FIFO and memory port size data transfers.

• Supports both big and little endian.

• DMA is configurable to a maximum of 16 words, 32 half-words, or 64 bytes for each channel.

• Bus utilization control for the channel that is not trigger by a DMA request.

• Burst time-out errors terminate the DMA cycle when the burst cannot be completed within a programmed time count.

• Buffer overflow errors terminate the DMA cycle when the internal buffer receives more than 64 bytes of data. This is useful when the source mode is set to end-of-burst enable FIFO, in case the

DMA_EOBI signal is not detected after 64 bytes of data are received.

• Transfer errors terminate the DMA cycle when a transfer error is detected during a DMA burst.

• DMA request time-out errors are generated for channels that are triggered by DMA requests to interrupt the CPU when a DMA request is not asserted after a programmed time count.

• Interrupts provided to the interrupt controller (and subsequently to the core) on bulk data transfer complete or transfer error.

• Each peripheral supporting DMA transfer generates a DMA_REQ signal to the DMA controller, assuming that each FIFO has a unique system address and generates a dedicated DMA_REQ signal to the DMA controller. For example, an USB device with 8 end-points has 8 DMA request signals to the DMA if they all support DMA transfer.

• The DMA controller provides an acknowledge signal to the peripheral after a DMA burst is complete. This signal is sometimes used by the peripheral to clear some status bits.

• Repeat data transfer function supports automatic USB host–USB device bulk/iso data stream transfer.

MOTOROLA

DMA Controller

13-1

DMA Controller

13.2 Block Diagram

AIPI

IP Bus

SPI

I

2

C

DMA IP Bus

DMA_REQ [31:0], DMA_ACK,

DMA_EOBO, DMA_EOBI,

DMA_EOBO_CNT,

DMA_EOBI_CNT

Figure 13-1. DMAC in MC9328MX1

Prioritize

BUS_REQ

AHB_BUS_ARB

Bus Arbiter BG

I

2

S

UART

Channel 0 registers

Channel 1 registers

AHB_BUS_ARB

System

Registers

Source Sel

DMA_EOBI, DMA_EOBI_CNT

DMA_REQ [31:0]i

Source Sel

Channel n registers

Source Sel

AHB_CNTL

AHB I/F

Cntl Signal

Generation

AHB_A [31:0]

AHB I/F

Address

Generation

AHB_D [31:0]

AHB I/F

Data Buffer

DMA_ACK,

DMA_EOBO, and

DMA_EOBO_CNT

Generation

Interrupt

Generation

DMA_ACK

DMA_EOBO

DMA_EOBO_CNT

DMA_ERR

DMA_INT

16

×

32 Data

FIFO

Figure 13-2. DMAC Block Diagram

13-2

MC9328MX1 Reference Manual

MOTOROLA

Source or

Destination

Address

Signal Description

DMA_REQ

DMA_DATA

DMA_ACK

Figure 13-3. DMA Request and Acknowledge Timing Diagram

Display Linear Memory 2D Memory

W-Size

X-Size

Y-Size

= no. of

X-Size

Y-Size

W-Size

Figure 13-4. 2D Memory Diagram

13.3 Signal Description

The MC9328MX1 signal descriptions are identified in Table 13-1.

Table 13-1. Signal Description

Signal Description

AHB_xxx

IP Bus

DMA_REQ

DMA_ACK

AHB bus signals

IP bus signals

DMA request signal generated by peripherals. One FIFO should generate one DMA_REQ signal. This signal must be negated by the peripheral automatically before the rising edge of

DMA_ACK. It is usually negated when the FIFO is read.

DMA request acknowledge generated by the DMA controller to signal the end of a DMA burst.

MOTOROLA

DMA Controller

13-3

DMA Controller

Table 13-1. Signal Description (Continued)

Description Signal

DMA_EOBI

DMA_EOBI_CNT

This signal is asserted by the USB device when the last data of the burst is read from the

FIFO.

This signal is asserted by the USB device when the last data of the burst is read from the

FIFO to indicate the number of valid bytes.

DMA_EOBO This signal is asserted by the DMA controller when the last data of the burst is written to the

FIFO.

DMA_EOBO_CNT This signal is asserted by the DMA controller when the last data of the burst is written to the

FIFO to indicate the number of valid bytes.

DMA_ERR

DMA_INT

This signal is asserted by DMA controller when any DMA error is detected.

This signal is asserted by DMA controller when data transfer is complete

— that is, the data count reaches the desired level.

13.3.1 Big Endian and Little Endian

The BIG_ENDIAN signal determines the MC9328MX1 memory endian configuration. BIG_ENDIAN is a static pin to the processor and if it is driven logic-high at power on reset the processor's memory system is configured as big endian. If it is driven logic-low at power on reset the processor's memory system is configured as little endian. The pin should not be changed after power on reset (POR) deasserts or during operation.

13.4 Programming Model

The DMA module includes 107 user-accessible 32-bit registers. These registers are divided into three groups by function:

• General registers for all functional blocks (see Section 13.4.1, on page 13-8)

• 2D memory registers to control the display width and the x and y of the window (see

Section 13.4.2, on page 13-16)

• Channel registers to control and configure channels 0–10 (see Section 13.4.3, on page 13-18)

Table 13-2 summarizes these registers and their addresses.

Table 13-2. DMA Module Register Memory Map

Description Name Address

General Registers

DMA Control Register

DMA Interrupt Status Register

DMA Interrupt Mask Register

DMA Burst Time-Out Status Register

DCR

DISR

0x00209000

0x00209004

DIMR 0x00209008

DBTOSR 0x0020900C

13-4

MC9328MX1 Reference Manual

MOTOROLA

MOTOROLA

Programming Model

Table 13-2. DMA Module Register Memory Map (Continued)

Description Name Address

DMA Request Time-Out Status Register

DMA Transfer Error Status Register

DMA Buffer Overflow Status Register

DMA Burst Time-Out Control Register

Channel 0 Source Address Register

Channel 0 Destination Address Register

Channel 0 Count Register

Channel 0 Control Register

Channel 0 Request Source Select Register

Channel 0 Burst Length Register

Channel 0 Request Time-Out Register

Channel 0 Bus Utilization Control Register

Channel 1 Source Address Register

Channel 1 Destination Address Register

Channel 1 Count Register

Channel 1 Control Register

Channel 1 Request Source Select Register

Channel 1 Burst Length Register

Channel 1 Request Time-Out Register

Channel 1 Bus Utilization Control Register

Channel 2 Source Address Register

Channel 2 Destination Address Register

Channel 2 Count Register

Channel 2 Control Register

Channel 2 Request Source Select Register

Channel 2 Burst Length Register

Channel 2 Request Time-Out Register

Channel 2 Bus Utilization Control Register

DRTOSR 0x00209010

DSESR 0x00209014

DBOSR 0x00209018

DBTOCR 0x0020901C

2D Memory Registers

W-Size Register A

X-Size Register A

Y-Size Register A

W-Size Register B

X-Size Register B

Y-Size Register B

Channel Registers

WSRA

XSRA

YSRA

WSRB

XSRB

YSRB

SAR0

DAR0

CNTR0

CCR0

RSSR0

BLR0

RTOR0

BUCR0

SAR1

DAR1

CNTR1

CCR1

RSSR1

BLR1

RTOR1

BUCR1

SAR2

DAR2

CNTR2

CCR2

RSSR2

BLR2

RTOR2

BUCR2

0x00209040

0x00209044

0x00209048

0x0020904C

0x00209050

0x00209054

0x00209080

0x00209084

0x00209088

0x0020908C

0x00209090

0x00209094

0x00209098

0x00209098

0x002090C0

0x002090C4

0x002090C8

0x002090CC

0x002090D0

0x002090D4

0x002090D8

0x002090D8

0x00209100

0x00209104

0x00209108

0x0020910C

0x00209110

0x00209114

0x00209118

0x00209118

DMA Controller

13-5

DMA Controller

Table 13-2. DMA Module Register Memory Map (Continued)

Description Name Address

Channel 3 Source Address Register

Channel 3 Destination Address Register

Channel 3 Count Register

Channel 3 Control Register

Channel 3 Request Source Select Register

Channel 3 Burst Length Register

Channel 3 Request Time-Out Register

Channel 3 Bus Utilization Control Register

Channel 4 Source Address Register

Channel 4 Destination Address Register

Channel 4 Count Register

Channel 4 Control Register

Channel 4 Request Source Select Register

Channel 4 Burst Length Register

Channel 4 Request Time-Out Register

Channel 4 Bus Utilization Control Register

Channel 5 Source Address Register

Channel 5 Destination Address Register

Channel 5 Count Register

Channel 5 Control Register

Channel 5 Request Source Select Register

Channel 5 Burst Length Register

Channel 5 Request Time-Out Register

Channel 5 Bus Utilization Control Register

Channel 6 Source Address Register

Channel 6 Destination Address Register

Channel 6 Count Register

Channel 6 Control Register

Channel 6 Request Source Select Register

Channel 6 Burst Length Register

Channel 6 Request Time-Out Register

Channel 6 Bus Utilization Control Register

Channel 7 Source Address Register

Channel 7 Destination Address Register

Channel 7 Count Register

Channel 7 Control Register

Channel 7 Request Source Select Register

Channel 7 Burst Length Register

Channel 7 Request Time-Out Register

Channel 7 Bus Utilization Control Register

Channel 8 Source Address Register

Channel 8 Destination Address Register

Channel 8 Count Register

Channel 8 Control Register

Channel 8 Request Source Select Register

Channel 8 Burst Length Register

Channel 8 Request Time-Out Register

Channel 8 Bus Utilization Control Register

SAR5

DAR5

CNTR5

CCR5

RSSR5

BLR5

RTOR5

BUCR5

SAR6

DAR6

CNTR6

CCR6

RSSR6

BLR6

RTOR6

BUCR6

SAR3

DAR3

CNTR3

CCR3

RSSR3

BLR3

RTOR3

BUCR3

SAR4

DAR4

CNTR4

CCR4

RSSR4

BLR4

RTOR4

BUCR4

SAR7

DAR7

CNTR7

CCR7

RSSR7

BLR7

RTOR7

BUCR7

SAR8

DAR8

CNTR8

CCR8

RSSR8

BLR8

RTOR8

BUCR8

0x002091C0

0x002091C4

0x002091C8

0x002091CC

0x002091D0

0x002091D4

0x002091D8

0x002091D8

0x00209200

0x00209204

0x00209208

0x0020920C

0x00209210

0x00209214

0x00209218

0x00209218

0x00209140

0x00209144

0x00209148

0x0020914C

0x00209150

0x00209154

0x00209158

0x00209158

0x00209180

0x00209184

0x00209188

0x0020918C

0x00209190

0x00209194

0x00209198

0x00209198

0x00209240

0x00209244

0x00209248

0x0020924C

0x00209250

0x00209254

0x00209258

0x00209258

0x00209280

0x00209284

0x00209288

0x0020928C

0x00209290

0x00209294

0x00209298

0x00209298

13-6

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Table 13-2. DMA Module Register Memory Map (Continued)

Description Name Address

Channel 9 Source Address Register

Channel 9 Destination Address Register

Channel 9 Count Register

Channel 9 Control Register

Channel 9 Request Source Select Register

Channel 9 Burst Length Register

Channel 9 Request Time-Out Register

Channel 9 Bus Utilization Control Register

Channel 10 Source Address Register

Channel 10 Destination Address Register

Channel 10 Count Register

Channel 10 Control Register

Channel 10 Request Source Select Register

Channel 10 Burst Length Register

Channel 10 Request Time-Out Register

Channel 10 Bus Utilization Control Register

SAR9

DAR9

CNTR9

CCR9

RSSR9

BLR9

RTOR9

BUCR9

SAR10

DAR10

CNTR10

CCR10

RSSR10

BLR10

RTOR10

BUCR10

0x002092C0

0x002092C4

0x002092C8

0x002092CC

0x002092D0

0x002092D4

0x002092D8

0x002092D8

0x00209300

0x00209304

0x00209308

0x0020930C

0x00209310

0x00209314

0x00209318

0x00209318

MOTOROLA

DMA Controller

13-7

DMA Controller

13.4.1 General Registers

This section describes the function of the general registers.

13.4.1.1 DMA Control Register

The DMA Control Register (DCR) controls the input of the system clock and the resetting of the DMA module.

DCR

BIT 31 30 29 28 27

DMA Control Register

26 25 24 23 22 21 20 19

Addr

0x00209000

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–2

DRST

Bit 1

DEN

Bit 0

15 14 13 12 11 10 9 8 7 6 5 4 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0

Table 13-3. DMA Control Register Description

r

0

Description

Reserved—These bits are reserved and should read 0.

3 r

0

2 r

0

1 0

DRST DEN w

0 rw

0

Settings

DMA Reset

—Generates a 3-cycle reset pulse that resets the entire DMA module, bringing the module to its reset condition. DRST always reads 0.

0 = No effect

1 = Generates a 3-cycle reset pulse

DMA Enable

—Enables/Disables the system clock to the DMA module.

0 = DMA disable

1 = DMA enable

13-8

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

13.4.1.2 DMA Interrupt Status Register

The DMA Interrupt Status Register (DISR) contains the interrupt status of each channel in the DMAC. The status bit is set whenever the corresponding DMA channel data transfer is complete. When any bit in the

DMA Interrupt Status Register (DISR) is set and the corresponding bit in the interrupt mask register is cleared, a DMA_INT is asserted to the interrupt controller (AITC). When an interrupt occurs, the interrupt service routine must check the DISR to determine the interrupting channel. Clear each bit by writing

1

to it.

DISR

BIT 31 30 29 28

DMA Interrupt Status Register

27 26 25 24 23 22 21 20 19

Addr

0x00209004

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–11

CH10–CH0

Bits 10–0 r

0

15 14 r

0

13 r

0

12 r

0 r

0

11 10 9 8 7 6 5 4 3 2 1 0

CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0

0x0000

Table 13-4. DMA Interrupt Status Register Description

Description

Reserved—These bits are reserved and should read 0.

Settings

Channel 10 to 0 Interrupt Status

—Indicates the interrupt status for each DMA channel.

0 = No interrupt

1 = Interrupt is pending

MOTOROLA

DMA Controller

13-9

DMA Controller

13.4.1.3 DMA Interrupt Mask Register

The DMA Interrupt Mask Register (DIMR) masks both normal interrupts and error interrupts generated by the corresponding channel. There is one control bit for each channel. When an interrupt is masked, the interrupt controller does not generate an interrupt request to the AITC, however the status of the interrupt can be observed from the interrupt status register, burst time-out status register, request time-out status register, or the transfer error status register. At reset, all the interrupts are masked and all the bits in this register are set to 1.

DIMR

BIT 31 30 29 28

DMA Interrupt Mask Register

27 26 25 24 23 22 21 20 19

Addr

0x00209008

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–11

CH10–CH0

Bits 10–0 r

0

15 14 r

0

13 r

0

12 r

0 r

0

11 10 9 8 7 6 5 4 3 2 1 0

CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 rw

1 rw

1 rw

1 rw

1 rw

1 rw

1 rw

1 rw

1 rw

1 rw

1 rw

1

0x07FF

Table 13-5. DMA Interrupt Mask Register Description

Description

Reserved—These bits are reserved and should read 0.

Settings

Channel 10 to 0

—Controls the interrupts for each DMA channel.

0 = Enables interrupts

1 = Disables interrupts

13-10

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

13.4.1.4 DMA Burst Time-Out Status Register

A burst time-out is set when a DMA burst cannot be completed within the number of clock cycles specified in the DMA Burst Time-Out Control Register (DBTOCR) of the channel. When any bit is set in this register and the corresponding bit in the interrupt mask register is cleared, a DMA_ERR is asserted to the interrupt controller (AITC). The DMA burst time-out status register (DBTOSR) indicates the channel, if any, that is currently being serviced and whether a burst time-out was detected. Each bit is cleared by writing 1 to it.

DBTOSR

BIT 31 30 29

DMA Burst Time-Out Status Register

28 27 26 25 24 23 22 21 20 19

Addr

0x0020900C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–11

CH10–CH0

Bits 10–0 r

0

15 14 r

0

13 r

0

12 r

0 r

0

11 10 9 8 7 6 5 4 3 2 1 0

CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0

0x0000

Table 13-6. DMA Burst Time-Out Status Register Description

Description

Reserved—These bits are reserved and should read 0.

Settings

Channel 10 to 0

—Indicates the burst time-out status of each DMA channel.

0 = No burst time-out

1 = Burst time-out

MOTOROLA

DMA Controller

13-11

DMA Controller

13.4.1.5 DMA Request Time-Out Status Register

A DMA request time-out is set when there is no DMA request from the selected DMA_REQ source within the pre-assigned number of clock cycles specified in the request time-out control register (DBTOCR) for the channel. When any bit is set in this register and the corresponding bit in the interrupt mask register is cleared, a DMA_ERR is asserted to the AITC. The DMA Request Time-Out Status Register (DRTOSR) indicates the enabled channel, if any, that detected a DMA request time-out. Clear each bit by writing 1 to it.

DRTOSR

BIT 31 30 29

DMA Request Time-Out Status Register

28 27 26 25 24 23 22 21 20 19

Addr

0x00209010

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–11

CH10–CH0

Bits 10–0 r

0

15 14 r

0

13 r

0

12 r

0 r

0

11 10 9 8 7 6 5 4 3 2 1 0

CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0

0x0000

Table 13-7. DMA Request Time-Out Status Register Description

Description Settings

Reserved—These bits are reserved and should read 0.

Channel 10 to 0

—Indicates the request time-out status of each

DMA channel.

0 = No DMA request time-out

1 = DMA request time-out

13-12

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

13.4.1.6 DMA Transfer Error Status Register

A DMA transfer error is set when the AHB bus signal HRESP [1:0] = ERROR is asserted during a DMA transfer. When any bit is set in this register and the corresponding bit in the interrupt mask register is cleared, a DMA_ERR is asserted to the AITC. The DMA Transfer Error Status Register (DSESR) indicates the channel, if any, detected a transfer error during a DMA burst. Clear each bit by writing 1 to it.

DSESR

BIT 31 30 29 28

DMA Transfer Error Status Register

27 26 25 24 23 22 21 20 19

Addr

0x00209014

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–11

CH10–CH0

Bits 10–0 r

0

15 14 r

0

13 r

0

12 r

0 r

0

11 10 9 8 7 6 5 4 3 2 1 0

CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0

0x0000

Table 13-8. DMA Transfer Error Status Register Description

Description

Reserved—These bits are reserved and should read 0.

Settings

Channel 10 to 0

—Indicates the DMA transfer error status of each

DMA channel.

0 = No transfer error

1 = Transfer error

MOTOROLA

DMA Controller

13-13

DMA Controller

13.4.1.7 DMA Buffer Overflow Status Register

The DMA Buffer Overflow Status Register (DBOSR) indicates whether the internal buffer of the DMA

Controller overflowed during a data transfer. The channel is not enabled until the corresponding bit is cleared. When any bit is set in this register and the corresponding bit in the interrupt mask register is cleared, a DMA_ERR is asserted to the AITC.

DBOSR

BIT 31 30 29

DMA Buffer Overflow Status Register

28 27 26 25 24 23 22 21 20 19

Addr

0x00209018

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET r

0

Name

Reserved

Bits 31–11

CH10–CH0

Bits 10–0

15 14 r

0

13 r

0

12 r

0 r

0

11 10 9 8 7 6 5 4 3 2 1 0

CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0

0x0000

Table 13-9. DMA Buffer Overflow Status Register Description

Settings Description

Reserved—These bits are reserved and should read 0.

Channel 10 to 0

—Indicates the buffer overflow error status of each DMA channel.

0 = No buffer overflow occurred

1 = Buffer overflow occurred

13-14

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

13.4.1.8 DMA Burst Time-Out Control Register

This register sets the time-out for DMA transfer cycle for all DMA channels, so that the DMA controller can release the AHB and IP buses on error. An internal counter starts counting when a DMA burst cycle starts, and resets to zero when the burst is completed. When the counter reaches the count value set in the register, it asserts an interrupt and sets the corresponding error bit in the DMA burst time-out error register.

The system clock is used as input clock to the counter.

DBTOCR

BIT 31 30 29

DMA Burst Time-Out Control Register

28 27 26 25 24 23 22 21 20 19

Addr

0x0020901C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15

EN rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0

9 rw

0

8 7

CNT rw

0

0x0000 rw

0

6 rw

0

5 rw

0

4 rw

0

3 rw

0

2 rw

0

Table 13-10. DMA Burst Time-Out Control Register Description

Settings Description

Reserved—These bits are reserved and should read 0.

1 rw

0

Name

Reserved

Bits 31–16

EN

Bit 15

CNT

Bits 14–0

Enable

—Enables/Disables the burst time-out.

Count

—Contains the time-out count down value.

0 = Disables burst time-out

1 = Enables burst time-out

0 rw

0

MOTOROLA

DMA Controller

13-15

DMA Controller

13.4.2 2D Memory Registers (A and B)

The two sets of 2D memory registers allow any one channel of the eleven channels to select any register set to define the respective 2D memory size.

13.4.2.1 W-Size Registers

The W-Size registers (WSRA and WSRB) define the number of bytes that make up the display width. This allows the DMA controller to calculate the next starting address of another row by adding the source/destination address to the contents of the W-Size register.

WSRA

WSRB

BIT 31 30 29 28 27

W-Size Register A

W-Size Register B

26 25 24 23 22 21 20 19

Addr

0x00209040

0x0020904C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–16

WS

Bits 15–0

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0

9 rw

0 rw

0

8

WS

0x0000

7 rw

0

6 rw

0

5 rw

0

Table 13-11. W-Size Registers Description

Description

Reserved—These bits are reserved and should read 0.

4 rw

0

W-Size

—Contains the number of bytes that make up the display width.

3 2 1 0 rw

0 rw

0 rw

0 rw

0

13-16

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

13.4.2.2 X-Size Registers

The X-Size registers (XSRA and XSRB) contain the number of bytes per row of the window. The value of this register is used by the DMA controller to determine when to jump to the next row.

XSRA

XSRB

BIT 31 30 29 28 27 26

X-Size Register A

X-Size Register B

25 24 23 22 21 20 19

Addr

0x00209044

0x00209050

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31

16

XS

Bits 15

0

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0

9 rw

0

8 7 rw

XS rw

0

0x0000

0

6 rw

0

5 rw

0

Table 13-12. X-Size Registers Description

Description

Reserved—These bits are reserved and should read 0.

4 rw

0

3 rw

0

2 rw

0

1 rw

0

Settings

X-Size

—Contains the number of bytes per row that define the X-Size of the 2D memory.

0 rw

0

MOTOROLA

DMA Controller

13-17

DMA Controller

13.4.2.3 Y-Size Registers

The Y-Size registers (YSRA and YSRB) contain the number of rows in the 2D memory window. This setting is used by the DMA controller to calculate the total size of the transfer.

YSRA

YSRB

BIT 31 30 29 28 27 26

Y-Size Register A

Y-Size Register B

25 24 23 22 21 20 19

Addr

0x00209048

0x00209054

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–16

YS

Bits 15–0

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0

9 rw

0

8 7 rw

YS rw

0

0x0000

0

6 rw

0

5 rw

0

Table 13-13. Y-Size Registers Description

Description

Reserved—These bits are reserved and should read 0.

4 rw

0

Y-Size

—Contains the number of rows that make up the 2D memory window.

3 rw

0

2 1 0 rw

0 rw

0 rw

0

13.4.3 Channel Registers

Channels 0 to 10 support linear memory, 2D memory, FIFO, and end-of-burst enable FIFO transfer. Only one enabled channel may be configured for 2D memory at any time.

The interrupt request DMA_REQ [31:0] does not have a priority assigned. The only priority available is the priority that is defined for each channel: channel 10 has the highest priority and channel 0 has the lowest priority. Channel priority is implemented only when more than one request occurs at the same time, otherwise, channels are serviced on a first come, first serve basis.

Each channel generates a normal interrupt to the interrupt handler when the data count reaches the selected value and the channel source mode is not set to end-of-burst enable FIFO.

Each channel generates an error interrupt to the interrupt handler when the following conditions exist:

• A DMA request time-out is true

• A DMA burst time-out is true during a burst cycle

• The internal buffer overflows during a burst cycle

• A transfer error acknowledge is asserted during a burst cycle

13-18

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

13.4.3.1 Channel Source Address Register

Each of the channel source address registers contain the source address for the DMA cycle. The value of the register remains unchanged throughout the DMA process. If the memory direction bit (MDIR) in the channel control register (CCR) is clear (indicating a memory address increment), then the channel source address register contains the starting address of the memory block. If MDIR is set (indicating a memory address decrement), then the channel source address register contains the ending address of the memory block.

SAR0

SAR1

SAR2

SAR3

SAR4

SAR5

SAR6

SAR7

SAR8

SAR9

SAR10

BIT 31

TYPE

RESET rw

0

30 rw

0

29 rw

0

Channel 8 Source Address Register

Channel 9 Source Address Register

Channel 10 Source Address Register

28 rw

0

Channel 0 Source Address Register

Channel 1 Source Address Register

Channel 2 Source Address Register

Channel 3 Source Address Register

Channel 4 Source Address Register

Channel 5 Source Address Register

Channel 6 Source Address Register

Channel 7 Source Address Register

27 rw

0

26 rw

0

25 rw

0

24 23

SA [31:16] rw

0

0x0000 rw

0

22 rw

0

21 rw

0

20 rw

0

19

Addr

0x00209080

0x002090C0

0x00209100

0x00209140

0x00209180

0x002091C0

0x00209200

0x00209240

0x00209280

0x002092C0

0x00209300

18 17 16 rw

0 rw

0 rw

0 rw

0

BIT

TYPE

RESET

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0

9

SA [15:2]

8 rw

0 rw

0

0x0000

7 rw

0

6 rw

0

5 rw

0

4 rw

0

3 rw

0

2 rw

0

1 0

SA [1] SA [0] rw

0 rw

0

Table 13-14. Channel Source Address Register Description

Description Name

SA [31:2]

Bits 31–2

SA [1], SA [0]

Bits 1–0

Source Address

—Contains the source address from where data is read during a DMA transfer.

Source Address [1] and Source Address [0]

—To ensure that all addresses are word-aligned these bits are set internally to 0. These bits will be read/write as any value if and only if running in big endian and source mode set to FIFO. This is to allow FIFO to use offset address during big endian mode.

MOTOROLA

DMA Controller

13-19

DMA Controller

13.4.3.2 Destination Address Registers

Each of the destination address registers (DARx) contain the destination address for a DMA cycle. The value of the register remains unchanged throughout the DMA process. If the memory direction bit (MDIR) in the channel control register (CCR) is clear (indicating a memory address increment), then the destination address register contains the starting address of the memory block. If MDIR is set (indicating a memory address decrement), then the destination address register contains the ending address of the memory block.

DAR0

DAR1

DAR2

DAR3

DAR4

DAR5

DAR6

DAR7

DAR8

DAR9

DAR10

BIT 31

TYPE

RESET rw

0

30 rw

0

29 rw

0

Channel 0 Destination Address Register

Channel 1 Destination Address Register

Channel 2 Destination Address Register

Channel 3 Destination Address Register

Channel 4 Destination Address Register

Channel 5 Destination Address Register

Channel 6 Destination Address Register

Channel 7 Destination Address Register

Channel 8 Destination Address Register

Channel 9 Destination Address Register

Channel 10 Destination Address Register

28 rw

0

27 rw

0

26 rw

0

25 rw

0

24 23

DA [31:16] rw

0

0x0000 rw

0

22 rw

0

21 rw

0

20 rw

0

19

Addr

0x00209084

0x002090C4

0x00209104

0x00209144

0x00209184

0x002091C4

0x00209204

0x00209244

0x00209284

0x002092C4

0x00209304

18 17 16 rw

0 rw

0 rw

0 rw

0

BIT

TYPE

RESET

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0

9

DA [15:2]

8 rw

0 rw

0

0x0000

7 rw

0

6 rw

0

5 rw

0

4 rw

0

3 rw

0

2 rw

0

1 0

DA [1] DA [0] rw

0 rw

0

Table 13-15. Channel Destination Address Registers Description

Description Name

DA [31:2]

Bits 31–2

DA [1], DA [0]

Bits 1–0

Destination Address

—Contains the destination address to which data is written to during a DMA transfer.

Destination Address [1] and Destination Address [0]

—To ensure that all addresses are word-aligned, these bits are set internally to 0.

13-20

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

13.4.3.3 Channel Count Registers

Each of the channel count registers (CNTRx) contain the number of bytes of data to be transferred. There is an internal counter that counts up (number of bytes—4 for word, 2 for halfword and 1 for byte) for every

DMA transfer. The internal counter is compared with the register after every transfer. When the counter value matches with the register value, the channel is disabled until the CEN bit is cleared and set again, or the RPT bit in the corresponding channel control register is set to

1

. The internal counter is reset to

0

when the channel is enabled again.

The length of the last DMA burst can be shorter than the regular burst length specified in the burst length register. However, when data is transferred out from an I/O FIFO and the last burst is less than BL, the I/O device must generate a DMA request for the last transfer. When data is transferred to an I/O FIFO and the last burst is less than BL, only the remaining number of data is transferred.

When the source mode is set to end-of-burst enable FIFO, this register becomes a read only register and the value of the register is the number of bytes being transferred.

CNTR0

CNTR1

CNTR2

CNTR3

CNTR4

CNTR5

CNTR6

CNTR7

CNTR8

CNTR9

CNTR10

BIT 31

TYPE

RESET r

0

30 r

0

29 r

0

28 r

0

27 r

0

Channel 0 Count Register

Channel 1 Count Register

Channel 2 Count Register

Channel 3 Count Register

Channel 4 Count Register

Channel 5 Count Register

Channel 6 Count Register

Channel 7 Count Register

Channel 8 Count Register

Channel 9 Count Register

Channel 10 Count Register

26 r

0

25 r

0

24 23 r

0

0x0000 rw

0

22 rw

0

21 rw

0

20

CNT

19 rw

0 rw

0

Addr

0x00209088

0x002090C8

0x00209108

0x00209148

0x00209188

0x002091C8

0x00209208

0x00209248

0x00209288

0x002092C8

0x00209308

18 17 16 rw

0 rw

0 rw

0

BIT 15

TYPE

RESET rw

0

Name

Reserved

Bits 31–24

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0

9 rw

0 rw

0

8

CNT

7

0x0000 rw

0

6 rw

0

5 rw

0

4 rw

0

Table 13-16. Channel Count Registers Description

Description

Reserved—These bits are reserved and should read 0.

3 rw

0

2 1 0 rw

0 rw

0 rw

0

MOTOROLA

DMA Controller

13-21

DMA Controller

Name

CNT

Bits 23–0

Table 13-16. Channel Count Registers Description (Continued)

Description

Count

—Contains the number of bytes of data to be transferred during a DMA cycle.

13.4.3.4 Channel Control Registers

Each of the channel control registers (CCRx) controls and displays the status of a DMA channel operation.

NOTE:

While any one of the eleven channels may be configured for 2D memory, only one enabled channel may be configured for 2D memory at any time,

This constraint does not apply to configuring the DMA channels for linear memory, FIFO, and end-of-burst enable FIFO.

CCR0

CCR1

CCR2

CCR3

CCR4

CCR5

CCR6

CCR7

CCR8

CCR9

CCR10

BIT 31 30 29 28

Channel 0 Control Register

Channel 1 Control Register

Channel 2 Control Register

Channel 3 Control Register

Channel 4 Control Register

Channel 5 Control Register

Channel 6 Control Register

Channel 7 Control Register

Channel 8 Control Register

Channel 9 Control Register

Channel 10 Control Register

27 26 25 24 23 22 21 20

Addr

0x0020908C

0x002090CC

0x0020910C

0x0020914C

0x0020918C

0x002091CC

0x0020920C

0x0020924C

0x0020928C

0x002092CC

0x0020930C

19 18 17 16

TYPE

RESET r

0 r

0 r

0 r

0

BIT

TYPE

RESET r

0

15 14 r

0

13

DMOD

12 rw

0 rw

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

11

SMOD

10 rw

0 rw

0

9 8

MDIR MSEL rw

0 rw

0

0x0000

7 6 rw

DSIZ rw

0 0

5 4 rw

SSIZ rw

0 0

3 2 1 0

REN RPT FRC CEN rw rw

0 0 w

0 rw

0

13-22

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Name

Reserved

Bits 31–14

DMOD

Bits 13–12

Table 13-17. Channel Control Registers Description

Description

Reserved—These bits are reserved and should read 0.

Settings

SMOD

Bits 11–10

MDIR

Bit 9

MSEL

Bit 8

DSIZ

Bits 7

6

SSIZ

Bits 5–4

REN

Bit 3

RPT

Bit 2

Destination Mode

—Selects the destination transfer mode.

Source Mode

—Selects the source transfer mode.

Memory Direction

—Selects the memory address direction.

00 = Linear memory

01 = 2D memory

10 = FIFO

11 = End-of-burst enable FIFO

00 = Linear memory

01 = 2D memory

10 = FIFO

11 = End-of-burst enable FIFO

0 = Memory address increment

1 = Memory address decrement

Memory Select

—Selects the 2D memory register set when either source and/or destination is programmed to 2D memory mode.

0 = 2D memory register set A selected

1 = 2D memory register set B selected

Destination Size

—Selects the destination size of a data transfer.

Note:

DSIZ1:DSIZ0 always reads/writes

00

when destination mode is programmed as end-of-burst enable

FIFO, because end-of-burst operation only works for 32-bit

FIFO.

00 = 32-bit destination port

01 = 8-bit destination port

10 = 16-bit destination port

11 = Reserved

Source Size

—Selects the source size of data transfer.

Note:

SSIZ1:SSIZ0 always reads/writes 00 when destination mode is programmed as end-of-burst enable

FIFO, because end of burst operation only works for 32-bit

FIFO.

00 = 32-bit source port

01 = 8-bit source port

10 = 16-bit source port

11 = Reserved

Request Enable

—Enables/Disables the DMA request signal.

When REN is set, the DMA burst is initiated by the DMA_REQ signal from the I/O FIFO. When REN is cleared, DMA transfer is initiated by CEN.

0 = Disables the DMA request signal (when the peripheral asserts a DMA request, no

DMA transfer is triggered);

DMA transfer is initiated by

CEN only

1 = Enables the DMA request signal

(when the peripheral asserts a

DMA request, a DMA transfer is triggered)

Repeat

—Enables/Disables the data transfer repeat function.

When enabled and when the counter reaches the value set in

Count Register, the Count Register is reset to its zero, an interrupt is asserted, and the corresponding channel bit in the

Interrupt Mask Register is cleared. The address is reloaded from the source and destination address register for the next

DMA burst. Data transfer is carried out continuously until the channel is disabled or it completes the last cycle after RPT is cleared.

0 = Disables repeat function

1 = Enables repeat function

MOTOROLA

DMA Controller

13-23

DMA Controller

Name

FRC

Bit 1

CEN

Bit 0

Table 13-17. Channel Control Registers Description (Continued)

Description Settings

Force a DMA Cycle

—Forces a DMA cycle to occur. FRC always reads 0.

DMA Channel Enable

—Enables/Disables the DMA channel.

Note:

1. Program all of the channel settings before enabling the channel.

2. To restart a channel, clear CEN, and then set CEN to 1.

0 = No effect

1 = Force DMA cycle

0 = Disables the DMA channel

1 = Enables the DMA channel

When the source mode is set to end-of-burst enable FIFO, the burst length is determined by the input signals DMA_EOBI and DMA_EOBI_CNT, and the DMA burst (from peripheral to memory) can be terminated only by disabling the channel (clearing the corresponding CEN bit in channel control register).

The count register (CNTR0-CNTR10) becomes read-only and indicates the number of bytes being transferred. This setting is typically used when the channel is configured to transfer data from an endpoint

FIFO of a USB device to an endpoint data packet buffer in system memory.

When the destination mode is set to end-of-burst enable FIFO, the channel operates the same as in normal

FIFO mode, the only difference is that at the end of each burst, the DMA controller generates a

DMA_EOBO and DMA_EOBO_CNT signal to the peripheral. This setting is typically used when the I/O channel is configured to transfer data from an endpoint data packet buffer in system memory to an endpoint FIFO of a USB device.

Table 13-18. DMA_EOBO_CNT and DMA_EOBI_CNT Settings

DMA_EOBI_CNT [1:0] or

DMA_EOBO_CNT [1:0]

Number of Bytes Per Transfer

00

01

10

11

2

3

4

1

13-24

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

13.4.3.5 Channel Request Source Select Registers

Each of the 32-bit channel request source select registers (RSSRx) selects one of the 32 DMA request signals (DMA_REQ [31:0]) to initiate a DMA transfer for the corresponding channel.

RSSR0

RSSR1

RSSR2

RSSR3

RSSR4

RSSR5

RSSR6

RSSR7

RSSR8

RSSR9

RSSR10

BIT 31 30

Channel 0 Request Source Select Register

Channel 1 Request Source Select Register

Channel 2 Request Source Select Register

Channel 3 Request Source Select Register

Channel 4 Request Source Select Register

Channel 5 Request Source Select Register

Channel 6 Request Source Select Register

Channel 7 Request Source Select Register

Channel 8 Request Source Select Register

Channel 9 Request Source Select Register

Channel 10 Request Source Select Register

29 28 27 26 25 24 23 22 21 20 19

Addr

0x00209090

0x002090D0

0x00209110

0x00209150

0x00209190

0x002091D0

0x00209210

0x00209250

0x00209290

0x002092D0

0x00209310

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–5

RSS

Bits 4–0 r

0

15 14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7 r

0

0x0000 r

0

6 r

0

5 r

0

4 rw

0

3 rw

0

2

RSS rw

0

1 rw

0

Table 13-19. Channel Request Source Select Registers Description

Description Settings

Reserved—These bits are reserved and should read 0.

Request Source Select

—Selects one of the 32 DMA_REQ signals that initiates a DMA transfer cycle for the channel.

0

00000 = select DMA_REQ [0]

00001 = select DMA_REQ [1]

...

11111 = select DMA_REQ [31] rw

0

MOTOROLA

DMA Controller

13-25

DMA Controller

13.4.3.6 Channel Burst Length Registers

The Channel Burst Length registers (BLRx) control the burst length of a DMA cycle. For a FIFO channel setting, the burst length is normally assigned according to the FIFO size of the selected I/O device, or by the FIFO level at which its DMA_REQ signal is asserted.

For example, when the UART RxD FIFO is 12

×

8 and it asserts DMA_REQ when it receives more than 8 bytes of data, BL is 8. When the memory port size also is 8-bit, the DMA burst is 8-byte reads followed by

8-byte writes.

When the memory port size is smaller than the I/O port size, the burst length of the byte writes is doubled.

For example, the I/O port is 32-bit, the memory port is 16-bit, and the burst length is set to 32. In this configuration, the DMA performs 8 word burst reads and 16 halfword burst writes for I/O to memory transfer.

BLR0

BLR1

BLR2

BLR3

BLR4

BLR5

BLR6

BLR7

BLR8

BLR9

BLR10

BIT 31 30 29 28

Channel 0 Burst Length Register

Channel 1 Burst Length Register

Channel 2 Burst Length Register

Channel 3 Burst Length Register

Channel 4 Burst Length Register

Channel 5 Burst Length Register

Channel 6 Burst Length Register

Channel 7 Burst Length Register

Channel 8 Burst Length Register

Channel 9 Burst Length Register

Channel 10 Burst Length Register

27 26 25 24 23 22 21 20 19

Addr

0x00209094

0x002090D4

0x00209114

0x00209154

0x00209194

0x002091D4

0x00209214

0x00209254

0x00209294

0x002092D4

0x00209314

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–6 r

0

15 14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7 r

0

0x0000 r

0

6 r

0

5 rw

0

4 rw

0

3 2 rw

0

BL rw

0

Table 13-20. Channel Burst Length Registers Description

Description Settings

Reserved—These bits are reserved and should read 0.

1 rw

0

0 rw

0

13-26

MC9328MX1 Reference Manual

MOTOROLA

Name

BL

Bits 5–0

Programming Model

Table 13-20. Channel Burst Length Registers Description (Continued)

Description Settings

Burst Length

—Contains the number of data bytes that are transferred in a DMA burst.

000000 = 64 bytes read follow 64 bytes write

000001 = 1byte read follow 1 byte write

000010 = 2 bytes read follow 2 bytes write

....

111111 = 63 bytes read follow 63 bytes write

13.4.3.7 Channel Request Time-Out Registers

The channel request time-out registers (RTOx) set the time-out for DMA_REQ from the selected request source of the channel, which detects any discontinuity of data transfer. The request time-out takes effect only when the corresponding request enable (REN) bit in the channel control register (CCR) is set. An internal counter starts counting when a DMA channel is enabled, the burst is completed, and the counter is reset to zero when a DMA request is detected. When the counter reaches the count value set in the register, it asserts an interrupt and sets its error bit in the DMA request time-out status register. The input clock of the counter is selectable from either the system clock (HCLK) or input crystal (CLK32K).

NOTE:

This register shares the same address as the bus utilization control register.

RTOR0

RTOR1

RTOR2

RTOR3

RTOR4

RTOR5

RTOR6

RTOR7

RTOR8

RTOR9

RTOR10

BIT 31 30

Channel 0 Request Time-Out Register

Channel 1 Request Time-Out Register

Channel 2 Request Time-Out Register

Channel 3 Request Time-Out Register

Channel 4 Request Time-Out Register

Channel 5 Request Time-Out Register

Channel 6 Request Time-Out Register

Channel 7 Request Time-Out Register

Channel 8 Request Time-Out Register

Channel 9 Request Time-Out Register

Channel 10 Request Time-Out Register

29 28 27 26 25 24 23 22 21 20 19

Addr

0x00209098

0x002090D8

0x00209118

0x00209158

0x00209198

0x002091D8

0x00209218

0x00209258

0x00209298

0x002092D8

0x00209318

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15

EN rw

0

14 13

CLK PSC rw

0 rw

0

12 rw

0

11 10 rw

0 rw

0

9 rw

0

8 7 rw

0

0x0000 rw

0

6

CNT rw

0

5 rw

0

4 rw

0

3 2 1 0 rw

0 rw

0 rw

0 rw

0

MOTOROLA

DMA Controller

13-27

DMA Controller

Name

Reserved

Bits 31–16

EN

Bit 15

CLK

Bit 14

PSC

Bit 13

CNT

Bits 12–0

Table 13-21. Channel Request Time-Out Registers Description

Description

Reserved—These bits are reserved and should read 0.

Settings

Enable

—Enables/Disables the DMA request time-out.

Clock Source

—Selects the counter of input clock source.

0 = Disables DMA request time-out

1 = Enables DMA request time-out

0 = HCLK

1 = 32.768 kHz

Prescaler Count

—Sets the prescaler of the input clock.

0 = Divide by 1

1 = Divide by 256

Request Time-Out Count

—Contains the time-out count down value for the internal counter. This value remains unchanged through out the DMA process.

13.4.3.8 Channel 0 Bus Utilization Control Register

The Bus Utilization Control register (BUCRx) controls the bus utilization of an enabled channel when the request enable (REN) bit in channel control register (CCR) is cleared. The channel does not request a

DMA transfer until the counter reaches the count value set in the register except for the very first burst.

This counter is cleared when the channel burst is started. When the count value is set to zero, the DMA carries on burst transfers one after another until it reaches the value set in count register. In this case, the user must be careful not to violate the maximum bus request latency of other devices.

NOTE:

This register shares the same address of request time-out register.

13-28

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

BUCR0

BUCR1

BUCR2

BUCR3

BUCR4

BUCR5

BUCR6

BUCR7

BUCR8

BUCR9

BUCR10

BIT 31 30

Channel 0 Bus Utilization Control Register

Channel 1 Bus Utilization Control Register

Channel 2 Bus Utilization Control Register

Channel 3 Bus Utilization Control Register

Channel 4 Bus Utilization Control Register

Channel 5 Bus Utilization Control Register

Channel 6 Bus Utilization Control Register

Channel 7 Bus Utilization Control Register

Channel 8 Bus Utilization Control Register

Channel 9 Bus Utilization Control Register

Channel 10 Bus Utilization Control Register

29 28 27 26 25 24 23 22 21 20 19

Addr

0x00209098

0x002090D8

0x00209118

0x00209158

0x00209198

0x002091D8

0x00209218

0x00209258

0x00209298

0x002092D8

0x00209318

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET rw

0

Name

Reserved

Bits 31–16

CCNT

Bits 15–0

15 14 rw

0

13 12 rw

0 rw

0

11 10 rw

0 rw

0

9 rw

0 rw

0

8

CCNT

7

0x0000 rw

0

6 5 rw

0 rw

0

4 rw

0

3 rw

0

Table 13-22. Channel 0 Bus Utilization Control Registers Description

Description

Reserved—These bits are reserved and should read 0.

2 1 rw

0 rw

0

Clock Count

—Sets the number of system clocks that must occur before the memory channel releases the AHB, before the next DMA request for the channel.

0 rw

0

MOTOROLA

DMA Controller

13-29

DMA Controller

13.5 DMA Request Table

Table 13-23 identifies the dedicated DMA request signal and its associated peripheral.

Table 13-23. DMA Request Table

DMA Request Peripheral

DMA_REQ [15]

DMA_REQ [14]

DMA_REQ [13]

DMA_REQ [12]

DMA_REQ [11]

DMA_REQ [10]

DMA_REQ [9]

DMA_REQ [8]

DMA_REQ [7]

DMA_REQ [6]

DMA_REQ [5]

DMA_REQ [31]

DMA_REQ [30]

DMA_REQ [29]

DMA_REQ [28]

UART 1 Receive DMA Request

UART 1 Transmit DMA Request

UART 2 Receive DMA Request

UART 2 Transmit DMA Request

DMA_REQ [27]

DMA_REQ [26]

SPI 2 Transmit DMA Request

SPI 2 Receive DMA Request

DMA_REQ [25] USB Device End Point 5 DMA Request

DMA_REQ [24] USB Device End Point 4 DMA Request

DMA_REQ [23] USB Device End Point 3 DMA Request

DMA_REQ [22] USB Device End Point 2 DMA Request

DMA_REQ [21] USB Device End Point 1 DMA Request

DMA_REQ [20] USB Device End Point 0 DMA Request

DMA_REQ [19]

DMA_REQ [18]

DMA_REQ [17]

DMA_REQ [16]

ASP ADC DMA Request

ASP DAC DMA Request

SSI Receive DMA Request

SSI Transmit DMA Request

SPI 1 Transmit DMA Request

SPI 1 Receive DMA Request

SDHC DMA Request

External DMA Request

DSPA MAC DMA Request

DSPA DCT DIN DMA Request

DSPA DCT DOUT DMA Request

MSHC DMA Request

CSI Receive FIFO DMA Request

CSI Statistic FIFO DMA Request

Reserved

13-30

MC9328MX1 Reference Manual

MOTOROLA

Table 13-23. DMA Request Table (Continued)

DMA Request Peripheral

DMA_REQ [4]

DMA_REQ [3]

DMA_REQ [2]

DMA_REQ [1]

DMA_REQ [0]

Reserved

Reserved

Reserved

Reserved

Reserved

DMA Request Table

MOTOROLA

DMA Controller

13-31

DMA Controller

13-32

MC9328MX1 Reference Manual

MOTOROLA

Chapter 14

Watchdog Timer Module

14.1 General Overview

The watchdog timer module of the MC9328MX1 protects against system failures by providing a method of escaping from unexpected events or programming errors. Once activated, the timer must be serviced by software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the watchdog timer module either asserts a system reset signal WDT_RST or a interrupt request signal

WDT_INT depending on software configuration. Table 14-1 on page 14-5 shows the watchdog timer module’s input and output signals. A state machine that demonstrates the time-out operation of the counter operation is shown in Figure 14-2 on page 14-4.

14.2 Watchdog Timer Operation

The following sections describe the operation and programming of the watchdog timer module.

14.2.1 Timing Specifications

The watchdog timer provides time-out periods from 0.5 seconds up to 64 seconds with a time resolution of

0.5 seconds. As shown in Figure 14-1, the watchdog timer uses the CLK2HZ clock (from RTC module) as an input to achieve the resolution of 0.5 seconds and a frequency of 2 Hz. This clock is connected to the input of a 7-bit counter to obtain a range of 0.5 to 64 seconds. The user can determine the time-out period by writing to the watchdog time-out field (WT[6:0]) in the Watchdog Control Register (WCR).

WHALT

WDE

CLK2HZ

7-bit Counter

(Time-Out)

CLK32K

0

1

Test Mode (TMD bit)

Figure 14-1. Watchdog Timer Functional Block Diagram

MOTOROLA

Watchdog Timer Module

14-1

Watchdog Timer Module

14.2.2 Watchdog During Reset

14.2.2.1 Power-On Reset

During a power-on reset (POR) all registers are reset to their reset values and the counter is placed in the idle state until the watchdog is enabled. The Watchdog Status Register (WSTR) contains the source of the reset event and the interrupt status bit TINT is reset to 0.

14.2.2.2 Software Reset

When software reset occurs, the software reset (SWR) bit in Watchdog Control Register (WCR) is set to 1, all registers are reset to their reset values and the counter is placed in the idle state until the watchdog is enabled.

14.3 Watchdog After Reset

After reset, watchdog timer operation can be divided into four states: initial load, countdown, reload, and time-out. The following sections define each of the watchdog timer states after reset.

14.3.1 Initial Load

The Watchdog Control Register (WCR) bits WT[6:0] must be written to before the watchdog is enabled.

The watchdog is then enabled by setting the one-time writable watchdog enable (WDE) bit in the WCR.

The time-out value is loaded into the counter after the service sequence is written to the Watchdog Service

Register (WSR) or after the watchdog is enabled. The service sequence is described in Section 14.3.3,

“Reload.” The counter state machine is shown in Figure 14-2 on page 14-4.

14.3.2 Countdown

The counter is activated after the Watchdog is enabled and begins to count down from its initial programmed value. If any system errors have occurred which prevents the software from servicing the

Watchdog Service Register (WSR), the timer will time-out when the counter reaches zero. If the WSR is serviced prior to the counter reaching zero, the watchdog reloads its counter to the time-out value indicated by bits WT[6:0] of the WCR and re-start the countdown. A reset will reset the counter and place it in the idle state at any time during the countdown. The counter state machine is shown in Figure 14-2 on page 14-4.

14.3.3 Reload

The recommended service sequence is to write a $5555 followed by a $AAAA to the WSR. To reload the counter, the writes must take place within the time-out value indicated by bits WT[6:0] of the WCR. Any number of instructions can be executed between the two writes. This service sequence is also used to activate the counter during the initial load. See Section 14.3.1, “Initial Load.”

If the WSR is not loaded with a $5555 prior to a write of $AAAA to the WSR, the counter will not be reloaded. If any value other than $AAAA is written to the WSR after $5555, the counter will not be reloaded.

14-2

MC9328MX1 Reference Manual

MOTOROLA

Watchdog Control

14.3.4 Time-Out

If the counter reaches zero, the TOUT bit in WSTR (Watchdog Status Register) is set to 1 indicating that watchdog has timed out. Reading the TOUT bit will clear it.

If the counter reaches zero, the watchdog asserts either a system reset signal WDT_RST or an interrupt request signal WDT_INT depending on the state of the WIE bit in the WCR. A 1 written to WIE configures the watchdog to generate a interrupt request signal to the interrupt handler. When a watchdog time-out interrupt is asserted, the TINT bit in WSTR (Watchdog Status Register) is set to 1 to indicate that an interrupt request is generated and the reading of this bit clears the interrupt and this bit. A 0 written to the WIE bit configures the watchdog to generate a WDT_RST signal to reset the module. The counter state machine is shown in Figure 14-2 on page 14-4.

14.3.5 Halting the Counter

The watchdog counting can be halted at any time by setting the WHALT bit (WCR[15]) to 1. The counter immediately stops counting and the counter value is held at the last value. The WHALT bit can be cleared by writing 0 to it or it can be automatically cleared by the occurrence of any of three system events, fast interrupt, slow interrupt, or system reset. The counter resumes counting from the stopped value. No other configurations are affected.

14.4 Watchdog Control

14.4.1 Interrupt Control

The watchdog timer generates interrupt request signal WDT_INT as a result of a WDOG time-out when

WIE bit of WCR set to 1. The TINT bit of WSTR is set to 1 to indicate that the interrupt request has been generated. Reading the TINT bit clears the interrupt and this status bit.

14.4.2 Reset Sources

The watchdog timer generates reset signal WDT_RST as a result of a WDOG time-out. This signal is an output to the Reset Module for system reset generation.

MOTOROLA

Watchdog Timer Module

14-3

Watchdog Timer Module

14.5 State Machine

No

Negated

?

Yes

Yes

Counting

Resumed

(fiq, irq, reset)

?

No

Idle

No

No

Time-out

Value

?

Yes

Watchdog

Enabled

?

Yes

Start Counter

Decrement Counter

Counter

Suspended

Yes

Counting

Halted

(WHALT=1)

?

No

14-4

Reload Counter

Yes

WSR

Serviced

?

No

Count

= 0

?

Yes

No

Assert Time-out

Indication

No

Assert wdt_rst

Interrupt

Request

?

Yes

Assert wdt_int

Reset

Module

Figure 14-2. Counter State Machine

Interrupt

Handler

MC9328MX1 Reference Manual

MOTOROLA

Watchdog Timer I/O Signals

14.6 Watchdog Timer I/O Signals

Table 14-1shows the watchdog timer module input and output signals.

Table 14-1. Watchdog Timer I/O Signals

Signal Name I/O Description

FIQ

IRQ

IPS_HARD_ASYNC_RESET

IPS_CONT_CLK

IPS_CONT_CLK

IPS_GATED_CLK

IPS_GATED_CLK

CLK2HZ

CLK32K

IPS_MODULE_EN

IPS_BYTE_15_8

IPS_BYTE_7_0

IPS_MRW

IPS_ADDR[11:2]

IPS_WDATA[31:0]

SCAN_MODE

SCAN_RESET

IPS_CONT_CLK_EN

IPS_XFR_ERR

IPS_XFR_WAIT

IPS_RDATA[31:0]

I

I

I

I

I

I

I

I

O

O

I

O

O

I

I

I

I

I

I

I

I Fast Interrupt

Normal Interrupt

WDOG global reset from reset module

96 MHz system clock

96 MHz system clock inverted

Bus clock

Bus clock inverted

2 Hz clock input from RTC module output in test mode, counter clock becomes 32 kHz clock

Watchdog module enable

Bit 15 to 8 enable

Bit 7 to 0 enable

Module read/write signal

Module address bus

Module write data bus

Indicates scan mode selection

Indicates scan reset ips_cont_clk enable

Transfer error acknowledge

Transfer wait acknowledge

Module read data bus

MOTOROLA

Watchdog Timer Module

14-5

Watchdog Timer Module

14.7 Programming Model

.

The watchdog timer has three registers in its programming model: Watchdog Control Register (WCR),

Watchdog Service Register (WSR), and Watchdog Status Register (WSTR).

Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R

WCR

($00201000)

W

0

WHA

LT

WT[6:0]

0 0 0

WIE TMD SWR WDEC WDE

WSR

($00201004)

WSTR

($00201008)

R

W

R

W

0 0 0 0 0 0

WSR[15:0]

0 TINT 0 0 0 0 0 0 0 TOUT

14.7.1 Watchdog Control Register

The WCR is a 32-bit read/write (byte writable) register. It controls the Watchdog operation. See

Table 14-2 on page 14-6 for bit descriptions and settings.

WCR

BIT 31

Watchdog Control Register

30 29 28 27 26 25 24 23 22 21 20 19 18

Addr

0x00201000

17 16

TYPE

RESET r

0 r r

0 0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15

WHALT rw

0

14 13 12 rw rw rw

0 0 0

11

WT

10 rw

0 rw

0

9 8 rw

0 rw

0

7 6 5 r

0 r

0

0x0000 r

0

4

WIE rw

0

3 2 1

TMD SWR WDEC rw

0 rw

0 rw

0

0

WDE rw

0

Table 14-2. Watchdog Control Register Description

Name Description Settings

Reserved

Bits

31–15

Reserved—These bits are reserved and should read 0.

WHALT

Bit 15

Watchdog Halt

—When set, the watchdog counter immediately stops counting and the counter value is held at the last value.

The WHALT bit can be cleared by writing 0 to it or it can be automatically cleared by the occurrence of any of three system events, fast interrupt, slow interrupt, or system reset.

0 = Counter is not halted

1 = Counter is halted

14-6

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Table 14-2. Watchdog Control Register Description (Continued)

Description Settings Name

WT[6:0]

Bits 14–8

Watchdog Time-Out Field

—This 7-bit field contains the time-out value and is loaded into the Watchdog counter after the service routine has been performed. After reset, WT[6:0] must be written before enabling the Watchdog.

Reserved

Bits 7–5

Reserved—These bits are reserved and should read 0.

WIE

Bit 4

TMD

Bit 3

Watchdog Interrupt Enable

asserted or WDT_INT is asserted upon a watchdog time-out.

Test Mode Enable

mode.

—Determines if the WDT_RST is

—Determines if WDOG timer is in test

Note:

This bit is used only for test purposes

Set to desired time-out value.

1 = Assert WDT_INT

0 = Assert WDT_RST

0 = Use 2 Hz clock as counter clock

1 = Use CLK32K as counter clock

SWR

Bit 2

WDEC

Bit 1

WDE

Bit 0

Software Reset Enable

—Determines if a software reset is enabled.

Watchdog Enable Control

—Controls the write access of the

WDE bit.

Watchdog Enable

—Enables or disables the watchdog module.

Write once-only if WDEC bit is low. Write multiple if

WDEC bit is high

0 = Software reset is not enabled

1 = Software reset is enabled

0 = WDE bit is write once only

1 = WDE bit is write multiple

0 = Disable Watchdog

1 = Enable Watchdog

14.7.2 Watchdog Service Register

The Watchdog Service register contains the watchdog service sequence. When Watchdog is enabled, the

Watchdog requires that a service sequence be written to the Watchdog Service Register (WSR) as described in Table 14-3.

WSR

BIT 31 30 29 28 27

Watchdog Service Register

26 25 24 23 22 21 20 19

Addr

0x00201004

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT 15 14 13

TYPE

RESET rw

0 rw

0 rw

0

12 11 rw

0 rw

0

10 9 rw

0 rw

0

8 7 rw

WSR rw

0 0

0x0000

6 5 4 3 2 1 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0

0 rw

0

MOTOROLA

Watchdog Timer Module

14-7

Watchdog Timer Module

Table 14-3. Watchdog Service Register Description

Description Settings Name

Reserved

Bits 31–16

WSR[15:0]

Bits 15–0

Reserved—These bits are reserved and should read 0.

Watchdog Service Register

—This 15-bit field contains the watchdog service sequence.

Both writes must occur in the order listed prior to the time-out, however any number of instructions can be executed between the two writes.

The service sequence must be performed as follows: a) Write $5555 to the Watchdog

Service Register (WSR).

b) Write $AAAA to the Watchdog

Service Register (WSR)

14.7.3 Watchdog Status Register

.

The WSTR is a read-only register which records the source of the RESET_OUT event and interrupt status.

It is cleared by reset. It records the source of the RESET_OUT event and interrupt status.

RESET_OUT can be generated by the following sources which are listed in priority from highest to lowest: Power-on reset, External reset, Clock Monitor event, Watchdog Time-out, and Software reset.

WSTR

Watchdog Status Register

Addr

0x00201008

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT 15

TYPE

RESET r

0

14 r

0

13 r

0

12 r

0

11 10 r

0 r

0

9 r

0

8

TINT r

0

7

0x0000 r

0

6 r

0

5 r

0

4 r

0

3 r

0

2 r

0

1 r

0

0

TOUT r

0

Table 14-4. Watchdog Status Register Description

Name Description Settings

Reserved

Bits 31–9

Reserved—These bits are reserved and should read 0.

TINT

Bit 8

Time-Out Interrupt

—Indicates whether the time-out interrupt generated

0 = No time-out interrupt generated

1 = Time-out interrupt generated

Reserved

Bits 7–1

Reserved—These bits are reserved and should read 0.

TOUT

Bit 0

Time-Out

out.

—Indicates whether the watchdog timer times 0 = Watchdog timer does not time-out.

1 = Watchdog timer times out.

14-8

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

MOTOROLA

Watchdog Timer Module

14-9

Watchdog Timer Module

14-10

MC9328MX1 Reference Manual

MOTOROLA

Chapter 15

Analog Signal Processor (ASP)

The analog signal processor (ASP) module of the MC9328MX1 consists of an ADC for touch panel input, and a CODEC (both ADC and DAC) for voice input/output.

15.1 Features

The ASP modules offers the following features:

• 9-bit PADC for touch panel and low voltage detection

• On-chip voltage reference for ADC

• 12

×

16-bit FIFO for PADC sample

• Embedded touch panel circuitry

• Supports auto and manual sampling mode

• Programmable pen down and pen-up interrupt to interrupt handler

• Provides data-ready and FIFO-full interrupt to interrupt handler

• True differential input

• Support for temperature compensation by software

15.2 ASP Signal Description

The ASP system block diagram shown in Figure 15-1 illustrates the operation of the individual modules that comprise the ASP.

PEN CONTROL REGISTER

Voltage

Detect

Uip, Uin

From Touch

Panel

PX2

PX1

PY1

PY2

SWITCH

CIRCUIT

SWITCH CNRL and

INPUT SELECT

LOGIC

U

X

Y

INPUT SELECT

PADC

For Touch Interrupt Generation

INTERRUPT

GENERATOR

SAMPLE RATE CTRL REG

COMPARE CONTROL REG

PEN SAMPLE REG (12X16-bit) comp_int touch_int pen_up_int pen_data_int

Figure 15-1. ASP System Block Diagram

MOTOROLA

Analog Signal Processor (ASP)

15-1

Analog Signal Processor (ASP)

Table 15-1. ASP Interface Signal Description

Signal Name Description

Uip, Uin External analog input signal (U-channel) to Pen ADC

PX1, PX2, PY1, PY2 Touch panel interface signals

DVDD

U-channel -ve Input

U-channel +ve Input

Ru2

Ru1

UIP UIN RVM

Rref1

RVP

QVDD GND

R pd

C d

Touch

Panel

SW1

SW3

PX1

PY1

R1A

R p1

R p2

R1B

R2A

R2B

PX2

PY2

SW2

SW4

SW5

AZSEL

AZSEL

SW7

USEL

SW6 SW8

USEL

Pen ADC

MIP(+)

MIM(-)

PADC_OP

PADC_OM

Read X: SW[8..1] = 1100 0110

Read Y: SW[8..1] = 0011 1001

Auto zero: SW[8..1] = 0000 0000

Auto Calibration X SW[8..1] = 1100 1100

Auto Calibration Y SW[8..1] = 0011 0011

Default: SW [8:1] = 0010 000

Figure 15-2. Simplified ASP Signal Path Diagram

15-2

MC9328MX1 Reference Manual

MOTOROLA

Interrupt Generation

Table 15-2. Simplified ASP Signal Path Parameters

Parameter Description Typical Value

R p1

, R p2

, R u1

, R u2

C d

R pd

R ref

QVDD

GND

Pen ADC input resister

Noise decoupling cap

Pen-down detect resister

Analog reference resister

ASP power supply

ASP circuit ground

200 kOhm

0.01 uF

100 kOhm

40 kOhm

1.8 V

0 V

15.3 Interrupt Generation

The following interrupts are provided:

• Pen Touch (pen down) Interrupt (IRQ number = 46)

It is generated upon a pen down event, can be programmed for level trigger or edge trigger.

• Pen Data Compare Interrupt (IRQ number = 9)

Every pen sample is compared with a desired value. If it is greater than (or less than, programmable) the desired value, an interrupt will be generated.

• Pen-up Interrupt (IRQ number = 5)

In Auto XYU or ZXYU mode, with PUIE bit set, whenever a pen-up event is detected, an interrupt signal is generated and sent to the interrupt controller.

• Pen FIFO Data Ready Interrupt (IRQ number = 33)

It is generated whenever there is at least 1 valid data in the FIFO.

• Pen FIFO Full Interrupt (IRQ number = 33)

15.4 Pen ADC (PADC) Operation

The Pen ADC, which has 9-bit accuracy, supports interfacing with a touch panel (X and Y-channel) and a low voltage auxiliary input (U-channel). The sampling sequence as well as the sample rate is user selectable and is up to 9.6 kHz for U-channel input, and 1.2 kHz for XYU + Auto Zero input.

There are 8 switches for the touch panel X and Y input signals, 2 switches for U-channel signal. In manual mode, the switches are turned off/on per the input command from the Switch Control and Input Select

Logic block. In auto mode, they are controlled by a state machine, which is able to automatically generate proper switch settings to select the target input signal for the PADC.

Sample data is stored into the Pen Sample FIFO, which is in 16-bit unsigned integer format. The FIFO is circular buffer design, so if the data is not read fast enough, the FIFO will overflow and old data will be overwritten. When an overflow occurs, the POV status bit is set in the Interrupt/Error Status Register.

MOTOROLA

Analog Signal Processor (ASP)

15-3

Analog Signal Processor (ASP)

AUTO

1

Don’t Care

0

PADE

1

0

1

MOD

00

01

01

10

10

Table 15-3. Pen ADC Operation

AZE

Don’t Care

0

Data Format in the

Pen Sample FIFO

ADC idle

X,Y,X,Y, ....

1

0

1

11 Don’t Care

Don’t Care Don’t Care

00

01

Don’t Care

0

01

10

10

11

1

0

1

Don’t Care

AZ,X,Y,AZ,X,Y, ....

X,Y,U,X,Y,U, ...

AZ,X,Y,U,AZ,X,Y,U, ...

U,U,U, ...

No valid data

ADC idle

X

AZ, X

Y

AZAZ, Y

U

Notes

No A/D sample

Only sample pen input, Disable U input with auto-zero disabled

Only sample pen input, Disable U input with auto-zero enabled

Sample pen input and U input with auto-zero disabled

Sample pen input and U input with auto-zero enabled

Only sample U input

Pen idle state

No A/D sample

In this manual mode, only sample when PADE is toggled from

0

to

1 by software.

When the Pen A/D is configured for AUTO sampling, the sampling operation is carried out continuously allowing the software to read the samples when either the Data Ready or ADC FIFO Full interrupts occur.

In manual mode, the AUTO bit is clear, the Pen ADC samples data only when the PADE bit is toggled from

0

to

1

by software. To get next data, software should restore PADE bit to 0, then set it to 1.

15.4.1 Current-Mode Operation

The ADC is operated in current-mode. The output digital sample is proportional to the differential input current (

i). Each of the input voltages (Vp, Vm) are converted to current (ip, im) by R1, R2, respectively.

The other end of the resister, R1a, R2b are clamped at 300 mV by internal circuitry.

Therefore:

• ip = (Vp - V1a) / R1

• im = (Vm - V2b) / R2

Where ip and im are limited to

• -2.5µA

ip

+9.5µA

• -2.5µA

im

+9.5µA

Calculation for

i is as follows:

-12

µ

A

∆ i

+12

µ

A

Eqn. 15-1

15-4

MC9328MX1 Reference Manual

MOTOROLA

Pen ADC (PADC) Operation

As a result, the input range can be adjusted to fit different panels by tuning the resister value.

NOTE:

The voltage level at all input pins, including XY and U channel, must not exceed QVDD—that is, 1.8 V.

15.4.2 Sample Rate Control

Table 15-4 shows the maximum PADC sample rates.

Table 15-4. Pen ADC Maximum Sample Rate

MODE (Auto) DMCNT IDLECNT DSCNT

Maximum

Sample Rate

ZXY

ZXYU

U

0

0

0

0

0

0

1

1

0

1.5 kHz

1.1 kHz

9.6 kHz idle idle t3 idle t1 t2 data Z into

FIFO data X into

FIFO data Y into

FIFO data U into

FIFO data Z into

FIFO t1 = Transistor switching and input selecting set up time, controlled by DSCNT t2 = Data setup time, controlled by DSCNT and DMCNT t3 = Point to point capture idle time, controlled by IDLECNT data X into

FIFO data Y into

FIFO data U into

FIFO

Figure 15-3. Pen Input Sampling Timing

Figure 15-3 shows the sample timing when AUTO = 1, AZE = 1 and MOD [1:0] = 10.

The output data rate can be calculated using the equations shown in Table 15-5. The variables used in the equations are fields of the Pen A/D Sample Rate Control Register (ASP_PSMPLRG).

• DSCNT (t1)—Data setup count: This controls the time for the MUX and touch panel to settle. The max value is 1.575ms at ACLK = 12MHz.

• DMCNT (t2)—Decimation count: This controls the number of samples to be averaged, which effectively performs a simple comb filter as the second-stage decimation filter.

MOTOROLA

Analog Signal Processor (ASP)

15-5

Analog Signal Processor (ASP)

• IDLECNT (t3)—Idle count: This controls the idle time after each set of measurement. During the idle time, all touch panel control switches are turned off, hence saving current consumption by the touch panel.

NOTE:

For channels X and Y, DSCNT must be at least 1 to allow sufficient settling time of the touch panel and the MUX.

Table 15-5. Output Data Rate Equations

MOD AZE

01 0

01

10

10

11

1

0

1

X

Equations for Output Data Rate

(X,Y,X,Y, ...)

(

DSCNT 1

)

2 × (

+

)

+

IDLECNT

(Z,X,Y,Z,X,Y, ....)

(

DSCNT 1

)

3 × (

+

)

+

IDLECNT

(X,Y,U,X,Y,U, ...)

(

DSCNT 1

)

3 × (

+

)

+

IDLECNT

(Z,X,Y,U,Z,X,Y,U, ...)

(

DSCNT 1

)

4 × (

+

)

+

IDLECNT

(U,U,U, ...)

( DSCNT DMCNT 1 )

+

IDLECNT

(

DSCNT 0

)

The best value for the analog clock ACLK is 12 MHz, which can be controlled by the PADC_CLK field of the Clock Divide Register. The decimation ratio of the filter is 1260, therefore fclk = ACLK/1260. When

ACLK = 12 MHz, fclk will be 9.6 kHz.

Some examples are provided to illustrate how to calculate the output data rate:

1. If MOD [1:0] = 01 and AZE = 0, the X and Y channels are selected and the auto-zero measurement is disabled. The maximum output data rate for each channel is 2.4 kHz when

DSCNT = 1, DMCNT = 0 and IDLECNT = 0.

To get a 200Hz output data rate, set DSCNT = 1, DMCNT = 0, and IDLECNT = 44

2. If MOD [1:0] = 10 and AZE = 1, all the channels are selected, with auto-zero measurement enabled. Maximum output data rate for each channel is 1.2 kHz when DSCNT = 1,

DMCNT = 0 and IDLECNT = 0.

To get a 200Hz output data rate, set DSCNT = 1, DMCNT = 7 (for example, if the decimation ratio = 8, and IDLECNT = 12.

3. If MOD [1:0] = 11, only U channel is selected and the AZE bit is ignored. Maximum output data rate is 9.6 kHz when DMCNT = 0 and IDLECNT = 0. DSCNT can be set to 0 as there is no need for the settling time for the touch panel and MUX.

To get a 200Hz output data rate, set DSCNT = 0, DMCNT = 0, and IDLECNT = 47.

15-6

MC9328MX1 Reference Manual

MOTOROLA

Pen ADC (PADC) Operation

15.4.3 Auto-Zero Function

Due to the large amount of flicker noise in MOS devices that degrade ADC accuracy, an auto-zero measurement method is introduced to store the flicker noise data during each set of measurements. This data will be subtracted from the output sample, by the user’s software. It is recommended that the auto-zero measurement always be enabled.

There are 2 options for the auto-zero point.

• AZ_SEL = 1: this option includes the 200k resistors

• AZ_SEL = 0: this option excludes the 200k resistors

15.4.4 Pen-Down Detection

The pen-down interrupt function is provided for idle mode configuration. In idle mode, PX1 is used as a trigger pin for pen-down interrupt generation. PX1 is normally pulled-up to VDD by Rpd, while PY2 is pulled-down to GND by SW6. When the pen is down, PX1 shorts to PY1 and then pulled to GND. A falling edge is produced which triggers the interrupt circuit to generate a pen-down interrupt.

15.4.5 Pen-Up Detection (Method 1 – Compare Value)

Using this method, a pen up condition is detected by sample value comparison.

Because the sample value of pen up is always smaller than that of pen down; this property can be used to detect pen up.

The value in the Compare Control Register is compared to every pen sample. If the sample is smaller than the register value, an interrupt is generated. The user should set a compare value which lies between the pen-up and minimum pen-down value. The compare value is panel-dependent and the user should experiment to determine the optimum setting.

15.4.6 Pen-Up Detection (Method 2 – Detect Rising Edge)

Using this method, a pen up condition is detected by sampling the level on PX1 pin, its trigger determined by level going high. The method is similar to the one used for pen down detection.

This method is available only in Auto XYU or Auto ZXYU mode. During the time slot for U, the switches are automatically configured to be the same as for pen down detection (idle mode), for example only SW6 is on. PX1 is normally pulled-down by SW6 when the pen touched the screen. When the pen is up, PX1 is released and pulled up by the external resistor Rpd. When the level goes high it is reflected by PUIS bit in the interrupt status register.

15.4.7 Temperature Compensation

In general, the characteristics of the ADC changes with temperature. To keep the ADC stable, either a compensation circuit or a compensation algorithm is required. Because a temperature compensation circuit does not exist in the ASP module, software must be used for compensation.

Auto calibration mode provides the necessary switch settings to help software provide temperature compensation.

MOTOROLA

Analog Signal Processor (ASP)

15-7

Analog Signal Processor (ASP)

Auto calibration mode is enabled by setting the ACAL bit and it works only in auto ZXY mode. The switch settings for X are changed from C6 to CC; and Y is changed from 39 to 33. This connects the ADC

+ve input to QVDD; while the ADC -ve input is connected to GND. This results in a differential input voltage equal to QVDD, which is fixed using an external regulator.

The Software calibration loop involves three steps:

1. At the beginning of panel calibration routine, enable auto ZXY + auto-calibration mode and get samples for X and Y. Store the AZ corrected samples in memory for use as a principle reference. Then disable the auto calibration mode and return to normal modes for sampling.

2. Every time a pen down condition is detected, or at regular time intervals, repeat step 1 to get an updated reference sample for X and Y. Compare the sample value with the principle reference taken in step 1 to determine the percentage change.

3. During normal sampling, apply the calculated percentage changes to AZ corrected samples.

This will compensate for the effect of temperature drift on the ADC gain.

15.5 Programming Model

The ASP module includes eight 32-bit registers. Table 15-6 summarizes these registers and their addresses.

Table 15-6. ASP Module Register Memory Map

Description

ASP Control Register

Pen A/D Sample Rate Control Register

Compare Control Register

Interrupt Control Register

Interrupt/Error Status Register

Pen Sample FIFO

Clock Divide Register

ASP FIFO Pointer Register

Name Address

ASP_ACNTLCR 0x00215010

ASP_PSMPLRG 0x00215014

ASP_CMPCNTL 0x00215030

ASP_ICNTLR

ASP_ISTATR

ASP_PADFIFO

ASP_CLKDIV

0x00215018

0x0021501C

0x00215000

0x0021502C

ASP_FIFO_PTR 0x00215034

15-8

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

15.5.1 ASP Control Register

The Control Register determines the configuration of PADC block.

ASP_ACNTLCR

BIT 31

TYPE

RESET r

0

30 r

0

29 r

0

Control Register

r

0

28 27 26 25

ASW

B

ACA

L

CLKEN rw

0 rw

0 rw

1

24 23

SWRST r

0 rw

0

0x0200

22 r

0

21

U_SEL AZ_SEL rw

0

20 rw

0

19 r

0

Addr

0x00215010

18 17 16 r

0 r

0 r

0

BIT

TYPE

RESET

15 14

AZE AUTO rw

0 rw

0

13

MOD

12 rw

0 rw

0

11 10 9 8 7 6 5

SW8 SW7 SW6 SW5 SW4 SW3 SW2 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0

0x0000

4

SW1 rw

0

Name

Reserved

Bits 31–28

ASWB

Bit 27

Table 15-7. Control Register Description

Description

Reserved—These bits are reserved and should read 0.

ACAL

Bit 26

CLKEN

Bit 25

3 r

0

2 r

0

1 0

PADE BGE rw

0 rw

0

Settings

Auto Mode Switch Bypass

—Controls the switch settings in Auto XY mode with AZ off. When enabled, switch settings take the value of SW[7...0], otherwise is determined by internal logic. This is only for ATE test (debug) purpose.

1 = Bypass enable. Switches are set by SW[7:0]

0 = Bypass disable. Switches are set by internal logic

Auto Mode Calibration

—Enables/Disables switch settings for auto-calibration in auto-ZXY mode. Switch settings for X

/ Y are changed from C6 / 39, to CC / 33 respectively.

1 = Enable

0 = Disable

Clock Enable

—Enables/Disables the clock into the Pen

ADC clock generator. This is used to save power when the

Pen ADC is not in use.

0 = Disable clock into the ADC clock generator

1 = Enable clock into Pen ADC clock generator

Reserved—This bit is reserved and should read 0.

Reserved

Bit 24

SWRST

Bit 23

Software Reset

—Resets the entire ASP module. All ASP registers will be restored to default value upon reset.

0 = No effect

1 = Reset -This automatically restores to 0

Reserved

Bit 22

U_SEL

Bit 21

Reserved—This bit is reserved and should read 0.

U-Channel Resistor Selection

—Selects which external resistor to use for U-channel measurement.

0 = Resistor at UIN and UIP pins

1 = Resistor at R1a and R2a pins

MOTOROLA

Analog Signal Processor (ASP)

15-9

SW8

Bit 11

SW7

Bit 10

SW6

Bit 9

SW5

Bit 8

SW4

Bit 7

SW3

Bit 6

SW2

Bit 5

SW1

Bit 4

Reserved

Bits 3–2

Analog Signal Processor (ASP)

Name

AZ_SEL

Bit 20

Reserved

Bits 19–16

AZE

Bit 15

Table 15-7. Control Register Description (Continued)

Description Settings

Auto-Zero Position Selection

—Selects the position of auto-zero measurement.

0 = Measurement taken without the external resistor at the R1a and R2a pins

1 = Measurement taken with the external resistor at R1a and

R2a pins

Reserved—These bits are reserved and should read 0.

AUTO

Bit 14

MOD

Bits 13–12

Auto-Zero Enable

measurement.

—Enables/Disables the auto-zero 0 = No auto-zero measurement

1 = Auto-zero measurement taken before every pin input measurement

Auto Sampling

—Enables/Disables Pen A/D auto sampling function. When set, transistor switches are sampled for selected analog inputs X, Y, or U. This process repeats when the IDLE counter reaches zero. In AUTO mode, the

IDLE counter is reloaded when it reaches zero.

0 = Auto sampling off (Manual mode sampling is selected)

1 = Auto sampling on

Mode

—Selects the analog input signals for A/D sampling dependent on AUTO bit setting. See Table 15-3.

00 = No input signal selected

01 = Auto XY, or Manual X

10 = Auto XYU, or Manual Y

11 = selects only U

Switch Control

—Turns the transistor switches on/off when the AUTO function is off or when the Pen A/D is off in touch panel idle state.

0 = Transistor off

1 = Transistor on

In manual modes, switches are set according to the configuration of SW[8...1] bits.

In auto modes, switches are set by internal logic. SW[8...1] are ignored and should be set to 0. Normal settings for sampling X is [11000110]; Y is [00111001].

Exception cases occur when ACAL bit or ASWB bits are set.

Reserved—These bits are reserved and should read 0.

15-10

MC9328MX1 Reference Manual

MOTOROLA

Name

PADE

Bit 1

BGE

Bit 0

Programming Model

Table 15-7. Control Register Description (Continued)

Description Settings

Pen A/D Enable

—Enables/Disables the Pen A/D

Controller. This bit must be set after all other control bits are set. After this bit is set, A/D starts sampling. This bit must be cleared by software when the touch penal is in idle state for power saving

— that is, waiting for a pen interrupt. When this bit is clear, it flushes the Pen Sample FIFO.

0 = Pen A/D disabled

1 = Pen A/D enabled

Voltage Reference Enable

—Enables/Disables the voltage reference circuit.

0 = Disable Voltage Ref

1 = Enable Voltage Ref

15.5.2 Pen A/D Sample Rate Control Register

The Pen A/D Sample Rate Control Register selects the sampling rate for touch pen input. Each application may require different pen input sampling rates. The maximum A/D sampling rate is limited by the A/D design and the input signal data setup time. The design is targeted to support up to a 200 Hz data rate for each input signal. The user must set the data setup time and idle time for power saving.

ASP_PSMPLRG

BIT 31 30 29

Pen A/D Sample Rate Control Register

28 27 26 25 24 23 22 21 20 19

Addr

0x00215014

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0X0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–15

DMCNT

Bits 14–12 r

0

15 14 13

DMCNT

12 rw

0 rw

0 rw

0

11 10

BIT_SELECT rw

0 rw

0

9 rw

0

8 rw

0

0X0000 rw

0

7 6

IDLECNT rw

0

5 rw

0

4 rw

0

3 rw

0

Table 15-8. Pen A/D Sample Rate Control Register Description

Description Settings

Reserved—These bits are reserved and should read 0.

rw

0

2 1

DSCNT rw

0

Decimation Ratio Count

—Controls the decimation ratio of the second-stage FIR. Input clock to this counter is fclk.

000 = Decimation ratio is 1

001 = Decimation ratio is 2

010 = Decimation ratio is 3

011 = Decimation ratio is 4

100 = Decimation ratio is 5

101 = Decimation ratio is 6

110 = Decimation ratio is 7

111 = Decimation ratio is 8

0 rw

0

MOTOROLA

Analog Signal Processor (ASP)

15-11

Analog Signal Processor (ASP)

Name

Table 15-8. Pen A/D Sample Rate Control Register Description (Continued)

Description Settings

BIT_SELECT

Bits 11–10

Bit Select

—Controls which bits to select from the FIR output.

IDLECNT

Bits 9–4

DSCNT

Bits 3–0

Idle Count

—Controls the number of clocks between the last capture and the first capture of two pen input points. Input clock to this counter is fclk.

Data Setup Count

—Controls the input signal data set up time after the transistor switching circuit and input select are settled. Input clock to this counter is fclk.

00 = 16 bits starting from 1st MSB of FIR output

01 = 16 bits starting from 2nd MSB of FIR output

10 = 16 bits starting from 3rd MSB of FIR output

11 = 16 bits starting from 4th MSB of FIR output

0x00 = 0 clock

0x01 = 1 clock

...

0x3F = 63 clocks

0000 = 0 clock

0001 = 1 clocks

...

1111 = 15 clocks

15.5.3 Compare Control Register

The Compare Control Register is used to detect the out-of-range samples on the selected input. Typical application of this function is to detect a pen-up event, or to serve as an alarm when the external input is beyond a specific range.

ASP_CMPCNTL

BIT

TYPE

RESET

31 r

0

30 r

0

29 r

0

28 r

0

27 r

0

Compare Control Register

26 r

0

25 r

0

24 23 r

0

0X0000 r

0

22 r

0

21 r

0

20 r

0

19

INT rw

0

Addr

0x00215030

18

CC rw

0

17 16

INSEL rw

0 rw

0

BIT

TYPE

RESET

15 rw

0

Name

Reserved

Bits 31–20

INT

Bit 19

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0 rw

0

9 8 7

COMPARE VALUE

6 rw

0 rw

0 rw

0

0X0000

5 rw

0

4 rw

0

Table 15-9. Compare Control Register Description

Description

Reserved—These bits are reserved and should read 0.

3 rw

0

2 rw

0

Settings

Interrupt Status

—Sets when a trigger event is detected. Write

1

to clear.

1 rw

0

0 = No trigger event was detected

1 = A trigger event was detected

0 rw

0

15-12

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

CC

Bit 18

Name

INSEL

Bits 17–16

COMPARE VALUE

Bits 15–0

Table 15-9. Compare Control Register Description (Continued)

Description Settings

Compare Control

operation.

Input Select

—Selects the input samples to compare with.

—Controls the compare 0 = Trigger when the compare value is greater than the sample

1 = Trigger when the sample is greater than the compare value

00 = No compare, interrupt disabled

01 = Channel X

10 = Channel Y

11 = Channel U

Compare Value

—Contains the value to compare with the selected sample.

15.5.4 Interrupt Control Register

The Interrupt Control Register enables and controls each interrupt function. All interrupts are grouped into one of the two outputs to the system interrupt handler: TOUCH_INT and PEN_DATA_INT.

ASP_ICNTLR

BIT

Interrupt Control Register

31 30 29 28 27 26 25 24 23 22 21 20 19

Addr

0x00215018

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0X0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET r

0

15 14 13 12 11 10 9

PUI

E r

0 r

0 r

0 r

0 r

0 r

0

8 r

0

7 6 5 4

POL EDGE PIRQE r

0

0X0000 rw

0 rw

0 rw

0

Table 15-10. Interrupt Control Register Description

Description

Reserved—These bits are reserved and should read 0.

3 r

0

Name

Reserved

Bits 31–11

PUIE

Bit 10

Reserved

Bits 9 - 7

POL

Bit 6

Pen-up Enable

—Enables/Disables Pen-up Interrupt signal.

The interrupt request number is 5.

Reserved—These bits are reserved and should read 0.

Pen Interrupt Polarity

—Selects the polarity of the TOUCH_INT input signal for interrupt trigger.

0 = Disable

1 = Enable

2 r

0

1 0

PFFE PDRE rw

0 rw

0

Settings

0 = Active low, or falling edge

1 = Active high, or rising edge

MOTOROLA

Analog Signal Processor (ASP)

15-13

Analog Signal Processor (ASP)

Name

EDGE

Bit 5

PIRQE

Bit 4

Reserved

Bits 3–2

PFFE

Bit 1

PDRE

Bit 0

Table 15-10. Interrupt Control Register Description (Continued)

Description Settings

Edge Enable

—Selects edge or level trigger on the TOUCH_INT input signal.

Pen Interrupt Enable

—Enables/Disables generation of the pen interrupt signal, TOUCH_INT.

Reserved—These bits are reserved and should read 0.

0 = Level trigger

1 = Edge trigger

0 = Disable

1 = Enable

Pen FIFO Full Interrupt Enable

—Enables/Disables the pen sample FIFO full interrupt.

Pen Data Ready Interrupt Enable

—Enables/Disables the pen sample ready interrupt.

0 = Disable

1 = Enable

0 = Disable

1 = Enable

15.5.5 Interrupt/Error Status Register

The Interrupt/Error Status Register shows the source of interrupts when there is an interrupt event. Each interrupt status bit in this register can be cleared by either writing 1 to it or by reading/writing the associated data register, depending on the nature of interrupt.

ASP_ISTATR

BIT 31

Interrupt/Error Status Register

30 29 28 27 26 25 24 23 22 21 20 19

Addr

0x0021501C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–11

PUIS

Bit 10

Reserved

Bits 9–8

15 r

0

14 13 12 11 10

PUI

S r

0 r

0 r

0 r

0 r

0

9 r

0 r

0

8 7 6

POV PEN rw

0 rw

0

0X0000

5 r

0

4 r

0

3 r

0

2 r

0

Table 15-11. Interrupt/Error Status Register Description

Description Settings

Reserved—These bits are reserved and should read 0.

1 0

PFF PDR rw

0 rw

0

Pen-up Status

—Bit is set when a pen-up event is pending.

Clear by writing ‘1’.

Reserved—These bits are reserved and should read 0.

0 = No pen-up interrupt is pending

1 = Pen-up interrupt is pending

15-14

MC9328MX1 Reference Manual

MOTOROLA

Name

POV

Bit 7

Programming Model

Table 15-11. Interrupt/Error Status Register Description (Continued)

Description Settings

Pen Sample Data Overflow

—Indicates whether there has been a pen sample data overflow in the Pen Sample FIFO. It will not generate an interrupt on overflow. It is recommended that software clear this bit at the beginning of a pen capture and check for an error at the end of a stroke. Clear by writing

1

.

0 = No overflow

1 = FIFO overflow

Pen Interrupt

—Indicates that a pen touch interrupt is pending.

Clear by writing

1

.

0 = No PEN interrupt is pending

1 = PEN interrupt is pending

Reserved—These bits are reserved and should read 0.

PEN

Bit 6

Reserved

Bits 5–2

PFF

Bit 1

PDR

Bit 0

Pen Sample FIFO Full

—Indicates that the Pen Sample FIFO is full. Reading the data in Pen Sample FIFO will clear this bit automatically.

0 = Pen sample FIFO is not full

1 = Pen sample FIFO is full

Pen Data Ready

—Indicates that at least one valid data sample is available in the Pen Sample FIFO. Reading all the data in the

Pen Sample FIFO will clear this bit automatically.

0 = No valid data in pen sample

FIFO

1 = At least one valid data in the pen sample FIFO

15.5.6 Pen Sample FIFO

The 12x16 Pen Sample FIFO holds the sample data after Pen A/D sampling. The data structure is controlled by the MOD bits of control register.

ASP_PADFIFO

BIT 31 30 29 28 27 26

Pen Sample FIFO

25 24 23 22 21 20 19

Addr

0x00215000

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0X0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET rw

0

15 14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0

9 rw

0

8 7

SAMPLE rw

0

0X0000 rw

0

6 5 rw

0 rw

0

4 rw

0

3 2 1 0 rw

0 rw

0 rw

0 rw

0

MOTOROLA

Analog Signal Processor (ASP)

15-15

Analog Signal Processor (ASP)

Name

Reserved

Bits 31–16

SAMPLE

Bits 15–0

Table 15-12. Pen Sample FIFO Register Description

Description

Reserved—These bits are reserved and should read 0.

Sample

—Holds the sample data after Pen A/D sampling. The data structure is controlled by the

MOD bits of control register. The format of the pen sample data is a 16-bit unsigned word format.

15.5.7 Clock Divide Register

The Clock Divide Register controls the divide ratio for the ASP Clocks. The system clock is divided down to generate the clocks for the pen ADC.

ASP_CLKDIV

BIT 31 30 29 28 27

Clock Divide Register

26 25 24 23 22 21 20 19

Addr

0x0021502C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0X0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7 r

0

0X0000 r

0

6 r

0

5 r

0

4 rw

0 rw

0

3 2

PADC_CLK

1 rw

0 rw

0

Table 15-13. Clock Divide Register Description

Name Description

Reserved

Bits 31–5

PADC_CLK

Bits 4–0

Reserved—These bits are reserved and should read 0.

PADC Clock Divider

—Selects the divide ratio to generate the clock for use by the pen ADC.

Settings

0x00 = Clock disabled

0x01 = Divider ratio is 2

...

0x1F = Divider ratio is 32

0 rw

0

15-16

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

15.5.8 ASP FIFO Pointer Register

Pen FIFO in the ASP module has the write pointer and read pointer reflected in this register.

ASP_FIFO_PTR

ASP FIFO Pointer Register

Addr

0x00215034

BIT

31

30 29 28 27 26 25 24 23 22 21 20 19 18 17 BIT16

TYPE

RESET r

0 r

0 r r r r r r

0 0 0 0 0 0 r

0 r

0

0X0000 r

0 r

0 r

0 r

0 r

0 r

0

BIT

15

14 13 12 11 10 9 8

TYPE

RESET r

0 r

0 r r r r r r

0 0 0 0 0 0

7 6 5 4

PEN_FIFO_READ_POINTE

R r r r

0 0

0X0000

0 r

0

3 2 1 BIT 0

PEN_FIFO_WRITE_POINTE

R r r r r

0 0 0 0

Table 15-14. ASP FIFO Pointer Register Description

Name

Reserved

Bits 31–5

PEN_FIFO_READ_POINTE

R

Bit 7–4

PEN_FIFO_WRITE_POINTER

Bit 3–0

Description Settings

Reserved—These bits are reserved and should read 0.

PEN_FIFO_READ_POINTER

—Holds the read pointer of PADC FIFO.

PEN_FIFO_WRITE_POINTER

—Holds the write pointer of PADC FIFO.

MOTOROLA

Analog Signal Processor (ASP)

15-17

Analog Signal Processor (ASP)

15-18

MC9328MX1 Reference Manual

MOTOROLA

Chapter 16

Bluetooth Accelerator (BTA)

This chapter describes the Bluetooth Accelerator (BTA) which, controlled by software running on the

ARM core, implements baseband protocols and other low-level link routines of the Bluetooth baseband.

This chapter covers the following main topics:

• Bluetooth Primer

• BTA Overview

• Pin Configuration for BTA

• Programming Model

16.1 Bluetooth Primer

Bluetooth is a short-range radio link intended to replace the cable connecting portable and/or fixed electronic devices. Key features of Bluetooth technology are robustness, low complexity, low-power, and low cost.

Bluetooth operates in the unlicensed ISM band at 2.4 GHz and uses frequency hopping to combat interference and fading. A symbol rate of 1 Mbps utilizing binary shaped FM modulation minimizes transceiver complexity. A slotted channel is applied with a nominal slot length of 625 µs. For full duplex transmission, a time division duplex scheme exchanges packets through the channel. Each packet is transmitted on a different hop frequency and typically occupies a single slot, however can extend to a maximum of five slots.

A Bluetooth system provides a point-to-point connection (only two Bluetooth units involved), or a point-to-multipoint connection where the channel is shared among several Bluetooth units. Two or more units sharing the same channel (set of hopping frequencies) form a piconet. One Bluetooth unit acts as the master of the piconet and any the other units act as slaves. A maximum of seven slaves can be active in the piconet, and many more slaves can remain locked to the master in a so-called parked state. Parked slaves cannot be active on the channel, however remain synchronized to the master.

Multiple piconets with overlapping coverage areas form a scatternet. Each piconet has a single master, and a master in one piconet can serve as a slave in another piconet. Slaves can participate in different piconets on a time-division multiplex basis. The piconets are not synchronized in time or frequency.

A Bluetooth system consists of a radio unit, a link control unit, and a support unit for link management and host terminal interface functions (see Figure 16-1 on page 16-2). The radio, link controller, and link manager are described in the

Specification of the Bluetooth System, version 1.1

.

MOTOROLA

Bluetooth Accelerator (BTA)

16-1

Bluetooth Accelerator (BTA)

16.2 BTA Overview

Figure 16-2 on page 16-3 shows the functional blocks of the BTA and its internal signals or connections.

BTA core features include:

• Low level baseband processing engine featuring:

— Packet assembler/disassembler

— HEC and CRC generation and checks

— Encryption/decryption

— Whitening/de-whitening

— 1/3 FEC and 2/3 FEC encoding/decoding

• Hop frequency selection co-processing module

• 32 words (of 16 bits each) bit buffer (Rx and Tx buffer)

• Maintenance of native/estimated Bluetooth clocks

• Access code correlation with bit/frame timing extraction

• Programmable RF controller supports two front ends, including:

— MC13180

— Silicon Wave (SiW 1502)

• SPI controller interface to RF front ends

• Joint detection for timing, frequency, and packet synchronization and Maximum Likelihood

Sequence Estimation (MLSE/JD) pre-processor for improved RF performance

• Bluetooth Application Timer (BAT)

• Low-power support

• IP-bus interface (

16-bit Blue-line Standard, version 2.0

)

2.4

GHz

Bluetooth Radio

Bluetooth

Link Controller

Bluetooth

Link Manager and I/O

Figure 16-1. Functional Blocks in a Bluetooth System

16-2

MC9328MX1 Reference Manual

MOTOROLA

Module Descriptions

Wake-Up Timer

Wake-Up 1 Comp.

Wake-Up 2

Wake-Up 3

Comp.

Comp.

Wake-Up

Counter

32

kHz

Clock

Bluetooth Core

Bit Buffer

Access Code

BitBuf

Correlator

Threshold

Trigger

Comp.

Controller

• Control FSM

Native Clock

Estimated Clock

Bit and Frame Timing

• I nterrupt Generation

Bluetooth Pipeline

HEC,

CRC

Encrypt White

FEC DSP

IP Bus I/F

IP Bus Interface

IP Interface

• Interface Control

Bus Buffering

Multi Clock Sync

Co-Processor

• Freq. Hop Generator

Timer

• BT App. Timer

Radio Interface

• SPI

µ

Programmable RF I/O

• PWM and RSSI

• TxPower PWM

Figure 16-2. Functional Blocks in the Bluetooth Accelerator

The main blocks include the Bluetooth pipeline, a bit buffer, the correlator functions, a wake-up timer, an

IP bus interface, a radio interface to an external radio, a co-processor for hop frequency generation, and a

Bluetooth application timer. The following sections contain an in-depth explanation of each block.

16.3 Module Descriptions

16.3.1 Bluetooth Core

The Bluetooth core implements low level time critical baseband routines. Through the IP bus, a number of registers in the Bluetooth core can be accessed to write to the control words and to retrieve the status of the

Bluetooth core. Within the Bluetooth core, the main functional blocks are:

• IP bus interface

• Sequencer

• Bluetooth pipeline processor

MOTOROLA

Bluetooth Accelerator (BTA)

16-3

Bluetooth Accelerator (BTA)

• Bit buffer

• Correlator

• Application timer

• Hop Selection Co-Processor

• Radio control

16.3.1.1 IP Bus Interface

The Bluetooth core interfaces to the IP 2.0 bus. The IP bus clock (ips_cont_clk) ranges from 24 MHz to

100 MHz. Running the clock outside of these ranges will cause the interface to fail due to internal synchronization logic.

The IP bus clock is faster than, and out of phase with, the internal 8 MHz clock. The Bluetooth module inserts dynamic wait states to synchronize the IP bus clock with this internal clock. Table 16-1 shows the recommended settings for inserting dynamic wait-states into the internal read and write cycles (by using the ips_xfr_wait signal) to complete the read/write cycle. Refer to Section 16.5.9.1, “Clock Control

Register.”

Table 16-1. CLK_CONTROL Register Settings for Synchronization

BT1_CLK_IN_DIV Value ips_clk (MHz) BT1_WSLOT Value BT1_RSLOT Value

16

24

32

40

48

64

80

96

64

80

96

24

24

32

40

48

2

3

4

4

3

3

6

4

4

6

4

4

2

2

2

3

4

2

2, (3)

2, (3)

6

2, (6)

2, (6)

4

4

4

2

2

16-4

MC9328MX1 Reference Manual

MOTOROLA

Module Descriptions

Table 16-1. CLK_CONTROL Register Settings for Synchronization (Continued)

BT1_CLK_IN_DIV Value ips_clk (MHz) BT1_WSLOT Value BT1_RSLOT Value

32

48

64

80

96

16

24

32

40

7

6

B

3

9

9

6

C

3

3

6, (7)

6, (7)

3

3

6

C

16.3.1.2 Sequencer

The sequencer is the main controller in the Bluetooth core. The sequencer handles all timing and synchronization of all the other BTA units. The sequencer provides control over the following units:

• Bluetooth clocks

• Interrupt generation

• Top-level Bluetooth pipeline

• Bit and frame timing

The pipeline control and bit and frame timing is handled by the Bluetooth pipeline processor, which is discussed in Section 16.3.1.3, “Bluetooth Pipeline Processor.”

16.3.1.2.1 Bluetooth Clocks

For Bluetooth packet timing purposes, the Bluetooth core maintains two internal clocks: NativeClk and

EstimatedClk. The Bluetooth related clocks and counters maintained by the Bluetooth core are listed in

Table 16-2.

Table 16-2. Bluetooth Clocks and Counters

Name Bit Size Input Frequency Precision Purpose

NativeCount

EstimatedCount

OffsetCount

NativeClk

12

12

12

28

8 MHz

8 MHz

8 MHz

3.2 kHz

High

High

High

Generate native 3.2 kHz SysTick.

Generate estimated 3.2 kHz SysTick of a remote master. The count is updated each time the access code is triggered unless a special override bit is set.

Difference between NativeCount and

EstimatedCount.

Low (power down)

High (operation)

Free-running native clock of the unit.

When the unit is the master of a communication, the remote slave must synchronize to this clock.

MOTOROLA

Bluetooth Accelerator (BTA)

16-5

Bluetooth Accelerator (BTA)

Name

EstimatedClk

OffsetClk

Table 16-2. Bluetooth Clocks and Counters (Continued)

Bit Size Input Frequency Precision Purpose

28

28

3.2 kHz

3.2 kHz

Low (power down)

High (operation)

Estimate of the remote master’s

NativeClk. Set by software and updated by the EstimatedCount.

Low (power down)

High (operation)

Difference between NativeClk and

EstimatedClk. This is updated each

SysTick.

When the unit is the master of a piconet, its NativeClk is used for timing of slots, hopping frequency sequence, whitening/de-whitening initialization, and so on.

NativeClk

is a free-running 28 bit counter updated at a frequency of 3.2 kHz. The 3.2 kHz clock is generated by dividing the high precision 8 MHz clock by 2,500 using a 12-bit counter (NativeCount).

Bluetooth specifications stipulate that, in connection states of high activity, a worst case accuracy of ± 20 ppm is expected for the native clock. In low-power states (Standby, Hold or Park modes), a relaxed accuracy of ± 250 ppm is allowed.

NOTE:

When temperature drift and aging are taken into account, the requirement of the high precision clock is more likely to be around ± 10 ppm.

EstimatedClk

is a clock that is maintained by the unit when it operates as a slave, and it keeps track of a remote master’s NativeClk. During a page scan, when the slave unit receives an access code trigger from the master, it presets the EstimatedCount with an expected count and sets the two least significant bits of

EstimatedClk to “00.” This value causes the unit to respond 625 µs later, relative to the beginning of the time slot, regardless of whether it receives the first or second page within the time slot.

Later in the link setup, the EstimatedClk is updated with the remote master’s native clock, which is sent in the FHS packet. EstimatedClk is incremented by the EstimatedCount. During active connection state, whenever the access code is triggered from the master’s transmission, EstimatedCount is updated with an expected count, therefore preventing the EstimatedClk from drifting away from the remote master’s

NativeClk.

A third value, OffsetClk, maintains the difference between EstimatedClk and NativeClk. OffsetClk is updated at every NativeClk tick. Writing to the OFFSET_CLK_LOW and OFFSET_CLK_HIGH registers will update EstimatedClk with the sum of NativeClk and OffsetClk on the next NativeClk tick.

16.3.1.2.2 Interrupt Generation

The Bluetooth core provides three interrupt lines:

1. A combination of three interrupts that are Logical-OR’ed together into a single active-high wire. This one-shot interrupt is termed “BTsys.”

2. An interrupt triggered by the Bluetooth application timer termed “BTtim.”

3. An interrupt generated during the wake-up sequence termed “BTwui.”

The interrupts are summarized and described in Table 16-3 on page 16-7.

16-6

MC9328MX1 Reference Manual

MOTOROLA

Module Descriptions

Table 16-3. Bluetooth Core Interrupts

Frequency Description Interrupt Type

BTsys SysTick 3.2 kHz (fixed) SysTick is the main Bluetooth heartbeat. The phrase depends on whether the NativeClk (when unit is the master) or

EstimatedClk (when unit is the slave) is used.

EndOfHeader (EOH) 800 Hz (max) EOH interrupts are issued after a header has been decoded during receive of certain types of packets. For ID, NULL and

POLL packets, no interrupt is generated. For HVx and FHS packets, an interrupt is generated after the packet header

(because packet length is fixed). For DMx, DHx, AUX and DV packets, an interrupt is generated after the payload header has been decoded. This interrupt is maskable via the COMMAND

Register.

BTtim

EndOfFrame (EOF) 1.6 kHz (max) Generated after any received or transmitted frame. This interrupt is maskable via the COMMAND Register.

BT timer – User programmable Bluetooth application-specific timer.

BTwui BT wakeup 2

BT wakeup 3

– Interrupt that occurs during the wakeup sequence. The interrupt is generated when the PLL is enabled and when it has stabilized.

16.3.1.3 Bluetooth Pipeline Processor

The Bluetooth core contains a Bluetooth pipeline in which all low-level processing is handled in dedicated hardware. The pipeline units are controlled by the sequencer, however each unit contains an additional, small controller to perform its function independently. The units communicate via a dedicated serial wire.

The control is handled by a request/acknowledge scheme when data is available. The pipeline contains the following four units:

• HEC/CRC generator and checker

• Encryption and decryption engine

• Whitening and de-whitening logic

• FEC coding and decoding

The four units process incoming or outgoing Bluetooth packets. Figure 16-3 shows the format of a

Bluetooth packet.

MOTOROLA

Bluetooth Accelerator (BTA)

16-7

Bluetooth Accelerator (BTA)

2

Single-Slot Packet

1 5

L_CH FLOW LENGTH

OR

2 1

L_CH FLOW

Multi-Slot Packet

9

LENGTH

4

Undefined

Bluetooth

Packet

72

Access Code

54

Header

Payload

Header

0 to 2745

Payload

AM_ADDR

3

TYPE

4

FLOW

1

ARQN

1

SEQN

1

HEC

8

Figure 16-3. Bluetooth Packet Format

The packet type information is available from the payload header field, which is the first one or two bytes of the payload depending on the packet type. The packet header and length information can be determined from this field.

The PACKET_HEADER and PAYLOAD_HEADER Registers hold header information. In transmit mode, these registers are written. In receive mode, these registers are read.

Each of the subsections of the Pipeline Processor are discussed in detail in the next sections.

16.3.1.3.1 HEC/CRC Generator and Checker

The Header Error Correction (HEC) and Cyclic Redundancy Check (CRC) unit can be enabled or disabled by software. If enabled, the unit operation depends on the direction of the bit stream transfer.

Transmit Function

—When a Bluetooth packet is to be transmitted by the unit, the HEC/CRC unit performs the following sequence of actions:

1. Generate the HEC for the packet header.

2. Generate the payload CRC based on the length supplied by software.

3. The software must specify the HEC/CRC initialization word by writing the initialization word to the HECCRC_CONTROL register. The initialization word is derived from the

Bluetooth clock. The generation of the initialization word is described in the

Specification of the Bluetooth System, version 1.1

.

4. Raise a flag to the sequencer after the last CRC bit has been encoded. This is used for zero stuffing (when necessary) before FEC encoding.

Receive Function

—When a Bluetooth packet is received, the HEC/CRC unit performs the following sequence of actions:

1. Extract the type and length information from the bit stream. This information is used to control the remaining parts of the bit stream.

The type information is available from the packet header and length information fields in the payload header field, which is the first one or two bytes of the payload, depending on the packet

16-8

MC9328MX1 Reference Manual

MOTOROLA

Module Descriptions

type. The CRC is the last 16 bits in the bit stream. The length information indicates the number of bytes in the payload excluding the payload header and the CRC code.

2. Evaluate the HEC.

3. Calculate the CRC.

If the HEC/CRC unit reads an erroneous type or length field because of channel errors, the

Bluetooth core will decode the stream incorrectly. The software must detect this condition by reading the HEC and CRC status from the STATUS register and act accordingly.

NOTE:

Errors in the type information field will probably be detected by the HEC check. The length information field cannot be validated until the CRC has been received.

Table 16-4 shows the relationship between packet types and the type of coding they imply. This information is encoded into a look-up table used in the controller.

Table 16-4. Packet Types and FEC/CRC Processing

Packet Type Length CRC Enabled

NULL

POLL

FHS

DM1

DH1

HV1

HV2

HV3

DV

0000

0001

0010

0011

0100

0101

0110

0111

1000

5

5

5

5

5

5

5

5

5

AUX1

DM3

DH3

_b

_b

1001

1010

1011

1100

1101

5

9

9

9

2

9

2 Disabled

DM5

DH5

1110

1111

9

9

1.

CRC and 2/3 FEC are performed on the data field only.

2.

Not defined in the standard yet.

Enabled

Enabled

Disabled

Disabled

Enabled

Enabled

Enabled

Disabled

Disabled

Disabled

Enabled

1

Disabled

Enabled

Enabled

Disabled

1/3 FEC

Enabled

Disabled

Disabled

Disabled

Disabled

Disabled

Enabled

Disabled

Disabled

Disabled

Disabled

Disabled

Disabled

Disabled

Disabled

Disabled

Disabled

2/3 FEC

Enabled

Disabled

Enabled

1

Disabled

Enabled

Disabled

Disabled

2

Disabled

2

Enabled

Disabled

Disabled

Disabled

Enabled

Enabled

Disabled

Disabled

Enabled

MOTOROLA

Bluetooth Accelerator (BTA)

16-9

Bluetooth Accelerator (BTA)

16.3.1.3.2 Encryption and Decryption Engine

The encryption engine handles all low-level time-critical Bluetooth security functions for encryption and decryption of user information (payload only). The key bit stream uses a method derived from the summation stream cipher generator attributable to Massey and Rueppel. Encryption and decryption are carried out without intervention from the Bluetooth core.

The encryption engine uses a local controller to perform initialization and runtime control. Encryption is enabled by software copying the CRC polynomial to the BTA. This task consists of writing thirteen 16-bit words in a row to the ENCRYPTION_CONTROL_X13 register. When the last word has been written, the engine starts initializing the registers as specified in the standard. The sequence takes 240 cycles to complete. When this sequence is complete, the encryption engine is armed and ready to perform encryption/decryption on the payload in the following slot.

CAUTION:

During the initialization cycle, the BTA uses

LW0

and

LW1

in the bit buffer

(see Section 16.3.1.4, <Emphasis>Bit Buffer) to store temporary information. Any information stored in

LW0

and

LW1

will be overwritten.

Initialization of the encryption engine requires an encryption key, the Bluetooth address of the master and clock information. The sequence to be written into the engine during initialization is shown in Table 16-5 and the nomenclature used in the table is as follows:

• CL[0] contains CL

7-0

, CL[1] contains CL

15-8

and CL[2] contains CL

23-16

. (see the

Specification of the Bluetooth System v. 1.1

)

• CL

0

through CL

25

correspond to CLK

1

through CLK

26

of the currently used clock; that is, CL

0-25 equal CLK

1-26

right-shifted by one.

• Kc’[0] though Kc’[15] specify the 128 bit encryption key.

• Addr[0] through Addr[5] are the Bluetooth address (BD_ADDR) of the master.

If no initialization value is written to the unit, encryption is disabled.

Table 16-5. Writing Sequence for Encryption Engine Initialization

Word Number Bits 15–8 Bits 7–0

6

7

4

5

2

3

0

1

8

9

10

Kc’[1]

Kc’[3]

Kc’[5]

Kc’[7]

Kc’[9]

Kc’[11]

Kc’[13]

Kc’[15]

Addr[1]

Addr[3]

Addr[5]

Kc’[0]

Kc’[2]

Kc’[4]

Kc’[6]

Kc’[8]

Kc’[10]

Kc’[12]

Kc’[14]

Addr[0]

Addr[2]

Addr[4]

16-10

MC9328MX1 Reference Manual

MOTOROLA

Module Descriptions

Table 16-5. Writing Sequence for Encryption Engine Initialization (Continued)

Word Number Bits 15–8 Bits 7–0

11

12

CL[1]

111000CL

25

CL

24

CL[0]

CL[2]

16.3.1.3.3 Whitening/De-Whitening

According to the Bluetooth specifications, all packets must be scrambled to randomize the data from highly redundant patterns and to minimize DC bias in the packet. The whitening unit performs this scrambling (whitening) and descrambling (de-whitening) of the packet header and payload (including the

CRC) during transmit and receive.

Whitening is enabled or disabled by software. To enable whitening, write the initialization word specified in the Bluetooth standard to the WHITE_CONTROL register. To disable, write all zeros to the same register. There is no status information available for the whitening/de-whitening unit.

16.3.1.3.4 FEC Coding/Decoding

The forward error correction (FEC) is a standard block encoder/decoder algorithm. Two forms of FEC are used in the Bluetooth standard:

• 1/3 FEC: Repeating each bit so that each bit occurs three times in a row. Simple majority decision is used in decoding—that is, if two or more bits are equal, the value of these bits is used.

• 2/3 FEC: Using a (15, 10) shortened Hamming code with a minimum distance of 4. This encoding allows correction of one-bit errors and detection of two-bit errors. For each block of 10 bits, 5 redundant bits are appended. In the receive decoding, the BTA checks each 15 bit block for errors and sets the REC2 and NREC flags in the status register accordingly.

FEC can be enabled or disabled by software according to the packet type.

16.3.1.4 Bit Buffer

The bit buffer is a 512-bit memory bank used for four different purposes. It is software accessible, and is arranged as eight 64-bit “long words,” designated

LW0

through

LW7

. Software views each long word as four concatenated 16 bit words that are accessed independently. Figure 16-4 illustrates the arrangement of the long words in the bit buffer.

MOTOROLA

Bluetooth Accelerator (BTA)

16-11

Bluetooth Accelerator (BTA)

Bit 63 Bit 0

Bit 127

Bit 191

Bit 255

Bit 319

Bit 383

Bit 447

Bit 511

Word 3 (16 bits)

Word 7 (16 bits)

Word 11 (16 bits)

Word 15 (16 bits)

Word 19 (16 bits)

Word 23 (16 bits)

Word 27 (16 bits)

Word 31 (16 bits)

LW0 (64 Bits)

Word 2 (16 bits) Word 1 (16 bits)

LW1 (64 Bits)

Word 6 (16 bits) Word 5(16 bits)

LW2 (64 Bits)

Word 10 (16 bits) Word 9 (16 bits)

LW3 (64 Bits)

Word 14 (16 bits) Word 13 (16 bits)

LW4 (64 Bits)

Word 18 (16 bits) Word 17 (16 bits)

LW5 (64 Bits)

Word 22 (16 bits) Word 21 (16 bits)

LW6 (64 Bits)

Word 26 (16 bits) Word 25 (16 bits)

LW7 (64 Bits)

Word 30 (16 bits) Word 29 (16 bits)

Word 0 (16 bits)

Word 4 (16 bits)

Word 8 (16 bits)

Word 12 (16 bits)

Word 16 (16 bits)

Word 20 (16 bits)

Word 24 (16 bits)

Word 28 (16 bits)

Bit 64

Bit 128

Bit 192

Bit 256

Bit 320

Bit 384

Bit 448

Figure 16-4. BitBuf Memory

The BTA uses time sharing to minimize the amount of hardware required. Time sharing of the bit buffer is feasible because the functions requiring the module are active at different times during a receive or transmit function. Table 16-6 lists the uses of the bit buffer and the number of bits used for each function.

The order is chosen so that the first function in the table function is the first in time to be executed.

Table 16-6. Functions Using the Bit Buffer

Function

Encryption initialization

Correlation

Receive

Transmit

Buffer Size (Bits) Transmit Receive

128

512

512

512

Used

Not used

Not used

Used

Used

Used

Used

Not used

Users must never access the contents of the bit buffer during the encryption initialization or correlation phases.

16.3.1.5 Correlator

The correlator performs correlation using eight times oversampling of the incoming bit stream to extract the bit timing information and correlates against the 64-bit access code. The access code is written by software to BTA registers SYNCH_WORD_0, SYNCH_WORD_1, SYNCH_WORD_2, and

SYNCH_WORD_3.

The threshold for the correlator is programmable via the THRESHOLD register. The correlation peak value in the most recent correlation window can be read from the same register.

Software access to the bit buffer is prohibited during correlation because of the bit buffer time sharing (see section 16.3.1.4).

16-12

MC9328MX1 Reference Manual

MOTOROLA

Module Descriptions

16.3.1.6 Bluetooth Application Timer

The Bluetooth core includes a 12-bit Bluetooth Application Timer (BAT) that can be configured to generate periodic interrupts. The BAT is programmable via the Bluetooth Application Timer Register

(BAT). When the software writes a value to the BAT register, the timer is initialized to this value.

The BAT is clocked with the 8 MHz clock and is decremented by one at each clock tick. When the timer expires, a “BTtim” interrupt is generated and the counter is automatically reloaded with the value written to the BAT register.

The “BTtim” interrupt can be masked via the ENABLE bit of the BAT register.

16.3.1.7 Hop Selection Co-Processor

The frequency selection scheme of the Bluetooth system consists of two parts:

• Sequence Selection

• Mapping of this sequence on the hop frequencies and the RF module frequency synthesizer programming

The hop selection co-processor is used to perform part of the computation that selects the hop frequency according to the Bluetooth specifications. Software must complete the addition of

F

(specified in the

Bluetooth specifications) and must also perform the modulo operation.

The selection is initiated by writing to the

HOP0 to HOP4 registers. Once the selection has been initiated, software can read the result back from the HOP_FREQ_OUT register. The software must then complete the sequence selection computation and map the selected channel to RF module frequency synthesizer programming parameters.

The sequence to be written into the co-processor is as shown in Table 16-7.

Table 16-7. Hop Selection Co-Processor Writing Sequence

Register Description Register Name Bits Notes

Hop 0 (Frequency In) Register

Hop 1 (Frequency In) Register

Hop 2 (Frequency In) Register

Hop 3 (Frequency In) Register

Hop 4 (Frequency In) Register

HOP0

HOP1

HOP2

HOP3

HOP4

CLK_LOW

CLK_HIGH

LAPUAP_LOW

LAPUAP_HIGH

SYS, STATE

CLK

15-0

of the used clock

CLK

25-16

of the used clock

LAP

15-0

{UAP

3-0

, LAP

23-16

}

See Section 16.5.11.5, “Hop 4 (Frequency

In) Register,” on page 16-84

16.3.1.8 Radio Control

The radio interface supports two RF front ends:

• Motorola Radio, MC13180, SPI Interface

• SiliconWave Radio, SiW1502, SPI Interface

The selection of the used interface is determined via software by writing to the RF_CONTROL register.

Table 16-8 on page 16-14 describes the interface of the Bluetooth pins to each of the RF front ends. Some pins are configurable as inputs and outputs, depending on which radio module is used. The reset values are shown for the output configurations.

MOTOROLA

Bluetooth Accelerator (BTA)

16-13

Bluetooth Accelerator (BTA)

Table 16-8. Bluetooth Pin Mapping for Various Radio Interfaces

Name Direction Reset MC13180 SiW1502

BT5

BT6

BT7

BT8

BT1

BT2

BT3

BT4

IN

Tri-State Out Hi-Z

In

In

In/Out

Out

In

Low

Out Low

Tri-State Out Hi-Z

BT9

BT10

Out

Out

Low

High

BT11 Out High

BT12 Tri-State Out Hi-Z

BT13 Out Low

Ref_Clk (In: 24 MHz) Ref_Clk (In: 16 MHz)

Tx_Data TxData

Rx_Data spi_data_in

RxData

SPI_TXD

In: Frame_Synch

PWM_Tx/GPO1

Diversity/BTRFOSC

PWM_RSSI

Out: PWM_RSSI

Reset_RM

Diversity/Enable_RM

TxEN

RxTx_en

BTRFOSC/GPO2 spi_en spi_data_out spi_clk

HOP_STRB

BTRFOSC/GPO2

SPI_SS

SPI_RXD

SPI_CLK

16.3.1.8.1 Frequency Synthesizer and Timing Control

Data is written to the RF front ends through the SPI_WORD0, SPI_WORD1, SPI_WORD2,

SPI_WORD3,

SPI_READ_ADDR and SPI_WRITE_ADDR registers. These registers are primarily used to program the frequency synthesizer of the RF front-end. Depending on the RF front end used, only some of the six interface registers are required.

In addition to the data interface, the Bluetooth core includes two registers, TIME_A_B and TIME_C_D, that are used to specify the timing of control signals to the RF module. The time written to the these registers refer to the number of µs before SysTick.

16.3.1.8.2 Pulse Width Modulators

RF control includes two pulse width modulators (PWMs) used to control transmit power and to generate the Received Signal Strength Indicator (RSSI). Both PWMs are clocked by the 8 MHz clock providing a resolution of 125 ns. They share the same 6-bit PWM counter. The transmit PWM and RSSI PWM are enabled by the PWM_TX_EN and RSSI_EN bits in the RF_CONTROL register respectively. When enabled, the PWM provides a pulse resolution of 32 steps and cycle time of 8 µs. The desired transmit power is written to the PWM_TX register while the RSSI value is written to the PWM_RSSI register.

16.3.1.8.3 Radio Module Interfaces

MC13180 Radio (3 Wire SPI)

The MC13180 radio is programmed via a three wire serial programming interface (SPI) comprised of the spi_data, spi_en, and spi_clk lines.

16-14

MC9328MX1 Reference Manual

MOTOROLA

Module Descriptions

The BTA supports 16-bit SPI reads from and writes to the radio. The MC13180 radio registers are accessed via register addresses. The BTA uses “burst” writes to the MC13180 radio by requiring that only the first of up to four consecutive register addresses be specified.

Data is written to the MC13180 radio as follows:

1. Write up to four 16-bit words to the SPI_WORD0 through SPI_WORD3 registers. The data is automatically buffered by the BTA and is not written to the radio until the address is specified in step 2.

2. Write the address of the first register to the SPI_WRITE_ADDR register. Once the address has been written, the BTA writes the buffered data word(s) to the MC13180 radio one word at a time. The radio increments the address of the radio register by one after each write.

The mapping of the data written to the SPI_WORD0 through SPI_WORD3 registers in the programming sequence illustrated in Figure 16-5.

SPI_W_Addr

SPI_0

SPI_1

WRITE

don’t care

7 r/w

Address (Bits 6-0)

Word 0 (Bits 15-0)

Word 1 (Bits 15-0)

SPI_R_Addr

SPI_0

READ

don’t care

7 r/w

Address (Bits 6-0)

Word 0 (Bits 15-0)

SPI_Data

_In

SPI_Clk

SPI_EN

Low indicates write

Address Word 0 Word 1

High indicates read

SPI_Data

_In

SPI_Data

_Out

Tri-

Stated

Address

SPI_Clk

Tri-Stated

Word 0

Tri-

Stated

SPI_EN

Figure 16-5. Programming Interfaces for the MC13180 Radio

Data is read from the MC13180 radio as follows:

1. Write the address of the first MC13180 register to be read to the SPI_READ_ADDR register.

Once the address has been written, the BTA retrieves data words from the MC13180 radio.

2. Read a 16 bit words from the SPI_WORD0 register.

The software must poll for the

DONE

flag in the SPI_STATUS register before reading or writing new data from or to the SPI.

Writing to the SPI_READ_ADDR or SPI_WRITE_ADDR register overrides any previous SPI address maintained in that register by the Bluetooth core.

The timing of the MC13180 radio is shown in Figure 16-6 on page 16-16.

MOTOROLA

Bluetooth Accelerator (BTA)

16-15

Bluetooth Accelerator (BTA)

Software writes to BTA

Time B

EOF/AAO/

Idle Mode

Software writes to BTA

Time B

EOF/AAO/

Idle Mode

SPI_Data

SPI_Clk

SPI_En

RxTx_En

Tx_Data

Frame_Synch

Can be tristated, depending on the

RF_Control

register

Bluetooth packet data

Can be tristated, depending on the

RF_Control

register

Rx_Data

Bluetooth packet data

SysTick SysTick SysTick

Idle Tx Idle Rx

Figure 16-6. Timing of the RF Module Control Signals for the MC13180 Radio

SiliconWave Radio (4 Wire SPI)

The SiliconWave radio is programmed via a four-wire serial programming interface (SPI) comprised of the

SPI_TXD, SPI_RXD, SPI_CLK, /SPI_SS. The definition of the signal direction is with reference to the

Radio.

The BTA supports byte SPI reads from and writes to the radio. The SiliconWave radio registers are accessed via register addresses. The BTA uses “burst” writes to the SiliconWave radio by requiring that only the first of up to eight consecutive register addresses be specified.

Data is written to the SiliconWave radio as follows:

1. Write up to eight bytes to the SPI_WORD0 through SPI_WORD3 registers. The data is automatically buffered by the BTA and is not written to the radio until the address is specified in step 2.

2. Write the address of the first register to the SPI_WRITE_ADDR register. Once the address has been written, the BTA writes the buffered data word(s) to the SiWave radio one word at a time. The radio increments the address of the radio register by one after each write.

The mapping of the data written to the SPI_WORD0 through SPI_WORD3 registers in the programming sequence illustrated in Figure 16-7.

16-16

MC9328MX1 Reference Manual

MOTOROLA

SPI_W_Addr

SPI_0

Write

15 r/w

Command (Bit 14-8)

7

Address (Bit 7-0)

Byte 0 (Bit 15-8) Byte 1 (Bit 7-0)

SPI_1

Byte 2 (Bit 31-24)

Hig h indicates wri te

Byte 3 (Bit 23-16)

Module Descriptions

SPI_R_Addr

15 r/w

Read

7

Command (Bit 1 4-8) Address (Bit 7-0)

SPI_0

Byte 0 (Bit 15-8) Byte 1 (Bit 7-0)

Low indicates rea d

SPI_Data_In

SPI_Clk

SPI_EN

Command,

Address

Byt e 0,1

B yt e 2, 3

SPI_Data_In

SPI_Data_Out t ri-stated

SPI_Clk

SPI_EN

Command,

Address

Byte 0, 1

Figure 16-7. Programming Interface for the SiWave Radio

Data is read from the SiliconWave radio as follows:

1. Write the address of the SiliconWave register to be read to the SPI_READ_ADDR register.

After the address has been written, the BTA retrieves data bytes from the SiliconWave radio.

2. Read up to two bytes from the SPI_WORD0 register.

The software must poll for the

DONE

flag of the SPI_STATUS register before reading or writing new data from or to the SPI.

Writing to the SPI_READ_ADDR or SPI_WRITE_ADDR register overrides any previous SPI address maintained in that register by the Bluetooth core.

The timing of the SiliconWave radio is shown in Figure 16-8.

Time B D

EOF/AAO/

IdleMode

SW write to BTA

Time B

EOF/AAO/

IdleMode

SW write to BTA

SPI_RXD

(BT12)

SPI_CLK

(BT13)

/SPI_SS

(BT11)

RxTx_en

(BT9)

TxEn

(BT8)

Tx_data

( 1) Ca n be t ristated depe nding on RF_ Contro l Register

Rx_data

BT pa cket dat a

If T x_Tr i_ En =1 ( BUT BT 8 itself is n ot T RI ST AT ED

Sa me as (1)

BT packet data

Idle

SysTick

Tx

Idle

SysTick

Rx

Figure 16-8. Timing of RF Module Control Signals for the SiWave Radio

MOTOROLA

Bluetooth Accelerator (BTA)

16-17

Bluetooth Accelerator (BTA)

16.3.2 Wake-Up Module

The BTA provides a wake-up module for power saving operation. Figure 16-9 shows the block diagram of the wake-up module.

BT1clkHold

WakeUp_1 compare

WakeUp_2 compare

WU_Count

WakeUp_delta4

+

BTRFOSC

WakeUp_4 compare

Figure 16-9. Block Diagram of the Wake-Up Module

The wake-up module consists of a wake-up counter clocked by a 32 kHz clock. The counter can be reset by software by setting the

CLR_CNT

bit in the WU_CONTROL register.

Power-down timing can be programmed via three wake-up registers. When the software specifies a power-down, the wake-up counts must be set up by writing to the WAKEUP_1, WAKEUP_2, and

WAKEUP_DELTA4 registers. The power-down process is then started by writing to the

PDE

bit in the

WU_CONTROL register.

All three wake-up compare registers specify wake-up times in 31.25 µs units (31.25 µs is the reciprocal of

32 kHz). The wake-up times indicate the elapsed time from when the power-down process is started

(wake-up counter is reset upon request). The wake-up events (

WU1

,

WU2

and

WU4

) are generated when the WU_COUNT register value equals their respective wake-up compare registers.

The three wake-up compare registers are used as follows:

1. After software determines that a power-down has to be performed, the WAKEUP_1 register specifies the delay until the BTRFOSC and BT1ClkHold signals are asserted. The assertion of BTRFOSC signals a power-down request to the oscillator source. Immediately after the activation of BTRFOSC (which is synchronized with the Bluetooth master clock),

BT1ClkHold is asserted. BT1ClkHold results in a synchronized hold of the Bluetooth master clock. The actual stopping of the source clock must not happen before BT1ClkHold is asserted.

2. The WAKEUP_2 register specifies the delay until BTRFOSC is deasserted, which is the the actual wake-up event. Once the BTRFOSC signal is deasserted, the source clock must be turned on.

3. The WAKEUP_4 register holds the value at which the Bluetooth clock is enabled again

(BT1ClkHold goes high). After receiving a WU2 event, WAKEUP_4 is updated with the sum of the WU_COUNT and WAKEUP_DELTA4 registers. The WAKEUP_DELTA4 value

16-18

MC9328MX1 Reference Manual

MOTOROLA

Pin Configuration for BTA

defines the amount of time that the oscillator needs to stabilize after having been turned on by the deassertion of BTRFOSC. When the counter reaches the WAKEUP_4 value, the

BT1ClkHold signal is de asserted and the Bluetooth master clock is started.

Figure 16-10 shows the timing of the wake-up signals.

Software w rites to pow er dow n an d clea rs co unter

WU 1 W U2 W U4

Software cl ears po wer-d own e nab le, cou nter and i nterrup t

PD E

WakeUp_1

WU 1

Wak eUp_2

WU 2

About 4m s

WU_Count+Wak eUp_delta4

WU 4

BT1C lkH old

BTR FOSC

BTwui

About 1.2s

Figure 16-10. Timing of the Wake-Up Signals

After resuming from a power down the total BT power-down time is determined from the difference between the values in the WAKEUP_4 and WAKEUP_1 Registers.

The current value of the power-down counter can be read at any time from the WU_COUNT register.

An interrupt is generated at the end of the BT1ClkHold interval (on a WU4 event). In the interrupt, the

PDE bit is cleared, and the external wake-up signal source is removed.

16.4 Pin Configuration for BTA

There are 15 pins used for the BTA module. Of these, 13 pins are multiplexed with other functions on the device, and must be configured for BTA operation.

NOTE:

The user must ensure that the data direction bits in the GPIO are set to the correct direction for proper operation. See Section 32.5.1, “Data Direction

Registers,” on page 32-9 for details.

MOTOROLA

Bluetooth Accelerator (BTA)

16-19

Bluetooth Accelerator (BTA)

Table 16-9. Pin Configuration

Configuration Procedure Pin Setting

BT1 Primary function of

GPIO Port C [31]

BT2 Primary function of

GPIO Port C [30]

1. Clear bit 31 of Port C GPIO In Use Register (GIUS_C)

2. Clear bit 31 of Port C General Purpose Register (GPR_C)

1. Clear bit 30 of Port C GPIO In Use Register (GIUS_C)

2. Clear bit 30 of Port C General Purpose Register (GPR_C)

BT3 Primary function of

GPIO Port C [29]

BT4 Primary function of

GPIO Port C [28]

1. Clear bit 29 of Port C GPIO In Use Register (GIUS_C)

2. Clear bit 29 of Port C General Purpose Register (GPR_C)

1. Clear bit 28 of Port C GPIO In Use Register (GIUS_C)

2. Clear bit 28 of Port C General Purpose Register (GPR_C)

BT5 Primary function of

GPIO Port C [27]

BT6 Primary function of

GPIO Port C [26]

1. Clear bit 27 of Port C GPIO In Use Register (GIUS_C)

2. Clear bit 27 of Port C General Purpose Register (GPR_C)

1. Clear bit 26 of Port C GPIO In Use Register (GIUS_C)

2. Clear bit 26 of Port C General Purpose Register (GPR_C)

BT7 Primary function of

GPIO Port C [25]

BT8 Primary function of

GPIO Port C [24]

1. Clear bit 25 of Port C GPIO In Use Register (GIUS_C)

2. Clear bit 25 of Port C General Purpose Register (GPR_C)

1. Clear bit 24 of Port C GPIO In Use Register (GIUS_C)

2. Clear bit 24 of Port C General Purpose Register (GPR_C)

BT9 Primary function of

GPIO Port C [23]

BT10 Primary function of

GPIO Port C [22]

1. Clear bit 23 of Port C GPIO In Use Register (GIUS_C)

2. Clear bit 23 of Port C General Purpose Register (GPR_C)

1. Clear bit 22 of Port C GPIO In Use Register (GIUS_C)

2. Clear bit 22 of Port C General Purpose Register (GPR_C)

BT11 Primary function of

GPIO Port C [21]

BT12 Primary function of

GPIO Port C [20]

1. Clear bit 21 of Port C GPIO In Use Register (GIUS_C)

2. Clear bit 21 of Port C General Purpose Register (GPR_C)

1. Clear bit 20 of Port C GPIO In Use Register (GIUS_C)

2. Clear bit 20 of Port C General Purpose Register (GPR_C)

BT13 Primary function of

GPIO Port C [19]

1. Clear bit 19 of Port C GPIO In Use Register (GIUS_C)

2. Clear bit 19 of Port C General Purpose Register (GPR_C)

16.5 Programming Model

The BTA module includes 93 user-accessible 32-bit registers. Only the lower 16 bits (bits 0-15) are used in each register. For the Bluetooth Accelerator, the register behavior may change between write and read functions. For clarification, when the behavior changes significantly, the same address is given two different names. Table 16-10 on page 16-21 summarizes these registers and their addresses. Table 16-11 on page 16-23 provides an alternate view of the memory map

.

16-20

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Command Register

Status Register

Packet Header Register

Payload Header Register

Native Count Register

Estimated Count Register

Offset Count Register

Native Clock Low Register

Native Clock High Register

Estimated Clock Low Register

Estimated Clock High Register

Offset Clock Low Register

Offset Clock High Register

HECCRC Control Register

White Control Register

Encryption Control X13 Register

Correlation Time Setup Register

Correlation Time Stamp Register

RF GPO Register

PWM Received Signal Strength

Indicator Register

Time A & B Register

Time C & D Register

PWM TX Register

RF Control Register

RF Status Register

RX Time Register

TX Time Register

Bluetooth Application Timer Register

Threshold Register

Table 16-10. BTA Module Register Memory Map

Description Name Address Read/Write

COMMAND

STATUS

PACKET_HEADER

PAYLOAD_HEADER

NATIVE_COUNT

ESTIMATED_COUNT

OFFSET_COUNT

NATIVECLK_LOW

0x00216000

0x00216000

Write

Read

0x00216004 Write/Read

0x00216008 Write/Read

0x0021600C Write/Read

0x00216010 Write/Read

0x00216014 Write/Read

0x00216018 Write/Read

NATIVECLK_HIGH

ESTIMATED_CLK_LOW

ESTIMATED_CLK_HIGH

OFFSET_CLK_LOW

0x0021601C Write/Read

0x00216020 Write/Read

0x00216024 Write/Read

0x00216028 Write/Read

OFFSET_CLK_HIGH

HECCRC_CONTROL

0x0021602C Write/Read

0x00216030 Write

WHITE_CONTROL 0x00216034

ENCRYPTION_CONTROL_X13 0x00216038

Write

Write

CORRELATION_TIME_SETUP 0x00216040

CORRELATION_TIME_STAMP 0x00216040

RF_GPO

PWM_RSSI

0x00216048

Write

Read

Write

0x0021604C Write/Read

TIME_A_B

TIME_C_D

PWM_TX

RF_CONTROL

RF_STATUS

RX_TIME

TX_TIME

BAT

THRESHOLD

0x00216050

0x00216054

0x00216058

0x0021605C

0x0021605C

0x00216060

0x00216064

0x00216068

0x0021606C

Write

Write

Write

Write

Read

Write

Write

Write

Write

MOTOROLA

Bluetooth Accelerator (BTA)

16-21

Bluetooth Accelerator (BTA)

Table 16-10. BTA Module Register Memory Map (Continued)

Description Name Address

Correlation Max Register

Synch Word 0 Register

Synch Word 1 Register

Synch Word 2 Register

Synch Word 3 Register

Buf Word 0 (LW0) Register

Buf Word 1 (LW0) Register

Buf Word 2 (LW0) Register

CORRELATION_MAX

SYNCH_WORD_0

SYNCH_WORD_1

SYNCH_WORD_2

SYNCH_WORD_3

BUF_WORD_0 (LW0)

BUF_WORD_1 (LW0)

BUF_WORD_2 (LW0)

Read/Write

0x0021606C

0x00216070

0x00216074

0x00216078

Read

Write

Write

Write

0x0021607C Write

0x00216080 Write/Read

0x00216084 Write/Read

0x00216088 Write/Read

Buf Word 29 (LW7) Register

Buf Word 30 (LW7) Register

Buf Word 31 (LW7) Register

Wake-Up 1 Register

Wake-Up 2 Register

Wake-Up Delta4 Register

Wake-Up 4 Register

WakeUp Control Register

Wake-Up Status Register

Wake-Up Count Register

Clock Control Register

SPI Word0 Register

SPI Word1 Register

SPI Word2 Register

SPI Word3 Register

SPI Write Address Register

SPI Read Address Register

SPI Control Register

SPI Status Register

Hop 0 (Frequency In) Register

BUF_WORD_29 (LW7)

BUF_WORD_30 (LW7)

BUF_WORD_31 (LW7)

WAKEUP_1

WAKEUP_2

WAKEUP_DELTA4

WAKEUP_4

WU_CONTROL

WU_STATUS

WU_COUNT

CLK_CONTROL

SPI_WORD0

SPI_WORD1

SPI_WORD2

SPI_WORD3

SPI_WRITE_ADDR

SPI_READ_ADDR

SPI_CONTROL

SPI_STATUS

HOP0

0x002160F4 Write/Read

0x002160F8 Write/Read

0x002160FC Write/Read

0x00216100 Write/Read

0x00216104 Write/Read

0x0021610C

0x0021610C

Write

Read

0x00216110

0x00216110

Write

Read

0x00216114 Read

0x00216118 Write/Read

0x00216120 Write/Read

0x00216124 Write

0x00216128

0x0021612C

Write

Write

0x00216130

0x00216134

0x00216138

0x00216138

0x00216140

Write

Write

Write

Read

Write

16-22

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Table 16-10. BTA Module Register Memory Map (Continued)

Description Name Address

Hop Frequency Out Register

Hop 1 (Frequency In) Register

Hop 2 (Frequency In) Register

Hop 3 (Frequency In) Register

Hop 4 (Frequency In) Register

Interrupt Vector Register

Synchronization Metric Register

Synchronize Frequency Carrier Register

Word Reverse Register

Byte Reverse Register

HOP_FREQ_OUT

HOP1

HOP2

HOP3

HOP4

INTERRUPT_VECTOR

SYNC_METRIC

SYNC_FC

WORD_REVERSE

BYTE_REVERSE

Read/Write

0x00216140

0x00216144

0x00216148

0x0021614C

Read

Write

Write

Write

0x00216150 Write

0x00216160 Write/Read

0x00216170

0x00216174

Read

Read

0x00216178 Write/Read

0x0021617C Write/Read

Table 16-11. BTA Module Register Overview

Functional

Unit

Address Read

Sequencer 0x00216000

0x00216004

Bluetooth

Clocks

0x00216008

0x0021600C

0x00216010

0x00216014

Bluetooth

Pipeline

COMMAND

PACKET_HEADER

PAYLOAD_HEADER

NATIVE_COUNT

0x00216018

0x0021601C

0x00216020

0x00216024

0x00216028

0x0021602C

0x00216030

0x00216034

ESTIMATED_COUNT

OFFSET_COUNT

NATIVECLK_LOW

NATIVECLK_HIGH

ESTIMATED_CLK_LOW

ESTIMATED_CLK_HIGH

OFFSET_CLK_LOW

OFFSET_CLK_HIGH

HECCRC_CONTROL

WHITE_CONTROL

0x00216038 ENCRYPTION_CONTROL_X13

Write

STATUS

PACKET_HEADER

PAYLOAD_HEADER

NATIVE_COUNT

ESTIMATED_COUNT

OFFSET_COUNT

NATIVECLK_LOW

NATIVECLK_HIGH

ESTIMATED_CLK_LOW

ESTIMATED_CLK_HIGH

OFFSET_CLK_LOW

OFFSET_CLK_HIGH

MOTOROLA

Bluetooth Accelerator (BTA)

16-23

Bluetooth Accelerator (BTA)

Table 16-11. BTA Module Register Overview (Continued)

Functional

Unit

Address Read

Radio

Control

0x00216060

0x00216064

Timer 0x00216068

Correlator 0x0021606C

0x00216070

0x00216074

0x00216078

0x0021607C

Bit

Buffer

0x00216040 CORRELATION_TIME_SETUP

0x00216048

0x0021604C

RF_GPO

PWM_RSSI

0x00216050

0x00216054

0x00216058

0x0021605C

TIME_A_B

TIME_C_D

PWM_TX

RF_CONTROL

0x00216080

0x00216084

0x00216088

RX_TIME

TX_TIME

BAT

THRESHOLD

SYNCH_WORD_0

SYNCH_WORD_1

SYNCH_WORD_2

SYNCH_WORD_3

BUF_WORD_0 (LW0)

BUF_WORD_1 (LW0)

BUF_WORD_2 (LW0)

Write

CORRELATION_TIME_STAMP

PWM_RSSI

RF_STATUS

CORRELATION_MAX

BUF_WORD_0 (LW0)

BUF_WORD_1 (LW0)

BUF_WORD_2 (LW0)

Wake-Up

System

0x002160F4

0x002160F8

0x002160FC

0x00216100

0x00216104

0x0021610C

0x00216110

0x00216114

0x00216118

BUF_WORD_29 (LW7)

BUF_WORD_30 (LW7)

BUF_WORD_31 (LW7)

WAKEUP_1

WAKEUP_2

WAKEUP_DELTA4

WU_CONTROL

CLK_CONTROL

BUF_WORD_29 (LW7)

BUF_WORD_30 (LW7)

BUF_WORD_31 (LW7)

WAKEUP_1

WAKEUP_2

WAKEUP_4

WU_STATUS

WU_COUNT

CLK_CONTROL

16-24

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Table 16-11. BTA Module Register Overview (Continued)

Functional

Unit

Address

SPI 0x00216120

0x00216124

0x00216128

0x0021612C

0x00216130

0x00216134

0x00216138

Frequency

Hopping

Interrupt

Joint

Detection

0x00216140

0x00216144

0x00216148

0x0021614C

0x00216150

0x00216160

0x00216170

0x00216174

Reversing 0x00216178

0x0021617C

Read

SPI_WORD0

SPI_WORD1

SPI_WORD2

SPI_WORD3

SPI_WRITE_ADDR

SPI_READ_ADDR

SPI_CONTROL

HOP0

HOP1

HOP2

HOP3

HOP4

INTERRUPT_VECTOR

WORD_REVERSE

BYTE_REVERSE

Write

SPI_WORD0

SPI_STATUS

HOP_FREQ_OUT

INTERRUPT_VECTOR

SYNC_METRIC

SYNC_FC

WORD_REVERSE

BYTE_REVERSE

MOTOROLA

Bluetooth Accelerator (BTA)

16-25

Bluetooth Accelerator (BTA)

16.5.1 Sequencer Registers

Three addresses correlate to sequencing functions. The Command Register and Status Register are write and read registers associated with one address.

16.5.1.1 Command Register

The write-only Command Register controls the BTA functions such as enabling or disabling interrupts, controlling the Bluetooth pipeline, and setting the correlation window size.

Reading address 0x00216000 returns the Status Register (see section 16.5.1.2). The Command Register bits and their settings are described in Table 16-12 on page 16-26.

COMMAND

BIT 31 30 29 28 27

Command Register

26 25 24 23 22 21 20 19

Addr

0x00216000

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15

AAO w

0

14

EHI w

0

13 12

EFI PIPE w

0 w

0

11 r

0

10 r

0

9 r

0

8 7 r

0

0x0004 r

0

6 5

OS CWS w

0 w

0

4 r

0

3

IDP w

0

2

MS w

1

1 0 w

0

CMD w

0

Name

Reserved

Bits 31–16

AAO

Bit 15

EHI

Bit 14

EFI

Bit 13

PIPE

Bit 12

Table 16-12. Command Register Description

Description

Reserved—These bits are reserved and should read 0.

Settings

Abort All Operations

—Indicates that the BTA must abort the current process. For example, when the software detects that the packet is not addressed to the unit, it aborts the reception. AAO initializes the FSM in the BTA and must always be 1 whenever a

CMD is given.

0 = Do not abort

1 = Abort

Enable End-of-Header Interrupt

—Enables/Disables the

End-of-Header interrupt during packet reception.

0 = Disable EHI interrupt

1 = Enable EHI interrupt

Enable End-of-Frame Interrupt

—Enables/Disables the

End-of-Frame interrupt during packet reception and transmission.

Bluetooth Pipeline Processing Control

—Determines whether to bypass the Bluetooth pipeline module. When bypass is selected (PIPE is set), data flows directly between the Bit Buffer and the RF sub-modules.

0 = Disable EFI interrupt

1 = Enable EFI interrupt

0 = Bluetooth pipeline enabled

1 = Bypass Bluetooth pipeline after the header trailer bits

16-26

MC9328MX1 Reference Manual

MOTOROLA

Reserved—These bits are reserved and should read 0.

Programming Model

Table 16-12. Command Register Description (Continued)

Description Settings Name

Reserved

Bits 11–7

OS

Bit 6

CWS

Bit 5

Reserved

Bit 4

IDP

Bit 3

Override ESTIMATEDCLK 2 LSBs

—Overrides the two least significant bits of the ESTIMATEDCLK when a trigger is received by the unit operating as a slave during synchronization.

0 = Preset the two LSBs to 00

1 = Do not preset the two LSBs

Correlation Window Size

—Selects the correlation window size.

When window search is selected (CWS is cleared), the window size is controlled by the TX_TIME and RX_TIME Registers. (see section 16.5.4.10 and 16.5.4.11 respectively for details).

0 = Window search

1 = Continuous search

Reserved—This bit is reserved and should read 0.

MS

Bit 2

CMD

Bits 1–0

ID Packet

—Indicates that the packet to transmit is an ID packet

(as specified in the Bluetooth specification) that contains only the access code.

0 = Non ID packet type

1 = ID packet type

NATIVECLK/ESTIMATEDCLK Selection

—Determines which of the two clocks maintained by the Bluetooth core is used as

SYSTICK.

0 = ESTIMATEDCLK

1 = NATIVECLK

Command

—Determines the BTA’s mode of operation.

00 = Idle

01 = Receive

10 = Transmit

11 = Continuous Rx/Tx test mode

16.5.1.2 Status Register

The read-only Status Register returns status information about the BTA, including the lower two bits of the

Bluetooth clock, information about FEC and CRC errors, the current operating state of the BTA and the long word bit buffer currently used by the BTA. The Status Register bits and their settings are described in

Table 16-13 on page 16-28.

STATUS

BIT 31 30 29 28 27

Status Register

26 25

Addr

0x00216000

24 23 22 21 20 19 18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 14

MS2LSB r

0 r

0

13 12 11 10 9

REC1 REC2 NREC CRC16 HEC8 r

0 r

0 r

0 r

0 r

0

0x0040

8 r

0

7 r

0

6

MS r

1 r

0

5 4

STATE

3 r

0 r

0 r

0

2 1

BUF_ADDR

0 r

0 r

0

MOTOROLA

Bluetooth Accelerator (BTA)

16-27

Bluetooth Accelerator (BTA)

Table 16-13. Status Register Description

Description Settings Name

Reserved

Bits 31–16

MS2LSB

Bits 15–14

REC1

Bit 13

Reserved—These bits are reserved and should read 0.

2 LSBs of the Current Bluetooth Clock

—Returns the 2 LSB bits of the current Bluetooth clock

(NATIVECLK or ESTIMATEDCLK).

Recoverable 1/3 FEC Check

a 1/3 FEC was performed.

—Indicates that

Note:

Although all 1/3 FEC errors are

“recoverable,” the decoded bit may be incorrect.

0 = No correction made

1 = Correction made

REC2

Bit 12

NREC

Bit 11

CRC16

Bit 10

HEC8

Bit 9

Reserved

Bits 8–7

MS

Bit 6

Recoverable 2/3 FEC Check

—Indicates that a correctable 1-bit error occurred.

Non-Recoverable Error in 2/3

FEC

—Indicates that a non-recoverable 2/3

FEC (more than 1-bit error) occurred.

Payload CRC Error

—Indicates an error in the payload CRC checksum.

Packet Header HEC Error

—Indicates an error in packet HEC checking.

0 = No correctable error

1 = Correctable error

0 = No unrecoverable error

1 = Unrecoverable error

0 = No CRC error

1 = CRC error

0 = No HEC error

1 = HEC error

Reserved—These bits are reserved and should read 0.

STATE

Bits 5–3

NATIVECLK/ESTIMATEDCLK

—Indicates which of the two clocks maintained by the

Bluetooth core is used as SYSTICK.

Operating State of the BTA

—Reflects the current operating state of the BTA.

0 = ESTIMATEDCLK

1 = NATIVECLK

000 = Idle state

001 = Standby for receive state

010 = Correlation phase in the receive state

011 = Receiving data in the receive state

100 = Standby for transmit state

101 = Transmitting preamble in the transmit state

110 = Transmitting data in the transmit state

111 = Reserved

BUF_ADDR

Bits 2–0

Pointer to Long Word Bit Buffer

—Points to the long word bit buffer for data reading. The software can read any long word in the bit buffer up to (but not including) the long word currently used by the

BTA. (It can read up to BUF_ADDR-1) The software must keep track of the last long word accessed.

16-28

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.1.3 Packet Header Register

The Packet Header Register is used for both receiving and transmitting. During a read, the Packet Header

Register contains the 10-bit packet header of the most recently received Bluetooth packet. When written to, the Packet Header Register specifies the 10-bit packet header of the Bluetooth packet to transmit. The

Packet Header Register bits and their settings are described in Table 16-14.

PACKET_HEADER

BIT 31 30 29 28 27

Packet Header Register

26 25 24 23 22 21 20 19

Addr

0x00216004

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET r

0

Name

Reserved

Bits 31–10

SEQN

Bit 9

ARQN

Bit 8

FLOW

Bit 7

TYPE

Bits 6–3

AM_ADDR

Bits 2–0

15 14 r

0

13 r

0

12 r

0

11 r

0 r

0

10 9 8 7

SEQN ARQN FLOW rw

0 rw

0 rw

0

0x0000

6 rw

0 rw

0

5

TYPE

4 rw

0

Table 16-14. Packet Header Register Description

Description

Reserved—These bits are reserved and should read 0.

3 rw

0 rw

0

2 1

AM_ADDR

0 rw

0 rw

0

SEQN

—Defined in the Bluetooth header standard.

ARQN

—Defined in the Bluetooth header standard.

FLOW

—Defined in the Bluetooth header standard.

TYPE

—Defined in the Bluetooth header standard.

AM_Addr

—Defined in the Bluetooth header standard.

MOTOROLA

Bluetooth Accelerator (BTA)

16-29

Bluetooth Accelerator (BTA)

16.5.1.4 Payload Header Register

The Payload Header Register is used for both receiving and transmitting. When read, the Payload Header

Register contains the 8- or 12-bit packet header of the most recently received Bluetooth packet. When written to, the Payload Header Register specifies the 8- or 12-bit packet header of the Bluetooth packet to transmit. The Payload Header Register bits and their settings are described in Table 16-15.

PAYLOAD_HEADER

BIT 31 30 29 28 27

Payload Header Register

26 25 24 23 22 21 20 19 18

Addr

0x00216008

17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–12

LENGTH

Bits 11–3

FLOW

Bit 2

L_CH

Bits 1–0 r

0

15 14 13 12 r

0 r

0 r

0

11 10 rw

0 rw

0

9 rw

0 rw

0

8 7

LENGTH

6 rw

0

0x0000 rw

0

5 rw

0

4 3 rw

0 rw

0

2

FLOW rw

0 rw

0

1

L_CH

0 rw

0

Table 16-15. Payload Header Register Description

Description

Reserved—These bits are reserved and should read 0.

Payload Length

—Contains a 5- or 9-bit payload length determined by packet type.

Flow

—Defined in the Bluetooth standard.

Logical Channel

—Defined in the Bluetooth standard.

16-30

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.2 Bluetooth Clocks Registers

Nine registers have Bluetooth clocking functions.

16.5.2.1 Native Count Register

The Native Count Register contains a high resolution counter that generates the NATIVECLK by dividing the 8 MHz clock by 2,500 to generate a 3.2 kHz SYSTICK that updates the NATIVECLK registers. The

Native Count Register field is described in Table 16-16.

NATIVE_COUNT

BIT 31 30 29 28 27

Native Count Register

26 25 24 23 22 21 20 19

Addr

0x0021600C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 rw

0

10 rw

0

9 rw

0

8 rw

0

0x0000 rw

0

7 6 5

NATIVE_COUNT

4 rw

0 rw

0 rw

0

3 rw

0

2 rw

0

1 rw

0

0 rw

0

Table 16-16. Native Count Register Description

Description Name

Reserved

Bits 31–12

Reserved—These bits are reserved and should read 0.

NATIVE_COUNT

Bits 11–0

Native Count

—Contains the NATIVECOUNT counter, which divides the high precision 8 MHz clock to generate the 3.2 kHz SYSTICK.

MOTOROLA

Bluetooth Accelerator (BTA)

16-31

Bluetooth Accelerator (BTA)

16.5.2.2 Estimated Count Register

The Estimated Count Register contains the high resolution counter that generates the ESTIMATEDCLK by dividing the 8 MHz clock by 2,500 to generate a 3.2 kHz SYSTICK that updates the ESTIMATEDCLK registers. The Estimated Count Register bits are defined in Table 16-17.

ESTIMATED_COUNT

BIT 31 30 29 28 27

Estimated Count Register

26 25 24 23 22 21 20 19

Addr

0x00216010

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 rw

0

10 rw

0

9 rw

0

8 rw

0

0x0004 rw

0

7 6 5 4

ESTIMATED_COUNT rw

0 rw

0 rw

0

3 rw

0

2 rw

1

1 rw

0

Table 16-17. Estimated Count Register Description

Description Name

Reserved

Bits 31–12

Reserved—These bits are reserved and should read 0.

ESTIMATED_COUNT

Bits 11–0

ESTIMATEDCOUNT

—Contains the ESTIMATEDCOUNT counter, which is clocked by the high precision 8 MHz clock and preset by the access code triggering.

0 rw

0

16-32

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.2.3 Offset Count Register

The Offset Count Register contains a high resolution counter that generates OFFSETCLK by dividing the

8 MHz clock by 2,500 to generate a 3.2 kHz SYSTICK that updates the OFFSETCLK registers. The Offset

Count Register bits are described in Table 16-18.

OFFSET_COUNT

BIT 31 30 29 28 27

Offset Count Register

26 25 24 23 22 21 20 19

Addr

0x00216014

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

Name

Reserved

Bits 31–12

OFFSET_COUNT

Bits 11–0

14 r

0

13 r

0

12 r

0

11 rw

0

10 rw

0

9 rw

0

8 rw

0

0x0000 rw

0

7 6 5

OFFSET_COUNT

4 rw

0 rw

0 rw

0

Table 16-18. Offset Count Register Description

Description

Reserved—These bits are reserved and should read 0.

3 rw

0

2 rw

0

Off Set Count

—Contains the OFFSETCOUNT, which generates OFFSETCLK.

1 rw

0

0 rw

0

MOTOROLA

Bluetooth Accelerator (BTA)

16-33

Bluetooth Accelerator (BTA)

16.5.2.4 Native Clock Low Register

The Native Clock Low Register concatenated with the Native Clock High Register (see section 16.5.2.5) comprise the free-running Bluetooth NATIVECLK. The Native Clock Low Register contains the 16 least significant bits (LSB) of the 28-bit NATIVECLK.

Writing to the Offset Clock Low Register and the Offset Clock High Register updates ESTIMATEDCLK with the sum of NATIVECLK and OFFSETCLK on the next NATIVECLK tick.

The Native Clock Low Register bits are described in Table 16-19.

NATIVECLK_LOW

BIT 31 30 29 28 27

Native Clock Low Register

26 25 24 23 22 21 20 19

Addr

0x00216018

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0 rw

0

9 8 7

NATIVECLK_LOW

6 rw

0 rw

0 rw

0

0x0000

5 rw

0

4 rw

0

3 rw

0

2 rw

0

Table 16-19. Native Clock Low Register Description

Description Name

Reserved

Bits 31–16

Reserved—These bits are reserved and should read 0.

NATIVECLK_LOW

Bits 15–0

Lower Two Bytes of the NATIVECLK

—Contains the LSB (bits 15–0) of the 28-bit

NATIVECLK.

1 rw

0

0 rw

0

16-34

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.2.5 Native Clock High Register

The Native Clock High Register concatenated with the Native Clock Low Register (see section 16.5.2.4) comprise the free-running Bluetooth NATIVECLK. The Native Clock High Register contains the 12 most significant bits (MSBs) of the 28-bit NATIVECLK.

Writing to the Offset Clock Low Register and the Offset Clock High Register updates ESTIMATEDCLK with the sum of NATIVECLK and OFFSETCLK on the next NATIVECLK tick.

The Native Clock High Register bits are described in Table 16-20.

NATIVECLK_HIGH

BIT 31 30 29 28 27

Native Clock High Register

26 25 24 23 22 21 20 19

Addr

0x0021601C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 rw

0

10 rw

0

9 rw

0

8 rw

0

0x0000 rw

0

7 6 5

NATIVECLK_HIGH

4 rw

0 rw

0 rw

0

3 rw

0

2 rw

0

1 rw

0

0

Table 16-20. Native Clock High Register Description

Description Name

Reserved

Bits 31–12

Reserved—These bits are reserved and should read 0.

NATIVECLK_HIGH

Bits 11–0

High Bits of the NATIVECLK

—Contains the MSBs (bits 27–16) of the 28-bit NATIVECLK.

rw

0

MOTOROLA

Bluetooth Accelerator (BTA)

16-35

Bluetooth Accelerator (BTA)

16.5.2.6 Estimated Clock Low Register

The Estimated Clock Low Register concatenated with the Estimated Clock High Register (see section

16.5.2.7) comprise the estimated Bluetooth clock. The Estimated Clock Low Register contains the 16 least significant bits (LSB) of the 28-bit ESTIMATEDCLK. The Estimated Clock Low Register bits are described in Table 16-21.

ESTIMATED_CLK_LOW

BIT 31 30 29 28 27

Estimated Clock Low Register

26 25 24 23 22 21 20 19

Addr

0x00216020

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0

9 8 7 6

ESTIMATED_CLK_LOW rw

0 rw

0 rw

0 rw

0

0x0005

5 rw

0

4 rw

0

3 rw

0

2 rw

1

1 rw

0

0 rw

1

Table 16-21. Estimated Clock Low Register Description

Name Description Settings

Reserved

Bits 31–16

ESTIMATED_CLK_LOW

Bits 15–0

Reserved—These bits are reserved and should read 0.

Lower 2 Bytes of the ESTIMATEDCLK

—Contains the LSB (bits 15–0) of the 28-bit

ESTIMATEDCLK.

16-36

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.2.7 Estimated Clock High Register

The Estimated Clock High Register concatenated with the Estimated Clock Low Register (see section

16.5.2.6) comprise the estimated Bluetooth clock. The Estimated Clock High Register contains the 12 most significant bits (MSBs) of the 28-bit ESTIMATEDCLK. The Estimated Clock High Register bits are described in Table 16-22.

ESTIMATED_CLK_HIGH

BIT 31 30 29 28 27

Estimated Clock High Register

26 25 24 23 22 21 20 19

Addr

0x00216024

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 rw

0

10 rw

0

9 rw

0

8 rw

0

0x0000 rw

0

7 6 5 4

ESTIMATED_CLK_HIGH rw

0 rw

0 rw

0

3 rw

0

2 rw

0

1 rw

0

Table 16-22. Estimated Clock High Register Description

Name Description

Reserved

Bits 31–12

ESTIMATED_CLK_HIGH

Bits 11–0

Reserved—These bits are reserved and should read 0.

High Bits of the ESTIMATEDCLK

—Contains the MSBs (bits 27–16) of the 28-bit

ESTIMATEDCLK.

0 rw

0

MOTOROLA

Bluetooth Accelerator (BTA)

16-37

Bluetooth Accelerator (BTA)

16.5.2.8 Offset Clock Low Register

The Offset Clock Low Register concatenated with the Offset Clock High Register (see section 16.5.2.9) comprise the difference between the native Bluetooth clock and the master Bluetooth clock. The Offset

Clock Low Register contains the 16 least significant bits (LSB) of the 28-bit OFFSETCLK. Offset Clock

Low Register bits are described in Table 16-23.

OFFSET_CLK_LOW

BIT 31 30 29 28 27

Offset Clock Low Register

26 25 24 23 22 21 20 19

Addr

0x00216028

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0 rw

0

9 8 7

OFFSET_CLK_LOW

6 rw

0 rw

0 rw

0

0x0000

5 rw

0

4 rw

0

3 rw

0

2 rw

0

1 rw

0

0 rw

0

Table 16-23. Offset Clock Low Register Description

Name Description

Reserved

Bits 31–16

Reserved—These bits are reserved and should read 0.

OFFSET_CLK_LOW

Bits 15–0

Lower 2 Bytes of OFFSETCLK

—Contains the LSB (bits 15–0) of the 28-bit OFFSETCLK.

16-38

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.2.9 Offset Clock High Register

The Offset Clock High Register concatenated with the Offset Clock Low Register (see section 16.5.2.8) comprise the difference between the native Bluetooth clock and the master Bluetooth clock. The Offset

Clock High Register contains the 12 most significant bits (MSBs) of the 28-bit OFFSETCLK. The Offset

Clock High Register bits are described in Table 16-24.

OFFSET_CLK_HIGH

BIT 31 30 29 28 27

Offset Clock High Register

26 25 24 23 22 21 20 19

Addr

0x0021602C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 rw

0

10 rw

0

9 rw

0

8 rw

0

0x0000 rw

0

7 6 5

OFFSET_CLK_HIGH

4 rw

0 rw

0 rw

0

3 rw

0

2 rw

0

1 rw

0

Table 16-24. Offset Clock High Register Description

Name Description

Reserved

Bits 31–12

OFFSET_CLK_HIGH

Bits 11–0

Reserved—These bits are reserved and should read 0.

High Bits of OFFSETCLK

—Contains the MSBs (bits 27–16) of the 28-bit OFFSETCLK.

0 rw

0

MOTOROLA

Bluetooth Accelerator (BTA)

16-39

Bluetooth Accelerator (BTA)

16.5.3 Bluetooth Pipeline Registers

Three registers control the units in the Bluetooth Pipeline.

16.5.3.1 HECCRC Control Register

The write-only HECCRC Control Register specifies the initialization word for the HEC and the CRC checksum generation. The initialization word is derived from the Bluetooth clock, as described in the

Specification of the Bluetooth System, version 1.1.

The HECCRC Control Register bits are described in

Table 16-25.

HECCRC_CONTROL

BIT 31 30 29 28 27

HECCRC Control Register

26 25 24 23 22 21 20 19

Addr

0x00216030

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 w

0

14 w

0

13 w

0

12 w

0

11 w

0

10 w

0 w

0

9 8 7

HECCRC_INIT w

0 w

0

0x0000

6 w

0

5 w

0

4 w

0

3 w

0

2 w

0

1 w

0

0 w

0

Table 16-25. HECCRC Control Register Description

Description Settings Name

Reserved

Bits 31–16

Reserved—These bits are reserved and should read 0.

HECCRC_INIT

Bits 15–0

HEC and CRC Initialization

Field

—Initializes the registers for generating the check bits for HEC and CRC.

Initialization values for the payload CRC registers. The lower byte (bits 7:0) is the same for both HEC and CRC while the upper byte (bits

15:8) is all 0s.

16-40

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.3.2 White Control Register

The write-only White Control Register writes the whitening initialization word. The whitening initialization word is derived from the master Bluetooth clock as specified in

Specification of the Bluetooth

System, version 1.1

. The White Control Register bits are described in Table 16-26.

WHITE_CONTROL

BIT 31 30 29 28 27

White Control Register

26 25 24 23 22 21 20 19

Addr

0x00216034

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7 r

0

0x0000 r

0

6 w

0

5 w

0 w

0

4 3

WHITE_INIT

2 w

0 w

0

1 w

0

Table 16-26. White Control Register Description

Description Name

Reserved

Bits 31–7

Reserved—These bits are reserved and should read 0.

WHITE_INIT

Bits 6–0

Whitening Unit Initialization Field

—Initializes the registers that generate the whitening sequence.

Settings

Initialization values for the registers that generate the whitening sequence.

0 w

0

MOTOROLA

Bluetooth Accelerator (BTA)

16-41

Bluetooth Accelerator (BTA)

16.5.3.3 Encryption Control X13 Register

The write-only Encryption Control X13 Register sets up the encryption key and enables encryption.

Thirteen values are written to the register in a row to accomplish those functions. To disable encryption, do not write to the Encryption Control X13 Register. The Encryption Control X13 Register bits are described in Table 16-27.

ENCRYPTION_CONTROL_

X13

BIT 31 30 29 28 27 26

Encryption Control X13

Register

25 24 23 22 21 20 19

Addr

0x00216038

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 w

0

14 w

0

13 w

0

12 w

0

11 w

0

10 w

0

9 w

0

8 7

ENCRYPT w

0

0x0000 w

0

6 w

0

5 w

0

4 w

0

3 w

0

2 w

0

1 w

0

0 w

0

Name

Reserved

Bits 31–16

ENCRYPT

Bits 15–0

Table 16-27. Encryption Control X13 Register Description

Description

Reserved—These bits are reserved and should read 0.

Settings

Encryption Words

—Receives a sequence of 13 words to initialize and set up the encryption engine.

To disable encryption, do not write to this register.

16-42

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.4 Radio Control Registers

Nine addresses correlate to radio control functions. The Correlation Time Setup Register and Correlation

Time Stamp Register are write and read registers associated with one address. Similarly, the RF Control

Register and RF Status Register are write and read registers associated with one address.

16.5.4.1 Correlation Time Setup Register

The write-only Correlation Time Setup Register is used when the unit is in slave mode to adjust the synchronization with the master clock. When the unit detects a valid access code, ideally 64 µs have passed since the last master clock tick, however because of delays through the radio and other external devices, the time may not be exactly 64 µs. The Correlation Time Setup Register can be used to adjust the time slightly. Reading address 0x00216040 returns the Correlation Time Stamp Register (see section 16.5.4.2).

The Correlation Time Setup Register bits are explained in Table 16-28 on page 16-43.

CORRELATION_TIME_

SETUP

BIT 31 30 29 28

Correlation Time Setup Register

27 26 25 24 23 22 21 20 19

Addr

0x00216040

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 w

1

8 7 w

0

0x0201 w

0 w

0

6 5 4 3

EST_PRELOAD_TIME w

0 w

0 w

0

2 w

0

1 w

0

0 w

1

Table 16-28. Correlation Time Setup Register Description

Description Name

Reserved

Bits 31–10

Reserved—These bits are reserved and should read 0.

EST_PRELOAD_TIME

Bits 9–0

Set Correlation Time

—Holds the preload time value. The EST_PRELOAD_TIME value is loaded into the ESTIMATEDCLK counter when the trigger is asserted during correlation in slave mode.

MOTOROLA

Bluetooth Accelerator (BTA)

16-43

Bluetooth Accelerator (BTA)

16.5.4.2 Correlation Time Stamp Register

The read-only Correlation Time Stamp Register contains the time value when a valid access code is detected. The time refers to the count value of the current clock when the correlation peak value is detected. The count is the NATIVECOUNT when the unit is in master mode, or the ESTIMATEDCOUNT when the unit is in slave mode. The Correlation Time Stamp Register bits are explained in Table 16-29.

CORRELATION_TIME_

STAMP

BIT 31 30 29 28

Correlation Time Stamp Register

27 26 25 24 23 22 21 20 19

Addr

0x00216040

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

Name

Reserved

Bits 31–12

CORR_TIME

Bits 11–0

14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7 r

0

0x0000 r

0

6 5

CORR_TIME r

0 r

0

4 r

0

Table 16-29. Correlation Time Stamp Register Description

Description

Reserved—These bits are reserved and should read 0.

3 r

0

Get Correlation Time

—Indicates the time when the trigger was asserted.

2 1 0 r

0 r

0 r

0

16-44

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.4.3 RF GPO Register

The write-only RF GPO Register controls two general-purpose outputs in the RF interface that are generally used only in Philsar or MC13180 mode. The RF GPO Register bits are explained in Table 16-30.

RF_GPO

BIT 31 30 29 28 27 26

RF GPO Register

25 24 23 22 21 20 19 18

Addr

0x00216048

17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT 15

TYPE

RESET r

0

Name

Reserved

Bits 31–6

GPO_EN2

Bit 5

GPO_EN1

Bit 4

Reserved

Bits 3–2

GPO_DOUT2

Bit 1

GPO_DOUT1

Bit 0 r

0

14 13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7 r

0 r

0

0x0000

6 r

0

5 4

GPO_

EN2

GPO_

EN1 w

0 w

0

3 r

0

Table 16-30. RF GPO Register Description

Description

Reserved—These bits are reserved and should read 0.

2 r

0

1 0

GPO_

DOUT2

GPO_

DOUT1 w

0 w

0

Settings

GPO Enable

—Enables/Disables the general purpose output to the

BT9 pad. When disabled, the normal pin value is forced on the output pin.

0 = Disabled

1 = Enabled

GPO Enable

—Enables the general purpose output to the BT6 pad when the PWM_TX_EN in the RF_CONTROL Register is set.

0 = Disabled

1 = Enabled

Reserved—These bits are reserved and should read 0.

GPO Data Out

—Holds the data value driven out to BT9 when GPO_EN2 is set to Enabled.

GPO Data Out

—Holds the data value driven out to BT6 when GPO_EN1 is set to Enabled.

MOTOROLA

Bluetooth Accelerator (BTA)

16-45

Bluetooth Accelerator (BTA)

16.5.4.4 PWM Received Signal Strength Indicator Register

Writing to the PWM Received Signal Strength Indicator Register takes effect only when the RSSIOR bit is set in the RF Control Register.

When writing to the PWM Received Signal Strength Indicator Register, the 6-bit PWM output is forced onto the BT8 pin and can be used as a standard PWM. The value written to the PWM Received Signal

Strength Indicator Register refers to a relative power of 0 (lowest) to 31 (maximum).

Reading the PWM Received Signal Strength Indicator Register returns the value of the digitized RSSI.

This reading will either be the peak RSSI value or the current RSSI value, depending on the value of the

PEAK_HLD bit in the RF Control Register.

The PWM Received Signal Strength Indicator Register bits are explained in Table 16-31.

PWM_RSSI

BIT 31 30 29

PWM Received Signal Strength Indicator

Register

28 27 26 25 24 23 22 21 20 19

Addr

0x0021604C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT 15 14 13 12 11 10 9 8 7

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r r

0

0x0000

0

1.

Write functions are only valid for the MC13180 radio.

6 r

0

5 4 rw

1

0 rw

1

0

3 2

PWM_RSSI rw

1

0 rw

0

1

1 rw

1

0

0 rw

1

0

Table 16-31. PWM Received Signal Strength Indicator Register Description (MC13180)

Name Description

Reserved

Bits 31–6

Reserved—These bits are reserved and should read 0.

PWM_RSSI

Bits 5–0

Pulse Width Modulation Setting/Received Signal Strength Indicator

—Sets the PWM for RSSI power control for MC13180 radios. When read, returns the RSSI digitized by the BTA. The returned value will either be the peak RSSI value or the current RSSI value, depending on the value of the

PEAK_HLD bit in the RF Control Register.

16-46

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.4.5 Time A & B Register

The write-only Time A & B Register sets up the radio module timing. The timing unit (for TIME_A and

TIME_B) is expressed in “µs before the next SYSTICK.” The Time A & B Register bits are explained in

Table 16-32.

TIME_A_B

BIT 31 30 29 28 27

Time A & B Register

26 25 24 23 22 21 20 19

Addr

0x00216050

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–16

TIME_B

Bits 15–8

TIME_A

Bits 7–0

15 w

0

14 w

0

13 w

0

12 11

TIME_B w

0 w

0

10 w

0

9 w

0

8 7 w

0

0x0000 w

0

6 w

0

5 w

0

Table 16-32. Time A & B Register Description

Description

Reserved—These bits are reserved and should read 0.

w

0

4 3

TIME_A w

0

Time B

—Sets the Timing B of the signals interfacing to the RF module.

Time A

—Sets the Timing A of the signals interfacing to the RF module.

2 w

0

1 w

0

Settings

0 w

0

The timing unit is expressed in “µs before the next SYSTICK”.

MOTOROLA

Bluetooth Accelerator (BTA)

16-47

Bluetooth Accelerator (BTA)

16.5.4.6 Time C & D Register

The write-only Time C & D Register sets up radio module timing. The timing unit (for TIME_C and

TIME_D) is expressed in “µs before the next SYSTICK.” The Time C & D Register bits are explained in

Table 16-33.

TIME_C_D

BIT 31 30 29 28 27

Time C & D Register

26 25 24 23 22 21 20 19

Addr

0x00216054

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–13

TIME_D

Bits 12–8 r

0

15 14 r

0

13 r

0

12 w

0

11 10

TIME_D w

0 w

0

9 w

0

8 7 w

0

0x0000 r

0

6 r

0

5 r

0

4 w

0

3 w

0

2

TIME_C w

0

1 w

0

Table 16-33. Time C & D Register Description

Description Settings

Reserved—These bits are reserved and should read 0.

0 w

0

Time D

—Sets the timing D of the signals interfacing to the RF module.

The timing unit is expressed in “µs before the next

SYSTICK”. See Figure 16-6 on page 16-16 for more details.

Reserved—These bits are reserved and should read 0.

Reserved

Bits 7–5

TIME_C

Bits 4–0

Time C

—Sets the timing C of the signals interfacing to the RF module.

The timing unit is expressed in “µs before the next

SYSTICK”. See Figure 16-8 on page 16-17 for more details.

16-48

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.4.7 PWM TX Register

The write-only PWM TX Register controls the transmitting power of the MC13180 radio. The value written to the PWM TX Register refers to a relative transmitting power of 0 (lowest) to 31 (maximum).

The PWM TX Register bits are explained in Table 16-34.

PWM_TX

BIT 31 30 29 28 27 26

PWM TX Register

25 24 23 22 21 20 19

Addr

0x00216058

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT 15 14 13 12 11 10 9 8 7 6 5 4

TYPE

RESET

Name

Reserved

Bits 31–6

PWM_TX

Bits 5–0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 w

0

Table 16-34. PWM TX Register Description

Description

Reserved—These bits are reserved and should read 0.

w

0

Pulse Width Modulation

—Sets the PWM for transmit power control.

Note:

This applies to the MC13180 radio only.

w

0

3 2

PWM_TX w

0

1 w

0

0 w

0

MOTOROLA

Bluetooth Accelerator (BTA)

16-49

Bluetooth Accelerator (BTA)

16.5.4.8 RF Control Register

The write-only RF Control Register controls various radio parameters such as the operation of the Joint

Detect module, tri-stating of the BT2 pin, and operation of the RSSI. Reading address 0x0021605C returns the RF Status Register (see section 16.5.4.9). The RF Control Register bits are explained in Table 16-35.

RF_CONTROL

BIT 31 30 29 28

RF Control Register

27 26 25 24 23 22 21 20 19

Addr

0x0021605C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3

RSSIOR BIST XPOL

TX_TRI

_EN

CLE DIV SEL

PEAK

_HLD

RSSI

_EN

PWM_

TX_EN

BT5_OE BT1_CONT

BT11_

AUTO_

SPIKE w

0 w

0 w

0 w

1 w

0 w w

0 0 w

0 w

0

0x1005 w

0 w

0 w

0 w

0

2 1

DELAY

_HOP

_STROBE

0 w w

1 0 w

1

Name

Reserved

Bits 31–16

RSSIOR

Bit 15

Table 16-35. RF Control Register Description

Description

Reserved—These bits are reserved and should read 0.

Settings

CLE

Bit 11

DIV

Bit 10

SEL

Bit 9

BIST

Bit 14

XPOL

Bit 13

TX_TRI_EN

Bit 12

RSSI Override

—Selects normal RSSI mode, or whether the RSSI value is controlled by writing to the PWM Received Signal Strength Indicator

Register (ARM Control) and displayed on BT8.

This bit must be set for this device.

0 = Normal RSSI functionality

1 = ARM controlled PWM

BIST Mode

—Sets the JD/MLSE module in normal or BIST mode.

0 = Normal

1 = BIST mode

Rx/Tx Polarity

—Changes the polarity of the

RxData and TxData signals to the radio.

Tri-State Enable

—Enables/Disables the tri-state mode of the BT2 pin when not transmitting data.

0 = Normal

1 = Inverted

0 = Disable tri-state when not transmitting data

1 = Enable tri-state when not transmitting data

Closed Loop Enable

—Enables the closed loop for PLL.

Antenna Diversity Selection

—Selects the antenna.

0 = Tx (open loop)

1 = Rx (closed loop)

0 = Antenna 0

1 = Antenna 1

Selection

—Selects the operation (either diversity selection or oscillator enable) of BT7 pin.

0 = Oscillator enable operation

1 = Diversity selection

16-50

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Name

PEAK_HLD

Bit 8

RSSI_EN

Bit 7

PWM_TX_EN

Bit 6

BT5_OE

Bit 5

BT1_CONT

Bit 4

BT11_AUTO_SPIKE

Bit 3

Table 16-35. RF Control Register Description (Continued)

Description Settings

DELAY_HOP_STROBE

Bits 2–0

Peak Hold for the RSSI PWM

Operation

—Selects the PWM_RSSI peak hold mode. If peak hold is disabled (PEAK_HLD = 0), the RSSI will be continuously updated during data packet reception.

Enable for the PWM_RSSI

—Controls the

PWM_RSSI operation.

0 = PWM_RSSI tracks the analog

RSSI

1 = PWM_RSSI remains at last peak value

0 = Disable the RSSI PWM operation

1 = Enable the RSSI PWM operation

Enable for the PWM_TX

—Controls the PWM_TX operation.

0 = Disable the TX PWM operation

1 = Enable the TX PWM operation

Enable BT5 as an Output

—Controls the direction of the BT5 pin.

0 = BT5 is an input

1 = BT5 is an output

BT1 Continuous Output

—Controls the gating of

BT1 clock output.

0 = BT1 clock output is gated

1 = BT1 clock output is continuous

Enable Auto Spike Generation

—Controls the automatic generation of a spike on EOF.

Delay HOP Strobe

—Delays the HOP strobe on

BT9 in the SiliconWave radio.

0 = Do not generate spike on

EOF

1 = Generate spike on EOF

000 = No delay

001 = 2µs

010 = 4µs

100 = 8µs

111 = 15µs

All other settings reserved

MOTOROLA

Bluetooth Accelerator (BTA)

16-51

Bluetooth Accelerator (BTA)

16.5.4.9 RF Status Register

The read-only RF Status Register indicates the operation of the radio. Most of the bits return the value written to the RF Control Register. The RF Status Register bits are explained in Table 16-36.

RF_STATUS

BIT 31 30 29 28

RF Status Register

27 26 25 24 23 22 21 20 19

Addr

0x0021605C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r r

0 0 r

0

BIT

TYPE

RESET

15 14 13 12 11 10 9 8 7 6 5 4 3

RSSIOR BIST XPOL

TX_TRI_

EN

CLE DIV SEL

PEAK

_HLD

RSSI

_EN

PWM

_TX

_EN

BT5_OE BT1_CONT

BT11

_AUTO

_SPIKE r

0 r

0 r

0 r

1 r

0 r

0 r

0 r

0 r

0

0x1005 r

0 r

0 r

0 r

0

2 1

DELAY

_HOP

_STROBE

0 r r

1 0 r

1

Table 16-36. RF Status Register Description

Description

Reserved—These bits are reserved and should read 0.

Settings

CLE

Bit 11

DIV

Bit 10

SEL

Bit 9

Name

Reserved

Bits 31–16

RSSIOR

Bit 15

BIST

Bit 14

XPOL

Bit 13

TX_TRI_EN

Bit 12

RSSI Override

mode.

BIST Mode

—Indicates the RSSI operating

—Indicates the whether JD/MLSE module is in normal or BIST mode.

Rx/Tx Polarity

—Changes polarity of the RxData and TxData signals to the radio.

Tri-State Enable

—Indicates the setting for the tri-state control for the BT2 pin.

Closed Loop Enable

—Indicates whether closed loop for the PLL is enabled.

Antenna Diversity Selection

—Indicates the antenna currently used.

Selection

—Indicates the operation (either diversity selection or oscillator enable) of BT7 pin.

0 = Normal RSSI functionality

1 = CPU controlled PWM

0 = Normal

1 = BIST mode

0 = Normal

1 = Inverted

0 = Disable tri-state when not transmitting data

1 = Enable tri-state when not transmitting data

0 = Disable closed loop

1 = Enable closed loop

0 = Antenna 0

1 = Antenna 1

0 = Oscillator enable operation

1 = Diversity selection

16-52

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Name

PEAK_HLD

Bit 8

RSSI_EN

Bit 7

PWM_TX_EN

Bit 6

BT5_OE

Bit 5

BT1_CONT

Bit 4

BT11_AUTO_SPIKE

Bit 3

DELAY_HOP_STROBE

Bits 2–0

Table 16-36. RF Status Register Description (Continued)

Description Settings

Peak Hold for the RSSI PWM

Operation

—Indicates the mode of operation of the PWM_RSSI.

Enable for the PWM_RSSI

—Indicates whether the PWM_RSSI operation is enabled.

0 = PWM_RSSI tracks the analog

RSSI

1 = PWM_RSSI remains at last peak value

0 = Disable the RSSI PWM operation

1 = Enable the RSSI PWM operation

Enable for the PWM_TX

—Indicates whether the

PWM_TX operation is enabled.

Enable BT5 as an Output

—Controls the direction of the BT5 pad.

0 = BT5 is an input

1 = BT5 is an output

BT1 Continuous Output

—Controls the gating of

BT1 clock output.

0 = Disable the TX PWM operation

1 = Enable the TX PWM operation

Enable Auto Spike Generation

—Controls the automatic generation of a spike on EOF.

0 = BT1 clock output is gated

1 = BT1 clock output is continuous

0 = Do not generate spike on

EOF

1 = Generate spike on EOF

Delay HOP Strobe

—Delays the HOP strobe on

BT9 in the SiliconWave radio.

000 = No delay

001 = 2µs

010 = 4µs

100 = 8µs

111 = 15µs

MOTOROLA

Bluetooth Accelerator (BTA)

16-53

Bluetooth Accelerator (BTA)

16.5.4.10 RX Time Register

The write-only RX Time Register defines the receive correlation window start and stop time to the

MS_CLK. The RX Time Register bits are explained in Table 16-37.

RX_TIME

BIT 31 30 29 28 27 26

RX Time Register

25 24 23 22 21 20 19

Addr

0x00216060

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 w

0

12 11 10

RX_TIME_END w

1 w

1 w

1

9 w

1

8 7 w

0

0x1E07 r

0

6 r

0

5 r

0

4 w

0

3 2 1

RX_TIME_START w

0 w

1 w

1

0 w

1

Table 16-37. RX Time Register Description

Description Name Settings

Reserved

Bits 31–14

RX_TIME_END

Bits 13–8

Reserved—These bits are reserved and should read 0.

Correlation Stop Time

—Sets the middle 6 bits of the search window end time. The MS_CLK is a 12-bit clock that counts from 0 (0x000) to 2499 (0x9C3). The

RX_TIME_END field defines the bits x.

MS_CLK[11:0] = 101x xxxx x000.

RX_TIME_END can range from

000000 to 111000, which means the search window end time ranges from 64µs to 127µs.

Reserved—These bits are reserved and should read 0.

Reserved

Bits 7–5

RX_TIME_START

Bits 4–0

Correlation Start Time

—Sets the middle 5 bits of the search window start time. The MS_CLK is a 12-bit clock that counts from 0 (0x000) to 2499 (x9C3). The

RX_TIME_START field defines the bits x.

MS_CLK [11:0] = 1001 xxxx x000.

RX_TIME_START can range from

00000 to 11000, which means that the search window start time ranges from 288µs and 312µs.

16-54

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.4.11 TX Time Register

The write-only TX Time Register defines the transmit start time to the MS_CLK. The TX Time Register bits are explained in Table 16-38.

TX_TIME

BIT 31 30 29 28 27 26

TX Time Register

25 24 23 22 21 20 19

Addr

0x00216064

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7 r

0

0x0000 r

0

6 r

0

5 r

0

4 w

0

3 2 1

TX_TIME_START w

0 w

0 w

0

0 w

0

Table 16-38. TX Time Register Description

Description Name

Reserved

Bits 31–5

Reserved—These bits are reserved and should read 0.

TX_TIME_START

Bits 4–0

Correlation Start Time

—Sets the middle 5 bits of the correlation start time. The MS_CLK is a 12-bit clock that counts from 0 (0x000) to 2499 (x9C3). The

TX_TIME_START field defines the bits x.

MS_CLK [11:0] = 1001 xxxx x000.

Settings

TX_TIME_START can range from 00000 to 11000, which means that the search window start time ranges from 288 µs and 312 µs.

MOTOROLA

Bluetooth Accelerator (BTA)

16-55

Bluetooth Accelerator (BTA)

16.5.5 Timer Register

There is only one timer register.

16.5.5.1 Bluetooth Application Timer Register

The write-only Bluetooth Application Timer Register controls the Bluetooth Application Timer (BAT).

When enabled, this timer generates period interrupts. The Bluetooth Application Timer Register enables the BAT and sets up its period in ticks of 8 MHz.

The Bluetooth Application Timer Register bits are explained in Table 16-39.

BAT

BIT 31 30 29 28

Bluetooth Application Timer Register

27 26 25 24 23 22 21 20 19

Addr

0x00216068

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15

EN w

0

14 r

0

13 r

0

12 r

0

11 w

0

10 w

0

9 w

0

8 7 w

0

0x0000 w

0 w

0

6 5

TIMER w

0

4 w

0

3 w

0

2 w

0

Table 16-39. Bluetooth Application Timer Register Description

Description Settings

Reserved—These bits are reserved and should read 0.

1 w

0

Name

Reserved

Bits 31–16

EN

Bit 15

Reserved

Bits 14–12

TIMER

Bits 11–0

Enable Bluetooth Application Timer

—Enables/Disables the

BAT and interrupt.

Reserved—These bits are reserved and should read 0.

Timer Preset Value

—Receives the preset value written to the

Bluetooth application timer. The timer is clocked by the 8 MHz clock. An interrupt is issued after the count is reached and automatic reloading is performed.

0 = Disable timer and interrupt

1 = Enable timer and interrupt

Preset value written to the application timer

0 w

0

16-56

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.6 Correlator Registers

Five addresses pertain to correlator functions. The Threshold Register and Correlation Max Register are write and read registers associated with one address.

16.5.6.1 Threshold Register

The write-only Threshold Register determines when an access code is considered valid. When the radio receives a message, the BTA calculates the correlation between the access word written to the appropriate

Synch Word X Register (see Synch Word 0 Register (Write)) and the bits in the received message. When the correlation value exceeds the value in the Threshold Register, the access code is considered valid.

The correlation depends on the signal strength and the access code. The values written to the Threshold

Register determine the signal energy level and the threshold required to accept the access word. The signal levels and threshold values are functions of the values written to the Threshold Register. Reading address

0x0021606C returns the Correlation Max Register (see section 16.5.6.2).

The Threshold Register bits, when used with the MC13180 radio, are explained in Table 16-40. The

Threshold Register bits, when used with the SiliconWave radio, are explained in Table 16-41.

THRESHOLD

BIT 31 30 29 28

Threshold Register (MC13180)

27 26 25 24 23 22 21 20 19

Addr

0x0021606C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 w

1

0x01C2 w

1

7 6 5

THRESHOLD_II

(MC13180)

4 3 2 w

THRESHOLD (SiliconWave) w w w w

1 0 0 0 0

1

THRESHOLD_I (MC13180) w

1

0 w

0

Table 16-40. Threshold Register Description (MC13180)

Name Description

Reserved

Bits 31–8

Reserved—These bits are reserved and should read 0.

THRESHOLD_II

Bits 7–4

Signal Energy

—Sets the clipping level for the access code correlation.

THRESHOLD_I

Bits 3–0

Threshold Value

—Sets the threshold value for the access code correlation.

Settings

Default setting is 0.5625

Default setting is 1.25

MOTOROLA

Bluetooth Accelerator (BTA)

16-57

Bluetooth Accelerator (BTA)

Table 16-41. Threshold Register Description (SiliconWave)

Description Name

Reserved

Bits 31–9

THRESHOLD

Bits 8–0

Reserved—These bits are reserved and should read 0.

Threshold Value

—Sets the threshold value for the access code correlation.

Table 16-42. Signal Energy Levels and Threshold Levels

THRESHOLD_I THRESHOLD THRESHOLD_II Signal Energy

5

6

3

4

0

1

2

0.50000

0.53125

0.56250

0.59375

0.62500

0.65625

0.68750

5

6

3

4

0

1

2

0.5000

0.5625

0.6250

0.6875

0.7500

0.8125

0.8750

11

12

13

14

9

10

7

8

0.71875

0.75000

0.78125

0.81250

0.84375

0.87500

0.90625

0.93750

7

8

9

10

11

12

13

14

0.9375

1.0000

1.0625

1.1250

1.1875

1.2500

1.3125

1.3750

15 0.96875

15 1.4375

Note:

Levels vary according to the values written to the THRESHOLD_I and THRESHOLD_II fields.

16-58

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.6.2 Correlation Max Register

The read-only Correlation Max Register contains the peak correlation value that is calculated when a valid access code is detected. A value of 0 corresponds to no correlation, and a value of 511 corresponds to a perfect match. The Correlation Max Register bits are explained in Table 16-43.

CORRELATION_MAX

BIT 31 30 29 28 27

Correlation Max Register

26 25 24 23 22 21 20 19

Addr

0x0021606C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–9

VALUE

Bits 8–0 r

0

15 14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7 r

1

0x01C2 r

1

6 r

1

5 r

0

4

VALUE r

0

3 r

0

Table 16-43. Correlation Max Register Description

Description

Reserved—These bits are reserved and should read 0.

2 r

0

1 r

1

Settings

Maximum Correlation Value

—Contains the maximum correlation value during the correlation phase.

Note:

N/A in MC13180 mode.

0 r

0

MOTOROLA

Bluetooth Accelerator (BTA)

16-59

Bluetooth Accelerator (BTA)

16.5.6.3 Synch Word 0 Register

The write-only Synch Word X registers specify the access code that the correlator attempts to match. Bits

0

15 of the correct access code are written to the Synch Word 0 Register; bits 16–31 to the Synch Word 1

Register; bits 32–47 to the Synch Word 2 Register; and bits 48–63 to the Synch Word 3 Register.

Synch Word 0 Register bits are explained in Table 16-44.

SYNCH_WORD_0

BIT 31 30 29 28 27

Synch Word 0 Register

26 25 24 23 22 21 20 19

Addr

0x00216070

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 w

0

14 w

0

13 w

0

12 w

0

11 w

0

10 w

0

9 w

0 w

0

8

WORD

7

0x0000 w

0

6 w

0

5 w

0

4 w

0

3 w

0

2 w

0

1 w

0

Name

Reserved

Bits 31–16

WORD

Bits 15–0

Table 16-44. Synch Word 0 Register Description

Description

Reserved—These bits are reserved and should read 0.

Part of Synchronization Code

—Receives bits [15:0] of the 64-bit access code for the correlation.

0 w

0

16-60

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.6.4 Synch Word 1 Register

The write-only Synch Word 1 Register bits are explained in Table 16-45.

SYNCH_WORD_1

BIT 31 30 29 28 27

Synch Word 1 Register

26 25 24 23 22 21 20 19

Addr

0x00216074

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–16

WORD

Bits 15–0

15 w

0

14 w

0

13 w

0

12 w

0

11 w

0

10 w

0

9 w

0 w

0

8

WORD

7

0x0000 w

0

6 w

0

5 w

0

4

Table 16-45. Synch Word 1 Register Description

w

0

Description

Reserved—These bits are reserved and should read 0.

3 w

0

2 w

0

1 w

0

0 w

0

Part of Synchronization Code

—Receives bits [31:16] of the 64-bit access code for the correlation.

MOTOROLA

Bluetooth Accelerator (BTA)

16-61

Bluetooth Accelerator (BTA)

16.5.6.5 Synch Word 2 Register

The write-only Synch Word 2 Register bits are explained in Table 16-46.

SYNCH_WORD_2

BIT 31 30 29 28 27

Synch Word 2 Register

26 25 24 23 22 21 20 19

Addr

0x00216078

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–16

WORD

Bits 15–0

15 w

0

14 w

0

13 w

0

12 w

0

11 w

0

10 w

0

9 w

0 w

0

8

WORD

7

0x0000 w

0

6 w

0

5 w

0

4

Table 16-46. Synch Word 2 Register Description

w

0

Description

Reserved—These bits are reserved and should read 0.

3 w

0

2 w

0

1 w

0

0 w

0

Part of Synchronization Code

—Receives bits [47:32] of the 64-bit access code for the correlation.

16.5.6.6 Synch Word 3 Register

The write-only Synch Word 3 Register bits are explained in Table 16-47.

SYNCH_WORD_3

BIT 31 30 29 28 27

Synch Word 3 Register

26 25 24 23 22 21 20 19

Addr

0x0021607C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT 15 14 13 12 11 10

TYPE

RESET w

1 w

1 w

0 w

1 w

1 w

0

9 w

1 w

0

8

WORD

7

0xDA25 w

0

6 5 w

0 w

1

4 w

0

3 2 1 0 w

0 w

1 w

0 w

1

16-62

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Name

Reserved

Bits 31–16

WORD

Bits 15–0

Table 16-47. Synch Word 3 Register Description

Description

Reserved—These bits are reserved and should read 0.

Part of Synchronization Code

—Receives bits [63:48] of the 64-bit access code for the correlation.

16.5.7 Bit Buffer Registers

Thirty-two addresses correlate to bit buffer functions. The Buf Word 0 (LW0) Register through the Buf

Word 31 (LW7) Register are used as the eight long words (LW0 through LW7) in the Bit Buffer

Sub-Module. The registers access the portions of the long words shown in Figure 16-4 on page 16-12.

16.5.7.1 Buffer Word Registers

The BTA keeps track of the most recently accessed long word accessed by the BTA. The Bluetooth software polls the BTA status (BUF_ADDR bit of the Status Register) to avoid Bit Buffer overrun or underrun.

The Buf Word 0 (LW0) Register to Buf Word 31 (LW7) Register bits are explained in Table 16-48.

BUF_WORD_0 (LW0)

BUF_WORD_1 (LW0)

...

BUF_WORD_30 (LW7)

BUF_WORD_31 (LW7)

BIT 31 30 29 28 27

Buf Word 0 (LW0) Register

Buf Word 1 (LW0) Register

...

Buf Word 30 (LW7) Register

Buf Word 31 (LW7) Register

26 25 24 23 22 21 20 19

Addr

0x00216080

0x00216084

...

0x002160F8

0x002160FC

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT 15

TYPE

RESET rw

0

14 rw

0

13 rw

0

12 rw

0

11 10 rw

0 rw

0

9 rw

0

8

WORD

7 rw

0

0x0000 rw

0

6 5 rw

0 rw

0

4 rw

0

3 2 1 0 rw

0 rw

0 rw

0 rw

0

Table 16-48. Buf Word 0 (LW0) Register to Buf Word 31 (LW7) Register Description

Name

Reserved

Bits 31–16

Description

Reserved—These bits are reserved and should read 0.

MOTOROLA

Bluetooth Accelerator (BTA)

16-63

Bluetooth Accelerator (BTA)

Table 16-48. Buf Word 0 (LW0) Register to Buf Word 31 (LW7) Register Description (Continued)

Name Description

WORD

Bits 15–0

Data Word

—Contains the value read from or written to the bit buffer.

Table 16-49. Bit Buffer Registers Numbers and Addresses

BUF_

WORD_

Register

Long

Word #

5

6

3

4

0

1

2

9

10

7

8

11

LW0

LW0

LW0

LW0

LW1

LW1

LW1

LW1

LW2

LW2

LW2

LW2

Address

0x00216080

0x00216084

0x00216088

0x0021608C

0x00216090

0x00216094

0x00216098

0x0021609C

0x002160A0

0x002160A4

0x002160A8

0x002160AC

BUF_

WORD_

Register

Long

Word #

15

16

17

18

12

13

14

19

20

21

22

23

LW3

LW3

LW3

LW3

LW4

LW4

LW4

LW4

LW5

LW5

LW5

LW5

Address

0x002160B0

0x002160B4

0x002160B8

0x002160BC

0x002160C0

0x002160C4

0x002160C8

0x002160CC

0x002160D0

0x002160D4

0x002160D8

0x002160DC

BUF_

WORD_

Register

Long

Word #

27

28

29

30

31

24

25

26

LW6

LW6

LW6

LW6

LW7

LW7

LW7

LW7

Address

0x002160E0

0x002160E4

0x002160E8

0x002160EC

0x002160F0

0x002160F4

0x002160F8

0x002160FC

16-64

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.8 Wake-Up Registers

Five addresses pertain to wake-up functions. The WakeUp Control Register and Wake-Up Status Register are write and read registers associated with one address.

16.5.8.1 Wake-Up 1 Register

The Wake-Up 1 Register contains the comparator value that determines the time for the power-down event.

The Wake-Up 1 Register bits are explained in Table 16-50.

WAKEUP_1

BIT 31 30 29 28 27

Wake-Up 1 Register

26 25 24 23 22 21 20 19

Addr

0x00216100

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT 15 14 13 12 11 10 9 8 7 6 5 4

TYPE

RESET

Name

Reserved

Bits 31–2

TIME

Bits 1–0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0001 r

0 r

0 r

0

Table 16-50. Wake-Up 1 Register Description

Description

Reserved—These bits are reserved and should read 0.

r

0

Value for Wake-Up Timer 1

—Sets wake-up timer 1 for low-power operation. The timer is clocked by the 32 kHz clock.

3 r

0

2 r

0

1 0 rw

TIME rw

0 1

Settings

Recommend using values greater than 1.

MOTOROLA

Bluetooth Accelerator (BTA)

16-65

Bluetooth Accelerator (BTA)

16.5.8.2 Wake-Up 2 Register

The Wake-Up 2 Register contains the comparator value that determines the wake-up time. The value written to this register can be read back from the register. The Wake-Up 2 Register bits are explained in

Table 16-51.

WAKEUP_2

BIT 31 30 29 28 27

Wake-Up 2 Register

26 25 24 23 22 21 20 19

Addr

0x00216104

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–16

TIME

Bits 15–0

15 rw

0

14 rw

1

13 rw

0

12 rw

1

11 rw

0

10 rw

1

9 rw

0 rw

1

8

TIME

7

0x55AA rw

1

6 rw

0

5 rw

1

4 rw

0

Table 16-51. Wake-Up 2 Register Description

Description Settings

Reserved—These bits are reserved and should read 0.

3 rw

1

2 rw

0

1 rw

1

0 rw

0

Value for Wake-Up Timer 2

—Sets wake-up timer 2 for low-power operation.

The timer is clocked by the 32 kHz clock.

A non-zero value enables wake-up on the time value specified (WU_COUNT = WAKEUP_2).

Writing 0x0000 to this register disables timed wake-up, and only an external event will wake up the BTA.

16-66

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.8.3 Wake-Up Delta4 Register

The write-only Wake-Up Delta4 Register contains the delta value that is added to the WU_COUNT value.

The sum is written to the Wake-Up 4 Register on wake-up. The value determines the time from wake up until the Bluetooth master clock is started.

Reading address 0x0021610C returns the Wake-Up 4 Register (see section 16.5.8.4). The Wake-Up Delta4

Register bits are explained in Table 16-52.

WAKEUP_DELTA4

BIT 31 30 29 28 27

Wake-Up Delta4 Register

26 25 24 23 22 21 20 19

Addr

0x0021610C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 w

1

8 7 w

0

0x0234 w

0

6 w

0 w

1

5

TIME

4 w

1

3 w

0

2 w

1

1

Name

Reserved

Bits 31–10

TIME

Bits 9–0

Table 16-52. Wake-Up Delta4 Register Description

Description

Reserved—These bits are reserved and should read 0.

Delta Value for Wake-Up Timer 4

—Sets the wake-up timer delta value that is added to the

WU_COUNT value after a wake-up event.

w

0

0 w

0

MOTOROLA

Bluetooth Accelerator (BTA)

16-67

Bluetooth Accelerator (BTA)

16.5.8.4 Wake-Up 4 Register

The read-only Wake-Up 4 Register contains the time when the Bluetooth master clock is started

(WU_COUNT + WAKEUP_DELTA4). The WAKEUP_DELTA4 register bits are explained in

Table 16-53.

WAKEUP_4

BIT 31 30 29 28 27

Wake-Up 4 Register

26 25 24 23 22 21 20 19

Addr

0x0021610C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–16

TIME

Bits 15–0 r

0

15 14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0 r

0

8

TIME

7

0x0018 r

0

6 r

0

5 r

0

Table 16-53. Wake-Up 4 Register Description

Description

Reserved—These bits are reserved and should read 0.

4 r

1

3 r

1

2 r

0

1 r

0

0 r

0

Value for Wake-Up Timer 4

—Contains the time value when the Bluetooth master clock was started.

16-68

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.8.5 WakeUp Control Register

The write-only WakeUp Control Register enables or disables power-down and resets the wake-up counter.

Reading address 0x00216110 returns the Wake-Up Status Register (see Section 16.5.8.6, “Wake-Up

Status Register,” on page 16-70). The WakeUp Control Register bits are explained in Table 16-54.

WU_CONTROL

BIT 31

WakeUp Control Register

30 29 28 27 26 25 24 23 22 21 20 19

Addr

0x00216110

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–5

PDE

Bit 4 r

0

15 14 13 12 11 10 r

0 r

0 r

0 r

0 r

0

9 r

0

8 7 6 r

0 r

0

0x0008 r

0

Reserved—These bits are reserved and should read 0.

5 r

0

4 3

PDE CLR_CNT w

0 w

1

2

Table 16-54. WakeUp Control Register Description

Description Settings

r

0

CLR_CNT

Bit 3

Reserved

Bits 2–0

1 r

0

0 r

0

Power Down Enable

mode.

—Enables/Disables the powerdown

Wake-Up Counter Reset

—Resets the wake-up counter in the wake up module.

0 = Do not reset the wake-up counter

1 = Reset the wake-up counter

Reserved—These bits are reserved and should read 0.

0 = Disable power down and clear

WU_STATUS bit BTWUI

1 = Enable power down

MOTOROLA

Bluetooth Accelerator (BTA)

16-69

Bluetooth Accelerator (BTA)

16.5.8.6 Wake-Up Status Register

The read-only Wake-Up Status Register indicates whether an interrupt has occurred, the clock status and the whether power-down is enabled. It also contains the delta value that was written to the Wake-Up

Delta4 Register (see section 16.5.8.3). The Wake-Up Status Register bits are explained in Table 16-55.

WU_STATUS

BIT 31

Wake-Up Status Register

30 29 28 27 26 25 24 23 22 21 20 19 18

Addr

0x00216110

17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 13 12 11 10 r

0 r

0 r

0 r

0 r

0 r

0

9 8 7 6

WAKEUP_DELTA4 r

0 r

0 r

0

0x0000

5 r

0

4 r

0

3 r

0

2 1

BTWUI BT1_CLK_HOLD r

0 r

0

0

PDE r

0

Table 16-55. Wake-Up Status Register Description

Description Name Settings

Reserved

Bits 31–13

WAKEUP_DELTA4

Bits 12–3

BTWUI

Bit 2

BT1_CLK_HOLD

Bit 1

PDE

Bit 0

Reserved—These bits are reserved and should read 0.

Wake-Up Delta 4 Value

register.

Interrupt Indicator

—Returns the value that was written to the Wakeup_Delta4

—Indicates that WU4 occurred.

0 = No interrupt

1 = Interrupt

Bluetooth Clock

—Indicates the status of the Bluetooth Clock 0 = BT clock running

1 = BT clock stopped

Power Down Enable

—Indicates status of power down enable function.

0 = Power down disabled

1 = Power down enabled

16-70

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.8.7 Wake-Up Count Register

The read-only Wake-Up Count Register indicates the value of the counter used by the wake-up comparators. The Wake-Up Count Register bits are explained in Table 16-56.

WU_COUNT

BIT 31 30 29 28 27

Wake-Up Count Register

26 25 24 23 22 21 20 19

Addr

0x00216114

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–16

COUNT

Bits 15–0 r

0

15 14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8

COUNT

7 r

0

0x0000 r

0

6 r

0

5 r

0

4 r

0

Table 16-56. Wake-Up Count Register Description

Description

Reserved—These bits are reserved and should read 0.

3 r

0

2 r

0

1 r

0

Counter Value

—Holds the count value used by the comparators in the wake-up units to trigger wake-up interrupts.

0 r

0

MOTOROLA

Bluetooth Accelerator (BTA)

16-71

Bluetooth Accelerator (BTA)

16.5.9 System Register

One register correlates to system control functions.

16.5.9.1 Clock Control Register

The write-only Clock Control Register configures the clocks of the radio module interface to the IP bus.

See Section 16.3.1.1, “IP Bus Interface,” for more information on the synchronization between the IP clock and the BTA clock. The Clock Control Register bits are explained in Table 16-57.

CLK_CONTROL

BIT 31

Clock Control Register

30 29 28 27 26 25 24 23 22 21 20 19 18

Addr

0x00216118

17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 rw

0

14

RFM rw

0

13 rw

0 r

0

12 11 10 9

BT1_RSLOT rw

0 rw

0 rw

0

8 rw

0 rw

0

7 6 5

BT1_WSLOT

0x0000 rw

0 rw

0

4 rw

0

3 r

0

2 r

0

1 0

BT1_CLK_IN_DIV rw

0 rw

0

Table 16-57. Clock Control Register Description

Description Name Settings

Reserved

Bits 31–16

RFM

Bits 15–13

Reserved—These bits are reserved and should read 0.

RF Mode Selection

—Selects the RF module serial interface standard.

011 = MC13180

100 = SiliconWave

All other settings reserved

Reserved—This bit is reserved and should read 0.

Reserved

Bit 12

BT1_RSLOT

Bits 11–8

BT1_WSLOT

Bits 7–4

Reserved

Bits 3–2

Bluetooth RSlot

Bluetooth WSlot

—See Section 16.3.1.1, “IP Bus Interface.”

—See Section 16.3.1.1, “IP Bus Interface.”

Reserved—These bits are reserved and should read 0.

BT1_CLK_IN_DIV

Bits 1–0

BT1 Clock In Frequency Divider Select

—Selects the frequency division of the BT1 clock in.

00 = Idle

01 = 16

10 = 24

11 = 32

16-72

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.10 SPI Registers

Seven addresses pertain to SPI functions. The SPI Control Register and SPI Status Register are write and read registers associated with one address.

The SPI registers program the radio modules, and have different implementations according to the radio module used. For the specific values written to the SPI registers, see the radio specifications. A maximum of four data words are buffered by writing multiple words in a row to the registers SPI_WORD0,

SPI_WORD1, SPI_WORD2 and SPI_WORD3.

NOTE:

The software must poll the DONE bit of the SPI Status Register before reading or writing new data from or to the SPI.

16.5.10.1 SPI Word0 Register

The SPI Word0 Register bits, when the MC13180 radio is used, are described in Table 16-58.

The SPI Word0 Register bits, when the SiliconWave radio is used, are described in Table 16-59.

SPI_WORD0

BIT 31 30 29 28 27

SPI Word0 Register

26 25 24 23 22 21 20 19

Addr

0x00216120

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT 15 14 13 12 11 10 9 8 7

WORD0 (MC13180)

6 5 4 3 2 1 0

TYPE

RESET rw

0 rw

0

BYTE0 (SiliconWave) rw rw rw rw

0 0 0 0 rw

0 rw

0

0x0000 rw

0 rw

0 rw

BYTE1 (SiliconWave) rw rw rw

0 0 0 0 rw

0 rw

0

Table 16-58. SPI Word0 Register Description (MC13180)

Description Settings Name

Reserved

Bits 31–16

Reserved—These bits are reserved and should read 0.

WORD0

Bits 15–0

Word of Data

—Contains word 0 of the data read from or written to the RF module

The address of the register from which data is read or written is automatically post-incremented after a data read or write.

The start address is written to the SPI Read

Address Register before reads are performed or to the SPI Write Address Register after writes are performed.

MOTOROLA

Bluetooth Accelerator (BTA)

16-73

Bluetooth Accelerator (BTA)

Table 16-59. SPI Word0 Register Description (SiliconWave)

Description Settings Name

Reserved

Bits 31–16

Reserved—These bits are reserved and should read 0.

BYTE0

Bits 15–8

BYTE1

Bits 7–0

Byte 0

—Contains the upper byte of the data read from or written to the RF module.

Byte 1

—Contains the lower byte of the data read from or written to the RF module.

The address of the register from which data is read or written is automatically post-incremented after a data read or write.

The start address is written to the SPI Read

Address Register before reads are performed or to the SPI Write Address Register after writes are performed.

16.5.10.2 SPI Word1 Register

The write-only SPI Word1 Register bits, when the MC13180 radio is used, are described in Table 16-60.

The write-only SPI Word1 Register bits, when the SiliconWave radio is used, are described in

Table 16-61.

SPI_WORD1

BIT 31 30 29 28 27

SPI Word1 Register

26 25 24 23 22 21 20 19

Addr

0x00216124

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–16

WORD1

Bits 15–0

15 w

0

14 13 12 11 10 9 8 7

WORD1 (MC13180)

6 5 4 3 2 w

0

BYTE2 (SiliconWave) w w w w

0 0 0 0 w

0 w

0

0x0000 w

0 w

0 w

BYTE3 (SiliconWave) w w w

0 0 0 0

Table 16-60. SPI Word1 Register Description (MC13180)

Description

Reserved—These bits are reserved and should read 0.

Word of Data

—Contains word 1 of the data read from or written to the RF module

1 w

0

0 w

0

16-74

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

.

Name

Reserved

Bits 31–16

BYTE2

Bits 15–8

BYTE3

Bits 7–0

Table 16-61. SPI Word1 Register Description (SiliconWave)

Description

Reserved—These bits are reserved and should read 0.

Byte 2

—Contents vary according to the RF module used.

Byte 3

—Contents vary according to the RF module used.

16.5.10.3 SPI Word2 Register

The write-only SPI Word2 Register bits, when the MC13180 radio is used, are described in Table 16-62.

The write-only SPI Word2 Register bits, when the SiliconWave radio is used, are described in

Table 16-63.

SPI_WORD2

BIT 31 30 29 28 27

SPI Word2 Register

26 25 24 23 22 21 20 19

Addr

0x00216128

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT 15 14 13 12 11 10 9 8 7

WORD2 (MC13180)

6 5 4 3 2

TYPE

RESET w

0 w

0

BYTE4 (SiliconWave) w w w w

0 0 0 0 w

0 w

0

0x0000 w

0 w

0 w

BYTE5 (SiliconWave) w w w

0 0 0 0

Name

Reserved

Bits 31–16

WORD2

Bits 15–0

Table 16-62. SPI Word2 Register Description (MC13180)

Description

Reserved—These bits are reserved and should read 0.

Word of Data

—Contains word 2 of the data read from or written to the RF module.

Name

Reserved

Bits 31–16

Table 16-63. SPI Word2 Register Description (SiliconWave)

Description

Reserved—These bits are reserved and should read 0.

1 w

0

0 w

0

MOTOROLA

Bluetooth Accelerator (BTA)

16-75

Bluetooth Accelerator (BTA)

Name

BYTE4

Bits 15–8

BYTE5

Bits 7–0

Table 16-63. SPI Word2 Register Description (SiliconWave) (Continued)

Description

Byte 4

—Contents vary according to the RF module used.

Byte 5

—Contents vary according to the RF module used.

16.5.10.4 SPI Word3 Register

The write-only SPI Word3 Register bits, when the SiliconWave radio is used, are described in

Table 16-64. The write-only SPI Word3 Register bits, when the SiliconWave radio is used, are described in Table 16-65.

SPI_WORD3

BIT 31 30 29 28 27

SPI Word3 Register

26 25 24 23 22 21 20 19

Addr

0x0021612C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT 15 14 13 12 11 10 9 8 7

WORD3 (MC13180)

6 5 4 3 2

TYPE

RESET w

0 w

0

BYTE6 (SiliconWave) w w w w

0 0 0 0 w

0 w

0

0x0000 w

0 w

0 w

BYTE7 (SiliconWave) w w w

0 0 0 0

Name

Reserved

Bits 31–16

WORD3

Bits 15–0

Table 16-64. SPI Word3 Register Description (MC13180)

Description

Reserved—These bits are reserved and should read 0.

Word of Data—

Contains word 3 of the data read from or written to the RF module.

Name

Reserved

Bits 31–16

BYTE6

Bits 15–8

Table 16-65. SPI Word3 Register Description (SiliconWave)

Description

Reserved—These bits are reserved and should read 0.

Byte 6

—Contents vary according to the RF module used.

1 w

0

0 w

0

16-76

MC9328MX1 Reference Manual

MOTOROLA

Name

BYTE7

Bits 7–0

Programming Model

Table 16-65. SPI Word3 Register Description (SiliconWave) (Continued)

Description

Byte 7

—Contents vary according to the RF module used.

16.5.10.5 SPI Write Address Register

The write-only SPI Write Address Register determines the address of the first radio register to write to.

Writing to this register overrides any previous SPI writes by the Bluetooth Core. The SPI Write Address

Register bits, when the MC13180 radio is used, are explained in Table 16-66. The SPI Write Address

Register bits, when the SiliconWave radio is used, are explained in Table 16-67.

SPI_WRITE_ADDR

BIT 31 30 29 28

SPI Write Address Register

27 26 25 24 23 22 21 20 19

Addr

0x00216130

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT 15

TYPE

RESET

R/W w

0

14 w

0

13 12 11 10

Don’t Care (MC13180)

9 w

COMMAND (SiliconWave) w w w w

0 0 0 0 0

8 7

R/W w

0

0x0000 w

0

6 w

0

5 4 3 2

ADDRESS (MC13180)

ADDRESS (SiliconWave) w w w w

0 0 0 0

1 w

0

Table 16-66. SPI Write Address Register Description (MC13180)

Description Settings Name

Reserved

Bits 31–16

Don’t Care

Bits 15–8

R/W

Bit 7

ADDRESS

Bits 6–0

Reserved—These bits are reserved and should read 0.

Don’t Care—Ignored by the BTA.

Read/Write

—Tells the radio if it is a read or write cycle.

Set to 0.

Radio Register Address

—Contains the address of the first radio register that the buffered SPI

Word0 Register entries are written to. The address is automatically post-incremented in the radio register.

0 w

0

MOTOROLA

Bluetooth Accelerator (BTA)

16-77

Bluetooth Accelerator (BTA)

Table 16-67. SPI Write Address Register Description (SiliconWave)

Description Settings Name

Reserved

Bits 31–16

R/W

Bit 15

Reserved—These bits are reserved and should read 0.

Read/Write

—Tells the radio if it is a read or write cycle.

Set to 1.

COMMAND

Bits 14–8

ADDRESS

Bits 7–0

Command

—Specifies the command sent to the radio.

See the SiliconWave specification sheet.

Radio Register Address

—Contains the address of the first radio register that the buffered SPI

Word0 Register entries are written to. The address is automatically post-incremented in the radio register.

16.5.10.6 SPI Read Address Register

The write-only SPI Read Address Register contains the address of the first radio register that will be read from the SPI Word0 Register. Any address written to the SPI Read Address Register overrides any previous SPI address maintained by the Bluetooth core. The SPI Read Address Register bits, when the

MC13180 radio is used, are explained in Table 16-68. The SPI Read Address Register bits, when the

SiliconWave radio is used, are explained in Table 16-69.

SPI_READ_ADDR

BIT 31 30 29 28

SPI Read Address Register

27 26 25 24 23 22 21 20 19

Addr

0x00216134

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT 15

TYPE

RESET

R/W w

0

14 w

0

13 12 11 10

Don’t Care (MC13180)

9 w

COMMAND (SiliconWave) w w w w

0 0 0 0 0

8 7

R/W

6 w

0

0x0000 w

0 w

0

5 4 3 2

ADDRESS (MC13180)

ADDRESS (SiliconWave) w w w w

0 0 0 0

1 w

0

Name

Reserved

Bits 31–16

Don’t Care

Bits 15–8

Table 16-68. SPI Read Address Register Description (MC13180)

Description

Reserved—These bits are reserved and should read 0.

Don’t Care—Ignored by the BTA.

Settings

0 w

0

16-78

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Name

Table 16-68. SPI Read Address Register Description (MC13180) (Continued)

Description Settings

R/W

Bit 7

ADDRESS

Bits 6–0

Read/Write

—Tells the radio if it is a read or write cycle.

Set to 1.

Philsar Register Address

—Contains the address of the register read from the SPI Word0 Register.

Table 16-69. SPI Read Address Register Description (SiliconWave)

Name Description Settings

Reserved

Bits 31–16

R/W

Bit 15

Reserved—These bits are reserved and should read 0.

Read/Write

—Tells the radio if it is a read or write cycle.

Set to 0.

COMMAND

Bits 14–8

ADDRESS

Bits 7–0

Command

—Specifies the command sent to the radio.

See the SiliconWave specification sheet.

Philsar Register Address

—Contain the address of the register read from the SPI Word0 Register.

16.5.10.7 SPI Control Register

The write-only SPI Control Register sets up the mapping of values written to SPI registers to the signals between the BTA and the radio module. The SPI Control Register selects the radio module and sets up the duty cycle of the SPI clock. Reading address 0x00216138 returns the SPI Status Register (see section

16.5.10.8). The SPI Control Register bits are explained in Table 16-70.

SPI_CONTROL

BIT 31 30 29 28

SPI Control Register

Addr

0x00216138

27 26 25 24 23 22 21 20 19 18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 14 13 12

BYTE_ONLY SPI_CLKINV SPI_CLKDIV3 w

0 w

0 w

0 w

0

11 10 9

SPI_CLKDIV2

8 w

0 w

0 w

0 w

0

0x0000 w

0

7 6 5

SPI_CLKDIV1

4 w

0 w

0 w

0

3 r

0 w

0

2 1 0

SPI_MODE w

0 w

0 r

0

MOTOROLA

Bluetooth Accelerator (BTA)

16-79

Bluetooth Accelerator (BTA)

Table 16-70. SPI Control Register Description

Description Name Settings

Reserved

Bits 31–16

BYTE_ONLY

Bit 15

SPI_CLKINV

Bit 14

SPI_CLKDIV3

Bits 13–12

SPI_CLKDIV2

Bits 11–8

Reserved—These bits are reserved and should read 0.

Byte/Word

—Specifies whether the current data is a byte or a word.

0 = Normal

1 = Single bytes only

Inverted SPI Clock

—Specifies whether the SPI clock output is inverted.

0 = Normal

1 = Inverted

State 3 Delay

Figure 16-11 on page 16-80 for details.

State 2 Delay

—Controls the SPI clock space period. See

—Controls the SPI clock mark period. See

Figure 16-11 on page 16-80 for details.

These divider settings determine the duty cycle division ratio for high and low signal levels, as well as for the clock. The ratios are specified as the target ratios minus one.

SPI_CLKDIV1

Bits 7–4

State 1 Delay

—Controls the SPI clock space period. See

Figure 16-11 on page 16-80 for details.

Reserved

Bit 3

SPI_MODE

Bits 2–0

Reserved—This bit is reserved and should read 0.

SPI Mode Selection

used.

—Sets SPI mode according to the radio 011 = MC13180

100 = SiliconWave

All Other Settings Reserved

SPI State

1 2

SPI_EN

3 1 2 3 1 2 3

1

2 3

SPI_CLK

Figure 16-11. SPI Clock Dividers Determine Duty Cycle of SPI Clock

16-80

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.10.8 SPI Status Register

The read-only SPI Status Register indicates that the SPI is active and is used only with the Philsar,

MC13180 and SiliconWave radios. The SPI Status Register indicates whether the Philsar, MC13180, or

SiliconWave radios are currently busy reading or writing data. The SPI Status Register bits are explained in Table 16-71.

SPI_STATUS

BIT 31 30 29 28 27

SPI Status Register

26 25 24 23 22 21 20 19 18

Addr

0x00216138

17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 12 11 r

0 r

0 r

0

10 r

0

9 r

0

8 7 r

0

0x0001 r

0

6 r

0

5 r

0

4 r

0

3 r

0

2 r

0

1 r

0

0

DONE r

1

Table 16-71. SPI Status Register Description

Name Description Settings

Reserved

Bits 31–1

Reserved—These bits are reserved and should read 0.

DONE

Bit 0

SPI Active or Ready

radio.

—Indicates whether the BTA is currently reading or writing data from/to the Philsar/MC13180/SiliconWave

0 = Currently reading/writing data

1 = Reading/writing done

16.5.11 Frequency Hopping Registers

Five addresses pertain to frequency hopping functions. The Hop 0 (Frequency In) Register and Hop

Frequency Out Register are write and read registers associated with one address.

The write-only frequency hopping registers (HOP0, HOP1, HOP2, HOP3, HOP4) select the frequency hopping sequence. See Section 16.3.1.7, “Hop Selection Co-Processor,” for a discussion of the contents written to the register.

Reading address 0x00216140 returns the Hop Frequency Out Register (see section 16.5.11.6). The read-only Hop Frequency Out Register returns the partially computed hopping frequency channel based on the sequence written to the Hopping Frequency Registers.

The Register bits are explained in Table 16-72 through Table 16-76.

MOTOROLA

Bluetooth Accelerator (BTA)

16-81

Bluetooth Accelerator (BTA)

16.5.11.1 Hop 0 (Frequency In) Register

HOP0

BIT 31 30 29 28

Hop 0 (Frequency In) Register

27 26 25 24 23 22 21 20 19

Addr

0x00216140

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 w

0

14 13 w

0 w

0

12 w

0

11 w

0

10 w

0 w

0

9 8

CLK_LOW

7 w

0 w

0

0x0000

6 w

0

5 w

0

4 w

0

3 w

0

2 w

0

1 w

0

0 w

0

Table 16-72. Hop 0 (Frequency In) Register Description

Description Settings Name

Reserved

Bits 31–16

CLK_LOW

Bits 15–0

Reserved—These bits are reserved and should read 0.

Lower Part of the Current Clock

—Contains bits [15:0] of the clock that selects the hop frequency.

CLK [15:0] of the current clock

CLK0 is written but ignored by the Bluetooth core as it is not required by the standard

16.5.11.2 Hop 1 (Frequency In) Register

HOP1

BIT 31 30 29 28

Hop 1 (Frequency In) Register

27 26 25 24 23 22 21 20 19

Addr

0x00216144

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET r

0

15 14 13 12 11 10 r

0 r

0 r

0 r

0 r

0

9 8 7 w

0 w

0

0x0000 w

0

6 w

0

5 4

CLK_HIGH w

0 w

0

3 w

0

2 1 0 w

0 w

0 w

0

16-82

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Table 16-73. Hop 1 (Frequency In) Register Description

Description Name Settings

Reserved

Bits 31–10

Reserved—These bits are reserved and should read 0.

CLK_HIGH

Bits 9–0

Upper Part of the Current Clock

—Contains bits [25:16] of the clock that selects the hop frequency.

CLK [25:16] of the current clock

16.5.11.3 Hop 2 (Frequency In) Register

HOP2

BIT 31 30 29 28

Hop 2 (Frequency In) Register

27 26 25 24 23 22 21 20 19

Addr

0x00216148

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 w

0

14 w

0

13 w

0

12 w

0

11 w

0

10 w

0 w

0

9 8 7

LAPUAP_LOW w

0 w

0

0x0000

6 w

0

5 w

0

4 w

0

3 w

0

2 w

0

1 w

0

0 w

0

Table 16-74. Hop 2 (Frequency In) Register Description

Name Description

Reserved

Bits 31–16

LAPUAP_LOW

Bits 15–0

Reserved—These bits are reserved and should read 0.

Lower Part of the Combined LAP and 4 LSBs of UAP

—Contains bits [15:0] of the LAP.

Settings

ADDR [15:0] of the LAP

MOTOROLA

Bluetooth Accelerator (BTA)

16-83

Bluetooth Accelerator (BTA)

16.5.11.4 Hop 3 (Frequency In) Register

HOP3

BIT 31 30 29 28

Hop 3 (Frequency In) Register

27 26 25 24 23 22 21 20 19

Addr

0x0021614C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 w

0

10 w

0

9 w

0

8 w

0

0x0000 w

0

7 6 5

LAPUAP_HIGH

4 w

0 w

0 w

0

3 w

0

2 w

0

1 w

0

0 w

0

Table 16-75. Hop 3 (Frequency In) Register Description

Description Name

Reserved

Bits 31–12

Reserved—These bits are reserved and should read 0.

LAPUAP_HIGH

Bits 11–0

Upper Part of the Combined LAP and 4 LSBs of

UAP

—Contains bits [23:16] of the LAP and bits 3-0 of the UAP.

Settings

ADDR [23:16] of the LAP and ADDR [3:0] of the UAP

16.5.11.5 Hop 4 (Frequency In) Register

HOP4

BIT 31 30 29 28

Hop 4 (Frequency In) Register

27 26 25 24 23 22 21 20 19

Addr

0x00216150

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT 15 14 13 12 11 10

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0

9 8 7 6 5 4 r

0 r

0

0x0000 r

0 r

0 r

0 r

0

3 r

0

2

SYS w

0 w

0

1

STATE

0 w

0

16-84

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Name

Reserved

Bits 31–3

SYS

Bit 2

STATE

Bits 1–0

Table 16-76. Hop 4 (Frequency In) Register Description

Description

Reserved—These bits are reserved and should read 0.

Hop System

—Controls whether the unit is a 23-hop or 79-hop system.

Hop State

—Controls the operation of the hop co-processor according to the operating state of the unit.

Settings

0 = 79-hop system

1 = 23-hop system

00 = Page/inquiry scan

01 = Page/inquiry

10 = Page/inquiry response

11 = Connection

16.5.11.6 Hop Frequency Out Register

The read-only Hop Frequency Out Register returns the partially computed hopping frequency channel based on the sequence written to the Hopping Frequency Registers. The software performs a subsequent module-79 or module-23 operation (according to the country) to complete the computation. The Hop

Frequency Out Register bits are explained in Table 16-77.

HOP_FREQ_OUT

BIT 31 30 29 28

Hop Frequency Out Register

27 26 25 24 23 22 21 20 19

Addr

0x00216140

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7 r

0

0x0000 r

0

6 r

0

5 r

0 r

0

4 3

HOP_OUT r

0

2 r

0

1 r

0

0 r

0

Table 16-77. Hop Frequency Out Register Description

Description Settings Name

Reserved

Bits 31–8

HOP_OUT

Bits 7–0

Reserved—These bits are reserved and should read 0.

Hopping Sequence Selection Output

—Reads from the hopping sequence co-processor output after the Hopping Frequency Registers have been written. Software must complete the computation of the hop frequency channel.

This register reads the results of the partial computation to select the hop frequency.

Software is expected to complete the addition of F (see the Bluetooth specifications) and also the modulo operation.

MOTOROLA

Bluetooth Accelerator (BTA)

16-85

Bluetooth Accelerator (BTA)

16.5.12 Interrupt Register

There is one interrupt control register.

16.5.12.1 Interrupt Vector Register

Reading the Interrupt Vector Register indicates the last BTA interrupt that occurred. The BTA generates the following interrupts:

• Timer interrupt

• Interrupt when a frame is received or transmitted

• Interrupt when the header of a frame is received or transmitted

• SYSTICK interrupt

When 1 is written to any bit in the Interrupt Vector Register, the interrupt flag associated with that bit is cleared. The Interrupt Vector Register bits are described in Table 16-78.

INTERRUPT_VECTOR

BIT 31

Interrupt Vector Register

30 29 28 27 26 25 24 23 22 21 20 19 18

Addr

0x00216160

17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–4

TIMER

Bit 3

EOF

Bit 2

EOH

Bit 1

SYSTICK

Bit 0 r

0

15 14 13 12 11 10 r

0 r

0 r

0 r

0 r

0

9 r

0

8 7 6 r

0 r

0

0X0000 r

0

5 r

0

4 r

0

3 2 1 0

TIMER EOF EOH SYSTICK rw

0 rw

0 rw

0 rw

0

Table 16-78. Interrupt Vector Register Description

Description

Reserved—These bits are reserved and should read 0.

Settings

Timer Interrupt

—Indicates whether a Bluetooth application timer interrupt has occurred. Write 1 to clear.

End of Frame Interrupt

—Indicates whether an end of frame transmission and reception has occurred. Write 1 to clear.

End of Header Interrupt

—Indicates whether an end of header reception has occurred. See Section 16.5.1, “Sequencer Registers.” Write 1 to clear.

0 = No EOH interrupt

1 = EOH interrupt

SYSTICK Interrupt

—Indicates whether a SYSTICK of the current clock has occurred. Write 1 to clear.

0 = No timer interrupt

1 = Timer interrupt

0 = No EOF interrupt

1 = EOF interrupt

0 = No SYSTICK interrupt

1 = SYSTICK interrupt

16-86

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

16.5.13 Joint Detect Registers

Two addresses pertain to joint detection functions. These registers are primarily used for testing the

Bluetooth radio.

16.5.13.1 Synchronization Metric Register

The read-only Synchronization Metric Register returns the peak value of the correlation energy. The energy depends primarily on the access word. The Synchronization Metric Register bits are explained in

Table 16-79.

SYNC_METRIC

BIT 31 30 29 28

Synchronization Metric Register

27 26 25 24 23 22 21 20 19

Addr

0x00216170

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0 r

0

8 7 6

SYNC_METRIC

0x0000 r

0 r

0

5 r

0

4 r

0

3 r

0

Table 16-79. Synchronization Metric Register Description

Description Name

Reserved

Bits 31–15

Reserved—These bits are reserved and should read 0.

SYNC_METRIC

Bits 14–0

Synchronization Metric

—Indicates the peak value of the correlation energy.

2 r

0

1 r

0

0 r

0

MOTOROLA

Bluetooth Accelerator (BTA)

16-87

Bluetooth Accelerator (BTA)

16.5.13.2 Synchronize Frequency Carrier Register

The read-only Synchronize Frequency Carrier Register (SYNC_FC) returns the offset from the carrier frequency. The resolution is 1/128 MHz per bit. The Synchronize Frequency Carrier Register bits are explained in Table 16-80.

SYNC_FC

BIT 31 30 29

Synchronize Frequency Carrier Register

28 27 26 25 24 23 22 21 20 19

Addr

0x00216174

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–8

SYNC_FC

Bits 7–0 r

0

15 14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7 r

0

0x0000 r

0

6 r

0

5 r

0 r

0

4 3

SYNC_FC r

0

Table 16-80. Synchronize Frequency Carrier Register Description

Description

Reserved—These bits are reserved and should read 0.

2 r

0

1 r

0

0 r

0

Carrier Frequency Offset

—Indicates the offset from the carrier frequency with a resolution of 1/128

MHz per bit.

16.5.14 Bit Reverse Registers

Two addresses pertain to reversing functions.

16.5.14.1 Word Reverse Register

The Word Reverse Register is written with the 16-bit word to be bit reversed. When read, the register gives the bit reversed word. The Word Reverse Register bits are explained in Table 16-81.

16-88

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

WORD_REVERSE

BIT 31 30 29 28 27

Word Reverse Register

26 25 24 23 22 21 20 19

Addr

0x00216178

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 rw

0

14 rw

0

Name

Reserved

Bits 31–16

WORD_REVERSED

Bits 15–0

13 rw

0

12 rw

0

11 rw

0

10 rw

0 rw

0

9 8 7

WORD_REVERSED

6 rw

0 rw

0 rw

0

0x0000

5 rw

0

4 rw

0

Table 16-81. Word Reverse Register Description

Description

Reserved—These bits are reserved and should read 0.

3 rw

0

2 rw

0

Settings

1 rw

0

0 rw

0

Word to be Bit Reversed

—Receives the 16-bit word to be bit reversed.

This register is written with the 16-bit word to be bit reversed.

Word Reversed

—Returns the bit reversed word.

When read, it gives the bit reversed word.

16.5.14.2 Byte Reverse Register

The Byte Reverse Register (BYTE_REVERSE) is written with the byte to be bit reversed. On reading the register gives the bit reversed word. The Byte Reverse Register register bits are explained in Table 16-82.

BYTE_REVERSE

BIT 31 30 29 28 27

Byte Reverse Register

26 25 24 23 22 21 20 19

Addr

0x0021617C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET r

0

15 14 13 12 11 10 r

0 r

0 r

0 r

0 r

0

9 r

0

8 7 6 r

0

0x0000 rw

0 rw

0 rw

0

5 4 3

BYTE_REVERSED

2 rw

0 rw

0 rw

0

1 rw

0

0 rw

0

MOTOROLA

Bluetooth Accelerator (BTA)

16-89

Bluetooth Accelerator (BTA)

Table 16-82. Byte Reverse Register Description

Description Settings Name

Reserved

Bits 31–8

BYTE_REVERSED

Bits 7–0

Reserved—These bits are reserved and should read 0.

Byte to be Bit Reversed

to be bit reversed.

Byte Reversed

byte.

—Receives the byte

—Receives the bit reversed

This register is written with the byte to be bit reversed.

When read, it gives the bit reversed byte.

16-90

MC9328MX1 Reference Manual

MOTOROLA

Chapter 17

Multimedia Accelerator (MMA)

17.1 Introduction

Many digital signal processing algorithms require iterative operations that can be closely pipelined, however they require irregular addressing for data access. These algorithms include FIR filtering, correlation, and FFT operations. In many system implementations, these operations account for a large percentage of the total processing cycles.

The multimedia accelerator (MMA) provides the MC9328MX1 with digital signal processing capability while maintaining efficient utilization of system and bus resources. The MMA in conjunction with the

ARM9 processor core (ARM920T processor), form a hybrid operating environment that combines the efficiency and simplicity of a RISC processor with the powerful, number crunching, iterative operations of a digital signal processor. The RISC processor implements the algorithms and processes, assisted by the

MMA in crucial digital signal processing operations. Applications include MPEG or MP3 encoding/decoding and speech compression/decompression such as G.723.1, CELP, or RPE-LTP for

GSM.

17.2 MMA Operation

The MMA module consists of two major blocks—a multiply-accumulate (MAC) block and a discrete cosine transform (DCT) block. Each of these blocks has its own set of control registers. The control registers are accessed by the ARM920T processor for configuration as well as data input and result access.

The ARM920T processor enables the signal processing functions in the MMA, which then automatically issues data access requests to the MC9328MX1’s embedded SRAM (eSRAM) through the memory controller to perform the required functions. The MMA can read from or write to the eSRAM. Output data is stored in the internal FIFO of the MMA. If the FIFO is not cleared, MMA processes halt so that no output data is overwritten or lost.

17.2.1 Memory Access

The MMA supports only 32–bit access to its registers because the bus interface to the system bus, referred to as the Advanced High-performance Bus (AHB), is 32 bits wide. Because the MMA processes data that is 24 bits wide, access to memory is always in 32–bit words. The MMA supports both big endian and little endian access.

The MMA’s access to the eSRAM is shared with the liquid crystal display controller (LCDC) and the

ARM920T processor. LCDC access to the eSRAM has the highest priority, followed by ARM920T processor access, and finally MMA access. For this reason, data access latency of the MMA to the eSRAM can be as long as the LCDC data burst access.

MOTOROLA

Multimedia Accelerator (MMA)

17-1

Multimedia Accelerator (MMA)

Figure 17-1 on page 17-2 shows the data access to the eSRAM by the MMA and the ARM920T processor.

AHB

AHB Access

Control

Ctrl Registers

Data Port

ARM920T Core

DCT MAC

Data Access Controller

Memory

Controller eSRAM

External

Memory

Figure 17-1. MMA Data Access

17.2.2 MAC

The MAC block provides the MC9328MX1 with fast multiply-accumulate capability. It can perform

1-D

×

1-D, 1-D

×

2-D, 2-D

×

1-D and 2-D

×

2-D matrix multiplication to support applications such as

MPEG audio encoder subband filtering, decoder subband synthesis, and MP3 IMDCT.

17.2.2.1 Basic MAC Operation

Two circular data addressing units in the MMA provide the control to fetch data for two operands. All memory access is in 32–bit words. The MAC can perform 24–bit

×

24–bit signed, unsigned, or alternating sign multiplication. The 48–bit multiplier output is added to a 56–bit accumulator, allowing for 8–bit overflow. After a user-defined number of MAC iterations, the accumulator value is stored in a 32

×

32–bit

FIFO and the accumulator is cleared. The user can select which 32–bit subset of the 56–bit accumulator result is stored in the FIFO.

17.2.2.2 Data Access

The two operands for the multiplier are supplied by the X and Y registers. The data for these two registers is loaded from memory by the data access controller. The MMA maintains two circular buffers in the eSRAM, one each for the X and Y operands.

To limit how long the bus is held when the MMA accesses memory, the MMA_MAC_BURST register sets the number of burst cycles permitted for each access, after which the eSRAM is released. The MMA resumes operation if there are no other eSRAM access requests pending.

Circular buffer operation for the X registers is shown in Figure 17-2 on page 17-3.

17-2

MC9328MX1 Reference Manual

MOTOROLA

eSRAM

MMA Operation

Base Register

Points to the start address of the circular buffer.

+

INDEX_LOAD

+

Index Register

Address Index added to the

Base Register to yield the actual physical location a) Initially b) After every

MMA_MAC_XCOUNT iteration if the

X INDEX LOAD bit is set.

Address Index

Base register added to Index register to produce Address

Index

+

Increment Register

This value is added to the

Index Register after every

XCOUNT iteration if the

X INDEX INCR bit is set.

Modify Register

This value is added to the

Address Index after each access.

Length Register

Determines the size of the circular buffer. Actual

Index = (index - length). Actual physical location is (Actual Index + Base)

Figure 17-2. Circular Buffering Operation

17.2.2.3 Cache

The X operand access has an associated cache and cache controller. Initially, the cache is cleared and the X operand data is accessed from the eSRAM and stored in the cache. Subsequent accesses to the same address cause a cache hit and the data is accessed from the cache.

The cache is a memory block of 512 24–bit words. Each word also has an associated valid bit to indicate data validity. The cache can be enabled or disabled. To fully use the cache, the base address of the operand must be on a 2K boundary. When a data access matches an address in the cache and the valid bit for that word is set, data is fetched from the cache. When the valid bit is cleared, data is accessed from the eSRAM or from external memory and stored in the cache, and the valid bit is set. The cache is cleared only by writing 1 to the CACHE CLR bit. This action also registers the base address of the 2K boundary as the valid cache block address. The user must program the MMA_MAC_XBASE register and the

MMA_MAC_XINDEX register before clearing the cache.

MOTOROLA

Multimedia Accelerator (MMA)

17-3

Multimedia Accelerator (MMA)

17.2.3 DCT/iDCT

The DCT/iDCT block in the MMA performs 2-D 8

×

8 discrete cosine transforms and inverse discrete cosine transforms on 8

×

8 blocks of pixel data. The design is based on a distributed arithmetic processor that computes two bits at a time. Latency is approximately 170 clock cycles after filling the input FIFO.

Figure 17-3 is a block diagram of the DCT/iDCT.

64

×

16

Data Buffer

AHB or

Mem Ctrl

Interface

FIFO

(32

×

32)

DCT

Figure 17-3. DCT/iDCT Architecture

The DCT/iDCT can be programmed to access data through the AHB bus or through the memory controller. When the memory controller is used, addresses are generated automatically—the user programs the start and destination addresses, the number of blocks in the X-direction (XCOUNT) and Y-direction

(YCOUNT), and the address offsets. The source address and destination address can be same.

Input data is loaded into a 32

×

32 FIFO. Each word in the FIFO represents two 16–bit pixels. The accuracy of the input data is 9 bits for a DCT, so the 7 least significant bits (LSBs) must be zero-filled. For an iDCT, the accuracy is 12 bits, so the 4 LSBs must be zero-filled.

D8 D7 D6

D11 D10 D9

D5

D8

D4 D3

D7 D6

D2

DCT Format

D1 D0 0

D5 iDCT Format

D4 D3 D2

0

D1

0

D0

0

0

0

0

0

0

0

0

Figure 17-4. Data Formatting for DCT and iDCT

The DCT/iDCT is enabled by writing 1 to the DCT ENA bit in the MMA_DCTCTRL register. After the bit is set, the DCT/iDCT is performed automatically. When the process is complete, an interrupt is generated and the DCT ENA bit is cleared. In this way, a DCT/iDCT can be run for an entire frame of data.

17-4

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

17.3 Programming Model

The MMA module includes 33 user-accessible 32-bit registers. Table 17-1 on page 17-5 summarizes these registers and their addresses.

Table 17-1. MMA Module Register Memory Map

Description Name Address

MMA MAC Control Registers

MMA MAC Module Register

MMA MAC Control Register

MMA MAC Multiply Counter Register

MMA MAC Accumulate Counter Register

MMA MAC Interrupt Register

MMA MAC Interrupt Mask Register

MMA MAC FIFO Register

MMA MAC FIFO Status Register

MMA MAC Burst Count Register

MMA MAC Bit Select Register

MMA_MAC_MOD

MMA_MAC_CTRL

MMA_MAC_MULT

MMA_MAC_ACCU

0x00222000

0x00222004

0x00222008

0x0022200C

MMA_MAC_INTR 0x00222010

MMA_MAC_INTR_MASK 0x00222014

MMA_MAC_FIFO 0x00222018

MMA_MAC_FIFO_STAT 0x0022201C

MMA_MAC_BURST

MMA_MAC_BITSEL

0x00222020

0x00222024

MMA MAC X Register Control Registers

MMA MAC X Base Address Register

MMA MAC X Index Register

MMA MAC X Length Register

MMA MAC X Modify Register

MMA MAC X Increment Register

MMA MAC X Count Register

MMA_MAC_XBASE

MMA_MAC_XINDEX

MMA_MAC_XLENGTH

MMA_MAC_XMODIFY

MMA_MAC_XINCR

MMA_MAC_XCOUNT

MMA MAC Y Register Control Registers

0x00222200

0x00222204

0x00222208

0x0022220C

0x00222210

0x00222214

MMA MAC Y Base Address Register

MMA MAC Y Index Register

MMA MAC Y Length Register

MMA MAC Y Modify Register

MMA MAC Y Increment Register

MMA MAC Y Count Register

MMA_MAC_YBASE

MMA_MAC_YINDEX

MMA_MAC_YLENGTH

MMA_MAC_YMODIFY

MMA_MAC_YINCR

MMA_MAC_YCOUNT

MMA DCT/iDCT Registers

0x00222300

0x00222304

0x00222308

0x0022230C

0x00222310

0x00222314

MOTOROLA

Multimedia Accelerator (MMA)

17-5

Multimedia Accelerator (MMA)

Table 17-1. MMA Module Register Memory Map (Continued)

Description Name Address

DCT/iDCT Control Register

DCT/iDCT Version Register

DCT/iDCT IRQ Enable Register

DCT/iDCT IRQ Status Register

DCT/iDCT Source Data Address

DCT/iDCT Destination Data Address

DCT/iDCT X-Offset Address

DCT/iDCT Y-Offset Address

DCT/iDCT XY Count

DCT/iDCT Skip Address

DCT/iDCT Data FIFO

MMA_DCTCTRL

MMA_DCTVERSION

MMA_DCTIRQENA

MMA_DCTIRQSTAT

MMA_DCTSRCDATA

MMA_DCTDESDATA

MMA_DCTXOFF

MMA_DCTYOFF

MMA_DCTXYCNT

MMA_DCTSKIP

MMA_DCTFIFO

0x00222400

0x00222404

0x00222408

0x0022240C

0x00222410

0x00222414

0x00222418

0x0022241C

0x00222420

0x00222424

0x00222500

17.3.1 MMA MAC Control Registers

There are 10 registers that control general MMA MAC operation.

17.3.1.1 MMA MAC Module Register

MMA_MAC_MOD

BIT 30

MMA MAC Module Register

29 28 27 26 25 24 23 22 21 20 19 18

Addr

0x00222000

17 16

TYPE

RESET

31

RST rw

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

RST

Bit 31

15 r

0

14 13 12 11 10 r

0 r

0 r

0 r

0 r

0

9 r

0

8 7 6 r

0 r

0

0x0000 r

0

5 r

0

4 r

0

3 r

0

2 r

0

1 r

0

0

MOD ENAB rw

0

Table 17-2. MMA MAC Module Register Description

Description

Software Reset for the MAC

—indicates whether the reset sequence is complete.

Settings

0 = Reset is complete

1 = Reset is in progress

17-6

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Table 17-2. MMA MAC Module Register Description (Continued)

Description Settings Name

Reserved

Bits 30–1

MOD ENAB

Bit 0

Reserved—These bits are reserved and should read 0.

Module Enable

—Enables or disables the MAC.

0 = Disable the MAC

1 = Enable the MAC

17.3.1.2 MMA MAC Control Register

MMA_MAC_CTRL

BIT 31 30 29 28

MMA MAC Control Register

27 26 25 24 23 22 21 20 19 18

Addr

0x00222004

17 16

TYPE

RESET w

0 w

0 rw

0 rw

0 rw rw

0 0 rw

0 rw

0 w w

0 0

0x0000 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0

BIT 15 14 13

TYPE

RESET r

0 r

0 r

0

12 r

0

11 10 r

0 r

0

9 r

0

8 7 6 r

0 r

0

0x0000 r

0

5 r

0

4 r

0

3 r

0

2 1

CACHE

CLR

CACHE

EN

0

OP EN w

0 rw

0 rw

0

Name

X MODIFY

PRESET

Bit 31

X INDEX CLR

Bit 30

X INDEX INCR

Bit 29

Table 17-3. MMA MAC Control Register Description

Description Settings

X Modify Preset

—Presets MMA_MAC_XMODIFY register to value 0x00000004.

0 = MMA_MAC_XMODIFY

Register is not preset

1 = MMA_MAC_XMODIFY

Register is preset to value

0x00000004

X Index Clear

—Clears MMA_MAC_XINDEX register to value of 0x00000000.

X Index Increment

—Determines whether the

MMA_MAC_XINDEX register in the XDAC module is incremented by the value in the MMA_MAC_XINCR register for every (MMA_MAC_XCOUNT + 1) iteration.

X INDEX INCR is used with X INDEX LOAD.

0 = MMA_MAC_XINDEX Register is not reset.

1 = MMA_MAC_XINDEX Register is reset to value 0x00000000

0 = MMA_MAC_XINDEX is not incremented

1 = MMA_MAC_XINDEX register is incremented

MOTOROLA

Multimedia Accelerator (MMA)

17-7

Multimedia Accelerator (MMA)

Table 17-3. MMA MAC Control Register Description (Continued)

Description Settings Name

X INDEX LOAD

Bit 28

X Index Load

—Determines whether the index in the

XDAC module is loaded with the values in the

MMA_MAC_XINDEX register for every

(MMA_MAC_XCOUNT + 1) iteration. When set, the Index is reloaded with the MMA_MAC_XINDEX register value.

When cleared, the index retains the last stored value.

X_DATA_SEL

Bit 27

0 = XDAC index register is not reloaded

1 = XDAC index register is reloaded

0 = Bits [23:0] used as operand

1 = Bits [31:8] used as operand

X SIGN ALT

Bit 26

X Data Select

—Selects which bits in the 32-bit data bus are used to create the 24-bit operand.

Note:

When the cache is enabled, X_DATA_SEL must be set to one.

X Operand Sign Alternate

—Determines whether the X operand alternates its operand sign of the operation.

0 = X operand sign is not alternated

1 = X operand sign is alternated

X SIGN INI

Bit 25

X SIGNED

Bit 24

Y MODIFY

PRESET

Bit 23

Y INDEX CLR

Bit 22

Y INDEX INCR

Bit 21

Y Index Increment

—Determines whether the

MMA_MAC_YINDEX register in the YDAC module is incremented by the value in the MMA_MAC_YINCR register for every (MMA_MAC_YCOUNT + 1) iteration.

Y INDEX INCR is used with Y INDEX LOAD.

Y INDEX LOAD

Bit 20

Y Index Load

—Determines whether the index in the

YDAC module is loaded with the values in the

MMA_MAC_YINDEX register for every

(MMA_MAC_YCOUNT + 1) iteration. When set, the index is reloaded with the MMA_MAC_YINDEX register value.

When cleared, the index retains the last stored value.

Y_DATA_SEL

Bit 19

Y SIGN ALT

Bit 18

Y Data Select

—Selects which bits in the 32-bit data bus are used to create the 24-bit operand.

Y Operand Sign Alternate

—Determines whether the Y operand alternates its operand sign of the operation.

Y SIGN INI

Bit 17

X Operand Initial Sign

—Determines the X operand initial sign of the operation with x.

0 = +(x)

1 = -(x)

X Operand Signed

—Determines whether the X operand is signed or unsigned. When set, the X operand is a signed value. When cleared, the X operand is unsigned.

0 = X operand is unsigned

1 = X operand is signed

Y Modify Preset

—Presets MMA_MAC_YMODIFY register to value 0x00000004.

0 = MMA_MAC_YMODIFY

Register is not preset

1 = MMA_MAC_YMODIFY

Register is preset to value

0x00000004

Y Index Clear

—Setting this bits clears the

MMA_MAC_YINDEX register to value 0x00000000.

0 = MMA_MAC_YINDEX is not reset

1 = MMA_MAC_YINDEX is reset to value of 0x000 0000

0 = MMA_MAC_YINDEX is not incremented

1 = MMA_MAC_YINDEX is incremented

Y Operand Initial Sign

—Determines whether the Y operand initial sign of the operation with y.

0 = Index register is not reloaded

1 = Index register is reloaded

0 = Bits [23:0] used as operand

1 = Bits [31:8] used as operand

0 = Y operand sign is not alternated

1 = Y operand sign is alternated

0 = +(y)

1 = -(y)

17-8

MC9328MX1 Reference Manual

MOTOROLA

Name

Y SIGNED

BIT 16

Reserved

Bits 15–3

CACHE CLR

Bit 2

CACHE EN

Bit 1

OP EN

Bit 0

Programming Model

Table 17-3. MMA MAC Control Register Description (Continued)

Description Settings

Y Operand Signed

—Determines whether the Y operand is signed or unsigned. When set, the Y operand is a signed value. When cleared, the Y operand is unsigned.

0 = Y operand is unsigned

1 = Y operand is signed

Reserved—These bits are reserved and should read 0.

Cache Clear

—Clears the X operand cache and writes the

(base + index) register value into the cache block register.

0 = No effect

1 = Clear X operand cache and write (base+index) register value into the cache block register

Cache Enable

—Enables or disables the X operand cache.

0 = X operand cache is disabled

1 = X operand cache is enabled

Operation Enable

—Initiates MAC operation and indicates if the operation is complete. The operation does not start if

MMA_MAC_MULT register contains 0.

0 = MAC operation is complete

1 = Initiate MAC operation or MAC operation is not complete

17.3.1.3 MMA MAC Multiply Counter Register

MMA_MAC_MULT

MMA MAC Multiply Counter Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19

Addr

0x00222008

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0X0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0 rw

0

9 8 7

MULT COUNTER rw

0 rw

0

6 rw

0

0X0000

5 rw

0

4 rw

0

3 rw

0

2 rw

0

1 rw

0

Table 17-4. MMA MAC Multiply Counter Register Description

Description Name

Reserved

Bits 31–16

MULT COUNTER

Bits 15–0

Reserved—These bits are reserved and should read 0.

Multiply Counter

—Determines the number of multiply operations that the MAC module performs. For proper operation, this value must be an integer multiple of the

(MMA_MAC_ACCU + 1) value.

0 rw

0

MOTOROLA

Multimedia Accelerator (MMA)

17-9

Multimedia Accelerator (MMA)

17.3.1.4 MMA MAC Accumulate Counter Register

MMA_MAC_ACCU

MMA MAC Accumulate Counter Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19

Addr

0x0022200C

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0X0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT 15

TYPE

RESET rw

0

Name

Reserved

Bits 31–16

ACCU

COUNTER

Bits 15–0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0 rw

0

9 8 7

ACCU COUNTER

6 rw

0 rw

0 rw

0

0X0000

5 rw

0

4 rw

0

3 rw

0

Table 17-5. MMA MAC Accumulate Counter Register Description

Description

Reserved—These bits are reserved and should read 0.

2 rw

0

1 rw

0

0 rw

0

Accumulate Counter

—Determines the number of accumulate operations that the MAC module performs before writing the accumulated result to the FIFO. The value written to this register is the actual value minus 1 (0x0003 for four accumulate operations).

17.3.1.5 MMA MAC Interrupt Register

MMA_MAC_INTR

BIT 31 30

MMA MAC Interrupt Register

29 28 27 26 25 24 23 22 21 20 19 18

Addr

0x00222010

17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 14 13 12 11 10 9 8 7 6 5 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0004 r

0

4

OP

ERROR rw

0

3

OP

END rw

0

2

FIFO

EMPT rw

1

1

FIFO

HALF rw

0

0

FIFO

FULL rw

0

17-10

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Table 17-6. MMA MAC Interrupt Register Description

Description Name Settings

Reserved

Bits 31–5

Reserved—These bits are reserved and should read 0.

OP ERROR

Bit 4

OP ERROR Interrupt

—Sets when there is a memory access error from the bus. Write 1 to clear

OP END

Bit 3

Operation End Interrupt

—Sets when the MAC operation ends. Write a 1 to clear.

FIFO EMPT

Bit 2

FIFO Empty Interrupt

—Sets when the FIFO is empty. Write a 1 to clear.

FIFO HALF

Bit 1

FIFO Half Full Interrupt

—Sets when the FIFO is half full.

Write a 1 to clear.

FIFO FULL

Bit 0

FIFO Full Interrupt

—Sets when the FIFO is full. Write a 1 to clear.

0 = No error in operation.

1 = Error in operation.

0 = MAC operation is not complete

1 = MAC operation is complete

0 = FIFO is not empty

1 = FIFO is empty

0 = FIFO is not half full

1 = FIFO is half full

0 = FIFO is not full

1 = FIFO is full

17.3.1.6 MMA MAC Interrupt Mask Register

MMA_MAC_INTR_MASK

BIT 31 30 29 28 27

MMA MAC Interrupt Mask Register

26 25 24 23 22 21 20 19

Addr

0x00222014

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7 r

0

0x001F r

0

6 r

0

5 r

0

4 3 2 1 0

OP

ERRO

R

OP

END

FIFO

EMPT

FIFO

HALF

FIFO

FULL r

1 rw

1 rw

1 rw

1 rw

1

Table 17-7. MMA MAC Interrupt Mask Register Description

Name Description

Reserved

Bits 31–5

Reserved—These bits are reserved and should read 0.

OP ERROR

Bit 4

OP ERROR Mask

—Masks the OP ERROR Interrupt.

OP END

Bit 3

Operation End Interrupt Mask

—Masks the OP END interrupt.

Settings

0 = Mask on/enable interrupt

1 = Mask off/disable interrupt.

0 = Mask on/enable interrupt

1 = Mask off/disable interrupt

MOTOROLA

Multimedia Accelerator (MMA)

17-11

Multimedia Accelerator (MMA)

Table 17-7. MMA MAC Interrupt Mask Register Description (Continued)

Description Settings Name

FIFO EMPT

Bit 2

FIFO Empty Interrupt Mask

—Masks the FIFO EMPT interrupt.

FIFO HALF

Bit 1

FIFO Half Full Interrupt Mask

—Masks the FIFO HALF interrupt.

FIFO FULL

Bit 0

FIFO Full Interrupt Mask

—Masks the FIFO FULL interrupt.

0 = Mask on/enable interrupt

1 = Mask off/disable interrupt

0 = Mask on/enable interrupt

1 = Mask off/disable interrupt

0 = Mask on/enable interrupt

1 = Mask off/disable interrupt

17.3.1.7 MMA MAC FIFO Register

MMA_MAC_FIFO

BIT 31 30

TYPE

RESET r

0 r

0

29 r

0

28 r

0 r

0

27

MMA MAC FIFO Register

26 r

0

25 24 23

FIFO REGISTER

22 r

0 r

0 r

0 r

0

0x0000

21 r

0

20 r

0 r

0

19

Addr

0x00222018

18 17 16 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

14 r

0

13 r

0

12 r

0

11 r

0

10 r

0 r

0

9 8 7

FIFO REGISTER r

0 r

0

0x0000

6 r

0

5 r

0

4 r

0

Table 17-8. MMA MAC FIFO Register Description

Name Description

FIFO REGISTER

Bits 31–0

FIFO Read Register

—Returns FIFO output.

3 r

0

2 1 0 r

0 r

0 r

0

17-12

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

17.3.1.8 MMA MAC FIFO Status Register

MMA_MAC_FIFO_ST

AT

BIT 31 30 29 28

MMA MAC FIFO Status Register

27 26 25 24 23 22 21 20

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0

Addr

0x0022201C

16 r

0

19 18 17

FIFO COUNT r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–21

FIFO COUNT

Bits 20–16

Reserved

Bits 15–3

FIFO EMPT

Bit 2

FIFO HALF

Bit 1

FIFO FULL

Bit 0

15 r

0

14 13 12 11 10 9 8 7 6 5 4 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0004 r

0 r

0 r

0

Table 17-9. MMA MAC FIFO Status Register Description

Description

Reserved—These bits are reserved and should read 0.

3 r

0

2

FIFO

EMPT r

1

1

FIFO

HALF r

0

0

FIFO

FULL r

0

Settings

FIFO Data Count

—Indicates the number of data in the FIFO.

Reserved—These bits are reserved and should read 0.

FIFO Empty Status

—Indicates the status of the FIFO EMPT interrupt.

FIFO Half Full Status

—Indicates the status of the FIFO HALF interrupt.

FIFO Full Status

—Indicates the status of the FIFO FULL interrupt.

See description

See description

See description

See description

MOTOROLA

Multimedia Accelerator (MMA)

17-13

Multimedia Accelerator (MMA)

17.3.1.9 MMA MAC Burst Count Register

MMA_MAC_BURST

BIT 31 30 29 28

MMA MAC Burst Count Register

27 26 25 24 23 22 21 20 19

Addr

0x00222020

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

15 r

0

Name

Reserved

Bits 31–8

BURST COUNT

Bits 7–0

14 r

0

13 r

0

12 r

0

11 r

0

10 r

0

9 r

0

8 7 r

0

0x0000 rw

0

6 rw

0

5 rw

0

4 3

BURST COUNT

2 rw

0 rw

0 rw

0

Table 17-10. MMA MAC Burst Count Register Description

Description

Reserved—These bits are reserved and should read 0.

1 rw

0

0

Memory Access Burst Count

—Determines the maximum number of read accesses to memory allowed in one burst. This feature ensures that the MMA does not hold the memory bus for too long.

rw

0

17.3.1.10 MMA MAC Bit Select Register

MMA_MAC_BITSEL

BIT 31 30 29 28 27

MMA MAC Bit Select Register

26 25 24 23 22 21 20 19

Addr

0x00222024

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT 15 14 13 12 11 10

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0

9 8 7 6 5 4 r

0 r

0

0x0000 r

0 r

0 r

0 r

0

3 r

0

2 rw

0

1

BITSEL rw

0

0 rw

0

17-14

MC9328MX1 Reference Manual

MOTOROLA

Programming Model

Name

Reserved

Bits 31–3

BITSEL

Bits 2–0

Table 17-11. MMA MAC Bit Select Register Description

Description

Reserved—These bits are reserved and should read 0.

Accumulator Output Bit Select

—Selects which 32–bit subset of the

56–bit accumulator is stored in the FIFO.

Settings

000 = bits 31:0

001 = bits 35:4

010 = bits 39:8

011 = bits 43:12

100 = bits 47:16

101 = bits 51:20

110 = bits 55:24

17.3.2 MMA MAC XY Count Accumulate Register

MMA_MAC_XYACCU

BIT

TYPE

RESET

31 w

0

30 w

0

29 w

0

28 w

0

MMA MAC XY Count Accumulate

Register

27 26 21 20 w

0 w

0

25 24 23 22

MMA_MAC_XY_COUNT w

0 w

0 w

0 w

0

0x0000 w

0 w

0

19 w

0

Addr

0x00222040

18 17 16 w

0 w

0 w

0

BIT

TYPE

RESET w

0

15 14 13 w

0 w

0

12 w

0

11 w

0

10 w

0

9 8 7 6

MMA_MAC_XY_COUNT w

0 w

0 w

0 w

0

0x0000

5 w

0

4 w

0

3 w

0

2 1 0 w

0 w

0 w

0

17.3.3 MMA MAC X Register Control Registers

There are 6 registers that reside in the X operand Data Access Controller (XDAC). The XDAC has an associated cache. The initial access by the XDAC is a cache miss, so the operand is fetched from memory and stored in the cache. Subsequent accesses to the same location cause cache hits, so the data is loaded from the cache instead of from memory.

MOTOROLA

Multimedia Accelerator (MMA)

17-15

Multimedia Accelerator (MMA)

17.3.3.1 MMA MAC X Base Address Register

MMA_MAC_XBASE

BIT 31

TYPE

RESET rw

0

30 rw

0

29 rw

0

28 rw

0

27

MMA MAC X Base Address Register

26 25 20 19

Addr

0x00222200

18 17 16 rw

0 rw

0 rw

0

24

XBASE

23 rw

0

0x0000 rw

0

22 rw

0

21 rw

0 rw

0 rw

0 rw

0 rw

0 rw

0

BIT

TYPE

RESET

Name

XBASE

Bits 31–0

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0

9 rw

0

8

XBASE

7 rw

0

0x0000 rw

0

6 rw

0

5 rw

0

4 rw

0

3 rw

0

2 rw

0

1 rw

0

0 rw

0

Table 17-12. MMA MAC X Base Address Register Description

Description

X Base Address

—Determines the base/start address of the X data buffer.

Writing 0 to this register will force the module to use the data stored in the cache when Cache_En bit is set.

17.3.3.2 MMA MAC X Index Register

MMA_MAC_XINDEX

BIT 31 30 29 28 27

MMA MAC X Index Register

26 25 24 23 22 21 20 19

Addr

0x00222204

18 17 16

TYPE

RESET r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

0x0000 r

0 r

0 r

0 r

0 r

0 r

0 r

0 r

0

BIT

TYPE

RESET

Name

Reserved

Bits 31–16

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0

9 rw

0

8

XINDEX

7 rw

0

0x0000 rw

0

6 rw

0

5 rw

0

4 rw

0

Table 17-13. MMA MAC X Index Register Description

Description

Reserved—These bits are reserved and should read 0.

3 rw

0

2 1 0 rw

0 rw

0 rw

0

17-16

MC9328MX1 Reference Manual

MOTOROLA

Name

XINDEX

Bits 15–0

Programming Model

Table 17-13. MMA MAC X Index Register Description (Continued)

Description

MAC X Index

—Determines part of the offset from the base address.

The X Address Index (actual access address) is equal to MMA_MAC_XBASE + contents of

MMA_MAC_XINDEX + [contents of MMA_MAC_XMODIFY + the number of iterations since initialization, the index last wrapped, or the last MMA_MAC_XCOUNT iterations (when the

X INDEX LOAD bit is set)].

17.3.3.3 MMA MAC X Length Register

MMA_MAC_XLENGTH

BIT 31 30 29 28

TYPE

RESET rw

0 rw

0 rw

0 rw

0

27 rw

0

MMA MAC X Length Register

26 rw

0

25 rw

0

24 23

COLUMN rw

0

0x0000 rw

0

22 rw

0

21 rw

0

20 rw

0

19

Addr

0x00222208

18 17 16 rw

0 rw

0 rw

0 rw

0

BIT

TYPE

RESET

Name

COLUMN

Bits 31–16

LENGTH

Bits 15–0

15 rw

0

14 rw

0

13 rw

0

12 rw

0

11 rw

0

10 rw

0

9 rw

0

8<