Tandy 1000 SL User manual

Tandy 1000 SL User manual
The T e c h n i c a l Reference Manual f o r t h e Tandy 1 0 0 0 S L d e s c r i b e s t h e
computer hardware components and t h e i r r e l a t i o n s h i p s t o one a n o t h e r , a s
w e l l a s t h e BIOS ( B a s i c I n p u t Output S e r v i c e s ) .
The i n f o r m a t i o n i n t h i s manual i s i n t e n d e d f o r hardware and s o f t w a r e
d e s i g n e r s , e n g i n e e r s , programmers, and anyone who r e q u i r e s a n
u n d e r s t a n d i n g o f t h e d e s i g n and o p e r a t i o n of t h e computer.
Timing diagrams f o r d e v i c e s used i n t h e system a r c h i t e c t u r e , Schematics,
s p e c i f i c a t i o n s , s w i t c h s e t t i n g s and jumpers, and a t h e o r y o f o p e r a t i o n
a r e provided f o r t h e f o l l o w i n g hardware s e c t i o n s :
Main Logic Board
Devices
Power S u p p l i e s
Keyboards
D i s k Drives
The Software s e c t i o n c o n t a i n s t h e following:
Quick Reference l i s t of s o f t w a r e i n t e r r u p t s
( f o r a l l d e v i c e , I / O , and system s t a t u s s e r v i c e s )
Keyboard ASCII and s c a n codes
An MS-DOS memory map
A
The i n f o r m a t i o n i n t h i s manual i s a supplement t o and based on a working
knowledge of t h e f o l l o w i n g l i t e r a t u r e :
The 1 0 0 0 S L I n s t a l l a t i o n and O p e r a t i o n Guide (Packaged w i t h t h
compute r )
The I n t e l iAPX 86/88/186/188 U s e r ' s Manual-Programmers
Reference. I n t e l o r d e r number 210911-003
The I n t e l iAPX 86/88/186/188 U s e r ' s Manual-Hardware Reference.
I n t e l o r d e r number 210912-001
AP-67 8086 System Design. I n t e l o r d e r number 230792-001
T h i s I n t e l l i t e r a t u r e may be o r d e r e d d i r e c t l y from I n t e l a t t h e f o l l o w i n
number: 1-800-549-4725
Tandy lOOOSL
Page Insertion Guide
Important Customer Note:
A gray stripe has been printed along the right edge of the
title page of each of the sections to facilitate your
finding the beginning of the section.
Also,
a tabbed divider for each section has been provided
for insertion at this point.
Exploded view: Insert at the end of the Assembly/Disassembly section
.
Foldout schematic pages: Insert at the end of the Main
Logic Board section
Schematics
C8000302 - Rev B
Sheets 1 of 7 thru 7 of 7
Schematic
C8000308 - Rev B
Sheet 1 of 1
Foldout PCB art: Insert after the Main Logic Board
schematics
Silkscreen
Layer 1 Component Side
Layer 2 GND Plane
Layer 3 + 5V Plane
Layer 4 Solder Side
1700378
-
Rev B
Foldout schematic page: Insert at the end of the 67
Watt Single Input Power Supply section
Schematic
Model No. 8790085
Foldout schematic page: Insert at the end of the 67
Watt Dual Input Power Supply section
Schematic
Model No. 8790084
Foldout keyboard art pages: Insert after the Fujitsu
Keyboard information in the Keyboard section
Keyboard Unit Assembly
Block Diagram
circuit Specification
circuit Specification
N86 0-47 03 4 0 01
4700
N86C-4700-0001
N86C-4700-0101
Foldout schematic page: Insert after the Fujitsu custom
IC Pin Signal sheet 2 of 3 in the Keyboard section
Schematic
Fujitsu Custom IC Pin Signals & Function
Sheet 3 of 3
Foldout TEAC schematic pages: Insert after the Section
3 - Maintenance portion of the Disk Drive section
PCBA Front Opt #N
Total Diagram
FD-55R
FD-55BR/FR/GR
Sheets 1 of 3 thru 3 of 3
PCBA MFD Control #N
FD-SsBR/FR/GR
Sheets 1 of 2 thru 2 of 2
Table Of Contents
Introduction
General Description
Specifications Summary
Optional Features
System Assembly/Disassembly (Including Exploded Views)
Main Logic Board
Introd uction
Switch Settings and Jumper Pin Configurations
Theory of Operation
8086 Microprocessor
8087 Numerical Math Coprocessor
Clock Generation
Command and Control Signal Generation
DRAM Control
Refresh Control
BIOS ROM Control
Reset Circuit
Wait State and Ready Logic
NMI Logic
8087 Control Logic
CPU Address Buffers
Data Buffers and Conversion Logic
1/0 Decode
Floppy Disk Controller
Interrupt Controller
video controller
Timer
Joystick Interface
Keyboard Interface
Sound Circuit
Additional Sound Features (DAC)
DMA Controller
RS232 Serial Port Interface
Parallel Printer Port Interface
Expansion Ports
System Expansion Bus
Expansion Bus Signal Description
Memory Map
1/0 Port Map of System
1/0 Port Map Summary
1
1
2
2
3
5
5
6
7
7
7
7
8
9
9
10
10
10
12
12
12
12
13
13
14
15
16
16
17
17
17
18
18
19
20
20
21
23
24
24
In t rod uc t io n
Introduction
General Description
The Tandym 1 0 0 0 SL i s m o d u l a r i n d e s i g n t o allow maximum
f l e x i b i l i t y i n s y s t e m c o n f i g u r a t i o n . The c o m p u t e r c o n s i s t s o f a
m a i n u n i t , a n d a d e t a c h a b l e k e y b o a r d w i t h c o i l e d c a b l e . The m a i n
u n i t i s s u p p l i e d w i t h o n e i n t e r n a l S f - i n c h 360K f l o p p y d i s k
d r i v e . The s t a n d a r d t y p e s o f m o n i t o r s u s e d w i t h t h e Tandy 1 0 0 0 SL
a r e t h e monochrome a n d t h e color RGB m o n i t o r . S i n c e t h e s e u n i t s
are m o d u l a r , you c a n p l a c e t h e m o n t o p o f t h e m a i n u n i t o r a t a n y
convenient location.
The Tandy 1 0 0 0 SL comes s t a n d a r d w i t h 384K o f s y s t e m RAM. An
o p t i o n a l 256K RAM c a n b e a d d e d o n t h e s y s t e m b o a r d t o e x p a n d t h e
memory t o a f u l l 640K b y t e s , t h e maximum RAM a l l o w e d by t h e
s y s t e m memory map.
Other f e a t u r e s i n c l u d e a p a r a l l e l p r i n t e r p o r t , a serial p o r t ,
t w o built-in joystick i n t e r f a c e s , a speaker f o r audio output, a
m i c r o p h o n e j a c k , a n d a h e a d p h o n e j a c k w i t h volume c o n t r o l .
1
S p e c i f i c a t i o n s Summary
8086 CPU r u n n i n g a t 8 MHz, 0 w a i t s t a t e , s w i t c h a b l e t o 4 MHz
S o c k e t f o r 8087 n u m e r i c a l c o p r o c e s s o r
384K b y t e s DRAM u p g r a d e a b l e t o 640K b y t e s ( 1 6 - b i t d a t a b u s )
4 M b i t BIOS ROM w i t h [email protected] a n d [email protected] ( 1 6 - b i t d a t a b u s )
Tandy 1 0 0 0 SL v i d e o c o n t r o l l e r t h a t s u p p o r t s :
128K b y t e s DRAM ( u s e d as s y s t e m a n d v i d e o memory)
a l p h a n u m e r i c mode
g r a p h i c s modes i n c l u d i n g :
1 6 0 X 200 1 6 - c o l o r
320 X 200 4 - C O l O r
320 X 200 1 6 - c o l o r
640 x 200 2 - c o l o r
640 X 200 4 - C O l O r
8237-5 DMA c o n t r o l l e r t h a t s u p p o r t s :
3 DMA c h a n n e l s
8-bit t r a n s f e r s
4 MHz c l o c k s p e e d
8259A i n t e r r u p t c o n t r o l l e r f o r 8 i n t e r r u p t s
8254 i n t e r v a l t i m e r t h a t s u p p o r t s :
system i n t e r r u p t timing
sound t i m i n g
Custom k e y b o a r d i n t e r f a c e c o n t r o l l e r
101-key Enhanced k e y b o a r d
Custom p a r a l l e l p r i n t e r p o r t
S e r i a l p o r t (RS-232-C)
Audio i n t e r f a c e c i r c u i t t h a t s u p p o r t s :
i n t e r n a l 8-OHM s p e a k e r
h e a d p h o n e j a c k w i t h u s e r a c c e s s i b l e volume c o n t r o l
microphone i n p u t
Joystick interface for two joysticks
Custom f l o p p y d i s k c o n t r o l l e r c i r c u i t t h a t s u p p o r t s :
5 f - i n c h 360K f l o p p y d i s k d r i v e s
3 3 - i n c h 720K f l o p p y d i s k d r i v e s
One 5 f - i n c h 360K f l o p p y d i s k d r i v e
Five 10" 8 - b i t expansion slots
Reset b u t t o n a n d s u p p o r t l o g i c
67-Watt power s u p p l y
-
.
-
-
-
-
-
.
Optional Features
.
Real-time clock w/battery
8087 n u m e r i c a l m a t h c o p r o c e s s o r
256K DRAM u p g r a d e ( 1 6 - b i t d a t a b u s memory)
S f - i n c h 360K f l o p p y d i s k d r i v e
3 3 - i n c h 720K f l o p p y d i s k d r i v e
Add-in h a r d d i s k d r i v e s
Hard d i s k c a r d ( 2 0 / 4 0 meg)
D i s p l a y a d a p t e r b o a r d s t h a t s u p p o r t mono, EGA, or o t h e r
s p e c i a l v i d e o modes
300, 1 2 0 0 , or 2400 baud modem b o a r d s
2
Assembly/Disassembly
System Assembly/Disassembly (Including Exploded Views)
The following instructions explain how the major subassemblies
are removed from the Tandy 1000 SL. Re-assembly of major subassemblies is accomplished by reversing the order of the removal
procedures.
1. Top Cover Removal
a. Remove the ( 2 ) screws from the side of the computer at the
rear.
b. Slide the cover forward enough to clear the power button,
volume knob, and disk drive eject button and off.
2.
5)-inch Floppy Drive Removal
a. Remove the top cover.
b. Unplug all cables from the disk drive.
c. Remove the ( 3 ) screws attaching the drive to the drive
mounting tower.
d. Slide the drive forward out of the drive mounting tower.
3 . Power Supply Removal
a. Remove the top cover.
b. Remove the rear panel by slightly bending the hooks on each
side near the bottom and rotating enough to clear the sheet
metal and then lift up.
c. Remove all cables from the main logic board and disk drives.
d. Remove the arm attached to the power supply switch.
e. Remove the ( 2 ) screws from the rear of the computer and (1)
screw from the side that secure the power supply to the rear
of the machine.
f. Slide the power supply up and out.
3
4 . Main L o g i c B o a r d Removal
a . Remove t h e t o p c o v e r .
b.
u n p l u g a l l c a b l e s and remove a l l t h e a d a p t e r b o a r d s from t h e
system.
c. Remove t h e power s u p p l y .
d . Remove t h e b a c k of t h e c h a s s i s by r e m o v i n g ( 2 ) screws a t t h e
rear o f t h e computer a n d p u l l i n g t h e b a c k o f t h e c h a s s i s t o
t h e rear a n d down t o clear t h e ( 3 ) h o o k s i n t h e bottom o f
t h e chassis.
e. Remove s p r i n g c l i p f r o m volume c o n t r o l k n o b p o s t .
f . Remove t h e (11) screws h o l d i n g t h e m a i n l o g i c b o a r d i n
place.
g. Remove t h e m a i n l o g i c b o a r d b y c a r e f u l l y p u l l i n g s t r a i g h t
back from under t h e d r i v e s u p p o r t and o u t of t h e c h a s s i s .
NOTE: WHEN REPLACING THE M A I N LOGIC BOARD, BE SURE THAT THE
VOLUME CONTROL KNOB POST SLIDES INTO THE VOLUME CONTROL
POT CORRECTLY.
4
PART
QTY.
1
5
5
4
4
1
1
11
4
4
1
1
1
3
1
4
1
1
1
2
1
1
1
1
1
2
1
2
1
4
1
2
1
1
3
1
2
2
2
1
1
1
4
DESCRIPTION
NUMBER
-
WELDMENT
CHASSIS
PANEL
OPTION SLOT
SCREW
#4-40 X 3/16
FOOT
#1661-0512
RIVET
P C BOARD
MAIN L O G I C
P C BOARD
FRONT & BACK (BREAK APART B D )
SCREW
#6-32 X 1/4
JACKNUT
#4-40 X 3/16
SHIELDING S T R I P
KNOB
VOLUME CONTROL
HAIRPIN
CLIP
CHASSIS
POWER S U P P L Y
SCREW
#6-32 X 5/16
POWER S U P P L Y
67 WATT
INT' L
DOM.
DOM.
SCREW - #6-32 X 5/16
DC HARNESS
SWITCH
POWER
SWITCH
POWER
INT'L
SCREW
M3 X 5 PPH
BUTTON
POWER
ACTUATOR - POWER SWITCH
RECEPTACLE
AC
HARNESS - AC
INT'L
HARNESS - AC
CAPACITOR
1000 P F D , 400V
TORROID
CORE F A I R R I T E
NUT
K E P S , #6-32
FAN
8 0 M M ; 12 VDC
SCREW
#lo T A P I T THREAD
ENDPLATE
POWER S U P P L Y
SCREW - #6-32 X 5/16
C H A S S I S - REAR
DISK DRIVE
5 1/4"
TEAC
SCREW - M 3 X 5 P P H
CABLE
SIGNAL
R A I L - 5 1/4" D R I V E
C L I P - GROUNDING, D R I V E
SCREW - #6
32 X 1/4 P H I L L I P S PAN HD
BRACKET
HARD CARD
#6-32 X 5/16
SCREW
SPEAKER W/CABLE
#6-32 X 5/16
SCREW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
8729709
8729562
8569333
8590179
8565014
8859024
8859110
8569326
8569341
8729658
8719624
8559080
8729690
8569339
8790084
8790085
8790091
8569339
8709857
8489111
8489112
8569293
8719625
8719620
8519246
8709868
8709873
8352106
8419030
8579004
8790424
8569301
8729691
8569339
8729693
8790136
8569293
8709856
8719603
8529064
8569098
8729704
8569339
8490013
8569339
MECHANICAL BILL OF MATERIAL
-
TANDY 1000 SL
TANDY 1000 SL FINAL ASSEMBLY
QTY.
1
1
2
5
1
4
1
1
1
1
1
1
1
1
1
1
1
1
1
PART
DESCRIPTION
NUMBER
PANEL - REAR
FRONT
BEZEL
P I N-GU ID E
SCREW
#6 X 3/8
CASE
TOP
#lo-24 UNC X 3/8"
SCREW
PHILLIPS OVAL HEAD MACHINE SCREW
BUTTON
RESET, FRONT
BUTTON
RESET, REAR
RESET BUTTON
SPRING
LABEL
SERIAL UL/FCC,
CORD
POWER 18/3 60/C
LABEL
SERIAL, CSA
NAMEPLATE
LABEL
SERIAL, INT'L
LABEL
SERVICE ADVISEMENT (6 LANG)
LABEL
CAUTION (6 LANG)
LABEL
EARTH GROUND INT'L
LABEL
VIDEO, MONOCHROME COMMAND
KEYBOARD ASSEMBLY
8719602
8719598
8739038
8569294
8729686
8569354
-
8719440
87 19 441
8739018
87 8 91644
8709057
87891645
8719618
87891646
87891571
87891572
87891253
87891648
Main Logic Board
Introduction
The main unit is the heart of the Tandy 1000 SL. It houses the
main logic assembly, system power supply, and floppy disk drive.
The main logic assembly is a large board mounted to the bottom of
the main unit and interconnected to the keyboard, power supply,
and disk drive by a series of cables.
The power supply is a 67W switching regulator type, designed to
provide adequate power capacity for a fully configured system
that has all the option slots in use.
The floppy disk drive uses 54-inch double-sided, double-density
diskettes to read, write, or store data. These are soft sector
diskettes. The disk drive assembly comes installed in the main
unit. All system programs, with the exception of the system
startup sequence, are stored on diskette.
5
S w i t c h S e t t i n g s a n d Jumper P i n C o n f i g u r a t i o n s
Main L o g i c B o a r d
Jumper
Function
Default
E1-E2
S e l e c t video I n t e r r u p t
on IRQ5
E2-E3
E2-E3
N o r m a l Video I n t e r r u p t
Sound I n p u t / O u t p u t
S a t e l l i t e Board
Jumper
Function
Default
El-E2
S e l e c t Direct L i n e
Audio I n p u t
E2-E3
E2-E3
S e l e c t M i c Audio
Input
6
Theory of Operation
8086 Microprocessor
The 8086 (U29) is a high-performance 16-bit microprocessor with
internal and external 16-bit data paths, one megabyte of memory
address space, and 64K of 1/0 address space. The 8086
communicates with the rest of the system via a 20-bit multiplexed
address/data/status bus and a command bus.
8087 Numerical Math Coprocessor
The 8087 (U21) performs high-speed arithmetic and logarithmic
functions and trigonometric operations that increase the
performance of an 8086 system. Performance increases are obtained
by the 8087's ability to perform math calculations faster than
the 8086, and also by executing math instructions in parallel
with the 8086.
Clock Generation
Clocks required by the system are generated by TTL oscillator Y2,
Y1 and the custom IC 8079024 (U41). There are two independent
clock circuits supplied by a Dual Oscillator Clock (Y2,Yl) from
which all other clocks, excluding video clocks, are derived.
The 24 MHz Clock is routed into the custom IC 879024, which
generates the output signal CPUCLK. The Clock Switch circuitry
required to toggle the 8086 Microprocessor between 8 MHz and 4
MHz mode, as well as the logic to prevent any short cycling
during a clock switch cycle, are implemented in the custom IC
879024 IC. If Bit 3 is asserted during an 1/0 write to Port 062
(hex), then the output signal CPUCLK operates the 8086 in 8 MHz
mode. If Bit 3 is negated low during an 1/0 write to Port 062
(hex), the output signal CPUCLK operates the 8086 in the 4 MHz
mode. When Reset is generated, the signal RESET is asserted and
defaults the Tandy 1000 SL to the 4 MHz mode.
The custom IC 879024 Chip also controls wait states to insert the
proper number of wait states required for a two clock mode of
operation. Zero to three wait states are inserted in all 8-bit
Memory and 1/0 cycles, in both 8 MHz and 4 MHz modes. These wait
states are separately programmable. During all 16-bit memory
cycles, either zero or one wait state is inserted in both the
8 MHz and 4 MHz modes. These values are programmable and will be
discussed later in the section "Wait State and Ready Logic".
7
Command a n d C o n t r o l S i g n a l G e n e r a t i o n
The command a n d c o n t r o l s i g n a l s r e q u i r e d f o r t h e Tandy
1 0 0 0 SL o p e r a t i o n are g e n e r a t e d by t h e 8079024 c u s t o m I C . The
command s i g n a l s are d e c o d e d f r o m t h e CPU s t a t u s s i g n a l s SOt h r o u g h S2- d u r i n g t h e TS c y c l e . The d e c o d e d s i g n a l s i n d i c a t e t h e
t y p e o f c y c l e t h a t i s t o b e e x e c u t e d (MEMR-, MEMW-, IOR-, IOW-,
INTA-). The c o n t r o l s i g n a l s CPUALE, BUSALE c o n t r o l t h e e x t e r n a l
l a t c h i n g o f a d d r e s s e s o n t o t h e b u s . D i r e c t i o n , e n a b l i n g of t h e
d a t a b u s b u f f e r s , a n d s t a r t a memory c y c l e i s d e t e r m i n e d i n t e r n a l
t o t h e 8079024 custom IC. The f o l l o w i n g t a b l e i n d i c a t e s t h e
d e c o d i n g o f t h e CPU s t a t u s s i g n a l s .
S1-
SO-
0
0
0
1
1
0
0
1
0
0
0
1
1
1
1
1
SO0
1
0
1
0
1
0
1
Type of Bus C y c l e
I n t e r r u p t Acknowledge
1/0 Read
1/0 W r i t e
Halt
Code Access
Memory Read
Memory Write
None: I d l e
CPU S t a t u s S i g n a l D e c o d i n g .
A0 a n d BHE- are d e c o d e d t o d e t e r m i n e t h e d a t a t r a n s f e r w i d t h t o
and f r o m t h e CPU. The f o l l o w i n g t a b l e shows t h e d a t a t r a n s f e r
w i d t h d e p e n d i n g o n t h e s t a t e o f A0 a n d BHE-.
BHE-
A0
W i d t h of Data T r a n s f e r
0
0
1
1
0
1
0
1
Word T r a n s f e r
Byte T r a n s f e r D8
B y t e T r a n s f e r DO
N o t Used
-
-
D15 ( o d d a d d r e s s )
D7 ( e v e n a d d r e s s )
Data T r a n s f e r W i d t h Decode.
8
DRAM C o n t r o l
The CPU a d d r e s s d e c o d e f o r t h e Dynamic Random Access Memory
(DRAM) a r r a y i s g e n e r a t e d by t h e 8079024 c u s t o m ( U 4 1 ) . T h e s e
s i g n a l s are l a t c h e d b y ALE i n t e r n a l l y t o t h e 8079024 c u s t o m I C
a n d h e l d f o r t h e c o m p l e t e c y c l e . The a d d r e s s d e c o d e s i g n a l s are
RASO-, RAS1-, RAS2-, RAS3-, a n d CAS-. Memory c o n f i g u r a t i o n s
s u p p o r t e d by t h e Tandy 1 0 0 0 SL a r e 256K, 512K, o r 640K b y t e s ( i n
a d d i t i o n t o 128K of v i d e o memory). The f o l l o w i n g t a b l e shows t h e
d i f f e r e n t o p t i o n s a v a i l a b l e o n t h e 8079024 c u s t o m I C .
Memory
Option
0
1
2
3
*
MCONFIGl MCONFIGO
0
0
1
1
0
1
0
1
System
Memory
T o t a l System
Memory *
256K
512K
512K
640K
384K
64 OK
640K
768K
Note: T o t a l s y s t e m memory i n c l u d e s 128K of v i d e o memory.
Memory O p t i o n 0 i s t h e power u p d e f a u l t .
Memory c o n f i g u r a t i o n s .
The s i g n a l s WEL- a n d WEH- p r o v i d e w r i t e c o n t r o l . F o r a 1 6 - b i t
access, b o t h are a s s e r t e d a t t h e same t i m e a n d are c o n t r o l l e d by
MEMW- (memory w r i t e ) . F o r a n 8 - b i t access, t h e a p p r o p r i a t e s i g n a l
i s asserted a c c o r d i n g t o t h e s t a t e o f A0 ( h i g h b y t e o r l o w b y t e ) .
Refresh Control
R e f r e s h t i m i n g is d e r i v e d i n t e r n a l t o t h e 8079024 c u s t o m I C (U41)
a n d p r o v i d e s a 5 1 2 c o u n t , 8 msec, RAS o n l y r e f r e s h f o r i n t e r n a l
memory, a n d a 256 c o u n t , 4 msec, RAS o n l y r e f r e s h f o r t h e b u s .
9
BIOS ROM Control
The 8079024 custom IC (U41) provides the CPU address decode used
for the ROM select. The signals generated are called ROMCSO- and
ROMCSl (ROM Chip Select). The 8079024 custom IC then generates
the ROM Page Selects (RPO-RP4) and Chip Enable for the BIOS ROMs
CU16 and CU17. These outputs are decoded from Address Bits ~ 1 6 A19 and IODO-IOD4. RPO-RP4 may be programmed by writing to Port
4. The appropriate ROM page selects are
FFE8 hex Bits 0
multiplexed with 1/0 decodes, and appear on DECO-DEC2 during a
memory address cycle in the ROM area.
-
Reset Circuit
The 8079024 custom IC (U41) controls the system reset required
either to initialize the complete system after power-up or to
reboot. The reset output signals, RSTIN-, is active low and
generated when a power-up condition is detected or when the reset
button on the front of the computer is pressed.
The RSTIN- signal is supplied to the 8079024 custom IC which
produces the RESET signal. The RESET signal is used as a general
system reset. The 8079024 custom IC (U41) also internally
controls the RESET signal to meet the requirements of the 8086
during a detected shutdown condition.
Wait State and Ready Logic
Wait state control is implemented internally to the 8079024
custom IC. The function of the wait state control logic is to
match the speed of the various devices in the Tandy 1000 SL to
the speed of the 8086 CPU. A programmable wait state generator is
contained within the 8079024 custom IC and can be accessed by
writing to Port FFE9 hex. The following is a table of
programmable wait states and their default values.
10
P o r t FFE9h
B i t ( s1
0
Default
0
Description
I n t e r n a l Memory W a i t States
0 = 0 w a i t states
1 = 1 w a i t states
E x t e r n a l Memory W a i t S t a t e s
00 = 0 w a i t states
0 1 = 1 w a i t states
1 0 = 2 w a i t states
11 = 3 w a i t s t a t e s
I/O
3,4
5
0
Cycle W a i t
00 =
01 =
10 =
11 =
States
0 wait
1 wait
2 wait
3 wait
states
states
states
states
DMA C y c l e W a i t S t a t e s
o = W r i t e Strobe w a i t
1 = S t a n d a r d 8137 write
Strobe
6
0
I n t e r n a l V i d e o W a i t States
o = 0 w a i t states
1 =1 w a i t s t a t e s
7
1
OSCIN S e l e c t
o = 2 8 . 6 3 6 3 6 MHz
1 = 24 MHz
Programmable W a i t S t a t e C o n t r o l
A n o t h e r m e t h o d i s c o n t r o l l e d by t h e d e v i c e b e i n g accessed, u s i n g
t h e IOCHRDY s i g n a l i n p u t t o t h e 8 0 7 9 0 2 4 c u s t o m I C . I f a d e v i c e
r e q u i r e s a d d i t i o n a l w a i t s t a t e s w i t h i n t h e b u s c y c l e , t h e device
s h o u l d n e g a t e IOCHRDY l o w u n t i l i t c a n s e r v i c e t h e b u s c y c l e .
A f t e r t h e r e q u i r e d number of w a i t s t a t e s h a v e b e e n i n s e r t e d , t h e
d e v i c e s h o u l d assert IOCHRDY, c a u s i n g t h e READY o u t p u t of t h e
8079024 c u s t o m I C t o b e a s s e r t e d h i g h , w h i c h t e l l s t h e CPU t o
terminate t h e cycle.
(Note: IOCHRDY s h o u l d n o t b e h e l d l o w f o r l o n g e r t h a n 1 5 u s e c ) .
11
NMI Logic
In the Tandy 1000 SL, the Non-Maskable Interrupt (NMI-1 indicates
an 1/0 error condition, or Numerical Math Coprocessor 8087 error
condition. Both error conditions are being generated internal to
the 8079024 custom IC.
8087 control Logic
The 8087 Numerical Coprocessor is connected to the 8086 address
and data lines in parallel. The 8087 will monitor the 8086 CPU
status (SO-S2) and Queue status (QSO-QSl) in order to decode
instructions in synchronization with the CPU. For
resynchronization, the 8087 NPBUSY signal is used to tell the CPU
that the 8087 is executing an instruction. The 8087 also has the
capability of informing the 8086 of an error or exception by
using the NPINT signal. This signal is sent to the 8079024 custom
IC which then generates the proper codes to the 8086. The 8087
signal to gain control of the bus for data
will use the RQ/GTOtransfers.
CPU Address Buffers
The 8079024 custom IC provides the buffering of the address lines
to the system. AO-Al9 are buffered and latched for the expansion
bus slots and 1/0 peripherals. ALE is used to latch AO-A11
internal to the 8079024 custom IC and CPUALE is used to latch
A12-Al9 externally. The addresses are held for the complete bus
cycle. AO-A19 are also used to address the BIOS ROMS and DRAM/DMA
Control. The multiplexed address lines MAO-MA8 are also generated
and buffered to the DRAM memory by the 8079024 custom IC.
Data Buffers and Conversion Logic
The 8079024 custom IC provides the data buses, buffers, and
drivers for DO-Dl5 to the system. Two data buses are generated,
IODO-IOD7 for the expansion bus slots, and ADO-AD15, which is
routed to the 8086 CPU, 8087 Coprocessor data bus, ROM, and DRAM.
The direction and control of the data buffers are provided
internal to the 8079024 custom IC. Conversion logic is also
implemented in the 8079024 custom IC. This conversion logic
allows data to be transferred from the lower to upper or upper to
lower data byte to meet the requirements of the CPU or receiving
device.
12
1/0 Decode
The 8079024 custom IC accomplishes the 1/0 Address decoding. This
IC provides all the necessary chip select signals to the system.
The DECO-, DEC1-, and DEC2- output signals of the 8079024 custom
IC are encoded device select lines that are fed directly to the
KFIT custom IC (u30) and 8079021 custom IC ( ~ ~ 4 0 1in
, which 1/0
address decoding is generated.
Floppy Disk Controller
The on-board Floppy Disk Controller (FDC) and KFIT custom IC
(U30) interface the system to the Floppy Disk Drive (FDD). Up to
two internal Sf-inch 360K or one 5)-inch and one 33-inch FDDs can
be accommodated.
The FDC circuit can be organized into the following subsections:
.
uPD765A FDC Chip
System Interface
Clock Generation
Precompensation
Data Separator
Disk Drive Interface
uPD765A Chip. The uPD765A FDC chip (EU4) integrates most of the
control logic necessary to:
.
.
.
interface the serial bit stream to or from the FDD to the
parallel bus of the system
implement the commands necessary to operate the FDD
maintain information about the status of the FDD
During a read or write data operation to the FDD, the FDC chip
generates a DMA request for a byte transfer to or from memory.
The FDC chip continues to generate DMA requests until the
preprogrammed amount of data is transferred as signified by
generation of a Termination Count (DMATC) Signal. After the DMATC
is reached, the FDC chip generates an interrupt to the system
through INT so that status and result data can be serviced.
System Interface. Various ICs, along with the KFIT custom IC,
latch and buffer data to and from the system. A DOR Write
(Digital Output Register) is generated on an 1/0 write to Port
3F2 (hex). This signal latches the data byte that is bit defined
as the Drive Select, DSO-, DS1-, and DS2-, Motor On, MTRON-, DMA,
(FDCDRQ), Interrupt Request (FDCINT), and a reset signal
(FDCRST-1 to the FDC controller U12.
13
Clock Generation. The FDC Support IC (u18) generates all clocks
required by the Floppy Disk circuit. These clocks are derived
from a 16 MHz input signal. FDCCLK, required by the FDC
Controller (U12), is derived by dividing the 16 MHz clock by 4.
The resulting 4 MHz clock is also used as a delay counter for the
DMA request signal DRQ as well as a reference clock for the write
precompensation circuit. The 4 MHz clock also generates a 250
nanosecond pulse at a frequency of 500 KHZ. The 500 KHz signal is
used as a write clock for the FDC Controller.
Precompensation. The precompensation circuit is implemented
internally to the FDC Support IC (U18). The write data bit can be
shifted either early or late in the serial bit stream, depending
on the requirements of the Floppy Disk Drive. This function is
programmable and controlled by the FDC IC signals PSO and PS1.
Data Separator. The FDC Support IC (u18) also contains the data
separator circuit. The data separator recovers the clock and data
signals from the serial bit stream of the Floppy Disk Drive. The
FDC Support IC supports only MFM or Double-density mode.
Disk Drive Interface. All FDC outputs to the FDD are driven by
high current 7414 SCHMITT trigger buffers or 7416 open collector
inverters. All FDC inputs from the FDD are buffered by 74HCT14
SCHMITT triggered inverters. The inputs are pulled up on-board by
1K terminating resistors. All outputs should be terminated on the
last FDD by 1K resistors.
Interrupt Controller
The Interrupt Controller is contained in the KFIT custom IC (U30)
and supplies the maskable interrupt input to the CPU. The KFIT
custom IC has eight interrupt inputs controlled through software
commands. It can mask (disable) and prioritize (arrange priority)
to generate the interrupt input to the CPU. The eight interrupts
are assigned as follows:
#5
Timer Channel 0
Keyboard
Interrupt on the Bus
Interrupt on the Bus
Interrupt on the Bus
Vertical Sync/mC
#6
#7
Floppy Disk Controller
Printer/Sound/DMA
#O
#1
#2
#3
#4
14
Software Timer
Keyboard Code Received
Optional Bus Interrupt
Modem (COM2)
RS-232 (COM1)
Hard Disk Controller/
Video Vertical sync
Optional BUS Interrupt
Optional Bus Interrupt
Interrupts 0 and 1 are connected to system board functions as
indicated in the chart. Interrupts 2-7 are connected directly to
the Expansion Bus, with the normal assigned functions listed in
the chart.
Video Controller
The next major block of the Tandy 1000 SL is the video interface
circuitry. This custom part contains all the logic necessary to
generate an IBM-compatible color video display. The video
interface logic consists of the 100-pin custom video circuit
(U26), four 64K X 4 DRAMS (U6, U7, U8, and U9), a 74LS273 latch
(U141, a 16K X 8 character ROM, and associated logic for
generating RGBI or Monochrome video.
The Tandy 1000 SL video interface circuitry controls 128K of
memory. This DRAM is shared by the CPU and the video. Normally,
the video requires only 16K or 64K for the video screen, and the
remainder of the 128K is available for system memory use.
The Tandy 1000 SL video interface custom circuit is composed of a
6845 equivalent design, dynamic RAM address generation/timing,
and video attribute controller logic.
Normal function of the video interface custom circuit is as
follows. After the 6845 is programmed with a correct set of
operating values, a 6:l multiplexer generates the address inputs
to the dynamic RAMS. This MUX switches between video (6845)
address and CPU address as well as between row and column
address. Also, the video interface chip provides the RAM timing
signals and generates a wait signal, VIDWT-, to the CPU for
proper synchronization with the video RAM access cycles.
The outputs from the RAM chips are only connected to the video
interface custom circuit, so all CPU read/write operations are
buffered by this part. During a normal display cycle, video data
from the RAM chips is first latched in the Video Attribute latch
and the Video Character latch. The video interface requires a
memory organization of 64K X 16 and latches 16 bits of memory
during each access to RAM. From the output of the two latches,
the data is supplied to the character ROM for the alpha modes or
to the shift registers for the graphics modes. A final 2:l MUX
switches between foreground or background in the alpha modes.
From the 2:l MUX, the RGBI data is combined with the PC color
select data and latched in the Pre-Palette latch. This latch
synchronizes the RGBI data before it is used to address the
Palette. The Palette mask MUX switches between incoming RGBI data
and the Palette address register. During a CPU write to the
Palette, this address register selects one of the 16 Palette
locations. Also, the Palette mask MUX allows any of the input
RGBI bits to be set to zero.
15
The Palette allows the 16 colors to be remapped in any desired
organization. Normally, the Palette is set for a 1:l mapping (red
= red, blue = blue, and so on) for PC compatibility. However,
instantly changing the on-screen colors is a powerful tool for
animation or graphics programs.
After the Palette, the RGBI data is resynchronized in the Post
Palette register. The final logic before the RGBI data is
buffered off the chip in the Border MUX. This MUX allows the
Border to be replaced with any color selected by the border color
latch. This latch is normally disabled in PC modes, but it is
used in all PC jr modes.
Timer
The final Tandy 1000 SL function other than 1/0 is the timer
found in the KFIT custom IC (U30). This part is composed of three
independent programmable counters. The clock for all three
counters is 1.1931 MHz, which is derived from 14.318 MHz/12.
Counters 0 and 1 are permanently enabled. Counter 2 is controlled
by port Hex 0061, Bit 0. Counter 0 is connected to system
interrupt 0 and is used for software timing functions. Counter 1
is used for refresh function timing. Counter 2 is connected to
the sound circuit and its output can be read at port Hex 0062,
Bit 5.
Joystick Interface
The joystick interface contained in the 8079021 custom IC (U40)
converts positional information from hand-held joysticks (1 or 2)
into CPU data. Each joystick provides one or two push-buttons and
X, Y position for a total of four bits each. Two joysticks can be
used.
The joystick handle is connected to two potentiometers mounted
perpendicular to each other; one for X position, one for Y
position. Through the cable, the main logic board applies +5 VDC
to one side and ground to the other of the pots. The pot wiper is
the position signal: a voltage between 0 and +5 VDC. This signal
is applied to one input of a comparator HU2. The other comparator
input is the reference signal (a ramp between 0.0 to +5.0 volts).
When the position signal is equal to or less than the reference
signal, the comparator output goes true. This comparator output
is the X or Y position data bit. The ramp is reset to 0.0 VDC
whenever an 1/0 Write is made at Port 200/201 Hex. The joystick
information is "read" by the CPU at Port 200/201 Hex through U40.
16
Keyboard I n t e r f a c e
The n e x t 1/0 f u n c t i o n of t h e Tandy 1 0 0 0 SL i s t h e K e y b o a r d
i n t e r f a c e c u s t o m c i r c u i t , p a r t o f t h e KFIT c u s t o m I C . The h e a r t
o f t h i s c u s t o m p a r t i s s e v e r a l read/write registers t h a t are u s e d
t o c o n t r o l t h e keyboard i n t e r f a c e logic. For t h e i n t e r f a c e t o
t h e k e y b o a r d c o n n e c t o r , a 1 6 4 - t y p e s h i f t register i s u s e d t o load
t h e s e r i a l d a t a a n d a l l o w t h e CPU t o r e a d i t as 8 p a r a l l e l b i t s .
Sound C i r c u i t
The s o u n d c i r c u i t i s o n e o f t h e f i v e 1/0 f u n c t i o n s o f t h e Tandy
1 0 0 0 SL. The c i r c u i t p r o v i d e s s o u n d o u t p u t f o r t h e i n t e r n a l
s p e a k e r as w e l l as f o r a n e x t e r n a l s o u n d c i r c u i t .
The main s o u r c e o f s o u n d i n t h e Tandy 1 0 0 0 SL i s t h e 8 0 7 9 0 2 1
c u s t o m I C ( U 4 0 ) . I t c o n t a i n s t h e e q u i v a l e n t o f a 76496 c o m p l e x
sound g e n e r a t o r . T h i s d e v i c e h a s t h r e e t o n e g e n e r a t o r s and one
w h i t e n o i s e g e n e r a t o r . Each t o n e g e n e r a t o r c a n b e programmed f o r
frequency and a t t e n u a t i o n . A l s o , t h i s d e v i c e h a s an a u d i o i n p u t
p i n c o n n e c t e d t o t h e g a t e d o u t p u t o f timer c h a n n e l 2. T h i s a u d i o
i n p u t s i g n a l is mixed w i t h t h e sound g e n e r a t o r s i g n a l a n d
supplied to t h e audio output pin.
The o u t p u t o f t h e 76496 e n a b l e s P o r t 6 1 , B i t 4, w h i c h t u r n s o f f
t h e a u d i o s i g n a l t o t h e s p e a k e r , headphone j a c k s , a n d e x t e r n a l
a u d i o o u t p u t . The o u t p u t o f t h e 76496 i s r o u t e d t o a u d i o
a m p l i f i e r s HU3 f o r t h e e x t e r n a l a u d i o o u t p u t a n d HU4 f o r t h e
i n t e r n a l s p e a k e r a n d h e a d p h o n e j a c k s . The volume o f t h e i n t e r n a l
s p e a k e r c a n b e a d j u s t e d by a u s e r - a c c e s s i b l e volume c o n t r o l
(HR14). When t h e h e a d p h o n e j a c k i s u s e d , t h e i n t e r n a l s p e a k e r i s
disabled
.
A d d i t i o n a l Sound F e a t u r e s (DAC)
An a d d i t i o n a l f e a t u r e o f t h e Tandy 1 0 0 0 SL s o u n d c i r c u i t r y i s a
D i g i t a l t o A n a l o g C o n v e r t e r ( D A C ) . The DAC i s c o n t r o l l e d by
r e a d / w r i t e P o r t s C4-C7. The DAC c a n b e u s e d t o c o n v e r t p r e recorded d i g i t a l s o u n d , v o i c e , o r m u s i c i n t o a n a l o g a u d i o o u t p u t .
A m i c r o p h o n e j a c k a n d a u d i o i n p u t c i r c u i t r y are p r o v i d e d f o r
r e c o r d i n g a n a l o g s o u n d , v o i c e o r m u s i c , a n d c o n v e r t i n g it t o
d i g i t a l d a t a . B i t programming d a t a f o r t h e s e p o r t s i s a v a i l a b l e
i n t h e data s h e e t s on t h e 8079021 custom I C l o c a t e d i n t h e
"Devices" s e c t i o n o f t h i s manual.
17
DMA Controller
The major components of the Direct Memory Access (DMA) circuit
consists of an 8237A-5 equivalent DMA controller, DMA control
logic, and a bi-directional address buffer internal to the
8079024 custom IC.
A DMA Operation. When a DMA operation is requested by software or
by a peripheral through a DREQ line, the 8079024 custom IC
initiates a Bus Hold Request to the 8086 CPU. The 8079024 custom
IC arbitrates the CPU Hold Request from the internal DMA
controller to the CPU.
when the CPU acknowledges the Hold request, the CPU control,
address, and data lines are tri-stated. The 8079024 custom IC
controls the direction and enables the memory or peripheral
address and data buses that correspond to the requested DMA
operation.
During the DMA operation, the 8237A-5 internal to the 8079024
custom IC acts as the bus master and, along with the associated
logic, generates all bus control signals and address and data
signals. The DMA transfers continue for the number of counts and
to the destination address that was previously programmed into
the DMA registers. See the device data sheet and the 1/0 map for
complete descriptions of the registers, their locations, and
their functions.
1/0 devices can extend the DMA bus cycle by controlling the
IOCHRDY signal of the expansion bus. Setup times must be observed
for IOCHRDY to be recognized.
RS-232 Serial Port Interface
The RS-232 Port is a single-channel, asynchronous communications
port. The heart of the serial port is the 8079021 custom IC (U40)
that functions as a serial data input/output interface. It
performs serial-to-parallel conversion on data characters
received from a peripheral device or modem and parallel-to-serial
conversion on data characters received from the CPU.
18
Status information reported includes the type and condition of
the ACE'S transfer operations as well as any error conditions
detected during serial data operations. The 8079021 custom IC
includes a programmable Baud Rate Generator that allows operation
from 50 to 9600 Baud. The 8079021 custom IC is supplied with a
clock of 24 MHz from the main Crystal Oscillator. The 8079021 can
be tailored to the user's requirements by being able to remove
start bits, stop bits, and parity bits. It supports 5 , 6 , 7, or 8
data bit characters with 1, 13, or 2 stop bits. Diagnostic
capabilities provide loopback functions of transmit/receive and
input/output signals.
The 8079021 custom IC serial port is programmed by selecting the
1/0 address 3F8 - 3FE hex and writing data out to the port.
Address Bits AO, Al, and A2 are used to define the modes of
operation by selecting the different registers to be programmed
or read. One interrupt is provided to the system from IRQ4.
Parallel Printer Port Interface
The final 1/0 interface of the Tandy 1000 SL is the Printer
Interface contained in the 8079021 custom IC (U40). This part
supplies all the signals required to interface to a typical
parallel printer. These signals are 8 data out lines, plus
various handshake control signals. Also, the printer interface
generates an interrupt to the CPU if enabled.
19
Expansion Ports
System Expansion Bus
This section identifies the 1/0 interface requirements for the 8bit, PC-compatible option cards. Each of the five slots has a 62pin connector socket.
The following connector pin assignment is used on the PC option
slots; this connector socket has 62 pins.
Pin
-
I/O
Signal Name
pin
-
A1
A2
A3
A4
A5
NMIIOD7
IOD6
IOD5
IOD4
I
I/O
I/O
I/O
I/O
B
B
B
B
B
A6
A7
A8
A9
A10
IOD3
IOD2
IODl
IODO
IOCHRDY
I/O
I/O
I/O
I/O
I
B 6
B 7
B 8
B 9
B10
DRQ2
-12v
N/C
+12v
GND
POWER
GROUND
A11
A12
A13
A14
A15
HLDA
A1 9
A18
A17
A16
0
0
0
0
0
B11
B12
B13
B14
B15
MEMWMEMRIOWIORDACK3-
0
0
0
0
0
A16
A17
A18
A19
A20
A15
A1 4
A13
A1 2
A11
0
0
0
0
0
B16
B17
B18
B19
B20
DRQ3
DACKIDRQ1
REFRSHBCPUCL
0
0
A21
A22
A23
A24
A25
A10
A9
A8
A7
A6
0
0
0
0
0
B21
B22
B23
B24
B25
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
I
I
I
I
I
A26
A27
A28
A29
A30
A31
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
B26
B27
B28
B29
B30
B31
DACK2DMATC
BUSALE
+5v
14MHz
GND
0
0
0
20
1
2
3
4
5
I/O
Signal Name
GND
RESET
+5 v
IRQ2
-5V
GROUND
0
POWER
I
POWER
I
POWER
I
0
I
POWER
0
GROUND
Expansion Bus Signal Description
The following signal descriptions for the System 1/0 Bus are for
PC bus-compatible option cards. Note that all signal lines are
TTL compatible levels and that 1/0 adapters should be designed
with a maximum of two low power Shottky (LS) loads per line.
BCPUCLK (B20). BCPUCLK is the System clock and has a period of
125x1s in 8 MHz mode, or 25011s in 4 MHz mode. It has a 50% duty
cycle and is used only for synchronization with the CPU. It is
not intended for uses requiring a fixed frequency.
A0 through A19 (A12-A31). These lines are 20 address bits used to
address memory and 1/0 devices within the Tandy 1000 SL. They are
gated on the system bus when the BUSALE signal is high and are
latched on the falling edge of the BUSALE signal. Generation of
these signals is accomplished by the CPU or a DMA controller. AOA19 are active high.
BUSALE (B28). BUSALE is a Buffered Address Latch Enable generated
by the CPU control IC. It is used to latch valid addresses from
the CPU, and can be used by an I/O board to indicate a valid CPU
address, in conjunction with HLDA. BUSALE is active high.
HLDA (All). HLDA is an Address Enable signal used to remove the
CPU and other devices from the bus to allow DMA transfers to take
place. During HLDA active, the DMA controller has control of the
address bus, the data bus, the READ command lines, and the WRITE
command lines. HLDA is active high.
IODO
Bits
bus.
most
through IOD7 (A2-A9). These signals are the data bus 1/0
0 through 7 from the CPU to memory and 1/0 devices on the
IODO is the least significant bit (lsb), and IOD7 is the
significant bit (msb).
BRESET (B2). BRESET is used to reset or initialize the expansion
logic during power-up time, line voltage outage, or when the
Reset switch on the front panel is pressed. BRESET is active
high.
NMI- (All. This signal indicates an uncorrectable system error
when active. The NMI- signal provides the system board with
parity information about memory or devices on the bus. NMI- is
active low.
IOCHRDY (A10). This signal is used to lengthen 1/0 or memory
cycles when driven low by the active device. (This signal should
not be held low more than 15 microseconds.) Any slow device using
this line should drive it low immediately upon detecting its
valid address and a READ or WRITE command. See the timing diagram
for setup times. IOCHRDY is active high (Ready condition).
21
IRQ2 through IRQ7 (B4, B21-B25). These signals are used to tell
the CPU that an 1/0 device needs attention. The Interrupt
Requests are prioritized with IRQ2 having the highest priority
and IRQ7 the lowest. An Interrupt Request is generated when any
IRQ signal is driven high and held high until the CPU
acknowledges the interrupt.
IOR- (B14). IOR- is a read signal that instructs an 1/0 device to
drive its data onto the data bus (IODO-IOD7). This line can be
driven by the CPU Control IC or by the DMA controller. IOR- is
active low.
IOW- (B13).
to read, or
line can be
controller.
IOW- is a write signal that instructs an 1/0 device
latch, the data from the data bus (IODO-IOD7). This
driven by the CPU Control IC or by the DMA
IOW- is active low.
MEMR- (B12). MEMR- is a read signal that instructs a memory
device to drive its data onto the appropriate data bus (IODOIOD7). This line can be driven by the CPU Control IC or by the
DMA controller through the CPU Control IC. MEMR- is active low.
MEMW- (Bll). MEMW- is a write signal that instructs a memory
device to read, or latch, the data from the appropriate data bus
(ADO-AD15 for 16-bit memory, IODO-IOD7 for 8-bit memory). This
line can be driven by the CPU Control IC or by the DMA controller
through the CPU Control IC. MEMW- is active low.
DRQ1, DRQ2, and DRQ3 (B18, B6, B16). These lines are
asynchronous DMA requests by peripheral devices to gain DMA
service. They are prioritized with DRQl having the highest
priority, DRQ2 next, and DRQ3 lowest. A DMA request is generated
by driving a DRQ line active high and holding it until the
corresponding DACK (DMA acknowledge) signal goes active. DRQ1,
DRQZ, and DRQ3 perform only 8-bit transfers. All DRQ lines are
active high.
DACK1-, DACK2-, and DACK3-, B17, B26, B15). These lines are DMA
acknowledge signals used to acknowledge DMA requests DRQ1, DRQ2,
and DRQ3. All DACK signals are active low.
REFRSH- (B19). This signal is used to indicate a refresh cycle
that can be used by a memory board to refresh Dynamic memory.
REFRSH- is active low and 4 cycles are generated every 62.5 usec.
DMATC (B27). DMATC is a signal that provides a pulse when the
terminal count for any DMA channel is reached. DMATC is active
high.
14MHz (B30). 14 MHz is an oscillator signal that is a high-speed
clock with a 70 nanosecond period (14.31818 megahertz). It has a
50% duty cycle.
22
Memory Map
Add ress
Name
A l l o c a t e d Function
00000-7FFFF
512K System RAM
System Memory
80000-9FFFF
128K System/Video
System Memory and
Video D i s p l a y Memory
o r System Memory
RAM
A0000-BFFFF
128K Video RAM
Reserved f o r
Graph i c s
D i s p l a y Memory
COOOO-DFFFF
128K Expansion
Reserved f o r
Above Board
Memory
EOOOO-FFFFF
128K BIOS ROM
23
Reserved For BIOS
1/0 P o r t Map of S y s t e m
1/0 P o r t Map Summary
Block
Usage
Function
0000-001F
0020-003F
0040-00 5F
0060-007F
0 080-0 0 9F
o OAO- o OBF
0OCO 0ODF
o OEO-OOFF
0100-01FF
0200-020F
0 2 10-0 2 F7
02F8-02FF
0 300-0 31F
0320-032F
0330-036F
0 370-0 3 7 7
0378-037F
0 38 0-0 3 CF
0 3DO-0 3DF
0 3EO-0 3EF
0 3FO-0 3F7
0 3F8-0 3FF
0 4 0 O-FFE7
FFE8-FFEF
0000-001F
0020-0027
0040-0047
0060-006F
0080-009F
DMA F u n c t i o n
Interrupt Controller
T i mer
PIO F u n c t i o n
DMA P a g e R e g i s t e r
NMI- Mask R e g i s t e r
Sound G e n e r a t o r
Numerical c o p r o c e s s o r
Re served
Joystick Interface
Reserved
Serial P o r t S e c o n d a r y (COM2)
Reserved
Hard D i s k C o n t r o l l e r ( o p t i o n a l )
R e ser v e d
Floppy Disk C o n t r o l l e r 2 ( o p t i o n a l )
P r in t e r
Reserved
-
0OAO
0 OCO- 0 0 C7
0OEO-0 OFF
0200-0207
-
0 2F8 0 2 FF
0370-0377
0378-037F
03DO-03DF
03FO-03F7
03F8-0 3FF
system video
Reserved
Floppy Disk C o n t r o l l e r 1
S e r i a l P o r t P r i m a r y (COM1)
N o t Us a b 1e
S y s t e m Programming O p t i o n s
24
Address
Description
0000
DMA C o n t r o l l e r
IOW-
= 0:
C h a n n e l 0 Base a n d C u r r e n t A d d r e s s
I n t e r n a l F l i p / F l o p = 0: Write AO-A7
I n t e r n a l F l i p / F l o p = 1: W r i t e A8-Al5
IOR- = 0: C h a n n e l 0 C u r r e n t Address
I n t e r n a l F l i p / F l o p = 0: Read AO-A7
I n t e r n a l F l i p / F l o p = 1: Read A8-Al5
0001
DMA C o n t r o l l e r
IOW-
= 0: C h a n n e l 0 Base a n d C u r r e n t Word C o u n t
I n t e r n a l F l i p / F l o p = 0: W r i t e WO-w7
I n t e r n a l l ? l i p / F l o p = 1: Write AW-W15
I O R - = 0:
C h a n n e l 0 C u r r e n t Word C o u n t
I n t e r n a l F l i p / F l O p = 0: Read WO-w7
I n t e r n a l F l i p / F l o p = 1: Read W8-Wl5
0002
DMA C o n t r o l l e r
IOW-
= 0: C h a n n e l 1 B a s e a n d C u r r e n t A d d r e s s
I n t e r n a l F l i p / F l o p = 0: write A O - A ~
I n t e r n a l F l i p / F l o p = 1: write A8-Al5
IOR-
= 0: C h a n n e l 1 C u r r e n t ' A d d r e s s
I n t e r n a l F l i p / F l o p = 0: Read A O - A ~
I n t e r n a l F l i p / F l o p = 1: Read A 8 - ~ 1 5
0003
DMA C o n t r o l l e r
IOW-
= 0:
C h a n n e l 1 Base a n d C u r r e n t Word C o u n t
I n t e r n a l F l i p / F l o p = 0: W r i t e WO-w7
I n t e r n a l F l i p / F l o p = 1: Write AW-Wl5
IOR-
= 0: C h a n n e l 1 C u r r e n t Word C o u n t
I n t e r n a l F l i p / F l o p = 0: Read WO-w7
I n t e r n a l F l i p / F l o p = 1: Read W8-wl5
25
A d d res s
Description
0004
DMA C o n t r o l l e r
IOW- = 0: c h a n n e l 2 B a s e a n d C u r r e n t A d d r e s s
I n t e r n a l F l i p / F l o p = 0: W r i t e A O - A ~
I n t e r n a l F l i p / F l o p = 1: Write A8-Al5
I O R - = 0: C h a n n e l 2 C u r r e n t A d d r e s s
I n t e r n a l F l i p / F l o p = 0: Read A O - A ~
I n t e r n a l F l i p / F l o p = 1: Read ~ 8 - ~ 1 5
0005
DMA C o n t r o l l e r
IOW- = 0: C h a n n e l 2 Base a n d C u r r e n t Word C o u n t
I n t e r n a l F l i p / F l o p = 0: Write WO-W7
I n t e r n a l F l i p / F l o p = 1: Write AW-W15
IOR- = 0: C h a n n e l 2 C u r r e n t Word C o u n t
I n t e r n a l F l i p / F l o p = 0: Read WO-W7
I n t e r n a l F l i p / F l o p = 1: Read W8-Wl5
0006
DMA C o n t r o l l e r
IOW-
= 0:
c h a n n e l 3 Base a n d C u r r e n t A d d r e s s
I n t e r n a l F l i p / F l o p = 0: W r i t e A O - A ~
I n t e r n a l F l i p / F l o p = 1: Write ~ 8 - ~ 1 5
IOR-
= 0:
Channel 3 C u r r e n t Address
I n t e r n a l F l i p / F l o p = 0: Read A O - A ~
I n t e r n a l F l i p / F l o p = 1: Read ~ 8 - ~ 1 5
J007
DMA C o n t r o l l e r
IOW-
= 0: C h a n n e l 3 Base a n d C u r r e n t Word Count
I n t e r n a l F l i p / F l o p = 0: Write WO-W7
I n t e r n a l F l i p / F l o p = 1: Write AW-W15
IOR-
= 0: C h a n n e l 3 C u r r e n t Word C o u n t
I n t e r n a l F l i p / F l o p = 0: Read WO-w7
I n t e r n a l F l i p / F l o p = 1: Read w8-Wl5
26
Address
Description
0008
DMA C o n t r o l l e r
IOW-
= 0 , Write command R e g i s t e r
Bit
Description
0
0 =
1=
Memory t o Memory D i s a b l e
Memory t o Memory E n a b l e
1
0 =
1=
X
C h a n n e l 0 A d d r e s s Hold D i s a b l e
C h a n n e l 0 A d d r e s s Hold E n a b l e
If B i t 0 = 0
2
0 =
1=
C o n t r o l l e r Enable
Controller Disable
0 =
1=
X
N o r m a l Timing
Compressed T i m i n g
If B i t 0 = 1
0 =
1=
Fixed P r i o r i t y
Rotating P r i o r i t y
3
--
4
5
--0
X
Late W r i t e Selection
Extended W r i t e S e l e c t i o n
If B i t 3 = 1
=
1=
6
*-O
=
1=
DREQ S e n s e A c t i v e High
DREQ S e n s e A c t i v e Low
7
-0 =
1=
DACK S e n s e A c t i v e Low
DACK S e n s e A c t i v e High
IOR-
= 0 , Read S t a t u s R e g i s t e r
Bit
Description
0
1=
1=
1=
1=
1=
1=
1=
1=
1
2
3
4
5
6
7
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
27
0 H a s Reached
1 Has R e a c h e d
2 Has R e a c h e d
3 H a s Reached
0 Request
1 Request
2 Request
3 Request
DMATC
DMATC
DMATC
DMATC
Add res s
Description
0009
DMA C o n t r o l l e r
IOW- = 0, Write R e q u e s t R e g i s t e r
Bit
Description
B i t s 0-1
Bit 1
Bit 0
0
0
1
1
0
1
0
1
Select C h a n n e l 0
Select C h a n n e l 1
Select C h a n n e l 2
Select C h a n n e l 3
Bit 2
0
1
Reset Request B i t
Set R e q u e s t B i t
Don I t C a r e
B i t s 3-7
,
OOOA
= 0, Illegal
IOR-
DMA C o n t r o l l e r
IOW- = 0 , W r i t e S i n g l e Mask R e g i s t e r
Bit
Description
B i t s 0-1
Bit 1
Bit 0
0
0
1
1
0
1
0
1
Select
Select
Select
Select
Channel
Channel
Channel
Channel
0 Mask
1 Mask
2 Mask
3 Mask
Bit
Bit
Bit
Bit
Bit 2
0
1
B i t s 3-7
C l e a r Mask B i t ( E n a b l e C h a n n e l )
Set Mask B i t ( D i s a b l e C h a n n e l )
Don' t C a r e
IOR- = 0 , I l l e g a l
28
Address
Description
OOOB
DMA C o n t r o l l e r
IOW-
= 0 , W r i t e Mode R e g i s t e r
Bit
Description
B i t s 0-1
Bit 1
Bit 0
0
0
1
1
0
1
0
1
Channel
Channel
Channel
Channel
0
1
2
3
Select
Select
Select
Select
B i t s 2-3
Bits 3
Bit 2
0
0
1
1
0
1
0
1
Verify Transfer
W r i t e T r a n s f e r To Memory
Read T r a n s f e r To Memory
Illegal
I f B i t s 6 a n d 7 = 11
X
f
,
\
t
Bit 4
0
1
A u t o i n i t i a l i z a t i o n Enable
A u t o i n i t i a l i z a t i o n Disable
Bit 5
0
1
Address I n c r e m e n t S e l e c t
A d d r e s s Decrement S e l e c t
B i t s 6-7
Bit 7
Bit 6
0
-0
1
1
IOR-
oooc
0
1
0
1
Demand Mode S e l e c t
S i n g l e Mode S e l e c t
B l o c k Mode Select -Cascade Mode S e l e c t
= 0, I l l e g a l
DMA C o n t r o l l e r
IOW- = 0, Clear B y t e P o i n t e r F l i p / F l o p
IOR- = 0 , I l l e g a l
29
-,
"
Description
DMA C o n t r o l l e r
IOW- = 0 , Master C l e a r
IOR- = 0 , R e a d T e m p o r a r y R e g i s t e r
DMA C o n t r o l l e r
IOW- = 0 , C l e a r Mask R e g i s t e r
IOR- = 0 , I l l e g a l
DMA C o n t r o l l e r
IOW- = 0 , W r i t e A l l Mask R e g i s t e r B i t s
Bit
Description
0
0 = C l e a r C h a n n e l 0 Mask B i t ( E n a b l e )
1 = Set C h a n n e l 0 Mask B i t ( D i s a b l e
1
0 = C l e a r C h a n n e l 1 Mask B i t ( E n a b l e )
1 = S e t C h a n n e l 1 Mask B i t ( D i s a b l e
2
0 = C l e a r C h a n n e l 2 Mask B i t ( E n a b l e )
1 = Set C h a n n e l 2 Mask B i t ( D i s a b l e
3
0 = C l e a r C h a n n e l 3 Mask B i t ( E n a b l e )
1 = Set C h a n n e l 3 Mask B i t ( D i s a b l e
4-7
Don't Care
IOR- = 0 , I l l e g a l
0010
-
OOlF
s a m e as 0 0 0 0 - 0 0 0 ~
30
Address
Description
0020
8259A Interrupt Controller
Note: Initialization words are set up by the operating system and
are generally not to be changed. Writing an initialization
word might cancel pending interrupts.
Bit
4 = 1
Initialization Command Word 1
Bit 0
ICW4 Needed
ICW4 Not Needed
0
1
Bit 1
Cascade Mode
Single Mode
0
1
Bit 2
Not Used
Bit 3
Edge Triggered Mode
Level Triggered Mode
0
1
Bits 5-7
Not Used
Bit
Operation Control Word 2
4 = 0
Bit 3 = 0 BitO-2: Determine The Interrupt Level
Acted On When the SL Bit Is Active
Interrupt Level =
0 1 2 3 4 5 6 7
Bit 0 (LO): 0 1 0 1 0 1 0 1
Bit 1 (Ll): 0 0 1 1 0 0 1 1
Bit 2 (~2):0 0 0 0 1 1 1 1
Bits 5-7: Control Rotate and End of Interrupt Modes
B7
0
0
1
1
B6
0
1
0
0
B5
1
1
1
0
0
0
0
1 1 1
1 1 0
0
1
0
Non-Specific EO1 Command
Specific EO1 Command
Rotate On Non-Specific EO1
Rotate In Automatic EO1 Mode
Rotate In Automatic EO1 Mode
*Rotate On Specific EO1 Command
* Set Priority Command
No Operation
(*LO - L2 Are Used)
31
End Of Interrupt
d&? Of Interrupt
Auto Rotation
(Set) Auto Rotation
(Clear) Auto Rotation
Specific Rotation
Specific Rotation
Address
Description
0020
8259A I n t e r r u p t C o n t r o l l e r
Bit 4 = 0 C
Bit 3 = 1
O p e r a t i o n C o n t r o l Word 3
B i t 0-1:
Bit 1
Bit 0
-
0
1
0
1
0
0
1
1
Read R e g i s t e r Command
No Action
No Action
Read I R R e g i s t e r On N e x t IORRead I S R e g i s t e r On N e x t I O R -
Bit 2
0
1
N o P o l l Command
P o l l Command
B i t s 5-6
Bit 5
Bit 6
0
0
1
1
-
0
1
0
1
S p e c i a l Mask Mode
No Action
No Action
Reset S p e c i a l Mask
S e t S p e c i a l Mask
Bit 7 = 0
0021
8259A I n t e r r u p t C o n t r o l l e r
I n i t i a l i z a t i o n C o n t r o l Word 2
B i t s 0-7:
N o t Used
B i t s 3-7:
T3-T7 of I n t e r r u p t Vector A d d r e s s
( 8 0 8 6 / 8 0 8 8 / 8 0 2 8 6 Mode)
I n i t i a l i z a t i o n C o n t r o l Word 3 (Master D e v i c e )
B i t s 0-7
1
0
Indicated I R Input Has a Slave
I n d i c a t e d I R I n p u t Does N o t Have a
S1a v e
32
Pulse
Pulse
Address
Description
0021
8259A Interrupt Controller
Initialization Control Word 3 (Slave Device)
Bits 0-2
IDO-2
Bit 0
0
0
Bit 1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
Bits 3-7
Bit 2
0
1
0
1
0
1
0
1
-
Slave ID #
0
1
2
3
4
5
6
7
(Not Used)
0
Initialization Control Word 4
Bit 0
Type Of Processor
MCS-80/85 Mode
8086/8088/80286 Mode
0
1
Bit 1
Type of End of Interrupt
Normal EO1
Auto EO1
0
1
Bits 2-3
Buffering Mode
Bit 3
Bit 2
0
1
1
X
0
1
Bit 4
Nesting Mode
0
1
Bit5-7
Non-Buf fered Mode
Buffered Mode/Slave
Buffered Mode/Master
Not Special Fully Nested Mode
Special Fully Nested Mode
0
(Not Used)
33
Address
Description
0021
825911 I n t e r r u p t C o n t r o l l e r
o p e r a t i o n C o n t r o l Word 1 (IORB i t s 0-7
I n t e r r u p t Mask F o r IRQO-IRQ7
Mask Reset ( E n a b l e )
Mask S e t ( D i s a b l e )
0
1
Note:
P e r i p h e r a l s r e q u e s t i n g a n i n t e r r u p t s e r v i c e must g e n e r a t e a
l o w t o h i g h edge a n d t h e n remain a t a l o g i c h i g h l e v e l
u n t i l s e r v i c e i s acknowledged. F a i l u r e t o do so r e s u l t s i n
a Default S e r v i c e f o r IRQ7.
0022-0027
Same as 0020-0021
0028-003F N o t Used
0040/0044 8254-2 Timer
IOW- = 0: Load C o u n t e r N o .
IOR- = 0: Read C o u n t e r N o .
0
0
0041/0045 8254-2 Timer
IOWIOR-
= 0:
= 0:
Load C o u n t e r N o .
Read C o u n t e r N o .
1
1
0042/0046 8254-2 Timer
IOW- = 0:
I O R - = 0:
Load C o u n t e r N o .
Read C o u n t e r N o .
2
2
Address
Description
0043/0047 8254-2 T i m e r
= 0: W r i t e Mode Word
IOW-
C o n t r o l Word F o r m a t
Bit 0
BCD
0
1
BCD C o u n t e r ( 4 D e c a d e s )
Binary c o u n t e r 16 B i t s
B i t s 1-3
Bit 3
0
0
Mode S e l e c t i o n
Bit 2
0
0
X
X
1
1
Bit 1
0
Mode
Mode
Mode
Mode
Mode
1
0
1
0
1
1
1
0
0
0
1
2
3
4
Mode 5
0043/0047 8254-2 Timer
B i t s 4-5:
Read/Load
Bit 5
Bit 4
0
0
1
1
0
1
0
1
Counter Latching Operation
Read/Load LSB Only
Read/Load MSB O n l y
Read/Load LSB F i r s t , Then MSB
B i t s 6-7
S e l e c t Counter
Bit 7
0
0
Bit 6
0
1
0
1
<
1
1
Select Counter 0
S e l e c t Counter 1
Select Counter 2
Illegal
I O R - = 0: N o - O p e r a t i o n
0048-005F N o t Used
35
3-State
Address
Description
0 060
Port A / K e y b o a r d Interface C o n t r o l Ports
(Read Only)
Bit
0
1
2
3
4
5
6
7
0061
Description
Keyboard B i
Keyboard B i
Keyboard B i
Keyboard B i
Keyboard B i
Keyboard B i
Keyboard B i
Keyboard B i
t
t
t
t
t
t
t
t
0-LSB
1
2
3
4
5
6
7-MSB
P o r t B R e a d or W r i t e
B i t
0
1
2
3
4
5
6
7
Description
1= 8253 Gate 2 Enable
1 = Speaker D a t a O u t E n a b l e
Not Used
Not Used
1 = D i s a b l e I n t e r n a l Speaker (Sound C o n t r o l 2 )
Not Used
0 = HOLOCK ( I f IBM P C K e y b o a r d Mode)
1= Keyboard C l e a r
36
Address
Description
0062
P o r t C Read/Write:
B i t s 0-3;
Read o n l y :
B i t s 4-7
Description
Bit
-
Read/Write
N o t Used
Read/Write
N o t Used
Read/Write
N o t Used
( O u t p u t ) CPU C l o c k Rate
0 = 4.00 MHz (PC C o m p a t i b l e R a t e )
1 = 8.00 MHz ( D e f a u l t By Boot ROM)
Video RAM S i z e
0 = 128K V i d e o
1 = 256K V i d e o
8 2 5 3 o u t #2
Monochrome Mode
0 = color M o n i t o r
1 = 350 L i n e M o n i t o r , Mono
Reserved
-
4
5
6
7
0063-0064 R e s e r v e d
0065
Planar Control Register
Bit
Description
0
1
2
3
4
5
6
7
Hard D i s k P o r t S e l e c t
Parallel Port Select
Video P o r t S e l e c t
Floppy Disk P o r t S e l e c t
Serial Port Select
N o t Used
N o t Used
P a r a l l e l P o r t Output Enable
0066
Reserved
0067
P o r t H Reserved
0068-007F R e s e r v e d
0080
DMA P a g e R e g i s t e r ( R e s e r v e d f o r D i a g n o s t i c s )
write o n l y
0081
DMA C h a n n e l 2 P a g e R e g i s t e r - W r i t e
Address
Bit
Bit
Bit
Bit
0
1
2
3
Description
Address
Address
Address
Address
37
A16
A17
A18
A19
Only
Address
Description
0082
DMA C h a n n e l 3 Page R e g i s t e r - W r i t e
Address
B
B
B
B
0083
i t
i t
it
it
Description
0
Address
Address
Address
Address
1
2
3
Address
i t
it
it
it
A16
~ 1 7
A18
A19
Page R e g i s t e r -Write O n l y
DMA C h a n n e l 0-1
B
B
B
B
Description
Address
Address
Address
Address
0
1
2
3
A16
~ 1 7
A18
A19
0084-008F
S a m e as 0080-0083
0 OAO
NMI-
Mask R e g i s t e r , Write O n l y
B it
D e s c r i p t i on
0-6
Not U s e d
7
1
0
00A1-00A7
Reserved
00A8-00AF
Not Used
Only
NMI- E n a b l e d
NMI- D i s a b l e d
38
Address
Description
OOCO-OOc3 Sound SN76496
B i t 7 B i t 6 Bit 5 B i t 4 Bit 3 B i t 2 Bit 1B i t 0
F9
0
F6
F8
F7
1
0
0
0
X
FO
F1
F2
F3
F4
1
0
0
1
A0
A1
A2
1
0
1
0
F6
F7
F8
0
X
FO
F1
F2
F3
F4
1
0
1
1
A0
A1
A2
1
1
0
0
F6
F7
F8
0
X
FO
F1
F2
F3
F4
1
1
0
1
A0
A1
A2
1
1
1
0
X
FB
NFO
1
1
1
1
A0
A1
A2
39
U p d a t e Tone
Frequency 1
F5 A d d i t i o n a l
F r e q u e n c y Data
A3 Update Tone
Attenuation 1
F9 Update Tone
Frequency 2
F5 A d d i t i o n a l
F r e q u e n c y Data
A3 Update Tone
Attenuation 2
F9 Update Tone
Frequency 3
F5 A d d i t i o n a l
F r e q u e n c y Data
A3 Update Tone
Attenuation 3
NF I Update Noise
control
A3 Update N o i s e
Attenuation
Address
Description
OOC4-OOC7 DAC F u n c t i o n s
OOC4
write
B i t s 0-1
Bit 0
0
0
1
1
Bit 2
0
1
Bit 3
0
1
Bit 4
0
1
Bit 5
0
1
Bit 6
0
1
Bit 7
0 OC4
Bit 1
0
1
0
1
DAC F u n c t i o n S e l e c t e d
Joystick
S u c c e s s i v e Approximation
sound Channel
Direct W r i t e t o DAC
DMA E n a b l e ( f o r SA, Direct R/W)
DMA D i s a b l e d
DMA E n a b l e d f o r SA, DA
DMA I n t e r r u p t Clear
DMA I n t e r r u p t Held Clear
DMA I n t e r r u p t Allowed
DMA I n t e r r u p t E n a b l e
DMA EOP I n t e r r u p t D i s a b l e d
DMA EOP I n t e r r u p t E n a b l e d
Sound D i v i d e r S y n c E n a b l e
Synchronization Disabled
Sync E n a b l e d ( W r i t e t o OOC6 o r OOC7 r e l o a d s
all dividers)
Sound C h i p E x t r a D i v i d e E n a b l e
Extra Divide Disabled
E x t r a Divide Enabled
Reserved
R ea d
Bit 3
DMA I n t e r r u p t F l a g . A DMA I n t e r r u p t h a s
o c c u r r e d . To clear t h e i n t e r r u p t f l a g , B i t 3
must be b r o u g h t l o w a n d t h e n h i g h a g a i n .
Bit 7
S u c c e s s i v e A p p r o x i m a t i o n Done. U s e f u l when
p o l l i n g i n s t e a d of u s i n g DMA.
40
Address
Description
0 OC5
Write
B i t s 0-2
B i t 0
Bit 1
0
0
0
1
1
0
0
1
1
0
0
0
1
1
1
1
Bit 3
R e served
Bit 4
Reserved
Bit 5
Reserved
Bit 6
0
0
0
1
0
1
1
1
0 OC5
0
1
0
1
0
1
0
1
Duty Cycle
6.25%
12.5%
18.75%
25.0%
31.25%
37.5%
43.75%
50.0%
Waveshape Select
B i t s 6-7
Bit 7
Bit 2
Waveshape Selected
Pulse
Ramp
Triangle
Reserved
R e ad
D i r e c t R e a d of DAC w h e n O O c 4 B i t s 0-1 = 1X
D i r e c t R e a d of C o n t r o l R e g i s t e r w h e n OOC4 B i t s 0-1
= 01
0 OC6
R/W
B
B
B
B
B
B
B
B
i
i
i
i
i
i
i
i
t
t
t
t
t
t
t
t
Frequency l s b f o r DAC s o u n d c h a n n e l
0
1
FO
F1
2
F2
3
F3
4
F4
5
6
7
F5
F6
F7
41
Address
Description
0 OC7
R/W A m p l i t u d e / f r e q u e n c y msb f o r DAC s o u n d c h a n n e l
Bit
Bit
Bit
Bit
B
B
B
B
i
i
i
i
t
t
t
t
0
4
F8
F9
F10
F11
Reserved
5
6
AMP 2
7
AMP3
1
2
3
AMP1
00C8-00CF R e s e r v e d
0100-01FF R e s e r v e d
0 2 0 0-0 2 0 7 J o y s t i c k
W r i t e C l e a r (Resets Ramp G e n e r a t o r To 0)
0201
Read R = R i g h t J o y s t i c k , L = L e f t J o y s t i c k
Bit
Description
0
1
2
3
R
R
L
L
R
R
L
L
4
5
6
7
-x
Y
-X
-Y
Horizontal Position
Vertical P o s i t i o n
Horizontal Position
Vertical P o s i t i o n
B u t t o n #1 ( L o g i c 0 = B u t t o n
B u t t o n #2 ( L o g i c 0 = B u t t o n
B u t t o n #1 ( L o g i c 0 = B u t t o n
B u t t o n #2 ( L o g i c 0 = B u t t o n
-
Pressed)
Pressed)
Pressed)
Pressed)
0208-020F N o t Used
0210-02F7 R e s e r v e d
2F8-2FF
S e r i a l P o r t s e c o n d a r y (COM2 O p t i o n a l )
02F8
W r i t e T r a n s m i t t e r Holding Register ( C h a r a c t e r t o s e n d )
Bit
Description
0
1
2
3
4
5
Bit
Bit
Bit
Bit
Bit
Bit
0
1
2
3
4
5
6
Bit 6
7
Bit 7
-
LSB ( F i r s t B i t S e n t S e r i a l l y )
-
MSB
42
Address
Description
0 2F8
Read R e c e i v e r B u f f e r R e g i s t e r ( C h a r a c t e r Received)
Bit
Description
0
1
2
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
3
4
5
6
7
02F8
LSB ( F i r s t B i t R e c e i v e d S e r i a l l y )
-
MSB
Bit
Description
0
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
3
4
5
6
7
0
1
2
3
4
5
6
7
D i v i s o r L a t c h MSB ( D i v i s o r L a t c h A c c e s s B i t DLAB ="l")
Bit
0
1
2
3
4
5
6
7
0 2F9
3
4
5
6
7
-
D i v i s o r L a t c h LSB ( D i v i s o r L a t c h A c c e s s B i t DLAB ="1")
1
2
0 2F9
0
1
2
Description
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
0
1
2
3
4
5
6
7
Interrupt Enable R e g i s t e r
Bit
Description
0
1
2
3
"1" = E n a b l e s t h e R e c e i v e d D a t a A v a i l a b l e
Interrupt
I1 1 I1 = E n a b l e s t h e T r a n s m i t t e r H o l d i n g R e g i s t e r
Int
"1" = E n a b l e s R e c e i v e L i n e S t a t u s I n t e r r u p t
"1" = E n a b l e s t h e Modem S t a t u s I n t e r r u p t
4-7
A l w a y s L o q i c a l 11011
43
Address
Description
0 2FA
Interrupt Identification Register
Bit
0
1-2
3-7
02FB
Description
II 0 II
= I n t e r r u p t Pending
Bit 2
Bit 1
II 0 II
It 0 II
Fourth Level P r i o r i t y
II 0 II
II 1II
Third Level P r i o r i t y
I1 1II
110n
Second L e v e l P r i o r i t y
II 1 1 1
II 1It
Highest Level P r i o r i t y
Always L o g i c a l
L i n e C o n t r o l Register
Bit
Description
0-1
Bit 1
Bit 0
0 II
II 0 It
tI 1It
II 1II
It
It
II
Five B i
Six B i t
Seven B
Eight B
0 II
1II
I t 0 II
t Word L e n g t h
Word L e n g t h
i t Word L e n g t h
i t Word L e n g t h
5
6
7
1It
= One S t o p B i t
II 1 1 1 = 1 3 S t o p B i t s When F i v e B i t L e n g t h
Selected
Two S t o p B i t s W i t h S i x , S e v e n , o r E i g h t B i t
"1II = P a r i t y E n a b l e
"0 11 = Odd P a r i t y S e l e c t
II 1
II
= Even P a r i t y S e l e c t
Stick Parity B i t
"1" = S e t B r e a k E n a b l e
"1" = D i v i s o r L a t c h Access B i t E n a b l e
Bit
Description
0
1It = Data T e r m i n a l Ready S e t (DTR)
0 It = Data T e r m i n a l Ready R e s e t (DTR)
R e q u e s t To Send (RTS)
out 1
out 2
Loop
Always L o g i c a l "0"
2
3
4
II
now
02FC
II
II
1
2
3
4
5-7
44
Address
Description
0 2FD
Line S t a t u s Register
Bit
6
7
02FE
Data Ready ( D R )
Overrun E r r o r (OR)
11111
= Detect P a r i t y E r r o r (PE)
II 1I1 = Detect F r a m i n g
E r r o r (FE)
II 1 II
= Break I n t e r r u p t (BI 1
T r a n s m i t t e r Holding Register
11 1 11 = C h a r a c t e r
T r a n s f e r r e d From H o l d i n g To S h i f t
Reg i s t e r
I1 0 11 = L o a d i n g T r a n s m i t t e r
Holding Register
T r a n s m i t t e r S h i f t Register Empty
1 1 1 1 1 = S h i f t Register
Idle
11 0 II
= Data T r a n s f e r From H o l d i n g Register
Always L o g i c a l 1101'
Modem S t a t u s R e g i s t e r
Bit
0
1
2
3
0 2FF
Description
Description
Delta Clear To S e n d (DCTS)
Delta Data S e t Ready (DDSR)
T r a i l i n g Edge R i n g I n d i c a t o r
II 1II
= on
11 0 II
= Off
D e l t a R e c e i v e d L i n e S i g n a l Detect ( I f B i t 0, 1, 2 ,
o r 3 i s s e t t o a "l", m o d e m s t a t u s i n t e r r u p t i s
generated)
II 0 11
= C l e a r To S e n d (CTS)
11 0 I1
= Data S e t Ready (DSR)
"0" = R i n g I n d i c a t o r ( R I )
"0" = R e c e i v e d L i n e S i g n a l Detect (RLSD)
Reserved
0300-036F R e s e r v e d
0370-0377 F l o p p y D i s k C o n t r o l l e r 2 ( o p t i o n a l )
45
Address
Description
0378
Printer
Data L a t c h
Bit
Description
0
Bit 0
Bit 1
1
2
3
4
5
6
7
0379
-
Bit
LSB
-
MSB
2
Bit
Bit
Bit
Bit
Bit
Bit
Printer
-
3
4
5
6
7
-
Read S t a t u s
Description
N o t Used
N o t Used
N o t Used
"011 = E r r or
"1" = P r i n t e r S e l e c t
"011 = o u t of P a p e r
"01' = Acknowledge
n o II = Busy
Printer
Bit
-
Control Latch
Description
I1 0 I1
= Strobe
" 0 " = A u t o FD XT
non = I n i t i a l i z e
110" = S e l e c t P r i n t e r
"1" = E n a b l e I n t e r r u p t
" 0 " = E n a b l e O u t p u t Data
N o t Used
N o t Used
0 37B
N o t Used
0 37C
Printer
-
Data L a t c h
037D
Printer
-
Read S t a t u s
037F-03CF N o t Used
03DO-03D3 N o t Used
03D4
6 8 4 5 A d d r e s s Register
46
Address
Description
0 3D5
6 8 4 5 Data R e g i s t e r
0 3D6
N o t Used
0 3D7
N o t Used
0 3D8
Mode S e l e c t R e g i s t e r
B i t 0 High R e s o l u t i o n C l o c k
Bit
Bit
Bit
Bit
Bit
0 3D9
= 0 S e l e c t s 40 By 25 A l p h a n u m e r i c Mode
= 1 S e l e c t s 80 By 25 A l p h a n u m e r i c Mode
1 Graphics Select
= 0 S e l e c t s A l p h a n u m e r i c Mode
= 1 S e l e c t s 320 By 200 G r a p h i c s Mode
2 B l a c k And W h i t e
= 0 S e l e c t s Color Mode
= 1 S e l e c t s B l a c k And W h i t e Mode
3 Video Enable
= 0 D i s a b l e s Video S i g n a l
= 1 Enables Video S i g n a l
4 640 D o t G r a p h i c s
= 0 D i s a b l e s 640 By 200 B&W G r a p h i c s Mode
= 1 E n a b l e s 640 By 200 B&W G r a p h i c s Mode
5 Blink Enable
= 0 Disables Blinking
= 1 Enables Blinking
Color S e l e c t R e g i s t e r
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Background Blue
Background Green
Background Red
Background I n t e n s i t y
Foreground I n t e n s i t y
color Select
47
Address
Description
03DA-03DE W r i t e V i d e o Array A d d r e s s a n d Read S t a t u s (03DA)
Write video A r r a y Data (03DE)
R e a d (03DA)
W r i t e (03DE)
Bit
Bit
Bit
Bit
00 B i t
0 Display I n a c t i v e
1 L i g h t Pen S e t
2 Light Switch Status
3 Vertical Retrace
01
01
01
01
Bit
Bit
Bit
Bit
0
1
2
3
Palette
Palette
Palette
Palette
02
02
02
02
02
Bit
Bit
Bit
Bit
Bit
0
1
2
3
5
Border B l u e
Border Green
B o r d e r Red
Border I n t e n s i t y
Reserved = 0
03
03
03
03
03
03
Bit
Bit
Bit
Bit
Bit
Bit
0
Mono E n a b l e = 1
Reserved = 0
Border Enable
4-COlOr H i g h R e s o l u t i o n
1 6 - C o l o r Mode
E x t r a V i d e o Mode
00
00
00
00
N o t Used
4
1
2
3
4
5
0 3DB
C l e a r L i g h t Pen L a t c h
0 3DC
P r e s e t L i g h t Pen L a t c h
0 3DD
Extended RAM Page R e g i s t e r
Bit
0
1
2
3
4
5
6
7
-
N o t Used
Not
Not
Not
Not
N o t Used
N o t used
video Page A d d r e s s 1117"
video P a g e A d d r e s s 1118"
P a g e A d d r e s s ''17"
P a g e A d d r e s s 1118"
Select 64K Or 256K RAM
48
Used
Used
Mask
Mask
Mask
Mask
CPU R e l a t i v e
Description
E x t e n d e d A d d r e s s i n g Modes
CRT
CRT
CPU
CPU
Used
used
0
1
2
3
Address
Description
0 3DF
C R T Processor Page R e g i s t e r
B
B
B
B
B
B
B
B
i
i
i
i
i
i
i
i
t
t
t
t
t
t
t
t
0
1
2
3
4
5
6
7
Descriptions
1 - 16K
4
4
4
2
12 2
2
4
p
p
p
p
8K
16K
8K
32K
32K
DO
3DDH
D7
3DFH
D6
3DFH
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
03EO-03EF
Reserved
0 3F0
Not Used
0 3F1
D r i v e Select S w i t c h
Bit 0
Bit 1
Bit 2
Bit 3
Not Used
"1" DSO = DSO
" 0 " DSO = D S 1
Not Used
Mux FDCDMATC ( W r i t e O n l y )
llo" FDCDMATC O u t
1
B
B
B
B
03F2
i
i
i
i
t
t
t
t
4
5
6
7
Not
Not
Not
Not
DOR R e g i s t e r
B i t s 0-1
Bit 1
0
0
B
B
B
B
B
B
i
i
i
i
i
i
t
t
t
t
t
t
2
3
4
5
6
7
V i d e o Memory R e l a t i v e
A 1 4 C R T Page 0
A 1 5 C R T Page 1
A 1 6 C R T Page 2
A 1 4 Processor Page 0
A 1 5 Processor Page 1
A 1 6 Processor Page 2
V i d e o A d d r e s s Mode 0
V i d e o A d d r e s s Mode 1
video
8p
8p
-
Input
Used
Used
Used
used
( W r i t e only)
D r i v e Select
Bit 0
0
D r i v e Select A*
1
D r i v e Select B*
0 = FDC R e s e t
1 = E n a b l e DMA R e q u e s t / I n t e r r u p t
1 = D r i v e A Motor On
1 = D r i v e B Motor On
1 = FDC T e r m i n a l C o u n t
Not Used
49
Address
Description
0 3F3
N o t Used
0 3F4
FDC
-
S t a t u s ( R e a d O n l y ) See FDC S p e c i f i c a t i o n
03F5
FDC
-
D a t a (R/W) See FDC S p e c i f i c a t i o n
03F6-03F7
Reserved
03F8-03FF S e r i a l P o r t P r i m a r y (COM1)
0 3F8
Write T r a n s m i t t e r H o l d i n g R e g i s t e r ( C h a r a c t e r t o s e n d )
Bit
Description
0
1
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
2
3
4
5
6
7
0 3F8
-
LSB ( F i r s t B i t S e n t S e r i a l l y )
-
MSB
2
3
4
5
6
7
Read R e c e i v e r B u f f e r R e g i s t e r ( C h a r a c t e r R e c e i v e d )
Bit
Description
0
1
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
2
3
4
5
6
7
0 3F8
0
1
0
1
2
3
4
5
6
7
-
LSB ( F i r s t B i t R e c e i v e d S e r i a l l y )
-
MSB
D i v i s o r L a t c h LSB ( D i v i s o r L a t c h A c c e s s B i t DLAB = "1")
Bit
Description
0
1
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
2
3
4
5
6
7
0
1
2
3
4
5
6
7
50
Address
Description
0 3F9
D i v i s o r L a t c h MSB ( D i v i s o r L a t c h Access B i t DLAB = "1")
Bit
Description
0
1
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
2
3
4
5
6
7
0 3F9
0
1
2
3
4
5
6
7
I n t e r r u p t Enable R e g i s t e r
Bit
Description
0
"1" = E n a b l e s t h e R e c e i v e d Data A v a i l a b l e
1
"1" = E n a b l e s t h e T r a n s m i t t e r H o l d i n g R e g i s t e r I n t
1'1" = E n a b l e s R e c e i v e L i n e S t a t u s I n t e r r u p t
"1" = E n a b l e s t h e Modem S t a t u s I n t e r r u p t
Interrupt
2
3
4-7
03FA
Always L o g i c a l "0"
I n t e r r u p t I d e n t i f i c a t i o n Register
Bit
Description
0
1-2
II0 II = I n t e r r u p t P e n d i n g
Bit 2
Bit 1
II 0 II
"0 n
Fourth Level P r i o r i t y
" 0 II
II1 n
Third Level P r i o r i t y
11 1 II
"0
Second L e v e l P r i o r i t y
11 1 n
111n
Highest Level P r i o r i t y
Always L o g i c a l "0"
I(
3-7
51
Address
Description
0 3FB
Line c o n t r o l Register
Bit
Description
0-1
Bit 1
Bit 0
0 II
II 0 I1
II
11
0 I1
1 1 1 I1
1II
II 0 II
1n
II 1 11
II 0 11 =
One S t o p B i t
II
II
2
111n
=
13
F i v e B i t Word L e n g t h
S i x B i t Word L e n g t h
S e v e n B i t word L e n g t h
E i g h t B i t Word L e n g t h
S t o p B i t s When F i v e B i t L e n g t h S e l e c t e d
Two S t o p B i t s W i t h S i x , S e v e n , or E i g h t B i t
3
n 1 n =
4
II
5
6
7
=
Stick
"1" =
"1" =
Bit
Description
0
"11'= Data T e r m i n a l Ready S e t (DTR)
0 II = Data T e r m i n a l Ready Reset (DTR)
R e q u e s t To Send (RTS)
Out 1
out 2
LOOP
Always L o g i c a l l l O g l
P a r i t y Enable
0 II = Odd P a r i t y S e l e c t
n l n
Even P a r i t y S e l e c t
Parity Bit
S e t Break Enable
D i v i s o r L a t c h Access B i t E n a b l e
0 3FC
11
1
2
3
4
5-7
03FD
Line S t a t u s Register
Bit
Description
0
1
Data Ready ( D R )
Overrun E r r o r (OR)
"1' = Detect P a r i t y E r r o r ( P E )
"1I1 = Detect F r a m i n g E r r o r (FE)
II 1I1 = B r e a k I n t e r r u p t
(BI)
Transmitter Holding R e g i s t e r
II 1I1 = C h a r a c t e r
T r a n s f e r r e d From H o l d i n g To S h i f t
R e g ist er
I1 0 II
= Loading T r a n s m i t t e r Holding R e g i s t e r
T r a n s m i t t e r S h i f t R e g i s t e r Empty
n111 = S h i f t R e g i s t e r I d l e
n o n = Data T r a n s f e r From H o l d i n g R e g i s t e r
Always L o g i c a l "0"
2
3
4
5
6
7
52
Address
Description
0 3FE
Modem S t a t u s R e g i s t e r
Bit
Description
0
1
Delta C l e a r To S e n d (DCTS)
D e l t a Data S e t Ready ( D D S R )
T r a i l i n g Edge R i n g I n d i c a t o r
'1" = On
"0" = Off
Delta Received L i n e S i g n a l Detect ( I f B i t 0, 1, 2 ,
o r 3 i s s e t t o a "l",m o d e m s t a t u s i n t e r r u p t i s
generated)
"0" = Clear To S e n d (CTS)
"0" = Data S e t Ready (DSR)
"0" = R i n g I n d i c a t o r ( R I )
"0" = R e c e i v e d L i n e S i g n a l Detect (RLSD)
2
3
4
5
6
7
0 3FF
Res e r v e d
53
Address
Description
FFE8-FFEB S y s t e m C o n t r o l R e g i s t e r s
FFE8
I
'
1
.' .
I
Video C o n f i g u r a t i o n R e g i s t e r
C
Bit
Description
0
Reserved
B i t 1-4
v i d e o Memory C o n f i g u r a t i o n
Bit
4
3
256K
E n a b l e A19
Bit
NOTE:
Bit
2
Bit
1
Memory
Start
Memory
Length
Memory
Range
~ 1 8 A17
0
0
0
0
0 0000
128K
0
0
0
1
2 0000
128K
0
0
1
0
4 0000
128K
0
0
1
1
6 0000
128K
0
1
0
0
8 0000
128K
0
1
1
1
B 0000
128K
1
0
0
1
0 0000
256K
1
0
1
0
2 0000
256K
1
0
1
1
4 0000
256K
1
1
0
0
6 0000
256K
1
1
1
1
B 8000
256K
0 00001 FFFF
2 00003 FFFF
4 00005 FFFF
6 00007 FFFF
8 00009 FFFF
B 0000B FFFF
( 4 Page)
0 00003 FFFF
2 00005 FFFF
4 00007 FFFF
6 00009 FFFF
B 0000B FFFF
( 8 Page)
To t u r n off o n - b o a r d V i d e o , b e sure P o r t AOH, Data B i t 0 is
a "1" a n d V i d e o A r r a y R e g i s t e r 3.
5
6
7
1 6 B i t CPU Memory = 1
Reserved
Reserved
54
Address
Description
FFE9
Programmable W a i t State P o r t
Bit(s1
Description
0
I n t e r n a l M e m o r y W a i t States
0 = 0 w a i t states
1 = 1 w a i t states
1,2
E x t e r n a l M e m o r y W a i t States
00 = 0 w a i t s t a t e s
0 1 = 1 w a i t states
1 0 = 2 w a i t states
11 = 3 w a i t s t a t e s
I/o C y c l e W a i t States
0 w a i t states
1 w a i t states
3,4
00 =
01 =
10 =
11 =
2 w a i t states
3 wait s t a t e s
DMA E a r l y W r i t e D i s a b l e
0 = DMA w a i t s f o r IOCHRDY = 1 t o s t a r t W r i t e
5
Strobe
1 = N o r m a l 8 2 3 7 A - 5 W r i t e Strobe G e n e r a t i o n
I n t e r n a l V i d e o W a i t States
0 = 0 w a i t states
1 = 1 w a i t states
O S C I N Select
0 = 2 8 . 6 3 6 3 6 MHz
1 = 2 4 MHz
FFEA
WRITE/READ
B
B
B
B
B
B
i
i
i
i
i
i
t
t
t
t
t
t
B i t
6-7
0:
1:
2:
3:
4:
5:
ROM
ROM
ROM
ROM
ROM
0
PAGING
PAGING
PAGING
PAGING
PAGING
1
2
3
4
0 = I n t e r n a l and B u s R e f r e s h
1 = I n t e r n a l R e f r e s h only
Description
Bit 7 Bit 6
0
0
1
1
Two B a n k s of 1 2 8 K m e m o r y
Four B a n k s of 1 2 8 K m e m o r y
0
1
0
1
O n e B a n k of 5 1 2 K m e m o r y
O n e B a n k of 5 1 2 K memory,
B a n k of 1 2 8 K m e m o r y
55
One
NOTE: When reading Port FFEA, Bit 4 will be inverted from what
was written, (i.e. when a 0 is written, a 1 will be read; when a
1 is written, a 0 will be read.)
ROM Paging Definition:
Two
2
Meg ROMs
ADDRESS
ROM PAGES
(Two 1 Meg ROMS) 19 18 17 16
F0000-FFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
4 Meg ROMS
F0000-FFFFF
EO0 00- EFFFF
EO 0 00-EFFFF
EO0 00- EFFFF
E0000-EFFFF
EO000-EFFFF
EO000-EFFFF
EO000-EFFFF
EO0 00-EFFFF
EO000-EFFFF
E0000-EFFFF
EOO 00-EFFFF
EO000-EFFFF
EO 000-EFFFF
EO 000-EFFFF
EO000-EFFFF
~0000-EFFFF
TWO
FFEB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
x
x
x
x
x
x
x
x
x
4
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
19 18 17 16
1 1 1 1
1 1 1 0
1 1 1 0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
x
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
x
1
1
1
1
0
0
0
0
1
x
1
1
0
0
1
1
0
0
0
x
1
0
1
0
1
0
1
0
SELECT 64K Page
ROMCS
2 1 0
ROM 0 ROM 1
#O #1
1
0 1
x l l
3 2 1 0
x
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
x
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
x
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
x
x
x
x
x
x
x
x
x
1
x
o
l
1
o
o
x
0
l
o
l
0
1
o
#O #1
0 1
1 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
1 0
1 0
1 0
2
1
x
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
x
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
1
1
0
0
1
1
1
0
0
0
UART Clock, Joystick, and Sound Enable
Bit
Description
0
0 = Clock divided by 13
1 = Clock Divided by 1
1
0 = Disable Joystick
1 = Enable Joystick
2
0 = Disable Sound Chip
1 = Enable Sound Chip
56
2
3
4
1
2
3
4
ROM 0 ROM 1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
QTY. DESCRIPTION
1
4
1
20
TANDY 1000 S L MAIN LOGIC PCB REV.
3
2
1
1
5
1
1
E2-4
U17
U6-11,15,16,
19,20,23,24
27,28,31,32,
34,35,36,37
SOCKET, 2 0 P I N D I P U13B
SOCKET, 24 P I N .300 U 1 8
SOCKET, 2 8 P I N D I P U 1 3 , 2 5
SOCKET, 3 2 P I N
HU1 ,HU2
OR S U 3 ,SU4
SOCKET, 4 0 P I N D I P U 1 2 , 2 1 , 2 9
SOCKET, 6 8 P I N PLCC U 3 0 , 4 0
CONNECTOR, 9 - P I N
J3
(POWER)
J2
(FLOPPY)
CONNECTOR, 3 4 P I N
J5-9
CONNECTOR, 6 2 P I N
J10
(SERIAL)
CONNECTOR, DB9
CONNECTOR, DB9
J11 (VIDEO)
1
CONNECTOR, 8 P I N
J1
1
CONNECTOR, 2 0 P I N
54
6
RESISTOR, 10 OHM
1 / 8 W 5 % SMD R 1 2 0 6
RESISTOR, 33 OHM
1 / 8 W 5 % SMD R 1 2 0 6
RESISTOR, 5 1 0 OHM
1 / 8 W 5 % SMD R 1 2 0 6
RESISTOR, 1 K OHM
1 / 8 W 5 % SMD R 1 2 0 6
RESISTOR, 1 . 2 K OHM
1 / 8 W 5 % SMD R 1 2 0 6
RESISTOR, 2.2K OHM
1 8 W 5 % SMD R 1 2 0 6
RESISTOR, 3.3K OHM
1 8 W 5 % SMD R 1 2 0 6
R11,14,16,22,
24,27
R2,3,18,3 4 ,
35,36,37
R4 1
1
1
2
2
7
1
6
1
1
1
VENDOR
DESIGNATOR
STAKE P I N
SOCKET, 8 - P I N D I P
SOCKET, 1 8 P I N D I P
(JOYSTK)
B
PART
NUMBER
8709843
AMP#1-87022-0
AMP#640463-1
AMP# 2 - 3 8 3 0 6 0- 3
8529014
8509011
8509037
AMP#640962-3
AMP#2-641605-3
8509009
8509029
8509007
8509048
AMP#2-641606-3
MOLEX#26-4 8-1095
MOLEX#70246-3402
AMP#747840-3
AMPC74 59 8 83
HOLMBERG# 4 50 9RA2 8 CM4 2
MOLEX # 8 2 0 0 9 -2 0 52
AMP# 5 -1 0 2 0 7 4- 8
BERG #6 5 0 0 1-2 0 8
MOLEXR90148-1108
AMP#5-102083-6
MOLEX#15-38-2020
BE RG # 6 5 0 0 0 - 2 10
8509002
8509020
8519191
8519324
8519236
8519269
8519279
8519365
8519366
X20301030
X20303330
X20315130
X20321030
RlA,20,21,23,
25,39
R4 2
X20321230
R2 9
X20322230
R2 8
X20323330
QTY. DESCRIPTION
5
10
5
2
2
1
1
1
1
7
RESISTOR, 4.7K OHM
1/8W 5% SMD R1206
RESISTOR, 10K OHM
1/8W 5% SMD R1206
RESISTOR, 27K OHM
1/8W 5% SMD R1206
RESISTOR, 47K OHM
1/8W 5% SMD R1206
RESISTOR, lOOK OHM
1/8W 5% SMD R1206
RES PAK, lK,
RES PAK, 4.7K
RES PAK, 10K
RES PAK, 10K
RES PAK, 33 OHM,
36
CAP 0.luf 50V 20%
SMD C0805
20
CAP 0.33 uf 50V
20% Z5U SMD C1210
4
2
6
2
1
6
CAP 10 uf
TANT RAD.
CAP 10 uf
ELECT.RAD.
CAP 22 uf
ELECT.RAD.
CAP 22 UF
ELECT.RAD.
CAP 47 uf
ELECT.RAD.
CAP 33 p f
SMD C0805
25V
20%
16V
20%
16V
20%
25V
20%
16V
20%
10% 50V
DES IGNAT0 R
VENDOR
PART
NUMBER
R1,4 ,5 ,17 ,33
X20324730
R6,7,8 ,9
10,12,13,15,
18A,19
R26,31,38,40,46
X20331030
X20332730
R30,45
X20334730
R43,44
X20341030
RP 3
RP 8
RP4
RP7
RP1,2,5,6,
9-11
C2-4,6,9,
10,10A,15A,
18,19,21,22,
28,31,35-37 I
39,47,69,
7 0-72,74-7 9,
82,84,87,91,
102,111,126
C7,8,11,12,
13,14,16,17,
20,23,25,26,
29,30,32,33,
40,41,51,52
C5,15,27,68
8290210
8294247
8290032
8292310
8290044
X30410345
X30433343
8336106
C81,86
8326106
C1,44-46,83,127
8326221
C42,43
8326224
ClOl
8326474
C2 4,34,38,50,
73,80
X30033240
QTY. DESCRIPTION
49
3
1
1
2
1
1
1
1
1
1
1
1
2
1
1
10
1
CAP 220 wf 10% 50V C48,49,53-67,
SMD C080k
85,88-90,
92-99,100
103,105,106,
109,110,
112-125
CAP 330 pf
C104,107,108
SMD C0805
OSCILLATOR,
Y1
DUAL 28/32 MHZ
OSCILLATOR,
Y2
DUAL 16/24 MHZ
IC, 74HCT14*
u33
IC, 74HCT273
U14
IC, 74LSOO
u5
IC, 74LS32
u22
IC, 74LS175
U13A
IC, 74LS244
u45
U38
IC, 74LS373
IC, MC1458S
u44
IC, MC1488
u39
U42,43
IC, MC1489
IC, VIDEO I1
U26
IC, BUFFER BLUE
U41
FB1-10
FERRITE BEAD
VR1
VOLT.REG. 78L05
VR2
1
VOLT.REG. 79M05CT
5
CF1-5
EM1 FILTER,
.22 u f W/FER. BEAD
1N4148 DIODE
CR1
1
PART
NUMBER
DESIGNATOR
* (CAN SUB LS FOR ALL HCT PARTS)
NOTE: DO NOT STUFF R32,E5,E6,E7,RlB.
X30122243
X30133244
DIAWA, MF
8409076
DIAWA, MF
8409075
GENfRIC
8026014
8026273
8020000
8020032
8020175
8020244
8020373
8052458
8050188
8050189
8079020
8079024
8419013
8052805
U
I1
II
MOTOROLA
GENERIC
n
I1
FAIRRITE82743002121
MOTOROLA MC78L05,
FAIRCHILD UA78L05
TEXAS INST. UA78L05C
MOTOROLA MC79M05CTI
8190005
FAIRCHILD UA7905
TEXAS INST. UA79M05CKC
MURATA#DTS310 55D-2235 8418013
8150148
QTY
DESIGNATOR
1
TANDY 1 0 0 0 S L SUBASSEMBLY REV. B
1
1
JUMPER PLUG
I C , EEPROM,
1K SERIAL
I C , 1 6 K X 8 ROM
(CHAR GEN) 2 0 ONS
I C , 64K X 4 DRAM
1 2 0 ns
1
4
8
1
1
1
1
1
1
1
1
1
1
1
1
*
DESCRIPTION
IC,
150
IC,
IC,
IC,
IC,
IC,
IC,
IC,
64K X 4 DRAM
ns
VIDEO I1
CPU 8086-2
BUFFER BLUE
PSSJ ( 6 8 PLCC)
FDSL
K F I T ( 6 8 PLCC)
UPD 7 6 5 A
IC, 256K X 8
(2MEG B I T ROM)
EVEN ( 2 0 0 N S ) *
I C , 256K X 8
(2MEG B I T ROM)
ODD ( 2 0 0 N S ) *
I C , 256K X 8
(2MEG B I T ROM)
EVEN ( 2 0 0 N S ) *
I C , 256K X 8
(2MEG B I T ROM)
ODD ( 2 0 0 N S ) *
I C , PAL 1 6 R 4 A
NOTE:
E2-E3
U17
U2 5
U6,7,8,9
U10,15,19,23,
27,31,34,36,
U26
U29
U4 1
U4 0
U18
U3 0
u12
PART
NUMBER
VENDOR
8859024
GENERIC
NAT. SEMI CONDUCTOR,
HYUNDAI, AMI
HITACHI, SHARP, NCR
8519098
8040346
F U J I T S U , HITACHI,
NEC, T I , SAMSUNG,
MICRON
8045164
GENERIC
8040464
8079020
8041086
8079024
8079021
8041401
8079019
8040272
AMD
8079027
HUl
INTEL,
ROCKWELL,
NEC
H ITACH I
HU2
HITACHI
8075312
su3
SHARP
8076323
su4
SHARP
8075323
U13B
AMD ,
NAT. SEMI CONDUCTOR
8042164
USE EITHER HITACHI ROMS (HU1,HUZ)
NOT BOTH SETS.
ZILOG,
8076312
OR SHARP ROMS ( s u 3 , s U 4 ) ,
BUT
QTY. DESCRIPTION
DESIGNATOR
1
TANDY 1000 SL SATELLITE PCB REV. B
3
1
STAKING PIN
JUMPER PLUG
CONNECTOR
CONNECTOR
CONNECTOR
CONNECTOR
El-3
E2-E3
J7 (SPEAKER)
J1 (KEYBOARD)
J2,3 (JOYSTICK)
J5
1
CONNECTOR
J4
1
1
1
2
1
1
9
4
3
1
1
1
1
8
2
1
1
4
7
3
1
3
RESISTOR, 47 OHM R26
1/8W 5% SMD R1206
RESISTOR, 10 OHM R39
1/8W 5% SMD R1206
RESISTOR, 33 OHM R1-9
1/8W 5% SMD R1206
RESISTOR, 1K OHM R14,17,21,23,
1/8W 5% SMD R1206
RESISTOR, 1.2K OHM R29,32,34
1/8W 5% SMD R1206
RESISTOR, 1.3K OHM R30
1/8W 5% SMD R1206
RESISTOR, 2.4K OHM R27
1/8W 5% SMD R1206
RESISTOR, 2.7K OHM R36
1/8W 5% SMD R1206
RESISTOR, 4.7K OHM R33
1/8W 5% SMD R1206
RESISTOR, 1 0 K OHM R10,13,18,19,
1/8W 5% SMD R1206 20,22,24,25
RESISTOR, 13K OHM R28,R35
1/8W 5% SMD R1206
RESISTOR, 91K OHM R31
1/8W 5% SMD R1206
RESISTOR, 300 OHM R37,38
1/8W 5% SMD R1206
RESISTOR, 1 MEG
R11,12,15,16
1/8W 5% SMD R1206
CAP 0.1 uf 50V
C23,33,36,38-41
20% SMD C0805
CAP .33 uF
c35,43,44
CAP .047 uF
C24
C1206P 20% 50V Z5U
CAP 3.3 uF
C26,29,30
VENDOR
PART
NUMBER
8709867
AMP#l-87022-0
8529014
8519098
8519193
MOLEX#22-29-20 21
HOSIDEN#TCS5040-17-4071 8519358
HOSIDEN#TCS5043-16-1911 8519318
AMP#103323-8
8519367
MOLEX#22-59-1108
BERG#68015-408
AMP#1-103324-0
8519368
MOLEX#10-88-1206
BERG#6805-420
X20304730
X20301030
X20303330
X20321030
X20321230
X20321330
X20322430
X20322730
X20324730
X20331030
X20331330
X20339130
X20313030
X20361030
X37410341
X30433343
X30347343
X3335332
QTY. DESCRIPTION
1
1
1
1
9
1
CAP 10 u f 20v
10% TANT. AX.
CAP 1 0 0 u f
ELECT. RAD. 2 0 %
CAP 1 0 0 0 pf 1 0 %
5 OV
XR7 SMD C 0 8 0 5
CAP 2 2 0 pf 5 0 V
2 0 % SMD C 0 8 0 5
IC, 7416
I C , MC1458
I C , LM339
I C , LM386
FERRITE BEAD
VOLT.REG. 7 8 L 0 5
1
1
1
1
RESET BUTTON
M I N I PHONE JACK
PHON0 JACK
POT. 1 0 K
2
1
2
25
DES I GNATOR
VENDOR
c20,21
PART
NUMBER
8336103
C4 2
8327108BAA
C27,34
X30210343
C1-19,28,31,
22,25,32,37
X30122243
u1
u3
u2
u4
FB1-9
VR1
s1
J6
J8
R4 0
GENERIC
FAIRRITE#2743002121
MOTOROLA MC78L05,
FAIRCHILD UA78L05
TEXAS I N S T . UA78L05C
ALPSIKHC15901
HSJ0862-01-1060
HSJ0842-01-1020
PT15N#510KA
8000016
8051458
8050339
8050386
8419013
8052805
8489065
8 519355
8519322
8270510
I
I
[email protected]
[email protected]
I
I
I
[email protected]
TANDY CORP.
MADE IN USA
170038Lf REV. B
PIN 8709867
S/A 8859110
AUDM/RESET I/O
I
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0
I
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0
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I
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I
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I-'.
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i
I
[email protected]
[email protected]
I
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[email protected]
1
m
m
I
[email protected]
CHARACTER
GENERATOR
1 4 MH7>
I
FLOPPY DISK DRIVE
KEYBOARD
24 MH7
24 MHz
16 MHz
16 MH7
Y2
I
1
SYSTEM CLOCK
BUS CLOCK
SERIAL RS-232-C
PARALLEL PRINTER PORT
FLOPPY DISK CONTROLLER CLOCK
FLOPPY DATA RATE
KEYBOARD DATA RATE
POWER SUPPLY SWITCHING RATE
++
-12v
8 / 4 MHZ
1 4 . 3 1 8 MHZ
1 4 . 3 AND 2 4 MHZ
500 CHAR/SEC MAX
16 MHZ
2 5 0 KBITS/SEC MAX
50 KBITS/SEC MAX
2 0 - 90 KHZ
CRYSTAL CONTROLLED OSCILLATOR Y1, Y2
EXPANSION
BUS
RS232C
JOYSTICKS
PRINTER
SOUND
41.6
5. 6. 7.
5.6.7.
41.3-
JmLs
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91.2
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TANDY
VIDEO I1
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m.2
81.2
81.2
m.2
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VIDEO
C- 8000302
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sH.4
sH.2
sH.2
91.2
91.2
sH.2
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1.
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I
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1
2
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91.2
91.4
91.2
91.2
91.2
91.2
91.2
91.2
91.2
91.2
91.2
91.3
91.2
91.2
91.2
91.4
111
BUS CONNECTORS
4
1
3
1
2
1
1
1
C-8000302
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DUG NO. 17ooJ18 REV. B
LAYERNAK
SILKSCREEN
LAYER M.
DATE
8/1/88
I
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[email protected]
I
I
-&I
REV. B
DUG ND. 1
LAYER N A M
COM)ONENT
LAYER ND.
1
DATE
8/1/88
SIDE
I
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I
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I
[email protected]
DWG M. 1788578 REV. B
LAYERNAPE
GN)pLAFE
LAYERM.
2
DATE
8/1/88
I
[email protected]
I
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DUG
M).
1900J78 REV. 8
LAYER NAME +5V R A M
LAYER No.
DATE
3
8/1/88
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DUG NO. 1700378 REV. 8
LAYER
NAME
SOLDER
LAYER
NO.
Lt
DATE
8/1/80
SIDE
I
[email protected]
I
[email protected]
Devices
TANDY BUFFER BLUE CUSTOM IC
PART # 8079024
The i n f o r m a t i o n c o n t a i n e d h e r e i n i s e x c l u s i v e p r o p e r t y of Tandy
C o r p o r a t i o n . N o r e p r o d u c t i o n of a n y k i n d may b e made w i t h o u t t h e
express w r i t t e n a u t h o r i z a t i o n of:
Tandy C o r p o r a t i o n
1 0 0 0 Two Tandy C e n t e r ,
F o r t Worth, T e x a s , 76102.
Table Of Contents
BUFFER BLUE PRELIMINARY SPECIFICATION
1.0 GENERAL
2.0
PIN LIST
3.0
ABSOLUTE MAXIMUM RATINGS
4.0
D. C. ELECTRICAL CHARACTERISTICS
5 .O AC CHARACTERISTICS
BUFFER BLUE PRELIMINARY SPECIFICATION
1 . 0 GENERAL
F u n c t i o n a l Description
1.1
The B u f f e r B l u e Custom I C i s a VLSI ASIC f o r u s e i n a PC/XT
It comprises t h e
t y p e a r c h i t e c t u r e u s i n g a n 8086 m i c r o p r o c e s s o r .
f o l l o w i n g elements:
- 8237 E q u i v q l e n t .
- DRAM c o n t r o l .
- A d d r e s s b u f f e r i n g and d e c o d i n g .
- Data Conversion and Buffering.
I t is c o n t a i n e d i n
mount i ng
.
2.0
a 100
p i n f l a t package s u i t a b l e f o r s u r f a c e
PIN LIST
PIN NAME
QW.
vcc
4
4
GND
-
I/o
DESCRIPTION
Power i n p u t s
Grounds
AD15
16
Bidir.
Multiplexed a d d r e s s and
data signals for
c o n n e c t i o n t o 8086 CPU,
ROM d a t a , a n d 16 b i t RAM
data.
-
4
Bidir.
A d d r e s s i n p u t s f r o m CPU,
A d d r e s s o u t p u t s f r o m DMA.
3
Inputs
S t a t u s i n p u t s f r o m CPU.
BH EB
1
Input
Bus High E n a b l e f r o m CPU
o r DMA.
RQ/GTB
1
Bidir.
Bus c o n t r o l h a n d s h a k i n g
w i t h CPU.
READY
1
output
CPU r e a d y s i g n a l , a c t i v e
high. This s i g n a l is
s y n c h r o n i z e d w i t h Clock.
RESET
1
output
CPU Reset s i g n a l , a c t i v e
high. This signal is
synchronized w i t h Clock.
ADO
ADR16
so -
s2
ADR19
1
PIN NAME
QTY.
I/O
DESCRIPTION
CPUCLK
1
output
CPU c l o c k s i g n a l , 1 2 MHz
50 % d u t y c y c l e , o r 8 o r
4 MHz 3 3 % d u t y c y c l e ,
i n t e r n a l l y switchable.
All
12
outputs
B u f f e r ed b u s a d d r ess
outputs, intended t o
d r i v e 5 XT t y p e 1/0
s l o t s , a s w e l l as a few
on board p e r i p h e r a l s .
-
8
Bidir.
Eight b i t peripheral data
bus, intended t o d r i v e 5
XT t y p e 1/0 s l o t s , a s
well a s a l l on b o a r d
peripherals.
I ORB
1
output
CPU/DMA 1/0 Read s i g n a l ,
a c t i v e low.
System
control line.
I OWB
1
output
CPU/DMA 1/0 W r i t e s i g n a l ,
a c t i v e low.
System
control line.
MEMRB
1
output
CPU/DMA Memory Read
s i g n a l , a c t i v e low.
System c o n t r o l l i n e .
MEMWB
1
output
CPU/DMA Memory W r i t e
s i g n a l , a c t i v e low.
System c o n t r o l l i n e .
RSTINB
Input
Master reset i n p u t ,
synchonized.
RDYIN
Input
Unsynchronized ready
input.
CPUALE
output
CPU Address L a t c h Enable.
S2
Decoded f r o m CPU SO
when u s e d w i t h C P U
a c c e s s e s . Used t o l a t c h
a d d r e s s e s on t h e
multiplexed address/data
bus.
output
DMA A d d r e s s L a t c h E n a b l e .
G e n e r a t e d by i n t e r n a l
t i m i n g when u s e d w i t h DMA
a c c e s s e s . used t o l a t c h
a d d r e s s e s o n t h e 1/0 b u s .
AQ
-
IODO
BUSALE
IOD7
1
2
-
PIN NAME
QTY.
I/O
DESCRIPTION
HLDA
1
Output
I n d i c a t e s DMA c y c l e i n
progress.
INTAB
1
Output
Decode of S 2 - SO t o
i n d i c a t e an i n t e r r u p t
acknowledge c y c l e i n
progress.
OSCIN
1
Input
C l o c k i n p u t , 30 MHz max,
50 % d u t y c y c l e .
9
Outputs
M u l t i p l e x e d Memory
Addresses. Intended t o
d r i v e 20 MOS memory
devices.
2
Outputs
Memory w r i t e e n a b l e
s i g n a l , a c t i v e low.
I n t e n d e d t o d r i v e 1 0 MOS
memory d e v i c e s .
RASOB RASlB
RAS2B ,RAS3B
4
Outputs
Memory Row A d d r e s s
S t r o b e s , a c t i v e low.
I n t e n d e d t o d r i v e 1 6 MOS
memory d e v i c e s . A l l
others intended t o d r i v e
4 MOS memory d e v i c e s
each.
CASB
1
Output
Memory Column A d d r e s s
S t r o b e s , a c t i v e low.
Each i n t e n d e d t o
d r i v e 20 MOS memory
devices.
DRQ1, DRQ3
FDDMARQ
3
Inputs
DMA c h a n n e l r e q u e s t s .
DACK1, DACK3
FDDMACKB
3
Outputs
DMA a c k n o w l e d g e s i g n a l s .
DMATC
1
Output
DMA e n d of p r o c e s s
signal.
ROMCS OB
ROMCSlB
2
Output
A c t i v e Low ROM C h i p
select v a l i d during a
MEMR w i t h A17, A l a , and
A19 a c t i v e .
MA0
-
MA8
WEHB, WELB
,
3
QTY.
I/O
DESCRIPTION
3
outputs
1/0 o r Rom p a g i n g
d e c o d e s , d e p e n d i n g upon
w h e t h e r a memory o r 1/0
c y c l e is i n p r o g r e s s .
IOCHCK
Input
NMI from 1/0 B u s .
COPRNMI
Input
N M I from 8 0 8 7
Coprocessor.
NMI OUT
output
N M I t o CPU.
REFRESH
output
Refresh request to t h e
1/0 Bus.
TRESET
Input
T e s t p i n . Must b e t i e d
Low.
PIN NAME
SELO
3.0
-
SEL2
ABSOLUTE M A X I M U M RATINGS
Min
-
S t o r a g e Temperature :
Operating Temperature:
A l l output pins
A l l input pins
Power S u p p l y ( V c c )
Power d i s s i p a t i o n
.
D.
4.1
Inputs
Leakage c u r r e n t
Vih
Vi1
2.0
-0.5
I n p u t capacitance
4.2
25
Max
-
Units
150
70
7.0
7.0
7.0
750
degrees C
degrees C
v o l t s DC
v o l t s DC
v o l t s DC
milliwatts
Max
-
Units
+/-lo
uA
v o l t s DC
v o l t s DC
PF
. ELECTRICAL CHARACTERISTICS
4 0
C
-65
0
-0.5
-0.5
-0.5
Typ
vcc+. 5
0.8
10
RQ/GT, READY, CLOCK, INTAK, ROMCSOB, ROMCSOB,
DACKl-DACK3, EOP, SELO-SELZ, NMIOUT, CPUALE
Min
Io1
vo 1
Ioh
Voh
Capacitive load
Max
2
mA
0.4
1
2.4
40
4
Units
v o l t s DC
mA
v o l t s DC
PF
4.3
ADO
-
AD15
Min
Io1
Units
mA
v o l t s DC
0.4
Ioh
Voh
C a p a c i t i v e load
RASlB,
RASZB,
1
2.4
mA
80
PF
Min Typ Max
Units
2
mA
v o l t s DC
RAS3B
Io1
vo 1
v o l t s DC
0.4
Ioh
1
2.4
160
Voh
C a p a c i t i v e load
4.5
Max
2
vo 1
4.4
Typ
MAO-MA8,
RASOB,
mA
v o l t s DC
PF
CASB
w i t h Slew R a t e C o n t r o l
Min Typ
Io1
Units
8
vo 1
mA
v o l t s DC
0.4
Ioh
Voh
C a p a c i t i v e load
4.6
Max
MEMRB, MEMWB, I O R B ,
IODO-IOD7,
REFRESH,
1
2.4
mA
160
PF
v o l t s DC
IOWB, B U S A L E , HLDA,
R E S E T , WEHB, WELB
BHE,
AO-Al9,
with Slew Rate Control
Min Typ
Io1
6
vo 1
Voh
C a p a c i t i v e load
NOTE:
Units
mA
0.4
Ioh
5.0
Max
v o l t s DC
2
2.4
mA
80
PF
v o l t s DC
AC C H A R A C T E R I S T I C S
A l l p i n s loaded w i t h 85pf except Memory A d d r e s s
RASO, and C A S , w h i c h a r e loaded a t 1 4 0 p f .
5
(MAO-8),
TIMING DIAGRAMS
FIGURE 1.
I <----------e-----I < - t H I ->I
I
I
I
I
I/
\I
......./
/I
0.4V... .../ I
-/I
I
VOH 4 . 0 V
VOL
CPUCLK
\
I 1
t R ->I I <
FIGURE 2 .
>I
tcyc
I
I<--I
....................
tLOW
---------------> I
I
I
I\ I
I \I
I
I
I /
I/
/
\
I
I<- t F
RESET
\
1
/
CPUCLK
?
/
\
I\
I
I
-I
\ /
RSTINB
RESET
6
FIGURE 3.
READY
I<+++++
I
CPUCLK
(OUTPUT)
/-
/
/
I
\I
I < - tl
I <--t2-->
I
t3-->I
\I
READY
(OUTPUT)
CPUCLK
(OUTPUT)
t5-->
TRUE
(INPUT)
RDYIN,
I
I
I
I<-
\-
I
I
I/
I
+++++++>I
//I
I\
-> I
RDY I N I FALS E
(INPUT)
T3/TW
I
I
I
I
1
-
I
I/-I
I
\
\-
I
I
I <-t4-> I
I/
/
/
I<+++++ T3/TW +++++++>I
I
I
\
.-/
/
I\
/I
\I
I
I
->I
I<-t6
->I
I <-I
I
I
I- \
I
I
I
\
I
I
I
I <----t 7 ---->I
t8
I<- : - / II
//I
I
I<-
-/
READY
(OUTPUT)
/
7
\-
tCH
FIGURE 4.
ALE
CONTROL GENERATOR
I
/
I
I
t7>I
I
IOR, MEMRINTAB
IOW,MEMW
I
t8>l I <
> II < t 6
I
\
8
I<
I
/-
FIGURE 5A.
ARBITTER/REQUEST
-
\
\-
CPUCLK
(ref)
RQ/GTB
/-\
/
(REQUEST t o CPU)
(output)
RQ/GTB (ACKNOWLEDGE f r o m
(input)
I <-
0 c l o c k s min
-> I
I
/--\ I
1-\
/
\
/
\
/I
\
1
\/
t2->II<--t 3 7 I
-I
I
I 1
I
I
I/-I-I
\
I REQUEST and ACKNOWLEDGE
I c a n o v e r l a p and be s e e n
7’
I
I
I a s o n e p u l s e by t h e
- > I t 4 I<- I
I
I circuit.
I <I/
CPU)
/
-1
t 6 ->I
I<I/
I
I
I
I
/-\
I
HLDA
FIGURE 5B.
ARBITTER/RELEASE
CPUCLK
(external)
/-\
1-\
\-
t 2
RQ/GTB (RELEASE t o CPU)
(output)
/I/-\
)-
/
->i
1
I<-
\I
\-I
i
I
/-\
->i
\I
/
1<-t3
I/-
I
-I
I<- t 6 - > I
/
I
\I
HLDA
A R B I T T E R PARAMETER
9
\-
MEMORY A C C E S S T I M I N G (NO R E F R E S H )
tl
t2
t3
t4
t5
t6
t7
t8
t9
t10
ADDRESS S E T U P T O RAS
ROW ADDRESS HOLD T I M E
RAS- WIDTH
COLUMN ADDRESS S E T U P T I M E
RAS- T O CAS- T I M E
WE- TO CAS- S E T U P T I M E
COLUMN ADDRESS HOLD T I M E
CAS- WIDTH
WE- WIDTH
RAS- PRECHARGE
min
25
17
150
29
73
29
40
230
220
109
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADDRESS AND DATA BUS
-
I
I
- 1
I
x-x
AD15
0
(write)
x=
data out
I <t3
>I
AD15 - 0
(I:e a d )
-
ADR19
,BHE
1
I
/-\
ALE ( r e f )
All
-
I
> I1 < t 8
I
X
A0
-
PACKAGE P I N O U T
QUAD F L A T PACK ( P R O D U C T I O N )
PACKAGE: P B 3 0 , D I E S I Z E : 5.510MM x 5.500MM
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
AD 1
ADO
BUSALE
C P UALE
CPUCLK
DRQl
FDDMARQ
DRQ3
IODO
IODl
IOD2
IOD3
IOD4
VDD
vs s
IOD5
IOD6
IOD7
IORB
I OWB
MEMRB
MEMWB
RQGTB
COPRNMI
BHEB
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
OSC24M
TRESET
RDYIN
RSTINB
IOCHCKB
DACKlB
FDDMACKB
DACK3B
A0
A1
A2
A3
A4
A5
vs s
VDD
A6
A7
A8
A9
A 10
A 11
SOB
S1B
S2B
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
11
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
HLDA
REFRESH
WELB
WE HB
RESET
READY
NMI OUT
INTAB
SEL2
SELl
SELO
ROMC SB 1
ROMCSBO
DMATC
CASB
vs s
VDD
RAS3B
RAS2B
RASlB
RASOB
MA8
MA7
MA6
MA5
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
MA4
MA3
MA2
MA1
MA0
ADD19
ADDl 8
ADD17
ADDl 6
AD15
AD14
AD1 3
AD12
VDDl
vs s
AD11
AD10
AD 9
AD 8
AD 7
AD6
AD5
AD4
AD3
AD2
6.0
PORT DEFINITION MAP
PORT 0 0
DMA C o n t r o l l e r
IOW* = 0: C h a n n e l
Internal
Internal
I O R * = 0: C h a n n e l
0 Base and C u r r e n t A d d r e s s
F l i p / F l o p = 0: Write AO-A7
F l i p / F l o p = 1: Write A8-Al5
0 Current Address
I n t e r n a l F l i p / F l o p = 0: Read AO-A7
I n t e r n a l F l i p / F l o p = 1: Read A8-Al5
PORT 0 1
DMA C o n t r o l l e r
IOW* = 0: C h a n n e l 0 Base and C u r r e n t Word C o u n t
Internal
Internal
IOR* = 0: C h a n n e l
Internal
Internal
PORT 0 2
Flip/Flop
Flip/Flop
0 Current
Flip/Flop
Flip/Flop
= 0: Write WO-W7
= 1: Write W8-Wl5
Word C o u n t
= 0: Read WO-W7
= 1: Read W8-Wl5
DMA C o n t r o l l e r
IOW* = 0: C h a n n e l 1 Base a n d C u r r e n t A d d r e s s
Internal
Internal
IOR* = 0 Channel
Internal
Internal
F l i p / F l o p = 0: Write AO-A7
F l i p / F l o p = 1: Write A8-Al5
1 Current Address
F l i p / F l o p = 0: Read AO-A7
F l i p / F l o p = 1: Read A8-Al5
PORT 0 3
DMA C o n t r o l l e r
IOW* = 0: C h a n n e l 1 Base a n d C u r r e n t Word C o u n t
I n t e r n a l F l i p / F l o p = 0: Write WO-W7
I n t e r n a l F l i p / F l o p = 1: Write W8-Wl5
I O R * = 0: C h a n n e l 1 C u r r e n t Word C o u n t
I n t e r n a l F l i p / F l o p = 0: Read WO-W7
I n t e r n a l F l i p / F l o p = 1: Read W8-Wl5
PORT 0 4
DMA C o n t r o l l e r
IOW* = 0: C h a n n e l 2 Base a n d C u r r e n t A d d r e s s
I n t e r n a l F l i p / F l o p = 0: Write AO-A7
I n t e r n a l F l i p / F l o p = 1: Write A8-Al5
I O R * = 0: C h a n n e l 2 C u r r e n t A d d r e s s
I n t e r n a l F l i p / F l o p = 0: Read AO-A7
I n t e r n a l F l i p / F l o p = 1: Read A8-Al5
PORT 0 5
DMA C o n t r o l l e r
IOW* = 0: C h a n n e l
Internal
Internal
IOR* = 0: C h a n n e l
Internal
Internal
2 Base and C u r r e n t Word C o u n t
Flip/Flop
Flip/Flop
2 Current
Flip/Flop
Flip/Flop
= 0:
= 1:
Word
= 0:
= 1:
12
Write WO-W7
Write W8-Wl5
Count
Read WO-W7
Read W8-Wl5
PORT 06
DMA Con t r 01 l e r
IOW* = 0: C h a n n e l
Internal
Internal
IOR* = 0: Channel
Internal
Internal
PORT 07
DMA C o n t r o l l e r
IOW* = 0: Channel 3 Base and C u r r e n t Word C o u n t
Internal
Internal
I O R * = 0: C h a n n e l
Internal
Internal
PORT 08
BIT
0
1
2
3
4
5
6
7
3 Base and C u r r e n t A d d r e s s
F l i p / F l o p = 0: Write AO-A7
F l i p / F l o p = 1: Write A8-Al5
3 Current Address
F l i p / F l o p = 0: Read AO-A7
F l i p / F l o p = 1: Read A8-Al5
Flip/Flop
Flip/Flop
3 Current
Flip/Flop
Flip/Flop
= 0: Write WO-W7
= 1: Write W8-Wl5
Word Count
= 0: Read WO-W7
= 1: Read W8-Wl5
DMA C o n t r o l l e r
IOW* = 0 , Write Command R e g i s t e r
Description
0 = Memory t o Memory D i s a b l e
1 = Memory t o Memory E n a b l e
0 = C h a n n e l 0 A d d r e s s Hold D i s a b l e
1 = C h a n n e l 0 A d d r e s s Hold E n a b l e
X
If bit 0 = 0
0 = Controller enable
1 = Controller disable
0 = Normal t i m i n g
1 = Compressed t i m i n g
x If b i t 0 = 1
0 = Fixed p r i o r i t y
1 = Rotating p r i o r i t y
0 = L a t e write s e l e c t i o n
1 = Extended write s e l e c t i o n
x If b i t 3 = 1
0 = DREQ s e n s e a c t i v e h i g h
1 = DREQ s e n s e a c t i v e low
0 = DACK s e n s e a c t i v e low
1 = DACK s e n s e a c t i v e h i g h
I O R * = 0 , Read S t a t u s R e g i s t e r
BIT
0
1
2
3
4
5
6
7
Desc r i p t i o n
1 = Channel
1 = Channel
1 = Channel
1 = Channel
1 = Channel
1 = Channel
1 = Channel
1 = Channel
has reached
h a s reached
has reached
h a s reached
Request
Request
2 Request
3 Request
0
1
2
3
0
1
TC
TC
TC
TC
13
PORT 0 9
BIT
0- 1
2
3-7
PORT OA
BIT
0- 1
2
3-7
DMA C o n t r o l l e r
IOW* = 0 , Write R e q u e s t R e g i s t e r
Description
B i t l BitO
0
0
S e l e c t channel
0
1
S e l e c t channel
1
0
S e l e c t channel
1
1
S e l e c t channel
0
R e s e t request b i t
1
Set request b i t
D o n ' t Care
IOR* = 0 , I l l e g a l
0
1
2
3
DMA C o n t r o l l e r
IOW* = 0 , Write S i n g l e M a s k R e g i s t e r
Description
B i t l BitO
0
0
S e l e c t channel 0 mask b i t
0
1
S e l e c t c h a n n e l 1 mask b i t
1
0
S e l e c t channel 2 mask b i t
1
1
S e l e c t channel 3 mask b i t
0
Clear m a s k b i t ( E n a b l e C h a n n e l )
1
S e t mask b i t ( D i s a b l e Channel)
D o n ' t Care
IOR* = 0 , I l l e g a l
14
PORT OB
BIT
0-1
2-3
4
5
6-7
PORT OC
DMA C o n t r o l l e r
IOW* = 0 , Write Mode Register
Description
Bit1 Bit0
0
0 Channel 0 s e l e c t
0
1 Channel 1 s e l e c t
1
0 Channel 2 s e l e c t
1
1 Channel 3 s e l e c t
Bit3 B i t 2
0
0 Verify t r a n s f e r
0
1 Write t r a n s f e r t o memory
1
0 Read t r a n s f e r t o memory
1
1 Illegal
X
I f b i t s 6 and 7 = 11
0
Autoinitialization disable
1
Auto i n i t i a l i z a t i o n enable
0
Address increment s e l e c t
1
Address decrement s e l e c t
Bit7 Bit6
0
0 Demand mode s e l e c t
0
1 Single mode s e l e c t
1
0 Block mode s e l e c t
1
1 Cascade mode s e l e c t
IOR* = 0 , I l l e g a l
DMA C o n t r o l l e r
IOW* = 0 , Clear Byte P o i n t e r Flip/Flop
IOR* = 0 , I l l e g a l
PORT OD
DMA C o n t r o l l e r
row* = 0 , Master Clear
IOR* = 0 , Read Temporary Register
PORT OE
DMA Con t r 01 l e r
IOW* = 0 , Clear Mask Register
IOR* = 0 , I l l e g a l
PORT OF
DMA C o n t r o l l e r
IOW* = 0 , Write a l l
Description
0 = Clear channel
1 = S e t channel 0
0 = Clear channel
1 = S e t channel 1
0 = Clear channel
1 = S e t channel 2
0 = Clear channel
1 = S e t channel 3
Don't Care
IOR* = 0 , I l l e g a l
Bit
0
1
2
3
4-7
Mask Register B i t s
0 mask b i t (Enable)
mask b i t (Disable)
1 mask b i t (Enable)
mask b i t (Disable)
2 mask b i t (Enable)
mask b i t (Disable)
3 mask b i t (Enable)
mask b i t (Disable)
15
PORT 6 2
B I T 3:
PORT 6 5
B I T 2:
-
- WRITE
ONLY I N BUFFER BLUE
0 = 16 B i t Video
1= 8 B i t Video (default)
PORT 80
PORT 8 1
Bit
0
1
DMA Page R e g .
-
2
3
4-7
PORT 82
B i t
0
-
1
2
3
4-7
PORT 83
Bit
0
-
7
-
(Not Used)
WRITE ONLY
D e s c r iption
DMA C h 2 A d d r e s s
DMA C h 2 A d d r e s s
DMA C h 2 A d d r e s s
DMA C h 2 A d d r e s s
Not Used
WRITE ONLY
D e s c r i pt i o n
DMA C h 3 A d d r e s s
DMA C h 3 A d d r e s s
DMA C h 3 A d d r e s s
DMA C h 3 A d d r e s s
N o t Used
A16
A17
A18
A19
A16
A17
A18
A19
WRITE ONLY
Description
1Address
DMA C h 0
1Address
DMA C h 0
1 Address
DMA C h 0
DMA C h 0
1 Address
Not Used
-
1
2
3
4-7
PORT A0
Bit
WRITE ONLY I N BUFFER BLUE
0 = S l o w CPUCLK ( d e f a u l t )
1 = F a s t CPUCLK
A16
A17
A18
A19
NMI M a s k R e g i s t e r , Write o n l y
Descr iption
1 = E n a b l e NMI
0 = D i s a b l e NMI ( d e f a u l t )
16
PORT F F E 9 - WRITE/READ
B I T 0:
0 = Z e r o W a i t s t a t e s for I n t e r n a l Memory
1 = O n e Wait S t a t e f o r I n t e r n a l M e m o r y
BIT
Description
1-2
Bit2 Bit1
0
0 Zero Wait S t a t e s f o r I n t e r n a l M e m o r y
0
1 O n e W a i t State for I n t e r n a l Memory
1
0 Two W a i t S t a t e s f o r I n t e r n a l M e m o r y
1
1 T h r e e W a i t States for I n t e r n a l Memory
BIT
Description
3-4
Bit4 Bit3
0
0 Z e r o W a i t S t a t e s f o r CPU I / O c y c l e
0
1 O n e Wait S t a t e f o r CPU I / O c y c l e
1
0 Two W a i t S t a t e s f o r CPU I / O c y c l e
1
1 T h r e e W a i t S t a t e s f o r CPU 1/0 c y c l e
B I T 5: 0 = E a r l y Write S t r o b e f o r DMA c y c l e
1 = N o E a r l y Write S t r o b e f o r DMA cycle
B I T 6:
0 = Z e r o W a i t States for 16 B i t V i d e o
1 = O n e W a i t State for 16 B i t V i d e o
B I T 7:
M u s t be 0 w h e n O S C I N i s e q u a l t o 2 8 . 6 3 6 3 6 M H z
M u s t be 1 w h e n O S C I N is e q u a l t o 2 4 MHz ( d e f a u l t )
PORT FFEA
B I T 0:
B I T 1:
B I T 2:
B I T 3:
B I T 4:
B I T 5:
BIT
6-7
-
WRITE/READ
ROM' PAGING 0
ROM PAGING 1
ROM PAGING 2
ROM PAGING 3
ROM PAGING 4
Not Used
Description
Bit7 Bit6
0
0 Two B a n k s of 1 2 8 K m e m o r y
0
1 F o u r B a n k s of 128K m e m o r y
1
0 O n e B a n k of 5 1 2 K m e m o r y
1
1 O n e B a n k of 512K m e m o r y , O n e B a n k of 128K m e m o r y
NOTE: When r e a d i n g P o r t F F E A , b i t 4 w i l l be i n v e r t e d f r o m w h a t w a s w r i t t e n ,
(i.e. w h e n a 0 w a s w r i t t e n , a 1 w i l l be read; w h e n a 1 w a s w r i t t e n , a 0 w i l l
be read.)
17
ROM P a g i n g D e f i n i t i o n :
Two 2 Meg ROMs
(TWO 1 Meg ROMs)
ADDRESS
19 18 17 16
F0000-FFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
TWO 4 Meg ROMS
F0000-FFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
~0060-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
E0000-EFFFF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
19
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 1
1 1
1 1
1 1
1
1
1
1
18 17
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
16
1
0
0
0
0
0
0
0
0
0
0
o
0
0
0
0
0
ROM PAGES
4 3 2 1 0
x x x x x
1 x 1 1 1
1 x 1 1 0
1 x 1 0 1
1 x 1 0 0
1 x 0 1 1
1 x 0 1 0
1 x 0 0 1
1 x 0 0 0
4 3 2 1 0
X X x x x
0 1 1 1 1
0 1 1 1 0
0 1 1 0 1
0 1 1 0 0
0 1 0 1 1
0 1 0 1 0
0 1 0 0 1
0 1 0 0 0
0 0 1 1 1
0 0 1 1 0
0 0 1 0 1
0 0 1 0 0
0 0 0 1 1
0 0 0 1 0
0 0 0 0 1
0 0 0 0 0
18
ROMCS
# O #1
0
1
0
0
0
1
1
1
1
#O
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
#1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
SELECT
2 1 0
x l l
x x x
x 1 0
x x l
x o o
64K P a g e
ROMO ROMl
1
2
3
4
x l l
x 1 0
1
2
3
x o 1
x
2
1
x
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
o
1
1
x
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
o
0
1
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
4
ROMO ROMl
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
U
8237~
HIGH PERFORMANCE
PROGRAMMABLE DMA CONTROLLER
(a237~,a237~-4,8237~-5)
Enabie/Dlsable Control of Individual
DMA Requests
Four independent DMA Channels
Independent Autoinitialization of Ail
Channels
Memory-to-Memory Transfers
Memorv Block initialization
Address Increment or Decrement
High Performance: Transfers up to
1.6M Bytes/&cond with MHz 823715-5
8 Directly Expandable to Any Number of
w
w
8
8
Channels
End of Proce8.s input for Termlnating
Transfers
Software DMA Requests
Independent Polarity Control for DREQ
and DACK Signals
Available in EXPRESS
Standard Temperature Range
Available In IO-Lead Cerdlp and Plastic
Packages
-
(See P*ging
Spec. Order r231369)
The 8237A Multimode Direct Memory Access (DMA) Controller is a peripheral interface circuit for microprocessor systems. It is designed to improve system performance by allowing external devices to directly transfer
information from the system memory. Memory-to-memory transfer capability is also provided. The 8237A
offers a wide variety of programmable control features to enhance data throughput and system optimization
and to allow dynamic reconfiguration under program control.
The 8237A is designedto be used in conjunction with an external 8-bit address latch. It contains four independent channels and may be expandedto any number of channels by cascading additional controller chips. The
three basic transfer modes allow programmabilityof the types of DMA service by the user. Each channel can
be individually programmed to Autoinitialize to its original condition following an End of Process
Each
channel has a full 64K address and word count capability.
(m).
The 8273A-4 and 8237A-5 are 4 MHz and 5 MHz versions of the standard 3 MHz 8237A respectively.
231406-2
231466-1
Figure 1. Block Diagram
2-234
Figure 2. Pin
Contlguration
w
8237A
Table 1. Pln Descrlptlon
I
Symbol
1
+ 5v supply.
vcc
POWER
vss
GROUND Ground.
CLK
I
Name and Function
TYP
I
CLOCK INPUT Clock Input controls the internal operations of the
8237A and its rate of data transfers. The input may be driven at up
to 3 MHz for the standard 8237A and up to 5 MHz for the 8237A-5.
I
CHIP SELECT Chip Select is an active low input used to select
the 8237A as an I/O device during the Idle cycle. This allows CPU
communicationon the data bus.
RESET
I
RESET Reset is an active high input which clears the Command,
Status, Request and Temporary registers. It also clears the first/
last flip/flop and sets the Mask register. Followinga Reset the
device is in the Idle cycle.
READY
I
READY Ready is an input used to extend the memory read and
write pulses from the 8237A to accommodateslow memories or
I10 peripheraldevices. Ready must not make transitions during its
specified setup/hold time.
I
HOLD ACKNOWLEDGEThe active high Hold Acknowledgefrom
the CPU indicates that it has relinquishedcontrol of the system
busses.
I
DMA REQUEST The DMA Request lines are individual
asynchronouschannel request inputs used by peripheralcircuits to
obtain DMA service. In fixed Priority, DREQO has the highest
priority and DREQ3 has the lowest priority. A request is generated
by activating the DREQ line of a channel. DACK will acknowledge
the recognition of DREQ signal. Polarity of DREQ is
programmable. Reset initializes these lines to active high. DREQ
must be maintaineduntil the correspondingDACK goes active.
I
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~~
~
~
I10
DATA BUS The Data Bus lines are bidirectionalthree-state
signals connected to the system data bus. The outputs are
enabled in the Program condition during the I/O Read to output
the contents of an Address register, a Status register, the
Temporary register or a Word Count register to the CPU. The
outputs are disabled and the inputs are read during an I10Write
cycle when the CPU is programmingthe 8237A control registers.
During DMA cycles the most significant 8 bits of the address are
output onto the data bus to be strobed into an external latch by
ADSTB. In memory-to-memoryoperations,data from the memory
comes into the 8237A on the data bus during the read-frommemory transfer. In the write-to-memorytransfer, the data bus
outputs place the data into the new memory location.
I10
I/O READ I10 Read is a bidirectional active low three-state line.
In the Idle cycle, it is an input control signal used by the CPU to
read the control registers. In the Active cycle, it is an output control
signal used by the 8237A to access data from a peripheralduring a
DMA Write transfer.
I10
I/O WRITE I/O Write is a bidirectional active low three-state line.
In the Idle cycle, it is an input control signal used by the CPU to
load information into the 8237A. In the Active cycle, it is an output
control signal used by the 8237A to load data to the peripheral
during a DMA Read transfer.
2-235
'able 1. Pln Dercrlptlon (Continued)
-
Symbol
Name and Function
m
END OF PROCESS:End of Processis an active low bidirectional
signal. Informationconcemin the completion of DMA services is
pin. The 8237A allows an
available at the bidirectional
external signal to terminate an active DMA service. This is
input low with an external
accomplishedby pulling the
signal. The 823719 also generatesa pulse when the terminal count
(TC) for any channel is reached. This generatesan
si nal
either
which is output through the
line. The reception of
internalor external, will cause the 8237A to terminate the service,
reset the request, and, if Autoinitialize is enabled, to write the base
registers to the current registers of that channel. The mask bit and
TC bit in the status word will be set for the currently active channel
by
unless the channel is programmed for Autoinitialize. In that
case, the mask bit remainsunchanged. During memory-to-memory
transfers,
will be output when the TC for channel 1 occurs.
should be tied high with a pull-up resistor if it is not used to
prevent erroneousend of process inputs.
ib
AQ-A3
A4-A7
I
ADDRESS: The four least significant address lines are
bidirectionalthree-state signals. In the Idle cycle they are inputs
and are used by the CPU to addressthe register to be loaded or
read. In the Active cycle they are outputs and provide the lower 4
bits of the output address.
0
ADDRESS: The four most significant address lines are three-state
outputs and provide 4 bits of address. These lines are enabled
only during the DMA service.
0
HOLD REQUEST:This is the Hold Requestto the CPU and is
used to request control of the system bus. If the corresponding
mask bit is clear, the presence of any valid DREQ causes 8237A to
issue the HRQ.
0
DMA ACKNOWLEDGE: DMA Acknowledgeis used to notify the
individualperipheralswhen one has been granted a DMA cycle.
The sense of these lines is programmable. Reset initializes them
to active low.
0
ADDRESS ENABLEAddress Enableenables the &bit latch
containing the upper 8 address bits onto the system address bus.
AEN can also be used to disable other system bus drivers during
DMA transfers. AEN is active HIGH.
0
ADDRESS STROBE The active high, Address Strobe is used to
strobe the upper address byte into an external latch.
0
MEMORY READ The Memory Read signal is an active low threestate output used to access data from the selected memory
location durina a DMA Read or a memow-to-memowtransfer.
-HRQ
DACKO-DACK3
I
I
d,
ADSTB
4
~
~~
~~
~
MEMORY WRITE The Memory Write is an active low three-state
output used to write data to the selected memory location during a
DMA Write or a memory-to-memory transfer.
1
PIN& This pin should always be at a logic HIGH level. An internal
pull-up resistor will establish a logic high when the pin is left
floating. It is recommendedhowever, that PIN5 be connected to
vcc.
2-236
w
8237A
valid DMA requests pending. While in SI, the DMA
controller is inactive but may be in the Program Condition, being programmed by the processor. State
SO (SO) is the first state of a DMA service. The
8237A has requested a hold but the processor has
not yet returned an acknowledge. The 8237A may
still be programmed until it receives HLDA from the
CPU. An acknowledge from the CPU will signal that
DMA transfers may begin. Si, S2, S3 and S4 are the
working states of the DMA service. If more time is
needed to complete a transfer than is available with
normal timing, wait states (SW) can be inserted between S2 or S3 and S4 by the use of the Ready line
on the 8237A. Note that the data is transferred directl from the I10 device to memory or vice versa)
and MEMW (or
and
being acwith
tive at the same time. The data is not read into or
driven out of the 8237A in 110-to-memory or memory-to-l/O DMA transfers.
FUNCTIONAL DESCRIPTION
The 8237A block diagram includes the major logic
blocks and all of the internal registers. The data interconnection paths are also shown. Not shown are
the various control signals between the blocks. The
8237A contains 344 bits of internal memory in the
form of registers. Figure 3 lists these registers by
name and shows the size of each. A detailed d e
scription of the registers and their functions can be
found under Register Description.
Nunkr
18 bb
18 bit0
18 bb
18 bb
18 bb
18bb
8bb
8bb
8bito
6bb
4 m
4 m
4
4
4
4
1
1
1
1
1
4
1
1
‘faR
Flgure 3.8237A Internal Regl8tOr8
The 8237A contains three basic blocks of control
logic. The Timing Control block generates internal
timing and external control signals for the 8237A.
The Program Command Control block decodes the
various commands given to the 8237A by the microprocessor prior to servicing a DMA Request. It also
decodes the Mode Control word used to select the
type of DMA during the servicing. The Priority End e r block resolves priority contention between
)MA channels requesting service simultaneously.
k)
Memory-to-memory transfers require a read-from
and a write-to-memory to complete each transfer.
The states, which resemble the normal working
states, use two digit numbers for identification. Eight
states are requiredfor a single transfer. The first four
states (Sll, S12, S13, S14) are used for the readfrom-memory half and the last four states (S21, S22,
S23, S24) for the write-to-memory half of the transfer.
IDLE CYCLE
DMA OPERATION
When no channel is requesting service, the 8237A
will enter the Idle cycle and perform “SI” states. In
this cycle the 8237A will sample the DREQ lines every clock cycle to determine if any channel is reuesting a DMA service. The device will also sample
35 looking for an attempt by the microprocessorto
write or read the internal registers of the 8237A.
When
is low and HLDA is low, the 8237A enters
the Program Condition. The CPU can now establish,
change or inspect the internal definition of the part
by reading from or writing to the internal registers.
Address lines AO-A3 are inputs to the device and
select which registers will be read or written. The
T6R and
lines are used to select and time reads
or writes. Due to the number and size of the internal
registers, an internal flip-flop is used to generate an
additional bit of address. This bit is used to determine the upper or lower byte of the 16-bit Address
and Word Count registers. The flip-flop is reset by
Master Clear or Reset. A separate software command can also reset this flip-flop.
The 8237A is designed to operate in two major cycles. These are called Idle and Active cycles. Each
device cycle is made up of a number of states. The
8237A can assume seven separate states, each
composed of one full clock period. State I (SI) is the
inactive state. It is entered when the 8237A has no
Special software commands can be executed by the
8237A in the Program Condition. These commands
are decoded as sets of addresses with the
and
The commands do not make use of the data
bus. Instructions include Clear First/Last Flip-Flop
and Master Clear.
The Timing Control block derives internal timing
from the clock input. In 8237A systems, this input
will usually be the 42 l T L clock from an 8224 or
CLK from an 8085AH or 8284A. 33% duty cycle
clock generators, however, may not meet the dock
high time requirement of the 8237A of the same frequency. For example, 82C84A-5 CLK output violates
the clock high time requirement of 8237A-5. In this
case 82C84A CLK can simply be inverted to meet
8237A-5 clock high and low time requirements. For
8085AH-2 systems above 3.9 MHz, the 8085
CLK(0UT) does not satisfy 8237A-5 clock LOW and
HIGH time requirements. In this case, an external
clock should be usod to drive the 8237A-5.
m.
2-237
(m)
ACTIVE CYCLE
When the 8237A is in the Idle cycle and a nonmasked channel requests a DMA service, the device
will output an HRQ to the microprocessor and enter
the Active cycle. It is in this cycle that the DMA service will take place, in one of four modes:
Single Transfer Mod-In
Single Transfer mode
the device is programmed to make one transfer only.
The word count will be decremented and the address decremented or incremented following each
transfer. When the word count “rolls over” from zero
to FFFFH, a Terminal Count (TC) will cause an Autoinitialize if the channel has been programmedto do
so.
DREQ must be held active until DACK becomes active in order to be recognized. If DREQ is held active
throughout the single transfer, HRQ will go inactive
and release the bus to the system. It will again go
active and, upon receipt of a new HLDA, another
single transfer will be performed. In 8080A, 8085AH,
8088, or 8086 system, this will ensure one full machine cycle execution betwaen DMA transfers. Details of timing between the 8237A and other bus
control protocols will depend upon the characteristics of the microprocessorinvolved.
Block Transfer Mod-In
Block Transfer mode the
device is activated by DREQ to continue making
transfers during the service until a TC, caused by
word count going to FFFFH, or an external End of
MICROPROCESSOR
Process
is encountered. DREQ need only be
held active until DACK becomes active. Again, an
Autoinitialization will occur at the end of the service
if the channel has been programmedfor it.
Demand Transfer Mode-In Demand Transfer
mode the device is programmed to continue making
is encountered
transfers until a TC or external
or until DREQ goes inactive. Thus transfers may
continue until the I10 device has exhausted its data
capacity. After the I/O device has had a chance to
catch up, the DMA service is reestablished by
means of a DREQ. During the time between services
when the microprocessor is allowed to operate, the
intermediate values of address and word count are
stored in the 8237A Current Address and Current
can cause an
Word Count registers. Only an
Autoinitialize at the end of the service.
is generated either by TC or by an external signal. DREQ
has to be low before S4 to prevent another Transfer.
m
Cascade Mode-This mode is used to cascade
more than one 8237A together for simple system
expansion. The HRQ and HLDA signals from the additional 8237A are connected to the DREQ and
DACK signals of a channel of the initial 8237A. This
allows the DMA requests of the additional device to
propagate through the priority network circuitry of
the preceding device. The priority chain is preserved
and the new device must wait for its turn to acknowledge requests. Since the cascade channel of the
initial 8237A is used only for prioritizing the additional device, it does not output any address or control
8257A
1Sf LEVEL
-
-
HRO
DREO
HLDA
DACK
WtA
DREO
DACK
C-
HRO
HLDA
HA0
HLDA
ADDITIONAL
DEVICES
Figure 4. Cascaded 8237As
2-238
231468-3
w
0237A
signals of its own. These could conflict with the outputs of the active channel in the added device. The
8237A will respond to DREQ and DACK but all other
outputs except HRQ will be disabled. The ready input is ignored.
The 8237A will respond to external
signals during memory-to-memory transfers. Data comparators
in block search schemes may use this input to terminate the service when a match is found. The timing
of memory-to-memory transfers is found in Figure
12. Memory-to-memory operations can be detected
as an active AEN with no DACK outputs.
Figure 4 shows two additional devices cascaded into
an initial device using two of the previous channels.
This forms a two level DMA system. More 8237As
could be added at the second level by using the
remaining channels of the first level. Additional devices can also be added by cascading into the channels of the second level device, forming a third level.
Autolnttlallm-By programming a bit in the Mode
register, a channel may be set up as an Autoinitialize
channel. During Autoinitialize initialization, the original values of the Current Address and Current Word
Count registers are automatically restored from the
Base Address and Base Word count registers of that
The base registers are loadchannel following
ed simultaneously with the current registers by the
microprocessor and remain unchanged throughout
the DMA sew’ce. The mask bit is not altered when
the channel is in Autoinitialize. Following Autoinitialize the channel is ready to perform another DMA
service, without CPU intervention, as soon as a valid
DREQ is detected. In order to Autoinitialize both
channels in a memory-to-memory transfer, both
word counts should be rogrammed identically. If inpulses should be applied
terrupted externally,
in both bus cycles.
m.
TRANSFER TYPES
Each of the three active transfer modes can perform
three different types of transfers. These are Read,
Write and Verify. Write transfers move data from an
I10 device to the memory by activating
and
ibw. Read transfers move data from memory to an
I10 device by activating
and
Verify
transfers are pseudo transfers. The 8237A operates
as in Read or Write transfers generating addresses,
and responding to EOP, etc. However, the memory
and I10 control lines all remain inactive. The ready
input is ignored in verify mode.
m.
Memory-to-Memory-To perform block moves of
data from one memory address space to another
with a minimum of program effort and time, the
8237A includes a memory-to-memory transfer feature. Programming a bit in the Command register
selects channels 0 and 1 to operate as memory-tomemory transfer channels. The transfer is initiated
by setting the software DREQ for channel 0. The
8237A requests a DMA sew’ce in the normal manner. After HLDA is true, the device, using four state
transfers in Block Transfer mode, reads data from
the memory. The channel 0 Current Address register
is the source for the address used and is decremented or incremented in the normal manner. The data
byte read from the memory is stored in the 8237A
internal Temporary register. Channel 1 then performs a four-state transfer of the data from the Temporary register to memory using the address in its
Current Address register and incrementingor decrementing it in the normal manner. The channel 1 current Word Count is decremented. When the word
count of channel 1 goes to FFFFH, a TC is generated causing an
output terminating the service.
&
Prlorlty-The 8237A has two types of priority encoding available as software selectable options. The
first is Fixed Priority which fixes the channels in priority order based upon the descendingvalue of their
number. The channel with the lowest priority is 3
followed by 2, 1 and the highest priority channel, 0.
After the recognition of any one channel for service,
the other channels are prevented from interfering
with that sew’ce until it is completed.
After completion of a service, HRQ will go inactive
and the 8237A will wait for HLDA to go low before
activating HRQ to service another channel.
The second scheme is Rotating Priority. The last
channel to get sew’ce becomes the lowest priority
channel with the others rotating accordingly.
Channel 0 may be programmed to retain the same
address for all transfers. This allows a single word to
be written to a block of memory.
2-239
With Rotating Priority in a single chip DMA system,
any device requesting service is guaranteed to be
recognized after no more than three higher priority
services have occurred. This prevents any one
channel from monopolizingthe system.
Current Word Reglster-Each channel has a 16bit Current Word Count register. This register determines the number of transfers to be performed. The
actual number of transfers will be one more than the
number programmed in the Current Word Count register (i.e., programming a count of 100 will result in
101 transfers). The word count is decremented after
each transfer. The intermediate value of the word
count is stored in the register during the transfer.
When the value in the register goes from zero to
FFFFH, a TC will be generated. This register is loaded or read in successive &bit bytes by the microprocessor in the Program Condition. Following the
end of a DMA service it may also be reinitialized by
an Autoinitialization back to its ori inal value. Autooccurs. if it is
initialize can occur only when an
not Autoinitialized, this register will have a count of
FFFFH after TC.
Compressed liming-In order to achieve even
greater throughput where system characteristics
permit, the 8237A can compressthe transfer time to
two clock cycles. From Figure 11 it can be seen that
state S3 is used to extend the access time of the
read pulse. By removing state S3, the read pulse
width is made equal to the write pulse width and a
transfer consists only of state S2 to change the address and state S4 to perform the read/write. S1
states will still occur when A8-Al5 need updating
(see Address Generation). Timing for compressed
transfers is found in Figure 14.
Address Generation-In order to reduce pin count,
the 8237A multiplexes the eight higher order address bits on the data lines. State S1 is used to output the higher order address bits to an external latch
from which they may be placed on the address bus.
The falling edge of Address Strobe (ADSTB) is used
to load these bits from the data lines to the latch.
Address Enable (AEN) is used to enable the bits
onto the address bus through a three-state enable.
The lower order address bits are output by the
8237A directly. Lines AO-A7 should be connected
to the address bus. Figure 11 shows the time relationships between CLK, AEN, ADSTB, DBO-DB7
and AO-A7.
During Block and Demand Transfer mode services,
which include multiple transfers, the addresses generated will be sequential. For many transfers the
data held in the external address latch will remain
the same. This data need only change when a carry
or borrow from A7 to A8 takes place in the normal
sequence of addresses. To save time and speed
transfers, the 8237A executes S1 states only when
updating of A8-Al5 in the latch is necessary. This
means for long services, S1 states and Address
Strobes may occur only once every 256 transfers, a
savings of 255 cbck cycles for each 256 transfers.
REGISTER DESCRIPTION
Current Address Register-Each channel has a
16-bit Current Address register. This register holds
the value of the address used during DMA transfers.
The address is automatically incremented or decremented after each transfer and the intermediate values of the address are stored in the Current Address
register during the transfer. This register is written or
read by the microprocessor in successive &bit
bytes. It may also be reinitialized by an Autoinitialize
back to its ori inal value. Autoinitialize takes place
only after an
&
Base Address and Base Word Count RegistersEach channel has a pair of Base Address and Base
Word Count registers. These 16-bit registers store
the original value of their associated current registers. During Autoinitialize these values are used to
restore the current registers to their original values.
The base registers are written simultaneously with
their corresponding current register in 8-bit bytes in
the Program Condition by the microprocessor.
These registers cannot be read by the microprocessor.
Command Reglster-This &bit register controls
the operation of the 8237A. It is programmed by the
microprocessor in the Program Condition and is
cleared by Reset or a Master Clear instruction. The
following table lists the function of the command
bits. See Figure 6 for address coding.
Mode Reglster-Each channel has a 6-bit Mode
register associatedwith it. When the register is being
written to by the microprocessor in the Program
Condition, bits 0 and 1 determine which channel
Mode register is to be written.
Request Register-The 8237A can respond to requests for DMA service which are initiated by software as well as by a DREQ. Each channel has a
request bit associated with it in the 4-bit Request
register. These are non-maskableand subject to prioritization by the Priority Encoder network. Each register bit is set or reset separately under software
control or is cleared upon generation of a TC or exThe entire register is cleared by a Reset.
ternal
To set or reset a bit, the software loads the proper
form of the data word. See Figure 5 for register address coding. In order to make a software request,
the channel must be in Block Mode.
&.
2-240
=.
w
8237A
Mask Register-Each channel has associated with
it a mask bit which can be set to disable the incoming DREQ. Each mask bit is set when its associated
channel produces an
if the channel is not programmed for Autoinitialize. Each bit of the 4-bit
Mask register may also be set or cleared separately
under software control. The entire register is also set
by a Reset. This disables all DMA requests until a
clear Mask register instructionallows them to occur.
The instruction to separately set or clear the mask
bits is similar in form to that used with the Request
register. See Figure 5 for instruction addressing.
Command Register
7
0
6
4
l l1 -1 n
L
7
0
0
4
3
2
1
OC-BllNumkr
00
01
10
11
S O k t channel 0 mMk bit
SqlWt channel 1 w k blt
SOlOCt channel 2 mMk blt
Select channel 3 w k bit
0
Clear meek blt
Set mark blt
1
(0
231466-8
DACK renw active iOw
DACK renw active high
1
231466-5
All four bits of the Mask register may also be written
with a single command.
Mode Reaister
-
7
00
01
10
11
0
6
4
3
2
1
Of-BllNumbu
0
1
Don’t Cue
CleU ChWbIlOl 0 mMk bll
SOt channel 0 mark blt
0 Clwr channel 1 m k blt
1 Set channel 1 m u k blt
4
00 V o r l f y t n n r f r
01 Write lnnrkr
10 Read tranrfer
11 111ega1
XX If blt8 6 .nd 71 11
0 Cleu channel 2 mark blt
1
[ 0t
a t ChMnOl2 mMk bit
CIOU channel 3 mark bit
Set channel 3 mark bit
231468-8
1
{
0
t
Addrerr increment wiect
Address decrement wlect
Register Operatlon
00 Demand mode nelect
01 Slngle mode rdect
10 Block mode reiect
11 Cascade mode relect
231466-6
Request Reaister
7
6
6
4
3
2
1
0 t-BltNunbn
00 Select channel 0
01 Select channel t
10 Select channel 2
I
Rawtrequestblt
1 Sat requert blt
(0
231486-7
I
I
Command Write
Write
Mode
Request Write
SetIReset
Mask
Write
Mask
Temporary Read
Read
Status
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
1
0
0
0
1
1
0
1
1
0
Figure 5. Deflnition of Register Codes
Status Register-The Status register is available to
be read out of the 8237A by the microprocessor. It
contains information about the status of the devices
at this point. This information includes which channels have reached a terminal count and which chan2-241
w
0237A
7
8
6
3
4
2
1 OC-BHNunkr
1
Channel 0 has reached TC
Channel 1 has reached TC
Channel 2 has reached TC
Channel 3 has reached TC
1
1
1
1
Channel 0 request
Channel 1 request
Channel 2 request
Channel 3 request
1
1
1
231488-10
nels have pending DMA requests. Bits 0-3 are set
every time a TC is reached by that channel or an
external
is applied. These bits are cleared upon
Reset and on each Status Read. Bits 4-7 are set
whenever their corresponding channel is requesting
service.
Temporary Reglater-The Temporary register is
used to hold data during memory-to-memorytransfers. Following the completion of the transfers, the
last word moved can be read by the microprocessor
in the Program Condition. The Temporary register
always contains the last byte transferred in the previous memory-to-memory operation, unless cleared
by a Reset.
1
I
1
I
1
I
1
I
Master Clear This software instruction has the
same effect as the hardware Reset. The Command, Status, Request, Temporary, and Internal
FirstILast Flip-Flop registers are cleared and the
Mask register is set. The 8237A will enter the Idle
cycle.
Clear Mask Register: This command clears the
mask bits of all four channels, enabling them to
accept DMA requests.
Software Commands-These are additional special software commands which can be executed in
the Program Condition. They do not depend on any
specific bit pattern on the data bus. The three software commands are:
I
Clear First/Last Fhp-Flw: This command must be
executed prior to writing or reading new address
or word count information to the 8237A. This initializes the flip-flop to a known state so that subsequent accesses to register contents by the microprocessor will address upper and lower bytes
in the correct sequence.
Figure 6 lists the address codes for the software
commands.
1
I
0
I
Figure 6. Software Command Codes
2-242
WflteAllMaskRegisterBits
I
023744
Channel
Reairtor
Operation
-
Signals
Internal Data Bus
A3 A2 A1 A0 FlbFloP DBO-DB7
CS
0
EaseandCurrentAddress
Current Address
1
3
Read
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
AO-A7
A8-Al5
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
AO-A7
A8-Al5
BaseandCurrentWordCount
Write
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
1
WO-W7
W8-Wl5
Current Word Count
Read
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
1
WO-W7
W8-Wl5
BaseandCurrentAddress
Write
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
1
AO-A7
A8-Al5
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
AO-A7
A8-Al5
Current Address
2
0
Write
Read
BaseandCurrentWordCount
Write
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
1
WO-W7
W8-Wl5
Current Word Count
Read
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
WO-W7
WB-Wl5
BaseandCurrentAddress
Write
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
AO-A7
A8-Al5
Current Address
Read
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
AO-A7
A8-AI5
BaseandCurrentWordCount
Write
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
1
WO-W7
W8-Wl5
Current Word Count
Read
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
WO-W7
W8-Wl5
BaseandCurrentAddress
Write
1
1
0
0
0
0
1
1
1
1
0
0
0
1
AO-A7
A8-AI5
Current Address
Read
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
I
A047
A8-AI5
0
0
1
0
0
0
0
1
1
1
I
1
1
1
0
1
WO-W7
W8-Wl5
0
0
0
0
1
1
0
0
1
1
1
1
1
0
1
WO-W7
W8-Wl5
0
BaseandCurrentWordCount
Current Word Count
Write
Read
1
Figure7. Word Count and Address Reglster Command Cedes
2-243
w
channels are unused. An invalid mode may force all
control signals to go active at the same time.
PROGRAMMING
The 8237A will accept programming from the host
processor any time that HLDA is inactive; this is true
even if HRQ is active. The responsibility of the host
is to assure that programming and HLDA are mutually exclusive. Note that a problem can occur if a DMA
request occurs, on an unmasked channel while the
8237A is being programmed. For instance, the CPU
may be starting to reprogram the two byte Address
register of channel 1 when channel 1 receives a
DMA request. If the 8237A is enabled (bit 2 in the
command register is 0) and channel 1 is unmasked,
a DMA service will occur after only one byte of the
Address register has been reprogrammed. This can
be avoided by disabling the controller (setting bit 2 in
the command register) or masking the channel before programming any other registers. Once the programming is complete, the controller can be enabledhnmasked.
After power-up it is suggested that all internal locations, especially the Mode registers, be loaded with
some valid value. This should be done even if some
APPLICATION INFORMATION(Note 1)
Figure 8 shows a convenient method for configuring
a DMA system with the 8237A controller and an
8080A/8085AH microprocessor system. The multimode DMA controller issues a HRQ to the processor
whenever there is at least one valid DMA request
from a peripheral device. When the processor replies with a HLDA signal, the 8237A takes control of
the address bus, the data bus and the control bus.
The address for the first transfer operation comes
out in two bytes-the least significant 8 bits on the
eight address outputs and the most significant 8 bits
on the data bus. The contents of the data bus are
then latched into an 8-bit latch to complete the full
16 bits of the address bus. The 8282 is a high
speed, &bit, three-state latch in a 20-pin package.
After the initial transfer takes place, the latch is updated only after a carry or borrow is generated in the
least significant address byte. Four DMA channels
are provided when one 8237A is used.
CCU
SVSTEY DATA I U S
J
231466-1 1
Figure 8.8237A System Interface
NOTE:
1. See Application Note AP-67 for 8086 design information.
2-244
0237A
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperatureunder Bias . . . . . .O"C to 70°C
Case Temperature . . . . . . . .. . . . .. .. .O"C to 75°C
storage Temperature . . . .. . . . . . -650cto + 5ooc
Voltage on Any Pin with
Respectto Ground. . . . . . . . . . . .. . -0.5V to 7v
Power Dissipation. . . . .. . . . . . .. . . . . . . . . . . 1.5 Watt
+
ICC
VCCSupply Current
Co
CI
Output Capacitance
Input Capacitance
Clo
I/O Capacitance
'Notice: Stresses above those listed under 'Mbsolute Mawmum Ratings" may cause permanent damage to the device. This is a stress rating on& and
h~nctionalOperation of the device at these Or anJ'
other conditions above those indicated in the operational sections of this specificationis not implid. Exposure to absolute maximum rating condtions for
eHend&pe,,&s
may affect device reliabiliw.
110
130
mA
TA = +25%
130
150
mA
TA = 0°C
4
8
PF
8
15
pF
10
18
pF
fc = 1 .O MHz, Inputs = OV
NOTE
1. Typical values are for TA = 25'C, nominal supply voltage and nominal processing parameters.
2-245
w
8237A
A.C. CHARACTERISTICS-DMA (MASTER) MODE
TA
0°C to 70°C, TCASE = 0°C to 75"C, V c c = +5V f5%, GND = OV
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
HIGH from CLK HIGH Delay Time (Note 2)
m LOW from CLK HIGH Delay Time
250
190
170
ns
250
190
170
ns
170
ns
TASM
ADR Stable from CLK HIGH
TASS
DB to ADSTB LOW SetuD Time
100
100
TCH
Clock High Time (Transitions<10 ns)
120
100
l e 0
TCL
Clock LOW Time (Transitions<10 ns)
168
ns
CLK Cycle Time
150
320
110
TCY
250
200
tlS
TDCL
CLK HIGHt o m or
270
200
190
ns
TDCTR
HIGH from CLK HIGH
(S4) Delay Time (Note 3)
270
21 0
190
ns
TDCTW
HIGH from CLK HIGH
(S4) Delay Time (Note 3)
200
150
130
ns
TW1
HRQ Valid from CLK HIGH Delay Time (Note 4)
160
120
120
250
LOW Delay (Note 3)
TW2
190
TEPW
60
Pulse Width
190
40
225
220
250
170
190
ITFAC
I
TRH
CLK to READY LOW Hold Time
20
TRS
READY to CLK LOW Setup Time
100
TSTL
ADSTB HIGH from CLK HIGH Delay Time
200
150
130
TSlT
ADSTB LOW from CLK HIGH Delay Time
140
110
90
or
Active from CLK HIGH
I
120
45
300
TFAAB ADR Float to Active Delav from CLK HIGH
ns
1
250
m LOW from CLK LOW Setup Time
TEPS
ns
100
I
12001
2-246
150
I
I
150
20
20
ns
ns
60
60
Ins1
w
823719
A.C. CHARACTERISTICS-PERIPHERAL (SLAVE) MODE
TA = QC to 70'C, TCASE= QC to 75%. Vcc = +5V *5%, GND = OV
NOTES
1. DREO and DACK signals may be active high or active low. Timing diagrams assume the active high mode.
is an
n collector output. This parameter assumes the presence of a 2.2K pullup to V m .
2
3: The net *or
Pulse width for normal write will be TCY - 100 ns and for extended write will be 2TCY - 100 ns.
or hAEMR pulse width for normal read will be 2TCY -50 ns and for compressed read will be TCY -50 ns.
The net
4. T W is specified for two different output HIGH levels. T W 1 is measured at 2.0V. T W 2 is measured at 3.3V. The value
for T W 2 assumes an external 3.3 Kfk pull-up resistor connected from HRO to V a .
5. Output Loading on the Data Bus is 1 TTL Gate plus 100 pF capacitance.
A.C. TESTING INPUT/OUTPUT WAVEFORM
I
I
2.4
2.0
2.0
231466-12
A.C. Testing: Inputs are driven at 2.4V for a Logk "1" and 0.45V
for a Logic "0." Timing measurements are made at 2.0V for a
Logic "1" and 0.W for a Logic "0." lnpul timing parameters as.
sum transition times of 20 ns or less. Waveform measurement
points for both input and wtput !4gnals are 2.0V for HIGH and
0.8V for LOW, unless othemise noted.
2-247
w
WAVEFORMS
SLAVE MODE WRITE TIMING
TCW
I
A043
I
I
INPUT VALfD
INPUT VALID
231486-13
NOTE
1. Successive read and/or write operations by the external processor to program or examine the controller must be
timed to allow at least 600 ns for the 8237A, at least 500 ns for the 8237A-4, and at least 400 ns for the 8237A-5 as
recovery time between active read or write pulses. The same recovery time is needed between an active read or write
pulse followed by a DMA transfer.
Flgure 9. Slave Mode Wrlte
;LAVE MODE READ TIMING
2-248
WAVEFORMS (Continued)
DMA TRANSFER TIMING
2-249
w
WAVEFORMS (Continued)
MEMORY-TO-MEMORYTRANSFER TIMING
231466-16
Figure 12. Memory-to-MemoryTransfer
?EADY TIMING
I " I " I
READY
aw
I
'w
I
84
I
\\\\\\\\\I
231466-17
Figure 13. Ready
2-250
0237A
WAVEFORMS (Continued)
;OMPRESSEDTRANSFER TIMING
CLK
I
l
l
I
A047
1I
VALID
mw.lRllw
TRS-
-
READY
m
-
TAM
-
--*
T11(
EOP
-
W
EOP
231488-18
Figure 14. Compressed Transfer
RESET TlMlNG
-
Tl)SlD
c
TRSTW
2-251
DATA SHEET REVISION REVIEW
DESIGN CONSIDERATIONS
1. Cascading from channeizero. When using multiple 8237s, always start cascading with channel
zero. Channel zero of the 8237 will operate incorrectly if one or more of channels 1, 2, or 3 are
used in the cascade mode while channel zero is
used in a mode other than cascade.
2. Do not treat the ORE0 signai as an asynchro-
nous input whiie the channel is in the “demand” or “cascade”modes. If DREQ becomes
inactive at any time during state s4,an illegal
state may occur causing the 8237 to operate improperly.
3. HRQ must remain active untii HLDA becomes
active. If HRQ goes inactive before HLDA is received the 8237 can enter an illegal state causing
it to operate improperly.
4. Make sure the MEMR# iine has 50 pF loading
capacitance on it. When doing memory to memory transfers, the 8237 requires at least 50 pF
loading capacitance on the MEMR+ signal for
proper operation. In most cases board capacitance is sufficient.
5. Treat the READY input as a synchronous input. If a transition occurs during the setup/hold
window, erratic operation may result.
The following list represents key differences between this and the -002 data sheet. Please review
this summary carefully.
1. Major cleanup on the “NOTE” sections of this
data sheet.
a. Pin 5 no longer references a note. It is now
included in the pin description area under the
name “PIN5”.
b. The note placed in the “typical” section of the
D.C. Characteristics table is now referenced to
a note section included with that table.
c. Notes in the A.C. Characteristics table have
been renumbered and are included in a notes
section for the A.C. Characteristics.
d. The note that was previously referenced in the
A.C. TESTING INPUT/OUTPUT WAVEFORM
diagram has been replaced with the actual
note.
e. The note that was previously referenced in the
SLAVE MODE WRITE TIMING diagram has
been included in a “NOTE” section with the
diagram.
f. The note that was previously referenced in the
SLAVE MODE READ TIMING diagram has
been included in a “NOTE” section with the diagram.
g. The note that was previously referenced in the
DMA TRANSFER TIMING diagram has been
included in a “NOTE” section with the diagram.
2. A “Design Considerations” section was added to
alert designers to certain design aspects of the
8237.
3. The timing parameters TAR for the 8237A-4 and
8237A-5 have been changed from 50 ns to 0 ns.
2-252
KFIT CUSTOM CHIP
(KEYBOARD, FLOPPY SUPPORT, INTERRUPT, TIMER)
The i n f o r m a t i o n c o n t a i n e d h e r e i n i s e x c l u s i v e p r o p e r t y o f Tandy
C o r p o r a t i o n . N o r e p r o d u c t i o n of any kind may b e made w i t h o u t t h e
express w r i t t e n a u t h o r i z a t i o n of:
Tandy C o r p o r a t i o n
1 0 0 0 Two Tandy Center
F o r t Worth, Tx 7 6 1 0 2
TANDY PART #:
8079019
T a b l e Of C o n t e n t s
FUNCTIONAL DESCRIPTIONS
Programmable P e r i p h e r a l I n t e r f a c e
Keyboard I n t e r f a c e L o g i c
Floppy D i s k I n t e r f a c e Logic
Programmable I n t e r v a l Timer
Programmable I n t e r r u p t
A d d r e s s Decoding Logic
BLOCK DIAGRAM
I NP UT/OUTP UT PIN DESC R I PTI ONS
I / O MAPS
1/0 S i g n a l D e f i n i t i o n :
Register Definition:
Interrupt
Timer
PPI/Keyboard
0060 - P o r t A
0061 - P o r t B
Port C
0062
P o r t n o t used
0063-0064
Planar Control
0065 - P l a n a r R e g i s t e r Read/Write
Non V o l a t i l e Memory Access
N o n - v o l a t i l e memory w r i t e o n l y
037C
Floppy Disk C o n t r o l
FDC Mode C o n t r o l
03F1
03F2
FDC D i g i t a l O u t p u t R e g i s t e r
03F4
FDC c h i p s e l e c t
03F5
FDC c h i p s e l e c t
03F7
FDC Data R a t e S e l e c t i o n
System C o n f i g u r a t i o n R e g i s t e r
FFEB - Non IBM C o m p a t i b l e R e a d / W r i t e
ELECTRICAL SPECIFICATIONS
KEYBOARD TIMING SPECIFICATIONS
FLOPPY DISK TIMING SPECIFICATIONS
ADDRESS PORT EQUATIONS
-
-
-
1
1
1
1
2
2
2
3
4
10
10
11
11
11
11
11
11
12
12
12
12
12
12
13
13
13
13
13
13
14
14
15
16
18
19
FUNCTIONAL DESCRIPTIONS
T h i s Tandy KFIT c u s t o m I C c o n s i s t s o f t h e f o l l o w i n g f u n c t i o n a l
blocks:
-
-
-
Programmable P e r i p h e r a l I n t e r f a c e ( P P I )
Keyboard I n t e r f a c e L o g i c
Floppy D i s k I n t e r f a c e Logic
P r o g r a m m a b l e I n t e r r u p t ( e q u i v a l e n t t o I n t e l 8259A)
and s h a r i n g i n t e r r u p t l o g i c
P r o g r a m m a b l e Timer ( e q u i v a l e n t t o I n t e l 8254-2 a n d
Clock D i v i d e r
Address Decoding Logic
Programmable P e r i p h e r a l I n t e r f a c e
T h i s s e c t i o n o f t h e KFIT c u s t o m i n t e g r a t e d c i r c u i t replaces t h e
I n t e l 8255A t h a t was u s e d on t h e o r i g i n a l Tandy 1 0 0 0 computer. On
t h e b l o c k d i a g r a m f o r t h i s s e c t i o n o f l o g i c , t h e 8255A i s
r e p r e s e n t e d by t h r e e 74LS244 b u f f e r s a d d r e s s e d by r e a d A ( 0 0 6 0 ) ,
r e a d B ( 0 0 6 1 ) , r e a d C ( 0 0 6 2 ) . A l s o t h e t w o l a t c h e s a d d r e s s e d by
write B ( 0 0 6 1 ) , w r i t e C (0062) which a r e p a r t o f t h e o r i g i n a l
8255A l o g i c .
Keyboard I n t e r f a c e L o g i c
T h i s s e c t i o n of t h e KFIT c u s t o m i n t e g r a t e d c i r c u i t is d e s i g n t o
s u p p o r t Tandy 1 0 0 0 k e y b o a r d or Tandy 1 0 1 e n h a n c e d k e y b o a r d .
KYBDTYP s i g n a l i s u s e d t o s e l e c t Tandy 1 0 0 0 k e y b o a r d when i s LOW
or Tandy 1 0 1 e n h a n c e d k e y b o a r d when i s HIGH. The KYBDTYP i s b e i n g
r e a d i n t o p o r t FFEB(hex) b i t 7. The KBDDATA
keyboard d a t a is
s e r i a l d a t a b i t stream a n d t h e n is c o n v e r t e d t o 8 b i t s p a r a l l e l
d a t a by 74LS322, The s e r i a l d a t a is e n t e r e d i n t h e LOW t o H I G H
t r a n s i t i o n of t h e KBCLK,
-
F l o p p y D i s k Interface L o g i c
T h i s s e c t i o n o f t h e KFIT c u s t o m i n t e g r a t e d c i r c u i t i s d e s i g n t o
s u p p o r t F l o p p y D i s k D i g i t a l O u t p u t R e g i s t e r (DOR) f u n c t i o n . T h i s
r e g i s t e r is mapped i n a d d r e s s 03F2 h e x
d a t a b i t 0 t o 7 (write
o n l y ) t o g e n e r a t e d r i v e s e l e c t DSOB,DSlB,DS2B; FDCRST (FDC r e s e t )
DMA/I a n d MTRONB ( m o t o r ON) s i g n a l . The DMA/I s i g n a l is u s e d t o
d i s a b l e FDCINTI, FDCDMRQ, a n d FDACKI s i g n a l s for a l l o w i n g t h e
u s e d of e x t e r n a l FDC c o n t r o l l e r .
-
1
Programmable I n t e r v a l Timer
T h i s s e c t i o n o f t h e KFIT c u s t o m i n t e g r a t e d c i r c u i t is e q u i v a l e n t
t o a n I n t e l 8254-5 a n d i s d e s i g n e d t o u s e w i t h t h e Tandy 1 0 0 0 TX.
I t is o r g a n i z e d a s t h r e e i n d e p e n d e n t 1 6 - b i t c o u n t e r s , e a c h w i t h a
c l o c k o f 1 . 1 9 MHZ. The 1 . 1 9 MHZ c l o c k is g e n e r a t e d from l4MHZ
d i v i d e d by 1 2 . All modes o f o p e r a t i o n a r e s o f t w a r e programmable.
P r og r ammabl e I n t e r r u p t
T h i s s e c t i o n o f t h e KTIF c u s t o m i n t e g r a t e d c i r c u i t is e q u i v a l e n t
t o a n I n t e l 8259A t h a t capable o f h a n d l i n g e i g h t - v e c t o r p r i o r i t y
i n t e r r u p t , i n d i v i d u a l r e q u e s t m a s k and programmable i n t e r r u p t
modes. T h i s c i r c u i t g e n e r a t e s INTR o u t p u t s i g n a l f o r t h e CPU. I n
a d d i t i o n , t h e s h a r i n g i n t e r r u p t l o g i c s a r e implemented i n t h e
d e s i g n f o r I R Q l (between keyboard and r e a l t i m e c l o c k i n t e r r u p t )
Address Decoding Logic
T h i s s e c t i o n c o n t a i n s 3 t o 8 a d d r e s s decode t o g e n e r a t e
Programmable I n t e r r u p t C h i p s e l e c t , Programmable I n t e r v a l Timer
c h i p s e l e c t , F l o p p y D i s k c h i p s e l e c t (FDCCHP*) and Programmable
P e r i p h e r a l I n t e r f a c e a d d r e s s of t h r e e d e c o d e d a d d r e s s A, B a n d C.
(see I O s i g n a l d e f i n i t i o n ) . The FDC p o r t i s e n a b l e d by P l a n a r
r e g i s t e r - p o r t 0065hex b i t 3 when b i t 3 i s H I G H .
2
BLOCK DIAGRAM
-
DO47
I
I
-REFFEO
SHARING
IR02-IR07
INTAB
KEYBOAm
SA0
SA I
SA2
U?
A
B
UmESs
DECrnIN6
-
LOGIC
C
IMIB
IMB
NOW1
cOLB/mN
PIAcm
OCB
FDWWW
FDICKIB
FaMLI
FWAEI
FOOIRI
3
INP UT/OUTP UT PIN DE SCRIPTION8
1
XDO
8ma
(S.T input)
14
Data b u s 0
2
XD 1
8ma
(S.T input)
15
Data bus 1
3
XD2
8ma
(S.T input)
16
Data b u s 2
4
XD3
8ma
(S.T i n p u t )
17
Data b u s 3
5
8ma
XD4
(S.T i n p u t )
19
Data b u s 4
6
XD 5
8ma
(S.T input)
20
Data b u s 5
7
XD6
8ma
(S.T input)
21
Data b u s 6
8
XD 7
8ma
(S.T i n p u t )
22
Data b u s 0 7
9
SA0
28
System a d d r e s s 0
10
SA 1
29
System a d d r e s s 1
11
S A2
30
System a d d r e s s 2
12
S A7
31
System a d d r e s s 7
13
A
32
CPU 1/0 a d d r e s s
d e c o d e LSB
14
B
33
CPU 1/0 a d d r e s s
decode
15
C
34
CPU 1/0 a d d r e s s
d e c o d e MSB
16
IOWB
37
A c t i v e LOW. CPU
1/0 w r i t e s i g n a l
17
IORB
36
A c t i v e LOW. CPU
1/0 r e a d s i g n a l
4
19
BUSY
(O.C.,
20
KYBDTYP
(Pull-up)
21
PPITM
8ma
Pull-up)
2ma
*
58
0
Keyboard busy
When High
61
I
Keyboard t y p e
s e l e c t . When
High, s e l e c t s IBM
PC keyboard.
When Low s e l e c t s
Tandy keyboard
12
0
P r og r ammab l e
Per i p h e r a 1
Interface Timer
output signal
f o r sound g e n e r a t o r .
22
KBDDATA
8ma
60
I/O
Input d a t a s i g n a l
from keyboard.
I n t h e IBM PC
keyboard t h i s p i n
is used a s an o u t p u t
t o hold t h e d a t a
Low.
8ma
59
I/O
Input clock s i g n a l
from keyboard. I n
t h e IBM PC keyboard
t h i s p i n is used a s
an o u t p u t t o hold
t h e c l o c k LOW.
( 3-s t a t e )
23
KBDCLK
(3-state)
24
DSOB
(O.C.
8ma
Pull-up*)
57
Drive s e l e c t s i g n a l
When Low.
25
DSlB
(O.C.
8ma
Pull-up*)
56
Drive s e l e c t s i g n a l
when is LOW.
26
DS2B
(O.C.
8ma
Pull-up*)
55
Drive s e l e c t s i g n a l
when i s LOW.
27
DCB
38
D i s k change s i g n a l
when is LOW.
(Pull-up)
5
28
DRATE
16ma
54
0
Data r a t e s e l e c t
s i g n a l . When i s
LOW, 500 kbps is
s e l e c t e d . When
is H I G H 250kbps i s
selected.
4ma
46
0
FDC r e s e t s i g n a l t o
t h e FDC c o n t r o l l e r
when i s H I G H .
66
I
System r e s e t i n p u t
s i g n a l when i s H I G H .
53
0
Floppy d i s k motor ON
o u t p u t s i g n a l when
i s LOW.
(O.C.)
29
FDCRST
30
RESET
31
MTRONB
(O.C.)
32
FDHSELI
33
FDHSELOB
(O.C.)
34
FDWREI
16ma
16ma
42
Head s e l e c t i n p u t
s i g n a l from f l o p p y
disk controller..
49
Head s e l e c t i n p u t
s i g n a l for floppy
d r i v e s when i s LOW.
41
Write e n a b l e i n p u t
s i g n a l from f l o p p y
disk controller.
35
FDWREOB
(O.C.)
16ma
Write e n a b l e o u t p u t
50
s i g n a l for floppy
d r i v e s when i s LOW.
Head t r a v e l
direction input
s i g n a l from FDC
controller.
36
FDD I R I
40
37
FDDIROB
(O.C.)
16ma
51
0
He ad t r a v e l
d i r e c t i o n f o r floppy
d r ive.
38
FDCCHPB
4ma
47
0
FDC c h i p s e l e c t
o u t p u t s i g n a l o r FDC
c o n t r o l l e r when i s
LOW.
6
39
FDACKIB
40
FDACKOB
41
FDC c o n t r o l l e r
acknowledge
o u t p u t s i g n a l when
i s LOW.
FDC c o n t r o l l e r
acknowledge o u t p u t
s i g n a l when i s LOW.
44
I
45
0
FDCINT
39
I
Floppy d i s k
interrupt input
s i g n a l when i s H I G H ,
42
FDCDMRQ
43
I
Floppy d i s k s e r v i c e
request input signal
t o DMA when i s LOW.
43
FDCDRQ
48
0
Floppy d i s k s e r v i c e
r e q u e st o u t p u t
s i g n a l t o t h e DMA
when i s LOW.
44
IRQ2
(S.T. Pull-up)
5
I
Interrupt request 2
input signal
45
IRQ3
( S O T . Pull-up)
6
I
Interrupt request 3
input signal
46
IRQ4
( S oT
7
I
47
IRQ5
8
I
Interrupt request 5
input signal
10
I
Interrupt request 6
input/output s i g n a l
9
I
Interrupt request 7
input signal
2ma
4ma
. Pull-up)
(S.T. Pull-up)
48
49
IRQ6
(3-state,
IRQ7
(S.T.
Pull-up)
Pull-up)
7
Interrupt request 4
i npu t s i g n a 1
50
INTAB
51
INTR
52
RTC I NTB
(S.T. P u l l - u p )
2ma
4
I
Interrupt
acknowledge s i g n a l .
T h i s signal i s used
to enable i n t e r r u p t
vector data onto the
d a t a b u s by a
sequence of
interrupt
acknowledge pulses
i s s u e d by t h e CPU
11
0
Interrupt request
signal. This signal
is u s e d t o i n t e r r u p t
t h e CPU when H I G H
2
I
Real t i m e clock
interrupt signal
f r o m t h e Real Time
C l o c k d e v i c e when
LOW.
26
NOV RAM d a t a i n
si g i i a l
2ma
23
NOV RAM c h i p e n a b l e
si g i i a l
NOVDO
2ma
25
NOV-RAM
signal
d a t a out
56
NOVCK
2ma
24
NOV-RAM
clock
57
RFRSHB
3
DMA a c k n o w l e d g e
53
NOVDI
54
NOVCE
55
s i g n a l f r o m 8237.
T h i s s i g n a l is
active HIGH
58
REFREQ
59
COL/MON
2ma
13
0
68
DMA R e q u e s t s i g n a l
f o r 8237. T h i s
s i g n a l is a c t i v e
HIGH
Input configuration
control s i g n a l
60
PARCHK
P a r i t y Check i n p u t
signal
67
8
61
62
63
64
65
66
67
68
VCC
VCC
GND
GND
not
not
not
not
Notes:-
-
-
used
used
used
used
Power s u p p l y +5V
Power s u p p l y +5V
Ground
Ground
1
35
52
18
62
63
64
65
= Open-Collector
3-State = Tri-State
S.T. = S c h m i t t T r i g g e r
* = Max.=1.6mal Min.=O.4ma s i n k i n g c u r r e n t .
These s i g n a l s must have e x t e r n a l t e r m i n a t i o n .
O.C.
9
I/O Mz4PS
1/0 Signal D e f i n i t i o n :
A d d r e s s R a n g e Hex
0
1
0
----------------0020 - 0027
0040 - 0047
OOCO - OOC7
0060 - 0067
0
1
1
1
0
0
1
0
1
03FO
0200
0378
1
1
1
1
0
1
-
0065
03F7
0207
037F
0 37C
03FF
FFEF
03F8 FFE8 ----------
Function
--------
Interrupts
Timer
Sound
PPI
Planar Register
F 1OPPY
Joystick
Printer
NOVRAM
Serial
Non IBM c o m p a t i b l e
Inactive
10
Register Definition:
I n t e r r u pt
0020
-
0021
-
0022
-
I n i t i a l i za t ion Command
Word 1
I n i t i a l i z a t i o n Command
Word 2
Not used
0027
Timer
0 0 4 0/0 0 4 4
.
Timer
0041/0045
-
Timer
0042/0 0 4 7
-
Timer
-
Note:
= r e f e r s t o system 1/0 maps.
PPI/Keyboard
Address Range Hex
----------------0060 - P o r t A
0061
-
Description
Bit
----------Keyboard Read Data
Read o n l y Keyboard
Read o n l y Keyboard
Read o n l y Keyboard
Read o n l y Keyboard
Read o n l y Keyboard
Read o n l y Keyboard
Read o n l y Keyboard
Read o n l y Keyboard
Input
b i t 0 LSB
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
b i t 7 MSB
Read/Write
Timer g a t e 1 2 enable
Speaker d a t a o u t e n a b l e
n o t used
n o t used
l = d i s a b l e i n t e r n a l speaker
n o t used
Port B
R/W
R/W
R/W
R/w
R/W
R/W
R/W
R/W
11
HOLDCK
l=keyboard c l e a r
A d d r e s s Range Hex
----------------0062 - P o r t C
Bit
--Read/Write
R/W n o t used
R/W n o t u s e d
R/W n o t used
R/W O=slow s p e e d
Read N O V D I
Read o u t p u t Timer # 2
Read O=color
Read l = P a r i t y check
P o r t n o t used
0063-0064
Planar Control
0065
P l a n a r R e g i s t e r Read/Write
R e se r ved
Reserved
Reserved
1=FDC c h i p s e l e c t e n a b l e
Reserved
Reserved
Reserved
Reserved
0066
Not Used
0067
P o r t D n o t used
Non V o l a t i l e Memory Access
037C
N o n - v o l a t i l e memory w r i t e o n l y
NOVDO
NOVCE
NOVC LK
Reserved
Rese r v ed
Reserved
Reserved
R e s e r ved
12
Description
-----------
Not used
0 3F0
FDC Mode Control
Not used
Write - Drive S e l e c t s w i t c h
0 = 0-0 1-1
0 3F1
0
1
1 = 0-1
1-0
Not used
N o t used
N o t used
N o t used
Not u s e d
Not used
FDC D i g i t a l Output Register
(DOR)
Write Only
0 3F2
DSO
Write
write
Write
Write
-
-
Write
Write
N o t used
N o t used
--0
0
DS1
DS2
0
1
--- --l
o
FDC r e s e t
Enable DMA Req/Int.
Drive 0 Motor ON
Drive 1 Motor ON
0 3F3
N o t used
0 3F4
FDC c h i p s e l e c t
0 3F5
FDC c h i p s e l e c t
0 3F6
N o t used
FDC Data Rate S e l e c t i o n
N o t used
Write - Data Rate
0 = 500K b i t s per second
1 = 250K b i t s per second
N o t used
0 3F7
0
1
N o t used
N o t used
Not used
N o t used
O = D i s k Change
13
System C o n f i g u r a t i o n Register
FFEB
Non IBM C o m p a t i b l e Read/Write
Reserved
Reserved
Reserved
Reserved
Reserved
Read l=Keyboard I n t e r r u p t
Read l = R e a l Time C l o c k
Interrupt
Write l = E n a b l e Real-Time clock
Inter rupt
Read Keyboard S e l e c t
O=Tandy Keyboard
1 = 1 0 1 Enhanced Keyboard
0
1
2
3
4
5
6
7
Summary on t h e a c t i v e / f l o a t
data bits.
(READ ONLY)
Address N e t N a m e A c t i v e B i t s
-------------- -----------
----------
0065
0 3F7
FFEB
XDO-XD2,
XDO-XD6
XDO-XD4
CSEN
FDMDRDB
CDENRDB
XD 3
XD7
XD5
XD6
XD7
14
Float B i t s
XD4-XD7
ELECTRICAL SPECIFICATIONS
15
KEYBOARD TIMING SPECIFICATIONS
16
I/O W r i t e C y c l e
Address C s .
l
-X
I I-
l l
X
I I-
X
l
I OWB
1/0 Read C y c l e
Address C s .
X
IORB
Data
17
FLOPPY D I S K T I M I N G S P E C I F I C A T I O N S :
1/0 Write C y c l e
A d d r e s s Cs.
X
l
1->i ;<-I <------I OWB
I
l
\
3---
Data
>I
2
la-->[
- - - - - -> I
/
I
I
4--->
X
I
-1
5-->1
6-->1
X
I-
I<-I <-I <---
Ix-
I<-I<--
PROGRAMMABLE INTERRUPT T I M I N G AND D E S C R I P T I O N S
M u s t meet I n t e l 8 2 5 9 A . A n y d i f f e r e n c e s m u s t be s p e c i f i e d .
PROGRAMMABLE TIMER T I M I N G AND D E S C R I P T I O N S
M u s t meet I n t e l 8 2 5 4 - 5 .
A n y d i f f e r e n c e s m u s t be s p e c i f i e d .
18
ADDRESS PORT EQUATIONS
................................................................
/*
/*
KEYBOARD, T I M E R CONTROL, I N T E R R U P T CONTROL, FDC-DOR
/*
. . . . . . . . .AND
. . . .DECODE
. . . . . . . LOGIC
............................................
/*
. . . . .Allowable
. . . . . . . . . .T. a. r. g. e. .t . Device
. . . . . . . .Types:
. . . . . . . . . .F153
........................
/**
Inputs
PIN
PIN
PIN
PIN
PIN
PIN
PIN
1
2
3
4
5
6
7
/**
outputs
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
/**
9
11
12
13
14
15
16
17
18
19
*/
*/
*/
*/
**/
=
=
=
=
=
=
=
saOl
saOO
sa02
!iow
!ior
!fdcport
!keyport
;
I
I
;
I
;
;
/*
/*
/*
/*
/*
/*
/*
System a d d r e s s 1
System a d d r e s s 0
System a d d r e s s 2
I / O Write
1/0 Read
FDC P o r t 03FO-03F8 hex
Keyboard P o r t 0 0 6 0 - 0 0 6 7
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
Read FDC P o r t 03F7 hex
*/
Write FDC P o r t 03F7 hex
*/
FDC Chip S e l e c t 03F4
03F5 */
W r i t e DORLTCH P o r t 03F2
*/
W r i t e P o r t 03F1 Driveswitch
*/
Write Keyboard P o r t 0 0 6 7 o r D*/
*/
Port 0062 or C
Port 0061 or B
*/
Read P o r t 0060
*/
Chip S e l e c t Enable P o r t 0065 */
*/
*/
*/
*/
*/
*/
*/
**/
=
=
=
=
=
.=
=
=
=
=
!f dmdrd
!fdmdwt
!fdcchp
dorltch
drvsck
wr i t d p
CP
bP
r eadap
csen
Logic Equations
I
I
I
I
I
I
I
;
I
;
**/
fdmdrd = f d c p o r t & sa02 & saOl & saOO & i o r ;
fdmdwt = f d c p o r t & s a 0 2 & saOl & saOO & iow;
fdcchp = f d c p o r t & sa02 & !saOl;
! d o r l t c h = f d c p o r t & iow & !sa02 & saOl & !saOO;
!drvsck = f d c p o r t & iow & !sa02 & !sa01 & saOO;
!readap = keyport & i o r & !sa02 & !sa01 & !saOO;
bp = keyport & !sa02 & ! s a 0 1 & saOO;
cp = keyport & !sa02 & saOl & !saOO;
csen = keyport & sa02 & !sa01 & saOO;
19
-
JACKSBORO SPECIFICATION
jmp
05-26-88
Table of C o n t e n t s
1 . 0 GENERAL
1.1 F u n c t i o n a l D e s c r i p t i o n
2.0
PIN LIST
3.0
ABSOLUTE MAXIMUM RATINGS
4.0
D. C . ELECTRICAL CHARACTERISTICS
4.1
Inputs
4.2
PDO - PD7, I N I T , /AFXT, /STROBE
4 . 3 /WAIT
4.4
DRQ, /TXD, /DTR, /RTS, PINT, SINT
4.5
I O D O - IOD7
5.0
AC CHARACTERISTICS
6.0
M o d i f i c a t i o n s t o t h e 76496
6.1
E x t r a B i t of D i v i s i o n b y e a c h c h a n n e l .
6.2
Synchronization of frequency dividers.
6 . 3 Minimum W a i t S t a t e G e n e r a t i o n
7.0
Software Specification
P o r t CO
C3 W r i t e
P o r t C4
Read
Port C5
Write
P o r t C5
Read
P o r t C6
R/W
P o r t C7
R/W
P o r t 2 0 0 - 2 0 7 WR
C l e a r J o y s t i c k DAC c o u n t e r
P o r t 2 0 0 - 2 0 7 RD
-- J o y s t i c k S t a t u s
Planar Control
1/0 Map Summary
-
--
i
1
1
1
4
4
4
4
4
4
5
6
7
7
7
7
8
8
9
9
9
10
10
10
11
11
12
1 . 0 GENERAL
1.1 F u n c t i o n a l D e s c r i p t i o n
T h e PSSJ T a n d y ASIC i s c o n t a i n e d i n a 6 8 p i n PLCC p a c k a g e , a n d
comprises t h e P r i n t e r p o r t ,
a S e r i a l (RS232) p o r t , t h e Sound
f u n c t i o n , a n d t h e J o y s t i c k f u n c t i o n of t h e T a n d y 1 0 0 0 c o m p u t e r s .
2.0
PIN L I S T
PIN NAME
PIN NO.
DRIVE
DESCRIPTION
vc c
1,35
--
Power i n p u t s
VBB
59
--
A n a l o g Power i n p u t
GND
18,52
--
Grounds
RST
25
TTL i n
System reset s i g n a l ,
a c t i v e high.
CLKl4M
2
TTL i n
Clock s i g n a l i n p u t ,
1 4 . 3 1 3 1 3 MHz, 5 0 % d u t y
cycle.
CLK2IN
37
TTL i n
Clock s i g n a l i n p u t ,
e i t h e r 24
MHz or 1 . 8 4 3 2 MHz, 5 0 %
duty
cycle.
14,15,16,17
19,20,21,22
DS1218,
8 mA TS
Eight b i t peripheral data
bus intended to d r i v e 5
XT t y p e 1/0 s l o t s , a s
w e l l as a l l on board
peripherals.
I OR-
10
TTL i n
CPU/DMA 1/0 Read s i g n a l ,
a c t i v e low.
System
control line.
I ow-
11
DS1218
CPU/DMA 1/0 Write s i g n a l ,
a c t i v e low.
System
control line.
- A2, A7
cso - c s 2
6,7,8,9
TTL i n
System a d d r e s s l i n e s .
3,4,5
TTL i n
Address decode i n p u t s .
PINT
12
2 mA TS
Printer Interrupt,
tristate.
IODO
A0
-
IOD7
1
PIN NAME
PIN NO.
DRIVE
DESCRIPTION
SINT
13
2 mA TS
Serial I n t e r r u p t ,
tristate.
PPITIM
68
TTL i n
Low f r e q u e n c y s o u n d
input.
AU D I 0-1 N
55
An i n .
Analog a u d i o i n p u t , 1 V
P-P
SND-OUT
57
An o u t
Analog a u d i o o u t p u t , 2 V
P-P
G A I N-OUT
56
An o u t
Analog a u d i o o u t p u t , 2 V
P-P
DRQ
23
2 mA TS
Data r e q u e s t f o r DMA
operations, tristate.
TC
27
TTL i n
Terminal Count i n p u t .
DACKl
26
TTL i n
Data a c k n o w l e d g e f o r DMA
ops.
WAIT-
24
2 mA OD
Sound c h i p w a i t o u t p u t ,
open d r a i n .
6 0 ,6 1 , 6 2 , 6 3
DS1218
Digital joystick position
input.
64,65,66,67
DS1218
D i g i t a l joystick switch
inputs.
58
An o u t
A n a l o g DAC o u t p u t f o r
external integration,
comparison w i t h j o y s t i c k
vo 1t a g e s .
51,50,49,48
47,46,45,44
DS1218
4 mA TS
Printer data
inputs/outputs.
INIT
40
4 mA OD
Printer initialization
output.
AFXT-
39
4 mA OD
P r i n t e r auto feed output.
STROBE-
38
4 mA OD
P r i n t e r s t r o b e output.
ACK-
41
TTL i n
P r i n t e r acknowledge
input.
JPOSl
-
JSWl
JPOS4
JSW4
DAC-OUT
PDO
-
PD7
2
PIN NAME
PIN NO.
DRIVE
DESCRIPTION
PE
43
TTL i n
P r i n t e r paper e m p t y
input.
SLCTIN-
53
TTL i n
P r i n t e r select input.
BUSY-
42
TTL i n
P r i n t e r busy i n p u t .
FAULT-
54
TTL i n
P r i n t e r f a u l t input.
DT R-
36
2 mA
RS232 d a t a t e r m i n a l r e a d y
output.
RTS-
33
2 mA
RS232 r e q u e s t t o s e n d
output
TXD-
34
2 mA
RS232 t r a n s m i t d a t a
output
RI-
29
TTL i n
RS232 r i n g i n d i c a t o r
input.
DCD-
30
TTL i n
RS232 c a r r i e r d e t e c t
input.
DS R-
28
TTL i n
RS232 d a t a s e t r e a d y
input.
CTS-
32
TTL i n
RS232 c l e a r t o s e n d
input.
RXD-
31
TTL i n
RS232 r e c e i v e d a t a i n p u t .
3
.
.
3.0
ABSOLUTE MAXIMUM RATINGS
Min-Typ-Max
Storage Temperature:
Operating Temperature:
All output pins
All input pins
Power Supply (Vcc)
Power dissipation
-65
0
-0.5
-0.5
-0.5
150
55
7.0
7.0
25
7.0
700
4.0
D. C. ELECTRICAL CHARACTERISTICS
4.1
Inputs
Leakage cur rent
Mi n-Typ-Max
4.2
PDO
-
2.0
2.1
-0.5
Vcc+.5
Vcc+.5
0.8
10
uA
volts DC
volts DC
volts DC
PF
PD7, INIT, /AFXT, /STROBE
Min-Typ-Max
4
Io1
vo 1
Ioh
Voh
Capacitive load
0.4
1
2.4
100
Mi n-Typ-Max
Io1
vo 1
Capacitive load
4.4
degrees C
degrees C
volts DC
volts DC
volts DC
milliwatts
Units
+/-lo
Vih (TTL in)
Vih (DS1218)
Vi1
Input capacitance
Units
4
Units
mA
volts DC
mA
volts DC
PF
Units
mA
0.4
100
volts DC
PF
DRQ, /TXD, /DTR, /RTS, PINT, SINT
Min-Typ-Max
Io1
vo 1
Ioh
Voh
Capacitive load
Units
2
0.4
1
2.4
40
4
mA
volts DC
mA
volts DC
PF
4.5
IODO
-
IOD7
M i n-Typ-Max
Units
8
Io1
vo 1
Ioh
Voh
Capacitive load
0.4
2
2.4
100
5
mA
v o l t s DC
mA
v o l t s DC
PF
5.0
AC CHARACTERISTICS
P a r ame t e r
Min-Typ-Max
Units
Tav ( A d d r e s s V a l i d )
Tah ( A d d r e s s Hold)
Trpw (Read P u l s e Width)
Twpw (Write P u l s e W i d t h )
Tdsu ( D a t a S e t u p ( W r i t e ) )
Tdacc ( D a t a Access ( R e a d ) )
Tdhr ( D a t a Hold ( R e a d ) )
Tdhw ( D a t a Hold ( W r i t e ) )
-15
30
120
125
65
nSec
nSec
nSec
nSec
nSec
nSec
nSec
nSec
Addr ,CSx
X
-->I
I<-- Tav
100
30
10
25
-->I
X
I<--Tah
IOWB
Data
1/0 Write C y c l e
Addr ,CSx
I ORB
-->I
X
X
I<-- Tav
I I<-------I
;
-
\
-->I I<--Tah
Trpw --_--_->I I
I
I
Data
1/0 Read Cycle
6
6.0
M o d i f i c a t i o n s t o t h e 76496
6.1
E x t r a B i t of D i v i s i o n by e a c h c h a n n e l .
When c l o c k e d by a 3.579545 MHz s i g n a l ,
t h e lowest frequency
g e n e r a t e d by t h e 76496
( w i t h i t s 1 0 b i t d i v i d e r s ) i s 109.24 Hz.
I t i s d e s i r e d t o be a b l e t o g e n e r a t e lower f r e q u e n c i e s .
An e x t r a
b i t of d i v i s i o n w i l l a l l o w f r e q u e n c i e s down t o 54.62 Hz, o r a n
o c t a v e lower t h a n t h e l o w e s t n o t e c u r r e n t l y a v a i l a b l e .
Since
t h e r e is an e x t r a b i t i n t h e frequency update r e g i s t e r (second
b y t e ) , i t makes s e n s e t o implement t h i s f e a t u r e h e r e .
However,
t o m a i n t a i n backwards c o m p a t i b i l i t y ,
s i n c e i t i s n o t known what
i s programmed i n t h i s b i t , t h e r e n e e d s t o b e a way of d e f e a t i n g
t h e e x t r a b i t of d i v i s i o n .
T h e r e f o r e , t h e r e i s a s i g n a l (SEDE),
which e n a b l e s t h e e x t r a b i t f o r a l l t h r e e c h a n n e l s . T h i s b i t
d e f a u l t s t o a l o g i c z e r o (low) on r e s e t .
when i t i s s e t , by
w r i t i n g t o p o r t C4 with b i t 6 high,
t h e e x t r a d i v i d e r w i l l be
enabled.
6.2
S y n c h r o n i z a t i o n of f r e q u e n c y d i v i d e r s .
The c u r r e n t 76496 d e s i g n l o a d s e a c h d i v i d e r when i n i t i a l l y
written to,
w i t h no p r o v i s i o n
f o r s y n c h r o n i z a t i o n of t h e
dividers.
T h i s i s a h a n d i c a p when programming f r e q u e n c i e s of low
i n t e g e r r e l a t i o n s h i p s t o each o t h e r , because it is n o t p o s s i b l e
t o guarantee
t h e phase
of
the
signals.
Therefore,
if
s y n c h r o n i z a t i o n i s d e s i r e d , i t is e n a b l e d by w r i t i n g t o p o r t C 4 ,
w i t h b i t 5 s e t (which d e f a u l t s t o r e s e t ) . When t h i s b i t i s h i g h ,
a n y w r i t e t o a f r e q u e n c y r e g i s t e r of t h e new sound c h a n n e l w i l l
not only load i t s d i v i d e r , but reload t h e d i v i d e r s i n t h e present
76496.
6.3
Minimum W a i t S t a t e G e n e r a t i o n
The 32 w a i t s t a t e s g e n e r a t e d by t h e 76496 need t o be r e d u c e d .
The c h i p must be g u a r a n t e e d t o l a t c h t h e d a t a w r i t t e n i n t h e same
t i m e a l l o t t e d f o r t h e 8250A m e g a c e l l .
Any w a i t s t a t e s g e n e r a t e d
should o n l y apply t o a s u c c e s s i v e w r i t e ( n o t t h e f i r s t i n a
series).
A l l w r i t e timing s h o u l d be r e f e r e n c e d t o t h e r i s i n g
e d g e o f t h e IOW- s t r o b e .
7
C4
W
(res)
SEDE
SDSE
DIEN
DICL-
DMAEN
DF1
DFO
Where :
DF1
Dac F u n c t i o n S e l e c t
0
0
1
1
Joystick
Sound Channel
S u c c e s s i v e Approximation
D i r e c t w r i t e t o DAC
DMAEN
DMA E n a b l e ( f o r SA, d i r e c t
R/W 1
DMA D i s a b l e d
DMA Enabled for SA, DA
0
1
DMA i n t e r r u p t c l e a r
DMA i n t e r r u p t h e l d c l e a r
DMA i n t e r r u p t a l l o w e d
DICL-
0
1
DMA I n t e r r u p t e n a b l e
DMA EOP i n t e r r u p t d i s a b l e d
DMA EOP i n t e r r u p t e n a b l e d
DIEN
0
1
Sound D i v i d e r Sync E n a b l e
Synchronization Disabled
Sync E n a b l e d : W r i t e t o C6
o r C7 r e l o a d s a l l d i v i d e r s
SDSE
0
1
Sound C h i p E x t r a D i v i d e
Enable
Extra Divide d i s a b l e d
Extra Divide enabled
S EDE
0
1
reserved
(res)
8
P o r t C4
[
Read
Readback a l l b i t s e x c e p t b i t 3.
bit 7
=
SAD-
-
bit 3
=
DIO
-
In addition:
]
S u c c e s s i v e Approximation
d o n e . U s e f u l when p o l l i n g
i n s t e a d o f DMA f o r
s u c c e s s i v e approximation.
DMA i n t e r r u p t h a s o c c u r r e d .
To c l e a r t h e i n t e r r u p t i t
i s n e c e s s a r y b r i n g DICL
low, t h e n back h i g h .
P o r t C5
Write
ws1
Where:
P o r t C5
wso
(res)
ws 1
wso
0
0
1
1
0
1
0
PW2
0
0
0
PW1
0
0
1
0
1
1
1
1
0
0
1
1
(res)
=
----
1
(res)
Pw2
PW1
PWO
Waveshape s e l e c t b i t s
Pulse
Ramp
Triangle
Reserved
6.25% d u t y c y c l e
12.5% d u t y c y c l e
18.75% d u t y c y c l e
25.0% d u t y c y c l e
31.25% d u t y c y c l e
37.5% d u t y c y c l e
43.75% d u t y c y c l e
50% d u t y c y c l e
1
Read
(DF1,O = 1 X b i n ) .
Direct r e a d of DAC (Succ. Approx.)
Direct r e a d of Snd C o n t r o l r e g i s t e r (DF1,O = 0 1 b i n ) .
9
P o r t C6
R/W
P o r t C7
R/W
A m p l i t u d e / f r e q u e n c y MSN f o r DAC sound c h a n n e l .
w i l l be
programmable i n
7
levels,
with
The a m p l i t u d e
The maximum l e v e l ('111') w i l l
a p p r o x i m a t e l y 3 dB p e r l e v e l .
c l o s e l y a p p r o x i m a t e t h a t i n t h e e x i s t i n g sound c h i p . A v a l u e of
' 0 0 0 ' w i l l r e s u l t i n no o u t p u t .
This level control a l s o applies
t o t h e raw DAC o u t p u t when o u t p u t t i n g d i g i t i z e d sound.
The t r i a n g l e
The ramp w i l l c o u n t up t h e f i v e M S B ' s of t h e DAC.
w i l l c o u n t up t h e f o u r M S B ' s of t h e DAC f o r t h e f i r s t h a l f of t h e
wave, t h e n c o u n t them back down f o r t h e s e c o n d h a l f .
The
f r e q u e n c y r a n g e of t h e DAC a s a sound c h a n n e l w i l l h a v e t h e same
u p p e r l i m i t and a l o w e r l i m i t of o n e o c t a v e l o w e r t h a n t h e new
Obviously,
f r e q u e n c y r a n g e of t h e sound c h i p (down t o 27.3 Hz.).
t h e b i t programming o r d e r o f t h e f r e q u e n c y is d i f f e r e n t . The
a c t u a l f r e q u e n c y w i l l b e 111.86 KHz d i v i d e d by t h e number
programmed i n t o t h e sound f r e q u e n d y r e g i s t e r ( s )
.
P o r t 200
-
207 WR
--
C l e a r J o y s t i c k DAC c o u n t e r
A write
t o p o r t 20X, where X = 0 t o 7 , w i l l c l e a r a f r e e - r u n n i n g
c o u n t e r , and l o a d a v a l u e o f 1 6 i n t o t h e 1 2 - b i t d i v i d e r .
The
e i g h t b i t f r e e - r u n n i n g c o u n t e r w i l l b e c l o c k e d by t h e 3.58 MHz
s i g n a l d i v i d e d by 2 4 , o r 1 4 9 . 1 KHz. The o u t p u t of t h e e i g h t b i t
c o u n t e r w i l l d r i v e t h e DAC t o p r o d u c e a s t a i r s t e p wave, which
s i m u l a t e s a ramp f o r u s e by t h e j o y s t i c k c o m p a r a t o r s .
When t h e
i t w i l l s t o p u n t i l p o r t 20X i s
c o u n t e r r e a c h e s a c o u n t of 255,
w r i t t e n t o again.
The e l a p s e d time f o r t h e c o m p l e t e ramp w i l l be a p p r o x i m a t e l y 1 . 7
m i l l i s e c o n d s , c l o s e l y a p p r o x i m a t i n g t h e e l a p s e d time of t h e
c u r r e n t Tandy 1 0 0 0 J o y s t i c k c i r c u i t r y .
10
P o r t 200
-
207 RD
--
J o y s t i c k Status
The d a t a r e a d a t p o r t 20X, w h e r e X = 0 t o 7 , w i l l b e t h e o u t p u t s
of t h e j o y s t i c k p o s i t i o n c o m p a r a t o r s and t h e s t a t e s o f t h e
j o y s t i c k pushbuttons,
i n t h e same manner a s t h e c u r r e n t Tandy
1000 J o y s t i c k c i r c u i t r y .
Planar Control
P o r t 6 5 c o n t a i n s t h r e e b i t s which a r e u s e d t o e n a b l e t h e p r i n t e r
i n t e r f a c e ( b i t l ) , t h e p r i n t e r o u t p u t ( b i t 7 ) , and t h e s e r i a l
port (bit 4).
These b i t s a r e a l l enabled ( s e t high) on reset,
and must be c l e a r e d by s o f t w a r e t o d i s a b l e t h e a p p r o p r i a t e
function.
The p r i n t e r o u t p u t e n a b l e f u n c t i o n i s l o g i c a l l y "ored" w i t h t h e c u r r e n t Tandy 1 0 0 0 p r i n t e r o u t p u t e n a b l e b i t , s o
t h a t e i t h e r one w i l l e n a b l e t h e p r i n t e r o u t p u t b u f f e r .
A d d i t i o n a l c o n t r o l i s a v a i l a b l e a t p o r t FFEB.
B i t DO
w h e t h e r t h e s e r i a l c l o c k i s d i v i d e d by 1 3 or 1. B i t D 1
h i g h t o e n a b l e t h e j o y s t i c k f u n c t i o n , a n d b i t D2 must be
e n a b l e t h e sound c h i p f u n c t i o n s . B i t s D 1 and D2 d e f a u l t
on power up.
11
selects
m u s t be
high t o
t o high
1/0 Map Summary
T h e f o l l o w i n g p o r t s a r e u t i l i z e d i n t h e PSSJ p a r t :
PORT
R/W
BITS
FUNCTION
.........................................................
.........................................................
0061
0065
OOCO-OOC3
OOC4-OOC7
0 2 0 0-0207
0378-037A
0 3F8-0 3FF
FFEB
W
R/W
W
R/W
R/W
R/W
R/W
R/W
4
1,4,7
a11
a1 1
a 11
a11
a11
0,1,2
12
Sound C h i p E n a b l e
Planar Control
S o u n d C h i p Data
DAC F u n c t i o n s
Joystick Function
Printer Interface
Serial Interface
UART c l o c k s e l e c t , JSE,DSE
TANDY COMPUTER PRODUCTS
Floppy Disk Support Chip Specification
TANDY COMPUTER PRODUCTS
Floppy Disk Support Chip Specification
Content8
Section
General Description
Pin Description
Block Diagram
Environmental Specifications
DC Electrical Specifications
AC Characteristics
Timing Diagrams
Page
TANOY COMPUTER PRODUCTS
Flopy Disk Support Logig
Tandy P a r t t 8 0 4 1 4 0 4
J a n u a r y 29, 1987
1.0
GENERAL DESCRIPTION
1.1 The Tandy P a r t # 8 0 4 1 4 0 4 - F l o p p y D i s k S u p p o r t L o g i c :
-Generates t h e c l o c k t o t h e 7 6 5 F l o p p y D i s k C o n t r o l l e r .
-Generates t h e w r i t e c l o c k t o t h e F l o p p y D i s k .
- G e n e r a t e s s t e p p u l s e s , t r a c k 0 i n d i c a t o r , DMA r e q u e s t ,
a n d FDC i n t e r r u p t s i g n a l s .
1-2 -3-4 -5--
CLK16M
WC K
FD CCLK
RDDATA*
RDD
6
RDW
FRES/S
RW*/SEEK
--
7-8 -9
--
lo--
11-12--
+5
SWITCH
INT+
DMA/INTE
DRQ
FDCINT
FDCDMRQ*
PSO
TRKO*
F/TRKO
STEP*
GND
FIGURE 1.
p51
WRD
WRE
WRDATA*
P i n Assignment
1
--24
--23
--22
--21
--20
--19
--18
--17
--16
--15
--14
--13
TANPY COMPUTER PRODUCTS
1.2 DESCRIPTION OF PINS:
DESCRIPTION
.....................................
1
CLKl6M
INPUT
Frequency = 16.0000 Tolerance = loopmm
2
WCK
OUTPUT
If SWITCH = 0, period = 2 us, 250 ns pulse
If SWITCH = 1, period = 1 us, 250 ns pulse
3
FDCCLK
OUTPUT
If SWITCH = 0, then CLK16M/4
If SWITCH = 1, then CLK16M/2
4
5
6
RDDATA
RDD
RDW
FRES/S
RW*/SEEK
TRKO*
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
Serial data from FDD
Serial data from FDC
Read Data Window
Step pulses to move head to another cylinder
Specifies seek mode when high
From FDD, indicating head is on track 0
To FDC, indicating head is on track 0
Moves head of FDD
Ground
Serial Data to FDD
Write Enable
Serial Data from FDC
Write precompensation status
Write precompensation status
DRQ delayed by 1.0 usec.
Interrupt request
FDC DMA Request
DMA request and FDC interrupt enable
Interrupt request generated by FDC
0 = low density drive
1 = high density drive
7
8
9
10
11
14
15
16
17
18
19
20
21
22
23
F/TRKO
STEP*
GND
WRDATA*
WRE
WRD
PS1
PS0
FDCDMRQ*
FDCINT
DRQ
DMA/ INTE
INT+
SWITCH
24
t5v
12
13
OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
+5 Volts
2
-TANDY COMPUTER PRODUCTS
DATA
PS8 :PS1
-
CI K16M
CLOCKS
ACK
DATH
SEPARATOR
RDD
SA I TCH
ROOATA
a
CONTROL
LOGIC
1-
FDCCl K
U
m r
I
W
L
CONTROL
LOGIC
BLOCK O I flGRF1H
3
RDW
Fer;e r l R O *
I
FI T-TRO
:=;TFpm
TANOY COMPUTER PRODUCTS
2.0 ENVIROMENTAL SPECIFICATIONS
2.1 Storage temperature: -65OC min.,
+15OoC max.
2 . 2 Operating temperature: O°C min., +25OC typ, +7OoC max.
3.0 DC ELECTRICAL SPECIFICATIONS
3.1 Absolute Maximum Rating:
Voltage on any pin
w.r.t. Ground:
-0.5 min., 7 . 0 max. volts
3.2 Operating Electrical Specifications:
Min.
---- Typ.
---- Max.
---- Units
-----
3.2.1 Operating Ambient:
Air Temperatue Range
0
25
70
4.5
0
5.0
0
5.5
0
OC
3.2.2 Power Supplies:
vcc
vss
ICC
Total Power
3.2.3 Leakage Current, All Inputs:
Vin = 0.0 v
Vin = 5.0 v
3.2.4
volts
volts
milliamps
milliwatts
-10
micro-
+10
microamps
YPS
Input voltages:
Except RDDATA" , TRK*
Logic r O g t
Logic ttl"
3.2.4 .2 RDDATA* , TRK*
Positive going threshold
Negative going threshold
Hysteresis voltage
3.2.4.1
.8
2.0
1.8
1.2
volts
volts
volts
volts
millivolts
220
3.2.5 Output Voltages:
3.2.5.1
Except WRDATA*, STEP*
@ 4.0 mA load
Logic
Logic I'1" @ 4.0 mA load
3.2.5.2
WRDATA* , STEP*
Logic "0" @ 48 mA
3.2.6 Input Capacitance (0.0
All inputs
3.2.7
.4
volts
volts
.5
volts
10
pf
50
pf
2.4
< Vin < 5.0)
Output Capacitance
All loads
5
TANDY COMPUTER PRODUCTS
4 .O
AC CHARACTERISTICS
4 . 1 FDCCLK T i m i n g
Min.
Typ.
Max.
90
120
5
120
250
130
10
160
255
Units
_--- ---- ---- -----
t
$'tF
100
245
Y
:t
nSec
nSec
nSec
nSec
4.2 WCK T i m i n g
100
250
250
5
10
t c y - ( tH+tR+tF
2 .o
nSec
nSec
pSec
4 . 3 WRDATA* T i m i n g
20
20
20
20
WCK -WEH
WCK'-WE~
PSDL
WDD
WDAW
WRDW
WDDH-WRDL e a r l y
WDDH-WRDL n o m i n a l
W D D H - ~ ~ ~l aLt e
115
150
275
400
100
1 00
W C K H - ~0
125
135
250
375
500
nSec
nSec
nSec
nSec
nSec
nS ec
nSec
nSec
nSec
4.4 DMA/INTERRUPT T i m i n g
30
30
IH-FIH
I -FIL
D k -FIL
W C ~ -DRQ
,
WCK -DRQ
DRQ;-FDR!~
D RQL- FD RQ
D I -FDRQ
F C -FD~ R b H
~
30
0
-20
750
6
1050
30
30
30
nSec
nSec
nSec
nSec
nSec
nSec
nSec
nSec
nSec
TANDY COMPUTER PRODUCTS
4.5 CONTROL Timing
---- Typ.
---- Max.
----
Min.
Parameter
---------
Units
---e-
30
30
30
30
30
30
nSec
nSec
nSec
nSec
nSec
nSec
550
313
260
900
nSec
nSec
nSec
nSec
pSec
4.6 DATA SEPARATOR Timing
RDAW
RDA -RDDH
RDD~
RDD -mW
200
188
240
850
RDAS
RDWC RDD
3062
15
RDAS
RDWC -RDDH
4812
RDAS
RDWC -RDDH
5062
15
RDWBNDI wc
-
350
250
875
2.0
nSec
nSec
19 38
nSec
nSec
c
7
nSec
nSec
TANOY COMPUTER PRODUCTS
FDSL AC TIMING
F I G . l FDCCLK
1
\
1
FIG. 2 WCK
WCKL-WEL+
FIG. 3
WRITE DATA TIMING.
9
TANDV COMPUTER PRODUCTS
I
I
I
FIG. 4
DMAlINTERRUPT TIMING.
10
TANDV COMPUTER PRODUCTS
I
TRKO+
I
I
FLT-TKO
I
TL-FTHA
FR - STP
FIG. 5
I
I
j /!
it
I
I
A
4b
' RSL-FTL
I
I
I
I
CONTROL LOGIC TIMING.
11
TANOY COMPUTER PRODUCTS
4
"A"
FRDAL-RDDH
RDD
I
RDW
1
II
I
I
1I
4 LRDWc-RDDH
RDDH-RDWC~
1
1
I
I
I
I
j+
FIG. 6
RDWC-4
RDDH
DATA SEPARATOR TIMING.
12
NEC
NEC Electronics Inc.
Description
The pPD765A is an LSI floppy disk controller (FDC) chip
which contains the circuitry and control functions for
interfacing a processor to4 floppy diskdrives. It is capable of either IBM 3740 single density format (FM), or IBM
System 34 double density format (MFM) including
double-sided recording. The pPD765A provides control
signals which simplify the design of an external phaselocked loop and write precompensation circuitry. The
FDC simplifies and handles most of the burdens associated with implementing a floppy disk interface.
The pPD7265 is an addition to the FDC family that has
been designed specifically for the Sony Micro Floppydisk" drive. ThepPD7265 is pincompatible and electrically equivalent to the 765A but utilizes the Sony
recordingformat. The pPD7265 can read a diskette that
has been formatted by the pPD765A.
Each of these devices is also available in a -2 version.
The -2 versions represent a reduction from 4-micron to
Bmicron design rule. Functionality is the same. Minor
differencesbetween the twoversions are detailed in the
AC Characteristics table. The -2 versions are only available in the plastic package at this time.
Hand-shaking signals are provided in the pPD765AI
pPD7265 which make DMA operation easy to incorporate with the aid of an external DMA controller chip,
such as the pPD8257. The FDC will operate in either the
DMA or non-DMAmode. In the non-DMAmode the FDC
generates interrupts to the processor every time a data
byte is to be transferred. In the DMA mode, the processor need only load the command into the FDC and all
data transfers occur under control of the FDC and DMA
controllers.
There are 15 commands which the pPD765AlpPD7265
will execute. Eachof these commandsrequires multiple
&bit bytes to fully specify theoperation which the processor wishes the FDC to perform. The following commands are available:
Read Data
Read Deleted Data
Read ID
Write Data
Specify
Format Track
Read Track
Write Deleted Data
Scan Equal
Seek
Scan High or Equal
Recalibrate
Scan Low or Equal
Sense Interrupt Status
Sense Drive Status.
pPD765A/7265
SINGLE/DOUBLE DENSITY
FLOPPY DISK CONTROLLERS
Features
Address mark detection circuitry is internal to the FDC
which simplifies the phase-locked loop and read electronics. The track stepping rate, head load time, and
head unload time are user-programmable. The
pPD765AlpPD7265 offers additional features such as
multi-track and multi-side read and write commands
and single and double density capabilities.
0 Sony (EMCA)-compatiblerecordingformat
bPD7265)
0 IBM-compatibleformat (single and double
density) bPD765A)
0 Multi-sector and multi-track transfer capability
0 Drive Up to 4 floppy or micro floppydlsk drives
0 Data scan capability- will scan a single sector or
an entire cylinder comparing byte-for-bytehost
memory and disk data
0 Data transfers in DMA or non-DMA mode
Parallel seek operations on up to four drives
0 Compatible with pPD8080/85, pPD8086/88 and
microprocessors
pPD780 (m)
0 Single-phase clock (8 MHz)
0 +5Vonly
ZBO is a registered trademark of the Zliog Corporation
Pin Configuration
6-3
NEC
pPD765A/7265
Ordering Information
Pin Functions
Max Frsq.
P8d
Number
PlCk8pC Typo
Ol Opsritinn
pPD765AC, pPD765AC-2
40-pin plastic DIP
8 MHz
pPD7266C.pPD7265C-2
&pin plastic DIP
8 MHz
Pin Identification
RESET (Reset)
The RESET input places the FDC in the idle state. It resets the output lines to the FDD to 0 (low). It does not
affect SRT, HUT, or HLT in the Specify command. If the
RDY input is held high during reset, the FDC will generate an interrupt within 1.024ms. To clear this interrupt,
use the Sense Interrupt Status command.
Ilo.
srnaoi
1
RESET
Reset input
m(Read Strobe)
Write control input
4
WR
w
Read control input
The m i n p u t allows the transfer of datafrom the FDC to
the data bus when low. Disabledwhen CS is high.
5
A0
Data or status select input
DBo-DB7
Bidirectional data bus
m ( W r i t e Strobe)
DRQ
DMA request output
The WR input allows the transfer of data tothe FDC
from the data bus when low. Disabledwhen CS is high.
2
3
6-13
14
15
-
RD
-
FUnctkn
Chip select input
DACK
DMA acknowledge input
16
TC
Terminal count input
17
I DX
Index input
18
INT
Interrupt request output
19
CLK
Clock input
20
GND
Ground
21
WCK
Write clock input
22
ROW
Read data window input -
23
ROD
Read data input
24
VCD
VCD sync output
25
WE
Write enable O U ~ O U ~
26
M FM
MFM output
27
HD
Head select output
USo, US1
FDD unit select output
WDA
Write data wtput
31,32
Bo. PSI
Preshift output
33
FLT I TRo
Faultltrack zero input
34
WP/TS
Write protectltwo side
input
28. 29
30
&(Data/Status Select)
The A0 input selects the data register (A0 = 1) or status
register (A0 = 0) contents to be sent to the data bus.
CS (Chip Select)
The FDC is selected when
and Ao.
is low, enabling
m,m,
DBo-DB7 (Data Bus)
DBo-DB7 are a bidirectional 8-bit data bus. Disabled
when CS is high.
DRQ (DMA Request)
The FDCasserts the DRQoutput high to request a DMA
transfer.
_.__
6-4
35
ROY
Ready input
36
HDL
Head load output
37
FRISTP
Fault reset/ step output
38
LCTIDIR
Low current direction
output
39
RW I SEEK
Readlwritelseek output
40
vcc
DC p e r
DACK (DMA Acknowledge)
input is low, a DMA cycle is active and
When the
the controller is performing a DMA transfer.
NEC
TC (Terminal Count)
PSO,P s (Preshift 0,l)
When theTC input is high, it indicates the termination of
a DMA transfer. It terminates data transfer during Read/
Writelscan commands in DMA or interrupt mode.
The PSo and PSI outputs are the write precompensation
status for MFM mode. They determine early, late, and
normal times.
IDX(lndex)
RDY (Ready)
The IDX input goes high at the beginning of adisk track.
The RDY input indicates that the FDD is ready to receive
data.
INT (Interrupt)
The INToutput is FDC’s interrupt request.
CLK (Clock)
CLK is the input for the FDC‘s single-phase, 8 MHz
squarewave clock.
WCK (Write Clock)
The WCK input sets the data write rate to the FDD. It is
500 kHz for FM, 1 MHz for MFM drives, with a 250 ns
pulse for both FM and MFM.
RDW (Read Data Window)
The ROW input is generated by the phase-locked loop
(PLL). It is used to sample data from the FDD.
RDD (Read Data)
The RDD input is the read data from the FDD, containing
clock and data bits.
HDL (Head Load)
The HDL output is the command which causes the
readlwrite head in the FDD to contact the diskette.
FLTlTRO(FaultlTrack 0)
In the readlwrite mode, the FLT input detects FDD fault
conditions. In the seek mode, TRO detects track 0.
WPlTS (Write ProtectlTwo Side)
In the readlwrite mode, the WP input senses write protected status. In the seek mode, TS senses two-sided
media.
FRlSTP (Fault ResetlStep)
In the readlwrite mode, the FR output resets the fault
flip-flop in the FDD. In the seek mode, STP outputs step
pulses to move the head to another cylinder. A fault reset pulse (FR) is issued at the beginning or each Read or
Write command prior to the HDL signal.
WDA(Write Data)
LCTlDlR (Low CunentlDirection)
WDA is the serial clock and data output to the FDD.
In the readlwrite mode, the LCT output lowers the write
current on the inner tracks. In the seek mode, the DIR
output determines the direction the head will move in
when it receives a step pulse.
WE (Write Enable)
The WE output enables writedata into the FDD.
vco (vco Sync)
W l S E E K (ReadlWritelSeek)
The VCO output inhibits the VCO in the PLL when low,
enables it when high.
The m l S E E K output specifies the readlwrite mode
when low, and the seek mode when high.
MFM (MFM Mode)
GND(Ground)
The MFM output shows the FDDs mode. It is high for
MFM, low for FM.
Ground.
VCC(+5v)
HD(Head Select)
+5 V power supply.
Head 1 is selected when the HD output is 1(high), head 0
is selected when HD is 0 (low).
USO,U s (Unit Select 0,l)
The US0 and US1 outputs select the floppy disk drive
unit.
6-5
Block Diagram
DC Characteristics
TA= -10% to +7OoC, V c c = +5 V f 5 % (crPD765A/7265A) and V c c
= +5V f10% @PD765A-2/7265A-2)
umm
k n d r
Inputvoltage
iow
Inputvoltage
high
OutputWage
low
Symbol
Mln
VIL
-0.5
VIH
2.0
lyp
rast
Mar
Unit
+0.8 V
Condltlonr
Vcc+O.5 V
0.45
V
IOL=Z.OmA
2.4
Vcc
V
lo~=-200pA
Inputvoltage- VIL(@) -0.5
low (CLK +WR
clock)
VIH(@) 2.4
Inputvoltage
high
0.65
V
Outputvoitaga
high
(CLK
VOL
VOH
Vcc+O.5 V
+m
clock)
Supply current
ICC
150
mA
Input load
current high
ILIH
'0
4
VIN=VCC
Input load
current low
ILIL
-10
4
VIN=OV
Output leakage ILOH
current hiah
10
Output leakage ILOL
current low
-10
pA
V0~~=+0.45V
Mar
UnH
20
pF
TA
Condltbni
(Note 1)
(Vcc)
Absolute Maximum Ratings
TA = 25%
Power sumiv voitaae. V r r
-0.510 +7V
Input voltage, VI
-0.510 +7V
Outout voltaae. Vn
-0.510 +7V
Operatingtemperature,Tom
Storaae temtwature. T m
Power dissipation,PO
-1O'C to +70°C
- 4 O O C 10 +125'C
1w
Comment: Exposingthe device to stresses above those listed
in the Absolute Maximum Ratings could cause permanent
damage. The device should not be operated under conditions
outside the limits describedin the operationalsections of this
specification. Exposure to absolute maximum rating conditions for extendedperiodsmay affect device reliability.
VOUT=VCC
Capacitance
TA =25'C, f c =1 MHZ, V c c = O V
unb
h n d r
Input Clock
capacitance
Symbol
GIN(@)
Yln
Sp
input
capacitance
CIN
10
pF
(Note 1)
output
caoacitance
COUT
20
pF
(Note 1)
Note:
(I)
All plns except pln undertest tied to AC ground
6-6
NEC
AC Characteristics
TA = -10%
to +70°C. VCC = +5 V f5% (crPD765Al7265A) and V c c = +5V flO% (lrPD765A-2n265A-2)
ulnlb
Plnmrkr
Clock Deriod
Symbol
@CY
Clock active (high, low)
@O
Yin
120
ns
Tnl
Condltkna
(Note4)
125
125
ns
8"FDD
250
250
ns
5114'' FDD
125
125
ns
3W'Sony (3)
70SA, 7905
Typ(i) Max
125
500
40
Yin
120
700A-2,7205-2
Typ(iJ Y u
125
500
40
ns
Clock rise time
@.
20
20
Clock fall time
41
20
20
no.=,
~AR
DACKsetuptimetomI
no, E,6ii% hold time from
t
-
RO width
t~
~ R R
Data access time from
mI
OB to float delay time from
no, E,DACKsetup time o
tm
b
Ao, E,
&$%hold
ns
ns
0
nS
0
0
ns
250
200
0
ns
200
~RD
t
Unit
IDF
20
tAW
0
100
10
140
ns
C~=100pF
85
ns
C~=100pF
0
ns
ns
0
0
WR width
h v
250
200
ns
Data setup time tomt
tDW
150
100
ns
time tomt
-
IWA
Data hold time f r o m m t
INT delay time from mt
INT delay time from
t
5
ns
0
500
tWD
tRl
400
400
500
tWl
tMCY
-
AM
MA
200
200
ns
DACK width
tAA
2
2
@CY
TC width
tTC
1
1
@CY
Reset width
tRSl
14
14
@CY
WCK cycle time
ICY
DACKI-
DRO t
DROIdelay
DACKI
-
delay
13
ns
DRO cycle time
-
13
ns
ps
140
200
4
16
@cy
8
@cy
MFM=l. 5114"
2
8
@rv
MFM=0.8
1
4
@cy
MFM=l. 31/2"(3)
2
2
@CY
10
CLKt-
WCKtdelav
trwu
0
40
0
40
ns
CLKt-
WCKIdelay
tCWL
0
40
0
40
ns
WCK rise time
1,
20
20
ns
WCK fall time
tf
20
20
ns
Preshiil delay time from WCKt
tcp
20
100
20
100
ns
WCKt
tCWF
20
100
20
100
ns
100
20
100
ns
WEt delav
WDA delay time from WCK t
ICD
20
ROO active time (high)
ADO
40
@cy=125ns (4)
2
WCK active time (high)
-
@~y=125ns(4)
ns
40
MFM=O. 5'14"
ns
6-7
4C Characteristics (cont)
Ta = -10%
to +7OoC. VCC = +5 V f 5 % (vPD765An265A)and VCC = +5V f10% (uPD765A-217265A-2)
Urnb
1651,7265
Panmotor
Window cycle time
Srnaol
Yin
tWCY
Typ(i)
766A-2,726S-2
Mar
Yln
Typ(i]
Max
UnH
TNt
Condltlons
4
4
pS
MFM=O,
2
2
ps
MFM=l. 5114"
5114"
2
2
pS
MFM=O.8"
1
1
pS
MFM=1.8"
2
2
pS
MFM=O, 3'/2"(3)
1
1
ps
MFM=l, 3'/2"(3)
Window hold time to RDD
tRDW
15
15
ns
Window hold time from RDD
US0.1 holdtimetowlseekt
tWRO
tu$
15
12
15
12
ps
8 MHz clock period(4)
tSD
7
7
ps
8 MHz clock period(4)
Low currentI directionhold time to
fault resetI step t
10s
1.0
1.0
ps
8 MHz clock period(4)
USo,1 hold time from fault reset1
steD 1
tgu
5.0
5.0
ps
8 MHz clock period(4)
RW I seek hold time to low
ns
currentldirectiont
Step active time (high)
tSTP
6
Step cycle time
tSC
33
Fault reset active time (high)
~FR
Write data width
~WDO
8.0
7
8
(Note 2) (Note 2)
10
10-50
6
33
8.0
7
8
(Note 2) (Note 2)
10
ps
(Note4)
ps
(Note4)
ps
(Note4)
10-50
ns
USo,1 hold time after seek
tsu
15
15
ps
8 MHz clock period(4)
Seek hold time from DIR
tDS
30
30
ps
8 MHz clock period(4)
DIR hold time after step
Index pulse width
tST0
24
ps
8 MHz clock period(4)
tlDX
24
4
4
@CY
RD iM a y from DRO
WRJdelay from DRO
~MR
800
800
ns
8 MHz clock period(4)
tMW
250
250
ns
8 MHz clock period(4)
WE or RD responsetime from DRO t
tMw
ps
8 MHz clock period(4)
-
12
12
Note:
(1) Typical values for Tn = 25% and nominal supply voltage.
(2) Under software control. The range is from 1ms to 16 ms at 8 MHz clock period, and 2 ms lo 32ms at 4 MHz clock period.
(3) Sony Micro Floppydlsk Fh" drive.
(4) Double thesa values for a 4 MHz clock perlod.
Tlmlng Waveforms
Processor Read Operation
I
6-8
Processor Write Operation
NEC
Timing Waveforms (cont)
Clock
DMA Operation
I
1
FDD Read operation
--*Glp-)-)
R.dD.1.Wlndav
ll0D1Elther poiarilydatawlndow io valid.
Terminal Count
FDD Wdte Operation
4 I-t.
Write Clock
Seek Operation
6-9
Internal Registers
Table 2. Main Status Register (cont)
The pPD765AlpPD7265 contains two registers which
may be accessed by the main system processor: a status register and a data register. The &bit main status
registercontains the status information of the FDC, and
may be accessed at any time. The &bit data register
(which actually consists of four registers,STO-ST3, in a
stackwith onlyone registerpresentedto thedata busat
a time), stores data, commands, parameters, and FDD
status information. Data bytesare read out of, or written
into, the data register in order to program or obtain the
results after a particular command (table 3). Only the
status register may be read and used to facilitate the
transfer of data between the processor and pPD765Al
pPD7265.
The relationship between the statusldata registersand
the signals RD, WR, and A0 is shown in table 1.
Table 1. StatuslData Register Addressing
b
E
W
R
rMotkn
0
0
1
0
1
0
Read main status register
Illegal
0
0
0
llleaal
1
0
0
Illegal
1
0
1
Read from data register
1
1
0
Write into data register
no.
DBg
DB7
Pln
wlnw
Function
DIO
Indicates direction of data transfer be(Data Input/Oulput) tween FDC and data register If DIO=l.
then transfer IS from data register to the
processor if DIO=O. then transfer is from
the processor to data register
ROM
Indicates data register is ready to send or
(Request for Master) receive data to or from the processor Both
bits DIO and ROM should be used to perform the hand-shaking functions of
"ready" and "direction" to the processor
The DIO and RQM bits in the status register indicate
when data is ready and in which direction data will be
transferred on the data bus. The maximum time between the last
or WR during a command or result
phase and DIO and RQM getting set or reset isl2ps. For
this reason every time the main status register is read
the CPU should wait 1 2 p ~ T h emaximum time from the
trailing edge of the last RD in the result phase to when
OB4 (FDC busy) goes low is 12ps. See figure 1.
Fiaure 7.
DIO and RQM
The bits in the main status register are defined in
table 2.
Table 2. Main Status Register
mn
Ik.
wlnw
FUnctkn
FDD number 0 is in the seek mode. If any
of the DnB bits is set FDC will not accept
read or write command.
OB0
DoB
(FDD 0 Busy)
DB1
D1B
(FDD 1Busy)
FDDnumberlisintheseekmode. lfanyof
the D,B bits is set FDC will not accept read
or write command.
DBp
DpB
(FDD 2 Busy)
DE3
D3B
(FOD 3 Busy)
DB4
CB
(FDC Busy)
DB5
EXM
(Execution Mode)
FDD number 2 is in the seek mode If any
of the D,B blts is set FDC will not accept
read or wrlte command.
FDD number 3 is in the Seek mode. If any
of the DnB bits is set FDC will not accept
read or write command.
A Read or Write command is in process.
FDC will not accept any other command.
This bit is set only during execution phase
in non-DMA mode. When DB5 goes low,
execution phase has ended and result
phase has started. It operates only during
non-DMA mode of operation.
6-1 0
om", A-
D m register ready lo +x wdlten Into by pmessoi.
6- Data ~ l s l e 1101
r ready 10 be written Info by pmcessor.
C- Dataregisterm d y for nad dala byte to be read by pmcessor.
P Data registernot ready Io +x read by pmcessror.
NEC
Table 3. status Register Identification
Table 3. Status Resister Identification(contl
Pln
no.
lknw
runctlon
IC
(Interrupt Code)
Pln
lknr
D7=0 and D6=O
Normal termination of command, (NT).
Command was completed and properly executed.
Dp
ND
(No Data)
D7 = O and Dg=l
Abnormal termination of command, (AT).
Execution of command was started but
was not successfultv completed.
D5
D4
SE
(Seek End)
EC
(Equipment Check)
NW
(Not Writable)
During execution of Write Data. Write Deleted Data or Format A Cylinder command,
if the FDC detects a write protect signal
from the FDD, then this flag is set.
Do
MA
(Missing Address
Mark)
If the FDC cannot detect the data address
mark or deleted data address mark, this
flag is set. Also at the same time. the MD
(missing address mark in data field) of
status register 2 is set.
When the FDC completes the Seek command. this flag is set to 1 (high).
Ifafaultsignal is receivedfromthe FOD. or
if the track 0 signal fails to occur after 77
step pulses (Recalibrate Command) then
this flag is set.
When the FDD is in the not-ready state and
a Read or Write command is issued, this
flag is set. If a Read or Write command is
issued to side 1 of a single-sided drive,
then this flag is set.
HD
(Head Address)
This flag is used to indicate the State of the
head at interrupt.
D1
us1
(Unit Select 1)
This flag is used to indicate a drive unit
number at interrupt.
US0
(Unit Select OI
This flag is used to indicate a drive unit
number at interruDt
Status Register 1
Dq
D3
When the FDC tries to access a sector beyond the final sector of a cylinder, this flag
is set
Status Register 2
D7
06
DE
(Data Error)
When the FDC detects a CRC(1) error in eithertheiDfieldorlhedatafield,thisflagis
set.
OR
(Overrun)
If the FDC is not serviced by the host system during data transfers within a certain
time interval. this llaa is set.
Not used. This bit is always 0 (low).
CM
(Control Mark)
Not used. This bit is always 0 (low).
During execution of the Read Data or Scan
command, if the FDC encounters a sector
which contains a deleted data address
mark, this flag is set.
D5
DD
(Data Error in
Data Field)
if the FOC detects a CRC error in the data
field then this flag is set.
D4
WC
(Wrong Cylinder)
This bit is related to the ND bit, and when
the contents of C(3) on the medium is different from that stored in the IDA. this flag
is set
Dg
SH
(Scan Equal Hit)
During execution of the Scan command, if
the condition of "equal" is satisfied, this
flao is set
Dp
SN
(Scan Not Satisfied)
During execution of the Scan command, if
the FDC cannot find a sector on the cylinder which meets the condition, then this
flag is set.
D1
BC
(Bad Cylinder)
This bit is related to the ND bit, and when
the contents of C on the medium is different from that stored in the IDR and the contents of C is FFH. then this flag is set.
Do
MD
(Missing Address
Mark in Data Field)
When data is read from the medium, if the
FDC cannot find a data address mark or
deleted data address mark, then this flag
is set.
Not used. This bit is always 0 (low).
D6
Dg
During execution of the Read A Cylinder
command, if the starting sector cannot be
found, then this flag is set.
D1
Dp
EN
(End of Cylinder)
During execution of the Read ID command,
if the FDC Cannot read the ID field without
an error. then this flag is set.
D7=landDg=l
Abnormal termination because during
command execution the ready signal from
FDD changed state.
NR
(Not Ready)
D7
During execution of Read Data. Write Deleted Data or Scan command, if the FDC
cannot find the sector specified in the
IDR(2) Register, this flag is set.
D7 = 1 and Dg=O
Invalid command issue, (IC). Command
which was issued was never started.
D3
Do
runctlon
Status Reoitter 1Icontl
Status Register 0
D73 D6
Yo.
6-11
Table 3. Status Register Identification (coni)
Command Symbol Description
Pin
No.
Function
Nanw
Status Register 3
A0 controls selection of main status register
(Ag=O) or data register (Ao=I).
(Fault)
This bit is used to indicate the status 01the
fault signal from the FDD.
C
(Cylinder Number)
C stands for the current/selected cylinder
(track) numbers 0 through 76 otthe medium.
WP
(Write Protected)
This bit is used to indicate the status 01the
write orotected sianal from the FDD.
D
IData)
D stands for the data pattern which is going to be
written into a sector.
RY
(Ready)
TO
(Track 0)
This bit is used to indicate the status of the
ready signal from the FDD.
D7-DO
(Data Bus)
This bit is used to indicate the status 01the
track 0 signal from the FDD
&bit data bus, where D7 stands for a most
significant bit. and DO stands for a least
significant bit.
D3
TS
(Two-Side)
This bit is used to indicate the Status of the
two-side signal from the FDD.
DTL
(Data Length)
When N is defined as 00, DTL stands for the data
length which users are going to read out or write
into the sector.
Dp
HD
(Head Address)
This bit is used to indicate the status of the
side Select signal tothe FDD.
EDT
(End of Track)
EDT stands for the final sector number on a cylinder. During read or write operations, FDC will stop
data transfer after a sector number equal to EOT.
Di
US1
(Unit Select 1)
This bit is used to indicate the status 01the
unit select 1signal to the FDD.
GPL
(Gap Length)
us0
This bit is used to indicate the status of the
unit select 0 sianal to the FDD.
GPL stands tor the length of gap 3. During Read /
Write commands this value determines the number 01 bytes that VCO sync will stay low after two
CRC bytes. During Format wmmand it determines the size of gap 3.
H
lHead Address)
H stands tor head number 0 or 1, as specified in
ID tieid.
HD
(Head)
HD stands for a selected head number 0 or 1 and
controlsthepolarityofpin27. (H=HDinalicommand words.)
HLT
(Head Load Time)
HLTstandsforthe headloadtimeintheFDD(2to
254 ms in 2 ms increments).
HUT
(Head Unload Time)
HUT stands for the head unload time after a Read
or Write operation has occurred (16 to 240ms in
16ms increments).
MF
(FM or MFM Mode)
If MF is low, FM mode is selected. and if it is high,
MFM mode is selected.
MT
(Multitrack)
IF MT is high, a multitrack operation is performed. if MT = 1after finishing read / write operation on side 0. FDC will automatically start
searchina for sector t on side 1
N
(Number)
N stands for the number of data bytes written in a
sector.
NCN
(New Cylinder Number)
NCN stands for a new cylinder number which is
going to be reached as a result 01the seek operation; desired position of head.
ND
1Non-DMA Mode)
ND stands tor operation in the non-DMA mode.
D7
D5
Dq
Do
FT
(Unit Select 01
Note:
(1) CRC= Cyclic Redundancy Check
(2) IOR= Internal Data Register
(3) Cylinder (C) is described more fully in the Command Symbol
Description.
Command Sequence
The pPD765AlpPD7265is capable of performing 15 different commands. Each command is initiated by a
multibyte transfer from the processor, and the result after execution of the command may also be a multibyte
transfer back to the processor. Because of this multibyte interchange of information between the pPD765AI
pPD7265and the processor, it is convenient to consider
each command as consisting of three phases:
Command
The FDC receives all information rePhase:
quired to perform a particular operation from the processor.
Execution
The FDC performs the operation it
Phase:
was instructed to do.
Result Phase: After completion of the operation,
status and other housekeeping information are made available to the
processor.
Table 4 shows the required preset parameters and
results for each command. Most commands require 9
command bytes and return 7 bytes during the result
phase. The “ W ’ to the left of each byte indicates a command phase byte to be written, and an “R” indicates a
result byte. The definitions of other abbriviations used
in table are given in the Command Symbol Description
table.
6-12
A0
(Address Line 0)
PCN
PCN stands tor the cylinder number at the com(Present Cylinder Number) pletion of Sense Interrupt Status command, position 01 head at present time.
R
(Record)
R stands for the sector number which will be read
or written.
RIW
(Read / Write)
R I W stands for either Read (R) or Write (W)
signal.
sc
SC indicafes the number of sectors per cylinder.
(Sector)
SK
(Skin)
SK stands lor skip deleted data address mark.
NEC
Command Symbol Description(cont)
NllM
Command Symbol Description (cont)
I*nw
FUnctkn
SRT stands for the stepping rate lor the FDD (1to
16ms in 1ms increments). Stepping rate applies
to all drives (FH =1 ms. EH =2 ms. etc.).
STO-ST3 stands for one of four registers which
store the status informationafter a command has
been executed. This information is available during the result phase after command execution.
These registersshould not be confused with the
main status register (selected by &=O).
STO-ST3 may be read only after a command has
been executedand contains information relevant
to that particularcommand.
SRT
(Step Rate Time)
STO-ST3
(Status0-3)
FMCtlon
STP
During a scan operation, if STP=1. the data in
contiguous sectors is comparedbyte by byte with
data sent from the processor (or DMA); and il
STP= 2. then alternate sectors are read and compared.
USo, US,
(Unit Select)
US stands for a selected drive number 0 or 1.
Table4. Instruction Set (Notes 7,2)
Read Data
Command
W
w
w
w
w
-
MT
X
MF
X
SK
X
0
X
0
X
1
HD
1
US1
0
US0
Y
Commandcodes
(Noie3)
SectnIDinformatlonprrortocanmandexenmon.
The4bytss
are comparedagainst header on floppy disk.
W
W
EOT
GPL
DTL
W
W
Data transfer between Me FDDand main system
Execution
Result
Read D a b d Data
Command
R
-
R
R
R
R
R
R
-
W
W
w
W
W
W
w
W
W
Status informationafter m m a n d mcution
STO
ST 1
ST2
-
-
-
MT
X
MF
X
SK
X
1
X
0
X
1
HD
0
0
US1
US0
Commandcodes
Sector ID informationprior to commandexecution. The 4 bytes
are m p a r e d against header on floppy disk.
F
.
I
-
EOT
GPL
DTL
Data transfer between the FDD and main system
Execution
Result
Sector ID informationafter m m a n d execution
R
R
R
R
R
R
STO
STI
ST2
Status information after commandexecution
-
Sector ID informationafter commandexecutii
Note:
(1) Symbols used in this table are described at the end of this sect1on.l
(2) A. should equal 1 for all operations.
(3) X = Don't care, usually made to equal 0.
6-13
Table4. Instruction Sei(Notes 1,2)fcont)
Plmn
RIW
DI
DI
DB
W
W
MT
X
MF
X
X
lllsmdmcoda
4
Da
4
I*nurLI
DI
Do
0
US1
US0
WfIbDn
Command
w
w
w
w
W
w
-
0
0
X
0
X
1
HD
-
-
biiutbn
ResuH
WIIMWlbb
Command
R
R
R
R
-
R
-
R
R
-
W
W
W
w
w
w
w
w
STO
ST1
ST2
Data transfer betweenthe main system and FDD
Status informationafter wmmand executlon
c
Sector ID information after commandexecution
II
MT
X
MF
X
0
X
-
0
X
1
X
0
HD
0
US1
1
US,
-
Commandcodes
Sector IDinformationpriwtouwnmandexecutlon.The4 bytes
are mpared against header on floppy disk.
EOT
GPL
- DTL
W
Data transfer batman the FDD and main system
Execution
Result
Sector ID information prior to m m a n d execution. The 4 bytes
are mpared against header on floppy disk.
-
EOT
GPL
DTL
W
Commandcodes
1
R
R
R
R
R
R
R
Status informationaner command execution
STO
sT1
ST2
-
Sector ID Information after commandexecution
F
RddATkk
Command
W
W
w
w
w
w
W
W
w
-
0
X
MF
X
SK
X
0
X
0
X
R
R
R
R
R
-
6-14
0
US0
Commandcodes
I
EOT
GPL
DTL
STO
sT1
-
Datatransfer betweenthe FDDand main system. FDC readsall
data fields from index hole to EOT.
Status informationafter command execution
sT2
Sector ID information after commandexecution
-
R
R
1
US1
Sector ID information prior to commandexecution
Execution
Result
0
HD
-
I
NEC
Command
0
X
W
W
MF
X
0
X
0
1
X
X
0
HD
1
US1
0
US0
Execution
Resuit
FonlA lhck
Command
The first correct ID informationon the cylinder is stored in data
register.
R
R
R
R
R
R
R
W
W
w
STO
-
Status informationalter command ixecution
STl
--
ST2
-
0
-
X
MF
X
0
0
1
X
X
X
1
HD
0
US1
1
US0
--
sc
W
W
GPL
W
-
Execution
Result
Commandcodes
R
R
R
R
R
R
R
STO
ST1
ST2
-
Sector ID informationread during execution phase from floppy
disk.
Commandcodes
Byteslurctor
Sectonhack
Gap 3
Filler byte
FDC formats an entire track.
Status informationalter command execution
In this case, the ID informationhas no meaning
Sun Equal
Command
W
W
W
W
w
w
w
MT
X
MF
X
-
W
W
SK
X
0
1
X
X
0
HD
R
R
R
R
R
R
R
-
Commandcodes
-
Data compared between the FDD and main system
1
US0
Sector ID inlormation prior to command execution
EOT
GPL
STP
Execution
Result
0
US1
STO
ST1
ST2
Status information aner command execution
Sector ID informationafter command execution
Not.:
(1) Symbols used in this table are described at the end of this section.
(2)AOshould equal 1 for ail operatlons.
(3) X = Don't care, usually made to equal 0.
6-1 5
Table4. lnsiruciion Sei (Notes 1,2)(coni)
Phaw
RIW
D,
De
DB
W
W
W
MT
X
MF
X
SK
X
lnrtrvstlonCod0
D4
D)
De
D(
Do
0
US1
US0
R.nurlu
Sean Low or Equal
Command
1
X
1
X
0
HD
1
-
P
w
-
W
W
w
EDT
GPL
STP
-
W
-
Status information after command execution
-
Sector ID information after command execution
Execueon
R
R
R
R
R
R
Sector ID information prior to command execution
z
W
Result
Commandcodes
ST 0
ST1
ST 2
-
Data compared between the FDD and main system
Scan High or Equal
Command
W
W
w
w
W
W
W
-
w
w
-
R
A
A
R
R
R
R
-
MT
X
MF
X
SK
X
1
X
1
X
0
US1
1
HD
1
-
Command
W
w
-
ST 0
STl
sr2
-
0
x
0
0
x
x
0
0
x
x
1
0
1
us1
1
us0
sense Interrupt status
Command
W
Result
R
0
0
0
0
W
W
W
W
W
Result
6-1 6
R
1
0
0
0
STO
PCN
R
WdfY
Senre Dlks Status
Command
Data compared between the FDD and main system
Status information after command execution
Sector ID information after command execution
Commandcodes
Head retracted to track 0
Execution
Command
Sector ID information prior to command execution
EDT
GPL
STP
Execution
Resuit
Commandcodes
US0
-
- -- 0
0
0
0
0
0
1
Commandcodes
HUT
SRT
HLT
0
X
1
Commandcodes
Status information about the FDC at the end of seek operation
0
0
0
X
X
X
ND
0
X
ST 3
1
HD
0
US,
0
US0
Commandcodes
Status information about FDD
NEC
Table4. instruction Set (Notes 1,2)(cont)
Phn4
W
nI-
RIW
D,
De
D6
DI
Da
Dp
DI
Do
W
W
0
X
0
X
0
X
0
1
X
1
HD
1
US1
1
US0
Renmrka
Swk
Command
w
-
X
Commandcodes
NCN
Head is positioned over proper cylinder on diskette
Execution
lnvalld
Command
W
Resuil
R
InvalidCodes
-
SI0
-
InvalidCommandcodes (Noop- FDC goes into standby state)
STO=80H
Note:
(1) SymbOls used in this table are describedat the end of this section.
(2) n,shouldequal 1 for all operations.
(3) X = Don’t care, usually made to equal 0.
System Configuration
Figure 2 shows an example of a system using a
pPD765AlpPD7265.
Figure 2.
System Configuration
/_I
to thepPD765AlpPD7265.On the other hand, during the
result phase, 06 and D7 in the main status register must
both be 1’s (06 = 1 and D7 = 1) before reading each byte
from thedata register. Notethat this readingof the main
status register before each byte transfer to the
pPD765AlpPD7265is requiredonly in the command and
result phases, and not during the execution phase.
During the execution phase, the main status register
need not be read. If the pPD765AIpPD7265is in the nonDMA mode, then the receipt of each data byte (If
pPD765AlpPD7265 is reading data from FDD) is indicated by an interrupt signal on pin 18 (INT = 1). The generation of a read signal
0) or write signal (WR = 0)
will clear the interrupt as well as output the data onto
the data bus. If the processor cannot handle interrupts
fast enough (every 13ps for the MFM mode and 27ps for
the FM mode), then it may poll the main status register
and bit 07 (RQM) functions as the lnterru t signal. If a
signal newrite command is in process then the
gates the reset to the interrupt signal.
Note that in the non-DMAmode it is necessary to examine the main status register to determine the cause of
the interrupt, since it could be a data interrupt or a command termination interrupt, either normal or abnormal.
If the pPD765AIpPD7265 is in the DMA mode, no interrupts are generated during the execution phase. The
pPD765AIpPD7265 generates DRQs (DMA requests)
when each byte of data is available. T K M A controller
responds to this request with both a DACK = 0 (DMA acknowledge) and an RD = 0 (read signal). When the DMA
acknowledgesignal goes low (DXK=O), then the DMA
request is cleared (DRQ = 0). If a write command has
been issued then a m s i g n a l will appear instead of
After the executionphase has beencompleted(terminal
count has occurred) or the EOT sector readlwrltten,
then an interrupt will occur (INT= 1). Thls signifies the
beginning of the result phase. When the first byte of
(m=
&
ProcessorInterface
During command or result phases the main status reg
ister (described earlier) must be read by the processor
before each byte of information is written into or read
from the data register. After each byte of data read or
written to the data register, CPU should wait forl2ps b e
fore reading main status register, bits D6 and @ in the
main status register must be in a 0 and 1 state, respectively, before each byte of the command word may be
written into the pPD765AlpPD7265. Many of the commands require multiple bytes and, as a result, the main
status register must be read prior to each byte transfer
m.
6-17
NEC
pPD76SA/7265
data is read during the result phase, the interrupt is automatically cleared (INT= 0).
The R-ormsignals should be asserted while E K Is
true. The =signal is used in conjunctionwith
and
WR as a gating function during programmed 110 operations.
has no effect during =operations.
If the
non-DMA mode is chosen, the DACK signal should be
pulled up to vcc.
It is important to note that during the result phase all
bytes shown In the command table (table 4) must be
read. The read data command, for example, has seven
bytes of data In the result phase. All seven bytes must
be read in order to successfully completethe Read Data
command.ThepPD765A/pPD7265wlllnot accept anew
comand until all seven bytes have been read. Other
commands may require fewer bytes to be read during
the result phase.
The pPD765AIpPD7265 contains five status registers.
The main status register mentioned above may be read
by the processorat any time. The other four status registers (STO, ST1, ST2, and ST3)are available only during
the result phase and may be read only after completing
a command. The particularcommandthat has been executeddetermineshow many of the status registerswill
be read.
The bytes of data which are sent to the pPD765AI
pPD7265 to form the command phase and are read out
of the pPD765AIpPD7285in the result phase must occur
in the order shown in table 4. That is, the commandcode
must be sent first and the other bytes sent in the prescribed sequence. No foreshortening of the command
or result phases is allowed. After the last byteof data in
the command phase is sent to the pPD765AIpPD7265,
the execution phase automatically starts. In a similar
fashion, when the last byte of data Is read out In the
result phase, the command is automatically ended and
the pPD765AIpPD7285is ready for a new command.
-
Figure 3. polling Feature
=
Polling
After reset has been sent to the pPD765AlpPD7285,the
unit select lines USoandU a will automatically go intoa
polling mode. In between commands(andbetween step
pulses in the Seek command) the pPD765AlpPD726.5
polls all four FDDs lookingforachange Inthe ready line
from any of the drives. If the ready line changes state
(usually due to a door opening or closing), then the
pPD765AlpPD726.5will generate an interrupt. When status register 0 ( S O ) Is read (after Sense interruptStatus
is issued), not ready (NR) will be indicated. The polling
of the ready line by the pPD765AIpPD7265occurs continuously between commands, thus notifying the processor which drives are on or off line. Eachdrive is polled
every 1.024ms except during the ReadlWrlte com6-18
mands.When used with a4 MHz clock for interfacingto
minifloppies, the polling rate is 2.048 ms. See figure 3.
Read Data
A set of nine (9) byte words are required to place the FDC
into the read data mode. After the Read Data command
has been Issued the FDC loads the head (if it Is in the
unloaded state), waits the specified head settling time
(defined in the Specify command), and begins reading
ID address marks and IDfields. When the current sector
number(R) stored in the ID reglster(1DR) compares with
the sector number read off the diskette, then the FDC
outputs data (from the data field) byte-to-byte to the
main system via the data bus.
After completion of the read operation from the current
sector, the sector number Is lncremented by one, and
the data from the next sector Is read and output on the
data bus. This continuous read function is called a
multi-sectorread operation. The Read Data command
may beterminatedby the receiptof a terminal count signal. TC should be issued at the same time that the
DACK for the last byte of data is sent. Upon receipt of
this signal, the FDC stopsoutputtlngdata to the processor, but will continue to read data from the current sector, check CRC (cyclic redundancy count) bytes, and
then at the end of the sector terminate the Read Data
command. The amount of data which can be handled
with a single command to the FDC depends upon MT
(multi-track), MF (MFMIFM), and N (number of bytes/
sector). Table 5 shows the transfer capacity.
The “multi-track” function (MT) allows the FDC to read
data from both sidesof the diskette. For a particular cylinder, data will be transferredstarting at sector 1, side 0
and completing at sector L, side 1(sector L = last sector
on the side). Note, this function pertainsto only one cylinder (the same track) on each side of the diskette.
When N = 0, then DTL defines the data length which the
FDC must treat as a sector. If DTL is smaller than the
actual data length in a sector, the data beyond DTL in
the sector Is not sent to the data bus. The FDC reads
(internally) the complete sector performing the CRC
check and, depending upon the manner of command
-
NEC
termination, may perform a multi-sector read operation.
When N is non-zero, then DTL has no meaning and
should be set to FFH.
Table 5. Transfer Capacity
Multl. MFMl Bytes1
lhck
FY &tor
MI
IF
N
MaxirnurnlhnrforCapacity
(Bytorl&ctor)
INurnborofSoctonl
Flnalkctor
Rudfmrn
Disk-
0
0
0
1
00
01
(128) (26) = 3.328
(256) (26) = 6,656
26atsideO
or26atstdel
1
1
0
1
00
01
(128) (52) = 6,656
(256)(52) = 13,312
26alside1
0
0
0
1
01
02
(256)(15) = 3,840
(512) (15) = 7,680
15alsideO
or15 at side1
1
1
0
1
01
02
(256) (30) = 7.680
(512)(30) = 15,360
15at side1
0
0
0
1
02
03
(512)(8) = 4,096
(1024)(8) = 8,192
8at side0
or8atsidel
1
1
0
1
02
03
(512)(16)= 8,192
f1024)1161 = 16 384
Eatside1
At the completion of the Read Data command, the head
is not unloaded until after head unload time interval
(specified in the Specify command) has elapsed. If the
processor issues another command beforethe head unloads then the head settling time may be saved between
subsequent reads. This time out is particularly valuable
when a diskette is copied from one drive to another.
If the FDC detects the index hole twice without finding
the right sector, (indicated in “R”), then the FDC sets the
ND (No data) flag in status register 1 to a 1 (high), and
terminates the Read Data command. (Status register 0
also has bits 7 and 6 set to 0 and 1, respectively.)
After reading the ID and data fields in each sector, the
FDC checks the CRC bytes. If a read error is detected
(incorrect CRC in ID field), the FDC sets the DE (data error)flag in status register1to a1 (high),and if aCRCerror
occurs in the data field, the FDC also sets the DD (data
error in data field) flag in status register 2 to a 1 (high),
and terminates the Read Data command. (Status registerO also has bits 7 and 6 set to 0 and 1, respectively.)
If the FDC reads a deleted data address mark off the
diskette, and the SK bit (bit D5 in the first command
word) is not set (SK = 0), then the FDC sets the CM (control mark) flag in status register 2 to a 1(high),and terminates the Read Data command, after reading all the
data in the sector. If SK=1, the FDC skips the sector
with the deleted data address mark and reads the next
sector. The CRC bits in the deleted data field are not
checked when SK = 1.
During disk data transfers between the FDC and the
processor, via the data bus, the FDC must be serviced
by the processor every 27ps in the FM mode, and every
13ps in the MFM mode, or the FDC sets the OR (Overrun)
flag in status register 1 to a 1 (high), and terminates the
Read Data command.
If the processor terminates a read (or write) operation in
the FDC, then the ID information in the result phase is
dependent upon the state of the MT bit and EOT byte.
Table 2 shows the values for C, H, R, and N, when the
processor terminates the command.
Functional Description of Commands
Write Data
A set of nine (9) bytes is required to set the FDC into the
write data mode. After the Write Data command has
been issued the FDC loads the head (if it is in the unloaded state), waits the specified head settling time(defined in the Specify command), and begins reading ID
fields. When all four bytes loaded during the command
(C, H, R, N) match the four bytes of the ID field from the
diskette, the FDC takes data from the processor byte-bybyte via the data bus and outputs it to the FDD. See
table 6.
Table 6. Command Description
YT
HD
rlnalwrmn*md
toPmcossor
C
H
R
N
0
0
Lessthan EOT
NC
NC
R+l
NC
0
0
EqualtoEOT
C+l
NC
R=01
NC
0
1
LessthanEOT
NC
NC
R+1
NC
0
1
EqualtoEOT
C+l
NC
R=01
NC
1
0
Lessthan EOT
NC
NC
R+l
NC
1
0
EqualtoEOT
NC
LSB
R=01
NC
NC
R+l
LSB
R=01
1
1
LessthanEOT
1
1
EoualtoEOT
NC
C+1
~~~
~~
~~
NC
NC
~
Note:
(1) NC(No Change):Thesarnevalueas the one at the beginning of cornrnand execution.
(2) LSB (Least Significant Bit): The least significant bit of H is cornpie
rnented.
After writing data into the current sector, the sector
number stored in R is incremented by one, and the next
data field is written into. The FDC continues this multisector write operation until the issuance of a terminal
count signal. If a terminal count signal is sent to the
FDC it continues writing into the current sector to
complete the data field. If the terminal count signal is
received while a data field is being written then the remainderof the data field is filled with zeros.
The FDC reads the ID field of each sector and checks
the CRC bytes. If the FDC detects a read error (CRC error) in one of the ID fields, it sets the DE (Data Error) flag
of status register 1to a 1(high) and terminates the Write
6-19
Data command. (Status register 0 also has bits 7 and 6
set to 0 and 1, respectively.)
The Write command operates in much the same manner as the Read command. The following items are the
same, and one should refer to the Read Data command
for details:
Transfer capacity
EN (end of cylinder) flag
ND (no data) flag
Head unload time interval
ID Information when the processor terminates
command
Definition of DTLwhen N = O and when N#O
In the write data mode, data transfers between the processor and FDC, via the data bus, must occur every 27ps
in the FM mode and every 13ps in the MFM mode. If the
time interval between data transfers is longer than this,
the FDC sets the OR (overrun) flag in status register 1
to a 1 (high) and terminates the Write Data command.
(Status register 0 also has bits 7 and 6 set to 0 and 1,
respectively.)
Write Deleted Data
This command is the same as the Write Data command
except a deleted data address mark is written at the beginning of the data field instead of the normal data address mark.
Read Deleted Data
This command is the same as the Read Data command
except that when the FDC detects a data address mark
at the beginning of a data field (and SK= 0 (low)), it will
read all the data in the sector and set the CM flag in status register 2 to a 1 (high), and then terminate the command. If SK = 1, then the FDC skips the sector with the
data address mark and reads the next sector.
Read a Track
This command is similar to the Read Data command except that this is a continuous read operation where the
entire data field from each of the sectors is read. Immedlatelyafter sensing the index hole, the FDC starts reading all data fields on the track as continuous blocks of
data. If the FDC finds an error in the ID or data CRC
check bytes, it continues to read data from the track.
The FDC compares the ID information read from each
sector with the value stored in the IDR and sets the ND
flag of status registerl toal(high)if thereisnocomparison. Multi-track or skip operations are not allowed with
this command.
This command terminates when the number of sectors
read is equal to E a . If the FDC does not find an ID ad6-20
dress mark on the diskette after it senses the index hole
for the second time, it sets the MA (missing address
mark) flag in status registerl t o a l (high)and terminates
the command. (Status register 0 has bits 7 and 6 set to 0
and 1, respectively.)
Read ID
The Read ID command is used to give the present position of the recording head. The FDC stores the values
from the first ID fteld it is able to read. If no proper ID
address mark is found on the diskette before the index
hole is encountered for the second time, then the MA
(missing address mark)flag in status register1is set to a
1 (high), and if no data is found then the ND (No data)
flag is also set in status register 1to a 1(high). The command is then terminated with bits7and 6 in status register 0 set to 0 and 1, respectively. During this command
there is no data transfer between FDC and the CPU except during the result phase.
Format a Track
The Format a Track command allows an entire track to
be formatted. After the index hole is detected, data is
written on the diskette; gaps, address marks, ID fields,
and data fields, all per the IBM System 34 (double density) or System 3740'(single density) format, are recorded. The particular format which will be written is
controlled by the values programmed into N (number of
byteslsector), SC (sectorslcylinder), GPL (gap length),
and D (data pattern) which are supplied by the processor during the command phase. The data field is filled
with the byte of data stored in D. The ID field for each
sector is supplied by the processor; that is, four data requests per sector are made by the FDC for C (cylinder
number), H (head number), R (sector number), and N
(number of byteslsector). This allows the diskette to be
formatted with nonsequential sector numbers, i f
desired.
The processor must send new values for C, H, R, and N
to the pPD765AlpPD7265for each sector on the track. If
FDC is set for the DMA mode, it will issue four DMA requests persector. If it isset forthe interrupt mode, it will
issue four interrupts per sector and the processor must
supply C, H, R, and N loads for each sector. The contents of the R register are incremented by 1 after each
sector is formatted; thus, the R register contains a value
of R when it is read during the result phase. This incrementing and formatting continues for the whole track
until the FDC detects the index hole for the second
time, whereupon it terminates the command.
If a fault signal is received from the FDD at the end of a
write operation, then the FDC sets the EC flag of status
register0 to a 1(high)and terminates the command after
setting bits7and6of statusregisterOtoOand1, respec-
NEC
pPD76bA/7265
tively. Also, the loss of a ready signal at the beginning of
a command execution phase causes bits 7 and 6 of status register0 to be set to 0 and 1, respectively.
Table 7 shows the relationship between N, SC, and GPL
for various sector sizes.
Table 7. Sector Size
Fornut
MWMU
n sc
aPi(1)
o#(z,q
8" Standard Floppy
FM Mode
MFM Model4)
128 Bytes/Seclor
00
1A
07
1B
256
01 OF
OE
2A
512
02
08
1B
3A
1024
03
04
47
8A
2048
04
02
C8
FF
4096
05
01
C8
FF
256
01
1A
OE
36
512
02
OF
16
54
1024
03
08
35
74
2048
04 04
99
FF
4096
05 02
FF
8192
06
01
C8
C8
128Bytes/Sector
00
00
12
10
07
128
09
19
FF
5V4" Minifloppy
FM Mode
MFM Mode(4)
10
256
01 08
18
30
512
02 04
46
87
1024
03 02
C8
FF
2048
256
04
01
12
C8
FF
OA
OC
32
01
256
01
10
20
512
02
08
2A
50
1024
03
04
80
FO
2048
04 02
C8
FF
4096
05
01
C8
FF
Scan Commands
The Scan commands allow data which is being read
from the diskette to be compared against data which is
being supplied from the main system. The FDC compares the data on a byte-by-byte basis and looks for a
sector of data which meets the conditions of
DFDD= Dprocessor, DFDD< Dprocessor, or DFDD>
Dprocessor. The hexidecimal byte of FF either from
memory or from FDD can be used as a mask byte because it always meets the condition of the comparison.
One's complement arithmetic is used for comparison
(FF = largest number, Do = smallest number). After a
whole sector of data is compared, if the conditions are
not met, the sector number is incremented(R + STP
R), and the scan operation iscontinued. The scan operation continues until one of the following conditions occur: the conditions for scan are met (equal, low, or high),
thelast sectoron thetrackisreached(ECTT),ortheterminal count signal is received.
If the conditions for scan are met, then the FDC sets the
SH (scan hit) flag of status register2 to a 1(high)and terminates the Scan command. If the conditions for scan
are not met between the starting sector (as specified by
R) and the last sector on the cylinder (Em,then the
FDC sets the SN (scan not satisfied) flag of status register 2 to a1(high)and terminatesthe Scan command. The
receipt of a terminal count signal from the processor or
DMA controller during the scan operation will cause the
FDC to complete the comparison of the particular byte
which is in processand then to terminatethecommand.
Table 8 shows the status of bits SH and SN under various conditions of Scan.
-
Table8. Scan Conditions
31h" Sony Mlcm Floppydirk
FM Mode
MFM Mode(4)
128ByteslSector
0
OF
07
1B
256
1
09
OE
2A
512
2
05
1B
3A
256
1
OF
OE
36
512
2
09
18
54
1024
3
05
35
74
Note:
(1) Suggested values of GPL in Read or Write commands to avoid
splice point between data field and ID field of contiguous sections.
(2) Suggested values of GPL in format command.
(3) A l l values except sector size are hexidecimal.
(4) In MFM mode FDC cannot perform a ReadlWritelFormat operation
with 128 byteslsector. (N =W).
Scan High or
0
1
DFDO = DPmcessor
Equal
0
0
DFW> Dprocessor
1
0
Dmn<
If the FDC encounters a deleted data address mark on
one of the sectors (and SK = 0), then it regards the sector as the last sector on the cylinder, sets the CM (control mark) flag of status register 2 to a 1 (high) and
terminates the command. If SK=1, the FDC skips the
sector with the deletedaddress mark and reads the next
sector. In the second case (SK = l),
the FDC sets the CM
6-21
(control mark) flag of status register 2 to a 1(high) in orderto show that a deletedsector has been encountered.
When either the STP (contiguous sectors = 01, or alternate sectors=02) sectors are read or the MT (multitrack) is programmed, it is necessary to remember that
the last sector on the track must be read. For example, if
STP=O2, MT=O, the sectors are numbered sequentially 1 through 26 and the Scan command is started at
sector 21,the following will happen: sectors 21,23, and
25 will be read, then the next sector (26) will be skipped
and the index hole will be encountered before the EOT
value of 26 can be read. This will result in an abnormal
termination of the command. If the EOT had been set at
25 or the scanning started at sector 20, then the Scan
command would be completed in a normal manner.
During the Scan command, data is supplied by either
the processor or DMA controller for comparison against
the data read from the diskette. In order to avoid having
the OR (overrun)flag set in status register 1, it is necessary to have the data available in less than 27ps (FM
mode) or 13ps (MFM mode). If an overrun occurs, the
FDC ends the command with bits 7 and 6 of status reg
ister 0 set to 0 and 1, respectively.
Seek
The readlwrite head within the FDD is moved from cylindertocylinder under control of theSeekcommand. FDC
has four independent present cylinder registers for
each drive. They are cleared only after the Recalibrate
command. The FDC compares the PCN (present cylinder number) which is the current head position with the
NCN (new cylinder number),and if there is a difference,
performsthe following operations:
PCN < NCN: Direction signal to FDD set to a 1 (high),
and step pulses are issued. (Step in)
PCN > NCN: Direction signal to FDD set to a 0 (low),
and step pulses are issued. (Step out)
The rate at which step pulses are issued is controlled by
SRT (stepping rate time) in the Specify command. After
each step pulse is issued NCN is compared against
PCN, and when NCN = PCN, the SE (seek end) flag is
set in status register0 to a 1(high), and the command is
terminated. At this point FDC interrupt goes high. Bits
DoB-D~Bin the main status register are set during the
seek operation and are cleared by the Sense Interrupt
Status command.
During the command phase of the seek operation the
FDC is in the FDC busy state, but during the execution
phase it is in the non-busy state. While the FDC is in the
non-busystate, another Seek command may be issued,
and in this manner parallel seek operations may be
done on up to four drives at once. No other command
6-22
can be issued for as long as the FDC is in the process of
sending step pulses to any drive.
If an FDD is in a not ready state at the beginning of the
command execution phase or during the seek operation, then the NR (not ready) flag is set in status register
0 to a 1 (high), and the command is terminated after
bits 7 and 6 of status register 0 are set to 0 and 1,
respectively.
If the time to write three bytes of Seek command exceeds 150ps, the timing between the first two step
pulses may be shorter than set in the Specify command
by as much as 1ms.
Recalibrate
The function of this command is to retract the read/
write head within the FDD to the track 0 position. The
FDCclearsthe contents of the PCN counter and checks
the status of the track 0 signal from the FDD. As long as
the track 0 signal is low, the direction signal remains 0
(low) and step pulses are issued. When the track 0 s i g
nal goes high, the SE(seek end) flag in status register0
is set to a 1(high) and the command is terminated. If the
track 0 signal is still low after 77 step pulses have been
issued, the FDC sets the SE (seek end) and EC (equip
ment check) flags of status register 0 to both 1s (highs)
and terminatesthe command after bits 7 and 6 of status
register0 are set to 0 and 1, respectively.
The ability to do overlapping Recalibrate commands to
multiple FDDs and the loss of the ready signal, as described in the Seek command, also applies to the Recalibrate command. If the diskette has more than 77
tracks, then Recalibrate command should be issued
twice, in order to position the readlwrite head to the
track 0.
Sense Interrupt Status
An interrupt signal is generated by the FDC for one of
the following reasons:
(1) Upon entering the result phase of:
(a) Read Data command
(b) Read a Track command
(c) Read ID command
(d) Read Deleted Data command
(e) Write Data command
(9 Format a Cylinder command
(9) Write Deleted Data command
(h) Scan commands
(2) Ready line of FDD changes state
(3) End of Seek or Recalibrate command
(4) During execution phase in the non-DMA mode
Interruptscaused by reasons 1and 4 above occur during
normal command operations and are easily discernible
by the processor. During an execution phase in non-
NEC
DMA mode, DB5 in the main status register is high.
Upon entering the result phase this bit gets cleared.
Reasons 1 and 4 do not require Sense Jnterrupt Status
commands. The interrupt is cleared by readinglwriting
data to the FDC. Interrupts caused by reasons 2 and 3
above may be uniquely identified with the aid of the
Sense InterruptStatus command. This command, when
issued, resets the Interruptsignal and, via bits5,6, and 7
of status register0, identifies the cause of the interrupt.
See table 9.
Specify
The Specify command sets the initial values for each of
the three internal timers. The HUT (head unload time)
defines the time from the end of the execution phase of
one of the ReadlWrite commands to the head unload
state. This timer is programmablefrom 16 to 240ms in
increments of 16 ms (01= 16 ms, 02 = 32 ms.. .
OFH = 240ms).TheSRT(step rate time)defines the time
interval between adjacent step pulses. This timer is
programmable from 1 to 16ms in increments of l m s
(F = 1ms, E =2 ms, D = 3 ms, etc.). The HLT (head load
time) defines the time between when the head load
signal goes high and the ReadlWrite operation starts.
This timer is programmable from 2 to 254ms in increments of 2ms (01=2ms, 02=4ms, 03=6ms ...
7F = 254 ms).
The time intervals mentioned above are a direct function of the clock (CLK on pin 19). Times indicated above
are for an 8MHz clock; if the clock was reduced to
4 MHz (minifloppy application), then all time intervals
are increasedby a factor of 2.
The choice of a DMA or non-DMA operation is made by
the ND (non-DMA)bit. When this bit is high (ND = 1) the
non-DMA mode is selected, and when ND = 0 the DMA
mode is selected.
Table9. InterruDt Status
0
1
1
Ready line changed state,
either wlarihr
1
0
0
Normal termination of Seek or
Recalibrate command
1
1
0
Abnormal termination of Seek
or Recalibrate command
The Sense Interrupt Status command is used in conjunction with the Seek and Recalibrate commands
which have no result phase. When the disk drive has
reached the desired head position the pPD765Al
pPD7265 will set the interrupt line true. The host CPU
must then issue a Sense Interrupt Status command to
determinetheactualcauseof the interrupt,which could
be seek end or a change in ready status from one of the
drives. A graphic example is shown in figure4.
Flgure 4.
Sense Drive Status
This command may be used by the processorwhenever
it wishes to obtain the status of the FDDs. Status regis-
Seek, Recalibrate, and Sense Interrupt Status
Seek (or Recalibrate) Command
-I-
Senw Intsnupt Status Command-Y
)cCommand P h a M ~ E x e c u t l o Phaw
n
A C o m m a n d Phaw+R.sult
I
INT
I
I
I
- s E
RD
1
WR
DIO
u
RBM
fl
Pha-4
I
I
I
I
I
I
I
I
u
u
u :
u
u
n
t
I
u u
u u
U
JL
JL
n
n
U
u
I
u
n
t
I
t
U
t
n
t
t
6-23
ter 3 contains the drive status information stored internally in FDC registers.
reads status register 0 it will find an 80H, indicating an
Invalidcommand was received.
A Sense InterruptStatus command must be sent after a
seek or recalibrate interrupt, otherwise the FDC will
consider the next command to be an Invalid command.
In some applications the user may wish to use this command as a No-Op command to place the FDC in a
standby or no operation state.
Invalid
If an Invalid command is sent to the FDC (a command
not defined above), then the FDC will terminatethe command after bits 7 and 6 of status register 0 are set to 1
and 0, respectively. No interrupt is generated by the
pPD765AIpPD7265during this condition. Bits 6 and 7
(DIO and RQM) in the main status register are both 1
(high), indicating to the processor that the pPD765AI
pPD7265 is in the result phase and the contents of status register 0 (STO) must be read. When the processor
figure 5.
I
Data Format
Figure 5 shows the data transfer format for thepPD765A
and pPD7265 in various modes.
Data format (Sheet 1 of 2)
pP0765A [FM Model
GAP4a
SYNC
IAM
FF
W
FC
GAP1
26.
FF
SVNC
6.
M
IDAM
FE
tL
~
;I
GAP2
111
FF
DATAAM
FBoiFB
DATA
C
g
m
GAP3
m
GAP4b
1 -
I
*de.
SYNC
6.
W
Fmpe.1 N Tim..
pP07265 [FMMode]
GAP1
161
FF
SYNC
6
.
W
IDAM
C
FE
L
Index
; Ii
GAP?
111
FF
SYNC
6x
W
DATA
DATAAY
FBorF8
m
C
QAP3
GAP4
; m
I
R l p a N Tim.
~ P 0 7 6 5 A[MFM Mode]
I
pPD7265 [MFM Mode]
IDAM
6-24
-1
N nm.
I
NEC
Figure 5.
Data Format (Sheet 2 of 2)
pPD765A
Inaex
Formal
V,,SINC
GAP&
I
IAM
7
I
I
GAP1
ID
[
GAP2
I
DA?A
I
GAP3
I
ID
1-
/
r - - -- - -7
WE
I
pPD7265A
Index
Formal
I
GAP1
I I
ID
GAP2
I
DATA
1
GAP3
I I
ID
GAP2
I
+/
I
D
J
T
V,.SYNC
__
'ION;
Read
WE
-------7
r------
6-25
Power Supply
loOoSL POWER SUPPLIES
(SINGLE AND DUAL INPUT)
lOOOSL 67 WATT SINGLE INPUT POWER SUPPLY
CONTENTS
BLOCK DIAGRAM
THEORY OF OPERATION
TROUBLESHOOTING
PARTS LIST
PCB ART
SCHEMATIC
DC OUTPUT
I
FANOUT
*
+ 12v
+ 12v
INPUT
m
c
'c1
z
z
Y
0
cl
AC 120V
OR 240V
RECTIFIER
FILTER
0
FG
*
SWITCHING
DRIVER
t
240V 0
INTERNAL JUMPER
-12v
o
+ 5v
x
0
t
I
41
-
,-A
OVER VOLTAGE
PROTECTOR
I
DC VOLTAGE
FEED BACK
Theory of Operation
AC Input Circuit
This circuit is composed of an AC Power Switch, a fuse, a line
filter, and an inrush current limiting circuit and rectifying
smoothing circuit. The inrush current limiting circuit controls
the charging current to electrolytic capacitors when power is ON.
The line filter reduces noise that leaks from the power source to
the AC line or that returns from the unit to the power souce; it
satisfies the specifications of noise regulations.
Control Circuit
&
Power Converter Circuit
This circuit is a self oscillation switching system, generally
called an R.C.C. (Ringing Choke Converter). The R.C.C. circuit
does not fix the oscillating frequency. Whenever input voltage
is high or the load becomes light, the oscillating frequency will
be high.
The current through R2 supplies transistor Ql's base, then Q1
turns ON. When transistor Q1 is On, the Q1 current excites the
transformer T1 and voltage rises in the bias coil of Tl(5-6)
which leads transistor Q1 positive bias, then transistor Q1 turns
ON.
When transistor Q1 turns ON, collector current charges the energy
to primary inductance of transformer T1 (1-3). Increasing the
collector current of transistor Q1 to the point of:
I > I .hfe
C = B
Then, transistor Q1 immediately turns OFF.
In a moment,
transformer T1 will have negative voltage which will be supplied
to the secondary circuit through a rectifier. A Short Circuit
Protector is provided to protect transistor Q1 from excess
amounts of current when the secondary circuit becomes shorted.
When transistor Q2 detects the voltage drop at R12, the collector
of 42 shorts the base and emitter of Q1. Then Q1 stops working
so that the circuit protects Q1 from over current.
The over current protector in the -12V line is provided by the
three terminal positive voltage regulator IC1 (built-in current
fold back protection 1 , which protects Q1 against excessive
current from the -12V line.
Start-Up
Load power supply with minimum load as specified i n Table 1.
Bring up power slowly with the Variable Transformer while
monitoring the +5 output with the oscilloscope and DVM. Supply
should start with approximately 40-60 VAC applied, and should
regulate when 90 VAC is reached. If output has reached 5 volts,
do a performance test on operating characteristics, if there is
no output, refer to "NO output" section.
5V Output Voltage D e t e c t i n g C i r c u i t
The c i r c u i t detects t h e c h a n g e of o u t p u t load c u r r e n t compared
w i t h t h e o u t p u t v o l t a g e and AC l i n e i n p u t v o l t a g e , which feeds
b a c k t o t h e c o n t r o l c i r c u i t t h r o u g h a p h o t o c o u p l e r PHCl t o k e e p
t h e o u t p u t v o l t a g e s t a b l e . The P h o t o c o u p l e r i s o l a t e s t h e
primary a n d s e c o n d a r y c i r c u i t s .
Over-Voltage P r o t e c t i o n
When t h e +5 o u t p u t v o l t a g e r i s e s , b e t w e e n 5.8V t o 6.8V, a c o n t r o l
s i g n a l t u r n s o n t h e p h o t o c o u p l e r PHC2 ( P h o t o T h y r i s t o r ) w i t h t h e
c u r r e n t of z e n e r diode ( D l 1 1 a n d s t o p s o s c i l l a t i o n by t u r n i n g o n
Q3, which t u r n s o f f Q 1 i n t h e s w i t c h i n g c i r c u i t .
I n t h e case of s t o p p e d o s c i l l a t i o n , correct t h e c a u s e of t h e
f a i l u r e , a n d r e i n p u t t h e power. The o v e r v o l t a g e p r o t e c t i o n
c i r c u i t w i l l reset a u t o m a t i c a l l y u n d e r good c o n d i t i o n s .
The P h o t o T h y r i s t o r i s o l a t e s t h e p r i m a r y and s e c o n d a r y c i r c u i t s .
Troubleshooting
E q u i p m e n t for T e s t Set-Up
I s o l a t i o n T r a n s f o r m e r ( m i n i m u m of 500 VA r a t i n g )
CAUTION
D a n g e r o u s l y h i g h v o l t a g e s are p r e s e n t i n t h i s p o w e r s u p p l y .
For t h e s a f e t y of t h e i n d i v i d u a l d o i n g t h e t e s t i n g , please
u s e a n i s o l a t i o n t r a n s f o r m e r . The 500 VA r a t i n g is n e e d e d
t o keep t h e AC waveform f r o m b e i n g c l i p p e d off a t t h e
p e a k s . T h e s e power s u p p l i e s h a v e p e a k c h a r g i n g capacitors
a n d draw f u l l power a t t h e p e a k of t h e AC waveform.
0-28OV Variable T r a n s f o r m e r (Variacl- Used t o v a r y i n p u t
voltage.
Recommend 10 amp, 1.4 KVA r a t i n g , minimum.
V o l t m e t e r - Need to m e a s u r e DC v o l t a g e s t o 50 VDC a n d AC
v o l t a g e s t o 200 VAC.
Recommend two d i g i t a l m u l t i m e t e r s .
Oscilloscope- Need x 1 0 and x 1 0 0 p r o b e s .
Load board w i t h c o n n e c t o r s - S e e T a b l e 1 f o r v a l u e s o f
loads r e q u i r e d .
The e n t r y on t h e t a b l e f o r Safe Load Power
is t h e minimum power r a t i n g s f o r t h e l o a d r e s i s t o r s u s e d .
NOTE: B e c a u s e of i t s d e s i g n , t h i s power s u p p l y m u s t h a v e a
load p r e s e n t or damaging o s c i l l a t i o n s may r e s u l t .
Never
t e s t t h e power s u p p l y w i t h o u t a s u i t a b l e l o a d .
Ohmmeter
Set-Up P r o c e d u r e
S e t up as shown i n F i g u r e 1. You w i l l want t o m o n i t o r t h e i n p u t
v o l t a g e a n d t h e o u t p u t v o l t a g e of t h e r e g u l a t e d b u s , w h i c h is t h e
+5 o u t p u t , w i t h D V M ' s .
A l s o m o n i t o r t h e +5 o u t p u t w i t h t h e
The DVM m o n i t o r i n g
o s c i l l o s c o p e u s i n g 500 mv/div s e n s i t i v i t y .
t h e +5 o u t p u t c a n also b e u s e d to c h e c k t h e o t h e r o u t p u t s . S e e
t e x t of "NO o u t p u t " s e c t i o n f o r t h e t e s t p o i n t s w i t h i n t h e power
supply
Visual Inspection
Check power s u p p l y f o r a n y b r o k e n , b u r n e d , or o b v i o u s l y damaged
components. V i s u a l l y check f u s e , i f any q u e s t i o n check w i t h
ohmmeter.
No o u t p u t
1.
Check f u s e :
I f f u s e is blown, replace it b u t do n o t a p p l y power u n t i l t h e
c a u s e of t h e f a i l u r e is f o u n d .
2.
P r e l i m i n a r y Check on Major P r i m a r y Components:
Check diode b r i d g e ( I l l ) , p o w e r t r a n s i s t o r ( Q l )a,n d d r i v e
t r a n s i s t o r (42,431 f o r s h o r t e d j u n c t i o n s .
I f a n y component
is f o u n d s h o r t e d , replace i t .
3.
P r e l i m i n a r y C h e c k on Major S e c o n d a r y Components:
U s i n g a n ohmmeter from a n o u t p u t t h a t is common t o e a c h
o u t p u t a n d w i t h o u t p u t loads d i s c o n n e c t e d , c h e c k f o r s h o r t e d
r e c t i f i e r s or c a p a c i t o r s .
4.
Check Over V o l t a g e Protector:
Read t h e o u t p u t v o l t a g e w i t h a DVM a t t h e +5 o u t p u t t e r m i n a l s
by i n c r e a s i n g t h e i n p u t v o l t a g e f r o m OV. O u t p u t v o l t a g e w i l l
a p p e a r a t some i n p u t v o l t a g e and t h e n go down t o OV a g a i n .
Check t h e D i o d e D 1 1 or P h o t o C o u p l e r (PHCZ)
.
5.
Check Q1Waveforms :
Read waveform of
probe.
Q1
Collector w i t h oscilloscope a t x 1 0 0
F i g u r e 2 is Q1Collector n o r m a l waveform.
F i g u r e 3 is
Q 1 Base
n o r m a l waveform.
F i g u r e 4 is t h e waveforms when s h o r t e d c i r c u i t s of t h e
s e c o n d a r y p a r t s as l i s t e d i n T a b l e 2 . Check l i s t e d p a r t s
a c c o r d i n g t o t h e waveform.
C o l l e c t o r Waveforms
I
S h o r t e d S e c o n d a r y Components
I
Table 2 .
L i s t of S h o r t e d C i r c u i t s
SOV/DIV
5p S/DIV
Q1 Collector Waveforms (Input 90 VAC Minimum Load)
0.5V/DIV
5p S/DIV
Q 1 Base Waveforms (rnput 90 VAC Minimum Load)
MINLOAD I LOAD R
OUTPUT
v
1.25A
4 ohms
20 w
7.0 A
0.7 ohms
60 W
v
-12 v
0.15A
80ohms
5w
2.4A
5ohms
5OW
0
0
0
0.25A
48ohms
5W
+5
+12
Table 1 Load Board Values ( 6 7 w a t t )
.ISOLATlON
OUTPUT LOADS
VARIAC
-
1
AC
L
TRANSFORMER
POWER
SUPPLY
Figure 1 T e s t Setup
+5v
+12v
'
Waveforms
Power Converter Circuit
Vin
Y
Collector Voltage Waveform
Collector Current Waveform
The i n p u t and o u t p u t v o l t a g e are r e p r e s e n t e d by t h e
following equations:
Vo = n x Vf
V o : Output v o l t a g e
n : Turn r a t i o of t h e t r a n s f o r m e r T 1
vf : Collector Voltage a t t u r n - o f f t i m e
Vin x Ton = vf x Toff
V i n : Input v o l t a g e
Ton : Turn-on t i m e of t r a n s i s t o r
t i m e of t r a n s i s t o r
T o f f : Turn-off
-
Q1 Collector Waveforms
Shorted Secondary Components (Input 90 VAC)
PARTS LIST FDR SWITCHING POWER SUPPLY UNIT
PART NO. 8790081
QTY RS
Description
Symbol
part
No.
Mfr's Pau-t No.
CAPACITORS
c1
Film
O.luF
25OVAC
1
XE-104
c2
0.22uF
25OVAC
1
-224
C3/4/11
Film
Ceramic
2200pF
4OOVAC
3
c5
Ceramic
lOOOOpF
4OOVAC
1
C6
Electrolytic
680uF
200WV
1
DE7100F222MVAl-KC
o r CSl3-sZG&222HXAS
DE?l50FZ103pVAl-KC
or CSl7-RGAlO3ZYAS
cETsw2D681
o r 20O~SS6Bo
C7/8/9
Film
0 . 0 4 7 ~ ~50v
3
c10
Film
O.luF
5OV
(0.1-0.22uF)
1
c12
Film
0.22uF
Cl3
Ceramic
1 5 0 0 ~ ~WV
1
1
C15/25
Electrolytic
luF
50wv
2
cEusMlH010
C16
Electrolytic
cEusMlE222
Electrolytic
Electrolytic lOOOuF
E l e c t r o l y t i c 4700uF
Electrolytic 2200uF
25wv
25wv
1
c17/23/24
C18
C19/20/21
2200uF
470uF
3
CEUSM1E%?l
16WV
1
cEusHlc102
l0WV
3
cEusm472
1
cEusMu222
c22
250V
l0WV
5OFzN73K
o r AMZF473K5OV
5 0 ~ ~ 1 0 4 ~
or ~~zlznW5ov
(Adjust 104K-224K)
250MW224K
~~1210~152~2~
o r CK45-B3DDl52KYAR
CONNECXIRS
SKl
Connector, 2 conductors Input
1
SK2
Connector, 2 conductors FBn-out
s~3-1
Connector, 10 conductors Output
SK3-2
Connector, 4 conductors Output
1
1
1
DIODES
D1
Silicon, Stack
4OOV
4A
1
s4vB40
o r RB401)
o r DBAME
Silicon
Silicon
5v
4QOmW
lA
2
HZ5B3
M / I ~
D3/4/5
600V
3
F'I-06
CI
a/?
Silicon
l0OV
200pDA
2
D8
Silicon, Stack
200V
5A
1
Vlgc
d5446
or l S 9 9
D~LCA~O
o r 5CH2SM
D9
QTY RS Part No.
Deecrlption
Symbol
Silicon, Stack 4OV
1
mse,
1
Mk's Part No.
FUSE
n
250v
2
h s e Clip
HEATSINK
HS1
HS2
1
H e a t s i n k , for Q l
Heatsink, for D ~ / D ~ / Q ~ / I c ~ 1
40-08440-01
4P-D2-0180
INDUCTORS
Ll
L2
Choke Coil
8mH
Choke Coil
4.3uH
I C , Regulator
37V
15011~
12V
0.5A
1
"0-9161-1
1
o r "0-9161
PSG-156
1
TLA31CLPB
INTECRATED
IC1
IC2
I C , Regulator
or uA43UWC
1
L78Ml2
or NJM78Ml2
IC3
I C , Regulator
36V
30d
1
35V
50d
1
4OOV
150d
1
M5236L
PHOTO COUPLERS
PHC-1
PHC-2
Photo Coupler
Photo Coupler
~~~5u-1
o r PC817
TLP91C
or S22MDl
PRINTED CIRCUIT BOARD
PC1
Printed C i r c u i t Board
1050~
XPC
1
2P-P1-0177
1.6A
1
117-080Jb5202
o r 8D-11
RESISTORS
R1
Thermistor
8
o r D4FFL8RoP
R2/3
Carbon
R4
Metal-oxide
R5/6/19/20
Metal-oxide
lOOK
27
(10-56)
27K
1/2w
2
RD50PlOOKohmsJ
o r RD50SlOOKohmsJ
2w
1
RSF2B27ohrnsJ
(Adjust 10-560hm)
2w
4
RSF2B27KohmsJ
QTY RS Part No.
Description
Symbol
Mfr's Part No.
2w
2
RSF2BWOohmsJ
560
(330-750)
1/4U
1
RD25P5600hplsJ
o r RI)25S5600hmJ
(Adjust 330-75Ooh.s)
Carbon
270
(180-470)
1/4W
1
RD25P270oWJ
or RD25S27OohmsJ
(Adjust 180-47Oohms)
Rll
Carbon
47
R12
Cement
0.27
m3
Carbon
R14
Hetal-oxide
R7/8
R9
Carbon
RlO
470
RD25P47oh.1~
J
o r RD25Sb7ohmsJ
5w
MPC71 0.27ohmsK
2%
1/4W
Carbon
39
1/4W
n5
Carbon
180
1/4W
Rl6
Carbon
100
1/4W
RD25P27KohmsJ
or RD25S27KohmsJ
RD25P390hmsJ
o r RD25S390hmsJ
RD25P180ohmsJ
o r RD25S180ohplsJ
RD25PlOOohmsJ
o r RD25SlOOohplsJ
Rl7/18/21/24
1
Carbon
2.w
1/4W
RD25P2.WohmJ
o r RD25S2.ZKohmsJ
R22/27
Carbon
220
1/4W
RD25P220ohmJ
o r RD25S2200hrsJ
E3
Carbon
18K
1/4W
E5
Carbon
1K
1/4W
RD25PlKohmsJ
o r RD25SlKohmsJ
R26
Carbon
1%
1/4W
RD25P15KohmsJ
o r RD25S15KohmsJ
R28
Carbon
1K
1/6W
RD16PlKohms.J
o r RD16SlKoWJ
VR1/2
Variable
2K
0.5~
V6EK-PV (15) 202b
o r H0615-222B
RD25P18Koh.sJ
o r ~~25slSK0h.s~
TRANSFORPER
n
To-4342
Transformer
TRANSISTORS
c1
Ransistor
4OOV
12A
2SC2833
o r 2SC2938
w 3
hansistor
5OV
2A
2801207
o r 2SC2655
Qr,
'hamistor
60V
5A
2SA1441
o r 2SB1019
Power Supply PCB
-
Silkscreen
Power Supply PCB
- Component
Side
OND
1
QND
AC IN
3
-12V
sK1
+12
a
cd
Nc
*l2V
QND
*SV
+sv
*sv
OND
QND
OH)
A I
Dl 1
D2
RIF
PHC2
model no.
8790085
R16
1
,
:
IZFA
sK2
lOOoSL 67 WATT DUAL INPUT POWER SUPPLY
lOOOSL 67 WATT DUAL INPUT POWER SUPPLY
CONTENTS
OPERATING CHARACTERISTICS
BLOCK DIAGRAM
THEORY OF OPERATION
TROUBLESHOOTING
PARTS LIST
PCB ART
SCHEMATIC
Operating Voltage Range
MINIMUM
TYPICAL
90
198
120
240
47
Line Frequency
MAXIMUM
UNITS
VAC
63
HZ
5.15
.
-10 .80
V
1 2 60
V
Output Voltages
Vol
4.05
v02
11.40
-13.20
v03
5.00
.
-120 .00
1 2 00
V
output Loads
Io1
I02
1.25
7.0
A
0.15
2.4
A
103
0
0.25
A
Over Current P r o t e c t i o n
Current L i m i t ICLl
14.0
A
ICL2
4.8
A
ICL~
1.0
A
6.8
V
Vol
50
mV P-P
v02
100
mV P-P
150
mV P-P
Over Voltage P r o t e c t i o n
Crowbar
5.8
Output Noise
V03
-
Efficiency
63
65
Holdup Time
Ail1 Load a t Nominal Line
mSec
16
.
I n s u l a t i o n Resistance
Input t o Output
7
1000
n
Input t o Ground
7
1000
M ohms
ohms
Isolation
Input t o Ground
1.25
KVAC
Input
3.75
KVAC
t.0
Output
DC OUTPUT
I
’
INPUT
AC 120V
m
aC
FG
SWLTCHING
z
Lc
m
RECTIFIER
c1
0
c1
x
DC VOLTAGE
FEED BACK
OVER VOLTAGE
L
1
‘ I
J
FAN OUT
Theory of Operation
AC Input Circuit
This circuit is composed of an AC Power Switch, a fuse, a line
filter, and an inrush current limiting circuit and rectifying
smoothing circuit. The inrush current limiting circuit controls
the charging current to electrolytic capacitors when power is ON.
The line filter reduces noise that leaks from the power source to
the AC line or that returns from the unit to the power souce; it
satisfies the specifications of noise regulations.
Control Circuit
&
Power Converter Circuit
This circuit is a self oscillation switching system, generally
called an R.C.C. (Ringing Choke Converter). The R.C.C. circuit
does not fix the oscillating frequency. Whenever input voltage
is high or the load becomes light, the oscillating frequency will
be high.
The current through R4 and R5 supplies transistor Ql's base, then
Q1 turns ON. When transistor Ql is On, the Q1 current excites
the transformer T1 and voltage rises in the bias coil of Tl(2-3)
which leads transistor Q1 positive bias, then transistor Q1 turns
ON.
When transistor Q1 turns ON, collector current charges the energy
Increasing the
to primary inductance of transformer T1 ( 4 - 6 ) .
collector current of transistor Q1 to the point of:
I > I .hfe
C = B
Then, transistor Ql immediately turns OFF.
In a moment,
transformer T1 will have negative voltage which will be supplied
to the secondary circuit through a rectifier. A Short Circuit
Protector is provided to protect transistor Q1 from excess
amounts of current when the secondary circuit becomes shorted.
When transistor 9 2 detects the voltage drop at R13, the collector
of 42 shorts the base and emitter of Q1. Then Q1 stops working
so that the circuit protects Q1 from over current.
The over current protector in the - 1 2 ~line is provided by the
three terminal positive voltage regulators IC2, IC3 (built-in
current fold back protection 1 , which protects Q1 against
excessive current from the -12V line.
Start-Up
Load power supply with minimum load as specified in Table 1.
Check up on the voltage selector jumper and don't apply over
voltage. Bring up power slowly with the Variable Transformer
while monitoring the +S output with the oscilloscope and DVM.
Supply should start with approximately 40-60/80-120 VAC applied,
and should regulate when 90/180 VAC is reached. If output has
reached 5 volts, do a performance test on operating
characteristics, if there is no output, refer to "NO output"
section.
5V Output Voltage Detecting Circuit
The c i r c u i t detects t h e c h a n g e of o u t p u t load c u r r e n t compared
w i t h t h e o u t p u t v o l t a g e and AC l i n e i n p u t v o l t a g e , which f e e d s
b a c k t o t h e c o n t r o l c i r c u i t t h r o u g h a p h o t o c o u p l e r PHCl t o k e e p
t h e o u t p u t v o l t a g e stable. The P h o t o c o u p l e r i s o l a t e s t h e
primary and secondary c i r c u i t s .
Over-Voltage Protection
When t h e +5 o u t p u t v o l t a g e rises, between 5.8V t o 6.8V, a c o n t r o l
s i g n a l t u r n s on t h e p h o t o c o u p l e r PHC2 ( P h o t o T h y r i s t o r ) w i t h t h e
c u r r e n t of z e n e r diode (Dl11 a n d stops o s c i l l a t i o n by t u r n i n g o n
4 3 , which t u r n s o f f Q1 i n t h e s w i t c h i n g c i r c u i t .
I n t h e case of s t o p p e d o s c i l l a t i o n , correct t h e c a u s e of t h e
f a i l u r e , a n d r e i n p u t t h e power. T h e o v e r v o l t a g e p r o t e c t i o n
c i r c u i t w i l l reset a u t o m a t i c a l l y u n d e r good c o n d i t i o n s .
The P h o t o T h y r i s t o r i s o l a t e s t h e p r i m a r y and s e c o n d a r y c i r c u i t s .
Troubleshooting
Equipment for Test Set-Up
Isolation Transformer(minimum of 500 VA rating)
CAUTION
Dangerously high voltages are present in this power supply.
For the safety of the individual doing the testing, please
use an isolation transformer. The 500 VA rating is needed
to keep the AC waveform from being clipped off at the
peaks. These power supplies have peak charging capacitors
and draw full power at the peak of the AC waveform.
0-28OV Variable Transformer (Variacl- Used to vary input
voltage. Recommend 5 amp, 1.4 KVA rating, minimum.
Voltmeter- Need to measure DC voltages to 50 VDC and AC
voltages to 300 VAC. Recommend two digital multimeters.
Oscilloscope- Need x 10 and x 100 probes.
Load board with connectors- See Table 1 for values of
loads required. The entry on the table for Safe Load Power
is the minimum power ratings for the load resistors used.
NOTE: Because of its design, this power supply must have a
load present or damaging =oscillations may result. Never
test the power supply without a suitable l o a d .
Ohmmeter
Set-Up Procedure
Set up as shown in Figure 1. You will want to monitor the input
voltage and the output voltage of the regulated bus, which is the
+5 output, with DVM's. Also monitor the +5 output with the
oscilloscope using 500 mv/div sensitivity. The DVM monitoring
the +5 output can also be used to check the other outputs. See
text of "NO output" section for the test points within the power
supply
Visual Inspection
Check power supply for any broken, burned, or obviously damaged
components. Visually check fuse, if any question check with
ohmmeter.
No Output
1.
Check fuse:
If fuse is blown, replace it but do not apply power until the
cause of the failure is found.
2.
Preliminary Check on Major Primary Components:
Check diode bridge (Dl), power transistor (Ql), and drive
transistors (42,931 for shorted junctions. If any component
is found shorted, replace it.
3.
Preliminary Check on Major Secondary Components:
Using an ohmmeter from an output that is common to each
output and with output loads disconnected, check for shorted
rectifiers or capacitors.
4.
Check Over Voltage Protector:
Read the output voltage with a DVM at the +5 output terminals
by increasing the input voltage from OV. Output voltage will
appear at some input voltage and then go down to OV again.
Check the Diode D11 or Photo Coupler (PHC2).
5.
Check Q1 Waveforms:
Read waveform of Q1 Collector with oscilloscope at x 100
probe.
Figure 2 is Q1 Collector normal waveform.
Figure 3 is Q1 Base normal waveform.
Figure 4 is the waveforms when shorted circuits of the
secondary parts as listed in Table 2. Check listed parts
according to the waveform.
6.
Collector Waveforms
Shorted Secondary Components
Figure 4
D8, D9, C17, C18, C20, C21, C22, C23,
Check Resistor (R26)
If R26 is open, check D10, C24 ,and IC2.
100V/DIV
Sp s/DIV
Ql Collector Waveforms (Input 90 VAC Minimum Load)
0. SV/DIV
5p S/DIV
01 Base Waveforms (Input 90 VAC Minimum Load)
MINLOAD
LOAD R
LOAFEWER
MAX
LOAD
LOAD R
v
1.25A
4ohms
20 W
7.0 A
0.7 ohms
60 W
+12V
0.15A
80ohms
5W
2.4A
5ohms
50 W
-12 v
0
0
0
0.25A
48ohms
5W
OUTPUT
+5
LOAF&R
Table 1 Load Board Values (67 watt)
ISOLATION
1
VARIAC
~
TRANSFORMER
AC
++5v
5v
+12v
-12v
POWER
SUPPLY
COMM
Figure 1 Test Setup
-
OUTPUT LOADS
D
Waveforms
Power Converter Circuit
'
Ton 'Toff
'
Collector Voltage Waveform
Collector Current Waveform
The input and output voltage are represented by the
following equations:
Vo = n x vf
Vo : Output voltage
n : Turn ratio of the transformer T 1
Vf : Collector Voltage at turn-off time
Vin x Ton = Vf x Toff
vin : Input voltage
Ton : Turn-on time of transistor
Toff: Turn-off time of transistor
100V/DIV
5p s/DIV
-
Q1 Collector Waveforms
Shorted Secondary Components (Input 90 VAC)
PARTS LIST FOR SWITCHING FOYER SUPPLY UNIT
PART NO. 8790084
Symbol
QTY RS P a r t NO.
Description
Mfr.6 P a r t
NO.
CAPACITORS
c2
Film
0.22uF
MOVAC
1
c3/4
Ceramic
4700pF
MOVAC
2
XE-224
DE7150&72MVAl.-KC
o r Cs17-E2cA4?2MT.~S
c5
Ceramic
lOOOOpF
MOVAC
1
DE7150FZ103PVAl-KC
or CSl7-FZCAl03ZYAS
C6/7
Electrolytic
330uF
200WV
2
CETSW2D331
o r 200LPSS330
c8/9.'10/15
film
0.047uF
5OV
4
5OF20473K
o r AMZ&73KgOV
c11
film
0. l u F
(0.1-0.22uF)
5OV
1
50 F2D104K
o r AMFl04K5OV
c12
Ceramic
470pF
2K V
1
DE0907R471KW
or CK45-BJDD47lKYAR
Cl3
Film
0. OluF
630V
1
C14
Ceramic
680pF
2KV
1
C F921L2J103K
o r MDDZ2J103K
DE1010R681K2K
or CK45-B3DD681KYAR
C16/26
Electrolytic
luF
50WV
2
CEUSMlHOlO
C17
Electrolytic
2200uF
25wv
1
CEUSKtE222
C10/24/25
Electrolytic
470uF
25wv
3
CEUSPU471
C19
Electrolytic
lOOOuF
16WV
1
CEUSMlC102
C20/21/22
Electrolytic
4700uF
l0WV
3
CEUSKlA472
c23
Electrolytic
2200uF
l0WV
1
CEUSIQA222
CONNECTORS
SK1
Connector, 2 conductors Input
1
SK2
Connector, 2 conductors b n - o u t
1
5277-0a
5045-02F
s~3-1
Connector, 10 conductors Output
1
5277-10A
s~3-2
Connector, 4 conductors Output
1
Pin Terminal, Voltage S e l e c t o r
2
5273-WA
RT-OlN-2.3A
Jumping Connector
1
4P-M3-0017
DIODES
1
S3WB60
5V
3A
400mW
2
HZ5B3
600V
1A
2
D1
S i l i c o n , Stack
600v
D2/11
S i l i c o n , Zener
D3/10
Silicon
f1-06
or VlgC
D4/5
Silicon
%/7/13
Silicon
800V
1A
2
FI-08
o r RU2B
l0OV
200mA
3
05446
or is954
Symbol
QTY
Description
ES
Part No.
Mfr's P a r t No,
D8
Silicon, Stack
200V
5A
1
D~LCA~O
o r gCH2SH
D9
Silicon, Stack
40V
1OA
1
DlOSC4H
o r lOCSO4SH
Fuse
250V
3A
1
2
FUSE
Fl
Fuse Clip
HEATSINK
HS1
Heatsink, f o r Q l
HS2
Heatsink, f o r D8/D9/w/Ic2
1
1
40-06440-01
4P-D2-0180
INDUCrORS
w 2
Choke Coil
L3
Choke Coil
0.5mH
2
8mH
1
To-9175
To-9161
I&
4.3uH
1
PSC-156
Choke Coil
INTEGRATED CIRCUITS
IC1
I C , Regulator
37V
150d
1
TL431CLPB
o r uA43UWC
IC2
I C , Regulator
12V
0.5A
1
L78Ml2
or NJM78Ml2
IC3
I C , Regulator
36V
3Oa
1
M5236L
1
Tu732
o r PClll
PHOTO WUPLER
PHCl
Photo Coupler
55V
60d
PHC2
Photo Coupler
600V
1 5 0 ~ ~1
TLP741J
PRINTED CIRCUIT BOARD
Printed C i r c u i t Board
1050~
XPC
1
2P-P1-0178
Rl
"hermister
16
1.2A
1
117-160-45201
o r 16D-13
o r WFF'L160P
R2/3/4/5
Carbon
lOOK
1/2w
4
RD5OPlOOKohmsJ
o r RD5OSlOOKohmsJ
R6
Metal-oxide
2w
1
RSFZB47ohmsJ
PC1
RESISTOAS
47
(15-68)
(Adj u s t 1 5 - 6 8 0 h ~ )
QTY RS Part No. Mfr's Part No.
Description
Symbol
R7/29
R8/9
Metal-oxlde
Metal-oxide
lOOK
100
RlO
Carbon
560
(330-680)
Rl1
Carbon
330
(220-560)
R12
Carbon
Rl3
0.56
R14
Cement
Carbon
27K
m5
Carbon
R16
Carbon
2u
2w
1/4U
RSFZBlOOKohmsJ
RSF2BlOOohmsJ
RD25P560ohmsJ
or RD25S5600hmsJ
(Adjust 330-68Oohms)
1/4W
1
RD25P330ohmsJ
or RD25S330ohmsJ
(Adjust 220-5600h~~)
1/4W
1
RD25P470hmsJ
or RD25S47ohmsJ
5w
1/4W
1
1
MPC71 0.560hmsK
RD25P27Kohms
or RD25S27KohnsJ
39
1/4W
1
RD25P39ohmsJ
or RD25S390hmsJ
180
1/4W
1
47
RD25P180ohmsJ
or RD25S180ohmsJ
R17
Carbon
100
1/4U
1
Rl8/19/22
Carbon
2.2K
1/4W
3
R20/27
Carbon
1K
1/4U
2
R21/23
Carbon
220
1/4U
2
R24
Carbon
18K
1/4U
1
R26
R28
hsing
Carbon
1
1/4W
1/4w
1
1
vRl/2
Variable
0.5W
2
1%
2K
TRANSlQRMER
T1
Transformer
TRANSISTORS
ql
Transistor
RD25PlOOohmsJ
or RD25S100ohmsJ
RD2p2.2KohmsJ
or RD25S2.2KohmsJ
RD25PlKohmsJ
or RD25SlKohmsJ
RD25P22OohmsJ
or RD25S220ohmsJ
RD25P18KohmsJ
or RD25S18KohmsJ
REZ5SlohmsJ
RD25P15KohmsJ
or RD25SljKohrnsJ
V6EK-PV( 15)202B
or H0615-222B
To-4341
800V
6A
2sc3460
or 2SC3680
w 3
Transistor
50v
a
Q1,
Transistor
60v
5A
2SD1207
or 2SC2655
2SA1441
or 2SBlOl9
Power Supply PCB
-
Silkscreen
.
I
Power Supply PCB
-
Component Side
Nc
*sv
'l 9
@fa
1
R27
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c
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*5v
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OM
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1
model no.
8790084
t12V FAN
Keyboard
FUJITSU KEYBOARD
ASSEMBLY # N860-4703-T
1.0 GENERAL
The keyboard is a direct, plug-conpatible replacent for the
Enhanced Keyboard for the I B M PC, XT, and AT personal ccorputer,
No software modification or special interface is needed by the
user
.
2.0 SCOPE
This specification describes the functional, mechanical,
electrical, environmental, and reliability characteristics of
the FUJITSU N860-4703-T Keyboard assembly.
The keyboard is encoded in such a way as to produce a unique
output code for each key that is pressed and/or released. The
connumication with the host corrputer is a synchronous serial
link. The Key Layout, Switch Encoding and Serial Carnrmnication
are a l l carpatible with the I B M PC, XT and AT.
3.0 MECHANICAL SPECIFICATION
3.1 Key Layout, Legends, and Colors
Figure 1 shows keytop layout, appropriate legends and keytop
colors. The keys are n&red
fran left to right starting with
the spacebar row (Raw A) and ending with the function key row
(ROW F).
1
-5F-
-aFIGURE 1
3.2.1 mal Travel:
0.150",
+/-
0.020'' (3.8, +/-0.5m)
3.2.2 FDRCE: A l l keyswitches s h a l l u t i l i z e a 2.0 ounce (+/- 0.9
oz) operating force. This is acconplished using both a rubber
keyswitch rmnbrane and springs.
3.2.3 RREAKOVEB EEEDBACK: The keyswitches u t i l i z e a tactile
feedback t o assure t h e operator t h a t t h e key has been f u l l y
pressed
.
4.0 FUNCTIONAL REQUIREMENTS
4.1
WES
The keyboard generates a unique Hex scan code d r each keyswitch
t h a t is pressed (mike code) and released (break code). For t h e
AT M e , t h e break code is t h e saxe as the make code preceded by
"F'"' Hex. Exarrple: The make code for the "ESC" key is 76 Hex
and t h e break code is t w o bytes, FO 76 Hex. For the XT Mode,
t h e break code is 80 Hex, plus t h e make code. Exarrple: The make
code f o r t h e llESC1l
key is 01 Hex and t h e break code is 81 Hex.
The k e y s w i t c h - t o - s c a n d e (make and break codes) assignmnts,
Standard ASCII Codes, and m e n d e d ASCII Codes are listed on t h e
follawing pages.
3
KEYBOARD SCAN CODES
Key Key
# Descript.
1
2
3
4
5
6
7
8
Esc
F1
F2
F3
F4
F5
F6
F7
9 F a
10
11
12
13
14
15
16
17
18
€9
F10
F11
F12
Print Scrn
Scroll Lock
Pause Break
-or\
!or 1
AT Mode
Make
Break
Code
Code
F076
76
FOO5
05
06
F006
04
F004
FOOC
oc
F003
03
FOOB
OB
F083
83
FOOA
OA
FOO1
01
FOO9
09
78
F078
07
€7007
E07C
EOM)7C
7E
F07E
E11477 ElFDl4F977
OE
FOOE
16
F016
XT Mode
Make
Standard ASCII
(ScancodelASCII code)
Break
u
01
3B
3c
3D
3E
3F
40
41
42
43
81
BB
BC
RD
BE
BF
co
c1
OllB
3B00
3COO
3D00
3EOO
3FOO
4000
4100
4200
4300
4400
c2
c3
44
c4
----57
D7
D8
58
E02AE037 WB7EOAA Note!
46
c6
Notef
EllD45
E19DC5
Note3
2B
AB
2960
02
82
0231
--e--
011B
5400
5500
5600
5700
5800
5900
SA00
5B00
5C00
5D00
------e--
Note:
Notef
Note3
297E
0221
Table 1
011B
5EOO
SF00
6000
6100
6200
6300
6400
6500
6600
6700
---------
7200
------.
Note'
-----
-----
Extended ASCII
(Scancode/ASCII code)
Shift
Ctrl
OllB
OllB
OllB
3B00
5E00
5400
3COO
5F00
5500
3D00
6000
5600
3E00
5700
6100
3FOO
5800
6200
4000
5900
6300
4100
SA00
6400
4200
5 BOO
6500
SCOO
4300
6600
4400
6700
SDOO
8500
8700
8900
8600
8800
8A00
Note'
Note'
7200
----Note2
Note2
Note3
Note3
Note4
----6000
7E00
----0231
0221
Alt
0100
6800
6900
6A00
6B00
6C00
6D00
6E00
6f00
7000
7100
8D00
8C00
-----
n0te2
n0te3
2900
7800
KEYBOARD SCAN CODES
Key Key
# Descript.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
@or2
# or3
$ or4
%or5
“or6
&or7
* or8
( or9
) or0
or? or =
Backspace
Insert
Home
PgUp
NumLock
i
*
-
AT Mode
Make
Break
Code
Code
FOlE
1E
F026
26
FO25
25
F02E
2E
F036
36
F03D
3D
3E
F03E
F046
46
F045
45
F04E
4E
F055
55
F066
66
EOF070
E070
EOF06C
E06C
EOF07D
E07D
F077
77
EOF04A
E04A
F07C
7c
F07B
7B
XT Mode
Make
Break
Standard ASCII
(Scancode/ASCII code)
Shift
Ctrl
Alt
03
83
0332
0340
0300
0423
04
84
0433
05M
----05
85
0534
0625
_-___
06
86
0635
07
87
0736
075E
071E
08%
_-___
08
88
0837
09
89
0938
092A
----OA
8A
OA39
OA28
----OB
8B
OB34
OB29
----oc
8C
OC2D OC5F
OClF
OD
8D
OD3D OD2B ----OE
8E
OE08
OEO8
OE7F
5200
E02AE052 EOD2EOAA 5200
E02AE047 EOC7EOAA 4700
4700
7700
E02AE049 EOC9EOAA 4900
4900
8400
~~~~5
c5
Note’
45
352F
----E035
EBB5
352F
372A
----37
B7
372A
4A
CA
4A2D 4A2D -----
u
_____
_____
_____
Extended ASCII
(Scancode/ASCII code)
Shift
Ctrl
0340
0332
0423
0433
0534
0524
0635
0625
0736
075E
0837
0826
0938
092A
OA39
OA28
OB34
OB29
OC2D
OC5F
OD3D
OD2B
OE08
OE08
52E0
52EO
47E0
47EO
49E0
49EO
Note’
Note’
EO2F
E02F
372A
372A
4A2D
4A2D
Ak
7900
7a00
7B00
7c00
7D00
7e00
7F00
8000
8100
8200
8300
OEOO
A200
9700
9900
Note’
A400
3700
4A00
KEYBOARD SCAN CODES
Key
#
Key
Descript.
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
Tab
Qorq
W orw
Eore
Rorr
Tort
Y ory
U or u
I or i
Ooro
Porp
i or[
1 or1
I or\
Delete
End
PageDown
7orHome
8
9orPage Up
AT Mode
Make
Break
Code
Co&
OD
FOOD
15
F015
1D
FOlD
FO24
24
2D
F02D
2c
F02C
F035
35
F03C
3c
F043
43
44
4D
54
5B
5D
E071
E069
E07A
6C
75
7D
Fo44
F04D
DO54
F05B
F05D
EOF071
EOF069
EOF07A
FO6C
F075
FO7D
XTMode
Make
Break
Standard ASCII
(Scancode/ASCII code)
Shift
Qrl
All
OF00
OF
8F
OF90
90
1071
1051
1011
10
11
91
1177
1157
1117
12
92
1265
1245
1205
13
93
1372
1352
1312
1454
1414
14
94
1474
15
95
1579
1559
1519
1655
1615
16
96
1675
1749
1709
17
97
1769
184F
180F
18
98
186F
1950
1910
99
1970
19
1A
9A
1A5B 1A7B lAlB
1B
9R
1B5D 1R7D lBlD
2B7C 2B1C
2B
AB
2B5C
5300
----E02AE053 EOD3EOAA 5300
4F00
7500
E02AE04F EOCFEOAA 4FOO
5100
7600
E02AE051 EODlEOAA 5100
4737
7700
47
c7
4700
4838
---48
c8
4800
49
c9
4900
4939
8400
u
_____
Extended ASCII
(Scancode/ASCII code)
Shift
Ctrl
OF00
9400
OF09
1051
1011
1071
1157
1117
1177
1245
1205
1265
1352
1372
1312
1454
1414
1474
1559
1519
1579
1655
1615
1675
1749
1709
1769
184F
180F
186F
1950
1970
1910
1A7B
lAlB
1A5B
lB7D
lBlD
1B5D
2B7C
2B1C
2B5C
53Eo
93EO
53EO
4FEO
75EO
4FE0
51EO
76EO
51EO
4737
7700
4700
4838
8D00
4800
4939
8400
4900
41t
A500
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
1A00
1B00
2B00
A300
9F00
A100
n0te6
Not e6
Note6
KEYBOARD SCAN CODES
Key
#
58
59
60
61
62
63
4
Key
Descript.
+
64
65
66
67
68
CapsLock
A or a
Sors
D ord
Forf
Gorg
Horh
J orj
Kork
Lor1
69
: or ;
70
71
72
73
74
" or '
Enter
4
5
6
AT Mode
Make
Break
Code
Code
79
F079
58
F058
1c
FOlC
1B
FOlB
F023
23
2R
F02B
34
F034
F033
33
F03B
3B
F042
42
4B
F04B
4c
F04C
F052
52
F05A
5A
F06B
6B
F073
73
F074
74
XT Mode
Make
Break
u
4E
3A
1E
1F
20
21
22
23
24
25
26
27
28
1c
4B
4c
4D
CE
BA
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
9c
CB
cc
CD
Standard ASCII
(Scancode/ASCI I code)
Shift
Ctrl
Alt
------4 E 2 7 4E2$
Note
---Note
Note7
1E61
1E41
lEol
lE00
1F73
1FS3
1F13
lF00
2064
2044
2004
2000
2166
2146
2106
2100
2267
2247
2207
2200
2368
2348
2308
2300
246A
244A
240A
2400
256B
254B
250B
2500
266C
264c
26oc
2600
273A
---273B
---2822
---2827
---1COD
1COD lCOA
4B00
4834
7300
Note6
-_--_ 4c35 --Note6
4D00
4D36
7400
Note'
____
Extended ASCII
(Scancode/ASCII code)
Shift
Ctrl
4E29
9000
4E29
---Note
Note
1E61
1m1
lEOl
1F73
1F53
1F13
2064
2044
2004
2166
2146
2106
2267
2247
2207
2368
2348
2308
246A
244A
240A
256B
254B
250B
266C
264c
26oc
---273B
273A
---2827
2822
lCOD
1COD
lCOA
4BOO
4834
7300
400
4c35
8FQO
4D36
4D00
7400
4E00
n0te7
lEOO
1f00
2000
2100
2200
2300
2400
2500
2600
2700
2800
lCOO
n0te6
n0te6
Note6
KEYBOARD SCAN CODES
Key
00
#
Key
Descript.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Left Shift
Zorz
Xorx
Corc
Vorv
Borb
N or n
Morm
< or,
> or.
?or/
Right Shift
Up Arrow
1 or End
2
3 or Pg Dn
Left Ctrl
Left Alt
Space
AT Mode
Make
Break
Code
Code
12
F012
1A
FO 1A
F022
22
21
F021
F02A
2A
F032
32
31
F031
F03A
3A
F041
41
49
F049
4A
F04A
59
F059
E075
EOF075
69
F069
72
FO72
F07A
7A
14
F014
FOll
11
F029
29
XT Mode
Make
Break
Standard ASCII
(Scancode/ASCII code)
Shift
Ctrl
All
AA
Note8 Note'
Note'
2A
Note8
2c
AC
2C7A
2C5A 2C1A
2c00
2D
AD
2D78
2D58 2D18
2000
2E
AE
2E63
2E43
2E03
2E00
2F
AF
2F76
2F56
2F16
2FOO
30
Bo
3062
3042
3002
3000
31
B1
316E
314E
310E
3100
32
B2
326D
324D
320D
3200
--------333C
33
R3
332C
--------343E
34
B4
3428
----353F
----35
B5
352F
36
B6
Note'
Note'
Note8
Note8
E02AE048 EOC8EOAA 4800
4800
----4F
CF
4FOO
4F31
7500
Note6
50
DO
5000
5032
---Note6
51
D1
5100
5133
7600
Note6
1D
9D
Note9 Note9 Note9
Note9
Note"
Note"
Note"
B8
38
Note"
39
B9
3920
3920
3920
3920
u
----
-
&tended ASCII
(Sca ncode/ASCII code)
NormShift
CtrlAll
Note'
Note'
Note'
2C5A
2C7A
2C1A
2c00
2D78
2D58
2D18
2000
2E43
2E63
2E03
2E00
2F56
2F76
2F16
2f00
3062
3042
3002
3000
314E
316E
310E
3100
326D
324D
320D
3200
----332C
333c
3300
----343E
342E
3400
352F
353F
3500
Note8
Note8
Note'
48Eo
48Eo
8de0
9800
4FoO
4F31
7500
n0te6
5000
5032
9100
n0te6
5100
5133
7600
n0te6
Note'
Note'
n0te9
Note"
Note"
Note"
Note"
3920
3920
3920
3920
n0te8
-----
n0te9
n0te8
KEYBOARD SCAN CODES
Key
#
Key
Descript.
95
96
97
98
99
100
101
102
Right Alt
Right Ctrl
LeftArrow
DownArrow
Right Arrow
OorIns
.orDel
Enter
AT Mode
Make
Break
u
EO11
EO14
E06B
E072
E074
70
71
E05A
EOF011
EOFo14
EOFo6B
EOF072
EOF074
F070
F071
EOFOSA
X T Mode
Make
Break
u
Standard ASCII
(Scancode/ASCII code)
Shift
Ctrl
ALt
Note;
Note;
Note;
Note910
EO38
EOB8
EOID
E02AE04B
E02AEOSO
E024E04D
52
53
EOlC
EO9D
Note
EOCBEOAA 4B00
EODOEOAA 5000
EOCDEOAA 4D00
D2
5200
D3
5300
EO9C
lCOD
Note
4B00
5000
4000
5230
532E
1COD
Note
7300
Note
7400
----
-----------
lCOA
-----
_____
Note
____
----
6
Extended ASCII
(Scancode/ASCII code)
ALt
Shift
Ctrl
Note;
Note;
Note;
Note910
Note
4BE0
5OEO
4DE0
5200
5300
EOOD
Note
4BEO
5OEo
4DEO
523H
532E
EOOD
Note
73E0
91EO
74EO
9200
9300
EOOA
Note
9B00
AOOO
9D00,
Note
--*--
A600
NOTES
Note1 -1NT
Note2 -the
Note3 -the
Note4 -1NT
Note5 -the
Note6 -ALT
Note7 -the
Note8 -hold
Note9 -hold
Notelo--hold
OSH is invoked and a screen dump is performed
scroll lock active bit is toggled
pause state is initiated
1BH is invoked
numlock active bit is toggled
num pad generates raw ascii code of typed number
caps lock active bit is toggled
shift lock active until key is released
control shift active until key is released
alternate shift active until key is released
5.0.1 W I C A T I C N MCDE 1 (PC/XT M e )
The keyboard commicates with t h e h o s t ccp[puter
using a
synchroncus serial protocol a t approximately 9600BPS. One start
b i t , e i g h t data b i t s , no s t o p b i t , and no p a r i t y are used t o
make up t h e n i n e b i t data word. When no c c m u n i c a t i o n s are i n
progress, t h e keyboard holds the data l i n e low and t h e clock
l i n e high.
Before s t a r t i n g a transmission, t h e keyboard lowers t h e clock
l i n e as a R e q u e s t To Send (RTS). The state of t h e dasa l i n e is
then checked. If t h e h o s t system is holding t h e &ta l i n e low,
transmissions are disabled. The keyboard w i l l r e t a i n the keyccde
for t h e pressed key i n its buffer u n t i l t h e clock and data l i n e s
r e t u r n to t h e idle state. The keyboard then r e m s scanning t h e
keyboard matrix u n t i l t r a n s n i s s i o n s are enabled.
When transmissions are enabled, 100 to 250 microseconds a f t e r
t h e keyboard d r i v e s t h e clock l i n e low, t h e keyboard t r a n s m i t s
its data i n t h e previously described format. Data is valid
during t h e tire t h e clock l i n e is high and f o r a minimum of 10
microseconds a f t e r t h e f a l l i n g edge of t h e clock l i n e . See
Figure 2 f o r a timing diagram.
< KEYBOARD DATA OUTPUT-XT MODE >
.______
DATA
,
T1
T2
T3
T4
/ I
START
I
DO
D1
D2
>
J
D7
( (
-
; 100 25011s (CHECKING TIME OF DATA OUTPUT READY OR PROHIBITION)
; 104p+20%
; 10ysMIN.
; 10pMIN.
FIGURE 2
11
5.0.2 COMWNICATION MCDE 2 (AT MCDE)
The keyboard camunicates with the host ccmputer using a
synchronous serial protocol at approximately 96OOBPS. One s t a r t
bit, eight data bits, odd parity, and one stop bit form the
eleven bit data wxd. T h i s conmmication is bi-directional, with
the keyboard clocking all data transfers. When no comnunications
are in progress, the data and clock lines are high, indicating
an idle state.
< KEYBOARD DATA OUTPUT-AT MODE >
Figure 3A
DATA
START
DO
T1
T2
T3
T4
< KEYBOARD DATA INPUT-AT MODE >
T5 ;
T6 ;
D
DI
-:'
; 104ys 220%
; 20ysMIN.
; 20ysMIN.
; 35p.s ?20%
Figure 38
60 ys MIN. (WAITING TIME FOR HOST DATA OUTPUT)
5ysMIN.
FIGURE 3
12
Before s t a r t i n g a transmission, t h e keyboard checks t h e s t a t u s
of t h e clock and data l i n e s . Transmissions are disabled i f t h e
clock l i n e is l o w and t h e code f o r t h e pressed key is held i n
t h e keyboard buffer u n t i l transmissions are enabled. I f t h e
clock l i n e is high and the data l i n e is low, t h e h o s t system is
sending a R e q u e s t To Send (RTS), and t h e code f o r t h e pressed
key is stored i n t h e buffer.
When transmissions are enabled and no RTS is detected f r m t h e
host system, both clock and data l i n e w i l l be high. T k keyboard
starts a transmission by sending a low start b i t , followed by
t h e rest of t h e data word. Data is v a l i d 20 microseconds minimum
prior t o t h e f a l l i n g edge of t h e clock. See Figure 3 f o r timing
diagram.
During t h e transmission of a data word, t h e keyboard
p e r i o d i c a l l y checks t h e state of t h e clock l i n e . I f t h e clock
l i n e is low during t h e s e checks p r i o r to t h e r i s i n g edge of t h e
p a r i t y b i t , a d a t a c o l l i s i o n occurs. When a data c o l l i s i o n
occurs, t h e keyboard s t o p s transmitting, r e t u r n s t h e code f o r
t h e pressed key t o t h e keyboard buffer, and prepares to respond
t o a c t i o n s requested by t h e host system.
5.1 COMMANDS FROM THE KEYBOARD TO THE HOST SYSTEM
Keyboard Buffer Overrun
- AT and XT &des
This buffer can store up t o s i x t e e n codes f o r pressed keys. When
t h i s buffer is f u l l and t h e seventeenth code is received, t h i s
code is replaced by an Overrun Code. The following c h a r t shows
t h e Overrun Codes f o r each d e .
Codes received after t h i s code are lost u n t i l t h e keyboard
clears additional space i n t h e keyboard buffer.
13
Self Test Passed
- AA H e x
AT and XT Modes
The keyboard issues this cornnand upon successful c a p l e t i o n of
t h e keyboard s e l f test. The s e l f test c o n s i s t s of t h e following.
XT MODE
1. &mry is cleared.
2. Keyboard buffer is cleared.
3. ROM checksum is read and canpared.
4. RAM is tested.
5. Self test c a p l e t i o n code is output.
6 . AA Hex is output t o i n d i c a t e successful s e l f test.
7. Fc Hex is output to i n d i c a t e a d e f e c t i n t h e s e l f test.
AT MODE
1. ROM checksum is read and carpared.
2. RAM is tested.
ex is
output t o i n d i c a t e successful self test.
4. Fc H e x is output t o i n d i c a t e a d e f e c t i n t h e s e l f test.
3. AA
This s e l f test is i n i t i a t e d by t h e h o s t system reset (ctrl, at,
Delete) or by Pwe.r-on Reset. Upon successful c a r p l e t i o n of t h e
Self Test during PaverR e s e t , t h e keyboard is set t o XT mude
i f t h e keyboard detects a l o w level on t h e data l i n e for more
than 10 microseconds a f t e r 5 microseconds fran t h e f a l l i n g edge
of the clock l i n e . I f t h i s condition is not met, t h e keyboard is
placed i n t h e AT Mode, and Typgnatic Rate and Delay are set to
t h e following defaults:
Typematic Rate 10.9 cps
Delay 500 milliseconds
EHO
- EE H e x
AT and XT Modes
The Echo C a m m d (EE H e x ) is s e n t i n response t o an Echo camnand
f r a n t h e host system instead of t h e normal Acknowledge (PIJK) f o r
d i a g n o s t i c purposes.
Acknuwledge
- FA Hex
AT Mode
The keyboard sends an Acknowledge (FA H e x ) i n response t o a
v a l i d carmand f r a n the host system, with t h e exceptions of t h e
R e s e n d and Who cara~nds.
14
Resend
- FE Hex
AT and XT Modes
The keyboard issues a Resend (FE Hex) in response to inputs
which have parity errors, framing errors, or invalid data
received fran the host system.
KEYEOARD BUFFER OVERFUN
- AT and XT Modes
When the 16-character keyboard buffer receives the 17th
character, an overflow condition occurs. This condition is
ccmmnicated to the host system by transmitting the Keyboard
buffer Overrun (FF Hex for XT Mode, 00 Hex for AT M e ) to the
host system.
Prior to sending CQmnands to the keyboard, the host system must
first check to see if the keyboard is sending data. If the
keyboard is transmitting, and the data is past the parity bit,
the host system must accept the data prior to initiating its own
transmission.
If the keyboard's data has not yet reached the tenth clock pulse
(Parity Bit), or is not transmitting data, the host system
a s s m s control by lowering the clock line for a minimum of 60
microseconds, then releasing the clock line after clanping the
data line low to indicate a start bit, The keyboard will respond
with an RTS within 5 microseconds by clocking the start bit into
the keyboard. The keyboard continues to clock data as shown in
the timing diagram (Figure 3B) The host system must ensure that
the data is valid prior to the rising edge and after the falling
edge of the keyboard clock pulse.
.
After the parity bit, the host system should raise the data line
to indicate a stop bit. The keyboard checks for a logical high
stop bit, then clanps the data line low prior to clock in the
stop bit, This signals the host system that the keyboard
received the data correctly (Acknawledge). If the host system
has not raised the data line to indicate a stop bit, a framing
error results and the keyboard continues to clock data until the
data line is raised by the host system. Upon receiving either a
framing or parity error, the keyboard issues a RESEM) to the
host system.
All cxmnands fran the host system require a response franthe
keyboard. The keybard will respond to these comnands within 20
microseconds.
15
The following ccmnmds may be s e n t t o t h e keyboard a t any t i n e ,
follaving t h e protocol described for t h e AT M e . These caminan&
are valid only i n the AT M e . During the reset ccnrpnand, the
keyboard w i l l not respond within 20 microseconds as described
above
.
Upon receiving t h i s carmand, t h e keyboard transmits an
Acknowledge t o t h e host system. The keyboard then waits f o r t h e
host system t o accept t h e Acknuwledge response. The host system
w i l l accept t h e Acknuwledge by r a i s i n g t h e clock and data l i n e s
f o r a mininun of 500 microseconds.
The keyboard then executes the s e l f test routine similar to t h e
Pckler-a~ R e s e t , and is placed i n its d e f a u l t state.
Upon receiving this carmand, t h e keyboard w i l l t r a n s n i t t h e last
byte of data s e n t t o t h e host system.
SEX' DEFAULT
- F6 Hex
This camand resets the keyboard t o t h e Paver-Up d e f a u l t state.
The keyboard responds with an Acknowledge, clears t h e output
buffer, sets t h e scanset t o AT Mule, sets t h e d e f a u l t typenatic
rate and delay, and continues to scan t h e matrix.
DEFAULT DISABLE:
- F5 Hex
T h i s ccpnmand is similar to the Set Default comnand, except t h e
keyboard stops scanning the matrix and w a i t s f o r f u r t h e r
i n s t r u c t i o n s t o be s e n t by t h e host system.
ENABLE
- F4 Hex
Upon receipt of this ccnrmand the keyboard responds with an
Acknowledge, clears t h e output buffer, and starts scanning t h e
matrix.
16
SET TYPEMATIC RATE/bELw
- F3 Hex
T h i s camand c o n s i s t s of one ccmnnand byte and one paramter
byte. The keyboard Acknowledges t h e conmand byte, stops scanning
t h e matrix, and waits for t h e parameter byte. Upon r e c e i v i n g t h e
parameter byte, t h e keyboard sends an Acknowledge, sets t h e
typematic rate and d e l a y as i n d i c a t e d i n Table 2, and continues
scanning t h e matrix.
I f another ccpnmand is received i n s t e a d of t h e paranreter byte,
t h e set typematic rate/delay f u n c t i o n ends w i t h no change to t h e
e x i s t i n g rate or d e l a y parameters. The new ccpnnand is processed
and t h e keyboard continues scanning t h e matrix,
The parameter byte c o n s i s t s of an e i g h t - b i t word w i t h b i t 7
(mst s i g n i f i c a n t b i t ) always being set, B i t s 0-4 set t h e
typenatic rate and b i t s 5-6 set t h e d e l a y ,
1 0
7 6
1 0 1 0 1 1 Paramter Byte
5 4 3 2 1 0 BitNunber
The above exanple shuws t h e d e f a u l t 10.9
500 microsecond delay. B i t s 0-4 (010111)
of 10.9 cps s h a m on Table 2 ii and b i t s
t h e 500 microsecond d e l a y shown i n Table
cps typematic rate and
correspond to t h e rate
5-6 (01) correspond to
2 i.
See Table 2 for Typematic Rate/Delay values other than t h e
default settings,
17
i 1 Delay
Delay
Bit
ms
65
00
250
0 1
500
10
750
1000
ii 1 Rate
1
4
3
Y
1
0
10
0
0
0
0 1 30.0
IO
0
0
0
1 1 26.7
10
0
0
1 0 1
1I
1
24.0
1
0
0
0
0
7.5
1
0
0
0
1
1
1
6.7
1 0 c ) l O
6.0
1
z
o
o
1
1
5.5
1
0
1
0
0
5.0
1
0
1
1
1
4.0
1
1
0
0
0
3.7
1
1
0
0
1
3.3
1
1
0
1
0
3.0
1
1
0
1
1
2.7
p+-q-y
10
0
0
1
1 1 21.8
0
0
1
1
0
10
0
1
1
11 16.0
10
1
0
0
01
15.0
0
1
1
0
0
10.0
0
1
1
0
1
9.2
0
1
1
1
0
8.6
0
1
1
1
1
8.0
1
1
TABLE 2
18
EICHO
- FE Hex
This camnand is provided f o r diagnostic purposes. The keyboard
s h a l l respond with EX Hex, instead of Z!cknowledge, and continue
scanning t h e matrix.
SE2/RESGT STATUS INDICATORS
- ED H e x
This ccnrmand c o n s i s t s of one camand byte and one paramter
byte. The keyboard Acknowledges t h e CarpMnd byte, stops scanning
t h e matrix, and waits for t h e p a r a m t e r byte. Upon receiving t h e
paramter byte, the keyboard sends an Acknowledge, sets t h e
s t a t u s indicators, and starts scanning t h e matrix.
If another camand is received instead of t h e parameter byte,
t h e keyboard disregards t h e Set/Reset S t a t u s Indicators ccnnmnd
without changing t h e present s t a t u s of t h e i n d i c a t o r s , processes
t h e new comnand, and starts scanning t h e matrix.
The parameter byte is an e i g h t - b i t word w i t h b i t s 3-7 always set
t o low. B i t 0 is the Scroll Lock Indicator, b i t 1 is t h e Num
Lock Indicator, and b i t 2 is t h e Caps Lock Indicator. A high i n
each individual b i t i n d i c a t e s t h a t Indicator is a c t i v e and t h e
i n d i c a t o r l a q should be on.
0 0 0 0 0 0 1 0 PARAMETERBYTE
7 6 5 4 3 2 1 0 BITNUMBER
The above exanple shows t h e power-on d e f a u l t of t h e Tan* 3000
M;. B i t 1 is high indicating Num Lock is a c t i v e and t h e Num Lock
indicator lanp is on.
This ccpnmand causes t h e keyboard t o r e t u r n two i d e n t i f i c a t i o n
bytes AB83 Hex. The keyboard responds with an Acknowledge t o t h e
c
d and stops scanning t h e matrix. The keyboard then
t r a n s n i t s t h e keyboard ID AB83 H e x and r e s u m s scanning t h e
matrix.
19
sET/REIu) SCAN SET
- FO
HeX
This camand is used t o select one of three Scan Sets or to tell
t h e host system which Scan Set is c u r r e n t l y being used. T h i s
canaMnd c o n s i s t s of a cumand byte and a paraneter byte. Upon
receiving this camand, t h e keyboard sends an Acknowledge t o t h e
h o s t system and waits f o r t h e parameter byte. When the keyboard
receives the paramter byte, it responds with an Acknmledge.
Aparamter byte of 00 H e x w i l l cause t h e keyboard t o transmit
t h e Hex value f o r t h e Scan Set c u r r e n t l y i n use. A paramter
byte of 01 H e x selects t h e Scan Set 1 (XT Scan Codes), 02 Hex
selects Scan Set 2 (Default AT Scan Codes) , and 03 Hex selects
Scan Set 3 (Special AT Scan Codes -- See Table 3 for Scan Codes
and Default Key State Information). The keyboard r e m s
scanning t h e matrix.
20
KEY DESCRIPTION
Esc
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
Fl2
Print E r n
Scroll Sack
Pause or Break
1
2
3
4
5
6
7
8
9
0
MAKE CCDE
08
07
OF
17
1F
27
2F
37
3F
47
4F
56
5E
57
5F
62
OE
16
IE
26
25
2E
36
3D
3E
46
45
-
4E
Backspace
Insert cursor pad
~ a n ec u r s o r pad
Page up cursor pad
Num Lock
/ number pad
* number pad
- number pad
Tab
55
66
67
6E
6F
76
77
7E
84
OD
15
-
9
W
lD
e
24
2D
r
t
Y
2c
35
:
3c
0
43
44
P
4D
[
I
54
5B
PRJ3AK CCDE
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
08
07
OF
17
1F
27
2F
37
3F
47
4F
56
5E
57
5F
62
OE
16
FO
FO
FO
FO
FO
26
25
2E
36
3D
3E
46
45
4E
55
66
67
6E
6F
76
77
7E
84
OD
15
1D
24
2D
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
Fo
Fo
1E
DEFAULT KEY STATE
W e Only
W e Only
W e Only
W e Qlly
W e Only
m e Only
W e Only
Make Cnly
m e Only
W e Only
W e Only
Make Only
W e Cnly
W e Cnly
W e OaiLy
Make Only
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Typematic
Nematic
Nematic
Typematic
Nematic
-tic
mematic
Make
W e
W e
m e
W e
Make
Make
m e
Cnly
oily
Only
m y
Only
Qlly
Only
Cnly
2c
-tic
Typematic
Typematic
Typematic
mematic
Nematic
35
Typematic
3c
Typematic
'rypematic
Typematic
Typematic
Typematic
43
44
4D
54
5B
21
-tic
\
5c
Delete cursor pad
64
65
6D
6C
75
7D
7c
14
H m
CuTSoI:
Page
UP cursor pad
pad
7 number pad
8 number pad
9 number pad
+ number pad
Caps Lock
a
IC
k
1B
23
2B
34
33
3B
42
1
4B
:
t
4c
S
d
f
g
h
j
Enter
4 number pad
5nmberpad
6rwnberpad
Left Shift
z
X
C
V
b
n
m
I
Right S h i f t
up Arrow cursor pad
1 number pad
2 number pad
3 nurnber pad
Enter number pad
Left C t r l
Left A l t
spacebar
Right A l t
Right C t r l
L e f t Arrw cursor
Dawn Arrw
Right Arrw
Ins number pad
Del number pad
Fo
FO
Fo
Fo
FO
FO
Fo
5c
64
65
6D
6C
75
7D
Fo 7c
Fo
Fo
FO
FO
FO
FO
FO
I%
FO
FO
14
1c
1B
23
2B
34
33
3B
42
4B
4c
52
5A
6B
73
74
12
Typematic
Typematic
M e Only
W e only
M e only
M e cnly
Make only
W e Only
Me/Break
W t i c
-tic
Typematic
!&permtic
Typematic
Typematic
lrLpematic
Typematic
[email protected]
Typematic
Typematic
mematic
M e Only
52
SA
6B
73
74
12
Fo
Fo
Fo
FO
Fo
Fo
Fo
lA
Ffl 1 A
22
21
2A
32
31
3A
41
49
59
63
69
72
7A
79
11
19
29
39
58
61
60
6A
70
71
Fo 22
Fo 21
-tic
Typematic
Typematic
Make only
Make Only
We/Break
2A
wematic
Fo 32
FO 31
Typematic
E'O 3A
'Qpematic
mematic
FO
Fo
Fo
FO
Fo
FO
F'O
FO
Fo
Fo
FQ
Fo
Fo
Fo
FO
Fo
Fo
Fo
41
49
59
63
69
72
7A
79
11
19
29
39
58
61
60
6A
70
71
22
mematic
mematic
We/&eak
Typematic
M e only
Make only
W e Only
W e only
We/Break
Me/Break
mematic
W e Qlly
Make cxlly
Typematic
Typematic
-tic
W e Only
Make Only
SET ALL KEYS
- TYPEMATIC - F7 H a
These comnands a f f e c t Scan Set 3 only, but may be s e n t using any
Scan Set. The keyboard responds with an Acknowledge, clears t h e
output buffer , sets a l l keys t o t h e function requested by t h e
carmand, and continues scanning t h e matrix i f it was previously
enabled.
SET SINGLe KEY
SET SINGLE
- TYPEMATIC - FB Hex
m - MAKE
ONLY
-- FD Hex
These c-ds
consist of a comMnd byte and a parameter byte.
he keyboard responds t o t h e ComMnd byte with an Acknmledge and
waits f o r t h e parameter byte. The parameter byte is t h e scan code
f r a n scan set 3 f o r t h e key t o be changed. upon receiving t h e
paramter byte, the keyboard sets t h e selected key to t h e
function selected by t h e cannand byte, and continues to scan t h e
matrix i f it was previously enabled. These camrands a f f e c t only
Scan Set 3 operation, but may be s e n t using any Scan Set.
5.3 KEY ROILOVER
The keyboard incorporates N-Key Rollover i n software to avoid
loss of keystroke data during high speed entry. N-Key Rollover is
defined as a l l keys pressed and released w i l l be output i n t h e
proper sequence. Haknever, when t h e keyboard detects more than
four keys pressed during a scan of t h e matrix, t h e keyboard does
not uutput t h e keycodes u n t i l one or more of t h e keys are
released. If t h e released key was not properly detected as a
pressed key, an error condition occurs and t h e keyboard issues an
buffer overrun code to t h e host system.
23
5.4 AUTOREPEAT
The --on
default condition W i l l cause the last key pressed to
repeat at 10.9 characters-per-second after a 500 millisecond
delay. This may be changed by the system when the keyboard is
using the AT Canrmnications Wde.
5.5
-
The keyboard is capable of storing 16 scan codes in a first in/
first out (FIFO)circular buffer. When the buffer overfluws, the
last code is replaced by a Hex 00, in AT W e and a Hex FF, in XT
Mode,
5.6 !?X'ATUS INDICATORS
T h r e e LED Status Indicators are provided: Num Lock, Caps Lock,
and Scroll Lock,
T h e s e indicators are located in the keytop of each respective
key. The keyboard will power up with a l l indicators OFF, except
when the host system (such as the [email protected] 3000 NL) sets them to a.
The interface consists of two bi-directional lines, clock and
data, which are controlled by 74Ls125 equivalent buffers. The
keyboard side is terminated by 2200 Ohm resistors. All voltage
levels are ?TL catpatible and the keyboard drivers are capable of
sinking 20 m~ minimum including the current sourced by the pullup
resistors on the keyboard,
The connector is a 5-pin DIN connector. Connections are shown in
the follming table.
Table 4
PIN #
SIGNAL
CLocu
1
2
3
4
5
DATA
No C0NNM;rrION
IQGIC GFaJND
+5 VOLTS Dc
24
6.2 CHASSIS
GR(xTND
chassis ground is isolated fran logic grand.
6.3 POWER REIQuIREMENI);s
The keyboard requires 5 Volts DC, +/-5%, at 500 millianps (-1.
WEBATING................O
NON-OPERATING............-20
to 50 degrees C
to 60 degrees C
7.2 RELATIVE HUMIDITY
20% to 90% non-condensing
7.3 SHOCK
-rating
and non-aperating
............10G
11 mS duration
7.4 VIBRATICN
-rating
and non-operating
55 HZ
............0.3
mn anplitude 10 to
8.0 RELIABILITY
8.1 SWITCH LIFE
Switch life of the keyboard is a minimum of 20 million cycles.
25
MEMBRANE
I
r-i
I
L
N07C
1IEY8rJAFtD UNIT ASSt
<PROPOSAL
>
-
I
I
I
3
I
I
4
Buffer
I
1
I
2
1
1
1
I
I
I
I
I
I
I
I
1
I
5
6
Clock
5
61.2 FDXA-4006.5
X140
x2 0
XI30
X6
9
1
A00
2
10
4
3
5
6
A12
7
8
BOO I311
11
AOI C~Z'BOO'
12
B01 B02 B03 B04 B05 B06 BO7 BO8
14
FOO F02 F03 F04 F05 F06 FO7 F 0 8
15
E O O E 0 1 I302 E 0 3 E 0 4 E 0 5 E 0 6 E 0 7
16
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7
17
CO1 C 0 2 C03 C 0 4 C 0 5 C06 C 0 7 C 0 8
20
Dl0 F09 F10 Fl1 F12 F13 F15 F16
21
E08 E09 El0 Ell El2 El3 D O 8 DO9
23
El5 El6 F 1 4 COO A09 El7 B20 E l 8
24
D l 1 D l 2 D l 3 D l 7 D l 8 D l 9 E l 9 E20
25
C09 C10 C11 C12 C17 C18 C19 D20
26
B09 B10 A05 A17 A19 B17 B18 B19
27
A14 A15 A16 B15 Dl4 Dl5 Dl6 El4
0
X8 0
XlOO
XI20
X5
0.
X9
0
XllO
Xl
0
x3
0
X4 0
x7
0
xo
0
vcco
L3 0
L, 2 0
18
19
I
tt
Scrol 1
1-
22
,q
N
Num
I
19
CHI
1
2
3
OOP
OV
3
‘CC
ov
+ 5 ‘1
CN 1
x
c El 3
l9
:
0
L
2
3
4
5
0
5
1
0
:
0
3 9’
38
37
l5
2
35
16
‘ I
9
35
I
34
33
32
5
2 4
25
26
L O
13
‘{14
21
20
6
10
0
0
3s
00
0 1
02
0 3
04
LOCK
PI1
PIG
ATA
Q
05
06
e 1
1
0 1
23
2 4
2.5
26
P12
2 1
1s
30
P l l
L2
L3
PLE
vcc
‘34
PL3
YO
1
2
c s v
3
4
5
5
’20
‘Y 1
U
dG
’ 2 L [M 1 1
’22 [no511
n.
tu
n.
tu
2
2
~
>ND
1
I
2
I
3
I
4
1
I
I
2
3
I
4
Port3
Port 3 is an &bit quai-bidirectional VO pon It .Ita
contains the interrupt. timer. saria~port and Ri5 and
WR pins that am used various options.
output latch comsponding to a special function mbe programmed to a one (1) for mat function to
PIN DESCRlPTlON
operate. Port 3 can ink/source
:zit
ground potenti.
"cc
*5V power supply during operaticn. programming
and verification.
Port 0
port 0 is an Ebit open drain bidirectional 1 1 0 port.
It is also the multip)a*ed brrorder address and data
bus when using extern4 memory. It is used for data
input .nd output during progunming and verificatiohPOCtOMrinkharrCw o r n r e
Port1
Port 1 is an Ebit quai-bibireaimal I10 port. It is
urc6 for the loworder rddrca byte during programming and verification. Port 1 un sinlrh0Urc.e one
load.
m
Port2
-
Port 2 is an Ebit quasi-bidirutiod Ix)port It rtro
emits the highorder8 bitsoladOmss*ha
external memory. It is usedforthehiphadcrrddrass;
and the control signals during pmgrrmming and
mification. port 2 can sin-rce
one
m.
m
one TlL load. The
special functions are assign& to the pins of
3.
as follows:
-RXO/data (P3.0). %rial port's receiver data input
(asynchronous) or data inputloutput (synchroWS).
-lXD/cloCk (P3.1). Serial port's transmitter data
outpul (asynchronous)or clock output (synchmnous).
-INTO (P3.2). Interrupt 0 input or gate control input
for counter 0.
--INT1 (~3.3). Interrupt 1 input or gate control
input for counter 1.
-lU (P3.4).Input to counter 0.
-11 (P3.5).Input to counter 1.
WR (P3.6). The write control signal latches the
data byte from Port 0 into the External Data
Memory.
(P3.7).The mad control signalenables External
Data Memory to Port 0.
-
--m
RSTNPD
A low to high transition 00 this pin (at approximately
3V) resets the 8051. If VPD is held within its spec
(approximately 4V). while VCC drops below spec.
Vpo will provide standby power to the RAM. When
V p g is low. the RAM'S current is drawn from Vcc.
A small internal resistor permits poweron reset
using only a capacitor connected to Vcc.
ALwPROG
Provides Address Latch Enable output used for
latching the address into external memory during
normal operation. R
e the program pulse
input during EPROM programming.
PSEN
The Program Store EnrMc output is a control signal
that enades the external Program Memory to the
bus during normal tcccn operations.
=DO
When held at a TIL high level. the 8051 executes
instructions from the internal ROMlEPROM when
the PC is less than 4096. When held at a l T L low
level. the 8051 fetches all instuctions from external
Program Memory. The pin also receives the 21V
EPROM programmingsupply voltage.
XTALl
Input to the oscillatoh high gain amplifier. A crystal
or external source can be used.
XTAU
Output from the oscillator's amplifier. Requiredwhen
a cryrtal is used.
r* r I
*O*l I n s o
IOU 1YIlV
1.00U 11111)
-
)ATE
DOCUMENT CONTROL SECTION
I
0
I
0
m
I
D
NOTE
1. C A P A C I T O R S A N D R E S O N A T O R
<X1>
T O BE B E N T
AS
A B O V E DRAWING A F T E R MOUNTED.
C A P A C I T O R <C6> T O B E N O T BENT.
2. C O N N E C T O R S
<CNl.CNZ.CN3
>
TO B E N O T FLOATED.
3. J U M P E R W I R E 52 TO BE N O T MOUNTED.
4.
J U M P E R W I R E I S 30 P O S I T I O N S < C O N T A I N J 1 >
5. C O M P O N E N T S H E I G H T I S LESS T H A N
r
m
I
0
7mm-
c)
I
m
I
000
000
N86D-4700-RIOI/OI
HANDA
Disk Drive
TEAC F D - 5 5 B R / F R / G R
MINI FLEXIBLE DISK DRIVE
MAINTENANCE P R W U - X
TABLE OF CONTENTS
Title
Page
SECTION 2 THEORY OF OPERATION
2-1
CONSTRUCTION AND FUNCTION
.........................................
200
........................................
201
..........................................
.............................................
2-1-1
G e n e r a l B l o c k Diagram
201
2-1-2
Mechanical S e c t i o n
202
2-2
.............................................
Read W r i t e C i r c u i t .............................................
Mode s e l e c t o r ................................................
CIRCUIT DESCRIPTIONS
2-2-1
2-2-1-1
2-2-1-4
.................................................
Write c i r c u i t ................................................
Low v o l t a g e s e n s o r ...........................................
2-2-1-5
F u n c t i o n a n d o p e r a t i n g waveform of
2-2-1-2
2-2-1-3
Read c i r c u i t
207
207
209
211
213
215
.............. 216
224
2-2-2
C o n t r o l C i r c u i t ................................................
2-2-2-1
S t r a p c i r c u i t ................................................
226
2-2-2-2
F r o n t LED c o n t r o l c i r c u i t ....................................
227
2-2-2-3
Head load c o n t r o l c i r c u i t ....................................
228
2-2-2-4
Write/erase c o n t r o l c i r c u i t ..................................
231
2-2-2-5
Motor o n gate ................................................
233
234
2-2-2-6
Ready d e t e c t o r ...............................................
2-2-2-7
S t e p p i n g m o t o r c o n t r o l c i r c u i t ...............................
237
241
2-2-2-8
T r a c k c o u n t e r ................................................
2-2-2-9
RD/INDEX g a t e ................................................
242
2-2-2-10
Door-close c i r c u i t ..........................................
243
2-2-2-11
O t h e r t e r m i n a l s a n d f u n c t i o n o f c o n t r o l LSI ................. 244
2-2-3
S e r v o C i r c u i t ..................................................
246
r e a d w r i t e LIS t e r m i n a l s
2-3
...................
T e s t P o i n t s ........................................
Variable Resistors .................................
FUNCTION OF TEST POINTS AND VARIABLE RESISTORS
2-3-1
F u n c t i o n of
2-3-2
F u n c t i o n of
247
248
253
Title
..................................................
3000
...........................................................
3101
SECTION 3 iYAINTENANCE
3-1
GENERAL
Page
3-1-1
P e r i o d i c Maintenance
............................................
3101
3-1-2
Check a n d A d j u s t m e n t
............................................
3102
3-1-3
Naintenance J i g s and Tools
......................................
E q u i p m e n t s ....................................................
T o o l s , j i g s , a n d d i s k s ........................................
3103
3-1-3-1
3-1-3-2
3-2
3-2-1
3-2-2
3-2-2-1
3-2-2-2
3-2-2-3
3-2-2-4
3-2-2-5
3-2-3
3-2-4
3-2-4-1
3-2-4-2
3-2-4-3
3-2-4-4
3-2-4-5
3-2-4-6
3-2-4-7
3-2-4-8
3-2-5
3-3
3-3-1
3-4
.......................................................
T o r q u e Applied t o S c r e w s a n d L o c k i n g P a i n t ......................
H a n d l i n g o f c o n n e c t o r s ..........................................
L o c a t i o n o f C o n n e c t o r s ........................................
C o n n e c t i o n a n d d i s c o n n e c t i o n o f c o n n e c t o r s ....................
P r e c a u t i o n s f o r w h i t e c o n n e c t o r s , J 6 a n d Jll ..................
P r e c a u t i o n s f o r b l a c k c o n n e c t o r s , 54 a n d 58 ...................
P r e c a u t i o n s f o r f l a t cable c o n n e c t o r s , 5 5 a n d J 7 ..............
Head Cable T r e a t m e n t ............................................
I n i t i a l S e t t i n g o f SKA ..........................................
Cable c o n n e c t i o n a n d s e t t i n g o f power s u p p l y v o l t a g e ..........
PRECAUTIONS
3103
3108
3201
3201
3202
3202
3204
3204
3205
3207
3209
3210
3210
...........................
S e t t i n g of s t e p r a t e a n d s e t t l i n g t i m e ........................
L e v e l d i s k c a l i b r a t i o n ........................................
A l i g n m e n t d i s k c a l i b r a t i o n ....................................
H u m i d i t y s e t t i n g ..............................................
G a i n s e t t i n g ..................................................
S e t t i n g of FDD s t r a p s a n d SKA special k e y .....................
Others ..........................................................
3232
............................................
3301
......................
3301
..............................................
3401
S e t t i n g of t h e maximum t r a c k number
PREVENTIVE LYAINTENANCE
C l e a n i n g o f M a g n e t i c Head by C l e a n i n g D i s k
CHECK AND ADJUSTMENT
3217
3218
3220
3223
3228
3229
3230
..................................
a n d A d j u s t m e n t of H o l d e r P o s i t i o n .........................
a n d A d j u s t m e n t o f A r m L i f t e r ..............................
o f CSS A s s ' y ..............................................
of F i l e P r o t e c t S e n s o r ....................................
o f Disk R o t a t i o n S p e e d ....................................
3-4-1
Adjustment of S e t A r m P o s i t i o n
3401
3-4-2
Check
3403
3-4-3
Check
3-4-4
Check
3-4-5
Check
3-4-6
Check
3-4-7
Check of E r a s e Gate D e l a y
3424
3-4-8
Check of Head Touch
3427
3-4-9
Check a n d A d j u s t m e n t of Asymmetry
.......................................
.............................................
...............................
of Read L e v e l ............................................
of R e s o l u t i o n ............................................
a n d A d j u s t m e n t of T r a c k A l i g n m e n t ........................
3406
3415
3419
3422
3432
3439
3-4-10
Check
3-4-11
Check
3-4-12
Check
3-4-13
Check a n d A d j u s t m e n t o f T r a c k 00 S e n s o r
3460
3-4-14
Check
3470
3-4-15
Check
3-5
........................
o f T r a c k 00 S t o p p e r ......................................
a n d A d j u s t m e n t o f I n d e x B u r s t Timing .....................
.....................................
Head C a r r i a g e A s s ' y ..............................
S t e p p i n g Motor A s s ' y .............................
MAINTENANCE PARTS REPLACEMENT
3-5-1
Replacement of
3-5-2
Replacement of
3-5-3
Replacement of DD motor A s s ' y ( S p i n d l e motor)
3-5-4
.....................................
Replacement o f Head Load S o l e n o i d ...............................
R e p l a c e m e n t of CSS A s s ' y ........................................
R e p l a c e m e n t of PCBA MFD C o n t r o l .................................
R e p l a c e m e n t of PCBA F r o n t OPT ...................................
R e p l a c e m e n t of F r o n t B e z e l A s s ' y ................................
R e p l a c e m e n t of F r o n t L e v e r A s s ' y ...............................
3-5-5
3-5-6
3-5-7
3-5-8
3-5-9
3-5-10
R e p l a c e m e n t of C o l l e t A s s ' y
...................
3444
3449
3473
3501
3501
3507
3510
3512
3513
3515
3516
3518
3519
3520
SECTION 2
THEORY O F OPERATION
-
200
-
2-1.
CONSTRUCTION AND FUNCTION
2-1-1.
G e n e r a l Block D i a g r a m
READ DATA
S I D E ONE
SELECT
WRITE DATA
DRIVE
SELECT 0*3
WRITE GATE
MOTOR ON
STEP
DIRECTION
SELECT
I N USE/
HEAD LOAD
4-i
Control
circuit
H e a d load solenoid-
TRACK 00
T r a c k 00 sensor
Stepping m o t o r
INDEX
WRITE
PROTECT
*
READY
DC POWER
4
( F i g . 2 0 1 ) G e n e r a l b l o c k diagram
-
201
-
2-1-2.
Mechanical S e c t i o n
S i n c e a d i s k i s f l e x i b l e r e c o r d i n g media made o f m y l a r f i l m a n d d a t a
i n t e r c h a n g e a b i l i t y between d i s k a n d FDD i s r e q u i r e d , t h e m e c h a n i c a l
s e c t i o n o f t h e FDD u s e s p r e c i s i o n p a r t s a n d i t is a l s o a s s e m b l e d
c a r e f u l l y and p r e c i s e l y .
For t h i s reason, o n l y t r a i n e d t e c h n i c i a n s
can h a n d l e t h e i n t e r n a l mechanism.
Never a p p l y e x c e s s i v e i m p a c t n o r
d r o p t h e FDD down on t h e d e s k .
The m e c h a n i c a l s e c t i o n i s c o n s t r u c t e d w i t h f r a m e , d o o r mechanism, d i s k
clamp mechanism, d i s k r o t a t i o n mechanism, m a g n e t i c head a n d c a r r i a g e ,
head l o a d mechanism ( o r CSs mechanism), head s e e k mechanism, v a r i o u s
d e t e c t i o n mechanisms, e t c .
(1) Frame
The main s t r u c t u r e f o r mounting t h e v a r i o u s mechanisms a n d p r i n t e d
c i r c u i t boards.
The frame i s made o f aluminum d i e c a s t t o m a i n t a i n
t h e s t a b i l i t y o f t h e FDD i n s t r e n g t h , p r e c i s i o n , d u r a b i l i t y , and
expansion c o e f f i c i e n t .
( 2 ) Door mechanism a n d d i s k clamp mechanism
The d o o r mechanism i s c o n s t r u c t e d w i t h main p a r t s o f set arm which f o r m s
t h e s t r u c t u r e f o r i n s t a l l i n g t h e d i s k on t h e s p i n d l e , o t h e r p a r t s o f
f r o n t l e v e r , clamp arm, e t c .
The s e t arm i s a t t a c h e d t o t h e r e a r o f t h e
frame w i t h l e a f s p r i n g a n d a c o l l e t ,
which forms t h e d i s k clamp
mechanism, i s a t t a c h e d on t h e t i p of t h e set arm.
When a d i s k i s i n s e r t e d a n d t h e d o o r ( f r o n t l e v e r ) i s c l o s e d , t h e c o l l e t
i s i n s e r t e d i n t o t h e c e n t e r h o l e of t h e d i s k a n d t h e d i s k i s clamped i n
t h e correct p o s i t i o n a l o n g t h e o u t e r c i r c u m f e r e n c e o f t h e c o l l e t .
( 3 ) Disk r o t a t i o n mechanism
The d i s k r o t a t i o n mechanism comprises DD m o t o r Ass'y
-
202
-
( s p i n d l e motor)
which i n c l u d e s s p i n d l e .
The DD motor i s a n o u t o r - r o t o r
t y p e DC b r u s h l e s s motor which h a s t h e
l o n g l i f e o f 30,000 h o u r s o r more i n c o n t i n u o u s r o t a t i o n .
Rotational
speed i s 300rpm f o r B and F models o r 360rpm f o r G model.
I t 1s
m a i n t a i n e d a t a s t a b l e c o n d i t i o n a g a i n s t l o a d v a r i a t i o n s and e n v i r o n mental changes by a feedback s i g n a l from AC tachometer i n t h e r o t o r .
The c o l l e t and t h e s p i n d l e a r e combined p r e c i s e l y t o m a i n t a i n t h e
c e n t e r p o s i t i o n c o r r e c t l y w i t h o u t damaging t h e c e n t e r h o l e of a d i s k
and so a s t o make t h e head be i n c o n t a c t w i t h t h e d i s k a t a c o r r e c t
position.
(4) Magnetic head and c a r r i a g e
Erase gaps
Read/write c o r e
-Rotational
direction
of disk
Erase cores
Read/write gap
(Fig.202) E x t e r n a l view o f magnetic head c o r e
The magnetic head assembly (head c a r r i a g e A s s ' y ) o f t h i s FDD h a s two
heads.
One i s f o r s i d e 1 s u r f a c e o f t h e d i s k and t h e o t h e r f o r s i d e 0
s u r f a c e of t h e d i s k (down s u r f a c e when t h e FDD i s s i t u a t e d h o r i z o n t a l l y ) .
Both o f t h e s i d e 0 and s i d e 1 heads a r e s u p p o r t e d by s p e c i a l l y d e s i g n e d
flexure.
The two magnetic heads a r e mounted a c c r o s s t h e d i s k on one
head c a r r i a g e , and t h e i r s u r f a c e s a r e d e s i g n e d f o r minimum d i s k wear and
maximum r e a d o u t p u t .
The head i t s e l f i s a long l i f e t y p e f o r improved
head wear.
The c o r e o f t h e head i s c o n s t r u c t e d w i t h r e a d / w r i t e gap which i s used
f o r d a t a w r i t e and d a t a r e a d o p e r a t i o n s and two e r a s e gaps which a r e
used t o e r a s e t h e edges o f t h e r e c o r d e d t r a c k immediately a f t e r t h e
r e c o r d i n g ( t u n n e l erase).
The head c a r r i a g e Ass'y forms t h e most
-
203
-
important p a r t of t h e FDD and i t i s s p e c i a l l y assembled w i t h high
precision.
( 5 ) Head load mechanism o r CSS mechanism
The head load mechanism i s used f o r models w i t h head load solenoid and
the CSS mechanism i s used f o r CSS model without head load soelnoid.
The head load mechanism functions t o make the head i n contacc w i t h a
disk only while a head load command i s received so a s t o reduce wear
of disk and head surfaces.
T h i s mechanism c o n s i s t s of head load
solenoid, arm l i f t e r , head p r o t e c t o r , e t c .
When t h e solenoid i s
energized, the arm l i f t e r goes down and t h e s i d e 1 head attached t o
the upper ann of the head c a r r i a g e i s depressed a g a i n s t the s i d e 1
surface of a disk w i t h an appropriate pressure, and the disk i s held
between two heads.
The s i d e 0 surface of the head and the disk a r e
s e t t o nearly the same height and the depression of the s i d e 1 head
produces the s t a b l e contact between the heads and the d i s k .
The CSS mechanism c o n s i s t s of CSS cam and head p r o t e c t o r .
I n t h e CSS
model, the magnetic heads a r e always i n contact w i t h a disk a s f a r a s
a disk i s i n s t a l l e d .
In order t o elongate the disk and head l i v e s ,
i t i s required t o make t h e disk r o t a t e only during read o r write
operation.
The CSS cam i s designed t o p r o t e c t t h e contact of s i d e 0
and s i d e 1 heads d i r e c t l y when the f r o n t l e v e r i s closed without a
disk.
For the purpose of p r o t e c t i n g the head being caught and damaged by t h e
head window edge a t disk i n s e r t i o n o r e j e c t i o n , the head p r o t e c t o r 1s
a l s o equipped t o both of the head load and CSS mechanisms t o l i f t up
the disk jacket.
(6) Head seek mechanism
The head seek mechanism c o n s i s t s mainly of stepping motor with a capstan
-
204
-
( p o o l y ) , s t e e l b e l t ( b a n d ) , and g u i d e s h a f t s .
The head c a r r i a g e i s
c o n n e c t e d t o t h e c a p s t a n o f t h e s t e p p i n g motor through t h e s t e e l b e l t
and i s s l i d e d a l o n g t h e g u i d e s h a f t s .
The s t e p p i n g motor r o t a t e s 2 s t e p s ( 3 . 6 " ) i n 4 8 t p i model and 1 s t e p
(1.8')
i n 9 6 t p i models f o r one t r a c k s p a c e .
To improve t h e c o n t i n u i t y
of head seek o p e r a t i o n and p r e c i s i o n of head p o s i t i o n i n g , h y b r i d t y p e
4-phase s t e p p i n g motor i s d r i v e n i n a unique manner which brought a
s u c c e s s i n r e d u c i n g t h e h e a t r a d i a t i o n and t o o b t a i n a h i g h l y p r e c i s e
positioning.
The p a r a l l e l i s m and t h e d i s t a n c e between t h e s h a f t s and t h e c e n t e r l i n e
of a d i s k , and s h a f t s and c a p s t a n t h e m s e l v e s a r e p r e c i s e l y machined.
A l s o t h e t h e r m a l expansion o f t h e frame, s t e e l b e l t , c a r r i a g e , e t c . a r e
t a k e n i n t o c o n s i d e r a t i o n i n t h e p r o c e s s o f d e s i g n so t h a t t h e y a r e
m u t u a l l y o f f s e t w i t h t h e expansion o f t h e d i s k .
(7) D e t e c t i o n mechanisms
( a ) F i l e p r o t e c t d e t e c t i o n mechanism
T h i s mechanism i s c o n s t r u c t e d w i t h an LED and a p h o t o - t r a n s i s t o r
to
d e t e c t t h e e x i s t e n c e of t h e w r i t e enable notch of t h e d i s k j a c k e t .
When a d i s k w i t h t h e notch covered i s i n s t a l l e d and t h e l i g h t p a s s
f o r d e t e c t i o n i s d i s t u r b e d , no w r i t e or erase c u r r e n t w i l l be s u p p l i e d
t o t h e r e a d / w r i t e and e r a s e heads and t h e r e c o r d e d i n f o r m a t i o n on t h e
d i s k i s p r o t e c t e d from an e r r o n e o u s i n p u t of a w r i t e command.
The LED i s mounted on t h e PCBA DD motor s e r v o and t h e p h o t o - t r a n s i s t o r
on t h e PCBA f r o n t O P T .
(b) Track 00 d e t e c t i o n mechanism
T h i s mechanism i s c o n s t r u c t e d w i t h a p h o t o - i n t e r r u p t e r
for detecting
t h e outermost t r a c k p o s i t i o n ( t r a c k 00) o f t h e head c a r r i a g e .
The p h o t o - i n t e r r u p t e r i s mounted on t h e main PCBA (PCBA MFD c o n t r o l ) .
I n s i d e t r a c k s from t h e t r a c k 00 on t h e d i s k are used.
- 205
-
Even i f an
e r r o n e o u s step o u t command is i n p u t from t h e t r a c k 00 p o s i t i o n , t h e
command w i l l be i g n o r e d by t h e i n t e r n a l c i r c u i t o f t h e FDD.
I f t h e head moves o u t from t h e t r a c k 00 by some r e a s o n s u c h a s
impact d u r i n g t r a n s p o r t a t i o n , t h e head c a r r i a g e s t r i k e s t h e frame
( f u n c t i o n s l i k e a t r a c k 00 s t o p p e r ) t o p r o t e c t t h e head from moving
o u t o f t h e r e t u r n a b l e r a n g e a t a n e x t power o n .
When s t e p - i n commands are i n p u t from t h e i n n e r m o s t t r a c k , t h e head
moves t o w a r d i n w a r d a n d s t o p s w i t h a n a p p r o p r i a t e s p a c e l e f t a g a i n s t
t h e head window e d g e o f t h e d i s k .
In order t o recalibrate the track
from t h i s p o s i t i o n ( r e t u r n i n g o p e r a t i o n t o t h e t r a c k 001, i t i s
r e q u i r e d t o i n p u t t h e s t e p - o u t command w i t h s e v e r a l a d d i t i o n a l s t e p s
t o t h e maximum t r a c k number.
C a u t i o n : S e n s e t i m i n g of t h e t r a c k 00 p o s i t i o n w i l l change i f you
l o o s e n a f i x i n g screw o f t h e main PCBA.
t h a t t h e t r a c k 00 p h o t o - i n t e r r u p t e r
This i s because
i s mounted o n t h e PCBA.
Be s u r e t o r e a d j u s t t h e t r a c k 00 s e n s o r t i m i n g a c c o r d i n g
t o i t e m 3-4-13.
( c ) I n d e x d e t e c t i o n mechanism
f o r d e t e c t i n g t h e index hole are l o c a t e d a t
LED a n d p h o t o - t r a n s i s t o r
t h e i n d e x window area o f t h e d i s k j a c k e t .
The LED i s mounted o n t h e PCBA DD motor s e r v o ( i n t h e r o t o r o f s p i n d l e
motor) a n d t h e p h o t o - t r a n s i s t o r on t h e PCBA f r o n t OPT.
w i l l be d e t e c t e d a l o n g t h e r o t a t i o n of t h e d i s k .
-
206
-
The i n d e x h o l e
2 - 2 . CIRCUIT DESCRIPTIONS
The e l e c t r o n i c s of t h e FDD is c o n s t r u c t e d with t h r e e s e c t i o n s which a r e
read w r i t e c i r c u i t , c o n t r o l c i r c u i t , and s e r v o c i r c u i t .
Read w r i t e
c i r c u i t and c o n t r o l c i r c u i t a r e mounted on t h e PCBA MFD c o n t r o l (main
PCBA), and s e r v o c i r c u i t i s on t h e PCBA DD motor s e r v o .
2-2-1.
Read Write C i r c u i t
The read w r i t e c i r c u i t i s c o n s t r u c t e d with mode s e l e c t o r , read c i r c u i t ,
w r i t e c i r c u i t , low v o l t a g e s e n s o r .
w r i t e LSI ( b i p o l a r LSI, U 2 ) .
Fig.203 shows t h e block diagram.
-
207
-
They a r e mostly packed i n a read
(Fig. 2 0 3 ) Block diagramof
read write c i r c u i t
LOV PASS F I L T E R
SWITCH F I L T E R
I
N
Q)
0
I
Jl-22
O
b
1
1
CFI
2-2-1-1.
Mode s e l e c t o r
Mode s e l e c t o r i s c o n s t r u c t e d with t h e switch f i l t e r and w r i t e c u r r e n t
switch.
Table 201 shows t h e s w i t c h i n g c o n d i t i o n of t h e read w r i t e c i r c u i t by
t h e t r a c k switch s i g n a l
(5
and SF1 s i g n a l s
i n t h e schematic diagram)
from t h e c o n t r o l c i r c u i t .
(1) Switch f i l t e r
Switch f i l t e r i s used f o r e l i m i n a t i n g t h e i n f l u e n c e o f s a d d l e waveform
( r e f e r t o Fig.204) a t t h e o u t e r t r a c k s .
When t h e
5and SF1 a r e
l e v e l , t h e switch f i l t e r c a p a c i t o r s ,
C14 and C1S a r e a c t i v a t e d t o i n c r e a s e t h e c a p a c i t y o f t h e low p a s s
f i l t e r c a p a c i t o r , C16.
and t h e c u t - o f f
T h i s s t a t e i s t h e o n - s t a t e of t h e switch f i l t e r ,
frequency o f t h e low p a s s f i l t e r i s s e t t o low.
( 2 ) Write c u r r e n t switch
W r i t e c u r r e n t s w i t c h is used only f o r 9 6 t p i models.
I t is used f o r
making t h e write c u r r e n t i n o u t e r t r a c k s h i g h e r than i n i n n e r t r a c k s
t o improve t h e o v e r - w r i t e c h a r a c t e r i s t i c s ( w r i t e 2F a f t e r 1F w r i t e
and measure t h e r e s i d u a l frequency components of 1 F ) .
W r i t e c u r r e n t i s s u p p l i e d t o t h e w r i t e d r i v e r by w r i t e c u r r e n t source
i n t h e r e a d w r i t e LSI, U2.
The s u p p l i e d value from t h i s c u r r e n t source
can be c a l c u l a t e d from t h e following e x p r e s s i o n combining t h e e x t e r n a l
r e s i s t o r s R6 and R7.
Outer t r a c k s : I w =
13
.2 + 12
.7 --R6
R7
Inner t r a s k s : I w =
13.2
--R6
-
No.2
209
-
No.1
E r a s e c u r r e n t i s c a l c u l a t e d from t h e f o l l o w i n g e x p r e s s i o n .
Erase
c u r r e n t is n o t switched depending on t h e t r a c k position.
I
SFO, SF1 s i g n a l s
Switch f i l t e r
Write c u r r e n t s w .
( C u r r e n t exp. )
I
Erase d r i v e r
(Current exp
,
1
Models a n d t r a c k p o s i t i o n
Tr.00~21
Tr.22~39
Y
T
H
Tr.00-43
Tr.44%79
L
H
I
ON
No.1
OFF
ON
No. 2
No. 1
OFF
No. 2
.
( T a b l e 201) S w i t c h i n g f u n c t i o n f o r read write c i r c u i t
-
210
-
2-2-1-2.
Read c i r c u i t
The read c i r c u i t c o n s i s t s of head m a t r i x s w i t c h , p r e - a m p l i f i e r ,
low
p a s s f i l t e r , d i f f e r e n t i a t i o n a m p l i f i e r , peak d e t e c t o r , S i - d i r e c t i o n a l
edge d e t e c t o r , o u t p u t d r i v e r , e t c .
Main c i r c u i t s a r e enclosed i n t h e
read w r i t e LSI, U2.
The minute v o l t a g e induced i n read o p e r a t i o n by t h e r e a d / w r i t e head i s
i n p u t t o p r e - a m p l i f i e r v i a m a t r i x switch f o r s e l e c t i n g s i d e 0/1 heads.
The p r e - a m p l i f i e r has t h r e e g a i n s e t t i n g t e r m i n a l s , G S O , G S 1 and GSC.
In B and F models, GSO-GSC i s s h o r t e d t o o b t a i n t h e g a i n of 1 1 5 t i m e s ,
approx., while GS1-GSC i s s h o r t e d i n G model t o o b t a i n t h e g a i n of 230
t i m e s , approx.
The pre-amp.
output i s supplied t o the d i f f e r e n t i a t i o n amplifier via
t h e low p a s s f i l t e r and t h e switch f i l t e r t o e l i m i n a t e u n d e s i r a b l e
high frequency n o i s e s .
The d i f f e r e n t i a t i o n a m p l i f i e r p h a s e - s h i f t s
the
peak p o s i t i o n of t h e reproduced waveform t o z e r o c r o s s p o i n t , and a t
t h e same t i m e , f u r t h e r a m p l i f i e s t h e s i g n a l with t h e m o s t a p p r o p r i a t e
equalization.
The d i f f e r e n t i a t e d o u t p u t s a r e s u p p l i e d t o t h e peak
d e t e c t o r c o n s t r u c t e d with a comparator a f t e r p a s s i n g through t h e
coupling c a p a c i t o r s , C20 and C 2 1 , and converted i n t o a square wave.
Then t h e edges of t h e square wave a r e d e t e c t e d by t h e b i - d i r e c t i o n a l
edge d e t e c t o r and they a r e o u t p u t a s t h e read d a t a p a u l s e s from t h e
FDD through t h e RD d r i v e r and t h e RD/INDEX g a t e i n t h e c o n t r o l LSI, U1.
-
211
-
Magnetization
on disk
Pre-amp.output
(TP41
Pre-amp-output
(TP5)
Differentiation
amp. output (TP7)
Differentiation
amp.output(TP8)
Peak detector
output in U2
RD
B,F models: lus,approx.
G model: O.5pslapprox.
U
READ DATA(J1-30)
u u u
(Fig.204) Read amplifier and peak detector waveforms
-
212
-
2-2-1-3.
Write c i r c u i t
The w r i t e c i r c u i t c o n s i s t s o f w r i t e c o n t r o l l o g i c , w r i t e c u r r e n t s o u r c e ,
w r i t e d r i v e r , e r a s e d r i v e r , c o m n d r i v e r , and e t c .
Most of t h e
c i r c u i t s a r e enclosed i n t h e read w r i t e LSI, U 2 .
Common d r i v e r o u t p u t t e r m i n a l s , COMO and COMl a r e connected t o t h e
c o m n terminals
respectively.
( c e n t e r t a p s ) of t h e s i d e 0 and s i d e 1 heads,
The o u t p u t s of t h e common d r i v e r a r e c o n t r o l l e d by t h e
SIDE ONE SELECT
(z),
write gate
( W C ) , and e r a s e g a t e ( E G ) s i g n a l s
When t h e COMO o r t h e COMl
s u p p l i e d through t h e w r i t e c o n t r o l l o g i c .
i s H I G H l e v e l (11.5V, a p p r o x . ) , t h e power t o t h e read c i r c u i t i s c u t
o f f i n t h e r e a d write LSI t o i n h i b i t t h e r e a d o p e r a t i o n .
I
Input s i g n a l s
Output v o l t a g e
FDD o p e r a t i o n
COMl
COMO
2.7V
S I D E 0 read o p e r a t i o n
11.5v
SIDE 0 w r i t e o p e r a t i o n
SIDE 0 w r i t e o p e r a t i o n
I
SIDE 1 r e a d o p e r a t i o n
I
SIDE 1 w r i t e o p e r a t i o n
SIDE 1 w r i t e o p e r a t i o n
11.5V
ov
ov
ov
(approx.)
I
I
ov
ov
ov
2.7v
11.5V
11.5v
(Table 2 0 2 ) Comon d r i v e r o u t p u t
The EG s i g n a l s u p p l i e d from t h e e r a s e t i m e r i n t h e c o n t r o l c i r c u i t
changes t o H I G H o r LOW l e v e l with an a p p r o p r i a t e t i m e d e l a y a g a i n s t t h e
WG s i g n a l
( r e f e r t o Fig.205).
Since t h e e r a s e gaps l o c a t e about 0.85mm
(B and F models) o r 0.585mm ( G model) backward from t h e r e a d / w r i t e gap,
i t i s necessary f o r t h e e r a s e d r i v e r t o d e l a y t h e WG s i g n a l so t h a t
t h e w r i t t e n d a t a i s completely trimmed by t h e e r a s e head ( t u n n e l e r a s e ) .
The t u n n e l e r a s e produces a guard band between t h e t r a c k s p r e v e n t i n g
d e t e r i o r a t i o n o f t h e S/N r a t i o r e s u l t i n g from a o f f - t r a c k
error).
(positioning
It a l s o e n s u r e s d i s k i n t e r c h a n g e a b i l i t y .
The WRITE DATA i n p u t p u l s e i s l a t c h e d by t h e w r i t e d a t a l a t c h i n t h e
-
213
-
write control logic. And appropriate write current determined by the
write current source is supplied to the read/write head with turning on
and off the two write drivers alternately.
WRITE GATE (51-24)
I
'
Erase-on
delay
Erase-off
delay
1
WG (U2-29)
I
EG (TP2)
L
WRITE DATA (51-22)
Write data latch
in U2
I
I
I
lu'u
n
n
Write driver output
(U2-17,18,121.15)
1
Write current
Magnetization on
disk
7
-- -
- * -
\
Previous magnetization
(Fig.205) Typical waveform of write circuit operation
-
214
-
2-2-1-4.
Low v o l t a g e s e n s o r
The low v o l t a g e s e n s o r ( L V S ) i s equipped t o p r o t e c t t h e FDD from
erroneous o p e r a t i o n due t o t h e i n t e r n a l c i r c u i t c o n s t r u c t i o n of t h e FDD
d u r i n g u n s t a b l e s t a t e of t h e power v o l t a g e such a s a t power on o r o f f .
Two s e n s o r s o f LVSO and L V S l a r e equipped i n t h e read w r i t e LSI, U2.
LVSO monitors t h e +5V v o l t a g e s u p p l i e d t o t h e i n t e r n a l c i r c u i t of t h e
read w r i t e L S I .
If t h e v o l t a g e i s lower than 3 . 5 V through 4 . 4 V ,
it
s u p p l i e s s i g n a l s t o i n h i b i t t h e o p e r a t i o n of t h e common d r i v e r , w r i t e
d r i v e r , e r a s e d r i v e r , and w r i t e c o n t r o l l o g i c i n t h e LSI, which p r o t e c t
t h e d i s k from t h e erroneous w r i t e o r erroneous e r a s e d u r i n g u n s t a b l e
s t a t e o f t h e power v o l t a g e .
L V S l i s equipped t o g e n e r a t e
c i r c u i t i n item 2 - 2 - 2 .
o f 3 . 5 V through 4 . 4 V .
AS
s i g n a l t o be s u p p l i e d t o t h e c o n t r o l
w e l l a s LVSO,
it i s a c t i v a t e d i n t h e range
The monitored v o l t a g e by t h e L V S l i s o n l y +5V
connected t o t h e LVGG t e r m i n a l ( p i n 3 7 ) of t h e r e a d w r i t e L S I .
the
Es i g n a l
i s LOW l e v e l , a l l t h e c o n t r o l c i r c u i t s (mainly c o n t r o l
L S I , U1) a r e r e s e t .
-
While
LVS (U2-32)
/
\
i
-
(Fig.206) Typical waveform o f low v o l t a g e sensor
-
215
-
2-2-1-5. Function and operating waveform of read write LSI terminals
Following shows the function of the read write LSI, U2 and typical
operating waveforms (1) Pre-amplifier
(a) RWOO (pin 121, RWOl (pin 14)
Terminals f o r side 0 head connection.
U
I
WRITE DATA interval
Side 0 read: 2.7V, approx.
Side 1 write: OV, approx.
Side 0 write
Side 1 read: OV, approx.
(b) Rwol (pin 13) , RWll (pin 15)
Terminals for side 1 head connection.
IT-
11.5V, approx.
WRITE DATA interval
1
Side 1 read: 2.7V, approx.
Side 0 write: OV, approx.
Side 1 write
Side 0 read: OV, approx.
(c) GSC (pin 111, G S O (pin 101, GS1 (pin 9)
Setting terminals of pre-amplifier gain.
If GSC-GSO is shorted or connected with a capacitor, the differential
voltage gain of the pre-amplifier is 115 times, approx.
-
216
-
I f GSC-GS1 i s s h o r t e d o r connected w i t h a c a p a c i t o r , it i s i n c r e a s e d
t o 230 t i m e s , approx.
( d ) PREO ( p i n 7 , p i n 6 )
D i f f e r e n t i a l o u t p u t t e r m i n a l s of t h e p r e - a m p l i f i e r .
p i n 6 and 7 a r e o p p o s i t e each o t h e r .
2.7Vl
The phase of
Refer t o Fig.204.
approx.
2.7V
Read
-
I
approx.
Write
( 2 ) Differentiation amplifier
( a ) DIFI ( p i n 5 , p i n 4 )
Differential input terminals t o the differentiation amplifier.
The phase of p i n 5 and 4 a r e o p p o s i t e each o t h e r .
2 . SV, approx.
SV, approx.
2.-
Read
-
Write
(b) DIFC ( p i n 3 , p i n 2 )
Time constant s e t t i n g terminals of the d i f f e r e n t i a t i o n amplifier.
The phase of p i n 3 and 2 a r e o p p o s i t e each o t h e r .
A-1.1v,
1. l V , approx.
approx.
Read
-
Write
-
-
217
-
(c) DIFO ( p i n 1, p i n 44)
D i f f e r e n t i a l output terminals of t h e d i f f e r e n t i a t i o n amplifier.
The phase of pin 1 and 44 a r e o p p o s i t e each o t h e r .
2.7V,
approx.
Read
-
2.7V,
approx.
Write
( d ) C I ( p i n 43, p i n 43)
D i f f e r e n t i a l i n p u t t e r m i n a l o f t h e comparator (peak d e t e c t o r ) .
The
phase o f p i n 43 and 42 a r e o p p o s i t e each o t h e r .
2.5V,
approx.
Read
-
2.5V,
approx.
Write
( 3 ) Time domain f i l t e r
( a ) TDCR ( p i n 40)
Pulse width s e t t i n g t e r m i n a l o f t h e f i l t e r .
1.5V, approx.
Delay p u l s e width
Write: 1.5V, approx.
Read
Read i n h i b i t : 0 . 7 V ,
-
218
-
approx.
( b ) RDCR ( p i n 39)
P u l s e width s e t t i n g t e r m i n a l f o r t h e RD o u t p u t p u l s e .
1
1
1
Y I V V V
2V, approx.
2v, approx.
-L
Write
RD p u l s e width
&
read i n h i b i t
Read
( 4 ) Write c i r c u i t
( a ) COMO ( p i n 211, COMl ( p i n 19)
Output t e r m i n a l s o f t h e common d r i v e r .
Two t e r m i n a l s a r e equipped
f o r t h e s i d e 0 and s i d e 1 heads r e s p e c t i v e l y .
Refer t o t a b l e s 202 and 203 a s t o t h e o u t p u t v o l t a g e a t each
operating condition.
( b ) EO0 ( p i n 241, E 0 1 ( p i n 2 2 )
Output t e r m i n a l s of t h e e r a s e d r i v e r which i s c o n s t r u c t e d with open
c o l l e c t o r NPN t r a n s i s t o r s .
Two t e r m i n a l s a r e equipped.
While t h e EG
i n p u t t e r m i n a l i s H I G H l e v e l , one o f t h e d r i v e r s which i s s e l e c t e d
by t h e
i n p u t t e r m i n a l t u r n s on (becomes LOW).
Refer t o Table 203.
( c ) WCSO ( p i n 261, WCSl ( p i n 25)
External r e s i s t o r terminals f o r s e t t i n g t h e w r i t e c u r r e n t .
shows t h e c i r c u i t diagram o f t h e t e r m i n a l .
By t h e p u l l up r e s i s t o r s
f o r t h e WCSO and WCS1, t h e w r i t e c u r r e n t i s determined.
is c a l c u l a t e d by t h e e x p r e s s i o n i n i t e m 2-2-1-1
-
219
-
Following
(2).
The c u r r e n t
I
5v
LS I
9
5v
M I RROR
( d ) WT ( p i n 1 7 , p i n 18)
External r e s i s t o r t e r m i n a l s f o r t h e head t e r m i n a t i o n i n w r i t e o p e r a t ion.
An a p p r o p r i a t e value of r e s i s t o r i s connected e x t e r n a l l y n o t
t o occur t h e abnormal overshoot nor undershoot a t w r i t e o p e r a t i o n .
These t e r m i n a l s a r e a l s o used f o r t h e asymmetry adjustment a t read
operation.
11V, approx.
12V, approx.
Read
Write
( e ) CD ( p i n 36)
In o r d e r t o p r o t e c t t h e head from u n d e s i r a b l e magnetization, t h i s
terminal i s used t o s e t t h e d e l a y t i m e t o keep t h e w r i t e c u r r e n t flow
a t a determined d i r e c t i o n f o r 1 through 5us, approx., a f t e r t h e
completion o f a w r i t e o p e r a t i o n (WG t u r n s o f f ) .
1.5V, approx.
l a y time
-
220
-
(f)
( p i n 27)
---
S c h m i t t TTL i n p u t
C o n t r o l i n p u t t e r m i n a l h a v i n g f o l l o w i n g two f u n c t i o n s .
Refer t o
T a b l e 203.
i ) ON/OFF c o n t r o l o f w r i t e c u r r e n t s e t t i n g t e r m i n a l WCS1.
i i ) S e l e c t i o n of erase d r i v e r o u t p u t t e r m i n a l s EO0 a n d E01.
(g)
WD
( p i n 28)
---
S c h m i t t 'IT5 i n p u t
WRITE DATA i n p u t t e r m i n a l from t h e h o s t c o n t r o l l e r
-lnnrlr
SV,
approx.
Read
-
Write
( h ) WG ( p i n 2 9 ) , EG ( p i n 30)
---
S c h m i t t TTL i n p u t
C o n t r o l i n p u t t e r m i n a l s f o r w r i t e permit (WG) a n d erase p e r m i t ( E G )
from t h e c o n t r o l c i r c u i t i n t h e FDD.
R e f e r t o T a b l e s 202 a n d 203.
(5) O t h e r s
(a)
( p i n 31)
---
S c h m i t t TTL i n p u t
I n p u t t e r m i n a l f o r c o n t r o l l i n g t h e s i d e s e l e c t i o n from t h e c o n t r o l
circuit.
The t e r m i n a l f u n c t i o n s a s t h e selector f o r common d r i v e r
o u t p u t s COMO/COMl a n d f o r head s w i t c h m a t r i x o f R W O O , O ~ / R w 10,ll
terminals.
(b) E ( p i n 32)
R e f e r t o T a b l e 203.
---
Open c o l l e c t o r TTL o u t p u t
-
LVS s i g n a l o u t p u t t e r m i n a l t o t h e c o n t r o l c i r c u i t o f t h e FDD.
t o i t e m 2-2-1-4.
-
221
-
Refer
-
( c ) O I N V ( p i n 3 5 ) , DS ( p i n 34)
---
TTL i n p u t
C o n t r o l i n p u t t e r m i n a l of RD o u t p u t .
(d)
i%( p i n
33)
---
Totempole TTL o u t p u t
Read d a t a p u l s e o u t p u t t e r m i n a l t o t h e c o n t r o l c i r c u i t .
The o u t p u t i s c o n t r o l l e d by O I N V and
Table 203.
i n p u t s i g n a l s a s shown i n
I n t h i s FDD, b o t h of t h e O I N V and
inputs a r e fixed
t o LOW l e v e l and n e g a t i v e p u l s e s a r e o u t p u t a t t h i s t e r m i n a l .
Refer
t o F i g . 204.
( e ) AGND ( p i n 1 6 ) . EGND ( p i n 2 3 ) . and DGND ( p i n 38)
OV p o w e r t e r m i n a l s mainly f o r t h e f o l l o w i n g c i r c u i t s i n t h e LSI.
AGND:
Analog o p e r a t i o n c i r c u i t s such a s p r e - a m p l i f i e r .
EGND: E r a s e d r i v e r .
XND:
D i g i t a l o p e r a t i o n c i r c u i t s such as w r i t e c o n t r o l l o g i c .
(f) AVGG ( p i n 8 ) , DVGG ( p i n 4 1 ) , LVGG ( p i n 37)
+5V p o w e r t e r m i n a l s mainly f o r t h e f o l l o w i n g c i r c u i t s i n t h e LSI.
AVGG:
Analog o p e r a t i o n c i r c u i t s such as p r e - a m p l i f i e r .
DVGG: D i g i t a l o p e r a t i o n c i r c u i t s such a s w r i t e c o n t r o l l o g i c .
LVGG: Low v o l t a g e s e n s o r (LVS1)
(9) EVCC ( p i n 20)
+12V p o w e r t e r m i n a l f o r common d r i v e r .
-
222
-
L
H
L
L
-
-
H
O
H
H
L
L
-
-
H
-
-
-
-
L
; v -
-
1
Z
0
F
0
Hi
Z
0
F
O
O
Z
Z
Z
H
L: Logic l e v e l 0 (LOW)
R : COM v o l t a g e ,
H : Logic l e v e l 1 ( H I G H )
P: P o s i t i v e p u l s e
Z : High impedance ( O P E N )
N : Negative p u l s e
Hi: COM v o l t a g e , 1 1 . 5 V .
approx.
2 . 7 V , approx.
F: FALSE (No p u l s e output)
LV:
Low v o l t a g e
(Table 2 0 3 ) Read w r i t e L S I c o n t r o l t a b l e
-
223
-
0
WCS 0+1
0
2-2-2.
Control C i r c u i t
The c o n t r o l c i r c u i t c o n s i s t s o f s t r a p c i r c u i t , f r o n t LED c o n t r o l c i r c u i t ,
head load c o n t r o l c i r c u i t , w r i t e / e r a s e
c o n t r o l c i r c u i t , motor-on g a t e ,
ready d e t e c t o r , s t e p p i n g motor c o n t r o l c i r c u i t , t r a c k c o u n t e r , RD/INDEX
gate, interface driver, e t c .
Almost a l l t h e c i r c u i t s except f o r s t r a p c i r c u i t and s t e p p i n g motor
d r i v e r a r e enclosed i n t h e c o n t r o l LSI ( b i p o l a r LSI, U l ) .
Fig.207 shows t h e block diagram.
-
224
-
)
I
L0AD
SOLENOI D
':EA0
TO/FROY
READ
fiRlTE
CI PCUlT
N
I
N
n
I
5
PCBA
FRONT
OPT
5
STEPPING
dOTOR
2-2-2-1.
Strap c i r c u i t
In o r d e r t o s e l e c t t h e v a r i o u s f u n c t i o n by u s e r s , s e v e r a l s t r a p p o s t s
a r e equipped.
Refer t o t h e S p e c i f i c a t i o n items 1-11 and 1 - 1 2 a s t o
t h e d e t a i l s of s t r a p f u n c t i o n .
Some m d e l s have n o t s t r a p p o s t s .
These models have s o l d e r e d jumping
wires i n s t e a d of t h e s t r a p p o s t s , and t h e f u n c t i o n i s f i x e d .
t o t h e v e r s i o n t a b l e i n t h e schematic d i a g r a m ) .
-
226
-
(Refer
2-2-2-2.
F r o n t LED c o n t r o l c i r c u i t
The c i r c u i t c o n s i s t s of LED g a t e a n d LED d r i v e r .
t h e c o n t r o l LSI,
DRIVE SELECT
U1.
(E)
and
t o t h e LED g a t e .
I N USE (:)signals
v i a s t r a p c i r c u i t are i n p u t
A c c o r d i n g t o t h e f u n c t i o n s e l e c t e d by U O / U l / I R
t h e s e i n p u t s i g n a l s are g a t e d to o u t p u t a s t h e E
LED d r i v e r .
Notes
They a r e e n c l o s e d i n
While t h e
1.
s:
2.
Eand
DLED
straps.
D s i g n a l through t h e
s i g n a l is LOW l e v e l , t h e f r o n t LED t u r n s o n .
LOW i n r e a d y .
Output s i g n a l from ready d e t e c t o r i n U 1 .
I U : I N USE i n p u t s i g n a l LOW.
IUL: I n t e r n a l s i g n a l of L S I .
L a t c h e d s i g n a l o f IN USE by
l e a d i n g edge o f DRIVE SELECT.
IUL c o n d i t i o n s a r e e f f e c t i v e o n l y when t h e I U s t r a p
is on-state.
( T a b l e 204) F r o n t LED t u r n - o n
-
227
-
condition
2-2-2-3.
Head load c o n t r o l c i r c u i t
The c i r c u i t s c o n s i s t s o f head load g a t e , o v e r d r i v e t i m e r 1, s o l e n o i d
d r i v e r , and o v e r d r i v e c i r c u i t 1.
(1) Head l o a d g a t e
D R I V E SELECT
and HEAD LOAD
(E:
signals
via strap c i r c u i t are
i n p u t t o t h e head load g a t e i n t h e c o n t r o l LSI, U1.
According t o t h e
s e l e c t e d f u n c t i o n d e s i g n a t e d by HL/HS s t r a p s , t h e s e i n p u t s i g n a l s a r e
g a t e d t o o u t p u t a s t h e HLC s i g n a l t o t h e s o l e n o i d d r i v e r U3 ( p i n 3-14).
While t h e HLC s i g n a l i s H I G H l e v e l , t h e head load s o l e n o i d i s a c t i v a t e d .
Notes
PRDY: Ready f Pre-ready
Pre-ready: I n t e r n a l s i g n a l o f LSI.
b e f o r e t h e ready s t a t e .
I t goes t o TRUE 50msec
Refer t o item 2-2-2-6.
(Table 205) Head load s o l e n o i d turn-on c o n d i t i o n
( 2 ) Solenoid d r i v e r
The HLC s i g n a l from t h e c o n t r o l LSI i s s u p p l i e d t o t h e d r i v e r I C , U 3 .
Refer t o Fig.208 a s t o t h e c o n s t r u c t i o n o f U 3 .
( 3 ) Overdrive t i m e r 1
The HLC s i g n a l i s a l s o s u p p l i e d t o t h e o v e r d r i v e t i m e r 1 i n t h e c o n t r o l
LSI.
The o v e r d r i v e t i m e r i s c o n s t r u c t e d with a r e t r i g g e r a b l e c o u n t e r .
-
228
-
ST0
OUT
IN 1
-
IN 2
OUT
-
IN 3
OUT
-
IN 4
OUT
-
IN 5
1
2
3
4
OUT
5
IN 6
OUT
6
GNO
COM
(Fig.208) Construction of d r i v e r I C , U 3
For t h e i n i t i a l 24msec of t h e s o l e n o i d a c t i v a t i o n , i t maintains t h e HOD
output a t HIGH l e v e l .
( 4 ) Overdrive c i r c u i t 1
The HOD o u t p u t s i g n a l i s s u p p l i e d t o t h e o v e r d r i v e c i r c u i t 1 c o n s t r u c t e d
by t r a n s i s t o r s 42 (NPN) and Q1 (PNP) and it makes Ql t u r n on while t h e
HOD s i g n a l i s H I G H l e v e l .
+ 1 2 V power i s a p p l i e d t o t h e s o l e n o i d a t t h a t
t i m e t o execute t h e drawing-in a c t i o n of t h e s o l e n o i d s e c u r e l y .
After the overdrive period,
t h e s o l e n o i d m a i n t a i n s i t s s i t u a t i o n with
+5V power through t h e diode C R 1 t o save t h e power.
-
229
-
HLC signal
HOD signal
llV,approx.
Applied vol taqe
to solenoid coil
-4V.
j
approx.
a
-
v
e
r
approx
1
(Fiq.209) Overdrive timing of head load solenoid
-
230
-
2-2-2-4.
Write/erase c o n t r o l c i r c u i t
The c i r c u i t c o n s i s t s o f write/erase g a t e a n d erase t i m e r .
Most o f t h e
p a r t s o f t h e c i r c u i t a r e e n c l o s e d i n t h e c o n t r o l LSI, U1.
(1) Write/erase g a t e
The g a t e j u d g e s w h e t h e r new d a t a c a n be w r i t t e n on a n i n s t a l l e d d i s k .
I f it c a n b e , t h e c i r c u i t s u p p l i e s t h e WG s i g n a l f o r t h e r e a d w r i t e
LSI a n d erase t i m e r .
The WG s i g n a l goes t o TRUE i n t h e f o l l o w i n g c o n d i t i o n .
Notes
WG: W r i t e o p e r a t i o n a t H I G H .
DSEL:
-
DRIVE SELECT i n p u t s i g n a l LOW.
IWG: WRITE GATE i n p u t s i g n a l LOW.
FPT: F i l e p r o t e c t s e n s o r o u t p u t (FPT i n p u t o f LSI) LOW.
The same a s t h a t t h e f i l e p r o t e c t s e n s o r d e t e c t s t h e w r i t e
e n a b l e n o t c h ( l i g h t p a s s i n g c o n d i t i o n ) o f a d i s k which i s
equivalent t o t h a t the
E (WRITE PROTECT)
output signal
1s H I G H ( w r i t e - e n a b l e c o n d i t i o n ) .
( 2 ) E r a s e timer
The c i r c u i t t o make t h e WG s i g n a l d e l a y from t h e write/erase g a t e a s i n
F i g . 2 0 5 t o o u t p u t t h e EG s i g n a l f o r t h e r e a d w r i t e LSI.
Refer t o i t e m
2-2-1-3.
V a r i o u s d e l a y t i m e c a n be s e t by HDS, HO, H 1 , a n d SS i n p u t t e r m i n a l s
Of t h e c o n t r o l LSI.
By t h e s e i n p u t t e r m i n a l s , t h e o u t p u t o f HD a n d
SPED
t e r m i n a l s are also s e t which e x e c u t e s t h e s e l e c t i o n o f t h e FDD f u n c t i o n .
The s e t t i n g o f t h i s FDD, however, i s f i x e d a s shown i n t h e f o l l o w i n g
Table.
-
231
-
Notes: 1. The f i g u r e i n t h e above Table i s t h e c a l c u l a t e d value
excluding t h e o s c i l l a t o r t o l e r a n c e and propagation d e l a y .
2 . HO and SS i n p u t t e r m i n a l s a r e connected t o H D o u t p u t .
HD o u t p u t s t a t e i s determined by HDS i n p u t s i g n a l s .
(Table 206) Erase delay c o n t r o l t a b l e
-
232
-
2-2-2-5.
-%tor-on
gate
The c i r c u i t , r e c e i v i n g a s p i n d l e motor-on c o m a n d from t h e h c s t
c o n t r o l l e r , s u p p l y t h e MC (motor c o n t r o l ) s i g n a l t o t h e s p i n d l e motor
servo c i r c u i t .
The c i r c u i t c o n s i s t s o f OR-gate,
1 3 3 ~ sd e l a y c i r c u i t
a n d a u t o - t u r n c i r c u i t which a r e e n c l o s e d i n t h e c o n t r o l LSI, U1.
A motor-on
command i n p u t t o t h e
3o r
terminal is supplied to
1 3 3 ~ 1 sd e l a y c i r c u i t v i a t h e OR-gate t o be d e l a y e d f o r 1 3 3
nd
267~s.
The d e l a y c i r c u i t e l i m i n a t e s t h e n o i s e s mixed o n t o t h e i n t e r f a c e l i n e
a n d p r o t e c t s t h e c o n t r o l c i r c u i t from e r r o n e o u s o p e r a t i o n .
The MC s i g n a l g o e s t o TRUE i n t h e f o l l o w i n g c o n d i t i o n s .
MC(H)= ( s ( L )
+ x ( L ) ) * 1 3 3 ~ sd e l a y * DISK(H)
MC: Motor r o t a t i o n a t H I G H .
Notes
MONO: MOTOR ON
MON1: DLED i s
i n p u t s i g n a l LOW.
low a t MI, s t r a p i s ON.
(Front bezel indicator is ON).
DISK: F i x e d t o TRUE ( H I G H ) .
The a u t o - t u r n c i r c u i t makes t h e s p i n d l e motor r o t a t e a u t o m a t i c a l l y a t
a d i s k i n s e r t i o n t o improve t h e c h u c k i n g a c c u r a c y .
The c i r c u i t i s s e t
by a n i n f o r m a t i o n o f d i s k i n s e r t i o n from t h e f i l e p r o t e c t s e n s o r , and
i s r e s e t by a d e t e c t i o n of r e a d y s t a t e o r by a d e t e c t i o n o f more t h a n
8 . 7 seconds, p a s s i n g a f t e r t h e
i n p u t t e r m i n a l k e e p i n g TRUE (LOW)
Even t h o u g h t h e FDD g o e s t o t h e r e a d y s t a t e by a command from t h i s
circuit, the
level)
o u t p u t s i g n a l i n i t e m 2-2-2-6
.
-
233
-
m a i n t a i n s FALSE ( H I G H
.
2-2-2-6.
Ready d e t e c t o r
Ready d e t e c t o r c o n s i s t s of 80% s p e e d d e t e c t o r , i n t e r n a l r e a d y l a t c h , XON
d e l a y c i r c u i t which a r e e n c l o s e d i n t h e c o n t r o l LSI, U1.
In t h e block
d i a g r a m , t h e s e c i r c u i t s a r e shown a s o n e b l o c k o f r e a d y d e t e c t o r .
The iclC s i g n a l f o r c o n t r o l l i n g t h e s p i n d l e motor i s i n p u t t o t h e r e a d y
d e t e c t o r which e n a b l e s t h e o p e r a t i o n o f a l l t h e above t h r e e c i r c u i t s .
As t h e motor s p e e d i n c r e a s e d , t h e 8 0 % s p e e d d e t e c t o r o p e r a t e s f i r s t , a n d
t n e n i n t e r n a l r e a d y l a t c h i s set when t h e i n d e x
becomes l e s s t h a n 250msec, a p p r o x .
(3)
pulse interval
( 1 . e . d i s k s p e e d r e a c h e s more t h a n
80% of 300rpm).
On t h e o t h e r hand, t h e MON d e l a y c i r c u i t g e n e r a t e s MON d e l a y 1 s i g n a l
(443
'L
(HIGH).
461msec d e l a y ) a f t e r t h e l e v e l change o f t h e MC s i g n a l t o TRUE
When t h e o u t p u t s of t h e MON d e l a y 1 a n d t h e i n t e r n a l r e a d y
l a t c h a r e c o i n c i d e n t w i t h e a c h o t h e r , FDD g o e s t o t h e p r e - r e a d y s t a t e
and t h e n i t r e a c h e s t o t h e r e a d y s t a t e a f t e r f u r t h e r 49
(MON d e l a y 2 ) .
The sum o f t h e d e l a y t i m e 1 s 492
%
5lmsec d e l a y
512ms.
DSEL i n p u t s i g n a l i s TRUE a f t e r t h e FDD r e a c h e s t o t h e r e a d y s t a t e ,
t h e Es i g n a l (which i n d i c a t e s t h a t t h e FDD i s i n r e a d / w r i t e r e a d y
If
s t a t e ) is o u t p u t from t h e FDD.
ready detector.
The
F i g . 2 1 0 shows t h e t i m i n g c h a r t of t h e
3s i g n a l
g o e s t o TRUE (LOW) i n t h e f o l l o w i n g
condition.
=(L)
= iMC(H)
I
Notes
RDYO:
*
80% s p e e d
*
MON d e l a y 11
*
MON d e l a y 2
*
E ( L )
1
I
Pre-ready
Ready a t LOW.
MC: Motor r o t a t e s a t HIGH.
80% s p e e d : Disk r o t a t i o n a l s p e e d i s more t h a n 80%, a p p r o x . of
300rpm.
MON d e l a y 1: I n t e r n a l s i g n a l o f LSI.
of motor-on
-
234
command.
-
443
461ms a f t e r a n i n p u t
MON d e l a y 2 :
I n t e r n a l s i g n a l o f LSI.
49
5lmsec a f t e r t h e ;?re-
9.
ready state.
DSEL: DRIVE
MC (Motor-on command)
SELECT i n p u t s i g n a l LOW
1
80% s p e e d d e t e c t i o n
Ready l a t c h i n U1
MON d e l a y 1 i n U1
Pre-ready
-
I
I
44 3246 l m s
_c
i n U1
I
MON d e l a y 2
(49%51ms)-ol
Ready s t a t e i n U1
DSEL i n p u t
I
Ready
I
I
(Ul-53)
I
IDXO o u t p u t
I
U
(U1-54)
Motor on
--Head
U
load enable
( w i t h HL s o l e n o i d model)
Notes
300rpm: B a n d F models
360rpm: G model
( F i g . 2 1 0 ) Ready d e t e c t o r waveforms
-
235
-
All t h e t h r e e c i r c u i t s of ready d e t e c t o r a r e r e s e t by t h e MC s i g n a l
g o i n t t o FALSE (LOW l e v e l ) .
-
236
-
2-2-2-7.
Stepping motor c o n t r o l c i r c u i t
Stepping motor c o n t r o l c i r c u i t c o n s i s t s of d i r e c t i o n l a t c h , i n t e r n a l
s t e p generator,
s h i f t r e g i s t e r , phase d r i v e s e l e c t o r , o v e r d r i v e t i m e r 2 ,
motor d r i v e r , and o v e r d r i v e c i r c u i t 2 .
All t h e above c i r c u i t s except f o r t h e motor d r i v e r and o v e r d r i v e c i r c u i t
2 a r e enclosed i n t h e c o n t r o l LSI, U1.
I n t h e block diagram, a l l t h e
enclosed c i r c u i t i n t h e c o n t r o l LSI except f o r t h e o v e r d r i v e t i m e r 2
a r e shown a s one block o f t h e s t e p p e r c o n t r o l c i r c u i e .
(1) D i r e c t i o n l a t c h
A t every i n p u t o f t h e STEP (-)
p u l s e from t h e h o s t c o n t r o l l e r , t h e
d i r e c t i o n l a t c h samples and holds t h e head seek d i r e c t i o n d e s i g n a t e d
by t h e DIRECTION SELECT
t o the bi-directional
(E)
signal.
The l a t c h e d o u t p u t i s s u p p l i e d
s h i f t r e g i s t e r and changes t h e a c t i v a t i n g o r d e r
o f t h e s t e p p i n g motor c o i l a s shown i n Fig.211.
( 2 ) I n t e r n a l s t e p generator
The c i r c u i t has following purposes.
(a) The c i r c u i t g e n e r a t e s an i n t e r n a l s t e p p u l s e 3msec l a t e r from t h e
STEP
(Ei)
nput
pulse.
This f u n c t i o n i s executed only when t h e
s i g n a l l e v e l a t t h e TDS t e r m i n a l i s L O W ( 4 8 t p i mode) and t h e s t e p p i n g
motor r o t a t e s f o r two s t e p space (3.6')
i n response t o one STEP p u l s e .
When t h e TDS i s H I G H ( 9 6 t p i mode), t h e s t e p p i n g motor r o t a t e s f o r one
s t e p space i n response t o one STEP p u l s e .
(b) The c i r c u i t g e n e r a t e s i n t e r n a l s t e p p u l s e s f o r a u t o - r e c a l i b r a t i o n a t
every 3msec.
The a u t o - r e c a l i b r a t i o n s t a r t s when t h e
Es i g n a l
from
t h e read w r i t e LSI i s changed from LOW t o H I G H a f t e r power-on and i t
c o n t i n u e s u n t i l t h e t r a c k 00 p o s i t i o n i s d e t e c t e d .
During t h e execution o f t h e a u t o - r e c a l i b r a t i o n ,
-
237
-
t h e FDD maintains
Not-ready
state
(E
output
H I G H ) and t h e S!EP
(E)
pulse
i n p u t from
t h e h o s t c o n t r o l l e r i s ignored.
( 3 ) S h i f t r e g i s t e r and phase d r i v e s e l e c t o r
S t e p p u l s e and t h e o u t p u t of t h e d i r e c t i o n l a t c h a r e s u p p l i e d t o t h e
s h i f t r e g i s t e r and t h e phase d r i v e s e l e c t o r t o be converted t o t h e
a p p r o p r i a t e timing s i g n a l s f o r u n i - p o l a r 1-phase d r i v e o f t h e 4-phase
s t e p p i n g motor.
These phase d r i v e s i g n a l s a r e o u t p u t from t h e c o n t r o l
LSI and s u p p l i e d t o t h e c o i l d r i v e r .
I n o r d e r t o improve t h e t o r q u e margin i n t h e seek o p e r a t i o n , p a r t i a l
2-phase d r i v e p e r i o d i s provided by t h e phase d r i v e s e l e c t o r only i n
t h e i n i t i a l s t a g e when t h e d r i v e phase is changed.
Refer t o Fig.211
f o r timing c h a r t .
( 4 ) Motor d r i v e r
Four o u t p u t s , PA, PB, PNA and PNB f r o m t h e c o n t r o l LSI, U1 a r e i n p u t t o
t h e motor d r i v e r IC, U 3 .
Refer t o Fig.208 a s t o t h e c o n s t r u c t i o n of U3.
(5) Overdrive timer 2
E x t e r n a l and i n t e r n a l s t e p p u l s e s a r e a l s o s u p p l i e d t o t h e o v e r d r i v e
t i m e r 2 i n t h e LSI.
The o v e r d r i v e t i m e r 2 is c o n s t r u c t e d with a
r e t r i g g e r a b l e counter.
During o n - s t a t e o f t h e t i m e r (24msec, a p p r o x . ) ,
SOD o u t p u t from t h e LSI goes t o H I G H l e v e l .
-
238
-
Refer t o Fig.212.
DIRECTION SELECT (51-18, m R )
Step-out
-
I
STEP ( J 1 - 2 0 , M )
D i r e c t i o n l a t c h i n Ul
U
Step-in
U
1
u 1 u
--I
-4
96tpi :
I n t e r n a l s t e p gen. i n U1
SOD(0verdrive t i m e r 2)
output
Coil d r i v e r i n p u t
PA
PB
PNA
PNB
48tpi :
I n t e r n a l s t e p gen.in U1
SOD(0verdrive t i m e r 2 )
output
Coil d r i v e r input
PA
PB
PNB
PNB
tl: I n t e r n a l s t e p d e l a y (3msec, a p p r o x . )
t 2 : P a r t i a l 2-phase a c t i v a t i n g p e r i o d (0.6ms,approx.)
(Fig.211) S t e p p i n g motor c o n t r o l c i r c u i t waveform
- 239 -
Final internal step
p u l s e i n U1
n
SOD o u t p u t
I
Applied v o l t a g e t o
motor c o i l s
I
*------I-----
4V,approx.
ov
( F i g . 2 1 2 ) S t e p p i n g motor o v e r d r i v e t i m i n g
Overdrive c i r c u i t 2
The SOD s i g n a l i s s u p p l i e d t o t h e o v e r d r i v e c i r c u i t 2 c o n s t r u c t e d by
U3 ( p i n s 2-15) a n d PNP t r a n s i s t o r 43 a n d i t makes Q3 t u r n on w h i l e t h e
SOD s i g n a l is H I G H l e v e l .
+12V power i s a p p l i e d t o t h e s t e p p i n g motor
c o i l s a t t h a t t i m e t o execute t h e seek and s e t t l i n g o p e r a t i o n s s e c u r e l y
with high torque.
A f t e r t h e c o m p l e t i o n of t h e s e t t l i n g , o n l y +5V power i s s u p p l i e d t o t h e
c o i l s t h r o u g h t h e d i o d e CR2 which minimize t h e power loss by s u p p l y i n g
o n l y t h e r e q u i r e d t o r q u e for holding t h e s t o p p o s i t i o n .
By t h e above
d e s i g n , h e a t r a d i a t i o n is d e c r e a s e d t o t h e minimum l e v e l a n d t h e power
consumption of t h e s t e p p i n g motor i n s e e k s t o p i s o n l y 0.25W, a p p r o x .
-
240
-
2-2-2-8.
Track counter
Track c o u n t e r memorizes t h e t r a c k p o s i t l o r . and o u t p u t s t r a c k s w i t c h
--
(SFO, SF1) s i g n a l s f o r t h e r e a d w r i t e c i r c u i t .
(TRACK 0 0 ) s i g n a l t o t h e h o s t c o n t r o l l e r .
I t also o u t p u t s
TOO
A l l t h e c i r c u i t s a r e enclosed
i n t h e c o n t r o l LSI, U1.
The o u t p u t s i g n a l f r o m t h e t r a c k 00 s e n s o r (TP3) i s s u p p l i e d t o t h e TOS
t e r m i n a l o f t h e LSI a n d i s o u t p u t a s t h e
latch c i r c u i t i n the track counter.
The
5s i g n a l
5s i p a l
through t h e g a t e and
g o e s t o TRUE i n t h e
following condition.
TOO(L)= TOS(H) *
Notes
TOO:
Step out
*
PA(H)
* DSEL(L)
T r a c k 00 d e t e c t e d a t LOW.
TOS: T r a c k 00 s e n s o r o u t p u t a t TP3 (TOS i n p u t o f L S I ) i s H I G H .
T r a c k 00 s e n s o r d e t e c t s t h e l i g h t d i s t u r b i n g w i n g o f t h e
h e a d c a r r i a g e ( t r a c k 00 p o s i t i o n ) .
Step out: Direction l a t c h output i s step-out direction.
PA: PA o u t p u t f r o m s t e p p i n g m o t o r c o n t r o l c i r c u i t i s H I G H .
Phase A
DSEL: DRIVE
When t h e
coil o f t h e motor i s energized.
SELECT i n p u t s i g n a l LOW.
s i g n a l goes t o TRUE (LOW), t h e t r a c k c o u n t e r s c o n s t r u c t e d
from up-down c o u n t e r s a r e r e s e t .
When a s t e p - i n o p e r a t i o n i s e x e c u t e d ,
t h e c o u n t e r s t e p s u p a n d t h e SFO/SFl o u t p u t s c h a n g e t o H I G H a t 4 4 t h
t r a c k f o r 9 6 t p i models ( 2 2 t h t r a c k f o r 4 8 t p i model).
2-2-1-1
as t o t h e f u n c t i o n o f t h e
SFO a n d
LOW a t T r .
(Table 207)
5a n d SF1 o u t p u t
-
241
-
Refer t o i t e m
signals.
, H I G H a t TR.
signals
2-2-2-3.
RD/INDEX g a t e
READ DATA
(G)a n d
INDEX
(E)
pulses
a r e o u t p u t to t h e h o s t c o n t r o l l e r
t h r o u g h t h e RD/INDEX g a t e which i s e n c l o s e d i n t h e c o n t r o l LSI, U1.
RD/INDEX
g a t e c h a n g e s i t s f u n c t l o n a c c o r d i n g t o t h e MKEN i n p u t l e v e l .
I n t h i s FDD, t h e MKEN t e r m i n a l i s f i x e d t o LOW l e v e l a n d t h e g a t e
functions as follows.
Notes
RDO:
-
N e g a t i v e READ DATA p u l s e o u t p u t t o t h e h o s t c o n t r o l l e r .
R D I : N e g a t i v e RD i n p u t from t h e r e a d i w r i t e LSI.
RDYO: RDYO o u t p u t
DSEL:
s i g n a l LOW.
FDD i s i n r e a d y s t a t e .
DRIVE SELECT i n p u t s i g n a l LOW.
IDXO: N e g a t i v e INDEX p u l s e o u t p u t t o
-
the host controller.
IDXS: N e g a t i v e p u l s e i n p u t from t h e i n d e x s e n s o r .
A l l t h e INDEX ( = ) o u t p u t
p u l s e s a r e v a l i d even i f t h e f i r s t o n e by
means o f i n d e x l a t c h c i r c u i t i n t h e LSI i n s p i t e o f t h e D R I V E SELECT
input timing.
F o r example, i f t h e FDD i s s e l e c t e d i n t h e m i d s t o f a n
IDXS ( i n d e x s e n s o r
host controller.
o u t p u t ) p u l s e , t h e p u l s e w i l l n o t be o u t p u t t o t h e
The p u l s e w i l l b e o u t p u t a f t e r o n e r e v o l u t i o n o f a
disk.
-
242
-
The
2-2-2-10.
Door-close c i r c u i t
Door-close
c i r c u i t i s o p t i o n a l l y u s e d i n some s p e c i a l models w i t h t h e
The c i r c u i t i s e n c l o s e d i n t h e c o n t r o l
door-close d e t e c t i o n switch.
L S I , U 1 a n d i t g e n e r a t e s DOOR CLOSE o r DRIVE STATUS s i g n a l u s i n g
-DCl/IXZ output
t e r m i n a l s a n d DcS/DCSW i n p u t t e r m i n a l s o f t h e L S I .
Refer
t o t h e S p e c i f i c a t i o n and Schematic diagram as t o t h e d e t a i l e d c o n d i t i o n
i n c l u d i n g t h e DC1
%
DC4 s t r a p s .
--
I n s t a n d a r d models w i t h o u t d o o r - c l o s e s w i t c h , DC1, DC2, and DCSW
t e r m i n a l s of t h e LSI a r e open a n d t h e d o o r - c l o s e c i r c u i t i s n o t u t i l i z e d .
-
243
-
O t h e r t e r m i n a l s a n d f u n c t i o n o f c o n t r o l LSI
2-2-2-11.
F o l l o w i n g e x p l a i n s o t h e r t e r m i n a l s a n d f u n c t i o n o f t h e c o n t r o l LSI, U l .
(1) OSCO/OSCl t e r m i n a l s a n d c l o c k g e n e r a t o r
I t s u p p l i e s c l o c k s f o r o p e r a t i o n t o all t h e c i r c u i t s i n t h e LSI by
e x t e r n a l ceramic o s c i l l a t o r .
(2)
Lvs
input terminal
LVS s i g n a l
i n p u t t e r m i n a l from t h e r e a d w r i t e LSI, U2.
When i t i s LOW, a l l t h e c i r c u i t s i n t h e c o n t r o l LSI a r e r e s e t .
(3)
SSI i n p u t
and
3o u t p u t
terminals
Terminals t o select t h e d i s k s i d e used.
The
o u t p u t s i g n a l k e e p s LOW l e v e l w h i l e t h e
i n p u t s i g n a l i s LOW which makes t h e
SSI
(SIDE ONE SELECT)
i n p u t of t h e r e a d w r i t e LSI LOW
t o s e t t h e FDD t o s i d e 1 o p e r a t i n g c o n d i t i o n .
However, w h i l e t h e WG o r EG o u t p u t s i g n a l from t h e c o n t r o l LSI k e e p s
H I G H l e v e l ( w r i t e o r erase o p e r a t i n g c o n d i t i o n ) , t h e
d o e s n o t change t h e s t a t e i n s p i t e o f t h e
t h e change o f s i d e 0
2 side
sso o u t p u t
signal
i n p u t s i g n a l and t h e r e f o r e ,
1 i s n o t e x e c u t e d t o complete t h e t u n n e l
erase o p e r a t i o n ( r e f e r t o i t e m 2 - 2 - 1 - 3 ) .
The s i d e - c h a n g e w i l l be done
a f t e r t h e WG a n d EG s i g n a l s r e t u r n t o LOW (read s t a t e ) by t h e s i d e s e l e c t
l a t c h i n t h e c o n t r o l LsI.
The above d e l a y o p e r a t i o n is n o t e x e c u t e d o n l y when t h e l e a d i n g e d g e of
the
E (INDEX)
the
SSI i n p u t
p u l s e i s detected d u r i n g t h e f o r m a t t i n g o f a d i s k , a n d
s t a t e i s informed t o t h e
delay t i m e .
( 4 ) DINV and DLEN i n p u t t e r m i n a l s
-
244
-
sso o u t p u t w i t h o u t
significant
T e r m i n a l s t o s e l e c t t h e d e s i g n a t i o n method f o r h i g h / n o r m a l d e n s i t y mode.
These t e r m i n a l s are n o t u s e d f o r t h i s FDD a n d t h e y a r e f i x e d t o H I G H
level.
-
( 5 ) WPO o u t p u t t e r m i n a l
T e r m i n a l t o o u t p u t t h e WRITE PROTECT
The
wpo o u t p u t
(e)
signal t o
the host controller.
g o e s t o LOW when t h e FPT s i g n a l from t h e f i l e p r o t e c t
s e n s o r i s LOW a n d when t h e DRIVE SELECT
(E)
input
s i g n a l i s TRCX
(LOW).
(6)
output terminal
I n v e r t o u t p u t t e r m i n a l o f t h e HD o u t p u t .
t h i s FDD.
( 7 ) TEST i n p u t t e r m i n a l
T h i s t e r m i n a l i s n o t u s e d f o r t h i s FDD.
( 8 ) VCC and GND t e r m i n a l
+5V a n d OV power t e r m i n a l s .
-
245
-
T h i s t e r m i n a l i s n o t used f o r
2-2-3. S e r v o C i r c u i t
The 3D motor A s s ' y ( s p i n d l e m o t o r ) o f t h i s FDD h a s t w o r o t a t i o n a l s p e e d s
which a r e 300rpm f o r B and F models and 360rpm f o r G model.
i s d e s i g n a t e d by
GJhen t h e
HSPD i s LOW.
HSPD
The s p e e d
i n p u t s i g n a l (57-5) from t h e PCBA MFD c o n t r o l .
is H I G H , t h e s p e e d i s 300rpm w h i l e i t i s 360rpm when t h e
S t a r t / s t o p o f t h e r o t a t i o n i s c o n t r o l l e d by t h e MC s i g n a l
s u p p l i e d t h r o u g h t h e motor-on g a t e i n t h e c o n t r o l LSI.
The s e r v o c i r c u i t aims t o m a i n t a i n t h e r o t a t i o n a l s p e e d o f t h e s p i n d l e
motor a t a d e t e r m i n e d c o n s t a n t s p e e d , a n d t h e c i r c u i t i s mounted on t h e
PCBA a s s e m b l e d w i t h t h e s p i n d l e motor.
The s p i n d l e motor i s a l o n g l i f e DC b r u s h l e s s motor h a v i n g 3-phase c o i l s
and b i - p o l a r d r i v e s y s t e m .
IC.
The c o i l s are d r i v e n by t h e e x c l u s i v e s e r v o
E n e r g i z a t i o n a n d m a g n e t i z e d d i r e c t i o n of t h e c o i l s a r e c o n t r o l l e d
by t h e s i g n a l from t h e h a l l e l e m e n t s mounted on t h e s e r v o PCBA a r o u n d
t h e r o t o r so t h a t t h e y a r e changed c o r r e s p o n d i n g t o t h e d e s i g n a t e d
rotational direction.
The r o t a t i o n a l s p e e d i s m a i n t a i n e d s t a b l y a n d p r e c i s e l y .
The f e e d b a c k
s i g n a l from t h e f r e q u e n c y g e n e r a t o r (FG) p r i n t e d a r o u n d t h e r o t o r i s
c o n v e r t e d i n t o t h e d r i v e v o l t a g e (F-V c o n v e r s i o n ) by s e r v o I C , and
s u p p l i e d t o t h e d r i v e c o i l s through t h e phase compensation c i r c u i t
Several manufacturers'
s p i n d l e m o t o r s a r e u s e d i n FD-55R series f o r t h e
Though t h e s e m o t o r s are t h e same i n
s t a b l e supply o f t h e motor.
f u n c t i o n a n d p e r f o r m a n c e , t h e y a r e d i f f e r e n t i n e x t e r n a l view.
-
246
-
2-3.
FUNCTION OF TEST POINTS AND VARIABLE RESISTORS
F o l l o w i n g shows t h e m o u n t i n g p o s i t i o n of t h e t e s t p o i n t s a n d v a r i a b l e
resistors.
TP1:
TP2:
TP3:
TP4:
TP5:
TP6:
TP7:
TP8:
Q
R1
Index
E r a s e gate
T r a c k 00
Pre-amp.
Pre-amp.
DC OV
Differentiator
Differentiator
LPCB
issue
J
( F i g . 2 1 3 ) L o c a t i o n of t e s t p o i n t s a n d v a r i a b l e r e s i s t o r s
-
247
-
2-3-1, Function of T e s t P o i n t s
Eight t e s t p o i n t s (one f o r DC OV) a r e equipped on t h e PCBA MFD c o n t r o l
f o r t h e check and adjustment o f t h e waveforms of t h e F D D .
(1) T P 1 ( I n d e x )
T e s t p o i n t to observe t h e o u t p u t of t h e index s e n s o r ( p h o t o - t r a n s i s t o r ) .
When t h e index h o l e i s d e t e c t e d , n e g a t i v e going p u l s e i s observed.
The p h o t o - t r a n s i s t o r
i s mounted on t h e PCBA f r o n t OPT and t h e LED i s
mounted on t h e DD motor A s s ' y ( s p i n d l e m o t o r ) .
TP1 i s used f o r t h e following purposes.
( a ) Confirmation of t h e d i s k r o t a t i o n a l speed.
(b) Rough confirmation and adjustment of t h e index b u r s t d e t e c t i o n timing.
B u r s t timing i s a d j u s t e d by t h e f i x i n g s c r e w s of t h e PCBA f r o n t OPT.
(Use INDEX i n t e r f a c e s i g n a l f o r p r e c i s e confirmation and adjustment)
TP 1 ( Index)
U
U
Index
interval
U
L
Pulse width
( F i g . 2 1 4 ) Typical waveform o f TP1 (Speed o b s e r v a t i o n )
TP4 o r 5
(Pre-amp. o u t p u t )
.:
-
Index b u r s t delay
(Fig.215) Typical waveform o f TP1
(Rough o b s e r v a t i o n o f b u r s t timing)
-
248
-
.
Models
It e m s
B and F models
G model
Index i n t e r v a l
200 2 3ms
166.7 5 2.5111s
Index b u r s t d e l a y
200 f 200ps
165 2 1 6 5 ~ s
(Table 208) Index timing
( 2 ) TP2 (Erase g a t e )
T e s t p o i n t t o observe t h e o u t p u t of t h e e r a s e g a t e .
When TP2 i s HIGH l e v e l , e r a s e c u r r e n t flows through t h e e r a s e head.
This TP i s used f o r t h e check of t h e r e q u i r e d d e l a y time of t h e e r a s e
g a t e s i g n a l a g a i n s t t h e WRITE GATE (WG) s i g n a l .
WRITE GATE i n p u t s i g n a l
-.-
TP2 (Erase g a t e )
On-delay
Off-delay
~
-
9
(Fig.216) Typical waveform of TP2
Mode 1s
Delay
B and F models
G model
On-delay
240
%
290~s
200
%
240~s
Of f-delay
890
%
990~s
530
%
590~s
(Table 209) Erase g a t e d e l a y
( 3 ) TP3 (Track 00 s e n s o r )
T e s t p o i n t t o observe t h e o u t p u t of t h e t r a c k 00 s e n s o r (photointerrupter)
.
-
249
-
The s i g n a l l e v e l a t t h i s TP i s o p p o s i t e i n phase t o t h a t of t h e TRACK 00
(TOO) o u t p u t s i g n a l .
When t h e head i s on t r a c k 00 o r around t r a c k 00
p o s i t i o n , TP3 goes t o H I G H l e v e l .
The v o l t a g e o f TP3 should be more than 4 V a t t r a c k 00 and l e s s than 0.5V
a t t r s c k 04 ( 9 6 t p i ) o r a t t r a c k 02 ( 4 8 t p i ) .
4.0V, M i n .
7p_
TP3 (Track 00 s e n s o r )
0.5V, Max.
Track 00
Track 04
02 ( 9
46
8tpi)
(Fig.217) Typical waveform of TP3
Notes: 1. The TRACK 00 o u t p u t s i g n a l goes t o TRUE (LOW l e v e l ) only when
t h e phase A ( P A ) c o i l o f t h e s t e p p i n g motor i s energized and
t h e d i r e c t i o n l a t c h i s s e t t o t h e step-out d i r e c t i o n .
Therefore, t h e l e v e l change timing of t h e TRACK 00 s i g n a l i s
n o t c o n s i s t e n t with t h a t o f t h e TP3 s i g n a l .
2 . Sense timing of t h e t r a c k 00 p o s i t i o n w i l l change i f you loosen
t h e f i x i n g screws o f t h e PCBA MFD c o n t r o l .
t h e t r a c k 00 s e n s o r i s mounted on t h e PCBA.
T h i s i s because t h a t
Be s u r e t o r e a d j u s t
t h e t r a c k 00 s e n s o r timing according t o item 3-4-14.
( 4 ) TP4, TP5 ( P r e - a m p l i f i e r )
Test p o i n t t o observe t h e read p r e - a m p l i f i e r
The p r e - a m p l i f i e r
output signals.
has two o u t p u t s of t h e o r d e r of s e v e r a l dozen t o
s e v e r a l hundred mVp-p,
and they d i f f e r i n phase by 180° ( o p p o s i t e p h a s e ) .
Both o u t p u t s a r e observed a t TP4 and TP5 r e s p e c t i v e l y .
For an a c c u r a t e
o b s e r v a t i o n of t h e read waveforms, use two channels of an o s c i l l o s c o p e
with one channel s e t t o I n v e r t mode and Add both channels.
t e s t p o i n t for t h e o s c i l l o s c o p e ground.
-
250
-
Use TP6 ( O V )
TP4 and TP5 a r e used f o r checking v a r i o u s c h a r a c t e r i s t i c s o f t h e read/
w r i t e head and a l s o f o r t h e check and adjustment of t h e head seek
mechanism such a s t r a c k alignment.
TP4, TP5
(Pre-amp .)
2 . Sv,approx.
(Fig.218) Typical waveform o f TP4 and TP5
( 5 ) TP7, TP8 ( D i f f e r e n t i a t i o n a m p l i f i e r )
T e s t p o i n t s t o observe t h e d i f f e r e n t i a t i o n a m p l i f i e r o u t p u t s i g n a l s .
Like t h e p r e - a m p l i f i e r ,
t h e d i f f e r e n t i a t i o n a m p l i f i e r a l s o has two
o u t p u t s o f t h e o r d e r of s e v e r a l hundred mVp-p t o s e v e r a l Vp-p which
d i f f e r i n phase by 180".
Both o u t p u t s a r e observed a t TP7 and TP8
respectively.
For an a c c u r a t e o b s e r v a t i o n of t h e waveforms, use two channels of t h e
o s c i l l o s c o p e with one channel s e t t o I n v e r t mode and Add both channels.
Use TP6 ( O W t e s t p o i n t f o r t h e o s c i l l o s c o p e ground.
TP7 and TP8 a r e used f o r checking t h e t o t a l o p e r a t i o n o f t h e r e a d / w r i t e
head and t h e read a m p l i f i e r and f o r t h e check and adjustment of t h e head
seek mechanism such a s t r a c k alignment.
TP7, TP8
( D if f e r e n t i a t o r ) J
2.5v,
approx.
(Fig.219) Typical waveform o f TP7 and TP8
( 6 ) TP6 (OV)
I t i s used a s t h e ground t e r m i n a l f o r measurement equipment.
-
251
-
Be sure
to use a small size c l i p to obtain a probe ground of the equipment.
-
252
-
Function of Variable Resistor
This item is applied only for a model with variable resistor on the
PCBA MFD control.
The variable resistor is correctly adjusted before the shipment of the
FDD and fundamentally it shall not be readjusted except for by a trained
technician.
R1 (for asymmetry adjustment)
Variable resistor for adjusting the asymmetry of the read data pulse.
Write and read 1F data and observe the pulse intervals at the READ DATA
output line.
Then adjust the variable resistor so that the read data
asymmetry takes the minimum value in Fig.220.
Repeat each adjustment
alternately for side 0 and side 1 heads to obtain the minimum asymmetry
for both sides.
Refer to item 3-4-9.
READ DATA
1F interval
1
3
2
Asymmetry at adjustment
B,F models: O.Gps,Max.
G model: 0.3~s,Max.
Trigger
Note: When the READ DATA waveform is observed at the DOUT terminal
of the SKA, positive going pulse is observed.
(Fig.220) Read data asymmetry
- 253 -
TEAC FD-55BR-521
DRAWINGS
&
PARTS
i
LIST
REV.A
TABLE OF CONTENTS
Page
Title
....................................................
4-1
CONFIGURATION
4-2
MECHANICAL BREAK-DOWN AND PARTS L I S T
4-2-1
4-2-2
4-3
.............................
FDD ............................................................
Screws and Washers .............................................
..................................................
ME'D Control #N (P/N 15532097-02) ..........................
Front O P T #N ( P / N 15532091-00) ............................
PCBA PARTS L I S T
4-3-1
PCBA
4-3-2
PCBA
4-4
PARTS LOCATION AND SCHEMATIC DIAGRAMS
4-5
RECOMMENDABLE SPARE PARTS L I S T
............................
...................................
401
406
406
411
412
413
414
415
423
4-1. CONFIGURATION
Following shows the configuration of the main parts of FD-55R series.
(Refer to Fig.401
%
Fig.404).
Refer to items 4-2 and 4-3 as to detailed
break-down.
Frame
DD motor Ass'y (Spindle motor)
Stepping motor Ass'y
Set arm Ass'y-
Collet Ass'y
Holder Ass'y
Lever shaft Ass'y
Clamp arm Ass'y
FD-55R
CSS sub ASS' y
Front bezel Ass'y
Front lever Ass'y
Head carriage Ass'y
Head carriage Ass'y (main structure)
PCBA MFD control #N
PCBA front OPT #N
(Table 401) Main parts configuration of FD-55R series
- 401 -
l e p r o t e c t sensor
PCBA f i x i n g screws
Index s e n s o r
PCBA f r o n t OPT #N
F r o n t b e z e l Ass'y
Front l e v e r
CSS sub Ass'y
J5(PCBA f r o n t OPT)
C o l l e t Ass'y
J1 ( S i g n a l i n t e r f a c e ,
S e t arm Sub Ass'y
(Fig.401)
E x t e r n a l view (No.1)
- 402 -
Spindle (DD motor A s s ' y )
DD motor A s s ' y
fixing screws
Index sensor (LED)
Lever shaft
Head carriage Ass'y
Stepping motor Ass'y
-
403
-
DD motor A S S ' Y
Front bezels cfri x
e iw
ng
sA
A
/
,-J6
(Stepping motor)
Head carriage A s s ' y
Track 00 sensor
57 (Spindle m t o r )
PCBA f i x i n g screws
Y'
L t e p p i n g motor
f i x i n g screws
MFD control #N
(Fig. 403) External view (No.3 )
- 404 -
f
Name p l a t e
L
Parts number of the FDD
(Fig-404) External view (~0.4)
- 405 -
4-2. MECHANICAL BREAK-DOWN AND PARTS LIST
4-2-1. FDD
(Fig.405) Mechanical section break-down
-
406
-
Nos.
1
Parts Nos.
Parts name and ratings
Q'tY
16153371-00 F r a m
Description
1
~~
29
15532097-02
PCBA WD control #N
1
30
15532091-00
PCBA front OPT #N
1
31
17967267-68
Front bezel Ass'y
1
32
17987261-68
Front lever Ass'y
1
( T a b l e 402) Parts l i s t of the FDD
-
407
-
J
Note: Head carriage A s s ' y can be broken-down t o the p a r t s level shown i n
Table 402-C.
However, order the maintenance p a r t s as an p a r t s number
i n Table 4 0 2 including s m a l l parts.
This i s because t h a t the head
carriage and two guide s h a f t s are supplied i n a p a i r f o r the matched
hole combination.
Two guide shafts a r e placed into the carriage holes
at the shipment and the shafts are selected for each hole.
sure not t o ignore the combiantion when you use them.
- 408 -
Be
SPARE PAGE
- 409 -
(Table 402-C)
Parts l i s t of head carriage Ass'y BR
- 410 -
4-2-2. Screws and Washers
Nos.
Parts Nos.
Parts n u 8 and ratings
S 1 16400304
[email protected]
s
18(o0305
Screcr.mn36SMc
S 3 164o0308
Screrr.mn3rBSaC
2
Descr i pt ion
s 7
S 8
s 9
-
s 11
s 12
16351180
E-ring 4J
~
~
~~
S 13 l(1196080- 00 Hy lar washer 0.11*4.1*8
~~
For adjustment
ls(SBoB1-00 Wlar washer 0.2l*4.1*8
For adjustment
16498081- 01 Hylar masher 0 . ~ 1 * 4 . 1 * 8
For adjustment
16196618-00 Nylon masher 0.3T*4.ld
For adjustment
18198082-00 Wlar washer 0.3Sl*4.188
For adjustment
- 16496818-01
Nylon washer O.41*4.1*8
For adjustment
(Table 403) Parts l i s t of screws 6 washers
-
411
-
4-3.
PCBA PARTS LIST
Following shows t h e p a r t s l i s t of PCBAs.
Notes f o r Table:
1. "REV" (PCBA Revision No.)
i n t h e Description column i n d i c a t e s t h a t
t h e p a r t s has been r e v i s e d i n t h e p a s t .
The r e v i s i o n number i s
i n d i c a t e d on t h e PCB i n one o r t w o a l p h a b e t s following t h e PCBA
v e r s i o n number.
The e a r l i e r t h e c h a r a c t e r i n t h e a l p h a b e t s i s ,
t h e o l d e r t h e r e v i s i o n of t h e assembly.
2 . The newest assembly p a r t s have
"%"
mark a f t e r , t h e "REV".
P a r t s with o l d r e v i s i o n number a r e used only i n t h a t r e v i s i o n .
3. In Tables having p l u r a l PCBA v e r s i o n s , p a r t s w i t h PCBA v e r s i o n i n
t h e Description column a r e e x c l u s i v e p a r t s for t h e v e r s i o n , while
p a r t s without PCBA v e r s i o n a r e conanon p a r t s .
- 412 -
4-3-1.
PCBA MFD C o n t r o l
Nos.
#N (P/N 15532097-02)
Parts ram and ratings
Parts WOS.
U
1
13442777-01
IC IRIIY(#M
U
2
13442429-00
IC -1CK
u
3
13428129
Transistor array 115153(P
Q 3
13421214
Transistor 2SA88IQ. R
I
I
I
13193~2
I
13419323
m1
I
I
I
I
I
Photo-interrupter c P 1 s
I
Photo-interrupter T L P ~
I
13411386
Dioda 1SSl3B
CR3
130403?7
Jumper wire JPI-01
cR4
130403?7
Jumper wire JH-01
cR5
13040377
Jumper wire JPI-01
CRAl
13411398
Diode pair (K) 1SS233F
13411409
Diode pair (K) MI321
I
RA 1
I
I
I second source
I
CR 2
I
I
r
I
I
Description
1
I
Second source
[
I
Resistor array 8-1K o h s J
13498881
- 1
I
(Table 4 0 4 ) PCBA MFD c o n t r o l # N parts l i s t (1/5)
-
413
-
I
I
Nos.
Parts Nos.
Parts name and ratings
RA 3
13498186-00
Resistor array T-9186
R 3
11186183
Resistor RD 1/51
18K ohms J
R 5
11186183
Resistor RD 1/5U
18K o h s J
R 6
11982968
Resistor RN 1/41
2.W o h s F
R 8
11186222
Resistor RD 1/51
2.B o h s J
R 9
11050121
Resistor RN 11 120 o h s J
119asO6s
Resistor RN 11 120 ohm J
R 10
11186223
Resistor RD I/%
22K o h s J
R 12
11186472
Resistor RD 1/51
4.7K o h s J
R 13
11186159
Resistor RD 1/51
1.5 ohms J
R 14
11186151
Resistor RD 1/51
150 ohms J
Description
I
I
Second source
( T a b l e 404) PCBA MFD c o n t r o l #N parts l i s t (2/5)
- 413B -
Nos.
Parts Nos.
Parts n u e and ratings
Description
Jn-01
R25
13010373
Jumper mire
C 2
12907000
Capacitor CE 25V 33crF M
--
~
C 4
12907078
Capacitor CE 1OV lW&F N
5
12907113
Capacitor CC 2 5 V 0.022pF Z
C 8
12907053
Capacitor CT 1OV 22crF N
C 7
12907113
Capacitor CC 2 5 V 0.022crF Z
C 9
12907098
Capacitor CC 5OV 470PF J
C10
12907098
Capacitor CC 5OV 470PF J
c11
12907648
Capacitor CC 12V 0.1crF M
c
12
12907104
Capacitor CC 16V 22OOPF K
C13
12907648
Capacitor CC 12V 0.1crF M
C 14
12907104
Capacitor CC 16V m)oPF K
C 15
12907104
Capacitor CC 16V 22OOPF K
C 16
12567222
Capacitor 04 5OV m)oPF C
c
18
12567152
Capacitor CP 5OV 15ooPF C
C 20
12907113
Capacitor CC 25V 0.022crF Z
C 21
12907113
Capacitor CC 2 5 V 0.022crF Z
C
( T a b l e 404) PCBA MFD control #N parts list ( 3 / 5 )
- 413C -
~~
Nos.
Parts Nos.
Parts name and ratings
C 22
12907113
Capacitor CC 25V 0.022uF Z
C23
12907081
Capacitor CC 5OV 1w)PF 1
C24
12907088
Cawitor CC 5OV lOOPF J
c 25
12467101
Cawitor CQ 5OV lOOPF
C28
12906659
Capacitor CE 5OV 6.8uF V
Description
~~
G
~
c29
12906659
Capacitor CE 5OV 6.8uF V
C 30
12907113
Cawitor CC 2 5 V 0.022uF Z
C 31
12907113
Cawitor CC 25V 0.022,uF Z
C 32
12907113
Capacitor CC 2SV 0.022uF Z
L 1
ll!384!38
Resistor 0 ohm
L 2
11984508
Resistor 0 ohm
L 3
14723892
Coil chalk 330uH J
L 4
14723892
Coil chalk 3 3 0 ~ c H J
L 5
14723692
Coil chalk 3 3 0 ~ H J
-~
1
13236004-00
Ceramic oscillator KBR-480
1 2
13121916
Connector 4P
J 4
13121235
Connector 11ZP polarizing
J 5
13123219
Connector 5P
Y
1
( T a b l e 404) PCBA MFD c o n t r o l #N parts list (4/5)
-
413D
-
Nos.
Parts Nos.
.
Parts
J 6
13121191
Connector 6P
J 7
13123257
Connector 5P
rime
a d ratings
Description
I
U1
11!384508
Resistor 0 ohm
DO, D1
13189406
4-Post pins
ML, RY
13189406
4-Post pins
1U
11984508
Resistor 0 ohm
TP1-TP8
13189108
8-Post pins
Unreplaceable
Unreplaceable
( T a b l e 404) PCBA MFD c o n t r o l #N parts l i s t ( 5 / 5 )
- 413E -
SPARE PAGE
- 413F -
4-3-2. PCBA F r o n t OPT #N (P/N 15532091-00)
Nos.
Parts Nos.
Parts
IUW
and ratings
Description
w51
13419080
Phot transistor
w52
13419060
Phot transistor
13040460
Jumper wire 5 lines 7
7
n
16787503-00
Index holder
(
16787502-00
Sensor holder
( For w52
For w51 1
1
(Table 405) PCBA F r o n t OPT XN parts list
-
414
-
4-4. PARTS LOCATION AND SCHEMATIC DIAGRAMS
Notes:
1. One of t h r e e types (Type S, K, and GI of DD motor A s s ' y a r e used f o r
the FDD.
These t h r e e types have compatibility w i t h no r e l a t i o n t o
r e v i s i o n number,
2. For Schematic diagram, p a r t s with an a s t e r i s k
each PCBA version.
(*)
are different i n
Refer t o VERSION TABLE.
I f t h e p a r t s w i t h an a s t e r i s k ( * ) a r e not l i s t e d i n t h e corresponding
column of the VERSION TABLE, i t means t h a t they a r e not used i n t h a t
PCBA version.
3 . Resistor (R) and r e s i s t o r a r r a y (RA) values a r e i n Ohms, 1/8W o r
l a r g e r , 25%(J), unless otherwise s p e c i f i e d .
4.
Capacitor ( C ) values a r e i n Microfarads,
5OV o r higher, f l O % ( K ) ,
unless otherwise specified.
5. Tolerance symbols f o r R , RA, and C a r e :
F: 21%
v:
+20-10%
J: 25%
G: 22%
M: 220%
-
K: f10%
2: +80-20%
415
-
VERSION
REVISION
- 416 -
PCBA DD MOTOR SERVO, PARTS LOCATION (Type K)
R
-\EV
ISI ON
-
416B
-
PCBA DD MOTOR SERVO, PARTS LOCATION ( Type G)
- 416C -
SPARE PAGE
-
416D
-
SPARE PAGE
- 416E -
PCBA DD MOTOR SERVO, SCHEMATIC (Type S)
f
0102
,
I
-’
m
5
r- K
0
Pi15
I
l
Pi12
4. 71:
5v
uc
12v
1
UlOl
W
M51784P
2
ov
-
417
-
FCBA DD MOTOR SERVO, SCHEMATIC (Type K)
HSPO 5
0
Ill05 1.51-31
4
PCBA DD MOTOR SERVO, SCHEMATIC (Type G)
12v
ov
RlM 2.2K
- 417C -
SPARE PAGE
-
417D
-
SPARE PAGE
-
417E
-
PCBA HFD CONTROL #N, PARTS LOCATION
/;..e
....i i
......a
............_^._.
e!11:
44
L v e r si o n
-
418
-
PCBA FRONT OPT # N ,
PARTS LOCATION
E
"0
LED51
s
Wi
PO52
R E V I SI ON
VERSION
0
-
-
419
-
PCB
ISSUE
SECTION 3
MAINTEN AN CE
3-1. GENERAL
3-1-1. Periodic Maintenance
The FDD is designed to be free from periodic maintenance for 5 years
such as replacement of parts, grease-up, etc. when it is operated at a
normal operation duty.
However, cleaning of the magnetic head is recomended using a cleaning
disk since it may be effective to improve the reliability of data.
If some of the parts in the FDD are operated at a specially heavy duty,
or if the FDD is operated over 5 years, it is recomended to replace
the wear parts according to Table in item 4-5.
Replacement of parts
should be executed according to item 3-5 referring to precautions in
item 3-2.
I Periodic maintenance items 1
E a n i n g of magnetic head I
~~
Recommended cycle
~
Replacement of wear parts
~~
1
Required time
~
Refer to item 3-3.1
5 minutes
Refer to items 4-5 and 3-5.
(Table 3101) Periodic maintenance items
-
3101
-
I
1
3-1-2. Check and Adjustment
Table 3102 shows all of the check and adjustment items.
not require periodic maintenance.
These items do
Check and adjustment should be done
when required during replacement of the maintenance parts or during
trouble shooting referring to items 3-2 and 3-4.
The numbered procedure in Table 3102 shows a typical procedure of the
general check and adjustment all over the FDD.
items of steps 1
After the mechanical
4, electric performance items of steps 5
15 should
be done.
I Required
kteps C h e c k and-adjustment items
I
1
II
time /Referred items
6
Check of disk rotational speed
7
Check of erase gate delay
3 minutes
3-4-7
8
Check of head touch
3 minutes
3-4-8
9
Check of asymmetry
3 minutes
3-4-9
10
Check of read level
3 minutes
3-4-10
11
Check of resolution
12
Check and adjustment of track
alignment
13
14
3 minutes
1
~
I
1
minutes
3 minutes
Check and adjustment of index burst
(Table 3102) Check and adjustment items
-
3102
-
3-4-6
1
3-4-11
3-4-12
Check and adjustment of track 00
sensor
Check of track 00 stopper
3 minutes
I
II
3-4-13
3-4-14-3-4-15
I
I
I
1
I
Maintenance J i g s and Tools
3-1-3.
The following a r e t h e j i g s and t o o l s required f o r adequate maintenance
of t h e FDD.
3-1-3-1.
Equipments
(A) When conventional Simulator KA (abbreviated t o SKA) i s used:
1
I
SKA model
I
SKA-A"JF
I
SKA-G
Applied FDD model
FD-55BR/FR
( o r SKA-GFII, G mode)
1
I
FD-55GR
(Table 3103) Conventional SKA model and applied FDD
Notes: 1. A l l SKAs a r e generally c a l l e d a s SKA i n the following explanat i o n unless otherwise designated.
2. SKAs i n Table 3103 can be used also f o r a l l t h e conventional
FD-55 s e r i e s .
( 2 ) Accessories f o r SKA
SKA needs the following accessories f o r operating t h e FD-55R s e r i e s .
The following accessories a r e common f o r all t h e 55R s e r i e s except f o r
s p e c i a l models.
( a ) SKA/FDD i n t e r f a c e cable #O, P/N 15922337-00
(b) Check cable #5, P/N 15922611-00
Check cable #5 includes SKA/FDD power cable.
( 3 ) Oscilloscope
(two channels)
-
3103
-
(4) DC power supply
(a) Commercially available DC power supply or any of the following TEAC
power unit can be used.
PS3, o r PS3-MINI
TEAC power unit: PS-11,
(b) Minimum required current for SKA operation.
+12V: 0.2A (for SKA)
+5V: 1.2A (for SKA)
+ a(for FDD)
+
-,:for FDD)
(c) Required accessory: PS/SKA power cable
(5) Thermometer and hygrometer
-
3104
-
(B) When Simulator KA3 ( a b b r e v i a t e d t o SKA3) i s used:
Notes: 1. Conventional SKAs and SKA3 a r e g e n e r a l l y c a l l e d a s SKA i n t h e
following e x p l a n a t i o n u n l e s s o t h e r w i s e d e s i g n a t e d .
2 . SKA3 b a s i c a l l y f u n c t i o n s l i k e a s a c o n v e n t i o n a l SKA and it i s
improved i n many p o i n t s when compared.
Also t h e SKA3 can be a p p l i e d t o a l l FDD models i n c l u d i n g 3.5"
FDDs s u p p l i e d from TEAC by r e p l a c i n g a small c a r t r i d g e f o r
each FDD model.
(1) sKA3
The following I s s u e and Version s h a l l be used f o r SKA3 i t s e l f and
i n s t a l l e d ROM.
(a) SKA3 hardware: I s s u e E o r l a t e r
(b) ROM i n s t a l l e d : Version V1.06 o r l a t e r
Note: I s s u e and Version a r e shown on bottom p l a t e of t h e SKA3.
( 2 ) Accessories f o r SKA3
SKA3 needs t h e following a c c e s s o r i e s f o r o p e r a t i n g t h e FD-55R s e r i e s .
( a ) Cartridge
C a r t r i d g e i s c o n s t r u c t e d with small p r i n t e d c i r c u i t board t o s e l e c t
a f u n c t i o n parameter o f t h e SKA3 matching with a t e s t e d FDD.
s h a l l be a t t a c h e d t o r e a r s i d e of t h e SKA3 b e f o r e o p e r a t i o n .
Table 3104 shows t h e s e l e c t i o n o f t h e c a r t r i d g e .
( b ) SKA/FDD i n t e r f a c e c a b l e #0, P/N 15922337-00
( c ) SKA/FDD power c a b l e , P/N 15922336-00
( d ) Check cable #8, P/N 15922670-00
-
3105
-
It
I Applied model 1
I Name of cartridge
I
I PCBA cartridge #1, FD-55V AB I
15532077-10
PCBA cartridge #1, FD-55V EF
15532077-11'
FD-55FR
PCBA cartridge # 1 , FD-55V G
15532077-12
FD-55GR
P/N
I
FD-55BR
I
(Table 3104) Selection of SKA3 cartridge
(3) Oscilloscope (two channels)
( 4 ) M3 power supply
(a) Commercially available DC power supply or TEAC power unit (PS3 or
PS3-MINI can be used.
Note: TEAC power unit, PS-I1 cannot be applied for the SKA3 as a rule,
because of small current capacity.
If it is temporarily used,
connect PSB output of the PS-I1 to the PSB input of the SKA3 and
set the FD PWR switch to the PSB side.
(b) Minimum required current for SKA3 operation
+12V: 0.25A (for SKA3) + a(for FDD)
+5v: 2.OA (for SKA3) + u(for FDD)
(c) Required accessory: PS/SKA power cable.
( 5 ) Thermometer and hygrometer
- 3106 -
(C) When an SKA is not used:
(1) FDD controller and DC power supply (user's system)
(2) Oscilloscope (.two channels)
(3) Frequency counter
( 4 ) Digital voltmeter
(5) Thermometer and hygrometer
-
3107
-
3-1-3-2. Tools, jigs, and disks
(1) Tools
(a) Cross-point screwdriver, M2.6 and M3
(b) Common screwdriver, small size
(c) Hexagon wrench key, 1.5mm
(d) A pair of tweezers
(e) Round nose pliers
(f) Cutting pliers
(9) Cutter knife
(h) Solder and soldering iron
(i) Scale, small size
(2) Special jigs
(a) Max. media jig for adjustment (Jig.C, P/N 17890746-00)
(b) Max. media jig for check (Jig E, P/N 17890746-02)
(c) Alignment adjustment jig (P/N 17851100-00)
( 3 ) Disks
(a) Work disk (commercially available disk)
1) For Normal density (FD55BR/FR)
ii) For High density (FD-55GR)
(b) Double sided cleaning disk (commercially available, dry type)
(c) Level disk
1) For Normal density (FD-SSBR/FR), P/N 14900015-00
ii) For High density (FD-SSGR), P/N 14900015-01
-
3108
-
Note: Commercially a v a i l a b l e d i s k s may be used i f t h e r e i s no doubt.
( b ) Alignment d i s k
i ) For double s i d e d , 4 8 t p i (FD-55BR1, P/N 14900016-21
ii) For double s i d e d , 9 6 t p i (FD-55FR), P/N 14900016-24
iii) For High d e n s i t y , double s i d e d , 9 6 t p i (FD-SSGR), P/N 14900016-25
( 4 ) Other a r t i c l e s used d u r i n g maintenance
( a ) Absolute a l c o h o l (Ethanol)
( b ) Cottom swab o r gauze
(c) Locking p a i n t (Three Bond, 1401B)
( d ) Screws and washers (Refer t o Table 403 i n P a r t s L i s t ) .
( e ) O i l (Kanto Chemicals Co., FLOIL 946P, TEAC P/N 10854022)
( f ) Grease (Kyodo Yushi, Co., Multemp P2B, TEAC P/N 10857031)
- 3109 -
3-2.
PRECAUTIONS
3-2-1.
Torque Applied t o Screws and Locking P a i n t
(1) The f o l l o w i n g t o r q u e s h o u l d be a p p l i e d t o s c r e w s , u n l e s s o t h e r w i s e
specified
.
(Table 3201) Torque a p p l i e d t o screws
( 2 ) Apply f r e s h l o c k i n g p a i n t t o t h e f o l l o w i n g d e s i g n a t e d p o i n t s a f t e r
tightening o r adjusting the screw.
(a) I n s t a l l a t i o n screws o f s t e p p i n g motor: M 3 , 2 p o i n t s
( b ) Adjustment s c r e w o f arm l i f t e r
(Only f o r models w i t h head l o a d s o l e n o i d ) : M 3 s e t s c r e w
(c) S t e e l b e l t and c a r r i a g e : 4 p o i n t s , r e f e r t o i t e m 3-5-1.
Note: Before a p p l y i n g a d r o p o f l o c k i n g p a i n t , be s u r e t o remove o l d l o c k i n g
p a i n t on t h e screw and around it.
-
3201
-
3-2-2.
Handling o f Connectors
3-2-2-1.
Location o f connectors
The f o l l o w i n g c o n n e c t o r s a r e u s e d i n t h e FDD.
F i g . 3 2 0 1 shows t h e
location.
( a ) J1: I n t e r f a c e c o n n e c t o r
(b) 5 2 : Power c o n n e c t o r
(c) 53: I C s o c k e t f o r t e r m i n a t o r network ( o n l y f o r f u l l s t r a p models)
( d ) 54 : Head c o n n e c t o r
( e ) J 5 : PCBA f r o n t OPT c o n n e c t o r
(f) 56: S t e p p i n g m o t o r c o n n e c t o r
( g ) J 7 : S p i n d l e m o t o r (DD m o t o r A s s ' y ) c o n n e c t o r
( h ) 5 8 : Head l o a d s o l e n o i d ( o n l y f o r models w i t h HL s o l e n o i d )
( i ) J10: ( O p t i o n , 1/1 s i z e f r o n t b e z e l i n d i c a t o r c o n n e c t o r )
(j) 511: ( O p t i o n , Door c l o s e A s s ' y o r Door l o c k s o l e n o i d A s s ' y c o n n e c t o r )
-
3202
-
F i l e protect sensor
PCBA f r o n t OPT
Index s e n s o r
Top view
(Fig.3201) Types o f c o n n e c t o r s
-
3203
-
3-2-2-2. Connection and disconnection of the connectors
Be sure to turn the power off before connecting and disconnecting the
connectors. Connection or disconnection should be done straightly and
correctly without applying excessive force to the cables and the post
pins.
3-2-2-3. Precautions for white connectors, J6 and Jll
(1) Disconnection of the connector
As
shown in Fig.3202, carefully push up the edges of the upper protruding
area of the connector little by little with the finger nails or with a
screwdriver.
Upper protruding area
Housing clamper
Post pin side
Push up
1
Pin numbers
(Fig.3202) Disconnection of J6 or Jll
(2) Connection of the connector
Push the connector into the post pin on the PCBA with the housing
clamper up.
(3) Removal of the pin (for reference)
Refer to Fig.3203.
Depressing the stopper of the pin lightly with a narrow object such
a s a pair of tweezers, pull the cable in the direction indicated by
-
3204
-
t h e arrow mark.
S t o p p e r (push)
Clamp
Cable
v
\Housing
'Contact a r e a
clamper
(Fig.3203) S e c t i o n a l view o f 56 and S l l
(4) I n s e r t i o n o f t h e p i n ( f o r r e f e r e n c e )
Before i n s e r t i o n , check t h e f o l l o w i n g t h r e e p o i n t s .
( a ) Confirm t h a t t h e s h e a t h and t h e c o r e o f t h e c a b l e are s e c u r e l y
clamped.
(b) Confirm t h a t t h e s t o p p e r i s l i f t e d as i n Fig.3203 and it i n h i b i t s
a c c i d e n t a l removal.
( c ) N o t a r n i s h o r c o n t a m i n a t i o n a d h e r e s on t h e c o n t a c t a r e a o f t h e p i n o r
t h e PCB s i d e post p i n .
I f t h e r e is, remove it.
C o n t a c t f a i l u r e may happen i f any o f t h e s e t h r e e p o i n t s i s n o t
satisfied.
When you i n s e r t t h e p i n , it s h a l l be SO i n s e r t e d t h a t t h e s t o p p e r f a c e s
t h e opening s i d e of t h e housing.
A f t e r t h e i n s e r t i o n , check t h e c o n n e c t i o n by p u l l i n g t h e c a b l e l i g h t l y .
3-2-2-4.
P r e c a u t i o n s f o r b l a c k c o n n e c t o r s , 54 and 58
(1) Disconnection o f t h e c o n n e c t o r
P u l l o u t s l o w l y h o l d i n g t h e housing w i t h t h e f i n g e r s or a round nose
-
3205
-
p l i e r s . B e s u r e n o t t o a p p l y t e n s i o n t o t h e f i n e c a b l e o f 54 (head
connector).
( 2 ) Connection o f t h e c o n n e c t o r
Make t h e p o l a r i z i n g key p o s i t i o n o f t h e h o u s i n g c o r r e s p o n d w i t h t h e
l a c k of t h e p o s t p i n , and push t h e h o u s i n g c a r e f u l l y w i t h t h e f i n g e r s .
( 3 ) Removal o f t h e p i n
L i f t i n g up t h e s t o p p e r o f t h e h o u s i n g w i t h a narrow o b j e c t such a s
c u t t e r k n i f e , p u l l t h e c a b l e w i t h a p a i r of t w e e z e r s i n t h e d i r e c t i o n
R e f e r t o Fig.3204.
i n d i c a t e d by t h e a r r o w mark.
,-Stopper
Projection
-7
ca)lmp
( p u l l up)
securely
-
Cable
Contact a r e a
--Lm
(Fig.3204) S e c t i o n a l view o f b l a c k c o n n e c t o r s
(4) I n s e r t i o n of t h e p i n
Before i n s e r t i o n , check t h e p i n s a c c o r d i n g t o i t e m 3-2-2-3
(4).
When you i n s e r t t h e p i n , i t s h a l l be so i n s e r t e d t h a t t h e p r o j e c t i o n
s i d e f a c e s t h e s t o p p e r o f t h e housing.
After the insertion, p u l l the
c a b l e w i t h a p a i r o f t w e e z e r s s o f t l y i n o r d e r t o c o n f i r m whether it
i s s e c u r e l y connected.
-
3206
-
3-2-2-5.
P r e c a u t l o n s f o r f l a t c a b l e c o n n e c t o r , J5 and 5 7
(1) 55 (PCBA f r o n t OPT c o n n e c t o r )
( a ) Disconnection o f t h e c o n n e c t o r
A f t e r d i s c o n n e c t i n g t h e a d j a c e n t c o n n e c t o r , 54 a c c o r d i n g t o i t e m
3-2-2-4,
p i c k up t h e f l a t c a b l e w i t h f i n g e r s and draw it o u t slowly.
( b ) Connection o f t h e c o n n e c t o r
i ) Confirm t h a t t h e c o r e w i r e s o f t h e t i p o f t h e f l a t c a b l e a r e
straight i n parallel.
i i ) Hold t h e f l a t c a b l e w i t h your r i g h t f i n g e r s and f i t t h e c o r e
w i r e s i n l i n e a g a i n s t t h e 55 r e c e p t a c l e on t h e s o l d e r e d s i d e o f
t h e PCBA MFD c o n t r o l .
i i i ) Guiding t h e c a b l e w i t h a t i p o f your l e f t f i n g e r and push t h e
cable i n t o t h e receptacle securely.
i v ) Confirm v i s u a l l y t h a t t h e c o r e s a r e n o t b e n t n o r j u t o u t .
( 2 ) 5 7 ( S p i n d l e motor c o n n e c t o r )
tal Disconnection o f t h e c o n n e c t o r
i ) L i f t up t h e f l a t c a b l e from t h e frame s u r f a c e by f i n g e r s o r by a
p a i r o f tweezers.
i i ) Depressing t h e t i p o f t h e 5 7 housing ( f r o n t b e z e l s i d e ) a g a i n s t
t h e r e a r end o f t h e FDD w i t h your thumb and draw o u t t h e f l a t
cable straightly.
B e c a r e f u l n o t t o p r e s s t h e r o t o r of t h e
s p i n d l e motor o r e l e c t r i c p a r t s on t h e PCBA.
( b ) Connection o f t h e c o n n e c t o r
i) Confirm that t h e c o r e wires o f t h e t i p o f t h e f l a t c a b l e are
-
3207
-
straight in parallel.
ii) Hold the flat cable with fingers or with a pair of tweezers and
fit the core wires in line against the 57 receptacle.
iii) Push the cable into the receptacle securdjy not to be bended nor
folded.
iv) Depress the center area of the flat cable- against the frame.
v) Confirm visually that the core wires are not bent nor jut out.
-
3208
-
3-2-3.
Head Cable Treatment
Head c a b l e s h a l l be arranged c o r r e c t l y so t h a t t h e head c a r r i a g e can
move on t h e guide s k a f t s smoothly.
When t h e FDD has head load s o l e n o i d Ass'y, remove t h e Ass'y r e f e r r i n g
t o item 3-5-5
b e f o r e t h e following s t e p s .
(1) Pass t h e head c a b l e under t h e l e f t b r i d g e of t h e s e t arm.
( 2 ) Hold t h e head c a b l e between t h e head connector and t h e frame so t h a t t h e
c a b l e has a p p r o p r i a t e space margin a g a i n s t t h e mechanical p a r t s when
t h e head c a r r i a g e i s s e t t o t h e innermost t r a c k ( f r o n t end o f t h e
moving a r e a ) and t r a c k 00 ( r e a r end o f t h e moving a r e a ) .
The head
c a b l e should run a t a balanced p o s i t i o n of moving a r e a .
Head connector
Hold t h e c a b l e .
Head c a b l e
L e f t b r i d g e of s e t arm
(Fig.3205) Head c a b l e arrangement
-
3209
-
3-2-4.
I n i t i a l S e t t i n g o f SKA
F o l l o w i n g i n i t i a l s e t t i n g s a r e r e q u i r e d f o r o p e r a t i n g a n SKA.
These
s e t t i n g s a r e a p p l i e d t o a l l t h e SKA models u n l e s s o t h e r w i s e s p e c i f i e d .
3-2-4-1.
C a b l e c o n n e c t i o n a n d s e t t i n g o f power s u p p l y v o l t a g e
( A ) C o n v e r t i o n a l SKA (SKA-ASF, SKA-G,
SKA-GFII)
(1) S e t t h e o u t p u t v o l t a g e of DC power s u p p l y t o + 1 2 V a n d +5V, a p p r o x .
( 2 ) Turn t h e DC power o f f and c o n n e c t t h e power c a b l e t o t h e PSA (SKA PWR)
c o n n e c t o r o f t h e SKA.
( 3 ) S e t t h e FD PWR s w i t c h o f t h e SKA t o t h e OFF p o s i t i o n .
( 4 ) Connect t h e SKA/FDD i n t e r f a c e c a b l e .
mark
Pay a t t e n t i o n t o i d e n t i f i c a t i o n
( V ) of t h e c o n n e c t o r so t h a t i t l o c a t e s a t p i n 1 s i d e .
( 5 ) Connect t h e FD PWR OUTPUT o f t h e SKA a n d 5 2 of t h e FDD w i t h t h e power
l i n e o f t h e check c a b l e $5.
( 6 ) Connect t h e b l a c k c o n n e c t o r ( 8 P ) o f t h e c h e c k c a b l e #5 t o TP1
t h e FDD.
%
TP8 of
B e s u r e t o c o n n e c t so t h a t t h e g r e e n w i r e comes t o TP8 s i d e .
( 7 ) Connect t h e w h i t e c o n n e c t o r w i t h s h i e l d e d w i r e of t h e check c a b l e #5 t o
terminals 6
9 , G o f t h e SKA.
The s h i e l d e d w i r e s come t o t e r m i n a l s 6
a n d 7 s i d e o f t h e SKA.
( 8 ) Connect t h e w h i t e c o n n e c t o r w i t h o u t s h i e l d e d w i r e o f t h e check c a b l e # 5
t o terminals 1
%
5 of t h e SKA.
Green w i r e comes t o t e r m i n a l 1 o f t h e
sa.
( 9 ) Turn t h e DC power o n .
S e t t h e FD PWR s w i t c h of t h e SKA t o t h e PSA s i d e .
-
3210
-
(10) Key i n "CB".
(+5V VOLTAGE)
(11) Adjust t h e Dc power v o l t a g e so t h a t t h e DATA i n d i c a t o r of t h e SKA, XX-XX
( V ) i n d i c a t e s a v a l u e w i t h i n t h e range of 5.00 f 0.lV.
(12) Key in "F".
( 1 3 ) Key i n "CC".
(STEP)
( + 1 2 V VOLTAGE)
( 1 4 ) Adjust t h e ELI pcwtr v o l t a g e so t h a t t h e DATA i n d i c a t o r , XX.XX
(V)
i n d i c a t e s a v a l u e w i t h i n t h e range of 12.00 2 0.24V.
(15) Key i n "F".
(STOP)
Note: The above i t e m s (11, (21, ( 7 ) , (81,
(10) % ( 1 5 ) may be o m i t t e d for
replacement o r temporary power o f f of t h e FDD.
I n t h i s c a s e , remain t h e DC power on for t h e SKA and c o n t r o l t h e FDD
power by t h e FD PWR s w i t c h .
- 3211 -
DC power supplies
(+12v,+Sv)
PCBA MFD c o n t r o l
L C o n n e c t t h e g r e e n w i r e t o TP8 s i d e .
( F i g . 3206) C o n n e c t i o n o f c o n v e n t i o n a l SKA
-
3212
-
A
(B) SKA3
(1) Attach an a p p r o p r i a t e c a r t r i d g e t o t h e SKA3 r e f e r r i n g t o Table 3104.
Pay a t t e n t i o n t o i d e n t i f i c a t i o n mark (VI o f t h e c a r t r i d g e connector so
t h a t i t matches with t h e mark o f t h e SKA3.
( 2 ) S e t t h e s l i d e switch mounted on t h e c a r t r i d g e f o r FD-55BR o r 55FR t o "W"
(upper) s i d e .
This means double s i d e d o p e r a t i o n by s i n g l e SKA3 command.
Note: C a r t r i d g e f o r FD-55GR has no s l i d e s w i t c h and "20" p o s i t i o n of t h e
c a r t r i d g e i s f i x e d t o "W"
side.
r
C a r t r i d g e type (m/EF/G)
k
A
J
[ FD-55V
262422 ZOW
10161412100 6 4 ID1 2
S l i d e switch
(Fig.3207) C a r t r i d g e s e t t i n g f o r FD-55BR and FR
( 3 ) S e t t h e o u t p u t v o l t a g e of Dc power supply t o +12V and +5V, approx.
( 4 ) Turn t h e DC power o f f and connect t h e power c a b l e t o t h e PSA (SKA PWR)
connector o f t h e SKA3.
( 5 ) S e t t h e FD PWR switch o f t h e SKA3 t o t h e OFF p o s i t i o n .
( 6 ) Connect t h e SKA/FDD i n t e r f a c e cable.
mark
(v)
Pay a t t e n t i o n t o i d e n t i f i c a t i o n
o f t h e connector so t h a t it l o c a t e s a t p i n 1 s i d e .
(7) Connect t h e FD PWR OUTPUT o f t h e SxA3 and J 2 of t h e FDD with t h e SKA/FDD
-
3213
-
power c a b l e .
( 8 ) Connect t h e black connector (8P) of t h e check c a b l e t o TP1
FDD.
%
TP8 of t h e
Be s u r e t o connect so t h a t t h e green wire comes t o TP8 s i d e .
( 9 ) Connect t h e white connector with s h i e l d e d wire of t h e check c a b l e t o
terminals 6
%
9 , G of t h e SKA3.
The s h i e l d e d w i r e s come t o t e r m i n a l s 6
and 7 s i d e of t h e SKA3.
(10) Connect t h e white connector without s h i e l d e d wire of t h e check c a b l e t o
terminals 1
%
5 of t h e SKA3.
Green wire comes t o t e r m i n a l 1 of t h e SKA3.
(11) Turn t h e DC power on and push t h e RESET switch a t t h e r e a r s i d e of t h e
SKA3.
The c o n t e n t s of t h e c a r t r i d g e parameter a r e read i n t o t h e SKA3.
Note: B e s u r e t o push t h e RESET switch when a c a r t r i d g e i s changed o r
a s l i d e switch i s r e s e t .
(12) S e t t h e F D PWR switch o f t h e SKA3 t o t h e PSA s i d e .
(13) Key i n "CB".
( + 5 V VOLTAGE)
(14) Adjust t h e DC power v o l t a g e so t h a t t h e DATA 0 i n d i c a t o r of t h e SKA3,
XX.XX
( V ) i n d i c a t e s a value w i t h i n t h e range of 5.00 f 0.1V.
Data 1 i n d i c a t o r shows c u r r e n t consumption XXXX (mA) a t t h a t time.
(15) Key i n "F".
(16) Key i n "CC".
(STOP)
( + 1 2 V VOLTAGE)
(17) Adjust t h e DC power v o l t a g e so t h a t t h e DATA 0 i n d i c a t o r , X X . X X
(V)
i n d i c a t e s a value w i t h i n t h e range of 1 2 . 0 0 2 0.24V.
DATA 1 i n d i c a t o r shows c u r r e n t consumption XXXX (mA) a t t h a t time.
-
3214
-
(18) Key i n "F".
(STOP)
Note: The above i t e m s (1)
%
(9)
(41,
%
(111, (13)
%
(17) may be o m i t t e d
f o r r e p l a c e m e n t o r t e m p o r a r y power o f f o f t h e FDD.
I n t h i s case,
r e m a i n t h e DC p o w e r on f o r t h e SKA3 a n d c o n t r o l t h e FDD power by t h e
FD PWR s w i t c h .
-
3215
-
'a'
(+12V1 +5V)
Check cable
Power
2
I--------
I
w
N
P
FDD
Cartridge
I
1
-
-1:'
SKA/FDD
interface
cable
-
-
I - T G r e e n cable :Pin 1
I
m
1
I
FD INTERFACE
~~
(Fig.3200) Connection of SKA3
c abl e
t
S e t t i n g o r c o n f i r m a t i o n o f t h e maximum t r a c k number
3-2-4-2.
T h i s i t e m i s n o t r e q u i r e d f o r SKA3 e x c e p t f o r s p e c i a l t e s t i n g because
t h e maximum t r a c k number i s p r e - s e t t o t h e c a r t r i d g e .
The f o l l o w i n g
shows t h e c o n f i r m a t i o n o r changing method f o r r e f e r e n c e .
For a c o n v e n t i o n a l SKA, s e t t h e maximum t r a c k number a c c o r d i n g t o t h e
f o l l o w i n g i n s t r u c t i o n s b e f o r e t h e check and t h e a d j u s t m e n t o f t h e FDD.
T b s e t t i n g w i l l be m a i n t a i n e d u n t i l t h e main DC power (SKA PWR) i s
t u n e d ::;"E
o r u n t i l t h e RESET s w i t c h o f t h e SKA i s d e p r e s s e d .
Since
t h e FD PWR s w i t c h is independent o f t h i s s e t t i n g , it i s c o n v e n i e n t t o
m a i n t a i n t h e main DC power on f o r t h e s u c c e s s i v e o p e r a t i o n s .
The i n i t i a l s e t t i n g o f t h e f o l l o w i n g i s n o t r e q u i r e d , i f t h e maximum
t r a c k number i s t h e same as tfie i n i t i a l v a l u e o f t h e SKA.
(1) Key i n "CF".
(SET TMAX)
( 2 ) The maximum t r a c k number s e t a t t h a t t i m e i s i n d i c a t e d w i t h t h e l a t t e r
two d i g i t s of t h e DATA (DATA 0 f o r SKA3) i n d i c a t o r , XXXX ( t r a c k ) .
Note: If t h e r e i s no change i n t h e maximum t r a c k number i n i t e m ( 2 1 ,
d e p r e s s "F" key.
( 3 ) Key i n new maximum t r a c k number used f o r t h e FDD i n two d i g i t s o f
decimal n o t a t i o n .
e.g.
4 8 t p i (FD55BR):
CF 39 ( f o r 40 c y l i n d e r s )
9 6 t p i (FD55FR):
CF 79 ( f o r 80 c y l i n d e r s )
9 6 t p i , h i g h d e n s i t y (FD-55GR):
CF 76 ( f o r 77 c y l i n d e r s )
Note: If 80 c y l i n d e r s are used i n FD-55GR, key i n '*CF 79" also f o r t h e
SKA.
Key i n "CF F", i f it i s t h e same as t h e i n i t i a l v a l u e o f t h e
SKA.
-
3217
-
3-2-4-3.
S e t t i n g o r confirmation of s t e p r a t e and s e t t l i n g time
This item i s not required f o r SKA3 except f o r 4msec seek model of
FD-55BR because the s t e p r a t e (STEP pulse i n t e r v a l ) and t h e s e t t l i n g
time of t h e FDD a r e pre-set t o t h e c a r t r i d g e .
The following shows t h e
comfinnation o r changing method for reference.
For 4msec seek model of FD-55BR o r f o r a conventional SKA, s e t t h e
s t e p r a t e and t h e s e t t l i n g time according t o t h e following i n s t r u c t i o n
before check and adjustment of t h e FDD.
The s e t t i n g w i l l be maintained u n t i l t h e main DC power (SKA PWR) i s
turned o f f o r u n t i l the RESET switch of t h e SKA i s depressed.
The
i n i t i a l s e t t i n g of the following is not required, i f the s t e p r a t e and
t h e s e t t l i n g time a r e t h e same a s t h e i n i t i a l values of the SKA.
(1) Key i n "DB".
(SET STEP RATE)
( 2 ) Step r a t e s e t a t t h a t time i s indicated by 0.lmsec s c a l e on the DATA
(ms).
(DATA 0 f o r SKA3) i n d i c a t o r , XXX.X
e .g. DATA i n d i c a t o r "XX60" means 6.Omsec.
(31 Key i n a new s t e p r a t e down t o one decimal place (unit:msec).
Note: I f t h e r e i s no change i n s t e p r a t e i n item ( 2 1 , omit item ( 3 ) and
forward t o item ( 4 ) .
(4) Key i n "F".
(Completion of s t e p r a t e s e t t i n g ) .
( 5 ) S e t t l i n g time a t t h a t time i s i n d i c a t e d by 0.lmsec s c a l e on t h e DATA
(ms).
(DATA 1 f o r SKA3) i n d i c a t o r , XXX.X
e.g.
DATA i n d i c a t o r "X150" means 15.0msec.
(6) Key i n new s e t t l i n g time down t o one decimal place ( u n i t : msec).
-
3218
-
Note: If there is no change in settling time in item (5), omit item (6)
and depress "F" key to complete the operation.
(7) Depress "F" key.
(STOP
--
Completion of settling time setting).
e.g. 48tpi, 6msec seek model
(Step rate 6msec, Settling time 15msec): DB 60 F 150 F
48tpi, 4msec seek model
(Step rate 4msec, Settling time l0msec): DB 40 F 100 F
96tpi, 3msec seek model
(Step rate jmsec, Settling time 15msec): DB 30 F 150 F
.
-
3219
-
3-2-4-4.
Level disk calibration
Setting of the following calibration value is required for accurate
measurement before the check of the read level or the resolution.
Use a level disk with a calibration value (100% center) written on the
label. The setting will be maintained until the main DC power (SKA PWR)
is turned off or until the RESET switch of the SKA is depressed.
If the calibration value is the same as the initial value (100%)of the
SKA, the initial setting of the following is not required.
Also the setting in this item is not required when the level disk is
not used (i.e., when it is substituted with a commercially available
disk and no accurate measurement is required).
(A) Conventional SKA
(1) Innermost track read level
(a) Key in "DO".
(CALIBRATION READ LEVEL)
(b) Calibration value set at that time is indicated in the latter three
digits of the DATA indicator, XXXX ( % I .
(c) Key in a new calibration value written on the level disk label
(three digits, Max. )
.
Notes: 1. If the side is changed for a double sided FDD, new calibration
value shall be keyed in.
The side is changed alternately by a depression of "4" key.
If the side 1 is selected, SIDE 1 indicator of the SKA turns on.
Confirm the used side by the indication of the SIDE 1 indicator
at the input of a new calibration value.
.
2 . If there is no calibration change in item (b), omit item (c)
-
3220
-
(d) Depress "F" key.
(STOP)
( 2 ) Innermost track resolution
(a) Key in "Dl".
(CALIBRATION RESOLUTION)
(b) The same as in item (l)-(b)
%
.
(d)
e.g. READ LEVEL 103%, RESOLUTION 96%: DO 103 F, D1 96 F
(B) SKA3
(1) Innermost track read level
(a) Key in "DO".
(CALIBRATION READ LEVEL)
(b) Side 0 calibration value set at that time is indicated in the latter
three digits of the DATA 0 indicator, XXXX
(%).
(c) Key in a new calibration value of side 0 written on the level disk
label (three digits, Max.).
(d) Key in "F".
(Completion of side 0 calibration setting)
(e) Side 1 calibration value set at that time is indicated in the latter
three digits of the DATA 1 indicator, XXXX ( $ 1 .
(f) Key in a new calibration value of side 1 written on the level disk
label (three digits, Ma x .) .
Note: If there is no calibration change, omit items (c) and (f).
( g ) Depress "F" key.
(Completion of side 1 calibration setting).
-
3221
-
( 2 ) I n n e r m o s t track resolution
(a) Key in "D1".
(CALIBRATION RESOLUTION)
(b) The same a s in i t e m (1)
e.g.
D o u b l e s i d e d FDD,
-
(b)
(9).
S I D E 0 READ LEVEL 103%, S I D E 1 REA2 LEVEL 95%
S I D E 0 RESOLUTION 96%, S I D E 1 RESOLUTION 98%:
DO 1 0 3 F 95 F , D 1 96 F 98 F
-
3222
-
3-2-4-5.
Alignment disk calibration
Setting of the following calibration value is required for accurate
measurement before the check and adjustment of the track alignment.
Use a correctly calibrated (0% center) alignment disk with a calibration
value written on the label.
The setting will be maintained until the
main DC power (SKA PWR) is turned off or until the RESET switch of the
SKA is depressed.
If the calibration value is the same as the initial value (0%)of the
SKA, the initial setting of the following is not required.
(A) Conventional SKA
(1) SIDE 0 alignment
(a) Key in "EO".
(CALIBRATION SIDE 0 ALIGNMENT)
(b) Calibration value set at that time is indicated in the latter two
d-igitsof the DATA indicator, XXXX
in the initial digit.
(%),
and the polarity is indicated
If a "0" is indicated, the polarity is positive.
Polarity indication: plus !-, minus
-
(c) Key in a polarity and a new calibration value (two digits, Max.)
written on the alignment disk label.
Designation of polarity: Depress "B" key only for minus designation.
(No designation is reauired for plus).
Note: If there is no change in the calibration value in item (b), omit
item (c).
(d) Depress "F" key.
(STOP)
-
3223
-
(2) Side 1 alignment
(a) Key in "El".
(CALIBRATION SIDE 1 ALIGNMENT)
(d).
(b) The same as in item (l)-(b)
(3) Index burst timing
ia!
Q-.-in
"E5".
(CALIBRATION INDEX TIMING)
(b) Calibration value set at that time is indicated in the latter three
digits of the DATA indicator, XXXX (us), and the polarity is indicated
in the initial digit.
Refer to item (l)-(b).
If a "0" is indicated, the polarity is positive.
(c) Key in a polarity and a new calibration value (three digits, Max.) of
side 0 written on the alignment disk label.
Refer to item (l)-(c) as
to the polarity designation.
Notes: 1. If the side is changed by key "4" for a double sided FDD, new
calibration value for side 1 shall be keyed in.
3-2-4-4,
2.
Refer to item
Note 1.
If there is no change in the calibration value in item (b),
omit item (c).
(d) Depress "F" key.
(STOP)
e.g. Double sided FDD, SIDE 0 ALIGNMENT +3%, SIDE 1 ALIGNMENT -5%,
INDEX TIMING - 2 5 ~ ~ :
EO 3 F, E l B5 F, E5 B25 F
-
3224
-
Lobe p a t t e r n
(TP7,8)
B
A
A
B
Notes: 1. The l o b e p a t t e r n r a t i o i s c a l i b r a t e d i n t h e SKA according t o t h e
following e x p r e s s i o n .
A-B
Lobe p a t t e r n r a t i o =
a f t e r calibration
Larger one o f A
&
B
100-Calibration
2 . If a c a l c u l a t e d value w i t h t h e above e x p r e s s i o n i s p o s i t i v e , t h e
p o l a r i t y i s p l u s , while t h e p o l a r i t y i s minus when a value i s
negative.
( F i g . 3209) C a l i b r a t i o n of alignment l o b e p a t t e r n
INDEX o u t p u t s i g n a l
7
1-‘
I
Index b u r s t (TP4,S)
Index b u r s t timing
F t
Notes: 1. The index timing i s c a l i b r a t e d i n t h e SKA according t o t h e
following e x p r e s s i o n .
C a l i b r a t e d timing = t
-
C a l i b r a t i o n value (us)
2. I f a c a l c u l a t e d v a l u e w i t h t h e above e x p r e s s i o n i s p o s i t i v e , t h e
p o l a r i t y i s p l u s , while t h e p o l a r i t y i s minus when a v a l u e is
negative.
(Fi9.3210) C a l i b r a t i o n of index b u r s t timing
-
3225
-
(1) Alignment
( a ) Key i n "EO".
(CALIBRATION SIDE 0 ALIGNMENT)
(b) Side 0 c a l i b r a t i o n value set a t t h a t t i m e i s i n d i c a t e d i n t h e l a t t e r
two d i g i t s of t h e DATA 0 i n d i c a t o r , XXXX ( % I , and t h e p o l a r i t y i s
indicated i n the i n i t i a l d i g i t .
I f a "0" i s i n d i c a t e d , t h e p o l a r i t y
is positive.
Polarity indication: plus
l-,
minus -
( c ) Key i n a p o l a r i t y and a new c a l i b r a t i o n v a l u e (two d i g i t s , Max.) o f
s i d e 0 w r i t t e n on t h e alignment d i s k l a b e l .
D e s i g n a t i o n o f p o l a r i t y : Depress "B" key o n l y f o r minus d e s i g n a t i o n .
(No designation is required f o r p l u s ) .
( d ) Depress "F" key.
(Completion o f s i d e 0 c a l i b r a t i o n s e t t i n g )
( e ) S i d e 1 c a l i b r a t i o n v a l u e set a t t h a t t i m e i s i n d i c a t e d i n t h e l a t t e r
two d i g i t s of t h e DATA 1 i n d i c a t o r , XXXX
(%),
and t h e p o l a r i t y i s
indicated i n the i n i t i a l d i g i t .
(f) Key i n a p o l a r i t y and a new c a l i b r a t i o n v a l u e (two d i g i t s , Max.) o f
s i d e 1 w r i t t e n on t h e a l i g n m e n t d i s k l a b e l .
Refer t o i t e m ( c ) as t o
t h e p o l a r i t y designation.
Note: I f t h e r e i s no change i n t h e c a l i b r a t i o n v a l u e , omit i t e m s ( c )
and ( f ) .
(g) Depress "F" key.
(Completion of s i d e 1 c a l i b r a t i o n s e t t i n g )
-
3226
-
( 2 ) Index burst timing
(a) Key in "E5".
(CALIBRATION INDEX TIMING)
(b) Side 0 calibration value set at that time is indicated in the latter
three digits of the DATA 0 indicator, XXXX (ps), and the polarity is
indicated in the initial digit.
Refer to item (l)-(b).
If a "0" is indicated, the polarity is positive.
( c ) Key in a polarity and a new calibration value (three digits, Max.)
side 0 written on the alignment disk label.
of
Refer to item (l)-(c) as
to the polarity designation.
(d) Depress "F" key.
(Completion of side 0 calibration setting)
(e) Side 1 calibration value set at that time is indicated in the latter
three digits of the DATA 1 indicator, XXXX ( u s ) , and the polarity is
indicated in the initial digit.
(f) Key in a polarity and a new calibration value (three digits, Max.)
of side 1 written on the alignment disk label.
Refer to item ( l ) - ( c )
as to the polarity designation.
Note: If there is no change in the calibration value, omit items (c)
and (f).
(g) Depress "F" key.
(Completion of side 1 calibration setting)
e.g. Double sided FDD, SIDE 0 ALIGNMENT + 3 % , SIDE 1 ALIGNMENT -5%
SIDE 0 INDEX TIMING -4Ops, SIDE 1 INDEX TIMING 20LIs:
EO 3 F B5 F, E5 B40 F 20 F
-
3227
-
3-2-4-6. Humidity s e t t i n g
For t h e check and a d j u s t m e n t o f t h e t r a c k a l i g n m e n t u s i n g a n a l i g n m e n t
d i s k , s e t t h e environmental r e l a t i v e humidity t o t h e SKA i n o r d e r t o
e x e c u t e t h e a c c u r a t e measurement.
T h i s s e t t i n g i s i m p o r t a n t when t h e r e l a t i v e humidity i s c o n s i d e r a b l y
d i f f e r e n t from 50% a t 9 6 t p i FDD.
The i n i t i a l s e t t i n g o f t h e f o l l o w i n g i s n o t r e q u i r e d i f t h e r e l a t i v e
humidity i s t h e same as t h e i n i t i a l v a l u e (50%) o f t h e SKA.
(1) Key i n "F2".
(CALIBRATION RH ALIGNMENT)
( 2 ) The r e l a t i v e humidity s e t a t t h a t t i m e i s i n d i c a t e d i n t h e l a t t e r two
d i g i t s o f t h e DATA (DATA 0 f o r SKA3) i n d i c a t o r , XXXX ( % I .
( 3 ) Key i n a new r e l a t i v e humidity ( % ) of t h e measurement environment
(two d i g i t s , Max.
e.g.
)
R e l a t i v e humidity 58%: E2 58
-
3228
-
3-2-4-7.
Gain setting
This item is applied only for conventional S K A s .
Operator need not feel
concern about this setting for the S - 3 .
(1) Track alignment of 96tpi (FD-55FR/GR) :
Key in "DD" to confirm that the H GAIN indicator is on.
( 2 ) Track alignment of 48tpi (FD-SSBR), and other items:
Confirm that H GAIN indicator is off.
again to turn it off.
-
3229
-
If it is on, depress "DD" key
3-2-4-8. Setting o f FDD straps and SKA special key
(1) Setting of FDD straps
It is required to confirm before the operation that the straps (short
bars) on the PCBA MFD control are at the appropriate p,osition for the
system to be used in the check and adjustment.
For the purpose of simplyfying the explanation, it is recommended to
sec
&??;e
following straps on when you use an SKA.
However, if you can
set w s straps correctly referring to Specification, Schematic Diagrams,
and Operation Manual, you need not to follow this recommendation.
Strap setting: Set the DO and FG straps to on-state as a general rule.
The other straps may be set as they were unless otherwise
designated.
For a model with head load solenoid, set the HS strap to
on-state and the HL strap should be o f f .
Notes: 1. I f the strap position of the FDD is changed from the initial
setting at the system installation, be sure to change it back
to the initial position after maintenance.
2 . When D1 strap is on, drive select is executed by key "1" of the
SKA.
Similarly D2 corresponds to key " 2 " and D3 to key "3".
These keys of DO
%
D3 can also release the drive select condition
by depressing the same key again.
(2) Setting of SKA special key
The signal level of the interface connector pin No.4 ( I N USE/HEAD LOAD)
changes alternately between TRUE and FALSE by depressing "A" (IN USE)
key of the SKA. When it 1s TRUE, "A" indicator turns on. Refer to
the Specification as to the function of the signal and its relation to
the straps.
-
3230
-
( 3 ) Signal o f i n t e r f a c e connector p i n ~0.34
While t h e o u t p u t s i g n a l o f i n t e r f a c e c o n n e c t o r p i n No.34 (READY, OPEN,
o r o t h e r o p t i o n a l s i g n a l s ) i s TRUE ( L O W l e v e l ) , "RDY" i n d i c a t o r o f t h e
SKA t u r n s on.
Refer t o t h e S p e c i f i c a t i o n as t o t h e f u n c t i o n o f t h e s i g n a l and i t s
relation to the straps.
-
3231
-
3-2-5.
Others
(1) T o t a l e r r o r t e s t
I n t h e check and a d j u s t m e n t i n i t e m 3-4,
included.
read/write e r r o r test is not
A f t e r t h e acFjustment o r t h e replacement o f t h e maintenance
p a r t s , it i s recommended t o perform a d a t a e r r o r t e s t by c o n n e c t i n g t h e
FDD t o t h e u s e r ' s system o r t h e TEAC s i m u l a t o r KB.
The window margin
t e s t i s t h e most recommended +-e%-
( 2 ) Terminator
When you check e a c h FDD w i t h a maintenance system such a s an SKA, it i s
n e c e s s a r y t o p u t t h e t e r m i n a t o r network i n t o t h e I C s o c k e t 53 on t h e
PCBA MFD c o n t r o l .
The t e r m i n a t o r s h a l l be r e t u r n e d t o t h e i n i t i a l
c o n d i t i o n a f t e r completion o f t h e maintenance.
For t h e f i x e d t y p e t e r m i n a t o r w i t h o u t I C s o c k e t ( s o l d e r e d on PCB), above
i n s t r u c t i o n is not applied.
( 3 ) Connection o f probe ground
Connect t h e probe ground o f t h e equipment a s f o l l o w s :
( a ) For o b s e r v a t i o n o f t e s t p o i n t s (TP) 4 , 5 ( P r e - a m p l i f i e r ) and TPs 7 , 8
(Differentiation amplifier) :
Connect t h e probe ground t o TP6 (OV) on t h e PCBA MFD c o n t r o l .
( b ) For o b s e r v a t i o n o f t h e o t h e r t e s t p o i n t s and FDD c i r c u i t s :
Connect t h e probe ground t o TP6 (OV) on t h e PCBA MFD c o n t r o l , o r GND
(OV) t e r m i n a l o f t h e system power s u p p l y u n i t , o r t h e GND t e r m i n a l o f
t h e SKA.
The frame o f t h e FDD may be a l s o used when t h e FG s t r a p
is o n - s t a t e .
-
3232
-
( c ) For o b s e r v a t i o n o f SKA t e s t p o i n t s :
Connect t h e probe ground t o t h e f o l l o w i n g t e r m i n a l .
i ) Conventional SKA: GND t e r m i n a l o f t h e SKA
ii) SKA3, PRE and DIF t e r m i n a l s : TPl (GND) of t h e SKA3
O t h e r t e r m i n a l s : TP4 (GND) o f t h e SKA3
Note: When you u s e t h e SKA, almost a l l t h e checks i n c l u d i n g t h e r e a d
amp. o u t p u t l e v e l a t TPs o f t h e FDD w i l l be done a u t o m a t i c a l l y
through t h e check c a b l e and FDD i n t e r f a c e c a b l e .
A l s o t h e s e s i g n a l s c a n be o b s e r v e d by a n o s c i l l o s c o p e u s i n g t h e
t e s t p o i n t s on a n SI(A.
( 4 ) Head l o a d o f CSS model
For a CSS model ( w i t h o u t head l o a d s o l e n o i d ) , t h e FDD i s always i n
head l o a d c o n d i t i o n as f a r as a d i s k i s i n s e r t e d and t h e f r o n t l e v e r
i s closed.
( 5 ) O r i e n t a t i o n o f t h e FDD
P o s i t i o n t h e FDD a s shown i n Fig.3211 u n l e s s o t h e r w i s e s p e c i f i e d .
Vertical s e t t i n g
Horizontal s e t t i n g
( F i g . 3211) General o r i e n t a t i o n of FDD d u r i n g maintenance
-
3233
-
( 6 ) Maintenance environment
Maintenance o f t h e FDD should be done on a c l e a n bench a t room
t e m p e r a t u r e and humidity.
I t i s recommended t o e x e c u t e t h e check and
a d j u s t m e n t o f t h e t r a c k alignment a f t e r l e a v i n g t h e FDD f o r a t l e a s t
2 h o u r s a t room t e m p e r a t u r e and humidity.
The magnetic head, d i s k ,
s t e e l b e l t , etc. might s u f f e r from d u s t and d i r t i f t h e maintenance i s
n o t undertaken i n a c l e a n environment.
(7) Disk
There a r e two s e c t o r i n g t y p e s i n normal d e n s i t y d i s k s which a r e s o f t
s e c t o r e d d i s k and h a r d s e c t o r e d d i s k .
Use s o f t s e c t o r e d d i s k s when an
SKA i s used.
For t h e check and a d j u s t m e n t o f h i g h d e n s i t y FDD (FD-55GR1,
h i g h d e n s i t y (HD) d i s k i s r e q u i r e d .
-
3234
-
appropriate
3-3. PREVENTIVE MAINTENANCE
3-3-1. Cleaning o f Magnetic Head by C l e a n i n g Disk
When you use t h e FDD i n d u s t y environment, it i s recommended t o c l e a n
t h e magnetic head s u r f a c e p e r i o d i c a l l y (e.g. once a month) w i t h a
commercially a v a i l a b l e c l e a n i n g d i s k .
For a t y p i c a l usage under t y p i c a l e n v i r o n m e n t a l coriZ?ition, t h e c l e a n i n g
c y c l e i s enough a t e v e r y t h r e e months.
( A ) Equipment
(1) Dry t y p e c l e a n i n g d i s k
( 2 ) SKA o r u s e r ' s system
(B-1)
Cleaning procedure (General method)
(1) I n s t a l l a n a p p r o p r i a t e c l e a n i n g d i s k and s t a r t t h e s p i n d l e motor.
Notes: 1. Do n o t u s e a damaged c l e a n i n g d i s k .
2 . B e s u r e t o u s e a double s i d e d c l e a n i n g d i s k .
S i d e 0 (lower s i d e )
and s i d e 1 (upper s i d e ) heads w i l l be c l e a n e d a t t h e same t i m e .
( 2 ) Execute head l o a d i n g and c l e a n t h e head a t a s u i t a b l e t r a c k p o s i t i o n
f o r 10
30 seconds, approx.
I n o r d e r t o a v o i d t h e c o n c e n t r a t i o n on
a s p e c i f i c t r a c k , it i s a good way t o make t h e head move between
t r a c k 00 and t h e innermost t r a c k d u r i n g c l e a n i n g o p e r a t i o n .
Note: The most a p p r o p r i a t e c l e a n i n g time i s d i f f e r e n t f o r e a c h t y p e o f
c l e a n i n g d i s k used.
Excessively long cleaning t i m e i s not e f f e c t i v e but has p o s s i b i l i t y
t o a c c e l e r a t e t h e head wear.
-
3301
-
(3) Remove t h e c l e a n i n g d i s k .
(B-2)
Cleaning p r o c e d u r e (SKA method)
(1) Connect an SKA r e f e r r i n g t o i t e m 3-2-4 and s e t t h e F D PWR s w i t c h t o
t h e PSA s i d e .
( 2 ) Execute d r i v e s e l e c t by key " 0 " .
( 3 ) Key i n "CO"
"00".
(DSO i n d i c a t o r t u r n s o n ) .
and confirm t h a t t h e TRACK i n d i c a t o r o f t h e SKA becomes
(RECALIBRATE)
See i t e m (B-l), "Notes".
( 4 ) I n s t a l l an a p p r o p r i a t e c l e a n i n g d i s k .
( 5 ) S t a r t t h e s p i n d l e motor by key "5".
( 6 ) Key i n "C6".
( 7 ) After 10
%
(MON i n d i c a t o r t u r n s o n ) .
(SEEK TEST)
30 seconds, d e p r e s s "F" key.
(8) E j e c t t h e c l e a n i n g d i s k .
-
3302
-
3-4.
3-4-1.
CHECK AND ADJUSTMENT
Adjustment o f S e t Arm P o s i t i o n
( A ) Equipment
(1) Cross p o i n t s c r e w d r i v e r , M3
(B) Adjustment p r o c e d u r e
(1) Loosen t w o f i x i n g s c r e w s of t h e s e t a r m ( s e e Fig.3401) so t h a t t h e s e t
arm c a n be moved manually w i t h o u t g e t t i n g o u t o f p l a c e .
(2) Close t h e s e t arm by t u r n i n g t h e f r o n t l e v e r .
(3) In t h i s condition
( i t e m ( 2 ) ) , a d j u s t t h e s e t arm so t h a t t h e v i s i a l
gap between t h e collet s h a f t and t h e s e t arm h o l e becomes even.
( 4 ) T i g h t e n t h e i n s t a l l i n g screws o f t h e s e t arm w i t h t h e s p e c i f i e d t o r q u e .
( 5 ) Open and c l o s e t h e s e t a r m by t u r n i n g t h e f r o n t l e v e r and c o n f i r m t h a t
i t d o e s so smoothly.
-
3401
-
f
/
shaft
retam
Collet
2-Set arm
fixing screws
between c o l l e t s h a f t and s e t arm h o l e
Front l e v e r
(Fig.3401) Adjustment of s e t arm p o s i t i o n
-
3402
-
3-4-2.
Check and Adjustment o f Holder P o s i t i o n
This i t e m i s a p p l i e d f o r a s t a n d a r d model without o p t i o n a l d i s k e j e c t
mechanism.
( A ) Equipment
(1) Cross p o i n t s c r e w d r i v e r , M3
! 2 ) MAX media j i g s C and E
(B) Check and adjustment procedure
(1) I n s e r t t h e MAX media j i g E from open s i d e u n t i l it s t r i k e s t h e frame
stopper.
Refer t o Fig. 3402.
( 2 ) When c l o s i n g t h e f r o n t l e v e r a t t h e s t o p s i d e o f t h e MAX media j i g E ,
confirm t h a t t h e wing of t h e f r o n t l e v e r d i s t u r b s t h e r o t a t i o n and t h a t
t h e l e v e r cannot be c l o s e d .
( 3 ) When t u r n i n g t h e MAX media j i g E o v e r t o i n s e r t it f o r p a s s s i d e , and
c l o s i n g t h e f r o n t l e v e r , confirm t h a t t h e l e v e r can be c l o s e d .
(4) I f the i t e m ( 2 ) o r ( 3 ) i s not s a t i s f i e d , a d j u s t the holder position
according t o t h e following procedure.
( a ) Loosen f o u r f i x i n g screws ( s e e Fig.3403) o f t h e h o l d e r so t h a t t h e
h o l d e r can be moved manually without going o u t of p l a c e .
(b) I n s t a l l t h e MAX media j i g C from open s i d e t o s e t i t t o be i n c o n t a c t
with t h e frame s t o p p e r .
( c ) Turn t h e f r o n t l e v e r t o c l o s e p o s i t i o n .
Loosen t h e f i x i n g screws o f
t h e holder a g a i n t o make t h e h o l d e r move toward t h e arrow i n d i c a t e d
d i r e c t i o n i n Fig.3403,
then d e p r e s s t h e wing a r e a of t h e f r o n t l e v e r
a g a i n s t t h e MAX media j i g C.
-
Refer t o Fig.3404.
3403
-
(d) T i g h t e n t h e f o u r f i x i n g screws of t h e h o l d e r w i t h s p e c i f i e d t o r q u e .
( e ) Confirm i t e m s (1) t h r o u g h ( 3 ) .
( f ) Check f o r t h e f i l e p r o t e c t s e n s o r a c c o r d i n g t o i t e m 3-4-5.
( g ) Check and a d j u s t t h e i n d e x b u r s t t i m i n g a c c o r d i n g t o i t e m 3-4-15.
L Pass s i d e
(Shorter s i d e )
(Fig.3402) I n s e r t i o n o f MAX media j i g
-
3404
-
Holder
7
E Holder f i x i n g screws
2-each s i d e
(Fig.3403) Adjustment of h o l d e r p o s i t i o n 1
Front b e z e l
Front l e v e r
-7
MAX media j i g
Wing
(Fig.3404) Adjustment of holder p o s i t i o n 2
-
3405
-
3-4-3.
Check and Adjustment of A r m L i f t e r
T h i s i t e m i s a p p l i e d o n l y f o r a double s i d e d model w i t h head l o a d
s o l e n o i d Ass'y.
(A) Equipment
(1) Common s c r e w d r i v e r , small s i z e
( 2 ) Work d i s k
( 3 ) SKA o r u s e r ' s system
(4) Oscilloscope
( 5 ) Locking p a i n t
(B-1) Check and a d j u s t m e n t p r o c e d u r e (General method)
(1) Use two c h a n n e l s o f o s c i l l o s c o p e .
Connect t h e 1st channel t o t h e
head l o a d command s i g n a l and t h e 2nd channel t o TP7 o r TP8 on t h e
PCBA MFD c o n t r o l .
T r i g g e r i n g should be done by t h e head l o a d command.
O s c i l l o s c o p e r a n g e , The 1st channel: DC mode, 2V,
The 2nd channel: AC mode, 0.5
20msec
T,
lV,
20msec
Note: For t h e purpose of check and a d j u s t m e n t i n t h i s i t e m , it i s n o t
p r o p e r t o e x e c u t e t h e head l o a d i n g by t h e MOTOR ON s i g n a l .
Use
e i t h e r of t h e D R I V E SELECT s i g n a l o r t h e I N USE/HEAD LOAD s i g n a l .
Refer t o i t e m 3-2-4-8
(1) o r t h e S p e c i f i c a t i o n i t e m 1-12.
( 2 ) I n s t a l l a work d i s k and s t a r t t h e s p i n d l e motor.
( 3 ) S e t t h e head t o t r a c k 00.
( 4 ) S e l e c t t h e s i d e 1 head.
(5) Execute t h e head l o a d i n g .
-
3406
-
Arm l i f t i n g p a r t
Head c a r r i a g e A s s ' y
Note: Viewed from f r o n t b e z e l s i d e .
(Fig.3405) Gap o f arm l i f t e r
Arm l i f t i n g p a r t
// -
Arm l i f t e r a d j u s t i n g screw
lifter\
/-Locking
paint
LHead load
s o l e n o i d Ass'y
Head c a r r i a g e Ass'y-/
(Fig. 3406) Adjustment o f arm l i f t e r
-
3407
-
(6) Confirm t h a t t h e gap between t h e upper arm and t h e am l i f t e r i s l a r g e r
than 0.2m.
Refer t o Fig.3405.
( 7 ) Execute 2F w r i t e o p e r a t i o n (WRITE DATA frequency o f 250KHz f o r FD-55BR
/FR and 500KHz f o r FD-55GR)
f o r one r o t a t i o n o f t h e d i s k .
( 8 ) Unload t h e head.
( 9 ) Repeat t h e head loading and unloading a l t e r n a t e l y ( t a p p i n g o p e r a t i o n )
and observe t h e waveform of TP7 o r TP8 by t h e o s c i l l o s c o p e .
(10) S e t t h e o s c i l l o s c o p e t r i g g e r t o t h e p o s i t i v e mode and observe t h e r e a d
waveform a t TP7 o r TP8 a f t e r t h e i n p u t o f an unload comnand.
(11) Confirm t h a t t h e r e i s no unload l e v e l (excludes very small one) a t
lOOmsec a f t e r t h e unload command a s shown by d o t t e d l i n e i n Fig.3407.
Note: T h i s i t e m s h a l l be executed when t h e s i d e 1 head is s e l e c t e d .
I f t h e s i d e 1 head i s l i f t e d t o o high d u r i n g unload o p e r a t i o n ,
t a p p i n g sound i n c r e a s e s and d i s k wear w i l l be a c c e l e r a t e d , while
unload l e v e l w i l l be observed when it i s t o o low.
(12) S e t t h e o s c i l l o s c o p e t r i g g e r t o t h e n e g a t i v e (-1 mode and observe t h e
waveform a t Tp7 o r Tp8 a f t e r t h e i n p u t o f a head l o a d command.
Confirm t h a t t h e read waveform more t h a n 50msec a f t e r t h e head l o a d
comnand i s almost s e t t l e d .
O r confirm t h a t bottom "A" of t h e r e a d l e v e l more than 35msec a f t e r t h e
i n p u t o f t h e head l o a d command i s more t h a n 0.7 a g a i n s t t h e average
read l e v e l "B".
(A/B
2
0.7 i n Fig.3407)
(13) Make t h e head move t o t h e innermost t r a c k .
(14) Repeat t h e procedure from i t e m ( 7 ) t o ( 1 2 ) .
-
3408
-
Head load command
TRUE
TP7 o r TP8
I
I
Head l o a d command
( S e t t l e d a t 50ms)
Head unload command
FALSE
t
-Spike
n o i s e i s allowed.
TP7 o r TP8
\Residual
read l e v e l
(Unload l e v e l )
Head unioad command
( F i g . 3407) Read waveforms a t head loading/unloading
( 1 5 ) I f t h e value i n i t e m (61, (111, (121, o r ( 1 4 ) i s o u t of t h e s p e c i f i e d
range, a d j u s t according t o t h e f o l l o w i n g procedure.
( a ) Execute items ( 3 ) through ( 1 0 ) .
(b) Loosen t h e unload a d j u s t i n g screw u n t i l t h e unload l e v e l i s observed
a t l O O m s e c a f t e r t h e unload command.
Refer t o d o t t e d l i n e i n Fig.3407.
( c ) Tighten t h e a d j u s t i n g screw l i t t l e by l i t t l e and s e a r c h t h e screwing
p o i n t where t h e unload l e v e l e x a c t l y d i s a p p e a r s a t l O O m s e c a f t e r t h e
unload command.
( d ) Make t h e head m v e t o t h e innermost t r a c k .
-
3409
-
(e) Confirm unload l e v e l a c c o r d i n g t o i t e m (11).
I f t h e unload l e v e l i s observed a t l O O m s e c a f t e r t h e unload
command, r e p e a t item ( c ) a t t h e innermost t r a c k .
( f ) Tighten t h e a d j u s t i n g screw by 90" from t h e above p o i n t .
( g ) Apply a drop o f l o c k i n g p a i n t on t h e a d j u s t i n g screw.
Again s e t t h e head t o t r a c k 00.
A f t e r opening t h e f r o n t l e v e r , draw o u t t h e d i s k slowly.
In the
p r o c e s s of drawing o u t , t h e s i d e 0 and s i d e 1 heads s h a l l n o t c a t c h
t h e head window edge o f t h e d i s k j a c k e t (opening a r e a o f t h e j a c k e t
t o make t h e head be i n c o n t a c t w i t h t h e d i s k s u r f a c e ) .
The j a c k e t
can be drawn o u t smoothly w i t h a p p r o p r i a t e space margin.
I n s e r t t h e d i s k slowly and confirm t h a t t h e d i s k j a c k e t does n o t touch
t h e s i d e 0 nor s i d e 1 head and goes i n t o t h e FDD smoothly with
a p p r o p r i a t e space margin.
I f t h e s t r a p s e t t i n g was changed, back it t o t h e i n i t i a l s e t t i n g
a f t e r t h e check and adjustment.
-
3410
-
(B-2) Check and a d j u s t m e n t p r o c e d u r e (SKA method)
(1) Connect an SKA a c c o r d i n g t o i t e m 3-2-4
and s e t t h e F D PWR s w i t c h t o
t h e PSA s i d e .
( 2 ) I n s t a l l a work d i s k .
( 3 ) U s e t w o c h a n n e l s of o s c i l l o s c o p e .
Connect t h e 1st channel t o t h e
WUT t e r m i n a l and t h e 2nd channel t o t h e D I F t e r m i n a l o f t h e SKA.
Apply n e g a t i v e t r i g g e r by t h e DOUT t e r m i n a l .
O s c i l l o s c o p e range, The 1st channel: DC mode, 2V, 2 h s e c
The 2nd c h a n n e l : AC mode, 0.5
%
lV, 20msec
Note: For t h e check and a d j u s t m e n t i n t h i s i t e m , it i s r e q u i r e d t o set
t h e s t r a p s a c c o r d i n g t o i t e m 3-2-4-8
( 4 ) Key i n "BC F".
(1).
(DRIVE SELECT o b s e r v a t i o n )
(5) S t a r t t h e s p i n d l e motor by key "5".
(MON i n d i c a t o r t u r n s o n ) .
(6) Key i n "CO" and c o n f i r m t h a t t h e TMCK i n d i c a t o r becomes "00".
(RECALIBRATE)
(SIDE 1 i n d i c a t o r t u r n s o n ) .
(7) S e l e c t t h e s i d e 1 head by key "4".
(8) Execute d r i v e select and head l o a d i n g by key " 0 " .
( E O indicator
turns on).
( 9 ) Confirm t h a t t h e gap between t h e upper arm and t h e arm l i f t e r i s
l a r g e r t h a n 0.2m.
R e f e r t o Fig.3405.
(10) Key i n "C9" f o r a c o n v e n t i o n a l SKA or key i n "C9A" f o r SKA3.
LOAD TIME).
-
3411
-
(HEAD
(11) Observe t h e waveform o f t h e DIF t e r m i n a l a t head unloading using t h e
oscilloscope.
SKA DOUT
FALSE
A
Spike n o i s e i s allowed.
SKA DIF
c
Residual r e a d l e v e l
(Unload l e v e l )
lOOms
Head unload command
(Fig.3408) Read waveform a t head unloading
(12) Confirm t h a t t h e r e i s no unload l e v e l (excludes very small one) a t
lOOmsec a f t e r t h e unload command a s shown by d o t t e d l i n e i n Fig.3408.
Note: T h i s i t e m s h a l l be executed when t h e s i d e 1 head i s s e l e c t e d
(SIDE 1 i n d i c a t o r t u r n s o n ) .
I f t h e s i d e 1 head i s l i f t e d too high d u r i n g unload o p e r a t i o n ,
t a p p i n g sound i n c r e a s e s and d i s k wear w i l l be a c c e l e r a t e d , while
unload l e v e l w i l l be observed when it i s too low.
(13) Confirm t h a t t h e DATA i n d i c a t o r , XXXX ( % ) o f t h e SKA i n d i c a t e s a v a l u e
w i t h i n t h e following range.
Head l o a d s e t t l i n g l e v e l : 7 0 % , Min.
(14) Key i n "F".
(STOP)
(15) I f t h e DSO i n d i c a t o r o f t h e SKA i s o f f , execute d r i v e s e l e c t by key
"0".
(DSO i n d i c a t o r t u r n s o n ) .
(16) Key i n "Cl".
(SEEK TMAX)
-
3412
-
(17) Repeat t h e procedure from item (10) t o ( 1 4 ) .
(18) I f t h e value i n item (91, (121, (131, or (17) is out of t h e s p e c i f i e d
range, a d j u s t according t o the following procedure.
( a ) Key i n '*CO"
(RECALIBRATE) and execute items (10) and (11).
( b ) Loosen the unload adjusting screw u n t i l t h e unload l e v e l i s observed
a t lOOmsec a f t e r the unload command.
Refer t o dotted l i n e i n Fig.3408.
( c ) Tighten the adjusting screw l i t t l e by l i t t l e and search t h e screwing
p o i n t where the unload l e v e l exactly disappears a t lOOmsec a f t e r t h e
unload command.
( d ) Key i n "F".
(STOP)
( e ) Key i n "C1" (SEEK TMAX) and execute items (10) and (11).
( f ) Confirm unload l e v e l according to item (12).
I f t h e unload l e v e l i s observed a t lOOmsec a f t e r the unload comnand,
repeat item (c) a t t h e innermost t r a c k .
(g) Key i n "F".
(STOP)
(h) Tighten t h e a d j u s t i n g screw by
90° from t h e above point.
( i )Apply a drop of locking p a i n t on t h e a d j u s t i n g screw.
(19) Key i n "CO" and confirm t h a t t h e TRACK i n d i c a t o r becomes "00".
(RECALIBRATE)
(20) After opening t h e f r o n t l e v e r , draw o u t t h e disk slowly.
I n t h e process
of drawing out, the s i d e 0 and s i d e 1 heads shall not catch t h e head
window edge of t h e disk jacket (opening a r e a of t h e j a c k e t to make the
- 3413 -
head be i n c o n t a c t w i t h t h e d i s k s u r f a c e ) .
The j a c k e t c a n be drawn
o u t smoothly w i t h appropriate space margin.
(21) I n s e r t t h e d i s k s l o w l y and c o n f i r m that t h e d i s k j a c k e t d o e s n o t t o u c h
t h e s i d e 0 n o r s i d e 1 head and g o e s i n t o t h e FDD smoothly w i t h
a p p r o p r i a t e space margin.
( 2 2 ) I f t h e s t r a p s e t t i n g w a s changed, back it t o t h e i n i t i a l s e t t i n g
a f t e r t h e check and a d j u s t m e n t .
- 3414 -
3-4-4.
Check o f CSS A s s ' y
T h i s i t e m i s a p p l i e d o n l y f o r a d o u b l e s i d e d CSS model ( w i t h o u t head
load solenoid).
( A ) Equipment
(1) Work d i s k
( 2 ) SKA o r u s e r ' s system
(B-1) Check p r o c e d u r e (General method)
(1) Open and c l o s e t h e f r o n t l e v e r w i t h no i n s e r t i o n o f a d i s k .
( 2 ) Confirm that t h e s i d e 1 head is l i f t e d even i f t h e f r o n t l e v e r i s
c l o s e d and it h a s enough gap a g a i n s t t h e s i d e 0 head.
(See Fig.3409).
Tide
r
head
L S i d e 0 head
(Fig.3409) Gap between s i d e 0 and s i d e 1 heads
( 3 ) A f t e r opening t h e f r o n t l e v e r , i n s e r t a work d i s k slowly.
Confirm t h a t t h e d i s k j a c k e t d o e s n o t t o u c h t h e s i d e 0 n o r s i d e 1 head
and goes i n t o t h e FDD smoothly w i t h a p p r o p r i a t e space margin.
( 4 ) D r a w o u t t h e d i s k slowly.
Confirm t h a t t h e s i d e 0 and s i d e 1 heads
do n o t c a t c h t h e head window edge o f t h e d i s k j a c k e t (opening area
of t h e j a c k e t t o make t h e head be i n contact w i t h t h e disk surface)
-
3415
-
and t h a t t h e j a c k e t can be drawn o u t smoothly w i t h a p p r o p r i a t e space
margin.
( 5 ) Confirm t h a t t h e cam ( n a t u r a l c o l o r ) of t h e CSS Ass'y a t t a c h e d t o t h e
l e f t s i d e o f t h e head c a r r i a g e moves a s i n Fig.3410 by opening/closing
o f t h e f r o n t l e v e r and i n s e r t i o n / e j e c t i o n o f t h e d i s k .
Rotates
about 90°
( a ) Disk i s n o t f u l l y i n s e r t e d .
(b) Disk i s f u l l y i n s e r t e d and
front lever is close.
(Fig.3410) Cam r o t a t i o n of CSS Ass'y
(6) I n s e r t a work d i s k and start t h e s p i n d l e motor.
( 7 ) S e t t h e head t o t r a c k 00.
( 8 ) I n t h e close c o n d i t i o n o f t h e f r o n t l e v e r , confirm that t h e gap
between t h e upper arm and t h e ann l i f t e r i s O . h ,
Fig. 3405'.
(9) Make t h e head move t o t h e innermost t r a c k .
(10) Confirm as i n i t e m ( 8 ) .
-
3416
-
Min.
Refer t o
(B-2)
Check procedure (SKA method)
(1) Open and c l o s e t h e f r o n t l e v e r w i t h no i n s e r t i o n o f a d i s k .
( 2 ) Confirm that t h e s i d e 1 head i s l i f t e d even i f t h e f r o n t l e v e r i s closed
and it has enough gap a g a i n s t t h e s i d e 0 head.
-fer
to Fig.3409.
(3) A f t e r opening t h e f r o n t l e v e r , i n s e r t a work d i s k slowly.
Confirm t h a t t h e d i s k j a c k e t does n o t touch t h e s i d e 0 n o r s i d e 1 head
and goes i n t o t h e FDD smoothly w i t h a p p r o p r i a t e space margin.
( 4 ) Draw o u t t h e d i s k slowly.
Confirm t h a t t h e s i d e 0 and s i d e 1 heads do
n o t c a t c h t h e head window edge o f t h e d i s k j a c k e t (opening a r e a o f t h e
j a c k e t t o make t h e head be i n c o n t a c t w i t h t h e d i s k s u r f a c e ) and t h a t
t h e j a c k e t can be drawn o u t smoothly w i t h a p p r o p r i a t e space margin.
(5) Confirm t h a t t h e cam ( n a t u r a l c o l o r ) o f t h e CSS Ass'y a t t a c h e d t o t h e
L e f t s i d e o f t h e head c a r r i a g e moves as i n Fig.3410 by opening/closing
o f t h e f r o n t l e v e r and i n s e r t i o n / e j e c t i o n o f t h e d i s k .
(6) Connect an SKA according t o i t e m 3-2-4
and set t h e FD PUR s w i t c h t o t h e
PSA s i d e .
(7) S t a r t t h e s p i n d l e m t o r by key " 5 " .
( 8 ) Execute d r i v e select by key "0".
(MON i n d i c a t o r t u r n s o n ) .
(DSO i n d i c a t o r t u r n s o n ) .
( 9 ) Key i n "CO" and confirm t h a t t h e TRACK i n d i c a t o r becomes "00".
(RECALIBRA'IZ)
(10) I n t h e c l o s e c o n d i t i o n of t h e f r o n t l e v e r , confirm that t h e gap between
t h e upper arm and t h e arm l i f t e r i s 0.2rmn, Min.
Refer t o Fig.3405.
- 3417 -
(11) Key i n "Cl".
(SEEK T W )
(12) Confirm as i n item (10).
-
3418
-
3-4-5.
Check o f F i l e P r o t e c t Sensor
( A ) Equipment
(1) MAX media j i g C
(2) SKA or u s e r ' s system
(B-1)
Check procedure (General method)
(1) Place t h e FDD on t h e work bench w i t h t h e LED i n d i c a t o r up and t h e
f r o n t l e v e r down.
(See Fig.3411).
( 2 ) Connect an o s c i l l o s c o p e (DC range, 2V/div)
t o t h e WRITE PROTECT
interface line.
( 3 ) I n s e r t t h e MAX media j i g C from open s i d e and s e t it so t h a t t h e
notch A a r e a i s l o c a t e d on t h e l i g h t p a s s from t h e f i l e p r o t e c t
sensor LED.
See Fig.3411.
(4) Adjust t h e o r i e n t a t i o n o f t h e FDD so t h a t it i s n o t exposed with
strong l i g h t .
(5) Confirm t h a t t h e WRITE PROTECT s i g n a l goes t o LOW level when power i s
s u p p l i e d and t h e FDD i s DRIVE SELECTed.
( 6 ) P u l l o u t t h e j i g a l i t t l e so t h a t t h e notch B a r e a i s l o c a t e d on t h e
l i g h t pass.
(7) Confirm t h a t t h e WRITE PROTECT s i g n a l goes t o H I G H l e v e l .
-
3419
-
LED indicator
F i l e protect
sensor
Y
(Fig.3411) Check of f i l e protect sensor
-
3420
-
(B-2) Check procedure (SKA method)
(1) Connect an SKA according t o i t e m 3-2-4 and set t h e FD PWR switch t o
t h e PSA s i d e .
( 2 ) I n s e r t t h e MAX media j i g C from open s i d e and set it so t h a t t h e
notch A a r e a is l o c a t e d on t h e l i g h t p a t h from t h e f i l e p r o t e c t
s e n s o r LED.
See Fig.3411.
( 3 ) Adjust t h e o r i e n t a t i o n o f t h e FDD so t h a t i t i s n o t exposed w i t h
strong light.
(4) Confirm that t h e WPROT i n d i c a t o r o f t h e SKA t u r n s on, when t h e FDD
i s s e l e c t e d by key "0".
(DSO i n d i c a t o r t u r n s o n ) .
(5) P u l l o u t t h e j i g a l i t t l e so t h a t t h e n o t c h B a r e a i s l o c a t e d on t h e
l i g h t path.
(6) Confirm that t h e WPROT i n d i c a t o r t u r n s o f f .
-
3421
-
34-6.
Check o f Disk F b t a t i o n Speed
Disk r o t a t i o n speed is set t o 300rpm for FD-sSBR/FR and 360rpm for
FD- 55GR.
(A)
Equipment
(1) SKA or u s e r ' s system
( 2 ) Frequency c o u n t e r ( n o t r e q u i r e d when an SKA i s usm.%~
( 3 ) Work d i s k
(B-1)
Check procedure (General method)
(1) Connect a frequency c o u n t e r t o -1
(Index) on t h e PCBA MFD c o n t r o l or
t o t h e INDEX i n t e r f a c e s i g n a l l i n e .
( 2 ) I n s t a l l a work d i s k and s t a r t t h e s p i n d l e motor.
( 3 ) S e t t h e head t o t r a c k 00.
( 4 ) Execute t h e head loading.
(5) Confirm t h a t t h e p u l s e i n t e r v a l a t TP1 or a t t h e INDEX i n t e r f a c e i s
withon t h e following range.
Index i n t e r v a l , FD-55BR/FR:
200 f 3msec
FD-55GR: 166.7 f 2.5msec
-
3422
-
(B-2)
Check procedure (SKA method)
(1) Connect a n SKA r e f e r r i n g t o i t e m 3-2-4
and s e t t h e FD PWR s w i t c h t o
t h e PSA s i d e .
( 2 ) I n s t a l l a work d i s k .
( 3 ) S t a r t t h e s p i n d l e motor by key "5".
( 4 ) Execute d r i v e select by key "0".
(MON i n d i c a t o r t u r n s o n ) .
(DSO i n d i c a t o r t u r n s o n ) .
(51 Key i n 'lCO" and confirm t h a t t h e TRACK i n d i c a t o r becomes "00".
(RECALIBRATE)
(6) Key i n "C3".
( I N D E X INTERVAL)
(7) Confirm t h a t t h e DATA (DATA 0 f o r SKA3) i n d i c a t o r , XXXX ( m s ) i n d i c a t e s
a v a l u e w i t h i n t h e f o l l o w i n g range.
Index i n t e r v a l , FD-SSBR/FR:
200 f 3msec
FD-55GR: 166.7 f 2.5msec
( 8 ) Depress llF'l key.
(STOP)
-
3423
-
Check o f Erase Gate Delay
3-4-7.
The purpose o f t h i s i t e m i s t o confirm t h e f u n c t i o n o f t h e c o n t r o l LSI.
T h i s i t e m i s n o t so important a s f a r a s t h e FDD o p e r a t e s normally.
(A)
Equipment
(1) SKA o r u s e r ' s system
( 2 ) O s c i l l o s c o p e ( n o t r e q u i r e d when an SKA i s used)
( 3 ) Work d i s k
(B-1)
Check procedure (General method)
(1) Use two c h a n n e l s o f o s c i l l o s c o p e .
Connect t h e t r i g g e r channel t o t h e
WRITE GATE i n t e r f a c e l i n e and t h e o t h e r channel t o TP2 (Erase g a t e
d e l a y ) on t h e PCBA MFD c o n t r o l .
O s c i l l o s c o p e range: For b o t h channels, DC mode, 5V, 100psec
(2) I n s t a l l a work d i s k and s t a r t t h e s p i n d l e motor.
(3) Execute t h e head loading.
(4) S e t t h e o s c i l l o s c o p e t o t h e n e g a t i v e t r i g g e r (-) mode.
W R I T E GATE s i g n a l TRUE
Make t h e
( w r i t e conmand).
( 5 ) Confirm that "tl" (Erase on d e l a y ) i n Fig.3412 i s w i t h i n t h e following
range.
E r a s e on d e l a y , FD-S5BR/FR:
240
FD-SSGR: 200
%
?,
290psec
24Opsec
( 6 ) S e t t h e o s c i l l o s c o p e t o t h e p o s i t i v e t r i g g e r (+) mode.
WRITE GATE s i g n a l FALSE.
-
3424
-
Make t h e
( 7 ) Confirm that " t 2 " ( E r a s e off d e l a y ) i n F i g . 3 4 1 3 i s w i t h i n the f o l l o w i n g
range.
E r a s e o f d d e l a y , FD-sSBR/GR:
FD-55GR:
8!30
530
%
%
390psec
590usec
7
WRITE GATE
TP2 ( E r a s e g a t e )
E r a s e on delay
( F i g . 3 4 1 2 ) E r a s e on delay
WRITE GATE
TP2 ( E r a s e g a t e )
I
t2
- E r a s e o f € delay
( F i g . 3 4 1 3 ) E r a s e off delay
-
3425
-
(B-2) Check p r o c e d u r e (SKA method)
(1) Connect an SKA and check cable a c c o r d i n g to i t e m 3-2-4
and set t h e FD
power s w i t c h t o t h e PSA side.
(2) I n s t a l l a work d i s k .
( 3 ) S t a r t t h e s p i n d l e motor by key "5".
(4) Execute d r i v e select by key "0".
( 5 ) Key i n " 7 " .
(HON i n d i c a t o r t u r n s o n ) .
(DSO i n d i c a t o r t u r n s o n ) .
(WRITE GATE ON)
( 6 ) Confirm t h a t t h e DATA (DATA 0 f o r SKA3) i n d i c a t o r , XXXX
(PSI
shows
a v a l u e w i t h i n t h e f o l l o w i n g range.
E r a s e on d e l a y , FD-55BR/FR: 240
FD-55GR: 200
( 7 ) Key i n "7" a g a i n .
%
%
290psec
240~sec
(WRITE GATE OFF)
( 8 ) Confirm t h a t t h e DATA (DATA 1 f o r SKA3) i n d i c a t o r , XXXX (ps) shows
a v a l u e w i t h i n t h e f o l l o w i n g range.
E r a s e o f f d e l a y , FD-SSBR/FR: 890
Fb55GR: 530
%
%
990weC
590usec
- 3426 -
3-4-8.
Check of Head m u c h
(Al Equipment
(1) Work d i s k
( 2 ) SKA or u s e r ' s system
(3) Oscilloscope ( n o t r e q u i r e d when an SKA i s used)
( 4 ) Dc c l i p on ammeter ( n o t r e q u i r e d when an SKA i s used)
(B-1) Check procedure (General method)
(1) Connect an o s c i l l o s c o p e t o TP7 or TP8 ( D i f f e r e n t i a t i o n amp.) on t h e
PCBA MFD c o n t r o l .
Oscilloscope range: AC mode, 0.1
'L
0.2V, 2Omsec
(2) I n s t a l l a work d i s k and s t a r t t h e s p i n d l e motor.
(31 S e t t h e head t o t h e innennost t r a c k .
(4) Execute t h e head loading.
(5) Repeat t h e c y c l e o f one w r i t e r o t a t i o n and one read r o t a t i o n .
Write d a t a should be t h e f i x e d p a t t e r n of 2F (250KHz o f W R I T E DATA
frequency f o r FD-SSBWFR and 5001Mz f o r FD-SSGR).
(6) Write down t h e average read l e v e l measured d u r i n g t h e r e a d o p e r a t i o n
o f i t e m (5).
(71 Execute items (5) and (6) w i t h a s l i g h t d e p r e s s i o n (very s l i g h t
depression easy t o release: 10
%
209) by a f i n g e r on t h e t o p o f t h e
upper head, and measure t h e average read l e v e l as i n i t e m (6).
( 8 ) Confirm t h a t t h e read l e v e l measured i n i t e m ( 6 ) i s g r e a t e r t h a n 80%
of that in item (7).
- 3427 -
(9) Execute items (5) through ( 8 ) r e s p e c t i v e l y f o r s i d e 0 and s i d e 1 heads.
(10) After making t h e head move t o t r a c k 00, execute items (5) through ( 9 ) .
(11) Possible causes f o r i n s u f f i c i e n t head touch:
Following causes a r e assumed f o r t h e i n s u f f i c i e n t r e s u l t i n items ( 8 )
.
through (10)
( a ) I n f e r i o r disk:
Disk and/or j a c k e t is deformed or damaged.
Replace the work disk
with a new one.
(b) I n f e r i o r head f l e x t u r e :
Because of t h e f a i l e d performance of t h e arm l i f t e r i n item 3-4-3
(model with head load solenoid) or t h e f a i l e d performance of t h e
CSS A s s ' y i n item 3-4-4 (CSS model without head load solenoid),
t h e f l e x t u r e on which t h e head piece i s located may be deformed.
Remove t h e d i s k .
Then open and c l o s e the f r o n t l e v e r slowly t o
observe the gap between the s i d e 1 and s i d e 0 heads from the f r o n t
bezel.
I f the two head surfaces a r e not i n p a r a l l e l each o t h e r ,
it i s considered t o be the deformation.
Replace t h e head c a r r i a g e A s s ' y according t o item 3-5-1.
( c ) I n f e r i o r load force:
I f t h e upper arm is o v e r - l i f t e d manually by c a r e l e s s handling during
replacement of t h e head c a r r i a g e Ass'y and e t c . ,
spring a t the upper
arm supporting p o i n t may be deformed and t h e head load force may
decrease.
Carefully replace t h e head c a r r i a g e A s s ' y according t o
item 3-5-1.
-
3428
-
(d) I n f e r i o r pressure of t h e jacket pads:
I f the jacket pad attached under the s e t arm does not touch the jacket
surface, replace t h e pads.
Refer t o Fig.405 i n P a r t s L i s t .
Caution: I f the j a c k e t surface i s excessively pressed by t h e pads, t h e
spindle motor might be overloaded because of increasing the
r o t a t i o n torque.
-
3429
-
( B - 2 ) Check p r o c e d u r e (SKA method)
(1) Connect a n SKA and check c a b l e a c c o r d i n g t o i t e m 3-2-4
and s e t t h e FD
PWR s w i t c h t o t h e PSA s i d e .
( 2 ) I n s t a l l a work disk.
( 3 ) S t a r t t h e s p i n d l e motor by key "5".
( 4 ) Execute d r i v e select by key "0".
(MON i n d i c a t o r t u r n s o n ) .
(DSO i n d i c a t o r t u r n s o n ) .
( 5 ) Key i n "CO" and c o n f i r m t h a t t h e TRACK i n d i c a t o r becomes "00".
( RECALIBRATE
(6) Key i n "Cl".
(SEEK TMAX)
(7) Key i n "D3".
(WRITF./READ
LEVEL PRE 2F)
( 8 ) W r i t e 2F and r e a d o p e r a t i o n s are r e p e a t e d .
The DATA i n d i c a t o r , XXXX (mV) i n d i c a t e s t h e a v e r a g e r e a d l e v e l a t
TP4 and TP5 (Pre-amp.)
a f t e r e a c h c y c l e of o p e r a t i o n (one r o t a t i o n
of w r i t e and one r o t a t i o n o f r e a d ) i s f i n i s h e d .
( a ) When SKA3 i s used:
By k e y i n g i n "D3", s i d e 0 and s i d e 1 r e a d l e v e l s are i n d i c a t e d on
DATA 0 and DATA 1 i n d i c a t o r s s u c c e s s i v e l y .
( b ) When c o n v e n t i o n a l SKA i s used:
Depress "F" key (STOP) and t h e n d e p r e s s "4" key t o e x e c u t e i t e m s
( 7 ) t h r o u g h (10) for s i d e 0 and s i d e 1 heads r e s p e c t i v e l y .
i s changed a l t e r n a t e l y by a d e p r e s s i o n o f "4* key.
The s i d e
If s i d e 1 is
s e l e c t e d , SIDE 1 i n d i c a t o r o f t h e SKA t u r n s on.
( 9 ) Observe t h e DATA i n d i c a t o r s w i t h a s l i g h t d e p r e s s i o n (very s l i g h t
-
3430
-
d e p r e s s i o n e a s y t o release: 1 0
209) by a f i n g e r on t h e t o p o f t h e
upper head.
(10) Confirm t h a t s i d e 0 and s i d e 1 r e a d l e v e l s measured i n i t e m ( 8 ) are
more t h a n 80% o f that i n i t e m ( 9 ) .
(11) Key i n 'CO"
(RECALIBRATE),
and e x e c u t e i t e m s (7) through (10) i n t h e
similar way.
(12) P o s s i b l e c a u s e s f o r i n s u f f i c i e n t head t o u c h :
Refer t o i t e m (11) o f "General method".
- 3431 -
3-4-9.
Check of Asymmetry
Adjustment i s applied only f o r a model with v a r i a b l e r e s i s t o r on the
PCBA MFD control.
( A ) Equipment
(1) Common screwdriver, small s i z e
( 2 ) Work disk
( 3 ) SKA o r u s e r ' s system
( 4 ) Oscilloscope ( n o t required when SKA3 i s used)
(B-1)
Check and adjustment procedure (General method)
(1) Connect an oscilloscope t o the READ DATA i n t e r f a c e l i n e .
Oscilloscope range: DC mode, 2V, 0.5
?,
lpsec
( 2 ) I n s t a l l a work disk and s t a r t the spindle motor.
(3) S e t t h e head t o t h e innermost t r a c k .
(4) Execute t h e head loading.
(5) Execute 1F write operation f o r one r o t a t i o n of t h e disk (125KHz of
WRITE DATA frequency f o r FD-55BR/FR and 250KHz f o r F D 5 5 G R ) .
(6) Measure the asymnetry r e f e r r i n g t o Fig.3414.
Note: Oscilloscope should be so s e t t h a t t h r e e READ DATA pulses can be
observed.
Asymmetry value s h a l l be measured a t t h e second READ
DATA pulse from the t r i g g e r pulse.
( 7 ) Confirm that t h e average asymmetry i s within t h e following range.
- 3432 -
Innennost t r a c k 1F asyymetry, FD-SSBR/FR:
0.7psec, Max.
FD-55GR: 0.35psec, Max.
Asymmetry
-
I
1F i n t e r v a l
Trigger
(Fig.3414) Measurement o f asymmetry
( 8 ) Execute i t e m s ( 5 ) through ( 7 ) f o r s i d e 0 and s i d e 1 heads r e s p e c t i v e l y .
(9) I f t h e v a l u e i n i t e m (7) o r (8) i s o u t o f t h e s p e c i f i e d range, a d j u s t
according t o t h e following procedure.
Note: T h i s i t e m i s a p p l i e d only for a model w i t h a v a r i a b l e r e s i s t o r f o r
asymmetry adjustment.
( a ) Adjust t h e v a r i a b l e r e s i s t o r , R l on t h e PCBA MFD c o n t r o l so t h a t t h e
asymmetry t a k e s a small value while r e p e a t i n g 1F w r i t e and 1F read
operations alternately.
(b) Repeat t h e o p e r a t i o n i n i t e m ( a ) f o r s i d e 0 and s i d e 1 heads a l t e r nately.
The v a r i a b l e r e s i s t o r s h a l l be so a d j u s t e d that both
asymmetry for s i d e 0 and s i d e 1 heads t a k e t h e minimum value.
Refer
t o Fig.220 i n i t e m 2-3-2.
(10) I f t h e v a l u e i n i t e m ( 7 ) or ( 8 ) i s o u t of t h e s p e c i f i e d range on a model
without v a r i a b l e r e s i s t o r , or i f t h e adjustment i n i t e m ( 9 ) cannot be
done s u f f i c i e n t l y , following c a u s e s a r e assumed.
( a ) Leakage f l u x d e n s i t y i n t h e environmental c o n d i t i o n o f t h e FDD i s
high :
-
3433
-
I f t h e r e i s some f l u x s o u r c e s n e a r t h e F D D s u c h a s magnet, t r a n s f o r m e r , motor, Brown t u b e , m a g n e t i z e d i r o n p l a t e , e t c . , t a k e it
a p a r t from t h e FDD.
Then measure t h e asymmetry a n d a d j u s t a g a i n .
(b) I n f e r i o r d i s k :
R e p l a c e t h e work d i s k w i t h a new o n e .
( c ) I n f e r i o r head:
R e p l a c e t h e head c a r r i a g e A s s ' y a c c o r d i n g t o i t e m 3-5-1.
( d ) I n f e r i o r PCBA MFD c o n t r o l :
R e p l a c e t h e PCBA a c c o r d i n g t o i t e m 3-5-7.
-3434
-
(B-2) Check a n d a d j u s t m e n t p r o c e d u r e ( C o n v e n t i o n a l SKA method)
(1) Connect a n c o n v e n t i o n a l SKA a c c o r d i n g t o i t e m 3-2-4
a n d s e t t h e FD PWR
s w i t c h t o t h e PSA s i d e .
( 2 ) Key i n "B1 F".
( 1 F DUTY)
( 3 ) C o n n e c t a n o s c i l l o s c o p e t o t h e DOUT t e r m i n a l o f t h e SKA.
O s c i l l o s c o p e range: DC mode, 2V, 0.1
%
O.2psec
(4) I n s t a l l a work d i s k .
( 5 ) S t a r t t h e s p i n d l e m o t o r by key "5".
(6) E x e c u t e d r i v e s e l e c t by key "0".
(MON i n d i c a t o r t u r n s o n ) .
(DSO i n d i c a t o r t u r n s o n ) .
(7) Key i n "CO" a n d c o n f i r m t h a t t h e TRACK i n d i c a t o r becomes "00".
(RECALIBRATE)
(8) Key i n "Cl"'.
(SEEK TMAX)
( 9 ) Key i n "D4".
(WRITE/READ LEVEL PRE 1 F )
(10) Measure t h e asymmetry as i n Fig.3415.
SKA DOUT
1 7 1 0
( F i g . 3415) Measurement o f asymmetry
(11) Confirm t h a t t h e a v e r a g e asymmetry i s w i t h i n t h e f o l l o w i n g r a n g e .
-
3435
-
Innermost t r a c k 1F asymmetry, FD-55BWFR:
0.7psec, Max.
FD-55GR: 0.35usec, Max.
( 1 2 ) Depress "4" key and execute items (9) through (11) f o r s i d e 0 and s i d e
1 heads respectively.
of "4" key.
The s i d e i s changed a l t e r n a t e l y by a depression
I f t h e s i d e 1 i s s e l e c t e d , SIDE 1 i n d i c a t o r of t h e SKA
t u r n s on.
(13) I f t h e value i n item (11) or (12) i s o u t of t h e s p e c i f i e d range, a d j u s t
according t o t h e following procedure.
Note: T h i s item i s applied only f o r a model with a v a r i a b l e r e s i s t o r f o r
asymmetry adjustment .
( a ) Adjust t h e v a r i a b l e r e s i s t o r , R l on the PCBA MFD c o n t r o l so t h a t t h e
asymmetry takes a small value by keying i n "D4".
(b) Execute t h e operation i n item ( a ) f o r both s i d e s a l t e r n a t e l y by
changing t h e s i d e by key "4".
The v a r i a b l e r e s i s t o r s h a l l be so
adjusted t h a t both asynrmetry f o r s i d e 1 and s i d e 0 heads take t h e
minimum value.
Refer t o Fig.220 i n item 2-3-2.
(14) I f t h e value i n item (11) o r ( 1 2 ) i s o u t of t h e s p e c i f i e d range on a
model without v a r i a b l e r e s i s t o r , or i f t h e adjustment i n item (13)
cannot be done s u f f i c i e n t l y , r e f e r t o item (10) of "General method".
-
3436
-
(B-3)
Check and adjustment procedure (SKA3 method)
(1) Connect t h e SKA3 r e f e r r i n g t o i t e m 3-2-4
and set t h e FD PWR switch t o
t h e PSA s i d e .
( 2 ) I n s t a l l a work d i s k .
( 3 ) S t a r t t h e s p i n d l e motor by key " 5 " .
( 4 ) Execute d r i v e select by key "0".
(MON i n d i c a t o r t u r n s o n ) .
(DSO i n d i c a t o r t u r n s o n ) .
( 5 ) Key i n "CO" and confirm t h a t t h e TRACK i n d i c a t o r becomes "00".
(RECALIBRATE)
(61 Key i n " C l " .
(SEEK TMAX)
(7) Key i n "DD".
(ASYMMETRY)
( 8 ) Write 1 F and r e a d o p e r a t i o n s a r e r e p e a t e d .
Asynmetry v a l u e s o f s i d e 0 and s i d e 1 heads a r e i n d i c a t e d on t h e DATA 0
and DATA 1 i n d i c a t o r s , XXXX ( n s ) s u c c e s s i v e l y a f t e r each c y c l e of
operation.
DATA 0 i n d i c a t e s a v a l u e of s i d e 0 head while DATA 1
i n d i c a t e s a v a l u e of s i d e 1 head.
The i n i t i a l d i g i t shows "E" which
has no r e l a t i o n t o t h i s i t e m .
(9) Confirm t h a t t h e both average v a l u e s are w i t h i n t h e following range.
Innermost t r a c k 1F asymmetry, FD-SSBWFR:
700nsec, Max.
FD-SSGR: 350nsec, Max.
(10) Key i n "F".
(STOP)
(11) I f t h e value i n i t e m (9) i s o u t of t h e s p e c i f i e d range, a d j u s t according
t o the f o l l o w i n g procedure.
-
3437
-
Note: This item is applied only for a model with a variable resistor for
asynmetry adjustment.
(a) Key in "DD" and adjust the variable resistor, R l on the PCBA MFD
control so that the asymmetry takes the minimum value. Since the
asymmetry changes at every measurement, rough adjustment will be
done.
(b) The variable resistor shall be so adjusted that both asymmetry for
side 0 and side 1 heads take the minimum value.
Refer to Fig.220 in
item 2-3-2.
(c) Key in "F".
(12) If the value in item (9) is out of the speci.fied range on a model
without variable resistor, or if the adjustment in item (11) cannot
be done sufficiently, refer to item (10) of "General method".
- 34313 -
3-4-10.
(A)
Check of Read Level
EQuipment
(1) Level d i s k
(21 SKA o r u s e r ' s system
(3) O s c i l l o s c o p e ( n o t r e q u i r e d when an SKA i s used)
(a-11 Check procedure (General method)
(1) U s e two channels o f an o s c i l l o s c o p e and connect them t o TP7 and TP8
( D i f f e r e n t i a t i o n amp.) on t h e PCBA MFD c o n t r o l .
O s c i l l o s c o p e range: AC m d e , 0.2
'L
0.5V
S e t both channels, 1 and 2 t o t h e above range.
Set e i t h e r of the
channels t o I n v e r t mode and Add both channels.
( 2 ) I n s t a l l a l e v e l d i s k and s t a r t t h e s p i n d l e motor.
( 3 ) S e t t h e head t o t h e innermost t r a c k .
(4) Execute t h e head l o a d i n g .
(5) Execute 2F w r i t e o p e r a t i o n f o r one r o t a t i o n o f t h e d i s k (250KHz of
WRITE DATA frequency f o r FD-55BR/FR
and 500KHz f o r FD-55GR).
(6) Measure t h e average amplitude (Vp-p) o f t h e read waveform a s i n
Fig. 3416.
(7) C a l c u l a t e t h e read l e v e l by s u b s t i t u t i n g t h e following e x p r e s s i o n
with t h e measured v a l u e i n i t e m (6) and READ LEVEL c a l i b r a t i o n value
(see l e v e l disk l a b e l ) .
Read l e v e l (True v a l u e ) = Measured v a l u e x
-
3439
-
100
C a l i b r a t i o n v a l u e ('I
(Fig.3416) Measurement of average read l e v e l (2F)
( 8 ) Confirm t h a t t h e t r u e value of t h e read l e v e l i s within the- following
range.
Innermost t r a c k read l e v e l , FD-55BR/GR:
8OOmVp-p, Min.
FD-55FR: 6OOmVp-p, Min.
(9) Execute items (5) through (8) f o r s i d e 0 and s i d e 1 heads r e s p e c t i v e l y .
(10) I f t h e value i n item (8) or (9) i s o u t of t h e s p e c i f i e d range,
following causes a r e assumed.
( a ) I n f e r i o r disk:
Disk and/or j a c k e t i s deformed o r damaged.
Replace t h e l e v e l d i s k
with a new one.
(b) Abnormal disk r o t a t i o n a l speed:
Check f o r t h e speed according t o item 3 4 - 6 .
(.c) I n f e r i o r head touch:
Check f o r t h e head touch according t o item 3-4-8.
(d) I n f e r i o r head:
Replace t h e head c a r r i a g e Ass'y according t o item 3-5-1.
( e ) I n f e r i o r PCBA MFD c o n t r o l :
-
3440
-
Replace the PCBA MFD control according t o item 3-5-7.
(11) Eject the l e v e l disk and r e l e a s e the Invert and Add modes of the
oscilloscope.
-
3441
-
(B-2) Check p r o c e d u r e (SKA method)
(1) Connect a n SKA and check cable r e f e r r i n g t o i t e m 3-2-4
and s e t t h e
FD PWR s w i t c h t o t h e PSA s i d e .
(2) I n s t a l l a level disk.
( 3 ) S t a r t t h e s p i n d l e motor by key " 5 " .
(4) Execute d r i v e select by key "0".
(MON i n d i c a t o r t u r n s o n ) .
( E O indicator turns on).
( 5 ) Key i n "CO" and c o n f i r m t h a t t h e TRACK i n d i c a t o r becomes "OO".
(RECALIBRATE)
(6) Key i n " C l " .
(SEEK TMAX)
( 7 ) Key i n '*D7".
(WRITE/-
LEVEL DIF 2F)
C a l i b r a t i o n v a l u e of the l e v e l d i s k s h o u l d be s e t p r e v i o u s l y i n t h e
SKA.
( 8 ) The DATA i n d i c a t o r , XXXX (mVo-p)
i n d i c a t e s t h e a v e r a g e r e a d level a t
TP7 and TP8 (Dif-amp.).
( a ) When SKA3 is used:
By k e y i n g i n "D7", s i d e 0 and s i d e 1 r e a d levels are i n d i c a t e d on
DATA 0 and DATA 1 i n d i c a t o r s s u c c e s s i v e l y .
(b) When c o n v e n t i o n a l SKA i s used:
Depress key "4" (STOP) and t h e n e x e c u t e i t e m ( 7 ) for s i d e 0 and
s i d e 1 heads r e s p e c t i v e l y .
d e p r e s s i o n of "4" key.
The s i d e is changed a l t e r n a t e l y by a
When s i d e 1 is s e l e c t e d , SIDE 1 i n d i c a t o r
o f t h e SKA t u r n s on.
( 9 ) Confirm that b o t h r e a d
levels are w i t h i n t h e f o l l o w i n g range.
-
3442
-
Innermost track read level, FD-5SBFtJGR:
4OOmVp-p, Min.
3OOmVo-p, Min.
FD-SSFR:
(10) If the value in item (9) is out of the specified range, refer to
item (10) of "General method".
(11) Eject the level disk.
-
3443
-
3-4-11.
Check of Resolution
( A ) Equipment
(11 Level d i s k
( 2 ) SKA or u s e r ' s system
( 3 ) O s c i l l o s c o p e ( n o t r e q u i r e d when an SKA i s used)
(B-1) Check procedure (General method)
(1) U s e two channels of an o s c i l l o s c o p e and connect them t o TP4 and TP5
-
(Pre-amp. 1 on t h e PCBA MFD c o n t r o l .
O s c i l l o s c o p e range: AC mode, 2OmV
0.1V
S e t both channels, 1 and 2 t o t h e above range.
S e t e i t h e r of t h e
channels t o I n v e r t mode and Add both channels.
( 2 ) I n s t a l l a l e v e l d i s k and s t a r t t h e s p i n d l e motor.
( 3 ) S e t t h e head t o t h e innermost t r a c k .
(4) Execute t h e head loading.
(5) Execute 1F w r i t e o p e r a t i o n f o r one r o t a t i o n of t h e d i s k (125KHz of
WRITE DATA frequency for FD-ssBR/FR and 250KHz f o r FD-55GR).
(6) Measure t h e average amplitude (VlF) a s i n Fig.3417.
(7) Execute 2F w r i t e o p e r a t i o n l i k e i n i t e m (51, doubled i n frequency t o
t h a t i n i t e m (5).
( 8 ) Measure t h e average amplitude (V2F) as i n Fig.3417.
-
3444
-
1F
2F
(Fig.3417) Measurement o f r e s o l u t i o n
(9) C a l c u l a t e t h e r e s o l u t i c n b y s u b s t i t u t i n g t h e following e x p r e s s i o n
w i t h t h e measured v a l u e s VlF, V2F, and RESOLUTION c a l i b r a t i o n v a l u e
(see l e v e l d i s k l a b e l ) .
Resolution ( t r u e v a l u e ) =
V2F
V1F
100
C a l i b r a t i o n value
(10) Confirm t h a t t h e t r u e v a l u e o f r e s o l u t i o n is w i t h i n t h e following
range.
Innermost t r a c k r e s o l u t i o n : 60%, Min.
(11) Execute items ( 5 ) through (10) f o r s i d e 0 and s i d e 1 heads
respectively.
(12) I f t h e value i n i t e m (10) or (11) i s o u t o f t h e s p e c i f i e d range,
following c a u s e s are assumed.
(a) Inferior disk:
Disk and/or j a c k e t is deformed or damaged.
Replace t h e l e v e l d i s k
w i t h a new one.
(b) I n f e r i o r d i s k r o t a t i o n a l speed:
Check f o r t h e speed according t o i t e m 3-4-6,
( c ) I n f e r i o r head touch:
Check f o r the head touch according t o i t e m 3-4-8.
-
3445
-
(d) Inferior head:
Replace the head carriage Ass'y according to item 3-5-1.
( e ) Inferior PCBA MFD control:
Replace the PCBA MFD control according to item 3-5-7.
( 1 3 ) Eject the level disk and release the Invert and Add modes of the
oscilloscope.
- 3446 -
( B - 2 ) Check p r o c e d u r e (SKA method)
(1) Connect a n SKA and check c a b l e r e f e r r i n g t o i t e m 3-2-4
and set t h e F D
PWR s w i t c h t o t h e PSA s i d e .
(2) I n s t a l l a l e v e l disk.
( 3 ) S t a r t t h e s p i n d l e motor by key "5".
( 4 ) Execute d r i v e select by key "0".
(MON i n d i c a t o r t u r n s o n ) .
(DSO i n d i c a t o r t u r n s o n ) .
(5) Key i n "CO" and c o n f i r m that t h e TRACK i n d i c a t o r becomes "00".
( RECALIBRATE)
(6) Key i n " C l " .
(SEEK TMAX)
( 7 ) Key i n "D8".
(RESOLUTION)
C a l i b r a t i o n v a l u e of t h e l e v e l d i s k s h o u l d b e s e t p r e v i o u s l y i n t h e
SKA.
( 8 ) The DATA i n d i c a t o r , X X X X
(Pre-amp. 1
( % I i n d i c a t e s t h e r e s o l u t i o n a t TP4 and TP5
.
(a) When SKA3 i s used:
By keying i n "D8", s i d e 0 and s i d e 1 r e s o l u t i o n s are i n d i c a t e d on
DATA 0 and DATA 1 i n d i c a t o r s s u c c e s s i v e l y .
(b) When c o n v e n t i o n a l SKA i s used:
Depress key "4" (STOP) and them e x e c u t e i t e m ( 7 ) for s i d e 0 and
s i d e 1 heads r e s p e c t i v e l y .
d e p r e s s i o n of "4" key.
The s i d e i s changed a l t e r n a t e l y by a
When s i d e 1 i s s e l e c t e d , SIDE 1 i n d i c a t o r
o f t h e SKA t u r n s on.
(9) Confirm that b o t h resolution v a l u e s are w i t h i n t h e f o l l o w i n g range.
- 3447 -
Innermost track r e s o l u t i o n : 609, Min.
(10) If the value i n i t e m (9) i s o u t of the s p e c i f i e d range, r e f e r t o i t e m
( 1 2 ) of "General method".
(11) Eject t h e level d i s k .
-
3448
-
3-4-12.
Check and Adjustment of Track Alignment
(A) Equipment
(1) Cross point screwdriver, M3
( 2 ) Alignment disk
( 3 ) Alignment adjustment jig or M3 screw of 1 5 m long
( 4 ) SKA or user's system
( 5 ) Oscilloscope
(6) Hygrometer
(71 Locking paint
(B) Precaution for check and adjustment
(11 Environmental condition
Check and adjustment of track alignment should be done in an
environment of room temperature of 20
humidity of 4 0
%
%
3OoC (68 % 86OF)
and relative
60%. Even if the environmental condition is within
the specified operational condition, extreemly high or low temperature,
or high or low humidity should be avoided.
Check and adjustment should
be done after two hours, Min. of storing the FDD and the alignment disk
in the above mentioned condition.
If the actual relative humidity is
out of the above range and it is difficult to control, use the humidity
calibration method in item (C) or (D).
(2)
Orientation of the FDD
It is recommended that the orientation of the FDD for the track
alignment check is the same as when the FDD is actually installed in
the user's system.
( 3 ) Alignment disk handling
-
3449
-
(a) Confirm that t h e i n t e r f a c e c a b l e is c o r r e c t l y connected b e f o r e power
on t o t h e FDD.
I f t h e odd numbered p i n s o f t h e i n t e r f a c e connector
are connected t o t h e even numbered p i n s , t h e d a t a on t h e d i s k might
be e r a s e d without a connuand from t h e h o s t s i d e .
(There w i l l be no
damage to t h e FDD i t s e l f ) .
(b) I n s t a l l and eject an alignment d i s k d u r i n g p o w e r on of t h e FDD.
( c ) Before i n s t a l l a t i o n , be sure t o check t h a t t h e write enable notch
of t h e alignment d i s k i s masked.
( d ) The i n s t a l l a t i o n o f an alignment d i s k t o t h e FDD should be a s less
t i m e a s possible.
Remove t h e d i s k immediately a f t e r t h e r e q u i r e d
check and adjustment.
- 3450 -
(C) Check and adjustment procedure (General method)
(1) U s e two channels of an o s c i l l o s c o p e and connect them t o TP7 and TP8
( D i f f e r e n t i a t i o n amp.) on t h e PCBA MFD c o n t r o l .
Also connect t h e
e x t e r n a l t r i g g e r o f t h e o s c i l l o s c o p e t o TP1 (Index) and apply p o s i t i v e
trigger.
Oscilloscope range: AC mode, 0.2
0.54,
20msec
S e t both channels, 1 and 2 t o t h e above ranoe.
S e t e i t h e r of t h e
channels t o I n v e r t mode and Add b o t h c h a n n e l s .
( 2 ) I n s t a l l an alignment d i s k and s t a r t t h e s p i n d l e motor.
( 3 ) Execute t h e head l o a d i n g .
(4) S e t t h e head t o t h e following alignment check t r a c k .
Alignment check t r a c k , 4 8 t p i (FD-55BR) : Track 16
9 6 t p i (FD-SSFWGR)
:
Track 32
(5) Confirm t h a t two l o b e p a t t e r n s a s i n Fig.3418 can be observed ( i t is
n o t necessary t h a t t h e l e v e l s of VA and VB a r e e q u a l ) .
T P ~and TP8 (Add)
48tpi
96tpi
(Fig.3418) Alignment check l o b e p a t t e r n
If only one l o b e p a t t e r n can be observed o r i f two l o b e s become one
-
3451
-
pattern, the head is not on the alignment check track.
In such event, execute step-out or step-in for the following tracks'
space to obtain the most similar waveform to that in Fig.3418.
48tpi: 2 tracks
96tpi: 4 tracks
Note: The above number of tracks to be stepped is required to make the
alignment track position be fit with the magnetized condition of
the basic phase "A" of the stepping motor.
If the stepped track
numbers are inassured, set it again from track 00 (TRACK 00 output
signal goes to TRUE).
For a 48tpi FDD, the lobe pattern in Fig.3418 shall be observed at
the even track, while it shall be observed at the track of multiple
number of four for a 96tpi FDD.
(61 After one or several step-outs from the check track, step in the head
to the check track again and measure VA and VB at that time.
(71 Calculate the true value of misalignment by substituting the value
in item (6) and ALIGNMENT calibration value (see alignment disk label,
attention to the side).
Misalignment (true value) =
-
VA-VB
(Larger value in VA
Calibration value)
-
L
VB
(Relative humidity-50) x K
"K" is humidity compensation factor.
48tpi : K-0.26
96tpi: K-0.42
e.g.
loo
96tpi, VA=O.58V, VB-0.61V, Calibration value=-6(%)
Relative humidity= 65%:
- 3452 -
Misalignment (true value)= {
0.61
x 0.42
OS6’ x 100-(-6)
-
(65-50)
= -5.2(%)
If the calculated value is positive, the magnetic head is shifted
inward from the reference position, while the head is shifted outward
from the reference position when the value is negative.
(8) Conversely, measure VA and VB when the head is on the alignment check
track by stepping-out after one o r several step-ins.
(9) Calculate the true value of misalignment as described in item (7).
(10) Confirm that both of the calculated values in items (7) and (9) are
within the following range.
True value of misalignment: 309, Max.
(11) Execute items (4) through (10) for side 0 and side 1 heads respectively.
(122 If the value in item (10) or (11) is out of the specified range, adjust
the track alignment according to the following procedure.
(a) Loosen the two fixing screws of the stepping motor a little.
(b) Insert the alignment adjustment jig of I43 screw from the back side
of the FDD as shown in Fig.3419.
(c) Repeat step-in and step-out operations and adjust the misalignment
to be the smallest on the alignment check track during both step-in
and step-out operations by turning the jig or the screw (stepping
motor moves little by little).
Note: When you adjust the alignment by observing the lobe pattern
using the oscilloscope, pay attention to the calibration value
on the alignment disk label and the ambient relative humidity.
-
3453
-
i) C a l i b r a t i o n value + (.Relative humidity
-
50) x k
0:
When t h e l e f t s i d e l o b e p a t t e r n l e v e l , VA i s assumed a s “l”,
l o b e p a t t e r n r a t i o should be so a d j u s t e d t h a t t h e r i g h t s i d e
lobe p a t t e r n l e v e l VB t a k e s t h e f o l l o w i n g value:
VB =
-
C a l i b r a t i o n value
ii) C a l i b r a t i o n value
+
+
( R e l a t i v e humidity
100
( R e l a t i v e humidity
-
5-j
x
-
50) x K
9 >_ 0 :
When t h e r i g h t s i d e l o b e p a t t e r n l e v e l , VB is aaanned a s “l“,
l o b e p a t t e r n r a t i o should be so a d j u s t e d t h a t t h e l e f t s i d e
l o b e p a t t e r n l e v e l VB t a k e s t h e following value.
=
-
C a l i b r a t i o n value
+ ( R e l a t i v e humidity
-
50)
K
100
e.g.
9 6 t p i , C a l i b r a t i o n value = -6%, R e l a t i v e humidity = 35%:
-6
+ (35
-
-
50) x 0.42 = -12.3 < 0
-6 + (35 - 50) x 0 . 4 2 = o.88
100
Therefore, t h e t a r g e t value o f VB when VB i s assumed a s “1”
i s 0.88.
( d ) Repeat t h e a d j u s t i n g o p e r a t i o n i n i t e m ( c ) a l t e r n a t e l y f o r s i d e 0
and s i d e 1 heads u n t i l t h e b o t h misalignment take t h e s m a l l e s t v a l u e .
( e ) Tighten t h e two f i x i n g screws o f t h e s t e p p i n g motor l i t t l e by
l i t t l e f o r a d j u s t i n g t h e t r u e value o f misalignment a f t e r t i g h t e n i n g
t h e screws w i t h t h e s p e c i f i e d t o r q u e t o be w i t h i n f20%.
( f ) Remove t h e alignment d i s k .
(9) Apply a drop o f l o c k i n g p a i n t to t h e head o f t h e s t e p p i n g motor
f i x i n g screws.
- 3454 -
(h) Check and a d j u s t t h e track 00 s e n s o r according to i t e m 3-4-13.
( i ) Check the track 00 stopper according to i t e m 3-4-14.
(131 Release the I n v e r t and Add modes of t h e o s c i l l o s c o p e .
Alignment adjustment j i g
(Fig.3419) Adjustment of track alignment
-
3455
-
(D) Check and a d j u s t m e n t p r o c e d u r e (SKA method)
(1) Connect a n SKA and check c a b l e r e f e r r i n g t o i t e m 3-2-4 and s e t t h e FD
PWR s w i t c h t o t h e PSA s i d e .
( 2 ) Use two c h a n n e l s of an o s c i l l o s c o p e .
Connect t h e 1st c h a n n e l t o t h e
DOUT t e r m i n a l o f t h e SKA and t h e 2nd c h a n n e l t o t h e D I F t e r m i n a l of
t h e SKA.
Apply p o s i t i v e t r i g g e r by DOUT t e r m i n a l .
O s c i l l o s c o p e range, The 1st channel: DC mode, 2V, 20msec
The 2nd c h a n n e l : AC mode, 0.2
( 3 ) Key i n "B9 F".
Q,
0.5V, 20msec
(INDEX o b s e r v a t i o n )
( 4 ) T h i s i t e m i s a p p l i e d o n l y f o r 9 6 t p i FDD (FD-SSFR/GR) u s i n g a conventi o n a l SKA.
Refer t o i t e m 3-2-4-7.
Key i n "DD".
(H GAIN i n d i c a t o r t u r n s On).
(5) I n s t a l l an alignment d i s k .
(6) S t a r t t h e s p i n d l e motor by key "5".
( 7 ) Execute d r i v e select by key "0".
(MON i n d i c a t o r t u r n s o n ) .
(DSO i n d i c a t o r t u r n s o n ) .
( 8 ) Key i n '*CO" and confirm that t h e TRACK i n d i c a t o r becomes "00".
(RECALIBRATE)
( 9 ) S e t t h e head t o t h e a l i g n m e n t check t r a c k by t h e f o l l o w i n g o p e r a t i o n :
4 8 t p i (FD-55BR): Key i n "C2 16" and c o n f i r m t h a t t h e TRACK i n d i c a t i o n
becomes "16".
% t p i (FD-SsFR/GR): Key i n "C2 32" and confirm t h a t t h e TRACK
i n d i c a t i o n becomes "32".
(10) Confirm that two lobe p a t t e r n s a s i n Fig.3418 c a n be o b s e r v e d by t h e
-
3456
-
o s c i l l o s c o p e ( i t i s n o t n e c e s s a r y t h a t t h e l e v e l s o f VA and VB are
equal)
.
I f o n l y one l o b e p a t t e r n can be o b s e r v e d o r i f two l o b e s become one
p a t t e r n , t h e head i s n o t on t h e a l i g n m e n t check t r a c k .
I n such e v e n t , e x e c u t e s t e p - i n o r s t e p - o u t o f t h e f o l l o w i n g t r a c k s '
space t o o b t a i n t h e most s i m i l a r waveform t o t h a t i n Fig.3418.
Step
o p e r a t i o n c a n be done by key "8)' (STEP-IN) and key "9" (STEP-OUT).
By
a d e p r e s s i o n of t h e s e keys, head w i l l move f o r one t r a c k s p a c e .
48tpi: 2 tracks
96tpi: 4 tracks
Note: The above number o f t r a c k s t o be s t e p p e d i n r e q u i r e d t o make t h e
alignment t r a c k p o s i t i o n be f i t w i t h t h e magnetized c o n d i t i o n of
t h e b a s i c phase "A" o f t h e s t e p p i n g motor.
For a 4 8 t p i FDD, t h e l o b e p a t t e r n s h a l l be observed a t t h e even
t r a c k , w h i l e i t s h a l l be o b s e r v e d a t t h e t r a c k o f m u l t i p l e number
o f f o u r f o r a 9 6 t p i FDD.
(11) Key i n "E3".
(ALIGNMENT)
C a l i b r a t i o n v a l u e o f t h e alignment d i s k and environmental r e l a t i v e
humidity should be s e t p r e v i o u s l y i n t h e SKA.
(12) The DATA i n d i c a t o r , XXXX
(%)
i n d i c a t e s t h e misalignment v a l u e .
,'-(+I
mark means t h a t t h e head i s s h i f t e d inward from t h e r e f e r e n c e p o s i t i o n ,
while
-
mark means t h a t t h e head i s s h i f t e d outward.
( a ) When SKA3 i s used:
By keying i n "E3", s i d e 0 and s i d e 1 v a l u e s are i n d i c a t e d on DATA 0
and DATA 1 i n d i c a t o r s s u c c e s s i v e l y .
or
2 (OUT).
"IN"
The i n i t i a l d i g i t i n d i c a t e s /(I1
means t h e v a l u e a f t e r s t e p - i n o p e r a t i o n , w h i l e
"OUT" means t h e v a l u e a f t e r s t e p - o u t o p e r a t i o n .
-
3457
-
(b) When conventional SKA i s used:
Key i n "0" following t h e o p e r a t i o n o f i t e m (11). The s i d e i s changed
a l t e r n a t e l y by a d e p r e s s i o n o f "0" key d u r i n g t h e execution o f E3
command.
When s i d e 1 i s s e l e c t e d , SIDE 1 i n d i c a t o r o f t h e SKA t u r n s
on.
(13) Confirm t h a t a l l t h e misalignment v a l u e s a r e w i t h i n t h e following range.
Misalignment value: Less t h a n 230%
(14) Depress "F" key.
CSTOP)
(15) I f t h e value i n i t e m (13) i s o u t o f t h e s p e c i f i e d range, a d j u s t t h e
t r a c k alignment according t o t h e f o l l o w i n g procedure.
( a ) Loosen t h e two f i x i n g screws o f t h e s t e p p i n g motor a l i t t l e .
( b ) I n s e r t t h e alignment adjustment j i g o r M3 screw from t h e back s i d e
o f t h e FDD as shown i n Fig.3419.
( c ) Key i n "E3" and a d j u s t t h e j i g o r M3 screw so that t h e DATA i n d i c a t o r ,
XXXX
(%)
The s t e p p i n g motor moves l i t t l e by
shows t h e s m a l l e s t value.
l i t t l e when t h e j i g o r t h e screw i s turned.
(d) Repeat t h e a d j u s t i n g o p e r a t i o n i n i t e m (c) a l t e r n a t e l y f o r s i d e 0 and
s i d e 1 heads u n t i l t h e both misalignment t a k e t h e smallest v a l u e .
Refer t o i t e m (12).
(e) Tighten t h e two f i x i n g screws of t h e s t e p p i n g motor l i t t l e by l i t t l e
t o o b t a i n t h e value w i t h i n 220% on t h e DATA i n d i c a t o r when t h e screws
a r e tightened with t h e specified torque.
( f ) Remove t h e alignment d i s k .
-
3458
-
( 9 ) Apply a drop of locking p a i n t on t h e screw head of t h e s t e p p i n g
motor f i x i n g screws.
( h ) Check and a d j u s t t h e t r a c k 00 sensor according t o item 3-4-13.
( i )Check t h e t r a c k 00 s t o p p e r according t o i t e m 3-4-14.
(16) Release t h e I n v e r t and Add d e s of t h e o s c i l l o s c o p e .
(17) When t h e H G A I N i n d i c a t o r of t h e conventional SKA i s on f o r a 9 6 t p i
FDD, key i n "DD" a g a i n t o t u r n o f f t h e i n d i c a t o r .
- 3459 -
3-4-13. Check and Adjustment o f Track 00 S e n s o r
( A ) Equipment
(1) C r o s s p o i n t s c r e w d r i v e r , M3
( 2 ) Work disk
(3) Alignment d i s k
(4) SKA o r u s e r ' s system
(5) O s c i l l o s c o p e o r d i g i t a l v o l t m e t e r ( n o t r e q u i r e d when SKA3 i s used)
(6) Locking p a i n t
(B-1)
Check and a d j u s t m e n t p r o c e d u r e ( G e n e r a l method)
Note: Check and a d j u s t m e n t o f t h e t r a c k 00 s e n s o r u s i n g t h i s g e n e r a l
method is n o t so p r e c i s e .
I t i s recommended t o u s e an SKA method
as much as p o s s i b l e .
(1) Connect a n o s c i l l o s c o p e o r d i g i t a l v o l t m e t e r t o TP3 (Track 00 s e n s o r )
on t h e PCBA ME'D c o n t r o l .
O s c i l l o s c o p e range: DC mode, 1V
( 2 ) I n s t a l l a work d i s k and s t a r t t h e s p i n d l e motor.
( 3 ) Execute t h e head l o a d i n g
( 4 ) Confirm t h a t t h e v o l t a g e a t TP3 i s w i t h i n t h e f o l l o w i n g range when t h e
head i s s e t t o t r a c k 00.
Track 00 p o s i t i o n TP3 v o l t a g e : 3.7V. Min.
(5) Turn t h e p o w e r o f f o f t h e FDD and t h e n t u r n i t on a g a i n a t t h e t r a c k 00
position.
Confirm t h a t t h e head c a r r i a g e once moves t o i n n e r t r a c k and
t h e n it r e t u r n s t o t r a c k 00 p o s i t i o n ( a u t o - r e c a l i b r a t i o n ) .
- 3460 -
( 6 ) S e t t h e head t o t h e following t r a c k .
4 8 t p i (FD-55BR): Track 02
9 6 t p i (FD55FWGR): Track 04
(7) Confirm t h a t t h e v o l t a g e a t TP3 i s w i t h i n t h e following range a t t h e
track position i n i t e m (6).
TP3 v o l t a g e a t t r a c k 02 ( 4 8 t p i ) or 04 ( 9 6 t p i ) : 0.5v, b x .
(8) I f t h e value i n i t e m ( 4 1 ,
(51, or (7) i s o u t o f t h e s p e c i f i e d range,
a d j u s t t h e p o s i t i o n o f t h e t r a c k 00 s e n s o r according t o t h e following
procedure.
( a ) Connect t h e o s c i l l o s c o p e t o TP7 o r TP8 ( D i f f e r e n t i a t i o n amp.) o f t h e
PCBA MFD c o n t r o l .
Oscilloscope range: AC mode, 0.2
(b) I n s t a l l an alignment d i s k .
?,
0.5V,
20msec
The t r a c k alignment should be p r e v i o u s l y
a d j u s t e d according t o i t e m 3-4-12.
( c l Make t h e head move t o t h e p o s i t i o n where t h e l o b e p a t t e r n a s i n Fig.
3418 can be observed.
( d ) Remove t h e alignment d i s k .
(e) Connect t h e o s c i l l o s c o p e or d i g i t a l v o l t m e t e r t o TP3 (Track 00 s e n s o r )
on t h e PCBA MFD c o n t r o l .
Oscilloscope range: DC mode, 1 V
( f ) S t e p o u t t h e head f o r t h e following space from t h e p o s i t i o n where
t h e normal l o b e p a t t e r n i s observed.
4 8 t p i : 15 t r a c k s ( t h e head w i l l be on t r a c k 01)
9 6 t p i : 30 t r a c k s ( t h e head w i l l be on t r a c k 0 2 )
- 3461 -
( g ) I n s t a l l a work d i s k .
( h ) Loosen t h e t h r e e f i x i n g screws o f t h e PCBA MFD c o n t r o l (see Fig.3420)
a n d move t h e PCBA p o s i t i o n a l i t t l e so t h a t t h e v o l t a g e a t TP3 f a l l s
w i t h i n t h e following range.
TP3 v o l t a g e a t t r a c k 01 ( 4 8 t p i ) o r t r a c k 02 ( 9 6 t p i ) :
1V
3V (2V, approx. c e n t e r )
( i )Confirm the items ( 4 ) t h r o u g h (7).
(j) A d j u s t t h e t r a c k 00 s e n s o r p o s i t i o n so t h a t t h e v a l u e s i n i t e m s
( h ) and ( i )s a t i s f y t h e s p e c i f i c a t i o n when t h e screws have been
t i g h t e n e d w i t h t h e s p e c i f i e d t o r q u e (6Kg.cm).
( k ) Check t h e t r a c k 00 s t o p p e r a c c o r d i n g t o t i e m 3-4-14.
-
3462
-
Head carriage Ass 'Y
rack 00 sensor
PCBA
fixing screws
(Fig.3420) Adjustment of track 00 sensor
-
3463
-
(B-2) Check and adjustment procedure (Conventional SKA method)
(1) Connect an SKA and check c a b l e r e f e r r i n g t o item 3-2-4
and set t h e F D
PUR switch t o t h e PSA s i d e .
( 2 ) Use two channels of o s c i l l o s c o p e and connect them a s follows:
( a ) The 1st channel: SKA DOUT t e r m i n a l
(b) The 2nd channel: TP3 (Track 00 s e n s o r ) on PCBA MFD c o n t r o l ,
2V range
( c ) E x t e r n a l t r i g g e r : DIRECTION SELECT i n t e r f a c e s i g n a l ( I n t e r f a c e
connector p i n No.18) o r p i n 3 o f 53 ( r e s i s t o r
network RA1 f o r t e r m i n a t o r ) on t h e PCBA MFD
control,
( 3 ) Key i n "B8 F".
(+) t r i g g e r .
(STEP o b s e r v a t i o n )
( 4 ) I n s t a l l a work d i s k and s t a r t t h e s p i n d l e motor by key "5".
(MON i n d i c a t o r t u r n s o n ) .
(5) Execute d r i v e select by key "0".
(DSO i n d i c a t o r t u r n s o n ) .
( 6 ) S e t t h e s t e p r a t e and t h e s e t t l i n g t i m e a s f o l l o w s r e f e r r i n g t o i t e m
3-2-4-3.
FD-55BR, 6msec seek model: S t e p r a t e limsec, S e t t l i n g t i m e lsmsec
FD-55BR, 4msec seek model: S t e p rate 4msec, S e t t l i n g time lOmsec
FD-55FFUGR: S t e p r a t e 3moec, S e t t l i n g t i m e 15msec
(7) Key i n "CO" and confirm t h a t t h e TRACK i n d i c a t o r becomes "00".
( RECALIBRATE)
( 8 ) Key i n "CS".
(TOO TIMING)
- 3464 -
Measure t h e t i m i n g , tA a c c o r d i n g t o Fig.3421.
t A shall b e w i t h i n
t h e following range.
Track 00 d e t e c t i o n t i m i n g :
FD-55BR (6msec s e e k model) and FD-55FWGR: tA= 7.5 5 1.5msec
FD-55BR (4msec s e e k model): t A = 6 . 3 2 1.3msec
DIRECTION SELECT
(External t r i g g e r )
Step-in
1
2
3
4
5
1
2
3
4
5
3
4
5
SKA DOUT
TP3
(Track 00 s e n s o r )
tA
4 8 t p i (FD-55BR)
Track 00
detection
1
2
3
4
5
4
1
2
SKA DOUT
TP3
(Track 00 s e n s o r )
__ I 1.
2v
--
9 6 t p i (FD55FR/GR)
ov
Track 00 d e t e c t i o n
(Fig.3421) Track 00 s e n s o r o u t p u t waveform
(10) Key i n "F".
(STOP)
(11) Turn t h e FD PWR s w i t c h of t h e SKA off a t t h e t r a c k 00 p o s i t i o n and
t h e n set it a g a i n t o t h e PSA s i d e .
Confirm that t h e head carriage
once moves t o i n n e r t r a c k and t h e n it r e t u r n s to t r a c k 00 p o s i t i o n
-
3465
-
(auto-recalibration).
(12) I f t h e v a l u e i n i t e m (9) o r (11) i s o u t of t h e s p e c i f i e d range, a d j u s t
t h e p o s i t i o n o f t h e t r a c k 00 s e n s o r according t o t h e following
procedure.
( a ) Connect t h e 2nd channel of t h e o s c i l l o s c o p e t o
m,PT
o r TP8 (Differen-
t i a t i o n amp.) o f t h e PCBA MFD c o n t r o l and change t h e t r i y g e r t o t h i s
channel.
Oscilloscope range: AC mode, 0.2
( b ) I n s t a l l an alignment d i s k .
%
O.SV, 20msec
The t r a c k alignment should be p r e v i o u s l y
a d j u s t e d according t o i t e m 3-4-12.
(c) Key i n "CO" and confirm t h a t t h e t r a c k i n d i c a t o r becomes "00".
(RECALIBRATE).
( d ) Key i n t h e following number and confirm t h a t two l o b e p a t t e r n s a s i n
Fig.3418 can be observed.
4 8 t p i : C2 16
9 6 t p i : C2 32
I f normal l o b e p a t t e r n cannot be observed, move t h e head t o t h e
t r a c k p o s i t i o n where t h e t y p i c a l l o b e p a t t e r n can be observed by
s t e p p i n g i n by key "8" o r by s t e p p i n g o u t by key "9".
(e) Remove t h e alignment d i s k .
( f ) Key i n t h e f o l l o w i n g number.
(SET TRACK NUMBER)
4 8 t p i : E4 16
% t p i : E4 32
(9) Key i n "C2 00".
Don't key i n ' T O " .
(SEEK 00)
(RECALIBRATE)
-
3466
-
( h ) Change t h e c o n n e c t i o n of t h e oscilloscope as i n i t e m ( 2 ) .
( i ) Key i n "CS".
(TOO TIMING)
(1) Loosen t h e three f i x i n g screws o f t h e PCBA ME'D c o n t r o l (see Fig.3420)
a n d move t h e PCBA p o s i t i o n so that t h e t r a c k 00 d e t e c t i o n t i m i n g falls
within t h e s p e c i f i e d range.
(k) Repeat t h e a d j u s t m e n t so t h a t t h e t i m i n g s a t i s f i e s t h e s p e c i f i c a t i o n
when t h e screws have b e e n t i g h t e n e d w i t h t h e s p e c i f i e d t o r q u e (6Kg.cm).
(L) Check t h e t r a c k 00 stopper a c c o r d i n g t o i t e m 3-4-14.
-
3467
-
(B-3) Check and adjustment procedure (SKA3 method)
(1) Connect t h e SKA3 and check cable r e f e r r i n g t o i t e m 3-2-4
and s e t t h e
FD PWR switch t o t h e PSA s i d e .
( 2 ) I n s t a l l a work d i s k .
( 3 ) S t a r t t h e s p i n d l e motor by key "5".
( 4 ) Execute d r i v e select by key "0".
(MON i n d i c a t o r t u r n s o n ) .
(DSO i n d i c a t o r t u r n s o n ) .
( 5 ) S e t t h e s t e p r a t e and t h e s e t t l i n g t i m e a s f o l l o w s r e f e r r i n g t o i t e m
3-2-4-3.
FD-SSBR,
6msec seek model: S t e p r a t e gmsec, S e t t l i n g t i m e l5msec
FD-55BR,
4msec seek model: S t e p r a t e Imsec, S e t t l i n g t i m e lOmsec
S t e p r a t e 3msec, S e t t l i n g t i m e 15msec
FD-sSFR/GR:
(61 Key i n "CO" and confirm t h a t t h e TRACK i n d i c a t o r becomes "00".
(RECALIBRATE)
(7) FD-55BR,
FD-SSBR,
FD-SsFR/GR:
6msec seek model: Key i n nC5".
4msec seek model: Key i n "CSA"
Key i n "C5".
(TOO T I M I N G )
(TOO TIMING, 4msec model)
(TOO TIMING)
(8) Confirm that DATA 0 i n d i c a t o r , XXXX ( m s ) i n d i c a t e s a value w i t h i n t h e
following range.
Value on DATA 1 i n d i c a t o r must be ignored.
Track 00 d e t e c t i o n t i m i n g
DATA 0 = 7.5 f 1. Smsec
FD-55BR
(6msec seek model)
FD-55BR
(4msec seek m d e l ) : DATA 0 = 6.3 2 1.3msec
FD-SSFWGR:
:
DATA 0 = 7.5 f 1.5msec
(9) Depress "F" key.
(STOP)
-
3468
-
(10) Turn t h e F D PWR switch o f t h e SKA3 o f f a t t h e t r a c k 00 p o s i t i o n and
then s e t it a g a i n t o t h e PSA s i d e .
Confirm t h a t t h e head c a r r i a g e
once moves t o i n n e r t r a c k and then i t r e t u r n s t o t h e t r a c k 00 p o s i t i o n
(auto-recalibration).
(11) If t h e value i n i t e m ( 8 ) o r (10) i s o u t o f t h e s p e c i f i e d range, a d j u s t
t h e p o s i t i o n of t h e t r a c k 00 s e n s o r a c c o r d i n g t o i t e m (B-2)-(12),
conventional SKA method excluding t h e s t e p ( h ) .
-
3469
-
3-4-14.
Check o f Track 00 S t o p p e r
( A ) Equipment
(1) SKA o r u s e r ' s system
(B-1)
Check p r o c e d u r e (General method)
(1) S e t t h e head t o t r a c k 00.
( 2 ) S t e p o u t t h e head from t h e t r a c k 00 p o s i t i o n .
( 3 ) Confirm t h a t t h e head c a r r i a g e d o e s n o t move by t h e s t e p - o u t command
(head c a r r i a g e rests on t r a c k 0 0 ) .
( 4 ) Repeat s t e p - i n
and s t e p - o u t o p e r a t i o n s between t r a c k 00 and t r a c k XX.
Confirm t h a t no impact sound can b e h e a r d between t h e head c a r r i a g e
and t h e o t h e r f i x i n g p a r t s ( t r a c k 00 s t o p p e r ) .
(5) Turn o f f t h e FDD p o w e r and d e p r e s s t h e head c a r r i a g e l i g h t l y toward
t h e rear end o f t h e FDD w i t h f i n g e r s .
( 6 ) Turn on t h e FDD p o w e r .
R e f e r t o arrow mark i n Fig.3422.
Confirm t h a t t h e head c a r r i a g e once moves t o
i n n e r t r a c k a u t o m a t i c a l l y and t h e n it r e t u r n s t o t r a c k 00 p o s i t i o n .
(7) Confirm t h a t t h e TRACK 00 o u t p u t s i g n a l i s Low d u r i n g DRIVE SELECTed.
-
3470
-
ead carriage A s s ’ y
tepping motor
Depress head carriage
toward the rear end
Track 0 0 sensor
(Fig.3422) Check of track 00 stopper
-
3471
-
(B-2)
Check procedure (SKA method)
(1) Connect a n SKA r e f e r r i n g t o i t e m 3-2-4
a n s s e t t h e FD PWR s w i t c h t o t h e
PSA s i d e .
( 2 ) Execute d r i v e select by key "0"-
(DSO i n d i c a t o r t u r n s o n ) .
( 3 ) Key i n "CO" and c o n f i r m t h a t t h e -'IT&CKi n d i c a t o r becomes "00".
( RECALIBRATE)
( 4 ) S e t t h e s t e p r a t e and t h e s e t t l i n g time as f o l l o w s r e f e r r i n g t o i t e m
3-2 -4- 3.
FD-55BR (6msec s e e k model): S t e p rate 6msec, S e t t l i n g t i m e 15msec
FD-55BR (4msec s e e k model): S t e p r a t e Imsec, S e t t l i n g t i m e l O m s e c
FD-SSFR/GR:
( 5 ) Key i n "9".
S t e p rate 3msec, S e t t l i n g t i m e 15msec
(STEP OUT)
(6) Confirm t h a t t h e head c a r r i a g e d o e s n o t move even i f "9" i s keyed i n
(head c a r r i a g e rests on t r a c k 0 0 ) .
( 7 ) Key i n "CO" and key i n "C5".
(STEP TIMING)
( 8 ) Confirm t h a t no impact sound c a n be h e a r d between t h e head
carriage
and t h e o t h e r f i x i n g p a r t s ( t r a c k 00 s t o p p e r ) .
(9) Turn o f f t h e FD PWR s w i t c h o f t h e SKA and d e p r e s s t h e head c a r r i a g e
l i g h t l y towards t h e rear end o f t h e FDD w i t h f i n g e r s .
R e f e r to a r r o w
w r k i n Fig.3422.
(10) Turn on t h e FD PWR s w i t c h a g a i n .
Confirm t h a t t h e head c a r r i a g e once
m v e s t o i n n e r t r a c k a u t o m a t i c a l l y and t h e n i t r e t u r n s t o t r a c k 00
position.
(11) Confirm that t h e TOO i n d i c a t o r o f t h e SKA i s on.
-
3472
-
3-4-15.
Check and Adjustment o f Index B u r s t Timing
( A ) Equipment
(1) Cross p o i n t screwdriver, M3
( 2 ) Alignment d i s k
( 3 ) SKA o r u s e r ' s system
( 4 ) Oscilloscope ( n o t r e q u i r e d when an SKA i s used)
(B-1) Check and adjustment proceudre (General method)
(1) U s e two channels of an o s c i l l o s c o p e .
Connect t h e 1st channel t o TP1
(index) on t h e PCBA W D c o n t r o l and t h e 2nd channel t o TP4 o r TP5
(Pre-amp. 1
.
Apply p o s i t i v e t r i g g e r by TP1.
Oscilloscope range, The 1st channel: I
X mode, 2V, SOusec
The 2nd channel: AC mode, 0.5V,
SOpsec
(2) I n s t a l l an alignment d i s k and s t a r t t h e s p i n d l e motor.
( 3 ) Execute t h e head loading.
( 4 ) S e t t h e head t o t h e following t r a c k :
4 8 t p i (FD55BR): Track 0 1
9 6 t p i (FD-55FR/GR) I Track 02
(5) Measure t h e index b u r s t timing i n Fig.3423.
(6) S u b s t i t u t e t h e following e q u a t i o n w i t h t h e measured value i n i t e m ( 5 )
and INDEX T I M I N G c a l i b r a t i o n value (see alignment d i s k label).
Index b u r s t timing ( t r u e v a l u e ) = Measured v a l u e
-
3473
-
-
C a l i b r a t i o n value (PSI
T P ~(Index)
J
1
I
TP4 o r TP5
- I Index b u r s t t i m i n g
(Fig.3423) Index b u r s t timing
(7) Confirm t h a t t h e t r u e v a l u e o f t h e index b u r s t timing i s w i t h i n t h e
following range.
Index b u r s t timing, FD-55BWFR:
FD-55GR:
200 f 200psec
165 2 165psec
(8) I f t h e value i n i t e m (7) is o u t o f t h e s p e c i f i e d range, a d j u s t t h e
index s e n s o r p o s i t i o n according t o t h e f o l l o w i n g procedure.
( a ) Loosen t h e two f i x i n g screws (see Fig.3424) o f t h e PCBA f r o n t OPT and
a d j u s t i t s p o s i t i o n t o make t h e t r u e v a l u e o f t h e index b u r s t t i m i n g
f a l l i n t h e s p e c i f i e d range i n i t e m (7).
(b) Repeat t h e adjustment so t h a t t h e t r u e v a l u e o f t h e index b u r s t t i m i n g
f a l l s i n t h e range of i t e m (7) when t h e f i x i n g screws have been
t i g h t e n e d with t h e s p e c i f i e d t o r q u e (4.5Kg.cm).
( 9 ) Remove t h e alignment d i s k .
-
3474
-
CBA f r o n t OPT
justing direction
PCBA f r o n t OPT
Index sensor
(Fig.3424) Adjustment o f index sensor
-
3475
-
(B-2) Check and a d j u s t m e n t p r o c e d u r e (SKA method)
(1) Connect a n SKA and check c a b l e r e f e r r i n g t o i t e m 3-2-4
and set t h e FD
PUR s w i t c h t o t h e PSA s i d e .
( 2 ) I n s t a l l a n alignment d i s k .
( 3 ) S t a r t t h e s p i n d l e motor by key "5".
( 4 ) Execute d r i v e select by key "0".
( 5 ) Key i n "CO"
(MON i n d i c a t o r t u r n s o n ) .
(DSO i n d i c a t o r t u r n s o n ) .
and confirm t h a t t h e TRACK i n d i c a t o r becomes " 0 0 " .
( RECALIBRATE1
( 6 ) S e t t h e head t o t h e i n d e x check t r a c k by t h e f o l l o w i n g o p e r a t i o n :
4 8 t p i (FD-55BR): Key i n "C2 01" and c o n f i r m t h a t t h e TRACK i n d i c a t i o n
becomes "01".
9 6 t p i (FD-SSFRJGR):
Key i n "C2 02" and c o n f i r m t h a t t h e TRACK
i n d i c a t i o n becomes "02".
(7) Key i n "E6".
(INDEX TIMING)
C a l i b r a t i o n v a l u e o f t h e i n d e x t i m i n g s h o u l d b e set p r e v i o u s l y i n t h e
SKA.
(8) Confirm t h a t t h e DATA i n d i c a t o r , XXXX (us) i n d i c a t e s t h e v a l u e w i t h i n
t h e f o l l o w i n g range.
Index b u r s t t i m i n g , FD-55BR/FR:
200 2 200psec
FD-55GR: 1 6 5 2 165psec
(9) Key i n "F".
(STOP)
(10) I f t h e v a l u e i n i t e m (8) i s o u t of t h e s p e c i f i e d range, a d j u s t t h e
-
3476
-
index sensor p o s i t i o n according t o t h e following procedure.
(a) Loosen t h e t w o f i x i n g screws (see Fig.3424) of t h e PCBA f r o n t OFT and
i t s p o s i t i o n so that t h e DATA i n d i c a t i o n under execution o f i t e m (7)
shows t h e median v a l u e i n t h e s p e c i f i e d range o f i t e m ( 8 ) .
(b) Repeat t h e adjustment so that t h e DATA i n d i c a t i o n takes t h e median
value when t h e f i x i n g screws have been t i g h t e n e d with the s p e c i f i e d
torque (4.5Kg.cm).
(c) Depress "F" key.
(STOP)
(11) Remove t h e alignment d i s k .
- 3477 -
3-5. MINTENANCE PARTS REPLACEMENT
3-5-1. Replacement of Head Carriage Ass'y
(A)
Fquipment
(1) Cross point screwdriver, M3
( 2 ) Conmon screwdriver, small size
(3) A pair of tweezers
(4) Alcohol and gauze
(5) Locking paint
(6) Oil (FLOIL 946P)
(7) SKA or user's system
(8) Required equipment for each referring item
(B) Replacement procedure
(1) Disconnect the head connector (J4).
(2) Remove the set ann sub Ass'y
(Fig.405, No.3) by removing two fixing
screws (Fig.405, S8).
( 3 ) Apply alcohol to locking paint areas on the head carriage.
There
are four points of shaded area as shown in Fig.3501 and Fig.3502.
(4) Wait a minute.
(5) Turn the FDD over so that the spindle motor (bottom side) goes up.
Depress A point of the steel belt (Table 402C, No.23~) according to
Fig.3501 in the direction of arrow mark using a common screwdriver or
rear end of a pair of tweezers, to make the locking paint 1 free.
(6) Depressing B area of the belt spring (Table 402C, No.23d) according to
Pig.3501 with fingers in the d i m t i o n of arrow mark, remove the steel
belt from the belt hook 1 of the carriage using a pair of tweezers.
-
3501
-
B e l t hook 1
r L o c k i n g paint 1
7
Lock:ing p a i n t
r
27
\
/ rsteel
\\
Even d i s t a n c e ,
S t e p (15)
S t e p (6)
L
B e l t spring
Locking p a i n t 3
J
\Spring
guide
(Fig.3501) B e l t hook a r e a i n t h e back s i d e of c a r r i a g e
B e l t hook 2
7
f
Locking p a i n t 4
(Fig.3502) B e l t hook area on t h e upper s i d e of t h e c a r r i a g e
( 7 ) Make t h e belt s p r i n g s l i d e i n t h e r e v e r s e d i r e c t i o n o f t h e a r r o w mark
i n Fig.3501 u s i n g a p a i r of tweezers, and make t h e l o c k i n g p a i n t 2
and 3 free.
Then remove t h e belt s p r i n g from t h e s p r i n g guide of t h e
carriage.
( 8 ) P l a c e t h e FDD
50
t h a t t h e t o p s i d e comes up.
P u l l C p o i n t o f t h e steel
belt i n t h e d i r e c t i o n of a r r o w mark i n Fig.3502 u s i n g a p a i r o f tweezers
to make t h e l o c k i n g p a i n t 4 f r e e .
-
3502
Then r e m v e t h e steel belt from t h e
-
belt hook 2 o f t h e c a r r i a g e .
(9) Remove t h r e e screws (Fig.405, S1) t o remove t h e s p r i n g g u i d e s A and
B (Fig.405, Nos.24
h
25) which f i x two guide s h a f t s (Table 402C, No.23b).
(10) Remove t h e head c a r r i a g e Ass'y with t h e guide s h a f t s .
Refer t o Fig.
3503.
(11) Remove a screw (Fig.405,
S1) on t h e c a p s t a n o f t h e s t e p p i n g motor Ass'y
and remove t h e s t e e l b e l t and t h e p l a t e washer (Fig.405, No.26).
(12) F i x a new s t e e l belt ( a c c e s s o r y o f t h e c a r r i a g e ) t e m p o r a r i l y t o t h e
c a p s t a n with t h e p l a t e washer and t h e screw i n i t e m (11) a s t h e y w e r e .
Notes: 1. Fundamentally, t h e s t e e l b e l t and t h e b e l t s p r i n g should be
r e p l a c e d with t h e head c a r r i a g e .
However, i f t h e r e i s no
i n f e r i o r p o i n t s f o r t h e s e belt and s p r i n g , t h e y may be used
a f t e r c l e a n i n g t h e s u r f a c e c a r e f u l l y w i t h a l c o h o l and gauze.
2. Pay a t t e n t i o n n o t t o darnage t h e s u r f a c e o f t h e s t e e l belt or
t h e capstan.
(13) I n s t a l l a new head c a r r i a g e Assly with two guide s h a f t s i n t h e r e v e r s e
o r d e r o f i t e m s (5) through ( 1 0 ) .
When f i x i n g t h e steel belt t o t h e c a r r i a g e , i n s t a l l t h e b e l t s p r i n g
a t t h e bottom s i d e f i r s t , and hook t h e s t e e l b e l t t o t h e b e l t hook 1.
Refer t o Fig. 3501.
Then p l a c e t h e FDD w i t h t h e t o p s i d e up.
P u l l t h e steel belt i n t h e
d i r e c t i o n of arrow mark i n Fig.3502 u s i n g a pair o f tweezers and hook
it t o t h e belt hook 2.
Note: When r e p l a c i n g t h e head c a r r i a g e Ass'y,
r e p l a c e t h e t w o guide
s h a f t s a t the same time because o f matching t h e r e s p e c t i v e hole
diameter o f t h e c a r r i a g e w i t h those of t h e guide s h a f t s .
-3503
-
Each
guide s h a f t i s t o be designated i n combination with corresponding
hole of t h e head c a r r i a g e Ass'y.
Guide s h a f t which goes through t h e hole of t h e c a r r i a g e smoothly
with a l i t t l e clearance is considered t o be the b e s t .
(14) After f i n i s h i n g the i n s t a l l a t i o n of t h e c a r r i a g e , loosen the screw
which f i x e s t h e s t e e l b e l t t o t h e capstan temporarily.
(15) Confirm t h a t t h e s t e e l belt runs on t h e center of t h e belt spring
r e f e r r i n g t o Fig.3501.
(16) After moving t h e head c a r r i a g e several times manually, t i g h t e n t h e
f i x i n g screw of the s t e e l belt i n i t e m (14) c a r e f u l l y with the
s p e c i f i e d torque of 4.5Kg.m.
i s tensioned s t r a i g h t l y .
A t this
t i m e , be c a r e f u l that t h e b e l t
Pay a t t e n t i o n not t o damage t h e surface of
t h e b e l t or t h e capstan.
Note: Do not pinch t h e upper arm of t h e head c a r r i a g e when move it
manually.
Pinch t h e r e a r s i d e of t h e c a r r i a g e .
(17) Mve t h e head c a r r i a g e t o t h e middle of movable area and apply a drop
of o i l (FLOIL 946P) on t h r e e p o i n t s of guide s h a f t s ' surface near t h e
s h a f t holes of t h e c a r r i a g e .
This item shall be omitted, i f t h e o i l
has been already applied.
Notes: 1..A s m a l l drop of o i l shall be applied t o each point.
For example, d i p t h e t i p of a narrow o b j e c t such a s wire or a
pair of tweezers with o i l .
2.
I f t h e head c a r r i a g e o r t h e head piece i s smeared with o i l , wipe
it out completely by such a cotton swab dipped with alcohol.
(18) Make t h e head c a r r i a g e move manually several times t o spread the o i l
on a l l over t h e moving area.
-
3504
-
(19) Apply a drop o f l o c k i n g p a i n t t o f o u r p o i n t s between t h e steel b e l t
and t h e c a r r i a g e r e f e r r i n g t o l o c k i n g p a i n t 1 through 4 i n Figs. 3501
and 3502.
(20) I n s t a l l t h e s e t arm and t h e head c a b l e according t o t h e r e v e r s e o r d e r
of i t e m s (1) and ( 2 ) .
Refer t o i t e m 3-2-3
a s t o t h e head c a b l e
treatment.
(21) Adjust t h e s e t arm p o s i t i o n according t o i t e m 3-4-1.
(22) Model w i t h head l o a d s o l e n o i d :
Check and a d j u s t t h e arm l i f t e r a c c o r d i n g t o i t e m 3-4-3.
CSS model:
Check t h e CSS Ass'y according t o i t e m 3-4-4.
(23) Make t h e head move c o n t i n u o u s l y between t h e t r a c k 00 and t h e innermost
t r a c k and confirm t h a t t h e s t e e l b e l t does n o t meander nor undulate.
When an SKA i s used, key i n I'C6" f o r t h i s check and key i n "F" f o r
stop.
Note: I f t h e s t e e l belt i s r e p l a c e d with a new one, c o n t i n u e t h e head
seek o p e r a t i o n i n item (23) f o r 3 minutes, approx.
(24) Check t h e head touch according t o i t e m 3-4-8.
(251 Check t h e asymmetry according t o i t e m 3-4-9.
(261 Adjust t h e t r a c k alignment according t o i t e m 3-4-12.
(271 Adjust t h e t r a c k 00 s e n s o r p o s i t i o n according t o i t e m 3-4-13.
(28) Check t h e t r a c k 00 s t o p p e r according t o item 3-4-14.
-
3505
-
(29) Check or adjust the index burst timing according to item 3-4-15.
(30) Check the read level accoding to item 3-4-10.
(31) Check the resolution according to item 3-4-11.
(32) It is recommended to connect the FDD to the system for overall test.
Refer to item 3-2-5
(1) for the window margin test.
Head carriage
Steppi
fts
(Fig.3503) Replacement of head carriage Ass'y
-
3506
-
3-5-2.
(A)
Replacement of Stepping Motor A s s ' y
Tools
(1) Cross p o i n t screwdriver, M3
(2) A pair o f tweezers
(3) Alcohol and gauze
( 4 ) Locking p a i n t
(5) SKA or u s e r ' s system
(6) Required equipment for r a c h r e f e r r i n g i t e m
(B) Replacement procedure
(1) Disconnect t h e s t e p p i n g motor connector (56).
( 2 ) Remove t h e s t e p p i n g motor c a b l e from t h e c a b l e hooks of t h e frame
t o make t h e c a b l e be f r e e .
(3) Remove t h e s t e e l belt (Table 402C, N o . 2 3 ~ ) and t h e b e l t s p r i n g (Table
402C, No.22d) according t o item 3-5-1
( 4 ) Remove t w o f i x i n g
( 3 ) through ( 8 ) .
screws (Fig.405, S9) of t h e s t e p p i n g motor A s s ' y
(Fig.405, No.27) and remove t h e s t e p p i n g motor with t h e s t e e l belt.
(5) Remove a screw (Fig.405, S1) on t h e c a p s t a n of t h e stepping motor and
remove t h e s t e e l belt and t h e p l a t e washer (Fig.405, No.26).
(6) Confirm t h a t t h e r e i s no i n f e r i o r nor d e f e c t i v e p o i n t f o r t h e s t e e l
belt and belt spring.
Then c a r e f u l l y c l e a n t h e s u r f a c e of t h e s t e e l
belt, belt s p r i n g and capstan with a l c o h o l and gauze.
If an i n f e r i o r o r d e f e c t i v e p o i n t i s found, r e p l a c e t h e s t e e l belt or
t h e belt s p r i n g with a new one.
(7) Fix the s t e e l belt temporarily t o t h e c a p s t a n of a new s t e p p i n g motor
-
3507
-
w i t h t h e p l a t e washer and t h e screw as t h e y w e r e .
Note: Never remove t h e p l a t e o f t h e s t e p p i n g motor A s s ' y s i n c e t h e y
are combined e a c h o t h e r .
( 8 ) I n s t a l l t h e s t e p p i n g motor i n i t e m (7) a c c o r d i n g t o t h e r e v e r s e o r d e r
o f items (1) t h r o u g h ( 4 ) .
When f i x i n g t h e s t e e l b e l t t o t h e c a r r i a g e , i n s t a l l t h e b e l t s p r i n g
a t t h e bottom s i d e f i r s t and hook t h e s t e e l b e l t t o t h e b e l t hook 1
( r e f e r t o F i g . 3501)
.
Then p l a c e t h e FDD w i t h t h e t o p s i d e up.
Pull the belt i n the
d i r e c t i o n of arrow mark i n Fig.3502 u s i n g a p a i r of t w e e z e r s and
hook it t o t h e b e l t hook 2 .
(9) Loosen t h e screw which f i x e s t h e s t e e l b e l t t o t h e c a p s t a n .
(10) Confirm t h a t t h e s t e e l b e l t r u n s on t h e c e n t e r of t h e b e l t s p r i n g when
viewed from t h e bottom s i d e .
Refer t o Fig.3501.
(11) A f t e r moving t h e head c a r r i a g e s e v e r a l times manually, t i g h t e n t h e
f i x i n g screw o f t h e steel b e l t i n i t e m ( 9 ) c a r e f u l l y w i t h t h e s p e c i f i e d
t o r q u e of 4.5Kg.cm.
tensioned s t r a i g h t l y .
A t t h i s t i m e , be c a r e f u l so t h a t t h e belt i s
Pay a t t e n t i o n n o t t o damage t h e s u r f a c e of t h e
belt o r t h e capstan.
Note: Do n o t p i n c h t h e upper arm o f t h e head c a r r i a g e when move it
manually.
Pinch t h e rear s i d e o f t h e c a r r i a g e .
(12) Make t h e head move c o n t i n u o u s l y between t h e t r a c k 00 and t h e innermost
t r a c k and confirm t h a t t h e s t e e l b e l t does n o t meander nor u n d u l a t e .
When a n SKA i s u s e d , key i n "C6" f o r t h i s check and key i n "F" for
stop.
I f t h e r e i s s o m e abnormal r u n n i n g o f t h e steel b e l t , r e a d j u s t
t h e b e l t w i t h screws i n i t e m (9). A f t e r t h e a d j u s t m e n t t i g h t e n t h e
-
3508
-
screws c a r e f u l l y with t h e s p e c i f i e d t o r q u e of 4 .SKg.cm.
Note: I f t h e s t e e l b e l t i s r e p l a c e d , execute t h e continuous seek
o p e r a t i o n i n i t e m (12) f o r 3 m i n u i t e s , approx.
(13) Adjust t h e t r a c k alignment according t o i t e m 3-4-12.
(14) Adjust t h e t r a c k 00 s e n s o r p o s i t i o n a c c o r d i n g t o i t e m 3-4-13-
- 3509 -
3-5-3. Replacement o f DD motor Ass'y ( S p i n d l e Motor)
(1) C r o s s p o i n t s c r e w d r i v e r , M3
(2) Comnon s c r e w d r i v e r , small s i z e
( 3 ) A p a i r o f tweezers
( 4 ) Locking p a i n t
( 5 ) SKA o r u s e r ' s system
(6) Required equipment f o r each r e f e r r i n g i t e m
(B) Replacement procedure
(1) Disconnect t h e s p i n d l e motor connector (57).
(2) Remove t h r e e f i x i n g screws (Fig.405, S5) o f t h e DD motor Ass'y from t h e
upper s i d e of t h e FDD and draw out t h e DD motor Ass'y from t h e r o t o r
s i d e (PCBA s i d e )
.
(3) I n s t a l l a new DD motor Ass'y i n t h e r e v e r s e o r d e r o f i t e m s (1) and (2).
Refer to i t e m 3-2-2-5 a s t o t h e handling o f 57 connector.
Note: The s p i n d l e a r e a o f t h e DD motor (clamping cup o f t h e d i s k ) i s
p r e c i s e l y machined.
For i n s t a l l i n g t h e motor t o t h e frame,
p l a c e t h e s p i n d l e i n p a r a l l e l t o t h e frame and push i n t o t h e frame
slowly.
Handle t h e s p i n d l e very c a r e f u l l y n o t t o damage t h e s p i n d l e
surface.
( 4 ) Adjust the s e t arm p o s i t i o n according t o i t e m 3-4-1.
(5) Check t h e f i l e p r o t e c t s e n s o r according t o i t e m 3-4-5.
(6) Check t h e d i s k r o t a t i o n a l speed according t o i t e m 3-4-6.
-
3510
-
(7) Adjust t h e t r a c k alignment according t o i t e m 3-4-12.
(8) Check o r a d j u s t t h e t r a c k 00 s e n s o r p o s i t i o n according t o i t e m 3-4-13.
(9) Check o r a d j u s t t h e index b u r s t timing a c c o r d i n g t o i t e m 3-4-15.
-
3511
-
3-5-4.
Replacement o f C o l l e t Ass'y
(A) Equipment
(1) Cross p o i n t s c r e w d r i v e r , H3
( 2 ) A pair of tweezers
( 3 ) Round nose p l i e r s
( 4 ) Locking p a i n t
( 5 ) SKA or u s e r ' s system
(6) Required equipment f o r each r e f e r r i n g i t e m
(B) Replacement procedure
(1) Remove t h e set arm sub Ass'y (Fig.405, No.3) by removing two f i x i n g
screws (Fig.405, S a ) .
( 2 ) Remove an E-ring
(Fig.405, 512) which f i x e s t h e c o l l e t Ass'y (Fig.405,
No.9) t o t h e set arm and remove t h e c o l l e t and t h e p r e s s u r e s p r i n g
(Fig.405, No.10).
(3) I n s t a l l a new c o l l e t Ass'y i n t h e r e v e r s e o r d e r .
o r i e n t a t i o n of t h e spring.
Pay a t t e n t i o n t o t h e
The smaller diameter s i d e s h a l l f a c e t h e
c o l l e t s i d e and t h e l a r g e r diameter s i d e s h a l l f a c e t h e s e t arm s i d e .
( 4 ) Adjust t h e s e t ann p o s i t i o n according t o i t e m 3-4-1.
( 5 ) Check (or a d j u s t ) t h e t r a c k alignment according t o i t e m 3-4-12.
-
3512
-
3-5-5.
Replacement of Head m a d Solenoid
T h i s i t e m i s a p p l i e d o n l y f o r a model w i t h head load s o l e n o i d Ass'y.
(A) Tools
(1) Cross p o i n t s c r e w d r i v e r , M3
( 2 ) Hexagon wrench key, 1 . 5 m
(3) A pair of tweezers
( 4 ) Locking p a i n t
( 5 ) SKA or u s e r ' s system
(6) Required equipment t o each r e f e r r i n g i t e m
(B) Replacement procedure
(1) Disconnect t h e head l o a d s o l e n o i d connector (J8).
( 2 1 Remove two f i x i n g screws (Fig.405,
Ass'y (Fig.405,
S2) t o r e m v e t h e head l o a d s o l e n o i d
No.20).
( 3 ) I n s t a l l a new head l o a d s o l e n o i d Ass'y i n t h e r e v e r s e o r d e r .
( 4 ) P o s i t i o n t h e head l o a d s o l e n o i d Ass'y so t h a t t h e arm l i f t e r i s i n
p a r a l l e l with t h e set arm.
Refer t o Fig.3504.
(5) Check and a d j u s t t h e arm l i f t e r according t o i t e m 3-4-4.
-
3513
-
m-
’
d load solenoid
LeaAss ‘Y
set armJ
(Fig.3504) I n s t a l l a t i o n of t h e head l o a d s o l e n o i d A s s ’ y
- 3514 -
3-5-6.
Replacement of CSS Ass'y
This item i s applied only f o r a CSS model (without head load s l e n o i d ) .
(A) T o o l s
(1) Cross p o i n t screwdriver, M3
( 2 ) Required equipment f o r each r e f e r r i n g item
(B) Replacement procedure
(1) Remove a f i x i n g screw (Fig.405, S2) t o remove t h e CSS A s s ' y (Fig.405,
No.21) from t h e frame.
( 2 ) I n s t a l l a new CSS Ass'y i n t h e reverse o r d e r .
Be c a r e f u l t o i n s t a l l
the arm l i f t e r a r e a t o be i n p a r a l l e l t o t h e s e t a m .
(3) Check t h e CSS Ass'y according t o item 3-4-4.
p l a t e
css
Ass'y
Arm l i f t e r
( P a r a l l e l t o s e t arm)
Set a m
(Fig.3505) CSS Ass'y and shift l e v e r p o s i t i o n
-
3515
-
3-5-7.
Replacement of PCBA MFD Control
( A ) Tools
(1) Cross p o i n t screwdriver, M3
(2) Common screwdriver, small size
( 3 ) SKA or u s e r ' s system
(41 Required equipment f o r each r e f e r r i n g item
(B) Replacement procedure
(1) DiscoMect a l l of t h e connectors connected t o t h e PCBA MFD c o n t r o l
(Fig.405, No.29) r e f e r r i n g t o item 3-2-2.
( 2 ) Remove t h e PCBA W D c o n t r o l by removing t h r e e f i x i n g s c r e w s (Fig.405,
S3).
( 3 ) I n s t a l l a new PCBA i n t h e r e v e r s e o r d e r .
(4) S e t t h e s t r a p s and terminator a s they were on t h e o l d PCBA.
(5). Check t h e f i l e p r o t e c t sensor according t o i t e m 3-4-5.
(6) Check t h e e r a s e g a t e delay according to i t e m 3-4-7.
( 7 ) Check (or a d j u s t ) t h e asymmetry according t o i t e m 3-4-9.
(81 Check t h e read l e v e l according t o i t e m 3-4-10.
( 9 ) Check t h e r e s o l u t i o n according
to i t e m 34-11.
(10) Adjust t h e t r a c k 00 sensor p o s i t i o n according t o i t e m 3-4-li.
(11) Check t h e index burst timing according t o i t e m 3-4-15.
- 3516 -
(12) I t is recommended to connect t h e FDD to t h e system for o v e r a l l t e s t .
Refer to i t e m s 3-2-5
(1) f o r t h e window margin t e s t .
-
3517
-
3-5-8.
(A)
Replacement o f PCBA Front OPT
Tools
(1) Cross p o i n t s c r e w d r i v e r , M3
( 2 ) SKA or u s e r ' s system
( 3 ) Required equipment for each r e f e r r i s q i t e m
( B ) Replacement procedure
(1) Disconnect PCBA f r o n t OPT connector (.J5).
( 2 ) Remove two f i x i n g screws (Fig.405,
S 7 ) t o remove t h e PCBA f r o n t OPT
(Fig.405, No.30).
( 3 ) I n s t a l l a new PCBA i n t h e r e v e r s e o r d e r .
( 4 ) Check t h e f i l e p r o t e c t s e n s o r according t o i t e m 3-4-5.
( 5 ) Adjust t h e index b u r s t timing according t o i t e m 3-4-15.
(6) Check t h e f r o n t b e z e l i n d i c a t o r .
- 3518 -
3-5-9.
Replacement o f F r o n t Bezel A s s ' y
(A) Tools
(1) C r o s s p o i n t s c r e w d r i v e r , M3
( 2 ) Required equipment f o r ea& r e f e r r i n g i t e m
(B) Replacement p r o c e d u r e
(1) D r a w o u t t h e f r o n t l e v e r
Ass'y
( f i g , 4 u S , No.32).
( 2 ) Remove two f i x i n g screws (Fig.405,
S8) o f t h e f r o n t b e z e l Ass'y ( F i g .
405, No.31) and draw t h e f r o n t b e z e l o u t .
( 3 ) I n s t a l l a new f r o n t b e z e l A s s ' y i n t h e r e v e r s e o r d e r .
For t h e
i n s t a l l a t i o n o f t h e f r o n t b e z e l , p r e s s t h e l o n g i t u d i n a l ends o f t h e
b e z e l a g a i n s t t h e frame and t i g h t e n t h e f i x i n g screws w i t h t h e
s p e c i f i e d torque.
( 4 ) I n s e r t t h e f r o n t l e v e r Ass'y f u l l y a g a i n s t t h e l e v e r s h a f t as it w a s .
-
3519
-
3-5-10.
Replacement of F r o n t Lever A s s ' y
( A ) Tools
(1) Required equipment f o r each r e f e r r i n g i t e m
(B) Replacement procedure
(1) Draw o u t t h e f r o n t l e v e r A s s ' y (Fig.405, No.32).
( 2 ) I n s e r t a new f r o n t l e v e r A s s ' y f u l l y a g a i n s t t h e l e v e r s h a f t a s i t was.
( 3 ) Check ( o r a d j u s t ) t h e h o l d e r p o s i t i o n according t o item 3-4-2.
-
3520
-
~
V
FPT
INDEX SENSOR
3
ov
-
2
0-!76>
E
~
~
~
*
~M ANI N S S P E C
15532091-00
STO
LED51 (RED I
15532091-01
STD
LEDSl(GREEN1
1553209 1-07
STD
LEDSl(GREEN1
15532091-10
STO
LED51(AMflERl
PARTS
6; i1
I
VERSION TABLE
NOTES: ABBREVIATED NAMES ARE AS FOLLOWS.
RED. GREEN. M E R
:
FRONT LED COLOR
P/N
0010230-01
15532091-XX(PCB
ISSUE
88L5
a
6 E i
d
d
b
.
b
s
mx
tll
a
%
7 - - - - - - - - - - - - ,
L
J l
AD CARRIAGE A S S ' Y
2
SIDE 0
HEAO
4
6
SIGNAL
E
10
12
14
16
18
20
22
24
26
28
30
INTERFACE
PCBA
SIDE 1
HEAO
MFO CONTROL
1 5 53 2 0 9 7 - X X
!
r------------
-
32
34
S I G N A L GNO
(000 NOS. )
[
1
I
2
33
!
L
7
I
I
I
POWER
INTERFACE
@
I
I
t12v
ov
ov
t
5v
I
I
I
I
I
'i
~
m
q
*DOOR CLOSE
ASS'Y-Q4
I
PHASE A
STEPPING
PHASE M A
PHASE NE
MOTOR
ASS'Y
I
I
!
COY A
I
I
I
I
I
I
I
I
F R A M E GROUND
J
2.SlGNALS
(FASTON TAB)
W I T H OOUELE
ASTERISKS(**)
ARE
USEO ONLY FOR O P T I O N A L VERSIONS.
REFER T O V E R S I O N TABLE.
I
NOTES
1 . P A R T S V I T H AN A S T E R I S K ( * )
REFER T O V E R S I O N TABLE.
ARE U S E O
I N SOME F O D V E R S I O N S .
U N L I S T E D P A R T S ARE
NOT USED
I N THAT VERSION.
P/N 1 9 3 0 7 2 7 X - X X
. .
. .
0010230-01
I
I
a it
*m
I
TEAC 7
a
T S - E
(
P)
ma
I
I
I
I
4
PI:,
gW32tf
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I
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I
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I
I
I
I
3 n*
n .7_-
.
\
P r 0 A VER(F;;
I
I
coN'PoL
ER-500
ER-528:
ETC
I C S S . F U L L STRAP
0R-501
0R-505:
ETC
IHL .FULL
STRAP
L
ASS'Y
-
I
-03
L
ASS'Y
A VERSll
TYPICAL
OD V E R S I O N
15532091-XX
M A I N SPEC
1 PARTS
:O CONTROL
FRO1
)pT
**
5532012-XX
-
SIGNALS
IO COLOE
to
:-oc
I E E N : -01
I E E R : -1C
-04
-05
I
:!,51"*
I
HL . F U L L
STRAP
IL A S S ' Y
i
-06
-07
I
I
I
E,",513*
E1-523
~ ~ - 5 7 6 .
ETC
FR-558.
FR-559
I H L .HALF
STRAP
)CSS.FULL
CUSTOM
STRAP.
I
IL
ASS'Y
-08
-11
-10
-12
-00
IL ASS'Y
-15
-01
I L ASS'Y
I L SOL.
ASS'Y
-16
-03
-17
-04
CSS. F U L L S T R A P .
D R I V E STATUS
IC
CSS. F U L L STRAP.
CUSTOM
IC
ASS'Y
-03
ASS'Y
-02
-18
z
7
7
fz
1 5 - 6 : DC S E N S O R
-04
J5-6:0
SEN
NOTE
:
A B B R E V I A T E D N A M E S ARE A S F O L L O Y S
HL
CSS
OC
DL
OL
SOL
0 SEN
:
:
:
:
:
:
HEAD L O A 0 S O L E N O I D
V I T H O U T HL S O L E N O I O
DOOR C L O S E
DOOR LOCK
DOOR LOCK S O L E N O I O
: D I S K SENSOR
P I N 1930727X-XX
VERSIONS TABLE
TYPICAL
)O V E R S I O N
M A I N SPEC
PARTS
f
1
CONlROL
-
**
SIGNALS
TYPICAL
10 V E R S I O N
rn
M A I N SPEC
PARTS
0 CONTROL
F RON
532091-XX
PT
532092-XX
** SIGNALS
P/N
VERSIONS TABLE
1930727X-XX
sa
m
m
m
a
s
b
M
( m a l a
f
Y
J1
/tn F I N I S H
a
2
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1 221
4
6
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3
7
9
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W l l f SATE
WITE DATA
STEP
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teseeveo
mivc SELECT
mivc
PLLCT
E
U l
11
14
I
A I
12
10
8
o
IIWX
1SEWEO
Ill USL/HtAO LOA0
FPT
2
3
4
5
UCSEMO
SImL
am
c
m Imr
6
5
1
2
Slf P? IME
UOTM ASS'V
tlZV
3
W
W
4
t5v
FASlCU
I
..
qn.7
.,
PCEA
MAIN
VERslMs
SPEC.
*
PARTS
PCBA
MA1 N
MRSIMS
SPEC.
*
PARTS
___
~~
-02
4ElPI
03. CR2. R6(2. BOK). RE(2. 2 1 ) . RS(120).
8-css
ClZ(2200P).
TlK
C 2 5 ( 1 0 0 P ) . C2E(6.8.50V).
1 1 0 . 1112. R l S ( 1 6 5 ) .
C 1 4 ( 2 2 0 0 P ) . C 1 5 ( 2 2 0 0 P ) . C16(ZZOOP).
C 2 9 ( 6 . 8. 50V).
JUMPER VIRE : CR3-CR5.
S T R A P POSTS : 00.
01.
Ll.
ML.
L2.
Ul.
IU.
C30.
120.
ClE(l5OOP).
R21(100).
C23(1EOP).
-07
R22(100).
C24(100P).
LO-L5(330)
S61DI
03. CR2. I!.
RE(3.74K).
F-CSS
R21(100).
TlK
C23(180P).
FG
48tDI
01.
02.
03. CR1. CR2. R4. R((2.801).
8-HL
R21(100).
T1K
C23(18OP).
122(100).
R20.
CP411OOP).
STRAP POSTS : 00. 01.
C12(2200P).
Ll.
IU.
L2.
Ul.
R 9 ( 1 2 0 ) - RlO. R12.
C14(2200P).
C15(2200P).
R19(165).
ClE(22OOPI.
C 2 9 ( 6 8. 50V).
C30.
-08
ClB(1500P).
L3-15(330).
JE(ZPl
FG
16(2.80K).
8-css
C 1 4 ( 2 2 0 0 P ) . C l 5 ( Z200P).
TlK
C28(K. 8. SOV).
JUYPER WIRE : CR3-CR5.
C l 6 ( 2 2 0 0 P ) . C l E ( 15OOP 1.
Ll.
Ll.
01.
Ut.
CR2.
Rl.
L2.
Ul.
IU.
RlO.
RlZ.
C15(2700P).
C30.
R19(150).
C16(220OPI.
1120.
C18(15OOP).
L3*L5(330)
FG
RY
01.
F-HL
RlS(150).
TlK
C16(2200P).
C 1 8 ( 1 5 0 0 P ) . CZ3(1EOP).
L3-L5(3301.
JE(2P)
HS. RY
C2916. E. 50V).
C 2 5 ( 1 0 0 P ) . C26-CZSI6. 8.2SV).
96tPI
UR(Z. 2K). RB(120). RlO. RlZ. R l S ( l E 5 ) . R Z l ( 1 0 0 ) . R 2 2 ( 1 0 0 ) . C 1 2 ( 2 2 0 0 P ) .
4EtDl
RO(2401.
C14(2700P).
RZO.
02. 03. CRl.
JUMPER
-04
C12(2200P).
CUT : s7
RE(2.ZK).
C28(6. E. 5OV).
C25(1OOP).
JUMPER WIRE : CR3-CP5.
C24(100P).
STRAP POSTS : 00.
RV
R7(13K). RE(4.71).
R24.
JUYPER W I R E : CR3-CR5.
~~
-03
R22(100).
C23( 1EOP).
C24( l o o p ) .
R2O. R 2 1 ( 1 0 0 ) .
WIRE
: CR3-CR5.
S T R A P POSTS : 00.
C25( 1OOP).
01.
R4. R6(3. 7 4 K ) .
R22(100).
Ll.
IU.
12. U l .
HS.
R22.
R7(13K).
R b ( 4 . 7K).
RZB. C l t ( 2 2 O O P ) .
C24(1CfiP).
CZ5(100P).
RS(240).
C14(2700P).
110, R12.
ClS(2700P).
C26-C29(E. E. 25V).
C30.
FG
RY
CUT : 57
L3-L51330)
L2.
Ul.
IU.
RV.
S4.
FG
-12
STRAP POSTS : 00. 0 1
48lDI
R1
e-css
THE OTHERS ARE THE SAME AS-02
TlK
VERSION TABLE
7.AEBREVIATEO NAUES ARE AS FOLLOWS:
PAT: PATTERN SHORT
JV : JWPER VIRE
5. TOLERANCE SVYBOLS FOR R. RA. C. A M 0 L ARE:
F: ilS.
0: i 2 l .
J: :IS.
I:ilO%
Y:
tZO1.
V: ti?O*-lOS.
Z:
tlO--2OS
P/N
4.INOUCTOR ( L 1 VALUES ARE I N Y l C R O - H E Y R I E S . i 5 S ~ J ) . U N L E S S
r-x
r --
. .
. .
L-..
I
. .
t
. .
I
3.CAPACITOR ( C 1 VALUES ARE I N MICRO-FARAOS.50V
OR HIGHER.f5l(J).UNLESS
2.RESISTOR ( R ) AN0 RESISTOR ARRAY ( R A ) VALUES ARE I N OWS.l/8W
UNLESS OTHERVISE SPECIFIEO.
15532097-XX
OTHERVISE SPECIFIED.
OTHERWISE SPECIFIED.
OR GREATER.tSS(J).
-.
?I
n
It .t
TEAC 7.4719 9t!kS&?i
Msc
FD-55BR/FR/GR
4-5.
RECOMMENDABLE SPARE PARTS LIST
I t is recommended t o replace t h e wear p a r t s p e r i o d i c a l l y i f t h e FDD
is operated a t a s p e c i a l l y heavy duty condition o r i f it i s operated
over f i v e years.
Periodic replacement i s not required f o r t h e p a r t s
i f t h e FDD i s operated a t a normal operation duty.
Table 406 shows a l l of t h e maintenance p a r t s .
Replace t h e wear parts
according t o the recomnended replacement cycle.
Periodic replacement
i s not required f o r p a r t s without a recommended replacement cycle.
The replacement of t h e p a r t s should be done according t o each r e f e r r e d
item i n Table 406.
Notes f o r Table:
1. Head c a r r i a g e Ass'y a r e used always i n p a i r with two guide s h a f t s .
The head c a r r i a g e A s s ' y represented by l i s t e d p a r t s number i n Table
406 includes these guide s h a f t s which p a r t s number i s d i f f e r e n t from
t h a t of a head c a r r i a g e Ass'y i t s e l f without these guide s h a f t s .
Refer t o Note 2 and Table 402-C i n item 4-2-1
a s t o the d e t a i l s .
2. I t i s recommended t h a t t h e s t e e l b e l t and b e l t spring a r e replaced
together with t h e head c a r r i a g e Ass'y.
P a r t s number of the head
c a r r i a g e Ass'y i n Table 406 includes these two p a r t s .
Refer t o
Note 2 and Table 402-C i n item 4-2-1 a s t o t h e d e t a i l s .
I f t h e s t e e l b e l t and b e l t spring a r e replaced i n d i v i d u a l l y o r
replaced with t h e stepping motor Ass'y, use t h e individual parts
number i n Table 406.
3. Periodic replacement i s not required f o r p a r t s without a recommended
replacement cycle.
Replace t h e p a r t s when required such a s during
repair.
4.
I f two recommended cycles a r e l i s t e d , t h e cycle which t h e p a r t s reach
-
423
-
first should have priority.
5. The required time for replacement includes the time f o r basic check
and adjustment after the replacement.
6. Use the designated parts number for ordering the spare parts.
-
424
-
(Table 406) FD-55BR recommendable spare parts l i s t
Spare parts
Parts name
Head carrirce
Ass’y
Steppinc motor
As’y
BR
Description
Parts No.
Note 1
17967603- 00
Software
Software
Software Contents
BIOS Services . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device 1/0Services . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Communications . . . . . . . . . . . . . . . . . . . . . .
Line Printer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sound Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . .
Diskette I/O Support for Diskette Only . . . . . . . . . . . . .
Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Size . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . .
SystemServices
Machine Identification . . . . . . . . . . . . . . . . . . . . . . .
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIOS Sound Support . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard ASCII and Scan Codes . . . . . . . . . . . . . . . . .
MS-DOS Memory Map . . . . . . . . . . . . . . . . . . . . . . .
ROM BIOS Data Area . . . . . . . . . . . . . . . . . . . . . .
Additional Data Area . . . . . . . . . . . . . . . . . . . . . . .
.............................
1
1
3
7
20
24
26
30
31
38
39
39
40
40
41
43
47
51
52
58
BIOS Services
Device I/O Services
Introduction
The BIOS (Basic Input/Output System) is the lowest-level interface
between other software (application programs and the operating system itself) and the hardware. The BIOS routines provide various
device input/output services as well as bootstrap and print screen and
other services. Some of the services that BIOS provides are not available through the operating system, such as the graphics routines.
All calls to the BIOS are made through software interrupts (that is, by
means of assembly language “INT x” instructions). Each I/O device is
provided with a software interrupt, which transfers execution to the
routine.
Entry parameters to BIOS routines are normally passed in CPU
registers. Similarly, exit parameters are generally returned from these
routines to the caller in CPU registers. To insure BIOS compatibility
with other machines, the register usage and conventions are, for the
most part, identical.
The following pages describe the entry and exit requirements for each
BIOS routine. To execute a BIOS call, load the registers as indicated
under the “Entry Conditions” banner. (Register AH will contain the
function number in cases where a single interrupt can perform more
than one operation.) Then issue the interrupt given for the call. The
following example can be used to read a character from the keyboard:
MOV AH,O
INT 16H
1.
Software
Upon return, AL contains the ASCII character and AH the keyboard
scan code.
Note: All registers except those used to return parameters to the
caller are saved and restored by the BIOS routines.
Following is a quick reference list of software interrupts for all device
I/O and system status services.
Service
Video Display
Equipment
Memory Size
Diskette
Serial Communications
System Services
Keyboard
Line Printer
Bootstrap Loader
System Clock
2.
Software Interrupts
10 hex (16 dec)
11hex (17 dec)
12 hex (18 dec)
13 hex (19 dec)
14 hex (20 dec)
15 hex (2ldec)
16 hex (22 dec)
17 hex (23 dec)
19 hex (25 dec)
lAhex (26 dec)
BIOS Services
Keyboard
16 hex (22 dec)
Function Summary
AH
0:
= 1:
= 2:
= 5:
AH
AH
AH
10H:
= 11H:
= 12H:
AH
AH
AH
=
=
Read keyboard (destructive with wait)
Scan keyboard (nondestructive, no wait)
Get current shift status
Store ASCII character and scan code in
keyboard buffer
Extended keyboard read
Extended ASCII status
Extended shift status read
Function Descriptions
Read Keyboard
Read the next character typed at the keyboard. Return the ASCII value
of the character and the keyboard scan code, removing the entry from
the keyboard buffer (destructive read).
Entry Conditions
AH
=
0
Exit Conditions
AL
=
ASCII value of character
AH
=
keyboard scan code
3.
Software
Scan Keyboard
Set up the zero flag (Z flag) to indicate whether a character is available to read from the keyboard or not. If a character is available, return
the ASCII value of the character and the keyboard scan code. The entry
remains in the keyboard buffer (non-destructiveread).
Entry Conditions
AH
= 1
Exit Conditions
z
= no character available
= a character is available, in which case:
NZ
AL
=
AH
=
ASCII value of character
keyboard scan code
Get Shift Status
Return the current shift status.
Entry Conditions
AH
=
2
Exit Conditions
= current shift status (bit settings: set = true, reset = false)
AL
Bit 0 = RIGHT SHIFT key depressed
Bit 1 = LEFT SHIFT key depressed
Bit 2 = CTRL (control) key depressed
Bit 3 = ALT (alternate mode) key depressed
Bit 4 = SCROLL state active
Bit 5 = NUMBER lock engaged
Bit 6 = CAPS lock engaged
Bit 7 = INSERT state active
4.
BIOS Services
Store ASCII Character
Entry Conditions
AH
CL
=
5
=
ASCIIcharacter
CH
= ScanCode
Exit Conditions
AL
= 00: Successful
= 01: Buffer full
AL
[C]
=
Operation failed
Extended Keyboard Read
Entry Conditions
AH
= 10H
Exit Conditions
AL
= ASCII value of Character
AH
=
keyboard scan code
Extended ASCII Status
Entry Conditions
AH
= 11H
Exit Conditions
z
NZ
AL
AH
No character is available
= A character is available, in which case:
= ASCII value of character
= keyboard scan code
=
5.
Software
Extended Shift Status Read
Entry Conditions
AH
=
12H
Exit Conditions
= shift status (bit settings: set
AL
Bit 7
=
Bit 6
=
INSERT active
CAPS LOCK active
Bit 5
Bit 4
=
NUM LOCK active
=
SCROLL LOCK active
Bit 3
Bit 2
Bit 1
Bit 0
=
AH
Bit 7
6.
=
true, reset
ALT pressed
= CTRL pressed
= LEFT SHIFT pressed
= RIGHT SHIFT pressed
extended shift status (bit settings: set
reset = false)
=
=
Bit 6
Bit 5
SYS REQ pressed
= CAPS LOCK active
= NUM LOCK active
Bit 4
=
SCROLL LOCK active
Bit 3
=
RIGHT ALT active
Bit 2
=
RIGHT CTRL active
Bit 1
=
Bit 0
=
LEFT ALT active
LEFT CTRL active
=
=
true,
false)
BIOS Services
Video Display
These routines provide an interface for the video display - the output
half of the console (CON) device. MS-DOS considers the video display to be the default standard output (STDOUT) device.
Software Interrupts
10 hex (16 dec)
Function Summary Table
Supported Video BIOS Calls
INT 10H
AH = 00
AH=01
AH = 02
AH = 03
AH = 05
AH=06
AH = 07
AH = 08
AH = 09
AH = OA
AH =OB
AH=OC
AH =OD
AH = OE
AH =OF
Set Video Mode
Set Cursor Type
Set Cursor Position
Read Cursor Position
Select Active Display Page
Scroll Active Page Up
Scroll Active Page Down
Read AttributeKharacter at
Current Cursor Position
Write AttributeKharacter at
Current Cursor Position
Write Character Only at
Current Cursor Position
Set Color Palette
Write Dot
Read Dot
Write l T Y to Active Display
Current Video State
7.
Software
IN" 10H
AH = 10
AL=OO
A L =01
AL=02
AH = 13
A L = 00
A L = 01
Color Palette Interface
Set Individual Register
Set Border Color
Set All Palette Registers and Border
Write String
Write Character String
Write Character String and
Move Cursor
A L = 02 Write Character and Attribute Strings
A L = 03 Write Character and Attribute Strings
and Move Cursor
8.
BIOS Services
Function Descriptions
Set CRT Mode
Entry Conditions
AH
=
0
AL
=
mode value, as follows:
Alpha Modes
AL = 0: 40x25 black and white
AL = 1: 40x25 color
AL = 2: 80x25 black and white
AL = 3: 80x25 color
Graphics Modes
AL = 4: 320x200 color graphics
AL = 5: 320x200 black and white
graphics with 4 shades
AL = 6: 640x200 black and white graphics
with 2 shades
AL = 7 monochrome text
Additional Modes
AL = 8: 160x200 color graphics
with 16 colors
AL = 9: 320x200 color graphics
with 16 colors
AL = A: 640~200colorgraphics
with 4 colors
Note: If the high order bit of the AL register is 1,then the video
buffer is not cleared.
9.
Software
Set Cursor Type
Set the cursor type and attribute.
Entry Conditions
AH
= 1
CH
=
bit values:
Bits 5-6 = an invisible or erratically blinking cursor
Bits 5-6 = 0: produces a visible, blinking cursor
Bits 4-0 = start line for cursor within character cell
CL
= bit values:
Bits 4-0
=
end line for cursor within character cell
Set Cursor Position
Write (set) cursor position.
Entry Conditions
AH
= 2
BH
=
page number (must be 0 for graphics modes)
DH
=
row (0 = top row)
DL
= column
(0 = leftmost column)
BIOS Services
Get Cursor Position
Read (get) cursor position.
Entry Conditions
AH
BH
=
3
=
page number (must be 0 for graphics modes)
Exit Conditions
DH
=
row of current cursorposition (0
DL
=
column of current cursorposition
(0 = leftmost column)
cursor type currently set [l]:
See previous “Set Cursor Type” (AH
CX
=
top row)
=
=
1).
Select Active Page
Select active display page (valid in alpha mode only).
Entry Conditions
AH
AL
AL
AL
AL
AL
AL
5
= 0 through 7:
new page value for modes 0, 1
= 0 through 3:
newpage values for modes 2, 3
= 80H: read CRT/CPU page registers
= 81H: set CPU page register to value in BL
= 82H: set CRT page register to value in BH
= 83H: set CRT and CPU page registers in BH and BL
=
Exit Conditions
If Bit 7 of AL = 1upon entry, then:
BH
= contents of CRTpage register
BL
= contents of CPUpage register
11.
Software
Scroll Up
Scroll active page up.
Entry Conditions
AH
AL
CH
CL
DH
DL
BH
6
= numbers of lines to scroll. The number of lines that
Will be left blank at the bottom of the window.
(0 = blank entire window)
= row of upper left comer of scroll window
= column of upper left comer of scroll window
= row of lower right corner of scroll window
=
column of lower tight corner of scroll window
= attribute (alpha modes) or color (graphics modes)
to be used on blank line
=
Attributes
Color modes.
Foreground color:
Bit 0 =
blue
Bit1 =
green
Bit2 =
red
Bit 3 =
intensity
All bits off =
black
Background color:
blue
Bit 4 =
green
Bit5 =
Bit6 =
red
blink
Bit 7 =
All bits off =
white
BIOS Services
Scroll Down
Scroll active page down.
Entry Conditions
= 7
AH
AL
=
CH
= row of upper left corner of scroll window
CL
DH
DL
BH
number of lines to scroll (0
=
blank entire window)
column of upper left comer of scroll window
= row of lower right corner of scroll window
= column of lower right corner of scroll window
= attribute (alpha modes) of color (graphics modes)
to be used on blank line. See “Scroll Up” (AH = 6) for attribute values and “Set Color Palette” (AH = 11) for
color values.
=
Read Attribute or Color/Character
Read a character and its attribute or color at the current cursor position.
Entry Conditions
AH
BH
8
= displaypage number (not used in graphics modes)
=
Exit Conditions
AL
=
characterread
AH
=
attribute of character (alpha modes only)
13.
Software
Write Attribute or Color/Character
Write a character and its attribute or color at the current cursor position.
Entry Conditions
AH
= 9
BH
= displaypage number (not used in graphics modes)
CX
= number of characters to write
AL
BL
= character to write
=
attribute of character (for alpha modes) or color of
character (for graphics modes. If Bit 7 of BL is set, the
color of the character is XOR’ed with the color value).
See “Scroll Up” (AH = 6) for attribute values and “Set
Color Palette” (AH = OBH) for color values.
Write Character Only
Write character only at current cursor position.
Entry Conditions
AH
BH
= OAH
CX
= number of characters to write
AL
BL
= character to write
14.
= displaypage number (valid for alpha modes only)
= color of character (graphics mode)
BIOS Services
Set Color Palette
Select the color palette.
Entry Conditions
AH
= OBH
BH
Set background color (0-15) to color value
in BL.
= colorvalue:
BL
1
2
3
4
= 0:
= blue
= green
= cyan
= red
5
6
7
8
9
10
11
12
= magenta
= yellow
= light grey
= dark grey
= lightblue
= light green
= light cyan
13 = light magenta
14 = yellow
15 = white
= light red
or
BH
= 1: Set default palette to the number (0 or 1) in BL.
In black and white modes:
BL
= 0: 1 for white
BL
= 1: lforblack
In 4 color graphics modes:
BL
BL
= 0:
=
(1 = green, 2
1: (1 =
red, 3 = yellow)
cyan, 2 = magenta, 3 = white)
=
In 16 color graphics modes:
1
2
3
4
= blue
= green
5 = magenta
6 = yellow
= cyan
7 = light grey
8 = dark grey
= red
9
10
11
12
= light blue
= light green
= light cyan
13 = light magenta
14 = yellow
15 = white
= light red
Note: For alpha modes, Palette Entry 0 indicates the border
color. For graphics modes, Palette Entry 0 indicates the border
and the background color.
15.
Software
Write Dot
Write a pixel (dot).
Entry Conditions
OCH
AH
=
DX
CX
AL
= rownumber
=
=
columnnumber
color value (When Bit 7 of AL is set, the resultant
color value of the dot is the exclusive OR of the current
dot color value and the value in AL.)
Read Dot
Read a pixel (dot).
Entry Conditions
AH
= ODH
DX
CX
=
rownumber
= columnnumber
Exit Conditions
AL
16.
=
color value of dot read
BIOS Services
Write TTY
Write a character in teletype fashion. (Control characters are interpreted in the normal manner.)
Entry Conditions
AH
AL
BL
BH
OEH
= character to write
= foreground color (graphics mode)
= dispZaypage (alpha modes)
=
Get CRT Mode
Get the current video mode.
Entry Conditions
= OFH
AH
Exit Conditions
AL
= current video mode. See the previous “Set CTR Mode”
(AH = 0) for values
AH
BH
number of columns on screen
= current active display page
=
17.
Software
Set Palette Registers
Sets palette registers.
Entry Conditions
AH
=
AL
=
BL
BH
AL
10H
0: Set Palette register
= number of palette register (0 -15) to set
= color value to store
=
1: Set border color register
color value to store
AL
= 2: Set palette color value to store and
border registers
ES:DX points to a 17-byte list.
Bytes 0-15 = values forpalette registers 0-15
Byte 16
= value for border register
BH
18.
=
BIOS Services
Write String
Display a string of characters on screen.
Entry Conditions
AH
=
13H
ES:BP = pointer to start of string
CX
= length of string (attributes do not count)
DX
= startingcursorposition (DH = row, DL = column)
BH
= page number (for text modes)
BL
= attribute for characters (graphics modes)
AL
= 00: Characters only string, cursor not updated
= 01: Characters only string, cursor updated
= 02: Character, attribute alternating string, cursor
not updated
=
03: Character, attribute alternating string, cursor
updated
19.
Software
Serial Communications
These routines provide asynchronous byte stream I/O from and to the
RS-232C serial communications port. This device is labeled the
auxiliary (AUX) I/O device in the device list maintained by MS-DOS.
Software Interrupts
14 hex (20 dec)
Function Summary
AH
AH
= 0:
AH
= 2:
AH
DX
= 3:
20.
=
=
Reset Commport
1: Transmit character
Receive character
Get current Comm status
communication port number (0 or 1)
BIOS Services
Function Descriptions
Reset Comm Port
Reset (or initialize) the communication port according to the
parameters in AL, DL, and DH.
Entry Conditions
AH
=
AL
=
0
RS-232Cparameters, as follows:
DX
=
port number (0 or 1)
7
6
5
Baud Rate
4
3
2
Parity
b
1
Stop Bits
0
Word Length
I
I
000
= 110baud
00 =none
0
=1bit
10 =7bits
001
= 150baud
01 =odd
1
= 2 bits
11 = 8 bits
010
=
011
100
= 600baud
= 1200 baud
101
=2400 baud
110
=4800baud
=9600 baud
111
300baud
11 =even
Exit Conditions
AX
= RS-232C status; See the fol1owing"Get Current
Comm Status" (AH = 3)
21.
Software
Transmit Character
Transmit (output) the character in AL (which is preserved).
Entry Conditions
AH
= 1
AL
DX
= character to transmit
=
port number (0 or 1)
Exit Conditions
AH
= RS-232C status; See the following “Get Current
Comm Status” (AH = 3). If Bit 7 is set, the routine was
unable to transmit the character because of a timeout
error .)
AL is preserved
Receive Character
Receive (input) a character in AL (wait for a character, if necessary).
On exit, AH will contain the RS-232 status, except that only the error
bits (1, 2, 3, 4, 7) can be set; the timeout bit (7), if set, indicates that
data set ready was not received and the bits in AH are not meaningful.
Thus, AH is non-zero only when an error occurred.
Entry Conditions
AH
= 2
DX
=
port number (0 or 1)
Exit Conditions
AL
AH
=
character received
= RS-232C status; See the following “Get Current
Comm Status’’ (AH
22.
=
3)
BIOS Services
Get Current Comm Status
Read the communication status into AX.
Entry Conditions
AH
=
3
DX
=
port number (0 or 1)
Exit Conditions
AH
=
RS-232Cstatus, as follows (set = true):
Bit0 = data ready
Bit 1 = overrun error
Bit 2
=
parity error
Bit3
=
framingerror
Bit4
=
breakdetect
Bit 5 = transmitter holding register empty
Bit 6
Bit 7
AL
=
transmitter shift register empty
timeout occurred
=
modem status, as follows (set = true):
=
Bit 0 = delta clear to send
Bit 1 = delta data set ready
Bit 2 = trailing edge ring detector
Bit 3
Bit4
=
Bit 5
Bit 6
=
=
data set ready
ring indicator
Bit 7
=
receive line signal detect
=
delta receive line signal detect
clear to send
23.
Sofhvare
Line Printer
These routines provide an interface to the parallel line printer.
This device is labeled “ P R N in the device list maintained by the
operating system.
Software Interrupts
17 hex (23 dec)
Function Summary
AH
AH
=
0: Print character
=
1: Reset printer port
AH
= 2:
Get current printer status
Function Descriptions
Print a Character
Entry Conditions
AH
AL
DX
=
0
character to print
=
printer to be used (0-2)
=
Exit Conditions
OAH
24.
=
printer status. See the following “Get Current
Printer Status” (AH = 2)
(If Bit 0 is set, the character could not be printed
because of a timeout error.)
BIOS Services
Reset Printer Port
Reset (or initialize) the printer port.
Entry Conditions
AH
= 1
DX
=
printer to be used (0-2)
Exit Conditions
AH
=
printer status; See the following “Get Current
Printer Status” (AH = 2)
Get Current Printer Status
Read the printer status into AH.
Entry Conditions
AH
=
2
Exit Conditions
DX
= printer to be used (0-2)
AH
= printerstatus as follows (set
Bit 0 = timeout occurred
Bit 1 = [unused]
Bit2 = [unused]
Bit3 = I/Oerror
Bit 4 = selected
Bit5 = out ofpaper
Bit6 = acknowledge
Bit7 = notbusy
=
true):
25.
Sofhvare
System Clock
These routines provide methods of reading and setting the clock maintained by the system. This device is labeled CLOCK in the device list
of the operating system. An interface for setting the multiplexer for
audio source is also provided.
Software Interrupts
1A hex (26 dec)
Function Summary
AH
=
0:
Get time of day
AH
=
1:
AH
=
2:
Set time of day
Read real-time clock
AH
=
3:
Set real-time clock
AH
= 4:
Read date from real-time clock
5:
Set the date in the real-time clock
AH
= 80H:
Set up sound multiplexer
The clock runs at the rate of 1,193,180/65,536 per second (about 18.2
times per second).
AH
26.
=
BIOS Services
Function Descriptions
Get Time of Day
Get (read) the time of day in binary format.
Entry Conditions
AH
=
0
Exit Conditions
CX
DX
AL
high (most significant)portion of the clock count
= low (least significant) portion of the clock count
= 0 of the clock was read or written (via AH = 0,l) within the
current 24-hour period; otherwise, AL = 0
=
Set Time of Day
Set (write) the time of day using binary format.
Entry Conditions
AH
=
1
CX
=
high (most significant)portion of clock count
DX
=
low (least significant) portion of clock count
27.
Software
Read Clock Time of Day
Read the time of day kept in the clock.
Entry Conditions
AH
= 2
Exit Conditions
CH
CL
DH
=
=
=
hoursinBCD
minutesinBCD
secondsinBCD
Set Clock Time of Day
Set the time of day kept in the clock.
Entry Conditions
AH
CH
CL
DH
28.
3
= hoursinBCD
= minutesin BCD
= secondsinBCD
=
BIOS Services
Read Clock Date
Read the date kept in the clock.
Entry Conditions
AH
= 4
Exit Conditions
CH
= centuryinBCD
CL
= yearinBCD
= monthinBCD
DH
DL
= dayinBCD
Set Clock Date
Set the date kept in the clock.
Entry Conditions
AH
= 5
CH
CL
DH
DL
centuryinBCD
= yearinBCD
= monthinBCD
= dayinBCD
=
29.
Soware
Sound Multiplexer
Sets the multiplexer for audio source.
Entry Conditions
AH
AL
00
02
03
30.
=
=
=
=
=
80
source of sound
8253 channel 2
audio in
complex sound generator chip
BIOS Services
Disk I/O Support for Diskette Only
System Configuration
Software Interrupt
13 hex (19 dec)
Function Summary
AH
=
0:
AH
=
1:
Reset diskette
Return status of last diskette operation
AH
=
2:
Read sector(s) from diskette
AH
=
3:
Write sector(s) to diskette
AH
AH
=
4:
Verify sector(s) on diskette
Format track on diskette
AH
AH
AH
5:
= 08H:
= 15H:
=
=
16H:
Read drive parameters
Read DASD type
Diskette change line status
31.
Software
Function Descriptions
Reset Diskette
Reset the diskette system. Resets associated hardware and recalibrates
all diskette drives.
Entry Conditions
AH
=
0
Exit Conditions
See the following “Exits From All Calls.”
Return Status of Last Diskette Operation
Returns the diskette status of the last operation in AH.
Entry Conditions
AH
= 1
Exit Conditions
AL
= status of the last operation. For values, see the
following “Exits From All Calls.”
32.
BIOS Services
Read Sector(s) from Diskette
Read the desired sector(s) from the diskette into RAM.
Entry Conditions
AH
=
DL
drive number (0-2 if Tandy 1000 TL; 0-1 if Tandy
1000 SL)
= head number (0-1)
= track number (0-79)
= sector number (1-9)
= sector count (1-9)
DH
CH
CL
AL
2
=
ES:BX = pointer to disk buffer
Exit Conditions
See the following “Exits from all Calls.”
AL
=
number of sectors read
Write Sector(s) to Diskette
Write the desired sector(s) from RAM to disk.
Entry Conditions
AH
=
DL
=
DH
=
CH
=
CL
=
AL
=
ES:BX =
3
drive number (0-2 if Tandy 1000 TL; 0-1 if Tandy
1000 SL)
head number (0-1)
track number (0-79)
sector number (1-9)
sector count (1-9)
pointer to disk buffer
33.
Software
Exit Conditions
See the following “Exits From All Calls.”
AL
=
number of sectors written
Verify Sector(s) on Diskette
Verify the desired sector(s) are readable.
Entry Conditions
AH
= 4
= drive number (0-2 if Tandy 1000 TL; 0-1 if Tandy
DL
1000 SL)
DH
= head number (0-1)
CH
=
CL
=
AL
=
track number (0-79)
sector number (1-9)
sector count (1-9)
Exit Conditions
See the following “Exits From All Calls.”
AL
= number of sectors verified
Format on Diskette
Format the desired track.
Entry Conditions
AH
= 5
AL
= sector count (1-9)
DL
= drive number (0-2 if Tandy 1000 TL; 0-1 if Tandy
1000 SL)
DH
= head number (0-1)
CH
= track number (0-79)
CL
= sector number (1-9)
34.
BIOS Services
ES:BX = pointer to a group of address fields for each track. Each address field is made up of 4 bytes. These are C, H, R, and
N, where:
C
= tracknumber
H
= headnumber
R
= sector number
N
= the number of bytes per sector
(00 = 128,Ol = 256,02 = 512,03 =
1024)
There is one entry for every sector on a given track.
Exit Conditions
See the following “Exits From All Calls.”
Read Drive Parameters
Return the drive parameters.
Entry Conditions
AH
= 08H
DL
= drive number (0-2 if Tandy 1000 TL; 0-1 if Tandy
1000 SL)
Exit Conditions
AX
= 0
BH
= 0
CH
= Maximum usable track number
= Maximum usable sector number
CL
DH
= Maximum usable head number
= Number of diskette drives installed (0-2 if Tandy
DL
1000TL; 0-1 if Tandy 1000 SL)
ES:Dl = Pointer to diskette drive parameter table for the
maximum media type supported on the specified
drive
Software
CF
=
0: Noerror
CF
=
1: Illegal parameter
Read DASD Type
Return the change line status.
Entry Conditions
AH
DL
=
=
15H
drive number (0-1 if Tandy 10000 TL; 0-1 if Tandy
1000 SL)
Exit Conditions
Operation was not successful. Previous versions
of the Tandy 1000 will return CF= 1.
CF
= 1:
AH
= 1: Invalid command.
CF
AH
=
36.
0: Operation was successful
= 0:
Drivenotpresent
= 1:
Diskette, no change line available
= 2:
Diskette, change line available
BIOS Services
Diskette Change Line Status
Return the status of the diskette change line.
Entry Conditions
AH
DL
=
16H
= drive number
(0-2 if Tandy 1000 TL; 0-1 if Tandy
1000 SL)
Exit Conditions
CF
CF
AH
=
=
=
=
=
=
0:
1:
0:
1:
6:
80:
IfAH=O
IfAHisnonO
Diskette change signal not active
Invalid diskette parameter
Diskette change signal active
Diskette drive not ready (drive door is open)
Exits From All Calls
AH
= Status of operation, where set
=
true
Error Code
Condition
01H
Illegal Function
02H
Address Mark Not Found
03H
Write Protect Error
04H
Sector Not Found
06H
Diskette Change Line Active
08H
DMA Overrun
Attempt to DMA Across a 64K Boundary
09H
Bad CRC on Disk Read
10H
20H
Controller Failure
40H
Seek Failure
Device
Timeout, Device Failed to Respond
80H
[NC] = operation successful (AH = 0)
= operation failed (AH = error status)
[C]
37.
Software
Equipment
This service returns the “equipment flag” (hardware configuration of
the computer system) in the AX register.
Software Interrupts
11hex (17 dec)
The “equipment flag” returned in the AX register has the following
meanings for each bit:
Reset
= the indicated equipment is not in the system
= the indicated equipment is in the system
Set
Bit 0
Bit 1
Bits 2,3
diskette installed
= math coprocessor
always = 11
Bits 4,5
initial video mode
01
10
=
40x25 Color
80x25 Color
11
80x25 Monochrome
Bits 6,7 number of diskette drives (only if Bit 0 = 1)
00
1
01
2
3 (Tandy 1000 TL ONLY)
10
0 = DMA present (always present)
Bit 8
1 = noDMApresent
number of RS232 cards
Bits 9, 10, 11
Bit 12
game I/O adapter present (joystick)
Bit 13
not used
Bits 14,15
number of printers
38.
BIOS Services
Memory Size
This service returns the total number of kilobytes of RAM in the computer system (contiguous starting from Address 0) in the AX register.
The maximum value returned is 640.
Software Interrupts
12 hex (18 dec)
Bootstrap Loader
Track 0, Sector 1is read into Segment 0, Offset 7COO.
Control is then transferred as follows: (CS)
(IP) = 7COOH
=
OOOOH
(DL) - drive where bootstrap sector was read
Software Interrupts
19 hex (25 dec)
39.
Software
System Services
Software Interrupts
15 hex (Zldec)
Function Summary
AH = COH: Machine identification
AH = 15H: Read and write EEPROM data
Function Descriptions
Machine Identification
The machine identification algorithm is the same as all previous Tandy
1000's. As well, the Tandy 1000SL and Tandy 1000 TL computers have
a new BIOS call to further identify the machine.
All current and previous Tandy 1000 computers have the following
machine identification:
Byte at address FFFF:E = FF hex (compatible with IBM PC)
Byte at address FC000:O
=
21 hex (Tandy 1000 unique)
Entry Conditions
AH
= COH
Exit Conditions
If CF
= o
ES:BX = pointer to machine identification data in ROM
DW 0003 Byte count of data that follows (always 3 )
DB xx
ModeiID
DB xx
DB xx
SubmodelID
BIOS revision levei
BIOS Services
IF CF
=
1,the call is not supported (all previous
versions of the Tandy 1000)
Model ID
Tandy 1000 SL
FF
Submodel ID
BIOS revision level
00
Tandy 1000 TL
FF
01
xx
Function Descriptions
Read From EEPROM
Read the 16-bit value from the indicated EEPROM word.
Entry Conditions
AH
AL
=
=
70H
0
BL
=
word number to read (0-63)
Exit Conditions
DX
= word value
Carry flag set indicates EEPROM call not supported.
41.
Software
Write to EEPROM
Write a 16-bit value to the indicated EEPROM word.
Entry Conditions
AH
AL
BL
DX
=
70H
= 1
= word number to write (0-63)
= word value to write
Exit Conditions
Carry Flag set indicates EEPROM call not supported.
42.
BIOS Services
Tandy 1000 SL and Tandy 1000 TL BIOS Sound
support
The BIOS in these computers has the same support for sound as all
previous Tandy 1000 computers, as well as support for additional
sound features. The API for this new BIOS support is defined in the
following information.
Software Interrupts
1A hex (26 dec)
Function Summary
AH
= 81H:
AH
AH
AH
=
=
=
82H:
83H:
84H:
Get sound status
Input sound (from the microphone)
Output sound (to the speaker)
Stop sound input and output
Function Descriptions
Get Sound Status
Gets sound status.
Entry Conditions
AH
=
81H
Exit Conditions
Not Busy:
AX
CF
=
=
OOC4H
0
43.
Software
Busy:
AX
=
OOC4H
CF
=
1
Input Sound
Inputs sound from the microphone.
Entry Conditions
AH
= 82H
ES:BX = buffer address
CX
= buffer length
= transfer rate (1-4095, where 1is the fastest
DX
transfer rate)
Exit Conditions
Not Busy:
AH
= 0
CF
Busy:
AH
CF
44.
=
0
= 0
=
1
BIOS Services
Output Sound
Outputs sound to the speaker.
Entry Conditions
AH
= 83H:
Output sound (to the speaker)
ES:BX = buffer address
CX
= buffer length
DX
= transfer rate (1-4095, where 1is the fastest
transfer rate)
volume (0-7, where 0
Exit Conditions
Not Busy:
AH
= 0
AL
=
CF
=
Busy:
AH
= 0
CF
=
=
no sound)
0
1
Stop Sound Input and Output
Stops sound input and output.
Entry Conditions
AH
= 84H
Notes: The transfer rate values in register DX are not the same
for calls AH = 82H and AH = 83H. To input a buffer of data with
the AH = 82H call with a given DX value, then play it back with
the AH =83H call so that it sounds the same, set the DX value
for output approximately 11.5 times as large as the DX value for
input when run on a Tandy 1000SL and approximately 10.0 times
faster on a Tandy 1000 TL.
45.
Software
This BIOS call uses the DMA hardware to input and output the
sound buffer. When functions AH = 82H and AH = 83H are
called, the BIOS initiates the 1/0 and returns to the calling
program immediately. When the DMA transfer is complete, the
BIOS will receive a hardware interrupt and will execute a
software INT 15H with AH = 91H and AL = FBH. If an application program needs to know when the data transfer is complete,
it has to hook INT 15H and watch for this event.
The BIOS call masks the hardware restriction of not being able
to DMA across a 64 kilobyte memory address boundary from the
calling program.
46.
BIOS Services
Keyboard ASCII and Scan Codes
Function Keys, Cursor Keypad, Numeric Keypad
SCAN
CODE
NORM CASE
ASCII CODE
UPPER CASE
ASCII CODE
CTRL CASEALT CASE
ASCII CODE
ASCII CODE
38
3c
3D
3E
3F
40
41
42
43
44
57
58
E037
46
E145
E046
E052
E047
E049
E053
E04F
E051
E048
E048
EO50
E04D
45
E035
37
47
48
49
4A
40
F1
x3B
F2
x3C
F3
x3D
F4
x3E
F5
x3F
F6
x40
F7
x41
F8
x42
F9
x43
F10
x44
e8500
F11
F12
e8600
PrintScrn*
Scr Lock
Pause*
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
4c
4D
4E
4F
50
51
52
53
EOfC
01
02
03
04
05
08
07
08
09
--
PrintScrn*
Scr LockPause*
x54
x55
x56
x57
x58
x59
x5A
x5B
x5c
x5 D
e8700
e8800
CPrSc
-Break*
Insert
Home
Page Up
Delete
End
Page Down
UP
Left
Down
Right
Num Lock-2F
2A
Home
x47
UP
x48
PageUp x49
2D
Left
x4B
e4CFO
RIGHT x4D
+
28
End
x4F
DOWN x50
PgDn
x51
Ins
x52
Del
x53
Enter
OD
ESC
1B
1
31
2
32
3
33
4
34
5
35
6
36
7
37
8
38
;
X52
x47
x49
X53
x4F
x51
X48
x4B
x50
x4d
Num Lock
;
7
8
9
4
5
6
+
1
2
3
0
Enter
ESC
!
@
x
b
%
A
&
*
x5E
x5F
X60
x6l
x62
X63
X64
X65
X66
x67
e8900
e8AOO
x72
e52EO
e47EO
e47EO
e53EO
e4FEO
e51EO
e48EO
e4BEO
e50EO
e4DEO
--
2F
2A
37
I
x77
x84
x75
x76
x73
x74
ClrSc
TOS
LWord
Word
ErEOL
ErEOS
30
2E
OD
1B
21
40
23
24
25
5E
26
2A
SysRq*
Scr Lock
Pause*
LF
ESC
e9500
e9600
x77
e8DW
x84
e8EOO
x73
e8F00
x74
em00
x75
e9100
x76
e9200
e9300
OA
1B
-
-
NULL
-
00
-Rs
-1E
-
x68
x69
x6A
x6B
x6C
x6D
x6E
x6F
x70
x7 1
e8600
e8c00
-
---
XOO
eA200
e9700
e9900
eA300
e9F00
ea100
eQ800
e9600
eA000
e9D00
e92EO
e77EO
e84EO
e93EO
e75EO
e76EO
e8DEO
e73EO
e91EO
e74EO
Num Lock
38
39
2D
34
35
36
28
31
32
33
F31
F32
F33
F34
F35
F36
F37
F38
F39
F40
-
--
eA400
e37f0
Y
Y
Y
e4af0
Y
Y
Y
MEFO
Y
Y
Y
Y
ALTl
ALTP
ALT3
ALT4
ALTS
ALTG
ALT7
ALT8
eA600
e01f0
x78
x79
x7A
x7B
x7C
x7D
x7E
x7F
47.
Software
SCAN
CODE
NORM CASE
ASCII CODE
OA
OB
9
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1c
1D
EO1D
1E
1F
20
21
22
23
24
25
26
BS
HT
q
08
09
71
W
77
e
r
t
65
72
74
79
75
69
6F
70
58
50
OD
oc
27
28
29
2A
28
2c
2D
2E
2F
30
31
32
33
34
35
36
38
E038
39
3A
56 +
48.
Y
u
i
0
r
I
Enter
Ctrl
Ctrl
a
S
d
f
g
i
I
,
39
30
20
3D
I
61
73
64
66
67
68
6A
6B
6C
38
27
60
LShift
\
z
X
C
V
b
n
m
UPPER CASE
ASCII CODE
(
1
-
+
Bs
BTab
Q
W
E
R
T
Y
U
I
0
P
1
Enter
Ctrl
Ctrl
A
S
D
F
G
H
J
K
L
N
CTRL CASEALT CASE
ASCII CODE
ASCII CODE
28
29
5F
28
-
us
1F
08
DEL
7F
e9400
11
17
05
12
14
19
15
09
OF
10
1B
1D
OA
XOF
51
57
45
52
54
59
55
49
4F
50
78
7D
OD
41
53
44
46
47
48
4A
48
4c
DC1
ETB
ENQ
DC2
DC4
EM
NAK
HT
SI
DLE
ESC
GS
LF
Ctrl
Ctrl
SOH
DC3
EOT
ACK
BEL
BS
LF
VT
FF
9
2c
i
2E
2F
RShift
Alt
AI!
SPACE 20
CapsLock-\
5c
I
Z
X
C
v
B
N
M
<
>
?
RShifl
AH
Alt
SPACE
Caps Lock
I
ALTQ
ALTW
ALTE
ALTR
ALTT
ALTY
ALTU
ALTl
ALTO
ALTP
x80
x8 1
x82
x83
eOEFO
eA500
XlO
xl1
x12
x13
x14
x15
x16
x17
x18
XlQ
elAFO
elBFO
elCFO
Ctrl
ct rl
01
13
04
06
07
08
OA
OB
oc
ALTA
ALTS
ALTD
ALTF
ALTG
ALTH
ALTJ
ALTK
ALTL
xlE
xlF
x20
x2 1
x22
x23
x24
x25
x26
e27f0
e28f0
e29f0
3A
22
7E
LShift
LShifl
5c
7A
78
63
76
62
6E
6D
ALTS
ALTO
ALTALT =
7c
5A
58
43
56
42
4E
4D
3c
3E
3F
20
7c
FS
SUB
CAN
ETX
SYN
STX
so
CR
RShift
Alt
Alt
SPACE
1c
1A
18
03
16
02
OE
OD
20
ALTZ
ALTX
ALTC
ALTV
ALTB
ALTN
ALTM
e2bf0
x2c
x2D
x2E
x2F
x30
x31
x32
e33f0
e34f0
e35f0
RShifl
AI!
Alt
20
SPACE
CapsLock
BIOS Services
Keyboard Tables
These symbols have special meanings in the following tables:
--
Indicates that no ASCII code is generated for the key combination.
X
Values preceded by x are extended ASCII codes. The
keyboard driver returns a NULL ASCII code and the number in the table for the scan code.
e
Values preceded by e are produced when you are using an
enhanced BIOS. When using the BIOS Read Key function,
these keys are either discarded or translated to a value compatible with older computers. When using the Enhanced
Read Key function, AH=lOH, INT l6H, these keys are
returned to your program.
+
A + in the scan code field denotes the extra key on the international version of the enhanced keyboard. This key is
not available on the standard USA enhanced keyboard.
Y
The ALT key provides a way to generate the ASCII code of
the decimal numbers in the range 1to 255. Hold down the
ALT key while typing a number in that range on the numeric
keypad. When you release the ALT key, the character of the
ASCII code you typed is generated and displayed.
BREAK Empties the keyboard queue and executes the keyboard
break interrupt (INT 1BH). Places a NULL ASCII scan
code in the keyboard queue.
PAUSE Delays system activity until you press another key.
PrtSC or Invokes the BIOS print screen function (INT 5H).
Print Scrn
49.
Software
CPrSc
SysRq
Tells MS-DOS to direct console output to both the printer
and the console. A second CPrSc halts printer output.
Interrupts the current process and allows another program
to take control, if supported. When the SysRq key is
pressed, INT 15H is invoked with AX=8500H. When the
key is released, INT 15H is invoked with AX = 8501H.
Reset
Restarts your computer.
50.
BIOS Services
MS-DOS Memory Map
Hexadecimal
Starting Address
(Segment:Offset)
ooo:oo
000:80
oo40:oo1
0050:OO
0070:OO
0190:oo2
05BO:002
X80O:0O3
XCOO:003
B800:004
E000:OO
F000:OO
FC00:OO
Description
BIOS Interrupt Vectors
Available Interrupt Vectors
ROM BIOS Data Area
MSDOS and BASIC Data Area
I/O.SYS Drivers
MS-DOS
Available to user
Video RAM in 32K video modes
Video RAM in 16K video mode
Video RAM Window (32K)
ROM Drive
Reserved for system ROM
System BIOS ROM
Notes:
Detailed description in following pages.
Approximate address; subject to change.
X is defined as follows:
X Value
128K
1
256K
3
384K
5
512K
7
9
640K
768K
B
Video memory accessed through the B800:O window for
all video modes.
Memory Size
51.
Software
ROM BIOS Data Area
The following table gives the starting offset, and length of each BIOS
device driver. This area is located at segment 40:OO.
Comm card address
0000
8 (1word per card)
Printer addresses
0008
8 (1word per printer)
Devices installed
Not used
Memory size
I/O channel RAM size
0010
0012
0013
0015
2 (16 bits)
1
2 (1word)
2 (1word)
KBD data area
0017
39
Disk data area
003E
0049
11
30
0067
006C
5
5
0071
3
0074
4
0078
4 (1 byte per printer)
007C
4 (1 byte per card)
0080
4 (2 words)
Video data area
Not used
Clock data area
KBD Break & Reset flags
Not used
Printer timeout counter
Comm timeout counter
KBD extra data area
52.
BIOS Services
The structure and usage of the Video driver RAM data area is as follows:
HEX Offset
From Segment
Length and
Intended Use
oo4o:oooo
49H
1byte -
current CRT mode (0-7)
4AH
1word -
screen column width
4CH
4EH
1word 1word -
byte length of screen
address/offset of beginning of
current display page
50H
8 words-
60H
lword
62
1byte -
current display page 1word base address + 4 of the CRT
controller card
65H
1byte -
copy of value written to
the Mode Select Register
66H
1 byte -
current color palette setting
-
row/col coordinates of the
cursor for each of up to 8
display pages
current cursor type (See
“Set Cursor Type” for correct
encoding)
53.
Software
The equipment check BIOS call (INT 11H) and memory size BIOS call
(INT 12H) return information from the following data areas:
HEX Offset
From Segment
Length and
oo4o:oooo
Intended Use
10H
Devices installed word
13H
Memory installed word
The structure and usage of the diskette driver RAM data area is as follows:
HEX Offset
From Segment
oo4o:oooo
3EH
Length and
Intended Use
1byte drive recalibration status - bit
3-0, if 0 then drive 3-0 needs
recalibration before next Seek.
Bit 7 indicates interrupt
occurrence
3FH
1byte -
motor status - Bit 3-0 drive
3-0 motor is on/off. Bit 7 current operation is write,
requires delay
40H
1byte -
motor turn off timeout
counter (see Timer ISR)
41H
1byte -
42H
7 bytes -
disk status - codes are
defined as in this section
7 bytes of status returned by
the controller during result
phase of operation
54.
BIOS Services
Value
01H
02H
03H
04H
06H
08H
09H
10H
20H
40H
80H
Error Condition
Illegal Function
Address Mark Not Found
Write Protect Error
Sector Not Found
Diskette Change Line Active
DMA Overrun
Attempt to DMA Across a 64K Boundary
Bad CRC on Disk Read
Controller Failure
Seek Failure
Device Timeout, Device Failed to Respond
The structure and usage of the RS232 driver RAM data area is as follows:
HEX Offset
From Segment
0040:OOOO
OOH
7CH
Length and
Intended Use
4 words - Base address of each one of 4
possible comm cards
4 words - 1word timeout count for each
of 4 possible comm cards
55.
Software
~~
~
The structure and usage of the Keyboard driver RAM data area is as
follows:
HEX Offset
From Segment
0040:0010
17
18
19
1A
1c
1E
56.
Length and
Intended Use
1byte- Keyboard shift state flag
returned by function 02
Bits 7- INSERT state active,
6 - CAPS LOCK On/Off,
5 - NUM LOCK on/off,
4 - SCROLL LOCK on/off,
3 - ALT key pressed
2 - CTRL key pressed
1- Left SHIFT key pressed,
0 - Right SHIFT key pressed,
lbyte- Secondary shift state flag,
Bits
INSERT key pressed,
6 - CAPS LOCK pressed,
5 - NUM LOCK pressed,
4 - SCROLL LOCK NUM LOCK
pressed,
4 - SCROLL pressed,
4 - SCROLL LOCK pressed,
3 - Pause odoff, pressed,
3 - Pause odoff,
2,1,0 - not used
1byte- Used to store ALT keypad entry
1word- Pointer to beginning of the
keyboard buffer
1word- Pointer to end of the keyboard
buffer
16Keyboard buffer (enough for words)
15Type ahead entries
BIOS Services
The structure and usage of the clock service routine is as follows:
HEX Offset
From Segment
Length and
oo4o:oooo
Intended Use
6CH
1word - Least significant 16 bits of
clock count
6EH
1word Most significant 16 bits of
clock count
70H
Twentyfour hour rollover
1byte flag
57.
Software
Additional Data Area
HEX Offset
From Segment
0040:0000
BOH
B4H
B5H
2 words international support
1byte
0 = No monochrome monitor
FFH = Monochrome monitor
1 byte
Bit 0: 0 = DriveA is 5-1/4"
1 = Drive A is 3-1/2"
Bit 1: 0
=
Drive B is 5-1/4"
1 = Drive B is 3-1/2"
Bit 2:
Bit3
Bit 4:
58.
0
=
Tandy 1000 keyboard layout
1
=
IBMkeyboard
layout
0
=
SlowCPUspeed
mode
1
=
Fast CPUspeed
mode
0
=
Internal color
video support
enabled
1
=
Internal color
video support
disabled, external
color video
enabled
BIOS Services
HEX Offset
From Segment
oo4o:oooo
Bit 5: 0
1
=
= No
external monochrome video installed
External monochrome video installed
B6H
1 byte Bit 0:
0
1
=
=
Drive C is 5-1/4"
Drive C is 3-1/2"
40:C2
1 byte
01
02
03
=
=
ROM drive is A:
ROM drive is B:
ROM drive is C:
=
59.
KEYBOARD SCAN CODES
Key Key
#
Dcscript.
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Esc
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
Print Scrn
Scroll Lock
Pause Break
or\
-
!or 1
Hardware
Make
Code--76
05
06
04
OC
03
0B
83
OA
01
Kybrd
Break
Kybrd Interrupt
Make
Break
.Code
Codc
_
_
_
-Code
F076
01
81
F005
3B
BB
FO06
3c
BC
F004
SD
BD
FOOC
3E
BE
F003
BF
3F
FOOB
C0
40
FOX3
41
c1
FOOA
c2
42
F001
43
C3
09
F009
44
c4
78
F078
57
D7
07
F007
58
D8
E07C
EOF07C
E 02A E 037 E 0B7E OA A
7E
F07E
C6
46
E11477 EIF014F077 EllD45
E19DC5
OE
FOOE
2B
AB
16
F016
02
82
-
Standard ASCII
(Scancode/ASCI I code)
Nur m ----01 1B
0118
01 1B
SB00
5400
6800
5 E 00
3C00
5500
5 F00
6900
3D 00
5600
6000
6A 00
3E00
5700
6 100
6B00
3F00
5800
6200
6C00
4000
5900
6300
6D 00
4 100
5A00
6400
6E 00
4200
5B00
6500
6F00
4300
5c00
6600
7000
4400
5D00
6700
7 100
-----
-----
-----
-----
-----
-----
Note'
Note:
Note'
2960
023 1
Note'
Note2
Note3
2978
0221
7200
-----
Note4
Note2
Note3
------
-----
-----
-----
_--_-
-----
7800
Extended ASCII
(Scan codelA SC I I code)
ShiftNorm
Alt
0 1 1B
01 IB
0llB
0100
3B00
6800
5400
5E00
3coo
5500
5F00
6900
SD00
5600
6000
6A 00
3E00
5700
6B00
6100
3F00
5800
6200
6C00
4000
5900
6300
6D 00
4 100
5A00
6400
6E 00
4200
5B00
6500
6F00
4300
5C00
6600
7000
4400
5D00
7100
6700
8500
8700
8900
8B00
8600
8800
8A 00
8c00
----Note'
Note'
7200
----Note2
Note2
4
Note3
Note3
Note
----6000
7E 00
2900
----_
023 1
022 1
7800
n0te2
n0te3
KEYBOARD SCAN CODES
Key Key
#
Descript.
Hardware Kybrd
Make
Break
_CodeCode
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
@or2
# or 3
$ or 4
% or 5
, or 6
&or 7
* or 8
( or 9
) or 0
- or t or =
Backspace
tnsert
Home
Pg u p
NumLock
I
*
-
1E
26
25
2E
36
3D
3E
46
45
4E
55
66
E070
E06C
E07D
77
E04A
7c
7B
FOlE
F026
F025
F02E
F036
F03D
F03E
F046
F045
F04E
F055
F066
EOF070
EOF06C
EOF07D
F077
EOF04A
F07C
F07B
Kybrd Interrupt
Make
Break
CAL--.CQdX
03
83
04
84
05
85
06
86
07
87
08
88
09
89
OA
8A
OB
8B
OC
8C
OD
8D
OE
8E
E02AE052 EOD2EOAA
E02AE047 EOC7EOAA
E02AE049 EOC9EOAA
45
C5
E 035
EOB5
37
87
4A
CA
Standard ASCII
(ScancodclA SC I I code)
Narm0332
0433
0534
0635
0736
0837
0938
OA 39
OB34
OC2D
OD 3D
OE 08
5200
4700
4900
Note’
352F
372A
4A 2D
0340
0423
0524
0625
075E
0826
092A
0A 28
OB29
OC5F
OD 2B
OE 08
5200
4700
4900
Note’
352F
372A
4A2D
Extcndcd ASCII
(Scancode/ASCII code)
Norm
S h ift0332
0340
0433
0423
0534
0524
0635
0625
0736
075 E
0837
0826
0938
092A
OA 39
OA 28
OB34
OB29
OC2D
OC5F
OD3D
OD2B
OE08
OE08
52EO
52EO
47E0
47E0
49E0
49E0
Note’
Note’
E02F
E02F
372A
372A
4A 2D
4A2D
A It
7900
7A 00
7 B 00
7c00
7D 00
7 E 00
7F00
8000
8 IO0
8200
8300
OE 00
A 200
9700
9900
Note’
A 400
3700
4A 00
KEYBOARD SCAN CODES
Key
#
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
Key
Descript.
Hardware Kybrd
Make
Break
Code
-CodeTab
OD
F 00 D
Q or q
15
F015
W or w
1D
FOID
E or e
24
F024
R or r
2D
F02D
Tort
2c
F02C
Y or y
35
F035
U or u
3c
F03C
I or i
43
F043
0 or o
44
F044
P or p
4D
F04D
{ or [
54
D 054
} or ]
5B
F05B
I or\
5D
F05D
Delete
E071
EOF071
End
E 069
E OF069
Page Down
E07A
EOF07A
7orHome
6C
F06C
8
75
F075
9 o r Page Up 7D
F07D
Kybrd Interrupt
Make
Break
Code-. .
Code
OF
8F
0
90
1
91
2
92
3
93
4
94
5
95
6
96
17
97
18
98
19
99
1A
9A
1B
9B
2B
AB
E02AE053 EOD3EOAA
E02AE04F EOCFEOAA
E02AE051 EOD1EOAA
47
c7
48
C8
49
c9
~
Standard ASCII
(Scancode/A SCI I code)
Norm
----OF90
OF00
I07 1
105 I
1 0 1I
000
1117
100
I177
1 I57
200
1265
1245
1205
1312
300
1372
1352
I474
1414
400
I454
I559
1519
500
1579
1675
1615
600
1655
1749
1769
I709
I700
180F
I800
184F
186F
1910
1900
1970
1950
1A5B
1A7B
1A IB
lBlD
1B5D
1B7D
2B7C
2B1C
2B5C
_---5300
5300
4F00
4F00
7500
----5100
7600
5 100
4700
4737
7700
Note6
---4800
Note6
4838
4939
8400
Note'
4900
Extended ASCII
(Scancode/ASCII code)
Norm
Shift
- C t L A
OF09
OF00
9400
1071
05 1
01 1
157
1 I7
1177
1265
205
245
1372
352
312
I474
454
414
1579
559
5 19
1675
655
615
1749
I769
1709
184F
I86F
180F
1950
1910
1970
lA1B
1A5B
1A7B
1 B5D
1 B7D
lBlD
2B7C
2B 1C
2B5C
53E0
53E0
93E0
4FE0
4FE0
75E0
51E0
51E0
76E0
4737
4700
7700
4800
4838
8D 00
4900
4939
8400
A t
A500
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
1a00
1BO0
2B00
A300
9F00
A 100
n0te6
n0te6
n0te6
KEYBOARD SCAN CODES
Key
#
Key
Descript.
Hardware Kybrd
Make
Break
Kybrd Interrupt
Make
Break
Standard ASCII
(Scancode/ASCII code)
-
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
+
Caps Lock
A or a
S or s
D or d
For f
C or g
H or h
J orj
Kor k
Lor I
: or ;
" or '
Enter
4
5
6
79
58
IC
1B
23
2B
34
33
3B
42
4B
4c
52
5A
6B
73
74
F079
F058
F0lC
FOlB
F023
F02B
F034
F033
F03B
F042
F04B
F04C
F052
F05A
F06B
F073
F074
4E
3A
1E
IF
20
21
22
23
24
25
26
27
28
IC
4B
4c
4D
CE
BA
9E
9F
A0
AI
A2
A3
A4
A5
A6
A7
A8
9C
CB
4E2B
Note'
1E61
IF73
2064
2166
2267
2368
246A
256B
266C
273B
2827
ICOD
4B00
CD
4D 00
cc
-----
_-----1 E41
I F53
2044
2146
2247
2348
244A
254B
264C
273A
2822
lCOD
4B34
4c35
4D 36
1EOl
1F13
2004
2 106
2207
2308
240A
2508
260C
----
---lCOA
7300
---
7400
Alt
----
Note7
1 E 00
1 FOO
2000
2 100
2200
2300
2400
2500
2600
----------
Note6
Note6
Note6
Extended ASCII
(Scancode/ASCII code)
Norm- - Shift - ... Ctrl - -~
A It
4E2B
9000
4E 00
4E2B7
___Note7
Note
IE61
IEOI
I E 00
IE41
1 F73
1 F53
IF13
1 FOO
2064
2044
2004
2000
2166
2146
2 106
2 100
2267
2247
2200
2207
2368
2348
2308
2300
246A
244A
240A
2400
256B
254B
250B
2500
266C
264C
2600
260C
---273B
273A
2700
---2827
2822
2800
lCOD
lCOD
lCOA
1coo
4800
4B34
7300
4COO
4c35
8F00
4D 00
4D 36
7400
Note6
n0tc7
n0te6
n0te6
KEYBOARD SCAN CODES
Key
#
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Hardware
Make
Code
~.
Lcft Shift
12
2 or z
IA
X or x
22
21
Cor c
V or v
2A
32
Bor b
31
N or n
3A
M or m
41
< or ,
40
> or .
?or1
4A
Right Shift
59
E075
Up Arrow
69
1 or End
72
2
IA
3 o r PgDn
Left Ctrl
14
11
Left Alt
Space
29
Key
Descript.
Kybrd
Break
Code
FO I2
FO 1 A
F022
F02 1
F02A
F032
F03 1
F03A
F04 I
F049
F04A
F059
E OF075
F069
F072
F07A
F014
F011
F029
Kybrd Interrupt
Make
Break
Codc
- CQdC
AA
2A
AC
2c
AD
2D
AE
2E
AF
2F
B0
30
B1
31
B2
32
B3
33
B4
34
B5
35
B6
36
E02AE048 E OC8E 0A A
CF
4F
DO
50
D1
51
9D
ID
B8
38
39
B9
Standard ASCII
(Scancode/ASCII code)
NormNote8
2C7A
2D 78
2E 63
2F76
3062
316E
326D
332C
3428
352F
Note8
4800
4F00
5000
5100
Note9
Note
3920
__ Shlift- _ C l r l
Note8
2C5A
2D58
2E 43
2F56
3042
314E
3241)
333c
3438
353F
Note'
4800
4F3 1
5032
5133
Note9
Notel'
3920
Note'
2C1A
2D 18
2E03
2F 16
3002
3 10E
320D
----_---_----
-A!t
Note'
2c00
2000
2E00
2F00
3000
3 100
3200
---------
-----
Note8
Note8
-----
----
7500
Note6
Note6
Note6
9
Note
Note"
3920
_---
7600
Note9
Notel'
3920
Extended ASCII
(Scancode/ASCII code)
Norm
Shift
ar!.---ALt
Note8
Note8
Note8
2C7A
2C1A
2c00
2C5A
2D 78
2D 18
2000
2D58
2E63
2E00
2E43
2E03
2F76
2F56
2F 16
2F00
3062
3002
3000
3042
316E
310E
3100
3 14E
326D
324D
320D
3200
----332C
3300
333c
----342E
343E
3400
----352F
3500
353F
Note8
Note8
Note8
48E0
8D EO
9800
48E0
4F00
4F3 1
7500
9100
5000
5032
5 100
7600
5133
Note9
Note9
Note9
Notel'
Not e l o Note"
Notel'
3920
3920
3920
3920
n0te8
n0te8
n0te6
n0te6
n0te6
n0te9
KEYBOARD SCAN CODES
Key
Hardware Kybrd
Make
Break
Kybrd Interrupt
Make
Break
€&Code
Cade-CLodc
#
Key
Descript.
95
96
97
98
99
100
101
102
EO11
Right Alt
E014
Right Ctrl
Left Arrow
E06B
Down Arrow E072
Right Arrow E074
Oor Ins
70
. o r Del
71
Enter
E05A
EOFOl I
EOF014
EOF06B
EOF072
EOF074
F070
F07 1
EOFOSA
~
E 038
EOID
E02AE04B
E02AE050
E024E04D
52
53
EOlC
E OB8
E09D
EOCBEOAA
EODOEOAA
EOCDEOAA
D2
D3
E09C
Standard ASCII
(Scancode/ASCII code)
Norm - Shift
C l r I- Alt
Note'
Notcl'
4800
5000
4D00
5200
5300
lCOD
Notel'
Note9
4B00
5000
4000
5230
5328
lCOD
Note:'
Notc
7300
----7400
----
Extended ASCII
(Scancodc/ASCII code)
Norm
Notc1°
Note'
-----------Note
----
----
1COA
----
6
Note'
4BE0
50EO
4DE0
5200
5300
EOOD
--
Sbft-~
__CtrI
Note"
Notc9
4BE0
50EO
4DEO
523H
532E
EOOD
-
Note1()
Notc9
73E0
91EO
74E0
9200
9300
EOOA
Ab
10
Notc 9
Notc
9800
A000
9D00,
Note
----A600
NOTES
Note1
Note2
Note3
Note4
Note5
Note6
Note7
Note8
Note9
Note l
+NT
05H is invoked and a screen dump is performed
--the scroll lock active bit is toggled
--the pause state is initiated
-1NT
1BH is invoked
--the numlock active bit is toggled
-ALT
num pad generates raw ascii code of typed number
- - t h e caps lock active bit is toggled
+old
shift lock active u n t i l key is released
- - h o l d control shift active until key is released
H o l d altcrnate shift active until key is released
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