Aiwa XD-DV370 Service Manual
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XD-DV370
HR(N) EZ(N, B) K(N)
U(B)
<HR(N)> <Except for HR(N)>
SERVICE MANUAL
DP2[6721R-0308A](HR/K/U)
DVD PLAYER BASIC DVD/CD MECHANISM :
DP3[6721R-0309A](EZ)
If requiring information about the ELECTRICAL ADJUSTMENT & MECHANSIM
ADJUSTMENT & MECHANISM PARTS LOCATION <EZ> & MECHANISM DISASSEMBLY
<EZ> & FL GRID ASSINGMENT/ANODE CONNECTION/PIN CONNECTION.
see Supplement Service manual of XD-DV370(HR/U/K/EZ) (S/M Code No. 09-00C-349-9S1)
S/M Code No. 09-009-349-9N1
DA
TA
TABLE OF CONTENTS
SPECIFICATIONS ........................................................................................................................................................................... 3
PROTECTION OF EYES FROM LASER BEAM DURING SERVING ............................................................................................ 4
ACCESSORIES LIST ...................................................................................................................................................................... 5
DISASSEMBLY INSTRUCTIONS ............................................................................................................................................. 6 ~ 7
ELECTRICAL MAIN PARTS LIST ........................................................................................................................................... 8 ~ 10
TRANSISTOR ILLUSTRATION ..................................................................................................................................................... 11
BLOCK DIAGRAM - 1 (OVERALL) <HR> ..................................................................................................................................... 12
BLOCK DIAGRAM - 2 (OVERALL) <Except HR> ......................................................................................................................... 13
BLOCK DIAGRAM - 3 (POWER) <U> .......................................................................................................................................... 14
BLOCK DIAGRAM - 4 (POWER) <Except U> .............................................................................................................................. 15
BLOCK DIAGRAM - 5 (RF/CD DSP/DVD SERVO) ...................................................................................................................... 16
BLOCK DIAGRAM - 6 (AUDIO) .................................................................................................................................................... 17
BLOCK DIAGRAM - 7 (MPEG) <HR> ........................................................................................................................................... 18
BLOCK DIAGRAM - 8 (MPEG) <Except HR> ............................................................................................................................... 19
BLOCK DIAGRAM - 9 (µ-COM) .................................................................................................................................................... 20
BLOCK DIAGRAM - 10 (KARAOKE) <HR> .................................................................................................................................. 21
WIRE HARNESS DIAGRAM ......................................................................................................................................................... 22
SCHEMATIC DIAGRAM - 1 (MAIN - 1/5, AUDIO SECTION) ........................................................................................................ 23
SCHEMATIC DIAGRAM - 2 (MAIN - 2/5, DRIVE & RF SECTION) ............................................................................................... 24
SCHEMATIC DIAGRAM - 3 (MAIN - 3/5, DVD DSP SECTION) ................................................................................................... 25
SCHEMATIC DIAGRAM - 4 (MAIN - 4/5, MPEG SECTION) <HR> .............................................................................................. 26
SCHEMATIC DIAGRAM - 5 (MAIN - 4/5, MPEG SECTION) <Except HR> .................................................................................. 27
SCHEMATIC DIAGRAM - 6 (MAIN - 5/5, MAIN µ-COM SECTION) ............................................................................................. 28
SCHEMATIC DIAGRAM - 7 (INTERFACE - 1/3, TIMER SECTION) (KEY1, KEY2 SECTION) <HR> ......................................... 31
SCHEMATIC DIAGRAM - 8 (INTERFACE - 1/3, TIMER SECTION) (KEY1, KEY2 SECTION) <Except HR> ............................. 32
SCHEMATIC DIAGRAM - 9 (INTERFACE - 2/3, JACK SECTION) <HR> ................................................................................... 33
SCHEMATIC DIAGRAM - 10 (INTERFACE - 2/3, JACK SECTION) <U> .................................................................................... 34
SCHEMATIC DIAGRAM - 11 (INTERFACE - 2/3, JACK SECTION) <EZ, K> ............................................................................... 35
SCHEMATIC DIAGRAM - 12 (INTERFACE - 3/3, POWER SECTION) <U> ................................................................................ 36
SCHEMATIC DIAGRAM - 13 (INTERFACE - 3/3, POWER SECTION) <Except U> .................................................................... 37
WIRING - 1 (MAIN C.B) <HR> ...................................................................................................................................................... 29
WIRING - 2 (MAIN C.B) <Except HR> .......................................................................................................................................... 30
WIRING - 3 (INTERFACE C.B) <HR> ........................................................................................................................................... 38
WIRING - 4 (INTERFACE C.B) <U> ............................................................................................................................................. 39
WIRING - 5 (INTERFACE C.B) <EZ, K> ....................................................................................................................................... 40
WIRING - 6 (KEY1, KEY2 C.B) ..................................................................................................................................................... 41
WAVEFORMS ....................................................................................................................................................................... 42 ~ 43
IC BLOCK DIAGRAM ............................................................................................................................................................ 44 ~ 45
IC DESCRIPTION ................................................................................................................................................................. 46 ~ 67
MECHANICAL EXPLODED VIEW 1/1 .......................................................................................................................................... 68
MECHANICAL MAIN PARTS LIST 1/1 ......................................................................................................................................... 69
COLOR NAME TABLE .................................................................................................................................................................. 70
DVD MECHANISM EXPLODED VIEW 1/1 ................................................................................................................................... 71
DVD MECHANISM MAIN PARTS LIST 1/1 ................................................................................................................................... 72
ELECTRICAL TROUBLESHOOTING GUIDE ....................................................................................................................... 73 ~ 83
DVD MECHANISM PARTS LOCATION <Except EZ> .................................................................................................................. 84
DVD MECHANISM DISASSEMBLY <Except EZ> ................................................................................................................ 85 ~ 87
-2-
SPECIFICATIONS
<HR, EZ, K MODELS>
Power supply 110 - 240 V AC, 50/60 Hz <HR, EZ>
230 V AC, 50 Hz <K>
Power consumption 16 W
Weight 3.2 kg
External dimensions 430
×
88
×
245 mm (w
×
h
×
d)
Laser Semicounductor laser,
Signal format
Supported discs wave length 650/750 nm
PAL/NTSC
DVD video discs
12 cm (single-sided single-layer, single-sided double-layer, double-sided-double layer)
8 cm (single-sided single-layer, single-sided double-layer, double-sided-double layer)
S video output
Video output
Compact discs (CD-DA, video CD)
12 cm and 8 cm discs
Y output: 1 Vp-p (75 ohms, sync negative)
C output: 0.286 Vp-p
1 Mini DIN 4 pin
Video composite output
1 Vp-p (75 ohms, sync negative)
1 RCA jack
1 Scart connector
Video component output <HR>
Y output: 1 Vp-p (75 ohms, sync negative)
1 RCA jack
P
B
,P
R
output: 0.7 Vp-p (75 ohms)
1 RCA jacks (P
B
,P
R
)
Audio output Digital output
0.5 Vp-p (75 ohms)
1 Fiber optical connector
1 RCA jack
Analogue output
2.0 Vr ms (1kHz, 0dB, 330 ohms)
1 RCA jacks (L/R)
Audio output characteristics
Signal to noise ratio
More than 105 dB (EIAJ)
Dynamic range
More than 95 dB (EIAJ)
Harmonic distortion
0.003%
Frequency range:
CD / VCD: 2 Hz to 20 kHz
DVD: 2Hz to 22kHz (48kHz sampling)
2Hz to 44kHz (96kHz sampling)
Wow and flutter: unmeasurable
Operating conditions
Design and specifications are subject to change without notice.
<U MODEL>
Power supply 120 V AC, 60 Hz
Power consumption 16 W
Weight 3.2 kg (7.1 lbs)
External dimensions 430
×
88
×
245 mm (w
×
h
×
d)
(17
×
3.5
×
9.9 inches)
Signal format NTSC
Supported discs DVD video discs
12 cm (single-sided single-layer, single-sided double-layer,
S video output double-sided-double layer)
8 cm (single-sided single-layer, single-sided double-layer, double-sided-double layer)
Compact discs (CD-DA, video CD)
12 cm and 8 cm discs
Y output: 1 Vp-p (75 ohms, sync
Video output
Audio output negative)
C output: 0.286 Vp-p
1 Mini Din 4 pin
Video composite output
1 Vp-p (75 ohms, sync negative)
1 RCA jack
Video component output
Y output: 1 Vp-p (75 ohms, sync negative)
1 RCA jack
P
B
,P
R
output: 0.7 Vp-p (75 ohms)
1 RCA jacks (P
B
,P
R
)
Digital output
0.5 Vp-p (75 ohms)
1 Fiber optical connector
Analog output
2.0 Vr ms (1kHz, 0dB, 330 ohms)
2 RCA jacks (L/R)
Audio output characteristics
Signal to noise ratio
More than 105 dB (EIAJ)
Dynamic range
More than 95 dB (EIAJ)
Harmonic distortion
0.003%
Frequency range:
CD / VCD: 2 Hz to 20 kHz
DVD: 2Hz to 22kHz (48kHz sampling)
2Hz to 44kHz (96kHz sampling)
Wow and flutter: unmeasurable
Operating conditions
Spatializer¤ 3-D Stereo, Spatializer N-2-2 (TM) and the circle-in-square device are trademarks owned by Desper Products, Inc,.
Manufactured under license from Dolby
Laboratories. Dolby , Pro Logic and the double-
D symbol are trademarks of Dolby Laboratories.
Confidential unpublished works. c1992-1997 Dolby
Laboratories. All rights reserved.
Manufactured under license from Digital Theater
Systems, Ino. US Pat. No. 5,451,942 and other worldwide patents issued and pending. DTS and
DTS Digital Surround are trademarks of Digital
Theater Systems, Inc. c1996 Digital Theater systems, Ino. All rights reserved.
-3-
PROTECTION OF EYES FROM LASER BEAM DURING SERVICING
This set employs laser. Therefore, be sure to follow carefully the instructions below when servicing.
WARNING!
WHEN SERVICING, DO NOT APPROACH THE LASER
EXIT WITH THE EYE TOO CLOSELY. IN CASE IT IS
NECESSARY TO CONFIRM LASER BEAM EMISSION.
BE SURE TO OBSERVE FROM A DISTANCE OF MORE
THAN 30cm FROM THE SURFACE OF THE OBJECTIVE
LENS ON THE OPTICAL PICK-UP BLOCK.
Caution: Invisible laser radiation when open and interlocks defeated avoid exposure to beam.
Advarsel:
CAUTION
Use of controls or adjustments or performance of procedures other than those specified herin may result in hazardous radiation exposure.
ATTENTION
ADVARSEL!
This Compact Disc player is classified as a CLASS 1
LASER product.
The CLASS 1 LASER PRODUCT label is located on the rear exterior.
VAROITUS!
VARNING!
CLASS 1
KLASSE 1
LUOKAN 1
KLASS 1
LASER PRODUCT
LASER PRODUKT
LASER LAITE
LASER APPARAT
(SPU3140)
Solder short for
CD laser diode
Solder short for
DVD laser diode
Precaution to replace Optical block
Body or clothes electrostatic potential could ruin laser diode in the optical block. Be sure ground body and workbench, and use care the clothes do not touch the diode.
1) After the connection, remove solder shown in the figures below.
-4-
ACCESSORIES LIST
REF. NO PART NO.
KANRI
NO.
DESCRIPTION
1 S8-35R-S00-12X INSTRUCTION ASSY<HRN>
1 S8-35R-S00-12W INSTRUCTION ASSY<UB>
1 S8-35R-S00-12V INSTRUCTION ASSY<KN>
1 S8-35R-S00-12Z INSTRUCTION ASSY<EZB,EZN>
2 S7-11R-2N0-13F REMOTE CONTROLLER ASSY<HRN>
2 S7-11R-2N0-13D REMOTE CONTROLLER ASSY<UB,EZB>
2 S7-11R-2N0-13E REMOTE CONTROLLER ASSY<KN,EZN>
3 S5-640-17B-000 PLUG ASSY PHONE CORD 1WAY
3 S5-640-18B-000 PLUG ASSY PHONO CORD
-5-
DISASSEMBLY -1/2
CABINET DISASSEMBLY
1. Top Case
1. Release 7 screws (A). (See Fig. 2-1)
2. Lift the top case with holding the back of it, and remove it in the direction of the arrow
Top Case
(A)
(A) (A)
(A)
(A)
(A)
(A)
3. Front Panel
1. Eject the disc tray. (See Fig. 2-2)
2. Remove the tray door. (See Fig. 2-2)
3. Release 2 screws (B).
4. Pull the front panel toward you while pressing
7 stoppers to disengage, and remove the front panel. (See Fig. 2-3)
(B)
(B)
Stopper
Stopper
Fig. 2-1
Front Panel
Fig. 2-3
2. Tray Door
1.Eject the disc tray.
2.Lift up the tray door in the direction of the arrow.
Tray Door
Disc Tray
Fig. 2-2
-6-
DISASSEMBLY -2/2
CIRCUIT BOARD DISASSEMBLY
1. Disassembling of Main Circuit Board and Interface Board 2. Key1 and Key2 Circuit Board
1. Remove the top case.(See Fig. 2-1)
2. Remove 12 screw (C).
3. Remove FF-cable (PMD02, PMD04), and remove the DVD MECHANISM.
4. Remove 2 connector (P3901, P5901) and remove Main Circuit Board from Interface Board.
5. Remove 2 screw (D).
6. Remove Interface Board from the chassis.
1. Remove the front panel.(See Fig. 2-3)
2. Release 4 screws (E), and remove the Key1, 2 circuit board.
(E)
(C)
(C)
(C)
(C)
DVD Mechansm
Key1
Circuit Board
(E)
(E)
(E)
Fig. 2-5
Key2
Circuit Board
Power Code
(D)
(D)
Interface
Board
PMD02
(C)
(C)
(C)
PMD04
P5901
(C)
Main Cir
P
(C)
(C) (C)
(C)
Fig. 2-4
-7-
ELECTRICAL MAIN PARTS LIST - 1/3
REF. NO PART NO.
KANRI
NO.
DESCRIPTION
IC
!
SI-SK6-153-00A IC,STR-G6153T 5P<EXCEPT U>
S2-309-024-040 SENSORLTV-817B PHOTO COU
SI-SS4-310-00A IC,KA431AZ
SI-SS7-808-00H IC,KA78R08 4P
SI-SH3-130-00B IC,PQ3RD13
SI-HY2-580-10B IC,GDC25D801C
SI-JR3-414-00C IC,NJM3414AM-TE1,3K/REEL
87-017-856-080 IC,TC4W53FU
SI-GL4-411-64A IC,GLT441L16-40
SI-TI3-337-21A IC,SSI33P3721
SI-FA3-032-00A IC,KA3032
SI-CU3-000-00A IC,ZIVA3-PE0<HR>
SI-CU4-100-00A IC,ZIVA4.1<EXCEPT HR>
SI-GS7-216-16C ICGM72V161621ET-7
SI-BB1-700-00A IC,PLL1700E 20P
SI-PH7-128-00A IC,SAA7128<HR>
87-A21-254-040 IC,BA7660FS<HR>
SI-SH2-050-00A IC,PQ20WZ5U 20WZ51
SI-SA7-135-00A IC,LA7135A<EXCEPT HR>
SI-BB1-716-00A IC,PCM1716E 28P
SI-JR4-580-00B IC,NJM4580M
SI-TO7-040-00F IC,TC7W04FU
SI-CB5-331-00A IC,CS5331A-KS<HR>
SI-HI6-417-03B IC,HD6417034AFI20
SI-AL4-981-92B IC,AT49F8192A-90TC
SI-MQ5-316-25A IC,V53C16256HK50
SI-SS2-402-10A IC,KS24C021CS
SI-TI7-437-40K IC,SN74AHC374PWLE
SI-XL9-536-15B IC,XC9536-15VQ44C-PROG
SI-RH3-308-00A IC,BA3308<HR>
SI-KE4-558-00A IC,KIA4558P<HR>
SI-SA8-661-12C IC,LC866112B-5N21
87-001-196-010 IC,KIA7042P
TRANSISTOR
ST-R44-190-0AA TR,KTC4419<U>
ST-R31-980-9AC TR,KTC3198-TP-BL
ST-R11-510-0AA TR,KSB1151-Y
ST-R10-370-9BB C-TR,2SA1037K-Q
87-A30-273-040 TR,DTC124EK
89-324-122-080 TR,2SC2412KR
ST-R15-040-9BF TR,KTA1504S-Y<EXCEPT HR>
ST-R15-050-9AD TR,KTA1505S-Y
ST-R10-000-9BM TR,UMZ1N 3K
87-026-609-080 TR,KTA1266-GR
ST-R10-300-9AE TR,KRC103M<K,EZ>
ST-R10-500-9AB TR,KRC105M
ST-R10-500-9AD TR,KRA105M
DIODE
87-A40-284-080 DIODE,ERA22-10<EXCEPT U>
SD-D22-060-9AA DIODE,ERA22-06<U>
SD-D01-000-9AC DIODE,EU01W
87-020-465-080 DIODE,1SS133
SD-R10-400-9AB DIODE,RL104
87-017-352-010 DIODE,RU3YXLF-C1 100V2
SD-R18-020-9AA DIODE,ERA18-02KFRB
SD-R10-451-0AA DIODE,B10A45V1
SD-R15-402-0BA DIODE,1N5402
SD-R10-400-0AA DIODE,RZ1040<U>
87-020-331-080 DIODE,DAN202K
MAIN C.B
C232 SC-H71-06C-611 C-CAP,10UF-6.3V
C271 SC-H71-06C-611 C-CAP,10UF-6.3V
-8-
REF. NO PART NO.
KANRI
NO.
DESCRIPTION
C272 SC-H84-76C-611 C-CAP,47UF-6.3V
C274 SC-H84-76C-611 C-CAP,47UF-6.3V
C275 SC-H71-06C-611 C-CAP,10UF-6.3V
C276 SC-H71-06C-611 C-CAP,10UF-6.3V
C278 SC-H71-06C-611 C-CAP,10UF-6.3V
C279 SC-H71-06C-611 C-CAP,10UF-6.3V
C280 SC-H71-06C-611 C-CAP,10UF-6.3V
C281 SC-H71-06C-611 C-CAP,10UF-6.3V
C284 SC-H84-76C-611 C-CAP,47UF-6.3V
C2D1 SC-H84-76C-611 C-CAP,47UF-6.3V
C2D2 SC-H84-76C-611 C-CAP,47UF-6.3V
C2D3 SC-H84-76C-611 C-CAP,47UF-6.3V
C2D4 SC-H84-76C-611 C-CAP,47UF-6.3V
C2D5 SC-H71-06C-611 C-CAP,10UF-6.3V
C2M1 SC-H81-07F-611 C-CAP,100UF-16V
C340 SC-H71-06C-611 C-CAP,10UF-6.3V
C361 SC-H81-07F-611 C-CAP,100UF-16V<HR>
C362 87-A12-114-080 C-CAP,TN 22UF-6.3V<HR>
C363 SC-H81-07F-611 C-CAP,100UF-16V<HR>
C364 87-A12-114-080 C-CAP,TN 22UF-6.3V<HR>
C367 SC-H81-07F-611 C-CAP,100UF-16V<HR>
C368 87-A12-114-080 C-CAP,TN 22UF-6.3V<HR>
C369 SC-H81-07F-611 C-CAP,100UF-16V<HR>
C370 87-A12-114-080 C-CAP,TN 22UF-6.3V<HR>
C371 SC-H81-07F-611 C-CAP,100UF-16V<HR>
C372 87-A12-114-080 C-CAP,TN 22UF-6.3V<HR>
C375 SC-H81-07F-611 C-CAP,100UF-16V<EXCEPT HR>
C382 SC-H84-76C-611 C-CAP,47UF-6.3V<EXCEPT HR>
C383 SC-H84-76C-611 C-CAP,47UF-6.3V<EXCEPT HR>
C384 SC-H84-76C-611 C-CAP,47UF-6.3V<EXCEPT HR>
C406 SC-H81-07F-611 C-CAP,100UF-16V
C407 SC-H84-76C-611 C-CAP,47UF-6.3V
C409 SC-H84-76C-611 C-CAP,47UF-6.3V
C410 SC-H84-76C-611 C-CAP,47UF-6.3V
C419 SC-H84-76C-611 C-CAP,47UF-6.3V
C421 SC-H84-76C-611 C-CAP,47UF-6.3V
C429 SC-H81-07F-611 C-CAP,100UF-16V
C430 SC-H81-07F-611 C-CAP,100UF-16V
C536 SC-H71-06F-621 C-CAP,10UF-16V
L201 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L202 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L203 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L204 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L207 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L208 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L211 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L2A1 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L2A2 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L301 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L302 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L303 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L304 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L305 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L306 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L307 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L308 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L309 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT<HR>
L371 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT<EXCEPT HR>
L401 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L402 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L4M1 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT<HR>
L501 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L502 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L503 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L505 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L506 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
L507 S2-00H-JC1-02A CER,FILTER HB-1M2012-102JT
P3901 S6-30R-BE0-340 CONN,BOAR2254-30S-T
P5502 S6-30H-XC1-15A CONN,04-6232-115-008-800
P5901 S6-30R-BE0-340 CONN,BOAR2254-30S-T
ELECTRICAL MAIN PARTS LIST - 2/3
REF. NO PART NO.
KANRI
NO.
DESCRIPTION
PMD02 S6-30R-FB0-2W0 CONN,04-6232-123-008-80
PMD03 S6-30R-FB0-2H0 CONN,04-6232-108-008-800
PMD04 S6-30R-3S0-06F CONN,5P
X301 S2-02R-BL0-1A0 X'TAL,HC-49/SM5H
X501 S2-12S-AML-CB0 RESONATOR CSTCV20.00MXJ040-TC
INTERFACE C.B
BC101 S6-360-04C-000 COIL,BFS3550R2FD8<EXCEPT U>
BD101 87-070-173-010 DIODE,S1WBA60
C100 87-010-408-040 CAP,E 47UF-50V<EXCEPT U>
!
C101 S6-240-88F-000 CAP,PCX2 275V 0.1UF,M
!
C102 S6-240-88F-000 CAP,PCX2 275V 0.1UF,M<EXCEPT U>
!
C103
!
C103
!
C105
SC-E10-7CT-610 CAP,100UF-350V<U>
SC-E68-6CU-611 CAP,E 68UF-400V<EXCEPT U>
87-016-375-010 CAP,0.01UF-630V
!
C106 S6-240-87B-000 CAP,100P-1KV
C111 87-010-403-040 CAP,E 3.3-50V<U>
!
C114
!
C114
87-012-379-010 CAP,3300PF-400V<EXCEPT U>
S6-240-86B-000 CAP,103-400V<U>
C116 87-010-387-010 CAP,E 470UF-25V KME
C118 87-010-112-080 CAP,E 100-16V
C119 87-010-408-040 CAP,E 47UF-50V
!
C120 S6-240-86B-000 CAP,103-400V<U>
C121 SC-E22-76F-638 CAP,E 220UF-16V
!
C122 SC-G33-10U-510 CAP,CER 330PF-400V<EXCEPT U>
C123 87-010-237-910 CAP,E 1000UF-16V
C124 87-010-237-910 CAP,E 1000UF-16V
C125 87-010-375-080 CAP,E 330-10V
C126 87-010-387-010 CAP,E 470UF-25V KME
C127 87-010-408-080 CAP,E 47-50V
C129 SC-E47-7CD-638 CAP,E 470UF-10V
C130 87-010-112-080 CAP,E 100-16V
C131 87-010-112-080 CAP,E 100-16V
C134 87-010-112-080 CAP,E 100-16V
C137 SC-E47-7CD-638 CAP,E 470UF-10V
C140 SC-E47-7CD-638 CAP,E 470UF-10V
C601 87-010-378-080 CAP,E 10-16V<EXCEPT HR>
C602 SC-E47-7CD-638 CAP,E 470UF-10V<EXCEPT HR>
C603 SC-E47-7CD-638 CAP,E 470UF-10V<EXCEPT HR>
C604 87-010-380-080 CAP,E 47-16V<K,EZ>
C663 SC-E47-7CD-638 CAP,E 470UF-10V<K,EZ>
C6Z1 SC-E47-7CD-638 CAP,E 470UF-10V<U>
C6Z2 SC-E47-7CD-638 CAP,E 470UF-10V<U>
C6Z3 SC-E47-7CD-638 CAP,E 470UF-10V<U>
C6Z4 SC-E47-7CD-638 CAP,E 470UF-10V<K,EZ>
C6Z5 SC-E47-7CD-638 CAP,E 470UF-10V<K,EZ>
C6Z6 SC-E47-7CD-638 CAP,E 470UF-10V<K,EZ>
C801 87-010-378-080 CAP,E 10-16V<HR>
C802 87-010-112-080 CAP,E 100-16V<HR>
C803 87-010-378-080 CAP,E 10-16V<HR>
C804 87-010-378-080 CAP,E 10-16V<HR>
C806 87-010-112-080 CAP,E 100-16V<HR>
C807 87-010-378-080 CAP,E 10-16V<HR>
C810 87-010-378-080 CAP,E 10-16V<HR>
C812 87-010-378-080 CAP,E 10-16V<HR>
C813 87-010-380-080 CAP,E 47-16V<HR>
C814 87-010-378-080 CAP,E 10-16V<HR>
C818 87-010-380-080 CAP,E 47-16V<HR>
C824 87-010-378-080 CAP,E 10-16V<HR>
C902 87-010-378-080 CAP,E 10-16V
C906 87-010-408-080 CAP,E 47-50V
C907 87-010-378-080 CAP,E 10-16V
C912 87-010-380-080 CAP,E 47-16V
C913 87-010-380-080 CAP,E 47-16V
C914 87-010-380-080 CAP,E 47-16V
DIG901 S3-02R-V10-3A0 DIGITRON 7-BT-273GN
!
F101 S5-850-11T-000 FUSE,1600MA 250V<EXCEPT U>
!
F101
!
F102
S5-850-27B-000 FUSE,1600MA 250V<U>
87-001-196-010 ICP-N10 T104<EXCEPT U>
-9-
REF. NO PART NO.
KANRI
NO.
DESCRIPTION
F602 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<EXCEPT HR>
F603 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF
F604 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF
F605 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<EXCEPT HR>
F606 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<EXCEPT HR>
F607 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<EXCEPT HR>
F608 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<U>
F609 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<U>
F610 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<U>
F611 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<K,EZ>
F612 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<EXCEPT HR>
F613 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<EXCEPT HR>
F614 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<K,EZ>
F615 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<K,EZ>
F616 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<K,EZ>
F617 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<K,EZ>
F618 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<K,EZ>
F619 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<K,EZ>
F620 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<K,EZ>
F621 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<K,EZ>
F622 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<K,EZ>
F801 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<HR>
F802 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<HR>
F803 S2-00H-JC9-01A SAM,FILTER CFI06B1H101MF<HR>
!
FH101 S5-860-08B-000 HOLDER,FUSE CLIP
!
FH102 S5-860-08B-000 HOLDER,FUSE CLIP
JK601 S6-12R-L00-1A0 TOTX178 HORIZONTA JK
JK602 S6-12R-C00-6G0 JACK,RCA<HR,U>
JK602 S6-12R-C00-6H0 JACK,RCA<K,EZ>
JK603 S6-20R-M00-02B SOCKET 1F-21P<K,EZ>
!
L101 S6-161-45E-000 FILTER KSE-145E<U>
L101 S6-161-45H-000 FILTER SHT LFS2020V4-04350<EXCEPT U>
L102 S6-330-88G-000 COIL,CHOCK TP 5MM
L103 S6-330-88D-000 COIL,20UH
L602 87-005-208-080 COIL,100<K,EZ>
L902 87-005-208-080 COIL,100
LED901 SD-L32-531-9AA LED SPR325MVWT31(GRN)
MJ801 S6-12R-B00-3A0 JACK,HEADPHONE<HR>
MJ802 S6-12R-B00-3A0 JACK,HEADPHONE<HR>
P6401 S6-30R-BE0-240 CONN,BOAR2254-30P-T
P9501 S6-30R-BE0-240 CONN,BOAR2254-30P-T
P9902 S5-617-11D-000 CONN,GIL-S-04P-S2T2-EF
P9904 S5-617-11L-000 CONN,12P
!
PW101 S5-612-92B-000 GP390 LGC 3P STRAIG P
!
R101 S6-140-07A-000 RES,CEM 2.7/2W
!
R102
!
R104
SR-S10-03K-619 RES,100K-2W<EXCEPT U>
SR-S33-02K-619 RES,M/F 33K-2W<U>
!
R104 SR-S56-02K-619 RES,56K-2W<EXCEPT U>
R110 SR-S12-00J-619 RES,M/F 120-1W<U>
!
R111 SR-S01-01K-619 RES,1-2W<U>
!
R111 SR-S05-10K-619 RES,0.51-2W<EXCEPT U>
R122 SR-S12-00J-619 RES,M/F 120-1W
R144 SR-S12-00J-619 RES,M/F 120-1W<U>
RC901 S7-12R-193-8GA REMOTE CONTROLLER RECEI
SW601 S6-00R-SH0-3A0 SW,SLIDE SKQ-23D15-G3-NA<EXCEPT U>
!
T101
!
T101
S6-420-21G-000 KSE-021G KWANG SUNG NARRO<U>
S6-420-23T-000 PT,SHT-023T/KSE-023T<EXCEPT U>
!
V101 S6-560-04C-000 V SVC681D-10A
VR801 S1-10R-RK0-3A0 VOLUME,ROTARY 20KB<HR>
VR802 S1-10R-RK0-3A0 VOLUME,ROTARY 20KB<HR>
VR803 S1-10R-RK0-3A0 VOLUME,ROTARY 20KB<HR>
X901 S6-160-20P-000 CSA6.00MGU MURATA 6MHZ
ZD101 SD-Z56-260-9AA ZENER,GDZJ5.6B 26MM TP
ZD102 SD-Z62-000-9BC ZENER,MTZJ6.2B<U>
ZD605 SD-Z56-260-9AA ZENER,GDZJ5.6B 26MM TP<EXCEPT HR>
ZD606 SD-Z56-260-9AA ZENER,GDZJ5.6B 26MM TP<EXCEPT HR>
ZD635 SD-Z56-260-9AA ZENER,GDZJ5.6B 26MM TP
ZD636 SD-Z56-260-9AA ZENER,GDZJ5.6B 26MM TP
ZD637 SD-Z56-260-9AA ZENER,GDZJ5.6B 26MM TP
ZD638 SD-Z56-260-9AA ZENER,GDZJ5.6B 26MM TP
ELECTRICAL MAIN PARTS LIST - 3/3
REF. NO PART NO.
KANRI
NO.
DESCRIPTION
ZD639 SD-Z56-260-9AA ZENER,GDZJ5.6B 26MM TP<K,EZ>
ZD640 SD-Z56-260-9AA ZENER,GDZJ5.6B 26MM TP<K,EZ>
KEY1 C.B
P9901 S5-636-02R-000 CONN,4P
SW901 S5-562-19B-000 SW,SKHV10910B
KEY2 C.B
P9903 S5-636-02S-000 CONN,12P
SW902 S5-562-19B-000 SW,SKHV10910B
SW903 S5-562-19B-000 SW,SKHV10910B
SW904 S5-562-19B-000 SW,SKHV10910B
SW905 S5-562-19B-000 SW,SKHV10910B
SW906 S5-562-19B-000 SW,SKHV10910B
SW907 S5-562-19B-000 SW,SKHV10910B
SW908 S5-562-19B-000 SW,SKHV10910B
SW910 S5-562-19B-000 SW,SKHV10910B
SW911 S5-562-19B-000 SW,SKHV10910B
SW912 S5-562-19B-000 SW,SKHV10910B
SW913 S5-562-19B-000 SW,SKHV10910B
SW914 S5-562-19B-000 SW,SKHV10910B
• Regarding connectors, they are not stocked as they are not the initial order items.
The connectors are available after they are supplied from connector manufacturers upon the order is received.
CHIP RESISTOR PART CODE
Chip Resistor Part Coding
8 8
A
Resistor Code
Figure
Value of resistor
Chip resistor
Wattage
1/16W
1/16W
1/10W
1/8W
Type
1005
1608
2125
3216
Tolerance
5%
5%
5%
5%
Symbol
CJ
CJ
CJ
CJ
Form
L
W
Dimensions (mm)
L W t
1.0
0.5
0.35
t 1.6
0.8
0.45
2 1.25
0.45
3.2
1.6
0.55
: A
Resistor Code : A
104
108
118
128
-10-
TRANSISTOR ILLUSTRATION
E C B
KTA1266
KTC3198
E C B
KTA1015
KTC103
KTC1015
B C E
KTC4419
E1
B1
C2
C1
B2
E2
UMZ1N 3K
E C B
KSB1151
C
B
E
2SA1037
2SC2412
DTC124EK
KTA1504
KTA1505
-11-
DISC
CD,DVD:A,B,C,D,E,F
SPINDLE
MOTOR
M
PICK
UP
Focus, tracking sled
LOADING
MOTOR
M spindle loading
OPEN S/W
CLOSE S/W
LIMIT S/W
AC100-
240V,
50~
60Hz
CD DECK MECHANISM
INTERFACE
BOARD
(POWER
SECTION)
VF+
VF-
-24V
8V
5.2VA
5V_A
5V_D
3.3V_M
3.3V
2.5V
8V
A.GND,D.NGD,M.GND
FL DISPLAY
IC901
LC866112B
-5N21
IC2A1
SSI33P3721
RF Signal
Processor
IC2M1
KA3032
Motor Driver loading drive
MIRR,TZC
FE,TE,RFRP,SBADD,DVD/CD RF
TEBAL,FEBAL,
DPOCTL,EQF,EQB
MON,SPINDLE_DRV
FDO,TDO,
FMO
SPINDLE_FG
IC201
IC205
GLT441L16
DRAM
256K x 16bit
GDC25D801C
CD/DVD DSP
DVD SERVO
IC302
GM72V161621ET-7
1M x 16bit
SDRAM
DVD_LDQM,DVD_SD,CSI
DVD_MA[0:11]
DVD_MD[0:15]
DVD_SD_CAS,
DVD_SD_RAS
DVD_SD_CLK
DVD_MWE
IC303
GM72V161621ET-7
1M x 16bit
SDRAM
DVD_DATA[0:7]
SDCLKI, ZISENB
REQZI
DVD_SD_CSO,
DVD_UDQM
3.38688MHz
SENS,FOK,MIRR
MSDATO,DEFECT,DSP_SENSE,
SQSO,SQCK,SCOR,AO[0:5]
XLAT,S_CLK,S_DATA,DO[0:7]
DA_DATA,
DA_LRCK,
DA_BCK
DA_XCK
IC301
ZiVA3-P
MPEG A/V
Decoder
D[00:07]
A[00:02]
POWER CONTROL
IC501
HD6417034AFI20
MAIN u-COM
RC901
TSOP2838WE1
REMOCON
RECEIVER
S_CLK,S_DATA,
DPLL_L
IIC_DATA,
IIC_CLK
IC304
PLL1700E
CLOCK
GENERATROR
27MHz
X-TAL
DA_DATA,
DA_LRCK,
DA_BCK
DAC_LO,
S_CLK,
S_DATA
IC401
PCM1716E
AUDIO
DAC
L/R
IC305
SAA7128
VIDEO
Encoder
CVBS,
Y,C
Y(G),
Pb(B)
Pr(R)
IC306/307
BA7660FS
6dB AMP
CVBS,Y,C
Y(G)Pb(B),Pr(R)
AMP
L/R
CVBS
Y
C
Y(G) Pb(B) Pr(R)
KEY Input
VIDEO
OUT
AUDIO
OUT
DISC
CD,DVD:A,B,C,D,E,F
SPINDLE
MOTOR
M
PICK
UP
Focus, tracking sled
LOADING
MOTOR
M spindle loading
OPEN S/W
CLOSE S/W
LIMIT S/W
AC100-
240V,
50~
60Hz
CD DECK MECHANISM
INTERFACE
BOARD
(POWER
SECTION)
VF+
VF-
-24V
8V
5.2VA
5V_A
5V_D
3.3V_M
3.3V
2.5V
8V
A.GND,D.NGD,M.GND
FL DISPLAY
IC901
LC866112B
-5N21
IC2A1
SSI33P3721
RF Signal
Processor
IC2M1
KA3032
Motor Driver loading drive
MIRR,TZC
FE,TE,RFRP,SBADD,DVD/CD RF
TEBAL,FEBAL,
DPOCTL,EQF,EQB
MON,SPINDLE_DRV
FDO,TDO,
FMO
SPINDLE_FG
IC201
IC205
GLT441L16
DRAM
256K x 16bit
GDC25D801C
CD/DVD DSP
DVD SERVO
IC302
GM72V161621ET-7
1M x 16bit
SDRAM
DVD_LDQM,DVD_SD,CSI
DVD_MA[0:11]
DVD_MD[0:15]
DVD_SD_CAS,
DVD_SD_RAS
DVD_SD_CLK
DVD_MWE
DVD_DATA[0:7]
SDCLKI, ZISENB
REQZI
IC303
GM72V161621ET-7
1M x 16bit
SDRAM
DVD_SD_CSO,
DVD_UDQM
3.38688MHz
SENS,FOK,MIRR
MSDATO,DEFECT,DSP_SENSE,
SQSO,SQCK,SCOR,AO[0:5]
XLAT,S_CLK,S_DATA,DO[0:7]
DA_DATA,
DA_LRCK,
DA_BCK
DA_XCK
IC301
ZiVA4.1
MPEG A/V
Decoder
Y(G)
Pr(C,R)
Pb(B)
D[00:07]
A[00:02]
POWER CONTROL
IC501
HD6417034AFI20
MAIN u-COM
S_CLK,S_DATA,
DPLL_L
IIC_DATA,
IIC_CLK
IC304
PLL1700E
CLOCK
GENERATROR
27MHz
X-TAL
DA_DATA,
DA_LRCK,
DA_BCK
RC901
TSOP2838WE1
REMOCON
RECEIVER
DAC_LO,
S_CLK,
S_DATA
IC401
PCM1716E
AUDIO
DAC
L/R
IC372
LA7135A
Switch IC
AMP
L/R
CVBS
Y
C
Y(G) Pb(B) Pr(R)
KEY Input
VIDEO
OUT
AUDIO
OUT
AC INPUT
3,4
2
1
5,7
RECTIFIER(FLD)
D107,D108
9
RECTIFIER(14V)
D110
LPF
C120,C127,
L102
13 RECTIFIER(9V)
D106
LPF
C116
11
RECTIFIER(5.2V)
D109
LPF
C124,C125,
L103
REG(8V)
IC105
KA78R08
Q107
D114
FEED B.
IC108
LTV-817B
D113
REG(3.3V)
IC106
PQ3RD13
REG(3.3V)
IC107
PQ3RD13
PWR CTL
VF+
VF-
-24VA
12VA
8V
5.2VA
5V_D
5V_A
2.5V
3.3V
3.3V_M
AC INPUT
3,4
2
1
5,7
RECTIFIER(FLD)
D107,D108
9
RECTIFIER(14V)
D110
LPF
C120,C127,
L102
13 RECTIFIER(9V)
D106
LPF
C116
11
RECTIFIER(5.2V)
D109
LPF
C124,C125,
L103
REG(8V)
IC105
KA78R08
Q107
D114
FEED B.
IC102
LTV-817B
D113
REG(3.3V)
IC106
PQ3RD13
REG(3.3V)
IC107
PQ3RD13
PWR CTL
VF+
VF-
-24VA
12VA
8V
5.2VA
5V_D
5V_A
2.5V
3.3V
3.3V_M
PICK
UP
DVD:A,B,C,D,
CD:A,B,C,D/E,F
4
6
11-16
IC2A1
SSI33P3721
RF Signal
Processdr
19,
36,
41,
42
57
29,
39
FE,TE,PI,SBADD 4
DVD/CD RF
MIRR,TZC
2
70,78,
131,132,
134
114,118 99,
101,
102,
103
162
129,
130
166,
168
83,
84,
88
80-82
IC201 175-177
GDC25D801C
CD/DVD DSP
DVD SERVO
30
170
5
2
3
3
8
6
8
SENS,FOK,
MSDATO,DEFECT,DSP_SENSE
SQSO,SQCK
XLAT,S_CLK,S_DATA
DSP_CS,/WR,/RD
DO[0:7]
AO[0:5]
DVD_DATA[0:7]
MCK
To
MAIN u-COM
SECTION
To
MPEG
SECTION
M/D
Spindle
IC2M1
KA3032
SpindleMotor,LoadingMotor,
Actuator Driver focus,tracking,loading,sled
MON,MDP
FDO,TDO,FMO
IC205
DRAM
256K x 16bit
SPINDLE_FG
Load open/close(loading control)
To
MAIN u-COM
SECTION
To
MAIN u-COM
SECTION
DAC_RST
S_DATA
S_CLK
DAC_L0
To
MPEG
SECTION
DA_LRCK
DA_BCK
DA_XCK
DA_DATA0
27
28
22
26
1
3
5
2
IC401
PCM1716E
Audio DAC
L
18
R
13
2
6
IC402
LPF &Buffer
NJM4580M
OP AMP
1
7
L
R
To
JACK
SECTION
To
DVD DSP
SECTION
DVD_DATA[0:7]
SDCLK1,ZISENB
REQZ1
To
MAIN u-COM
SECTION
A[00:02]
D[00:07]
MPEG_ERROR
MPEG_RST
8
2
3
8
171
192,
196
191
161
3,166,
167
IC301
ZiVA3-P
MPEG A/V
Decoder
159
157,
158
200
13
82,84,
85,86 90 80
DVD_LDQM
DVD_SD_CS0
16 12
DVD_MD[0:15]
DVD_MA[0:11]
DVD_UDQM
4
14 18 36
IC302
GM72V161621ET-7
1M x 16bit
SDRAM 15-17,35
DVD_SD_CAS
DVD_SD_RAS
DVD_SD_CLK
DVD_MWE
36 18 14
15-17,35
IC303
GM72V161621ET-7
1M x 16bit
SDRAM
169
88 79
177
2
2
HSYNC,VSYNC
VDATA[0:7]
8
DA_XCK
MPEG_CLK
DAI_DATA
DA_DATA0
DA_BCK,DA_XCK,DA_LRCK
SPDIF
7,8
IC305
SAA7128
NTSC/PAL
Encoder
30
CVBS
27
Y
24
C
Y
29
Pb
Pr
23
40 41,42
2
2
4
7
IC306
BA7660FS
6dB AMP
15
3
10
CVBS
Y
C
4
2
7
IC307
BA7660FS
6dB AMP
15
3
10
Y
Pb
Pr
DAC_RST
11 17
IC304
PLL1700E
CLOCK
GENERATROR
1,19,20
12
5 6
X301
27MHz
X-TAL
S_CLK,S_DATA,DPLL_L
MCK
3
To
AUDIO
SECTION
To
JACK
SECTION
To
MAIN u-COM
SECTION
To
DVD DSP
SECTION
To
DVD DSP
SECTION
DVD_DATA[0:7]
SDCLK1,ZISENB
REQZ1
To
MAIN u-COM
SECTION
A[00:02]
D[00:07]
MPEG_ERROR
MPEG_RST
3
8
8
2
161
171,
173
122,126
172
174
5
78,90,
91,94 95
IC301
ZiVA4.1
MPEG A/V
Decoder
127
133
139
145
151
125
96 77
159
2
DA_XCK
MPEG_CLK
DVD_LDQM
DVD_SD_CS0
DVD_MD[0:15]
DVD_MA[0:11]
16 12
4
14,36 18
IC302
GM72V161621ET-7
1M x 16bit
SDRAM 15-17,35
DVD_SD_CAS
DVD_SD_RAS
DVD_SD_CLK
DVD_MWE
18 14,36
15-17,35
IC303
GM72V161621ET-7
1M x 16bit
SDRAM
DA_DATA0
DA_BCK,DA_XCK,DA_LRCK
CVBS
SPDIF
CVBS/G/Y
Y/B/U
C/R/V
3
10
6
15
19
IC372
LA7135A
SwitchIC
21
13
17
1,2
CVBS
Y
C
Y(G)
PB(B)
PR(R)
Y.SEL
11 17
IC304
PLL1700E
CLOCK
GENERATROR
1,19,20
12
5 6
X301
27MHz
X-TAL
S_CLK,S_DATA,DPLL_L
MCK
3
To
JACK
SECTION
To
MAIN u-COM
SECTION
To
DVD DSP
SECTION
To
AUDIO
SECTION
MPEG_ERROR
,DAC_L0
,RF_LAT
,/DSP_CS
,/MPEG_CS
,/PP_CS 16:9,
,Y_SEL
,,MPEG_RST
8
To
JACK
SECTION
To
MPEG
SECTION
10
/PWR_CTL
,SENS,LIMIT_SW
,MIC_ON,CLOSE_SW
,OPEN_SW,MPEG_WAIT
,/WR,/IOCS1,
,M_RESET
To
TIMER
SECTION
8
M_RESET
,RXD0
,TXD0
,SCK0
,F_REQ
,MODE_SW
,M_REQ,
,ECHO
16:9,SYSTEM_SW
IC506
XC9536
D[00:07],A[00:02],IIC_CLK,IIC_DATA,SCLK, MPEG_RST
,MPEG_INT,V_MUTE,DAC_RST,Y_SEL
IC504
EEPROM
KS24C02KS
IIC_CLK
,IIC_DATA 2
SENS_MCOM
, MICOM_WAIT
2
/IOCS1,/WR
2
A[19:21]
D[00:04]
3
5
IC501
HD6417034AFI20
A[01:22] 22
A[01:20]
20
16
D[00:15]
IC502
AT49F8192A
FLASH
ROM
LD_ON,LOAD CLOSE,MIRR,ACT_MUTE
LOAD_OPEN,SPINDLE_FG
D[00:07],A[00:05], ,E_SIN,E_CLK
LOCK,DEFECT,FOK,DSP_SENSE,
16 D[00:15]
A[01:09]
9
16
D[00:15]
IC503
V53C16256HK
DRAM
To
DRIVE & RF
SECTION
To
DVD DSP
SECTION
8
D[00:07]
8
IC505
SN74AHC374P
DAC_RST
,E_DR
,/S_XRST
,XLAT
,ACT_MUTE
,LOAD_OPEN
,LOAD CLOSE
,/PWR_RST
EXP_W2
,/PWR_CTL
2
MJ801
MIC1
MJ801
MIC1
Microphone
Signal
PREAMP
IC801
BA3308
AMP
IC802
KIA4558
AUDIO
ADC
IC4M1
CS5331A-KS
MPEG
IC301
ZIVA3-P
DVD DSP
IC201
GDC25D801C
AUDIO
DAC
IC401
PCM1716E
WIRE HARNESS DIAGRAM
P3901
DOWNLOAD
JIG
KEY 1 C.B
KEY 2 C.B
INTERFACE
C.B
16:9
ECH_VOL
MIC_ON
P5901
MAIN C.B
DVD MECHA.
PICK UP CB
DVD MECHA.
LOADING
MOTOR C.B
DVD MECHA.
SPINDLE
MOTOR C.B
-22-
SCHEMATIC DIAGRAM - 1 (MAIN -1/5, AUDIO SECTION)
MAIN-1/5 (AUDIO SECTION) C.B
(3/3)
(3/3)
(3/3)
HB-1M2012-102JT
PQ20WZ5U
HB-1M2012-102JT
100UF/16V
47UF/6.3V
47UF/6.3V
47UF/6.3V
47UF/6.3V
(1/3)
(1/3)
(1/3)
(2/3)
(2/3)
(2/3)
<HRJNK>
CS5331A-KS
HB-1M2012-102JT
E1
E2
E3
E4
E5
E6
E7
E8
To
MAIN-5/5
(MAIN u-COM)
E1-E8
D17
D1
D2
D5
D3
D9
D10
D11
D6
D7
D8
D4
D12
D13
D14
D15
D16
D18
D19
<HRJNK>
L2
L3
L1
R3
R8
To
MAIN-4/5
(MPEG)
D1-D19
To
MPEG
SECTION
L1-L3
To
MAIN-5/5
(MAIN u-COM)
R3,R8
AUDIO L SIGNAL
AUDIO R SIGNAL
-23-
SCHEMATIC DIAGRAM - 2 (MAIN -2/5, DRIVE & RF SECTION)
To
DVD MECHA.
PICK UP CB
To
MAIN-5/5
(MAIN u-COM)
R1-R3,R5,R8
R2
R1
R8
R3
R5
MAIN-2/5 (DRIVE & RF SECTION) C.B
HB-1M2012-102JT (3/3)
7.5K
5.6K
MOTOR DRIVE
To
MAIN-5/5
(MAIN u-COM)
H1-H7
To
MAIN-3/5
(DVD DSP)
G1-G7
H1
H2
H3
H7
G2
G3
G4
G5
G6
H4
H5
H6
G7
G1
DTC124EK
DTC124EK
(1/3)
TRACKING LOOP
FOCUS LOOP
SLED LOOP
SPINDLE LOOP
WAVEFORM
To
DVD MECHA.
LOADING
MOTOR C.B
To
DVD MECHA.
SPINDLE
MOTOR C.B
-24-
-TE1
4
1 6
SSI33P3721
RF SIGNAL
PROCESSOR
2 3
1
G19
H11
H12
H13
To
MAIN-3/5
(DVD DSP)
G19
To
MAIN-5/5
(MAIN u-COM)
H11-H13
G8
H8
H9
G14
G15
G16
G9
G10
G11
G12
G13
To
MAIN-3/5
(DVD DSP)
G8-G13
To
MAIN-5/5
(MAIN u-COM)
H8,H9
To
MAIN-3/5
(DVD DSP)
G14-G18
G17
G18
H10
To
MAIN-5/5
(MAIN u-COM)
H10
SCHEMATIC DIAGRAM - 3 (MAIN -3/5, DVD DSP SECTION)
MAIN-3/5 (DVD DSP SECTION) C.B
IC205
GLT441L16
DRAM
VCC
VCC GND
NC
NC
NC
NC
VCC
GND
10UF/6.3V
To
MAIN-5/5
(MAIN u-COM)
R5,R7,R8
R5
R8
R7
(3/3)
5
IC201
GDC25D801C
CD/DVD DSP
DVD SERVO
(4/4)
6 5
(2/3)
(2/4)
(1/3)
(2/3)
F24
F25
F26
F27
F28
F29
F30
F17
F18
F19
F20
F21
F22
F23
F31
F32
F33
F34
F35
F36
F37
F9
F10
F11
F12
F13
F14
F15
F16
F5
F6
F7
F8
F1
F2
F3
F4
To
MAIN-5/5
(MAIN u-COM)
F1-F37
G10
G16
G9
G17
G11
G15
G12
G19
G3
G18
G1
G2
G4
G13
G6
G7
G5
G8
G14
To
MAIN-2/5
(DRIVE & RF)
G1-G19
* L201-L204,L207,L208,L211
HB-1M2012-102JT
(1/3)
(3/3)
K8
K9
K10
K11
K3
K12
K2
K1
K4
K5
K6
K7
To
MAIN-4/5
(MPEG)
K1-K12
TRACKING LOOP
FOCUS LOOP
SLED LOOP
SPINDLE LOOP
WAVEFORM
-25-
SCHEMATIC DIAGRAM - 4 (MAIN -4/5, MPEG SECTION) <HR>
MAIN-4/5 (MPEG SECTION) C.B <HR>
To
INTERFACE-1/3 C.B
(JACK)
P6401
SDRAM
ET-7
ZIVA3-P
MPEG A/V
DECODER
WAVEFORM * L301-L309
HB-1M2012-102JT
SDRAM
ET-7
5
(2/3)
6
8
1
7
2
9
VIDEO
ENCODER
11 4
1
10
3
27MHz
CLOCK
GEN.
DPLL_L
MODE
VDD
GND
XT2
XT1
GND
VDDP
RSV
MCKO
S_CLK
S_DATA
MICOM_RESET
DA_XCK
VDDB
GNDB
SCK02
SCK04
MCK
MPEG_CLK
2SC2412
2SC2412
2SC2412
2SC2412
(3/3)
(1/3)
(3/3)
(3/3)
C17
C18
C25
C20
C21
C12
C13
C14
C15
C16
C22
C19
C23
C24
C26
C27
C5
C6
C7
C8
C9
C10
C11
C1
C2
C3
C4
L1
L2
L3
R4
R6
R8
R7
(3/3)
D12
D13
D14
D15
D16
D18
D19
D17
D5
D6
D7
D8
D9
D10
D11
D1
D2
D3
D4
K6
K7
K8
K9
K10
K11
K12
K1
K2
K3
K4
K5
To
MAIN-3/5
(DVD DSP)
K1-K12
To
MAIN-1/5
(AUDIO)
D1-D19
To
MAIN-5/5
(MAIN u-COM)
C1-C27
To
MAIN-1/5
(AUDIO)
L1-L3
To
MAIN-5/5
(MAIN u-COM)
R4,R6-R8
-26-
SCHEMATIC DIAGRAM - 5 (MAIN -4/5, MPEG SECTION) <Except HR>
MAIN-4/5 (MPEG SECTION) C.B <U, K, EZ>
To
INTERFACE-1/3 C.B
(JACK)
P6401
1%
SDRAM
ET-7
MPEG A/V
DECODER
SDRAM
ET-7
27MHz
CLOCK
GEN.
(1/3)
(2/3)
(2/3)
(2/3)
(3/3)
6.3V
6.3V
SWITCH
A
6.3V
MPEG_CLK
2SC2412KR
(BR)
*
L301-L308,L371
HB-1M2012-102JT
DPLL_L
MODE
VDD
GND
S_CLK
S_DATA
MICOM_RESET
DA_XCK
XT2
XT1
GND
VDDP
RSV
MCKO
VDDB
GNDB
SCK02
SCK04
MCK
MPEG_CLK
S
-27-
2SC2412KR
(BR)
(3/3)
(3/3)
D8
D9
D10
D11
D12
D1
D2
D3
D4
D5
D6
D7
D13
D14
D15
D16
D17
K5
K6
K7
K8
K9
K1
K2
K3
K4
K10
K11
K12
(1/3)
C5
C6
C7
C8
C1
C2
C3
C4
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
(3/3)
(3/3)
R4
R6
R8
R7
L1
L2
L3
To
MAIN-3/5
(DVD DSP)
K1-K12
To
MAIN-1/5
(AUDIO)
D1-D17
To
MAIN-5/5
(MAIN u-COM)
C1-C24
To
MAIN-1/5
(AUDIO)
L1-L3
To
MAIN-5/5
(MAIN u-COM)
R4,R6-R8
SCHEMATIC DIAGRAM - 6 (MAIN -5/5, MAIN
µ
-COM SECTION)
To
MAIN-2/5
(DRIVE & RF)
H1-H13
To
MAIN-3/5
(DVD DSP)
F1-F37
To
MAIN-4/5
(MPEG)
C1-C27
To
MAIN-1/5
(AUDIO)
E1-E8
C24
C1
C20
DAC_RST
C21
C25
IIC_CLK
IIC_DATA
C26
C27
C23
C2
C17
C18
C16
C6
C19
C22
C7
C9
C10
C11
C12
C13
C14
C15
C3
C4
C5
C8
<HRJNK>
E6
E1
E4
E5
E3
E2
E7
E8
F7
F18
F27
F30
F22
F1
F16
F17
F5
F6
F19
F21
F20
F28
F26
H7
H8
H9
H11
H12
H13
H6
H3
H2
H4
H5
H1
H10
F35
F2
F3
F4
F8
F9
F10
F11
F12
F13
F14
F15
F23
F24
F37
F32
F33
F34
F31
F29
F25
F36
(1/5)
(1/5)
(1/4)
(1/6)
(2/5)
(2/5)
(4/4)
(3/5)
(3/5)
(3/3) DAC_RST
(1/3) IIC_CLK
(1/3)
IIC_DATA
(2/3)
(4/5)
(4/5)
MAIN-5/5 (MAIN u-COM SECTION) C.B
(2/6)
AT49F8192A
FLASH ROM
HD6417034AFI20
MAIN u-COM
* L501-L503,L505-L507
HB-1M2012-102JT
DRAM
50
(4/6)
(3/4)
KS24C021CS
EEPROM
(2/3)
(2/3)
(1/3)
EXPANDER
(4/4)
(6/6)
(5/5)
(5/5)
(3/3)
(3/3)
<UBK,KNK,EZBK/EZNK>
R507 0
R508 0
CPLD
(2/4)
(1/4)
-28-
C536
10
µ
/16V
R1
R2
R3
R4
R5
R6
R7
R8
DOWNLOAD
JIG
To
MAIN-1/5~4/5
(AUDIO,
DRIVE & RF,
DVD DSP,
MPEG)
R1-R8
To
INTERFACE-1/3 C.B
(TIMER)
P9501
WIRING - 1 (MAIN C.B) <HR>
32 31 30 29 28 27
MAIN C.B <HR>
26 25 24 23 22 21 20 19 18 17
P3901
To
INTERFACE C.B
P6401
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
8 5
1 4
1
4
8
5
8 5
1 4
B
E
C
B
E
C
B
E
C
B
E
C
8
10
5
1
8
1
5
4
6 4
1 3
5
1
15
14 10
9
6
5
2
1
B
C
E
8
B
C
E
5
1 4
C
E
B
P5502
DOWN LOAD
JIG
P5901
To
INTERFACE C.B
P9501
-29-
PMD04
To
DVD MECHA.
LOADING
MOTOR C.B
23
22
21
18
17
14
13
10
9
6
5
2
1
1
4
8
5
8
7
2
1
C
E
B
PMD02
To
DVD MECHA.
PICK UP C.B
PMD03
To
DVD MECHA.
SPINDLE
MOTOR C.B
5
8
4
1
C
E
B
P
Q
N
O
R
L
M
J
K
S
T
U
G
H
E
F
I
C
D
A
B
WIRING - 2 (MAIN C.B) <Except HR>
32 31 30 29 28 27
MAIN C.B <U, K, EZ>
26 25 24 23 22 21 20 19 18
P3901
To
INTERFACE C.B
P6401
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
50 45 35 26
5 15 25
40 35 30 25 21
28 20 15
1 10 14
1
12
24
13
B
C
E
B
E
C
B
E
C
B
E
C
B
C
E
B
C
E
B
E
C
B
E
C
8
1
5
6 4
4
1 3
1 5 10 15 20
23
22
8
5
1 4
12
11
24 20 10 1
33
34
44
1
25 35 4548
8 5
1 4
1
48
37
36
5
1
15
14 10
9
6
5
12
13
24
25
B
C
E
8
B
C
E
5
2
1
C
E
B
1 4
P5502
DOWN LOAD
JIG
P5901
To
INTERFACE C.B
P9501
PMD04
To
DVD MECHA.
LOADING
MOTOR C.B
-30-
5
1
5
1
10
9
6
5
2
1
23
22
21
18
17
14
13
1
4
8
7
2
1
C
E
B
55 49
1
64
10
16
17
8
5
E B
C
32
33
48
40
PMD02
To
DVD MECHA.
PICK UP C.B
PMD03
To
DVD MECHA.
SPINDLE
MOTOR C.B
56
85
5
8
4
1
C
E
B
29
52
105
112
104
26 30 40 50
53
157
25 20 10 1
156
208
P
Q
N
O
R
L
M
J
K
S
T
U
G
H
E
F
I
C
D
A
B
SCHEMATIC DIAGRAM - 7 (INTERFACE - 1/3, TIMER SECTION) (KEY1, KEY2 SECTION) <HR>
INTERFACE-2/3 (TIMER SECTION) C.B <HR>
KEY2 C.B
SW904
STOP
SW903
PLAY
SW902
OPEN/CLOSE
KEY1 C.B
STANDBY/ON
SW908
SW907
MENU
SW906
/
SW905
/
SW911
SW912
SW913 SW914
SW910
ENTER
RESET
To
INTERFACE-2/3
(JACK)
B1-B10
TSOP2838WE1
REMOCON
RECEIVER
(2/3)
LC866112B-5N21
FRONT CONTROL
(4/4)
MIC 1
MIC 2
To
MAIN-5/5 C.B
(MAIN u-COM)
P5901
* T/W:JUMPER WIRE
MF
MF
PREAMP
MF
MIC 1
VOL
MIC 2
VOL
AMP
P
1.8K
22K
DIGITAL
ECHO
-31-
7-BT-273GN
(3/4)
(1/3)
A9
A7
A12
A5
A10
A16
A14
A13
A15
A8
A6
A17
A1
A2
A4
A3
A11
To
INTERFACE-3/3
(POWER)
A1-A17
SCHEMATIC DIAGRAM - 8 (INTERFACE - 1/3, TIMER SECTION) (KEY1, KEY2 SECTION) <Except HR>
INTERFACE-1/3 (TIMER SECTION) C.B <U, K, EZ>
KEY2 C.B
SW904
STOP
SW903
PLAY
SW902
OPEN/CLOSE
KEY1 C.B
STANDBY/ON
SW908
SW907
MENU
SW906
/
SW905
/
SW911
SW912
SW913 SW914
SW910
ENTER
LC866112B-5N21
FRONT CONTROL
RESET
To
INTERFACE-2/3
(JACK)
B1-B10
TSOP2838WE1
REMOCON
RECEIVER
(2/3)
To
MAIN-5/5 C.B
(MAIN u-COM)
P5901
(4/4)
-32-
7-BT-273GN
(3/4)
(1/3)
A12
A5
A10
A6
A17
A16
A14
A13
A15
A8
A9
A7
A1
A2
A4
A3
A11
To
INTERFACE-3/3
(POWER)
A1-A17
SCHEMATIC DIAGRAM - 9 (INTERFACE -2/3, JACK SECTION) <HR>
INTERFACE-2/3 (JACK SECTION) C.B <HR>
JK602
VIDEO
OUT
(
DIGITAL
OUT
)
(
DIGITAL
OUT
)
S-VIDEO
OUT
4
1
3
2
R
AUDIO
OUT
L Y
COMPONENT
VIDEO OUT
Pr Pb R
AUDIO
OUT2
L
R622
22
R6M2 R6M1
(1/3)
(1/3)
To
MAIN-4/5 C.B
(MPEG)
P3901
C608
0.047UF
D603
T/W
D604
T/W
To
INTERFACE-1/3
(TIMER)
B1-B10
B9
B10
B5
B6
B7
B8
B1
B2
B3
B4
KTA1266-GR
* T/W:JUMPER WIRE
OPTICAL
COMP.VIDEO
S VIDEO (Y)
KTC3198
KTC3198
S VIDEO (C)
AUDIO (L)
AUDIO (R)
-33-
SCHEMATIC DIAGRAM - 10 (INTERFACE -2/3, JACK SECTION) <U>
INTERFACE-2/3 (JACK SECTION) C.B <U>
JK602
VIDEO
OUT
R
AUDIO
OUT
L
(
DIGITAL
OUT
)
(
DIGITAL
OUT
)
S-VIDEO
OUT
4 3
1 2
Y
COMPONENT
VIDEO OUT
Pr Pb R
AUDIO
OUT2
L
R622
22
R6M2
R6M1
470U/10V
(1/3)
(1/3)
To
MAIN-4/5 C.B
(MPEG)
P3901
C608
0.047UF
D603
T/W
D604
T/W
KTC3198
To
INTERFACE-1/3
(TIMER)
B1-B10
B5
B6
B7
B8
B1
B2
B3
B4
B9
B10
KTA1266-GR
* T/W:JUMPER WIRE
OPTICAL
COMP.VIDEO
S VIDEO (Y)
KTC3198
S VIDEO (C)
AUDIO (L)
AUDIO (R)
-34-
470U/10V
T/W
SCHEMATIC DIAGRAM - 11 (INTERFACE -2/3, JACK SECTION) <K, EZ>
INTERFACE-2/3 (JACK SECTION) C.B <K, EZ>
(
DIGITAL
OUT
)
(
DIGITAL
OUT
)
S-VIDEO
OUT
4 3
1 2
JK602
VIDEO
OUT
R
AUDIO
OUT
L
R622
22
(2/3)
To
MAIN-4/5 C.B
(MPEG)
P3901
To
INTERFACE-1/3
(TIMER)
B1-B10
B9
B10
B5
B6
B7
B8
B1
B2
B3
B4
(1/3)
KTA1266-GR
C608
0.047UF
D603
T/W
D604
T/W
* T/W:JUMPER WIRE
OPTICAL
COMP.VIDEO
S VIDEO (Y)
KTC3198
KTC3198
S VIDEO (C)
AUDIO (L)
AUDIO (R)
470U/10V
-35-
470U/10V
KTA1266-GR
100U
47U/16V 0.01UF
680
680
100
KTA1266-GR
100
KTA1266-GR
To
21PIN SCART
CONNECTOR
C6Z5
470U/10V
C6Z6
470U/10V
C6Z4
470U/10V
470U/10V
SCHEMATIC DIAGRAM - 12 (INTERFACE -3/3, POWER SECTION) <U>
INTERFACE-3/3 (POWER SECTION) C.B <U>
350V
275V
-10A
1W
TRANS
-02
-02
-01
LTV-817B
3
1
2
AC INPUT
8V REG
GDZJ5.6B
GDZJ6.2B
PQ3RD13
3.3V REG
-Y
PQ3RD13
3.3V REG
(T/W)
470 /10V
A1
A2
A3
A4
A10
A11
A12
A13
A14
A15
A5
A6
A7
A8
A9
A16
A17
To
NTERFACE-1/3
(TIMER)
A1-A17
-36-
NOTES) Warning
NOTES) Parts that are shaded are critical
NOTES) With respect to risk of fire or
NOTES) electricial shock.
* T/W:JUMPER WIRE
SCHEMATIC DIAGRAM - 13 (INTERFACE -3/3, POWER SECTION) <Except U>
INTERFACE-3/3 (POWER SECTION) C.B <HR, K, EZ>
TRANS
275V
275V
-10A
400V
(1/2W)
DRIVE &
OVER CURRENT LIMIT
AC INPUT
-02
-C1
LTV-817B
3
1
2
GDZJ5.6B
8V REG
PQ3RD13
3.3V REG
-Y
PQ3RD13
3.3V REG
A1
A2
A3
A4
A10
A11
A12
A13
A14
A15
A5
A6
A7
A8
A9
A16
A17
To
NTERFACE-1/3
(TIMER)
A1-A17
NOTES) Warning
NOTES) Parts that are shaded are critical
NOTES) With respect to risk of fire or
NOTES) electricial shock.
* T/W:JUMPER WIRE
-37-
WIRING - 3 (INTERFACE C.B) <HR>
32 31 30 29 28 27
JK601
DIGITAL
OUT
INTERFACE C.B
<HR>
1 3
26 25 24 23 22
S-VIDEO
OUT
21
DIGITAL
OUT
4
1
3
2
20 19 18
AUDIO
OUT2
R
L
COMPONENT
VIDEO OUT
Y
Pr
Pb
17 16 15 14
VIDEO
OUT
R
L
AUDIO
OUT
PAL
SW601
NTSC AUTO
13 12 11 10 9
1 3
1
3
P6401
To
MAIN C.B
P3901
2
6
10
14
9
13
1
5
18 17
22 21
26 25
30 29
P9501
To
MAIN C.B
P5901
2
6
10
14
9
13
18 17
1
5
22 21
26 25
30 29
3
1
E
C
B
E
C
B
E
C
B
1
3
B
C
E
1
B
C
E
4
3
1
3 4
2 1
1 4
B
C
E
8 7
AC INPUT
6 5 4 3 2 1
1 4 1 4
B
C
E
1
3
1
2
3
4
5
1 2 3 4
13 11 9 7 5
1
3
3
2
1
3
2
1
P
Q
N
O
R
L
M
J
K
S
T
U
G
H
E
F
I
C
D
A
B
P9904
To
KEY2 C.B
P9903
RC901
(REMOCON RECEIVE)
* T/W:JUMPER WIRE DIG901
(DIGTRON)
-38-
P9902
To
KEY1 C.B
P9901
VR803
DIGITAL
ECHO
VR802
MIC 2
VOL
VR801
MIC 1
VOL
MJ802
MIC 2
MJ801
MIC 1
WIRING - 4 (INTERFACE C.B) <U>
32 31 30 29 28 27
JK601
DIGITAL
OUT
INTERFACE C.B <U>
1 3
26 25 24 23 22
S-VIDEO
OUT
21
DIGITAL
OUT
4
1
3
2
20
AUDIO
OUT2
R
L
19 18
COMPONENT
VIDEO OUT
Y
Pr
Pb
17 16
VIDEO
OUT
R
AUDIO
OUT
L
15 14 13 12 11 10 9
1
3
1 3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
P6401
To
MAIN C.B
P3901
2
6
10
14
9
13
18 17
1
5
22 21
26 25
30 29
P9501
To
MAIN C.B
P5901
2
6
10
14
9
13
1
5
18 17
22 21
26 25
30 29
3
1
E
C
B
E
C
B
E
C
B
B
C
E
1
B
C
E
4
3
1
1 4
B
C
E
8 7
AC INPUT
6 5 4 3 2 1
3 4
2 1
E
C
B
1 4 1 4
B
C
E
1 2
E C B
T/W
3 4
13 11 9 7 5
T/W
T/W
P
Q
N
O
R
L
M
J
K
S
T
U
G
H
E
F
I
C
D
A
B
P9904
To
KEY2 C.B
P9903
RC901
(REMOCON RECEIVE)
* T/W:JUMPER WIRE
DIG901
(DIGTRON)
-39-
WIRING - 5 (INTERFACE C.B) <K, EZ>
32 31 30 29 28 27 26 25 24 23
JK601
DIGITAL
OUT
INTERFACE C.B
<K, EZ>
1 3
1
3
1
3
JK603
To
21PIN SCART
CONNECTOR
22 21
S-VIDEO
OUT
DIGITAL
OUT
4
1
3
2
20 19 18 17 16 15 14
VIDEO
OUT
R
L
AUDIO
OUT
PAL
SW601
NTSC AUTO
13 12 11 10
P6401
To
MAIN C.B
P3901
2 1
6 5
10 9
14 13
18 17
22 21
26 25
30 29
1
3
1
3
1
3
1
3
1
3
1 3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
E
C
B
E
C
B
B
C
E
E
C
B
E
C
B
E
C
B
1
3
1
3
1
3
E
C
B
E
C
B
3
1
9
3 4
2 1
8 7
AC INPUT
6 5
2
1 3
4
5
1 2 3 4
4 3 2 1
13 11 9 7 5
P9501
To
MAIN C.B
P5901
2
6
1
5
10 9
14 13
18 17
22 21
26 25
30 29
3
1
B
C
E
1
B
C
E
4
1 4
B
C
E
1 4 1 4
B
C
E
P
Q
N
O
R
L
M
J
K
S
T
U
G
H
E
F
I
C
D
A
B
P9904
To
KEY2 C.B
P9903
RC901
(REMOCON RECEIVE)
* T/W:JUMPER WIRE DIG901
(DIGTRON)
-40-
P9902
To
KEY1 C.B
P9901
WIRING - 6 (KEY1, KEY2 C.B)
15 14 13 12 11 10 9
KEY2 C.B
SW911
KEY1 C.B
SW912
SW910
SW914
SW901
POWER
SW913
SW911
SW912
SW910
ENTER
SW914
SW913
8
LED901
STANDBY/ON
4 1
To
INTERFACE C.B
P9902
SW906
7 6
SW905
SW907 SW908
SW906
/
SW907
MENU
SW904
STOP
SW905
/
SW908
5 4
SW904
To
INTERFACE C.B
P9904
12
SW903
SW903
PLAY
3 2 1
SW902
Q
SW902
OPEN/CLOSE
R
O
P
M
N
K
L
I
J
S
T
U
G
H
E
F
C
D
A
B
-41-
WAVEFORMS - 1/2
IC305 (VIDEO ENCODER)
1 IC305 Pins 9 ~ 16 MPEG Data
1.0V/500µs
T
2 IC305 Pin30 Composite
500mV/20µs
3 IC305 Pin24 Chrominance
500mV/20µs
M 500 s CH1 280/mV
Ch3 1.00V
4 IC305 Pin27 Luminance
500mV/20µs
5 IC305 Pins 40,41 SDA/SCL
1.0V/25ms
T
7 IC305 Pin7 Vertical SYNC
1.0V/5ms
T
6 IC305 Pin4 MPEG Clock (27MHz)
1.0V/500µs
T
8 IC305 Pin8 Horizontal SYNC
1.0V/20µs
T
M 500 s CH1 280/mV
Ch3 1.00V
9 IC305 Pin29 Component Pb
500mV/20µs
Ch3 1.00V
M 5 .00ms CH1 280/mV
Ch3 1.00V
10 IC305 Pin23 Component Pr
500mV/20µs
11
M 20.0 s CH1 280/mV
IC305 Pin27 Component Y
500mV/20µs
-42-
WAVEFORMS - 2/2
IC2A1, IC201 (RF/SERVO)
1 IC2A1 Pin24 Focus Error
IC2A1 Pin36 Pi
500mV/5ms
2 IC2A1 Pin41 Tracing Error
500mV/2ms
3 IC2A1 Pin41 VBR Tracking Error
500mV/300µs
4 IC2A1 Pin57 RF
0.5V/0.1µs
5 IC201 Pin88 SLED Driver (FMO)
IC201 Pin18 SLED FG
A: 2.0V/500ms, B: 500mV/500ms
A
6 IC2A1 Pin42 Focus Error(in Focus Search)
IC201 Pin83 Focus Drive (FDO)
A: 200mV/100ms, B: 500mV/100ms
A
B B
-43-
IC BLOCK DIAGRAM - 1/2
IC, PCM1716E
BCKIN 3
LRCIN
DIN
1
2
Serial
Input
I/F
ML/IIS 28
MC/DM1
MD/DM0
27
26
CS/IWO
MODE
MUTE
RST
23
24
25
22
Mode
Control
I/F
8X Oversampling
Digital Filter with
Function
Controller
Enhanced
Multi-level
Delta-Sigma
Modulator
20 19 9 10
DAC
Low-pass
Filter
DAC
Low-pass
Filter
SCK
5
XTI
Crystal/OSC
6
XTO
BPZ-Cont.
Open Drain
Power Supply
4
CLKO
15 14 8
V
CC1
AGND1 V
DD
7
DGND
16
18
V
OUT
L
EXTL
13 V
OUT
R
11 EXTR
21 ZERO
IC, PQ20WZ5U
IN 1
Vc 2
3 OUT
Specilic IC
5
GND
4 V
ADJ
IC, TC4W53FU
VDD
8
A 5
INH 2
4
VSS
3
VEE
OUT IN
C
1 COMMON
7 CH0
OUT IN
C
6 CH1
IC, GLT441L16-40
OE 27
WE 13
UCAS
LCAS
28
29
RAS 14
16
ICADDR0~
ICADDR8
22
26
V
SS
V
SS
V
SS
21
35
40
V
CC
V
CC
V
CC
1
6
20
Timing
Generator
Column
Address
Buffers
Internal
Address
Counter
Row
Address
Buffers
Refresh
Control
Clock
Column Decoders
Sense Amps
Memory Cells
I/O Controller I/O Controller
I/O Selector
Output
Buffer
Input
Buffer
Output
Buffer
Input
Buffer
2
7
ICDATAO0~
ICDATAO7
10
31
36
ICDATAO8~
ICDATAO15
39
-44-
IC BLOCK DIAGRAM - 2/2
IC, PLL1700E
RST 18 Reset
MODE
14
ML
1
MC
20
MD
19
V
DDP
3
GNDP V
DDB
2 8
GNDB
7
V
DD
16
GND
15
Power Supply Mode
Control
I/F
PLL2
XT1 5
XT2 6
OSC PLL1
Counter Q Counter P
12 11
MCKO MCKO
17
SCKO1
9
SCKO2
10
SCKO3
13
SCKO4
IC, XC9536_15VQ44C-PROG
JTAG Port
I/O
I/O
I/O
I/O
I/O/GCK
I/O/GSR
I/O/GTS
I/O
I/O
I/O
I/O
3
1
2
1
3
JTAG
Controller
I/O
Blocks
In-System Programming Controller
18
54
18
18
18
54
54
54
Function
Block 1
Macrocells
1 to 18
Function
Block 2
Macrocells
1 to 18
Function
Block 3
Macrocells
1 to 18
Function
Block 4
Macrocells
1 to 18
-45-
10
15
16
17
18
11
12
13
14
19
20
21
22
23
24
25
26
27
28
29
30
31
CN
F
E
CDTE
CEIN
B
A
D
C
CE1
VNB
DVDRD
DVDLD
CDPD
CDLD
___________
LDON
VC
VCI
VPB
MIRR
MP
MB
______________
FDCHG
IC DESCRIPTION - 1/11 (SSI33P3721)-1/2
Pin No.
3
4
1
2
5
6
7
8
9
32
33
34
35
Pin Name
DVDRFP
DVDRFN
PD1
PD2
A2
B2
C2
D2
CP
MLPF2
MLPF1
MIN
–
–
I
–
–
I
I
I
I
I
I
I
I
O
I
–
I
O
I
–
–
–
–
–
O
I/O
I
I
I
I
I
I
I
I
–
Description
RF SIGNAL INPUTS: Differential RF signal attenuator input pins.
CD PHOTO DETECTOR INTERFACE INPUTS: Inputs from the CD photo detector outputs.
PHOTO DETECTOR NTERFACE INPUTS: AC coupled inputs for the DPD from the main beam Photo detector matrix outputs.
DIFFERENTIAL PHASE TRACKING LPF PIN: The external capacitance is connected between
CN.
DIFFERENTIAL PHASE TRACKING LPF PIN: The external capacitance is connected between
CP.
I
PHOTO DETECTOR INTERFACE INPUTS: Inputs from the main beam Photo detector matrix outputs.
CD TRACKING ERROR INPUTS: Inverted(F) and non-inverted(E) inputs of the OP-Amp for the CD tracking error.
CD TRACKING: E-F Opamp output for feed back.
CD CENTER ERROR INPUT: Inverted input of the OP-Amp for the CD center error.
CENTER ERROR OPAMP OUTPUT: CEIN Opamp output for feedback.
Ground pin for the servo block.
APC INPUT: DVD APC input pin from the monitor photo diode.
APC OUTPUT: DVD APC output pin to control the laser power.
APC INPUT: CD APC input pin from the monitor photo diode.
APC OUTPUT: CD APC output pin to control the laser power.
APC OUTPUT ON/OFF: APC output control pin. A low level activates LD output.(open high)
REFERENCE VOLTAGE OUTPUT: This pin provides the internal DC bias reference voltage
(+2.5 V fix). Output impedance is less than 50 ohm.
REFERENCE VOLTAGE INPUT : DC bias voltage input for servo output reference.
Power supply pin for the servo block
MIRROR DETECT OUTPUT: Mirror detect comparator output. Pseudo CMOS output.
MIRR SIGNAL PEAK HOLD PIN: The external capacitance is connected to VPB.
MIRR SIGNAL BOTTOM HOLD PIN: The external capacitance is connected to VPB.
LOW IMPEDANCE ENABLE: TTL compatible input pin that activates the FDCHG switches.
A low level activates the switches and the falling edge of the internal FDCHG triggers the fast decay for the MIRR bottom hold circuit.(open high)
MIRR SIGNAL LPF PIN: The external capacitance is connected to VPB.
MIRR SIGNAL LPF PIN: The external capacitance is connected to VPB.
RF SIGNAL INPUT FOR MIRROR: AC coupled inputs for the mirror dection circuit from pullin signal output (PI).
-46-
IC DESCRIPTION - 1/11 (SSI33P3721)-2/2
Pin No.
36
40
41
42
43
44
45
37
38
39
46
47
48
49
50
51
52
53
54
55
60
61
62
63
64
56
57
58
59
Pin Name
PI
DFT
TPH
TZC
TEI
TE
FE
CE
BYP2
HOLD2
SCLK
SDATA
SDEN
HOLD1
VNA
FNN
FNP
DIP
DIN
RX
BYP
SIGO
VPA
AIP
AIN
ATON
ATOP
CDRF
CDRFDC
I
O
O
I
O
–
I
–
O
I
O
I
I
–
O
O
–
O
I
O
–
O
O
I
I/O
O
I/O
I
I
–
Description
PULL-IN SIGNAL OUTPUT: The summing signal output of A,B,C,D inputs for mirror detection. Reference to VCI.
DEFECT OUTPUT: Pseudo CMOS output. When defect is detected, the DFT output goes high.
Also the servo AGC output can be monitored at this DFT pin, when CAR bit7-4 is ‘0011’.
PI TOP HOLD PIN: An external capacitance is connected to VPB.
TRACKING ZERO CROSSING SIGNAL OUTPUT: Tracking zero crossing output. Pseudo
CMOS output.
TRACKING ERROR AC COUPLED INPUT: AC couple input for the tracking zero crossing signal output.
TRACKING ERROR SIGNAL OUTPUT: Tracking error output reference to VCI.
FOCUSING ERROR SIGNAL OUTPUT: Focus error output reference to VCI.
CENTER ERROR SIGNAL OUTPUT: Center error output reference to VCI.
The Servo AGC integration capacitor CBYP2, is connected between BYP2 and VNB.
HOLD CONTROL: TTL compatible control pin which, when pulled high,disables the Servo
AGC charge pump and holds the Servo AGC amplifier gain as its present value. (open high)
SERIAL CLOCK: Serial clock CMOS input. The clock applied to this pin is synchronized with the data applied to SDATA. (not to be left open)
SERIAL DATA: Serial data bidirectional CMOS pin. NRZ programming data for the internal registers is applied to this input. (not to be left open)
SERIAL DATA ENABLE: Serial enable CMOS input. A high level input enables the serial port.
(not to be left open)
HOLD CONTROL: TTL compatible control pin which, when pulled high, disables the RF AGC charge pump and holds the RF AGC amplifier gain as its present value. (open high)
Ground pin for the RF block and serial port.
DIFFERENTIAL NORMAL OUTPUTS: Filter normal outputs.
ANALOG INPUTS FOR RF SINGLE BUFFER: Differential analog inputs to the RF single-end output buffer and full wave rectifier.
REFERENCE RESISTOR INPUT: An external 12.1 or 8.2 k ohm, 1% resistor is connected from this pin to ground to establish a precise PTAT (proportional to absolute temperature) reference current for the filter.
The RF AGC integration capacitor CBYP, is connected between BYP and VPA.
SINGLE-ENDED NORMAL OUTPUT: Single-ended RF output.
Power supply pin for the RF block and serial port.
AGC AMPLIFIER INPUTS: Differential AGC amplifier input pins.
DIFFERENTIAL ATTENUATOR OUTPUTS: Attenuator outputs.
RF SIGNAL INPUT : Single-ended RF signal attenuator input pin.
CD RF SIGNAL OUTPUT: Single-ended CD RF summing output.
-47-
IC DESCRIPTION - 2/11 (KA3032)-1/1
20
21
22
23
15
16
17
18, 19
12
13
14
10
11
8
9
Pin No.
3
4
1
2
5
6, 7
37, 38
39
40
41
42, 43
44
45
24
25
26, 27
28, 29
30, 31
32, 33
34
35, 36
46
47
48
Pin Name
OUT1
IN2.1
IN2.2
OUT2
IN3.1
GND
REV
SGND
OPOUT
GND
OPIN (+)
OPIN (-)
MUTE4
MUTE3
IN3.2
OUT3
IN4.1
IN4.2
OUT4
CTL
FWD
MUTE1, 2
PVCC1
DO5.2, DO5.1
DO4.2, DO4.1
GND
DO3.2, DO3.1
PGND
DO2.2, DO2.1
DO1.2, DO1.1
PVCC2
REG50
REG050
GND
RES50
SVCC
REF
IN1.1
IN1.2
I
I
I
I
O
–
I
–
O
I
I
I
I
I
O
I/O
I
O
O
I
I
–
–
I
–
O
O
O
–
I
I
I
–
O
–
O
O
O
I
–
Description
CH 1 op-amp output
CH 1 op-amp input (+)
CH 2 op-amp input (-)
CH 2 op-amp output
CH 3 op-amp input (+)
Ground
CH 3 op-amp input (-)
CH 3 op-amp output
CH 4 op-amp input (+)
CH 4 op-amp input (-)
CH 4 op-amp output
CH 5 motor speed control
CH 5 forward input
CH 5 reverse input
Signal ground
Opamp output
Ground
Opamp input (+)
Opamp inpt (-)
CH 4 mute
CH 3 mute
CH 1, CH 2 mute
Power supply voltage (For CH 5)
CH 5 drive output
CH 4 drive output
Ground
CH 3 drive output
Power ground
CH 2 drive output
CH 1 drive output
Power supply voltage (For CH 1, CH 2, CH 3, CH 4)
Regulator output
Regulator 5V output
Ground
Regulator reset
Signal supply voltage
Bias voltage input
CH 1 opamp input (+)
CH 1 opamp input (-)
-48-
28
29
30
31 ~ 34
35
36 ~ 39
40
14
15
16 ~ 19
20
21
22 ~ 26
27
Pin No.
1
2 ~ 5
6
7 ~ 10
11, 12
13
IC DESCRIPTION - 3/11 (GLT441L16-40)-1/1
Pin Name
VCC
DQ0 ~ DQ3
VCC
DQ4 ~ DQ7
NC
______
WE
________
RAS
NC
A0 ~ A3
VCC
GND
A4 ~ A8
_____
OE
__________
UCAS
__________
LCAS
NC
DQ8 ~ DQ11
GND
DQ12 ~ DQ15
GND
–
I/O
–
I
I
–
I/O
–
I
I
I
–
I
–
I/O
–
I/O
–
I/O
–
I
Power Supply (+3.3 V)
Data-In / Data-Out
Power Supply (+3.3 V)
Data-In / Data-Out
Not used
Write Enable
Row Address Strobe
Not used
Address Input
Power Supply (+3.3 V)
Ground (0 V)
Address Input
Output Enable
Column Address Strobe
Column Address Strobe
Not used
Data-In / Data-Out
Ground (0 V)
Data-In / Data-Out
Ground (0 V)
Description
-49-
IC DESCRIPTION - 4/11 (GM72V161621ET-7)-1/2
14
19
20
25
26
27
28
29
30
31
32
33
21
22
23
24
15
16
17
18
Pin No.
7
8
9
5
6
3
4
1
2
10
11
12
13
MA10
MA0
MA1
MA2
MA3
VCC
GND
MA4
MA5
MA6
MA7
MA8
MA9
NC
Pin Name
VCC
DQ0
DQ1
VSSQ
DQ2
DQ3
VCCQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VCCQ
LDQM
_____
MWE
_______
CAS
________
RAS
___
CS1
MA11
–
I/O
–
I/O
–
I/O
–
I/O
–
I/O
–
–
I
I
I
I
I
I
–
Description
3.3 V is applied. (VCC is for the internal circuit.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
DRAM.
Ground is connected. (VSSQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
DRAM.
3.3 V is applied. (VCCQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
DRAM.
Ground is connected. (VSSQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
DRAM.
3.3 V is applied. (VCCQ is for the output buffer.)
DQM controls input/output buffers.
- Read operation: If DQM is High, The output buffer becomes High-Z. If the DQM is Low, the output buffer becomes Low-Z.
- Write operation: If DQM is High, the previous data is held (the new data is not written). If
DQM is Low, the data is written.
Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section.
____ ____
When CS is Low, the command input cycle becomes valid. When CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held.
A11 is a bank select signal (BS). The memory array of the GM72V161621ET/ELT Series is divided into bank 0 and bank 1. GM72V161621ET/ELT Series contain 2048 row x 256 column x
16bits. If A11 is Low, bank 0 is selected, and if A11 is High , bank 1 is selected.
Row address (AX0 to AX10) is determined by A0 to A10 level at the bank active command cycle CLK rising edge. Column address is determined by A0 to A7 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address.
A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by A11 ( BS) is precharged.
3.3 V is applied. (VCC is for the internal circuit.)
Ground is connected. (VSS is for the internal circuit.)
Row address (AX0 to AX10) is determined by A0 to A10 level at the bank active command cycle CLK rising edge. Column address is determined by A0 to A7 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address.
A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by A11 ( BS) is precharged.
Not used.
-50-
IC DESCRIPTION - 4/11 (GM72V161621ET-7)-2/2
Pin No.
Pin Name
34
35
36
43
44
45
46
47
48
37
38
39
40
41
42
49
50
CKE
CLK
UDQM
MD11
VCCQ
MD12
MD13
VSSQ
MD14
NC
VCCQ
MD8
MD9
VSSQ
MD10
MD15
GND
–
I/O
–
I/O
–
–
I/O
–
I/O
–
I/O
I
I
I
Description
This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for powerdown and clock suspend modes.
CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge.
DQM controls input/output buffers.
- Read operation: If DQM is High, The output buffer becomes High-Z. If the DQM is Low, the output buffer becomes Low-Z.
- Write operation: If DQM is High, the previous data is held (the new data is not written). If
DQM is Low, the data is written.
Not used
3.3 V is applied. (VCCQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
DRAM.
Ground is connected. (VSSQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
DRAM.
3.3 V is applied. (VCCQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
DRAM.
Ground is connected. (VSSQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
DRAM.
Ground is connected. (VSS is for the internal circuit.)
-51-
IC DESCRIPTION - 5/11(PLL1700E)-1/1
Pin No.
1
2
10
11
12
8
9
6
7
13
14
15
16
17
18
19
3
4
5
20
Pin Name
D PLL L
MODE
VDD
GND
XT2
XT1
GNDP
VDDP
RSV
MCKO
MPEG CLK
SCKO1 MCK
SCKO4
SCKO2
GNDB
VDDB
DA XCK
RESET
S DATA
S CLK
O
O
O
–
–
I
–
–
–
O
O
O
I
I
–
–
–
I/O
I
I
I
Description
Latch Enable for Software Mode/Sampling Rate Selection for Hardware Mode. When MODE pin is LOW, ML is selected.(1)
Mode Control Select. When this pin is HIGH, device is operated in hardware mode using SR0
(pin 1), FS0 (pin 19), and FS1 (pin 20). When this pin is LOW, device is operated in software mode by three-wire interface using ML (pin 1), MD (pin 19) and MC (pin 20).(1)
Digital Power Supply, +5V.
Digital Ground.
27MHz Crystal. When an external 27MHz clock is applied to XT1 (pin 6), this pin must be connected to GND.
27MHz Oscillator Input/External 27MHz Input.
Ground for PLL.
Power Supply for PLL, +5V.
Reserved. Must be left open.
27MHz Output.
Inverted 27MHz Output.
Fixed 33.8688MHz Clock Output.
768f
S
Clock Output.
256f
S
Clock Output.
Digital Ground for VDDB.
Digital Power Supply for Clock Output Buffers, +3.3V.
384f
S
Output. This output has been optimized for the lowest jitter and should be connected to the audio DAC(s).
Reset. When this pin is LOW, device is held in reset.(1)
Serial Data Input for Software Mode/Sampling Frequency Selection for Hardware Mode. When
MODE pin is LOW, MD is selected.(1)
Shift Clock Input for Software Mode/Sampling Frequency Selection for Hardware Mode. When
MODE pin is LOW, MC is selected.(1)
-52-
IC DESCRIPTION - 6/11 (PCM1716E)-1/1
18
19
20
21
14
15
16
17
11
12
13
9
10
7
8
26
27
28
22
23
24
25
Pin No.
3
4
1
2
5
6
Pin Name
LRCIN
DIN
BCKIN
CLKO
XTI
XTO
DGND
VDD
VCC2R
AGND2R
EXTR
NC
VOUTR
AGND1
VCC1
VOUTL
NC
EXTL
AGND2L
VCC2L
ZERO
_______
RST
_____
CS/IWO
MODE
____________
MUTE
MD/DM0
MC/DM1
ML/IIS
–
O
O
–
O
–
–
–
O
–
O
–
–
–
–
I
I
I
I
I
I
I
I/O
I
O
I
I
I
O
Description
Left and Right Clock Input. This clock is equal to the sampling rate - f
S
.(1)
Serial Audio Data Input. (1)
Bit Clock Input for Serial Audio Data.(1)
Buffered Output of Oscillator. Equivalent to System Clock.
Oscillator Input (External Clock Input)
Oscillator Output
Digital Ground
Digital Power +5V
Analog Power +5V
Analog Ground
Rch, Common Pin of Analog Output Amp
Not used
Rch, Analog Voltage Output of Audio Signal
Analog Ground
Analog Power +5V
Lch, Analog Voltage Output of Audio Signal
Not used
Lch, Common Pin of Analog Output Amp
Analog Ground
Analog Power +5V
Zero Data Flag
Reset. When this pin is low, the DF and modulators are held in reset. (2)
Chip Select/Input Format Selection. When this pin is low, the Mode Control is effective. (3)
Mode Control Select. (H: Software, L: Hardware). (2)
Mute Control
Mode Control, DATA/De-emphasis Selection 1. (2)
Mode Control, BCK/De-emphasis Selection 2. (2)
Mode Control, WDCK/Input Format Selection. (2)
NOTES: (1) Pins 1, 2, 3; Schmitt Trigger input.
(2) Pins 22, 24, 25, 26, 27, 28; Schmitt Trigger input with pull-up resister.
(3) Pin 23; Schmitt Trigger input with pull-down resister.
-53-
16, 17
18 ~ 25
26
27
28
29
30
31
35
36
37
38
32
33
34
39
40
41
42
43
44
45
46
47
48
Pin No.
1 ~ 8
9
10
11
12
13 ~ 15
IC DESCRIPTION - 7/11 (AT49F8192A-90TC)-1/1
Pin Name
A16 ~ A9
A20
NC
_______
WE
____________
RESET
NC
A18, A17
A7 ~ A0
_____
CE
GND
_____
OE
I/O0
I/O8
I/O1
I/O9
I/O2
I/O10
I/O3
I/O11
VCC
I/O4
I/O12
I/O5
I/O13
I/O6
I/O14
I/O7
I/O15/A-1
GND
___________
BYTE
A17 I
I
I
–
I
I
O
I/O
I/O
I/O
I/O
I/O
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
I/O
–
I
I
I
I
–
Addresses
Addresses
Not used
Write Enable
Reset
Not used
Addresses
Addresses
Chip Enable
Ground
Output Enable
Data Inputs/Outputs
Data Inputs/Outputs
Description
I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode)
Ground
Selects Byte or Word Mode
Addresses
-54-
IC DESCRIPTION - 8/11 (V53C16256HK50)-1/1
28
29
30
31 ~ 34
35
36 ~ 39
40
14
15
16 ~ 19
20
21
22 ~ 26
27
Pin No.
1
2 ~ 5
6
7 ~ 10
11, 12
13
Pin Name
VCC
D00 ~ D03
VCC
D04 ~ D07
NC
______
WE
________
RAS
NC
A01 ~ A04
VCC
VSS
A05 ~ A09
_____
OE
_____
CASH
_____
CASL
NC
D08 ~ D11
VSS
D12 ~ D15
VSS
–
I/O
–
I
I
–
I/O
–
I
O
I
–
I
–
I/O
–
I/O
–
I/O
–
I
Description
+5V Supply
Data Input, Output
+5V Supply
Data Input, Output
Not used
Write Enable
Row Address Strobe
Not used
Address Inputs
+5V Supply
0V Supply (GND)
Address Inputs
Output Enable
Column Address Strobe Upper Byte Control
Column Address Strobe Lower Byte Control
Not used
Data Input, Output
0V Supply
Data Input, Output
0V Supply
-55-
Pin No.
3
4
1
2
5
6
20
21
22
23
15
16
17
18
19
27
28
29
30
31
24
25
26
11
12
13
14
9
10
7
8
40
41
42
35
36
37
32
33
34
38
39
IC DESCRIPTION - 9/11(LC866112B-5N21)-1/2
Pin Name
P35
P36
P37
PWM1
TEST1
_______
RES
P82
P83
P84
P85
P86
P87
MODE SW
M REQ
P72
P73
G1
G2
G3
G4
G5
G6
G7
XT1
XT2
VSS
CF1
CF2
VDD
P80
P81
P4
P5
P6
P1
P2
P3
P7
P8
P9
VPP
VKK
I/O
I
O
I
I
–
I
I
I
I
I/O
I
I
I
I
I
O
O
O
O
O
I
O
O
I
I
O
–
–
I
I
O
O
I
I
O
O
O
O
O
O
O
O
Description
______
Select DOWN SW input from SW914
Enter SW input from SW910
Select right SW input SW911
Not used.
Not used. (TEST port)
Reset signal input from IC902 3pin
Not used. (Input for 32.768 kHz crystal oscillation)
Not used. (Output for 32.768 kHz crystal oscillation)
Ground
Ceramic resonator X501 (6 MHz) oscillation input
Ceramic resonator X501 (6 MHz) oscillation output
Vcc (5 V)
Key in input from SW901 ~ SW908
Reserved
Shuttle 3 line A/D input
Reserved
“LOW” at program download mode
Request signal (active “LOW”) from IC501 (Main µ-COM, HD64173034AFI20)
Not used.
Remocon receiver signal input
VFD display control signal output. DIG901 G1 to G7
VFD display control signal output. DIG901 P1 to P9
Vcc (5 VAU)
-24 V input
-56-
IC DESCRIPTION - 9/11(LC866112B-5N21)-2/2
Pin No.
63
64
65
66
67
68
69
70
71
72
73
74
55
56
57
58
59
60
61
62
49
50
51
52
53
54
43
44
45
46
47
48
75
76
77
78
79
80
Pin Name
P04
P05
ZOOM RST
V07
VSS
P10
P11
P12
RXDO
TXDO
SCKO
F REQ
S28
S29
S30
S31
P00
P01
P02
P03
P16
P17
P18
P19
S26
S27
P10
P11
P12
P13
P14
P15
M RESET
PWR CTL
P31
P32
P33
P34
I/O
–
–
I/O
–
–
–
–
I
I
–
O
O
–
–
–
–
–
–
–
–
O
O
O
O
–
–
O
O
O
O
O
O
I
I
O
O
I/O
I
Description
VFD display control signal output. DIG 901 P10 to P19
Not used.
D902 option (Present at AIWA remocon model)
Not used.
Diode option input
Not used.
Reserved
Not used
Not used
Ground
Reserved
Serial data to IC501 (Main µ-COM)
Serial data input from IC501 (Main µ-COM)
Serial clock input from IC501 (Main µ-COM)
Request signal (active “LOW”) to IC501 (main µ-COM)
Reset signal (active “LOW”) to IC501 (main µ-COM)
Power control (active “HIGH”) to main board
Not used.
UP signal input from SW912
Jog signal “JSW1” input, Not used
Left signal input from SW915
-57-
IC DESCRIPTION - 10/11(GDC25D801C)-1/5
Pin No.
13
14
15
16
9
10
11
12
17
18
19
20
21
22
7
8
5
6
3
4
1
2
35
36
37
38
31
32
33
34
39
40
41
42
27
28
29
30
23
24
25
26
Pin Name
DAT9
DAT10
DAT11
DAT12
DAT13
DAT14
DAT15
DAT16
VSS
ADD1
ADD2
ADD3
ADD4
VDD
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
DAT8
VDD
RAS
UCAS
LCAS
WE
OE
SCAN_IN
TEST_SE
ADD5
ADD6
ADD7
ADD8
ADD9
X2_MCK
VSS
MCK
TEST_OUT12
TEST_OUT11
TEST_OUT10
TEST_OUT9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
–
–
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
O
O
O
O
–
O
O
O
O
O
–
I
O
I
O
O
O
O
Description
Bi-directional data to DRAM
Bi-directional data to DRAM
Bi-directional data to DRAM
Bi-directional data to DRAM
Bi-directional data to DRAM
Bi-directional data to DRAM
Bi-directional data to DRAM
Bi-directional data to DRAM
Bi-directional data to DRAM
Bi-directional data to DRAM
Bi-directional data to DRAM
Bi-directional data to DRAM
Bi-directional data to DRAM
Bi-directional data to DRAM
Bi-directional data to DRAM
Bi-directional data to DRAM
Digital ground
Address output to DRAM
Address output to DRAM
Address output to DRAM
Address output to DRAM
Digital power supply
Address output to DRAM
Address output to DRAM
Address output to DRAM
Address output to DRAM
Address output to DRAM
Master clock from oscillator for 2x decoding
Digital GND
Master clock from oscillator
Digital power supply
Row address strobe to DRAM
Column address upper byte control strobe to DRAM
Column address lower byte control strobe to DRAM
Write enable signal to DRAM
Output enable signal to DRAM
Scan data input
Test mode selection (low for normal)
Test output (Not used)
Test output (Not used)
Test output (Not used)
Test output (Not used)
-58-
IC DESCRIPTION - 10/11(GDC25D801C) - 2/5
76
77
78
72
73
74
75
68
69
70
71
64
65
66
67
79
80
81
82
83
84
60
61
62
63
56
57
58
59
53
54
55
49
50
51
52
Pin No.
43
44
45
46
47
48
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
VSS
SENS
E_SOUT
VDD
E_ST0
E_ST1
E_ST2
GPIO7
GPIO6
GPIO5
VDD
SCLK
SDATA
XLAT
AOUT1
AOUT2
Pin Name
TEST_OUT8
TEST_OUT7
TEST_OUT6
T_SEL
TEST_OUT5
TEST_OUT4
TEST_OUT3
TEST_OUT2
TEST_OUT1
TEST_OUT0
TEST_SEL0
TEST_SEL1
TEST_SEL2
TEST_SEL3
TESTSERVO
E_SIN
E_CLK
E_ENB
E_DRB
VSS
SERVO_CLK
I/O
–
O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
O
O
O
–
I
I
–
I
O
O
–
I
I
I
I
I
I
I
I
I
I
O
O
O
O
I/O
O
I
O
O
O
O
Description
Test output (Not used)
Test output (Not used)
Test output (Not used)
Test mode selection
Test output (Not used)
Test output (Not used)
Test output (Not used)
Test output (Not used)
Test output (Not used)
Test output (Not used)
Test mode output selection
Test mode output selection
Test mode output selection
Test mode output selection
TEST PIN ( NORMAL STATE = H )
SERVO DSP PGM. DOWNLOADING DATA INPUT
SERVO DSP PGM. DOWNLOADING CLK
SERVO DSP DOWNLOADING ENABLE
SERVO DSP PGM. DOWNLOADING DIRECTION
Digital GND
SERVO DSP CLOCK INPUT
SERVO DSP PGM. DOWNLOADING DATA OUTPUT
Digital power supply
SERVO DSP DOWNLOADING STATUS 0 (Not used)
SERVO DSP DOWNLOADING STATUS 1 (Not used)
SERVO DSP DOWNLOADING STATUS 2 (Not used)
SERVO DSP GENERAL I/O: FSON(FOCUS OK INVERTING)
SERVO DSP GENERAL I/O: PSEL
SERVO DSP GENERAL I/O: ADADDR3
SERVO DSP GENERAL I/O: FKRST
SERVO DSP GENERAL I/O: FKSET (Not used)
SERVO DSP GENERAL I/O: FEL
SERVO DSP GENERAL I/O (Not used)
SERVO DSP GENERAL I/O: DSP_SENSE (Not used)
Digital GND
SERVO DSP INTERNAL STATUS MONITOR
Digital power supply
Serial Command CLOCK
Serial Command DATA
Serial Command LATCH
FDO
TDO
-59-
IC DESCRIPTION - 10/11(GDC25D801C) - 3/5
Pin No.
97
98
99
100
93
94
95
96
101
102
103
104
105
106
89
90
91
92
85
86
87
88
119
120
121
122
115
116
117
118
123
124
125
126
111
112
113
114
107
108
109
110
Pin Name
AGND
VREFN
VREFP
INP
AGND
AIN4
AIN3
AVDD
AVDD
VCM
AGND
AOUT3
AOUT4
DGND
RFVCM
VDD
AIN2
AIN1
AIN0
ADCVCM
SCK
EXT_AD0
EXT_AD1
EXT_AD2
EXT_AD3
EXT_AD4
EXT_AD5
SELEFM
EXCK
SQCK
C16M
DOTX
VDD
SQSO
VSS
PWMCH1
PWMCH2
PWMCH3
PWMCH4
PWMCH5
PWMCH6
DEFECT_IN_A
I/O
I
–
–
I
I
I
–
I
I
I
O
I
I
I
I
–
O
–
–
O
–
O
O
O
–
O
–
O
O
O
O
I
O
O
I
I
I
I
I
I
I
I
Description
Analog power supply for ADC
TDF
Analog GND for ADC
FMQ
D_VREF
Digital GND for ADC
TDF
Analog GND for ADC
TDF
TDF
TDF
TDF
Analog GND for ADC
TDF
TDF
Analog power for ADC
TDF
TDF
TDF
TDF
PLL clock output
ADC data input
ADC data input
ADC data input
ADC data input
ADC data input
ADC data input
EFMDATA INPUT SELECTION
SUB DATA REQUEST INPUT (Not used)
SUB Q DATA REQUEST
5.6448 MHz(DIGITAL OUT CLOCK) (Not used)
CD DIGITAL DATA OUTPUT (Not used)
Digital power supply
SUB Q DATA OUTPUT
Digital GND
PWM CHANNEL1(x3 CARRIER)
PWM CHANNEL1(x3 CARRIER)
PWM CHANNEL1(x3 CARRIER):SLED DRIVE OUTPUT
PWM CHANNEL1(x1 CARRIER):PDO_CTR PWM OUTPUT
PWM CHANNEL1(x1 CARRIER):RF_GAIN_CTL PWM OUTPUT
PWM CHANNEL1(x1 CARRIER):TE_BAL_CTL PWM OUTPUT
EXTERNAL DEFECT INPUT PIN
-60-
IC DESCRIPTION - 10/11(GDC25D801C) - 4/5
144
145
146
147
140
141
142
143
133
134
135
136
137
138
139
Pin No.
127
128
129
130
131
132
156
157
158
159
160
161
162
163
164
165
166
167
152
153
154
155
148
149
150
151
Pin Name
SI_ENC1
SI_ENC2
TZC
MIRR
MSDATAO
FOK
VDD
DEFECT
VSS
SLD_FG
C_SIG
COMP
INT1
INT2
VSS
INT3
INT4
VDD
ADCSB
ADCOMP_
VDCDATA0
VDCDATA1
VDCDATA2
VDCDATA3
VDCDATA4
VDCDATA5
VDCDATA6
VDCDATA7
ADADDR0
DVDD
ADADDR1
DGND
AGND
VRT
AVDD
RF
VRM
VRB
MDS
MDP
OVER64
I
I
–
O
O
O
O
–
O
O
O
–
O
–
O
I/O
I
I
I
I
O
O
I
–
I
–
–
–
O
O
O
I
I
O
I
O
I
I
I
I
I
I
Description
SLED ENCODER1 INPUT
SLED ENCODER2 INPUT
TRACK CROSS PULSE 2 INPUT
TRACK CROSS PULSE 1 INPUT
SERVO DSP INTENAL STATUS SERIAL OUTPUT
INTERNAL GENERATED FOK(Focus OK) H=OK
Digital power supply
INTERNAL GENERATED DEFECT : H=DEFECT
Digital GND
SLD_FG=(SL_ENC1) XOR (SL_ENC2)
TRACK CROSS PULSE
TRACK CROSS MONITOR
SERVO DSP INTERRUPT 1 MONITOR(MICOM COMMAND INT)
SERVO DSP INTERRUPT 2 MONITOR(FOCUS SERVO INT)
Digital GND
SERVO DSP INTERRUPT 1 MONITOR(TRACK SERVO INT)
SERVO DSP INTERRUPT 1 MONITOR
Digital power supply
PLESSY D/A CHIP SELECTION
A/D 7824 A/D CONVERTER A/D CONVERSION END STATUS
A/D 7824 A/D CONVERTER DATA BUS0
A/D 7824 A/D CONVERTER DATA BUS1
A/D 7824 A/D CONVERTER DATA BUS2
A/D 7824 A/D CONVERTER DATA BUS3
A/D 7824 A/D CONVERTER DATA BUS4
A/D 7824 A/D CONVERTER DATA BUS5
A/D 7824 A/D CONVERTER DATA BUS6
A/D 7824 A/D CONVERTER DATA BUS7
A/D 7824 A/D CONVERTER ADDRESS
Digital power supply for ADC
A/D 7824 A/D CONVERTER ADDRESS
Digital GND for ADC
Analog GND for ADC
TDF
Analog power supply for ADC
TDF
TDF
TDF
Spindle motor control signal (Not used)
Spindle motor control signal
Spindle motor reversal sensing signal output (Not used)
-61-
IC DESCRIPTION - 10/11(GDC25D801C) - 5/5
185
186
187
188
181
182
183
184
174
175
176
177
178
179
180
Pin No.
168
169
170
171
172
173
197
198
199
200
201
202
203
204
205
206
207
208
193
194
195
196
189
190
191
192
Pin Name
MON
LOCK
FG_M
VSS
SCAN_OUT
VDD
A3
A4
A5
VSS
PS0
VDD
PS1
PS2
INT
RN
WN
CS
A0
A1
A2
PS3
PS4
PS5
PS6
PS7
RESET
REQ_DIVX
REQ_MPEG
MPEG1
MPEG2
MPEG3
MPEG4
MPEG5
MPEG6
MPEG7
MPEG8
SENB
SDCLK
SERR
SYNC
I/O
–
I/O
I/O
I
I
I
I
I
I
I
I
I
O
I
I/O
I
–
O
O
O
–
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I/O
I
I/O
I/O
I/O
I/O
Description
Spindle motor ON/OFF control signal
CLV servo lock signal
TDF
Digital GND
SCAN DATA OUTPUT (Not used)
Digital power supply
Interrupt request to Host
Read strobe from HOST
Write strobe from HOST
Chip select from HOST
Internal register address from HOST
Internal register address from HOST
Internal register address from HOST
Internal register address from HOST
Internal register address from HOST
Internal register address from HOST
Digital GND
Bi-directional data to Host
Digital power supply
Bi-directional data to Host
Bi-directional data to Host
Bi-directional data to Host
Bi-directional data to Host
Bi-directional data to Host
Bi-directional data to Host
Bi-directional data to Host
HARDWARE RESET
Data request from DIVX module (Not used)
Data request from MPEG
MPEG data
MPEG data
MPEG data
MPEG data
MPEG data
MPEG data
MPEG data
MPEG data
MPEG data valid signal (low for valid)
MPEG data transfer clock
MPEG data error detection signal (low indicates error occurred)
SERVO DSP INTERRUPT 1 MONITOR(MICOM COMMAND INT) (Not used)
-62-
IC DESCRIPTION - 11/11(ZIVA4.1) - 1/5
Pin No.
1
2
3
4
5
6
7
8
9 ~ 12
13
14
15 ~ 18
19
20
21 ~ 28
29
Pin Name
_____
RD
____
R/W
VDD_3.3
___________
WAIT
____________
RESET
VSS
VDD_3.3_5
_______
INT
NC
VDD_2.5
VSS
NC
VSS
VDD_3.3_5
VDATA0 ~
VDATA7
_______
VSYNC
30
_______
HSYNC I/O
31
32
33 ~ 35
36
37
38 ~ 42
43
44
45
46 ~ 52
53, 54
55
56
VSS
VDD_3.3_5
NC
VDD_2.5
VSS
NC
PIO0
VSS
VDD_3.3_5
PIO1 ~ PIO7
MDATA0, MDATA1
VDD_3.3
VSS
–
O
I/O
–
–
–
–
–
O
I/O
I/O
–
–
I/O
I
I
–
I
–
–
O
–
O
O
–
–
–
O
O
I/O
Description
Read strobe in I mode. Must be held HIGH in M Mode.
____
Read/write strobe in M mode. Write strobe in I mode. Host asserts R/W LOW to select Write and
LOW to select Read for M Mode only.
3.3-V supply voltage for I/O signals.
Transfer not complete / data acknowledge. Active LOW to indicate host initiated transfer is not
___________ ____ complete. WAIT is asserted after the falling edge of CS and reasserted when decoder is ready to complete transfer cycle. Open drain signal, must be pulled-up via 1k ohm to 3.3 volts. Driven high for 10 ns before tristate.
Active Low Reset. Assert for at least 5-milliseconds in the presence of clock to reset the entire chip.
Ground for core logic and I/O signals.
3.3/5-V supply voltage for I/O signals.
Host interrupt. Open drain signal, must be pulled-up via 4.7k ohm to 3.3 volts. Driven high for
10 ns before tristate.
Not used
2.5-V supply voltage for core logic.
Ground for core logic and I/O signals.
Not used
Ground for core logic and I/O signals.
3.3/5-V supply voltage for I/O signals.
Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up, the decoder does not drive VDATA. During boot-up, the decoder uses configuration parameters to drive or 3state VDATA.
Vertical sync. Bi-directional, the decoder outputs the top border of a new field on the first
_____________ ______________ ______________
HSYNC after the falling edge of VSYNC. VSYNC can accept vertical synchronization or top/
______________ ______________ bottom field notification from an external source. (VSYNC HIGH = bottom field. VSYNC LOW
= Top field)
Horizontal sync. The decoder begins outputting pixel data for a new horizontal line after the
_____________ falling (active) edge of HSYNC.
Ground for core logic and I/O signals.
3.3/5-V supply voltage for I/O signals.
Not used
2.5-V supply voltage for core logic.
Ground for core logic and I/O signals.
Not used
Programmable I/O pins.
Ground for core logic and I/O signals.
3.3/5-V supply voltage for I/O signals.
Programmable I/O pins.
SDRAM Data
3.3-V supply voltage for I/O signals.
Ground for core logic and I/O signals.
-63-
IC DESCRIPTION - 11/11(ZIVA4.1) - 2/5
Pin Name I/O
MDATA2 ~ MDATA7
MDATA15
VDD_3.3
VSS
MDATA14
VDD_2.5
I/O
I/O
–
–
I/O
–
O
I
–
–
–
O
O
I
–
I
I
–
O
O
O
O
–
–
O
O
–
O
O
–
–
–
I
O
I/O
O
O
–
I/O
–
–
VSS
MDATA13 ~ MDATA9
VDD_3.3
VSS
MDATA8
LDQM
SD-CLK
CLKSEL
MADDR9, MADDR8
VDD_3.3
VSS
MADDR7 ~ MADDR5
VDD_2.5
VSS
MADDR4
__________
MWE
______________
SD-CAS
VDD_3.3
VSS
______________
SD-RAS
_____________
SD-CS0
_____________
SD-CS1/MADDR11
____________
SD-BS
MADDR10
MADDR0
VDD_3.3
VSS
MADDR1 ~ MADDR3
VSS ADC
NC
DAI XCK
DAI-LRCK
DAI-BCK
VDD_3.3
VSS
79
80, 81
82
83
84 ~ 86
87
88
89
68
69 ~ 73
74
75
76
77
78
Pin No.
57 ~ 62
63
64
65
66
67
98
99
100
101
102 ~ 104
105
106 ~ 111
112
113
114
115
116
94
95
96
97
90
91
92
93
Description
SDRAM Data
SDRAM Data
3.3-V supply voltage for I/O signals.
Ground for core logic and I/O signals.
SDRAM Data
2.5-V supply voltage for core logic.
Ground for core logic and I/O signals.
SDRAM Data
3.3-V supply voltage for I/O signals.
Ground for core logic and I/O signals.
SDRAM Data
SDRAM Lower or Upper Mask
SDRAM Clock
Selects SYSCLK or VCLK as clock source. Normal operation is to tie HIGH.
SDRAM Address
3.3-V supply voltage for I/O signals.
Ground for core logic and I/O signals.
SDRAM Address
2.5-V supply voltage for core logic.
Ground for core logic and I/O signals.
SDRAM Address
SDRAM Write Enable
Active LOW SDRAM Column Address
3.3-V supply voltage for I/O signals.
Ground for core logic and I/O signals.
Active LOW SDRAM Row Address
Active LOW SDRAM Chip Select 0
Active LOW SDRAM Chip Select 1 or use as MADDR11 for larger SDRAM (64 Mbits).
SDRAM Bank Select
SDRAM Address
SDRAM Address
3.3-V supply voltage for I/O signals.
Ground for core logic and I/O signals.
SDRAM Address
Not used
Not used
Tie to VSS or VDD_3.3
PCM left/right clock.
PCM input bit clock.
3.3-V supply voltage for I/O signals.
Ground for core logic and I/O signals.
-64-
IC DESCRIPTION - 11/11(ZIVA4.1) - 3/5
126
148
149
150
151
144
145
146
147
140
141
142
143
136
137
138
139
152
153
154
155
156
157
158
127
132
133
134
135
128
129
130
131
DA-BCK
DA-IEC
VDD_2.5
VSS
NC
VSS_DAC
VSS_VIDEO
CVBS +sync
VDD_DAC
VDD_VIDEO
NC
VSS_DAC
VSS_VIDEO
CVBS/G/Y
VDD_DAC
VDD VIDEO
NC
VSS_DAC
VSS_VIDEO
Y/B/U
VDD DAC
VDD_VIDEO
NC
VSS_DAC
VSS_VIDEO
C/R/V
VDD DAC
VDD_VIDEO
VSS_RREF
RREF
VDD_RREF
A_VSS
SYSCLK
O
–
O
–
–
–
–
–
O
–
–
–
–
–
O
–
–
–
–
I
–
I
–
–
O
–
–
–
O
–
–
–
–
Pin No.
117
118 ~ 121
122
123
124
Pin Name
DAI-DATA
DA-DATA3~ DA-DATAO
DA-LRCK
VDD_3.3
VSS
I/O
O
–
I
O
–
125 DA-XCK I/O
Description
PCM data input.
PCM Data Out. Eight channels. Serial audio samples relative to DA_BCK and DA_LRCK.
PCM Left Clock. Identifies the channel for each sample. The polarity is programmable.
3.3-V supply voltage for I/O signals.
Ground for core logic and I/O signals.
Audio External Frequency Clock input or output. DA_BCK and DA_LRCK are derived from this clock. DA_XCK can be 384 or 256 times the sampling frequency.
PCM Bit Clock. Divided by 8 from DA_XCK. DA_BCK can be either 48 or 32 times the sampling frequency.
PCM data out in IEC-958 format or compressed data out in IEC-1937 format.
2.5-V supply voltage for core logic.
Ground for core logic and I/O signals.
Not used
Analog Video DAC Ground.
Analog Video Ground.
DAC video output format
3.3-V Analog Video Power.
3.3-V Analog Video Power.
Not used
Analog Video DAC Ground.
Analog Video Ground.
DAC video output format.
3.3-V Analog Video Power.
3.3-V Analog Video Power.
Not used
Analog Video DAC Ground.
Analog Video Ground.
DAC video output format
3.3-V Analog Video Power.
3.3-V Analog Video Power.
Not used
Analog Video DAC Ground.
Analog Video Ground.
DAC video output format
3.3-V Analog Video Power.
3.3-V Analog Video Power.
Analog Video Ground.
Reference Resistor. Connecting to pin 139 through a 4.7k ± 1% resistor is recommended
3.3-V Analog Video Power.
Analog PLL Ground.
Optional System Clock. Tie to A_VDD through a 1k Ohm resistor
-65-
IC DESCRIPTION - 11/11(ZIVA4.1) - 4/5
Pin No.
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
Pin Name
VCLK
A_VDD
DVD-DATA0/CD-DATA
DVD-DATA1/
CD-LRCK
DVD-DATA2/
CD-BCK
DVD-DATA3/
CD-C2P0
–
I
I
I
I
DVD-DATA4/
CDG-SDATA
VSS
VDD_3.3
DVD-DATA5/
CDG-VFSY
DVD-DATA6/
CDG-SOS1
DVD-DATA7/
CDG-SCLK
VDACK I
I
I
I
–
–
I
VREQUEST
VSTROBE
174
175
176
177
178
179
180
181
182 ~ 184
185 ~ 187
188
ERROR
VDD_3.3
RESERVED
VDD_3.3
VSS
NC
RESERVED
NC
HADDR0 ~ HADDR2
RESERVED
VSS
–
–
I
I
–
I
–
I
–
–
I
I/O
I
I
O
Description
Video clock. Clocks out data on input. VDATA[7:0]. Clock is typically 27 MHz.
System clock that drives internal PLLs and internal DENC. ZiVA-4 requires an external 27-MHz
TTL oscillator.
3.3-V Analog PLL Power
Serial CD data. This pin is shared with DVD compressed data DVD-DATA0.
Programmable polarity 16-bit word synchronization to the decoder (right channel HIGH). This pin is shared with DVD compressed data DVD-DATA1.
CD bit clock. Decoder accept multiple BCK rates. This pin is shared with DVD compressed data
DVD-DATA2.
Asserted HIGH indicates a corrupted byte. Decoder keeps the previous valid picture on-screen until the next valid picture is decoded. This pin is shared with DVD compressed data DVD-
DATA3.
DVD parallel compressed data from DVD DSP. Or CD+G (Subcode) data indicating serial subcode data input.
Ground for core logic and I/O signals.
3.3-V supply voltage for I/O signals.
DVD parallel compressed data from DVD DSP. Or CD+G (Subcode) Frame Sync indicating frame-start or composite synchronization input.
DVD parallel compressed data from DVD DSP. Or CD+G (Subcode) Block Sync indicating block-start synchronization input.
DVD parallel compressed data from DVD DSP. Or CD+G (Subcode) Clock indicating subcode data clock input or output.
In synchronous mode, bitstream data acknowledge. Asserted when DVD data is valid. Polarity is programmable.
Bitstream request. Decoder asserts VREQUEST to indicate that the bitstream input buffer has available space. Polarity is programmable.
Bitstream strobe. Programmable dual mode pulse. Asynchronous and synchronous. In
Asynchronous mode, an external source pulses VSTROBE to indicate data is ready for transfer.
In synchronous mode, VSTROBE clocks data.
Error in input data. If ERROR signal is not available from the DSP it must be grounded.
3.3-V supply voltage for I/O signals.
Tie to VSS or VDD_3.3
3.3-V supply voltage for I/O signals.
Ground for core logic and I/O signals.
Not used
Tie to VSS or VDD_3.3
Not used
Host address bus. 3-bit address bus selects one of eight host interface registers.
Tie to VSS or VDD_3.3
Ground for core logic and I/O signals.
-66-
IC DESCRIPTION - 11/11(ZIVA4.1) - 5/5
Pin No.
189
190
191
192
193 ~ 196
197
198
199
200
201
202
203
204
205
206
207
208
Pin Name
VDD_2.5
RESERVED
VSS
VDD_3.3
RESERVED
HDATA7
VSS
HDATA6
HDATA5
HDATA4
HDATA3
HDATA2
VDD_3.3
VSS
HDATA1
HDATA0
____
CS
–
I/O
I/O
I/O
I/O
I/O
–
–
I/O
I/O
–
–
–
I
I
I/O
Description
2.5-V supply voltage for core logic.
Tie to VSS or VDD_3.3.
Ground for core logic and I/O signals.
3.3-V supply voltage for I/O signals.
Tie to VSS or VDD_3.3.
HDATA[7] is the 8-bit bi-directional host data bus through which the host writes data to the decoder Code FIFO. MSB of the 32-bit word is written first. The host also reads and writes the decoder internal registers and local SDRAM/ROM via HDATA[7].
Ground for core logic and I/O signals.
I/O
I
HDATA[6 ~ 2] is the 8-bit bi-directional host data bus through which the host writes data to the decoder Code FIFO. MSB of the 32-bit word is written first. The host also reads and writes the decoder internal registers and local SDRAM/ROM via HDATA[6 ~ 2].
3.3-V supply voltage for I/O signals.
Ground for core logic and I/O signals.
HDATA[1, 0] is the 8-bit bi-directional host data bus through which the host writes data to the decoder Code FIFO. MSB of the 32-bit word is written first. The host also reads and writes the decoder internal registers and local SDRAM/ROM via HDATA[1, 0].
____
Host chip select. Host asserts CS to select the decoder for a read or write operation. The falling edge of this signal triggers the read or write operation.
-67-
MECHANICAL EXPLODED VIEW 1/1
463
463
250
465
462
465
332
467
260
465
462
463
275
283
467
452
PWB
<EXCEPT FOR HR>
280
PWB
452
285
467
300
281
283
PWB
452
280
PWB
001
PWB
279
452
285
<HR ONLY>
-68-
463
463
PWB
MECHANICAL MAIN PARTS LIST 1/1
REF. NO PART NO.
KANRI
NO.
DESCRIPTION
001 S9-30R-018-5A0 HOLDER DIGITRON
250 S1-10R-018-4G0 CASE TOP<HRN,KN,EZN>
250 S1-10R-018-4A0 CASE TOP<UB,EZB>
260 ———— CHASSIS ASSY MAIN
275 S9-30R-018-3A0 HOLDER MAIN PCB
279 S9-30R-019-9A0 HOLDER CONNECTOR
280 S7-21R-F15-7B0 PANEL ASSY FRONT<HRN>
280 S7-21R-F15-7A0 PANEL ASSY FRONT<UB>
280 S7-21R-F15-7C0 PANEL ASSY FRONT<KN,EZN>
280 S7-21R-F15-7D0 PANEL ASSY FRONT<EZB>
281 S9-40R-V01-0A0 KNOB,VOLUME<HRN>
283 S5-81R-T00-6B0 DOOR ASSY TRAY<HRN,KN,EZN>
283 S5-81R-T00-6A0 DOOR ASSY TRAY<UB,EZB>
285 ———— PLATE ASSY
!
300 S4-10R-CHR-02C POWER CORD<HRN,EZB,EZN>
!
300 S4-10R-AHC-02B POWER CORD<UB>
!
300 S4-10R-LHR-02E POWER CORD<KN>
332 ———— PLATE MAIN
452 S3-530-51A-000 SCREW,SPECIAL
462 S3-530-85A-000 SCREW,DECORATION
463 S3-530-51B-000 SPECIAL SCREW
465 S3-530-46K-000 SPECIAL SCREW 3-10 B.K
467 S3-530-46N-000 SPECIAL SCREW 3-8 BK
-69-
COLOR NAME TABLE
Basic color symbol
B
G
LT
R
T
WT
LM
LD
YM
LA
Color
Black
Green
Transparent Blue
Red
Brown
Transparent White
Metallic Blue
Dark Blue
Metallic Yellow
Aqua Blue
COLOR NAME TABLE
Basic color symbol
S
V
Y
LL
DT
C
H
N
DM
GL
Color
Cream
Gray
Gold
Silver
Violet
Yellow
Light Blue
Transparent Orange
Metallic Orange
Light Green
Basic color symbol
D
L
P
ST
W
YT
GT
GM
PT
Color
Orange
Blue
Pink
Titan Silver
White
Transparent Yellow
Transparent Green
Metallic Green
Transparent Pink
-70-
DVD MECHANISM EXPLODED VIEW 1/1
429
001
002
003
A01
004
429
026
017
014
013
PWB
431
A03
018
A02
012
430
432
008
009
016
430
012
430
012
430
012
020
430
011
-71-
DVD MECHANISM MAIN PARTS LIST 1/1
REF. NO PART NO.
KANRI
NO.
DESCRIPTION
001 S3-00R-054-7A0 PLATE CLAMP
002 ———— CLAMP MAGNET 8,10-5,1-1.5
003 ———— CLAMP UPPER
004 S9-30R-017-1A0 HOLDER CLAMP
008 S4-70R-004-7A0 GEAR ASSY RACK<HRN,UB,KN>
008 S4-70R-008-0A0 GEAR ASSY, RACK<EZB,EZN>
009 S4-70R-005-3A0 GEAR MIDDLE<HRN,UB,KN>
009 S4-70R-007-9A0 GEAR MIDDLE<EZB,EZN>
011 S2-11R-002-1B0 FRAME ASSY<HRN,UB,KN>
011 S2-11R-002-8A0 FRAME ASSY UP/DOWN<EZB,EZN>
012 ———— RUBBER REAR
013 S4-00R-000-6A0 BELT LOADING
014 S4-70R-005-5A0 GEAR PULLEY
016 S4-70R-005-0A0 GEAR ASSY FEED<HRN,UB,KN>
016 S4-70R-008-1A0 GEAR ASSY, PINION<EZB,EZN>
017 S4-70R-005-6A0 GEAR LOADING
018 S9-74R-002-3A0 GUIDE UP/DOWN
020 ———— BASE MAIN
026 S3-90R-000-5A0 TRAY DISC<HRN,UB,KN>
026 S3-90R-001-0A0 TRAY DISC<EZB,EZN>
429 SS-ZZR-001-2A0 SCREW,B-TITE
430 SS-ZZH-100-3A0 SCREW,+D2.0-6MM
431 87-741-035-410 SCREW,2.0-6
432 ———— SCREW,MACHINE
A01 S8-61R-000-6A0 CLAMP ASSY DISC
A02 S0-41R-001-0C0 BASE ASSY MAIN<HRN,UB,KN>
A02 S0-41R-002-0A0 BASE ASSY MAIN<EZB,EZN>
A03 S0-41R-001-7A0 BASE ASSY SLED<HRN,UB,KN>
A03 S0-41R-001-8A0 BASE ASSY SLED<EZB,EZN>
-72-
ELECTRICAL TROUBLESHOOTING GUIDE -1/11
1. Power(SMPS) Circuit
A.
No VF+
B.
No 5V_D or 5V_A .
Is 5.2VA section working?
NO
YES
Is oscillation present at the anode of D109?
YES
NO
Replace D109.
No 5.2VA.
NO
Is 5.2VA section working?
YES
NO Is oscillation present at the
Base of Q108?
YES
Replace Q108.
Check R127, 128.
(SHUTDOWN CKT)
Is 5.2V applied to IC102
Pin 1?
NO
Check Fuse(F101).
YES
Is there a DC voltage at the
(+) terminal of BD101?
YES
Is R111 0.5
Ω
?
YES
Replace Q101, 102.
YES
NO
NO
Check L103, C116, 117.
Replace BD101.
(Bridge rectifier)
Replace R111.
-73-
ELECTRICAL TROUBLESHOOTING GUIDE -2/11
2. µ-COM Circuit
A. No Power
POWER ON
Does Bar appear at FLD?
NO
YES
Does Logo appear on the screen?
YES
OK
Do all five Bars appear?
NO
NO
1
Is oscillation of
X501 normal?
YES
NO
Check the oscillation
Are IC503 Pins 14, 28 8 and 29 normal?
YES
NO
A
Check short.
OK
Replace IC501 or IC503.
NO
Is P5901 connected normally?
YES
Reconnect it.
Check power.
(Refer to power)
If power is normal
NO
Refer to Front Part
Is P5901 Pin 24 normal?
YES
A
1
The waveform on A[00:21] and D[00:15] of IC501 normal?
YES
Check short
Replace IC506.
NO
Are IC506 Pins 7, 8 normal?
YES
Replace Main B/D.
-74-
ELECTRICAL TROUBLESHOOTING GUIDE -3/11
B. Audio abnormal
AUDIO ABNORMAL
C. Video abnormal
VIDEO ABNORMAL
Check Audio jack.
YES (If OK)
Check PLL FC of MPEG part.
YES (If OK)
Refer to Audio part.
YES (If OK)
Refer to MPEG part.
YES (If OK)
Replace B/D.
Check Video jack.
YES (If OK)
Refer to Video part.
YES (If OK)
Refer to Encoder part.
YES (If OK)
Refer to MPEG part.
YES (If OK)
Replace B/D.
D. Open/Close abnormal
OPEN/CLOSE ABNORMAL
Check Front.
YES (If OK)
Check the connection of P5901.
NO
Check the connection of MD.
YES
NO
Check IC501 Pins 13, 14.
YES
YES
Refer to SERVO part.
Reconnect it.
-75-
ELECTRICAL TROUBLESHOOTING GUIDE -4/11
E. Picture abnormal
PICTURE ABNORMAL
Check the disc.
Refer to Servo part
If OK
Check PLL IC of MPEG part
YES (If OK)
Check DSP
YES (If OK)
Check MPEG
YES (If OK)
Replace B/D
F. Disc Error
DISC ERROR
Check Disc
YES (If OK)
Refer to Servo part
YES (If OK)
Replace B/D
-76-
ELECTRICAL TROUBLESHOOTING GUIDE -5/11
3. MPEG Circuit
Power is on
Does LG Logo appear on the screen?
YES
Does the moving picture of the DVD Disc play on the screen normally?
YES
Does the moving picture of the video
CD play on the screen normally?
YES
Does the audio sound output normally?
YES
END
NO
Check power & clock.
YES
NO
Is MPEG data signal normal?
YES
NO
OK
Check CD/DVD DSP output signal.
OK
Check MPEG Decoder input signal.
YES
Is error signal normal?
NO Check CD/DVD DSP output signal.
OK
Check MPEG Decoder input signal.
NO
Is MPEG data signal normal?
YES
NO
Check CD/DVD DSP output signal.
OK
Check MPEG Decoder input signal.
NO
Check clock signal
Is Clock normal?
YES
NO Does the audio sound output from MPEG decoder?
YES
Check clock signal
-77-
ELECTRICAL TROUBLESHOOTING GUIDE -6/11
4. Front Circuit (Digitron & key)
START
Power on.
LED ON?
YES
NO
Is oscillation of
X901 normal?
YES
Is Digitron on normally?
NO
YES CD
Do all the buttons work normally?
YES
NO
Check waveform of
IC901 Pin 13.
YES
Check waveform of IC901 Pin 6.
YES
Is waveform of IC901
Pin 76 normal?
YES
NO
Solder defective parts again.
NO
NO
NO
Check Power.
Replace IC902.
Check waveform of IC901 Pin 13.
YES
Replace IC901.
NO
Solder Key part.
Check waveform of IC901 Pin 2.
YES
Replace LED901.
NO
Replace Q901.
Check and replace
R903,R912, R904, R905,
R941, R906, R907.
Does remote control work normally?
YES
Complete repairing Front B/D.
NO Does pulse waveform of RC901 Pin 1 appear?
YES
NO
Is IC901
Pin 24 connected to
RC901 Pin 1 ?
YES
Replace IC901.
YES
Is RC901 Pin 2 5V?
YES
NO
Solder defective parts
Replace RC901.
YES
Re-solder.
YES
Recheck
-78-
ELECTRICAL TROUBLESHOOTING GUIDE -7/11
5. RF/Servo Circuit
A.
CHECK POINT(General)
Does signal goes
"High" to IC201 Pin194 when the power is on?
YES
NO
Does signal pulse input to IC201 Pins 58, 59 when the powe is on?
YES
NO
Does
TTL pulse output to
IC201 Pins 140, 142?
YES
NO
Check "2.µ-COM Part".
Does
33.8688MHz clock input to IC201 Pin 63?
YES
NO
Replace IC201
(IC206 soldering or IC defect).
Is IC201
Pins 83, 84, 88, 89 voltage about 2.2V?
YES
NO
END
Check power circuit.
Replace X301 or IC304
(30MHz clock defect)
-79-
B.
ELECTRICAL TROUBLESHOOTING GUIDE -8/11
No disc
Power on Check loading Part.
Does tray open or close?
YES
NO Push Pick-up to inner track to the end by hand.
Does
PMD03 Pin 7 change high to low?
YES
NO
Pressing the open/close key repeatedly, check the voltage of IC2M1
Pins 13, 14 change
0V to 5V
YES
NO
Does the voltage change at PMD04 Pins 1, 2 more than
2V on the basis of
3.8V?
YES
NO
DECK assembly is defective.
DECK assembly is defective.
(Limit sw) check µ-COM Part.
Replace IC2M1.
Fig.1. SLED Driver waveform
Does the pick-up slide inner or outer track?
YES
NO
Fig.2. Focus Driver waveform
Does the pick-up lens move up and down?
YES
NO
Slide the pick-up to inner track.
Check SLED Driver output.
IC201 Pin 88 IC2M1 Pins 28, 29.
IC201 Pin 88 no output : IC201 is defective
IC2M1 Pin 18 no output : IC2M1 is defective
Check Focus Driver output.
(IC201 Pin 83, IC2M1 Pins 37, 38)
IC201 Pin 83 no output : IC201 is defective
IC2M1 Pins 1, 2 no output : IC2M1 is defective
END
-80-
ELECTRICAL TROUBLESHOOTING GUIDE -9/11
C.
DISC IN
OPEN/CLOSE
FOCUS ON?
YES
NO
Check the focus error moving the lens up and down.
(IC2A1 Pin 42)
YES
NO
Fig.3. FOCUS ERROR waveform
Check IC2A1 Pin 11,12,13,14 in DVD Mode
IC201 no output : Pick-up is defective.
Does the
TTL level change at IC201
Pin 78 and 132 moving the lens?
YES
NO
Replace IC201.
Replace µ-COM or IC201.
Does the disc turn?
YES
NO Check IC2M1 Pin 21, PMD03
Pin 6 turn when the IC2M1
Pin 21 is less than 2.2V.
Check IC201 and IC2M1 when PMD03 Pin 6 is abnormal
IC201 Pin169 is "High"?
YES
NO
Check A
Does the signal pulse appear at IC2A1 Pins
39, 29?
YES
NO
IC2A1 is defective.
NO
Is OK the track jump.
YES
Does the screen appear?
NO Video Part is defective.
Check "5.MPEG Circuit."
Check "7.OSD/Video Circuit."
YES
END
Replace µ-COM part.
-81-
ELECTRICAL TROUBLESHOOTING GUIDE -10/11
D.
CHECK A
Fig.5. RF waveform
Check RF Eye-Pattern.
RF : 1.5-1.6V(IC2A1 Pin 57)
YES
NO
Check IC2A1 Pins 5, 6, 7, 8.
No signal: Pick-up is defective
Is the eye-pattern vivid?
YES
NO Does the sawtooth waveform emit at IC2A1 Pin 41?
YES
NO
Does the 1.6V emit?
YES
NO
Replace IC2A1.
Replace IC201.
Check IC201 Pin84.
No signal at IC201 : IC201 is defective
Check IC201 Pin 162.
Check the clock at the IC201 Pins 28, 30.
Both are normal : IC201 is defective
END
-82-
ELECTRICAL TROUBLESHOOTING GUIDE - 11/11
6. KARAOKE Circuit <EZ>
Start
Insert the Mic jack
Replace VR803.
Check pattern.
NO
Replace the IC4M1.
NO
NO
Is the Mic signal at the
YES
Does the signal change at the IC802
(Echo VR)?
YES
NO
Is the Mic signal at the
NO
Is the Mic signal normal?
YES
Is the Digital signal output at the IC4M1
YES
Replace the VR801,
VR802.
Does the
Mic signal input the IC301
YES
Replace IC301.
YES
Replace IC801.
NO
Replace the mic jack
-83-
DVD MECHANISM PARTS LOCATION <Except EZ>
• Top View (With Tray)
• Top View (Without Tray)
Procedure
Parts Fixing Type
Starting No.
1
1, 2
1, 2, 3
1, 2, 3, 4
1
1, 6
3
4
5
6
7
1, 2, 6
1, 2, 6, 8
8
9
Gear Assembly
Feed
Gear
Middle
10 Gear Assembly
Rack
1, 2, 6, 8,
9
1, 2, 7
1, 2, 7
11 Rubber Rear
12 Frame Assembly
1, 2
1, 2 ,13
13
Up/Down
Belt Loading
14 Gear Pulley
1, 2, 13, 14 15 Gear Loading
1, 2, 7, 12, 13, 14 16 Guide Up/Down
1, 2, 13 17 PWB Assembly
Loading
1, 2, 7, 12, 13,
14, 15, 16, 17
1
2
18
Holder
Clamp
Clamp Assembly
Disc
Plate Clamp
Magnet Clamp
Clamp Upper
Tray Disc
Base Assembly Sled
2 Screws,
2 Locking Tabs
4 Screws,
1 Connector
1 Locking Tabs
Base Main
1 Screw
1 Screw
1 Locking Tab
1 Locking Tab
1 Locking Tab
1 Hook
2Screw
2 Locking Tabs
Disass embly
Figure
4-1
4-1
4-1
4-1
4-1
4-2
4-3
4-3
4-3
4-3
4-3
Bottom 4-4
4-4
4-4
4-4
4-4
Bottom 4-4
4-4
• Bottom View
-84-
Note
When reassembling, perform the procedure in reverse order.
The “Bottom” on Disassembly column of above
Table indicates the part should be disassembled at the Bottom side.
DVD MECHANISM DISASSEMBLY - 1/3 <Except EZ>
PLATE CLAMP
MAGNET CLAMP
CLAMP UPPER
(S1)
HOLDER CLAMP
CLAMP ASSEMBLY DISC
(A)
(S1)
HOLDER CLAMP
(Fig. A)
TRAY DISC
EMERGENCY EJECT HOLE
BASE MAIN
(L1)
(L1)
BASE MAIN
HOLDER CLAMP
(B)
LEVER
BOTTOM SIDE VIEW
BASE MAIN
Fig. 4-2
(A)
Fig. 4-1
1. Holder Clamp (Fig. 4-1)
1) Release 2 Screws(S1).
2) Unhook 2 Locking Tabs(L1).
3) Lift up the Holder Clamp and then separate it from the
Base Main.
1-1. Clamp Assembly Disc
1) Place the Clamp Assembly Disc as Fig. (A)
2) Lift up the Clamp Assembly Disc in direction of arrow(A).
3) Separate the Clamp Assembly Disc from the Holder
Clamp.
1-1-1. Plate Clamp
1) Turn the Plate Clamp to counterclockwise direction and then lift up the Plate Clamp.
1-1-2. Magnet Clamp
1-1-3. Clamp Upper
2. Tray Disc (Fig. 4-2)
1) Insert and push a Driver in the emergency eject hole(A) at the right side, or put the Driver on the
Lever(B) of the Gear Emergency and pull the Lever(B) in direction of arrow so that the Tray Disc is ejected about 15~20mm.
2) Pull the Tray Disc until it is separated from the Base
Main completely.
-85-
DVD MECHANISM DISASSEMBLY - 2/3 <Except EZ>
(L2)
GEAR MIDDLE
GEAR ASSEMBLY RACK
(S2)
(S3)
PICK UP
ASSEMBLY
GENERAL
(C1)
(S2)
GEAR ASSEMBLY FEED
(S2)
BASE PU(OUTSERT)
(S2)
GEAR ASSEMBLY FEED
GEAR MIDDLE
GAER ASSEMBLY RACK
MOTOR ASSEMBLY SPINDLE
RUBBER REAR
PICK UP ASSEMBLY GENERAL
MOTOR ASSEMBLY SPINDLE
Fig. 4-3
3. Base Assembly Sled (Fig. 4-3)
1) Release 4 Screw(S2).
2) Disconnect the FFC Connector(C1)
3-1. Gear Assembly Feed
1) Unhook the Locking Tab(L2) in direction of arrow.
3-2. Gear Middle
3-3. Gear Assembly Rack
1) Release the Scerw(S3)
4. Rubber Rear (Fig. 4-3)
-86-
DVD MECHANISM DISASSEMBLY - 3/3 <Except EZ>
GUIDE UP/DOWN
GEAR LOADING
(L3)
(L6)
GEAR PULLEY
(L4)
(L6)
BASE MAIN
BELT LOADING
(H1)
PWB ASSEMBLY LOADING
(L6)
(C2)
(S5)
BASE MAIN
(A)
(A)
(L5)
GUIDE UP/DOWN
FIG. (A)
FRAME ASSEMBLY UP/DOWN
(B)
(C)
FIG. (C)
(B) (S4)
(A)
(B)
FIG. (B)
GUIDE UP/DOWN
GUIDE UP/DOWN
Fig. 4-4
5. Frame Assembly Up/Down
Note
Put the Base Main face down(Bottom Side)
1) Release the Screw(S4)
2) Unlock the Locking Tab(L3) in direction of arrow and then lift up the Frame Assembly Up/Down to separate it from the Base Main.
Note
• When reassembling move the Guide Up/Down in direction of arrow(C) until it is positioned as Fig.(C).
• When reassembling insert (A) portion of the Frame
Assembly Up/Down in the (B) portion of the Guide
Up/Down as Fig.(B)
6. Belt Loading(Fig. 4-4)
Note
Put the Base Assembly Main on original position(Top Side)
7. Gear pulley (Fig. 4-4)
1) Unlock the Locking Tab(L4) in direction of arrow(B) and then separate the Gear Pulley from the Base Main.
8. Gear Loading (Fig. 4-4)
9. Guide Up/Down (Fig. 4-4)
1) Move the Guide Up/Down in direction of arrow(A) as
Fig.(A)
2) Push the Locking Tab(L5) down and then lift up the
Guide Up/Down to separate it from the Base Main.
Note
When reassembling place the Guide Up/Down as Fig.(C) and move it in direction arrow(B) until it is locked by the
Locking Tab(L5). And confirm the Guide Up/Down as Fig.(A)
10. PWB Assembly Loading
Note
Put the Base Main face down(Bottom Side)
1) Release 2 Screws(S5)
2) Unkool the Loading Motor Connector (C2) from the
Hook (H1) on the Base Main.
3) Unlock 2 Locking Tabs(L6) and separate the PWB
Assembly Loading from the Base Main.
11. Base Main(Fig. 4-4)
-87-
920074
2–11, IKENOHATA 1–CHOME, TAITO-KU, TOKYO 110-8710, JAPAN TEL:03 (3827) 3111
Printed in Singapore

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