Wavetek 1391 50 MHz VXI Pulse generator Owner's Manual

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Wavetek 1391 50 MHz VXI Pulse generator Owner's Manual | Manualzz

O P E R A T I O N A N D

X I A I N T E N A N C E 3 1 A N U A L

Model 1391

I N C L U D I N G S C P I A N D M A T E I C I I L

L A N G U A G E D E S C R I P T I O N S

50 MHz VXI Pulse Generator

Q 1992 Wavefek

This dacumenl conlalns Inlormatlon proprietary to Wavelek and Is provided solely lor lnsrnrment operation and maintenance. The inlormtion In this document may not be duplicated in any manner withoul the prior approval in Wflting lrOm

Wamek.

Wavalek

Instruments Dlvlslon

9045 Balboa A v c .

San Dicgo. CA 921 23

Tel: (619) 279-2200

800-223-9885

Fax (619) 565-7942

Manual Revision B, 4/93

Manual Part NumSer 1006-00-0694

WARRANTY

Wavetek warrants thar all products manufactured by Wavetek conform to published Wavetek specifications and are free from defecrs in materials and workmanship for a period of one (1) year from the date of delivery when used under normal conditions and within the service conditions for which [hey were fur- nished.

The obligation of Wavetek arising from a {Vananty claim shall be limited to repairing, or at its option, replacing without charge, any product which in Wavetek's sole opinion proves to be defective within the scope of the Warranty. In the event Wavetek is not able to modify, repair or replace non-conforming defective parts or components to a condition as warranlied within a reasonable time after receipt thereof,

Buyers shall be credited for their value at the original purchase price.

Wavetek must be notified in writing of the defect or nonconformity within the Warranty period and the affected product returned to Wavetek's factory or to an authorized service center wirhin (30) days after discovery of such defect or nonconformity.

For product warranries requiring return to Wavetek, products must be returned to a service facility desig- nated by Wavctrk. Buyer shall prepay shipping charges, faxes, duties and insurance for products returned to Wavetek for warranty service. Except for products returned to Buyer from another country, Wavetek shall pay for return of' products to Buycr.

Wavetek shall have no responsibility hereunder for any defect or damage caused by improper storage, improper installation, unauthorized modification, misuse, neglect, inadequate maintenance, accident or for any product which has becn repaired or altered by anyone other than Wavetek or its authorized representa- tive and not in accordance with instructions furnished by Wavetek.

Exclusion of Other Warranties

The Warranty described above is Buyer's sole and exclusive remedy and no other warranty, whether written or oral, is expressed or implied. Wavetek specifically disclaims the implied warranties of understanding, oral or wrincn, made by an agent, distributor, representative, or employee of Wavetek, which is not conraincd in thc foregoing Warranty will bc binding upon Wavetek, unlcss madc in writing and exccu~cd an aurhorizcd Uravctek employee. Under no circumstances shall Wavetek be liable for any direct, indirect, special, incidental, or consequentlal damages, expenses, losses or delays (includ-

ing loss of profits) based on contract, tort, or any other legal theory.

Page

1-4,

Paragraph

1.3.7,

Coollng Requlrment:

Replace

"Minimum airflow requirement

k r 10°C rise

is 0.381 mm (.015 in) Hz0 1 1.34

llsec

(24

CFM).'

with

"Minimum airllow requirement for 10% rise is Q

Page 3-20, Paragl

1.3.7, SUMBUS

Operatlon

At

.

..

- L tne Donom

or

. ..

secona

- column, cnange from

Receiver: IN1T:CONT OFF

TR1G:SOUR:ECLTO

. ~ e c e i v e r : OFF

TRIG:SOUR ECLTO

SAFETY FIRST

PROTECT YOURSELF.

Follow these precautions:

Don't touch the outputs of the instrument or any exposed test wiring c a v i n g the output signals. This instrument can generate hazardous voltages and currents.

Don't bypass the VXI chassis' power cord's ground lead with two-wire extension cords or plug adaptors.

Don't disconnect the green and yellow safety-earth-ground wire that connects the ground lug of the VXI chassis power receptacle to the chassis ground terminal (marked with

@

or

a

Don't hold your eyes extremely close to an rf output for a long time. The normally nonhazardous low-power rf energy generated by the instrument could possibly cause eye injury.

Don't energize the VXI chassis until directed to by the instaIlation instructions,

Don't repair the instrument unless you are a qualified electronics techni- cian and know how to work with hazardous voltages.

Pay attention to the WARNING statements. They point out situations that can cause injury or death.

Pay attention to the CAUTION statements. They point out situations that can cause equipmenr damage.

SECTION 1

CONTENTS

SPECIFICATIONS

1.1 THE MODEL 1391 ............................................................................... 1-1

1.2 SPECIFICATIONS ...................................................................................... 1-1

1 . 2.1 Functions .............................................................................................

1.2.2 Operating Modes .

.

.

.

.

.

.

.

.......................................... 1-1

1.2.3 Inputs ................................................................................................ 1-2

1 . 2.4 OU~PUIS 1-2

1.2.5 Pulse Characteristcs ........................ 7-3

1 . 2.6 Muhichannel Operafion .......................................................................

3 GENERAL ................................................................................................ 1-4

1 . 3.1 SCPl Programming ........................................................................... 1-4

1.3.2 VXlbus Interface ..................................................................................

1.3.3 Environmental . ..

..

..............................................

1 . 3.4 Size ...........................

1 . 3.5 Power ............................................................................................... 1-4

1.3.6 Reliability .............................................................................................

7.3.7 Cooling Requirement .

.... .

........................................ 1-4

1.3.8 Safety .............................................................................................. 1-4

1.3.9 EMC ............................................................................................... 1-4

SECTION 2 PREPARATION

2.1 RECEIVING INSPECTION . ..

..

2.1.1 Unpacking Instructions .......................................................................

2.1.2 Returning Equipment ........................................................................ 2-1

2.2 PREPARATION FOR STORAGE OR SHIPMENT .................................. 2-1

2.2.1 Packaging ...........................................................................................

2.2.2 Storage ................................................................................................

2.3 PREPARATION FOR USE ...................................................................

2.3.1 .................... .... .

2-1

2-2

2.3.2 Data Transfer Bus Arbitration ..............................................................

2.4 INSTALLATION ..........................................................................................

2.5 INITIAL CHECKOUT AND OPERATION VERIFICATION ...........................

SECTION 3 OPERATION

3.1 INTRODUCTION ........................................................................................

3.2 CONNECTORS AND LED INDICATORS

.

3 . 3 MODEL 1391 PROGRAMMING ............................... ..

3.3.1 SCPl Command Table ....................................

..

.... ................................

3.3.1.1 Long and Short Form Keywords ...................................................

3.3.2 Command Message Format ............................................................. 3-3

3.3.2.1 Program Message Unit .

.

.

.

.

3.3.2.2 Program Message .......................................................................

3-4 3.3.2.3

3.3.2.4

Program Messzge Delimiters .....................................................

Parameter Forms .

3.3.2.5 Program Message Terminators ..................................................

3.3.2.6 Queries ......

3 . 3 . 3 Model 1391 SCPl Commands .

3-4

CONTENTS (Continued)

3.3.3.1

3.3.3.2

3.3.3.3

3.3.3.4

3.3.3.5

3.3.3.6

3.3.3.7

3.3.3.8

CALibrate Subsysiem ...................................................................

TEST Subsystem ....................... .

3-7

INlTiate Subsystem ...................... .

........................................ 3-8

OUTPut Subsystem ...................................................................... 3-8

RESet Subsystem ..............................................

.

. . . . . . . . . . 3-8

SOURce Subsystem .....................................................................

SYSTem Subsystem ....................

3-9

TRlGger Subsystem .................................................................... 3-12

3.3.3.9 DlAGnostic Subsystem ................................................................ 3-13

3.3.3.10

3.3.4

STATUS Subsystem

IEEE 488.2 Common Commands

.

.

.

3-14

3.4 MODEL 1391 OPERATION ........................................................................

3.4.1 Outpur Terminations ............................................................................

3.4.2 Input/Outpul Protection .......................................................................

3.4.3 PowerOn/ResetDefaults ....................

3.4.4 Continuous Operation ........................

.

............................................

3.4.4.1 Frequency/Period Parameters ......................................................

3.4.4.2

3.4.4.3

Pulse Parameters ......................................................................... 3-19

Output Levels .......................... 3-19

PulseISquare Functions ................................................................ 3.4.4.4

3.4.5 Marker Operation ..................................... ........................................

3.4.6 SUMBUS Operation

3.4.7

.

3-20

PAM Operation ....................................................................................

3.4.8 Triggered Operation

3.4.8.1

3.4.8.2

3.4.8.3

3.4.8.4

Level and Slope Parameters ............................. ................

External Trigger Inpul ................................................................ 3-23

Internal Trigger ............................ .

.......................................... 3-23

BUS Trigger Commands ..

..

..

..

..

..

..

3.4.8.5 VXI Trigger Bus Input

3.4.9 Gated Operation ....................... 3-24

3.4.9.1 External Width Operation

................... .

3.4.10 Rurst Operation ...................................................................................

3.4.1 1 MasterJSlave Operation ............................ .

3.4.12 Status Commands .......................................................................... 3-26

SECTION 4 CIRCUIT DESCRIPTION

4.1 INTRODUCTION ........ ........

.,

...............................................................

4.2 VXI INTERFACE BOARD

4.2.1 VXlbus Overview .................................................................................

4.2.2 Interface Board ....................

4.3 PULSE GENERATOR BOARD

-

DIGITAL CIRCUITS ................................. 4-3

4.3.1 Interconnect and Power Distribution ...................................................

4.3.2 Digital Interface and Data Registers

.

.

4-5

4.3.3 Frequency Synthesizer .......................................................................

4.3.4

4.3.5

4.3.6

Trigger Amplifier .................................................................................

VXlbus TTL Trigger Receiver ..............................................................

VXlbus ECL Trigger Receiver ........................................................... 4-8

SECTION 5

CONTENTS (Continued)

Trigger Source Selector

Mode Control LogrcIBurst Counter ............................................... 4-8

Gatable Oscillator/Divider 4-9

PGEN Source Selector ..................................................................... 4-10

Delay and Width One-Shots ................................................................

Pulse Generator ............................. .

Output Mode Selector ........................................................................

Sync Source Selector ....................................................................... 4-12

Sync Output Driver ...................

...............

............................................ 4-13

VXlbus E C W L Trigger Drivers

Delay - Width

-

......................

Frequency Autocalibration

.

..........................

4-73

.

.......... 4-13

............

4-13

4.4 PULSE . ............................ 4-73

Main High-speed Analog Signal Path ............................................. 4-14

Level Shift

Current Switch .

.

.

.

.

.

. .

Timing Capacitors ......................................................................... 4-15

Trapezoid Shaper ............................................................................. 4-16

Multiplier .................... .

4-17

Output Amplifier 4-17

SUMBUS Driver .................................................................................. 4-17

Control Voltage D to A Converters ......................................................

Amplitude Conrrol/PAM Circuitry ................................................. 4-18

Transition Control Currenl Sources ...............................................

Delay - Width One-Shot Control ..........................

.

Relay Driver ..................................................................................... 4-19

Power Oscillator ......................

.

Charge Pump ................................................................................. 4-19

AutoCal/Buill-In-Test Circuitry ..................... .

CALIBRATION

5.1 FACTORYREPAlR .....................................................................................

5.2 CALIBRATION ..........................................................................................

5.3 REQUIRED TEST EQUIPMENT ......................................................... 5-1

5.4 PERFORMANCE VERlFlCATlON PROCEDURE ........................................

Preliminary Tests .................................................................................

Quick Functional Test .................................... .... .................................

Sync Waveform Characteristics Test .............................................

5-2

5-2

Gated Mode Test .............................................................................. 5-2

Burs! Mode Tesr

Pulse Amplitude Accuracy Test .......................................................... 5-3

Pulse Width Accuracy Test .

Pulse Delay Accuracy Test ......................

.

.

.

......................... 5-4

Function Delay Test .......................................................................... 5-5

Pulse Output Transition Times Accuracy Test

Pulse Output Aberrations Test ..................................................... 5-5

Trigger Level Test ...............................................................................

Synthesizer Frequency Tesr ..............................................................

SECTION 6

CONTENTS (Continued)

5.4.15 Burst Gatable Oscillator Frequency Test ............................................

5.4.16 External Trigger Frequencies Test ......................................................

5.4.17 Trigger Source Test ............................. .

........................................ 5-7

5.4.18 Trigger Output Mode Test ...................................................................

5.4.19 MasterISlave Tesl .

5.4.20 SUtvlBUS Test ................................................................................ 5-8

5.4.21 PAM Input Test ....................................................................................

5.5 ALIGNMENT PROCEDURE .......................

.

.

5.5.1

5.5.2

Self Calibration ....................................................................................

Semi-Automated Procedure ..............

5.5.3 Preparation ..........................................................................................

5.5.4 Connector Termination ........................................................................

5.5.5 Alignment Procedure ..........................

TROUBLESHOOTING

6.1 FACTORY REPAIR ..................... .

6.2 BEFORE YOU START ........................................................................... 6-1

6.3 REQUIRED TEST EQUIPMENT .................................................................

6.4 ISOLATING A PROBLEM .................... .

6.5 TROUBLESHOOTING ....................... .

6-2

Ampl~tude .......................

Trailmg Edge DAC Error Bit 1

................... .

...........................

Leading Edge DAC Error Bit 2 ............................................................

Limit Amplifier Error Bit 3

SUMBUS Error Bit 4

...........................

Delay Gatable Oscillator Error Bi! 5 ....................................................

Width Gatable Oscillator Error Bit 6 ...................................................

25-50 MHz Gatable Oscillator Error Bit 7 ............................................

BUS Error Error Bit 14

.

.

Abnormal LED State ......................

,

.................................................. 6-4

Pulse Board Digital Interface .

.

, ,

Autocal/Built-In Test ........................

. . . . . . . . . . . . . . . . . . . 6-4

Frequency Reference .....................

Frequency Synthesizer ...................

.

TRIG IN

.

Trigger Source SelecLor

TTL/ECL Triggers to Backplane ..........................................................

TTUECL Triggers from Backplane ......................................................

Mode Control LogiclBurst Counter ............................................ 6-5

Amplitude Control and Multiplier

PAM IN ............................................................................................. 6-6

Transition Time Generator ................................................................ 6-6

Trapezoid Shaper .................... .

....................................................

6-7

Output Power Supplies ..................................................................

Output ArnplifierIPULSE OUT .

SECTION 7

CONTENTS (Continued)

PARTS AND SCHEMATICS

7.1 DRAWINGS

7.2 ERRATA ..................................................................................................... 1

7.3 ORDERING PARTS ....................................................................................

APPENDIX

APPENDIX A: MATEICIIL PROGRAMMING .............................................

APPENDIX B: SCPl COMMAND TREE .................................................. 8-1

APPENDIX C: SELF CALIBRATION ......................................................

APPENDIX D: SELF TEST ...................................................................... D-1

APPENDIX E: SCPl CONFORMANCE INFORMATION ........................... E-1

Table 2-7

Table 3-1

Table 3-2

Table 3-3

Table 3-4

Table 3-5

Table 5-1

Table 6-1

Table 6-2

Table 6-3

Table 6-4

Table 6-5

Table 6-6

Table 6-7

TABLES

Tesl Equipment and Tools ....................

Model 1391 Front Panel .........................

....

...................... 3-3

Model 1391 Command Summary 3-5

Error Messages. ......................................................................

IEEE 488.2 Common Commands

.

................. 3-76

Input and Output Impedances ................................... .... . 3-16

List of Test Equipment ........................ .

5-1

List of Test Equipmenl and Tools

Problems Identified by 'TST

......................................... 6-1

....................... 6-2

Problems not Identified by 'TST ....................................... 6-2

Trigger Source Selector Control Lines ....................................

Sync Selector Control Lines ....................................................

Transition Timing Range Capacitor Selection ........................ 6-6

Figure 1-1

Figure 1-2

Figure 2-1

Figure 2-2

Figure 3-1

Figure 3-2

Figure 3-3

Figure 3-4

Figure 3-5

Figure 3-6

Figure 3-7

Figure 3-8

Figure 4-1

Figure 4-2

Figure 4-3

Figure 4-4

Figure 4-5

Figure 4-6

Figure 4-7

Figure 4-8

Figure 4-9

Figure 4-10

Figure 4-1 1

Figure 4-12

Figure 4-1 3

Figure 4-1 4

Figure 4-15

Figure 4-16

Figure 4- 17

Figure 5-1

Figure 6-1

Figure 6-2

Figure 6-3

Figure 6-4

Figure 6-5

Figure 6-6

Figure 7-1

ILLUSTRATIONS

Model 1391 50 MHz VXI Pulse Generator

..............................

1-0

Definitions of Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Set the Logical Address ........................ .

2-2

Bus Arbitration Level Jumpers ................................................

Model 1391 Front Panel .

.

.

.

.

Output Termination ................... .

.......................

3-2

... 3-17

Model 1391 Basic Operation Setup

......................................

3-18

Continuous Waveform Characleristics ................................. 3-18

SUMBUS Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

Triggered Waveform Characteristics .....................................

Synchronous Gate Waveform Characteristics ........................ 3-24

External Width Waveform Characteristics

Model 1391 Pulse Generator Overall Block Diagram .............

3-25

4-1

VXlbus Interface Board Block Diagram ................................ 4-2

Pulse Generator Digital Circuits Block Diagram .....................

4-6

Dual Modulus PLL ................................................................... 4-7

Mode Control Logic

Mode Control Logic

-

Gated ................................................ 4-9

-

Burst

Gatable Oscillalor ........................... .

4-9

Divider .....................................................................................

Analog One-Shol .

....... .

4-11

Digital One-Shot .

.

.

.

.............................. 4-11

Simplified Pulse Generator .

.

.

............................

Pulse Generator Analog Circuits Block Diagram .................... 4-14

Simplified Upper Level Limiter ...............................................

Simplified Trapezoid Shaper

Simplified SUMBUS Driver ......................................................

Simplified Charge Pump Circuits ......................................... 4-19

Test Points and Adjustments

Delay One-Shot Troubleshooting Flow Chart ......................... 6-8

Width One-Shot Troubleshooting Flow Chart

Gatzble Oscillator Troubleshooting Flow Chart

..

6-15

Frequency Synthesizer Troubleshooting Flow Chart

Burst Mode Troubleshooting Flow Chat ................................

Sync Selector Troubleshooting Flow Chart .............................

Surface Mount Parts Pjn-Outs .................................................

PULSE OUT

Specifications Section 1

1.1 The Model 1891

The model 1391 is a 1 mHz to 5 0 MHz "C" size VXI

Programmable Pulse Generator. 11 can generate single, double, and delayed pulses with programmable period, width, delay, riselfall uansitions, and output

IeveIs. T h e generator operales as a continuous, triggered, gated o r burst pulse source up to 5 0 IMHz.

Additionally, the Model 1391 can be programmed for a square wave function (-50% time symmetry) up to with 4 digit resolu~ion,

2000 seconds, and riselfall transition times setrable from 5 ns to 5 0 ps.

The pulse ouput amplitude may be specified as upper and lower levels, which can be programmed in a

+16 V window (z8V into 50R terminalion). Peak to peak amplitude, upper level value minus lowcr level value, is continuously variable in 10 mV steps from

150 mVp-p to 16 Vp-p (50R). The pulse amplitude

(upper, lower, o r both) may be modulated (PAM) with an external signal.

Control of the pulse generator adheres to the SCPI

(Standard Commands for Programmable Instruments) format Version 1992.0. February 1992 (refer to the

SCPI manual for further information). SCPI is an industry standard language for remote instrument programming. Using any manufacturer's VXI chassis, the Model 1391 can be controlled using the SCPI language and the appropriate controller.

multiple pulse generators may be linked and operated together inside one VXIbus chassis. Series operation is provided by full support of the VXIbus SUIMBUS.

A signal programmed at the output may be sent to the

SUMBUS, o r signal present at the SUMBUS may be summed into the model 1391 oulput. In paraIlel operation, model 139 1's may be slaved to a master clocWtrigger bus on thc VXIbus backplane to create a multichannel pulse generator.

The model 139 1 has extensive self-adjustment utilities built in. Calibration constants are maintained in non- volatile memory.

Programmable single. double o r deIaycd pulse and fixed (-50%) duty cycle square wave.

1.2.2

Operntlne

Modes

Contlnuous:

Pulse period generated continuously internal to the modcl 139 1 at programrncd frequcncy/pcriod. Sc- lecrcd pulsc waveform is continuously outpul at

PULSE OUT with programmed pulsc characteristics.

Pcriod riming signal appears a[ SYNC O U T (if cnablcd) and may be sclectcd for output to the backplane. Pulsc periods programmablc up to

25 MHz in double pulse. 5 0 lMHz in single o r delaycd pulse, and 100 IMHZ in square wavc. Pulse Amplitude

Modulation may be enabled for cxternal signal at

PAM IN.

Triggered:

As above for Continuous mode, except that p u k e period generation is disabled. Output quiescent until triggered by an external signal at TRIG IN. a

TTLTRG or ECLTRG signal, internal trigger fre- quency, or a VXIbus command. then generates one pulse period with [he programmed pulse waveform and pulse characteristics. Triggered pulse periods operate to 25 IMHZ in doubIe pulse. 5 0 MHz in single o r delayed pulse and square wave.

Gated:

Similar to rriggercd mode except output condnucs for the duration of gate signal. T h e last pulse pcriod started is complctcd.

Burst:

Similar to triggered mode except programmable number of pulse periods in a burst. Burst length, initiated by the [rigger signal, is programmable belween 2 and 10,000,000 cycles.

Trig In:

Front panel BNC input for extcrna1 triggering signal.

Variable trigger level control accepts TTL or variable amplitude bipolar signals. In addition, any of the rrigger lines on the VXIbus backplane can be sclecred as the trigger input, see Trigger Inpur (from VXI

Backplane). TRIG IK is protec~ed input range.

Variable Tripper Level.

Range:

Resolution:

Accuracy:

Minimum input level:

Maximum input level.

50 m?,

+ 5C3 mV

750 mVpp

Pulse Output:

Front panel BNC output, supplies the I50 mVpp to

50 MHz. Programmable on or off (Zoff > 500 k R ) .

Output is protected against short circuits.

Source lm~edance: 5 0 0 . h'OTE: Ylhen overload current

IS delecled, the prolection an overload, turn the power of!, wait two minutes, and turn the posver back on.

Sync Output:

T T L lcvel pulsc (active high) inlo 50R. Program- mable as cithcr thc pulsc pcriod (IMARKc~:TYPE

CLOCk) or as a copy of the cxternal gating signal

(MARKcr:TYPE GATE). Whcn in continuous mode, thc Sync Output is an approximarc 50% duty cycle squarc wave dcfining thc timing o f a pulse period up to 5 0 MHz. For frcqucncics >50 lMHz and up to

100 MHz, the Sync Output operates as a clock source. lnpul im~edance: rlkR shunled by s10 pF

A 0 0 ps: for 2750 mVpp square wave inout with 4 0 transitions.

PAM In:

Front panel BNC connector. used to externally PuIse

Amplitude Modulate the model 1391. PAAM modula-

[ion scale factor is set so that a 1 volt input at this connecror will result in a 2 volt change in upper/lower level amplitude at the PULSE OUT connector. Input is prorccted to 250 V inputs.

In triggered mode (1NITiatc:CONTinuous OFF), thc

Sync Output ( M A R K e r T Y P E CLOCk) is a copy of the triggering signal. The Sync Output (MARKer:

TYPE GATE) is valid only in burst mode (TRIGger:

COUNt <value>, where "value" is greater than 1) or in gated mode (TR1Gger:GATE ON). The SYNC

O U T BNC is short circuit protecred.

Band-widlh:

Accuracy: dc l o >20 kHz

~ 5 %

SUMBUS lnput

(from VXI

Backplane):

Analog signals on the VXIbus SULMBUS line may be summed into a model 1391 PULSE OUT with a fixed scale factor. A full-scale PULSE OUT signal of

16 Vpp requires a 2Vpp (80 mApp driving 2 5 R ) input signal at the SUlMBUS line. SUMBUS receiver specifications are:

Scale laclor: 8 V N

Accuracy:

Input impedance,

Band#jd:h:

2

(64; + 2122 mV + 2.5 mA)

>I0 kR in parallel with c20 pF

> 50 MHz

Trigger lnput

(Irom

VXI Backplane):

Any one of the eighl VXIbus TTLTRG lines or either of thc two ECLTRG lines may be selected as the [rigger input for the model 139 1. When a TTLTRG line is selected, the rriggering signal on that line is limited

LO a maximum of 12.5 MHz by [he VXIbus specification.

Timing:

Transilion lime:

50% point 01 rising edge delines Ihe start of a pulse period. Conliguration dependent delay (see Trigger Latency,

Figure 1-2 and Ihe lable below) lollowing lrigger event. r5ns with 3 lee1 RG-58 50R coax cable lerminared into 5012.

Trigger

-

1,. see Figure 1-2)

Configuration* Trigger Latency

Extcmal Triggcr Input**

Trigger ~Modc

Burst Mode, Pulse

Burst kfodc, Squarc

ECL Trigger** typically 58 ns typically 83 ns typically 63 ns typically 52 ns

TTL Trigger typically 52 ns

' Trigger delays rezsured lor 2 single pulse.

22 ns xhen unit is configured as the tiasler.

SUMBUS Oulput (to VXI Backplane):

Pulse output signals from the mode1 1391 may be summed onto the VXIbus SUMEUS line with levels proportiona1 to the pulse output. A full-scale PULSE

OUT signal of 16 Vpp results in an 80 mApp signal driving the SUAVEUS line. SUMBUS driver specifi- cations are:

Scale lactor:

Accuracy: load Impedance:

Oulpul impedance:

5 m W

+

(6% + 2.5 mA)

25R 2 2 % (VXI Specification)

>10

kn

in parallel w ~ t h p F

Bandwidth:

Pulse Period:

Range:

Pulse Oul:

Sync Out:

Resolulion:

Accuracy:

> 50 MHz (limited by Ihe backplane).

Trlgger Output (lo VXI Backplane):

Any one of the eight VXIbus TTLTRG lines or either of the two ECLTRG lines may be selected to be driv- en by a signal from the model 1391, The internal form may be selected to be output. When a TTLTRG line is selected, the triggering signal on that line is limited to a maximum of 12.5 ,MHz by the VXlbus specification.

1.2.6 Pulse Characterl8tlc8

See Figure 1-2 for an illustration defining the various pulse characteristics. Pulse functions are programma- ble using operating mode, pulse period (frequency), width. delay, transition times, and amplitude levels.

NOTE: All pulse characlerislics specilicalions require high-quality 50R cable (s3 a high-frequency 50R (r I:V) lerminalion at the far end of lhe cable lrom Ihe PULSE OUT B t K .

20 ns

to

1000 s ( 1 mHz to 50 MHz)

10 ns lo 1000 s (1 mHz to 100 MHz)

4 digits. limiled by 1 mHr

Same as the VXlOus CLKlO reference in cafltjnuws morle

( Z

0.01% Typical). z

2% of sening in non-conlinuous mcdes.

Pulse Width:

Range:

Resolulion:

Accuracy:

Jilte::

Oury Cycle:

10 ns to 1000

s

(up to 2CZO s with external trigger).

4 digrls. limited by 1C0 ps

+ ( I % t

2 ns) t

(0.05% + 100 ps)

95% limited by min. off-lime 01 10 ns.

Pulse

Delay:

Range:

Resolution:

Accuracy:

Jiller.

Duly Cycle:

0 ns to 2000 s

4 digits, limited by 100 ps

+

(1% + 5 ns); transilion limes set to minimum.

~(0.0546 I00 ps)

95% limited by minimum olf-time ol

12 ns.

Rise

and Fall Transllions:

Range:

Resolulion:

Accuracy:

Aberralions (Vpp):

5 ns to 50 p

4 digits. lirniled by 1CO ps

~ ( 5 % ns) c (5% ol Vpp + 20 mV)

NOTE: The n l i o ot rise lime lo fall lime may not exceed

10: 1. For Ampliludes > 12 Vpp lhe Aberralions specilicalion applies lor /ransitions r 7 ns.

Upper and Lower Levels:

Range:

Resolution: z B V

10 mV

Vpp Amplllude (Upper

Level

-

Lower Level)

Accuracy:

Vpp r 0.5

Vpp < 0.5

+ (2% 01 selting t

50 mV)

= ( 2 % 01 selling t

25 mV)

Onset ((Upper

Level

+ Lower Levelfl)

Accuracy: r ( 2 1 ol selling t

50 mV)

NOTE: The minimum amplilude (upper - lower) may not be less than f50 mVpp. Pulses less than 500 mVpp are reslricted to a + 2V cindow.

1.2.0 Multlchennel Operatlon

Multiple 1391 modules may be operated together in series or in parallel to create a multichannel pulse generator.

Serles (SUMBUS) Operatlon

A module may be selected to drive the SUIMBUS. reccive from the SUIVBUS. o r disconnect from thc

SUMBUS. AIlows the signal from one module to be summed with rhc signal at the output of anothcr.

Allows for morc complex waveform generation than providcd with simple pulsc gcncrator features, such as

Parallel (MaslerlSlave) Operation

Up to 10 model 1391 modules may be operated in hfaster/Slave configuration within a VXIbus chassis.

This mode of operation uses the high bandwidth and tight timing of the ECL trigger lines to couple the start of triggered pulse periods of Slave modules to

[he trigger output of the Master module. Sets the

"start of pulse period" (1,) timing points of adjacent modules into close agreement. Modules further away will have a timing delay of approximately 0.5 ns per slot, dependent upon the VXIbus chassis backplane.

1.8 GENERAL

1.8,l 8CPI Prograrnrnlnu

Conforms

LO

SCPI Version 1992.0 (see Appendix E) and IEEE-488,2 standard mandated commands. Root level commands include:

Alrliude:

Operallnp: Sea level l o

Storale: Sea level to

Relalive Humidity (non-condensing):

10,OCO

0°C to +lO°C:

+30°C:

+40°C:

+4t°C to +50°C: not controlled.

95 25% flH rnax.

75 + 5% RH max.

45

2 rnax.

Vibralian:

Shock:

Bench Handling:

0.013 in., 5 lo 55 Hz, 2g rnax.

Non-operaling. 40 g, 9 rns hall-sine.

Non-operating, 4 inch or point o l balance drop, any lace, solid wooden surface.

1.8.4 8 h

Dimensions:

Weight;

Single slol, 'C' size VXI module.

1.65 (3.63 3.64 kg

DlAGnostic OUTPut

STATUS

INlTiate

TEST

SYSTem

CALi brate

SOURce

TRlGger

RESet

1.8.2 VMbus Interlace

Message Based Dcvice (MBD), 256 byte input buffer.

A 16lA24 D16/D24 Mastcr, A16lA24 D I6m24 Slave;

VXIbus Instrument Protocol (I);

VXIbus IEEE-488.2 Instrument Protocol (14);

Event Generator. Response Generator;

DC (DynamicalIy ConfigurabIe) Device.

The model 1391 supports all Word Serial Commands specified in the VXIbus System Specification (Rev.

1.4), Tables E.l and E.2 for the above subset/protocol classification.

1.8.8 Envlronrnental

Temperature Range:

Operating:

Storage:

Yiarm-up Time:

Scecificalions apply 04C to 50°C, when calibrated al23'C + 3%.

-40°C to (RH no! cootrolled).

30 rninules tor specilied operation, except stablllty speclticallons require

60 minules.

1.8.6 Power

Total:

Voltage t 2 4 Vdc t 1 2 Vdc

+5 Vdc

-2 Vdc

-12 Vdc

-24 Vdc

< 47 watts

Peak Current

0.4 A

1.0 A

1.0 A

1.1 A

1.8 A

0.8 A

0.4 A

Dynamlc Cunent

0.1 A

0.2 A

0.1 A

0.1 A

0.1 A

0.3 A

>22,000 hours MTBF at 2S°C, ground benign.

MIL-HDBK-217 calculation at 50% component stress.

Coonno

Requlrernent

Within a VXI mainframe with cooling air. Minimum airflow requirement for 10°C rise is 0.381mm

(.015 in) H,O at 11.34 Vsec (24 CFM).

1.8.6 8nlety

Designed and tested to MIL-T-28800D, UL-1244, and the VXI System Specification, Revision 1.4.

1.8.0 €MC

Designed and tested to MIL-STD-461C. Part 7, RE-

02, and VXI System Specification, Revision 1.4; RE,

RS, CE, CS.

TRIG w

I/

PRESET TRGGER LEVEL. POS!TNE SLOPE

MORMAL

PULSE

OUT

I

'

I

I I

I

I

1

COMPLIMENTARY

PULSE OUT

I

TIME REF:

I I

1 I b

I 1

I

I

12 b

I,

I1

-

-

-

UL -UPPER LEVEL VOLTAOE

L L

PA

TL

-

-

-

-

= (UL

=

1, t l

-

LL)

- b

PD

-

=

PW

LE

TE

-

-

-

0s-OVERSHOOT

US- UNDERSHOOT

A s s -ABERRATIONS ( D L - ~ k )

-

( 0 s + USYPA. 100%

Figure 1.2 Definitions of Pulse Characterlslics

-

LL. TOP LINE

Preparallon Secllon 2

2.1 RECEIVING INSPECTION

Check the shipment at the time of delivery and inspect each box for damage. Describe any box damage and list any shortages on the delivery invoice.

2.2 PREPARATION FOR STORAGE OR SHIPMENT

1. Unpack the boxes. Unpack the boxes in a clean and dry environment. Save all the packing material in case the instrument must be returned for repair.

2. Inspect the shipment for damage. Inspect the equipment carefully for any signs of mechanical damage regardless of the condition of the shipping boxes.

3. If necessary, file a clalm. In the case of mechani- cal damage, call the shipper immediately and start the claim process.

4. Cell Wavetek. Call Wavetek's Customer Service representative (619 279-2200) to inform them that the shipment arrived damaged. Please be prepared to provide

a

detailed damage report.

If at all possible. always use the original shipping container. However, when using packing materials other than the original, use the following guidelines:

1. Wrap the Model 139 1 in ESD sensitive packing material.

2. Use a double-walled cardboard shipping container.

Protect all sides, including the top and bottom, with shock absorbing material (minimum of 2 inch thick material) to prevent movement of the Model 1391 within the container. Seal the shipping container with approved sealing tape. Mark "FRAGILE" on all sides, top, and bottom of the shipping container.

The Model 1391 should be stored in a clean, dry environment. In high humidity environments, protect the Model 1391 from temperature variations that could cause internal condensation. The following environ- mental conditions apply to both shipping and storage;

Follow these steps when you return equipment to

Wavetek:

1. Save the packing material. Always return equipment in its original packing material and boxes. If you use inadequate material, you'll have to pay to repair any shipping damage as carriers won't pay claims on incorrectly packed equipment.

2. Call Wavetek Customer Servlce and ask for a r e t u r n authorization. The Wavetek Customer

Service representative (619 279-2200) will ask for your name, telephone number, company name, equipment type, model number. serial number, and a description of the problem.

3. Peck and ship the equlprnent.

Temperature

Relarive Humidify

Alrirude

Shock

-40°C to +71°C not controlled, non-condensing.

<15000 ft

< 40g

2.3 PREPARATION FOR USE

Paragraph 2.3 covers the following topics:

Logical Address Selection

Data Transfer Bus Arbitration

Installation

The VXI chassis Resource Manager identifies units in the system by the unit's logical address. The VXI logical address can range from 0 addresses 0

Address

255 permits the Resource Manager to dynamically address the unit based on the unit's VXI chassis slot.

To change the ?vIodel 1391's logical address, use the eight position DIP switch (figure 2-1) accessible from

[he side panel. The Model 1391 uses binary values (2' to 2')

LO set the address using the active low address switch. This means the OFF position represents a logical 1. Conversely. an ON position represents a logical 0. Switch position number one is the least significant bit of the address, Insert A in figure 2-1 illuslrates a switch set to a logical address of 3.

Wavetek ships the Model 1391 with a logical address of 255 for Dynamic Configuration. Refer to insert B in figure 2- 1.

The Model 1391 has VMEbus Mastership capability.

This means the Pulse Generator, when enabled, sends

Responses and Events as signals to its Commander.

The Model 1391 cannot drive the interrupt lines.

The Model 1391 is configured as a level 3 requestor by the factory. The level 3 Bus Request and Bus Grant lines are used (BR3*. BG3IN*, and BG30UT*), The orher Bus Grant lines arc daisy-chained by jumpers.

The VMEbus specifications describe three priority schemes: Prioritized, Round-robin, and Single level.

The Prioritized arbitrafion assigns the bus according to a fixed priority scheme where each of four bus lines has a priority from highest (BR3*) to lowest (BRO*).

Round-robin arbitration assigns the bus on a rotating basis. Single level arbitration only accepts requests on

BR3*.

If a different requestor level is required, the jumpers must be changed. The following instructions and figure 2-2 will aid in reconfiguring the Model 1391 to

Figure 2-1. Set the Logical Address

I

I

I

FACTORY

S W I N G

1

12 z g =

2

0

$ Cj

ARBITRATION

1

,

E 6 6 h s g # i g

LEVEL

I I

Flpure 2-2. Bus Arbltrallon Level Jumpers

PREPMON

2-3

Table 2.1.

Test

Equlpment and Tools

a new level. Refer to the VkIEbus specification for more information on 'dara rransfer bus arbirra~ion'.

CAUTION

The Pulse Generator contains CMOS devices which a r e sensitive to static electricity, When performing the bus arbitration level change, static elec- tricity dIschargestrapsshould be worn.

Remove thc four flat hcad screws on the Model

1391 lcft sidc pancl. rcmove thc panel.

Rcmovc the four pan hcad scrcws holding the VXI

Interface card ro the main Pulsc Generator board.

Slowly and gently lift thc VXI Intcrfacc card up from thc Pulsc Generator board. Considcrable force may be required as there arc four connectors bctween the two boards with a total of I36 pins.

Do not use a metallic prying tool.

Change the data transfer bus arbitration jumpers to the dcsired Icvcl. Refer to figure 2-2.

Carefully install the VXI Intcrfacc card onto the

Pulse Gcncrator board. Install thc four pan hcad scrcws, the sidc pancl and the four flat head screws.

Equlprnent

Oscilloscope

Signal Source

BNC 5OR Feed- through (2ea)

BNC Coax

Cablc (3ca)

Comments t--- r

1

Frequency: 10 kHz

I

Outpul: r 1 V sine wave

Accuracy: 0.5%

Power: 2W

RG58U, 3 ft, lcngth

2.4 INSTALLATION

The instrument will be installcd in a VXI mainframe in any slot except slot 0 (zero). When inserting the instrument into the mainfrnrnc, it should be gently rocked back and forth to scat the connectors into the backplnne receptacles. The ejectors will be at right angles to the front pancl when thc instrument is properly scatcd into thc backplane. The two captive screws above and bclow the ejectors are used to secure the instrument into the chassis.

LED

Run

Fail

MODID

A16

A24

Normal Result

On

Off

Flashes

Flashcs

Off

2) Send: '

If response = 0, continue

If response 0, decode error value

(see Appendix D).

2.6 INITIAL CHECKOUT AND OPERATION

VERIFICATION

This procedure provides the operator, service techni- cian, receiving inspector, etc. with a quick method of verifying the functional operation of the Model 1391.

This procedure does not test the unit's specifications.

This procedure assumes the Model 1391 is properly installed in a "C" sizc VXI chassis with a VXI control- ler in slot 0. Required tools and test equipment are given in tabIe 2-1.

Bccause each step in thc procedure is dcpcndent on the preceding step, start with step 1 and continue through to the end. Do not send any command unIcss specifi- caIly instructed to do so within the procedurc.

I) Verify proper LED operation during instrument power-up

NOTE

Ifrhe test fails on a new o r newly fac- tory repaired unit, call Wavetek Cus- tomer Service at 619R79-2200 or FAX

61 9/565-9558.

3) Connect two coax cables between the Model 139 1

PULSE OUT and SYNC OUT connectors and the

oscilloscope. Use a 5OR terminator on each cable. Connect the SYNC OUT ro CHI and the

PULSE OUT to CH2, and synchronize the oscillo- scope internally from CHI.

Send: o u t p o n : : m a r k o n

Verify the SYNC waveform on CHI is a 1 MHz,

TTL lcvel square. Verify rhc pulse waveform on

CH2 as follows:

Verify the double pulses now have a leading transition time of 100 ns, a pulse width (between the 50% points) of 800 ns, a trailing transition time of 300 ns, and that the second is delayed from the first by 2 ps,

NOTE

Numeric values should nor be verified for accuracy in rhis operafional check- our, bur should be checked visually on

[he oscilloscope trace for approximare accuracy. Use rhe Performance Verifi- carion Procedure in Secrion 5 of rhis manual, if required, ro resr rhe unir to specijicarion. single pulse; 1 ps period

+2.5 V upper and lower levels

250 ns pulse width s 5 ns leading and mailing transition times

Verify the various pulse functions (waveforms) and pulse characteristics:

Send: p u 1 s : d e l 6 0 0 e - 9

Verify the single pulse is now delayed 600 ns relative to the rising edge of the SYNC.

Send: p u 1 s ; d o u b o n

Verify double pulses with the second pulse delayed 400 ns relative to the rising edge of the

SYNC.

Send: f u n c s q u

Verify a 50% square wave output coincident with the SYNC.

Send: f u n c p u 1 s ; f r e q 2 0 0 e 3

Verify the waveform returns to double pulse, and that the waveform period (determined by the sync) has increased to 5 ps.

Send: p u 1 s : d o u b : d e l 2 e - 6

5) Verify the output levels as follows:

Send: v o 1 t : h i g h 4 : l o w - 2

Verify the output levels change from i 2 . 5 V to a low lcvel of -2V and a high level of +4V.

6) Set the extcrnal gcnerator up for a + lV, 10 kHz sinc wave. Connect the external signal to thc

Model 139 1 TRIG IN connector.

Send: i n i r : c o n t o f f r r i g : l e v 0 ; s o u r e x t

Verify a double pulse with all of the characteris- tics set up in steps 3 and 4, excepr that the pulse period is now triggered by the 10 kHz rate set by the external signal.

Send: t r i g : c o u n 3

Verify the double pulses are now triggered for 3 periods (six pulses in all) at the 10 kHz rate,

Send: t r i g : g a t e o n

Verify the double pulse periods are gated on for approximately half the time by the 10 kHz external signal.

Send: i n i t : c o n t o n

Verify continuous operation.

7) Move the cable from the the TRIG IN connector to the the PAM IN connector.

Send: p u 1 m : s t a t o n : a m p l p o s

Verify the lower level is at zero volts and that the upper level is being amplitude modulated around its 4V median level with a +2V sinusoidal enve- lope.

8) This completes the operational verification.

Disconnect the test equipment.

Operation

8.1 lntroductlon

This section provides the OperatorProgrammer with the information needed to operate the Model 139 1

Pulse Generator in a VXI system. The unit resides in a

VXI chassis and is subject to a11 of the reslrictions and benefits of that environmenr.

Paragraph 3.2 describes the Model 1391 connectors and LED indicators. Paragraph 3.3 defines the Model

139 1 SCPI programming messages. Paragraph 3.4 demonstrates how to operate the Mode1 1391 using the defined messages.

3.2 Connactors and

LED

lndlcators

This paragraph describes the Model I39 1 front panel connectors and LED indicators. Figure 3-1 illuslrates the front panel; bold numbers identify the indicators and connectors. Table 3-1 describes rhe function of each item shown in figure 3-1.

8.8 Model 1801 Programming

The Model 1391 communicates within the SCPI (Stan- dard Commands for Programmable Instruments) and

IEEE 488.2 standards. It may also communicate using the CIIL (Control Interface Intermediate Language) language described in the MATE specification as an option. When the CIIL language is included. the "Na- tive" SCPI Ianguage is also retained, because it has a much broader set of features. For MATEJCIIL infor- mation. refer to Appendix A at the end of this manual.

The standard Model 1391 must respond to two types of commands: SCPI commands and IEEE 488.2 Common

Commands. The IEEE 488.2 Common Commands support functions that are common to all instruments, such as reset, self test and status reporting. Common

Commands are non-heirarchical (can be included with- in SCPI commands without disturbing their heirarchi- cal relationships) and are easily identified by their leading asterisk (*).

SCPI commands support functions that are specific to the instrument. The SCPI language is heirarchical, re- quiring commands to be entered in a very specific fashion, and this manual contains tabular and graphical representations of the logic used by the SCPI parser

(the 139 1's firmware) to process commands.

This section provides the following infomation:

SCPI Command Table

Command Message Format

Model 1391 SCPI Commands

SeIf Test Query Response

Paragraph 3.3.1.

Paragraph 3.3.2.

Paragraph 3.3.3.

Paragraph 3.3.4.

System Trigger Paragraph 3.3.5.

IEEE 488.2 Common Commands Paragraph 3.3.6.

8.8.1 8CPI Command Table

Table 3-2 lists the SCPI commands used in the Model

I39 I and indicates their hierarchical relationships.

The IEEE 488.2 Common Commands are listed in a separate table (Table 3-4). The SCPI Command Table is organized as follows:

Keyword Parameler Form

I

Notes

[ S O U R c e ]

: F R E Q u e n c y

[ : C W ]

: M O D E

S T A R r

S T O P

The indentations of keywords indicates their hierarchi- cal relationships according to a tree system. The left- most edge is called the roo1 node. Keywords closer to

!he root node are higher in hierarchy; lower nodes are to the right of their parent node. To program or query a settable parameter, the full path must be defined to reach the keyword appended with the required parame- ter form. A SCPI programming string typically starts at the root node and proceeds to the right through branch nodes to the leaf node. This string of keywords separated by colons and completely defining a single path is defined as a Program Header, and is commonly referred to as a "command" (see paragraph 3.3.2) or as a "query" (see paragraph 3.3.2.6). A Program Header followed by Program Data is defined as a Program

Mcssage Unit (paragraph 3.3.2.1).

In the example above, !he left-most keyword,

[ el

, is directly off the root node. Nodes in this position are called Subsysrems, and all keywords

Pulse Generator model 1391

RUN (g

FAIL

@

SYNC our

PAM IN

PULSE OUT model 1391

FI&B 3-1. Model 1391 Front Panel

ltem ltem Name

RUN LED Indicator

FAIL LED Indicator

MODID LED Indicator

A16 LED Indicator

Table 3-1. Model 1391 Front Panel

Funcllon

Whcn lit, indicates the VXIbus Interface Module microprocessor is running.

When lit, indicates the VXIbus Interface Module registers are not initialized.

This indicator turns on momentarily indicating the Resource Manager has dctected the prescnce of the model 139 1.

When lit, indicates that devices on the VXIbus are accessing the generator's A16 registers.

A24 LED Indicator

TRIG IN Connector

SYNC OUT Connector

PAM IN Connector

PULSE OUT Connector

This indicator illuminates during a VMEbus access to the A24 shared memory. This LED will not function in a Model 1391.

This connector receives the external trigger signal for the Model 139 1 's triggered, gated, and burst modes.

This connector outputs TTL pulses for waveform synchronization.

This connector is the input for external signals to Pulse Amplitude

Modulate the PULSE OUT levels.

This connector suppIies the generator's waveform output. Output Ievel is 150 mVpp to 16 Vpp into 50Q. indented under [ S O U R c 1 are part of the Source

Subsystem. F R E Q u e n c is one of the main parame- ters under the Source Subsystem. The third level key- words under FREQuency set or query the various fre- quency related parameters. The brackets around the

SOURce and CW keywords indicate that they are im- plied nodes, and they may be included in or omitted from the message at the programmer's option. When included, do not use the brackets in the command.

Referring to Table 3-2, [ SOURcel is the only

Mode1 1391 Subsystem which is in brackets. This is the default Subsystem. and is assumed unless another

Subsystem is specified at the Start of a command.

The root node itself is an implied node and is not di- rectly programmed. A colon at the start of a command resets the SCPI parser (included in instrument firm- ware) to the root node. A leading colon at the root node location is unnecessary (see paragraph 3.3.2.3).

8.8.1.1 Lonu and Short Form Keywords

The Mode1 139 1 recognizes specific keywords that must be in the accepted long or short format. No other form of the keyword is accepted. For example, to send

'f r e u n as part of a message, the short form keyword, shown in the table as upper case letters ing both upper and lower case characters c may be sent. Equal weight is given to upper and lower case characters when sending messages to the

Model 1391.

8.8.4 Cammand Message Fopmat

The following paragraphs provide the programmer1 op- erator with an introduction to the genera1 rules that must be followed when sending messages to the Model

139 1. For an understanding beyond what is covered in this paragraph, refer to the appropriate SCPI and IEEE

488.2 documents.

Operating the Model 1391 is easy, provided the pro- grammer/operator pays strict attention to the message format, as shown in this manual. Each character, in- cluding spaces, must be properly placed or the model

139 1 will record any unrecognized parts of the com- mand string as an error.

TabIe 3-2 shows the Model 1391 message structure and message relationships. Refer to this while work- ing within this paragraph.

The Model 1391 records programming errors in its memory. The programmer/ operator must use the

' S Y S T E M : ERROR7'query ro review these errors.

The Program Header (command or query) has been previously defined as a complete single path to a leaf node. It consists of one or more keywords separated by colons. It may also have a leading colon used to explicitly select the root node as the starting point. A

Program Message Unit,

< pmu

> , consists of a Program

Header followed (optionally) by Program Data.

8.8.4.2 Program Mertrge

The Program Message (message) consists of one or more <pmurts deliminated by semicolons and fol- lowed by a Program Message Terminator. <p m t

>.

8,8.4.8 Program Merrave Dellmltsrr

To piece together the Program Message, the ~Modcl

139 1 expects commands nnd parameters in the correct order (per Table 3-2). separated by defined delimiters: colons (:), semicolons (;), and spaces ( ).

Use the coIon to separate keywords (nodes) within a

Program Message Unit, for example.

VOLT : LEV : Im : 5

Do not insert spaces between keywords and colons.

Placing the optional colon at the beginning of a h o - gram Message Unit ensures the parser starts from the

"root" or top IeveI. For example, a complete message with the leading colon is as follows:

The leading colon at the beginning of any new mes- sage is optional because the Program Message Termi- nator ( < >) at the end of the previous message sets the parser to the "root" level. The leading colon is not shown for most messages in this section.

The semicolon is used as a Program Message Unit

Separator ( < p m s > ) . It permits the message units to be linked rogether in a single message. The colon may follow the semicolon to stan the next message unit at the "root". For example,

Without the coIon following the semicolon. the mes- sage must start within the same subsystem as the previ- ous message. For example:

S0UR:FUNC SQU;FREQ:CW 1E4

A space separates the Program Header from its data, as shown in the previous example.

8.8.4.4 Parameter Forms

For the Model 139 1, parameters may be in the form of a decimal numeric value (numeric-data), alpha charac- ters (character-data), or Boolean data. Examples of all three are:

FREQ 1 0 0 0 (numeric-data)

F U N C SQU (character-data)

OUTP ON (Boolean-data)

Notice that in all cases, a space separates the header from data.

Numeric data values for most parameters may be in the form of an integer. a fixed or floating point value, or a special keyword as shown in the following: integer;

FREQ 1 0 0 0 fixed point;

FREQ 1 0 . 1 floating point;

FREQ 10E3 specialform characrer;

FREQ M I N

When any of the three special form decimal numeric

'MAXirnum', or 'DE

-

Fa u 1 ', are sent, the parameter being addressed is set to a predetermined numeric value. The 'MAXimum' and 'MINimum' numeric values are the upper and low- er limit values of the parameter. The I ' nu- meric value is within the limits of the parameter select- ed. Defaults values are listed in paragraph 3.4.3.

The Model 1391 uses several character data keywords.

These are shown in Table 3-2.

Boolean data expresses an enabled ('on' or '1') or dis- abled ('off or '0')

8.8.4.6 Program Menrage Tsrmlnatorr

The Model 1391 accepts New Line (NL

.

< L F > ) ,

E N D , or NL with END as the Program Message Ter- minator (<pmr>). However, the E N D ( < E O I > ) is the preferred < p m t > because it initiates an immediate transfer from the commandldata buffer to the Lan- guage Processor for parsing. The other terminators may be delayed until the buffer fills.

KEYWORD

[ :ALL]

INITiate

[ : I m e d i a t e ]

:CONTinuous

OUTPur

:ECLTrg<n>

[ : STATel

: SOURce

[ STAT^]

: SUMBus

[ : STATe]

:TTLTrg<n>

[

1

Table 3-2. 1391 Command Summary

PARAMETER FORM NOTES

<n>=O to 1 VXlbus

ECLTrigger lines

<n>=O to 7 VXlbus

RLTrigger lines

[ SOURce]

:FREQuency

[:CU

I

FIXed]

: FUNCtion

[ : SHAPe]

: TYPE

: WIDTh (nuneric-value)

(numeric-value)

[ : STATe

: POLarity

(numeric-value)

(Boolean-data)

<NORMal

]

( Q E )

COMPlement

:TRANsition

[ : LEADing]

: TRAi

:AUTO

: SUMBus

[ : STATe]

(Boolean-data)

(numeric-value)

(numeric-value)

<Boolean-data)

[ : LEVel]

[ : I ~ M e d i a t e ]

:HIGH

: LOW

[ : AMPLitude]

: OFFSet

<nuneric-value)

<numeric-value)

(nuneric-value)

(numeric-value)

KEYWORD

Table 3-2.

PARAMETER FORM

: PULW

[ : STATel

:AMPLitude

STATUS

:OPERation

:CONDition?

: ENABle

:QUEStionable

: CONDition?

: ENABle

[:EVENtJ?

: PRESet

SYSTem

: ERRor?

: DATE

: VERSion?

NOTES

391 MATE only

TRIGger

: GATE

[ : STATel

:MODE

:MODE

: SLOPe

: SOURce

(Boolean-data>

<SYNChronous

<MASTer

<IhTernal

I

S L A V e >

< P O S i t i v e

I

NEGative>

I

BUS

I

EXTernal ] T T L T ~ ~ < ~ > [

ECLTrg<n> f TOFF>

(numeric-value)

(SEE)

1

EXTWidth)

DIACnostic

:CALibrace?

: ,%kSure

: e?

: SAVE

TEST

[:ALL]?

Unless otherwise indicated, each header with a param- Performs a Self Calibration and stores thc calibration eter form also has a query form so that thc current set- data in lion-volatile memory. If the calibratiori is suc- ring may be reporled back. A query is programmed by cessful. use of the data is enabled. if the calibration is following the leaf node keyword with a question mark unsuccessful for any reason, use of the data is disabled

(?), no space. For example, send: and default correction factors are used. The response

SOUR:FREQ:CV? value will indicate the nature of the failure. or the reduced form:

FREQ?

The value of a 16-bit Self Calibration Status Word is returned in response to the calibration query. The for- mat of thc Status Word is shown below: to qucry the frcqucncy setring. The response for this

- qucry is a floating point numerical value representing the frequency in Hcrtz. For examplc, if rhc response is 1

Error Code

9 a

7 6 5 4 3 2

1 0 '

1.0OOOOOE+03 Self Calibration Status Word

For queries rhat include parameters, rhe question mark The Error Code field contains a bit weighred code that and a space are inserted prior to the parameter: is unique to the failed srep. Refer to Appendix C for

FREQ? K A X more information.

Some commands may exist in query form only: 8.8.8.2 TEST 8ubsy8lem

SYSTEX : ERROR?

Some queries are mandated such as ESE ? ,

' and

' ; see paragraph 3,3.4.

The IEEE-488.2 self test query causes an internal Self

Test lo performed and a be placed i n the

8,a.a Model 18fll 8CPI Commands

This paragraph introduces the operalor to the Model

1391 SCPI command set. Paragraph 3.4 covers the re- lationship berween these units. For a description of message format, refer to paragraph 3.3.2. This para- graph uses only the short form keyword recognized by the Model 1391 (refer 10 Table 3-2). Program Mes- sage Terminators are assumed, and therefore not shown in the examples. However, most optional key- words are shown Lo document the program flow. test passed. The interpretation of the value returned in the event of a failed self tesr is lisred in Appendix D.

The ' Self Test func[iOns and returns the same rePonsc as the SCPI

T E S T [ : ALL] 1 query. Following is the TEST s u b -

Vstern the SCP1

T E S T

[ :ALL]?

The IEEE-488.2 calibrarion query (see paragraph

3.3.2.6) causes an internal Self CaIibration to be per- formed and a response to be placed in rhe Output

Performs a Self Tcst and sends the resulrs ro the Out- put Queue. The response value will indicate the nature of the failure.

Queue. The value of 0 is returned if the self calibra- tion passed. The interpretation of the value returned

The valuc of a 16-bit Self Test Status Word is returned in rcsponsc to thc calibration query. The format of the in the event of a failed self calibration is listed in Ap- Status Word is shown bclow: pendix C.

The

. query invokes the same internal Self Cali- bration functions and returns the same reponse as rhe Error Code

3 2 1 0' S C P I C A ~ i b r a t i o n [ : A L L ] ? q u c r y . 5 1 1 1 0 9

7 6 5 the CALibrate Substcm cxccrpted from the SCPI Com- mand Table:

Self Test Status Word

C A L i b r a t i o n

The Error Code field contains a bit weighted code that is unique to the failcd step. Refer to Appendix D for more information.

[ : A L L ] ?

sclector and the inputs ro he width and delay one-shot gcnerarors. The sclecmr chooses one signal among several, dependant upon operating mode, to trigger the one-shots. The PULSe signal is the output of the one- shots bcforc it is applied to the analog ou[put condi- tioning circuit blocks.

This command is included to support the SCPI specifi- cation, bur i t does nor altcr the setup of the modcl

1391.

OYTPc [ :

2

<5001ean>

Controls the state of the funclion outpur relay, turning the signal to thc PULSE O U T on or off. Defaul[ selcc- tion is "OFF" (O), enabled with "ON" or "1".

This command sclects bctwccn continuous modc of operation and a non-continuous ( r r i g w c d , gatcdl or burst) mode of operation.

8.8.8.4 OUTPut Subsystem

C3T31.r

: E C L T r g < n >

(TRIP

I

P U L S e >

( B o o i e a n - d a t a >

: S C Z R c e

:

: STAT^]

: SUi33us

[ STAT^]

: T T L T r g < n >

[ : S T A T e ]

: S O D R c e

< 3 0 0 1 e a n _ d a t a >

< 5 o o l e a n _ d a t a >

< T R I P

I

P U L S e >

Connects or disconnects thc Model 1391 to the

VXIbus backplane SUMBUS line. Default selection is "OFF" (0); "1". When ON, the Model 1391 drivcs the SUMBUS with a current proportional to the voltage wavcform at PULSE OUT.

C U T P ~ ~ : T T L T ~ ~ < ~ > [ : S T A T ~ ]

< O N J ~ I O F F I O >

Enablcs the selected model 1391 SOURce signal to drive one of rhe VXIbus backplane TTL Trigger Lines.

Each TTL Trigger Line output can be separately en- abled, one at a time. VaIid numeric suffixes ( a > ) are in the range 0

(0). enabled with "ON" or "I".

C T R I P I P U L S e >

I I I

Enables ~ h c 1391 SOURce signal to drivc one of the VXlbus backplane ECL Triggcr Lincs.

Each ECL Trigger Line output can be separately en- abled, one at a time. Valid numeric suffixes ( a > ) are in thc range 0 1. Default selection is "OFF"

(O), "I".

Selects lhe signal (internal to the 1391) which is to be enabled to drive one of the backplane TTL Trigger

Lines. The default selection is the "[rigger pulse".

TRIP, which exists at the circuit node between a signal selector and the inputs to the width and delay one-shot generalors. The selector chooses one signal among several, dependent upon operating mode. to [rigger the one-shots. The PULSe signal is the outpul of the one- shols before it is applicd to the analog output condi-

O U ' T ? u r : E C L T r g < n > : S C L J R c e tioning circuit blocks.

< T R I P ] P u 3 S e >

8.3.8.6 RESet Subsystem

Sclccrs the stgnal (internal to the 1391) which is to bc

R E S e enabled to drivc one of thc backplane ECL Triggcr

Lines. Thc dcfault sclcction is rhe "triggcr pulsc".

Resers all parameters to their default state (see para-

TRIP, which cxists at thc circuit nodc bcrwccn a signal graph 3.4.3).

8.8.8.8 SOURce

Subtyttem

[ S O U R c e j

: F R E Q u e n c y

[ : C V

I

F I X e d j ( n u m e r i c - v a l u e )

: F U N C r i o n

i

: S H A P e j r

( P U L S e

I

S Q U a r e )

: T Y P E

I

: S T A T e ]

: PL'LSe

< C L O C k

1

G A T E )

( B o o l e a n )

: W I D T h

: D E L a y

: D O U B l e

:

: D E L a y

[ : S T k T e ]

P O L a r i t y

< n u m e r i c - v a l u e )

( n u m e r i c - v a l u e )

< n u m e r i c - v a i u e )

(Boolear.)

< N O R M a l l C O K P l e m e n t l

I N V e r r e d )

( n u m e r i c - v a l u e )

: T R A N s i t i o n

: S T A T e < B o o l e a n >

[ : L E A D i n g ] ( n u m e r i c - v a l u e )

: T R k i l i n g < n u m e r i c - v a l u e )

: A U T O ( B o o l e a n )

: S U M B u s

[

:

< 9 0 0 1 e a n >

[ S O U R c e : F U N C r i o n i : S H A P e ] ( P U L S e ] S Q U a r e >

Selects the shape of the output signal. For the Model

139 1 , the Funcrions available at the PULSE OUT are the PULSe and thc SQUare. Additionally, with the

PULSe selected, other PULSe parameters in this Sub- system are used to sclecr single, delayed, o r double pulses within cach period. Default selection is PULSe.

Enables or disables the SYNC output. Default se- lection is "OFF" (0); enabIed with "ON" or "1".

[ S O U R c e : ] X A R K e r : T Y P E < C L O C H ( G A T E >

Selects the method used to generate the SYNC ourput.

CLOCk

GATE

A signal derived from the rcpetitian rate (period) generator.

A signal derived from the triggering circuitry. T h e GATE signal goes true when a triggerlgatelburst cycle is ini- tiated, and goes false when the trig- gerlgare signal goes false.

[ S O U R c e : ] P U L S e : W I D T h ( n u m e r i c - v a l u e )

Sets the width of the pulse waveform in seconds. De- fined a s the time between the 50% points o f leading and trailing transitions. Each pulse period can have single o r double pulses. Width parameler values range from a rMINimum of I 0 ns to a MAXimum of

2000 s , DEFault value is 250 ns.

[ : L E V e l ]

: I K K e d i a t e ]

: H I G H

: L O W

( n u m e r i c - v a l u e )

< n u m e r i c - v a l u e )

[ : A K P L i t u d e ] ( n u m e r i c - v a l u e )

: O F F S e z ( n u m e r i c - v a l u e )

Scrs the dclay of a single pulse waveform in scconds.

Defined as the timc between the start of a pulsc period

(50% point of SYNC OUT) and the 0 % point of the leading transition of a single pulse. Delay parameter values range from a MINimum of 0 ns to a MAXimum of 2000 s. DEFault value is 0 ns.

[ S O U R c e j F R E Q u e n c y

[ : C X ( F I X e d ] ( n u m e r i c - v a l u e )

Scrs pulsc generator "frequency" as an altcrnatc to sct- ling S O U R : : to control the pulse period, FREQuency and PERiod are "coupled" parameters. s o thal programming one updales the value of the other. "CW" and "FIXed" are intcrchangable.

Parameter values range from a MINimum of 0.001 Hz to a MAXimum of I00 MHz. DEFault valuc is

I MHz.

[ S O U R c e : ] P U L S e : D O U B l e : D E L a y

( n u m e r i c - v a l u e )

Scrs the dclay of a double pulse waveform in seconds.

Defined as the rime bcrween the start of a pulse period

(50% point of SYNC OUT) and the 0% point of the leading transition of the second pulsc. Delay paramc- tcr values range from a MINimum of 2 0 ns ro a 1MAXi- mum of 2000 s. DEFault value is 400 ns.

Enables or disables the double pulse function. De- fault sclcction is "OFF" (0); cnabled with ''ON" or

"I". Enabling the doublc pulsc selects the

? U L S e : DGU91e : D S L a y paramcter in place of the

? U I. : 3 E L a y paramclcr.

Scrs [he width of the pulse waveform transilions in bcconds when TRANsition state is ON. Programming this value sets "auto-trailing" OFF if it is ON. Defined as the timc between the 10% point and 90% point of a trailing transition. TRAiling parameter values range from a MINimum of 5 ns to a hlAXimum o f 5 0 p,

DEFaull value is 5 ns.

Allows the internal signal at thc one-shor generalor ourput ro bc invertcd (complemented) bcforc being ap- plied to the output circuits and to the PULSE OUT.

Default selection is NORMal.

NORMal Pulse lcading transitions arc rising transitions, Pulse width is activc high.

COMPlemcnt Pulse leading transitions are falling transitions. Pulse width is active low.

INVcned Alias for COMPlement.

When cnabled, causes the parameter values for the

TRAiling transition time to be set along with the ing transition has its own parameter values, and

LEADing and TRAiling [ransirions are independenl. restricted only by the maximum 10: 1 ratio, Default selection is "ON" (1); disabled with "OFF" or "0".

[SOURce: j SUXBus [ : STATe] < O N /

I

OFF

I

O >

Connects o r disconnects the Model 1391 to the

VXIbus backplane SUMBUS line. Default selection is "OFF" (0); enabled with " O W or "1". When set to

ON. the model 1391 sums the waveform on the SUIM-

BUS with the PULSE OUT waveform.

Sets the pcriod of the pulse waveform in seconds. De- fined as the time between the 50% points of thc rising transitions of two adjaccnr SYNC OUT waveforms

IMARKer:TYPE CLOCL). Thjs is the same as [he rime between two adjacent, idenrical transitions at the

PULSE OUT. Each pulse period can have single or double pulses. Period paramerer values range from a

.MIiVimum of 10 ns to a LlAXimum of 1000 s. DE-

Faulr value is I W . PERiod is "coupled" to the FRE-

Quency parameter such that changing one parameter updates the other.

I S O U R c e : ] VOLTage [ : L E V e l ] : I t G I e d i a t e ]

: H I G H < n u m e r i c - v a l u e )

Sets thc amplitude i n volts peak (50Q) of the upper level of the pulse waveform at the PULSE OUT.

Should be programmed along wirh the LOW LEVel parameter (see (he NOTE below). HIGH level param- eter values range from a MIWimum of -7.850 V (50Q) to a AMAXimum of +8V (50S2). DEFault value is

+2.50 V (50S2). [ S O U R c e : ] T R A N s i t i o n : STATe

< O K I ~ ] O F F I O >

Sets the pulse transition timc generators ON or OFF.

Dcfaul! is OFF. If the stale is off, then the transi~ions are set to rhe minimum values of 5 ns. If the state is on, the transitions arc determined by the values for

LEADing and TRAiling.

: S 9 U 4 c e : P u L S ~ : [ : L E A D i n g ]

{ n u m e r i c - v z l u e >

Sets the width of the pulse waveform transitions in seconds when TRANsition stare is OK. Defincd as thc lime between the 10% point and 90% point of a Icad- ing ~ransilion. LEADing parameter values range from a MISimum of 5 ns to a XlAXimum of 5 0 ps. DEFault value is 5 ns.

NOTE

The AMPLitude and OFFSer paronte- rers, and the HIGH and LOW level pa- rameters, are two ways of setting rhe orirpur levels. Use HIGH and LOW ro- gerher, o r use AMPLitude ond OFFSer rogerher. These are "coupled" func- riorrs - serring up one pair causes the orher pair to updare ro equivalenr val-

U P S .

3-10 OPEFUT~ON

1

P U L M [ : S T A T e ] < O N

I

1

I

O F F

1

0 )

Sets the amplitude in volts peak (50R) of the lower level of the pulse waveform at the PULSE OUT.

Should be programmed along with the HIGH LEVel parameter (see the NOTE above). LOW level parame- ter values range from a MINimum of -8V (50Q) to a

MAXimum of +7.850 V (50R). DEFault value is

-2.50 V (50R).

Connects or disconnects the PAM IN connector to the

Model 1391. This enables or disables Pulse Ampli- tude Modulation. Default selection is "OFF" (0); en- abled with "ON" or "I".

I

? u L M : ~ ~ P ~ i t u d e

I positive

1 m T i v e )

[ S O U R c e ] V O L T a g e [ : L E V e l ] [ : IH.IMediate]

Determines how the Model 1391 pulse amplitude mod- ulates the PULSE OUT signal using the PAM input.

Default selection

is

BIPolar.

: O F F S e t ( n u m e r i c - v a l u e )

Sets the offset in volts dc (50R) of the pulse waveform at the PULSE OUT. Should be programmed along with the AMPLitude LEVel parameter (see the NOTE above). OFFSet parameter values range from a MINi- mum of -7.925 Vdc (5OR) to a MAXimum of

+7.925 Vdc (50R). DEFault value is 0.

BIPolar The PULSE OUT waveform's lower level is a mirror image of its upper level. The instantaneous amplitude of the levels is a linear function of the signal at the PAM input.

VOLT^^^ [ : ~ E V e l l I M M e d i a t e ]

[ : k M P L i t u d e ] < n u m e r i c - v a l u e )

POSitivc The PULSE OUT waveform's lower level is fixed at the programmed

F F S t setting. The instantaneous amplitude of the upper level is a lin- ear function of the signal at the PAM input.

Sets the amplitude in volts peak-to-peak (50R) of the pulse waveform at the PULSE OUT. Should be pro- grammed along with the OFFSet LEVel parameter

(see the NOTE above). AMPLitude parameter values range from a MINimum of 0.150 Vpp (50R) to a

MAXimum of 16 Vpp (50R). DEFauIr value is

5 Vpp (50R). hTEGative The PULSE OUT waveform's upper- level is fixed at the programmed

O F F S e setting. The instantaneous amplitude of the Iower level is an in- verted linear function of the signal at the PAM input.

NOTE

Restrictions on output levels: The sum of Vpk amplitude (halfthe programmed

Vpp value) and the absolute offset value cannot exceed 8V. Additionally, for pulses less than 0.5 Vpp, this resrricrion is reduced to

2

V.

When setting the output in terms of

HIGH and LOW levels, the HIGH level must be at least 0.15 V more positive than the LOW level. HIGH and LOW levels are programmed within a +

8

V window, reduced to a i 2 when (upper

- lower) is less than 0.5 V.

: ERRor?

: DATE < y e a r > , < m o n t h > . < d a y >

: T I M E < h o u r > . < r n i n u t e > . < s e c o n d )

: V E R S i o n ?

: L A N G u a g e

: C I I L

: COUN:

1

: M O D E

[ : STATe]

: M O D E

: S L O P e

: S O U R c e

Sets rhe system date using the following format: y y ~ ~ * m m , d d .

Returns the next message from the system error queue.

With each query, the unit returns a number followed by a brief description. The error queue holds up to eight errors, with one returned for each query sent, un- til the queue is empty. Table 3-3 describes the system crror mcssages.

SYSTem:TIKE < h o u r > , < m i n u t e > , < s e c o n d >

Sets the system time using the following 24 hour for- mar: hh,mm,ss.

NOTE

When INITiate:CONTinuous is ON, the pulse generator mode is continuous, re- gardless of the settings in this Sub- system. When INITiate: CONTinuous is

OFF, the mode is non-continuous and determined by these settings. When

GATE[:STATe] is OFF, the pulse gen- erator is in a triggered mode if the

COUNt parameter is I , o r in a burst mode ifthe COUM is set higher than 1 ,

When the GATE[:STATe] is ON, the pulse generator is in a gated mode, us- ing either the SYNChronous o r EXT-

Width sub-modes.

Rerurns the system's idea of the time in the following format:

< h o u r > . < m i n u t e > , < s e c o n d >

: C O U N t <numeric-value>

This command sets the number of pulse periods gener- ated after a trigger is received. MINimum and DE-

Fault value is 1 . MAXimum value is 10,000,000.

Returns the system's firmware version number in the folIowing format:

I

O > . < f i r m w a r e - l e v e l

I

0)

This enables or disables gated mode of operation. See the above note. Default selection is nbled with "ON" or "I".

"OFF' (0); en-

Used only with the MATEKIIL option. A unit with rhe option installed uses CIIL as its default command language and SCPI as its alternate or "native" com- mand language. Many of the more complex features in the SCPI command sct are not implemented in CIIL.

When in CIIL, the operator can usc the CIIL GAL command to go to SCPI to accomplish a task nceding the additional features. This command is used to re- turn

10

CIIL from SCPI.

Selects the GATE sub-mode. Default is SYNChro- nous.

SYNChronous The pulse generator is quies- cent at the lower level value. When a trigger is received, the generator out- puts pulse periods (with selected pulse parameters) as long as the gat- ing signal is uue. When the gating

signal goes false before the 5 0 2 point of the current period, the generator completes its current period, and then returns to the quiescent stale. Whcn the gating signal goes false beyond the 5070 point of the currenr period, the generaror completes its current period and the next full period, and then returns to the quiescent state.

When the triggering signal is false, the pulse generator outpuls its lower level. When the triggering signal is true, the pulse generator outputs its upper level. Transition times can be programmed.

EXTernal

INTernal

Selects an external signal at the TRIG

IN connector a s the trigger source.

Selects the Model 1391 internal sig- nal programmed by the trigger TIlMer as rhe trigger source.

BUS Selects the IEEE-488 bus (488.1 GET command or 488.2 +TRG command) or the VXIbus (Word Serial Trigger command) as the triggering source.

TTLTrg<n> Selects one of the VXIbus TTL Trig- ger Lines from the backplane. Valid numeric suffixes are in the range 0 through 7.

ECLTrg<n> Selects one of the VXIbus ECL Trig- ger Lines from the backplane. Valid numeric suffixes are 0 and 1.

TOFF Disables all trigger sources.

This command selccls the voltage threshold level for the trigger comparator. This determines the triggering point on an external signal applied to rhe TRIG Ih' connector. Determine TRIGger SLOPe at thc same

T R 1 G g e r : T I M e r ( n u m e r i c - v a l u e >

Sels the period of an internal periodic signal source, is +10V. DEFault value is 1V. ed trigger source. lMINimum value is 20 ns and

MAXimum value is 1000 s. DEFault value is 10 ms.

This command seIects whether a 1391 module is inde- pendent, a master o r a slave. A master supplies a trig- ger to other modules. A slave picks up the trigger from a master. Masler/Slave triggering operation al- lows multiple modules in a VXIbus chassis to operate as a muItiple channel pulse generator system. Timing between channels is very tightIy controlled. When set to SLAVe, but not making use of a trigger from a mas- ter, then the module is "independent". Default is SLAVe.

MASTer The module supplies its SYNC OUT signal to an ECLTrg line for slave modules to use.

SLAVe Can pick up thc master trigger from an ECLTrg line.

This command selects whether a trigger is initiated as the selected trigger signal passes through the thresh- old set by trigger LEVel in a positive-going o r a nega- tive-going direction. Default is Positive.

8.1.8.9 DlAGnostlc Iluhsystem

D I A G n o s r i c

: C A L i b r a t e ?

: C A L i b r a r e

< s r e p >

: H E A S u r e < s r e p > . < n u m e r i c - v a l u e >

: i - i E A S u r e ? < s t e p >

: SAVE

: IXIT

Initiates the manual calibration system. The <step> entered is the manual calibration step number that is to be set up for and performed. Some steps in the manual calibration procedure are handled automatically by the

Model 1391, and this will be indicated by the return message. Manual steps requiring measuremenrs with external test equipmenl and/or adjustments will return a message giving the appropriate instruclions,

Selects the source of the trigger signal. The trigger signal is used to initialc activity when the instrument is in a non- continuous mode of operation. Default is LVTernal.

When the particular step requires an external measure- ment (see above), this command allows the operator to

enter the value measured into the Model 1391's vola- tile memory. These values may be entered step-by- step as the data is taken, or all at once at the end of a successful manual calibration. See the SAVe com- mand for making the new data non-volatile. mary bit. The Model 1391 supports the command by saving the mask value and by not generating an error, alrhough the Status registers do not exist.

The <NRf> notation indicates that SCPI's

<numeric-valuer format is not used in this case. Re- fer to the IEE488.2 <DECIMAL NUMERIC PRO-

GRAM DATA>, flexible Numeric Representation for more information.

Query form of the above command. Allows operator to query the currently stored Calibration Data for the given step number. The "STATus : : ENAB1 e?" query re- turns the enable mask of the Operation Event Register.

The Model 1391 returns the value sent previously with the command above using the <NRI> format.

Transfers the block of calibration data values from vol- atile to non-volatile memory. After the manual cali- bration has been successfully completed, the operntor

S T A T u s : O P E R a t i o n [ : E V E N t ? ] should send [his command so that the new values are Returns the contents of the Operation Event Register. used to optimize the unit's accuracy. The Model 1391 supports this query, but will only re- turn the value "Ow, indicating operational condition,

D i A G n o s t i c : C A L i b r a t e : I N I T

Replaces the current calibration data values in non- volatile memory with a set of "default" values in

ROM. The default values are nominal values which should aid in troubleshooting whether a unit's mal- function is due to miscalibration or to hardware fail- ure,

S T A T u s : P R E S e t

Sets the enable registers to all 1's. The Model 1391 accepts the command without performing any action.

S T A T u s : O P E R a t i o n : C O N D I t i o n ?

Returns the contents of the Operation Condition Regis- ter. The Model 1391 supports this query, but will only return the value "0". indicating operational condition.

STATUS

: O P E R a t i o n

: C O N D i t i o n 7

: ENAB e

[ : E V E N t ] ?

: P R E S e t

: Q U E S t i o n a b l e

: C O N D i t i o n ?

: ENABle

[ : EVENt I ?

< N R f

< N R f

>

>

S T A T u s : O P E R a t i o n : E N A B l e < N R f >

Sets the enable mask of the Operation Event Register, which allows true conditions to be reported in the sum- mary bit. The Model 1391 supports the command by saving the mask value and by not generating an error, although the Status registers do not exist.

The <NRf> notation indicates that SCPI's

<numeric-value> format is not used in this case. Re- fer to the IEE488.2 <DECIMAL NUMERIC PRO-

GRAM DATA>, flexible Numeric Representation for more information.

The "STATus : turns the enable mask of the Operation Event Register.

The Model 1391 returns the value sent previously with the command above using the <NRl> format,

S T A T u s : O P E R a t i o n : C O N D i t i o n ?

Returns the contents of the Operation Condition Regis- ter. The Model 1391 suppons this query, but will onIy return the value "0". indicating operational condition.

S T A T u s : O P E R a t i o n : E N A B l e < N R f >

Sets the enable mask of the Operation Event Register, which allows true conditions to be reported in the sum-

: O P E R a t i o n : E V E N t ?

Returns the contents of the Operation Event Register.

The Model 1391 suppons this query, but will only re- turn the value

Error Number

Table 3-3. Error Messages

-

Message

'No error'

"Command error'

"lnvalid character'

'Syntax error'

'Invalid separator'

'Data type error"

"GET not allowed"

"Parameter not allowed"

'Command header error'

'Header separator error'

"Program mnemonic too long'

"Undefined header'

'Header suffix out of range'

'Numeric data error'

'Invalid character in number'

"Exponent too large'

'Too many digits'

'Numeric data not allowed'

'Suffix error'

'Invalid suffix"

'Suffix too long"

'Character data error'

'Character data too long'

'Character data not allowed'

'String data error'

"Invalid string data'

'String data not allowed'

'Block data error'

'Invalid block data'

'Block data not allowed'

'Expression error'

'Invalid expression'

'Expression data not allowed'

'Macro error'

"Invalid outside macro definition'

'Invalid inside macro definition'

'Macro parameter error'

"Execution error'

'Invalid while in local'

'Settings lost due to rtl"

'Trigger error'

Error Number Message

'Data out of range'

'Too much data'

'Illegal parameter value'

'Data corrupt or stale'

'Data questionable'

'Hardware error'

'Hardware missing'

'Mass storage error'

"Missing mass storage'

'Missing media'

'Corrupt media'

'Media full'

'Directory full'

'File name error'

'Media protected'

"Expression error'

"Math error in expression'

'Macro error'

'Macro syntax error'

'Macro execution error'

'Illegal macro label'

'Macro parameter error'

'Macro definition too long'

'Macro recursion error'

'Macro redefinition not allowed'

'Macro header not found'

'Program error'

'Cannot create program'

'Illegal program name'

'Illegal variable namem

"Program currently running'

'Program syntax error'

'Program run time error'

'Device specific error'

'System error'

'Memory error'

'PUD Memory lost'

'Save/recall memory lost'

'Configuration memory lost'

'Self test failed'

a.a.4 IEEE-4883 Common Commands

The CAL? self calibrate query. the ' T S T ? self test query, and the ' command are discussed else- where in this manual (along with their equivalent SCPI query or command),

The ' query is equivaIenr to the SCPI C A L i

- b r a t e [ : ALL] 7 query. The self calibration query is discussed in Appendix C of this operator's manual.

The ' query is equivalent ro the SCPI

T E S T [ :

I

? query. The self test query is dis- cussed in Appendix D of this operator's manual.

The 'TRG is an IEEE Common Command used to providc a properly sequenced uigger and execute to an addressed 1391 via the VXI data bus ('BUS' must be selected as thc trigger source in the Trigger subsystem).

The prcvious paragraphs describe in detail the three most commonly used IEEE Common Commands, Ta- blc the modcl 1391.

PAM Operation

Triggered Operation

Gated Operation

Burst Operation

Internal Frequency Sweep

Paragraph 3.4.7

Paragraph 3.4.8

Paragraph 3.4.9

Paragraph 3.4.10

Paragraph

Before beginning, review the data in paragraphs 3.4.1,

3.4.3.

8.4.1 Output TsPmlnatlons

Each output connector must be properly terminated during its use to minimize signal reflection or power loss due to an impedance mismatch. High quality 50R coax cable and terminations should be used for pulse waveform fidelity. Terminators should be placed at the end of the coax cable at the point of signal deliv- ery. Figure 3-2 50R termination for the

PULSE OUT connector, with R, representing the Mod- cl R, representing the termi- nation or load resistance. and R representing the re- ceiving instrument input impedance. Table 3-5 a11 the input and output impedances of the Model 1391.

The following paragraphs describe the SCPI language commands for various modes of operation for the

Model 1391.

Continuous Operation

Marker Opcration

SUMBUS Operation

Paragraph 3.4.4

Paragraph 3.4.5

Paragraph 3.4.6

Table 3-5 Input and Output Impedances

Connector

I

Impedance

PULSE OUT

SYNC OUT

TRIG IN

PAM IN

50R

TTL (0 rl kR, pF rl k R

Table 3-4 IEEE 488.2 Common Commands

'CLS

'ESE

'ESE?

'ESR?

'OPC

'OPC?

'RST

'SRE

'SRE7

'STB?

'TRG

'TST7

' W A I

Command

Calibration Query

Clear Status Command

Standard Event Status Enable

Standard Event Status Enable Query

Standard Event Status Register Query

Identification Query

Operation Complete Command

Operation Complete Query

Reset Command

Service Request Enable Command

Service Request Enable Query

Read Status Byte Query

Trigger Command

Self Test Query

Wait

- to

-

Continue Command

Starts self-cal, places passlfail response in output queue

Clears Status Data Registers, forces OCISiOQIS

Sets Event Status Enable Register bits

Returns contents of Event Status Enable Register

Returns contents of Event Status Register

Identifies devices over the system interface

Requires oper. comp. message in Event Status Reg.

ASCII ' 1 ' in dev. out, queue when operations complete

Resets the device

Sets Service Request Enable Register bits

Returns contents of Service Request Enable Register

Returns status and master summary status bytes

Initiates a properly sequenced trigger and execute

Startsself-test, placespasslfail response inoutput queue

Blocks devicecommands until 'No-Op-Pend' flag is true

-

8.4.2 InputlOutput ProtacUon

The Model I391 provides protection for internal cir- cuitry connected to input and output connectors. Refer to the Specifications in Section 1 of this manual to de- termine the level of protection associated with each in- put or output connector.

8.4.8 Power OniRssst Ddsults

At power on, or as the result of sending ' S T or RE -

S e , the Model 139 1 defaults to the following condi- tions:

PAM Mode

Sumbus

Sumbus Mode

Trigger Mode

TTL Trigger Lines

ECL Trigger Lines

Trigger Slope

Trigger Level value

Trigger Source

Trigger Timer

Trigger Count

Gate State

Gate Sub-Mode

Subsystem

Operational Mode

Function Shape

Frequency value

Upper Level value

Lower Level value

Amplitude value

Offset value

Pulse Output

Pulse Period value

Pulse Width value

Pulse Delay value

Double Pulse state

Double Pulse Delay

Pulse Transition state

Leading Transition

Trailing Transition

Auto-Trailing state

Pulse Polarity

Sync Marker Output

Sync Marker Type

PAM Input

SOURce

CONTinuous

PULSe

I MHz

+2.5 V into 50R

-2.5 V into 50Q

5 VPP

0 Vdc

OFF

1 P

250 ns

OFF

400 ns

OFF (5 ns)

5 ns

5 ns

ON

NORMal

OFF

CLOCk

Disabled (Off)

BIPolar

Off (not input or output)

DRIVe

SLAVe

Off (not input or output)

Off (not input or outpur)

Positive c1.0 v

Imernal

10 ms (100 Hz)

1

OFF

SYNChronous

8.4.4 Eantlnuous Oparatlon

This paragraph shows how to set up the Model 1391 for a pulse waveform output using the default settings provided at power-on. The subsequenr paragraphs un- der this heading will then demonstrate the conrinuous mode pulse period, pulse waveforms and characteris- tics, and the output levels. All of the parameters shown here are derailed in earlier paragraphs. Much of the information given here directly transfers to other modes.

Connect the Model 1391's PULSE OUT connector

(terminated) to the device under test, as shown in fig- ure 3-3, Use the SYNC OUT signal as a synchronizing source. Figure 3-4 illustrates the SYNC OUT and

PULSE OUT relationships.

At power on, the Model 1391's PULSE OUT is always turned OFF. To enable the PULSE OUT connector, send the command:

CIRCUIT COMMON

COAX

CHARACTERISTIC

IMPEDANCE

Zo TERMINATION

R

L

I RECEIVING

INSTRUMENT

RI," R,

R

I,

COMMON

-

Fioure

3-2.

Output Termlnatlon

MODEL 1391

1

SIGNAL

INPUT

-fl

DEVICE

UNDER

TEST v

SYNC

INPUT

1

NOTE!

Two Equal-Length

k'

RG-58

BNC Cables

At power on, the Model 139

Figure 3-3. Model 1391 Basic Operation Setup

-

- turned OFF. To enable the SYNC OUT connector, send the command:

S0UR:MARK:STAT ON

The two previous commands could be shortened and combined as follows:

OUTP 0 N ; : K A R K ON

SYNC OUT is always Set up a 2 channel, high bandwidth oscilloscope as the

DUT in Figure 3-3. Connect the SYNC to CH 1 and the PULSE to CH 2. Trigger the scope internaIly from

CH 1. Compare the pulse waveform to Figure 3-4 be- low. The default pulse waveform should be a Single

Pulse with its 0% point coincident with the 50% point of the rising edge of the SYNC, as shown in the dia- gram. The pulse period is 1 pi and the Leading Tran- sition (tr) and Trailing Transition (t,) should both bc no more than 5 ns. Verify 250 ns Pulse Width.

PULSE

OUT BNC

SINGLE

PULSE

DOUBLE

PULSE

DELAYED

PULSE

I

DELAY d w

I

I

I

I

I

I nmn e

I m-+f

LOW LEVEL

.

I

-PULSE PERIOD-

1IFREO

I

Figure 3-4. Continuous Waveform Characteristics

3.4.4.1 Frequency/Period Parameters

The FREQuency and PERiod parametcrs are "cou- pled", meaning that setting one updates the other ap- propriately. The current default serrings from the pre- vious setup are 1 ps period and 1 MHz frcqucncy.

Change the period from 1 p-5 to 10 ps by sending:

P3LS:PER i E - 5

Verify the frequency valuc has been updated by send- ing the query:

FREQ?

The returncd response should be ' FREQ ; '

(100 kHz). The display on the oscilloscope should now have a pulse period of 10 ps, with the other pulse paramerers remaining the samc.

The double pulse should appear much like the one in

Figure 3-4. Note that the delay values for the delayed pulse and the double pulse are two independent param- eters.

3.4.4.3 Output Levels

Lcavc the unit set up per the previous paragraph. Note that the dcfault scttings for output amplitudes of the pulse waveform result in levels o f +2.5 V into a 5 0 Q termination.

The output levels can be sct up using the AMPLitudc and OFFSct paramcrcrs, o r b y using the HIGH and

LOW lcvel parameters. Usc HIGH and LOW together, or usc AMPLiludc and OFFSet rogcther. These are

"coupled" functions - setring up onc pair causcs the othcr pair to updatc to equivalcnt valucs.

3.4.4.2 Pulse Parameters

Programmable pulse parametcrs included in this para- graph are [he WIDTh, LEADing TRANsirion, TRAil- ing TRANsition, DELAY, and DOUBle DELay. Para- graphs 3.4.4 and 3.4.4.1 above have the Model 139 1 set up in its default values except thar the PULSE and

SYNC outputs arc ON and the period has been changed ro

10 ps, There should be a 250 ns single pulse wirh 5 ns rransitions on the oscilloscope. Changc the single pulse width and transidon rimes as follows:

Setting up the output is nor as simple as many of the other parametcrs. Bccause the output amplifier is only capable of generating an output within a fixed "win- dow" without limiting, thcrc are interactions between the scttings. This window is +8V with the attenuator off and z 2 V with the attenuator on.

When using the AMPLitude and OFFSet paramcters, thc sum of Vpk amplitude (half the programmed Vpp valuc) and the absolute valuc of the offset parameter cannol excced 8V. AdditionaIly. for pulses less than

0.5 Vpp, [his restriction is reduced to 2 V.

PULS XIDT 2E-

The first command enables thc transition rinies for pro- gramming to values other than the default minimum of

5 ns, The second command causcs the trailing transi- tion to be programmed along with the leading transi-

[ion. The next changes the single pulse width to 2 p , and the final command command sets the leading (and lhus both) transition to 200 ns. The oscilloscope dis- play should now show a 2 ps wide single pulse with

200 ns [ransitions. Dccouple the trailing transition from the leading transition as follows:

When serting thc ourput in tcrms o f HIGH and LOW levels, the HIGH level must be at least 0.15 V more positive than the LOW level, HIGH and LOW lcvcls are programmed within a +8 V window, reduced to a

+ 2 V window when (upper - lower) is less than 0.5 V.

Set up rhc pulsc waveform for negative supply ECL levcls using AMPLitude and OFFSct paramcters as follows:

VOLT 9 E - 1

Observe normal ECL lcvcls on the oscilloscope wave- form. Thc upper lcvcl should bc -0.9V and thc lower lcvcl should be -1.7V.

Sct up rhc pulse waveform for C M O S lcvcls using

HIGH and LOW LEVel paramcters as follows:

PULS:TRAN:TRA 6 0 0 E - 9

The trailing transition should increase to 600 ns.

Changc from a single to a delayed pulse as follows:

PULS DEL 2E

-

6

VOLT:E(IGH 5

VOLT: 0

The waveform should change to CMOS levels.

The pulsc should now start 2 ps after the SYNC rather Note thar the pulse waveform is "false" at the lowcr than coincident with the SYNC. S C ~ level and pulses "true" to the upper level. This is as follows: NORlMal PULSe POLarity. Reverse the levels by pro- gramming the following:

PULS:POL COMP (or INV)

Note the change in the waveform from positive to neg- alive logic. This feature can be used to increase duty cycle to >95% by programming the complement of the desired waveform.

Paragraph 3.4.4.2 demonstrates how t o set up single. delayed and double pulses. These three waveforms are available under the default setting:

[SOUR FUNC [ : SHAP] PULS

The Model 1391's default settings are designed to pro- vide a "generic" starting point for common operations. e t or R ST) and then turn the

PULSE and SYNC outputs back on (see paragraph

3.4.4). This is the single pulse. Observe a delayed pulse by sending:

PULS:DEL 100E-9

Observe a double pulse by sending:

PULS:DOUS ON

And finally, observe thc SQUare function by sending:

FUNC SQU

The square has the same timing characteristics as a

CLOCk SYNC, and its vansitions and levels are setta- ble like the PULSe waveforms. Additionally, the square's upper frequency is extended to 100 MHz. there is an end-to-end scale factor of 1 VinNout for two Model 1391s.

NOTE

This simple I VinNout scale factor ap- plies io unartenuared amplitudes. Use

V N if both the driving-and the receiv- ing units are unattenuated (both have their amplitudes 20.5 Vpp). This 1 V N factor is also valid if both have rheir amplitudes set c 0 . 5 Vpp. Ifrhe unit

driving rhe SUMBUS is below and the

Designate one of the units as the Driver. Its amplitude setting is Vin. Designate the other as the Receiver. Its amplitude setting is Vout. The Receiver unit will have its PULSE OUT and SYNC OUT connected to the os- cilloscope as in Figure 3-4. First. set up the pulse waveforms of both units to match Figure 3-5, as fol- lows:

Driver: driving the SUMBUS is above and the receiving unir is below 0 . 5 Vpp, use a

4 VinNour scale facror.

RES

OUTP ON: :

8.4.6 M w k e r Operation

The pulse waveform Marker is the SYNC OUT wave- form. The SYNC waveform can be set up as a pulse period marker, or a s a non-continuous modc timing marker. The continuous mode default setting is as a period marker. This can be programmed as fotlows:

MARK:TYPE CLOC

For the non-continuous modes, GATE and BURSt, the marker type can be changed as foIlows:

KARK:TYPE GATE

The GATE SYNC will be described in paragraphs

3.4.9 and 3.4.10 and in the related figures.

Receiver:

OUTP ON : :

8.4.8 SUMBUS OpeFatlon

SUMBUS operation requires the use of at least two

Modcl 1391 s o r one 1391 and a VXlbus module sup- porting the SUMBUS. This discussion assumes two

Model 1391s. The modulcs may bc located anywhere in thc VXIbus chassis (exccpt slot 0).

Notc that rhe scale factors (sec Section 1) for output- ting to the SUMBUS (5 m A N ) and inputting from the

SUMBUS (0.2 V/mA) arc reciprocals. This means that

Now, set up the Driver as the Master and the Receiver as the Slave (Master/Slave Operation is explained in paragraph 3.4.1 1). as follows:

Driver:

TR1G:MODE MAST

Receiver:

1NIT:CONT OFF

This slaves the Receiver's period to the Driver's. Fi- nally, enable the SUMBUS, as follows:

Driver:

Receiver:

[SOUR ] SUXB ON

The oscilloscope waveform should look like thc "RE-

CEIVER W/SUIMBUS" waveform in thc figure. Note that the Driver and Receiver waveforms wcre a[ thcir defauIt amplitudes of 5 Vpp. The summed waveform should be 10 Vpp because of the 1 V N scale factor.

8.4.7 PAM Operallon

PAM operation requires a Model 1391 and an external signal source to drive the PAM IN connector. Setting the Pulse ModuIation (PULM) STATe ON enables sig- nals at the PAM IN inpul to amplitude modulate the pulse level(s) around the value ser by the programmed

VOLTage setting. PAM is accomplished with four- quadrant multiplication of the 1391's pulse signal and the externaI PAM IN signal. Pulse Modulation has three sub-modes of operation. "POSitive AMPLitude" modulation causes the Iorvrr level to be fixed at the currently programmed OFFSet value and the median value upper level to be at irs programmed value. The signal at PAM IN wiIl amplitude modulate the instan- taneous value of the upper level around this median value. The envelope of the modulated upper level wilI have the same shape as the external signal. limited by the >20 kHz bandwidth of the PAIM input. The scale factor between the amplitude of the external signal and the amplitude of the modulation envelope is 2V of change in the output level per 1V of change in the external signal.

This scalc factor is reduced to 0.5 V of change in the out- put per 1 V of change in the external signal when the pro- is set below 0.5 Vpp.

"NEGative A~MPLitude" PAM is the mirror image of the POSitive case. The upper level is fixed at the cur- rently programmed OFFSer value and the lower level is amplitude modulated. Note that the moduIation en- velope is also the mirror image of the external signal.

"BIPolar A~MPLitude" modulation is essentiaIly the sum o f the POSitive and NEGative sub-modes.

The programmer/operator needs to be aware of two things when setting up PULseModulation. First, the output swing is limited to a window o f +8V (+2V for

Vpp amplitudes less than 0.5 Vpp). Since the 1391's firmware has no knowledge o f the external signal's amplitude and offset, the unit cannot issuc an output stagc clipping warning as it does with an AMPLitudel

OFFSet setting conflict, Second, the multiplier can be overdriven resulting in overmodulation (including a polarity revcrsal of the pulses because of four-quadrant

PULSE

I I

-

I

I I

-

1

I I

I I I

I

I

I

I

1

RECEIVER

WISUMBUS I

I

I 1

I I i

I

I

I I

I I

I I '

I

' 1

I I

I

SYNC OUT m

Figure 3-5 SUhlBUS Waveforms

operation). To avoid these problems, the desired PAM wavefom should be designed using the following steps:

Sketch the desired PAM output waveform. From the sketch, select the required pulse characteristics

(paragraph 3.4.4), PULM sub-mode. and the medi- an pulse output level(s). Ensure that the required wavefom can be produced within the 1391's out- put window capability.

Program [he Model 1391 for pulse period, func- tion, transitions, width and delay for the required pulse characteristics as discussed in the previous paragraphs. Turn on the pulse output.

Based on the PULM sub-mode selected from the sketch, set up the pulse upper and lower levels to the desired median level(s). Note that for POSi- tive or NEGative sub-modes. the programmed val- ue of the level which is to be set to zero by the sub-mode is nor important.

Enable the PAM IN and select a sub-mode, for ex- ample:

P U L K O N

P U L M : A M P L P O S

Verify the PULSE OUT waveform to ensure matches the sketch. i t

Set up the external signal waveshape and ampli- tude. From the Vpp amplitude of the envelope in the sketch and the known scale factor, set the ex- ternal signal's Vpp amplitude. Connect the exter- nal signal to the PAM IN connector. The 21 kR input impedance should not reduce the signal am- plitude unless its source impedance is very high.

Compare the result to the sketch and fine adjust the external signal as necessary. In generaI, the oscilloscope should be synchronized to the lowest frequency component in the waveform, the exter- nal signal.

In the triggered mode, the Model 1391's output re- mains quiescent until triggered by the trigger source.

All Madel 1391 functions may be triggered. When triggered. the Model 1391 produces one complete waveform period, then returns to the quiescent state.

The quiescent state for Positive POLarity is the lower level. The quiescent state for NEGative POLarity is the upper level. The unit may be triggered by using

V I R Z d l E TWOOER

L M L

EXTERNAL TRIGGER

POSITIVE SLOPE

EXTERNAL TRIQGER

NEQATIVE SLOPE

SINGLE PULSE

(POSITIVE POLARITY)

SINGLE PULSE

(NEGATIVE POLARITY)

DELAYED

PULSE

DOUBLE

PULSE

SYNC O W

1

Figure 3-6. Triggered Waveform Characteristics

trigger command, or rhc VXI trigger bus input.

To set the Model 1391 for the triggered mode, follow the instrucrions in paragraph 3.4.4, then change the mode to rriggered by sending:

1NIT:CONT OFF

The default settings select triggcrcd modes rathcr than onc of the other non-continuous modcs. Thcse default settings are:

TR1G:GATE OFF

The pulse waveform could be complemented by send- ing rhc command:

POL COX?

Referring to Figure 3-6, the time t, is shown to be the poi111 where the sclected external signal transirion, pos- itive-going or negative-going, crosses the programmed trigger level voltage. T h e rime r, is the 50% point of the rising edge of the SYNC O U T (MARKer:TYPE

CLOCk). The time t , is the 0 % point on the leading edgc of a dclayed pulsc. The timc (t,

- tJ is a fixed eircuit delay between [he triggering event and the srart of a waveform period. Both the syne output (50% point) and the non-delayed pulse (0% point) occur at

1,. regardless o f the operating mode. The time (t,

- t,) is thc programmable DELay parametcr.

In order to properly trigger the 1391, the TRIGgcr

SOURce, MODE. TIMer. SLOPe and LEVcl may also need to be set up.

3.4.8.1 Level and Slope Parameters

The TRIger LEVel and SLOPe parameters are used to tailor the response of the trigger input comparator to external triggering signals applied to the TRIG IN con- neclor. This is only applicable when the triggering

SOURce is sclected as EXTernal. The LEVel should be set to a voltage level which corresponds to a point on the external signal where the dV/dt value of the sig- nal's transitions is maximum, This minimizes trigger- ing uncertainty Ijilter). Thc SLOPe selection deter- mines whether the 1391 is lriggered on a positive- going or a negative-going transirion through the select- ed voltage level. See Figure 3-6.

3.4.8.3 Internal Trigger

The [rigger slope and level parameters have no effect on an internal trigger source. T o trigger the generator internally, set up the internal trigger TIMer to a value greater than the pulse period. Using the previous ex- ample as a starting point, select the internal triggering source and program the TIlMer as follows:

TR1G:SOUR 1 N T ; T I X (value)

Where <value> is thc dcsired ~riggering gercd periods opcrate to 25 ,MHz in double pulsc,

50 MHz in single or dclayed pulse, and 100 MHz in square,

3.4.8.2 External Trigger Input

First set up the desired pulse characteristics per para- graph 3.4.4. Each trigger input will iniliate one pulse period with these selected characterisrics. Then deter- mine the level and slope requirements (see the previ- ous paragraph) for the external signal to be applied to the TRIG IN connector. and program the unit for trig- gered mode, external source. For example, for an ex- ternal

!PULSE CHARACTERISTICS)

TR1G:SLOP P0S;LEV 1:SOUR EXT

1NIT:COXT OFF

The result will be one period of the selected pulse waveform each time rhe external TTL signal makes a low-ro-high transirion. Notc [hat the period of the ex- ternal signal musr be greater than the pulse period.

Figure 3-6 illustrates triggering of each of the pulse functions. The SQUare may also be triggered, with timing coincident with the SYNC.

3.4.8.4 BUS Trlgger Commands

T o trigger the generator using the IEEE 4 8 8 bus (exter- nal host) or the VXIbus, set up the generator in a trig- gered mode as described above, then select the bus trigger command by sending:

TR1G:SOUR BUS

Trigger the generator by sending either the 488.2

'TRG or 488.1 G E T the word serial T r r over the VXIbus. The

'TRG command is mandated to be rccognized by the

Commander and by the Model 139 1. Thc G E T mand causes the Commander to send the VXIbus word

Serial T i g g e r command to addressed devices which suppon T r g g e r and d o not have their DIR bit cleared to

Trigger level or slope d o no1 apply when using the

B U S as the trigger source, and the bus commands onIy have effect when the Model 1391 is in a triggered mode of operation and the selected trigger source is

BUS.

3.4.8.5

VXI n E L

Trlpper

flus

Input

The Model 139 1 may also be triggered from the

VXIbus TTL or ECL trigger lines on the backplane.

The signal must be placed on the bus from another source within the VXI chassis.

To use the trigger bus as a trigger source, first set up the Model 1391 per the previous examples. Next, se- lect one of the eight TTL trigger lines by sending the message:

Wherc

< n

> represents one of rhe two ECL Trigger lines, 0 or 1. The ECL trigger lines will have higher bandwidth and tighter timing coupling between mod- ules. Note that a TTL trigger line has a maximum bandwidth of 12.5 MHz

Thc selccted signal will trigger the Model 139 1 on thc leading edge. Trigger level or slopc does not apply when using one of the TTL Trigger lines as the trigger source.

The Model 139 1 also offers a special operation mode op[imized for triggering a 1391 from a 1391 using the

ECL trigger lines (see paragraph 3.4.1 1).

Where

< n

> represents one of the eight TTL Trigger lines, 0 through 7. Alternatively, select one of the two

ECL trigger lines by sending the message:

The synchronous gated mode is identical to the trig- gered mode, except the output from the Model 139 1 starts from the quiescent state, produces continuous pulse periods for the duration of the trigger signal, then returns to the quiescent state. All waveforms may be gated (see figure 3-7).

To view synchronous gated mode, set up the Model

1391 pulse characteristics per the previous exampks, and set the unit up for trigger mode using an EXTernal

SOURce at the TRIG IN input. To observe gate mode properly, set the oscilloscope to both display and sync to the external triggering signal on CHI, and to display the 1391 PULSE OUT on CH2. Then switch from triggered to gated mode:

EXTERNAL TRIGGER

POSITIVE SLOPE

COMPARATOR

OUTPUT

SYNC OUT

(PULSE PERIODS)

SINGLE

PULSE

DELAYED

PULSE

DOUBLE

PULSE

Figure 3.7. Synchronous Gate Waveform Characteristics

The default setting is "synchronous" rather than "ex- ternal width" gate mode, which can be programmed with rhe command:

TR1G:GATE:MODE SYNC

The SYNC OUT should appear as in Figure 3-7.

Change the Sync waveform to be similar to the "COM-

PARATOR O U T P U T waveform in the figure by sending:

XARK:TYPE GATE

Gate mode may also use various trigger sources. The unit may be triggered by the external TRIG IN as de- scribed above, the internal source as described in para- graph 3.4.8.3, or the VXI trigger bus input as de- scribed in paragraph 3.4.8.5. The BUS trigger commands as defined in paragraph 3.4.8.4 do not pro- vide a trigger duration and are not valid in gated mode.

3.4.9.1 External Wldlh Operation

In external width, the ModcI 1391 produces an output pulse whose period and width are determined by the selected triggering signal and the trigger level and slope settings, as shown in figurc 3-8. To select exter- nal width, set up the 1391 in gated mode as described above and then send the command:

TR1G:GATE:MODE EXTW

Frequency or period commands are not required for exlernal width. All other pulse characteristics are as described in paragraph 3.4.4. The external width ac- cepts trigger inputs from all four trigger sources: exter- nal TRIG IN, internal trigger generator, VXI Trigger

Bus, and the Trigger command. However, the most useful trigger source for external width is the external

TRIG IN connector. This is because an externally de- fined signaI is used and the trigger level and slope are adjustable as described in paragraph 3.4.8.1. To select the TRIG IN connector as the trigger source, send the command:

TR1G:SOUR EXT

To seIecc the intcrna1 signal source (the frequency syn- thesizcr) for the Extcrnal Width function, send the fol- lowing:

TR1G:TIX < v a l u e > : S O U R I N T

The internal TIMer value is defined in paragraph

3.4.8.3; It is not recommended that this setup be used. since the identical result may be obtained by simply using a continuous square function.

A third trigger source for external width is rhe VXI backplane, described in paragraph 3.4.8.4. The period and width of the instrument output is dependent on the characteristics of the selected signal. A backplane sig- nal is selected by programming one of the eight TTL trigger lines by sending the message:

Where

< n > represents one of the eight TTL Trigger lines, 0

ECL trigger lines by sending the message:

Where < n > represents one of thc two ECL Trigger lines, 0 I. The ECL trigger lines will have higher bandwidth and tighter timing coupling between mod- ules. Note that a TTL trigger Iine has a maximum bandwidth of 12.5 MHz per the VXIbus specification.

The remaining trigger source available to the Model

1391 in external width is the trigger command

"

1

,!/

M E W TRKKIER

CIEQ*nVE SLOPE

1

Figure 3-8. External Width Waveform Characteristics

described in paragraph 3.4.8.3. When using the trigger command, the period and width of the oufput signal is dctcrmined by the ' T R G bit. T o sclcct thc triggcr command, scnd:

TR1G:SOUR BUS

A pulse will bc gencratcd, whosc width will bc a func- tion of the commander's T R G write cycle time.

3.4.1 0 Burst Uperatlon

Thc burst mode is idcntical to the triggcrcd mode, ex- ccpt whcn a trigger is rcceivcd, the Modcl 1391 lcaves its quicscent state, produces a predefined numbcr of pulse periods, then returns to its quiescent statc. Burst waveforms (with COUNt set to "3") will be identical to thc gate waveforms illustrated in Figure 3-7.

T o observe the burst mode, sct up the Model 1391 for triggcrcd modc as describcd in paragraph 3.4.8. thcn scnd the burst mode command:

Slave module. Slave modules further away from the

Master will have a backplane delay of approximately

0.5 ns per slot. Thereforc, for best timing perfor- mance, the I391 modulcs in the MasterfSlavc group should be adjacenl to one another and rhe Master should be thc one in the middle of the group.

The default setling for a 135) 1 module is "Slave", which allows it to be a Slave module in a MasrerfSlave group o r an independent module. Once the Master module is chosen, scnd it the command:

T R I G : XODE XAST

Thcre can only be one Master connected to a group of

Slaves using one particular ECL Trigger line. Program the ECL Trigger line to be used by the group by send- ing the following command to the Mastcr:

OUTP:ECLT<n> ON

Sct up the Slaves to receive the Master's trigger on this particular ECL Trigger line by sending the follow- ing command to each Slave:

Where rhe value <n> is a numbcr greater than 1 and up to 10 million. Numeric values are explained in para- graph 3.3.1.4. For burst count messages, numeric val- ues may be in the form of an integer or floating point value, or one of the special casc character keywords,

' X A X i r n u m ' , ' X I N i m u m ' , lion depends on rhe period or frequency programmed.

Both types of Sync waveform (see Gate Mode) are val- id and programmable in Burst Mode.

A burst is initiated when the unit is triggered by the se- lected trigger source. The trigger source may be the external TRIG IN. as described in paragraph 3.4.8.2, rhe internal trigger source as defined in paragraph

3.4.8.3, the BUS trigger command as described in paragraph 3.4.8.4. or the VXI trigger bus input as de- scribed in paragraph 3.4.8.5.

The Master is operatcd in continuous mode or a non- continuous mode with its trigger source set to anything other than the particular ECL Trigger line being used to trigger thc Slaves. The Slaves must be set to a non- continuous mode with the trigger source set up as above. Each module, )Master or Slave, can have all pulse characteristics (see paragraph 3.4.4) set up inde- pendently. The only restriction is that rhe master repe- tition period determined by the signal placed on the

ECL Trigger line by the Master (essentially the signal that drives its SYNC OUT) is the longest period pro- duced by any module. Each time a Slave is triggered by the Master, it must complete its output sequence, raking into consideration its period and COUNL value, and return to a quiescent state before the next Master trigger.

8.4.1 1 MasterlNlave Operatlon

,Master/Slave triggering allows a VXIbus chassis with more than one Model 1391 module installed to operare as a multichannel pulse generator system. An ECL

Trigger line is used to distribute the Master's trigger signal to the Slaves to ensure tight coupling. Addi- tionally, signal timing is optimized to closely match the t , points (start of a pulse period, see Figure 3-7 and paragraph 3.4.8.2) of the Master module [ o an adjacent

8.4.12 8tatus Commands

This subsystem contains the Status reporting registers.

Neither the Operation, nor the Questionable registers are implemented in the Model 1391. A11 queries will rerurn a "0" (zero). The Enable subcommands for each register will be accepted, bur will not perform any function. Preset may be exercised. but will pcrform no funcrion.

Circuit Description Section

4

4.1 INTRODUCTION

Figure 4-1 shows the Wavetek model 1391 VXIbus

Pulse Generator overall block diagram. The VXlbus connects to the module a1 backplane connectors P1 and

P2, which supply the module with a digital interface, power supplies, [rigger lines and a master clock. The module contains three printed circuit boards: the V X - lbus Interface Board, pulse generator Main Board, and the pulse generator Amplifier Board. The VXIbus In- terface Board conrains the VXIbus P I and P2 connec- tors and provides an interface b e w e e n Ihe VXIbus and the Pulse Generator Main Board. The Pulse Generator

Main Board receives control signals and data from the interface and genera[es pulse waveforms. The Ampli- fier Board plugs into the Main Board and provides rhe high voltage, 5OR source impedance pulse outpur sig- nal to the PULSE OUT connector.

Under the direction of its VXlbus Commander (and more directly, [he VXlbus Interface Board), the

Wavetek Mode1 139 1 Pulse Generator module produc- es pulse waveforms at the PULSE OUT BNC connec-

[or, and a TTL l e w I puIse at the S Y N C OUT BNC connector for pulse wavcform synchronization. It also receives external triggering inputs at the T R l G IN

BNC and exrernal modulating signals at the PAM IN

BNC.

The Model 1391 can also drive or receive triggering signals on the TTLTRIG or ECLTRIG lines on the

VXlbus chassis backplane. This allows intermodule triggering and MastedSlave opcration. In this manner, each .Model 1391 module can be one channel in a multichannel pulse generator system.

The VXIbus chassis backplane also providcs an analog

SUIMBUS, which is utilized by the Modcl 1391.

VXlbus

P2

VXlbus

P 1

-

'ULSE GENERATOR MAIN BOARD

I

4

Pulse Generator

DigilalCircuits

(see Figure

4-3)

SYNC OUT

-----@

VXlbus

INTER-

FACE see Figure

1-2)

--@

PAM IN

Pulse Generator

Analog Circuits

(see Figure 4-1 3)

AMPLIFIER BOARD

PULSE OUT

E l -

Figure 4-1. Model 1391 Pulse Generator Overall Block Diagram

4.2 VMlBUS INTERFACE BOARD

411 operating instructions and data for the Model 1391 module originate from ils Commander, localed within the VXI chassis. Thc VXIbus Interface Board, mount- cd within the Model 1391 module, rransfers signals be- tween the Pulse Generator and the VXlbus. An eight-position rocker switch, located on the inrcrface board, determines the module's logical address.

Because of its high density, multilayer printed circuit card utilizing LSI and custom ASIC surface mount parts. the Interface Board is documented in this manual only as necessary to support factory repair. Maintc- nance information is provided to aid in fault isolation to the board level.

4.2.1 Wlbut Ovarvlaw

A block diagram of the VXIBUS Interface Board is shown in figure 4-2. The VXIbus is contained in the chassis' backplane, and interconnects to the Model

1391 module PI and P2 connectors. Refer to the VX-

Ibus System Specifications for electrical specifications of the PI and P2 connectors, the CLK10 line, the

MODID line. the TTLTRG*/ECLTRIG* lines, and [he

TTLTRG*/ECLTRIG* protocols if detailed informa- tion is needed on the inputs to rhe VXI Interface Board.

Thc VXIbus System Specifications will also provide sys[em architecture information that will be of help to understand [he various tasks that the interface board pcrforms. For Wavetck's implcmentarion, the follow- ing sections should he understood: Device Overview, blessage Based Devices, Message Based Device Com- munication Protocols, VXIbus and IEEE-488.2 Instru- ment Protocols. Shared Memory (present, but not used in the Model 1391). and Dynamic Configuration. The

Wavetek VXlbus chip is an ASIC device which imple- ments these protocols under direction of the interface

68HC000 CPU and systcm firmware.

4.2.2 Interlace Board

The block diagram (figure 4-2) segments the Interface

Board into a VXT INTERFACE block, a CPU & MEM-

ORY block and an INSTRUMENT INTERFACE block. The VXI INTERFACE block contains the P I and P2 connec[ors, [he VXI ASIC device, the Shared h,iemory, moduIe addressing, and various drivers and transceivers. The VXI ASIC device implements the complete VXIbus Message Based Device interface. It generates control signals that regulate the transfer of data between the interface CPU and the VXIbus. The

VXIbus A16 regislers are located within the ASIC. It also controls the RUN, FAIL, MODID, A16 and A24

*

P4

-

P7

INSTRUMENT INTERFACE t

CPU L MEMORY

1

WAVETEK

CHIP

Figure 4-2. VXlbus Interface Board Block Diagram

LEDs on the module's front panel. The VXIBUS in- terface contains 32K x 16 RAh4 as 64K bytes of A241

D I 6 Shared .Memory which may be used to efficienrly move large quantities of data. The Logical Address

Switch and Bus Arbiuarion jumpers are explained in

Section 2 of this manual.

The CPU & iMEMORY bIock contains thc micropro- cessor. local RAM and ROM, decoders, a rcal time clock/timer, an interrupt controller, a bus error timcr and various drivers and transccivers. Thc local ROM eonsisis of 128K of EPROM containing VXIbus Sys- tem and Application (the Mode1 1391 Pulsc Gencrator) code. There is also 64K bytcs of local static RAX4 for variable data. stack and hcap. Thc real-time clock pro- vides timer and cvent capability. Up to seven inter- rupt inputs may be priority encoded; three from thc application (not used in the 1391), three from thc VXI

ASIC, and one from the real timc clock. The bus error timer generates a Iocal BERR\ signal if data transfer acknowledgment (Iocal DTACK\) is nor given before time-out occurs. BERR\ is generaled if a microproces- sor access cyclc exceeds 16 F ,

The INSTRUMENT INTERFACE block consists of connectors P 4 through P7. The pin-ours and signal names of the interface between the VXI Interface

Board and thc Main Board are shown in shcet 1 of the

Modcl 1391 Pulse Board schcmatic, 1 104-00-3612, in

4.8 PULSE GENERATOR BOARD

-

0161TAL CIRCUITS

Refer to figures 4- I and 4-3, orher indicated figures, and the Main Board schematic 1104-00-3612 in Sec- tion 7 of this manual for the paragraphs under this heading. The Main Board is divided into "digital" and

"analog" circuits, as indicated in figure 4- 1. These paragraphs describc the theory of operation for rhe

"digital" circuit blocks. Paragraphs under the 4.4 heading cover thc "analog" circuit blocks of the Main

Board and the Amplifier Board.

The interconnection of the digital circuits of the pulse generaror is illustrated in figure 4-3. The main signal path is indicated by rhe heavier signal lines. This sig- nal palh is for normal operation in Continuous Mode.

The signal path will be different for each mode. The following paragraphs give a quick overview of the pur- pose of each digital circuit block shown in figure 4-3.

These descriptions will be foIloured by detailed circuit descriptions concentrating on each block.

Frequancy Synlheslzer

The synthesizer's ourput is a square wave with a pro- grammable frequency range of l m H z to 100 IMHz. The synthesizer produces the basic timing signa1 for the continuous modes. The synthesizer also provides the inlernal trigger source for non-continuous modes. The synthesizer's output is routed to the S Y N C outpul to provide clock oulputs from 50 ,MHz lo 100 MHz. controI signals are described in paragraph 4.3.2 and are ilIustrated in figure 4-4.

Figure

4-3. Pulse Generator Digital Circulis

Block

Diagram

Trigger Ampllller

The trigger amplifier conditions the external triggering signal applied to the TRlG IN BNC connector. The trigger level is controlled by the TDAC signaI from the analog section.

VXlbus TfL Trlgper Recelver

The triggcr rccciver sclccts onc of the cight VXIbus

TTL Triggcr Lines to trigger the model 1391 when non-continuous modes arc selcctcd.

VXlbus ECL Trigger Racalver

The trigger receiver selects one of thc two VXIbus

ECL Trigger Lines to trigger the Model I39 1 when non-continuous modes are selected.

Trlager Source Selector

The trigger source selector selccrs one of five trigger- ing sourccs to trigger thc Model 1391 when non-con- tinuous modcs are selccred,

Mode Control Lo~lclBunrt Counter

The mode control logic provides the gating signal to the gatabic oscillatorldivider upon receiving a trigger when gated or burst modes are selected. In gated gering signal. When burst mode is selected, the gat- able oscillator runs until the programmed number of cycles havc been produced. The mode logic also pro- vides an output GATE SYNC, routed to the sync out- put driver, coincident with the oscillator's gating signal. signals accounts for thc time delays incurred driving and receiving the VXIbus ECL Trigger Lines so that master arid slave ,Model 1391's are time synchronized.

Oelay and Wldlh One-Shols

The dclay and width one-shots produce narrow output glitches ar a programmed time dclay aftcr they arc trig- gcrcd. The onc-shots have two scctions; a coarsc res- olution digital seclion and a fine rcsolution analog scction. The digital scctions providc 10 ns srcps, while the analog sccrions providc I00 ps stcps. The analog delay scctions arc controlled by the DDAC and

WDAC signals from the analog section. Thc

VBB-U74 and VBB-U82 signals arc uscd to generate

~ h c voltages.

Pulse Generator

Thc pulse generator circuitry routes the DLY TRG G signal to thc delay and width one-shots, The delay one-shot is always triggered by the DLY TRG G sig- nal. The delay one-shot's output triggers the width one-shot. Thc signal routing for normal and delayed pulses are the same. A normal pulse is a delayed pulse with zero programmed delay. When the width onc-shot is triggered, a flip-flop is set. The flip-flop is reser by the width one-shot's output. The flip- flop's output is a pulse whose width is determined by the width one-shot's programmed time delay.

When double pulses are selected, the DLY TRG G sig- nal triggers both the width and delay one-shots. The width one-shot is immediately triggered, producing a pulsc. and then triggered by the delay one-shot, pro- ducing a second pulse. When the delay one-shot is triggered, a second flip-flop is set. The output of the delay one-shol resets the flip-flop. This flip-flop pro- duces a pulse whose width is equal to the programmed dclay. This pulse, DLY, is used to calibrate the delay one-shot,

Gatable Dsclllalor~lvlder

Thc oscillator's output is a square wave with a pro- grammablc frequency range of 25 to 50 MHz when gatcd "on" by the mode control logic. The oscillaror's frcqucncy is controlled by the FDAC signal from the analog section, The oscillator also provides

IWO refer- cncc voltages, 4.SVREF and SVREF uscd by thc ana- log scction. The dividcr produces frcqucncies from lmHZ to 50 MHz from thc oscillator's output.

PGEN Source Selector

Thc source sclcctor sclccts the pulse gcncrator's trig- gering source. The sclcctor produces thrce outputs,

TRG, DLY TRG, and DLY TRG G, from thc selected triggering source. The TRG output is the triggering source. This output can be routcd to thc VXIbus ECL

Trigger Lincs to drivc othcr Model 1391's configured as slaves. Thc DLY TRG output is thc triggering sourcc dclaycd by about 20 ns. This output is routcd to the sync output driver to produce a synchronizing output coincidcnt with thc pulsc output. Thc DLY

TRG G signal is a narrow glitch coincident with thc lcading edgc of the DLY TRG signal. This signal clocks the pulsc generator. The 20 ns delay bctween the TRG signal and the DLY TRG and DLY TRG G

Output Mode Selector

The output mode selector selects the signals to drive thc differential ECL signals PULSE and PULSE\.

These signals drive thc analog section, the VXIbus

E C L m L trigger lines, and the autocalibration circuit- ry. For normal, delayed, and double pulses, the pulse gencrator's output is selected. For square wave out- puts, the DLY TRG signal is selected. The TRG sig- nal is selected for external width mode. The DLY signal is selected during an autocalibration of pulse de- lay. The CAL signal is a TTL version of the PULSE and PULSE\ signals.

Sync Source Selector

The sync source selector selects one of threc signals to drive the sync output driver. The selector also has several programmable time delays to account for the

Model 139 1's many operating modes.

Two types of sync are available from the Model 1391; pulse sync is coincident with the rising edge of the pulsc output, gate sync is high whcn bursts of pulses arc gencratcd o r thc pulsc gcncrator i s gated.

When squarc wavcs ovcr 50 MHz are prograrnmcd, [he frcqucncy synthesizer's output is routcd to thc sync driver.

Sync Output Drlver

The sync output driver level shifts the sync source se- lector's ECL output to drive TTL levels into a 5 0 R load.

The trigger driver roules the PULSE or the TRG signal to any one of the eight VXIbus TTL trigger lines. The

PULSE and TRG signals can also be routed to either of the two VXIbus ECL trigger lines as well.

Delay

-

Wldth

-

Frequency Autocallbrallan

The autocalibration circuitry is used to charac~erizc gated oscillator frequency and the delay and width one-shots digital section's pcriods.

Mlcropracessar Interface

The interface allows the microprocessor's parallel data bus to talk to the serial data ClMOS and NCMOS con- troI registers.

CMOS and NCMOS Cantral R e ~ l s l e n

The registcrs control the analog and digital sections of the ,Model 139 1. The CMOS control registers have 0 to +5 volt output levels, and control analog section and the VXIbus T T L triggcr driver and receiver sections. output levels that are compatible with thc ECL logic used throughout the Model 139

4.8.1

Sheet 1 of the Model 1391 Pulse Board schematic shows all of the connections between the pulse genera- tor and the VXIbus Interface Board. All power sup- plies and instrument control originates from the VXI

Interface Board. Coded lines are identified as follows:

'A' for address; 'D' for data, 'L' for a VXIbus Inter- face Board origin, and 'B' for a buffered line. Each front panel LED is independently enabled (logic low) or disabled (logic high) by the VXIBUS Interface

Board through control lines VA16 LD\. MID-LD\,

FAIL-LD\ and R U N L D \ .

4.8.2

Interconnect and Power Dlstrlbutlon

Dleltal Interlace and Data Reglrrterrr

Refer to figure 4-4 and Pulsc Board schematic shects 2

,Model

I .

1391 s ~ r o b e d trol, and static control. Dynamic control lines origi- nate from programmable logic devices U2 and U3.

These lincs are synchronized to Interface Board micro- processor system timing and are conrroIled by LR/W

(ReadiWrite) and LUDS\ (data strobe) to insure proper timing. LUDS\ is enabled after the 16 data bus lines have stabilized following a data change. Address lines

(LA[01:05 and 14:20]) are always controlled by the In- terface Board microprocessor. Parallel Data lines

(LD[00:15]) are bidirectional between the Interface and Pulse Boards. Parallel Data is restricted to the de- vices on sheet 24 of the Pulse Board schematic. The

Pulse Board data interface on sheets 2 and 3 of the schematic uses serial dara on the bidirectional LDOO data line.

U2 acknowledges successful dara transfer between the

Pulsc Board and VXIbus Interface Board (DTACK\).

Abscncc of this important signal results in a Bus Error

(BERR\) at the Interface microprocessor. U2 also gen- erates threc strobes for the data registcr dccoders.

REGSA strobes U1. RECSB strobes U8, and RECSC strobes U9. U1, U8, and U9 generate all of the strobed control signals. The R L Y E M dynamic control signal generated by U2 determines when thc attenuator rclays can be energized (sheets 21 and 22 of the Pulse Board schematic). U2 also generates the DAC 1-LD and

DAC2-LD dynamic conrrol signals which load data to thc DACs on shcet I 5 of thc schematic.

U3 buffers the bidirectional LDOO serial data line as

LDATAOO, which is the source o f data to all of the sc- rial data registers, which produce all of the static con- trol lincs for the pulse generator circuilry. U 3 controls thc reading and writing o f serial data to and from U4, the seriaI Calibration Data Memory. U4 is a 4096 bit

EEPROIM, organized as 256 sixteen bit words.

CS-S,MEM\ and SMELM-CLK are dynamic controls lines to U4, LDATAOO is the input data, and SLMEIMD-

OUT is the output data. This allows thc microproces- sor to read from and write to thc Calibration Data

Memory, U4, using U3 and LDOO. CS-ADC\ and

CS-901\ are dynamic control signals used to select thc

ADC (U109, Analog-to-Digital Convcrtcr) and the

Countcrflimer (U112) on sheet 24 of the schematic.

ADC-SCLK is thc ADC cIock.

When both REGSA (from U2) and LUDS\ (from the

VXIbus Interface Board) are low, three to eight-line decoder U1 briefly enables (pulses low) one of eight control lines (YO through Y7), as dctermincd by the status of address lincs LA(14: 161. Four of thcse eight strobcd control lines operate the three serial data regis- tcrs U7, U1 1, and U15, which produce thc static con- trol lincs for the pulse generator circuits that operate at normal T T L o r CMOS levels. S-CLK\ clocks all seri- al data. R-ENl\, R_EN3\, and R_EN2\ strobe regis- ters U7, U11, and U15. U7 controls the output attenuator relays (sheet 2 1 ) and the frequency refer-

-

VXlbus I N T E R F A C E BOARD

r

,

O a

J

2 s u e

D

r l W

STATICCONTROL

_) SERIALDATAOUT

TO DACs

'CMOS'

STATIC

CONTROL

E 8

E E

LUDSI

'CMOS' TO 'NCMOS'LEVELSHIFTER

V

/

U8iU9

STROQED CONTROL DEMUX

I b

+

U13, 14, 16. 17, 18, 19, 20

STATICCONTROLREGISTERS

'NCMOS'

STATIC

CONTROL

LINES

SERIALDATAOUT

TODNCs

Figure 4-4. Digital Interface and Data Registers

ence (sheet 24). U11 controls transition rime range se- lection (TRI\, TR2\, TR3\ lines to sheet 19 and the

LE<IONS and TE<IONS lines to sheer 17) and PAM enable and modes (PAMEW NPSEL\, and PPSEL\ lines to sheet 16). The serial data outputs of U7 and

UI I are also used to supply data for the quad DACs,

U87 and U89 on sheet 15. R-EN3\ is sent to enablc serial data register U15 (sheet 3 ) , which controls thc selection of TTLTRIG* outputs to and inputs from the

VXIbus backplane (shcet 6).

The remaining U 1 gcncra~ed

(U109, U110, and Ul l on shcct 24) and the BUS trig- ger. SWTRIG\ is thc softwarc gcncratcd trigger sig- nal. ADCL-EM, ADCL-CLK\, and ADCR-CLK\ selcct and enablc serial data rcgistcrs U l 10 and U1 1 1 .

Thc serial data output o f U109 connccts to thc serial data input of U 110, cascading thcm to transform thc scrial ADC data into I6 bit words [LDOO: 161 for the microprocessor.

U5 and U6, leveI shificrs, translate the normal ChlOS levels of the LA[l4: 161, REGSB, REGSC, LUDS\.

LDATAOO, S-CLK\. and L R E S E n signal lines to NC-

MOS. These signals, now with a "T" prefix, control the data decoders. US and U9. These decoders operate as described for Ul. except that their outputs (strobed control lines) are at NClMOS levels.

TDATAOO, TS-CLK\, and T R E S E n , buffered by

4.8.3

Frequency Ilyntherlzer

The frequency synthesizer consists of two sections; a phase locked loop (Pulse Board schematic, sheet 4) and a frequency divider\selector (sheet 5). The phase locked loop produces an ECL level square wave be- tween 50 and 100 MHz with 10 kHz resolution. A ba- sic phase locked loop consists of a phase comparator, a loop filter. a VCO. and a programmable (+ N) counter. The phase comparator drives the VCO via the loop filter until the + N counter's output is the same frequency and phase as the reference frequency. For outpul frequencies between 50.01 and 100.00

MHz,

"N" ranges between 5001 and 10000, with a reference frequency ( I LSB step) of 10

kHz.

The loop filter de- termines the loop dynamics as wcIl as suppresscs ref- crencc frequency sidebands. Thc Model 1391 employs a slightly different loop, called Dual Modulus prescal- ing. This technique produccs an addiriona1 digit of rcsolution at the samc time as it scales down the

100

MHz

VCO frcqucncy to a value that the + N countcr can manage. A simplified dual modulus phase lockcd loop is shown in figurc 4-5. Thc VCO's output is applicd to thc dual modulus prescaler. The prcscalcr dividcs FoYI signal. The prescalcr's output drives two low spccd countcrs; + A and + N. The + A counter controls the prcscalcr's division ratio.

(U13 through U20, except UI5, on sheer 3).

US generates the srrobcs, R_CLK[0:6]\. for the NC-

MOS data registers. U9's outputs, buffered by U12. are sen[ as strobed control signals to various pulse gen- erator circui~s. DDKCEN and WDNCEN arc sent to the Delay and thc Width onc-shots (shccts 12 and 13) ro enable the DNC2016 countcrs. Likcwisc, CDN-

CEK, SDMCEN, and BDXCEW are sent to DNC2016 cnablc pins in thc clock divider (shcct 9). frequency divider (sheet 5), and thc burst countcr (shcet 10).

PLLEN cnablcs thc singlc-chip PLL, U2 1, on shcct 4.

BRSTCNT (buffcrcd rcsct to countcrs) initializes and clcars thc Mode Control logic (shcct 7). thc Bursr

Counter (sheet 10). thc Pulsc Gcncrator (shcct I I), thc

Delay onc-shot (shcct 12), and the Widrh onc-shot

(shcct 13).

The KCMOS data rcgistcrs, strobcd by U8, are on sheet 3 of the Pulse Board schematic. These are U13 rhrough U20, excluding U15. NCMOS levels are cre- ated by running CMOS devices with -5.2 volts at [heir ground pins and -0.6 voIrs (n diode drop from ground) at their supply pins. The resulting NChlOS logic lev- els can be used as static control lines to ECL logic without further logic lcvel translation.

Flgure

4-5.

Dual Modulus

PLL

Thc counter system operates as follows. Thc overall division ratio, N total, is factored into two parts; "A" and '3'". Values for A and N are calcuIated from thc equation:

K,,,,,

= (N*P)+ The counter system di- vidcs FOY, vidcs FoU, "P" (N-A) times. In the Model

1391, "P" equals 64. For example, to produce a

100.00 MHz output, NIOU, 10000. Therefore A = 16 and N = 156 (10000 = 16 6 5 + 140 * 64).

Refer to the schematic, sheet 2. The phase lockcd loop's reference is provided by the 10 MHz VXIbus

CLKIO signals, BCLRIO+ and BCLKIO-. U29 buff- crs thc rcfercncc and drives U21's rcferencc inpur.

U21 contains a rcfercnce divider programmcd to di- vide by 1000 to provide the 10 kHz rcfercnce for thc phasc lockcd loop. U21 also contains thc divide by A and N counters along with thc phase comparator.

U21's dividers arc programrncd scrially by thc micro- processor. Scrial data, PLLDATA, is clocked inro

U21 by thc S-CLKA\ signal. Thc data larchcs into

U21 by thc PLLEN linc. Thc phasc dctcctor's output is applied to thc loop filter compriscd o f U23 and its associated cornponcnts. The phase dctcctor's oulput contains 10 kHz rcfcrcnec frequency componcnrs that would modulatc thc VCO's output. Thc sideband sup- prcssion filrcr, compriscd of U22 and its associated componcnts filrcr out thc rcfcrcncc frcqucncy compo- nents. Thc R-C filtcr, R l4-C23, providc additional high frcquency filtcring. U24 and its associatcd corn- ponents form thc VCO. The VCO's frcquency is dc- tcrmincd by thc LC tank circuit comprised of L1 and varactor diodes CR 14 through CR17. As thc voltagc on rhc varactor diodcs cathodes riscs, thc diodes ca- paei~ancc increasing the VCO's frcqucncy.

CR13, CR18. and R I 5 limit thc rangc of thc VCO's control voltagc to ensure start-up whcn powcr is ap- plied. U24's 50.01 10 100.00 MHz o u t p u ~ by U30. U25 divides thc buffercd VCO ourput by 64 or 6 5 as selectcd by U21's M C output. The phase locked loop is powered by isolalcd supplies provided by U26 thru U28. Thc VCO's 50.01 to 100.00 MHz output is successively dividcd by two providing the lower ou[put frequencies. Thc buffered VCO output is applied to multiplexer U33 and to the divide-by-two stage U32\A. U32\A's output drives the multiplexer.

U33. and the second divide-by-two stage U32\B.

U32\B1s ourput drives thc multiplexer and the ECL to

NTTL translator comprised of 4 2 , 4 3 , R23. and R24.

Thc translated 12.5 to 25 MHz signal drives program- mablc divider U3 I . Scrial data, SDNCDATA, is clocked into U31 by the S-CLKA\ signal. The data is latchcd inlo U3 1 by the SDNCEN signal. U3 1's NC-

AMOS level output is level shifted by CR19 and R22 to

ECL levels and applied to the multiplexer, U33. U33's output provides an ECL lcvel square wavc, ranging from 500 uHz to 100 MHz. Whcn frequencies bc- twccn 5 0 and 100 MHz

U32\A and B arc disablcd by thc VCOf2-OF and

VCOIJ-OF signals to remove sub-harmonic jitter causcd by coupling within thc ECL logic dcviccs. Di- vidcr, U32\B is disabled when f'requcncies berween 25 and 5 0 MHz arc programmed. U33's output, buffcrcd by one section of U30, produces the SYNTH signal. which is again buffered by U36/B producing the

BSYNTH signal.

The external triggering signal is compared to the trig- gering level signal by high speed comparator, U34; see schematic 1 104-00-36 12 sheet 6. The output of the trigger level DAC. TDAC, swings between 0 volts and

4.5 volts. An offsetting current is added via R27 and

R28 to allow serting the triggering level down to -10 volts. The input of U34 is restrained to about ~ 0 . 6 volts by CR20 and CR21 ro preserve speed. Positive feedback around U34, provided by R29 and R30, pro- duces about 4 0 mV of hystcrcsis. One section of U36 buffers U34's ourput.

4.8.5 YNlbur TTL Trlutjer Receiver

Data selector U38 selects one of eight VXIbus TTL trigger lines to drive TTL to ECL translator U35; see schematic 1104-00-3612 sheet 6. The desired trigger input is selected via the IN-TTLTRGA,

IhT-'ITLTRGB, and IN-TTLTRGC signals.

4.3.8 YNlbur ECL Trluuer Rscelvw

Thc differenrial ECL trigger signals, ETRGINO+, ETR-

GINO-, ETRGINI+, and ETRGIXI-. are buffered by two seclions of U29; see schematic 1104-00-3612 sheet 6.

4.3,7 Trlgeer Source Selector

Data selector U37, controlled by rhe TRG-SRCA.

TRG-SRCB, and TRG-SRCC signals. selects the unit's triggering sourcc; see schematic 1104-00-3612 sheet 6. The TTL level software triggering signal.

SWTRG\ signal is translated to ECL levels by one sec- tion of U35 to drive U37. U37's output invened by exclusive-OR gate U4 1 provides trigger slope selec- tion. The SLP-CMP signal sclccts the slope.

4.8.8 Mode Control LogAWur8t Counter

The mode control logic controls the operation of the 25 to 5 0 MHz gatable oscillalor; see schematic 1104-00-

3612 sheets 7 and 10. When the gated mode is select- ed, thc gatable oscillator runs for the duration of the external triggering signal, and always produces an in- tcger number of cycles. When burst mode is selected, the gatable oscillator runs until the programmed num- ber of cycles have been produced. Simplified mode control logic for the gated mode is shown in figure 4-

6. When the triggering signal goes high, flip-flop

U46\A, is ser driving its Q\ output low, starting the gatable oscillator. The triggering signal also clears flip-flop U46\B, holding its Q ourput low. When the triggering signal returns low, !he DIV-CLK\ signal from the garable oscillator clocks U46\B1s Q output

high, which clocks a low into U 4 6 h stopping the gat- able oscillator. The RES-CLK signal, produced by

U46\B. resets the gatable oscillator to a known state, ready for irs next opcrating cycle. F i p r c 4-7 shows the mode control logic configured for burst mode. Thc gIitcher produces a narrow -5ns wide pulse on the leading edge of the triggering signal. The glitcher sets flip-flop U 4 6 h starting the gated oscillator. The glitcher's output also arms the burst countcr. The burst counter counts the gared oscillator's output,

DIV-CLK, driving the B-END signal high after the programmed burst count has been reached. Flip-flop

U46\B's Q output is then clocked high which clocks

U 4 6 h stopping the gatable oscilla[or. The RES-CLK signal, produced by U46\B, resets the gatable oscilla- tor to a known state, ready for its next operating cycle.

The glitcher circuit. as shown on the schematic dia- grams, comprised of U43 sections A and B along with

R3 1 and C32 producc a narrow pulse coinciden[ with thc lcading edgc of thc TRIG signal. U43 scction C along with U44 scctions A and B form a multiplexer

hat routes thc g l i ~ c h c r TRIG signal to the

D input of U46\A under control of thc G-MODE\.

B-AMODE\. and OSCONOFF signals. U 4 S A applies rhc B-END signal o r a logic high to thc D input of flip-flop U46\B under control of thc B-AMODE\ signal.

The burst countcr is a high spccd counter that counts down from its programmed count to zcro aftcr it has bcen armcd by the B-START signal, producing thc

B-END signal. The burst countcr is compriscd of two scctions, a short count high spccd ECL scction, and a long count low spccd NCMOS section, Flip-flop U58 secrions A and B d o n g with gates U57 A lhru D form a two bit Johnson countcr, clocked from the gatable oscillator's output DIV-CLK. NOR gates U57 preset the Johnson counter to any one of its four states when flip-flop U59\8 is cleared by the B-START signal.

The states are selected by the BH14\, BH23\, BH12\, and BH34\ signals.

NTTL levels by Q18, Q19. R53, and R54 to load the programmed count into U60. When U6O counts down to zero, its CYDA o u ~ p u t CR25 and R55 level shift thc CYDA output to ECL compatible levels to drive the D inpur of U59/B high. The high leve1 is clocked thru U59\B producing the B-END signal, and reloading programmable counter U60. Serial data,

BDNCDATA. is clocked into U60 by the S-CLKB\ signal. Thc scrial data is latched into U6O by the

BDNCEN signal.

Figure 4-7. Mode Conlrol Logic

-

Bursl

4.8.0 Gatable U#clllator

I

Dlvldsr,

When gated, the gatable oscillalor (schematic 1104-00-

3612 shee[s 8 and 9) produces a 25 to 5 0 ,MHz square wave output by charging and discharging a timing ca- pacitor with a constant currenl. The frequency of os- cillation is controlled by varying the charging I discharging current. The magnitude of the current is controlled by the FDAC signal. A simplified gatable oscilIator is shown in figure 4-8. The timing capacitor is always charged with a current of +I. A current of

-21 is switched in to discharge the liming capacitor.

When the oscillalor is disabled, the timing node i s bi- ased to maintain rhe first oscillator period the same length as the following oscillator periods.

Figure 4-6. Model Control Loglc

-

Gated

The Johnson counter's output. translated to NTTL lev- els by Q 16, Q 17, R5 1 , and R52, clocks thc program- mable CMOS countcr U60. T h c Johnson counter divides thc 50 ,MHz maximum frequency DIV-CLK signal by four. producing a 12.5 X?Hz maximum clock compatible with U60, U59\B's output is translated ro

Figure 4-8. Gatable Osclllalor

Voltage divider. R35

-

R37, divides the 0 to 4.5 volt

FDAC signal down to 0 to about 3.5 volts. U48/B and

Q5 force the voltage on the botrom of R38 equal to the divided down FDAC signal; refer to schematic 1104-

00-36 12 sheets 8 and 9. U47 provides a precise

10 volts reference voltage to the voltage divider formed by R32 thru R34. Thc voltage divider produc- es reference outpurs o f about 4 . 5 volts and 5 volts that are used throughout the Model 139 1 . U48lA and 4 4 force the top of R38 to +5 volts. As the FDAC signal swings between 0 and 4.5 volts, the voltage across R38 swings between 5 and I .5 volts, producing a current o f

2.11 mA to 0.55 mA rhru RNI9/D, Q4, R38, Q5, and

RNl9/C. The end result is variable voltages referenced to the 2 1 2 volts power supply rails. The voltages drive two complementary current sources, U49

U50

-

4 6 . and

-

Q9. U49 and 4 6 force the variablc volrage to ap- pear across RN19/E, producing a collector current of

2.11 to 0.55 mA in 4 6 . US0 and Q9 opcratc in a simi- lar manner. Q9's collector currcnt swings between 1.1 and 4.22 mA as RN19 sections A and B arc in parallel.

Thc discharging currcnt is switched into the timing ca- pacitor, C36 by diode switch CR22

-

CR23. When the oscillator is disablcd, an amplifier comprised of Q10

-

Q11 and thcir associated components biases the timing node so that the oscillator's first period is thc same length as the following periods. R42 provides adjust- ment of the first period. Current source Q7

-

R40 bias- es emitter followcr Q11 with a current equal to the discharging current to compensate for QIO's Vbc shift with current. The frequency of thc oscillator is depen- dent on the value of the timing capacitor, the charging current, and the threshold voltage of U51. The oscil- lation frequency versus control voltage is also slightly non-linear. T o account for these errors, thc frequency autocalibration system measures the oscillator's output frequency at several programmed values and applies a correction factor to the FDAC signal,

The gated oscillator's 25 to 50 MHz output is succes- fer to figure 4-9 for a simplified diagram o f the divider. The gated oscillator's output is applied to a divide by 2 stage and to one input of a multiplexer.

The divide by two stages output drives another input of the multiplexer, a second divide by two stage and a

2/N stage. The 2fi1 stage output i s divided by 2 before bcing applied to the mulriplcxer. to 50 MHz, refer again to the schematic diagrams.

Three secrions of U53 add time delay to the

CLK25-50 signal to match the delays of the other di- vider paths before driving the multiplexer U55 to pro- vide [he 25 to 50 MHz frequency range. The

CLK25-50 signal is divided by 2 by U52/B. U53 adds time delay before driving the multiplexer U55 to pro- vide the 12.5 to 25 ,MHz frequency range. The

RNG2-OFF signal disables U52tB when frequencies between 25 and 5 0 MHz are programmed to remove sub-harmonic jitter caused by coupling within the ECL logic devices. The RES-CLK signal sets flip-flop

U52/B to a known state. U1 15/A, configured as a di- vide by 2 stage further divides U52/B9s output provid- ing the 6.25 to 12.5 MHz frequency range. Flip-flop

U52/A is configured as a divide by two when the

CLK-SEL signal is low which routes U52/A's Q\ our-

RES-CLK signal sets flip-flop U52lA to a known slate. When the CLK-SEL signal is high. programma- ble divider U56 is included in the feedback loop to the

D input o f U52/A. U52/A1s output is translared to

NTTL levels by 4 1 2 , 4 1 3 , R46, and R47 to drive the load inpul of U56. The 12.5 to 25 ,MHz output of U52/

B, buffered by U45, is translated to NTTL levels by

4 1 4 , Q15, R48, and R49 to clock U56. CR24 and R50 translate U56's NClMOS level output to ECL Levels.

The programmable divider operates as follows. The

RES-CLK signal sets U521A's Q output low which loads the down counter U56. U56's CYDA output

is

low which is inverted by U54 providing a high to the

D input of U52fA. When U52/A is clocked, its Q out- put goes high allowing U56 to count down from its programmed value. When U56 counls down to zero, its CYDA output goes high placing a low on U52fA.s

D input. T h e next clock reloads the down counter U56 and the cycle is repeated. U52/A1s unsymmetrical out- put is turned into a square wave by divide by two stage

U115lB. The RES-CLK signal sets flip-flop U115fB's ourput to a known state. The divide by N stage is con- figured as described above so that the placement of the lcading edge of the divided output is accurately de- fined. Serial data. CDNCDATA. is clocked into U56 by thc S-CLKB\ signal. The serial data is latched inro

U56 by the CDNCEN signal.

4.8.10 PGEN Source Selector

Multiplexer U61 selects one of three triggering sources

(schematic 1104-00-3612 sheet 1 l ) , The BSYNTH signal is selected by the C-MODE\ signal for the con-

Flgure 4-9. Divider

tinuous mode. The TRIG signal is selected via the

T-MODE\ signal for the triggered mode. The

BG-MODE\ signal selects the BGCLK signal for gated and burst modes. The multiplexer's output is applied to deIay line DL1 and to a second multiplexer, U63, along with the VXIbus ECL trigger drivers. Thc delay line's output is applied to the second multiplexer U63, controlled by the ODL-SEL\ and 5DL_SEL\ signals se- lects a fixed delay when rhe unit is configured as a master in a multiple unit sysrem. The fixed delay ac- counts for the rime delays incurred driving and receiv- ing the VXIbus ECL trigger lines. Multiplexer, U63's output clocks the pulse generator and sync output cir- cuitry. threshold voltage only, which is controlled by the

DDAC signal.

A simplified digital one-shot is shown in figure 4-1 1.

Thc digital one-shot produces precise delays with

10 ns resolution by counting periods of a 100 MHz gared oscillator. T o generate very long time delays, i.e. 2000 seconds. a large counter is required (about 38 bits). A 38-bit counter thar clocks at LOO MHz is very expensive, complex, and power hungry, so the counter is split into two sections. a 2-bit high speed ECL counter. and a 36-bit low speed C M O S counter.

4.8.1 1

Delay and Wldlh One-ehotr

The width and delay one-shots (schematic 1104-00-

3612 sheets 12 and 13) are identical; only the delay one-shot will be described. After triggering, the one- shots produce a narrow pulse. -5ns widc, at the pro- grammed time delay. The one-shots consist of a log section providing 100 ps resolution. When delays of less than 10 ns are programmed. the analog section is triggered directly. For longer delays the digital sec- tion is triggered, which in turn triggers the analog sec- tion. A simplified analog one-shot is shown in figure

4-10. Quiescently, the Q\ output of the flip-flop sits at logic high, and the timing capacitor Ct is charged to about -0.9 volts. When triggered. the flip-flop's output is released, and the current source discharges the ca- pacitor producing a linear ramp. The comparator mon- itors the ramp voltage, and clears the flip-flop when the threshold voltage is exceeded.

Figure 4-10, Analog One-Shot

Whcn thc flip-flop is clcared, its Q\ output rapidly chargcs the timing capacitor back to -0.9 volts. A nar- row pulse is generated during the timc it takcs to chargc the capacitor. Thc rime delay bctwccn this pulse and thc triggering pulsc is proportional to the threshold voltage and thc value of the timing capacitor and inverscly proportional to the discharging currcnl.

With the timing capacitor's valuc and the dischargc current fixcd, thc timc delay is dctcrmincd by the

Flgure 4-11. Digital One-Shot

The 2-bit counter provides 10 ns resolution steps, while the 36-bit counter provides 4 0 ns resolution steps. The desired time delay is factored into X

4 0 ns steps

+

Y

'L

10 ns steps

+

* analog delay. The trig- gering signal resets the flip-flop, enabling the

100 M H z gatable oscillator and !he Johnson counter, and releases the load input of the CMOS counter. Af- ter Y 10 ns steps the Johnson counter clocks the

CMOS counter. After the C M O S counter clocks X

4 0 ns steps, its carry output sets the flip-flop's D input high. On the next clock. the Q output returns high, and the counters are reloaded awaiting their next trigger.

The rising edge of the delayed pulse then clocks the analog one-shot.

Refer to the schematic diagrams in section 7. NOR gates U7 l \ A and B, route the DLYIE\ signal to the an- alog or digital one-shots, under control of the DLA-

LSEL\ and DLDSEL\ signals. When long delays are selected, the DLYIP!! signaI clears flip-flop U70\8.

U70\B's output is translated to NTTL levels by Q22,

Q23, R67, and R68 to drive the load input of CMOS counter U75. U70\B's output also enables the gatable oscillator and releases the preset inpuls of the Johnson counter. NOR gate U72\C and delay line DL3 form a

100 MHz is determined by the propagation delay of the gate and the length of the delay line, U72\A, configured as a

Vbb generator, biases the input of the delay line to en- sure that the first period of the oscillator is [he same length as later cycles. Gates, U7 1\B.

U72\B delay the oscillator's output to eliminate a race condition in the one-shot, Gate. U72\D performs a similar function.

The gated oscillator runs at about I00 MHz. The exact frcquency is unimportant, as the frequency is measured during autocalibration to determine the exact period of the "10 ns" steps. Both sections of U69 form a

Johnson or twisted ring counter. The counter has four states each with equal duty cycle, at one fourth of the clock frequency. NOR gates U68\A to D allow prcsct- ting thc counter to any of its four states. U69\B's out- put is translated to NTTL Icvcls by 420, 421, R65. and R66 to clock CMOS counter U75. CR26 and R64 levcl shift the counter's NCMOS output to ECL com- patible lcvcls. Serial data. DDNCDATA. is clocked into U75 by the S-CLKA\ signal. and latchcd into U75 by rhc DDNCEN signal. At the cnd of the long dclay period, U70\B1s Q output clocks a logic high into nip- flop U70\A to slart the analog one-shor.

Whcn short delays are sclectcd. [he D L Y N signal is routcd to the set input of U70\A to start the analog onc-shot. U73 and its associatcd components form a constant currcnt source to discharge timing capacitor

C46. Common base stage 4 2 4 buffers the current source output and limits the voltage swing of U70\A's output. U73 and 4 2 5 forcc the rcfercnce voltage pro- vided by U86 to appear across R7 1, producing a con- stant discharging current. The voltage ramp on the timing capacitor is compared against thc DDAC signal by comparator, U74\B. RC nctwork R724244.S re- duce timing jitter. U74\C buffcrs the comparator's output producing the DLPLS signal to drive the pulse generator.

4.8.1 2 Pulse Generator

The pulse generator (schematic 1104-00-3612 sheet

11) routes the triggering signal to the width and dclay onc-shots. The triggering pulse is always routed thru the delay onc-shor, as a normal pulse is a delayed pulsc with zero deIay. A simplified pulsc gencrator is shown in figurc 4-12. Thc glitcher produccs a narrow pulsc, -5 ns wide, on the rising edge of the triggering signal. This pulse triggers thc dclay one-shot. and re- sets the dclay flip-flop. Whcn double pulse is selected, this pulse is also roulcd to the width onc-shot. The de- lay onc-shot produccs a narrow pulse after its pro- grammed dclay. This pulsc triggers the width onc-shot as wcll as clocking a logic high into the delay flip- flop. The pulse rcscrs the width flip-flop 3.5 ns later.

The width one-shot produccs a narrow pulse after its programmed dclay. This pulsc clocks a Iogic high into the width flip-flop. The outputs of the flip-flops are pulses whose widths are equal to the programmed pulsc width and delay. Thc 3.5 ns delay line allows generating a puke width less than the minimum pro- grammable delay of the width one-shot. Refer to the schematics. U64 seclions A and C along with R56 and

C65 produce a narrow pulse or glitch on the rising edge of the triggering signal.

Figure 4-12. Simplified

- -

Pulse

Generator

This pulsc is routcd to the delay onc-shot. U65 sec- tions A and C route rhc pulsc to thc width onc-shot un- der contro1 of thc DP-SEL signal. R59 and R60 terminatc DL2's output into its characteristic imped- ance.

4.8.1a Output Mode Selector

The output mode selector (schematic 1104-00-3612

Sheet 11) routes the dclay and width outputs from the pulse generator and the pulsc generator triggering sig- nal to the analog pulse shaping circuitry and to the au- tocalibration system. Multiplexer, U67, under control of the PLS-SEL\, SQR-SEL\, TRG-SEL, and

DLY-CAL signals, selects the signal applied to cxclu- sivc OR gates U41\B and C. The exclusive OR gate inverts the multiplexer's output when pulse comple- men[ is selected, via the PLS-COMP signal. U4 1W.s differential outputs drive the analog pulse shaping cir- cuitry. U4 l\C's outputs drive ECL to TTL translator

4.3.14 Sync 8ource lelector

The sync source selector (schematic 1 104-00-3612 sheet 14) selccts the type of sync signal, pulse or gate, and selectable time delays to account for the various delays of the different pulse modes. U64\B, along with U117 sections A and B, select the GATE-SIG or

PLS-SRC signals under control of the SYNCTYPE signal. Thc GATE-SIG signal is delayed 20 ns by

DL7. R248 and R249 terminate the output of DL7.

Delay lines DL5, 6, and 8 add additional dclay to the selected sync signal. Data selector, US4 under conrroI of the SYNC-SELI, SYNC-SEL2, and SYNC-SEL3

signals select either the delayed sync signal or the

SYNTH signal when square waves greater than

50 MHz are selected.

4.8.15 Sync Output Drlver

The single-ended output from the sync source selector

U84 (schematic 1 104-00-3612 sheet 14) is converted to differential signals by U36 to drive diffcrcntial am- plifier 4 3 2 - 433. R90. R91, and R153 provide a con- stant current to 4 3 2 - 4 3 3 . When the sync signal changes state, transisrors 4 3 2 and 4 3 3 divert the cur- rent to ground or ro the R88

-

R89 combination and the sync output. When 4 3 3 is turned off, the sync output is pulled up to +5 volts by R88 and R89. When 4 3 3 is turned on, the constant current thru R88 and R89 drops the voltage at the sync output to about zero volts.

When an external 5OR load is connecred. a voltage di- vider is formed w i h R88 and R89 producing an upper sync level of about +2.5 volts. The lower level remajns at about 0 volts. nents disable the reference via the REFOM signal dur- ing normal unit operation. U l l 3 ' s differential ECL level ourpurs are rranslated ro TTL levels by U42.

U1 I4 section A divides the reference by 5 producing a

2MHz reference for rimer-counter U112. The timer/ counter can directly measure low frequencies up to about 10 kHz. The 25 to 50 MHz gatable oscillator is characterized by programming a burst of 50 cycles at programmed frequcncy of about 1kHz. The period of the 50 cycles is measured and the actual oscillator fre- qucncy is calculated, knowing the programmed divider ratio. This is repeated eight times for frequencies be- tween 1 and 2kHz to determine the oscillalor frequen- cy verses control voltage. The delay and width one-shots are characrcrized by programming a burs[ of fifty Ims pulses. The periods of the pulses are aver- aged and the actual gated oscillator frequency is calcu- lated knowing the programmed divider ratio.

The VXIbus ECLTRG and TTLTRG lines can be driv- en by either the pulsc signal, with con!rollcd width and delay, or the pulsc gcneraror's triggering signnl; see schematic 1104-00-3612 shccts 6, 11, and 14. U92 sections A thru D, configured as a data sclcctor. under control of thc TTLT-SEL signal. sclects which signal drives the VXIbus TTLTRG lines. One section of U42 rranslarcs [he ECL signal to TTL levels.

Data sclcctor U39, controlled by thc OT-TTLTA,

OT-TTLTB, OT-TTLTC, and TTRG-EN\ signals, se- lects which VXIbus TTLTRG line will be driven.

Only one of the VXIbus TTLTRG lines may be driven at a time. Buffer U40 provides the output drive cur- rent necessary ro drive the VXIbus backplane. The sin- gle-ended PULSE\ and P-START signals are buffered and convened to differentia1 signals by U98 sections A and C. The differential signals are received and con- verted back to single-endcd signals by U! 13 sections

A and C. NOR gates U62 and U91, configured as mul- liplexers. controlled by the EPLSSLO\, EP-SELO\.

EPLSSLl\, and EP-SELI\ signals, select which signal drives the VXIbus ECLTRIG lines. Each of the two

ECL trigger lines may be indcpendently conrrolled.

4.8.17 Delay

-

Wldth

-

Frequency llulocalihratlon

The autocalibrarion circuirry (schemaric 1104-00-3612 sheet 24) compares the frequencies of the 25 to

50 ,MHz gatable oscillator and the delay and width

VXlbus Clock10 frequency rcferencc.

The BCLKlO+ refcrcncc signal is buffered by U113U3.

Common base stage 4 5 0 0 and its associated compo-

4.8.10 Microprocessor Interlacs Schematic Dlsurarn

The analog and digital circuitry of the Model 1391 is controlled by the microprocessor located on the VXI

Interface board (schematic 1 104-00-3612 sheers 1.2, and 3). Signals to and from the interface board are routed thru connectors 54 thru J7. The microproces- sor's address space is divided into blocks by decoder

UI and PLD's U2 and U3. Calibration constants are stored in EEROX?. U4,

The analog and digital circuitry is controlled by serial input parallel output shift regisrers that are spread around the main PCB. Serial communication is used to reduce the number of signals on the board. Shift registers U7, U 1 I , and U 15 control the analog circuitry and the VXIbus TTL trigger circuitry. Thc ECL logic used throughout the Modcl 139 1 is powered from the -

5.2 volts supply. These devices have a logic high level of -0.9 volts, and a logic low level of -1.8 volts. The logic low level can bc as low as -5.2 volts but the logic high level cannot swing above about -0.6 volts without

U14, and U16 thru U20 are powered between -5.2 and about -0.6 volts via diodcs CR6 thru C R l I to control the ECL logic, The CIMOS logic levels (0 to +5 volts) of the rnicroproccssor circuitry are translated to nega- tive CMOS levcls (-5.2 to -0.6 voIts) by translators US and U6, powered thru diode CR2. Decoders U8 and

U9 further decode thc address space providing cn- abling signals to latch the data into the shift registers.

4.4

PULSE GENERATOR BOARD

-

ANALOG CIRCUITS

Refer to the Model 1391 Analog Block Diagram (fig- ure 4-13). The shcct numbers shown inside the circuit blocks correspond to the schematic diagram sheet numbers of the Mode1 139 1 main board ( I 104-00-

36 12).

4.4.1 Maln Hluh #peed llnalou fllgnal Path

The differential ECL level pulse from the pulsc gener- ator circuitry is applied to the Ievcl shifter. The level shifter converts the ECL (-0.9 to - I .8 volts) levels to a pulse of about 3Vpp centered around ground to drive the current switch. The current switch alternately switches the RE11 and FEII currenrs from the transi- rion control current sources into the timing capacitors.

As the timing capacitors charge, a linear voltage ramp is produced. The larger the RE11 or FEII current, the faster the timing capacitor will charge, providing faster edge transitions. Four ranges of timing capacitors can be selected to allow programming slower edge transi- tions. A larger timing capacitor produces a slower edge speed.

The limiter restrains the voltage on the timing capaci- tor to 1,2 Vpp. The resulting trapezoidal waveform has smooth leading and trailing edges but large amounts of overshoot that is dependent on the pro- grammed cdge speed. The trapezoid shaper clips off the top and the bottom pans of the trapezoidal wave- form. The shaper also allows selective clipping of the rop or bottom portions of the waveform to produce positive- or negative-going pulses. The multiplier pro- vides gain control to adjust the peak-to-peak output amplirude of the pujse. The pulse amplitude can be modulated via the PAM I N BNC conneclor. The our- put amplifier provides voltage and current gain to pro- duce 16 Vpp pulses into a 50R load. The output amplifier includes three attenuators to oroduce low level pulses. The signal on the VXI SUMBUS can also be added to the pulse output using the SUMBUS driver.

The SUMBUS driver contains circuitry to drive and re. ceive the signal on the VXI SUMBUS. The SUMBUS driver produces a currenl output to the SUMBUS pro- portional to the amplitude of the pulse o u t p u ~ .

The support circuitry provides the control voltages and currents required by the high speed analog signal path, and other sections of the Mode1 1391.

Control Voltaue D lo A Convertors

The Digital to Analog Convertors (DAC) provide con- trol voltages to adjust the pulse output transitions. am- plitude, and offset, the analog width and delay one-shots, the trigger IeveI, and the gated oscillator frequency.

Transillon Conlrol Current Sources

The current sources produce current oulputs propor- tionaI to rhe control voltage DAC LEDAC and TEDAC outputs to control the leading and trailing edge speeds.

Amplllude Control /PAM

This circuitry processes thc control voltage DAC out- put ADAC, and the PAM IN signal to produce the con- trol voItagc for the multiplier, AIMPCNTL, to vary the output amplitude.

Flnure 4-13. Pulse Generator Analon Circuits Block Diagram.

OelaylWldlh One-shot Control

This circuitry processes the control voltage DAC out- puts DLDAC and WDDAC to produce the control volt- ages for the width and delay analog one-shots, DDAC and WDAC,

Relay Orlver

This circuitry buffers the control lines to drive thc re- lays in the output amplifier and SUIMBUS driver.

Power Osclllalor

The power oscillator provides a 12 Vpp, 100 kHz square wave to drive the charge pump voltage conver- tor.

Charge Pump

The charge pump produces approximate 230 volts power supply rails, +SUP and -SUP, from the

224 volts VXIbus supplies and the power oscillator output. These high voItage supplies are required for the output amplifier.

Aulocal-BIT A l o D Converlor

The Analog to Digital Converter (ADC) measurcs the output amplifier output to calibrate the pulse ampIitudc and offset, The ADC also monitors several control voltages rhroughout the analog circuirry for the "Builr-

In-Test" function. the level shifter outpur to drive the diode switching bridge. C R5 1. biased by R 135- R 138. compensates for the Vbe's of 4 4 4 and 445. C96 and C97 provide AC bypass around CR5 1 to preserve the edge speeds.

The diode bridge comprised of CR52 thru CR54 alter- nately switches the FEIl and the REIl currents into the timing capacitors, Common base stages 4 4 6 and 4 4 7 buffer the diode bridge from the output capacitance of the current sources, and stray PCB capacitances. The bases of 4 4 6 and 4 4 7 are biased at about +5 volts by a resistive divider located in the transition control cur- rent sources. When the level shifter's outpul is high

(about +1.5 volts), CR53 is forward biased and 444 sources current into rhe REIl current source and re- verse biases the lower section of CR54. CR52 is re- verse biased and the FEIl current flows thru the upper section of CR54 and into the timing capacitor. When the level shifter's output is low (about -1.5 volts),

CR52 is forward biased and 4 4 5 sinks the current from the FEII current source and reverse biases the upper seclion of CR54. CR53 is reverse biased and the

RE11 current flows out of the timing capacitor thru the lower section of CR54.

4.4,2 Level Shllt

See Schematic Diagram Sheet 19 (1100-04-3612).

U98 receives the differentia1 pulse signal from the pulse generator. DuaI diodes CR45 and CR46 biased by R125 thru R128 level shift U98's output about 1.2 volts negative. Thc bases of 4 4 1 and 4 4 2 swing thru abour -2.1 to -3 volrs. 4 4 1 and 4 4 2 are configured as a differentia1 amplifier biased from a constant current source via diodes CR47 and CR48. 4 4 3 and its asso- ciated components form a constant current source.

The voltage across CR5O is impressed across R132 producing a collector current in 4 4 3 of about 28 mA.

CR49 offsets the Vbe of 4 4 3 providing first order tem- perature compensation of current. When pin 6 of U98 is high (pin 7 is low). 4 4 1 is turned on and current flows from ground thru 4 4 1 and CR47 into 443. 4 4 2 is off and its collector sits at about +1.5 volts as set by the voltage divider R 133 and Rl34. With pin 6 low.

4 4 1 turns off and 4 4 2 turns on and 442's collector sits at about -1.5 volts. To increase the speed of the level shifter. 4 4 1 and 4 4 2 are not allowed to turn

1mA) current bleed to keep the stage biased.

4.43 Current Swltch

See Schematic Diagram Sheet 19 (1 104-00-3612).

CompIcmentary emitter folIowers 444 and 4 4 5 buffer

4,4.4 Tlmlng Capacltom

See Schematic Diagram Sheet 19 (1 104.00-3612).

Four ranges of transition time are provided by timing capacitors C106 thru C109. The fastest transition range is set by C 106 and stray capacitances. Timing capacitors C107 thru C109 are switched in one at a time by diode switches CR56 thru CR58 driven by lev- el shifter 448.

The operation of the three diode switches are the same.

Only the C107 switch will be explained. C107 is se- lected by driving the T R l l line to a ClMOS logic low

(0 voIts) which turns on Q48lA. Current flows thru

Q481A and R147 and forward biases both sections of

CR56. The bottom end of C107 then see's a low im- pedance to ground and is effectively put in parallel with C 106 slowing down the edge speed.

With the T R l I signal at a CMOS Iogic high (+5 volts),

Q481A is turned off and its collector is pulled to -I2 volts via R148 reversc biasing the upper section of

CR56. The lower section of CR56 is reverse biased to about -7.2 volrs, set by voltage divider R145 and

R146, via R142.

4,4.6 Llmlter

See Schematic Diagram Sheets 18, I9 (1 104-00-3612).

The voltage across the timing capacitor is limited to about i

0.75 volts by the limiting circuit. U481D buff- ers thc 5 volt refcrcncc applicd to inverring amplifier

U971D. RN26lA and R 124 set the gain to -0.15 pro- ducing the lower limit levcl of -0.75 volts. U97IB. ar- ranged as a unity gain invertcr, produces the upper

limit level of 0.75 volts. A simplified upper level lim- iter circuit is shown in figure 4- 14. Feedback around

LT97/C maintains the voltage on the inverting inpul at

+0.75 volts. As the volrage across the timing capacitor rises, CR55 conducts and the FEIl current flows into

U97. W i ~ h equal ro FEII, the voltage drop across

CR43 is equal to the volrage drop across CR55, the volt- age across the timing capaciror will limit at +0.75 volts. tion of CR60 into R158; producing a voltage drop of about -0.5 volts across R163. At the same time, the upper section of CR59 is forward biased and currenr flows thru R157 and into [he BUTT signal.

The end result is a clean IVpp waveform across R163.

If either of the constant currents is turned off, the waveform will be clipped at ground, producing mo- nopolar pulses. 4 3 4 sections C and B are configured as swirches that turn off the current sources. 4 3 4 sec- tions A and D level shift the control signals NPSEL/ and PPSEL/ to drive the switches.

Figure 4-14. Simplified Upper Level Llmlter

C to sink thc FEII and FE12 currents. CR35 rcduccs

!he powcr dissipation in 4 3 0 . R N 2 6 E bleeds a small currcnt (about 1 mA) into 4 4 0 to stabilize its operating point. R221 and C77 provide U97K with loop com- pensation. R256 limits 4 4 0 ' s basc currenr on [urn on, as well as damping high frequency oscillations. The lower level limiter operates in the same manncr but with rcvcrscd polaritics. R223 and R224 are part of the built in tcst circuitry. The midpoint of rhesc resis- tors will sit vcry ncar 0 volts when thc limiter circuitry is operating correctly.

See Schematic Diagram Sheets 16 and 20 ( 1 104-00-

3612). U99, configured as a non-inverting amplifier with a gain of 1.67. buffers the voltage on the timing capacitors to drive the diode shaper. R162 shapes the transient response of U99. U99 is powered from about a6.9 volts via CR61 and CR62. The output of U99.

BUTT, is a waveform of about 2.5 Vpp with smoolh leading and trailing edges, but rough top and bottom edges. The distortion is caused by the turn-off time of the limiter diodes. Thc diode shaper clips off the top and bottom portions of the waveform.

Figure 4-15 shows a simplified shaper. The bridge is fcd constant currents via R157 and R158. When the

BUTT signal is high, current flows thru R157 and he upper section of CR6O into R163. producing a volrage of about 0.5 volts, At the same time the lower section of CR59 is forward biased and currenl flows from the

BUTT signal into R158. When the BUTT signal swings low, currenl flows thru R163 and the lower sec-

REVERSED

01ASED

40.5 V

Figure 4-15, Simplllied Trapezoid Shaper

4.4.7 Mulllplfer

See Schematic Diagram Sheet 20 (1 104-00-36 12). The output of the trapezoid shaper is applied to the four quadrant multiplier. UlOI. Resistors R226 and R227 terminate the unused differentia1 inputs of U101. R 170 supply. R169 biases U 10 1's positive power supply.

UlOl produces a differential current output, propor- tional to the product of the trapezoidal waveform and

[he AMPCNTL signal, into R172 and R231. Resistors

R228, R232, R230, and R233 level shift rhe outpur to within the input common mode range of U 102. U 102 converts the mulriplier's differential ourpur inta a sin- gle ended signal of about 2Vpp maximum when the output is I6 Vpp into 50R.

CR34. Additional voltage gain is provided by non-in- verting amplifier UlOO and its associated components.

RI66 and R167 set the voltage gain to about 2.6.

RI65 is used to shape UlOO's transient response.

R168 isolates U100's outpur from the stray capaci- tance of the track leading lo the SUMBUS driver. output. Diodes CR7 thru CR9 set the quiescent current in Q8 and Q9. R42 thru R45 prevent thermal runaway in Q8 and Q9. Proteclion diodes CRlO and CRI 1 limit

[he amplifier's outpur to the power supply voltages.

The amplifier's DC path is comprised of U3 and its as- sociared components, Q1, and CRI4. U3 mainrains the amplifier's virtual earth at zero volts by stealing cur- rent from Q6 via Q1. CR14 reduces the power dissipa- tion in Q1. The operating current of Q6 is larger than that of 4 7 so that QI always has to pull current from

Q6. U3 is powered from voltage regulators U 1 and

U2. Zener diodes CR12 and CR13 reduce the power dissipation in the regulators,

The amplifier's 50R outpur impedance is set by the parallel combinarion of R46 and R47. R l l allows for measuring the amplifier's ourput directly during an au- tocalibration. The amplifier's 50Q output is appIied to three relay selected "pi" section attenuators. Relay K4 is uscd to disable the ourput of the amplifier.

4.4.8 Oulpul Ampllflsr

See the Schematic Diagram Sheet 21 (1 104-00-3612) and Schematic Diagram Shccts 1,2 (1 104-00-3605).

Thc multiplier's output signal. OADRV, drives the output amplificr board. The output amplificr is a dis- crete inverting stage that providcs both voltage and currcnt gain. Thc ampIificr's output is thc sum of thc

AMPDRV, SUMIN, and ODAC signals. Thc amplifi- er's gain for the AMPDRV and SUMIN signals is abaut -6.2 sct by the ratios of the fcedback resistors.

R34, R35, and R38 to the input resistors R5 and R9,

The gain for the ODAC signal is about -1.1 sct by the ratio of the feedback resistors, R34, R35, and R38 to the input resistor RIO. Thc output ampIifier has two signal paths. There is a high speed AC path and a low spced DC correction path. The AC path is divided into two complemcntary scctions, one for cacb poIarity.

Only the positive path will bc dcscribcd. CI 1 AC cou- plcs the virtual earth of thc arnplificr into the common base amplifier 4 2 , CR5 biascs Q2's basc to +15 volts, while R20 sets the stagc's operating current to about

HmA. Emittcr follower stage 4 4 buffcrs Q2's collec- tar to drive thc gain sragc Q6. Dual diode CR1 tcm- perarurc compcnsatcs the Vbe's of Q2 and 4 4 . R22 bleeds a small current inta CR5 to ensurc start-up whcn power is applied. 4 6 operates as a constant cur- rent sourcc that is modulated by thc AC signal. Q6's voltage gain is very high as its collector load is the high impedance secn looking into the currcnt sourcc

Q7. RC network C15 - R32 adjusts thc ovcrshoot of rhe sragc, Local feedback around thc AC path via C17 and C19 adjusts thc waveform quality. Camplcmcnta- ry cmitter followcrs QH and Q9 buffer the gain stage's

4,4,8 SUMBUB Driver

See Schematic Diagram Sheet 22 (1 104-00-3612). The

SUMBUS driver is a wideband currcnt output amplifi- er. A simplified schematic is shown in figure 4- 16.

U 105lB maintains the emitter of Q55 at about -3 volts, forcing a currcnt of abaut 100 mA thru R191. This currcnt is the sum of Q55's collector current and the current flowing in R189 and R187-RI88. U104, con- figured as a unity gain differential amplifier, forces the voltage across R189 to bc equal to the input signal

SUMBDRV. 4 5 4 buffcrs thc output of U104. R189 is sclected so that a 1Vpp input signal causcs a 0 to

80 mA currcnt in R189. Rcsistors R l 7 8 and R179 bias

U104's inputs to zero volts forcing a constant 10 mA to flow in R 187-R 188. Q55's collector current will then swing between 10 and 90 mA. The 50 mA con- stant currcnt source offsets Q55's collector current, producing an 80 mApp current into the VXI SUIMBUS.

Referring ro the schematics, CR65 provides a reference voltage referred to the + I 2 volt rail. A portion of the reference is impressed across R192 by U105lA and

456, producing a colIector current in 4 5 6 of 50 mA. independent of power supply variations. R 196 allows for adjusting the nominal currenl to set the zero offsei of the driver. Rclay K 1 decouples the SUIMBUS cir- cuitry from the VXIBUS backplane. R500 and R501 provide an internal 25 ohm load to allow testing of the

SUMBUS circuitry. U106 configured as a nan-invert- ing gain of two receives the SUMBUS signal. R200 adjusts thc transicnt responsc of U106. U107, with an inverting gain of about 1.5, provides an overall gain of

-3 betwcen the VXI SUMBUS and the output arnplifi- cr. R204 adjusts thc transient responsc of U107.

U106 and U107 are powered from about 4 . 9 volts via zcncr diodes CR67 and CR6H.

4.4,10 Conlral Vollaga 0 to A Converlorr

See Schematic Diagram Sheet 15 (I 104-00-36 12).

U48lB buffers the 4.5 volts reference voltage applicd to quad 12 bit D to A convertors U87 and U89. Serial data, DACI DATA and DAC2DATA, is clocked into the DAC's by the serial data clock signal S-CLK\.

The data is latched with the DAC 1 -LD and DAC2-LD signals. Quad DAC U87 provides control vollages to the delay and width one-shor controls, the gatable os- cillator, and the trigger amplifier. Voltage follower

U901B buffers the trigger level conlrol voltage. Quad

DAC U89 provides control voltages to the transition control current sources, the amplitude contro1IPAX.l: circuitry, and the outpul amplifier. U901A and its as- sociated components offset the DAC output and pro- vide voltage gain to produce a bipolar output conrrol voltage to set the output amplifier offset. R109 and the serieslparallel combination of R I 10, R 107-R 108 provide a gain of about 7.26 to the DAC output and a gain of about -3.72 to the 4.5 volt reference. The ner ro about r17.2 volts to power U90.

See Schematic Diagram Shect 16. The 0 to 4.5 volts control signal ADAC is invcrted by unity gain amplifi- er U93lC bcforc being applicd lo the summing amplifi- e r U93lD. The summing amp has a gain of about

-0.232. providing a zero to 1 volt output control volt- age to the multiplier AMPCNTL. The PAM-IN signal is inverted by unity gain amplifier U 9 3 B and applied to the summing amplifier via analog switch U94/C.

R113 adjusts the PAM scale factor to account for com- ponent tolerances. The summing avplifier's output can be monitored for resling via R213.

4.4.1

2

Traneltlon Control Curpent 8ourcer

Sce Schematic Diagram Sheet 17 ( 1 104-00-3612). The trailing edge of the waveform is conrrolled by the TE-

DAC signal from the c o n m l voltage D to A conver- tors. U93/A buffers the DAC output to drive the two voltage dividers R214-R215 and R116-R117. Analog switches U94/A and B select which dividcr drives the current source. When a trailing edge speed of I 0 ns or greater is programmed, the TE<IONS\ signal is high enabling U94lA via Q40, which sclccts the R214-R215 dividcr. The divider providcs about a 0.28 volt input to the currcnt source for a full scale TEDAC output.

For trailing cdgcs fastcr than 10 ns, thc R116-R117 di- vider providcs about a 3.5 volt input ro the trailing edgc currcnl sourcc.

U96lA drivcs the bases of 4 3 8 sections D, B, and C via level shift zener CR39. Varying thc base voltage of Q38 varics the col1ector currcnts, Q38lD's collector current produces a volragc drop across RN25IE. Com- mon base stagc Q38lA provides a constant collccror load for 4 3 8 section D. Q38IA's base is biased to about +5 volts by voltagc divider Rh'24/D-R217. Neg- ativc fcedback around thc loop drivcs the voltagc across RN2YE equal to the input control voltage at

TP30. Because 4 3 8 scctions B and C arc similar to

*BIAS

-00 to +40 mA

SUMBUS

OUTPUT

SIGNAL

INPUT

Figure 4-16, Sirnplllied SUMBUS Drlver.

section D, and their emitter resistors are equal, the col- lector currents will be equal to that of section D. Re- sistors RI20 and R122 stop parasitic oscillations in 438.

The leading edge of the wavcform is controlled by the

LEDAC signal from the control voltage D to A conver- tors. U96/C, an inverting amplifier with selectable gain. inverts and scales the LEDAC signal. When leading edges of 10 ns or greater are programmed,

U961C provides an inpul to the leading edge current source of about -0.28 volts for a full scaIe LEDAC out- put. When edges faster than 10 ns are programmed. the LE<lONS\ signal enables analog switch U94ID placing RI 18 in parallel with R216. U96lC then pro- vides an input of about -3.5 volts to the leading edge current source.

The operation of the leading edge current source is [he same as that of thc trailing cdge. The voltages across

RN25 sections E and A can bc monitored by R2I9 and

R220 for testing.

4.4.18 Delay

-

Wldth One-shot Control

Scc Schcrnatic Diagram sheet 15 (1 104-00-3612). US5 section A, buffcrs thc DAC output to drive invcrting amplificr U851D. Thc amplificr has an invcrting gain of about 0.83 producing a swing of about 0.37 volts for a zero to full scale swing of the DAC. The amplificr adds an offsct to rhc signal that tracks thc threshold of the ECL comparator in the one-shot. The amplifier has a non-inverting gain of about 0.8 to the offsct volr- age. Thc amplifier's ovcrall output is a swing from about -1 volts to about -1.37 volts to control thc delay analog one-shot.

Thc opcrarion of the widrh analog one-shot circuitry is identical to that of thc dclay one-shot. the +12 volt supply. F1, a self-resetting circuit protec- tor, shuts down the oscillator if excessive current is drawn.

4.4.18 Charee Pump

Scc Schcmatic Diagram Sheet 21 (1 104-00-3612). Thc dual charge pump generatcs about +36 volr rails (un- loaded) for thc output amplifier. When Ioadcd the rails drop to about 232 volts. The charge pump operates by stacking thc *24 volt supplics on top of thc power os- cillator's 12 Vpp output. Simplified chargc pumps are shown in figure 4- 17.

POWER OSCILLATOR

SUP

4.4.14 Relay Drlvar

See Schematic Diagram Shect 21 (1 104-00-3612),

U103 buffers the control lincs to drive the rclays in the output amplifier and SUMBUS drivcr circuits. 4 5 3 and associated components switch the power supply to the relay coils. A flip-flop in thc microprocessor inter- face scction is sct upon power up. which turns off 453.

Oncc the microprocessor is alive and in a known state, the flip-flop is reset, driving the RLYEN\ low. turning on the power to the relays.

-24 V

Figure 4-17. Simplified Charge Pump Ctrculls

4.4.1 6 Power Oaclllator

See Schematic Diagram Sheet 21 (1 104-00-3612).

U1 I 8 a universal timer, running in thc astable mode, oscillates at about 100 kHz. Irs output at pin 3 is a 0 to

12 volt square wave. Complementary MOSFET's Q51 and 4 5 2 buffer Ul18's ourput to drive the charge pump circui~ry. C213 provides transient current 10 the

IVOSFET'S. L2 decouples thc switching spikes from

Positivc pump: When thc power oscillator's outpul is law, C221 is charged to +24 volts thru CR37. When thc oscillator's output swings up to +12 volts, CR37 is rcvcrse biased and the lop of C22 1 sits at +36 volts.

C221's charge is dumped into C217 and C225 thru

CR73. When thc oscillator's output swings low again,

CR73 is rcversc biased preventing thc discharge of

C217 and C225. This cyclc is repeated at about a

100 kHz rate.

For the negative pump: When the power oscillator's output is high, C222 is charged to 3 6 volts thru CR38.

When the oscillator's output swings down to zero volts, CR38 is reverse biased and the bottom of C222 sits at -36 volts. C222's charge is dumped into C218 and C226 thru CR74. When the oscillalor output swings high again, CR74 is reverse biased preventing the discharge of C218 and ed at about a 100 kHz rate.

Going back to the schematic diagrams, multiple capac- itors are used in parallel to reduce the ESR to improve protectors. F2 and F3, disconnecr the 224 volt sup- plies from the charge pumps if excessive currrnt is drawn from the output amplifier.

4.4.17 Autocall Bullt

-

In

-

Test Clrcullry

See Schematic Diagram Sheers 23.24 9 1 IO4-00-3612),

Unity gain followers U I08 and U 120 buffer [he inputs of the A ro D convertor U109. The outputs of the buff- ers are restrained to 1 5 volts by the dual diodes to pro- rect the ADC from over-voltage. Resistor R209 is part of a vollage divider used to calibrate the output ampIi- firr. U109 is a 12 bit successive approximation con- vertor with a serial data output. Shift registers U1 10 and U l I 1 convert the serial data to parallel data to simplify interfacing with the microprocrssor. The A to

D is clocked by a 4 MHz signal generated by dividing down the 16 MHz

Calibration Section

5

5.1 FACTORY REPAIR 5.3 REQUIRED TEST EQUIPMENT

Waverek maintains a factory repair department for The test equipment required to perform the Perfor- those customers not possessing the necessary person- mance Verification Procedure and the Alignment Pro- nel or test equipment to maintain the ins~rument. If an cedure is listed in table 5-1. instrument is returned to the factory for calibration o r repair. a detailed description of the specific problem should be attached to minimize the turn-around time.

Table

5-1. List

of Test Equipment

Equipment Quantity

Calibrarion is the process of Schedulcd iMainrmance as described in this section of [he Model 1391 manual.

Through Calibration, the unit is certified to be opera-

If the Alignment Procedure cannot be run successfully, o r if the Performance Verifica~ion Data still has out- of-tolerance readings after alignment, then refer to

Section 6 of this manual for Foulr lsolarion.

The Performance Verification Procedure may also be run before and aftcr Unscheduled Maintenance (Trou- bleshooring) to locate problcms and to ensure thar all failures have been repaired.

VXI Requirements of this manual. The Calibration is valid over a speci- fied Calibrarion hrrerval. Afrer the intcrval (rypically

1 ycar), thc opcratar rcturns thc unit to thc mctrology laboratory for Calibrarion. Units returncd ar the sehed- uIcd intcrval, wilhout a failurc description, may be cal- ibratcd and rcturned to the opcratar using the procedures in this section of thc manual,

Start thc Calibration with thc Performance Verificarion

Procedure foIlowing immediately in this section. Per- formance Verification rests the unit vigorously to the specifications in Section 1, using exlernal test equip- ment and signals at the unit's input and output connec- lors. There are Performance Verification Data sheets at the end of this section which are intended to be cop- ied and used to record the data values from the verifi- cation tesr, Completed Performance Verificarion Data sheets with no out-of-tolerance readings is sufficient for certification o f Calibrarion and rerurn ro the opera- tor.

If there are out-of-tolerance readings, perform the

Alignment Procedure later in this secrion. After suc- cessful completion of alignmenr, completc the Perfor- mance verification procedure.

Multimctcr

Oscilloscope

Frequency Countcr

Signal Gencntor

Voltage Source

Adaptors

Coaxial cable

Pro be

50R Terminadon

1

1 ea.

5.4 PERFORMANCE VERIFICATION PROCEDURE

VXI chassis.

VXI slot-0 controller.

VXI "C" board.

(Optional-see text)

HP 3478A or cquiva- lcnt.

Tektronix 2465 or equivalcnt.

HP 5334A Univcrsal

Counter.

Wavetekmodel1391 or equivalenl VXlbus gen- eraror, mggerable, s5Q accuracy from 25 Hz to

50 MHz.

-10 Vdc to +10 Vdc.

BNC female to banana jacks. BNC "tee".

BNC male connec- tors, RG58U cable.

10 M R .

Feedthrough, 0, 1% accuracy. 2W.

Thc Performance Verification Procedure is given in the following paragraphs. Thesc step-by-step proce- dures outline the equipment setup and inrerconnect.

Once set up for a reading, the various parameter set- tings and are given in the specified data table in rhe Performance Verification Data sheets at the end o f this section.

6.4.1 Preltmlnary Test8

After noting the serial number from the label bc- twcen the PI and P2 connectors, install the Modcl

I391 Unic Under Test (UL'T) in a VXIbus chassis

(no extender). Send the following command in or- der to ensure proper addressing and communica- tion with thc Commander: d) Connect SYNC O U T to the frequency counter (the use of a 3 foot RG-58 BNC cable and a 50R termi- nation will be assumed unless otherwise speci- fied). Record the I MHz = 0.01 % frequency in stcp 2 of the Data Shccr e ) If thc UUT is functional, continue with the re- maining test paragraphs.

Verify the following query response message re- turned from the UUT:

" Y a v e t e k I n s r r u m e c t s , 1 3 9 ; . C .

6.4.8 tync Waveform Characterlatlcr Terl

Purpose: Verify pulsc characteristics of sync wave- form.

Specifications: See the following table:

Allow thc UUT 30 minutcs of warm-up time. Ob- lain a copy of thc Performancc Vcrification Data shccts and fill in the preliminary data including the serial number and the UUT's software version number "X.XW.

Pcrform thc "automatic" steps of the Alignment

Proccdure by sending rhc command:

G A L S

Vcrify rhe following qucry response message rc- turned from the UUT is the valuc "00". indicaling

AutoCal passed. If a non-zero value is rcturned. rcfer to the Troublcshooting data in sccrion 6 of this manual.

6.4.2 Qulck Functional Check

Purpose: Functional test to vcrify that thc UUT is functioning correctly with power-on defaults. Also vcrifics that the pulsc outpul can bc turncd off and on.

Perform thc Sclf Tcst by scnding the command:.

'TST?

Verify error code response string is "OO", and rccord this valuc for step 1 undcr paragraph 5.4.2 of the Data Shccts. If the value is not "00". rcfcr to Appendix D.

Send thc UUT the R E S command 10 set all pa- rameters to their default valucs (paragraph 3.4.3).

Connect PULSE OUT to thc oscilloscope using 3 fcct 50R BNC cablc and 5 0 R termination at rhc oscilloscope. Verify PULSE OUT output is off.

Send the O U T P O N : O N command to turn on the PULSE O U T and SYNC OUT outputs.

Vcrify PULSE O U T is on with default values, as follows (do nor measure at this time, just verify approximate values on oscilloscope): single pulse, 1 ~5 period

*2.5 V upper and lower levels

250 ns pulse width

5 5 ns transitions

Step #

1.2

3

4

5,6

P a r a m e t e r

Sync riselfall rime

Hi

level (into 5 0 R )

Lo level (into 5 0 R )

Sync Pulsc Width

Specification

< 5 ns

>2.0 V

:

NI A

Send the following commands to the UUT:

3 E S

:{ARK O N

Connect SYNC OUT to the oscilloscope. Mcasurc thc rise time, fall time, uppcr Icvcl, and Iowcr Icv- el of thc SYNC OUT waveform. Record thcsc values in stcps 1 through 4 undcr paragraph 5.4.3 of thc Data Sheet.

Send the following commands to the UUT:

I N 1 T : C O N T OFF

T R 1 G : C O U N 3 ; T I K 1 0 E - 6

P U L S E : W I D T 1 0 0 E - 9

Measure the pulse width of the SYNC OUT wave- form and rccord the value in step 5 of the Data

Sheet.

Send the folIowing command to the UUT:

K A R K : T Y P E G A T E

Measure the pulse width of the SYNC O U T wave- form and rccord the value in step 6 of the Data

Sheet.

6.4.4 Gated Mode Teal, a ) Select an external pulse or square wave signal generator to providc a gating signal for this wsr.

This extcrnal signal must cover the rangc of

200 ns (2.5 ,MHz square wave) to 200 ms (25 Hz d) Send the UUT the

T R square wave) with 5 8 or better accuracy. The

: C O U 2 command and then the T R G command. Record the counter/ generator must be capable of being manually trig- timer value in step 2. gered for a "Ie l h e range of the external generator and set it ro a typi- ca1 value, for example "TTL" or "21 volt bipolar". e) Send [he UUT [he T R I G O U 4 command and then the T R G command. Record the counter/ rimer value in step 3. b) Send the following commands to set the UUT to

Gated ,Mode, external gating source:

R E S f) Send the UUT the and then the 'TRG

: C O U N I E 3 command command. Record the counter/timer value in step 4. Disconnect the counterltimer.

O U T P 0 N ; : F R E Q 5 E 7 ; P U L S : V I D T 1 % - 8

1 N I T : C O N T 0 P F : : T R I G : G A T E ON 6.4.8 Pul6e Amplitude A C C U ~ ~ C Y

T R 1 G : S O U R E X T : L E V < v a l u e > Purpose: Verify the accuracy of the pulse amplitude levels.

C ) where <value> is a dc voltage threshold appropri- ate for gating on the external signal, for example

+

1.5 volts for "TTL" or 0 volts for "bipolar".

Connect the PULSE OUT to a counterltimer set up to trigger on the 22.5 voh pulse output of the

UUT. Set the counrcrltimer to count "events".

Comment: Setting the UUT to the External Width function (no trigger input) causes it to output a dc volt- age ar the lowcr level value. Then setting the pulse logic to complement causes it to output a dc voltage at the uppcr level value.

Specifications: + ( ( I % of Vpp set

+

50 mV)).

+ 35 mV) + (24 d) Set the external generator for 200 ns and single cycle it. The counrer/timer should indicate t h a ~ the UUT was g a ~ e d 10 cy- cles. Record [he value in step 1 of paragraph 5.4.4 of the Data Sheets. Reset the counterltimer to "0

- h) Change the UUT to 1 rMHz, the external generator

. value in step 2. Remove the external generator.

5.4.6 Burtt Made Tett,

Purpose: Vcrify the functionality of thc triggered and burst modes, and of the burst counter.

Comment: Burst count is programmable from 1 to

~0,000,000. The observed count must be equal to tbe programmed value. a) Program the UUT as follows to set up in External

Width. dc level output:

R E S

1 N I T : C O N T 0 F F : : T R I G ; G A T E 0 N : S O U R

T 0 F P : G A T E : X O D E E X T W : : O U T P O N

V 0 L T : H I G H 8 : L O W - 8 b) Connect the PULSE OUT to the multimcter (DCV function), using an accurate 50Q termination. Set

: P O L

COW and measure the upper level value. Record the upper level value in step l a of paragraph 5.4.6 of the Data Sheets. Set

: P O L N O R M and measurc the lower level valuc and record it in step 1 b. a) Send the following commands to set the UUT to

TriggerlBurst Mode. "manual" trigger:

R E S b) Connect the PULSE OUT to a counterllimer set up to trigger on the 22.5 volt pulse output of the

UUT. Set the counter/timer to count "events".

C) Send the UUT the 'TRG command, The counter/ timcr should indicate that the UUT gencratcd a single cycle. Record the value in stcp I of para- graph 5.4.5 of the Data Sheets. Reset the counter/ timer to "0 cvents" betwccn readings. c) Program the UUT as follows:

V 0 L T : H I G H 0 . 5 : L O W - 0 . 5

P U L S : P O L C O W P

Measure the upper level value and record it in step

2a. Set PULS-:-POL and measurc thc lowm- cr lcvcl valuc and record it in stcr, 2b. d) Program the UUT as follows:

V O L T ; H I G H 0 . 2 ; L O W - 0 . 2

P U L S : P O L C O K P

,Measure the upper level value and record it in step

3a. Set ? U L : P O L N O R M and measure the low- cr lcvcl valuc and rccord it in stcp 3b.

Program rhe UUT as follows:

V 0 L T : H I G H 6 : L O V 7

P V L S : P C L COX? hlcasurc the uppcr lcvcl value and record i! in step

4a. Sct P U L S P O L N O R X and measure the low- er level value and record it in step 4b.

Program the UUT as follows:

P U L S : P O L C O K P

Mcasurc thc upper Ievel valuc and rccord it in stcp

5a. Sct P U : P O L N O R K and measure the low- er level value and record it in step 5b.

6.4.7 Pulre Wldth Accuracy Teat

Purpose: Verify pulsc width accuracy.

Comment: Pulsc width is measurcd from thc 50% voltagc lcvel on the leading cdgc of thc pulsc ro thc

50% voltage level of the trailing cdgc of thc pulsc.

Specifications:

*

( 1.0 Q of setting + 2 ns).

Program the UUT as follows:

R E S

O U T P 0 N ; : K A R K O N the SYNC OUT to the 0% voltage poinr on leading edge of the single pulse (see Figure 1.2).

Specifications:

-.

( 1.0 5" of setting + 5 nsec).

Program the UUT as follows:

R E S

O U T P O N : X A 3 K O N

V 0 L T : H ; G H 5;LO'd - 5

Connect thc PULSE OUT to CH 1 and the SYNC

OUT to CH2 of the oscilloscope. Trigger the 0s- ciIloscope from the SYNC OUT (CH2, Internal). lMeasure the pulsc delay. Record the pulse delay value in step 1 of paragraph 5.4,8 of the Dara

Sheets.

Set P V L S : and measure thepulsede- lay, and record the value in step 2.

Set P U L S D E L < v a l u e > data sheet for steps 3 through 10. Measure the pulsc delay. and record the values in steps 3 through 10.

SetFREQ lE4:PULS:'kTDT 1 E - 6 : D E L

9

.

9 record the value in step 11.

Sct F R E Q l E 3 ; P U L S : D E L 9 9 . 9 9 9 E - 6 mcasurc thc pulsc dclay, and rccord thc value in stcp 12.

Connect the PULSE OUT to CH 1 and the SYNC

OUT to CH2 of thc oscilloscope. Trigger rhe 0s- cilloscope from the SYNC OUT (CH2, InternaI).

Set P U L : WI E - 9 and measure the pulse width. Record the pulse width value in step 1 of paragraph 5.4.7 of the Data Sheets.

Set P U L S andmeasurcthe pulse width, and record thc valuc in step 2.

Set P U L S W T D T < v a l u e > data sheel for steps 3 through 10. Measure the pulse width, and record the values in steps 3

~hrough 10.

Set F R E Q 1 E 5 : and measure the pulse width, and record the value in step 11.

Set PULS:!JIDT 1 . andmeasure the pulse width, and record the value in step 12.

6.4.8 Pulra Delay Accuracy Tart

Purpose: Verify singlc pulse dclay accuracy of the

PULSE OUT.

Comment: The definition for single pulse delay is the time interval from 50% voltage point of rising edge of

6.4.8 Double Puha Dalay Accuracy T e a

Purpose: Verify doublc pulsc dclay accuracy of the

PULSE OUT.

Comment: The definition for doublc pulse delay is thc timc interval from 50% voltage point of rising edge of rhe SYNC OUT to the 0% voltage point on lcading cdge of the second puIsc of a double pulse [rain.

Specifications: + ( 1 , O % of scrting

+

5 nscc).

Program thc UUT as follows:

R E S

O U T P 0 N : : M A R K O N

P U L S : D O U B O N

P U L S : D O U B : D E L 2 0 E - 9

V 0 L T : H I G H 5 : L O V - 5

Connect the PULSE OUT to CHI and the SYNC

OUT to CH2 of the oscilloscope. Trigger the 0s- cilloscope from rhe SYNC OUT (CH2, Inrernal).

Measure the double pulse delay. Record the dou- ble pulse delay valuc in step I of paragraph 5.4.9 of the Dara Sheets.

c) Set F R E Q 1 0 : PULS : WIDT 1 E - 3 :

D0UB:DEL 1 0 E - 3 andmeasure thedouble pulse delay (use Countcrrrimcr in startlstop modc to make this measurcment), and record thc value in step 2.

(rise time) and I b (fall time) of paragraph 5.4.1 1 of the Data Sheets.

S e t ? C L S : T R A N 4 5 E - 9 ; T R A N : S T A T O N and mcasurc the pulse transitions, and record thc

6.4.10 Functlon Delay Teat

Purpose: Verify delay accuracy of the various func- tions at the PULSE OUT.

Comment: The definition for function delay is the rime interval from 50% voltage point of rising edgc of the SYNC OUT to thc 0% voltage point on the first leading edge of the selectcd function (single. double o r square).

Specifications: +

( 1.0 '% of setting + 5 nsec).

Program the UUT as follows:

RES

OUTP 0N::MARK O N

V 0 L T : H I G H 5:LOW - 5

Connect the PULSE O U T to C H I and the SYNC

O U T to CHZ of the oscilloscope. Trigger the 0s- cilloscope from the SYNC OUT (CHZ, Internal).

Measure the single pulse delay and record the val- ue in step 1 of paragraph 5.4, I 0 of the Data

Sheets.

Set P UL S : DOUB O N and measure the delay to the first pulse, and record the value in step 2.

Set FUNC : S Q U and measure the delay to the square function, and record the value in step 3.

6.4.11 Pulre Output Transltlon Tlrnet Accuracy Test

Purpose: Verify pulse transition times accuracy for the four different ranges.

C o m m e n t : T h e leading edge transition rime (rise time) is measured from the 10% voltage level to the

90% voltage level o f the leading edge of the normal pulse. The trailing edge transition time (fall time) is measured from the 9070 voltage level to rhe 10% volt- age level of the trailing edge of the normal pulse.

Speclficnlions: +

( 5.0 % of sctting + 2 ns).

Program thc UUT as follows:

RES

OUTP 0 N ; : X A R K ON

V 0 L T : H I G S 5 ; L O W - 5

Connect the PULSE OUT to C H I and the SYNC

OUT to C H 2 of thc oscilloscope. Trigger thc 0s- cilloscopc from thc SYNC OUT (CH2, Internal).

Mcasurc thc pulsc rise and fall timcs (5 ns).

Rccord thc pulsc transition time valucs in stcp l a

Scr F R E Q l E 5 : P ' L I L S WIDT 2 . 5 E - 6 .

Set PYLS : X R A < v a l u e > to the values in thc data shcct for stcps 3 through 5 , Measure the pulsc transitions, and rccord the valucs in stcps 3 through 5.

S c t F R E Q 1 E 4 : P S L S WIDT 2 5 E - 6 .

Sct PULS :TRAN < v a l u e > to the values in the data sheet for steps 6 through 7. Measure the pulse transitions, and record the values in steps 6 through 7.

Set FREC 1 E 3 : P : ' L S : V I D T 2 5 0 E - 6 :

TR A N 5 0 E -

6 . Measure the pulse transitions, and record thc valucs in step 8.

Set F X E 4 l E 6 ; P U L S : W I D T 2 5 0 E - 9 .

Se1PULS:TRAN < v a l u e > ; T R A N : T R A

< v a 1

> to the values in the data shecl (note diffcrcnt LEADing and TRAiling valucs) for steps

9 through 10. Mcasure the pulse transitions, and record thc values in steps 9 through 10.

S c t F R E Q l E 5 : P U L S V I D T 2 . 5 E - 6 .

S e t P U L S : T R A N < v a l u e > ; T R A N : T R A

< v a 1 u e

> to thc values in the data shect for stcps

11 thc pulse transitions. and record thc values in stcps 11 through 12.

S c t F R E Q 1 E S : P U L S : W I D T 2 5 0 E - 6 .

Se1PULS:TRAN < v a l u e > ; T R A N : T R A

< v a 1 u e

> to the values in the data sheet for steps

I3 through 14. Measure the pulse rraositions, and record thc values in steps 13 through 14.

5.4.1

2

Pulae Output Aberratlona Taet

Purpose: Verify pulse output wavcform quality.

Specifications: Peak-to-peak aberrations 4 5 % of

Vpp amplitude

+

20 mV).

Program the UUT as follows:

3 E S

OUTP ON; : KARK O N ; FUNC SQU

V 0 L T : H I G H 6 ; L O W - 6

Connect the PULSE OUT to C H I and the SYNC

OUT to CHZ of the oscilloscope. Trigger the oscillo- scope from the SYNC OUT ICH2. Internal). Mea- sure the peak-to-peak aberrations. Record the aberration values in srep l a (leading edge) and I b

(trailing edgc) of paragraph 5.4.12 of the Data Sheets,

5.4.18 Trlgger Level Test

Purpose: Perform functional test of the trigger slopc control and verify triggerlevel accuracy.

Comment: Trigger level is defined as the midpoint of rhe trigger circuit hysteresis. Therefore, the accuracy of the trigger level setting will be determined by ap- plying a DC level to the TRIG IN connector. The DC level will be incrernented, starting from bclow the

"Trig off' level, with respcct to the slope setting, while monitoring the generator's PULSE OUT to de- termine when the unit triggers "on". The DC level is then decremented (with respect to the slope setting) to

1 volt abovc thc programmed level setting. Veri- fy that the UUT PULSE OUT is at the lower level

(-2.5 Vdc) on the oscilloscopc. Dccremenr [he

Signal Generaror dc output in the ncgarivc direc- tion until the PULSE OUT switchcs to the upper level (+2.5 Vdc), indicating passing through [he trigger threshold. Note the value of the dc level at the DVM. Then increment thc Signal Generator dc output in the posititle direcrion until the PULSE

OUT swirches back to the lower level. Nore this value on thc DVM. Calcularc the Triggcr Level and record the value for step 4.

6.4.1 4 Syntheslzar Frequency Test ( >1Hz)

The Pulse Generator will be set 10 the External Width function so that the oscilloscope can be used to rnoni- tor the PULSE OUT and determine the trigger 'on' and

'off' points by noting a leveI change.

Specifications: + 500 mV.

Purpose: To verify functionality and accuracy of syn- thesizer up to 100 MHz ( I MHz synthesizer accuracy has been tested in paragraph 5.4.1).

Specifications: + 100 ppm. a) Program thc UUT as follows: a) Program thc UUT as follows:

RES

M A R K 0 N : : F U N C S Q U ; F X E Q 1 2 . 5 E 6

OUTP 0 N ; : I K I T : C O N T OFF b) Connect the SYNC OUT to rhe counter/timer (set up to measure frequency), Record the 12.5 MHz

TR1G:GATE:STAT 0N:XODE EXTW value in step 1 of paragraph 5.4.14 of the Data

Sheets. b) Conncct thc PULSE OUT to CH1 of the oscillo- scope. Triggcr thc oscilloscopc from CHI, Inter- nal. Connccr the Signal Gcnerator output to both

C) Set FREQ

< v a l u e

> to the values in the data sheet for steps 2 through 5. Measure the frequen- cy, and record the values in steps 2 through 5. the TRIG IN conncclor and the DVM input. Set thc Signal Gencrator to outpur approxiiately

1 volt bclow thc programmed levcl se~ting. Vcri-

6.4.16 Burst Gateable Oselliator Frequency Teat fy that the UUT PULSE OUT is ar thc lower level Purpose: To verify accuracy and functionality of

(-2,5 Vdc) on thc oscilloscope. burst gateable oscillator up to 50 IMHz. c) Incrcmcnt the Signal Generator dc output in thc Specifications: positive direction until thc PULSE OUT switches a) Program to the upper level (+2.5 Vdc). indicating passing throughthe trigger threshold. Note the value of the dc level at the DVM. Then decrement the Sig- nal Gencrator dc output in the negative direction

RES

+ 2%.

UuT as

1NIT:CONT OFF until lhc PULSE OUT switches back to the lower

Icvcl. Note this value on the DVM. Calculate the

Triggcr Level as follows:

TRIG:SOUR EXT:GATE O N

M A R K 0 N : : F U N C S Q U : F R E Q 1 0 0

Tririgger level =

( "Trig orr " level + "Trig of' level ) / 2

Record rhe Trigger Lcvcl under paragraph 5.4.13. step 1 in the Data Sheets. d) SendtheUUTTR1G:LEV < v a l u e > . w h e r e b) Connect the SYNC OUT to the counterltimer (set up to measure frequency). Set the Signal Genera- ror to output approximately +5 Vde and apply i t to the TRIG I N connector of [he UUT. Record the

LOO Hz value in step 1 of paragraph 5.4.15 of the

Data Sheets. through 3. Rcpcat rhe procedure of steps b) and c ) C ) Set FREO < v a l u e > to the values in the data abovc ro calcuIate and record the Trigger Level shcct for steps 2 through 9. Measure the frequcn- values under steps 2 through 3. cy. and record the values in stcps 2 through 9. el S e n d t h e U U T T R 1 G : S L O P NEC;LEl! - 5 .

Set the Signal Generaror to outpul approximately

6.4.18 External Trlugar Frsquencler Tsrt

Purpose: T o verify functionality of exrernal trigger input up to 5 0 MHz at minimum specified amplitude.

Setup: Single Pulse function. Pulse width lOns. Modc triggered.

Specifications: Frequency accuracy equal to that of the external SignaI Generator;

2

100 ppm i f a second model 1391 is used. a) Program the UUT as follows:

R E S

XARK 0 N : : I N I T : C O N T O F F c) S e t T R 1 G : T I X 1 E - 6 a n d r e c o r d t h e l M H z i n - ternal trigger frequcncy in step 2. d) Program the UUT as foIlows:

TR1G:SDUR 'T'TLTO

Program rhe extcrnal Signal Generator as follows:

F R E Q 2 2 3

Record the 2 kHz frequency in step 3. e ) Program the UUT as follows:

Program thc external Signal Generator as follows:

P R E Q ( f r e q u e n c y ) up to measure frequency). Verify that rhe UUT is no[ generaring a frequency. Set up thc Signal

Generator for a 100 Hz, $1 volt square (when properly terminated) and connect its output to the

TRIG IN connector. Record the 100 Hz value in step 1 of paragraph 5.4.16 of the Data Sheets. c ) Set the SignaI Generator to 50 MHz. Measure the

UUT frequency and record the value in step 2.

Where the parameters <source> and <frequency> are taken from the Data Sheet step as the test step advances from step 4 through step 12. Record the

UUT frequency value for each step in the Data

Sheet.

6.4.17 Trlgger Source Test

Purpose: Pcrform functional test to vcrify that all thine.cn triggcr sources arc selectabIe and operational.

Comment: The thirteen triggcr sources arc; External,

Intcrnal, BUS, VXIbus eight TTLTRG lines, and thc

[wo VXIbus ECLTRG lines. "External" and "BUS" trigger have bcen vcrified in a previous tcst. "Inter- nal" scIccts the internal trigger generator. A second model 139 I o r equivalent VXIbus modulc will be re- quircd to output triggering signals to the VXIbus ECL and TTL triggcr Iines. Thc commands given in this tcst for the cxternal Signal Generator will assume that a model 1391 is used.

Specifications: Intcrnal: + 100 pprn. For ECLTRG and TTLTRG, frequency accuracy equal to that of the external Signal Generator; + 100 ppm if a second mod- el 139 1 is used.

Program thc UUT as follows:

RES

XARK ON : : I N I T : CONT O F F

P U L S : W I D T 1 0 E - 9

T R 1 G : S O U R 1 N T : T I M 2 0 E - 9

Connect the SYNC O U T to the countcrltimcr (set up ro measure frcquency). Rccord the 50 h3Hz value in step 1 of paragraph 5.4.17 of the Data

Shcets.

6.4.18 Trlgger Output Mode Tert

Purpose: Perform functional test to verify that the

Pulse Generator can serve as a trigger source for one of eight of the VXIbus TTLTRG lines, and one of two of the VXIbus ECLTRG lines. There are two possible sources for this signal, T R I P and PULSE.

Specificalions: Trigger frequency generated by the

139 1 UUT accuracy is + 100 ppm. a ) Program the UUT as follows:

RES

FUNC S Q U : F R E Q 1 2 E 3

Program the cxtcrnal Signal Generator as follows:

R E S

MARK 0 N : : I N I T : C O N T OFF

T R 1 G : S O U R TTLTO b ) Connect the cxternal Signal Generator's SYNC

O U T to the countcrltimer (set up to measure fre- quency). Record the 12 kHz value in step 1 of paragraph 5.4.18 of the Dara Sheets. c) Set the UUT oUTP : T T L T O : SOUR PULS : :

FREQ 1 1 E 3 and record the I I kHz trigger fre- quency in step 2.

Set the UUT OUTP : T T L T O : S O U R T R I P .

Program the external Signal Gcncrator as follows:

3 I G : S O U R < s o u r c e )

Program the UUT as follows:

F R E Q ( f r e q u e n c y )

O U T ? : < t r i g line) ON

Where the parameters <source>, <frequency>. and elrig line> are taken from the Data Sheet srcp as h e rest stcp advances from step 3 through step 10.

Record the Signal Generalor's triggered frequency value for the listed steps in the Dara Sheet.

Set the UUT O U T P ECLTO : S O U X P U L S :

F 2 EQ 1 ? E 3 and rccord rhc 1 1 kHz triggcr frc- qucncy in step 11.

Set the UUT : E C L T 1 : S T A T O;4 : S O U R

T X I P : 1 0 E 6 , s e t t h e S i g n a l G e n e r a t o r

7 R I G : S O U R E C L T 1 , a n d r e c o r d t h c l O M H z trigger frequency in step 12.

Set thc UUT : E C L T 1 : SOUR P U L S

F R E Q 2 I E 3 and record the 21 kHz trigger fre- quency in step 13. c) Connect the UUT'S PULSE O U T to the oscillo- scope CH1 and the external Signal Generator's

PULSE OUT to CH2. Record the time skew value between the

I W O rising edge 50% poinrs in step 2.

Purpose: Pcrform functional test of the SUMBUS drivcr and rcccivcr scction, and vcrify voltagc scaling accuracics.

Comment: This test can only be run if the external signal gencraror is a VXIbus module supporting the

SUMBUS per the VXIbus System Spccifications. This procedure will use SCPI commands which assume that the external gcneraror is another Wavetek model 139 1 ,

Specification: The 139 1's SUMBUS driver outputs

5 mA per volt (at rhe Pulse Output) to the 25Q 2%

+

2.5mA). The

1391's SUMBUS receiver generates 8 volts at the

Pulse Output per volt SUMBUS signal with an acuracy

+

200 mV

+

2.5 mA). End-to-end specifica- tion (one 1391 driving the SUMBUS, one 1391 receiv- ing) is the sum of thc percentage and offset volrage terms, and the current offset terms mulriplied by 25R and the receiver gain of eight. This results in *(Id%

+

1.2 V) end-to-end.

Program the UUT as follows:

6.4.1 0

Masterl8lave Tert

Purpose: Perform functional tcst of rhe MASTcr/

SLAVe control, and vcrify intermodule timc skcw ac- curacy.

Comment: This test can only be run if the external

Signal Gcneraror is a Wavetck model 139 1. The UUT is designated the MASTer. The model 1391 used as the external generator is designated as the SLAVe.

The ,MASTer and SLAVe units must be in adjacent slots in [he VXIbus chassis to test close coupling of signal delays.

Program the UUT as follows:

R E S

O U T P 0 N : E C L T O 0 N : : K A R K ON

T R I G : X O D E K A S T

Program the external Signal Generator as follows:

O U T P 0 N ; : I N I T : C O N T O F F

T R I G : S O U R T 0 F F : : V O L T 4

Connccr rhc UUT's PULSE OUT to thc DVM.

Rccord thc lower level valuc in step 1 of para- graph 5.4.20 of the Data Sheets.

Program the UUT a s follows:

S 0 U R : S U X B O N

Program (he exrernal Signal Generator as follows:

M A R K 0 N ; : O U T P 0 X : : I N I T : C O N T O F F

T R 1 G : S O U R ECLTO

Connccr the UUT'S SYNC OUT to the oscillo- scope CH1 and the extcrnal Signal Generator's

SYNC OUT to CH2. Triggcr the oscilloscopc in- tcrnally from C H I . Record thc timc skcw value bctwccn the two rising edge 50% points in stcp 1 of paragraph 5.4.19 of thc Data Shrcts.

1 N I T : C O N T 0 F F ; : O U T P : S U M B O X

T R 1 G : S O U R T 0 F F : : V O L T 4

: P O L C O X P

Record the lower level in step 2.

Set the external Signal Generator V O L T 1 6

.

Record the lower level in step 3.

Perform sreps a ) through d ) above, except reverse the rolcs of the "UUT" and the "externaI Signal

Generator". Record the data values in steps 4 through 6.

6.4.21 PAM Input Teat

Purpose: Perform functional test of the PAM IN cir- cuitry, and verify voltage scaling accuracies.

Program the UUT as follows:

S O U R T O F F : 10

P U L S : P O L C O X P

Connect the UUT's PULSE OUT to the DVM.

Record the upper level valuc in step 1 of para- graph 5.4.21 of the Data Sheets.

Set the UUT P U L S : lower level in step 2.

P O L N O R K and record the

Apply

+

1.00 Vdc to the UUT's PAAM IV connec-

Lor. Verify accuracy with the DVM.

Set the UUT to PULP: O N : ?ULS : POL COXP and record h e upper level in stcp 3. Set the UUT

POL NORK and record the lower level in step 4.

Set the UUT

LO

PLJL;.i: ; : P U L S

O L C O X P and record the upper level in step 5 .

Set the UUT : lower level in step 6 .

P O L L O R M and record the

Set the UUT to : : P U L S

P O L C O N ? and record the upper level in step 7.

Set the UUT P U L S lower level in step 8. and record the moving across the components. T h e Pulse

Generator has many high-speed digital logic devices and discrete analog circuits which require some cooling air for continu- ous operation. Do not operate the module in this configuration for more than a few minutes without directing some cooling a i r across the face of the Main Pulse Board and the Amplifier Board using an external utility fan. Avoid burns

- d o not touch components in the module,

The model 1391 performs a Self Calibration in re- sponse to rhe SCPI C A L [ : I

? command or ro the

IEEE-488.2 C A L ? command. The Self Calibration performs only those steps in the "full" Calibration pro- cedure of paragraph 5.5.5 which are marked "automat- ic". Self Calibration steps are performed by the instrument firmware at any time the operator/program- mer sends the appropriate commands following the 30 minute warm-up. Self Calibration sets up various in-

This completes the Performance Verification-

Procedure. age s m d a r d s to store "fresh" Alignment Data which is used to optimize the unir's performance accuracy.

During the Self Calibration, the unit disconnects all in- puts and outputs, and at the end of Self Calibration it restores its current setup.

A Self Calibration is performed just prior to running the Performance Verification Procedure. Therefore, if there is an out-of-tolerance reading, the Self Calibra- tion is not likely to correcr it, and the "full" Alignment

Procedure in paragraph 5.5.5 should be run.

ALIGNMENT PROCEDURE

The procedure given in paragraph 5.5.5 requires that the model 139 1 be part of a VXI system as described in table 5-1. The model 1391 will be installed on a C- size VXI extender card and controlled by the Resource

,Manager, The computer/dispIay device can be the Re- source )Manager (internal host in a Stand-Alone sys- tem) or an externaI host connected to the Resource

Manager via the IEEE-488 (GPIB) programming bus.

With the covers removed, low voltage d c power supplies a r e exposed. Do not be misled by the term "low voltage". Under adverse conditions, potentials as low as 50 volts can cause serious injury o r death.

With the module on a n extender card and the covers removed, no chassis cooling a i r is

6.6.2 Seml-Automated Procedure

When the alignment procedure is initiated, the Model

1391 firmware returns an abbreviated dcscription of the current alignmcnt step to the system console, and instructs the Pulse Gencraror to modify its settings in preparation for making that adjustment. The abbrevi- ated description identifies the parameter. alignment tolerance, and adjustment component. Thc proccdurc is initiated by sending 'DIAG:CAL?', followed by thc alignment stcp number. and a program message termi- nator.

NOTE

The completion of the alignmenr procedure rerurns rhe itlstrumenr ro correct dignmenr.

Alignment limits and tolerances are nor irrstrument specifications. lnsrrurnenr speciji'cariorrs are given in Section

1 of rhis Manual.

Obtain access to adjustable components by removing the side panel wirhout the address switch cutout.

Mount the module on an cxtcndcr card, or plug i t into a VXI chassis connector that will allow access during calibration. Provide cooling air across the face of the module using the VXIbus chassis or an cxternal utility fan. Allow at least a 30 minute warm-up.

6.6.4 Connaclor Termlnatlon

When used as tcst points, the SYNC OUT and PULSE

OUT conncctors must bc terminated with 50R.

2) Automatic linearity adjustment of burst gateable oscillator frequency. a ) Send thc command:

h ) Successful completion of this step is indicated by the response message;

( r e s p o n s e m e s s a g e > . P z s s e d

3) Automatic measure of width gateable osci1lator frequency

. a) Send the command:

6.6.6 Allgnrnent Procedure

To prepare the instrument for each step, send

'DIAG:CAL?', followed by the calibration step num- ber and the END program message terminator (see paragraph 3.3.2.5). For steps that are identified as in-

[eracling with another step, all interacting steps must be within calibration tolerancc before advancing to [he next step. Figure 5-1 shows test point and adjustment

Iocarions. b) Succcssful cornplction of this stcp is indicatcd by the rcsponse mcssagc;

( r e s p o n s e n e s s z g e ) . P a s s e d

4) Automatic measure of dclay gatcable oscillator frcqucncy. a ) Scnd the command:

NOTE

An auromared version o f rhis procedure is available ro reduce rhe set-up rime and operator programming. The program is wrirren rising WaveTesr'" and rhere are operaror panels which prompts rhe calibraror wirh insrructions

O H which conrponenrs/ parameters ro adjust. For customers wirh rhe

WaveTest" programming environmenr, this program can be obrained-from rhe Waverek

Customer Service deparrmenr (see paragraph

6 . 1 ) .

J f

rhe calibrarion program is not available, then perform the procedure below f o calibrare rhe rtnir. The pulse widrh, pulse delay and rhe rise/fcrll tinre calibration section requires be entered inro rhe Model

1391 darabase.

Instrument set-up and database initialization a ) Scnd the command to force insrrument powcr- up statc; b) If thc unit being calibrated has bccn repaircd or is known to bc opcrating outside of spccificd lim- its, then scnd thc command ro initialize inrrumenr databasc; b) Succcssful cornplction of this stcp is indicated by thc rcsponsc mcssagc;

( r e s p o n s e m e s s a g e ) . P a s s e d

5 ) ,Manual calibration of amplitude limitcr offset. a ) Scnd the command:

: d i a g : c a l ? 4 b) Connect DMM HI to Output AmpIifier P1 pin

5 , and DMlM LO to Output Amplifier TP1.

C ) Apply a 500 mVpp, OV offset. 0.05 Hz square wave from the function generator to PALM input

BNC of rhe pulsc generator. Use the 5 0 R feed-rhru terminalor, d) Adjust

The absolute value of the offset voltage is unim- portant. e ) Disconnect the cable to the pulse generator

PAM input BNC.

6 ) Manual calibration of pre-amplifier offset. a ) Send the command:

: d i a g : c a l ? 5 b) Connect DIMM HI to Output Amplifier P1 pin 5, and DMIM L O to Output Amplifier TP1.

C) Adjust R520 for a DC offset of < 2 mV. d) Disconnect DMM leads.

Automatic amplitude and offset calibration, a) Send the command: b) Successful completion of this slep is indicarcd by the responsc message;

( r e s p o n s e m e s s a g e ) . P a s s e d

IManual pulsc amplitude modulation gain calibra- tion. a) Send the command:

500 mVldiv, 5 0 S2 internal load of the scope. Sync rhc scope on CHZ. Set a sweep rate of 10 nsldiv. b) Send the command:

: d i a g : c a l ? ! O c ) Adjust R76, R33 and C19 on the Output

Amp and R165 on mainboard for minimum aber- rations ( < 4 8 of peak-to-peak amplitude). Verify r h a ~ < 5 ns.

NOTE

If sarisfacrory resrrlrs are not obtained f i e . , b) Apply a 0.500 VDC signal from the function generator to PAM input BNC of the pulse genera- tor. Use the 5 0 R feedthru terminaror.

C)

Adjust R113 for a change of 0 . 5 Vdc

2

10 mV measured by the DIMM at PULSE OUT of' rhe pulse generator. Use the 50 R feedthru terminator a1 PULSE OUT BNC. d) Disconnect the cable to the pulse generator

PAM input BKC.

Gareable Oscillator First Period Adjustment. a) Connect PULSE O U T of the pulse generator to the scope C H 1, 2VIdiv. 5 0 R internal load. Con- nect the pulse generator's SYlUC OUT to CH2,

500 mVIdiv, 5 0 S2 internal load of the scope. Sync the scope on CH2. Set a sweep rate of 5 nsldiv,

X I 0 magnifier on. At cursors on, b) Send the command: c ) Using the cursor and the horizontal position controls, measurc the period of thc third cyclc of the burst. T h e period should be approximately

4 0 ns.

measure

the period of the first cyclc of the burst and adjust R42 to the same period as the third cycle. d ) Send the command: inlo specificarion ar the same rime), reset the four adjusrmenrs of srep c ) a s indicated in

Figure 5-1 and repear the srep.

1 1) SUMBUS offset adjustment. a) Connect the DIMAM HI to P7-A18 on the VXI lntcrfacc board. Connect the DAMIM LO to TP38 on the 1391 pulse generator board. Measure and record thc SUMBUS D C offset and make sure it is < I m V before continuing. b) Send the command:

: d i a g : c a l ? 1 1

C) Adjust R196 for the same SUMBUS dc offset as measured in 1 l a above

2

1 mV.

12) Width one-shot analog calibration. a ) Connect PULSE O U T of the pulse generator to the scope C H I , 2 Vldiv, 5 0 R internal load. Con- nect the pulse generator's SYNC O U T to CH2,

500 mVIdiv, 5 0 R internal load of the scope. Sync the scope on CH2. Set up the scope for pulse width measurement. b) Send the command: e) The period should be approximately 20 ns at this step. Repeat the measurements of the periods of cycles 1 and 3 as in step 9.c.

Ajusl R42 to split the error difference between the adjustment in step 9.c and this step. f) Repeat sreps 9.b through 9 . e as necessary ro minimize the errors.

10) Waveform Quality adjustment. a ) Connect PULSE O U T of the pulse generator to the scope C H I , 2 Vldiv, 5 0 S2 internal load. Con- nect the pulse generator's SYNC OUT to CH2,

C )

Measure the pulse widrh from the 5070 point of the rising edge to the5070 point of the falling edge of the signal at PULSE OUT. This value should be around 17.0 ns, d ) Send the command:

: d i e g : c a l : r n e a s 1 2 , < p u l s e w i d t h ) where pulse width is the measurement made in slep 12.c above. This stores the measurement made into the model 1391 dalabase. e l Send thc command:

: d i a g : c a l ? 1 3 f) Measure the pulse width from the 50% point of the rising edge to the50% point of the falling edge

of the signal at PULSE OUT. This vatue is ap- proximately 29.0 ns. g) Send the command: where pulse width i s rhe measurement made in step 12.f above.

13) Delay one-shot analog calibration. a ) Connect PULSE O U T of the pulse generator to the scope C H I , 2 Vldiv, 50 R internal load. Con- nect the pulse generator's SYNC OUT to CH2,

500 mVldiv, 50 R internal load of the scope. Sync the scope on CH2. Set up the scope for pulse dc- lay measurement. b) Send the command:

: c a l ? 1 4 c) Measure the delay from the 5 0 8 poinr of the

SYNC O U T signal

10 the 070 point of the PULSE

OUT signal. This value is approximarely 10.0 ns.

NOTE

The delay ar rhe 0% poirrf of rhe PULSE OUT signal can be easily found by following [he sfeps below.

1) Measure thc delay from thc 5070 point of thc SYNC OUT signal to the 5070 point of the PULSE OUT signal.

2

3

O U T signal at the 10% to 90% points.

Multiply this number by 518.

The 0 % delay is found by subtracting thc numbcr found in srep 2) from the numbcr found in step 1). d ) Scnd rhc command:

: d i a g : c a l : m e a s i 4 . < p a l s e d e l a y > where pulsc delay is the mcasurcmcnt made in step 13.c abovc. c) Scnd rhc command:

: d i a g r c a l ? 1 5 f) Measure the dclay from the 5 0 8 point of thc

SYNC O U T signal ro thc 0% point of the PULSE

O U T signal. This valuc is approximatcly 22.0 ns. g) Send thc command:

: d i a g : c a l : m e a s 1 5 . < p u l s e d e l a y ) where pulsc delay is thc rncasuremcnt made in stcp 13.f abovc.

14) Leading edgc transition times measurcmcnt. a) Connect PULSE O U T of the pulse generator to

[he scope C H I , 2 Vldiv. 50 R internal load. Con- necr [he pulse generaror's S Y N C O U T to CH2,

500 mV/div, 50 R internal load of the scope. Sync rhe scope on CH2. b) Scnd rhe command:

: d i a g : c a l ? < s t e p n u m b e r ) where <step number> goes from 16 through 45.

C )

Measure rhe rise time at the 10% to 90% points of the pulse on the PULSE O U T BNC. d ) Send the command:

: d i a g : c a l : n e a s < s t e p - n u m b e r ) .

( m e a s u r e d v a l u e > whcre <measured value> is the measurement made in srep 14.c above. e) Repeat steps 14.b through 14.d for the remain- ing srep numbers.

Trailing edge rransition limes measurement. a ) Send the command:

: c a l ? < s t e p n u m b e r ) where <step number> goes from 46 through 75. b) Mcasure the fall timc at the 90% to 1070 points of the pulse on the PULSE O U T BNC. c ) Scnd the command:

: d i a g : c a l : m e a s

< s t e p - n u m b e r > . < r n e a s u r e d v a l u e > where <measured valucz is the measurcrnent made in step 15.b above. d) Repcar steps 15.a through 15.c for the remain- ing stcp numbers.

Databasc storage a) Scnd thc command:

: d i a g : c a l : s a v e to store the measured constants into non-volatilc memory.

NOTE

To veriJL rhe accuracy of Aiignmenr Data in srorage, send rhe command D I A G : S ?

< n

> to query the values for a given srep < n > .

These values may have been entered e i ~ h e r auromaricaily or manrrully.

An our-of -rolerance Performance Vergicarion step may have a falilry data enfry relating f o rhur paramerer.

T h i s completes the Alignment P r o c e d u r e .

Flgure 5-1. Test Polnts and Adjustments.

Serial Number

PERFORMANCE VERIFICATION

D

ATA SHEETS

Wavetek Model 1391 VXlbus Pulse Generator

Test Conductor

Date Flrmware Version

Hlstory:

0 Scheduled Malntalnance (Callbratfon)

5 . 4 2 Qulck Functional Check

Step # Parameter

1 'TST Error Response

2 1 MHz Frequency

Lo llmlt

00

999,900

Reading HI lirnlt

00

Unit

NIA

1,000,100 Hz

Step # Parameter

1

2

Sync Rise time

Sync Fall time

3

4

5

6

Hi level(into 50R)

Lo level(into 50R)

CLOCk Type Sync Width

GATE Type Sync Width

Lo llmlt

NIA

NIA

2.0

N I A

400

2

Readlng Hi llmlt

5.0

5.0

NIA

0.4

600

3

Unlt ns ns

V

V ns

us

54.4 Gated Mode Test.

Step # Gate Stgnal Wldth

1 200ns

2 200ms

L o Ilrnlt

9

180,000

Readlng HI l l m l t

11

Unlt

Events

220,000 Events

Step # Burst Count

1 1

2

3

4

2

4

1,000

L o llrnlt

1

2

4

1,000

6.4.8 Pufee Amplitude Accupacy Test

Step #

1 a l b

4a

4b

5a

5b

2a

2b

3 a

3b

Parameter

8V upper level

-8V lower level

0.5V upper level

-0.5V lower level

0.2V upper level

-0.2V lower level

8V upper level

7 V lower level

-7V upper level

-8V lower level

L o limlt

7.755

-8.245

0.405

-0.595

0.1 1 1

-0.289

7.755

6.755

-7.245

-8.245

5.4.7 Pulse Width Accupacy Test

1

2

3

4

5

6

Step # Parameter

10 ns Pulse width

13 ns Pulse width

14 ns Pulse width

15 ns Pulse width

16 ns Pulse width

28 ns Pulse width

L o limit

Readlng

Readlng

Reading

HI llmlt

1

2

4

1,000

Unlt

Events

Events

Events

Events

H I limit Unlt v v v v v v v v v v

HI limit Unlts

Step # Parameter

7 38 ns Pulse width

0

9

10

11

12

48

58

68 ns Pulse ns Pulse ns Pulse

999

1.999 width width width ns Pulse width us Pulse width

5.4.8 Pulse Delay Accuracy Test

Step #

5

6

7

8

1

2

3

4

9

10

11

12

Parameter

0 ns Pulse Delay

8 ns Pulse Delay

9 ns Pulse Delay

10 ns Pulse Delay

11 ns Pulse Delay

23 ns Pulse Delay

33 ns Pulse Delay

43 ns Pulse Delay

53 ns Pulse Delay

63 ns Pulse Delay

9.999 gs Pulse Delay

99.999 ps Pulse Delay

Lo limit

-5.00

2.92

3.91

4.90

5.89

17.77

27.67

37.57

47.47

57.37

9.894

98.994

5.4.8 Double Pulse Delay Accuracy Test

Step # Parameter

1 20 ns Double Delay

2 10 ms Double Delay

Lo limit

14.8

9.90

5.4.10 Function Delay Test

Lo llmlt

35.62

45.52

55.42

65.32

987

1.977

Step # Parameter

t

2

Single Pulse

Double Pulse

3 Square

Lo limlt

-5.00

-5.00

Reading

Reading

Reading

H i llmlt

40.38

50.48

60.58

70.68

101 1

2.021

Unlts n s ns ns n s n s

P S

H i limlt

5.00

13.08 l4,Og

15.10

20.23

38.33

48.43

58.53

68.63

10.104 lOl.OO4

Unlts n s ns ns n s ns ns n s ns ns n s

PS us

HI l i m i t

25.2

10.10

Units n s ms

H i limit

5.00

5.00

Unlts n s ns

5.4.1 1 Pulse Output Transltlon llmes Accuracy Test

Step # ParameterlTransltlon tlme L o Ilmlt

Rise time15 ns

Fall time15 ns

Rise time145 ns

Fall time145 ns

Rise time155 ns

Fall time/55 ns

Rise time1450 ns

Fall lime1450 ns

Rise time1550 ns

Fall time1550 ns

Rise time14.5 ps

Fall timd4.5 ps

Rise timel5.5 ps

Fall time15.5 ps

Rise timel50

LLS

Fall time150 ps

Rise t1me125 ns

Fall time1250 ns

Rise time1250 ns

Fall time125 ns

Rise time/250 ns

Fall timd2.5 ps

Rise timel2.5 ps

Fall time/250 ns

Rise time12.5 ps

Fall time/25 ps

Rise time125 ps

Fall time/2.5 ps

5.4.1 2 P u k e Output Aberrations Test

Step # Parameter

1 a

1b

+ Aberrations

-

Aberrations

L o limlt

NIA

NIA

Readlng

Reading n s ns n s n s n s v

S ns ns ns ns

PS p s ps us us ns

Unlts n s n s n s n s n s

P s

HI l l m l t

7.25

7.25

49.25

49.25

59.75

59.75

474.5

474.5

579.5

579.5

4.727

4.727

5.777

5.777

52,50

52,50

28.25

264.5

264.5

28.25

264.5

2.627

2.627

264.5

2.627

26.25

26.25

2.627 ns ps ps

PS ps

HI l l m l t

0.620

0.620

Unit

VPP

VPP

Step #

1

2

3

4

Slope/Trlgger level

PositiveArig level cP -9.0

Positive/trig level 63 0.0

Positive/trig level cP +9.0

Negativehrig level 63 -5.0

Lo llmlt

-9.50

-0.50

8.50

-5.50

5.4.14 Synthesizer

Frequency Test

Step # Frequency Set

1

2

3

4

5

12.50 MHz

25.0 MHz

50.00 MHz

50.01 MHz

100 MHz

Lo Ilmit t 2,498,750

24,997,500

49,995,000

49,994,999

99,990,000

W.15

Burst Gateable Oeclllator Frequency Test

5

6

7

8

9

Step #

1

2

3

4

Frequency Set

100 Hz

1 MHz

9.375 MHz

18.75 MHz

25.1 MHz

31.0 MHz

37.5 MHz

43.0 MHz

50.00 MHz

Reading

Reading

Reading

HI llmlt

-8.50

0.50

9.50

-4.50

Unlts v v v

v

Hi limit t 2,501,250

25,002,500

50,005,000

5O,Ol5,OOl

100,010,000

Unlts

Hz

Hz

Hz

Hz

Hz

Hi llmit

102

1,020,000

9,562,500

19,125,000

25,602,000

31,620,000

38,250,000

43,860,000

51,000,000

Unlts

Hz

Hz

Hz

Hz

Hz

Hz

Hz

Hz

Hz

External Trlgger Frequenclee Test

Step # External trlgger freq

1

2

100

50

Lo Ilmlt'

99.99

49.995

Reading HI limlt'

100.01

50.005

Unlts

Hz

MHz

* 1 1 0 limits apply when thc external generator is another model 1391, olhcrwisc apply the specified Ire- quency accuracy limits of the cxwnal gcneraror.

5.4.1 7 Trlgger Source Test

6

7

8

9

10

11

12

Step #

1

2

3

4

5

SourcelFrequency

Internal150 MHz

Internal11 MHz

TTLTRG012 kHz

TTLTRG113 kHz

TTLTRG214 kHz

TTLTRG315 kHz

TTLTRG412 kHz

TTLTRG513 kHz

TTLTRG614 kHz

TTLTRG715 kHz

ECLTRG0130 MHz

ECLTRG1150 MHz

6.4.1 8 Trlgger Output Mode Test

8

9

10

11

5

6

7

Step # Trig linelsource1Frequency L o limlt

1 TTLTRGOTTRlPl12 kHz 1 1.9988

2

3

TTLTRGO/PULS/l 1 kHz

TTLTRGlTTRIPl22 kHz

10.9989

21.9978

4 TTLTRG2TTR I P/32 kHz 31.9968

12

13

TTLTRG3TTRI PI42 kHz 4 1.9958

TTLTRG4TTR IP/52 kHz

TTLTRG5TTRIPl62 kHz

51,9948

61.9938

TTLTRG6TTRIP172 kHz

TTLTRG7TTRlP182 kHz

71.9928

81 .9918

ECLTRGOTTRIP125 MHz 24.9975

ECLTRGO/PULSE/11 kHz 10.9989

ECLTRG1TTRtPllO MHz 9.9990

ECLTRGllPULSEl21 kHz 20.9979

5.4.18 Masterlslave Test

Step # Parameter

1 UUT Sync to SLAVe Sync

2

Lo

llrnlt

-2.0

UUT Pulse to SLAVe Pulse -2.0

Readlng

Readlng

Reedlng Hf limit

82.0082

25.0025

11.001 1

10.0010

21 .a021

Unit kHz kHz kHz kHz kHz kHz kHz kHz kHz

MHz kHz

MHz kHz kHz kHz kHz

MHz

MHz

Unlt

MHz

MHz kHz kHz kHz kHz kHz

HI llrnlt

2 .O

2.0

Unlt n s n

s

5.4.20 8UhlBU8 Teet

Step # Parameter

1

2

3

Lo llmlt

UUT lower level Q -2V

SUMBUS 4V; UUT lower level

-2.10

-

1.58

SUMBUS 16 V; UUT lower level 3.58

4

5

Sig Gen lower level G -2V -2.10

SUMBUS 4V; SG lower level -1.58

6 SUMBUS 16 V; SG lower level 3.58

6.4.21 PAM Input Teet

5

6

7

8

Step #

1

2

3

4

Parameter

UUT upper level

UUT lower level

Q 5V

Lo llmit

4.815

-5.185

5.765 Bipolar 1 V; UUT upper level

Bipolar 1 V; UUT lower level -6.235

Negative 1 V; UUT upper level -0.085

Negative 1V; UUT lower level -6.235

Negative 1V; UUT upper level 5.765

Negative 1 UUT lower level -0.085

Readlng

Readlng

HI l l m l t

-1.90

1.58

8.42

-1.90

1.58

8.42

HI l l m i t

5.185

-4.81 5

6.235

-5.765

0.085

-5.765

6.235

0.085

Unlt v v v v v v v v

Unlt v v v v v v

Troubleshooting Section

0.1 FACTORY REPAIR

Wavetek maintains a factory repair dcpartmenr for those customers not possessing the necessary person- nel or test equipment to maintain the insrrumcnt. If an instrument is rcturncd for calibration or rcpair, a de- tailed description of the specific problem and any re- lated symptoms should be attached to thc instrumcnt.

Before rerurning a unit to thc factory, aulhorization from Customer Service musr be obtained by caIling or writing ro:

0.3 REPUIRED TEST EPUIPMENT

Tablc 6-1 lists required tools and test equipment for troublcshooting.

Table 6-1.

Llst

of Test Equlprnent and Tools

Equipment Specifications

Cusromcr Service

Wavetek San Diego, Inc.

9045 Balboa Ave,

San Diego, C A 92123

Telephone: (61 9) 279-2200

FAX: (6 19) 565-9558

0.2 BEFORE YOU START

A list of rccommcnded sparc parts is includcd in the drawings scction of this rnanuaI (scction 7). Thcsc parts shouId be ordcrcd prior to an insrrumcnt failurc to minimize rcpair turn-around time.

Sincc no troublcshooting guidc can possibly covcr all the potential problems, thc aim of this guide is to give a methodology which, if applied consistently, will lead to thc problcm area. Thcrcforc, it is necessary to fa- miliarize yoursclf with rhe instrumcnt by rcviewing the circuit description (scction 4) in conjunction with the schcmatics (section 7 ) . Succcssful troublcshooting dc- pends upon understanding the circuit operalion within each functional block as wcll as the block rclation- ships.

The intcnt of this scction is ro provide the information required ro rcturn the instrumcnt to proper operation.

Beforc bcginning the rroublcshooting process, vcrify the instrurncnt's subsystems arc set correctly. For morc information about insrrumcnt opcration. rcfcr to section 3 o f this manual. Also. try to rule our calibra- tion as a possible problem. Finally, inspect thc instru- ment's wiring, and circuit boards for hcat damage.

VXI Requirements

Muldmercr

Oscilloscope

Frequcncy Counter

Adaptor

Coaxial cable

Probe

50Q Termination

VXI chassis

VXI slot-0 controller

VXI board

(Oprional-see text)

KF' 3478A or equiva- lent

Tektronix 2465 or equivalent

B P 5334A Universal

Counter

BNC fcmale to double banana jacks

BNC male connec- tors, RG58U cable

I 0 M R

Feedthrough. 0.190 accuracy, 2W

0.4 ISOLATING A PROBLEM

Bcgin the troubleshooting procedure by sending

I n many cascs, running this test will help to isolate the faulty block. Rcfcr to Appendix D of this manual to identify thc failed tcst. If a number othcr than zcro is rcrurncd after running ' T S T ? . rcfcr to Tablc 6-2 to idcntify the paragraph containing the information necdcd to isolatc lhc fau1ty circuit block and rclated componcnts.

If thc ' S T ? query response returns no fault cvcn though a problem does cxist, rcfcr to Tablc 6-3. This table lists problems that thc Self Test cannot identify.

6

Table 6-2. Problems Identified By 'TST?

Error BR Test Name Paragraph

6.5.1

6.5.2

6.5.3

6.5.4

6.5.5

6.5.6

6.5.7

6.5.8

7

6.5.9

With the covers removed, low voltage dc power supplies a r e exposed. Do not be misled by the term "lowf ~oltage". Under adverse conditions, potentials a s low as 50 volts can cause serious injury o r death. 0

1

5

6

7

2

3

4

8

14

Arnplitude/Offset DAC

Trailing Edge DAC

Leading Edge DAC

Limit Amplifier

SUMBUS

Delay Gatable Oscillator

Width Gatable Oscillator

25-50 MHz Gatable Oscillator

-

Bus Error

Table 6-3. Problems Not Identilied By 'TST?

\Vith the module on a n extender card and the covers removed, no chassis cooling air is moving across the components. The Pulse

Generator has many high-speed digital logic devices and discrete analog circuits which require some cooling a i r for continuous operation. Do not operate the module in this configuration for more than a few minutes without directing some cooling air across the face of the Main Pulse

Board and the Amplifier Board using an external utllitp fan. At80id burns

- d o not come into direct contact with components in thc module.

Problem Paragraph

Abnormal LED State

Pulse Board Digital Interface

AutoCaVBuilt-In-Test

Frequency Reference

Frequency Synthesizer

TRIG IN

Trigger Source Selector

T U E C L Triggers to Backplane lTUECL Triggers from Backplane

Mode Control Logic/Bursl Counter

SYNC OUT Selector and Driver

Amplitude Control and Multiplier

PAM IN

Transition Time Generator

Trapezoid Shaper

Output Power Supplies

Output AmplifierPULSE OUT

6.5.18

6.5.19

6.5.20

6.5.21

6.5.22

6.5.23

6.5.24

6.5,25

6.5.26

6.5.10

6.5.1 1

6.5.12

6.5.13

6,5.14

6.5.15

6.5.16

6.5.1 7

Do not discorrrrect or remove any board from chassis power. Sunre board assemblies contain devices that can be damaged i f r h e board i s removed or replaced wirlt the power on. Several components, including MOS devices, can be damaged by electrosfafic discharge. Use conductive foam and grounding straps when servicing is required around sensitive componenfs. Use care when unplugging ICs front high-grip suckers.

NOTE

If possible, fake all measuremenrs with only

[he confroller and Model 1391 Pulse

Generator in the chassis. Unless orhenvise

OUTconnecror (frhar circuit is being resred) i n f o 50R.

When raking waveform readings within !he

6.5 TROUBLESHOOTING

Thc following procedures rcquirc thal thc Modcl 1391 bc part of a V X I systcm as described in tablc 6-1. Thc

Xlodcl 139 1 will bc installed on a C-size V X I extender card and controllcd by rhe Rcsourcc Manager. The compu!cr/display dcvice can bc rhc Rcsourcc Managcr or an extcrnal host connccted to thc Rcsourcc Manager via the IEEE-488 ground lead ro prevent loading and reduce the amount of waveform ringing.

6.5.1 Arnplllude DAC

Error

Blt 0

Inslrument Setup: RESET

This test verifies the amplitude control voltage to the multiplier circuitry. The test sets the amplitude DAC to minimum and measures control voltage. A failure

10.1 volts. The test then sets the amplitude control

DAC to maximum and again measures the control volt- age. A failure will occur if the control volrnge is less than 0,798 volts or greatcr than 1.298 volts. A failure may be caused by U93. U94, or U89, and their associ- ated circuitry.

This test measures the SUMBUS driver output. This voltngc is nominally zcro volts. A failure will occur if the voltage is greater than -0.05 volts. A failure may be causcd by R 196 or R232 being misadjusted. Verify that the voltage on pin 5 of output amplifier connector

PI is 0

1

0.002 volts, if not follow the calibration pro-

6.6.2 Tralllng Edge DRC Error Blt 1

Instrument Setup: RESET

This test verifies the trailing edge current source cir- cuitry. The test sets the trailing edge DAC to mini- mum and mensures the current source feedback voltage. A failure will occur when the measured volr- age is greater than 0.25 volts. The test then sets the trailing edge DAC to maximum. and the TEclOns line to 0 and measures the feedback voltage. A failure will occur if the voltage is less than 3.371 volts or greater than 4.071 volts. The test then sets (he TE<IOns line to 1, and remeasures the feedback volrage. A failure will occur if the voltage is less than 2.761 volts or

U89, U96, U94, 4 3 8 . and their associated circuitry. preamplifier offset.

These adjustments are described in the alignment pro- cedure steps 5 and 6. The procedure for adjusting

R 196 is described in rhe alignment procedure step I 1,

This adjustment should be made only after the adjust- ment of steps 5 and 6 have been made. If the adjust- ment of R 196 cannor be made. the problem can be isolated by measuring the voltage of the ODAC signal.

This signal should be approximateIy 0 volts t 0.1 volts. If not. the output amplifier, or offset control cir- cuitry should be suspected. The next step is to mea- sure the voltage across R191. It should be about9. I volrs. If not CR66, Q55, and U105 and associated componcnts should be suspected. The voltage across

R192 should then be checked. It should be about 6 volts. If not. 4 5 6 . CR65, and U105 and associated components should be suspected.

8.6.8 Leadlng Edge DAC Errar Blt 2

Instrument Setup:

R E S E T

This test verifies the leading edge current source cir- cuitry. The rest sets the leading edge DAC to mini- mum and measures the current source feedback voltage. A failure will occur when the measured volt- age is greater than t 0 . 2 5 volts. The test !hen sets the leading edge DAC to maximum, and the LE<lOns line to 0 and measures the feedback voltage. A failure will occur if the voltage is less than -4.089 volts or greater than -3.389 volts, The test then sets the LE<IOns line to 1, and remeasures the feedback voltage. A failure will occur if the voltage is less than -3.3006 volts or greater than -2.706 volts. A failure may be caused by

U89. U96. U 9 4 . 4 3 9 , and their associated circuitry.

6.6.0 Delay Gatable Oacllletor Error 811 5

Instrument Setup:

F R E Q l e 3 : V O L T 5 ; P U L S : W I D T

2 5 0 e - 6 ; : D E L 1 2 5 e - 6 : : F U N C

P U L S E : : T R I G : S O U R 0 U S ; C O U N

5 0 ; : I N I T : C O N T 0 F F : : D I A G : R E G

<va:ue>

This test routcs the delay one-shot output flip-flop to the Autocal mcasuremcnt system. T h e DlAGnostic

SCPI Subsystem routes signals and data to the Autocal system, and is used in factory level diagnostics. A failure will occur if the measured delay is less than

100 ps, or greatcr than 150 ps. A fault may be isolated by rcfcrring to Figure 6- 1 Dclay One-Shot Troublc- shooting Flowchart.

0.5.4 Llmlt RmplRler Error Blt 8 lnstrument Setup:

R E S E T

This test monitors the limiter clamp voltages. The mid- point of the two voltages is nominally zero volts. A failure will occur if the voltage is outside of 20.150 volts. A failure may be caused by U97 and its associ- ated circuitry.

6.6.5 SUMBUS Error Blt 4

Instrument Setup:

R E S E T

6.6.7 Wldth Gatable Osclllator Error Blt 0

Instrument Setup:

F R E Q l e 3 : V O L T 5 ; P U L S : W I D T

2 5 0 e - 6 : D E L 1 2 5 e - 6 ; : F U N C

P U L S E ; : T R I G : S O U R B U S ; C O U N

This test routes the width one-shot output flip-flop to the autocal measuremen[ system. A failure will occur if the measured width is leis than 200 ps, or greater than 350 ps. A fault may be isolated by referring to

Figure 6-2 Width One-Shol Troubleshooting Flow- chart.

8.6.8 26-60 MHz Galable Oeclllator

Error

Blt 7

Instrument Setup:

F R E Q 6 6 6 . 7 : VOLT 5 ; F U M C

S Q 0 A R E : : T R I G : S O U R B 3 S : C O U X

5 0 : : I N I T : C O K T O F F

6.6.10 Abnormal LED Stele

Thc VXI Interface board conlrols each front panel

LED. Thc LED states may bc used to isolatc faults in thc VXI inlcrfacc and rhc main board,

RUN LEO

The RUN LED should bc illuminated continuously, in- dicating that the Interface board CPU is operational.

FAIL LED

The FAIL LED should bc extinguished, except during the first 5 seconds after powcr up. If thc LED is on af- ter system power on, the interface board was either not able to initialize it's configuration registers or i t failed it's own sclf test. This should not be confused with the Self Test of rhe main board, If the FAIL LED is il- luminated, the interface board is not operational.

MDOlO LEO

The MODID LED flashes on momentarily during pow- er up, This may be too short in duration to be seen.

A16 LED

The A16 LED flashes on while the VXI Interface

Board is being addressed by the VXlbus.

A24 LED

Thc A24 LED is illuminated during a VMEbus acccss to thc A24 shared mcmory.

Troublcshoor the LEDs as followts.

1 . Verify t h a ~ 1 module is in fact non-opcra- lional in the chassis. If rhc 139i module is opcra- tional. but thc RUN LED is extinguished. troubleshoot the LED and the RUN-LED\ signal

(refer to sheet I of the main board schematic).

2. If thc 1391 module is non-operational, the fault may be in the interfacc board or the main board. the autocal nleasuremenr system. The gatable oscilla- tor produces a pulse with a width of 749.9625 1

(0.5 '

/ 666.7 Hz ). The averagc width of 50 cycles is measured. A failure will occur if the averagc width is less than 700 pi or greater than 800 p. A fault may be isolated by referring to Figure 6 - 3 Gatable Oscilla- tor Troubleshooting Flowchart.

6.6.8 Bua

Error

Error 01114

The Bus Error bit will be set if the main board fails to assert thc DTACK\ signal after writing to the main board. If this failure occurs, U2 or U 1 I 2 should be sus- pected. move thc 1391 module, remove the left side pane1 and then the VXI inrcrface board. Plug the Inter- face board directly on to the P I and P2 connectors of the VXI chassis and reboot thc system. Check the module status using the host computer. If the interfacc board is operational, i t will idenrify itself normally in it's slot as a Wavetek Model 1391. A

SYSTcm:ERRor? query will rcturn an error mes- sage, but this is because thc interface board does not receivc a DTAC\ rcsponsc with the main board rcmovcd. If thc intcrfacc board is still non-opera- lional, call Wavctek customcr service at (619)

279-2200 to arrangc repair.

3. If thc intcrfacc board is operational, rcinstall it in thc madulc and troubleshoot thc intcrconncct sig- nals on thc P4 through P7 connectors on thc main board (rcfcr to main board schcrnatic diagram shect I ) .

4. If the RUN and FAIL LEDs are operating normal- ly, troubleshoor the remaining LEDs (refer to main board schematic sheet I),

6.6,lI Pulse Board ftlultel Int8rface checking the functionality of the various circuit blocks of the unit. As it is very difficult to document the states of all of the control lines for all functions fre- quencies and modes, the best way to troubleshoot rhc digital interface is to look at the logic levels of the sig- nals.

Do they wiggle between logic low and high?

Are they stuck low or high?

Are they someplace between low and high?

Problems in the voltage measuring portion of the Au-

~ocal/built in test circuitry may be isolated by measur- ing the voltages a! the inputs of the ADC buffers and comparing these voltages to lhose on the outputs of the buffers. The voltages should be within about 10 mV of each other. The 4 MHz clock signal 4MHZCLK should be measured. If everything is correct, U 109 should be suspec~ed.

Problcms in the period measuring portion of the Auto- callbuil! in test circuitry may be isolated by measuring the 2 MHz refercnce signal. 2MHZREF. If this signal is bad or missing, the CLK10 signals from the VXIbus backplane should be traced out to U112, If everything is correct, U112 should be suspected,

6.6.1 8 Frequency Relerence

The frequency reference for the Model 139 1 is provid- ed by the VXI controller. The controller provides a precise 10 MHz differential ECL signal to the back- plane. The backplane distribures the signal ro each slot, via individual buffers. If the frequency reference is suspected. the module should first be tried in anoth- er slot ro determine if the problem is due lo the back- plane. If the fault follows the module posirion, the

CLKlO+ and CLKlO- signals from rhe P2 connector should be traced through the inlerface board to the main board and up to U21.

Table 6-4. Trigger Source Selector Control

Trlgger Source

Llnes.

1

TAG-s~cc

I

TUG-ems

I

TUG-such

VXI ECL TRGO

VXI ECL TRGl

VXI l T L TRGn

Software Trigger

Internal Trigger

Ewternal Trigger

Problems in the basic operation of the frequency syn- thesizer can be determined by observing the UNLOCK

LED ( DS5 ) on the main board. The LED is visible through the hole in the top of the synthesizer shield.

The UNLOCK LED is normally extinguished, indicat- ing the loop is locked. The LED will momenlarily flash when a large step change in frequency is pro- grammed, Refer to Figure 6-4 Frequency Synthesizer

Troubleshooting Flowchart to isolate a synthesizer fault.

6.6.16 Trtgear

Source

Selector

Problems in the rriggcr sourcc selector circuitry can be isolnlcd by applying an cxtcrnal rriggcring signal to the TRTG IN BNC connector. selecting cxtcrnal triggcr and monitoring TP12. Changing the trigger slopc will invert the signal at TP12. Thc rriggcr sourcc is select- ed by the TRG-SRCA, TRG-SRCB, and TRG-SRCC signals. T h c sratcs of thesc signals for cach trigger sourcc is shown in tablc 6-4. If the control data is cor- ruptcd, U18 should be suspecrcd.

6.6.17 TTUECL Trlggers to Bsckplane

A second Model 139 1 is useful to troubleshoot the

TTLlECL triggering signals ro rhe backplane. The unit under tesr should be programmed to drive each trigger line in turn while the second model 1391 is pro- grammed to receive the trigger from the backplane. If only one or two TTL trigger lines are inoperable, U15,

U39, and U40 should be suspected. If a11 of the TTL trigger lines are inoperable, U18, U42. and U92 should be suspected in addition lo U15. U39, and U40. If

ECL-TRGO is inoperable, U17, U62. U98. and U113 along with U44 on the interface board shouId be sus- pected. If ECLTRG I is inoperable, U 17. U9 1, U98, and U113 along with U44 on the interface board should be suspected.

6.6.16 TRIG IR

Problems in the trigger input circuitry can easily be isolated by applying a [riggering signal to the TRIG I N

BNC connector and monitoring T P l 1 on the main board. The duty cycle of the waveform a[ TP11 should change with the programmed trigger level. The trigger

IeveI control voltage TDAC should swing from about zero to about 4.5 volts as the trigger level, is pro- grammed from + I 0 volts to -10 volts. If the TDAC signal is not present o r incorrecr, U87 and U90 should be suspected, If no waveform is present at TP11, U34 and U36 should be suspecred.

6.6.1 6 TTUECL Trlggers from Beckplane

A second Model 1391 is useful to troubleshoot the

T T L E C L triggering signals from the backplane. The second 1391 should be programmed to drive each trig- ger line in turn while the unit under test is programmed to receive the trigger from the backplane. If only one or two TTL trigger Iines are inoperable, U15 and U38 should be suspected. If all TTL trigger lines are inop- erable, U35 and U37 should also be suspected. Tf ei- ther of the ECL trigger lines are inoperable, U29 and

U37 along with U43 on the interface board should be suspecred.

6.6.16 Moda Control Loglc/Eurat Counter

Problems in the mode control logic for burst mode may be isolated by programming the unit under test as follows, and then foIlowing Figure 6-5 Burst Mode

Troubleshooring Flowchart:

FREQ 2 e 4 : F U N C S Q U ; : I N I T : C O N T

0 F F : : T R I G : G A T E 0 F F : T I X l e - 3 :

COUN 4 0

0,6,20 SYNC OUT Selector and Drlvar

Problcms in the Sync selcctor and driver can be isolat- cd by programming the unit under tcsr as follows, and then following Figure 6-6 Sync Selecror Troubleshoot- ing Flowchart:

F R E Q l e 3 : F U N C S Q U ; M A R K O N ;

V O L T 1 0

The srates of the sync selector conrrol lines are shown in table 6-6.

Thc signal path for the Gate Type of sync can be trou- bleshot by programming the unit under test as follows. and then following Figure 6-6 Sync Selector Trouble- shooting Flow Chart:

F R E Q 2 e 4 : X A R K 0 N ; X A R K : T Y P E

G A T E ; : T R I G : C O U N i 0 : T I X l e - 3 ;

S O U R I X T : : I X I T : C O X T O F F

Sync Functlon

Of!

Single Pulse

Double Pulse

Square

> 50 MHz

Clock

Gate

Table 6-5. Sync Selector Control Lines.

/

SYNC-SEW b

/

SYNC-SEL2

I

SYNC-SEL~

0.6.21 Amplitude Control end Multlpller

Problems in the amplitude control and multiplier cir- cuitry can be isolated by programming the unit under test as follows:

F R E Q l e 3 : V O L T 1 6 : F U N C S Q U

TP26 should measurc about + 1 volt. If not. U89 and

U 9 j should bc suspected. The input of the multiplier, pin 8 of U101, should bc a 1 Vpp squarc wave. If nor rhc trapezoid shapcr circuitry should bc suspcctcd.

Pin 6 of U102 should bc rnonitorcd for abour a 2Vpp square wave. If not UlOl and U102 should bc sus- pccrcd. Pin 6 of UlOO should bc monirorcd for abour a

5.2 Vpp squarc wavc. If not, UlOO should bc suspccl- cd.

0.6.22 PAM IN

Problems in the PAM IN circuitry can bc isolatcd by removing rhc output amplifier and programming the unil under rest as follows:

VOLT 1 0 ; F R E Q l e 3 ; F U N C S Q U :

P U L N OOIu'

A 1 Vpp squarc wavc should be applicd to thc PAM IN

BNC conncctor. Pin 7 of U93 should bc rnonitorcd for a 1Vpp squarc wavc. If not, U93 should bc suspcctcd.

Pin 10 of U94 should thcn bc monitored for a 1 Vpp squarc wavc. If not U 11 and U94 should bc suspcctcd.

TP26 should be monitorcd for a lVpp squarc wavc with a positivc DC offsct. If not, U93 should be sus- pccred.

0,6.23 Tranaltton Tfme Generelor

Problcrns in the transition timc gcncrator may bc iso- latcd by programming thc unit undcr tcst for:

V O L T 1 0 : F R E Q l e 3 ; F U N C S Q U :

? U L S : T R A N : S T A T 0 N ; T R A : A U T O O N

U98 pins 9 and 10 should be monitored for a lkHz

ECL level square wave. If no square wave is presenr, thc width one-shot circuitry should be suspected. U98 pins 6 and 7 should then bc monitored for ECL level square waves. If no square wave is present U98 should be suspected. The bases of Q4 1 and Q42 should be monitored for square waves that swing be- tween about -2.3 and -3.2 volts.

If the square waves are not present. CR45 and CR46 should be suspected. The collector of 4 4 2 should be monitored for about a 3Vpp square wave symmetrical about ground. If no square wave is present, 4 4 1 - 4 4 3 should be suspected. The top of ClO6 should then be monitored for a 1.5 Vpp square wave, symmetrical about ground. If no square wave is present 4 4 4 - 4 4 7 and associated components should be suspected. The selection of timing capacitor for each range of transi- tion times is shown in table 6-6.

Table 6-6 Transltlon Tlmlng Range Capacllor

Selection

Tmnsirion Range

4.5 ns

-

17 ns

1

I

Timing Capacitors

C106 depend on calibrarion.

Problems in rhe trapezoid shaper may be isolarcd by programming the unit under tesr as follows:

F R E Q l e 3 ; V O L T 1 0 ; F U N C S Q U

Pin 3 of U99 should be monitored for a 1.5 Vpp square wave. If not, the transition generator should be sus- pected. TP37 should be monitored for a 3.2 Vpp square wave. If nor U99 should be suspecred, Pin 8 o f

U1Ol should be monitored for a 1 Vpp square wave.

If not, the unit should be powered down and the output amplifier removed. Power should then be reapplied and the unit reprogrammed to the above slatc. The voltages on 4 3 4 pins 6 and 4 should be monitored for

+18 volts and -18 volts respectively. If nor 4 3 4 and

UI I should be suspected.

8.6.26 Output P o w e r Suppllar

Problems in rhe output amplifier power supplies may be isolated by removing thc output amplificr board and

14 shouId be about e 3 6 volls. These voltages will drop to abour k 3 0 volrs wirh the output amplifier in- stalled. If the voliages are correct without the output amplifier installed, the problem is probably in the out- pu[ amplifier, If the unloaded volrages are incorrect, the voltage on L2 should be measured.

If the voltage is nor about 12 volts, Q5 I or 4 5 2 may be shorted. The drains of 4 5 1 and 4 5 2 should swing a symmetry of about 60140. if not U118, 4 5 1 . and 4 5 2 should be suspected. If the voltage at J12 pin 2 is about +24 volrs CR37 shouId be suspected. Similarly if the voltage ar J 12 pin 14 is about -24 volts CR38 should be suspected.

8.6.28 Output I\mpllllerlPULSE OUT

Problems in the outpur amplificr can be isolated by firs[ programming thc unil under test as follows:

F R E Q l e 3 ; V O L T 1 0 ; F U N C

S Q U : V O L T : 0 : : O U T P O X

The volrages on ou[put amplifier connector 11 should bc as shown in Table 6-7, If the volrages are not cor- rect, the associated main board circuitry should first bc rroublcshot and rhc problems corrected before proceed- ing. The voltages on ourput amplifier T P 2 and T P 3 should be about +12 and -12 volts respecrively, If not

U l , U2, and U3 should bc suspected. If the amplifier's output is stuck high, TP4 should be about +10 volts, if not U3 should be suspectcd. The voltages on the col- lecrors of Q 8 and Q 9 should be measured. They should be about e 2 8 volts. If not. circuit protector

CB 1 or CB2 may have [ripped, Transistors Q 8 and Q9 should then be checked for shorts.

J1

Table 6-7 Output Amplifier Voltages

Pin No.

1.4,6,8.9.10.12.15

2 J

5

11

13,14

Voltage

0 volts

-+30 volts

-

3.24 Vpp Square wave

0 *0.050 volts

-30 volts

1 0 3 . 33OvS

P U L S E U 4 2

. q 1

1 0 0 - l 5 O u S f

U l 1 B A D

- l nS P U L S E

O u a 4 . rr

U d 7 -

I H I O H

I

w

I

U I 7 B A D

I

I

Figure 6-1. Delay One-Shot Troubleshooting Flow Chart

Figure 6-1 (Cont'd). Delay One-Shot Troubleshooting Flow Chart

UiO

,

15 LOW

UIO

-

1 4 HIGH

- 7 HlCH

U 7 0 . 10 HIGH

N

022.Q23.RSI.R66

B A D

I

U 7 5 BAD

PULSE @U70 -

! 5

U 7 I

-

4 H I G H

U l B BAD

I

?-I

U74 BAD

-

5 n S PULSE

T

-

5 nS PULSE

@ U ? 4 . ! 4

ANALOG O N E S H O T

C I R C U I T R Y B A D

Figure 6-1 (Cont'd). Delay One-Shot Troubleshooting Flow Chart

G A T A B L E 0 5 C . PULSE Z U42. t l

203

-

300 U S

PULSE

S

T P I E ti nlan

U67

-

I HIGH

1 K H z S O V A R E W A V

U M . A S 6 , C65

Figure 6-2. Width One-Shot Troubleshooting Flow Chart

U14 B A D

DELAY WE,SWOT

U12 0AD

- 5 n S P U L S E

@Ub6 - 6

Flgure 6-2 (Cont'd). Wldth One-Shot

Troubleshooting

Flow Chart

-1 r-h

WAVE

3

U 7 S

-

O c

U l d B A D

3

U l I B A D

Figure 6-2 (Cont'd). Width One-Shot Troubleshooting Flow Chart

h' -

U 7 8 . 1 5 LOW h

U 7 8 . I4 HIGH

Y

U78 BAD

0 2 8 , 0 2 9 . R 8 0 , R B 1

BAD

U83 . 7 HIGH

Y

Y

U78 . 10 HIGH

N

PULSE Q U 7 8 . 1 5

<

-

5 nS

PULSE

N

ANALOG ONESHOT

CIRCUITRY BAD

-

5 nS PULSE

@ U 8 2 . 1 4

Flgure 6-2 (Cont'd). Width One-Shot Troubleshootlng Flow Chart

I

\KHz SPUAREWAVE 3

U 3 3 . 1 4

U33

.

132 LOW

U 3 3 . r

1

HIGH

Y

U14 BAD

'

32.768MHz 3 T P 6

,

U 1 4 BAD U33 BAD

U32 BAD

U19 BAD

Flgure 6-3. Gatable Osc[llator Troubleshooting Flow Chart

-

~ C K H Z U21 - 13

65.5VHz 3 U24

.

3

ANY OSCILLATION

J24, C R I C - C R l l , L1

U22. ASS C O W S

FREQ @ U25 . 5

U25 BAD U21, U23 BAD

U14 BAD

U32 B A D

02, 03. R23. R24

B A D

H

1KHr 3 TP4

Y

Figure 6-3 (Cont'd). Gatable Oscillator Troubleshooting Flow Chart

~ 3 3 . HIGH

U33

.

132 LOW

S T A R T

52

U30 B A D

Figure 6-4. Frequency Synthesizer Troubleshooting Flow Chart

A N Y OSCILLATIOS

J24, CRl4.CRl7, 11

1 1-

U21. U23 BAD

U 1 4 B A D

16.38MHz Q T P 7 ,

U 3 2 . 12 LOW

U32 BAD

N

16.38MHz @TPS

N

02. R23. Fl?C

U 3 1 B A D

Y

C R I 9 BAD

Flgure 6-4 (Cont'd). Frequency Synthesizer Troubleshooting Flow Chart

I

START

/ i l d E h

@ U44

.

13

T R G t E R SQURCE

S E L E C T O R B A D

-

SnS PULSE A T

I

,KHz RATE

8 TP 13

.

10 LOW

Flgure 6-5, Burst Mode Troubleshooting Flow Chart

I

U S 8 B A D

I

I

US7 B A D

I

Figure 6-5 (Cont'd), Burst Mode Troubleshooting Flow Chart

Figure 6-6. Sync Selector Troubleshooting Flow Char4

Figure 6-6 (Cont'd). Sync Selector Troubleshooting Flow Chart

Parts

and

Schematics Seclion 7

7.1 DRAWINGS

The following schematics and assembly drawings are in the arrangement shown below. inserted inside the shipping carton with this manual. If no such pages exist, the manual is correcl a s printed.

7.2 ERRATA

Under Wavetek's product improvement program, the latest eIectronic designs and circuits are incorporated into each Wavetek instrument a s quickly as develop- men1 and testing permit. Because of the time needed to compose and print instruction manuals, it is nor always possible lo include the most recent changes in the initial printing. Whenever this occurs, errata pages are prepared

10 summarize the changes made and are

7.8 ORDERING PARTS

When ordering spare parts, please specify part number, circuit reference, board, serial number of unit and, if applicable, the function performed.

NOTE

An assembly drawing number is not necessarily the assembly purr number. However, the assembly parrs Iisr number is rhe assembly part number.

DRAWING NUMBER DRAWING

Outline Drawing

Instrument Schematic

Instrument Assembly Drawing

Instrument Parts List (Standard)

Inslrument Parts List (MATE)

Main Board Schematic

main Board Assembly

,Main Board Parts List

Amplifier Board Schcmaric

Amplifier Board Assembly Drawing

Amplifier Board Parts List

Spares Kit Parts List

PART MARKING PIN-OUT

3866 NPN

5160 PNP

5583 PNP

5943 NPN

Figure 7-1. Surface

Mount

Parts Pin-Outs

REFERENCE D E S I G N A T O R S

-.

REF

REF

REF

REF

REF

1 6

A/D W E L 1 3 9 1 50 H z

V X I PG

ATS MODEL 1 3 9 1

INSTR SCHEMTIC MODEL

1 3 9 1

W U A L MODEL 1 3 9 1

CALIB PROCEWRE MODEL

1 3 9 1

INSTRWENT LABEL

MOOEL 1 3 9 1

25

1 4

1 9

9

1 5

1 8

6

2

4

5

2 3

1 7

NONE

PCA 5 m Z

K A , V X I INTERFACE

BOARD MODEL 1 3 9 1

CHASSIS RAIL, TOP

CHASSIS RAIL,BOTT(W

REAR PANEL VXI:

COVER,SIDE

PANEL, RIGHT

WYlK LOGO HPWEPLATE

V X I LOGO W E P L A T E

FRONT PANEL 1 3 9 1

WOLE,EXTRACTOR,TOP,

BLACK

1

10

2 4

2 1

SCREW,4-W1/4,PHP,W

LOCK PATCH,Z 4 - 4 8 W 4

WASHER REF:21188-721,

BAG OF 188 PCS

SCREW,PLPS.FH,lHl

DEG,S/S,2-56HCx3/16"

NYLK PATCH

SCREW, F H, 82DEG, 'TYPE

B ' , 4 x l / Z n JNC PLT

8 XREW,COLLAR,WZ.Sxll,

NICKEL PLATE

REF:21188-379, BAG DF

188 PCS

SCREW,CHEESE 22

HEAO,MZ.5xl0,ZINC

-

REF:21188-138, BAG OF

188 PCS

T I T L E

WAVETEK

V X I PULSE

PARTS LIST

1

WYlK

M K

W r K

M K

W r K

W r K

W r K

W r K

WYCK lVYRI

W r K

SCHRF

SCHRF

M C L

SCHRF

QRCL

WrK

wwu

WYlK

WYIK

WVTK

M K

W r K

C M C L

SCHRF

SCHRF

-

PAGE 1

R E F E R E N C E O E S I G N A T O R S P A R T D E S C R I P T I O N O R I C - M F C R - P A R T - N O

CHAF

W A V E T E K N O .

5;s

I E F : 2 1 1 0 0 - 4 2 9 . BAG OF

.@a

PCS

CHRF

IEF :

.00 PCS vr

K

1 3 9 1 S 0 MHz V X I PULSE

TOR

ASSEMBLY NO.

1BBB-00-0694-01

PACE 2

1 6

23

1 7

1 3

1 4

19

9

1 5

1 8

REFERENCE D E S I G N A T O R S PART D E S C R I P T I O N ORIG-MFGR-PART-NO

REF

REF

REF

REF

REF

A/D MODEL 1391 SO

V X I PG mz

ATS MODEL 1 3 9 1

INSTR SCHEMATIC HODEL

1 3 9 1

MANUAL MODEL 1 3 9 1

CALIB PROCEWRE MODEL

1 3 9 1

25

WVYK

M K

WYlK

WVTK

M K

WVYK

WAVETEK NO.

IHSTRWEKI LABEL

MODEL 1 3 9 1 MATE

M P L I F I E R BD

PCA 5 W z V X I MAIN BD

PCA, V X I INTERFACE BD

HOUEL 1 3 9 1 M4TE

CHASSIS RAIL, TOP

CHASSIS RAIL, Eon#!

COVER,SIDE PANEL, LEFT

REAR PANEL V X I

6

2

4

5

1

WVTK LOGO W E P L A T E

V X I LOGO W E P L A T E

FROKT PANEL 1 3 9 1

HANDLE, EXTRACTOR ,TOP,

BLACK

11

2 1

10

2 4

8

22

SCREW,4-48XL/4,PHP,NY

LOCK PATCH,Z 4-@XL/4

WASHER REFi21188-721,

BAG OF 188 PCS

SCREW, PLPS, FH, 1 8 8

DEG,S/S,Z-56NCx3/16'

NYLK PATCH

SCREW,FH,8ZDEG, 'TYPE

0 ' ,4xl/Z",ZNC PLT

SCREW, COLLbR,UZ. 5x11,

NICKEL PLATE

REF :21188-379, BAG OF

100 PCS

SCREW,CHEESE

HEAD,MZ.5xl0,2IHC

REF:211BB-138, BAG OF

188 PC5

TITLE

WAVETEK

PARTS LIST

GENERATOR

M z PULSE

I

SCHRF

CMCL

S U R F

CCRCL

M K

WYlK

M K

M K

WVTK

WVTK

WVTK

WVTK

WVYK

WYTK

M K

M K

SCHRF

M C L

SCHRF

SCHRF

-

PAGE 1

REFERENCE DESIGNATORS PART D E S C R I P T I O N )RIG-MFGR-PART-NO

I

MFG WAVETEK NO.

SCHR 888-54-8214

:/sK,

MZ.

JXS

IEF: 21168-429. BAG OF

SCHR ;LEEVE,BLK

'LASTIC, 5.9x3.3 tEF:Z1100-591, HAG OF

100 PCS

IARTN, 1SxlZx3

L/Z,225P,DHLSLDE

'ACK, SNGL WALL

WVTK

I

TITLE

W A ~ E K

WTE 50 u l z PULSE

I ASSEMBLY NO.

1 m - 8 6 - 0 6 9 - 1 1

NONE

-

REFEREHCE OESIGHATORS - - PART D E S C R I P T I O H

I

WD 50 W2 V X I MAIN

I ED

NONE SCHEMATIC 50 M z V X I

I

NONE SUB ASSEMBLY FOR

I

SURFACE WNl

COMWHENlS

I

I

CAP, CER, DISC,

I

10PF,lKV, COG,5%, RAD

LD .25

I

I

I

I

I

I

I

I

I

1

TITLE

WAVETEK

5 0

PARTS LIST

1 COG 5% RADIAL LD SP

.2

I

1

I

1 RADIAL LEAD,SP .20

1 CAP,ELECT,lBBMF,25V,R i hOIAL LEAD-SP SIZE

I CAP ,MET

I WLYS,.MF,l696,63V,.l

*LS

I

I

W, MET. WLYS,

I a.@lWF, 2696, 63V,

I a.lLS

1

BOARD

I

W K

SPRAG

CORHG

AVX

AVX

AVX

-

-

WVTK 1101-88-3612

Q T Y / P T

1

WVTK 1

1 HYMEG

WVTK 1

1

4

1

6

5

77

KY CRA

NIC

NIC

WIMA

WIM

WIM

SPRAG

S PRAG

COlCC

-

PAGE 1

2

1

1

2

5

2

10

5

1

REV

1

REFERENCE DESIGNATORS

DL2 DL3 DL4

PART D E S C R I P T I O N

DELAY LINE,PASSIVE,

3 . 5 NS, 186 OHMISIP

INDUCTOR, 1 8 8 uH,

IS%, l.lA,DCR 0.208

DELAY LINE, 2 0 NS,

186 OW,PASSIVE,SIP

DLY LINE,PASSIVE, 10

NS, 1 6 8 OM,SIP

DELAY LINE,PASSIVE,

7.5 NS, 1 6 8 OW,SIP

CONN, BNCCPC)

CONN,SIP, 1 5 PIN,LOW

PROFILE

SKKET,40 PIN,ST,LOW

INSERT

SOCKET, 2 0 PIN, ST, LOW

INSERT

SOCKET,36 PIN,5T,LW

INSERT

SKKET,20 P I N r P 1 TPZ TPZZ TP24 TP29 TP3 rP34 TP38 TP9

TEST WIKT,BLK,PC

TEST WIKT,RED,PC

WAVETEK NO.

18BB-86-8658

1 8 8 8 - 0 0 4 0 5 9

1800-00-BBQ

1800-86-8663

1886-88-0064

2168-61-6819

188-02-0312

2188-03-6866

2166-83-8861

2100-03-8886

2100-03-8851

2168-04-8654

2188-84-0055

TEST W I K T , SCOPE

PROBE, COAXIAL

STANDOFF, 3/8 LG,

3/16 DIA, 4 - 4 0

THRD,ALLM

HEATSINK,TO-5 PKG

SCREW,4-40Xl/4,PHP,NY

LOCK PATCH,Z 4 - 4 0 X V 4

HOLE PLUG,BINDER

HEAD ,NTRAL NYLON

RIVET PLASTIC

BALUN CORE

RELAY, 2 FORM C. 5V,

LOW PROFILE

SMITH 2868-82-8848

BIVAR 2888-11-8663

IERC 2888-11-8912

CWCL 2800-23-4104

FASTX 2 8 6 8 - 3 5 4 0 0 9 I I

BECK 4609-98-0005

BECK 4609-98-8813

BECK 4609-90-0023 WT, 20T. TOP TRIM,

586 O W

PARTS LIST

TITLE rnz vxr

MAIN BOARD

NO. I ASSEMBLY

I

11BB-88-3612-01

PAGE 2

REV

L

REFERENCE D E S I G N A T O R S P A R T D E S C R I P T I O N

RES,MFLM, 1/8W, 0.196,

188 P W C , 24.9K OHW

O R I G - M F G R - P A R T - H O MFGR WAVETEK HO. t

RES, MF,1/8W, .196 T 2

4 9 9

JALE 4 7 0 1 - 0 2 - 4 9 9 1 RES. MF,1/8W1.1% I 2

4.99K

RES,MF,1/81,196,188

RES1MF,1/8W,l%,10

RES,MF,1/8W1196,1.5K

RES,MF, l/8W,l%, l . 6 2 K

RES ,MF, l/8W, 196, 1 6 5

YEPCC

TRW

TRW rw

RES,MFI1/8W,l%,4.02K

RE5,MF,1/8W.l%,432

RE5 ,MF,1/8W1l%,464

RES,MFD1/8,196,499

RES,MF,1/BW,l%,4,99K

RES,MF11/8W,l%,49.9

RES,MF,l/8W1l%,511

RES,MF ,l/8W11%,523

RES,MF,l/8W,l%,7.5K

RES,MFLM,1/8W,l%,75

RES, m ,

P W C , 248 OHM

RES,MF, 1W,l%,100

RE5 H E M 4 7 0 l 0 P I N S I P XSOL

2%

RES,HTWK, 2K OW

ZX,SXP,ISOLATED

x 5 ,

TITLE

WAVETTEK

V X I M I N BOARD

PARTS LIST

IRW

IUW

TRW

IRW

TRW

4781-63-4021

4701-03-4320

4 7 0 1 - 0 3 - 4 6 4 8

4701-03-4998

4781-03-4991

CORNG 4701-03-4999.

TRW

TRYl

TRW

4701-03-5110

4781-03-5230

4701-03-7501

YEPCO 4701-03-7509

BtlYOP 4701-86-2488

IRW 4701-33- 1888

I

ASSEMBLY NO.-

1100-00-3612-01

PAGE 3

4770-00-8627 BOURN I

REFERENCE DESIGNATORS

RN1 RNl8 R H l l RHl2 RN13

RN14 RNl5 RH16 RN17 RKl8

RSZ RNZZ RH3 RK30 RN31 RN4

RN5 RN6 RV7 RN8 RH9

CRl0 C R l l CR13 CR19 CR2

CR24 C R S CR26 CR27 CR28

CR29 CR3 CR3Z CR6 CR7 CR8

C R9

CRZQ CR2l

CRZ2 CR23 CR6BB

DIODE, ZENER, 3.9V,

IN748

DIODE, HIGH

CONDUCTAHCE, ULTR4

FAST

DIODE, ULTRA FAST

DIODE 5082-2811

SCHOllKY, lSV,ZBM4

CR14 CR15 CR16 CR17

055

DSZ 053

1

1N748A

IN5282

~ N U U

5882-2811

LED,AMBER,RECT BAR LTL-3Z51A

LED,GREEH,PC MT., INT 556-B206

HOLDER

LED,YELLW,PC

IK1UNl.Ih-l. HOLDER

558-8306

LED,RED, PC M l . , XNT. 558-8486

HOLDER

RXE065 CIRCUIT PROT. ,SELF

RESETIHG, 0.65 M P

TRANS ZN2905A PNP

GENERAL PURPOSE TO-5

ZNZ905A

Q l 0 Q24 430 Q9

Q32 9 3 3

QZS 9 3 1

Q l Q l l QSSe 9 7

TRANS 1013866 lRANS 2N3904 NPH

GENERAL PURPOSE TO-92

?TUNS 2N3906 PNP

GEHERAL PURPOSE TO-92

ZN3986COBS)

TRANS, P-CHANNEL

J E T S

1 zNs462

I

ZN5771 M S 2H5771 PHP

SWITCH 1 0 - 9 2

FAIR 4881-81-0748

F U R 4801-81-5282

T/CSF 4807-02-8777

HP 4809-02-2811

PHLIP 4899-88-6646

L I T E 4899-88-6856

DIALT 4899-00-8866

DIALT 4899-00-6867

DIALT 4899-BB-0068 I I

UAYCM I I 4899-00-6869

NSC 4901-02-9051 I I

HSC 4981-03-5638

HOT 4901-03-8664

FAIR 4901-03-9040

FAXR 4981-83-9868

DP

MIC POWER VOLT REF

VOLTAGE REFERENCE,

10V, 8 PIN DIP

ADC, 12 8IT,W/

WX

I

I

I

M 8 5 B Z - 2 . 5

RCA 4902-88-0618

HARXS 4902-68-8818

T I 7000-88-5188

T I 7888-88-5488

RCA 7888-B8-8200

L I M E 7000-03-8500

L I M E 7688-10-2101

LIKlE m - 1 2 - 9 8 6 8

REV

L

-

R E F E R E N C E D E S I G N A T O R S

-,

P A R T D E S C R I P T I O N

REG, POSITIVE,

,

18

VOLT, lW, TO-92

O R I G - M F G R - P A R T - N O

VOLT REGULATOR,

NEGATIVE

REG, NEG, 1 8 VOLTS,

1W, TO-92

COMPAIIATOR, HIGH

SPEED, ECL

U l l U l l 0 U 1 1 1 U13 U 1 4 U 1 5

U 1 6 U 1 7 U18 U 1 9 U 2 0 U7

XLATOR, PROC, HEX

SHFT

REG,8-BIT,CWS,DCITPLJl

CLR

MECL l 0 K H HIGH-SPEED

ECL

GATE, AND QUAD, ECL

GATE, OWNOR, TRIPLE

2 - 3 - 2 I N

-

1 8 0 1 MOT 7 8 6 6 - 7 8

I

MOT 7 8 8 8 - 7 9 - 0 5 8 8

L I N T E 8 0 0 0 - 1 0 - 4 5 8 8

T I 8 6 6 6 - 7 4 - 5 9 5 0

MOT 8 8 8 1 - 0 1 - 0 7 0 1

RECEIVER-TRIP LN ECL

GATE,OR AND/OR AND

I W E R W A L WIDE, ECL

FLIP-FLOP, W A L D,

WAS/SL, ECL

1 OF 8

DECODEWDEWLTIPLEXER

COUNTER, W A L 4 0 BCD, l l L

EEPROn,SERXAL,

B I T

4096

PRESCALER,WAL

W W L U S , DIVIDE-BY-&/

P L L SERIES INPUT FREQ

S Y W E S I Z E R

BUFF ER,OCTAL,OPEN

COLTR .64U4

WA-K

PARTS LIST

TITLE

PCA 58 Wz M I WAIN BOARD

ASSEMBLY NO.

1 1 8 8 - 8 8 - 3 6 1 2 - 0 1

F A I R 8 0 0 7 - 4 1 - 5 1 2 0

F A I R 8 8 8 7 - 4 3 - 9 6 1 0

R E F E R E N C E D E S I G N A T O R S

OSC EMT CUPLD, ECL

;AL,PROG,USES

IBBB-16-8882 FOR MOD

.391, REF U 3

I MC1648P

8 6 8 6 - 0 0 - 0 7 4 5

1 8 8 6 - 1 6 & 0 2 FOR HOD

1391,REF U 2

E n t e r A l t - F 1 t o name

REF your f

. e

VO

ID

5 0 WZ V X I MAIN 1 1 0 1 - 0 0 - 3 6 1 2

'ANT, 4.7MF1 i 0 V , Y O , E I A 7343 CASE

PCT4.7/500M

:AP,TAHT, 6.8MF, 20V.

!a,

E I A 6 0 3 2

:ASE

PCT6.8/20CM

:AP, YO CER

.00PF/50V

NPO ClZ06ClBLJZGAC

C103 C184 C105 C l l 0 C l l l

C l l Z C113 C 1 1 4 C115 C116

IWK 8 6 0 0 - 8 6 - 0 7 4 5

EYlK 8 6 8 8 - 8 8 - 0 7 4 6

'LESS 8700-00-6885

;PRAG 1 5 8 8 - 8 1 - 5 8 8 1

' H C I P 1 5 0 0 - 8 1 - 5 2 0 1

:AP,CER, 15BB8PF, iWlW, 50V,X7R,YO l 2 8 6 CASE

:AP,CER, 1 8 0 PF, iRi,NPO,W 1 2 0 6 CASE

C15331206XFLB OR T

12861A181JAT050R OR 0

' H L I P 11500-81-5388

' H L I P 1 5 8 6 - 8 2 - 0 2 0 1

:AP,CER, 2200PF, iWlBllb, 50V,X7R,YO

1286 CASE

PARTS LIST

I

TITLE

MHz VXI MAIN 80ARD

CZZZJ1206XFLB OR T

1

ASSEMBLY NO.

1

1 1 8 6 - 0 0 - 3 6 1 2 - 0 1

PAGE 6

REFERENCE D E S I G N A T O R S P A R T D E S C R I P T I O N

-

CAP,CER, 470PF,

Wlm,

SBV, HPO

,

O R I G - M F G R - P A R T - N O

C471J1206CFLB OR T

CAP,CER, 8.2PF, 5%)

50V,NW,WD 1206 CASE

PCB 5 0 MHz V X I W I N

BD REF: SPEC

8668-00-0455 REV E

Wf,SMD,TRIM,WULTI-TU

RN, V 4 " SQ.

-

PHLIP

PHLIP

M K

BECK

WAVETEK NO.

BOURN POT, WD, 5 0 0

W , S I N G L TURN, 4 W4

RES, 100 Mi, 191,

VBW, 2 0 0 P W C , Y I D

1206 CASE

PES, 200PPM. 191,

VSW, lK, 1206,WD

1206 CASE

Yaw, 191, 2 0 0 PPM,

188 KOW,WD 1206

EASE tES, ZWPPM,ll%W,

W,10 OW,WD, 1206

1206 CASE

E S . 115 O M . 191. vaw,

200 w t i . ~ o

12%

ZE5,MF, l A W , W, 2 0 0

J W C , 12.4 KOHU,SCID

1206 CASE

IES, 12.4 OW, 191, vaw.

2 0 0 P W C . W

1206. CASE

7E5, 1 5 0 OW, 191, vaw,

288 PPWC,YID

1206 CASE

PHLIP

WEPCO

PHCOM

MEPCO

PHL I

DALE

PHLIP

PHLIP

MEPCO

6

QTY /P T

2

1

1

1

1

11

5 a

1 4

1

1

1

2

ZES, 15K O M , 191,

VaW, 2 0 0 P W C , Y I D

1206 CASE

1E5, 165 W, 191, vaw, tea

PWC,YID

1206 CASE

E 5 , 169 OW, W, vaw,

ZBB PWC,YID

1206 CASE

PHLIP

PHLIP

3

1

1

DALE 1

2

WAVETEK

PARTS LIST

ZES, 1.87K OW, W , vaw,

288 PPM,WD

1206

IE5,MF, VBW, 191, 200

J W C , 196 OM,SMD

1206 CASE

PHLIP

DALE

1

ASSEMBLY NO.

1188-88-3612-01

PAGE 7

1

REV

L

REFERENCE DESIGNATORS PART D E S C R I P T I O N WAVETEK NO. ORIG-MFGR-PART-NO HFGI

===I=

PHLIP 4793-13-2100 RES, 210 om, l%,

1/8W, 286 PWC,SMD

1206 CASE

PHL I ? 0703-13-2321 RES. 2.32K OW. 196.

PHLIP 1703-13-2430

R166 R186 R199 R 2 0 l R20Z

RZW RZ05 R227

RES, 243

OH(,

1%. l/W, 200 P W C w,

1206 CASE

RES, ZMPPM, l%,

1/8W, 249 W,

1206, SwD

RES, 2.49K OW, 196,

1/8W, 2 8 6 PPWC

,sm

1206 CASE

RES, 1/8W, 196, 200

PPWC, 24.9 KW,SMD

1206 CASE

RES, 200 PPM, l%,

1/8W, 2 8 . 7 , W , 1206

MEPCO 1703-13-2490

PHLIP $703-13-2491

DALE 1703-13-2492

MEPCO 0703-13-2879

MEPCO t703-13-3011

PHLIP 8703-13-3248

PHLIP $783-13-3320

PHLXP $783-13-3741

RES, 324 om, 196,

1/8W, 2BB P W C , SMD

1206 CASE

RES, 332

OH(,

196,

1/m.

2 0 0 P W C , SMD

1286 CASE

RES. 3.74K OHW, 196,

1/8W, 2 0 0 PWC,SWD

12% CASE

RES, 200 PPM, 196,

1/8W, 38.3 0 W . W

1206 CASE

RES, 482 O W , 196,

1/m,

200 PPM/C,y.y)

1206 CASE

RES, 4.32K OW, 196,

1/8W, 286 PPM,WD

1206

RES,Z00 PPM, l/8WIl%.

453 OW,SMD,1206

RES, ZMPPM, 196, vaw.

499 OHW,

1206, SwD

RES, 4.99u OHW, 196, v a w ,

2e0 PWC,SWD

1206 CASE

RES, 49.9K OW, l%, m w ,

2 0 0 P W C , S M

1206 CASE

MEPCO $783-13-3839

PHLIP 8703-13-4820

PtlLIP t703-13-4321

MEPCO 1703-13-4530

MEPCO 1703-13-4998

PHLIP 1703-13-4991

PHLIP 1703-13-4992

DALE t703-13-4999

T I T L E

WAVETEK

50 MHZ

PARTS LIST

I vxx

W BOARD

ASSEMBLY NO.

1186-86-3612-01

PAGE 8

R E V

L

REFERENCE D E S I G N A T O R S

R137 R138 R148 R141

PART D E S C R I P T I O N

RES, 51.1 OW, I % ,

1/0W, 288 PPM/C,SMD

1206 CASE

RZ03

R187 R161

RES. 549 OW. 1%.

IAW, 288 PP);VC,SWD

1206 CASE

RES, 604 OW, l%,

1/0W, 288 PPM,SMD

1206

R I B 9

R230 R233

1/8W, 203 PPM,SMD

It86

I RES. 6 8 1 OW. 1%.

R180

R506

R145

I RES,M, 1/8W, l%, 2 0 0

I P W C , 7.32 KOW,WD

1286 CASE l A W ,

1206 om, is,

2B8 PR4,SMD

I OW, l%,

1/8W, 288 PWC,SMD

1286 CASE

I RES, ZWPPM, 75 OHM, l%, 1/0W, 1286

R127 R l 2 8 R530

R106 R99

R116

R119

R108

1/8W, 288 P W , W D

1206

8 0 6 OW. l%. lJ0W. j

I ?ES, 8.2% O m , I%,

VSW, 2 8 8 P W C SMD,

1286

I PES, 887 am, I%,

L/0W. 200 PPM.WD

R178 R179 I RES, 200 P W C , l%,

VSW, 909 OW,WD

1286 CASE

R570

R147 R149 R151

R l l 0

VSW, 288 PR4,SMD

1286

I RES, 98.9 OW, 196,

VgW, teB PWC,SWO

1286 CASE

I RES, 9.5% OW, l%,

LAW, 288 PPM,SMD

1286

R192

R148

WA-K

PARTS LIST

TITLE

PCA 5 8

I 121 OW, I%, 2 W

I SJUl 1812

4 L4SE

I ?ES, 1 5 0 OW,

I l W ,

(

L4SE l%, 2 W

I

PHLIP

PHL I

RCD

RCD

-

PAGE 9

-

- NO. Q T Y / P T

PHLIP 4

PHLIP

PHLIP

PHLIP

PHLIP

PHLI P

PHLIP

PHLIP

PHLIP

PHLIP

DALE

PHLIP

PHLXP

MEPCO

PHLIP

3

2

1

1

1

1

2

1

1

2

1

1

2

1

3

1

1

1

REV

L

REFERENCE DESIGNATORS

RE5, 1BW OW, 596,

1/8K, 288 P W C , W D

1206 CASE

RES, YID 1/8 LONG

188PPM I% 14.3K OW

CRCWlZ06106JT

9Cl2063A1432FKR

RES, 5HD 1/8 LONG

188PPM L% 4.02K OW

MCR18FXTA402lF

RES, W D

188PFM

1/8 LONG

I% 51.1K OW

9C12063A5112FKR

RES, 88.70 OW, I % , MC4020 88.7 @M I% T

200 P W C , 2W,SMD

4020 CASE

DALE 4703-20-1065

MEPCO 4703-21-4321

R O W 4703-24-0211

MEPCO 4703-25-1121

RCD 4703-30-8879

BECK 4770-68-0062

RES,hTW, 180 OW, a,

RES,NlWK, Z.7K,

SEC, ISOL,YID

4816P-881-181 BWRN 4770-88-8671

BOURN 4776-00-8872

BOURN 4770-68-6873

MOT 4801-01-5235

MOT 4801-02-5226

MOT 4801-02-5231

MOT 4801-02-5239

C

0

E

I D,SOT-23 k

DIODE ,SILICDN,DWL,SM BA99LT1 I

1

RLS4148

C

E t IIOOE, LEADLESS

E iQU1VALENT

I :N4148, WW, 940

'RANS,NPN,HI-FREQ,SWD WBTH10LTl

SOT-23 PKG

1

SOT-23 PKG

1

MHS,PNP,HI-FREQ,WD WBTH81LTl

I

TITLE

W A ~ E K

YXI MAlN BOARD

PARTS LIST

MOT 4803-02-0991

MOT 4886-02-1120

HP 480642-2822

R W 4807-01-4148

HP 4899-BB-8661

MOT 4901-86-1010 eKlT 4901-86-8110 mlT 4901-02-2222

ASSEMBLY NO.

1186-68-3612-01

PAGE 1 0

REFERENCE D E S I G N A T O R S PART D E S C R I P T I O N ORIG-MFGR-PART-NO

TRAHS,PNP, n I

FREQ,WD,SOI PKG

TWS,NPN,HI

FREQ,SMO,SO8 PKG

URF5583

MRF5943 wilP96m

WAVETEK NO.

MOT 4901-05-5831 m T 4981-05-9431

MOT 0981-66-7882

TLO-52CD T I 7688-88-5201

3P-AW,QUAO,JFET,SMD,

SO- 14

TL0-54CD

DGZllDY

T I

SLCON

CLC484AJE c0w11

3P-bWP,HI SLEW RATE,

LURNT FEBK,SLlt),SO-8

CLC489AJE

TIMER, UNIVERSAL, W, i 0 - 8

11083431

COMLR

W T

40

IP-bWP,ORECISION,LOn'

IFFSET,QUAD,SHO

50L-16 CASE

)P-MP, HIGH SLEW

UTE, 886 LHZ, CURR

'DBK

LT1014DS

HFA1100IB

MRLINGTW TRANSISTOR

UIRAY, SMD

U L N Z W D

K 3 3 0 7 6 D

)AC, I 2 BIT, 4

~HAH,SOIC PKG

'ERIPHERAL

, 52 P I N PLCC

M888351PF

K68981FN

3288-01-8884

L INTE

HARIS

SIC

UIT

FUJI

W T

MVTK

GAL16V8A-1SP

GaL16v8A-lSP

L ATT

LATT

BOARD

I

PAGE 11

R E F E R E N C E D E S I G N A T O R S

.

-

P A R T D E S C R I P T I O N

TITLE

W A ~ E K

PARTS LIST

BOARD

I

PAGE 12

6

5

4

-

REFERENCE D E S I G N A T O R S - -

PART D E S C R I P T I O N ORIG-MFGR-PART-NO

W D AMPLIFIER BD REF

REF

-

-

W K

W K

WVlK

,

I HEATSINK, OUTPUT

PAPLIFIER PCA

TAW, 4.;*IF,

50V,SMD,EIA 7343 CASE

~ 1 8

C29 C38 C31 C32 C33 C34 C3!

3

C37 C38 C39 C4 C5 C6 C7 C9

5

5

I

'

CAP, SWD CER 5% 50V

1000PF

CAP, SMD CER

33PF

5% 50V

CAP,SMD,CER, 3.9 PF,

S%, NPO, 1206 CASE

NEMCO

KEMET

KEMET

KEMET

PHLIP

JOHAti

AVX

1

P1 P3

T P 1

TPZ TP3 TP4

3

CAP,CER, 82 PF,

5%,NPO,SWD 1206 CASE

PC0,AMPLIFIER BD REF:

SPEC 6688-68-0455 REV

E

I HEADER, SIP, 1 5 P I N

TEST POINl,8LK,PC

TEST WIW,RED,PC

SPACER. 0.187 OD.

I

I 0.120 ID, 0.050 ?HK

NYLON

I HUT, HEX, 8-32,3/32

THK, .25 FLT,MINI,SS

W r K

SAM c m p c c m p c

BIVAR

W R L m c c

7

8

KZ K4

I LOCKWASHER,M SPLIT

I RING, SS

P4

I

I KIT, MCHIHE SCREW,

18-8 55, #4-40

M C L mc1

M C L

A R M

BOUW R32 R33 R76

R H

I

I

I POT, 186 OW, 4 mn

SQ, SIHGLR TURH, SMD

R79 I

R55 I

WAVETEK

-

TITLE

PHPLIFIER BOARD

PARTS LIST

ASSEMBLY NO. l l W - W - 3 6 8 5 - 0 1

DALE

TRW

TRW

REFERENCE DESIGNATORS

-

P A R T D E S C R I P T I O N ORIG-MFGR-PART-NO MFGl ____t

TRW

WAVETEK NO.

0781-03-1509

BWOP 1781-64-1650 RES,MFLM, 165 OW,

0. U, 1/4R, 100 PWJC

RES,MFLM, 169 OW,

0.156, 1/4W, 1 6 8 P W C

EUYOP 1701-84-1690

MEKO 1701-38-1868 RES, MF,1W1.Z5%, T2

1 6 8

RES. ZBBPPM. U. MEPCO L763-13-1001

1286 CASE

RES, 200PPM,l/SW,

156.10 OW,SMD, 1206

1206 CASE

MEPCO 1703-13-1689

MEPCO 1703-13-1501

PHLIP 1703-13-1620 RES. 162 OW, U, l A w , 200 PPM,SMD

1286

RES, W8W, U, 200

PPWC, 1.78K OHM,SMD

1286 CASE

RES, ZBBPW,

W8W, 249 l%,

OHH,

1206,SMD

RES, 1/8W,

PPWC, 24.9 KOH14,WI

1286 CASE

RES, 2 0 0 PPM, l%,

W8W, 28.7,SLO, 1286

RES, ZBBPPM, l%,

W8W, 3.01K, 1286,SIU)

RES, 1/8W, 156, ZB8

P W C , 41.2 O W , W

1286 CASE

RES, ZBBPPM, l A W ,

I%,

4 9 9 OW,

1206,SMl

RE5, 4.99K OW, l%,

Wmf, ZBB PPWC,SMl

1266 CASE

PHLIP 1703-13-1781

MEPCO 1703-13-24W

DALE 1783-13-2492

MEPCO 1703-13-2879

MEPCO 1703-13-3011

PHLIP 1763-13-4129

MEPCO 1763-13-4990

PHLIP 1703-13-4991

DALE 4703-13-4999

PHLIP 1703-13-5769 IES, 1/81, l%, 2 0 0

'PWC, 57.6 O W , W

1286 CASE

E S P 2 0 0 P W C , l%,

1/8W, 989

1286 CASE

OHM,sMD mk,

4 . 7 o ~ , S I U )

1 Z M CASE

7ES. 0 O W J W E R

PHLIP 1783-13-WW

DALE 1703-20-4709

R o w 1799-BB-6687

WAWEK

PARTS LIST

I 1 PAGE 2

REV

C

REFERENCE D E S I G N A T O R S PART D E S C R I P T I O N

)IODE,ZENER, 9.1V, i%, 5 M ,

iwo, LEADLESS

)IODE,ZENER, 15V, 58, i M , S M D LEAOLESS lIODE,SILICOH,DUAL,SM

1, SOT-23 i.P. RECTIFIER W V ,

LA LEADLESS IN4004, iwo

IIODE, LEADLESS

LQUIVALENT

: N 4 1 4 8 , M , y(D

XRCUIT PROT-SELF

IESETING, 0 . 2 W

DNS,NPN,RF,SMD, SO8

W S , N P N , H I FREQ,HI

IOL,FQIF548 STUD MWNT

TRANS,PNP,HI FREQ,HI

IOLTAGE STUD MWNT, aF549

TRANS, PNP

,

H I

:REP, SMD

,

WNS,NPN,HI

:REQ,YID,SOB PKG

)P AUP,SW),508 PKG

IEG, +lZV, S W

IEG, -12V, YID

JOT

9 T

JOT

JOT

9 T

-1NTE

JOT

JOT

KIT

O T

O T

QT low

WAVETEK NO.

WAV-K

PARTS LIST

I

I

AMPLIFIER BOARD

I

PAGE 3

R E F E R E N C E D E S I G N A T O R S P A R T D E S C R I P T I O N I R I G - M F G R - P A R T - N O

-

W A V E T E K N O .

W A ~

TITLE

K

PARTS LIST

I

ASSEMBLY NO.

1100-86-3605-81

PAGE 4

REFERENCE D E S I G N A T O R S

I

PART D E S C R I P T I O N

NONE

NONE

I

CAP, CER, DISC,

10PF.lKV. COG.5%, RAD

NONE

NONE

HONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

CAP,ELECT,l0WF,35V

RADIAL LEAD,SP .Z0

I

CAP. T M T , lMF, 35V

TANT, 4.7MF1

I

CASE

SBV,YO,EIA 7343 CASE

CAP,TMT, 6.8MF, Z W ,

2896, SMD EIA 6632

NONE

NONE

NONE

NONE

NONE

NONE

NOHE

NONE

NONE

NONE

RELAY,Z FORMC,5V101P

1 4

RELAY, 2 FORM C, SV,

LOiV PROFILE

DIODE, DUAL

SWITCHING, C W N

CAMDE,50T-23

I DIODE 5082-2811

SCHO~KY,~SV,ZBMR

LED,GREEN,PC MT., I K T

WILDER

LED.YELLW,PC

MWKT, INT. HOLDER

CIRCUIT PROT.,SELF

RESETING, 0.65 nMP

CIRCUIT PROT,SELF

RESETING, 0.2 AWP

TITLE

WAVETEK

PARTS LIST

HP

PHLIP

DIALT

DIALT

RAYW

RAYCY

I

ASSEMBLY NO.

1288-68-3613

PAGE 1

AVX

KEMET

A R M

AROMl

BOURN

MOT

48

SPRAG

AVX

AVX

AVX

STANT

N I C

SPRAG

SPRAG

N E K O

N E K D

REV

A

REFERENCE DESIGNATORS PART D E S C R I P T I O N ORIC-MFCR-PART-NO

WHE TRAHS 2N2905A PHP

SENERAL PURPOSE TO-5

NCNE

EWE r w s

2 ~ 3 9 ~

2ENERAL PURPOSE 10-92

VSC 4901-03-5630

FAIR 4901-03-9060

HONE

HON E tiON E tiONE tiON E

IRANS, P-CHAHNEL

I F ETS

TRANS,NPH,HI FREQ,HI iOL,MRF548 STUD HOUNT

TRANSIN-CHAHNEL JFETS

TRANS,PNP,HI FREQ,HI

VOLTAGE STUD WUNT,

WF549

TRAHS ZN5771 PNP

SWITCH TO-92

YSC 4901-05-7710

HONE

NONE

NONE rx

7888-68-5168

ITACH 8888-43-0256

Q T 8000-68-8868

NONE

T I 8666-74-0123

NONE

NONE

WLTIVIBRATOR,RETRIG,

HOHOSTABLE, SOIC

DECOOEWOEWLTIPLEXER

,3-10-8 LINE SOXC

TI 8866-74-0138

5IG 8000-74-0260

NONE COUNTER, WAL,4

BIT,SOIC

T I 8090-74-0393

NONE

T I 8000-74-1035

NONE IDT 8886-74-5430

NONE

NONE

HONE

NONE

NONE

NONE

NDNE

NONE

XCVR, OCTAL

REGISTERED,3-STATE

WTPUTS ,

F L I P FLOP,OCTAL D,W/3

STATE OUTPUTS ,CHDS

SHFT

REC,I-BIT,CWDS,O(ITPLJT

CLR

XCVR

,

BUS,3-STATE

DIITPLJTS ,CHOS

WECL 10KH HIGH-SPEED

ECL

GATE, OWHOR, TRIPLE

2-3-2 I H

RECEIVER-TRIP LN ECL

GATE,OR AND/OR M D

INVER WAL WIDE, ECL

1 OF 8

DECODEWDEWLTIPLEXER

I D T 8688-74-5740

T I 8888-74-5950

I D T 8888-74-6450

MOT 8001-01-0201

MOT 8861-01-0501

WOT 8001-01-1601

HOT 8881-01-2168

MOT 8007-41-3840

T I T L E

W A ~ E K

PARTS LIST

I

PAGE 2

R E V

A

R E F E R E N C E D E S I G N A T O R S

UONE

I

P A R T D E S C R I P T I D N

I

REAL TIME CLOCK

W / M , CWOS

GAL, 2 0

PIH,15NS , 1 6 V 8 - 1 5 ,PLCC

UONE

UONE ENCODER.8-TO-3

P R x O R I n

I

L I N E DRIVER,OCTAL

BUFFER,CWOS

UONE

LTACH

. A n

. A n rx

[ DT

U S S

WA-PC

PARTS LIST

I

I

1

M O E L 1 3 9 1 SPARES K I T

ASSEMBLY NO.

1 2 8 8 - 0 0 - 3 6 1 3

PAGE 3

REFERENCE DESIGNATORS PART D E S C R I P T I O N MFG WAVETEK NO.

PARTS LIST

I

ASSEMBLY NO,

1288-88-3613

PAGE 4

MATElClll Programming Appendix

A

11.1 INTRODUCTION

This appendix covers the remote operation of the Mod- el 1391 VXIbus Pulse Generator using the CIIL lan- guage in a MATE system. Section 3 of this manual covers the "Native" SCPI operation of the unit. This appendix discusses the MATE system (hardware and language) and the commands and syntax the Model

139 1 MATE Pulse Generator will recognize.

A.2 THE MATE SYSTEM

The MATE (Modular Automatic Test Equipment), an

Air Force specification for automated test systems, standardizes general purpose test equipment intercon- nection, instaIlarion, and control syntaxes. To recog- nize MATE commands, the unit must be specified as a

"Model 139 1 MATE" rather than a standard ModeI

139 1 at the time of purchase.

A.2.l MATE nardwars

Because of constraints of the VXIbus environment,

VXIbus modules do not implement a complete MATE hardware configuration. There will be no panel mounted MATE interface enable switch or Discrete

Fault Indication connector usuaIly associated with

MATE equipment. Nor is there a front panel display device to indicate MATE status at power-on.

MATE compatibility is limited to CIIL language pro- cessing in VXIbus modules. In the Model 1391

MATE, this is accomplished with an instrument ROM change. where both the SCPI and CIIL language pars- ers are contained in the instrument's firmware. MATE units default into the CIIL parser at power-on.

A.2.2 MATE Lanuusgs

The operator programs the MATE system controller using the ATLAS language. The controller communi- cates with the Model 139 1 MATE via the IEEE-488 bus (external host) or via the VXIbus (embedded con- troller) using the CIIL command strings. The Model

139 1 MATE uses its language parser to translate the

CIIL command strings into the Model 1391's native

SCPI language. This appendix deals with only the

CIIL commands.

ATLAS (Abbreviated Test Language for All Systems ) is an easy-to-read English-like language. The ATLAS language does not allow partial insrrument setups.

This means all items, except defaults, must be entered in each string. For further information on the ATLAS programming language, refer to ANSIlIEEE Std 4 16-

198 1, IEEE Std 7 16- 1982, and IEEE Std 7 17- 1982.

The system uses the CIIL (Control Interface Interme- diate Language) language to communicate between the controller and the Pulse Generator. The CIIL com- mands are sent as an ASCII string. The CIIL language uses standard sets of commands which allow the Mod- el 1391 MATE to be used in test systems without the necessity of rewriting the test software. However, this limits the language to standard commands that will function for all manufactures of a specific type of test equipment. To utilize any unique features of the Mod- el 1391 MATE, it is necessary to use the G A L com- mand to exit from the CIIL language and use the native language of the Model 1391 MATE. Use

SYST : L A N G : CI I L command while in native lan- guage to return to CIIL. For more information on the

CIIL language, refer to Air Force standard 2806763

Revision C, 21 June 1988. The following list defines the ModeI 1391 MATE'S MATEKIIL capabiIities:

Set up of Pulse Generator functions and pulse characteristics.

Burst, triggered, gated or continuous output mode setup.

Output amplitude and dc offset control.

Output frequency/periodfpulse repetition rate control.

External triggerlgate slope and level contro1.

Pulse amplitude modulation.

MATEiCIIL

PROGRAMSIING

A.8 THE MODEL 1891 MATE IN THE MATE SYSTEM

A.8.1 System Connactlon

The Modcl 1391 MATE is part of a VXlbus system, and i l residcs in a VXIbus chassis. As such, it is sub- ject to all benefits and rcstrictions of the VXlbus envi- ronment, Whcn the MATE controller is external to the

VXlbus chassis, it communicates over the GPlB bus to the GPIBNXlbus rranslaror located in the Command- er (slot 0)

VXlbus chassis has a Primary GPIB Address and the

1391 MATE module within the chassis is reached with a GPIB Secondary Address. When rhe VXlbus Com- mander is an embedded controller, the GPIB bus is not involved and communication between the Commander and the 1391 MATE module is restricted to the VX1- bus Protocols.

The system interconnections for a 1391 MATE unit are the same as for the standard unit described in Section 3 of this manual.

A.8,2 ldentllylns

a

Model 1881 MATE

There are two methods of verifying a 1391 is a MATE unit. First, check the "rear panel" of the module; the serial tag between the P1 and P2 connectors will indi- cate "1391 MATE" for a MATE unil and "1391" for a standard unit under the mode1 number. Also, if the module(s) are plugged into the VXIbus chassis, a stan- dard unit will respond with full Manufacturer and

Model number information to the mandated IEEE-

488.2 ' D N command, whereas the 1391 MATE unit responds with a "space" character, indicating a non-

MATE command.

A.4 THE Clll LANGUAGE

The notations listed in Table A-1 represent the ele- ments of CIIL command strings uscd in this manual.

Thcsc notations aid in describing [he correct syntax for command strings. In practice the controller transmirs the ASCII code for the indicated syntax.

A.4,1

Clll

Command Strlnst

Shown bclow is the standard form of the CIIL com- mand string:

Table A-2 defines the command string items used by the Model 1391 MATE. Figure A-1 contains the de- tailed Pulsemiming Generator syntax diagrams.

A.4.2

Syntax Pntht

The path, as shown in Figure A-1, through the syntax diagram follows the standard form of the CIIL com- mand string. All commands appenring on the syntax path must be included in that command string. When the Model I39 1 MATE receives a

< c r

.

1

>

(carriage rcturn and line fced), the unit assumes the command string is completc. On the diagram, a solid line by- passing some commands indicate defaults; adjacent to each defauIt line is a default value. To get a default. omit the default command from thc string.

Notation

I

.I. b chan num set code noun modifier value

Tnbla 11.1. CllL Notstlons

Meaning

Separator between elements in a set of values. Only one element of the values presented may be selected.

These brackets surround elements in a string that are necessary for a com- plete command string.

These brackets surround optional ele- ments in a command string and are not necessary for a complete com- mand string. indicates that other elements may be required or desired as pan of the com- mand string.

Indicates the necessity for an ASCII space in the pan of the command string where it appears.

Indicates that a channel number must be specified as part of the command string where it appears.

Indicates that a CIIL set code must appear as pan of the command string where it appears. There are only three set codes. They are: SETISRNISRX.

Indicates that a CIIL noun must ap- pear as pan of the command string where it appears.

Indicates that a CIIL modifier must appear as pan of the command string where it appears.

Indicates that a numeric value must appear as part of the command string where it appears. This number can be expressed in floating point, engineer- ing or integer notation. Can also indi- cate a non numeric value; the possible non-numeric choices in that instance are given in the syntax diagrams.

Indicates the necessity for an ASCII carriage return followed by a line feed in the command string where it appears.

Op Code

Noun

Chsn Num

Set Codes

Modifiers

Teble A-2, Model1881 MATE CIIL Commundr

CFRQ

DCOF

DELA

PREQ

GALV

ClIL

Command

CLS

CNF

FNC

I S T

OPN

R S T

STA

Closes

- activates Pulse Gene output

Initiates confidence test

Selects function

Initiates self-test

Opens

- deactivates Pulse Ge output.

Reset-deactivates Pulse Gene output and returns Pulse Gt to power-up conditions.

Requests status

PAM

PDC

PDT

SQW

Pulse Amplitude Modulation

Selects single pulse output.

Selects double pulse output.

Selects square wave output.

: C H 0

S E T

SRN

SRX

Set value

Set minimum

Set maximum

BURS Sets up burst count.

CAMP Sets pulse carrier amplitude

(PAM).

Sets pulse carrier frequency

(PAM).

Sets up dc offset of selected waveform.

Sets pulse delay relative to sync output.

Sets frequency of square wav

Sets external gate level.

None

None

None

None

PDC, PDT, SQW, or PAM.

None

None

None

0 only

None, each code has the same effect on the Model 1391 MATE.

--

PDC. PDT, SQW, or PAM:

1 to 10e6 counts.

PAM only;

0.15 to 16.0 Vpp, (50R).

PAM only;

0.001 Hz to 50e6 Hz.

PDC, PDT, or SQW;

-8.0 to +8.0 Vdc (50R).

PDC or PAM

;

0.0 ns to 2000 s.

SQW only; 0.00 1 Hz to IOe6 Hz.

PDC, PDT. SQW, to +10.0 Vdc.

: -10.0 Vdc

Modifiers

(continued)

Table A-2. Model 1391 MATE CIIL Commands (Continued)

CIIL

Command

GASC

Description

GSTA

Selects either internal or external gate source.

Selects the exrernal gate srart slope.

GSTO

MDSC

PER1

PLWD

PRFR

R I S E

FALL

SPCG

TIMP

TRFR

TRLV

TRSC

TRSL

VLPK

VLPP

VRMS

Selects the external gate stop slope.

Selects the PAH modulation source: internal or externa1.

Sets period of single pulse or square.wave.

Sets pulse width for singIe and double pulse and PAM.

Sets pulse repetition rate for single and double pulses and PAM.

Set the rise time (10% to 90%) of the leading transitions.

Set the fall time (10% to 90%) of the trailing transitions.

Set delay belween two pulses in the double pulse mode.

Sets Pulse Generator output impedance.

Sets internal triggering frequency.

Sets external trigger level.

Selects internal or externaI triggering source.

Selects external trigger slope.

Sets amplitude peak value.

Sets square wave amplitude peak to peak value.

Sets square wave RMS amplitude.

Llmlts

PDC, PDT, SQW, or PAM :

I N T orEXT.

PDC, PDT, SQW, or PAK. POS or

NEG; must be opposite of GSTO.

PDC, PDT, SQW, or PAX. POS or

NEG; must be opposite of GSTA.

PAM only;

EXT only.

PDC or SQW;

I&-9 to 1000

S.

PDC, PDT, or PAM;

10e-9 to ZOO0 s.

PDC, PDT, or PAM;

0.001 to 50c6 Hz (25e6 Hz for double).

PDC, PDT, SQW, or PAM :

5e-9 to 50e-6 s.

PDC, PDT, SQW, or PAM;

5e-9 to 50e-6 s.

PDT only ;

2 0 ~ - 9

S.

PDC. PDT, SQW, or PAM; 50Q only.

PDC, PDT, SQW, or PAM;

20e-9 to 2000 s.

PDC, PDT. SQW, or PAM:

+10.0 to -10.0 Vdc.

PDC. PDT, SQW, or PAN:

I N T orEXT.

PDC, PDT, SQW, o r PAM ;

POS orNEG.

PDC, PDT, or SQb!;

75e-3 to 8.0 Vpk

S QW only ;

150e-3 to 16.0 Vpp.

SQW only ;

75e-3 to 8.0 Vrms.

NOTE

See Figure A-I at the rear of this section for MATE syntax diagrams.

A.6. USING THE PULSE GENERATOR IN THE MATE

SY STEM

11.6.1

Power

Up 8attlnga

At power up the Pulse Generator defaults to the fol- lowing conditions:

Output Frequency:

Waveform:

Amplitude:

1 MHz. single pulse; 250 ns width. upper +0.5V. lower -0.SV.

Mode:

Output:

Continuous.

Off.

To close the output relay, send the CIIL command string:

11.6.8 U8lng 181 (In8Pument 8slf 1881) Op Code

Use I ST (instrument self test) to activate the built in test (BIT) to functionally check the module. During the test the instrument uses its own DVM, counter, trigger generator, and VXIbus system clock to evaIuate the module. The diagnostics will isolate failures, if they occur, to the module. If a failure is reported, fur- ther diagnostics, not necessarily supported in CIIL can be run on a module level to assist in aoubleshooting.

Use STA (status) to verify the unit has passed the self test. To initiate the instrument self tesl. send the com- mand: I S T

< c r , 1

> .

See Appendix D for detailed information on the ing this command. mission). The STA command causes the Model 1391

MATE to return one of two valid responses.

" F 0 7 P L G O O : < A S C I I m e s s a g e > < c r , l f > " indicates a failure was dctccted during the confidence test, or an error was detected in the information rc- ceived in the instrument setup command.

"

< b

> < c r , 1

>

" indicates no failures or errors.

To check the status, send the command:

S T A < c r ,

>.

1.6.6 Udng the CLS (Cloas Output) Op Code

The Pulse Generator initializes with the output relay open. Send the CLS command string to close the out- put relay to obtain an output. Send the command suing:

1.6.2 Ualng CNF (Conlldanee

1

Op Cods

Use CNF (confidence) to test overall Mode1 1391

MATE operation by programming predetermined mod- ule set-ups and verifying the instrument provides the expected output. At the completion of the confidence test, the unit resets to the power-on condition. Use

STA (status) to verify the Model 1391 MATE has passed the confidence test. To initiate the confidence test, send the command: CNF

< c r ,I

> .

See Appen- dix D for detailed information on the which is run following this command.

1.6.4 U8lnfl ST11 (8tatu8) Op Coda

Send S TA (status) afrer a confidence tesr (CNF), in- ternal seIf-test ( I ST), or setup command (FNC trans-

11.6.8 U8lnu the FNC Op Cods

Use the FNC command to set up the Pulse Generator.

The syntax diagrams, figure A-1, illustrate the FNC paths required to set up the generator.

A.5.6.1 Pulse Oul Oulpul Amplllude and Tlmlng

Figure 3-4 shows the pulse waveforms and their asso- ciated amplitude and timing modifiers.

Values for the voltage peak (VLPK) modifier set the peak amplitude for the pulsed dc (PD C) and the pulsed dc train (PDT) waveforms; the waveform baseline for all waveforms is specified by the dc offset (DCOF) value.

Square wave (SQW) amplitude can be specified with the modifiers shown; volts-peak-to-peak (VLP P) can only be used to specify a value for the square wave peak-to-peak, specifying values for VL P K or VRM S sets the peak value of the square wave.

Specifying a value for the period (PER I ) se ts the peri- od for all waveforms; the spacing (S P C G ) value sets the time between the leading edge of the first and sec- ond pulses for pulsed dc trains (PDT) only.

Specifying a value for the pulse width (PLWD) sets the pulse width for pulsed dc and pulsed dc trains only.

The transition times for all pulses and the square wave can be set with the rising ( R I S E ) and falling (FALL) transition times commands.

The pulse repetition frequency ( P RF R ) modifier can be used to specify a value for pulse repetition frequen- cy as an alternative for setting the waveform period.

A.5.6.2 Pulsed DC (PDC) Wavelorm Programming

Table A-3 shows the modes and controls supponed by

CIIL for single pulse generation. Refer to the syntax diagram, figure A-I, to find the required command strings for the desired setup.

MATEICIIL PROGRAMMING

A.5.6.3 Pulsed DC Traln (PDT) Waveform Programrnlng

Table A-4 shows the modes and controls supported by

CIIL for double pulse generation. Refer to the syntax diagram, figure A-1, to find the required command strings for the desired setup.

A.5.6.4 Square wave (SOW) Waveform Programrnln~

Table A-5 shows the modes and controls supported by

CIIL for squarc wave generation. Refer to the syntax diagram, figure A-1, to find the required command strings for the desired setup.

A.5.6.8 Output Impedance

The test equipment impedance value the module's output impedance. The only allowable value for the Model 1391 is 50R.

A.6 SYNTAX EXAMPLE8

Follow the syntax diagram. figure A-1, to help under- stand the CIIL command strings given in the examples.

In the rriggered mode, the Pulse Generator starts a waveform when it receives a valid trigger. The fol- lowing describes the trigger commands. The triggered mode cannot be used for square waves.

Specify the non-numeric valucs (EXT or INT) to se- lect the trigger source (TRSC). EXT (external) se- lects the module's TRIG IN input BNC connector as rhe trigger source. INT (internal) selects Model

1391's internal trigger (TRFR) bus as the trigger source.

Specify the non-numeric valucs to sclcct the trigger

Specify the numeric value to sets the trigger level

(TRLV).

A.5.6.6 Gatlng

In the gated mode, the Model 1391 MATE produces a wavef6rn-i as long as the trigger (gate) is aciive. Fig- ure 3-7 shows the relationship between the gating sig- nal and the Pulse Out.

~pecifyingeitherPOS (positive)orNEG (negative)

A.B.1 Pulsed DC (PDC) Conrlnuous

This CIIL command string sets the Pulse Generator output for continuous 10 ns, 4V

20 ns. The pulse repetition frequency is IMHz, and the dc offset is 1V. Output impedance is set to 50R. The transition times wilI be at their default value of

A.6.2 TrleneFed Pulred DC (PDC)

This CIIL command string sets up the Pulse Generator for triggered 10 ns, 2V pulses. An external source trig- gers the pulses on the negative slopc at +3V. The waveform is offset +2V. The output impedance is

50R. The leading edge is 10 ns, and the trailing edge is minimum (5 ns).

F N C < b > P D C < b > C H o < b > S E T < b > V L P K < b > 2 < b >

S E T < b > P L W D < b > l O e - 9 < b > S E T < b > T R S C < b >

EXT<b>SET<b>TRSL<b>NEG<b>SET<b>TRLV<b>3<b>

S E T < ~ > D C O F < ~ > ~ < ~ > S E T < ~ > T I M P < ~ > ~ O < ~ >

(GSTO). These values set the trigger slope on which thc waveform stans and stops.

The gate stan slope (GSTA) and gate stop slope

(GSTO) values can never be both positive or both neg- ative. Specifying one value without the other causes the Model 1391 MATE to automatically switch, if nec- essary, the remaining unspecified modifier value to the opposite slope. Specifying equal values results in an error message and termination of the command string.

See Table A-6 at the rear of this appendix for error messages.

A.5.6.7 Bunt

In the Burst mode, the Mode1 1391 MATE produces a user programmed number of waveforms each time the trigger is valid. The burst (BURS) value sets the num- ber of waveform periods generated for each trigger.

5

- 9 < c , 1

A.0.8 Pultad DC TFoln (PDT) B u ~ t t

This CIIL command string sets up the Pulse Generator for a triggered burst of 50, ns, 5V double pulses at

1 MHz and 20 ns spacing between the double pulses.

The external source triggers the module on the positive slope (default slope) at +2V. The pulses are offset

+1V. The output impedance is 5 0 R (defauh imped- ance).

Supported Modes

Conhuous

Triggered

Bursr

Gated

Tsbls 1.8. Avsllabls Plllrad OC Wavslorm Mod08 and Control8

Trlgger Controls

Trigger Freq (TRFR)

Trigger Slope (TRS L)

Trigger Level (TRLV)

Trigger Source (TRS C)

Gate Controls

Gate Start Slope (GS TA)

Burst Controls

Burst Count (BURS )

Gate Stop Slope (GSTO)

Gate Level (GALV)

Trigger Freq (TRFR)

Trigger Slope (TRS L)

Trigger Freq (TRFR) Trigger Level (TRLV)

Trigger Source (TR S C)

Supported Modes

Continuous

Triggered

Burst

Galed

Trigger Controls

Trigger Freq (TRFR)

Trigger Slope (TR S L)

Trigger Level (TRLV)

Trigger Source (TRS C)

Gate Controls

Gate Stan Slope (GSTA)

1

Burst Controls

Burst Count (SURS)

Gare Stop Slope (GS TO)

Gate Level (GALV)

Trigger Freq (TRF R)

Trigger Freq (TRFR)

Trigger Slope (T R S L)

Trigger Level (TRLV)

Trigger Source (TR S C)

Spacing between double pulses must be specified with the SPCG modifier, its attendant value and the modifiers

Square wave (SQ W ) outputs.

Supported Modes

Continuous

Triggered

Burst

Gated

Table A+. AvsllabIa Ilqurre wsvs Mode8 and Control8

Trigger Controls

Trigger Freq (TRF R)

Trigger Slope (TR S L)

Trigger Level (TR L V)

Trigger Source (TR S C)

Gate Controls

Gate Start Slope (G STA)

I

Burst Controls

Burst Count (BURS)

Gate Stop Slope (GS TO)

Gate Level (GALV)

Trigger Freq (TRFR)

Trigger Freq (TRFR)

Trigger Slope (T R S L)

Trigger Level (TRLV)

Trigger Source (T R S C)

The trigger confrols are used for the burst mode only.

AJ.4 Contlnuout 8quara Wave (Saw)

This example sets up the Pulse Generator for continu- ous 2 Volt peak-to-peak, 2 MHz square waves. The de- faults for dc offset and output impedance are used.

1.7.1 PAM Example

In this example, the Pulse Generaror (at address 3) pro- duces a 2MHz, 3Vp-p, 300ns pulse. The external sig- nal (MATE compatible Function Generator at address

2) modulates the Pulse Generator with a 3Vp-p, 6 kHz triangle wave.

Write @ secondary address 2:

A.6.6 Gated Pulte DC Traln

In this example the Pulse Generator produces gated

10 ns. 5V double pulses at a 1 MHz rate. The space between the double pulses is 20 ns. An external source gates the Pulse Generator on the negative slope and stops on the positive slope. Threshold level 1V.

DC offset and output impedance are the default values.

Write @ secondary address 3:

A.7 SELECTING PULSE AMPLITUDE MODULhTION

(PAM)

The Pulse Generator can be pulse amplitude modulated from an external source. To externally modulate the

Pulse Generator, apply a moduIating signal not greater than 20 kHz to the PAM IN input. The CAMP com- mand sets the pulse amplilude, and the CFRQ sets the pulse carrier frequency.

A.8 PULSE GENERATOR ERROR MESSAGES

Table A-6 lists all the possible Pulsefliming Generator error messages that could occur during normal opera- tion. Each message contains in quoles a brief explana- tion of the messages meaning. One of two ASCII strings ("FO7PLGOO (MOD)

"F O 7 P L C D ) : precedes each error message.

When the term <ASCII> appears in the error messages listed below, i t represents any continuous suing of

ASCII characters except space, tab, LF, CR.

.

This string can represent valid nouns, modifiers, or data, as well as misspelled or garbage strings. If the string syntax is valid, then the string could be out of order or there could be some other reason the string was not ac- cepted.

Table A-0.

Error

M e r r a g e r

E r r o r Message

"<P,SCII> or: a l l o w e d "

" < A S C I I > m i s s i n g "

" < A S C I I > l i n i t e r r o r "

"GSTA/GSTO s l o p e e r r o r "

" c h a n n e l n u m b e r e r r o r "

" s e t r i n g m i s s i r g f r o m F N C c o m o a n d "

"INT/EXT n o r a l l o w e d with <ASCII>"

"?OS/NEG n o t a l l o w e d w i t h <ASCII>"

" n u m e r i c v a l u e n o t a l l o w e d w i t h <ASCII>"

" v a l u e n e e d e d < A S C I I > "

"command terminated b e f o r e c o m p l e t e "

Comments

This ASCII string cannot bc used as cntcrcd.

A mandatory modifier is missing in the command string.

For example, thc command requires a V L P K modifer.

The value sent exceeds the modifier's limit.

Both the gate start and slop slopcs wcrc scr to thc samc valuc.

Only channel 0 can be used with the Pulse Generator, because it has only one programmable o u t p u ~ .

Thc command string was correct up lo the mandatory

S E T modifier which is missing.

The modifier is correct, but modifier values.

I or E X T are not valid

The modifier is correct, bur P O S or N E G are not valid modifier vaIues.

The modifier sent does not accept numeric values.

T R S and G A S are examples of modifiers that do not take numeric values.

The modifier noted in the ASCII string requires a value.

"FNC P D C < c r > < l f > " c a u s e s t h i s e r r o r m e s s a g e .

The command string is correct up to the terminating characters. But, the entire command string is incom- plete.

This message represents any Pulse Generator dependent error message.

"TRSL/TRLV n o t a l l o w e d w i t h G A S C "

"TRSL/TRLV n e e d T R S C EXT"

" G S T A / G S T O / G A L V n o t a l l o w e d w i t h

T R S C "

" G S T A / G S T O / G A L V n e e d G A S C E X T "

Trigger slope and trigger level values are not valid when set up for a gate source.

Trigger slope and trigger level values are only valid when set up for an external trigger source.

Gate slope and level not valid when using a trigger source.

Gate slope and level only valid when using an externaI gate source.

"BURS n o t a l l o w e d w i t h G A S C , n e e d s

TRSC"

" 5 0 . 0 o h m i m p e d a n c e o n l y "

Burst modc uses source).

(internal or external trigger

The only valid arguement for T I M P is 50Q.

"TRFR is n o r a l l o w e d f o r E X T s o u r c e " TRFR is the internal trigger frequency.

" T R F R i s m a n d a t o r y f o r I M T s o u r c e "

" E X T s o u r c e o n l y w i t h M D S C "

" X D S C o n l y a l l o w e d w i t h P A X "

Must specifiy an internal triggering frequency when triggering from the internal source.

Thcrc is no internal source for P A M modulation sourcc.

Set up the modulation source only with PAM.

Format ol Common Commends

Modlllert Supported In each Funellon (noun)

MODIFIER

P A M

NOUN

PDC

1

P D T

G ALV

GAS C

G S T A

GSTO

MDSC

P E R 1

PLWD

P R F R

R I S E

S PCG

T I M P

T R F R

T R L V

T R S C

T R S L

VLPK

V L P P

VRXS

BURS

CAMP

CFRQ

DCOF

DELA

F A L L

F R E Q

Flgura A-1. Pulse Generator CllL Syntax Dlagrams.

F o r m a t f o r s i n g l e p u l s e

<b>cvalue>

I continuous made

.

@ T o < ~ > b ) D E L A c D defauft 0.0 wal

SRX

Cefault 0.0

Flgure A-1. Puka Generator CllL Syntax Dlagrams (Contlnusd).

Format f o r double pulse note: GSTA and GSTO carvlol be set to sane s l o w

SRX default 0.0

SRX

Flsurs A-1. Pulta Generttor Clll lyntax Dlasramt

(Continued).

F o r m a t f o r s q u a r e

MPK

I NT

I

cantlnuous mode

<b~TR5ub<$z&><:~>b>TRLv<b>

SRX w u derzv, t I ,O

F o r m a t f o r p u l s e a m p l i t u d e modulation t r t a a e r e d mod? b u r s t mode

PRF <b><vaIue)

1

continuous mode note: GSTA and GSTO cznnot be set to same s l o w de iau l t POS or c c ~ o s GSTO

SRX

Self Calibration Appendix C

C.1 lntroductlon

This appendix provides the Operator/Programmer with response value to either the C A L ? IEEE-488.2 Com- mon Command or to the SCPI C A L i b r a t e [ : ALL1 ? query. This informalion supplements paragraphs

3.3.3.1 ( C A L i b e ) and 3.3.4 ( ' CAL?). these "automatic" Alignmenl steps, equivalent to send- ing the SCPI command : D I A G : C A L ?

< n

> four times, whcrc "n" equals I,2,3, and 6.

If the Self Calibration is not succcssful, the Alignmcnt data i s not storcd in the instrument and the query re- sponsc is non-zero. The Error Code field contains a bit-weighted code that is uniquc to which parameter failed and has the following meaning:

C.l .I CRLtbrate Query Response

Error Code Bit M e a n i n g

According to IEEE Std. 488.2-1987 section 10.38, the

Calibration query causes an internal Self Calibration to be performed and a responsc to be placed in the Outpul

Queue. The response to the C A L ? query is an ASCII string representing an integer value. The value of 0 is returned if the Self Calibrarion passed and a non-zero value in the range of 32767 to -32768 is returned if the

Self Calibration failed. The interpretation of the value returned in the event of a failed self calibration is de- fined by rhe module manufacturer.

The ' query invokes the same internal seIf cali- bration funcrions and returns the same reponse as the

C A L i b : A L L ] ? qucry documented below.

CALI brate[:ALLl?

The C k L i [ : A L L ] ? query returns a detailed error code indicating the nature of a failure. The value of a 16-bit Self Calibration Status Word is returned in response to the Calibration query, The formal of the

Self Calibration Status Word is shown below:

Amplitude

Offset

Delay gatable oscillator frequency

Width gatable oscillator frequency

Gatable trigger oscillator mini- mum frequency greater than 25MHz.

Gatable trigger oscillaror maxi- mum frequency less than 5 0 MHz.

Hardware failure,

The auro calibration sets the UUT back to its previous state after the calibration is complete. While perform- ing the auto calibration the output relays remain open s o as not to disturb any cxternal devices. For each step, all parameters no1 listed under the bil number are at reset state during the Self Calibration.

Sell Calibrallon Staius Word

The S t l f Calibration consists of performing all steps of thc Alignment Proccdurc (Paragraph 5.5) which are in- dicalcd as "automatic". If the Sclf Calibration is suc- cessful, thc modulc pcrforms a11 o f these steps and rccords "frcsh" alignment data without extcrnal test equipment o r opcrator adjustmcnts, and then returns the valuc zcro as a qucry response. Thcre are four of

C.1.2 Sell C8llbP8tlOll E r r o r Codes

BH 0 & 1: Amplllude and Onset Error

The Mode1 1391 is set up according to a

: D I : C A L ? 6 command, as follows:

R E S E T

V O L T 5

F R E Q l e 3

F U N C S Q U A R E

I N I T : O F F

T R I G : T O F F

P U L S : P O L A R I T Y C O H P L E M E N T

The amplitude and offset DAC's are set to 0. The out- Blt 3: Width Gatable Osclllatur Frequency Error put voltage is read and i f i t is outside of = 1.0 volt,

The Model 1391 is set up according to a bit 1 is set. The offset DAC is then set to 910 (approx.

: D I A G : L? 2 command. as follows:

+5.5 V offset). If thc output voltage is not between

4.5 Vdc and 6.5 Vdc, bit 1 is set. Thc offset DAC is then set to 3 185 (approx. -5.5 V offset). If the ourput

R E S E T

VOLT 5 voltage is not between -6.5 Vdc and -4.5 Vdc, bit 1 is I N I T : O F F set. The offset DAC is set back 10 0 and the amplitude T R I G : B U S

DAC is set to 3185 (approx. +6.5 V level). If the out- T R 1 G : C O U N 5 0

P 2 L S : U I D T H 5 0 0 e - 6 put voltage is nor between 5.5 Vdc and 7.5 Vdc, bit 0 is set. The amplitude DAC is set to 910 (approx.

+2.0 V level). If the output voltage is not between

1.0 Vdc and 3.0 Vdc, bit 0 is set. These measured val-

The pulse width is measurcd and thcn the eatable os- cillator frequency is dcternlined. If not between 95e6

3 is set. ues are used to establish zero offset and the value

"mV/bitV in amplitude and offset setup routines.

These values are saved in the cal data base unless an error occurs, at which time the default values are saved.

Bit 4 1 5 : Trigger Gateable Osclilarur Frequency Error

The Model 1391 is set up according to a

: D : C A L ? I command, as follows:

Blt 2: Delay Gatable Oscillator Frequency Error

The Model 1391 is set up according to a

: D A : 3 command, as follows:

R E S E T

V O L T 5

I N I T : O F F

T R I G : B U S

I R I G : C O U N 5 0

? U L S : D E L A Y 5 O O e - 6

The pulse delay is measured and thcn the gatable oscil- lator frequency is determined. If the oscillator fre- se[.

X E S E T

V O L T 5

F R E Q 2 5 e 6

F'i'NC S Q U A R E

INIT C O N T O F F

: S O U R B U S

T R 1 G : C O U N 5 0

Thc trigger gatable oscillator DAC is set to 0 and fre- quency is measured, then the DAC is incremenled by

585 and measured until the maximum DAC value is reached. The span should be from less than 25 M H z to greater than SOMHt. If minimum value is > 25e6 then bit 4 is set. If maximum value is < 50e6 [hen bit 5 is set.

Blt 14: Hardware Enor

The processor had a bus failure in trying to access hardware,

Sell Test Appendix

D.1 INTRODUCTION

The Error Code field contains a bit weighted code that is defined in the following table.

This appendix provides the OperatorlProgrammer with additional information needed to interpret a non-zero response value to either the ' mon Conimand or the SCPI TEST [ : ALL] 7 query.

This information supplements paragraphs 3.3.3.2

(TEST) and 3.3.4 ( ' T S T ? ) .

E r r o r Code Bit Meaning

D.1 .I TEST Query Response

According to IEEE Std. 488.2-1987 section 10.38, the self test query causes an internal Self Test to be per- formed and a response to be placed in the Oulput

Queue. The response to the ' T S T ? query is an ASCII string representing an integer value. The value of 0 is returned if rhe Self Test passed, and a non-zero value in the range of 32767 to -32768 is returned if the Self

Test failed. The interpretation of rhe value returned in the event of a failed Self Test is defined by the module manufacturer.

The T functions and returns the same response as the

TEST [ : ALL ] ? qucry docurncnted beIow.

Amplitude DAC Control

Trailing Edge DAC control & c10ns control

Leading Edge DAC control & <Ions control

Limit amplifier

SUMBUS

Delay gateable oscillator

Width gateable oscillator

25-50 MHz gateable oscillator

Hardware bus error

If no failures were detected by the self test then the Er- ror Code field will be set to zero.

The TEST I ALL] ? query returns a detailed error code indicating the nature of any failure. The value of a 16-bit Self Test Status Word is returned in response to the TEST [ :

I

? query. The format of the Self

Test Status Word is shown below:

Error Code

" ' 1 5 1 4 1 3 1 2 1 1 10 9 1 7 1 5

Self Test Status Word

The Self Test saves the state of the instrument prior to starting and restores it after the test is complete.

While performing rhe Self Test, the output relays re- main open so as not to disturb any external devices.

D.1.2 8all Tart Error Codas

Blt 0: Amplitude DAC

The model 1391 is set according to the following:

RESET

Program amplitude DAC to 0.

1 2 0 '

Set bit zero (Fail the test) if voltage at ADCCHl is outside r 0 . I Vdc. Program amplitude DAC to 4095 and Ser bit zero if voltage at ADCCHl is outside of

1.048 Vdc 0.25 Vdc.

D

Bll 7 : Tralllnu E d ~ a

Thc modcl 1391 is set according ro thc following:

R E S E T

Program trailing edge DAC ro 0 and set bit 1 if voltage at ADCCH2 is > 0.25 Vdc. Program trailing edge

DAC to 4095 and set bi; 1 if vollage at ADCCH2 is

< 3.361 Vdc or > 4.071 Vdc. Program U11-6 & 7 high and ser bit 1 if the voltage at ADCCH2 is < 2.761 Vdc or > 3.36 1 Vdc.

P U L S : D E L 1 2 5 e - 6

F'LNC P U L S E

T X I G : S O Y X B U S

I X I T C D N T OFF

5 0

Program U13-6 low and U13-3,4,& 5 high to s e l e c ~ delay pulse signal for the intcrnal measurement circuir.

Measure delay and ser bit 5 if the delay value is not between 100e-6 and 150e-6.

Blt 2: LeadInQ EdQe DAC

The model 1391 is set according to thc following:

R E S E T

Program leading edge DAC to 0 and set bit 2 if the volrage at ADCCH3 is < -0.25 Vdc. Program leading edge DAC to 4095 and set b i t 2 if the voltage at AD-

CCH3 is < -4.089 Vdc or > -3.389 Vdc. Program Ul l -

6 Br 7 high and set bit 2 if voltage at ADCCH3 is

< -3.3006 Vdc

OT

> -2.706 Vdc.

011 3: Llrnlt Arnpllller

The rnodcl 139 1 is set up according to the following:

R E S E T

Set bit 3 if the voltage at ADCCH4 is outside

2

0.15 Vdc.

Bll6: Wldth Galeable osclllator

The model 1391 is set up according to the following:

F R E Q le3

V O L T 5

P S L S : W I D T 2 5 0 e - 6

P U L S : D E L 1 2 5 e - 6

F U N C P U L S

T R 1 G : S O U R B U S

I N 1 T : C O N T O F F

T R 1 G : C O U N 50

Measure the width and set bit 6 if rhe width value is nor between 200e-6 and 300e-6.

Bit 4: SUMBUS the model 1391 is set up nccording to the following:

R E S E T

Program U7-5 high and set bit 4 if the voltage at AD-

CCH5 is outside r 0.05 Vdc.

Bit 7: 25-50 MHz Galeable oscillator the model 1391 is se[ up according to the following:

F R E Q 6 6 6 . 7

V O L T 5

F U N C S Q U A R E

T R 1 G : S O U R B U S

1 N I T : C O N T O F F

T R 1 G : C O U N 50

This setup generates a 749.9625 e-6 width signal to

Blt 5: Delay Galeabla osclllator

The model I391 is ser up according to the following:

F R E Q ie3

V O L T 5

P U L S : W I D T 2 5 0 e - 6 the width value is not between 700e-6 and 800e-6.

Blt 14: Hardware Bus f a l l a e .

The processor had a bus failure in trying ro access hardware.

SCPI

Conformance Information Appendix

E

E.l INTRODUCTION

This Appendix contains compliance data as required by the SCPI 1992 Specification. Volume 1: Synrax and

Style. Specifically, paragraph 4.2.3. Documentation

Requirements, specifies the Conformance Information requirements for SCPI products.

E.2 MODEL 1 8 9 1 SCPI VERSION

The Model 139 1 VXIbus Pulse Generator has been dc- signed to comply with SCPI Version 1992.0, dated

February 1992. idenrified with with the notarion "Approved" in the third column.

E.8.8 Commands not part ol the 8CPI 8ueclllcatlon

The SCPI Specification does allow products using the

SCPI language to have specialized commands included which are outside of the SCPI definition. Refer to Ta- ble E. 1 for rhe complete syntax of Model 1391 SCPI commands. Any Model 1391 commands which are not in the SCPI definition will be identified with the nota- tion "Not SCPI Approved" in the third column.

E.8 MODEL 1 8 8 1 SCPI COMMAND SYNTAX

The SCPI specification, Version 1992.0. defines three type of SCPI commands which may be used in a SCPI product: Confirmed Commands, Approved Commands. and commands which are nor pan of the SCPI defini- tion.

E.8.4 Incomplete Command lnplementatlon

The SCPI definition specifics cach command com- plercly, and if the command keyword is at the leaf node, it specifies the parameter data and query re- sponses. In some cases. a SCPI product may not im- plement all of the choices given in the specification.

For example, when parameter character data is in the form of a list of choices. the product's hardware may not support all of those choices:

Confirmcd Commands are those commands which are published in the SCPI 1992 Specification. Volume 2:

Command Reference. Rcfer to Table E. 1 for the com- plete syntax of iModel 1391 SCPI commands. Model

1391 Confirmed Commands will be identified with with the notation "Confirmed" in the third column.

Approved Commands are those commands which have been approved by the SCPI Consortium. but are not published in the SCPI 1992 Specification. Refer to

Table E. 1 for the complete synrax of Model 1391 SCPI commands. Model 139 1 Approved Commands will be

In this example, a complete list of possible Frequency

Modes is given. However, the product's feature set may want to have a settable Frequency Mode in order to set a CWIFIXED frequency. and to enter a Frequen- cy Sweep Mode. The other Modes, LIST and SENSe, may not have any hardware to support them. In this case, the SCPI Syntax Table (see Table E. 1) would use footnotes to indicate partia1 conformance to the SCPI

Specifica~ion.

KEYWORD

Table E-1. Model 1391 SCPI Command Syntax

PARAMETER FORM

OUTPut

:ECLTrgCn>

[ STATe]

: SOURce

[ : STATe]

: SUMBus

I

: STATe

:TTLTrg<n>

1

: SOURce

RESet

1

SOURc

I

:FREQuency

[:CW

I

FIXed]

: tion

[ : SHAPel

(numeric-value)

:TYPE

[ : STATe]

: PULSe

:WIDTh

: DELay

: DOUBle

[ STAT^]

: POLarity

: PERiod

:TRANsition

(numeric-value)

<numeric-value)

(numeric-value>

<Boolean-data> (QEE)

<NORHal

]

COMPlement

[ LEADing]

(Boolean-data>

<numeric-value)

(numeric-value)

(~oolean-data) : AUTO

: SUMBus

[ STATeI

[ :LEVell

:HIGH

[ :AMPLitude:

(numeric-value>

(numeric-value)

(numeric-value>

(numeric-value)

I

INVerted)

NOTES

--

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed1

Confirmed

Not SCPI Approved

Not SCPI Approved

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Not SCPf Approved

Confirmed

Confirmed

Conf rmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Conf rmed

Confirmed

Not SCPI Approved

Not SCPI Approved

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

KEYWORD

Table E-1. Model 1391 SCPl Command Syntax (Continued)

PARAMETER FORM

[SOURce] ( C o n t i n u e d )

: PULM

: A M P L i t u d e

NOTES

Confirmed

Confirmed

Not SCPl Approved

STATus

:OPERation

: C O N D i r i o n ?

: ENABle

[ 7

:QUEStionable

:CONDition?

:PRESet

(numeric-value)

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

SYSTern

: T I M E

: VERSion?

: LAh'Guage

:CIIL

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed *

Confirmed *

T R I G g e r

: G A T E

[ STAT^]

:NODE

: MODE

: SLOPe

: SOURce

<Boolean-data)

(PEE)

< S S .

[ EXTWidth)

< M A S T e r ]

->

< m i t i v e

I

NEGative)

< J N T e r n d

I

BUS

I

EXTernal

I

TOFF>

1

T T L T r g < n >

(numeric-value)

Contirmed

Confirmed

Confirmed

Not SCPl Approved

Not SCPl Approved

Not SCPl Approved

Not SCPl Approved

Confirmed

Confirmed

Confirmed

Confirmed

Confirmed

Conlirmed

Confirmed

Confirmed

Confirmed

'

TEST

[ :ALL]

Confirmed

Confirmed

I . Devicc d c p c n d c n ~

2. Incomplete implementation; at lcast onc paramctcr not supported pcr SCPI specification.

3 . STATus Subsystcm commands opcratc pcr the specification, but rhc physical Status Registers are nor imple-

4. mented in the hardware,

"System Language" specifics device dcpcndenr parameter character data; implemcnrcd CIIL a s keyword.

INFOWIAT[OS

E-3

E-4

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