Artesyn ATCA-7360 Installation And Use Manual

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ATCA-7360

Installation and Use

P/N: 6806800J07S

May 2016

Trademarks

Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of

Artesyn Embedded Technologies, Inc. All other names and logos referred to are trade names, trademarks, or registered trademarks of their respective owners. © 2016 Artesyn Embedded Technologies, Inc. All rights reserved. For full legal terms and conditions, please visit www.artesyn.com/legal .

Notice

While reasonable efforts have been made to assure the accuracy of this document, Artesyn assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Artesyn reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Artesyn to notify any person of such revision or changes.

Electronic versions of this material may be read online, downloaded for personal use, or referenced in another document as a URL to an Artesyn website. The text itself may not be published commercially in print or electronic form, edited, translated, or otherwise altered without the permission of Artesyn.

It is possible that this publication may contain reference to or information about Artesyn products (machines and programs), programming, or services that are not available in your country. Such references or information must not be construed to mean that

Artesyn intends to announce such Artesyn products, programming, or services in your country.

Limited and Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Artesyn.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in

Technical Data clause at DFARS 252.227-7013 (Nov. 1995) and of the Rights in Noncommercial Computer Software and

Documentation clause at DFARS 252.227-7014 (Jun. 1995).

Contact Address

Artesyn Embedded Technologies

Marketing Communications

2900 S. Diablo Way, Suite 190

Tempe, Arizona 85282

Artesyn Embedded Technologies

Lilienthalstr. 17-19

85579 Neubiberg/Munich

Germany

About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Safety Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Sicherheitshinweise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.2 Standard Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

1.3 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

1.5 Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2 Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.1 Unpacking and Inspecting the Blade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.2 Environmental and Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.2.1 Environmental Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.2.2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2.3 Blade Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2.4 Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

2.5 Installing Blade Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

2.5.1 DIMM Memory Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

2.5.2 PMEM and SATA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2.5.3 USB 2.0 Flash Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

2.6 Installing and Removing the Blade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

2.6.1 Installing the Blade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

2.6.2 Removing the Blade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3 Controls, Indicators, and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.1 Mechanical Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.2 Faceplate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.2.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.2.2 Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

ATCA-7360 Installation and Use (6806800J07S) 3

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3.2.3 Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.2.3.1 Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.2.3.2 Serial Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.2.3.3 USB Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.3 On-board Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.3.1 PMEM/SFMEM Module Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.3.2 USB Flash Module Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.4 AdvancedTCA Backplane Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4 BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.2 Accessing the Blade Using the Serial Console Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.2.1 Requirements for Serial Console Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.2.2 Default Access Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.2.3 Connecting to the Blade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.3 Changing Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.4 Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.4.1 Supported Boot Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.4.2 Selecting The Boot Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.4.3 By Boot Selection Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

4.4.4 iSCSI Setup for Base and Fabric Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4.4.4.1 ISCSI Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.4.4.2 iSCSI Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

4.4.4.3 iSCSI Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4.4.4.4 iSCSI Challenge Handshake Authentication Protocol (CHAP) Configuration 98

4.5 BIOS Setup Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.5.1 Main. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.5.2 Advanced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.5.2.1 Advanced -> CPU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.5.2.2 Advanced -> Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4.5.2.3 Advanced -> Chipset - North Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

4.5.2.4 Advanced -> Chipset - South Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

4.5.2.5 Advanced -> SATA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4.5.2.6 Advanced -> USB Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4.5.2.7 Advanced -> Super IO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4 ATCA-7360 Installation and Use (6806800J07S)

Contents

4.5.2.8 Advanced -> Serial Port Console Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . 107

4.5.2.9 Advanced -> UEFI Network Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.5.2.10 Advanced -> Runtime Error Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.5.2.11 Advanced -> SMBIOS Event Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

4.5.2.12 Advanced -> Local IPMI System Event Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

4.5.2.13 Advanced -> WHEA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

4.5.3 IPMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

4.5.3.1 IPMI -> IPMI Watchdog Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

4.5.3.2 IPMI -> System Event Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4.5.4 iSCSI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4.5.5 Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

4.5.5.1 Boot -> Option ROM Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

4.5.6 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

4.5.7 Save & Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

4.6 CPU Performance Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

4.7 Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

4.7.1 Independent Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.7.2 Spare Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.7.3 Mirrored Channel Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.7.4 Lockstep Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

4.8 Restoring BIOS Default Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

4.9 Shelf Slot Power Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

4.10 LED Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

4.11 Upgrading the BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

4.12 BIOS Error Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

4.12.1 Runtime Error Logging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

4.12.2 Error Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

4.12.3 IPMI Error Logging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

4.12.4 SMBIOS Error Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

4.12.4.1 Single-bit ECC Memory Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

4.12.4.2 Multi-bit ECC Memory Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

4.12.4.3 POST Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

4.12.4.4 PCI Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

4.12.4.5 PCI System Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

4.12.4.6 CPU Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

4.12.4.7 Correctable Memory Log Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

ATCA-7360 Installation and Use (6806800J07S) 5

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4.12.4.8 Log Area Reset/Cleared . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

4.12.4.9 System Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

4.12.4.10OEM Event EFI Status Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

4.13 BIOS Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

4.13.1 Status Code Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

4.13.2 Standard Status Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

5.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

5.2 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

5.3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

5.3.1 Persistent memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

5.4 Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

5.5 I/O Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

5.6 Firmware Flashes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

5.7 Ethernet Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

5.8 Storage Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

5.9 Embedded Flash Disk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

5.9.1 SATA Embedded Flash Solid State Disc (SSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

5.10 BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

5.11 IPMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

5.12 Serial Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

5.13 Serial Over LAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

5.14 Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

5.15 Front Board Faceplate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

5.16 USB 2.0 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

5.17 SMBus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

5.18 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

6 Maps and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

6.1 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

6.2 PCI Express Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

6.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

6.3.1 Register Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

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6.3.1.1 LPC Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

6.3.1.2 SPI Register Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

6.3.2 POST Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

6.3.3 Super IO Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

6.3.3.1 Entering the Configuration State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

6.3.3.2 Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

6.3.3.3 Super IO Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

6.3.4 UART1 and UART2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

6.3.4.1 UART Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

6.3.4.2 UART Registers DLAB=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

6.3.4.3 Programmable Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

6.4 FPGA Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

6.4.1 LPC I/O Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

6.4.2 IPMC SPI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

6.4.3 Module Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

6.4.4 Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

6.4.5 Serial Redirection Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

6.4.6 Serial Over LAN (SOL) Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

6.4.7 Serial Line Routing Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

6.4.8 IPMC Power Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

6.4.9 SPD PROM MUX Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

6.4.10 Reset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

6.4.10.1 BIOS Reset Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

6.4.10.2 Reset Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

6.4.10.3 BIOS IPMC Watchdog Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

6.4.10.4 BIOS Push Button Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

6.4.10.5 OS Reset Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

6.4.10.6 OS IPMC Watchdog Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

6.4.10.7 IPMC Watchdog Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

6.4.10.8 IPMC Reset Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

6.4.11 RTM SPI Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

6.4.12 Interrupt Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

6.4.12.1 RTM Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

6.4.12.2 External Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

6.4.12.3 Processor Hot Status/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

6.4.12.4 Telecom Status/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

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6.4.12.5 Interrupt Mask and Map Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

6.4.13 Flash Status and Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

6.4.14 BIOS Boot Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

6.4.15 SFMEM Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

6.4.16 Update Channel Equalization Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

6.4.17 IPMC E-Keying Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

6.4.18 IPMC E-Keying Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

6.4.19 IPMC GPIO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

6.4.20 LED Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

6.4.21 NMI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

6.4.22 Telecom Clock Supervision Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

6.4.22.1 Telecom Clocking Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

6.4.22.2 Telecom Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

6.4.23 Miscellaneous Status/Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

6.4.24 Scratch Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

7 Serial Over LAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

7.2 Installing the ipmitool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

7.3 Configure SOL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

7.3.1 Using Standard IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

7.3.2 Using ipmitool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

7.4 Establishing a SOL Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

8 Supported IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

8.1 Standard IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

8.1.1 Global IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

8.1.2 System Interface Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

8.1.3 Watchdog Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

8.1.4 SEL Device Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

8.1.5 FRU Inventory Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

8.1.6 Sensor Device Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

8.1.7 Chassis Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

8.1.7.1 System Boot Options Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

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8.1.8 LAN Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

8.2 PICMG 3.0 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

8.2.1 Set/Get Power Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

8.3 Artesyn Specific Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

8.3.1 Serial Output Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

8.3.1.1 Set Serial Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

8.3.1.2 Get Serial Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

8.4 Pigeon Point Specific Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

8.4.1 Get Status Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

8.4.2 Get Serial Interface Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

8.4.3 Set Serial Interface Properties Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

8.4.4 Get Debug Level Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

8.4.5 Set Debug Level Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

8.4.6 Get Hardware Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

8.4.7 Set Hardware Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

8.4.8 Get Handle Switch Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

8.4.9 Set Handle Switch Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

8.4.10 Get Payload Communication Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

8.4.11 Set Payload Communication Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

8.4.12 Enable Payload Control Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

8.4.13 Disable Payload Control Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

8.4.14 Reset IPMC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

8.4.15 Hang IPMC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

8.4.16 Graceful Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

8.4.17 Get Payload Shutdown Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

8.4.18 Set Payload Shutdown Time-Out Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

8.4.19 Get Module State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

8.4.20 Enable Module Site Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

8.4.21 Disable Module Site Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

8.4.22 Reset Carrier SDR Repository Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

9 FRU Information and Sensor Data Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

9.1 FRU Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

9.2 MAC Address Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

9.3 E-Keying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

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9.4 Power Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

9.5 Sensor Data Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

10 Firmware Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

10.1 HPM.1 Firmware Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

10.1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

10.1.2 Installing the Ipmitool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

10.1.2.1 Update Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

10.1.3 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

10.1.3.1 KCS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

10.1.3.2 IPMB-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

10.1.3.3 LAN over Ethernet (BASE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

10.2 IPMC Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

10.3 BIOS/FPGA Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

10.4 Upgrade Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

A Replacing the Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

A.1 Replacing the Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

B.1 Artesyn Embedded Technologies - Embedded Computing Documentation . . . . . . . . . . . . . . . 285

B.2 Manufacturers’ Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

10 ATCA-7360 Installation and Use (6806800J07S)

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Standard Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Blade Variants - Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Blade Accessories - Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Critical Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Faceplate LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

BIOS Key Codes for Terminal Emulation Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Ethernet port mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Select iSCSI Boot priority hot keys: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Main Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

CPU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Chipset - North Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Chipset - North Bridge -> Intel (R) VT for Directed I/O Configuration . . . . . . . . . . . . . . . . . 103

Chipset - North Bridge -> IOH Thermal Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Chipset - South Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Chipset - South Bridge -> USB Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Advanced -> SATA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Advanced -> USB Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Super IO Configuration -> Serial Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Advanced -> Serial Port Console Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Serial Port Console Redirection -> Console Redirection Settings . . . . . . . . . . . . . . . . . . . . . 107

Advanced -> UEFI Network Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Advanced -> Runtime Error Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

SMBIOS Event Log -> SMBIOS Event Log Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Advanced -> Local IPMI System Event Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Advanced -> WHEA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

IPMI -> IPMI Watchdog Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

IPMI -> System Event Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

iSCSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Boot -> Option ROM Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Save & Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

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Logged Error Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

BIOS Supported IPMI Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Single-bit ECC Memory Error event format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

Memory Information Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

Multi-bit ECC Memory Error Event Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

Memory Information Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

POST Error Event Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Result First DWORD supported POST Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Result Second DWORD supported POST Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

PCI Parity Error Event Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

PCI Information Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Multi-bit ECC Memory Error Event Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Memory Information Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

CPU Failure Event Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Correctable Memory Log Disabled Event Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

Memory Information Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

Log Area Reset/Cleared Event Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

System Boot Event Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Status Code Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Status Code Value Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Class Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

SubClass EFI_COMPUTING_UNIT_CHIPSET (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

SubClass EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR (02h) (IPMI) . . . . . . . . . . . . . .133

Status Code Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

SEC Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

PEI Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

DXE Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Ethernet Controller Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

SMBus Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Non-APIC (PIC mode / 8259 Mode) Interrupt Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

APIC Mode Interrupt Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

PCIexpress Port mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

Register Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

Register Access Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

LPC I/O Register Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

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IPMC SPI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

POST Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Super IO Configuration Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Super IO Configuration Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Global Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Super IO Logical Device Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Super IO Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Super IO Device Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Super IO LPC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Global Super IO SERIRQ and Pre-divide Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Logical Device Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Logical Device Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Logical Device Base IO Address MSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Logical Device Base IO Address LSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Logical Device Common Decode Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Logical Device Primary Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Logical Device 0x74 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Logical Device 0x75 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Logical Device 0xF0 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

UART Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Receiver Buffer Register (RBR) if DLAB=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Transmitter Holding Register (THR) if DLAB=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Interrupt Enable Register (IER), if DLAB=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

UART Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Interrupt Identification Register (IIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

FIFO Control Register (FCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Line Control Register (LCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Modem Control Register (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Line Control Register (LCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Modem Status Register (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Scratch Register (SCR)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Divisor Latch LSB Register (DLL), if DLAB=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Divisor Latch MSB Register (DLM), if DLAB=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

FPGA Register Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Module Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

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Serial Redirection Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

Serial over LAN Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

Serial Line Routing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

IPMC Power Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

SPD PROM MUX Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

BIOS Reset Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

Reset Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

BIOS IPMC Watchdog Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

BIOS Push Button Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Reset Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

OS IPMC Watchdog Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

IPMC Watchdog Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

IPMC Reset Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

RTM SPI Address/Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

RTM SPI Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

RTM SPI Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

External Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

Processor Hot Status/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

Telecom Status/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

Address Map of Interrupt Mask and Map Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

Interrupt Mask and Map Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

Default Boot SPI Flash Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

Recovery Boot SPI Flash Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

BIOS Boot Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

SFMEM Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

Update Channel Equalization Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

IPMC E-Keying Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

IPMC E-Keying Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

IPMC GPIO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

LED Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

NMI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Telecom Backplane Clocking Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Telecom Backplane Clocking Latch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Telecom CH1_CLK1A clock period MSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Telecom CH1_CLK1B clock period MSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

ATCA-7360 Installation and Use (6806800J07S)

List of Tables

Telecom CH1_CLK1B clock period LSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Telecom CH1_CLK1A clock period LSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Telecom Timer MSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Telecom Timer LSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

CPLD Version and Spare Signal Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

LPC Scratch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

IPMC Scratch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

SOL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Supported Global IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Supported System Interface Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Supported Watchdog Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Supported SEL Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Supported FRU Inventory Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Supported Sensor Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Supported Chassis Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Configurable System Boot Option Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

System Boot Options Parameter #96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

System Boot Options Parameter #97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

System Boot Options Parameter #98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

System Boot Options - Parameter #100 - Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

System Boot Options Parameter #100 - SET Command Usage . . . . . . . . . . . . . . . . . . . . . . 227

System Boot Options Parameter #100 - GET Command Usage . . . . . . . . . . . . . . . . . . . . . . 228

System Boot Options Parameter #100 - Supported Parameters . . . . . . . . . . . . . . . . . . . . . 229

boot_order Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Supported LAN Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Supported PICMG 3.0 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Serial Output Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Request Data of Set Serial Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Response Data of Set Serial Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Request Data of Get Serial Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Response Data of Get Serial Output Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Pigeon Point Extension Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

IPMC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Get Status Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Get Serial Interface Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Set Serial Interface Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

ATCA-7360 Installation and Use (6806800J07S) 15

List of Tables

Get Debug Level Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

Set Debug Level Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

Get Hardware Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

Set Hardware Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

Get Handle Switch Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247

Set Handle Switch Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

Get Payload Communication Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

Set Payload Communication Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249

Enable Payload Control Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

Disable Payload Control Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

Reset IPMC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

Hang IPMC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

Graceful Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

Get Payload Shutdown Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

Set Payload Shutdown Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

Get Module State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

Enable Module Site Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256

Disable Module Site Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256

Reset Carrier SDR Repository Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

FRU Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

Artesyn MAC Addresses Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260

Artesyn MAC Address Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261

Interface Type Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261

Contents of the Blade Point-to-Point Connectivity Record Area . . . . . . . . . . . . . . . . . . . . . .262

Power Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

IPMI Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

Sensor Data Records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268

HPM Upgrade Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280

Artesyn Embedded Technologies - Embedded Computing Publications . . . . . . . . . . . . . .285

Manufacturer’s Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286

16 ATCA-7360 Installation and Use (6806800J07S)

List of Figures

Serial Number Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Location of Critical Temperature Spots (Blade Top Side) . . . . . . . . . . . . . . . . . . . . . . 49

ATCA-7360 Blade Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Mechanical Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Faceplate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Location of Faceplate LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Location of Faceplate Reset Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Location of Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Ethernet Interface Connectors Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Location of Serial Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Serial Interface Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Location of USB Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

USB Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Location of PMEM/SFMEM Module Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

PMEM/SATA Module Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Location of USB Flash Module Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

USB Flash Module Connector Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Location of AdvancedTCA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

P10 Backplane Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

P20 Backplane Connector Pinout - Rows A to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

P20 Backplane Connector Pinout - Rows E to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

P23 Backplane Connector Pinout - Rows A to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

P23 Backplane Connector Pinout - Rows E to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

P30 Backplane Connector Pinout - Rows A to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

P30 Backplane Connector Pinout - Rows E to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

P32 Backplane Connector Pinout - Rows A to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

P32 Backplane Connector Pinout - Rows E to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Save and Exit Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Option ROM Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

iSCSI Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

iSCSI Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

iSCSI Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

iSCSI CHAP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Interrupt Structure on ATCA-7360 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

ATCA-7360 Installation and Use (6806800J07S) 17

List of Figures

IOH36D PCIe Port mapping on ATCA-7360 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

SOL Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

System Boot Options Parameter #100 - Information Flow Overview . . . . . . . . . . 225

Location of Temperature Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

IPMC Component Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

SPI Busses Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Location of On-board Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

18 ATCA-7360 Installation and Use (6806800J07S)

About this Manual

Overview of Contents

This Reference Guide is intended for users qualified in electronics or electrical engineering.

Users must have a working understanding of Peripheral Component Interconnect (PCI),

AdvancedTCA®, and telecommunications.

The manual contains the following chapters and appendices:



About this Manual on page 19 lists all conventions and abbreviations used in this manual

and outlines the revision history.

Safety Notes on page 27 lists safety notes applicable to the blade.



Sicherheitshinweise on page 31 provides the German translation of the safety notes section.

Introduction on page 37 describes the main features of the blade.



Installation on page 45

outlines the installation requirements, hardware accessories, switch settings, installation and removal procedures.

Controls, Indicators, and Connectors on page 67 describes external interfaces of the blade.

This includes connectors and LEDs.



BIOS on page 87

describes the features and setup of BIOS.

Functional Description on page 141 describes in more detail functional blocks of the blade.

This includes a block diagram, description of the main components used and so on.

Maps and Registers on page 151 provides information on the blade’s maps and registers.

Serial Over LAN on page 211

provides information on how to establish a serial-over LAN session on your blade.

Supported IPMI Commands on page 217

lists all supported IPMI commands.

FRU Information and Sensor Data Records on page 259 provides information on the blade’s

FRU info and sensor data.

Firmware Upgrade on page 275 provides information on how to upgrade the firmware

components.

Replacing the Battery on page 281

provides the battery exchange procedures.

documentation.

ATCA-7360 Installation and Use (6806800J07S) 19

About this Manual

Abbreviations

This document uses the following abbreviations:

FIFO

FPGA

FRU

HDD

IDE

IPMB

IPMC

IPMI

LPC

MAC

NEBS

DDR

DIMM

DMA

DPLL

DRAM

ECC

EMC

EMV

Abbreviation

ANSI

APIC

ATA

ATCA

BIOS

CMOS

Definition

American National Standards Institute

Advanced Programmable Interrupt Controller

Advanced Technology Attachment

Advanced Telecommunications Computing Architecture

Basic Input/Output System

Complementary Metal Oxide Semiconductor

Double Data Rate

Dual Inline Memory Module

Direct Memory Access

Digital Phase Locked Loop

Dynamic Random Access Memory

Error-Correction Code

Electromagnetic Compatibility

Elektromagnetische Vertraeglichkeit

First In First Out

Field-Programmable Gate Array

Field Replaceable Unit

Hard Disk Drive

Integrated Device Electronics

Intelligent Platform Management Bus

Intelligent Platform Management Controller

Intelligent Platform Management Interface

Low Pin Count

Media Access Control

Network Equipment Building System

20 ATCA-7360 Installation and Use (6806800J07S)

About this Manual

SMI

SOL

SPD

SPI

SCSI

SDR

SDRAM

SELV

SRAM

SROM

VGA

POST

PROM

RHEL

RTC

RTM

RoHS

SAS

SATA

Abbreviation

NVRAM

OEM

PCI

PEM

PICMG

PMC

ATCA-7360 Installation and Use (6806800J07S)

Definition

Nonvolatile Random Access Memory

Original Equipment Manufacturer

Peripheral Component Interconnect

Power Entry Module

PCI Industrial Computer Manufacturers Group

PCI Mezzanine Card

Power-On Self-Test

Programmable Read-Only Memory

Red Hat Enterprise Linux

Real Time Clock

Rear Transition Module

Restriction of the use of Certain Hazardous Substances

Serial Attached SCSI

Serial ATA

Small Computer System Interface

Sensor Data Record

Synchronous Dynamic Random Access Memory

Safety Extra Low Voltages

Serial Management Interface

Serial-over-LAN

Serial Presence Detect

Serial Peripheral Interface

Static Random Access Memory

Serial Read-Only Memory

Video Graphics Array

About this Manual

Conventions

The following table describes the conventions used throughout this manual.

Notation

0x00000000

0b0000 bold

Screen

Courier + Bold

...

Reference

File > Exit

<text>

[text]

Description

Typical notation for hexadecimal numbers (digits are

0 through F), for example used for addresses and offsets

Same for binary numbers (digits are 0 and 1)

Used to emphasize a word

Used for on-screen output and code related elements or commands in body text

Used to characterize user input and to separate it from system output

Used for references and for table and figure descriptions

Notation for selecting a submenu

Notation for variables and keys

Notation for software buttons to click on the screen and parameter description

Repeated item for example node 1, node 2, ..., node

Omission of information from example/command that is not necessary at the time being

Ranges, for example: 0..4 means one of the integers

0,1,2,3, and 4 (used in registers)

Logical OR

22 ATCA-7360 Installation and Use (6806800J07S)

Notation

About this Manual

Description

Indicates a hazardous situation which, if not avoided, could result in death or serious injury

Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury

Indicates a property damage message

No danger encountered. Pay attention to important information

ATCA-7360 Installation and Use (6806800J07S) 23

About this Manual

Summary of Changes

Part Number Publication Date Description

6806800J07S

6806800J07R

May 2016 Removed Declaration of Conformity .

September 2015 Updated GR-1089 related information in the sections

Standard Compliances on page 38 ,

Installation on page 28 and

Installation on page 32 .

6806800J07P June 2015

6806800J07N February 2015

6806800J07M

6806800J07L

May 2014

February 2014

Updated the section

Environmental Requirements on page 46 .

Updated the

Figure "Location of Critical Temperature Spots

(Blade Top Side)" on page 49 and PWR Entry Status

information in Table "Sensor Data Records" on page 268

Rebranded to Artesyn.

Updated

Table "Faceplate LEDs" on page 70 and

Table "Sensor

Data Records" on page 268 .

Updated

Table "Get Handle Switch Command" on page 247

and Table "Set Handle Switch Command" on page 248 .

Updated

Table "Environmental Requirements" on page 47 .

6806800J07K

6806800J07J

April 2012

March 2012

Updated

Table 2-3

and a note in

DIMM Memory Modules on page 56

. Updated Table 6-71 ,

Using ipmitool on page 213 , and

Table 8-16

Added a Notice in Installation on page 28 and

Installation on page 32 .Updated

Table 2-4 .

Updated

EMC on page 27 and

EMV on page 32 .

6806800J07I September 2011 Updated

Serial Interface Connector on page 73 .

Updated

Figure "Location of AdvancedTCA Connectors" on page 80 .

Updated

Chapter 3, USB Connectors, on page 74 .

Updated

Chapter 4, BIOS, on page 87

Updated

Sensor Data Records on page 264 .

6806800J07H October 2010  Added

Sensor Data Records on page 264 .

 Updated

Power Requirements on page 50 .

6806800J07G

6806800J07F

6806800J07E

August 2010 Updated

Appendix A, Replacing the Battery

Added

Chapter 10, Firmware Upgrade, on page 275 .

January 2010 GA version

November 2009 Updated EA version

24 ATCA-7360 Installation and Use (6806800J07S)

About this Manual

Part Number Publication Date Description

6806800J07D November 2009 EA version

6806800J07C November 2009 Updated

Sensor Data Records on page 264

Added the following:

Chapter 4, BIOS, on page 87

Chapter 5,

Functional Description, on page 141

, Chapter 6, Maps and

Registers, on page 151 , and

Appendix A, Replacing the Battery .

Updated board illustrations, showing different components

Added weight of blade in Mechanical Data on page 39

Added

Figure "Serial Number Location" on page 42

Added

Table "Contents of the Blade Point-to-Point

Connectivity Record Area" on page 262

Added Steady state Power Draw Levels, Watt in Table "Power

Configuration" on page 264

Added

Figure A-1 on page 281

Moved location of Safety Notes on page 27

and

Sicherheitshinweise on page 31

Changed faceplate labels: "OK" to "IS" and "ATN" to "ATTN"

Added

Figure "P10 Backplane Connector Pinout" on page 81 ,

Figure "P20 Backplane Connector Pinout - Rows A to D" on page 82

Figure "P20 Backplane Connector Pinout - Rows E to

H" on page 83 , Figure "P23 Backplane Connector Pinout -

Rows A to D" on page 83

, Figure "P23 Backplane Connector

Pinout - Rows E to H" on page 84 ,

Figure "P30 Backplane

Connector Pinout - Rows A to D" on page 85 , Figure "P30

Backplane Connector Pinout - Rows E to H" on page 85

, Figure

"P32 Backplane Connector Pinout - Rows A to D" on page 86 ,

Figure "P32 Backplane Connector Pinout - Rows E to H" on page 86

6806800J07B June 2009 Updated

Sensor Data Records on page 264

6806800J07A June 2009 First version

ATCA-7360 Installation and Use (6806800J07S) 25

About this Manual

26 ATCA-7360 Installation and Use (6806800J07S)

Safety Notes

This section provides warnings that precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed during all phases of operation, service, and repair of this equipment. You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment.

Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment.

Artesyn intends to provide all necessary information to install and handle the product in this manual. Because of the complexity of this product and its various uses, we do not guarantee that the given information is complete. If you need additional information, ask your Artesyn representative.

The product has been designed to meet the standard industrial safety requirements. It must not be used except in its specific area of office telecommunication industry and industrial control.

Only personnel trained by Artesyn or persons qualified in electronics or electrical engineering are authorized to install, remove or maintain the product.

The information given in this manual is meant to complete the knowledge of a specialist and must not be used as replacement for qualified personnel.

Keep away from live circuits inside the equipment. Operating personnel must not remove equipment covers. Only factory authorized service personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment.

Do not install substitute parts or perform any unauthorized modification of the equipment or the warranty may be voided. Contact your local Artesyn representative for service and repair to make sure that all safety features are maintained.

EMC

The blade has been tested in a standard Artesyn system and found to comply with the limits for a Class A digital device in this system, pursuant to part 15 of the FCC Rules, EN 55022 Class

A respectively. These limits are designed to provide reasonable protection against harmful interference when the system is operated in a commercial environment.

ATCA-7360 Installation and Use (6806800J07S) 27

Safety Notes

This is a Class A product based on the standard of the Voluntary Control Council for

Interference by Information Technology Interference (VCCI). If this equipment is used in a domestic environment, radio disturbance may arise. When such trouble occurs, the user may be required to take corrective actions.

To ensure EMC protection use only shielded cables when connecting peripherals to assure that appropriate radio frequency emissions compliance is maintained. Installed blades must have faceplate's installed and all vacant slots in the shelf must be covered.

The blade generates and uses radio frequency energy and, if not installed properly and used in accordance with this guide, may cause harmful interference to radio communications.

Operating the system in a residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at his own expense.

Installation

Damage of Circuits

Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life.

Before touching the blade or electronic components, make sure that you are working in an

ESD-safe environment.

Removing the blade with the blue LED still blinking causes data loss.

Wait until the blue LED is permanently illuminated, before removing the blade.

Damage of Blade and Additional Devices and Modules

Incorrect installation of additional devices or modules may damage the blade or the additional devices or modules.

Before installing or removing an additional device or module, read the respective documentation

28 ATCA-7360 Installation and Use (6806800J07S)

Safety Notes

WARNING: The intra-building port (s) of the equipment or subassembly is suitable for connection to intra-building or unexposed wiring or cabling only. The intra-building port (s) of the equipment or subassembly MUST NOT be metallically connected to interfaces that connect to the outside plant (OSP) or its wiring. These interfaces are designed for use as intrabuilding interfaces only (Type 2 or Type 4 ports as described in GR-1089) and require isolation from the exposed OSP cabling. The addition of primary protectors is not sufficient protection in order to connect these interfaces metallically to OSP wiring.

The intra-building port(s) of the equipment or subassembly must use shielded intra-building cabling/wiring that is grounded at both ends.

Operation

Blade surface

High humidity and condensation on the blade surface causes short circuits.

Do not operate the blade outside the specified environmental limits. Make sure the blade is completely dry and there is no moisture on any surface before applying power.

Blade Overheating and Blade Damage

Operating the blade without forced air cooling may lead to blade overheating and thus blade damage.

When operating the blade, make sure that forced air cooling is available in the shelf.

When operating the blade in areas of electromagnetic radiation ensure that the blade is bolted on the system and the system is shielded by enclosure.

Injuries or Short Circuits

Blade or power supply

In case the O-Ring diodes of the blade fail, the blade may trigger a short circuit between input line A and input line B so that line A remains powered even if it is disconnected from the power supply circuit (and vice versa).

To avoid damage or injuries, always check that there is no more voltage on the line that has been disconnected before continuing your work.

ATCA-7360 Installation and Use (6806800J07S) 29

Safety Notes

Switch Settings

Switches marked as 'reserved' might carry production-related functions and can cause the blade to malfunction if their setting is changed.

Therefore, do not change settings of switches marked as 'reserved'. The setting of switches which are not marked as 'reserved' has to be checked and changed before blade installation.

Battery

Setting/resetting the switches during operation can cause blade damage.

Therefore, check and change switch settings before you install the blade.

Wrong battery installation may result in hazardous explosion and blade damage.

Therefore, always use the same type of Lithium battery as is installed and make sure the battery is installed as described in this manual.

Environment

Always dispose of used blades, system components and RTMs according to your country’s legislation and manufacturer’s instructions.

30 ATCA-7360 Installation and Use (6806800J07S)

Sicherheitshinweise

Dieses Kapitel enthält Hinweise, die potentiell gefährlichen Prozeduren innerhalb dieses

Handbuchs vorrangestellt sind. Beachten Sie unbedingt in allen Phasen des Betriebs, der

Wartung und der Reparatur des Systems die Anweisungen, die diesen Hinweisen enthalten sind. Sie sollten außerdem alle anderen Vorsichtsmaßnahmen treffen, die für den Betrieb des

Produktes innerhalb Ihrer Betriebsumgebung notwendig sind. Wenn Sie diese

Vorsichtsmaßnahmen oder Sicherheitshinweise, die an anderer Stelle diese Handbuchs enthalten sind, nicht beachten, kann das Verletzungen oder Schäden am Produkt zur Folge haben.

Artesyn ist darauf bedacht, alle notwendigen Informationen zum Einbau und zum Umgang mit dem Produkt in diesem Handbuch bereit zu stellen. Da es sich jedoch um ein komplexes

Produkt mit vielfältigen Einsatzmöglichkeiten handelt, können wir die Vollständigkeit der im

Handbuch enthaltenen Informationen nicht garantieren. Falls Sie weitere Informationen benötigen sollten, wenden Sie sich bitte an die für Sie zuständige Geschäftsstelle von Artesyn.

Das System erfüllt die für die Industrie geforderten Sicherheitsvorschriften und darf ausschließlich für Anwendungen in der Telekommunikationsindustrie und im Zusammenhang mit Industriesteuerungen verwendet werden.

Einbau, Wartung und Betrieb dürfen nur von durch Artesyn ausgebildetem oder im Bereich

Elektronik oder Elektrotechnik qualifiziertem Personal durchgeführt werden. Die in diesem

Handbuch enthaltenen Informationen dienen ausschließlich dazu, das Wissen von

Fachpersonal zu ergänzen, können dieses jedoch nicht ersetzen.

Halten Sie sich von stromführenden Leitungen innerhalb des Produktes fern. Entfernen Sie auf keinen Fall Abdeckungen am Produkt. Nur werksseitig zugelassenes Wartungspersonal oder anderweitig qualifiziertes Wartungspersonal darf Abdeckungen entfernen, um Komponenten zu ersetzen oder andere Anpassungen vorzunehmen.

Installieren Sie keine Ersatzteile oder führen Sie keine unerlaubten Veränderungen am Produkt durch, sonst verfällt die Garantie. Wenden Sie sich für Wartung oder Reparatur bitte an die für

Sie zuständige Geschäftsstelle von Artesyn. So stellen Sie sicher, dass alle sicherheitsrelevanten Aspekte beachtet werden.

ATCA-7360 Installation and Use (6806800J07S) 31

Sicherheitshinweise

EMV

Das Blade wurde in einem Artesyn Standardsystem getestet. Es erfüllt die für digitale Geräte der Klasse A gültigen Grenzwerte in einem solchen System gemäß den FCC-Richtlinien

Abschnitt 15 bzw. EN 55022 Klasse A. Diese Grenzwerte sollen einen angemessenen Schutz vor Störstrahlung beim Betrieb des Blades in Gewerbe- sowie Industriegebieten gewährleisten.

Das Blade arbeitet im Hochfrequenzbereich und erzeugt Störstrahlung. Bei unsachgemäßem

Einbau und anderem als in diesem Handbuch beschriebenen Betrieb können Störungen im

Hochfrequenzbereich auftreten.

Benutzen Sie zum Anschließen von Peripheriegeräten ausschließlich abgeschirmte Kabel. So stellen Sie sicher, dass ausreichend Schutz vor Störstrahlung vorhanden ist. Die Blades müssen mit der Frontblende installiert und alle freien Steckplätze müssen mit Blindblenden abgedeckt sein.

Warnung! Dies ist eine Einrichtung der Klasse A. Diese Einrichtung kann im Wohnbereich

Funkstörungen verursachen. In diesem Fall kann vom Betreiber verlangt werden, angemessene Maßnahmen durchzuführen.

Installation

Beschädigung von Schaltkreisen

Elektrostatische Entladung und unsachgemäßer Ein- und Ausbau von Blades kann Schaltkreise beschädigen oder ihre Lebensdauer verkürzen.

Bevor Sie Blades oder elektronische Komponenten berühren, vergewissern Sie sich, daß Sie in einem ESD-geschützten Bereich arbeiten.

Datenverlust

Wenn Sie das Blade aus dem Shelf herausziehen, und die blaue LED blinkt noch, gehen Daten verloren.

Warten Sie bis die blaue LED durchgehend leuchtet, bevor Sie das Blade herausziehen.

32 ATCA-7360 Installation and Use (6806800J07S)

Sicherheitshinweise

Beschädigung des Blades und von Zusatzmodulen

Fehlerhafte Installation von Zusatzmodulen, kann zur Beschädigung des Blades und der

Zusatzmodule führen.

Lesen Sie daher vor der Installation von Zusatzmodulen die zugehörige Dokumentation.

Beschädigung des Systems

Warnung: Die intra-Gebäude Port (s) des Geräts oder Baugruppe ist für den Anschluss an den inner Gebäude oder unbelichteten Verdrahtung oder Verkabelung nur. Die intra-Gebäude

Port(s) des Geräts oder Baugruppe muss nicht metallisch mit Schnittstellen, die an der

Außenanlage (OSP) oder dessen Verkabelung anschließen angeschlossen werden. Diese

Schnittstellen sind für die Verwendung als intra Gebäude Schnittstellen nur entworfen, (Typ 2 oder Typ 4 Ports wie in GR-1089 beschrieben) und erfordern Isolierung von der freiliegenden

OSP-Verkabelung. Die Zugabe von primären Schutz nicht ausreichenden Schutz, um diese

Schnittstellen metallisch mit OSP Verdrahtung verbinden.

Die intra-Gebäude Port (s) des Gerätes oder einer Unterbaugruppe müssen abgeschirmte innerGebäudeVerkabelung / Verdrahtung, die an beiden Enden geerdet ist zu verwenden.

Betrieb

Beschädigung des Blades

Hohe Luftfeuchtigkeit und Kondensat auf der Oberfläche des Blades können zu Kurzschlüssen führen.

Betreiben Sie das Blade nur innerhalb der angegebenen Grenzwerte für die relative

Luftfeuchtigkeit und Temperatur. Stellen Sie vor dem Einschalten des Stroms sicher, dass sich auf dem Blade kein Kondensat befindet.

Überhitzung und Beschädigung des Blades

Betreiben Sie das Blade ohne Zwangsbelüftung, kann das Blade überhitzt und schließlich beschädigt werden.

Bevor Sie das Blade betreiben, müssen Sie sicher stellen, dass das Shelf über eine

Zwangskühlung verfügt.

Wenn Sie das Blade in Gebieten mit starker elektromagnetischer Strahlung betreiben, stellen

Sie sicher, dass das Blade mit dem System verschraubt ist und das System durch ein Gehäuse abgeschirmt wird.

ATCA-7360 Installation and Use (6806800J07S) 33

Sicherheitshinweise

Verletzungen oder Kurzschlüsse

Blade oder Stromversorgung

Falls die ORing Dioden des Blades durchbrennen, kann das Blade einen Kurzschluss zwischen den Eingangsleitungen A und B verursachen. In diesem Fall ist Leitung A immer noch unter

Spannung, auch wenn sie vom Versorgungskreislauf getrennt ist (und umgekehrt).

Prüfen Sie deshalb immer, ob die Leitung spannungsfrei ist, bevor Sie Ihre Arbeit fortsetzen, um Schäden oder Verletzungen zu vermeiden.

Schaltereinstellungen

Fehlfunktion des Blades

Schalter, die mit 'Reserved' gekennzeichnet sind, können mit produktionsrelevanten

Funktionen belegt sein. Das Ändern dieser Schalter kann im normalen Betrieb Störungen auslösen.

Verstellen Sie nur solche Schalter, die nicht mit 'Reserved' gekennzeichnet sind. Prüfen und

ändern Sie die Einstellungen der nicht mit 'Reserved' gekennzeichneten Schalter, bevor Sie das

Blade installieren.

Beschädigung der Blade

Das Verstellen von Schaltern während des laufenden Betriebes kann zur Beschädigung des

Blades führen.

Prüfen und ändern Sie die Schaltereinstellungen, bevor Sie das Blade installieren.

Batterie

Beschädigung des Blades

Ein unsachgemäßer Einbau der Batterie kann gefährliche Explosionen und Beschädigungen des Blades zur Folge haben.

Verwenden Sie deshalb nur den Batterietyp, der auch bereits eingesetzt wurde und befolgen

Sie die Installationsanleitung.

34 ATCA-7360 Installation and Use (6806800J07S)

Sicherheitshinweise

Umweltschutz

Entsorgen Sie alte Batterien und/oder Blades/Systemkomponenten/RTMs stets gemäß der in

Ihrem Land gültigen Gesetzgebung und den Empfehlungen des Herstellers.

ATCA-7360 Installation and Use (6806800J07S) 35

Sicherheitshinweise

36 ATCA-7360 Installation and Use (6806800J07S)

Chapter 1 Introduction

1.1 Features

The ATCA-7360 is a high-performance ATCA compliant single board computer designed for demanding storage and processing applications.

The following is the list of main features:

 Dual socket Intel Xeon5500 Series CPU

Standard configuration ATCA-7360: Intel Xeon 5500 L5518 60W 2.13GHz

DDR3 memory running at 1066 MHz

3 independent memory channels on each CPU

2+2+1 sockets each CPU (10 sockets in total)

Max 80 GB (10 x 8 GB)



Intel 5520 I/O hub spanning 36 PCIe Gen2 lanes (5 Gbps)

4 GB onboard USB flash module assembly option with capacity up to 16GB

PCIe Generation 2 with 5 Gpbs

Dual Gb Ethernet AdvancedTCA base interface



Dual 10/1Gb Ethernet AdvancedTCA fabric interface (PICMG opt. 9 and 1)

Additional GbE ports on faceplate and AdvancedTCA Updated Channel

Serial over LAN via AdvancedTCA base interface

CPU and I/O virtualization support

Power management support

Crisis recovery for BIOS, IPMC firmware and FPGA code

Extension slot for SATA module

Extension slot for Persistent Memory module (PMEM)

Designed for NEBS level 3

ATCA-7360 Installation and Use (6806800J07S) 37

Introduction

1.2 Standard Compliances

The product is designed to meet the following standards.

Table 1-1 Standard Compliances

Standard

UL 60950-1

EN 60950-1

IEC 60950-1

CAN/CSA C22.2 No 60950-1

CISPR 22

CISPR 24

EN 55022

EN 55024

FCC Part 15

EN 300386

NEBS Standard GR-1089 CORE

ISO 8601

NEBS Standard GR-63-CORE

ETSI EN 300019 series

Description

Legal safety requirements

EMC requirements on system level (predefined Artesyn system)

PICMG 3.0 and 3.1

Y2K compliance

NEBS level three

Product is designed to support NEBS level three. The compliance tests must be done with the customer target system.

Defines mechanics, blade dimensions, power distribution, power and data connectors, and system management

1. The blade does not fulfill the “Unpacked Equipment Shock Criteria” as defined in NEBS GR63 4.3.2. During tests which consisted of dropping the blade from 100 mm height, we observed that on some blades the AdvancedTCA zone

2 and 3 connectors got damaged. Although it was possible to manually repair the connectors and the blade was fully functional again afterwards, the criteria imposed by the NEBS standard were not fulfilled.

38 ATCA-7360 Installation and Use (6806800J07S )

Introduction



This blade contains an embedded power source rated >150W. To achieve NEBS compliance on system level, Shelf Ground (chassis ground) and Logic Ground (logic signal return) have to be connected. The connection may be implemented inside the shelf, for example at the backplane, or the shelf has to provide a possibility to lead Logic

Ground out of the shelf for external connection to Central Office Ground. For further information refer to Telcordia GR-1089-CORE, section 9.8.2, requirement R9-14.

The product has been designed to meet the directive on the restriction of the use of certain hazardous substances in electrical and electronic equipment (RoHS) Directive

2002/95/EC.

1.3 Mechanical Data

The following table provides details about the blade's mechanical data, such as dimensions and weight.

Table 1-2 Mechanical Data

Feature

Dimensions (width x height x depth)

Weight of blade

Value

30 mm x 351 mm x 312 mm

8U form factor

3.8 kg

ATCA-7360 Installation and Use (6806800J07S) 39

Introduction

1.4 Ordering Information

The following table lists the blade variants that were available as of the time of writing this manual. Consult your local Artesyn sales representative for the availability of further variants.

Table 1-3 Blade Variants - Ordering Information

Product Name

ATCA-7360-0GB

ATCA-7360-12GB

ATCA-7360-24GB

ATCA-7360-48GB

Description

ATCA processor blade, dual L5518 quad-core (2.13 GHz), 0GB, 10G support

ATCA processor blade, dual L5518 quad-core (2.13 GHz), 6X 2GB, 10G support

ATCA processor blade, dual L5518 quad-core (2.13 GHz), 6X 4GB, 10G support

ATCA processor blade, dual L5518 quad-core (2.13 GHz), 6X 8GB, 10G support

1. No memory installed

The following table lists the blade accessories that are available upon release of this publication. Consult your local sales representative for the availability of other accessories.

Table 1-4 Blade Accessories - Ordering Information

Accessory

ATCA-7360-MEM-2G

ATCA-7360-MEM-4G

ATCA-7360-MEM-8G

RTM-ATCA-7360

RTM-ATCA-7360-L

RTM-ATCA-7360-FC

ATCA7360-HDD1-SAS

ATCA7360-HDD2-SAS

ATCA7360-HDD3-SATA

Description

2 GB DDR3 VLP memory module for ATCA-736X product series

4 GB DDR3 VLP memory module for ATCA-736X product series

8 GB DDR3 VLP memory module for ATCA-736X product series

RTM for the ATCA-736X product series, 6x GBE, 2x SAS, 1x optional

HDD

RTM for the ATCA-736X product series, 2x GBE, 2x SAS, 1x optional

HDD

RTM for the ATCA-736X product series, 6x GBE, 2x SAS, 2x FC

147 GB SAS HDD for the RTM-ATCA-7360

300 GB SAS HDD for the RTM-ATCA-7360

80 GB SATA HDD (ext. temp.) for the RTM-ATCA-7360

ATCA-7360 Installation and Use (6806800J07S )

Introduction

Table 1-4 Blade Accessories - Ordering Information (continued)

Accessory

RTM-ATCA-7360-HDDKIT

ATCA7360-MMOD-SATA1

ATCA7360-MMOD-SATA2

ATCA7360-SFMMOD

RJ45-DSUB-ATCA7140

SA-BBS-WR30-7360

Description

HDD kit for RTM-ATCA-7360

32 GB on-board solid state disk at SATA for ATCA-736X product series

64 GB on-board solid state disk at SATA for ATCA-736X product series

Reset persistent memory, 16MB SRAM, 64MB Flash for the ATCA-

736X product series

RJ-45 DSUB cable for the ATCA-7140, 7150, 7350, 736X

CD - BBS SW and WR PNE3.0 for ATCA-7360

1. HDD kit option for RTM-ATCA-7360 and RTM-ATCA-7360-L

2. Persistent memory and solid state disk mutually exclusive

ATCA-7360 Installation and Use (6806800J07S) 41

Introduction

1.5 Product Identification

The following figure illustrates the location of the serial number label.

Figure 1-1 Serial Number Location

42 ATCA-7360 Installation and Use (6806800J07S )

Introduction

ATCA-7360 Installation and Use (6806800J07S) 43

Introduction

44 ATCA-7360 Installation and Use (6806800J07S )

Installation

2.1 Unpacking and Inspecting the Blade

Chapter 2

Damage of Circuits

Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life.

Before touching the blade or electronic components, make sure that you are working in an

ESD-safe environment.

Shipment Inspection

To inspect the shipment, perform the following steps.

1. Verify that you have received all items of your shipment:



ATCA-7360 blade



One printed copy of Quick Start Guide

One printed copy of Safety Notes Summary

Any optional items ordered

2. Check for damage and report any damage or differences to the customer service.

3. Remove the desiccant bag shipped together with the blade and dispose of it according to your country’s legislation.

The blade is thoroughly inspected before shipment. If any damage occurred during transportation or any items are missing, please contact our customer service immediately.

ATCA-7360 Installation and Use (6806800J07S) 45

Installation

2.2 Environmental and Power Requirements

In order to meet the environmental requirements, the blade has to be tested in the system in which it is to be installed.

Before you power up the blade, calculate the power needed according to your combination of blade upgrades and accessories.

2.2.1 Environmental Requirements

The environmental conditions must be tested and proven in the shelf configuration used. The conditions refer to the surrounding of the blade within the user environment. The product supports the specified temperature conditions in a shelf with airflow characteristics meeting at least the CP-TA B.4

cooling profile.



The environmental requirements of the blade may be further limited down due to installed accessories, such as hard disks or mezzanine modules, with more restrictive environmental requirements.

Operating temperatures refer to the temperature of the air circulating around the blade and not to the actual component temperature.

Blade Damage

Blade surface

High humidity and condensation on the blade surface causes short circuits.

Do not operate the blade outside the specified environmental limits. Make sure the blade is completely dry and there is no moisture on any surface before applying power.

Blade Overheating and Blade Damage

Operating the blade without forced air cooling may lead to blade overheating and thus blade damage.

When operating the blade, make sure that forced air cooling is available in the shelf.

46 ATCA-7360 Installation and Use (6806800J07S )

Installation

Table 2-1 Environmental Requirements

Requirement

Temperature

Operating

Normal Operation: +5 °C (41 °F) to +40

°C (104 °F) according to Telcordia GR-

63-CORE (NEBS) and ETSI EN 300 019-

1-3, Class 3.1

Exceptional Operation: -5 °C (23 °F) to

+55 °C (131 °F) according to Telcordia

GR-63-CORE (NEBS)

Note: This exceeds ETSI EN 300 019-1-

3, Class 3.1E requirements (-5°C to

+45°C)

Temp. Change +/- 0.25 °C/min according to Telcordia

GR-63-CORE

Rel. Humidity Normal Operation: 5%rH to 85%rh noncondensing

Exceptional Operation: 5%rH to 90%rh non-condensing

According to Telcordia GR-63-CORE

(NEBS) and EN 300 019-1-3, Classes 3.1 and 3.1E

Vibration 1g from 5 to 200Hz and back to 5Hz at a rate of 0.25 octave/minute

(according to Telcordia GR-63-core)

Shock

Free Fall -

Half-sine, 11 ms, 30 m/s

Non-Operating

-40 °C (-40 °F) to +70 °C (158 °F) according to Telcordia GR-63-CORE

(NEBS) and ETSI EN 300 019-1-2, Class

2.3

Note: This exceeds ETSI EN 300 019-1-

1, Class 1.2 requirements (storage from -25 °C to +55 °C

Note: This may be further limited by installed accessories.

+/- 0.25 °C/min

5% to 95% non-condensing according to Telcordia GR-63-CORE (NEBS) and

EN 300 019-1-1, Classes 1.2 and 2.3

5-20 Hz at 0.01 g

/Hz (according to

Telcordia GR-63-core and ETSI EN 300

019-2-2)

20-200 Hz at -3 dB/octave Hz

(according to Telcordia GR-63-core and ETSI EN 300 019-2-2)

Random 5-20Hz at 1 m

Random 20-200Hz at 3 m

Blade level packaging

Half-sine, 6 ms at 180 m/s

1.2 m/ packaged (according to ETSI

300 019-2-2)

100 mm unpackaged (according to

Telcordia GR-63-core)

ATCA-7360 Installation and Use (6806800J07S) 47

Installation

During the safety qualification of this blade, the following on-board locations were identified as critical with regards to the maximum temperature during blade operation. To guarantee proper blade operation and to ensure safety, you have to make sure that the temperatures at the locations specified in the following are not exceeded. If not stated otherwise, the temperatures should be measured by placing a sensor exactly at the given locations.

Table 2-2 Critical Temperature Limits

Component

Nehalem-EP

Tylersburg IOH36 D

ICH10R

Intel 82599 (Niantic)

Intel 82576 (Kawela)

Intel 82572EI

Payload DCDC 48 V/12 V

DDR3 DIMM Modules

CPU VCC controller (up to

100 A)

Thermal Design

Power

60 W

27.1 W

4.5 W

8.82 W

2.8 W

2.1 W (typ. 1.5W)

10 W

6.9 W (estimate TS team)

6 W

Max Case or Junction

Temperature

T jmax

=100°C (junction)

T cmax

=105°C (case)

T cmax

=105°C

T cmax

=120°C

T cmax

=110°C (case)

T cmax

=97°C (case)

85° C

48 ATCA-7360 Installation and Use (6806800J07S )

Installation

For your convenience all temperature spots are shown in the figure below that provides a detailed view of the blade.

Figure 2-1 Location of Critical Temperature Spots (Blade Top Side)

C1273

C1272

C1277

C1276

C1274

C1275

239

120

R2719

R2718

C3144

C4053

C4765

C4766

C4767

C4768

169

C4215

167

R3045

Temperature Test Point #1

Max. 100°C

Temperature Test Point #2

Max. 90°C

J35

R1598

R1597

R1615

C4498

C4497

C4490

C2029

C4496

C4495

C4494

31 3

1 5

12 14

32 34

31 33 35

L83 L93 L82

J34

Q55 Q78 Q54

C1258

C1260

P9910

C1263

C1262

J111

MH19

CE30 CE31

CE29

GH10

CD10

A10

P23

GH1

R1249

CD1

Temperature Test Point #3

Max. 105°C

Note: Temperature Test Point #1 (on DC/DC Converter Module): Max. 100°C (Exact location: In the geometric middle of the heat spreader).

Temperature Test Point #2 (on Power Input Module): Max. 90°C (Exact location: On top of the transformer).

Temperature Test Point #3 (on Hold-Up Capacitor): Max. 105°C

ATCA-7360 Installation and Use (6806800J07S) 49

Installation

If you integrate the blade in your own system please contact your local sales representative for further safety information.

2.2.2 Power Requirements

The blade's power requirements depend on the installed hardware accessories. If you want to install accessories on the blade, the load of the respective accessory has to be added to that of the blade. In the following table you will find typical examples of power requirements with and without accessories installed. For information on the accessories' power requirements, refer to the documentation delivered together with the respective accessory or consult your local

Artesyn representative for further details.

The blade must be connected to a TNV-2 or a safety-extra-low-voltage (SELV) circuit. A TNV-2 circuit is a circuit whose normal operating voltages exceed the limits for a SELV circuit under normal operating conditions, and which is not subject to over -voltages from telecommunication networks.

Table 2-3 Power Requirements

Characteristic

Rated Voltage

Exception in the US and Canada

Operating Voltage

Exception in the US and Canada

Maximum power consumption of ATCA-7360 (with

RTM-ATCA-7360 including a SAS HDD)

Maximum power consumption of ATCA-7360 (without

RTM-ATCA-7360)

Value

-48 VDC to -60 VDC

-48 VDC

-39 VDC to -72 VDC

-39 VDC to -60 VDC

260 W

(200 W typical)

240 W

(185 W typical)

50 ATCA-7360 Installation and Use (6806800J07S )

Installation

The blade provides two independent power inputs according to the AdvancedTCA

Specification. Each input has to be equipped with an additional fuse of maximum 90 A located either in the shelf where the blade is installed or the power entry module (PEM).

The power consumption has been measured using specific boards in a configuration considered to represent the worst-case (with RTM-ATCA-7360 and SAS HDD, maximum memory population, USB-Flash, SF-MEM persistent memory module) and with software simultaneously exercising as many functions and interfaces as possible. This includes a particular load software provided by Intel designed to stress the processors to reach their theoretical maximum power specification.

Any difference in the system configuration or the software executed by the processors may affect the actual power dissipation. Depending on the actual operating configuration and conditions, customers may see slightly higher power dissipation, or it may even be significantly lower. There is also a dependency on the batch variance of the major components like the processor and DIMMs used. Artesyn does not represent or warrant that measurement results of a specific board provide guaranteed maximum values for a series of boards.

ATCA-7360 Installation and Use (6806800J07S) 51

Installation

2.3 Blade Layout

The following figure illustrates the location of components on the ATCA-7360:

Figure 2-2 ATCA-7360 Blade Layout

52 ATCA-7360 Installation and Use (6806800J07S )

Installation

2.4 Switch Settings

The blade provides the configuration switches SW1, SW2, SW3, and SW4. Their location is shown in

Figure "ATCA-7360 Blade Layout" on page 52 .

Blade Malfunction

Switches marked as 'Reserved' might carry production-related functions and may cause the blade to malfunction if their setting is changed.

Therefore, do not change settings of switches marked as 'Reserved'. The setting of switches which are not marked as 'Reserved' has to be checked and changed before blade installation.

Blade Damage

Setting/resetting the switches during operation can cause blade damage.

Therefore, check and change switch settings before you install the blade.

For normal operation, all switches must be OFF. Switches are used only for repair, manual maintenance and critical crisis recovery. For remote maintenance and in order that all firmware upgrade features through IPMC are available, all switches must be in their default

OFF position and are controlled through IPMC.

ATCA-7360 Installation and Use (6806800J07S) 53

Installation

Table 2-4 Switch Settings

Switch

SW1-1

SW1-2

SW1-3

SW1-4

SW2-1

SW2-2

SW2-3

SW2-4

SW3-1

SW3-2

Description

Default Boot-Flash (BIOS) write protection

OFF: Write-enabled (default)

ON: Write-protected

Recovery Boot-Flash (BIOS) write protection

OFF: Write-enabled (default)

ON: Write-protected

TSOP or debug-socket SPI boot select

OFF: Boot from TSOP SPI flash (either Default/Recovery) (default)

ON: Boot from debug socket SPI flash

ICH10 GPIO33-Pinstrap: SPI Flash Descriptor Security Override Strap and ME disable if sampled LOW

OFF: No SPI Flash Descriptor security override and ME working in S0/S1 (default)

ON: Flash security descriptor and ME disabled (for debugging only)

Serial Line #1 and #2 Routing

OFF: FPGA-COM#1 to faceplate, FPGA-COM#2 to RTM (default)

ON: FPGA-COM#1 to RTM, FPGA-COM#2 to faceplate

IPMC Debug Console Routing

OFF: IPMC debug console at 3-pin header (default)

ON: IPMC debug console at faceplate instead of FPGA COM

FPGA-Bitstream PROM selection

OFF: FPGA loads from default Bitstream PROM

ON: FPGA loads from Recovery Bitstream PROM

PECI Master selection

OFF: IPMC is PECI master

ON: ICH10 is PECI master

Enable manual “Default SPI Boot Flash” / “Recovery SPI Boot Flash” selection

OFF: IPMI selects boot flash (default)

ON: SW3-2 selects Boot Flash

SW3-2 controls boot flash selection if SW3-1 is set to ON

OFF: Boot from “Default Boot Flash” device (default)

ON: Boot from “Recovery Boot Flash” device

ATCA-7360 Installation and Use (6806800J07S )

Installation

Table 2-4 Switch Settings (continued)

Switch

SW3-3

SW3-4

SW4-1

SW4-2

SW4-3 and

SW4-4

Description

Enable faceplate (Frontboard and RTM) reset push button

OFF: Reset push button enabled (default)

ON: Reset push button disabled

ICH10 TCO Timer system reboot feature

OFF: ICH10 TCO Timer system reboot feature enabled (default)

ON: ICH10 will disable the TCO Timer system reboot feature

ICH10 TOP Swap override

OFF: Default

ON: system is strapped to the “topblock swap” mode (Intel ICH10 inverts A16 for all cycles targeting BIOS space).

ICH10 TCO Timer system reboot feature

OFF: ICH10 TCO Timer system reboot feature enabled (default)

ON: system is strapped to the “No Reboot” mode (ICH10 will disable the TCO Timer system reboot feature).

Load BIOS default settings

OFF, OFF: Normal operation

OFF, ON: Load BIOS default from IPMI Boot Parameter DEFAULT area

ON, OFF: Reserved

ON, ON: Status Codes to COM

2.5 Installing Blade Accessories

The following additional components are available for the blade:



DIMM memory modules

PMEM (persistent memory) module



SATA module

USB flash module

Rear transition modules

They are described in detail in the following sections. For order numbers refer to section

Ordering Information on page 40 .

ATCA-7360 Installation and Use (6806800J07S) 55

Installation

2.5.1 DIMM Memory Modules

The blade provides 10 memory slots for main memory DIMM modules. You may install and/or remove DIMM memory modules in order to adapt the main memory size to your needs. The corresponding installation/removal procedures are described in this section.

The location of the DIMM Memory Modules are shown in

Figure 2-2 on page 52 .

When installing DIMM memory modules, the DIMM sockets farthest away on each memory channel from the CPU device need to be populated first. Only qualified DDR3 DIMMs (Dual

Ranked RDIMM) are allowed. The reason is the thermal limit/budget of the blade and the high variation of the power consumptions of different DIMMM types. For thermal reasons, no 4-rank

DIMMs and no dual-Die DIMM are allowed.

DIMM modules used within one channel must be based on the same memory technology.

To achieve proper functionality in all use cases, it is highly recommended to insert only one type of memory module from one vendor across all DIMM slots on the board. If mixing different types of DIMMs or using the same type of DIMM from different vendors on one blade, then the full functionality in all cases cannot be guaranteed.

Damage of Circuits

Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life.

Before touching the module or electronic components, make sure that you are working in an ESD-safe environment.

Installation Procedure

To install a DIMM module, proceed as follows:

1. Remove the blade from system as described in

Installing and Removing the Blade

on page 60 .

2. Open the locks of memory module socket.

ATCA-7360 Installation and Use (6806800J07S )

Installation

3. Insert the DIMM module carefully into the socket.

As soon as the memory module has been fully inserted, the locks get closed automatically.

4. If applicable, repeat steps 2 to 3 to install further modules.

Damage of Circuits

Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life.

Before touching the module or electronic components, make sure that you are working in an ESD-safe environment.

Removal Procedure

To remove a DIMM module, proceed as follows:

1. Remove the blade from system as described in

Installing and Removing the Blade

on page 60 .

2. Open the locks of socket at both sides.

The memory module is automatically lifted up.

3. Remove module from the socket.

4. Repeat steps 2 to 3 in order to remove further memory modules.

2.5.2 PMEM and SATA Module

The PMEM/SATA extension slot allows assembly of either a PMEM or SATA module which are available as upgrade kits for ATCA-7360. PMEM module consists of an SRAM and a flash memory. The SRAM has a capacity of up to 16 MB and can be used as persistent memory, that means a memory that holds up the contents during reset. The flash memory has a capacity of up to 64 MB organized as two memory banks. The S/F memory module connects to the blade's

PCI subsystem. It can be configured via an FPGA register.

ATCA-7360 Installation and Use (6806800J07S) 57

Installation

The SATA module consists of a Solid State Disc of up to 128 GB and a SATA controller and connects physically to ICH10 SATA Port #5.

The extension module is mechanically fastened to the blade with two screws. The location of the two corresponding mounting holes as well as the S/F memory module connector is shown in

Figure 2-2 on page 52 .

The PMEM and SATA module are accessory kits and are not part of the default ATCA-7360. The following procedure describes the steps to install/remove the PMEM/SATA module.

Installation Procedure

To install a PMEM/SATA module, proceed as follows:

Damage of Circuits

Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life.

Before touching the module or electronic components, make sure that you are working in an ESD-safe environment.

1. Remove the blade from the system as described in

Installing and Removing the Blade

on page 60

.

2. Plug the PMEM/SATA module on the blade so that the module's standoffs fit in the blade's mounting holes.

3. Fasten the

PMEM/SATA module

to the blade using the two screws that previously had fixed the S/F memory module to the blade.

4. Reinstall the blade into the system as described in

Installing and Removing the Blade

on page 60

.

The additional resource (either memory or SATA SSD) will be detected automatically during the boot-up sequence.

ATCA-7360 Installation and Use (6806800J07S )

Installation

Removal Procedure

To remove a PMEM/SATA module, proceed as follows:

Damage of Circuits

Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life.

Before touching the module or electronic components, make sure that you are working in an ESD-safe environment.

1. Remove the blade from the system as described in

Installing and Removing the Blade

on page 60

.

2. Remove the two screws holding the

PMEM/SATA module

.

3. Remove the

PMEM/SATA module

from the blade.

4. Reinstall the blade into the system as described in

Installing and Removing the Blade

on page 60

.

2.5.3 USB 2.0 Flash Module

The blades provides a USB 2.0 flash module with a capacity of 4 GB or 16 GB. The corresponding removal/installation procedures are described in this section.

ATCA-7360 Installation and Use (6806800J07S) 59

Installation

The location of the USB 2.0 Flash Module is shown in

Figure "ATCA-7360 Blade Layout" on page

Damage of Circuits

Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life.

Before touching the module or electronic components, make sure that you are working in an ESD-safe environment.

Removal Procedure

To remove a USB flash module, proceed as follows:

1. Remove blade from system as described in

Removing the Blade

on page 64

.

2. Remove the screw on the left side of the flash module (see figure

Figure 2-2 on page 52 ).

3. Lift the flash module from the socket.

Installation Procedure

To install a USB flash module, proceed as follows:

1. Remove blade from system as described in

Removing the Blade

on page 64

.

2. Insert new flash module into the socket (see figure

Figure 2-2 on page 52 ).

3. Tighten the screw on the left side of the flash module.

2.6 Installing and Removing the Blade

The blade is fully compatible to the AdvancedTCA standard and is designed to be used in

AdvancedTCA shelves.

60 ATCA-7360 Installation and Use (6806800J07S )

Installation

The blade can be installed in any AdvancedTCA node slot. Do not install it in an AdvancedTCA hub slot.

Damage of Circuits

Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life.

Before touching the blade or electronic components, make sure that you are working in an

ESD-safe environment.

Blade Malfunctioning

Incorrect blade installation and removal can result in blade malfunctioning.

When plugging the blade in or removing it, do not press on the faceplate but use the handles.

2.6.1 Installing the Blade

To install the blade into an AdvancedTCA shelf, proceed as follows.

ATCA-7360 Installation and Use (6806800J07S) 61

Installation

Installation Procedure

The following procedure describes the installation of the blade. It assumes that your system is powered. If your system is not powered on, you can disregard the blue LED and thus skip the respective step. In this case it is a purely mechanical installation.

1. Ensure that the top and bottom ejector handles are in the outward position by squeezing the lever and the latch together.

2. Insert blade into the shelf by placing the top and bottom edges of the blade in the card guides of the shelf. Ensure that the guiding module of shelf and blade are aligned properly.

3. Apply equal and steady pressure to carefully slide the blade into the shelf until you feel resistance. Continue to gently push the blade until the blade connectors engage.

4. Squeeze the lever and the latch together and hook the lower and the upper handle into the shelf rail recesses.

ATCA-7360 Installation and Use (6806800J07S )

Installation

5. Fully insert the blade and lock it to the shelf by squeezing the lever and the latch together and turning the handles towards the faceplate.

If your shelf is powered on, as soon as the blade is connected to the backplane power pins, the blue LED is illuminated.

When the blade is completely installed, the blue LED starts to blink. This indicates that the blade has signified its presence its presence to the shelf management controller.

If an RTM is connected to the front blade, make sure that the handles of both the RTM and the front blade are closed in order to power up the blade’s payload.

6. Wait until the blue LED is switched off, then fasten the faceplate screws, which secure the blade to the shelf.

When the blue LED is switched OFF and the green LED (IS) is switched ON, this indicates that the payload has been powered up and the blade is active.

7. Connect cables to the faceplate, if applicable.

ATCA-7360 Installation and Use (6806800J07S) 63

Installation

2.6.2 Removing the Blade

This section describes how to remove the blade from an AdvancedTCA system.

Damage of Circuits

Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life.

Before touching the blade or electronic components, make sure that you are working in an

ESD-safe environment.

Blade Malfunctioning

Incorrect blade installation and removal can result in blade malfunctioning.

When plugging the blade in or removing it, do not press on the faceplate but use the handles.

Removal Procedure

The following procedure describes how to remove the blade from a system. It assumes that the system is powered. If the system is not powered on, you can disregard the blue LED and skip the respective step. In that case, it is purely a mechanical procedure.

1. Unlatch the lower handle by squeezing the lever and the latch together and turning the handle outward just enough to unlatch the handle from the faceplate. Do not rotate the handle fully outward.

The blue LED blinks indicating that the blade power-down process is ongoing.

2. Wait until the blue LED is illuminated permanently, then unlatch the upper handle and rotate both handles fully outward.

If the LED continues to blink, a possible reason may be that the upper layer software rejected the blade extraction request.

64 ATCA-7360 Installation and Use (6806800J07S )

Installation

Data Loss

Removing the blade with the blue LED still blinking causes data loss.

Wait until the blue LED is permanently illuminated, before removing the blade.

3. Remove faceplate cables, if applicable.

4. Unfasten the screws of the faceplate until the blade is detached from the shelf.

5. Remove the blade from the shelf.

ATCA-7360 Installation and Use (6806800J07S) 65

Installation

66 ATCA-7360 Installation and Use (6806800J07S )

Controls, Indicators, and Connectors

Chapter 3

3.1 Mechanical Layout

The following figure illustrates the mechanical layout of the blade.

Figure 3-1 Mechanical Layout

DIMM

Sockets

CPU#0

MH7

M31

J256

LED15

R1067

120

239

120

239

CE10

DISP1

R975 R973

R971

J233

DISP2

J104

R904

120 C1244

LED18

J126

J128

R937 C1212 C1213

J204 J234

R3597

J285

J31

J76 J122 J236

BATH1

R938

R1631

R1636

C1238

R1603

R1596

C1239

C4628

C1211 C1210

J135 J119 J121

J235

J257

J208

M33

Q85

C4087

J105

Q83

R3466

P18

FIL14 FIL13

Q82

C4082

Q80

L95 L94

C1243 R1028

R1669 R2725

R1666

R1667

C2085

167

YEL

R1664

R1665

C2084

R2708

GRN

SW7

L17 L18

J199

P17

J29

R3591

C4690

R3471

C4691 C4159

J250

J278

R3482

R3481

R3480

R3479

R3478

R3477

R3476

R3475

R3455

MH9901

C4725

J77

R3492

J120

C1514

J228

C3195

C3179

C3180

C3188

C3196

C3197

C3186

C3178

J227

DN2

P42

J286

J49

C3193

C3192

C3182

C3191

C3185

C3194

C3190

C3189

J282

P27

D57

C533

C525

R3206

R3207

R3188

R3174

R407

D56

R2501

R950

J5002

R1210 R1209

Q26 Q25

C527

C543

C4761

C536

C532 C552

C546

C522

C2886

C529

C2885

C560

C549

C535

C558

C528

C537

C4760

C534

R2854

R2852

R2853

R2694

R2695

C530

C544

C523

C3132 R2690

J195 J190

J255

J194

P05

R1390

R1382

C1433

R1206

R1189

J116

C1422

D19

C1451

R1213

R1192

R1207

R1211

Q44

R1627

Q40

L80

P06

R1624

C3340 D54

Q42

Q38

L78

C4512

C4509

C4513

C2048

P45

J207

P46

C4516

C4511

C4520

Q41

Q37

L77

40 38

36 34

3133 29

25 23 21

121

P03

120

239

R1663

R1662

C2077

167

R1660

R1661

C2076

R2707

C1267

P04

MH10

120

239 167 121 43

42 40

37 35

3032

29 27 25

26 24 22

23 21 19

16 14 12

13 11

C1265

C1273

C4763

C1277

C1276

C1272

C1274

C1275

239

R2719

R2718

C3144

R3045 R2716

C3143

R2706

121

P01

C4053

C4765 C4767 +

C4215

C4217

C4764 C4769 C4770 C4771

C4203

Q43

Q39

L79

R1629

R1630

L89

C3822

C3816

C3819

C3824

MH13

Q69

Q68

+ C3974

C3971

C3970

R3418

C3840

R3419

R3420

R3421

R3422

R3423

R3424

R3319

J253

C3818

R3431

C3827

R3327

C3972

R3417

R3416

C3973

R3329

R3328

P200

FIL38

C3821

C3975

1 59

R3625

R3681

R3682

MH20

C1258

C1260

J35

J34

P9910

C1263

C1262

J111

R1598

R1597

R1615

R2488

C2094 R1675 R1677

239

P11

Q51

Q55

14 20

27 29

C4498

C4497

C4490

C2029

C4496

C4495

C4494

35 37

41 43

L83

2 4

3 5

16 18

2 24

23 25

2 6 28

31 33

3 5

9 41

L93

Q77

Q78

L82

Q50

Q54

L84

Q52

Q56

R1594

R1591

C4486

C4484

C4477

C4483

R2529

C2894

C4478

J187

C3955

C3958

+ C3954

L91

C3862

C3864

C3865

Q72

Q71

C3859

C3959

C3867

R3607

ZHS4

121

R2710 R1680

C2100 R1679

R2721

R2711

C3147 R2720

R3406 R3408

R3411

R3334 C3961

C3858 J254

C4624

R3343

C4742

R3414

C3968

R3346

R3413

R3415

C3969

C4643

R3498

R3518

R3543

R3519

R3520

R3521

R3522

R3523

R3524

R3525

J277

C4722 C4724

C4723

R3620

R3619

M27

L96

167

R3499

C4202

L97

C2101

R1681

R1682

C3148

R2722

R2723

A30

P39

C2862

R2486

C2863

C2867

C3067

C3052

C3058

C3050

R2667

R2668

R2665

R2666

R2738

ZHS3

120

239

120

239

120

239

120

MH19

CE30

GH10

CE29

CD10

A10

ZHS5

C4332

P23

CE31

GH1

R1249

CD1

J118

C1490

C4338

R1252

R1276

R1275

R1272

L21

R3191

R3193

R3184

R3194

R3189

R3190

R3233

R3232

R3203

R3185

R3186

R3210

R3204

R3205

Q93

R3080

LED28

C4688

C4687

C4689

LED30

LED31

GH10

J242

L22

CD10

A10

J232

P20

CD1

M29

U 1

C4005

C3988

U 1

C1059

R704

U 9

C1060

C4032

C4016

U 1 8

J71

J188

J46

P38

AK1

ZKEY2

J26

A10

P32

L50

R2259

R2790

C2955

C2957

C2975

C2977

R2080

R2037

R2032

C2974

C2976

C2954

C2956

AT1

L51

L49

C4682

C4678

C4686

C4672

C4683

C4669

C4680

C4667

C4674

C4676

C1473

R1240 R1241

C1472

C1470

C1468

GH1

L20 L19

C1463

T220

D21

C3026

R1236

R1235

R1223

C1453

R1238

R1243

J117

R1244

R1242

C1481 R1247 R1219 R1225

C1480

R1221

R1239

R1228

A10

U20

R3349

C3901

P30

P24

GH1

CD1

L87

Q66

P14

P13

P16

P15

A36 C3065 R2613 R2609

L69

C2909

C2912

R2741

C2496

R2735

R2060

R2026

R2029

R2048

R2021

R2022

R2020

R2087

R2089

R2094

R2083

R2118

R2049

R2038

R2023

R2109

R2057

R2108

R2091

R2131

R2085

L38

R2611

R2939

R2940

R2921

R3057

C2432

C2439 R2917

R2885

R2886

C4753

FIL49

C2901

J196

C4749

R2079

R2077

R2058

R2031

R2034

R2039

R2076

R2078

R2056

R2923

R2922

R2918

R2919

R2920

C3939

ZKEY4

CPU#1

DIMM

Sockets

Intel 5520

I/O Hub

ATCA-7360 Installation and Use (6806800J07S) 67

Controls, Indicators, and Connectors

3.2 Faceplate

The following figure illustrates the connectors, keys and LEDs available at the faceplate.

Figure 3-2 Faceplate

68 ATCA-7360 Installation and Use (6806800J07S )

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3.2.1 LEDs

The following figure illustrates all the LEDs available at the faceplate.

Figure 3-3 Location of Faceplate LEDs

ATCA-7360 Installation and Use (6806800J07S) 69

Controls, Indicators, and Connectors

The meaning of these LEDs is described in the following table.

Table 3-1 Faceplate LEDs

LED

OOS

ATN

ETH Status LEDs

U1, U2

Description

Out of Service

This LED is multicolored (red/amber) and is programmable via IPMC.

Its default color is red and its local control state (on or off) reflects the payload power state (on or off).

It permits override control by higher layer software, such as middle ware or applications, as specified in PICMG 3.0 specification.

In Service (Pay Load Power Status)

This LED is multicolored (green/red/amber) and is programmable via IPMC.

Its default color is green and its local control state is off.

It permits override control by higher layer software, such as middle ware or applications, as specified in PICMG 3.0 specification.

Attention

This LED has amber color and is programmable via IPMC.

Its local control state is off.

It permits override control by higher layer software, such as middle ware or applications, as specified in PICMG 3.0 specification.

The Ethernet connector provides two status LEDs

Link (upper)

Green: Link is available

Off: No link

Activity (lower)

Yellow: Activity

Off: No activity

Base interface activity is visualized via FPGA LEDs U1 and U2

User LED, selectable color via FPGA register.

Colors: red, green, orange

70 ATCA-7360 Installation and Use (6806800J07S )

Controls, Indicators, and Connectors

Table 3-1 Faceplate LEDs (continued)

LED

H/S

Description

Hot Swap

FRU State Machine

During blade installation:

Permanently blue: On-board IPMC powers up

Blinking blue: Blade communicates with shelf manager

OFF: Blade is active

During blade removal:

Blinking blue: Blade notifies shelf manager of its desire to deactivate

Permanently blue: Blade is ready to be extracted

3.2.2 Keys

The blade provides one faceplate reset key.

Figure 3-4 Location of Faceplate Reset Key

U1 U2 U3

ATCA-7360 Installation and Use (6806800J07S) 71

Controls, Indicators, and Connectors

On pressing it, a hard reset is triggered and all attached on-board devices are reset.

You cannot reset the IPMC via this key.

3.2.3 Connectors

The blade provides the following connectors at its faceplate:



One Ethernet

One Serial

Two USB

3.2.3.1

Ethernet Connector

The blade provides one Ethernet 1000Base-T interface connector at its faceplate. It is intended for blade configuration and constitutes, besides the two AdvancedTCA Base interfaces, a third

Ethernet interface to access the blade. The location of the Ethernet connector is shown in the following figure.

Figure 3-5 Location of Ethernet Connector

U1 U2 U3

72 ATCA-7360 Installation and Use (6806800J07S )

Controls, Indicators, and Connectors

The pinout of the connector is as follows.

Figure 3-6 Ethernet Interface Connectors Pinout

ETH_TX+

ETH_TX-

ETH_RX+ n.c.

n.c.

ETH_RXn.c.

n.c.

3.2.3.2

Serial Interface Connector

The blade provides one RS-232 serial interface connector at its faceplate. It is of type RJ-45 and corresponds to the physical serial interface port 1. By default, the BIOS maps this interface to the serial interface COM1. The on-board switch 2-1 allows to swap COM1 with COM2 and thus make COM2 accessible via the faceplate connector instead. Note that the BIOS serial redirection feature uses COM1 as access interface. Therefore swapping the serial interfaces via

SW2-1 also changes the serial connector that you need to access to make use of the serial redirection feature. The location of the connector is shown in the following figure.

Figure 3-7 Location of Serial Connector

U1 U2 U3

USB1 USB2

ATCA-7360 Installation and Use (6806800J07S) 73

Controls, Indicators, and Connectors

The pinout of the serial interface connector is shown in the following figure.

Figure 3-8 Serial Interface Connector Pinout

2 n.c.

n.c.

COM1_RS232_TXD

GND

COM1_RS232_RXD n.c.

n.c.

3.2.3.3

USB Connectors

The blade provides two USB connectors at its faceplate. They are compliant to the USB 2.0 standard and correspond to the blade's USB interfaces 3 and 4. Their location is shown in the following figure.

Figure 3-9 Location of USB Connectors

U1 U2 U3

USB1 USB2

74 ATCA-7360 Installation and Use (6806800J07S )

Controls, Indicators, and Connectors

The pinout of each USB connector is given in the following figure.

Figure 3-10 USB Connector Pinout

VP5_USB

USB_x_D-

USB_x_D+

GND

Exceeding the maximum USB current rating of 500mA per port will result in ATCA-7360 protecting itself through a controlled board shutdown.

3.3 On-board Connectors

The blade provides the following on-board connectors:



PMEM/SATA module connector

USB flash module connector

3.3.1 PMEM/SFMEM Module Connector

The PMEM/SFMEM Module connects to the blade through a connector that carries the following types of signals:

 PCI interface signals



I2C signals for connection with on-board IDROM device

Four configuration pins used for memory configuration

One SATA port connection (ICH10 port #5)

Power supply 5V and 3.3V

ATCA-7360 Installation and Use (6806800J07S) 75

Controls, Indicators, and Connectors

The location of the PMEM/SFMEM module connector is shown in the following figure.

Figure 3-11 Location of PMEM/SFMEM Module Connector

76 ATCA-7360 Installation and Use (6806800J07S )

Controls, Indicators, and Connectors

The pinout of this connector is shown in the following figure.

Figure 3-12 PMEM/SATA Module Connector Pinout

ATCA-7360 Installation and Use (6806800J07S) 77

Controls, Indicators, and Connectors

3.3.2 USB Flash Module Connector

The location of the flash memory module connector is shown in the following figure.

Figure 3-13 Location of USB Flash Module Connector

78 ATCA-7360 Installation and Use (6806800J07S )

Controls, Indicators, and Connectors

You can find the pin assignment of the flash connector in the following figure.

Figure 3-14 USB Flash Module Connector Pin Assignment

USB_D-

USB_D+

GND

KEY n.c.

n.c.

ATCA-7360 Installation and Use (6806800J07S) 79

Controls, Indicators, and Connectors

3.4 AdvancedTCA Backplane Connectors

The AdvancedTCA backplane connectors reside in the three zones 1 to 3 as specified by the

AdvancedTCA standard and are called P10, P20 and 23 and P30 and 32. The pinouts of all these connectors are given in this section.

Figure 3-15 Location of AdvancedTCA Connectors

80 ATCA-7360 Installation and Use (6806800J07S )

Controls, Indicators, and Connectors

The connector residing in zone 1 is called P10 and carries the following signals:

 Power feed for the blade (VM48_x_CON and RTN_x_CON)



Power enable (ENABLE_x)

IPMB bus signals (IPMB0_x_yyy)



Geographic address signals (HAx)

Ground signals (SHELF_GND and GND)

Reserved signals

Figure 3-16 P10 Backplane Connector Pinout

Zone 2 contains the two connectors P20 and P23. They carry the following types of signals:



Telecom clock signals (CLKx_)

Base interface signals (BASE_)

ATCA-7360 Installation and Use (6806800J07S) 81

Controls, Indicators, and Connectors



SAS update channel

100Base-BX update channel

Some of the pins provided by P20 and P23 are defined as optional in the AdvancedTCA specification and are unused on the blade. If the AdvancedTCA specification defines these signals as input signals, they are terminated on the blade and marked as "TERM_" in the following pinouts. In all other cases the pins are not connected and consequently marked as

"n.c.".

The pinouts of P20 and P23 are as follows.

Figure 3-17 P20 Backplane Connector Pinout - Rows A to D

82 ATCA-7360 Installation and Use (6806800J07S )

Controls, Indicators, and Connectors

Figure 3-18 P20 Backplane Connector Pinout - Rows E to H

Figure 3-19 P23 Backplane Connector Pinout - Rows A to D

ATCA-7360 Installation and Use (6806800J07S) 83

Controls, Indicators, and Connectors

Figure 3-20 P23 Backplane Connector Pinout - Rows E to H

Zone 3 contains the two connectors P30 and P32. They are used to connect an RTM to the blade and carry the following signals:

 Serial (RS232_x_yyyy)



Serial ATA (SATAx_yyy)

USB (USBxy)

PCI Express (PCIEx_yyy)

IPMI (IPMB1_xxx, ISMB_xxx)

Power (VP12_RTM, V3P3_RTM, VP5_RTM)

ATCA-7360 Installation and Use (6806800J07S )

Controls, Indicators, and Connectors



SAS Update channels

General control signals (BD_PRESENTx, RTM_PRSNT_N, RTM_RST_KEY-, RTM_RST-)

Figure 3-21 P30 Backplane Connector Pinout - Rows A to D

Figure 3-22 P30 Backplane Connector Pinout - Rows E to H

ATCA-7360 Installation and Use (6806800J07S) 85

Controls, Indicators, and Connectors

Figure 3-23 P32 Backplane Connector Pinout - Rows A to D

Figure 3-24 P32 Backplane Connector Pinout - Rows E to H

86 ATCA-7360 Installation and Use (6806800J07S )

Chapter 4 BIOS

4.1 Introduction

The Basic Input/Output System (BIOS) provides an interface between the operating system and the hardware of the blade. It is used for hardware configuration. Before loading the operating system, BIOS performs basic hardware tests and prepares the blade for the initial boot-up procedure.

During blade production, identical BIOS images are programmed into both boot flash banks. It is possible to select boot flash as device to boot from. This is done via an IPMI command. For further details refer to section

System Boot Options Parameter #96 on page 222 .

The BIOS used on the blade is based on the AMI UEFI BIOS with several Artesyn extensions integrated. Its main features are:

 Initialize CPU, chipset and memory



Initialize PCI devices

Setup utility for setting configuration data

IPMC support

Serial console redirection for remote blade access

Boot operation system

The BIOS complies with the following specifications:

 UEFI Specification 2.0



Plug and Play BIOS Specification 1.0A

PCI BIOS Specification 2.1



SMBIOS Specification 2.7

BIOS Boot Specification 1.01

Preboot Execution Environment (PXE) 2.1

Symmetric Multi Processing (SMP) 1.4

Advanced Configuration and Power Interface (ACPI) 3.0b

The BIOS setup program is required to configure the blade hardware. This configuration is necessary for operating the blade and connected peripherals. The configuration data are stored in the same flash device from which the board boots.

ATCA-7360 Installation and Use (6806800J07S) 87

BIOS

When you are not sure about configuration settings, restore the default values. This option is provided in case a value has been changed and you wish to reset settings. To restore the default values, press <F3> key in Setup.



Loading the BIOS default values will affect all setup items and will reset options previously altered.

If you set the default values, the displayed default values takes effect only after the BIOS setup is saved and closed.

4.2 Accessing the Blade Using the Serial Console

Redirection

The blade’s firmware provides a serial console redirection feature allowing remote access to the blade through a terminal connected to the blade's serial interface.

The terminal can be connected to display VGA text information. Terminal keyboard input is redirected and treated as a normal PC keyboard input. The serial console redirection feature can be configured via a setup utility.

4.2.1 Requirements for Serial Console Redirection

For serial console redirection, the following is required:

 Terminal or terminal emulation which supports a VT100 mode

 NULL-modem cable

Terminal emulation programs such as TeraTermPro can be used. In order to use TeraTermPro using the function keys, the keyboard configuration file of TeraTermPro has to be modified as follows:

Table 4-1 BIOS Key Codes for Terminal Emulation Program

Function Key

PF1

PF2

Key Code

88 ATCA-7360 Installation and Use (6806800J07S )

BIOS

4.2.2 Default Access Parameters

By default, the blade can be accessed using the serial interface COM1. By default, this interface is accessible using a RJ-45 connector at the blade's faceplate.

A NULL-Modem cable is available as accessory kit for the blade. It converts the RJ-45 connector to a standard DSUB connector which can be connected to a remote terminal. The following communication parameters are used, by default:

 Baud rate: 9600



Flow control: None

VT-100

8 data bits

No parity

1 stop bit

4.2.3 Connecting to the Blade

Procedure

To connect to the blade using the serial console redirect feature:

1. Configure terminal to communicate using the same parameters as in BIOS setup.

2. Connect terminal to NULL-modem cable.

3. Connect NULL-modem cable to COM port of the blade.

4. Start up blade.

4.3 Changing Configuration Settings

When the system is switched on or rebooted, the presence and functionality of the system components is tested by Power-On Self-Test (POST).

ATCA-7360 Installation and Use (6806800J07S) 89

BIOS

Press <F2> key when requested. The main menu appears. It looks similar to the one shown in the following figure.

Figure 4-1 Main Menu



Make sure that BIOS is properly configured prior to installing the operating system and its drivers.

If you save changes in setup, the next time the blade boots up, BIOS will configure the system according to the setup selections stored. If those values cause the system boot to fail, reboot and enter setup to get the default values or to change the selections that caused the failure.

In order to navigate in setup, use the arrow keys on the keyboard to highlight items on the menu. All other navigation possibilities are shown at the bottom of the menu.

Additionally, an item-specific help is displayed on the right side of the menu window.

ATCA-7360 Installation and Use (6806800J07S )

BIOS

4.4 Boot Options

This section describes which boot devices are supported by the BIOS and how to select the boot device.

4.4.1 Supported Boot Devices

The BIOS supports booting from the following devices/sources:



USB devices, such as floppy, CD ROM and hard disk

Solid State Disk connected to the SATA interface. (available only when SSD SATA is assembled)

Storage devices connected to the SAS controller (by RTM)



Network (Front Panel Ethernet, Base Ethernet and Ethernet on RTM)

Storage devices connected to the Fiber Channel module (by RTM) iSCSI block devices connected to Base or Fabric Ethernet

4.4.2 Selecting The Boot Device

There are two possibilities to determine the device from which BIOS attempts to boot:

 By setup to select a permanent order of boot devices

 By boot selection menu to select any device for the next boot-up procedure only

ATCA-7360 Installation and Use (6806800J07S) 91

BIOS

By Setup

To select the boot device by setup, proceed as follows:

1. From the menu, select Boot.

2. Select the order of the devices from which BIOS attempts to boot the operating system.

3. Enter the submenu "Option Rom Execution" to enable/disable booting from specific devices. Changes have to be saved and the board has to be rebooted when changing the Option Rom Execution.

If BIOS is not successful at booting from one device, it tries to boot from the next device on the list.

ATCA-7360 Installation and Use (6806800J07S )

4.4.3 By Boot Selection Menu

1. From the menu, select Save & Exit.

Figure 4-2 Save and Exit Menu

BIOS

2. Override existing boot sequence by selecting another boot device from the boot override list.

If the selected device does not load the operating system, BIOS resets the board and reverts to the previous boot sequence.

ATCA-7360 Installation and Use (6806800J07S) 93

BIOS

4.4.4 iSCSI Setup for Base and Fabric Ethernet

The board supports boot from iSCSI block devices connected to Base or Fabric Ethernet. To enable the iSCSI boot, proceed as follows:

1. From the menu, select Boot.

2. Under the Option ROM Execution sub menu, select the iSCSI item of Fabric Network Boot setup option.

Figure 4-3 Option ROM Execution

3. Save and Exit the BIOS setup.

4. To enter iSCSI setup, press Ctrl-D when following message displayed:

ATCA-7360 Installation and Use (6806800J07S )

4.4.4.1

ISCSI Port Selection

The following figure depicts the iSCSI Port Selection screen.

Figure 4-4 iSCSI Port Selection

BIOS

The following table provides information about Ethernet Port Mapping.

Table 4-2 Ethernet port mapping

Network Device

Base1

Base2

Fabric1

Fabric2 iSCSI Option ROM Device

Dev:10C9 Loc:1:0:0

Dev:10C9 Loc:1:0:1

Dev:10FC Loc:4:0:0

Dev:10FC Loc:4:0:1

ATCA-7360 Installation and Use (6806800J07S) 95

BIOS

Table 4-3 Select iSCSI Boot priority hot keys:

Key

Enter

Function

Selected device is primary boot device

Selected device is secondary boot device

Disable selected device

Blink LED (not supported)

Enter the Port configuration menu for the selected device

4.4.4.2

iSCSI Port Configuration

The following figure depicts the iSCSI Port Configuration screen.

Figure 4-5 iSCSI Port Configuration

Configure iSCSI port, Discard, Save and Exit menu items.

ATCA-7360 Installation and Use (6806800J07S )

4.4.4.3

iSCSI Boot Configuration

The following figure depicts the iSCSI Boot Configuration screen.

Figure 4-6 iSCSI Boot Configuration

BIOS

Enter Initiator and Target network configuration parameter.

ATCA-7360 Installation and Use (6806800J07S) 97

BIOS

4.4.4.4

iSCSI Challenge Handshake Authentication Protocol (CHAP)

Configuration

The following figure depicts the iSCSI CHAP Configuration screen.

Figure 4-7 iSCSI CHAP Configuration

Enter Challenge Handshake Authentication Protocol configuration parameter.

ATCA-7360 Installation and Use (6806800J07S )

BIOS

4.5 BIOS Setup Configuration

4.5.1 Main

The following table contains description about the options that can be configured on Main menu screen.

Table 4-4 Main Configuration

Item

System Date

Values

[Thu 11/11/2010]

System Time [15:48:21]

Description

Set the Date.

Use Tab to switch between Date elements

Set the Time.

Use Tab to switch between Time elements

4.5.2 Advanced

4.5.2.1

Advanced -> CPU Configuration

Table 4-5 CPU Configuration

Item

Hyper-threading

Values

Enabled (Default)

Disabled

Active Processor Core All (Default)

1, 2, 3, 4, 5

Limit CPUID Maximum Enabled

Disabled (Default)

ATCA-7360 Installation and Use (6806800J07S)

Description

Enabled for OS optimized for Hyper-Threading

Technology,

Disabled for other OS not optimized for Hyper Threading

Technology. When Disabled only one thread per enabled core is enabled.

Number of cores to enable in each processor package.

If set to enabled, limits the CPUID instruction function 0 to return a maximum value of 3. Some OS like Windows NT cannot handle a value greater than 3.

Default value is disabled. The CPUID instruction function 0 returns the number of the maximum standard functions.

BIOS

Table 4-5 CPU Configuration (continued)

Item

Execute Disable Bit

Hardware Prefetcher

Adjacent Cache Line

Prefetch

L1 Data Prefetcher

CPU C3 Report

CPU C6 report

100

Values

Enabled (Default)

Disabled

Enabled (Default)

Disabled

Enabled (Default)

Disabled

Enabled (Default)

Disabled

Data Reuse Optimization Enabled (Default)

Disabled

Intel Virtualization

Turbo Mode

Performance/Watt Traditional (Default),

Power Optimized

Package C State limit

Enabled (Default)

Disabled

Enabled (Default)

Disabled

Enabled

Disabled (Default)

Enabled (Default)

Disabled

C0, C1, C3, C6, C7,

No Limit (Default)

Description

XD can prevent certain classes of malicious buffer overflow attacks when combined with a supporting OS e.g.

Windows Server 2003 SP1, Windows Server 2008,

Windows XP SP2, SuSE Linux 9.2 and newer, RedHat

Enterprise 3 Update 3 and newer.)

To turn on/off the L2 Cache (MLC streamer) prefetcher.

See CPU Performance Settings on page 115

To turn on/off prefetching of adjacent cache lines to L2 cache. See chapter 4.5 CPU Performance Settings

Enable/Disable L1 Data Prefetcher.

See CPU Performance Settings on page 115

Data Reuse Performance Optimization for Server workloads.

See CPU Performance Settings on page 115

When enabled, a VMM can utilize the additional hardware capabilities provided by Intel Virtualization Technology.

Enable/Disable Turbo Mode. Turbo Mode allows processor cores to run faster than the marked frequency if the physical processor is operating below power, temperature and current specification limits.

Optimized - Turbo Boost engages after highest performance state is sustained for more than 2 seconds.

Traditional Intel Turbo Boost Technology is engaged immediately when possible.

Enable/Disable CPU C3 report to OS via ACPI table. CPU C3 state corresponds with ACPI C2 state.

CPU C3: Execution Clock is stopped. Core Caches flushed.

Intel recommends disabling CPU C3 report to OS.

Enable/Disable CPU C6 report to OS via ACPI table. CPU C6 state corresponds with ACPI C3 state.

CPU C6: Execution Clock stopped, Core states stored in the

Last Level Cache, Core caches flushed.

Intel recommends enabling CPU C6 report to OS.

Specifies the lowest C-State (Low Power idle state) for the

CPU package. Lower C states correspond lower power consumption and with a longer C-state entry/exit latency.

ATCA-7360 Installation and Use (6806800J07S )

BIOS

Table 4-5 CPU Configuration (continued)

Item

Socket 0 CPU Information

Values

Socket 1 CPU Information

Description

Show CPU 0 Information: CPU String, Stepping and

Microcode Version

Show CPU 1 Information: CPU String, Stepping and

Microcode Version

4.5.2.2

Advanced -> Memory Configuration

Table 4-6 Memory Configuration

Item

DIMM Information

Memory Mode

NUMA

Values

Independent (Default),

Mirroring, Lock-Step,

Sparing

Enable (Default)

Disable

Channel Interleaving

Rank Interleaving

Auto (Default), 6 Way, 4

Way, 3 Way, 2 Way, 1 Way

Auto (Default), 4 Way, 2

Way, 1 Way

Hardware Memory Test Enable (Default)

Disable

Description

Submenu for displaying DIMM presence and size information.

Select the mode for memory initialization

See

Memory Configuration on page 115

Enable/Disable support for Non uniform Memory

Access (NUMA) aware Operating Systems. Select

Enable for NUMA aware OS e.g Windows Server 2008.

Linux with kernel 2.6.xx. Select Disable for all other.

If enabled, BIOS creates the corresponding ACPI tables with Resource Affinity information. If disabled BIOS will set up memory interleaving between the two CPU packages.

Select different Channel Interleaving setting.

Recommended value: Auto

Select different rank Interleaving setting.

Recommended value: Auto

Enable/Disable hardware memory test.

ATCA-7360 Installation and Use (6806800J07S) 101

BIOS

Table 4-6 Memory Configuration (continued)

Item

Patrol Scrub

Values

Enable (Default)

Disable

Demand Scrub Enable

Disable (Default)

Description

Enable/Disable Patrol Scrubbing Feature.

Patrol scrubs are intended to ensure that data with a correctable error does not remain in DRAM long enough to stand a significant chance of further corruption to an uncorrectable error. The Integrated

Memory Controller will issue a Patrol Scrub in the background at a rate sufficient to write every line once a day.

Enable/Disable Demand Scrubbing Feature.

If a single ECC memory error is detected during normal read/write operation, the correct data and ECC check bits will be written back to memory.

4.5.2.3

Advanced -> Chipset - North Bridge

Table 4-7 Chipset - North Bridge

Item

Auto-Detect RTM

PCIe to RTM

Values

Enable (Default)

Disable

RTM PCIe Gen1 Speed Enable

Disable x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16

Description

If enabled, the RTM is detected and the RTM PCIe parameter are set for this RTM. If disabled the RTM

PCIe parameter can be set manually.

This option force RTM PCIe root ports to Gen1 operation. If this option is disabled RTM PCIe support both Gen1 and Gen2 devices.

This option is active when Auto-Detect RTM is set to

Enable.

Selects PCIe port bifurcation for Zone 3 connector

(RTM). This option is active when Auto-Detect RTM is set to Enable.

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4.5.2.3.1 Advanced -> Chipset - North Bridge -> Intel (R) VT for Directed I/O Configuration

Table 4-8 Chipset - North Bridge -> Intel (R) VT for Directed I/O Configuration

Item

Intel (R) VT-d

Interrupt Remapping

Coherency Support

ATS Support

Pass-through DMA

Values

Enable

Disable (Default)

Enable (Default)

Disable

Enable

Disable (Default)

Enable

Disable (Default)

Enable (Default)

Disable

Description

Enable/Disable Intel® Virtualization Technology for

Directed I/O. VT-d extends Virtualization Technology by providing hardware support for I/O-device virtualization.

Enable/Disable VT-d Engine Interrupt Remapping support.

Enable/Disable VT-d Engine Coherency support

Enable/Disable VT-d Engine Address Translation Services

(ATS) support.

Enable/Disable VT-d Engine Pass through DMA support.

4.5.2.3.2 Advanced -> Chipset - North Bridge -> IOH Thermal Sensors

Table 4-9 Chipset - North Bridge -> IOH Thermal Sensors

Item

Thermal Sensors

Values

Enable

Disable (Default)

Description

Enables/disables integrated North Bridge thermal sensors.

Recommended value: Disable

Low temperature threshold for thermal sensor.

Low Threshold

High Threshold

70..127

Default 90

70..127

Default 100

Catastrophic Threshold 70..127

Default 110

High temperature threshold for thermal sensor.

Critical temperature threshold for thermal sensor.

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4.5.2.4

Advanced -> Chipset - South Bridge

Table 4-10 Chipset - South Bridge

Item

Front Panel Ethernet

High Precision Timer

Values

Enable (Default)

Disable

Enable (Default)

Disable

Description

Enable/Disable Front Panel Ethernet Controller

Enable/Disable the High Precision Event Timer

4.5.2.4.1 Advanced -> Chipset - South Bridge -> USB Configuration

Table 4-11 Chipset - South Bridge -> USB Configuration

Item

All USB Devices

Values

Enabled (Default)

Disabled

USB 2.0(EHCI) Support Enabled (Default)

Disabled

Front Panel USB Enabled (Default)

Disabled

Onboard USB Flash Disk Enabled (Default)

Disabled

ARTM USB Enabled (Default)

Disabled

Description

Enable/Disable All USB devices.

Enable/Disable USB 2.0 (EHCI) Support

Enable/Disable Front Panel USB

Enable/Disable Onboard USB FlashDisk

Enable/Disable USB on ARTM

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4.5.2.5

Advanced -> SATA Configuration

Table 4-12 Advanced -> SATA Configuration

Item

SATA Mode

Values

Disable, IDE Mode

(Default), AHCI Mode,

RAID Mode

SATA Controller 0

SATA Controller 1

Disable, Enhanced,

Compatible (Default)

Disable,

Enhanced (Default)

4.5.2.6

Advanced -> USB Configuration

Description

Select the SATA Mode:

Disable: Disable the SATA controller

IDE Mode: SATA controller works in IDE compatible mode.

AHCI Mode: STATA controller works in AHCI Mode

RAID Mode: STATA controller works in RAID Mode,

Additionally a SATA RAID Option Rom is loaded.

Disable or select mode of Serial ATA Controller 0.

Enhanced: work in SATA mode

Compatible: work in IDE compatible mode.

Only available when SATA Mode is set to IDE mode.

Disable or select mode of Serial ATA Controller 1.

Enhanced: work in SATA mode

Only available when SATA Mode is set to IDE mode.

Table 4-13 Advanced -> USB Configuration

Item

Legacy USB Support

Values

Enabled (Default)

Disabled

EHCI Hand-off

Port 60/64 Emulation

Enabled (Default)

Disabled

Enabled (Default)

Disabled

ATCA-7360 Installation and Use (6806800J07S)

Description

Enables Legacy USB support. AUTO option disables legacy support if no USB devices are connected.

DISABLE option will keep USB devices available only for EFI applications.

Select Disabled to enable a workaround for OS without EHCI hand-off support.

Enables I/O port 60h/64h emulation support. This should be enabled for the complete USB keyboard legacy support for non-USB aware OS.

105

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Table 4-13 Advanced -> USB Configuration (continued)

Item

Device Reset timeout

Controller Timeout

USB Device Name

Values

10..40 seconds

Default 20 sec.

1..20 seconds

Default 20 sec.

Auto, Floppy, Forced FDD,

Hard Disk, CD-ROM

Description

USB mass storage device Start Unit command timeout. 10, 20, 30, 40 seconds.

The time out value for Control, bulk & interrupt transfer. 1, 5, 10, 20 seconds.

Mass storage device emulation type.

'AUTO' enumerates devices according to their media format. Devices less than 530MB are detected as floppies. Optical drives are emulated as 'CD-ROM', drives with no media will be emulated according to a drive type.

Forced FDD option can be used to force HDD formatted drive to boot as FDD (e.g. ZIP drive).

4.5.2.7

Advanced -> Super IO Configuration

4.5.2.7.1 Advanced -> Super IO Configuration -> Serial Port 0 Configuration

Table 4-14 Super IO Configuration -> Serial Port 0 Configuration

Item

Serial Port

Values

Enabled (Default)

Disabled

Change Settings Auto,

IO=3F8h IRQ=4 (Default),

IO=3F8h IRQ=3,4,5,6,7,10,11,12,

IO=2F8h IRQ=3,4,5,6,7,10,11,12,

IO=3E8h IRQ=3,4,5,6,7,10,11,12,

IO=2E8h IRQ=3,4,5,6,7,10,11,12

Description

Enable or Disable Serial Port (COM 0)

Select IO port and Interrupt settings for COM 0

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4.5.2.8

Advanced -> Serial Port Console Redirection

Table 4-15 Advanced -> Serial Port Console Redirection

Item

Console Redirection

Terminal Type

Values

Enabled (Default)

Disabled

Enabled (Default)

Disabled

VT100, VT100+,

VT-UTF8 (Default), ANSI

Description

Enable/Disable Console Redirection

Enable/Disable Console Redirection for Windows

Emergency Management Services (EMS)

VT-UTF8 is the preferred terminal type for out-of-band

Windows EMS management. The next best choice is

VT100+ and then VT100.

4.5.2.8.1 Advanced -> Serial Port Console Redirection -> Console Redirection Settings

Table 4-16 Serial Port Console Redirection -> Console Redirection Settings

Item

Terminal Type

Values

VT100 (Default), VT100+,

VT-UTF8, ANSI

Description

Terminal Emulation:

ANSI: Extended ASCII char set.

VT100: ASCII char set.

VT100+: Extends VT100 to support color, function keys, etc.

VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.

Bits per second

Data Bits

9600 (Default), 19200,

57600, 115200

7, 8 (Default)

Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.

Data Bits

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Table 4-16 Serial Port Console Redirection -> Console Redirection Settings (continued)

Item

Parity

Stop Bits

Recorder Mode

Resolution 100x31

Legacy OS Redirection

Values

None (Default), Even,

Odd, Mark, Space

1 (Default), 2

Enabled,

Disabled (Default)

Enabled,

Disabled (Default)

80x24 (Default), 80x25

Description

A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1's in the data bits is even. Odd: parity bit is 0 if num of 1's in the data bits is odd. Mark: parity bit is always 1. Space: Parity bit is always 0. Mark and Space

Parity do not allow for error detection.

Stop bits indicate the end of a serial data packet. The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.

On this mode enabled only text will be send. This is to capture Terminal data.

Enables or disables extended terminal resolution.

Specifies the Number of Rows and Columns supported by legacy serial redirection.

4.5.2.9

Advanced -> UEFI Network Stack

Table 4-17 Advanced -> UEFI Network Stack

Item

UEFI Network stack

Values

Enable,

Disable (Default)

Description

Enable/Disable the UEFI network stack. This is needed for UEFI network boot (PXE and iSCSI).

4.5.2.10 Advanced -> Runtime Error Logging

See Runtime Error Logging on page 119

Table 4-18 Advanced -> Runtime Error Logging

Item Values

Runtime Error Logging Enabled (Default)

Disabled

Description

Enable/Disable Runtime Error Logging Support. Events are sent to SMBIOS error log and IPMI SEL.

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Table 4-18 Advanced -> Runtime Error Logging

Item

PCI Error Logging

Error Threshold

Error Logging Limit

Values

Enabled (Default)

Disabled

1…1000,

Default 10

1…20

Default 10

Description

Enable/Disable PCI Error Logging.

Memory Correctable Error Threshold value. Range

[1..1000] Default 10.

Memory Correctable Error Logging Limit value. Range

[1..20] Default 10.

4.5.2.11 Advanced -> SMBIOS Event Log

4.5.2.11.1 Advanced -> SMBIOS Event Log -> SMBIOS Event Log Settings

Table 4-19 SMBIOS Event Log -> SMBIOS Event Log Settings

Item

SMBIOS Event Log

Erase Event Log

When Log is Full

Log EFI OEM Errors

Convert OEM Codes

Inject Errors

Values

Enabled (Default)

Disabled

No (Default),

Yes On next reset, Yes On every reset

Do Nothing (Default),

Erase Immediately

Description

Change this to enable or disable all features of SMBIOS

Event Logging during boot.

Choose options for erasing SMBIOS Event Log. Erasing is done prior to any logging activation during reset.

Enabled (Default)

Disabled

Enabled (Default)

Disabled

Enabled

Disabled (Default)

Choose options for reactions to a full SMBIOS Event Log.

This option does not take effect until the computer is restarted.

Enable or disable the logging of EFI Error Codes as OEM

Codes.

Enable or disable the converting of EFI Error Codes to

Standard SMBIOS Types. EFI Errors which cannot be translated are logged as SMBIOS Post Errors.

Inject Errors before booting a OS: Following errors are injected: No Console found, IPMI Boot Parameter

Checksum error, CPU Self test failure, Bad Battery.

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4.5.2.12 Advanced -> Local IPMI System Event Log

Table 4-20 Advanced -> Local IPMI System Event Log

Item

Erase Local SEL

Values

No (Default),

Yes On next reset, Yes On every reset

Description

Choose options for erasing local SEL.

This option does not take effect until the computer is restarted.

4.5.2.13 Advanced -> WHEA Configuration

Table 4-21 Advanced -> WHEA Configuration

Item

WHEA Support

Values

Enable,

Disable (Default)

Description

Enable or disable support for Windows Hardware Error

Architecture.

4.5.3 IPMI

4.5.3.1

IPMI -> IPMI Watchdog Configuration

Table 4-22 IPMI -> IPMI Watchdog Configuration

Item

POST Timer (FRB2)

FRB2 Timer timeout

Values

Enable,

Disable (Default)

3, 4, 5, 6 minutes

Default 6 minutes

Description

Enable or Disable FRB2 timer (POST timer).

This watchdog monitors BIOS initialization tasks.

Enter value Between 3 to 6 min for FRB2 Timer Expiration value.

Not available if FRB2 Timer is disabled.

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Table 4-22 IPMI -> IPMI Watchdog Configuration (continued)

Item

FRB2 Timeout Action

O/S Watchdog Timer

Timeout

Values

Do Nothing,

Reset (Default),

Power Down

Power Cycle

Enable,

Disable (Default)

Description

Configure how the system should respond if the FRB2

Timer expires.

Not available if FRB2 Timer is disabled.

If enabled, starts a BIOS timer just before booting the OS.

The OS has to shut off the watchdog timer when successfully booted.

Configure the time out of the O/S Boot Watchdog Timer.

Not available if O/S Boot is disabled.

O/S Watchdog Timeout

Action

1,2,3,5, 7, 10, 15, 20 minutes

Default 5 minutes

Do Nothing,

Reset (Default),

Power Down

Configure how the system should respond if the O/S Boot

Watchdog Timer expires. Not available if O/S Boot

Watchdog Timer is disabled.

4.5.3.2

IPMI -> System Event Log

Table 4-23 IPMI -> System Event Log

Item

Log EFI Status Codes

Values

Disabled,

Both (Default),

Error code, Progress code

Description

Configure the logging of EFI Status Codes to IPMI

Firmware Progress/Error events and other Status/Error

IPMI events. See

IPMI Error Logging on page 122

4.5.4 iSCSI

This menu is for configuration of iSCSI boot of UEFI compatible Operating Systems. iSCSI boot is enabled when UEFI Network stack is set to Enabled (see BIOS setup Advanced -> UEFI

Network Stack link).

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Enalbe iSCSI

For every network device, there is a submenu for configuration of iSCSI boot.

Table 4-24 iSCSI

Item iSCSI Initiator Name

Values Description

The worldwide unique name of the initiator. Only IQN

(iSCSI Qualified Name) format is accepted.

Enable/Disable iSCSI for this Ethernet Port.

Enable DHCP

Initiator IP Address

Initiator Subnet Mask

GateWay

Enable,

Disable (Default)

Enable,

Disable (Default)

0.0.0.0

Enable/Disable DHCP to retrieve IP address, Subnet

Mask, Gateway…

IP Address of the Initiator. Not available when DHCP is enabled.

Subnet Mask for the Initiator Network. Not available when DHCP is enabled.

Enter IP Address of Gateway. Not available when DHCP is enabled.

Get target info via DHCP.

Get target info via DHCP Enable,

Disable (Default)

Target Name

Target IP Address

Target Port

Boot LUN

CHAP Type

0.0.0.0

None (Default),

One Way,

Mutual

Enter the Target Name. Not available when DHCP is enabled.

IP Address of the Target. Not available when DHCP is enabled.

Target Port. Not available when DHCP is enabled.

Hexadecimal representation of the LUN, Examples are:

4752-3A4F-6b7e-2F99, 6734-9-156f-127, 4186-9. Not available when DHCP is enabled.

Select the CHAP (Challenge-Handshake Authentication

Protocol) type.

Save Changes

Back To Previous Page

Press Enter to Save Changes

Press Enter to Return to the previous Page (same as ESC)

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4.5.5 Boot

Table 4-25 Boot

Item Values

Setup Prompt Timeout 0..65535 seconds

Default 2 seconds

Bootup NumLock State On/off

Default on

Interrupt 19 Capture Enable,

Disable (Default)

Boot Option Priorities

4.5.5.1

Boot -> Option ROM Execution

Description

Number of seconds to wait for setup activation key.

65535(0xFFFF) means indefinite waiting.

Select the keyboard NumLock state.

If enabled, allows Option ROMs to trap Int 19. This is needed e.g. for some SCSI/SAS controller.

Select the boot device order.

Table 4-26 Boot -> Option ROM Execution

Item

Front Panel Net Boot

Values

Enabled (Default),

Disabled

Base Network Boot

Fabric Network Boot

Enabled (Default),

Disabled

Enabled (Default),

Disabled

ARTM Network Boot Enabled,

Disabled (Default)

ARTM SAS Boot Enabled (Default),

Disabled

ATCA-7360 Installation and Use (6806800J07S)

Description

Controls execution of the Option ROM for the Front Panel

Ethernet controller. Select Enabled when Front Panel

Boot is required.

Controls execution of the Option ROM for both Base

Network Ethernet controller. Select Enabled when Base

Network Boot is required.

Controls execution of the Option ROM for both Fabric

Network Ethernet controller. Select Enabled when Fabric

Network Boot is required.

Controls execution of the Option ROM for RTM Network

Ethernet controller. Select Enabled when RTM Network

Boot is required.

Controls execution of the Option ROM for RTM SAS controller. Select Enabled when RTM SAS Boot is required.

113

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Table 4-26 Boot -> Option ROM Execution (continued)

Item

ARTM FC Boot

Values

Enabled,

Disabled (Default)

Description

Controls execution of the Option ROM for RTM Fibre

Channel controller. Select Enabled when RTM Fibre

Channel Boot is required.

4.5.6 Security

If ONLY the Administrator's password is set, then this only limits access to Setup and is only asked for when entering Setup If ONLY the User's password is set, then this is a power on password and must be entered to boot or enter Setup. In Setup the User will have Administrator rights.

4.5.7 Save & Exit

Table 4-27 Save & Exit

Item

Save Changes and Exit

Discard Changes and Exit

Save Changes and Reset

Discard Changes and Reset

Save Changes

Discard Changes

Restore Defaults

Boot Override

Values Description

Exit BIOS setup after saving the changes.

Exit BIOS setup without saving any changes.

Reset the system after saving the changes.

Reset system setup without saving any changes.

Save Changes done so far to any of the setup options.

Discard Changes done so far to any of the setup options.

Restore/Load Defaults values for all the setup options.

Select a Boot Device to boot one time. Boot order is not changed.

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4.6 CPU Performance Settings

In order to get optimal performance, Intel recommends different settings of the CPU prefetcher for Westmere EP (Xeon 56xx) CPUs.

See BIOS setup -> Advanced -> CPU Configuration

Depending on the main purpose of the blade, the following settings are recommended:

 HPC and General Purpose Server:



Hardware Prefetcher [Enabled

]

Adjacent Cache Line Prefetch [Enabled]

L1 Data Prefetcher [Enabled]

DataReuse Optimization [Enabled]

Enterprise Platforms:

Hardware Prefetcher [Disabled]

Adjacent Cache Line Prefetch [Disabled]

L1 Data Prefetcher [Disabled]

DataReuse Optimization [Disabled]

It is recommended to test the application which will run on the blade with different CPU settings in order to select the best configuration.

4.7 Memory Configuration

The Intel Xeon processor 5600 series supports four different memory RAS (Reliability,

Availability, and Serviceability) modes: Independent Channel Mode, Spare Channel Mode,

Mirrored Channel Mode, and Lockstep Channel Mode.

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4.7.1 Independent Channel Mode

In independent mode, all three channels are operating independently. The ECC code appears in each independent channel. Failure of the DRAM can be corrected. The correction capabilities in independent mode are:



Correction of any x4 DRAM device failure.

Detection of 99.986% of all single bit failures that occur in addition to an x4 DRAM failure.

Detection of any 2-bit uncorrectable errors.

4.7.2 Spare Channel Mode

In Spare Channel Mode, Channel 0 and 1 are active channels and Channel 2 is the spare of the other two channels. The spare channel is held in reserve and is not available as system memory.

The spare channel must have identical population to the channel being copied from. This means that all three channels must have identical population with regards to size and organization. DIMM slot populations. The Memory Controller will maintain correctable ECC error counters for each DIMM in the system that can either trigger an SMI event or be periodically polled by software to determine whether a high error rate is happening. SMI software can then configure the Integrated Memory Controller to copy contents from one channel to another.

4.7.3 Mirrored Channel Mode

The Integrated Memory Controller supports mirroring across channels. DIMM organization in each slot of one channel must be identical to the DIMM in the corresponding slot of the other channel. When mirroring is enabled, the memory image in Channel 0 is maintained the same as Channel 1. DIMMs in Channel 2 are not used.

Uncorrectable errors are logged and signaled as correctable, but change the channel state to

"Disabled", and the working partner to Redundancy Loss.

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4.7.4 Lockstep Channel Mode

The Lockstep configuration requires a minimum of two DIMMs one in Channel 0 and Channel

1. Channel 2 is not used in Lockstep Channel Mode. The ECC DRAM on each DIMM is mapped to two adjacent symbols, so any failure of the DRAM can be corrected. The correction capabilities in lockstep mode are:

 Correction of any x4 or x8 DRAM device failure.



Detection of 99.986% of all single bit failures that occur in addition to an x8 DRAM failure.

The Memory Controller will detect a series of failures on a specific DRAM and use this information in addition to the information provided by the code to achieve 100% detection of these cases.

Detection of all permutations of 2 x4 DRAM failures.

4.8 Restoring BIOS Default Settings

The blade provides an on-board configuration switch that allows to load BIOS settings from the

DEFAULT area of the IPMI Boot Parameters. In order to restore the BIOS default settings using this switch, you have to proceed as follows.

Procedure

To restore the BIOS default settings, proceed as follows:

1. Remove the blade from the system.

See

Installing and Removing the Blade

on page 60

for procedure.

2. Set the on-board switch SW4-3 OFF and SW4-4 ON.

See

Switch Settings

on page 53

for location of SW4.

3. Install and power up the blade.

See

Installing and Removing the Blade

on page 60

for procedure.

4. Wait until the blade has completely booted and is up and running.

5. Remove the blade from the system again.

See

Installing and Removing the Blade

on page 60

for procedure.

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6. Set switch SW4-3 and SW4-4 to OFF.

Now the BIOS default settings are restored.

4.9 Shelf Slot Power Requirement

The ATCA-7365-CE blade always requests from the shelf manager to run at full performance

(300 Watt). The system needs to support this for the slot used for the ATCA-7365-CE so that the shelf manager will enable the board at that power level.

In older systems supporting only slots with 200 Watts, the shelf manager may not grant the power level requested and may not enable the board.

4.10 LED Usage

BIOS uses LEDs U1, U2 and U3 on the front panel to indicate activity of start up progress.

In boot loader phase (PEI phase) U1 and U2 glow red, U3 is glowing alternately red, green and orange.

In main initialization phase (DXE phase) only U3 is glowing alternately red, green and orange.

U1 and U2 are set to the default value: base Ethernet interface link and activity LEDs.

Shortly before closing BIOS and starting an operation system, LED U3 is set to OFF.

4.11 Upgrading the BIOS

A BIOS upgrade kit for the blade allows the BIOS to be upgraded. The BIOS upgrade kit contains documentation which describes in detail how to upgrade the BIOS.

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Update tool for Linux is provided with Basic Blade Services (BBS). For details on how to upgrade

BIOS from Linux, please refer to Basic Blade Services Software for the ATCA-7365 Programmer’s

Reference .

The BIOS can also be upgraded via IPMI - HPM.1 (Hardware Platform Management IPM

Controller Firmware Upgrade). Please refer to

Firmware Upgrade

After performing a BIOS upgrade or after restoring a corrupted BIOS image, all BIOS settings are reset to their default values except for parameters that are stored in IPMC storage area.

See Table "System Boot Options Parameter #100 - Supported Parameters" on page 229 .

4.12 BIOS Error Logging

BIOS supports the following methods to report errors:



SMBIOS error logging

IPMI event logging

Error logging to the console

4.12.1 Runtime Error Logging

BIOS supports Runtime Error Logging for memory errors and PCI errors. See BIOS Setup

Advanced -> Runtime Error Logging. Errors are logged to the IPMI controller and to the SMBIOS event log.

The Runtime Error Logging can be enabled or disabled. If enabled, the PCI Error Logging can be enabled or disabled separately.

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For correctable memory error logging, there are two additional parameters to prevent the flooding of the event logs. The parameters are:

 Error Threshold - Correctable memory errors are logged when the threshold is reached.

The first correctable memory error is always logged.

 Error Logging Limit - The number of logged correctable memory errors for a DIMM is limited. If the last entry in the log is SMBIOS: 'Correctable memory log disabled' and IPMI:

Memory event 'Correctable ECC logging limit reached'. No further correctable errors are logged for this DIMM.

Table 4-28 Logged Error Events

Error

Correctable:

- Correctable ECC Memory Error

Correctable:

- Memory Error Limit Reached

- Correctable ECC logging limit reached

Uncorrectable:

- Uncorrectable ECC Memory Error

PCI PERR

SMIBIOS

Single-bit ECC memory error

Correctable memory log disabled

Multi-bit ECC memory error

PCI Parity Error

IPMI

Sensor: Memory, Offset 00h

Sensor: Memory, Offset 05h

Sensor: Memory, Offset 01h

PCI SERR PCI System Error

Sensor: Critical Interrupt,

Offset 04h PCI PERR

Sensor: Critical Interrupt,

Offset 05h PCI SERR

4.12.2 Error Simulation

For test purposes, it is possible to inject errors.

Enable 'Inject Errors' in 'Event Logs' -> 'SMBIOS Event Log Settings' in BIOS setup.

The following errors are injected short before the OS is booted:

 No Console found



IPMI Boot Parameter Checksum error

CPU Self test failure

Bad battery

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These errors are logged to SMBIOS error log, IPMI error log (local SEL and Shelf manager) and to the console.

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4.12.3 IPMI Error Logging

BIOS generates status events like Firmware Progress event and error events.

The table below shows all BIOS supported IPMI Sensors and their possible events.

Table 4-29 BIOS Supported IPMI Events

Sensor

System Firmware

Progress (0Fh)

Event

Offset 00h System Firmware Error

Supported Event Data2:

00h unspecified Error

01h No system memory

02h No usable system memory

03h SATA device failure

07h No console in found

0Ah No console out found

0Bh Firmware ROM corrupted

FDh OEM Error Extension

Supported Event Data3

09h Flash Write Error

21h CPU BIST Error

22h PCI Out Of Resource

50h IPMI Boot Parameter Default Area Read Error

51h IPMI Boot Parameter Default Area Locked

52h IPMI Boot Parameter Default Area Checksum Error

53h IPMI Boot Parameter User Area Read Error

54h IPMI Boot Parameter User Area Locked

55h IPMI Boot Parameter User Area Checksum Error

56h IPMI Boot Parameter User Area Write Error

60h North Bridge Error

62h No Space for Legacy OptionRom

Offset 02h System Firmware Progress

Supported Event Data2:

01h Memory initialization

02h Hard-Disk (SATA) initialization

03h Secondary processor initialization

04h User authentication

05h User-initiated system setup

06h USB configuration

07h PCI configuration

08h Option ROM initialization

09h Video initialization

0Ah Cache initialization

0Ch Console input initialization

13h Starting Operating System

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Table 4-29 BIOS Supported IPMI Events (continued)

Sensor

Memory (0Ch)

Event

Offset 00h Correctable ECC

Offset 01h Uncorrectable ECC

Offset 04h Memory Device Disabled

Offset 05h Correctable ECC error logging limit reached

Offset 06h Presence detected

Offset 07h Configuration Error (Out of order)

Event Data3:

Critical Interrupt (13h)

Boot Error (1Eh)

Battery (29h)

System Firmware

Progress (0Fh)

Bit Description

------------------------------------------------------------------

0-3 DIMM number 1..12

Fh DIMM number unknown

4 DIMM number per Channel 0..1

5-6 DIMM channel 0..2

7 CPU Socket 0..1

Offset 04h PCI PERR

Offset 05h PCI SERR

Event Data2: Bus number

Event Data 3:

Bit Description

----------------------------------------------------------------

0-3 PCI Function number

4-7 PCI Device number

Offset 00h No bootable media (no boot device found)

Offset 01h Battery failed

Offset 00h System Firmware Error

70h Front Panel Network not detected

78h Base Network not detected

79h Base Network reduced PCI performance

7Ah Base Network Device Error

80h Fabric Network not detected

81h Fabric Network reduced PCI performance

82h Fabric Network Device Error

88h Update Channel Network not detected

89h Update Channel Network reduced PCI performance

8Ah Update Channel Network Device Error

90h Reboot after a FRB2 Watchdog Timeout

91h Reboot after a BIOS/POST Watchdog Timeout

92h Reboot after a OS Load Watchdog Timeout

93h Reboot after a SMS/OS Watchdog Timeout

94h Reboot after a OEM Watchdog Timeout

ATCA-7360 Installation and Use (6806800J07S) 123

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4.12.4 SMBIOS Error Logging

See System Management BIOS (SMBIOS) Reference Specification Version: 2.7.0 Chapter 7.16 System

Event Log (Type 15) . The specifications can be downloaded from http://www.dmtf.org/standards/smbios

The event log is a fixed length area in BIOS flash. Information about the SMBIOS event log area can be obtained from the DMI structure System Event Log Type 15. The DMI table can be read by the Linux tool dmidecode

The "Log Change Token" in SMBIOS Type 15 structure is not supported.

The following SMBIOS Events are supported:



Single-bit ECC memory error

Multi-bit ECC memory error



POST Error

PCI Parity Error

PCI System Error

CPU Failure



Correctable memory log disabled

Log Area Reset/Cleared

System boot

OEM Event: "EFI Status code"

See System Management BIOS (SMBIOS) Reference Specification Version: 2.7.0 Chapter 7.16.6.1

Event Log Types .

124 ATCA-7360 Installation and Use (6806800J07S )

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4.12.4.1 Single-bit ECC Memory Error

This event is generated from the runtime error logging module. See Runtime Error Logging on page 119 .

Table 4-30 Single-bit ECC Memory Error event format

Offset

00h

01h

02h-07h

Name

Event Type

Length

Date/Time Fields

Format

BYTE

08h-0Bh Memory Information UINT32

Description

Event Type = 01h always 0Ch

These fields contain the BCD representation of the date and time

OEM extension

Table 4-31 Memory Information Definition

Bit

0-7

8-15

16-23

24-31

Description reserved

DIMM number per Channel 0..1

DIMM channel 0..2

CPU Socket 0..1

4.12.4.2 Multi-bit ECC Memory Error

This event is generated from the runtime error logging module. See Runtime Error Logging on page 119 .

Table 4-32 Multi-bit ECC Memory Error Event Format

Offset

00h

01h

Name

Event Type

Length

Format

BYTE

Description

Event Type = 02h always 0Ch

ATCA-7360 Installation and Use (6806800J07S) 125

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Table 4-32 Multi-bit ECC Memory Error Event Format (continued)

Offset

02h-07h

08h-0Bh

Name

Date/Time Fields

Memory Information

Format

BYTE

UINT32

Description

These fields contain the BCD representation of the date and time

OEM extension

Table 4-33 Memory Information Definition

Bit

0-7

8-15

16-23

24-31

Description reserved

DIMM number per Channel 0..1

DIMM channel 0..2

CPU Socket 0..1

4.12.4.3 POST Error

If an error has occurred during the BIOS phase, a POST Error event is generated. There is only one POST Error event per boot generated.

A set bit at a Result DWORD bit position implies that the error associated with that position has occurred. If there was a error which has no corresponding bit in the Result DWORDs, the bit 0 form the Second DWORD is set (OEM: Unspecified Error).

Table 4-34 POST Error Event Format

Offset

00h

01h

02h-07h

Name

Event Type

Length

Date/Time Fields

08h-0Bh

0Ch-0Fh

Result First DWORD

Result Second DWORD

Format

BYTE

UINT32

Description

Event Type = 02h always 0Ch

These fields contain the BCD representation of the date and time

See

Table 4-35 on page 127

See

Table 4-36 on page 127

126 ATCA-7360 Installation and Use (6806800J07S )

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Table 4-35 Result First DWORD supported POST Errors

Bit

Description

CMOS RAM Battery Failure. Battery is bad, removed or replaced

Keyboard Not Functional. No console input device found or device error

Memory Decreased in Size. DIMM errors during memory initialization found.

Failed DIMM disabled

RTC Time Not Set. Found invalid Date/Time. Date/Time reset to a valid default value.

OEM: IPMI failure

OEM: IPMI Boot Parameter read/write error

OEM: IPMI Boot Parameter checksum error

OEM: IPMI Boot Parameter locked

Table 4-36 Result Second DWORD supported POST Errors

Bit

Description

OEM: unspecified error

OEM: North Bridge error

OEM: CPU error. This bit will be set additionally when a SMBIOS CPU Failure event is logged.

Front Panel Network Error

Base Network Error

Fabric Network Error

Update Channel Network Error

PCI Memory Conflict

Static Resource Conflict e.g. No Space for OPROM

System Board Device Resource Conflict

Primary Output Device Not Found

NVRAM Data Invalid. Flash write error

ATCA-7360 Installation and Use (6806800J07S) 127

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4.12.4.4 PCI Parity Error

This event is generated from the runtime error logging module. See Runtime Error Logging on page 119 .

Table 4-37 PCI Parity Error Event Format

Offset

00h

01h

02h-07h

Name

Event Type

Length

Date/Time Fields

Format

BYTE

08h-0Bh PCI Information UINT32

Description

Event Type = 09h always 0Ch

These fields contain the BCD representation of the date and time

OEM extension

PCI Information Definition:

Table 4-38 PCI Information Definition

Bit

0-7

8-15

16-23

24-31

Description reserved

PCI Function

PCI Device

PCI Bus number

128 ATCA-7360 Installation and Use (6806800J07S )

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4.12.4.5 PCI System Error

This event is generated from the runtime error logging module. See Runtime Error Logging on page 119 .

Table 4-39 Multi-bit ECC Memory Error Event Format

Offset

00h

01h

02h-07h

Name

Event Type

Length

Date/Time Fields

Format

BYTE

08h-0Bh PCI Information UINT32

Description

Event Type = 0Ah always 0Ch

These fields contain the BCD representation of the date and time

OEM extension

Table 4-40 Memory Information Definition

Bit

0-7

8-15

16-23

24-31

Description reserved

PCI Function

PCI Device

PCI Bus number

4.12.4.6 CPU Failure

This error is generated when a CPU Built In Self Test error has occurred.

Table 4-41 CPU Failure Event Format

Offset

00h

01h

02h-07h

Name

Event Type

Length

Date/Time Fields

Format

BYTE

Description

Event Type = 0Bh always 0Ch

These fields contain the BCD representation of the date and time

ATCA-7360 Installation and Use (6806800J07S) 129

BIOS

4.12.4.7 Correctable Memory Log Disabled

This event is generated from the runtime error logging module. It is logged when the

Correctable Memory Error logging limit for the DIMM is reached. No further error events for this DIMM are logged.

See Runtime Error Logging on page 119 .

Table 4-42 Correctable Memory Log Disabled Event Format

Offset

00h

01h

02h-07h

Name

Event Type

Length

Date/Time Fields

Format

BYTE

08h-0Bh Memory Information UINT32

Description

Event Type = 01h always 0Ch

These fields contain the BCD representation of the date and time

OEM extension

Table 4-43 Memory Information Definition

Bit

0-7

8-15

16-23

24-31

Description reserved

DIMM number per Channel 0..1

DIMM channel 0..2

CPU Socket 0..1

4.12.4.8 Log Area Reset/Cleared

This log entry is the first entry in the SMBIOS log.

Table 4-44 Log Area Reset/Cleared Event Format

Offset

00h

01h

02h-07h

Name

Event Type

Length

Date/Time Fields

Format

BYTE

130

Description

Event Type = 16h always 08h

These fields contain the BCD representation of the date and time

ATCA-7360 Installation and Use (6806800J07S )

BIOS

4.12.4.9 System Boot

This log entry is the first entry on a system boot.

Table 4-45 System Boot Event Format

Offset

00h

01h

02h-07h

Name

Event Type

Length

Date/Time Fields

Format

BYTE

Description

Event Type = 17h always 08h

These fields contain the BCD representation of the date and time

4.12.4.10 OEM Event EFI Status Code

EFI status codes are logged when "Convert OEM Codes" in "Smbios Event Log Settings" BIOS setup menu is set to disabled. In this case, no SMBIOS POST Error Event and no CPU Failure

Events are generated.

Table 4-46 System Boot Event Format

Offset

00h

01h

02h-07h

Name

Event Type

Length

Date/Time Fields

08h-0Bh

0Ch-0Fh

10h-13h

Status Code Type

Status Code Value

Instance

Format

BYTE

UINT32

Description

Event Type = E0h always 14h

These fields contain the BCD representation of the date and time

Error Code Severity

Error Code Value

Additional Information e.g. DIMM Socket number

ATCA-7360 Installation and Use (6806800J07S) 131

BIOS

For a detailed description of the Status Code Type and the Status Code Value please refer to

Intel Platform Innovation Framework for EFI Status Codes Specification Version 0.92. The specifications can be downloaded from http://www.intel.com/technology/framework/download.htm

Table 4-47 Status Code Type Definition

Bit

0-7

8-23

24-31

Description

Type: 2 = Error Code reserved

Severity: 4 = Minor, 8 = Major

Table 4-48 Status Code Value Definition

Bit Description

0-15 Operation code

16-23 SubClass code

24-31 Class code

Table 4-49 Class Code

Bit

Description

Computing Unit

Peripheral

IO-Bus

Software

4.12.4.10.1Artesyn OEM Extensions

Class Computing Unit:

Table 4-50 SubClass EFI_COMPUTING_UNIT_CHIPSET (06h)

Operation Code Description

800Bh Bad Battery

132 ATCA-7360 Installation and Use (6806800J07S )

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Table 4-50 SubClass EFI_COMPUTING_UNIT_CHIPSET (06h) (continued)

Operation Code Description

800Dh North Bridge Error

Table 4-51 SubClass EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR (02h) (IPMI)

Operation Code Description

8100h IPMI Boot Parameter USER area read error

8101h

8102h

IPMI Boot Parameter DEFAULT area read error

IPMI Boot Parameter USER area write error

8103h

8104h

8105h

8106h

8107h

IPMI Boot Parameter DEFAULT area write error

IPMI Boot Parameter USER area checksum error

IPMI Boot Parameter DEFAULT area checksum error

IPMI Boot Parameter USER area locked

IPMI Boot Parameter DEFAULT area locked

4.13 BIOS Status Codes

The following tables list the BIOS status codes applicable to the used AMI UEFI BIOS. The BIOS status codes are written to the blade's I/O Port 80 register and can be obtained by reading the

"POST code" on-board IPMI sensor. The reading of the "POST code" sensor is only valid when the board is in the BIOS phase. The reading can be used to locate the cause of a board hang during

BIOS phase. When the board has booted a OS, the reading of the '"POST code" sensor returns no valid status code.

ATCA-7360 Installation and Use (6806800J07S) 133

BIOS

4.13.1 Status Code Ranges

Table 4-52 Status Code Ranges

Status Code Range

0x01 – 0x0F

0x10 – 0x2F

0x30 – 0x4F

0x50 – 0x5F

0x60 – 0xCF

0xD0 – 0xDF

0xE0 – 0xE8

0xE9 – 0xEF

0xE8 - 0xEF

0xB0 - 0xBF

0xE8 - 0xEE

Description

SEC Status Codes & Errors

PEI execution up to and including memory detection

PEI execution after memory detection

PEI errors

DXE execution up to BDS

DXE errors

S3 Resume (PEI)

S3 Resume errors (PEI)

Memory initialization errors

Additional Memory Initialization Status Codes

Additional Memory Error Status Codes

4.13.2 Standard Status Codes

134

Table 4-53 SEC Status Codes

Status Code Description

Progress Codes

0x1

0x2

0x3

0x4

Power on. Reset type detection (soft/hard).

AP initialization before microcode loading

North Bridge initialization before microcode loading

South Bridge initialization before microcode loading

ATCA-7360 Installation and Use (6806800J07S )

BIOS

Table 4-53 SEC Status Codes (continued)

Status Code

0x5

0x6

0x7

0x8

0x9

0xA

0xB

SEC Error Codes

0xC – 0xD

0xE

0xF

Description

OEM initialization before microcode loading

Microcode loading

AP initialization after microcode loading

North Bridge initialization after microcode loading

South Bridge initialization after microcode loading

OEM initialization after microcode loading

Cache initialization

Reserved for future AMI SEC error codes

Microcode not found

Microcode not loaded

Table 4-54 PEI Status Codes

Status Code

Progress Codes

0x10

0x15

0x19

0x2F

0x31

0x32

0x33

0x34

0x35

0x36

Description

PEI Core is started

Pre-memory North Bridge initialization is started

Pre-memory South Bridge initialization is started

Memory initialization (other)

Memory Installed

CPU post-memory initialization is started

CPU post-memory initialization. Cache initialization

CPU post-memory initialization. Application Processor(s)

(AP) initialization

CPU post-memory initialization. Boot Strap Processor

(BSP) selection

CPU post-memory initialization. System Management

Mode (SMM) initialization)

ATCA-7360 Installation and Use (6806800J07S) 135

BIOS

136

Table 4-54 PEI Status Codes (continued)

Status Code

0x37

Description

Post-Memory North Bridge initialization is started

0x3B

0x3F-0x4E

Post-Memory South Bridge initialization is started

OEM post memory initialization codes

0x4F

Memory Initialization Codes

DXE IPL is started

0xB1

0xB2

0xB3

0xB4

0xB5

0xB6

0xB7

0xB8

0xB9

0xBA

0xBB

0xBF

PEI Error Codes

0x53

0x55

0x56

0x57

0x58

0x59

0x5A

Detect reset state

DIMM detect

Clock initialization

Read SPD data early memory controller initialization

Check DIMM population

Channel initialization

Channel training

Run Build In Self Test

Initialize memory map

Setup RAS configuration

Memory initialization complete

Memory initialization error. No usable memory detected

Memory not installed

Invalid CPU type or Speed

CPU mismatch

CPU self test failed or possible CPU cache error

CPU micro-code is not found or micro-code update is failed

Internal CPU error

ATCA-7360 Installation and Use (6806800J07S )

BIOS

Table 4-54 PEI Status Codes (continued)

Status Code

0x5B

Memory Error Codes

0xE8

0xEA

0xEB

0xED

0xEE

Recovery Progress Codes

0xF0

0xF1

0xF2

0xF3

0xF4

0xF5-0xF7

Recovery Error Codes

0xF8

0xF9

0xFA

0xFB – 0xFF

Description

Reset PPI is not available

No Memory

DDR initialization error

Memory test error

Mixed memory types

Population error

Recovery condition triggered by firmware (Auto recovery)

Recovery condition triggered by user (Forced recovery)

Recovery process started

Recovery firmware image is found

Recovery firmware image is loaded

Reserved for future AMI progress codes

Recovery PPI is not available

Recovery capsule is not found

Invalid recovery capsule

Reserved for future AMI error codes

Table 4-55 DXE Status Codes

Status Code

0x60

0x61

0x62

0x63

0x68

Description

DXE Core is started

NVRAM initialization

Installation of the South Bridge Runtime Services

CPU DXE initialization is started

PCI host bridge initialization

ATCA-7360 Installation and Use (6806800J07S) 137

BIOS

138

Table 4-55 DXE Status Codes (continued)

0x9C

0x9D

0xA0

0xA1

0xA2

0xA3

0x94

0x95

0x96

0x97

0x98

0x99

0x9A

0x9B

0x78

0x79

0x80

0x81

0x90

0x91

0x92

0x93

Status Code

0x69

0x6A

0x70

0x71

0x72

Description

North Bridge DXE initialization is started

North Bridge DXE SMM initialization is started

South Bridge DXE initialization is started

South Bridge DXE SMM initialization is started

South Bridge devices initialization

ACPI module initialization

CSM initialization

IPMI Boot Parameter Initialization

Initialize Boot Variables

Boot Device Selection (BDS) phase is started

Driver connecting is started

PCI Bus initialization is started

PCI Bus Hot Plug Controller Initialization

PCI Bus Enumeration

PCI Bus Request Resources

PCI Bus Assign Resources

Console Output devices connect

Console input devices connect

Super IO Initialization

USB initialization is started

USB Reset

USB Detect

USB Enable

IDE initialization is started

IDE Reset

IDE Detect

IDE Enable

ATCA-7360 Installation and Use (6806800J07S )

BIOS

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

0xB3

0xB4

0xB5

0xB6

0xB7

DXE Error Codes

0xD0

0xD1

0xA9

0xAB

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

Status Code

0xA4

0xA5

0xA6

0xA7

0xA8

Table 4-55 DXE Status Codes (continued)

Description

SCSI initialization is started

SCSI Reset

SCSI Detect

SCSI Enable

Setup Verifying Password

Start of Setup

Setup Input Wait

Ready To Boot event

Legacy Boot event

Exit Boot Services event

Runtime Set Virtual Address MAP Begin

Runtime Set Virtual Address MAP End

Legacy Option ROM Initialization

System Reset

USB hot plug

PCI bus hot plug

Clean-up of NVRAM

Configuration Reset (reset of NVRAM settings)

CPU initialization error

North Bridge initialization error

South Bridge initialization error

Some of the Architectural Protocols are not available

PCI resource allocation error. Out of Resources

No Space for Legacy Option ROM

No Console Output Devices are found

No Console Input Devices are found

ATCA-7360 Installation and Use (6806800J07S) 139

BIOS

Table 4-55 DXE Status Codes (continued)

Status Code

0xD8

0xD9

0xDA

0xDB

0xDC

Description

Invalid password

Error loading Boot Option (LoadImage returned error)

Boot Option is failed (StartImage returned error)

Flash update is failed

Reset protocol is not available

140 ATCA-7360 Installation and Use (6806800J07S )

Chapter 5 Functional Description

5.1 Block Diagram

The block diagram shows how the devices work together and which data paths they use.

Figure 5-1 Block Diagram

DDR3

Xeon L5518

QPI

Xeon L5518

DDR3

QPI QPI

6 x DDR3 socket 6 x DDR3 socket

Intel 5520 Chipset

10/100/1000Base-T

PMEM/SATA Module

PCI/SATA

SATA

USB2.0 ICH10

Port 0+2

4GB

SSD

USB2.0

ICH10 Port 6

SPI

PHY

82567

ICH10

ESI

PCIe x4

PCIe x8

82599

(Niantic)

82576

Kawela

SPI

Debug

Socket

Rec.

SPI

LPC

82572

USB2.0 ICH10 Port8

COM_RTM,RST

PCIe x4

CLK-

INTERRUPT

2x 10GBase-BX4

2x 1000Base-BX

1000Base-BX

2x 10/100/1000Base-T

SMB: Serial over LAN Pass Through

COM

COM_RTM

FPGA

COM_IPMC

Port80

LED

KCS

IPMC

RS232

3.3V

12V

-48V

FUSING.

EMI,

INRUSH,

5 ms holdup

Zone 1

Zone 3

P30

P31

P32

Zone 2

P20 5x UC

P21

P22

ATCA3.1 Option1,9

Fabrif IF

P23

ATCA3.0 Base IF

P24

IPMB-A/B

ATCA-7360 Installation and Use (6806800J07S) 141

Functional Description

5.2 Processor

ATCA-7360 provides two Intel Xeon L5518 Quadcore processors as central processing unit

(CPU). Both CPUs are based on 45 nm process technology and provide the following main features:

 2.13GHz core frequency



32 KB instruction cache per core

32 KB L1 data cache per core

256 KB L2 cache per core

16 KB data and instruction cache

The processor features two Intel QuickPath Interconnect point-to-point links capable of up to

5.86 GT/s, 8 MB of shared Last Level cache (L3), and an Integrated Memory Controller (IMC).

The processor support all the existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD

Extensions 3 (SSE3) and Streaming SIMD Extensions 4 (SSE4). The processor supports several

Advanced Technologies: Execute Disable Bit, Intel 64 Technology, Enhanced Intel SpeedStep

Technology, Intel Virtualization Technology (Intel VT), and Simultaneous Multi Threading

(SMT).

5.3 Memory

The Xeon L5518 CPU features an integrated memory controller. The memory controller provides three memory channels that allow flexible memory configurations. DDR3 DIMM technology is exclusively supported. Different types of memory modules can be installed including registered DIMMs with ECC and un-buffered DIMMs with either ECC or non-ECC. The

DIMM speeds can be either DDR3-800, DDR3-1066 or DDR3-1333. DIMMs of different speed selections can coexist but the lowest speed selection will determine the used speed for all memory channels. Note that not all processor variants support all three memory clock speeds.

142 ATCA-7360 Installation and Use (6806800J07S )

Functional Description

5.3.1 Persistent memory

The Blade supports a persistent memory. The persistent memory (PMEM Module) is an array of random access memory that preserves its contents during a payload reset. The memory is mapped into the memory address range of the CPU. Persistent memory is a necessary prerequisite for performing postmortem analysis of log data after reset and reboot of the payload CPU.

5.4 Chipset

The Intel 5520 chipset provides access between the two processors and the I/O subsystem. The chipset provides up to 36 PCI Express generation two lanes. The Blade makes use of 5 times four

PCIe lanes routed to the Zone 3 connector.

The chipset is connected to the ICH10R I/O Controller via the Enterprise South Bridge Interface

(ESI).

5.5 I/O Controller

The ICH10R provides extensive I/O interface support and the BOOT path to SPI Boot Flash devices for the processor. ICH10R is connected to the system through the Enterprise

Southbridge Interface (ESI) of the Xeon 5520 chipset.

The following is a list of the main internal features and the I/O interface functions provided by the ICH10R Southbridge.



Six x4 PCI Express 1.1 Interface

LPC interface



SPI Interface (Boot Flash): up to two devices 20 + 33 MHz

Six serial ATA (SATA) interfaces (2 used on ATCA-7360)

Twelve USB 2.0 interfaces (4 used on ATCA-7360)

Two 8259 Interrupt Controllers and I/O APIC controllers

Integrated I/O APIC

Power management support

ATCA-7360 Installation and Use (6806800J07S) 143

Functional Description



Two 8237 DMA controller

8254 based Counter Timer/timers

High precision Event timers (HPET)

RTC with 256-byte battery-backed SRAM

System TCO (total cost of ownership) Reduction circuits

SMBus interface

Two stage Watchdog timer

PCI 2.3 interface 32-bit/ 33 MHz (connects to PMEM module)

General purpose I/O pins

ATCA-7360 does not provide a legacy Super-I/O device and no legacy Keyboard/Mouse interface. Keyboard and Mouse are supported through USB. Serial COM Interfaces are provided from FPGA.

5.6 Firmware Flashes

The blade has two physically separate 1 MB flash devices hosting the BIOS firmware:

 Primary (or Default BIOS) Flash (SPI 0)

 Recovery BIOS Flash (SPI 1)

The flash is allocated for storing the binary code of the BIOS. The ATCA-7360 boots from the primary flash SPI 0 under normal circumstances. If booting BIOS from primary flash SPI 0 fails, a hardware mechanism automatically changes the flash device select logic to boot from the recovery flash SPI 1. The image that the processor will boot from after next reset is determined by the IPMC. It can be selected via dedicated IPMI OEM command.

144 ATCA-7360 Installation and Use (6806800J07S )

Functional Description

5.7 Ethernet Ports

The blade utilizes various Ethernet controllers that serve the ATCA Base I/F, Fabric I/F, Update

Channel and Ethernet console. All Ethernet interfaces have 1GbE capability except for the

Fabric I/F controller which can operate at 10 GbE or 1 GbE (PICMG 3.1 Option 9 and 1). The fabric I/F is fully operable in both 10 G and 1 G mode without the presence of an RTM.

One Ethernet port is available on the front panel. Additional Ethernet ports for external access are provided via the RTM.

The Ethernet controllers support I/O virtualization.

Table 5-1 Ethernet Controller Types

Interface

Base Interface

Location Controller

P23 Intel 82576

Intel 82599

Intel 82567

Update Channel IF P20 Intel 82572

Count

2 x

1 x

Ethernet Type

10,100,1GB copper

10G/1G Serdes

10,100,1 GB Copper

1 GB Serdes

5.8 Storage Controller

Using an optional RTM, the blade provides a Serial Attached SCSI (SAS) controller. One onboard hard disk drive located on the RTM is connected to the controller. A minimum of two (2) ports are available on the RTM faceplate. They can be used to attach an external storage RAID

(JBOD). Another SAS port of the controller is routed to ATCA Zone 3 for the purposes of synchronizing with a RTM based disk located in a logically paired ATCA slot.

5.9 Embedded Flash Disk

The ATCA-7360 by default, provides an onboard USB Flash module (4GB) solid state disk. The disk can keep data, application SW and OS boot images. Booting from the device is supported.

The flash disk controller provides a wear leveling algorithm to improve the longevity of the flash device.

ATCA-7360 Installation and Use (6806800J07S) 145

Functional Description

5.9.1 SATA Embedded Flash Solid State Disc (SSD)

As an option, a SATA embedded flash SSD solution can be provided through assembly of the

ATCA-7360/SATA module which is available as an accessory kit.

5.10 BIOS

The ATCA-7360 blade provides a BIOS firmware that is stored in flash memory. It can be updated remotely via Ethernet or locally via operating system. Along with the BIOS and BIOS

Setup program, the flash memory contains POST and Plug and Play support.

The BIOS displays a message during POST identifying the type of BIOS and a revision code.

A BIOS extension is provided for the RTM based SAS controller to support RAID configuration.

5.11 IPMC

The blade features an Intelligent Platform Management Controller (IPMC) compliant to PICMG

3.0 and IPMI 1.5 and 2.0 (SOL only). The IPMC is a management subsystem providing monitoring, event logging, and recovery control. The IPMC serves as the gateway for management applications to access the payload hardware.

The IPMC firmware (FW) is stored in two independent memory images. Crisis recovery control is provided to allow reboot of the IPMC from a 2nd image if the upgraded FW image is corrupted. FW images can be upgraded via HPM.1/IPMI using either IPMB or KCS interface.

The IPMC supports the initiation of a graceful shutdown of the host CPU. The IPMC can force the CPU to reset.It also controls the power and reset of the payload. As part of the power control logic, circuitry is provided that controls the correct power-up and power-down sequencing of all payload specific power domains to prevent latch-up and damage of devices.

The IPMC provides a watchdog that supervises the payload. If enabled, the payload software needs to re-trigger the Watchdog to prevent a time-out. A watchdog time-out can generate a

NMI, a payload reset or disabling/cycling of the payload power. The watchdog settings, including enable/disable, can be changed by payload software (setup menu). Time-out values can be selected from as short as seconds to as long as minutes.

The IPMC is supervised by a separate hardware Watchdog, which can not be disabled. IPMC FW re-triggers the Watchdog timer.

146 ATCA-7360 Installation and Use (6806800J07S )

Functional Description

The IPMC monitors the Port 80 POST codes generated by the payload CPU. The IPMC is connected to various sensors on the blade that provide temperature sensor readings at all major devices and voltage sensor readings of all major voltages. The IPMC monitors reset events caused by devices like Watchdog, IPMI command, and reset button.

The FRU information of the various modules including front board, RTM, and other modules can be read via the IPMC and if necessary upgraded thru the IPMC.

The IPMC features Serial over LAN (SOL) for the payload CPU serial console. The SOL interface is available via the ATCA Base I/F. SOL is activated by specific IPMI commands.

5.12 Serial Redirection

The CPU serial redirection reroutes the console input and output; that is the text output to the text screen and input from the standard keyboard. The console typically is used by the BIOS setup menus, BIOS initialization and boot routines, OS boot loaders and loaded OS.

The serial console of the payload CPU is available via SOL. In addition to the SOL capability the serial console is also available on the blade faceplate using a RJ45 connector with Cisco pin-out.

If a SOL session is established, only the output is available on the faceplate. Input is not possible during this time via the faceplate. Alternatively to the CPU serial console, the IPMC serial console is also available on the faceplate serial connector. It can be selected via specific IPMI

OEM command.

5.13 Serial Over LAN

Serial Over LAN (SOL) enables suitably designed blades and servers to transparently redirect a serial character stream of a baseboard UART to/from a remote client via LAN over RMCP+ sessions. This enables users at remote consoles to access the serial port of a blade/server and interact with a text-based BIOS console, operating system, command line interfaces, and serial text-based applications.

ATCA-7360 Installation and Use (6806800J07S) 147

Functional Description

The IPMC provides a dedicated sideband connection to the Base Interface Ethernet controller.

This connectivity is not shared with IPMB-0 or any other I2C/SMBus/IPMB connections that the

IPMC may use on the blade for hardware management. Data from the payload serial redirection is routed through the sideband connection to the Base I/F. Vice versa the Ethernet controller filters packets based on either MAC address, RMCP port number, or IP address and forwards them to the serial redirection over the sideband interface. Alternatively routing of

SOL via PCIe may be considered if feasible by design.

Client software like openIPMI is required to enable SOL and to communicate with the SOL based serial console.

5.14 Control Logic

The blade provides control logic for specific functions including:

 Payload power supervision and sequencing



Payload resets

Multiple HW interfaces between payload and IPMC

Support for sensors as required

Any control circuitry based on programmable logic whether intended for payload supervision or as part of the payload is remotely upgradeable. Crisis recovery circuitry is provided to prevent board lock-ups as the result of a failed remote upgrade of the board control logic.

5.15 Front Board Faceplate

The blade's faceplate provides the following interfaces and control elements:



Two USB 2.0 ports

Serial console port to connect to either payload or IPMC serial I/F



Out of Service, In Service, Attention, and Hot Swap LEDs

One 1000Base-T Ethernet port

Recessed reset button

The blade design provides the possibility to cover unused faceplate elements like LEDs or push button behind a custom overlay foil.

148 ATCA-7360 Installation and Use (6806800J07S )

Functional Description

5.16 USB 2.0 Interface

The ICH10R provides internal USB1.1/ USB 2.0 host controllers with up to twelve USB 2.0 ports.

Two ports are routed to the faceplate, one port is used on-board to connect a USB 2.0 SSD User

Flash Module and one port is routed to the RTM. The ports available at the faceplate are routed to a dual stacked connector. The ports are USB 2.0 compliant.

5.17 SMBus Interface

The SMBus interface of the ICH10R is connected to on-board devices like Clock PLL’s, temperature sensors and the SPD PROMs of all twelve DDR3 DIMM memory modules. I 2 C Bus

Repeater of type PCA9515 is used to buffer the SMBus portion going to the SPD PROMs on the

DIMM. The BIOS reads memory configuration parameters from SPD PROM. To address more than 8 memory I2C devices, the SMBus to the SPD PROMS is segmented.

Table 5-2 SMBus Devices

Device Name

SPD EEPROM

Temp Sens#0

Temp Sens#1

DDR3 VREF_D margining

24C02

LM75

ISL90728

Device Type

24C02

Address

1010.000x b=A0

1010.001x b=A2

1010.010x b=A4

1010.011x b=A6

1010.100x b=A8

1010.101x b=AA

1010.000x b=A0

1010.001x b=A2

1010.010x b=A4

1010.011x b=A6

1010.100x b=A8

1010.101x b=AA

0x90

0x92

0x7C

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Table 5-2 SMBus Devices (continued)

Device Name

DDR3 VREF_D margining

Clock

DB1200 clock

CK_MNG_133

ICH10R Slave SMBus IF

Xeon 5520 (Tylersburg IOH36 D) Slave

SMBus IF

MAX6618 PECI

Hub

Device Type

ISL90727

ICS932S421

ICS9DB1200

ICS9FGP202

ICH10R

Xeon 5520 (Tylersburg

IOH36 D)

MAX6618

Address

0x5C

0xD2 + 0xD3

0xDC + 0xDD

0xD0 + 0xD1

0x88 + 0x89

0xE0 (IOH Boostrap

SMBUSID option is 0xC0)

0x54

5.18 Real Time Clock

An external 32.768 kHz crystal sources the internal real time clock inside ICH10R with a frequency tolerance of 20 PPM. The RTC is fully DS1287, MC14618, PC87911 and Y2K compliant and provides 256 bytes of backed up CMOS RAM (of which 14 bytes containing the

RTC time and date info and RTC configuration). During power-down, the RTC consumes 0.9 uA/hr. The optional power-down backup method uses a Super CAP with a 1 Farad capacity. This provides 300 hours of RTC/SRAM backup. The default battery is an external +3 V lithium battery with a capacity of 200 mAh, which provides 3 years of backup.

150 ATCA-7360 Installation and Use (6806800J07S )

Chapter 6 Maps and Registers

6.1 Interrupt Structure

The ATCA-7360 supports NON-APIC (legacy PIC Mode) and APIC mode of Interrupt delivery to the CPUs. The 8259 PIC mode interrupt concentrator inside the ICH10R supports 16 interrupts

(8 external signal inputs). The IO-APIC device inside the ICH10R supports 24 interrupt sources.

In APIC mode the ICH10R supports only front side bus interrupt delivery (not the serial APIC mode). The following figure and tables summarize the interrupt sources and mappings for

ATCA-7360 blade. APIC mode is configured through BIOS after boot-up phase which is done in legacy PIC mode.

Figure 6-1 Interrupt Structure on ATCA-7360

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152

Table 6-1 Non-APIC (PIC mode / 8259 Mode) Interrupt Mapping

Master

Slave

8259

IRQ Typical Interrupt Source

Internal

Keyboard

Internal

Serial Port A

Serial Port B

Parallel/Generic

Floppy

Parallel/Generic

Internal RTC

Generic

PS/2 Mouse

Internal

SATA

Interrupt Source

8254 Counter 0, Timer 0 (HPET)

IRQ1 via SERIRQ

Slave 8259 INTR output

IRQ3 via SERIRQ, PIRQ#

IRQ4 via SERIRQ, PIRQ#

IRQ5 via SERIRQ, PIRQ#

IRQ6 via SERIRQ, PIRQ#

IRQ7 via SERIRQ, PIRQ#

Internal RTC, Timer 1 (HPET)

IRQ9 via SERIRQ, SCI, TCO, or PIRQ#

IRQ10 via SERIRQ, SCI, TCO, or PIRQ#

IRQ11 via SERIRQ, SCI, TCO, or PIRQ# or

Timer#2 (HPET)

IRQ11 via SERIRQ, SCI, TCO, or PIRQ# or

Timer#3 (HPET)

State Machine output based on processor

FERR# assertion. May optionally be used for SCI or TCO interrupt if FERR# not needed.

SATA Primary (legacy mode), or via SERIRQ or

PIRQ#

SATA Secondary (legacy mode), or via SERIRQ or

PIRQ#

Table 6-2 APIC Mode Interrupt Mapping

IRQ

Interrupt Source

Cascade from 8259 1

8254 Counter 0, Timer 0 (legacy mode)

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Table 6-2 APIC Mode Interrupt Mapping (continued)

IRQ

Interrupt Source

RTC, Timer 1 (legacy mode)

Option for TCI, TCO

Timer 2, Option for TCI, TCO

Timer 3

FERR# logic

SATA Primary (legacy mode)

SATA Secondary (legacy mode)

PIRQ[A]#

PIRQ[B]#

PIRQ[C]#

PIRQ[D]#

PIRQ[E]# (GPIO)

PIRQ[F]# (GPIO)

PIRQ[G]# (GPIO)

PIRQ[H]# (GPIO)

In APIC mode the PCI Interrupts A:H are mapped to IRQ[16:23].

If an interrupt is used for PCI IRQ[A:H], SCI or TCO it must not be used for ISA (legacy)-style interrupts (via SERIRQ).

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6.2 PCI Express Port Mapping

Xeon 5520 (Tylersburg IOH36 D) PCI express ports have the naming convention as seen in

Figure 6-2 on page 154

Table 6-3 PCIexpress Port mapping

Port# 1 2 3 4 5 6 7 8 9 10 x2 x2 x4 x4 x4 x4 x4

x8 x8 x8 x4 x4

x16 x16 x4

Figure 6-2 IOH36D PCIe Port mapping on ATCA-7360

6.3 Registers

For register description the convention shown in

Table 6-4 Register Default and Table 6-5

Table 6-4 Register Default

Default

Description

Not applicable or undefined

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Table 6-4 Register Default (continued)

Default

0 or 1

Description

Default value after PWR_GOOD is valid or after ICH_PLTRST deassertion.

<reset>: 0 or 1

Ext.

Default value after deassertion of the reset signal <reset>.

External Reset Source. Default depends on external logic level.

Table 6-5 Register Access Type

Access Description r/w w1c r/w1c r/w1s r/w1t

LPC:

IPMC:

Read and write

Write-1-to-clear, ignore bit while reading

Read and write-1-to-clear, write 0 has no effect

Read and write-1-to-set, write 0 has no effect

Read and write-1-to-toggle, write 0 has no effect

The prefix “LPC:” signals that the access is restricted to the LPC interface.

E. g.: LPC: r/w means that the register bit is read/writable from the

LPC interface

The prefix “IPMC:” signals that the access is restricted to the IPMC

SPI interface.

For example, IPMC: r/w means that the register bit is read/writable from IPMC SPI interface

6.3.1 Register Decoding

The FPGA registers may be accessed from the host or the IPMC. For the host the LPC bus interface is used. The IPMC uses an SPI interface.

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6.3.1.1

LPC Decoding

The LPC bus supports different protocols.

6.3.1.1.1 LPC I/O Decoding

The LPC interface responds to LPC I/O accesses listed in

Table 6-6

. All other LPC I/O accesses are ignored.

Table 6-6 LPC I/O Register Map Overview

Base Address

0x4E

Address

Size

Address Range

Name

SIW

0x80

BASE1

BASE2

0x600

128

POSTCODE

COM1

COM2

REGISTERS

Description

Super IO Configuration Registers for Index and

Date

POST Code Register

UART1. Serial Port 1 (Logical Device 4). BASE1 address is set up during Super IO Configuration.

UART2. Serial Port 2. (Logical Device 4). BASE2 address is set up during Super IO Configuration.

FPGA Registers

All LPC I/O accesses to address POSTCODE, within the address range REGISTERS and within the address ranges of COM1 or COM2 (only when enabled during Super IO configuration) are decoded by the LPC core.

6.3.1.1.2 LPC Memory Decoding

The LPC interface never responds to LPC Memory accesses.

6.3.1.1.3 LPC Firmware Decoding

The LPC interface never responds to LPC Firmware accesses.

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6.3.1.2

SPI Register Decoding

All SPI accesses from the IPMC towards the FPGA with the SPI select signal IPMC_SPI_SS_FPGA_ asserted are accepted.

Table 6-7 IPMC SPI Register

SPI Address Range

0x00 – 0x7F

Address Range Name

REGISTERS

Description

FPGA Registers

6.3.2 POST Code Register

The FPGA provides an 8 bit wide register to store POST codes to the LPC I/O address 0x80. The two nibbles of the register are converted to 7 segment codes and are displayed as two hex values by two 7 segment LED Displays.

The IPMC may read the POST code using the SPI interface (with the signal IPMC_SPI_SS_FPGA_ asserted) and the SPI address 0x7F.

Table 6-8 POST Code Register

LPC I/O Address: 0x80

IPMC SPI Address: 0x7f

Bit

7:0

Description

POST codes from host

Default Access

0 LPC: r/w

IPMC: r

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6.3.3 Super IO Configuration Register

After a LPC Reset (ICH_PLTRST_ is asserted) or “Power On Reset” the Super IO is in the Run

Mode with the UARTs disabled. They may be configured using the LPC IO Address Range SIW

(INDEX and DATA) by placing the Super IO into Configuration Mode. The BIOS uses these configuration addresses to initialize the logical devices at POST. The INDEX and DATA addresses are only valid when the Super IO is in Configuration State. The INDEX and DATA addresses are effective only when the Super IO is in the Configuration State. When the Super

IO is not in the Configuration State, reads return 0xFF and write data is ignored.

Table 6-9 Super IO Configuration Index Register

LPC I/O Address: 0x4E

Bit

7:0

Description

INDEX. Configuration

Index.

Default

0xff

Access

LPC: r/w

Table 6-10 Super IO Configuration Data Register

LPC I/O Address: 0x4F

Bit

7:0

Description Default

DATA Configuration Data. 0xff

Access

LPC: r/w

6.3.3.1

Entering the Configuration State

The device enters the Configuration State by the following contiguous sequence:

1. Write 68 to Configuration Index Port.

2. Write 08 to Configuration Index Port.

6.3.3.2

Configuration Mode

The system sets the logical device information and activates desired logical devices through

INDEX and DATA ports.

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The desired configuration registers are accessed in two steps:

1. Write the index of the Logical Device Number Configuration Register (that is, 07) to the

INDEX PORT and then write the number of the desired logical device to the DATA PORT.

2. Write the address of the desired configuration register within the logical device to the

INDEX PORT and then write or read the configuration register through the DATA PORT.

If accessing the Global Configuration Registers, step (1) is not required. The Super IO returns to the RUN State.

Only two states are defined (Run and Configuration). In the Run State the Super IO is always ready to enter the Configuration State.

6.3.3.3

Super IO Configuration Registers

Address locations that are not listed are considered reserved register locations. Reads to reserved registers may return non-zero values. Writes to reserved locations may cause system failure.

6.3.3.3.1 Global Control Configuration Registers

The Super IO Global Registers lie in the address range 0x00-0x2F. All eight bits of the ADDRESS port are used for register selection. All unimplemented registers and bits ignore writes and return zero when read. The INDEX PORT is used to select a configuration register in the chip.

The DATA PORT is then used to access the selected register. These registers are accessible only in the configuration mode.

Table 6-11 Global Configuration Register Summary

Index Address

0x07

0x20

0x21

0x28

0x29

Description

Super IO Logical Device Number

Super IO Device ID

Super IO Device Revision

Super IO LPC Control

Super IO SERIRQ and Pre-divide Control

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Table 6-12 Super IO Logical Device Number Register

Index Address: 0x07

Bit

7:0

Description

Logical Device Number:

0x04: Logical Device 4 (UART 1Serial Port 1)

0x05: Logical Device 5 (UART2 Serial Port 2)

A write to this register selects the current logical device. This allows access to the control and configuration registers for each logical device.

Table 6-13 Super IO Device Identification Register

Index Address: 0x20

Bit

7:0

Description

Device ID

Default Access

0 LPC: r

Table 6-14 Super IO Device Revision Register

Index Address: 0x21

Bit Description

7:0 Device Revision

Default

0x01

Access

LPC: r

Table 6-15 Super IO LPC Control Register

Index Address: 0x28

Bit

Description

LPC Bus Wait States:

1: Long wait states (sync 6)

1 Reserved

Default

Access

LPC: r

Default

Access

LPC: r/w

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Table 6-16 Global Super IO SERIRQ and Pre-divide Control Register

Index Address: 0x29

Bit Description

0 SERIRQ enable:

0: disabled. Serial interrupts disabled.

1: enabled. Logical devices participate in interrupt generations.

3:2

7:4

SERIRQ Mode:

1: Continuous Mode

UART Clock pre-divide

00: divide by 1

01: divide by 8

10: divide by 26 (CLK_UART is 48 MHz)

11: reserved

Reserved

Default

Access

LPC: r/w

LPC: r

LPC: r/w

LPC: r

6.3.3.3.2 Logical Device Configuration Registers

Used to access the registers that are assigned to each logical unit. The Super IO supports two logical units and has two sets of logical device registers. The two logical devices are UART1

(Logical Number 4) and UART2 (Logical Number 5). A separate set (bank) of control and configuration registers exists for each logical device and is selected with the Logical Device

Number Register. The INDEX PORT is used to select a specific logical device register. These registers are then accessed through the DATA PORT. The logical device registers are accessible only when the device is in the configuration state.

Table 6-17 Logical Device Configuration Register Summary

Index Address Description

0x30 Enable

0x60 Base IO Address MSB

0x61

0x70

0x74

Base IO Address LSB

Primary Interrupt Select

Reserved

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162

Table 6-17 Logical Device Configuration Register Summary (continued)

Index Address Description

0x75 Reserved

0xF0 Reserved

The logical register addresses are shown in the tables below.

Table 6-18 Logical Device Enable Register

Index Address: 0x30

Bit

Description

Logical Device Enable:

0: disabled. Currently selected device is inactive.

1: enabled.The currently selected device is enabled.

7:1 Reserved

Default

Access

LPC: r/w

LPC: r

Table 6-19 Logical Device Base IO Address MSB Register

Index Address: 0x60

Bit

7:0

Description

Logical Device Base IO Address MSB

Default

Access

LPC: r/w

Table 6-20 Logical Device Base IO Address LSB Register

Index Address: 0x61

Bit Description

2:0

7:3

Bits 0 to 2 are read only. Decode is on 8 Byte boundary.

Logical Device Base IO Address LSB. (Bits 3 to 7)

Default

Access

LPC: r

LPC: r/w

Registers 0x60 (MSB) and 0x61 (LSB) set the Logical Device Base IO for this logical device. For example for Base IO address 0x3F8 the content of Register 0x60 is 0x03 and the content of

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See the table below for Common Decode Ranges:

Table 6-21 Logical Device Common Decode Ranges

IO Address range Description

0x3F8 – 0x3FF COM1

0x2F8 – 0x2FF

0x2E8 – 0x2EF

0x3E8 – 0x3EF

COM2

COM3

COM4

Table 6-22 Logical Device Primary Interrupt Register

Index Address: 0x70

Bit

3:0

7:4

Description

Interrupt level is used for Primary Interrupt.:

0x0: no interrupt selected

0x1: IRQ1

0x2: IRQ2

0x3: IRQ3

0x4: IRQ4

0x5: IRQ5

0x6: IRQ6

0x7: IRQ7

0x8: IRQ8

0x9: IRQ9

0xA: IRQ10

0xB: IRQ11

0xC: IRQ12

0xD: IRQ13

0xE: IRQ14

0xF: IRQ15

Reserved

Default Access

1 LPC: r/w

0 LPC: r

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An Interrupt is activated by enabling this device (offset 0x30), setting this register to a nonzero value and setting any combination of bits 0-4 in the corresponding UART IER and the occurrence of the corresponding UART event (that is Modem Status Change, Receiver Line

Error Condition, Transmit Data Request, Receiver Data Available or Receiver Time Out) and setting the OUT2 bit in the MCR.

Table 6-23 Logical Device 0x74 Reserved Register

Index Address: 0x74

Bit Description

7:0 Reserved

Default Access

0x04 LPC: r

Table 6-24 Logical Device 0x75 Reserved Register

Index Address: 0x75

Bit

7:0

Description

Reserved

Default Access

0x04 LPC: r

Table 6-25 Logical Device 0xF0 Reserved Register

Index Address: 0xF0

Bit Description

7:0 Reserved

Default

0x04

Access

LPC: r

6.3.4 UART1 and UART2 Register Map

The LPC IO Base addresses BASE1 for UART1 and BASE2 for UART2 are set up during Super IO configuration. See

Super IO Configuration Registers on page 159 .

6.3.4.1

UART Register Overview

Table 6-26 on page 165 shows the registers and their addresses as offsets of a base address for

one of the two UARTs.

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The state of the Divisor Latch Bit (DLAB), which is the MOST significant bit of the Serial Line

Control Register (SCR), affects the selection of certain UART registers. The DLAB bit must be set high by the system software to access the Baud Rate Generator Divisor Latches (DLL and DLM).

Table 6-26 UART Register Overview

LPC IO Address DLAB Bit value

Base 0

Base

Base + 1

Base + 2

Base + 3

Base + 4

Base + 5

Base + 6

Base + 7

Base

Base + 1

Description

Receiver Buffer (RBR). Read Only

Transmitter Holding (THR). Write Only.

Interrupt Enable Register (IER)

Interrupt Identification Register (IIR). Read Only

FIFO Control Register (FCR). Write Only.

Line Control Register (LCR)

Modem Control Register (MCR)

Line Status Register (LSR). Read Only

Modem Status Register (MSR). Read Only

Scratch Pad Register (SCR)

Divisor Latch LSB (DLL)

Divisor Latch MSB (DLM)

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6.3.4.2

UART Registers DLAB=0

6.3.4.2.1 Receiver Buffer Register (RBR)

In non-FIFO mode, this register holds the character received by the UART's Receive Shift

Register. If fewer than eight bits are received, the bits are right-justified and the leading bits are zeroed. Reading the register, empties the register and resets the Data Ready (DR) bit in the Line

Status Register to zero. Other (error) bits in the Line Status Register are not cleared. In FIFO mode, this register latches the value of the data byte at the top of the FIFO.

Table 6-27 Receiver Buffer Register (RBR) if DLAB=0

LPC IO Address: Base

Bit

7:0

Description

Receiver Buffer Register (RBR)

Default Access

Undefined LPC: r

6.3.4.2.2 Transmitter Holding Register (THR)

This register holds the next data byte to be transmitted. When the Transmit Shift Register becomes empty, the contents of the Transmit Holding Register are loaded into the shift register and the transmit data request (TDRQ) bit in the Line Status Register is set to one.

Table 6-28 Transmitter Holding Register (THR) if DLAB=0

LPC IO Address: Base

Bit Description

7:0 Transmitter Holding Register (THR)

Default Access

Undefined LPC: w

In FIFO mode, writing to THR puts data to the top of the FIFO. The data at the bottom of the

FIFO is loaded to the shift register when it is empty.

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6.3.4.2.3 Interrupt Enable Register (IER)

This register enables four types of interrupts which independently activate the "int signal" and set a value in the Interrupt Identification Register. Each of the four interrupt types can be disabled by resetting the appropriate bit of the IER register. Similarly, by setting the appropriate bits, selected interrupts can be enabled.

Table 6-29 Interrupt Enable Register (IER), if DLAB=0

LPC IO Address: Base + 1

Bit

Description

Receive data interrupt enable/disable:

1: receive data interrupt enabled

0: receive data interrupt disabled

7:4

Transmitter holding register empty (THRE) interrupt enable/disable

1: THRE interrupt enabled

0: THRE interrupt disabled

Receiver line status interrupt enable/disable

1: receiver line status interrupt enabled

0: receiver line status interrupt disabled

Modem status interrupt enable/disable:

1: modem status interrupt enabled

0: modem status interrupt disabled

Reserved

Default Access

0 LPC: r/w

LPC: r/w

LPC: r

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6.3.4.2.4 Interrupt Identification Register (IIR)

In order to minimize software overhead during data character transfers, the UART prioritizes

interrupts into four levels (listed in Table 6-30 ) and records these in the Interrupt Identification

Register. The Interrupt Identification Register (IIR) stores information indicating that a prioritized interrupt is pending and the source of that interrupt.

Table 6-30 UART Interrupt Priorities

Priority Level Interrupt Source

1 (highest)

Receiver Line Status. One or more error bits were set.

Received Data is available. In FIFO mode, trigger level was reached; in non-

FIFO mode, RBR has data.

Receiver Time out occurred. It happens in FIFO mode only, when there is data in the receive FIFO but no activity for a time period.

Transmitter requests data. In FIFO mode, the transmit FIFO is half or more than half empty; in non-FIFO mode, THR is read already

Modem Status: one or more of the modem input signals has changed state

Table 6-31 Interrupt Identification Register (IIR)

LPC IO Address: Base + 1

Bit Description

2:1

Interrupt status bit:

1: no interrupt pending

0: interrupt pending

Interrupt priority level and source:

11: Receiver line status

10: Receiver data available

01: Transmitter holding register empty

00: Modem status

5:4

Time Out Detected:

0: No time out interrupt is pending

1: Character time-out indication (FIFO mode only)

Reserved

Default

Access

LPC: r

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Table 6-31 Interrupt Identification Register (IIR) (continued)

LPC IO Address: Base + 1

Bit Description

7:6 FIFO Mode Enable bits:

00: Default mode

01: Reserved

10: Reserved

11: FIFO mode

Default

Access

LPC: r

6.3.4.2.5 FIFO Control Register (FCR)

FCR is a write-only register that is located at the same address as the IIR (IIR is a read-only register). FCR enables/disables the transmitter/receiver FIFOs, clears the transmitter/receiver

FIFOs, and sets the receiver FIFO trigger level.

Table 6-32 FIFO Control Register (FCR)

LPC IO Address: Base + 2

Bit

Description

FIFO enable/disable:

1: Transmitter and Receiver FIFO enabled

0: FIFO disabled

5:4

Receiver FIFO reset:

1: Bytes in receiver FIFO and counter are reset. Shift register is not reset

(bit is self-clearing)

0: No effect

Transmit FIFO reset:

1: Bytes in receiver FIFO and counter are reset. Shift register is not reset

(bit is self-clearing)

0: No effect

Receiver/Transmitter ready. Not supported.

Reserved

Default

Access

LPC: w

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Maps and Registers

Table 6-32 FIFO Control Register (FCR) (continued)

LPC IO Address: Base + 2

Bit Description

7:6 Receiver FIFO interrupt trigger level:

00: 1 byte

01: 4 bytes

10: 8 bytes

11: 14 bytes

Default

Access

LPC: w

6.3.4.2.6 Line Control Register (LCR)

In the Line Control Register (LCR), the system programmer specifies the format of the asynchronous data communications exchange. The serial data format consists of a start bit

(logic 0), five to eight data bits, an optional parity bit, and one or two stop bits (logic 1). The

LCR has bits for accessing the Divisor Latch and causing a break condition. The programmer can also read the contents of the Line Control Register. The read capability simplifies system programming and eliminates the need for separate storage in system memory.

Table 6-33 Line Control Register (LCR)

LPC IO Address: Base + 3

Bit Description

1:0

Serial character WORD length:

00: 5 bits

01: 6 bits

10: 7 bits

11: 8 bits

Stop bit length:

1: 1.5 stop bits for 5 bit WORD length

1: 2 stop bits for 6, 7, and 8 bit WORD length

0: 1 stop bit for any serial character WORD length

Default

Access

LPC: r/w

170 ATCA-7360 Installation and Use (6806800J07S )

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Table 6-33 Line Control Register (LCR) (continued)

LPC IO Address: Base + 3

Bit Description

Parity enable/disable

When bit 3 is set, a parity bit is generated in transmitted data between the last data WORD bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is cleared, no parity is generated or checked.:

1: Parity enabled

0: Parity disabled

Parity even/odd

When parity is enabled and bit 4 is set, even parity

(an even number of logic ones in the data and parity bits) is selected. When parity is disabled and bit 4 is cleared, odd parity (an odd number of logic ones) is selected.:

1: Even parity

0: Odd parity

Stick parity

When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. If bit 5 is cleared, stick parity is disabled.:

1: Stick parity enabled

0: Stick parity disabled

Break control bit

Bit 6 is set to force a break condition, i.e. a condition where TXD is forced to the spacing

(cleared) state. When bit 6 is cleared, the break condition is disabled and has no affect on the transmitter logic. It only effects TXD:

1: Break condition enabled

0: Break condition disabled

Default

Access

LPC: r/w

ATCA-7360 Installation and Use (6806800J07S) 171

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Table 6-33 Line Control Register (LCR) (continued)

LPC IO Address: Base + 3

Bit Description

7 Divisor latch access bit (DLAB)

Bit 7 must be set to access the divisor latches of the baud generator during a read or write. Bit 7 must be cleared during a read or write to access the RBR, THR, or IER.:

1: Access to DLL and DLM registers

0: Access to RBR, THR and IER registers

Default

Access

LPC: r/w

6.3.4.2.7 Modem Control Register (MCR)

This 8-bit register controls the interface with the modem or data set (or a peripheral device emulating a modem).

Table 6-34 Modem Control Register (MCR)

LPC IO Address: Base + 4

Bit

Description

Data terminal ready (DTR#) output control:

1: DTR# output in low (active) state

0: DTR# output in high state

Request to send (RTS#) output control:

1: RTS# output in low (active) state

0: RTS# output in high state

User output control signal (OUT1#):

1: OUT1# output in high state

0: OUT1# output in low state

Not supported

User output control signal (OUT2#):

1: OUT2# output in high state

0: OUT2# output in low state

Not supported

Default Access

0 LPC: r/w

LPC: r/w

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Table 6-34 Modem Control Register (MCR) (continued)

LPC IO Address: Base + 4

Bit Description

7:6

Local loop back diagnostic control

When loop back is activated: Transmitter TXD is set high. Receiver RXD is disconnected.

Output of Transmitter Shift register is looped back into the receiver shift register input.

Modem control inputs are disconnected

Modem control outputs are internally connected to modem control inputs. Modem control outputs are forced to the inactive

(high) levels:

1: Loop back mode activated

0: Normal operation

Autoflow control enable:

1: Autoflow control enabled (auto-RTS# and auto-CTS# or auto-CTS# only enabled)

0: Autoflow control disabled

Reserved

Default Access

0 LPC: r/w

LPC: r/w

LPC: r

6.3.4.2.8 Line Status Register (LSR)

This register provides status information to the processor concerning the data transfers. Bits five and six show information about the transmitter section. The rest of the bits contain information about the receiver.

In non-FIFO mode, three of the LSR register bits, parity error, framing error, and break interrupt, show the error status of the character that has just been received. In FIFO mode, these three bits of status are stored with each received character in the FIFO. LSR shows the status bits of the character at the top of the FIFO. When the character at the top of the FIFO has errors, the LSR error bits are set and are not cleared until software reads LSR, even if the character in the FIFO is read and a new character is now at the top of the FIFO.

ATCA-7360 Installation and Use (6806800J07S) 173

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Bits one through four show error conditions that produce a receiver line status interrupt when any of the corresponding conditions are detected and the interrupt is enabled. These bits are not cleared by reading the erroneous byte from the FIFO or receive buffer. They are cleared only by reading LSR. In FIFO mode, the line status interrupt occurs only when the erroneous byte is at the top of the FIFO. If the erroneous byte being received is not at the top of the FIFO, an interrupt is generated only after the previous bytes are read and the erroneous byte is moved to the top of the FIFO.

Table 6-35 Line Control Register (LCR)

LPC IO Address: Base + 5

Bit Description

Receiver data ready (DR) indicator

DR is set whenever a complete incoming character has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of the data in the RBR or the FIFO:

1: New data received

0: No new data

Overrun Error (OE) indicator

When OE is set, it indicates that before the character in the RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every time the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO beyond the trigger level, an overrun error occurs only after the FIFO is full and the next character has been completely received in the shift register. An overrun error is indicated to the CPU as soon as it happens. The character in the shift register is overwritten but it is not transferred to the FIFO:

1: Overrun error occurred

0: No overrun error

Default Access

0 LPC: r

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Table 6-35 Line Control Register (LCR) (continued)

LPC IO Address: Base + 5

Bit Description

Parity Error (PE) indicator

When PE is set, it indicates that the parity of the received data character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO:

1: Parity error occurred

0: No parity error

Framing Error (FE) indicator

When FE is set, it indicates that the received character did not have a valid

(set) stop bit. FE is cleared every time the CPU reads the contents of the LSR.

In the FIFO mode, this error is associated with the particular character in the

FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the next start bit. The ACE samples this start bit twice and then accepts the input data:

1: Framing error occurred

0: No framing error

4 Break Interrupt (BI) indicator

When BI is set, it indicates that the received data input was held low for longer than a full-word transmission time. A full-word transmission time is defined as the total time to transmit the start, data, parity, and stop bits. BI is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after RXD goes to the marking state for at least two Receiver CLK samples and then receives the next valid start bit:

1: Full WORD transmission time exceeded

0: Normal operation

Default Access

0 LPC: r

LPC: r

ATCA-7360 Installation and Use (6806800J07S) 175

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Table 6-35 Line Control Register (LCR) (continued)

LPC IO Address: Base + 5

Bit Description

Transmit Holding Register Empty (THRE) indicator

THRE is set when the THR is empty, indicating that the ACE is ready to accept a new character. If the THRE interrupt is enabled when THRE is set, an interrupt is generated. THRE is set when the contents of the THR are transferred to the TSR. THRE is cleared concurrent with the loading of the

THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared when at least one byte is written to the transmit FIFO:

1: THR/Transmit FIFO empty

0: THR/Transmit FIFO contains data

Transmitter Empty (TEMT) indicator

TEMT bit is set when the THR and the TSR are both empty. When either the

THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode,

TEMT is set when the transmitter FIFO and shift register are both empty:

1: THR/Transmit FIFO/TSR empty

0: THR/Transmit FIFO/TSR contains data

FIFO data error

In the FIFO mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO. If FIFO is not used, bit always reads 0:

1: FIFO data error encountered

0: No FIFO error encountered

Default Access

0 LPC: r

LPC: r

6.3.4.2.9 Modem Status Register (MSR)

This 8-bit register provides the current state of the control lines from the modem or data set

(or a peripheral device emulating a modem) to the processor. In addition to this current state information, four bits of the Modem Status register provide change information. Bits 03:00 are set to a logic 1 when a control input from the Modem changes state. They are reset to a logic 0 when the processor reads the Modem Status register.

176 ATCA-7360 Installation and Use (6806800J07S )

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When bits 0, 1, 2, or 3 are set to logic 1, a Modem Status interrupt is generated if bit 3 of the

Interrupt Enable Register is set.

Table 6-36 Modem Status Register (MSR)

LPC IO Address: Base + 6

Bit

Description

Change in clear-to-send (DCTS) indicator

DCTS indicates that the CTS# input has changed state since the last time it was read by the CPU. When DCTS is set (autoflow control is not enabled and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is enabled

(DCTS is cleared), no interrupt is generated:

1: Change in state of CTS# input since last read

0: No change in state of CTS# input since last read

Change in data set ready (DDSR) indicator

DDSR indicates that the DSR# input has changed state since the last time it was read by the CPU. When DDSR is set and the modem status interrupt is enabled, a modem status interrupt is generated:

1: Change in state of DSR# input since last read

0: No change in state of DSR# input since last read

Trailing edge of the ring indicator (TERI) detector

TERI indicates that the RI# input to the chip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled, a modem status interrupt is generated. Not supported.

Change in data carrier detect (DDCD) indicator

DDCD indicates that the DCD# input to the chip has changed state since the last time it was read by the CPU. When DDCD is set and the modem status interrupt is enabled, a modem status interrupt is generated. Not supported.

Default

Access

LPC: r/w

ATCA-7360 Installation and Use (6806800J07S) 177

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Table 6-36 Modem Status Register (MSR) (continued)

LPC IO Address: Base + 6

Bit Description

Complement of the clear-to-send (CTS#) input

When the Asynchronous Communications Element (ACE) is in diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1

(RTS#).

Complement of the data set ready (DSR#) input

When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR#).

Complement of the ring indicator (RI#) input

When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 2 (OUT1#). Not supported.

Complement of the data carrier detect (DCD#) input

When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2#). Not supported.

Default

Ext.

Access

LPC: r

6.3.4.2.10 Scratch Register (SCR)

This 8-bit read/write register has no effect on the UART. It is intended as a scratch pad register for use by the programmer.

Table 6-37 Scratch Register (SCR))

LPC IO Address: Base + 7

Bit Description

7:0 Scratch Register (SCR)

The scratch register is an 8 bit register that is intended for the programmer's use as a scratch pad in the sense that it temporarily holds the programmer's data without affecting any other ACE operation.

Default

Undef.

Access

LPC: r/w

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6.3.4.3

Programmable Baud Rate Generator

The UART contains a programmable Baud Rate Generator that is capable of taking the

UART_CLK input and dividing it by any divisor from 1 to (2 16 -1). The output frequency of the

Baud Rate Generator is 16 times the baud rate. Two 8-bit latches store the divisor in a 16-bit binary format. These Divisor Latches must be loaded during initialization to ensure proper operation of the Baud Rate Generator. If both Divisor Latches are loaded with 0, the 16X output clock is stopped. Upon loading either of the Divisor latches, a 16-bit baud counter is immediately loaded. This prevents long counts on initial load. Access to the Divisor latch can be done with a word write.

The UART_CLK is the CLK_UART (48MHz) input divided by the pre-divider set by the Super IO

Configuration Register (Offset 0x29).

The baud rate of the data shifted in/out of the UART is given by:

Baud Rate = UART_CLK / (16X Divisor)

For example, if the pre-divider is 26 the UART_CLK is 1.8461538MHz. When the divisor is 12, the baud rate is 9600.

A Divisor value of 0 in the Divisor Latch Register is not allowed.

Table 6-38 Divisor Latch LSB Register (DLL), if DLAB=1

LPC IO Address: Base

Bit Description

7:0 Divisor Latch LSB (DLL)

Default Access

Undef.

LPC: r/w

Table 6-39 Divisor Latch MSB Register (DLM), if DLAB=1

LPC IO Address: Base + 1

Bit

7:0

Description

Divisor Latch MSB (DLM)

Default

Undef.

Access

LPC: r/w

6.4 FPGA Register Mapping

ATCA-7360 Installation and Use (6806800J07S) 179

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6.4.1 LPC I/O Register Map

The FPGA registers may be accessed via LPC I/O cycles in the I/O address range REGISTERS. See

Table 6-40 . For LPC register access, use the base address 0x600 and add the Address Offset. An

LPC I/O write access to an address not listed in this table or not marked with an “X” in the LPC

I/O column is ignored. A corresponding read access delivers always zero.

Note: LPC I/O Address = 0x600 + Address Offset

6.4.2 IPMC SPI Register Map

The FPGA registers may be accessed via IPMC SPI transactions (with the signal

IPMC_SPI_SS_FPGA_ asserted). A SPI write access to an address not listed in this table or not marked with an “X” in the IPMC SPI column is ignored. A corresponding read access delivers always zero.

Table 6-40 FPGA Register Map Overview

Address

Offset

0x00

0x01

0x03 - 0x05 x

0x06 x

0x08

0x10 x x

LPC I/O x x

0x11

0x12

0x13

0x14

0x15

0x16

0x17 -

0x18 -0x19 x

x x x x x

x x x

x x x x x x x x x

IPMC

SPI Description

Module Identification Register

FPGA Version Register

Serial Line Routing Registers

IPMC Power Level Register

SPD PROM MUX Control Register

BIOS Reset Source Register

Reset Mask Register

BIOS IPMC Watch dog timeout Register

BIOS Push Button Enable Register

OS Reset Source Register

OS IPMC Watch dog timeout Register

IPMC Watch dog timeout Register

IPMC Reset Source Register

RTM SPI Interface

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Table 6-40 FPGA Register Map Overview (continued)

Address

Offset

0x20

0x21

0x22

0x23 – 0x2D x

0x40 x x x

LPC I/O x

0x41 – 0x42 x

0x43 x

0x45

0x48 x x

0x49

0x4A

0x4B

0x50 x x x x

0x58 x

0x60 -0x66 x

0x6F

0x7D x x

0x7E

0x7F x x

1. For LPC I/O accesses add the LPC I/O Base Address 0x600

x x x

IPMC

SPI x x

x x x

Description

External Interrupt Status Register

Processor Hot Status/Control Register

Telecom Status/Control Register

Interrupt Mask and Map Registers

Flash Control and Status Register

Boot Flash Write Enable Registers

BIOS Boot Mode Register

SFMEM Module Configuration Register

Update Channel Equalization Control

IPMC E-Keying Status Register

IPMC E-Keying Control Register

IPMC GPIO Register

LED Status and Control Register

NMI Status and Control Register

Telecom Clocking Registers

Miscellaneous Status/Control Register

LPC Scratch Register

IPMC Scratch Register

POST codes from host

Note: For LPC I/O address 0x80 is used.

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6.4.3 Module Identification Register

The Module Identification Register identifies the ATCA-7360 Blade (Wellbeck).

Table 6-41 Module Identification Register

Address Offset: 0x00

Bit

7:0

Description

ATCA-7360 Blade (Wellbeck) Module Identification

Default Access

0x60 r

6.4.4 Version Register

The version register provides the version of the FPGA bit stream. The initial value starts at 0x01 and increments with each new release.

Table 6-42 Version Register

Address Offset: 0x01

Bit Description

7:0 Specifies FPGA version

Default

1 (Initial

Value)

Access r

6.4.5 Serial Redirection Control Register

BIOS set the corresponding bit, which is used for serial redirection. The IPMC uses this information to route the corresponding port to serial IPMC interface in case of SOL.

BIOS should never set both status bits.

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Table 6-43 Serial Redirection Control Register

Address Offset: 0x03

Bit Description

COM1 used for serial redirection:

0: COM1 not used for serial redirection

1: COM1 used for serial redirection

COM2 use for serial redirection

0: COM2 not used for serial redirection

1: COM2 used for serial redirection

7:2 Reserved

Default

Access

LPC: r/w

IPMC: r

LPC: r/w

IPMC: r r

6.4.6 Serial Over LAN (SOL) Control Register

The IPMC software can route serial data from serial port 1 (COM1) or serial port 2 (COM2) to the IPMC.

When both control bits are enabled bit 1 is ignored.

Table 6-44 Serial over LAN Control Register

Address Offset: 0x04

Bit

Description

SOL over COM1 enable:

0: disabled

1: enabled. COM1 is forwarded to IMPC

7:2

SOL over COM2 enable:

0: disabled

1: enabled. COM2 is forwarded to IMPC

Reserved

Default

PWR_GOOD: 0

Access

LPC: r/w

IPMC: r

LPC: r/w

IPMC: r r

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6.4.7 Serial Line Routing Register

Table 6-45 Serial Line Routing Register

Address Offset: 0x05

Bit

1:0

Description

Inverted level of signals SEL_SERIAL[1:0], which are controlled by switches SW2.2 and SW2.1. Switch setting may be overwritten by IPMC Software:

00: COM1 to faceplate and COM2 to RTM

01: COM1 to RTM and COM2 to faceplate

10: Reserved

11: Reserved

7:2 Reserved

Default

Ext.

(SW2.2

, SW2.1)

00: (OFF,OFF)

01: (OFF,ON)

10: (ON,OFF)

11: (ON,ON)

Access r

0 r

1. The Signal SEL_SERIAL[1] is reserved. The switch SW2.2 should always be “OFF” and IPMC should not overwrite the default value.

6.4.8 IPMC Power Level Register

Table 6-46 IPMC Power Level Register

Address Offset: 0x06

Bit

7:0

Description

IPMC Power Level. IPMC writes a value, which correspond to a defined power level.

Default

PWR_GOOD:0

Access

IPMC: r/w

LPC: r

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6.4.9 SPD PROM MUX Control Register

Table 6-47 SPD PROM MUX Control Register

Address Offset: 0x08

Bit

Description

Signal Level of SMBUS_MUX0_IN

Signal Level of SMBUS_MUX1_IN

Signal Level of BIOS_POST_CMPLT_IN

Reserved

SMBUS_MUX0_OUT.

0: SMBUS_MUX0_OUT is driven low

1: SMBUS_MUX0_OUT is driven high

SMBUS_MUX1_OUT.

0: SMBUS_MUX1_OUT is driven low

1: SMBUS_MUX1_OUT is driven high

BIOS_POST_CMPLT_OUT.

0: BIOS_POST_CMPLT_IN is driven low

1: BIOS_POST_CMPLT_IN is driven high

SPD PROM MUX locked by BIOS

1: The output signals XXX_OUT are directly controlled by the corresponding input signals XXX_IN.

0: The output signals XXX_OUT are controlled by the corresponding bits 4 to 6.

Default

Ext.

Ext.:

SMBUS_MUX0_IN

Ext.:

SMBUS_MUX1_IN

Ext.:

BIOS_POST_CMPLT

_IN

Access r r r r

LPC: r

IPMC: r/w

LPC: r

IPMC: r/w

LPC: r

IPMC: r/w

LPC: r/w

IPMC: r

1. When the SPD PROM MUX is locked by BIOS (Bit 7 is set) the signal level of SMBUS_MUX0_IN is read.Write transactions are ignored.

2. When the SPD PROM MUX is locked by BIOS (Bit 7 is set) the signal level of SMBUS_MUX1_IN is read.

Write transactions are ignored.

3. When the SPD PROM MUX is locked by BIOS (Bit 7 is set) the signal level of BIOS_POST_CMPLT_IN is read. Write transactions are ignored.

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6.4.10 Reset Registers

6.4.10.1 BIOS Reset Source Register

The BIOS Reset Source Register stores the source of the most recent reset. A one in the register bit indicates that the associated reset has occurred. If more than one reset occurs from different sources without clearing the corresponding register bits, one can not determine the most recent reset source since more than one bit will be set. The same situation will happen, if two reset sources go active at the same time.

OS should never write to this register.

Table 6-48 BIOS Reset Source Register

Address Offset: 0x10

Bit

Description

PWR_GOOD Payload Power-on reset

1: Reset occurred

XDP0_BRD_PWROK CPU Debugger System reset request

1: Reset occurred

PB_RST_ faceplate push button reset

1: Reset occurred

XDP1_DBRST_ CPU Debugger reset

1: Reset occurred

RTM_PB_RST_ Reset key at RTM

1: Reset occurred

CPU_RST_ CPU Reset signal from CPU

1: Reset occurred

XDP0_DBRST_ CPU Debugger reset

1: Reset occurred

Default

PWR_GOOD:1

PWR_GOOD:0

Access

LPC: r/w1c

IPMC: r

LPC: r/w1c

IPMC: r

LPC: r/w1c

IPMC: r

LPC: r/w1c

IPMC: r

LPC: r/w1c

IPMC: r

LPC: r/w1c

IPMC: r

LPC: r/w1c

IPMC: r

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Table 6-48 BIOS Reset Source Register (continued)

Address Offset: 0x10

Bit Description

7 IPMC_RST_ REQ_ Payload Reset from IPMC.

1: Reset occurred

Default

PWR_GOOD:0

Access

LPC: r/w1c

IPMC: r

6.4.10.2 Reset Mask Register

The reset mask register enables or disables forwarding of a reset source to reset output signal.

Only Push Button Resets requests are affected by the reset mask register. The register default values are latched when PWR_GOOD is asserted. This register can be read or written by the host CPU. A one in the register bit indicates that the associated reset is enabled. A zero indicates that the associated reset source is masked.

Table 6-49 Reset Mask Register

Address Offset: 0x11

Bit Description

Reserved

Spare switch SW3.4

PB_RST_ faceplate push button reset

1: enabled

0: disabled

7:5

Reserved

RTM_PB_RST_ Reset key at RTM

1: enabled

0: disabled

Reserved

Default

PWR_GOOD:1

PWR_GOOD:0

Access r r r/w r r/w r

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6.4.10.3 BIOS IPMC Watchdog Timeout Register

When one of the bit of IPMC Watchdog Timeout Register is set the corresponding BIOS IPMC

Watchdog Timeout bit is set. The BIOS clears this status bit, writing one.

OS should never write to this register.

Table 6-50 BIOS IPMC Watchdog Timeout Register

Address Offset: 0x12

Bit Description

BIOS IPMC Watchdog Timeout:

1: IPMC Watchdog Timeout occurred

BIOS IPMC Pre-Timeout

1: IPMC Pre-Timeout occurred

7:2 Reserved

Default

PWR_GOOD:0

6.4.10.4 BIOS Push Button Enable Register

The BIOS needs to write to this register to enable the Front Panel push button reset, the RTM push button reset and the IPMC reset.

After a timeout of 8s the resets are armed again.

Access

LPC: r/w1c

IPMC: r

LPC: r/w1c

IPMC: r r

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Table 6-51 BIOS Push Button Enable Register

Address Offset: 0x13

Bit Description

7:0 BIOS Push Button Enable Register

6.4.10.5 OS Reset Source Register

The OS Reset Source Register stores the source of the most recent reset as it is done in the BIOS

Reset Source Register. A one in the register bit indicates that the associated reset has occurred.

If more than one reset occurs from different sources without clearing the corresponding register bits, one can not determine the most recent reset source since more than one bit will be set. The same situation will happen, if two reset sources go active at the same time.

BIOS should never write to this register.

Default Access

LPC: w

Table 6-52 Reset Source Register

Address Offset: 0x14

Bit Description

PWR_GOOD Payload Power-on reset

1: Reset occurred

XDP0_BRD_PWROK CPU Debugger System reset request

1: Reset occurred

PB_RST_ faceplate push button reset

1: Reset occurred

XDP1_DBRST_ CPU Debugger reset

1: Reset occurred

RTM_PB_RST_ Reset key at RTM

1: Reset occurred

Default

PWR_GOOD:1

PWR_GOOD:0

Access

LPC: r/w1c

IPMC: r

LPC: r/w1c

IPMC: r

LPC: r/w1c

IPMC: r

LPC: r/w1c

IPMC: r

LPC: r/w1c

IPMC: r

ATCA-7360 Installation and Use (6806800J07S) 189

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Table 6-52 Reset Source Register (continued)

Address Offset: 0x14

Bit Description

CPU_RST_ CPU Reset signal from CPU

1: Reset occurred

XDP0_DBRST_ CPU Debugger reset

1: Reset occurred

7 IPMC_RST_ REQ_ Payload Reset from IPMC.

1: Reset occurred

Default

PWR_GOOD:0

6.4.10.6 OS IPMC Watchdog Timeout Register

When the IPMC Watchdog Timeout: bit of IPMC Watchdog Timeout Register is set the OS IPMC

Watchdog Timeout bit is set. The OS clears this status bit, writing one.

BIOS should never write to this register.

Access

LPC: r/w1c

IPMC: r

LPC: r/w1c

IPMC: r

LPC: r/w1c

IPMC: r

Table 6-53 OS IPMC Watchdog Timeout Register

Address Offset: 0x15

Bit

Description

OS IPMC Watchdog Timeout:

1: IPMC Watchdog Timeout occurred

7:2

OS IPMC Pre-Timeout

1: IPMC Pre-Timeout occurred

Reserved

Default

PWR_GOOD:0

Access

LPC: r/w1c

IPMC: r

LPC: r/w1c

IPMC: r r

190 ATCA-7360 Installation and Use (6806800J07S )

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6.4.10.7 IPMC Watchdog Timeout Register

The IPMC set the corresponding bit to signal an IPMC watchdog timeout event. When the IPMC

Watchdog Timeout bit is set from low to high, the corresponding bits in

Table 6-50 BIOS IPMC

Watchdog Timeout Register and

Table 6-53

OS IPMC Watchdog Timeout Register are set.

IPMC needs to clear the IPMC watchdog timeout bit to arm IPMC watchdog timeout event recognition.

Table 6-54 IPMC Watchdog Timeout Register

Address Offset: 0x16

Bit

Description

IPMC Watchdog Timeout:

0: No IPMC Watchdog Timeout

1: IPMC Watchdog Timeout occurred

7:2

IPMC Pre-Timeout

0: No IPMC Pre-Timeout

1: IPMC Pre-Timeout occurred

Reserved

Default

PWR_GOOD:0

Access

IPMC: r/w

IPMC: r/w r

ATCA-7360 Installation and Use (6806800J07S) 191

Maps and Registers

6.4.10.8 IPMC Reset Source Register

The IPMC Reset Source Register stores the source of the most recent reset. A one in the register bit indicates that the associated reset has occurred. If more than one reset occurs from different sources without clearing the corresponding register bits, one cannot determine the most recent reset source since more than one bit will be set. The same situation will happen, if two reset sources go active at the same time.

Table 6-55 IPMC Reset Source Register

Address Offset: 0x17

Bit

Description

PWR_GOOD Payload Power-on reset

1: Reset occurred

XDP0_BRD_PWROK CPU Debugger System reset request

1: Reset occurred

PB_RST_ faceplate push button reset

1: Reset occurred

XDP1_DBRST_ CPU Debugger reset

1: Reset occurred

RTM_PB_RST_ Reset key at RTM

1: Reset occurred

CPU_RST_ CPU Reset signal from CPU

1: Reset occurred

XDP0_DBRST_ CPU Debugger reset

1: Reset occurred

IPMC_RST_ REQ_ Payload Reset from IPMC.

1: Reset occurred

Default

PWR_GOOD:1

PWR_GOOD:0

Access

IPMC: r/w1c

192 ATCA-7360 Installation and Use (6806800J07S )

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6.4.11 RTM SPI Interface Registers

The signals RTM_SPI_SCK, RTM_SPI_SS_, RTM_SPI_MISO and RTM_SPI_MOSI are used to support a SPI master protocol. The signal RTM_SPI_MISO is used to signal the base board an

ARTM interrupt.

At the moment there is no ARTM with an SPI interface defined.

A write access to the RTM SPI Address/Command Register starts the SPI transaction. The write access terminates, when SPI transaction has finished.

Table 6-56 RTM SPI Address/Command Register

Address Offset: 0x18

Bit Description

7:1

Command Bit

0: Write

1: Read

RTM SPI Address bits [6:0]

Default

PWR_GOOD:0

Access

IPMC: r/w

A write access to the RTM SPI Address/Command Register with the Command Bit 0 (Write) starts a SPI write transaction. The value of the RTM SPI Write Register is written to the SPI device.

Table 6-57 RTM SPI Write Register

Address Offset: 0x19

Bit Description

7:0 RTM SPI write data -

Default Access

LPC: w

ATCA-7360 Installation and Use (6806800J07S) 193

Maps and Registers

A write access to the RTM SPI Address/Command Register with the Command Bit 1 (Read) starts a SPI read transaction. The value of the RTM SPI Read Register contains the data read from the SPI device.

Table 6-58 RTM SPI Read Register

Address Offset: 0x19

Bit Description

7:0 RTM SPI read data -

Default Access

LPC: r

6.4.12 Interrupt Control and Status Registers

The interrupt status registers indicate the status of the interrupt input signals. They are read only registers. When an interrupt is active the corresponding status bit is read 1. Write access to these register bits does not have any impact.

6.4.12.1 RTM Interrupt Status Register

The RTM Interrupt Status Register will be located in the RTM SPI address space. The host can access the RTM register using the RTM SPI Master Interface.

No RTM interrupt sources are defined yet.

6.4.12.2 External Interrupt Status Register

194

Table 6-59 External Interrupt Status Register

Address Offset: 0x20

Bit

Signal

Description

IPMC2HOST_INT_ IPMC signals interrupt

LM75_INT_

SFMEM_IRQ_

Default

Ext.

Interrupt input from payload Temp sensor Ext.

Interrupt from SFMEM Module Ext.

THERM_SEN0

THERM_SEN1

IRQ request from 82599 Thermsen0

IRQ request from 82599 Thermsen1

Ext.

Access

LPC: r

ATCA-7360 Installation and Use (6806800J07S )

Maps and Registers

Table 6-59 External Interrupt Status Register (continued)

Address Offset: 0x20

Bit

Signal

THERM_ALERT_

APB_ALARM

RTM_SPI_MISO

Description

IRQ request from IOH Thermo-sensor

An 48V input alarm (low voltage, etc)

RTM interrupt sources

0: RTM_SPI_MISO is high. No RTM interrupt.

1: RTM_SPI_MISO is low. One or more

RTM interrupt sources are active. When RTM

SPI Master face is active the current level is latched.

1. When an interrupt is active the corresponding status bit is read 1.

Default

Ext.

Access

LPC: r

6.4.12.3 Processor Hot Status/Control Register

Table 6-60 Processor Hot Status/Control Register

7:4

Address Offset: 0x21

Bit

Signal

CPU0_PRCHT_

CPU1_PRCHT_

CPU0_PRCHT_

CPU1_PRCHT_

Description

IPMC signals interrupt

Default Access

Ext.

LPC: r

Interrupt input from payload Temp sensor Ext.

Interrupt from SFMEM Module 0

LPC: r

LPC: r/w

IRQ request from 82599 Thermsen0

Reserved -

0 LPC: r/w r

ATCA-7360 Installation and Use (6806800J07S) 195

Maps and Registers

6.4.12.4 Telecom Status/Control Register

Table 6-61 Telecom Status/Control Register

7:4

Address Offset: 0x22

Bit

Signal Description

CH1_CLK1A_IN Clock CLK1A of Chassis 1 has changed state from static to toggle or toggle to static.

CH1_CLK1B_IN Clock CLK1A of Chassis 1 has changed state from static to toggle or toggle to static.

Telecom timeout occurred.

Reserved

Counter of Telecom timeout occurred.

Clearing bit 2 of this register also clears this counter.

Default

Access

LPC: r/w1c

LPC: r/w1c r

LPC: r

6.4.12.5 Interrupt Mask and Map Registers

Each interrupt signal of the External Interrupt Status Register, Processor Hot Status/Control

Register or Telecom Status/Control Register can be mapped to one of the CPU_IRQ_X_ interrupt or any IRQ Frame number of the serialized IRQ protocol.

Multiple interrupt sources may share the same CPU_IRQ_X_ or the same IRQ Frame. In this case all interrupt sources need to be of type “level active low”.

Each Interrupt source has an Interrupt Mask and Map Register. See the table below.

Table 6-62 Address Map of Interrupt Mask and Map Registers

Interrupt Source

IPMC2HOST_INT_

LM75_INT_

Description

IPMC signals interrupt

Interrupt input from payload Temp sensor

Address

Offset of

Interrupt

Mask

0x23

0x24

196 ATCA-7360 Installation and Use (6806800J07S )

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Table 6-62 Address Map of Interrupt Mask and Map Registers (continued)

Interrupt Source

SFMEM_IRQ_

THERM_SEN0

THERM_SEN1

THERM_ALERT_

APB_ALARM

RTM_SPI_MISO

CPU0_PRCHT_ CPU0

CPU1_PRCHT_ CPU1

Telecom Status/Control

Description

Interrupt from SFMEM Module

IRQ request from 82599 Thermsen0

IRQ request from 82599 Thermsen1

IRQ request from IOH Thermo-sensor

A 48V input alarm (low voltage, etc)

RTM interrupt sources

“Processor hot” interrupt

0x2B

0x2C

Active when at least one Status bit (bit 0, 1 or 2) is set.

0x2D

Address

Offset of

Interrupt

Mask

0x25

0x26

0x27

0x28

0x29

0x2A

ATCA-7360 Installation and Use (6806800J07S) 197

Maps and Registers

Each Interrupt Mask and Map Register has the same layout. See the table below for more details.

Table 6-63 Interrupt Mask and Map Registers

Address Offset: 0x23 – 0x2D

Bit

4:0

Description

IRQ Frame Number of Serialized IRQ protocol. Any valid Frame number enables interrupt.

0x00: Interrupt is mapped to CPU_IRQ_X_. See Bit 7:5 of this register.

0x01: Frame number 1. IRQ0

0x02: Frame number 2. IRQ1

0x03: Frame number 3. IRQ2 (SMI_)

0x04: Frame number 4. IRQ3

0x05: Frame number 5. IRQ4

0x06: Frame number 6. IRQ5

0x07: Frame number 7. IRQ6

0x08: Frame number 8. IRQ7

0x09: Frame number 9. IRQ8

0x0A: Frame number 10. IRQ9

0x0B: Frame number 11. IRQ1

0x0C: Frame number 12. IRQ11

0x0D: Frame number 13. IRQ12

0x0E: Frame number 14. IRQ13

0x0F: Frame number 15. IRQ14

0x10: Frame number 16. IRQ15

0x11: Frame number 17. IOCHK_

0x12: Frame number 18. INTA_

0x13: Frame number 19. INTB_

0x14: Frame number 20. INTC_

0x15: Frame number 21. INTD_

0x16 – 0x1F: Frame number 22-31. IRQ Frame Number not valid. Value is ignored.

Default

Access

LPC:r/ w

198 ATCA-7360 Installation and Use (6806800J07S )

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Table 6-63 Interrupt Mask and Map Registers (continued)

Address Offset: 0x23 – 0x2D

Bit Description

7:5 An external Interrupt Signal CPU_IRQ_X_ is used.

Only used when IRQ Frame Number is 0x00:

0x0: Interrupt is masked (disabled).

0x1: Map Interrupt to CPU_IRQ_A_

0x2: Map Interrupt to CPU_IRQ_B_

0x3: Map Interrupt to CPU_IRQ_C_

0x4: Map Interrupt to CPU_IRQ_D_

0x5: Map Interrupt to CPU_IRQ_F_

0x6: Map Interrupt to CPU_IRQ_G_

0x7: Map Interrupt to CPU_IRQ_H_

Default

Access

LPC:r/ w

6.4.13 Flash Status and Protection Registers

The flash status register indicates the actual status of the mechanical switches SW1.1 (Signal

BOOT_DEF_WP_), SW1.2 (Signal BOOT_REC_WP_), SW1.3 (Signal BOOT_TSOP), SW3.1

(Signal BOOT_SEL_EN_) and SW3.2 (Signal BOOT_DEFAULT) and the status of IPMC signal

BOOT_SELECT.

Table 6-64 Flash Status Register

Address Offset: 0x040

Bit Description

3:2

Default Boot SPI Flash Write protection Status. See

Default Boot SPI Flash Write Enable register, how to disable write protection.

0: Default Boot SPI Flash is unprotected

1: Default Boot SPI Flash is protected

Recovery Boot SPI Flash Write protection Status. See

Recovery Boot SPI Flash Write Enable register, how to disable write protection

0: Recovery Boot SPI Flash is unprotected

1: Recovery Boot SPI Flash is protected

Reserved

Default

Ext. BOOT_DEF_WP_

0: SW1.1 OFF

1: SW1.1 ON

Ext. BOOT_REC_WP_

0: SW1.2 OFF

1: SW1.2 ON

Access

LPC: r

ATCA-7360 Installation and Use (6806800J07S) 199

Maps and Registers

Table 6-64 Flash Status Register (continued)

Address Offset: 0x040

Bit Description

TSOP or PLCC Boot select. Signal BOOT_TSOP.

0: TSOP selected

1: PLCC selected

Manual Boot Flash select enable. Signal

BOOT_SEL_EN_.

0: Signal BOOT_SELECT selects active boot flash

1: Switch SW3.2 selects the active Boot Flash.

Manual Boot Flash select. Signal BOOT_DEFAULT.

Used when SW3.1 is ON:

0: Selects Default Boot SPI Flash.

1: Selects Recover Boot SPI Flash.

IPMC signal BOOT_SELECT. Boot Flash Select.

0: Selects Default Boot SPI Flash

1: Selects Recovery Boot SPI Flash

1. The default is latched from SW1.1 when ICH_PLTRST_ is deasserted.

2. The default is latched from SW1.2 when ICH_PLTRST_ is deasserted

Default

Ext.

0: SW1.3 OFF

1: SW1.3 ON

Ext.

0: SW3.1 OFF

1: SW3.1 ON

Ext.

0: SW3.2 OFF

1: SW3.2 ON

Ext.

Access

LPC: r

Write protection status signals for the Boot SPI flashes are determined by external switch settings SW1.1and SW1.2. Software can overwrite the status of the write protection status by writing a magic word to the Boot SPI Flash Write Enable Registers.

Table 6-65 Default Boot SPI Flash Write Enable

Address Offset: 0x41

Bit Description

7:0 Default Boot SPI Flash Write enable/disable.

A write value 0xC3 enables the Boot Block. All other values disables the Boot Block

Default Access

LPC: w

200 ATCA-7360 Installation and Use (6806800J07S )

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Table 6-66 Recovery Boot SPI Flash Write Enable

Address Offset: 0x42

Bit Description

7:0 Recovery Boot SPI Flash enable/disable.

A write value 0xC3 enables the Flash. All other values disables the Flash

Default

6.4.14 BIOS Boot Mode Register

Access

LPC: w

Table 6-67 BIOS Boot Mode Register

Address Offset: 0x43

Bit

Description Default

The switch signals SW_BIOS[1:0] controls the BIOS Boot Mode: -Ext.

1: SW4.3 ON

0: SW4.3 OFF

1 Ext.

1: SW4.4 ON

0: SW4.4 OF

7:2 Reserved

6.4.15 SFMEM Module Configuration Register

Access r r r

Table 6-68 SFMEM Module Configuration Register

Address Offset: 0x45

Bit

3:0

Description

Control output signals SFMEM_CONF[3:0]

Default

PWR_GOOD:0

Access

LPC: r/w

IPMC: r

ATCA-7360 Installation and Use (6806800J07S) 201

Maps and Registers

Table 6-68 SFMEM Module Configuration Register (continued)

Address Offset: 0x45

Bit Description

7:4 Reserved

Default

6.4.16 Update Channel Equalization Control Register

Access r

Table 6-69 Update Channel Equalization Control Register

Address Offset: 0x48

Bit Description

Control output Signal UC1_EQ_RX:

0: UC1_EQ_RX is driven low.

1: UC1_EQ_RX is tri-state.

Control output Signal UC1_EQ_TX:

0: UC1_EQ_TX is driven low.

1: UC1_EQ_TX is tri-state.

Control output Signal UC2_EQ_RX:

0: UC2_EQ_RX is driven low.

1: UC2_EQ_RX is tri-state.

Control output Signal UC2_EQ_TX:

0: UC2_EQ_TX is driven low.

1: UC2_EQ_TX is tri-state.

Control output Signal UC3_EQ_RX:

0: UC3_EQ_RX is driven low.

1: UC3_EQ_RX is tri-state.

Control output Signal UC3_EQ_TX:

0: UC3_EQ_TX is driven low.

1: UC3_EQ_TX is tri-state.

Default

Access

LPC: r/w

IPMC: r

LPC: r/w

IPMC: r

LPC: r/w

IPMC: r

LPC: r/w

IPMC: r

LPC: r/w

IPMC: r

LPC: r/w

IPMC: r

202 ATCA-7360 Installation and Use (6806800J07S )

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Table 6-69 Update Channel Equalization Control Register (continued)

Address Offset: 0x48

Bit Description

Control output Signal UC4_EQ_RX:

0: UC4_EQ_RX is driven low.

1: UC4_EQ_RX is tri-state.

Control output Signal UC4_EQ_TX:

0: UC4_EQ_TX is driven low.

1: UC4_EQ_TX is tri-state.

Default

6.4.17 IPMC E-Keying Status Register

Table 6-70 IPMC E-Keying Status Register

Address Offset: 0x49

Bit

4:0

Description

IPMC_UPDCH_[4:0]. IPMC electronic key signals

IPMC_FAB1_10G_SEL_.

IPMC_FAB2_10G_SEL_.

Reserved

Default

Ext.

Access

LPC: r/w

IPMC: r

LPC: r/w

IPMC: r

Access

LPC: r

LPC: r r

ATCA-7360 Installation and Use (6806800J07S) 203

Maps and Registers

6.4.18 IPMC E-Keying Control Register

Table 6-71 IPMC E-Keying Control Register

Address Offset: 0x4A

Bit

Description

Shut off the Intel82567 Faceplate GB Eth PHY.

0: FP_LAN_DISABLE_ driven low. Disabled

1: FP_LAN_DISABLE_ driven high. Enabled

Shut off the Intel8257x BASE-Eth Controller

0: BASEIF_DEV_OFF_ driven low. Device is off

1: BASEIF_DEV_OFF_ driven high. Device is on

Enable/Disable Base-IF#1.

0: BASEIF_LAN0_DIS_ driven low. Disabled

1: BASEIF_LAN0_DIS_ driven high. Enabled

Enable/Disable Base-IF#2.

0: BASEIF_LAN1_DIS_ driven low. Disabled

1: BASEIF_LAN1_DIS_ driven high. Enabled

Enable/Disable Fabric-IF#1.

0: FABIF_LAN0_DIS_ driven low. Disabled

1: FABIF_LAN0_DIS_ driven high. Enabled

Enable/Disable Fabric-IF#2.

0: FABIF_LAN1_DIS_ driven low. Disabled

1: FABIF_LAN1_DIS_ driven high. Enabled

Enable/Disable Update Channel ATCA Zone2 Port0.

0: UPDCIF_LAN_DIS_ driven low. Disabled

1: UPDCIF_LAN_DIS_ driven high. Enabled

Disable/Enable USB Port 8 to RTM.

0: RTMUSB_ENABLE_ driven low. Enabled

1: RTMUSB_ENABLE_ driven high. Disabled

Default

PWR_GOOD: 1

Access

LPC: r/w

IPMC: r/w

LPC: r/w

IPMC: r/w

LPC: r/w

IPMC: r/w

LPC: r/w

IPMC: r/w

LPC: r/w

IPMC: r/w

LPC: r/w

IPMC: r/w

LPC: r/w

IPMC: r/w

LPC: r/w

IPMC: r/w

204 ATCA-7360 Installation and Use (6806800J07S )

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6.4.19 IPMC GPIO Register

Table 6-72 IPMC GPIO Register

7:3

Address Offset: 0x4B

Bit

Description

IPMC_GPIO1

IPMC_GPIO2

Reserved

6.4.20 LED Status and Control Register

Default

Ext.

Table 6-73 LED Status and Control Register

Address Offset: 0x50

Bit Description

Control green LED output Signal LED_GREEN_:

0: LED_GREEN_ is driven high.

1: LED_GREEN_ is driven low.

Control read LED output Signal LED_RED_:

0: LED_RED_ is driven high.

1: LED_RED_ is driven low.

5:4

Control user LED output Signal LED_USER1_:

0: LED_USER1_ is driven high.

1: LED_USER1 is driven low.

Control user LED output Signal LED_USER2_:

0: LED_USER2_ is driven high.

1: LED_USER2 is driven low.

Reserved

ATCA-7360 Installation and Use (6806800J07S)

Default

Access

LPC: r

Access

LPC: r/w

IPMC: r

LPC: r/w

IPMC: r

LPC: r/w

IPMC: r

LPC: r/w

IPMC: r r

205

Maps and Registers

Table 6-73 LED Status and Control Register (continued)

Address Offset: 0x50

Bit Description

Signal level of ME_DISABLE_ (Connected to SW1.4 and ICH10 GP33)

FPGA PROM select signal FPGA_PROM_SEL controlled by IPMC

Default

Ext.

6.4.21 NMI Status and Control Register

7:4

Table 6-74 NMI Status and Control Register

Address Offset: 0x58

Bit

Description

Diagnostic NMI Status

Watchdog NMI Status

Reserved

Access r r

Default

Access

LPC: r/w1c

IPMC: r/w

LPC: r

IPMC: r/w

LPC: r/w1c

IPMC: r/w

LPC: r

IPMC: r/w r

206 ATCA-7360 Installation and Use (6806800J07S )

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6.4.22 Telecom Clock Supervision Registers

6.4.22.1 Telecom Clocking Status Registers

The telecom backplane clocking status register indicates when the backplane input clock signals are toggling.

Table 6-75 Telecom Backplane Clocking Status Register

Address Offset: 0x66

Bit Description

0: CH1_CLK1A_IN is static or period is not in the correct range.

1: CH1_CLK1A_IN is toggling

0: CH1_CLK1B_IN is static or period is not in the correct range.

1: CH1_CLK1B_IN is toggling

7:2

Default

PWR_GOOD:0

Reserved 0

Access

LPC: r

LPC: r r

Table 6-76 Telecom Backplane Clocking Latch Register

Address Offset: 0x67

Bit

7:0

Description

Latch clock period measurements for CH1_CLK1A and CH1_CLK1B.

Write data is discarded.

Default Access

LPC: w

The clock period of CH1_CLK1A is measured periodically. The result of the measurement

(number of LPC clock cycles) is latched with a write access to the Telecom Backplane Clocking

Latch Register. The 16 bit value is stored in the registers Telecom CH1_CLK1A clock period MSB

Register and Telecom CH1_CLK1A clock period LSB Register. When the clock is static or the period is higher than a 16 bit value the result is always 0xFFFF.

Table 6-77 Telecom CH1_CLK1A clock period MSB Register

Address Offset: 0x61

Bit Description

7:0 MSB of CH1_CLK1A clock period

Default Access

PWR_GOOD: 0xFF LPC: r

ATCA-7360 Installation and Use (6806800J07S) 207

Maps and Registers

Table 6-78 Telecom CH1_CLK1A clock period LSB Register

Address Offset: 0x60

Bit Description

7:0 LSB of CH1_CLK1A clock period

Default Access

PWR_GOOD: 0xFF LPC: r

The clock period of CH1_CLK1B is measured periodically. The result of the measurement

(number of LPC clock cycles) is latched with a write access to the Telecom Backplane Clocking

Latch Register. The 16 bit value is stored in the register Telecom CH1_CLK1B clock period MSB

Register and Telecom CH1_CLK1B clock period LSB Register. When the clock is static or the period is higher than a 16 bit value the result is always 0xFFFF.

Table 6-79 Telecom CH1_CLK1B clock period MSB Register

Address Offset: 0x63

Bit

7:0

Description

MSB of CH1_CLK1B clock period

Default Access

PWR_GOOD: 0xFF LPC: r

Table 6-80 Telecom CH1_CLK1B clock period LSB Register

Address Offset: 0x62

Bit Description

7:0 LSB of CH1_CLK1B clock period

Default Access

PWR_GOOD: 0xFF LPC: r

6.4.22.2 Telecom Timer Registers

The Telecom Timer is decremented with each rising edge of the input clock.

The Telecom Timer is disabled when loaded with 0 (MSB and LSB Timer registers are 0). It is programmed from 1 to 65535, which allows timeout values from 125ìsec to 8.191875sec

(based on an 8kHz input clock).

When a timeout occurs (the timer is 0) the timeout bit is set. See

Table 6-61

Telecom

Status/Control Register. The Telecom Timer is reloaded with the timer start value stored in

Telecom Timer LSB Register and Telecom Timer MSB Register and armed again, waiting for a rising edge of the input clock.

208 ATCA-7360 Installation and Use (6806800J07S )

Maps and Registers

A write access to Telecom Timer MSB Register load the 16 bit Telecom timer with the write data of the current access and the content of the Telecom Timer LSB Register.

Table 6-81 Telecom Timer MSB Register

Address Offset: 0x65

Bit

7:0

Description Default

MSB of Telecom Timer start value PWR_GOOD: 0

Access

LPC: r/w

Table 6-82 Telecom Timer LSB Register

Address Offset: 0x64

Bit

7:0

Description Default

LSB of Telecom Timer start value PWR_GOOD: 0

Access

LPC: r/w

6.4.23 Miscellaneous Status/Control Registers

Table 6-83 CPLD Version and Spare Signal Status Register

Address Offset: 0x6F

Bit Description

2:0 CPLD Version. The CPLD uses the signals

CPLD_SPARE[3:1]

7:4

Default

Ext.

CPLD_SPARE[4] Ext.

Reserved 0 r r

Access r

ATCA-7360 Installation and Use (6806800J07S) 209

Maps and Registers

6.4.24 Scratch Registers

Table 6-84 LPC Scratch Register

Address Offset: 0x45

Bit

7:0

Description

LPC Scratch bits.

Default

PWR_GOOD:0

Access

LPC: r/w

IPMC: r

Table 6-85 IPMC Scratch Register

Address Offset: 0x45

Bit Description

7:0 IPMC Scratch bits.

Default

PWR_GOOD:0

Access

LPC: r/w

IPMC: r

210 ATCA-7360 Installation and Use (6806800J07S )

Chapter 7 Serial Over LAN

7.1 Overview

Serial Over LAN (SOL) is a mechanism that you can use to redirect the serial console from the blade via an IPMI session over the network. SOL uses the RMCP+ protocol.

The IPMC is used to establish and control the SOL session. SOL is only available on the base interface. The sideband interface of the Intel 82576 (in pass-through mode) is used to transmit/receive its terminal characters via the base interface.

Figure 7-1 SOL Overview

You can configure the SOL parameters via standard IPMI commands or via an open source tool called "ipmitool".

7.2 Installing the ipmitool

You can download the latest version of ipmitool from http://ipmitool.sourceforge.net

Documentation for this tool is also available on this site.

ATCA-7360 Installation and Use (6806800J07S) 211

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Procedure

To install the ipmitool, proceed as follows.

1. Download the latest ipmitool-<version>.tar.bz2

tar file from http://ipmitool.sourceforge.net

to your blade.

2. Extract the source code.

prompt>

tar -xjvf ipmitool-<version>.tar.bz2

3. Go to the directory to which you have extracted the ipmitool.

prompt>

cd <path>/ipmitool-<version>

4. Build the ipmitool.

prompt>

./configure && make && make install

7.3 Configure SOL Parameters

You can configure the following SOL parameters.

Table 7-1 SOL Parameters

Parameter

Set LAN Configuration Parameter (IP address/MAC address)

Set Channel Access (Privilege level)

Set User Name

Set User Password

Description

Use this command to set the IP and MAC address

Use this command to set the privilege level

Default value is soluser

Default value is solpasswd

You can use standard IPMI commands or the ipmitool to modify the parameters.

7.3.1 Using Standard IPMI Commands

This example shows how to setup the SOL configuration parameter with standard IPMI commands. Ipmicmd is used on the local IPMC and the IP is configured.

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Sample Procedure

To set the IP address, proceed as follows:

1. Establish an IPMI connection to the blade.

2. Set LAN Configuration Parameter Set In Progress Lock.

ipmicmd -k "f 0 c 1 5 0 1" smi 0

3. Set LAN Configuration Parameter Set IP (172.16.10.11 on channel 5).

ipmicmd -k "f 0 c 1 5 3 ac 10 0a dd" smi 0

4. Set LAN Configuration Parameter Set In Progress Commit.

ipmicmd -k "f 0 c 1 5 0 2" smi 0

7.3.2 Using ipmitool

The example below shows how to setup a LAN configuration parameter for a potential SOL session with ipmitool for Base Ethernet Channel 1 (channel 5).

n0s70:~ # ipmitool lan set 5 ipaddr 172.16.0.221

Setting LAN IP Address to 172.16.0.221

n0s70:~ #

The following example shows how to query the LAN parameters that are currently in use for a potential SOL session for Base Ethernet Channel 1 (channel 5) and Base Ethernet Channel 2

(channel 6): root@localhost: ~# ipmitool lan print 5

Set in Progress : Set Complete

Auth Type Support :

Auth Type Enable : Callback :

: User :

: Operator :

ATCA-7360 Installation and Use (6806800J07S) 213

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214

: Admin :

: OEM :

IP Address Source : Unspecified

IP Address : 172.16.0.221

Subnet Mask : 255.255.0.0

MAC Address : 00:00:00:00:00:00

Default Gateway IP : 172.16.0.1

Default Gateway MAC : 00:00:00:00:00:00

RMCP+ Cipher Suites : 1,2,3,3

Cipher Suite Priv Max : Not Available root@localhost: ~# ipmitool lan print 6

Set in Progress : Set Complete

Auth Type Support :

Auth Type Enable : Callback :

: User :

: Operator :

: Admin :

: OEM :

IP Address Source : Unspecified

IP Address : 172.17.1.220

Subnet Mask : 255.255.0.0

MAC Address : 00:00:00:00:00:00

Default Gateway IP : 172.17.0.1

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Default Gateway MAC : 00:00:00:00:00:00

RMCP+ Cipher Suites : 1,2,3,3

Cipher Suite Priv Max : Not Available root@localhost: ~#

MAC Address 00:00:00:00:00:00 means the address is shared between base and SOL interface. The address can be found out in the MAC address record of the FRU.

7.4 Establishing a SOL Session

To start a SOL session the following requirements must be fulfilled:

 An Ethernet LAN connection to the 82576 controller of the ATCA-7360 must exist.

 ATCA-7360 IPMC FW must correspond to version 2.00.7 and above.

Procedure

To establish a SOL session, proceed as follows.

1. Make sure that the requirements detailed above are fulfilled.

2. Compile and install the ipmitool on your target which is destined for opening the

SOL session on the ATCA-7360 - for details refer to

Installing the ipmitool

on page

211 .

3. Apply an IP address to the ATCA-7360 SOL interface - for details refer to

Configure

SOL Parameters

on page 212 .

4. If necessary change user and password.

Defaults are "soluser" as user and "solpasswd" as password.

5. Configure the network between the ATCA-7360 and your target, which is destined for opening the SOL session, so that the SOL IP address is accessible.

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6. Start ATCA-7360 SOL session on your target with the ipmitool and the configured

IP address for the ATCA-7360 SOL interface.

ipmitool -C 1 -I lanplus -H 172.16.0.221 -U soluser -P solpasswd -k gkey sol activate

For details on the command parameters, refer to the ipmitool documentation available on http://ipmitool.sourceforge.net

.

To access BIOS setup screen, it's necessary to reset the payload. SOL session is only available if the payload is powered on and initialized by the BIOS.

216 ATCA-7360 Installation and Use (6806800J07S )

Chapter 8 Supported IPMI Commands

8.1 Standard IPMI Commands

The IPMC is fully compliant to the Intelligent Platform Management Interface v.1.5. This section provides information about the supported IPMI commands.

8.1.1 Global IPMI Commands

The IPMC supports the following global IPMI commands.

Table 8-1 Supported Global IPMI Commands

Command

Get Device ID

Cold Reset

Warm Reset

Get Self Test Results

Get Device GUID

Master Write-Read

NetFn

(Request/Response) CMD Comments

0x06/0x07 0x01 -

0x06/0x07

0x02

0x03

0x04

0x08

0x52

Only for accessing private I2C buses.

8.1.2 System Interface Commands

The system interface commands are supported by blades providing a system interface.

Table 8-2 Supported System Interface Commands

Command

Set BMC Global Enables

Get BMC Global Enables

Clear Message Flags

Get Message Flags

Get Message

Send Message

NetFn (Request/Response) CMD

0x06/0x07

0x2E

0x2F

0x06/0x07

0x30

0x31

0x33

0x34

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Table 8-2 Supported System Interface Commands (continued)

Command

Set Channel Access

Get Channel Access

Get Channel Info

Set User Access

Get User Access

NetFn (Request/Response) CMD

0x06/0x07 0x40

0x06/0x07

0x41

0x42

0x43

0x44

Set User Name

Get User Name

Set User Password

Set User Payload Access

0x06/0x07

Get User Payload Access 0x06/0x07

Set Channel Security Keys 0x06/0x07

0x45

0x46

0x47

0x4C

0x4D

0x5C

8.1.3 Watchdog Commands

The watchdog commands are supported by blades providing a system interface and a watchdog type 2 sensor.

Note: The options pre-timeout and power-cycle are not supported.

Table 8-3 Supported Watchdog Commands

Command

Reset Watchdog Timer

Set Watchdog Timer

Get Watchdog Timer

NetFn

(Request/Response) CMD

0x06/0x07

0x22

0x24

0x25

218 ATCA-7360 Installation and Use (6806800J07S )

8.1.4 SEL Device Commands

Table 8-4 Supported SEL Device Commands

Command

Get SEL Info

Reserve SEL

Get SEL Entry

Add SEL Entry

Clear SEL

Get SEL Time

Set SEL Time

NetFn

(Request/Response) CMD

0x0A/0x0B 0x40

0x0A/0x0B

0x42

0x43

0x44

0x47

0x48

0x49

8.1.5 FRU Inventory Commands

Table 8-5 Supported FRU Inventory Commands

Command

NetFn

(Request/Response) CMD

Get FRU Inventory Area Info 0x0A/0x0B 0x10

Read FRU Data

Write FRU Data

0x0A/0x0B

0x11

0x12

Supported IPMI Commands

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8.1.6 Sensor Device Commands

Table 8-6 Supported Sensor Device Commands

Command

Get Device SDR Info

Get Device SDR

Reserve Device SDR

Repository

Get Sensor Reading Factors

Set Sensor Hysteresis

Get Sensor Hysteresis

Set Sensor Threshold

Get Sensor Threshold

Set Sensor Event Enable

Get Sensor Event Enable

Get Sensor Event Status

Get Sensor Reading

Get Sensor Type

Set Event Receiver

Get Event Receiver

Platform Event

NetFn

(Request/Response) CMD Comments

0x04/0x05 0x20 -

0x04/0x05

0x21 -

0x22 -

0x04/0x05

0x23 -

0x24 -

0x25 -

0x26 Most of the threshold-based sensors have fixed thresholds.

Before using this command, check whether threshold setting is supported by using the Get Device SDR command.

0x27 -

0x28 -

0x29 -

0x2B -

0x2D -

0x2F -

0x00 -

0x01 -

0x02 -

220 ATCA-7360 Installation and Use (6806800J07S )

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8.1.7 Chassis Device Commands

Table 8-7 Supported Chassis Device Commands

Command NetFn (Request/Response) CMD

Set System Boot Options 0x00/0x01

Get System Boot Options 0x00/0x01

0x08

0x09

8.1.7.1

System Boot Options Commands

The IPMI system boot options commands allow you to control the boot process of a blade by sending boot parameters to the blade’s boot firmware (for example BIOS, U-Boot or VxWorks).

The boot firmware interprets the sent boot parameters and executes the boot process accordingly. Each boot parameter addresses a particular functionality and consists of a sequence of one or more bytes. The IPMI specification assigns numbers to boot parameters.

Boot parameters 0 to 7 are standard parameters whose structure and functionality is defined by the IPMI specification. The boot parameters 96 to 127 are OEM-specific which can be used for different purposes.

When using the Get/Set System Boot Options commands, except for parameter 100, use the response/request data fields with the Set Selector and the Block Selector set to 0x00. When using the Get/Set System Boot Option for the parameter 100, the Set Selector and the Block

Selector have a specific meaning. Details are given in

System Boot Options Parameter #100 on page 224 for details.

The following table lists which boot properties can be configured and the corresponding boot parameter number.

Table 8-8 Configurable System Boot Option Parameters

Configurable Boot Property

Selection between default and backup boot flash as device to boot from

Selection between default and backup EEPROM as device where the on-board FPGA loads its configuration stream from

Corresponding Boot Parameter Number

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Table 8-8 Configurable System Boot Option Parameters (continued)

Configurable Boot Property

POST Type

Timeout for graceful shutdown

BIOS boot parameters as defined in Table 8-15 on page

229

Corresponding Boot Parameter Number

100

8.1.7.1.1 System Boot Options Parameter #96

This boot parameter is an Artesyn-specific OEM boot parameter. Its definition is given in the following table.

Table 8-9 System Boot Options Parameter #96

Data Byte

Description

Bits 7..2: Reserved

Bit 1: FPGA configuration stream load

0: Load configuration stream from default boot flash

1: Load configuration stream from backup boot flash

Note: The new FPGA configuration stream is loaded into the FPGA at the next powerup of the payload.

Bit 0: Default/backup boot flash selection

0: Boot from default boot flash

1: Boot from backup boot flash

Note : the newly selected boot flash is connected to the payload immediately, that means writing to the flash is possible. Its image is executed after the next power-up or cold reset of the payload.

The System Boot Options parameter #96 is non-volatile. During blade production its data is initialized to 0xFF and its state is set to invalid. Its parameter data remains preserved after IPMC power cycles and firmware upgrades.

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8.1.7.1.2 System Boot Options Parameter #97

This boot parameter is an Artesyn-specific OEM parameter. Its definition is given in the following table.

Table 8-10 System Boot Options Parameter #97

Data Byte

Description

POST Type

Data 1 - Set Selector. This is the processor ID for which the boot option is to be set.

Data 2 - POST Type Selector. This parameter is used to specify the POST type that the IPMC will execute.

0x00: Short POST

0x01: Long POST

0x02 to 0xFF: Not used

The System Boot Options parameter #97 is non-volatile. During blade production its data is initialized to 0xFF and its state is set to invalid. Its parameter data remains preserved after

IPMC power cycles and firmware upgrades.

8.1.7.1.3 System Boot Options Parameter #98

This boot parameter is an Artesyn-specific OEM parameter.

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This timer specifies how long the IPMC waits for the payload to shut down gracefully. If the payload software does not configure its OpenIPMI library to be notified for graceful shutdown requests, the IPMC shuts down the payload when the timer expires.

Table 8-11 System Boot Options Parameter #98

Bit Description

15:8 Timeout for GRACEFUL_SHUTDOWN, LSB (given in 100 msec)

7:0 Timeout for GRACEFUL_SHUTDOWN, MSB (given in 100 msec)

The System Boot Options parameter #98 is non-volatile. During blade production its data is initialized to 0xFF and its state is set to invalid. Its parameter data remains preserved after

IPMC power cycles and firmware upgrades.

8.1.7.1.4 System Boot Options Parameter #100

The system boot options parameter #100 allows you to send multiple boot options to the blade’s boot firmware and thus control the boot process. The boot options which you can configure via this parameter are typically a subset of the boot options which you can configure in the boot firmware directly, for example via a setup menu. Details are given in this section.

The IPMC contains a storage area where the boot parameters are stored. When the blade boots, the boot firmware reads out the storage area, interprets the parameters and executes the boot process accordingly. Note that the boot parameters in the IPMC storage area have higher priority than the same boot options which may be configured in the firmware itself, for example via the setup menu.

The storage area is divided into two parts: the default area and the user area. The user area can be read and written by an IPMI user and is, by default, the area which the boot firmware reads out and uses during the boot process. The default area can only be read (both by an IPMI user and the boot firmware). Its purpose is to store factory-programmed default boot options which can be used to restore the standard settings. If you want the boot firmware to read out and use the boot parameters stored in the default area and thus use the factory settings, you

224 ATCA-7360 Installation and Use (6806800J07S )

Supported IPMI Commands need to configure the blade accordingly. This is typically done by an on-board switch (for example "Clear CMOS RAM"). Refer to the <Product-Short> Installation and Use manual for details. It depends on the blade and firmware which settings are stored in the default area.

Details are given in the following sections.

On some blades with particular firmware types, changing a boot parameter in the firmware setup menu changes the boot parameter in the user area as well, if the same parameter is defined both in the user area and the set-up menu. Details are given below.

The following figure summarizes the previously explained basic information flow related to the system boot options parameter #100.

Figure 8-1 System Boot Options Parameter #100 - Information Flow Overview

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The boot options need to be stored as a sequence of zero terminated strings. The following table describes in detail the format of the boot options to be used when setting or reading the

System Boot Options parameter #100.

Table 8-12 System Boot Options - Parameter #100 - Data Format

Byte

0..1

2 .. n

Description

Number of bytes used for boot parameters (LSB first)

The number of bytes must be calculated and written into these two bytes by the software which writes into the storage area. The values 0x0000 and

0xFFFF indicate that no data has been written to the storage area. When reading from the storage area and you find any of these two values, your software should assume that no user-specific boot options have previously been written to the storage area.

Boot parameters data

The boot parameters are stored as ASCII text with the following general format:

, where all name/value pairs are separated by a zero byte. The end of the boot parameter data is indicated by two zero bytes. Allowed and supported name/value pairs are blade-specific. Details are given below. n + 1 .. n + 2 16 byte checksum over the boot parameters data section. (LSB first)

For backward compatibility reasons, the checksums 0x0000 and 0xFFFF are accepted as valid. They indicate that no checksum has been calculated and stored.

When writing to or reading from the storage area, you can only read or write chunks of 16 bytes at a time. For this reason, the default and user area are divided into numbered blocks of 16 bytes which need to be addressed individually. For this purpose, the "Block Selector" field in the request data field is used. The "Set Selector" field, on the other hand, is used to select either the default or user area. The following two tables describe in detail how the request and response data fields need to be filled and interpreted when performing SET and GET accesses

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Table 8-13 System Boot Options Parameter #100 - SET Command Usage

Byte

Request Data

Description

4 .. n (n <= 19)

Bit 7: when set to 1, the storage area on the IPMC is locked, i.e. no other software can access it. This should be set, before doing any modifications and cleared again after the final access.

Bits 6..0: must contain the value: 100, indicating this OEM system boot option.

Set Selector

Must be set to 0 (user area). You can only write to the user area, therefore no other values are supported.

Block Selector

Zero based index of the 16-byte block which you want to write to.

Index 0 refers to the first block of 16 bytes, which includes the first two bytes which indicate the boot parameter data size.

Depending on the total length of the boot option data, your software may need to write several blocks of 16 bytes in a row, each individually addressed via the block selector.

Data which you want to write into the addressed block. This will be a chunk of the boot parameter data. If less than 16 bytes are written, then only the provided data is written, the remaining bytes in the addressed storage area block are left unchanged.

Response Data

1 0x00: write successful

0x80: boot parameter storage not supported by the IPMC

0x81: storage area is locked by another software entity

0x82: illegal write-access

0xC9: block selector is outside of the allowed range.

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228

Table 8-14 System Boot Options Parameter #100 - GET Command Usage

Byte

Request Data

Description

Bit 7: reserved. Set to 0.

Bits 6..0: must contain the value: 100, indicating this OEM system boot option.

Set Selector

0: User area

1: Default area

Block Selector

Zero based index of the 16-byte block which you want to read from.

Index 0 refers to the first block of 16 bytes, which includes the first two bytes which indicate the boot parameter data size.

Response Data

4 .. 19

0x00: Read successful

0x80: boot parameter storage not supported by the IPMC

0xC9: block selector is outside of the allowed range.

Reserved. Set to 1.

Bit 7: If set to 1, the addressed storage area is locked.

Bits 6..0: value 100, indicating this OEM boot option command.

The content of the read 16-byte block.

In order to detect the maximum size of writable storage area, your software can perform a series of read accesses while incrementing the block selector with each access. Once the error code C9 is returned, the limit has been reached and the total available space in the writable storage area can be easily determined by the number of previously performed successful read accesses.

This is supported by HPI, for details refer to the System Management Interface Based on HPI-B

User’s Guide related to your system environment.

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The following table lists boot parameters which can be configured for the ATCA-7360 blade, using the system boot option parameter #100.

Artesyn provides the tool "ipmibpar" to interpret the ASCII parameters. To obtain the tool contact your local sales representative.

Observe that the boot parameters and their values when used in the System Boot Options parameter #100 are case-sensitive.

All boot options listed in the following table are set by the BIOS setup menu and can be configured via the System Boot options command #100. The IPMC and BIOS software automatically synchronize the settings made in the BIOS setup menu and the settings specified via the System Boot Options command #100. Changing a parameter in either of these, automatically changes the respective value in the other.

Table 8-15 System Boot Options Parameter #100 - Supported Parameters

Parameter baudrate usb

os_boot_watchdog frontnet_boot

Description Values

Console baud rate 9600/19200/57600/115200

USB support fp_on/fp_off,rtm_on/rtm_off,onboard_on/onb oard_off

OS boot Watchdog

(IPMI)

Example: usb=fp_off,rtm_off,onboard_on

-> Front panel USB off, RTM USB off, Onboard

Flash USB on on/off, timeout in minutes, action

Timeout range 1,2,3,5,7,10,15,20 action: noaction/reset,poweroff,

Example: os_boot_watchdog=on,10,reset

-> watchdog is on, 10 minutes timeout, action=reset off/on basenet_boot

artm_net_boot

Boot from Front Panel

Network

Boot from Base

Network

Boot from ARTM

Network off/on off/on

ATCA-7360 Installation and Use (6806800J07S) 229

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230

Table 8-15 System Boot Options Parameter #100 - Supported Parameters (continued)

Parameter artm_sas_boot artm_fc_boot

boot_order

Description

Boot from ARTM SAS device

Boot from ARTM FC device

Boot priority order

Values off/on off/on device1,devcice2,..device8

See boot_order Devices

frontnet basenet0 basenet1 fabricnet0 fabricnet1 usb1 usb2 usbonboard usbartm usbkey usbcdrom usbhdd

Table 8-16 boot_order Devices

Device sata0 sata1 sata5 sataonboard sashdd sas0_nn

Description

SATA device 0 (Debug SATA)

SATA device 1 (RTM Debug SATA)

SATA device 5 (Onboard SATA)

SAS HDD mounted on the RTM

SAS Controller nn = SCSI ID

(use this when a SAS array is connected to the RTM)

Front Panel Network

Base Ethernet Interface Channel 1

Base Ethernet Interface Channel 2

Fabric Ethernet Interface Channel 1

Fabric Ethernet Interface Channel 2

USB frontpanel 1

USB frontpanel 2

USB onboard HDD

USB artm

USB key

USB cdrom

USB hdd

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Table 8-16 boot_order Devices (continued)

Device usbfdd

Description

USB floppy disk efishell Built in UEFI shell

Up to 8 boot devices are supported.

Example: boot_order=sas0_03,basenet0,usbkey,sata1

8.1.8 LAN Device Commands

The following table provides the LAN Device Commands information.

Table 8-17 Supported LAN Device Commands

Command

Set LAN Configuration Parameters

Get LAN Configuration Parameters

Set SOL Configuration Parameters

Get SOL Configuration Parameters

NetFn (Request/Response)

0x0C/0x0D

CMD

0x01

0x02

0x21

0x22

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8.2 PICMG 3.0 Commands

The Artesyn IPMC is a fully compliant AdvancedTCA intelligent Platform Management

Controller i.e. it supports all required and mandatory AdvancedTCA commands as defined in the PICMG 3.0 and AMC.0 R2.0 specifications.

Table 8-18 Supported PICMG 3.0 Commands

Command

Get PICMG Properties

Get Address Info

FRU Control

NetFn

(Request/Response)

0x2C/0x2D

Get FRU LED Properties

Get FRU LED Color Capabilities

Set FRU LED State

Get FRU LED State

Set IPMB State

Set FRU Activation Policy

Get FRU Activation Policy

Set FRU Activation

Get Device Locator Record ID

Set Port State

Get Port State

Compute Power Properties

Set Power Level

Get Power Level

Get IPMB Link Info

0x2C/0x2D

CMD Comments

0x00 -

0x01 -

0x04 The blade supports the cold reset and graceful reboot options.

0x05 -

0x06 -

0x07 -

0x08 -

0x09 -

0x0A -

0x0B -

0x0C -

0x0D The Artesyn IPMCs support the standard PICMG 3.0 and the extended AMC.0

R2.0 versions of this command.

0x0E

0x0F

0x10 -

0x11 -

0x12 -

0x18 -

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Table 8-18 Supported PICMG 3.0 Commands (continued)

Command

Set AMC Port State

Get AMC Port State

Get FRU Control Capabilities

Get target upgrade capabilities

Get component properties

Abort firmware upgrade

Initiate upgrade action

Upload firmware block

Finish firmware upload

Get upgrade status

Activate firmware

Query self-test results

Query rollback status

Initiate manual rollback

NetFn

(Request/Response)

0x2C/0x2D

CMD Comments

0x19 -

0x1A -

0x1E -

0x2E -

0x2F

0x30 -

0x31 -

0x32 -

0x33 -

0x34 -

0x35 -

0x36 -

0x37 -

0x38 -

The firmware upgrade commands supported by the blade are implemented according to the PICMG HPM.1 Revision 1.0 specification.

The boot block can be updated with PICMG HPM.1 specific commands.

8.2.1 Set/Get Power Level

The blade supports two power levels. In case of a shelf which only allows 200W per slot the P-

States of the blade will be restricted to match this requirement. The second power level has no restrictions.

For more information, refer to Chapter 4, BIOS, on page 87 .

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Supported IPMI Commands

8.3 Artesyn Specific Commands

The Artesyn IPMC supports several commands which are not defined in the IPMI or PICMG 3.0 specification but are introduced by Artesyn: serial output commands.



Before sending any of these commands, the shelf management software must check whether the receiving IPMI controller supports Artesyn specific IPMI commands, by using the IPMI command 'Get Device ID'. Sending Artesyn specific commands to IPMI controllers which do not support these IPMI commands will lead to no or undefined results.

Proper handling of these commands is required to write a portable application.

8.3.1 Serial Output Commands

Table 8-19 Serial Output Commands

Command Name

Set Serial Output

NetFn (Request/Response)

0x2E/0x2F

Get Serial Output 0x2E/0x2F

CMD Description

0x15

See Set Serial Output Command on page 234

0x16

See Get Serial Output Command on page 236

8.3.1.1

Set Serial Output Command

The Set Serial Output command selects the serial port output source for a serial port connector.

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8.3.1.1.1 Request Data

The following table lists the request data applicable to the Set Serial Output command.

Table 8-20 Request Data of Set Serial Output Command

Byte

Data Field

LSB of Artesyn IANA Enterprise number. A value of 0xCD has to be used.

Second byte of Artesyn IANA Enterprise number. A value of 0x65 has to be used.

MSB of Artesyn IANA Enterprise number. A value of 0x00 has to be used.

Serial connector type

0: Faceplate connector

1: Backplane connector

All other values are reserved.

Note: Only the faceplate connector is supported. No connector on the RTM available.

Serial connector instance number. A sequential number that starts from 0.

Serial output selector

0: BIOS

2: IPMC debug console

All other values are reserved.

8.3.1.1.2 Response Data

The following table lists the response data applicable to the Set Serial Output command.

Table 8-21 Response Data of Set Serial Output Command

Byte

Data Field

Completion code

LSB of Artesyn IANA Enterprise number.

Second byte of Artesyn IANA Enterprise number.

MSB of Artesyn IANA Enterprise number.

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8.3.1.2

Get Serial Output Command

The Get Serial Output Command provides a way to determine which serial output source goes to a particular serial port connector.

Currently, only BIOS output is supported.

8.3.1.2.1 Request Data

The following table lists the request data applicable to the Get Serial Output command.

Table 8-22 Request Data of Get Serial Output Command

Byte

Data Field

LSB of Artesyn IANA Enterprise number. A value of 0xCD has to be used.

Second byte of Artesyn IANA Enterprise number. A value of 0x65 has to be used.

MSB of Artesyn IANA Enterprise number. A value of 0x00 has to be used.

Serial connector type

0: Faceplate connector

1: Backplane connector

All other values are reserved.

Note: Only the faceplate connector is supported. No connector on the RTM available.

Serial connector instance number. A sequential number that starts from 0.

8.3.1.2.2 Response Data

The following table lists the response data applicable to the Get Serial Output command.

Table 8-23 Response Data of Get Serial Output Command

Byte

Data Field

Completion code

236 ATCA-7360 Installation and Use (6806800J07S )

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Table 8-23 Response Data of Get Serial Output Command (continued)

Byte

Data Field

LSB of Artesyn IANA Enterprise number.

Second byte of Artesyn IANA Enterprise number.

MSB of Artesyn IANA Enterprise number.

Serial output selector

8.4 Pigeon Point Specific Commands

The IPMC supports additional IPMI commands that are specific to Pigeon Point. This section provides detailed descriptions of those extensions:

Table 8-24 Pigeon Point Extension Commands

Command

Get Status Table 8-26 on page 239

Get Serial Interface Properties

Table 8-27 on page 241

Set Serial Interface Properties Table 8-28 on page 242

Get Debug Level Table 8-29 on page 243

Set Debug Level

Table 8-30 on page 244

Get Hardware Address Table 8-31 on page 246

Set Hardware Address Table 8-32 on page 246

Get Handle Switch Table 8-33 on page 247

Set Handle Switch

Table 8-34 on page 248

Get Payload Communication Time-Out Table 8-35 on page

248

Set Payload Communication Time-Out

Table 8-36 on page

249

Enable Payload Control

Table 8-37 on page 250

Disable Payload Control

Table 8-38 on page 250

Reset IPMC

Table 8-39 on page 251

NetFn

(Request/Response)

0x2E/0x2F

CMD

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

ATCA-7360 Installation and Use (6806800J07S) 237

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Table 8-24 Pigeon Point Extension Commands (continued)

Command

Hang IPMC Table 8-40 on page 251

Graceful Reset

Table 8-41 on page 252

Get Payload Shutdown Time-Out

Table 8-42 on page 253

Set Payload Shutdown Time-Out Table 8-43 on page 254

Get Module State

Table 8-44 on page 254

Enable Module Site

Table 8-45 on page 256

Disable Module Site

Table 8-46 on page 256

Reset Carrier SDR repository

Table 8-47 on page 257

NetFn

(Request/Response)

0x2E/0x2F

CMD

0x0E

0x11

0x15

0x16

0x27

0x28

0x29

0x33

Some of the following commands refer to IPMC modes which are defined as follows:

Table 8-25 IPMC Modes

Mode

Standalone

Manual standalone

Description

In standalone mode, the carrier IPMC disconnects from IPMB-0 but keeps on listening to the serial debug and payload interfaces and serving requests coming from them, as well as managing the modules, AMC point-to-point

(P2P) and clock E-keying. Standalone mode is intended for debugging purposes and/or operation in a non-ATCA environment. In standalone mode, the carrier IPMC automatically activates and deactivates the on-carrier payload and modules whenever it does not violate any carrier limitations.

Manual standalone mode is equivalent to standalone mode with only one exception: carrier IPMC control over the on-carrier payload is automatically disabled in manual standalone mode.

238 ATCA-7360 Installation and Use (6806800J07S )

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8.4.1 Get Status Command

The Get Status command can be used by the payload software to retrieve the status of the

IPMC.

Table 8-26 Get Status Command

Request Data 1:3

Response Data 1

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

Bit [7] Graceful Reboot Request

If set to 1, indicates that the payload is requested to initiate the graceful reboot sequence.

Bit [6] Diagnostic Interrupt Request

If set to 1, indicates that a payload diagnostic interrupt request has arrived.

Bit [5] Shutdown Alert

If set to 1, indicates that the payload is going to be shutdown.

Bit [4] Reset Alert

If set to 1, indicates that the payload is going to be reset.

Bit [3] Sensor Alert

If set to 1, indicates that at least one of the IPMC sensors detects a threshold crossing.

Bits [2:1] Mode

The current IPMC modes are defined as:

0: Normal

1: Standalone, for a description refer to Table 8-25

2: Manual Standalone, for a description refer to

Table 8-25

Bit [0] Control

If set to 0, the IPMC control over the payload is disabled.

ATCA-7360 Installation and Use (6806800J07S) 239

Supported IPMI Commands

Table 8-26 Get Status Command (continued)

Bits [4:7] Metallic Bus 2 Events

These bits indicate pending Metallic Bus 2 requests arrived from the shelf manager:

0: Metallic Bus 2 Query

1: Metallic Bus 2 Release

2: Metallic Bus 2 Force

3: Metallic Bus 2 Free

Bits [0:3] Metallic Bus 1 Events

These bits indicate pending Metallic Bus 1 requests arrived from the shelf manager:

0: Metallic Bus 1 Query

1: Metallic Bus 1 Release

2: Metallic Bus 1 Force

3: Metallic Bus 1 Free

Bits [4:7] Clock Bus 2 Events

These bits indicate pending Clock Bus 2 requests arrived from the shelf manager:

0: Clock Bus 2 Query

1: Clock Bus 2 Release

2: Clock Bus 2 Force

3: Clock Bus 2 Free

Bits [0:3] Clock Bus 1 Events

These bits indicate pending Clock Bus 1 requests arrived from the shelf manager:

0: Clock Bus 1 Query

1: Clock Bus 1 Release

2: Clock Bus 1 Force

3: Clock Bus 1 Free

240 ATCA-7360 Installation and Use (6806800J07S )

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Table 8-26 Get Status Command (continued)

8 Bits [4:7] Reserved

Bits [0:3] Clock Bus 3 Events

These bits indicate pending Clock Bus 3 requests arrived from the shelf manager:

0: Clock Bus 3 Query

1: Clock Bus 3 Release

2: Clock Bus 3 Force

3: Clock Bus 3 Free

8.4.2 Get Serial Interface Properties Command

The Get Serial Interface Properties command is used to get the properties of a particular serial interface.

Table 8-27 Get Serial Interface Properties Command

Request Data

Response Data

1:3

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Interface ID

0: Serial Debug Interface

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

ATCA-7360 Installation and Use (6806800J07S) 241

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Table 8-27 Get Serial Interface Properties Command (continued)

5 Bit [7] Echo On

If this bit is set, the IPMC enables echo for the given serial interface.

Bits [6:4] Reserved

Bits [3:0] Baud Rate ID

The baud rate ID defines the interface baud rate as follows:

0: 9600 bps

1: 19200 bps

2: 38400 bps

3: 57600 bps (unsupported)

4: 115200 bps (unsupported)

8.4.3 Set Serial Interface Properties Command

The Set Serial Interface Properties command is used to set the properties of a particular serial interface.

Table 8-28 Set Serial Interface Properties Command

Request Data 1:3

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Interface ID

0: Serial Debug Interface

242 ATCA-7360 Installation and Use (6806800J07S )

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Table 8-28 Set Serial Interface Properties Command (continued)

Response Data

2:4

Bit [7] Echo On

If this bit is set, the IPMC enables echo for the given serial interface.

Bits [6:4] Reserved

Bits [3:0] Baud Rate ID

The baud rate ID defines the interface baud rate as follows:

0: 9600 bps

1: 19200 bps

2: 38400 bps

3: 57600 bps (unsupported)

4: 115200 bps (unsupported)

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

8.4.4 Get Debug Level Command

The Get Debug Level command gets the current debug level of the IPMC firmware.

Table 8-29 Get Debug Level Command

Request Data

Response Data

1:3

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

ATCA-7360 Installation and Use (6806800J07S) 243

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Table 8-29 Get Debug Level Command (continued)

5 Bit [7] IPMB-L Dump Enable

If set to 1, the IPMC provides a trace of IPMB-L messages that are arriving to/going from the IPMC via IPMB-L.

Bit [6] n/a

Bit [5] KCS Dump Enable

If set to 1, the IPMC provides a trace of KCS messages that are arriving to/going from the IPMC via KCS.

Bit [4] IPMB Dump Enable

If set to 1, the IPMC provides a trace of IPMB messages that are arriving to/going from the IPMC via IPMB-O.

Bit [3] n/a

Bit [2] Alert Logging Enable

If set to 1, the IPMC outputs important alert messages onto the serial debug interface.

Bit [1] Low-level Error Logging Enable

If set to 1, the IPMC outputs low-level error/diagnostic messages onto the serial debug interface.

Bit [0] Error Logging Enable

If set to 1, the IPMC outputs error/diagnostic messages onto the serial debug interface.

8.4.5 Set Debug Level Command

The Set Debug Level command sets the current debug level of the IPMC firmware.

Table 8-30 Set Debug Level Command

Request Data 1:3 PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

244 ATCA-7360 Installation and Use (6806800J07S )

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Table 8-30 Set Debug Level Command (continued)

Response Data 1

2:4

Bit [7] IPMB-L Dump Enable

If set to 1, the IPMC provides a trace of IPMB-L messages that are arriving to/going from the IPMC via IPMB-L.

Bit [6] n/a

Bit [5] KCS Dump Enable

If set to 1, the IPMC provides a trace of KCS messages that are arriving to/going from the IPMC via KCS.

Bit [4] IPMB Dump Enable

If set to 1, the IPMC provides a trace of IPMB messages that are arriving to/going from the IPMC via IPMB-O.

Bit [3] n/a

Bit [2] Alert Logging Enable

If set to 1, the IPMC outputs important alert messages onto the serial debug interface.

Bit [1] Low-level Error Logging Enable

If set to 1, the IPMC outputs low-level error/diagnostic messages onto the serial debug interface.

Bit [0] Error Logging Enable

If set to 1, the IPMC outputs error/diagnostic messages onto the serial debug interface.

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

ATCA-7360 Installation and Use (6806800J07S) 245

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8.4.6 Get Hardware Address Command

The Get Hardware Address command reads the hardware address of the IPMC.

Table 8-31 Get Hardware Address Command

Request Data

Response Data

1:3

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

Hardware Address

8.4.7 Set Hardware Address Command

The Set Hardware Address command allows to override the hardware address read from hardware when the IPMC operates in (manual) standalone mode (for a description refer to

Table 8-25 ).

Table 8-32 Set Hardware Address Command

Request Data

Response Data

1:3

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Hardware Address

If set to 00, the ability to override the hardware address is disabled.

NOTE: A hardware address change only takes effect after an IPMC reset.

Completion Code

246 ATCA-7360 Installation and Use (6806800J07S )

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Table 8-32 Set Hardware Address Command (continued)

2:4 PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

8.4.8 Get Handle Switch Command

The Get Handle Switch command reads the state of the hot-swap handle of the IPMC.

Overriding of the handle switch state is allowed only if the IPMC operates in (manual) standalone mode (for a description refer to

Table 8-25 ).

Table 8-33 Get Handle Switch Command

Request Data 1:3

Response Data

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

FRU ID (specify as 0)

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

Handle Switch Status

0x00: The handle switch is open.

0x01: The handle switch is closed.

0x02: The handle switch state is read from hardware.

ATCA-7360 Installation and Use (6806800J07S) 247

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8.4.9 Set Handle Switch Command

The Set Handle Switch command sets the state of the hot-swap handle switch in (manual) standalone mode (for a description refer to

Table 8-25 ).

Table 8-34 Set Handle Switch Command

Request Data

Response Data

1:3

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

FRU ID (specify as 0)

Handle Switch Status

0x00: The handle switch is open.

0x01: The handle switch is closed.

0x02: The handle switch state is read from hardware.

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

8.4.10 Get Payload Communication Time-Out Command

The Get Payload Communication Time-Out command reads the payload communication time-out value.

Table 8-35 Get Payload Communication Time-Out Command

Request Data

Response Data

1:3

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Completion Code

248 ATCA-7360 Installation and Use (6806800J07S )

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Table 8-35 Get Payload Communication Time-Out Command (continued)

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

Payload Time-out

Payload communication time-out measured in hundreds of milliseconds. Thus, the payload communication timeout may vary from 0.1 to 25.5 seconds.

8.4.11 Set Payload Communication Time-Out Command

The Set Payload Communication Time-Out command sets the payload communication timeout value.

Table 8-36 Set Payload Communication Time-Out Command

Request Data

Response Data

1:3

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Payload Time-out

Payload communication time-out measured in hundreds of milliseconds. Thus, the payload communication timeout may vary from 0.1 to 25.5 seconds.

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

ATCA-7360 Installation and Use (6806800J07S) 249

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8.4.12 Enable Payload Control Command

The Enable Payload Control command enables payload control from the serial debug interface.

Table 8-37 Enable Payload Control Command

Request Data

Response Data

1:3

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

8.4.13 Disable Payload Control Command

The Disable Payload Control command disables payload control from the serial debug interface.

Table 8-38 Disable Payload Control Command

Request Data

Response Data

1:3

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

250 ATCA-7360 Installation and Use (6806800J07S )

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8.4.14 Reset IPMC Command

The Reset IPMC command allows the payload to reset the IPMC over the KCS host interface.

Table 8-39 Reset IPMC Command

Request Data

Response Data

1:3

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Reset Type Code

0x00: Cold IPMC reset to the current mode

0x01: Cold IPMC reset to the Normal mode

0x02: Cold IPMC reset to the Standalone mode, for a description refer to

Table 8-25

0x03: Cold IPMC reset to the Manual Standalone mode, for a description refer to

Table 8-25

0x04: Reset the IPMC and enter Upgrade mode

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

8.4.15 Hang IPMC Command

The IPMC provides a way to test the watchdog timer support by implementing the Hang IPMC command, which simulates firmware hanging by entering an endless loop.

Table 8-40 Hang IPMC Command

Request Data

Response Data

1:3

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Completion Code

ATCA-7360 Installation and Use (6806800J07S) 251

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Table 8-40 Hang IPMC Command (continued)

2:4 PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

8.4.16 Graceful Reset Command

The IPMC supports the Graceful Reboot option of the FRU Control command. On receiving such a command, the IPMC sets the Graceful Reboot Request bit of the IPMC status, sends a status update notification to the payload, and waits for the Graceful Reset command from the payload. If the IPMC receives such a command before the payload communication time-out time, it sends the 0x00 completion code (Success) to the shelf manager. Otherwise the 0xCC completion code is sent.

The IPMC does not reset the payload on receiving the Graceful Reset command or time-out. If the IPMC participation is necessary, the payload must request the IPMC to perform a payload reset. The Graceful Reset command is also used to notify the IPMC about the completion of the payload shutdown sequence.

Table 8-41 Graceful Reset Command

Request Data

Response Data

1:3

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

252 ATCA-7360 Installation and Use (6806800J07S )

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8.4.17 Get Payload Shutdown Time-Out Command

When the shelf manager commands the IPMC to shut down the payload (i.e. sends the Activate

FRU (Deactivate) command), the IPMC notifies the payload by forwarding the command

Activate FRU (Deactivate) to the KCS interface. Provided the OpenIPMI driver has registered this command for notification, the payload gets notified. Upon receiving this notification, the payload software is expected to initiate the payload shutdown sequence. After performing this sequence, the payload should send the Graceful Reset command to the IPMC over the payload interface to notify the IPMC that the payload shutdown is complete.

To avoid deadlocks that may occur if the payload software does not respond, the IPMC provides a special time-out for the payload shutdown sequence. If the payload does not send the

Graceful Reset command within a definite period of time, the IPMC assumes that the payload shutdown sequence is finished, and resets the payload.

Table 8-42 Get Payload Shutdown Time-Out Command

Request Data

Response Data

1:3

2:4

5:6

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

Time-Out measured in hundreds of milliseconds, LSB first

ATCA-7360 Installation and Use (6806800J07S) 253

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8.4.18 Set Payload Shutdown Time-Out Command

The Set Payload Shutdown Time-Out command is defined as follows.

Table 8-43 Set Payload Shutdown Time-Out Command

Request Data

Response Data

1:3

4:5

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Time-Out measured in hundreds of milliseconds, LSB first

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

8.4.19 Get Module State Command

The Get Module State command is used to query the state of a module (RTM with site ID1) via any of the external interfaces.

Table 8-44 Get Module State Command

Request Data

Response Data

1:3

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Module Site ID

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

254 ATCA-7360 Installation and Use (6806800J07S )

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Table 8-44 Get Module State Command (continued)

5 Module Status

Bit [0]

0: Module site is enabled.

1: Module site is disabled.

Bit [1]

0: Module is not present.

1: Module is present.

Bit [2]

0: Management power is disabled.

1: Management power is enabled.

Bit [3]

0: Management power is bad.

1: Management power is good.

Bit [4]

0: Payload power is disabled.

1: Payload power is enabled.

Bit [5]

0: Payload power is bad.

1: Payload power is good.

Bit [6]

0: IPMB-L buffer is not attached.

1: IPMB-L buffer is attached.

Bit [7]

0: IPMB-L buffer is not ready.

1: IPMB-L buffer is ready.

ATCA-7360 Installation and Use (6806800J07S) 255

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8.4.20 Enable Module Site Command

The Enable Module Site command is used to enable a module site.

Table 8-45 Enable Module Site Command

Request Data

Response Data

1:3

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Module Site ID

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

8.4.21 Disable Module Site Command

The Disable Module Site command is used to disable an module site. If an module site is disabled, the IPMC firmware ignores the module inserted and acts as if the module is not present.

Table 8-46 Disable Module Site Command

Request Data 1:3

Response Data

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Module Site ID

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

256 ATCA-7360 Installation and Use (6806800J07S )

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8.4.22 Reset Carrier SDR Repository Command

The Reset Carrier SDR Repository command is used to clear and rebuild the carrier SDR repository.

Table 8-47 Reset Carrier SDR Repository Command

Request Data

Response Data

1:3

2:4

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00

Completion Code

PPS IANA Private Enterprise ID

0x00400A = 16394 (Pigeon Point Systems)

LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00

ATCA-7360 Installation and Use (6806800J07S) 257

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258 ATCA-7360 Installation and Use (6806800J07S )

Chapter 9 FRU Information and Sensor Data Records

9.1 FRU Information

The blade provides the following FRU information in FRU ID 0.

Table 9-1 FRU Information

Area

Internal use area Not used

Board info area

Description

Mfg date / time

Value

According to Platform Management FRU information Storage Definition v1.0

Board product name Product name of the specific blade variant r

Board serial number r

Board part number

Defined by Artesyn Embedded

Technologies - Embedded

Computing

Defined by Artesyn Embedded

Technologies - Embedded

Computing r

Access r

Product info area Product manufacturer

Product name

'ARTESYN' r

Product name of the specific blade variant r

Product serial number Defined by Artesyn Embedded

Technologies - Embedded

Computing r

ATCA-7360 Installation and Use (6806800J07S) 259

FRU Information and Sensor Data Records

Table 9-1 FRU Information (continued)

Area

Multi record info area

Description Value

Product part number Defined by Artesyn Embedded

Technologies - Embedded

Computing

Blade Point-To-Point

Connectivity Record

Area

User Info Area

Custom usage

This multi record area contains the ATCAblade Point to Point Connectivity Record according to PICMG 3.0, Rev.1.0. The contents are described in the section 'E-

Keying'.

Artesyn OEM ID: 0x48, 0x0E, 0x00, 0x00

Followed by 255 byte of user info area data

Minimum 256 Byte available

Access r r r/w r/w

9.2 MAC Address Record

The blade provides one OEM FRU record which contains information about on-board MAC addresses.

The format of the record is described in the following table.

Table 9-2 Artesyn MAC Addresses Record

Offset

Length

Description

Record Type ID. A value of C0h (OEM) shall be used forArtesyn OEM records.

End of List / Version

[7] End of List. Set to 1b for the last record

[6:4] Reserved. Write as 000b.

[3:0] Record format version. Write as 2h.

Record Length

Record Checksum (zero checksum)

Header Checksum (zero checksum)

LSB of Manufacturer ID. Write as CDh.

Second Byte of Manufacturer ID. Write as 65h.

260 ATCA-7360 Installation and Use (6806800J07S )

FRU Information and Sensor Data Records

Table 9-2 Artesyn MAC Addresses Record (continued)

Offset

Length

N*7

Description

MSB of Manufacturer ID. Write as 00h.

Artesyn Record ID. 01h for Artesyn MAC Address Record.

Record Format Version. 00h for this specification.

Number of MAC Address Descriptors (N).

Artesyn MAC Address Descriptors. Refer to Table 21 for definitions of Artesyn MAC Address Descriptor.

Table 9-3 Artesyn MAC Address Descriptor

Offset

Length

Description

Interface Type. Refer to the table below for Interface

Type Assignments.

MAC Address. First Octet comes first.

Table 9-4 Interface Type Assignments

Interface Type Description

01h

02h

ATCA Base Interface or AMC / MicroTCA Common Options Region

ATCA Fabric Interface or AMC / MicroTCA Fat Pipe Region

03h

04h

Front Panel

AMC / MicroTCA Extended Fat Pipe Region

ATCA-7360 Installation and Use (6806800J07S) 261

FRU Information and Sensor Data Records

9.3 E-Keying

The following table lists the e-keying information provided by the blade. The respective information is contained in the point-to-point connectivity record area.

The fibre channel interfaces (link type extension 2) described in the point-to-point connectivity record area are physically not supported by the blade.

262

The following table details the contents of the Blade Point-to-Point Connectivity Record Area.

Table 9-5 Contents of the Blade Point-to-Point Connectivity Record Area

No.

Link

Grouping

Interface

0 (Base

Interface)

0 (Base

Interface)

1 (Fabric

Interface)

1 (Fabric

Interface)

Channel

Number

Ports

Link

Type

0x01 0

Link Type

Extension

1 - NOT SET

2 - NOT SET

3 - NOT SET

0 -SET

1 - NOT SET

2 - NOT SET

3 - NOT SET

0 -SET

1 - SET

2 -SET

3 -SET

0 -SET

1 - NOT SET

2 - NOT SET

3 - NOT SET

0x01 1

0x02 1

0x02 0

Link

Descriptor

Value

ATCA-7360 Installation and Use (6806800J07S )

FRU Information and Sensor Data Records

Table 9-5 Contents of the Blade Point-to-Point Connectivity Record Area (continued)

No.

Link

Grouping

Interface

1 (Fabric

Interface)

1 (Fabric

Interface)

2 (Update

Channel

Interface)

2 (Update

Channel

Interface)

2 (Update

Channel

Interface)

2 (Update

Channel

Interface)

2 (Update

Channel

Interface)

Channel

Number

Ports

Link

Type

0x02 1

Link Type

Extension

0 -SET

1 - NOT SET

2 - NOT SET

3 - NOT SET

0 - NOT SET

1 - SET

2 - NOT SET

3 - NOT SET

0 - NOT SET

1 - NOT SET

2 - SET

3 - NOT SET

0 - NOT SET

1 - NOT SET

2 - NOT SET

3 - SET

1 - SET

2 -SET

3 -SET

0 -SET

1 - NOT SET

2 - NOT SET

3 - NOT SET

0 -SET

1 - NOT SET

2 - NOT SET

3 - NOT SET

0x02 0

0xF0 0

0xF1 0

0xF2 0

0xF3 0

0xF4 0

Link

Descriptor

Value

ATCA-7360 Installation and Use (6806800J07S) 263

FRU Information and Sensor Data Records

9.4 Power Configuration

The following table provides the power configuration information.

Table 9-6 Power Configuration

Item Value

Dynamic power reconfiguration support

No Dynamic power configuration

Number of power draw levels

Early Power Draw Levels,

Watt

Steady state Power Draw

Levels, Watt

Transition from early to steady levels, sec

2.13GHz 6x4GB DDR3 + RTM =

180 - 220 Watts

Max - 260 Watts

0s -

Description

While the blade is powered, it supports only one power level.

The power level is fixed and does not change)

The amount of possible power levels

Complete early power level including IPMC

Complete steady power consumption including IPMC

9.5 Sensor Data Records

The sensors available on the blades are shown in the table below. See Table 9-8 on page 268 for

a detailed description of the Sensor Data Records.

Table 9-7 IPMI Sensors

Sensor Name

1.2V

1.5V

1.5V DDR3

1.8V Eth

12.0V

Sensor Type

Voltage

Sensor

Number

0x0A

0x09

0x0C

0x08

0x05

264 ATCA-7360 Installation and Use (6806800J07S )

FRU Information and Sensor Data Records

Table 9-7 IPMI Sensors (continued)

Sensor Name

3.3V

3.3V Mgmt

-48v Amps

-48v A Volts

-48v B Volts

ATCA-7360 IPMC

BMC Watchdog

Boot Bank

Boot Error

Boot Initiated

CPU0 temp

CPU1 temp

CPU Status

DDR 1 temp

DDR 2 temp

DDR 3 temp

DDR 4 temp

DDR 5 temp

DDR 6 temp

DDR 7 temp

DDR 8 temp

DDR 9 temp

DDR 10 temp

DDR 11 temp

DDR 12 temp

Fw Progress

Sensor Type

Voltage

Current

Voltage

Artesyn IPMC Status

Watchdog 2

Artesyn-specific Discrete

Digital

Boot Error

System Boot Initiated

Temperature

Processor

Temperature

System Firmware Progress

ATCA-7360 Installation and Use (6806800J07S)

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x13

0x14

0x27

0x28

0x26

0x19

0x1A

0x23

0x24

0x11

Sensor

Number

0x06

0x07

0x2B

0x29

0x2A

0x15

0x04

0x10

265

FRU Information and Sensor Data Records

Table 9-7 IPMI Sensors (continued)

Sensor Name

HoldUp Cap Volts

Hot Swap Carrier

Hotswap_RTM

Sensor

Bottom Edge Temp

Sensor

IPMB Physical

IPMC POST

IPMC temp

OS Boot

Top Edge Temp

Sensor

POST code

Sensor Type

Voltage

PICMG 3.0: FRU HotSwap

Temperature

PICMG 3.0: IPMB Physical Link 0x03

Management Subsystem

Health

0x0F

Temperature 0x25

OS Boot

Temperature

0x12

0x0E

Sensor

Number

0x2C

0x00

0x01

0x0D

0x17

PWR Entry Temp

PWR Entry Status

Power Good

Reset Source

VCC CPU0

Version change

Artesyn-specific Discrete

Digital

Temperature

OEM reserved

Entity Presence

Artesyn-specific Discrete

Digital

Voltage

Version Change

0x2D

0x2E

0x16

0x18

0x0B

0x02

266 ATCA-7360 Installation and Use (6806800J07S )

FRU Information and Sensor Data Records

The following figure shows the locations of all temperature sensors available on-board.

Figure 9-1 Location of Temperature Sensors

ATCA-7360 Installation and Use (6806800J07S) 267

FRU Information and Sensor Data Records

The sensors available on the blades are detailed in the table below.

For sensor threshold definition please use the "ipmitool" found on http://sourceforge.net/projects/ipmitool/files/ipmitool/ with the parameter "sensor".

Table 9-8 Sensor Data Records

Sensor

Number Sensor Name

Hot Swap

Carrier

Hotswap_RTM

Sensor Type

Hot Swap

0xF0

Hot Swap

0xF0

Event/Reading

Type

Sensor-specific discrete

0x6F

Sensor-specific discrete

0x6F

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Event

Data

Byte 1 Event Data Byte 2

[7:4] = Cause

[3:0] = Previous State

[7:4] = Cause

[3:0] = Previous State

Change type

Event Data Byte 3 Event Threshold/Description

FRU ID 0x0: M0

0x1: M1

0x2: M2

0x3: M3

0x4: M4

0x5: M5

0x6: M6

0x7: M7

FRU ID

0xFF

0x0: M0

0x1: M1

0x2: M2

0x3: M3

0x4: M4

0x5: M5

0x6: M6

0x7: M7

0x7: Software or F/W change successful

Version change

IPMB Physical

Version

Change

0x2B

Physical

IPMB-0

0xF1

Sensor-specific discrete

0x6F

Sensor-specific discrete

0x6F

0x0

0x1

0x2

0x3

[7:4] = Channel Number

[3:0] = Reserved reading 0x0: IPMB-A disabled, IPMB-B disabled

0x1: IPMB-A enabled, IPMB-B disabled

0x2: IPMB-A disabled, IPMB-B enabled

0x3: IPMB-A enabled, IPMB-B enabled

Asrt: Assertion Unr: Upper non-recoverable threshold Uc: Upper critical threshold Unc: Upper non-critical threshold

Deass: Deassertion Lnr: Lower non-recoverable threshold Lc: Lower critical threshold Lnc: Lower non-critical threshold

268

Assertion

Deassertion Rearm

Asrt Auto

Asrt

Auto

ATCA-7360 Installation and Use (6806800J07S )

FRU Information and Sensor Data Records

Table 9-8 Sensor Data Records (continued)

Sensor

Number Sensor Name Sensor Type

Event/Reading

Type

Event

Data

Byte 1 Event Data Byte 2 Event Data Byte 3 Event Threshold/Description

4 BMC

Watchdog

Watchdog 2

0x23

Sensor-specific discrete

0x6F

Threshold

0x01

Threshold

0x01

Threshold

0x01

Threshold

0x01

Threshold

0x01

Threshold

0x01

Threshold

0x01

Threshold

0x01

0x0

0x1

0x2

0x3

0x8

See IPMI Spec 0xFF 0x0: Timer expired

0x1: Hard Reset

0x2: Power Down

0x3: Power Cycle

0x8: Timer Interrupt unr uc lnr lc 5

12.0V

3.3V

3.3V Mgmt

1.8V Eth

1.5V

1.2V

VCC CPU0

1.5V DDR3

Voltage

0x02

Voltage

0x02

Voltage

0x02

Voltage

0x02

Voltage

0x02

Voltage

0x02

Voltage

0x02

Voltage

0x02 reading reading reading reading reading reading reading reading threshold threshold threshold threshold threshold threshold threshold threshold unr uc lnr lc unr uc lnr lc unr uc lnr lc unr uc lnr lc unr uc lnr lc unr uc lnr lc unr uc lnr lc

Bottom Edge

Temp

Top Edge

Temp

0x01

Temp

0x01

Threshold

0x01

Threshold

0x01 reading reading threshold threshold unr uc unc unr uc unc

Asrt: Assertion Unr: Upper non-recoverable threshold Uc: Upper critical threshold Unc: Upper non-critical threshold

Deass: Deassertion Lnr: Lower non-recoverable threshold Lc: Lower critical threshold Lnc: Lower non-critical threshold

Assertion

Deassertion Rearm

Asrt Auto

Asrt / Deass Auto

ATCA-7360 Installation and Use (6806800J07S) 269

FRU Information and Sensor Data Records

Table 9-8 Sensor Data Records (continued)

Sensor

Number

Sensor Name

IPMC POST

Sensor Type

Management

Subsystem

Health

0x28

OEM

0xD2

Event/Reading

Type digital Discrete

0x06

Event

Data

Byte 1 Event Data Byte 2

0x0

0x1

0xFF

Event Data Byte 3

0xFF

Event Threshold/Description

0x0: Performance Met

0x1: Performance Lags

Boot Bank

Fw Progress System

Firmware

Progress

0x0F

OS Boot

0x1F

Sensor-specific discrete

0x6F

Sensor-specific discrete

0x6F

0x0

0x1

0x2

0xFF

Refer

IPMI Error Logging page 122 on

0xFF

Refer

IPMI Error

Logging

122 on page

0x0: Boot Bank A

0x0: System Firmware Error

0x1: System Firmware Hang

0x2: System Firmware Progress

18 OS Boot Sensor-specific discrete

0x6F

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0xFF 0xFF 0x0: A: boot completed

0x1: C: boot completed

0x2: PXE boot completed

0x3: Diagnostic boot completed

0x4: CD_ROM boot completed

0x5: ROM boot completed

0x6: boot completed

19 Boot Error Boot Error

0x1E

Sensor-specific discrete

0x6F

0x0

0x1

0x2

0x3

0x4

0xFF 0xFF 0x0: No Bootable media

Asrt: Assertion Unr: Upper non-recoverable threshold Uc: Upper critical threshold Unc: Upper non-critical threshold

Deass: Deassertion Lnr: Lower non-recoverable threshold Lc: Lower critical threshold Lnc: Lower non-critical threshold

Assertion

Deassertion Rearm

Asrt Auto

Asrt

Auto

270 ATCA-7360 Installation and Use (6806800J07S )

FRU Information and Sensor Data Records

Table 9-8 Sensor Data Records (continued)

Sensor

Number

Sensor Name

Boot Initiated

ATCA-7360

IPMC

Sensor Type

System Boot

Initiated

0x1D

OEM

0xD5

Event/Reading

Type

Sensor-specific discrete

0x6F

Sensor-specific discrete

0x6F

Event

Data

Byte 1 Event Data Byte 2

0x0

0x1

0x2

0x3

0x4

0x0

0x1

0x2

0x3

0x4

0x5

0x6

[7:4] Active BIOS major version

[3:0] Active BIOS minor version

Event Data Byte 3 Event Threshold/Description

[7:4] Active BIOS sub-minor version

[3:0] Reserved

0x0: Initiated by power up

0x1: Initiated by hard reset

0x2: Initiated by warm reset

0x3: User requested PXE boot

0x4: Automatic boot to diagnostic

0x0: Watchdog Reset

0x1: Software Reset

0x2: Power Failure

0x3: Hard Boot

0x4: Cold Boot

0x5: Warm Boot

0x6: Reserved

Power Good

POST code

Entity

Presence

0x25

OEM

0xD2

Sensor-specific discrete

0x6F

Sensor-specific discrete

0x6F

0x0

0x1

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0xFF

0xFF 0x0: Entity Present

0x1: Entity Absent

0x0: No events for this sensor.

Reading according to EFI BIOS port80 status codes.

Asrt: Assertion Unr: Upper non-recoverable threshold Uc: Upper critical threshold Unc: Upper non-critical threshold

Deass: Deassertion Lnr: Lower non-recoverable threshold Lc: Lower critical threshold Lnc: Lower non-critical threshold

Assertion

Deassertion Rearm

Asrt Auto

Asrt

Auto

ATCA-7360 Installation and Use (6806800J07S) 271

FRU Information and Sensor Data Records

Table 9-8 Sensor Data Records (continued)

Sensor

Number

Sensor Name

Reset Source

Sensor Type

OEM

0xD2

Event/Reading

Type

Sensor-specific discrete

0x6F

Threshold

0x01

Threshold

0x01

Threshold

0x01

Threshold

0x01

Threshold

0x01

Threshold

0x01

Threshold

0x01

Threshold

0x01

Event

Data

Byte 1 Event Data Byte 2

0x0 [7] =

IPMC_RST_REQ_Payload

[6] = XDP0_DBRST_CPU

[5] = CPU_RST_CPU

[4] RTM_PB_RST_Reset

[3] = XDP1_DBRST_CPU

[2] = PB_RST_Face

[1] XDP0_BRD_PWROK

[0] = PWR_GOOD reading

Event Data Byte 3

[7:2] = Reserved

[1] = IPMC Pre-

Timout

[0] = IPMC

Watchdog

Timeout

Event Threshold/Description

0x0: Payload Reset detected.

Cause delivered in Event Byte

2/3

DDR 1 temp

DDR 2 temp

DDR 3 temp

DDR 4 temp

DDR 5 temp

DDR 6 temp

DDR 7 temp

DDR 8 temp

Temp

0x01

Temp

0x01

Temp

0x01

Temp

0x01

Temp

0x01

Temp

0x01

Temp

0x01

Temp

0x01 reading reading reading reading reading reading reading threshold threshold threshold threshold threshold threshold threshold threshold unr uc unc unr uc unc unr uc unc unr uc unc unr uc unc unr uc unc unr uc unc unr uc unc

DDR 9 temp

DDR 10 temp

Temp

0x01

Temp

0x01

Threshold

0x01

Threshold

0x01 reading reading threshold threshold unr uc unc unr uc unc

Asrt: Assertion Unr: Upper non-recoverable threshold Uc: Upper critical threshold Unc: Upper non-critical threshold

Deass: Deassertion Lnr: Lower non-recoverable threshold Lc: Lower critical threshold Lnc: Lower non-critical threshold

272

Assertion

Deassertion Rearm

Asrt Auto

Asrt / Deass Auto

ATCA-7360 Installation and Use (6806800J07S )

FRU Information and Sensor Data Records

Table 9-8 Sensor Data Records (continued)

Sensor

Number

Sensor Name

DDR 11 temp

DDR 12 temp

IPMC temp

Sensor Type

Temp

0x01

Temp

0x01

Temp

0x01

Event/Reading

Type

Threshold

0x01

Threshold

0x01

Threshold

0x01

Event

Data

Byte 1 Event Data Byte 2 reading reading reading

Event Data Byte 3 threshold threshold threshold

Event Threshold/Description unr uc unc unr uc unc unr uc unc

CPU Status

CPU0 temp

CPU1 temp

-48v A Volts

-48v B Volts

-48v Amps

HoldUp Cap

Volts

Processor

0x07

Temp

0x01

Temp

0x01

Voltage

0x02

Voltage

0x02

Current

0x03

Voltage

0x02

Sensor-specific discrete

0x6F

Threshold

0x01

Threshold

0x01

Threshold

0x01

Threshold

0x01

Threshold

0x01

Threshold

0x01

0x1 0xFF reading reading reading reading reading reading

0xFF threshold threshold threshold threshold threshold threshold

0x1: Thermal Trip uc unc uc unc unr uc lnr lc unr uc lnr lc

No Thresholds unr uc lnr lc

45 PWR Entry

Temp

0x01

Threshold

0x01 reading threshold unr uc unc

Asrt: Assertion Unr: Upper non-recoverable threshold Uc: Upper critical threshold Unc: Upper non-critical threshold

Deass: Deassertion Lnr: Lower non-recoverable threshold Lc: Lower critical threshold Lnc: Lower non-critical threshold

Assertion

Deassertion Rearm

Asrt / Deass Auto

Asrt Auto

Asrt / Deass Auto

Auto

Asrt / Deass Auto

ATCA-7360 Installation and Use (6806800J07S) 273

FRU Information and Sensor Data Records

Table 9-8 Sensor Data Records (continued)

Sensor

Number

Sensor Name

PWR Entry

Status

Memory

Sensor Type

OEM

0xD7

Memory

0x0C

Event/Reading

Type

Sensor-specific discrete

0x6F

Sensor-specific discrete

0x6F

Event

Data

Byte 1 Event Data Byte 2

0x0

0x1

0x4

0x5

0x6

0x7

Pwr Entry Module:

[6] = VOUT_low

[5] = Hotswap

[4] = Holdup

[2] = Alarm

[1] = Enable_B

[0] = Enable_A

0xFF

Event Data Byte 3

[7:6] = Pwr Entry

Module

0 = Default

1 = Reserved

[7] = CPU Socket

0/1

[6:5] = DIMM channel 0..2

[4] = DIMM number per

Channel 0/1

[3:0] = DIMM number 1..12

0xF in DIMM number means unknown number

0xFF

Event Threshold/Description

0x0: Pwr Entry Module Status

Change detected

0x0: Correctable ECC

0x1: Uncorrectable ECC

0x4: Memory Device Disabled

0x5: Correctable ECC

0x6: Presence detected

0x7: Configuration error.

Critical IRQ

Battery

48V A Supply

48V B Supply

Critical

Interrupt

0x13

Battery

0x29

Power Supply

0x08

Power Supply

0x08

Sensor-specific discrete

0x6F

Sensor-specific discrete

0x6F

Sensor-specific discrete

0x6F

Sensor-specific discrete

0x6F

0x4

0x5

0x1

0x0

0x1

0x0

0x1

0xFF

See IPMI Spec

0xFF

0x4: PCI PERR

0x5: PCI SERR

0x1: Battery failed

0x0: Presence detected

0x1: Power Supply Failure detected

0x0: Presence detected

0x1: Power Supply Failure detected

Asrt: Assertion Unr: Upper non-recoverable threshold Uc: Upper critical threshold Unc: Upper non-critical threshold

Deass: Deassertion Lnr: Lower non-recoverable threshold Lc: Lower critical threshold Lnc: Lower non-critical threshold

Assertion

Deassertion Rearm

Asrt Auto

Asrt

Auto

Asrt / Deass Auto

274 ATCA-7360 Installation and Use (6806800J07S )

Chapter 10 Firmware Upgrade

10.1 HPM.1 Firmware Upgrade

10.1.1 Overview

The primary update mechanism for the ATCA-7365 blades is the FCU tool which is delivered with the BBS package for the board. However, the ATCA-736X board family also supports upgrade of the firmware with the HPM.1 specification. Upgradeable components of the board include the BIOS flash, FPGA flash, and IPMC flash. For update, it is recommended to use the

Pigeon Point System modified Ipmitool.

10.1.2 Installing the Ipmitool

Procedure

To install the ipmitool, proceed as follows:

1. Download the latest ipmitool-<version>.tar.bz2 tar file from http://ipmitool.sourceforge.net

to your blade.

2. Extract the source code.

Prompt>tar -xzvf Ipmitool-<version>.tgz

3. Go to the directory where you have extracted the Ipmitool.

Prompt>cd <path>/Ipmitool-<version>

4. Build the Ipmitool.

Prompt>./configure && make && make install

10.1.2.1 Update Procedure

The Ipmitool HPM update requires two steps for an update:

1. Upgrade the component.

Example: ipmitool hpm upgrade <file>

ATCA-7360 Installation and Use (6806800J07S) 275

Firmware Upgrade

2. Activate the component.

Example: ipmitool hpm activate

Both steps can also be integrated into one command.

ipmitool hpm upgrade <file> activate

10.1.3 Interface

The HPM.1 upgrade supports three different interfaces for upgrading the firmware. These are

KCS, IPMB-0, and LAN over BASE. The LAN interface is only supported if the payload is powered on (M4). The BASE Ethernet controller also has to be powered on for this feature.

10.1.3.1 KCS Interface

The standard way to upgrade the firmware of the payload is through the KCS interface. Update through this interface is the fastest HPM.1 upgrade. The images and the Ipmitool need to be on the payload to be upgraded.

Example:

Prompt>ipmitool hpm upgrade <file>

10.1.3.2 IPMB-0

This interface represents the backplane IPMI bus and allows remote firmware upgrade. The count of the simultaneous upgrades is limited because of the bus speed.

Example from shelf manger:

Prompt>Ipmitool -t 0x92 hpm upgrade <file>

Example with RMCP+:

Prompt>ipmitool -I lan -H 192.168.34.8 -U Administrator -P

Administrator -t 0x92 hpm upgrade <file>

276 ATCA-7360 Installation and Use (6806800J07S )

Firmware Upgrade

10.1.3.3 LAN over Ethernet (BASE)

The LAN over Ethernet interface uses the BASE Ethernet controller to do firmware upgrades.

The interface has to be configured before the first use. Configuring this interface is described in

Chapter 7, Configure SOL Parameters, on page 212 .

Example:

Prompt>Ipmitool -I lan -H 172.16.0.221 -U "" -P "" hpm upgrade

<file>

10.2 IPMC Upgrade

The IPMC component is fully HPM.1 compatible and contains three elements as shown on the figure below.

Figure 10-1 IPMC Component Elements

There are images for the boot loader and the firmware. There is also a combined image containing the boot loader and the firmware. The Boot loader update should only be done if it's required.

ATCA-7360 Installation and Use (6806800J07S) 277

Firmware Upgrade

The boot loader does not perform any upgrade action. The boot loader is able to boot either of two redundant copies of the firmware in the flash depending on the current value of the special partition status byte that is stored in the internal IPMC EEPROM. The boot loader can fall back to the backup copy by booting the alternate partition. The boot loader manages two firmware partitions; the active and backup partition. It is responsible for detecting if the active firmware is invalid or has failed. If the active firmware failed or is invalid, the Boot loader will switch to the backup partition. When switching, the partitions change their roles. Switching of the partitions also takes place when the firmware is upgraded and activated using the HPM.1 upgrade procedure.

The firmware image is the regular firmware and change with every update.

10.3 BIOS/FPGA Upgrade

Both components (BIOS and FPGA) have two independent boot banks. The switching of this boot banks is not supported by HPM commands of ATCA-736X.

Both BIOS/FPGA boot banks can be updated with HPM.1. The BIOS/FPGA upgrade is not fully

HPM.1 compatible. Payload update of this device is required. Without this update, automatic boot bank switching via the IPMC is not possible. Boot bank switching is a requirement for

HPM.1 to activate.

278 ATCA-7360 Installation and Use (6806800J07S )

Firmware Upgrade

Payload always has access to the active boot bank and the IPMC always has access to the inactive boot bank. All HPM.1 commands are directed to the inactive boot bank (this includes

"get component properties"). The following figure shows the connection of the SPI busses which are switched with "Set System Boot Options" -> Boot Bank (parameter 0x96). Description can be found in the document "OEM Extensions for ATCA / MicroTCA Hardware Platform

Management System". HPM activate command is not supported for the BIOS/FPGA component.

Figure 10-2 SPI Busses Connection

FPGA and BIOS upgrade may last from fifteen minutes up to two hours. The time varies with the selected programming interface. A power cycle is required after the BIOS/FPGA update.

ATCA-7360 Installation and Use (6806800J07S) 279

Firmware Upgrade

10.4 Upgrade Package

The HPM upgrade package for this release contains the following files:

Table 10-1 HPM Upgrade Package

Filename atca-7360-hpm.1-all.img

atca-7360-hpm.1-boot.img

atca-7360-hpm.1-ipmc.img

Description

HPM file contains the boot loader and firmware image

HPM file contains only the boot loader image

HPM file contains only the firmware image

9806865F07E_A736BIOS-120.bin.hpm

HPM file contains the version 1.2.0 BIOS image atca7360_spi_13_old.bin.hpm

HPM file contains the version 0.13 FPGA image

Ipmitool-1.8.9-pps-7.tgz

PPS modified Ipmitool necessary for HPM upgrades on

ATCA736X

280 ATCA-7360 Installation and Use (6806800J07S )

Appendix A

Replacing the Battery

A.1 Replacing the Battery

Some blade variants contain an on-board battery. Its location is shown in the following figure.

A battery-less variant based on SUPERCAP is available on demand.

Figure A-1 Location of On-board Battery

Battery

MH7

J256

DISP1

R975 R973

R971

J233

DISP2

J104

R904

120 C1244

C1267

M31

C1265

C1273

C1272

C4763

C1277

C1276

C1274

C1275

LED18

LED15

R1067

120

239

120

239

120

239

120

239

120

239

CE10

J126

J128

R937 C1212 C1213

J204 J234

R3597

J285

J31

BATH1

R938

R1631

R1636

C1238

R1603

R1596

C1239

C4628

C1211 C1210

J135

J105

J76 J122 J236

J208

J119

J121

Q85

M33

C4087

J235

J257

Q83

R3466

L95

P18

FIL14 FIL13

Q82

C4082

Q80

L94

C1243 R1028

R1669 R2725

R1666

R1667

C2085

R1663

R1662

C2077

R2719

R2718

C3144

C4053

C4765

C4766

C4767

C4768

169

C4215

167

YEL GRN

167

SW7

P17

J199 J29

R3591

C4690

C4691

R3471

C4159

J250

R3482

R3481

R3480

R3479

R3478

R3477

R3476

R3475

R3455

MH9901

R3492

J77

J120

J278

C4725 C1514

J228

J227

C3195

C3179

C3180

C3188

C3196

C3197

C3186

C3178

DN2

P42

J286

J49

C3193

C3192

C3182

C3191

C3185

C3194

C3190

C3189

L17 L18

P27

R1210 R1209

D57 D56

R2501

R950

J5002

J282

Q26 Q25

C525

R3206

R3207

R3188

R3174

R407

C533

C527

C543

C4761

C536

C532

C552

C546

C522

C2886

C529

C2885

C560

C549

C535

C528

C558

C537

C4760

C534

R2854

R2852

R2853

R2694

R2695

C530

C544

C523

C3132 R2690

J255

J195 J190 J194

P05

R1664

R1665

C2084

R2708

P06

121

P03

R1390

R1382

R1206

C1433

R1189

C1422

J116

D19

C1451

R1213

R1207

R1192

R1211

Q44

R1627

R1624

Q40

L80

C3340 D54

Q42

Q38

L78

C4512

C4509

C4513

C2048

P45

J207

P46

C4516

C4511

C4520

Q41

Q37

L77

40 38

36 34

33 31 29

27 25

23 21

R1660

R1661

C2076

R2707

P04

MH10

121

43 41

42 40 38

39 37 35

36 34

33 31

3032

28 26

27 25 23

24 22

19 17

18 16

13 11

12 10

P01

R3045 R2716

R2717

C3143

R2706

P02

121

167

C4217

169

C4764 C4769 C4770 C4771

C4203

Q43

Q39

L79

C1258

C1260

J35

J34

P9910

C1263

C1262

J111

R1598

R1597

R1615

R1629

R1630

R2709

C2094

R1676

R1675

R2488

C2095

R1677

R1678

L83

10 12

16 18

15 17

30 32

29 31

33 35

36 38

41 43

C4498

C4497

C4490

C2029

C4496

C4495

C4494

12 14

24 2

6 28

32 34

31 33 3

37 3 9

L93 L82 L84

R1594

R1591

C4477

C4478

C4486

C4484

C4483 R2529

C2894

C3955

C3958

C3954

J187

L91

C3862

C3864

C3865

Q72

Q71

R3607

C3859

C3959

C3867

121

R2710

C2100

R1680

R1679

R2711

C3147

R2721

R2720

R3334

R3406 R3408 R3411

C3961

C3858

J254

C4624

R3343

C4742

R3414

C3968

R3346

R3413

R3415

C3969

C4643

R3498

R3518

R3519

R3520

R3543

R3521

R3522

R3523

R3524

R3525

J277

C4722

C4723

C4724

R3620

R3619 M27

L96

167

R3499

C4202

L97

C2101

R1681

R1682

C3148

R2722

R2723

C2862

R2486

C2863

C2867

C3067

C3052

C3058

C3050

R2667

R2668

R2665

R2666

A1 ZHS3

Q51

Q55

Q77

Q78

Q50

Q54

Q52

Q56

ZHS4

MH19

CE29

CE30

GH10

CD10

A10

P23

CE31

GH1

R1249

CD1

J118

C1490

C4338

R1252 R1276

R1275

ZHS5

C4332

R1272

L21

R3191 R3194

R3193

R3184

R3185

R3189

R3190

R3210

R3186 R3204

R3233

R3232

R3203

R3205

Q93

J242

R3080

A24

LED28

LED30

LED31

GH10

C4688

C4689

C4687

CD10

L22

A10

J232

P20

AD1

M29

U 1

C4005

C3988

C1059 R704

U 1 9

C1060

C4032

C4016

U 1

J71

J188

CD1

ZKEY2

J26

A1 A30

P39

R2738

J46

P38

AK1

A10

P32

L50

R2259

R2790

C2955

C2957

C2975

C2977

C2974

C2976

C2954

C2956

R2080

R2037

R2032

L51

C4683

C4682

L49

C4678

C4686

C4672

C4669

C4680

C4667

C4674

C4676

R1240 R1241

C1473

AT1

C1472

C1470

C1468

GH1

L20 L19

C3026

T220

C1463

R1236

R1235

R1244

R1223

C1453

R1238

R1243

J117

C1481 R1247 R1219

R1242

R1225

D21

C1480

R1221

R1239

R1228

A10

U20

R3349

C3901

P30

P24

GH1

CD1

L89

239

120

239

120

239

C3822

C3816

C3819

C3824

P12

P11

P14

P13

P16

P15

A36 C3065

L69

R2613 R2609

C2909

C2912

R2741

C2496

R2087

R2089

R2094

R2083

R2118

R2049

R2038

R2023

R2109

R2057

R2108

R2085

R2091

R2131

R2735

R2060

R2026

R2029

R2048

R2021

R2022

R2020

L38

C2432

C2439

R2611

C4753

J196

R2939

R2940

R2921

R3057

R2917

R2885

R2886

FIL49

C2901

C4749

R2079

R2077

R2058

R2031

R2034

R2039

R2076

R2078

R2056

R2923

R2922

R2918

R2919

R2920

Q66

C3939

ZKEY4

MH13

Q68 Q69

C3974

+ C3971

C3970

C3840

R3418

R3419

R3420

R3421

R3422

R3423

R3424

R3319

P200

J253

R3431

C3827

R3327

C3818

C3972

R3417

R3416

C3973

R3329

R3328

FIL38

C3821

C3975

MH20

120

L87

R3625

R3681

R3682

ATCA-7360 Installation and Use (6806800J07S) 281

Replacing the Battery

The battery provides data retention of seven years summing up all periods of actual data use.

Artesyn, therefore assumes that there is usually no need to replace the battery except, for example, in case of long-term spare part handling.

Board/System Damage

Incorrect replacement of lithium batteries can result in a hazardous explosion.

Therefore, replace the battery as described in this chapter.

Data Loss

If the battery does not provide enough power anymore, the RTC is initialized and the data in the NVRAM is lost.

Therefore, replace the battery before seven years of actual battery use have elapsed.

Data Loss

Replacing the battery always results in data loss of the devices which use the battery as power backup.

Therefore, back up affected data before replacing the battery.

Data Loss

If installing another battery type other than what is mounted at board delivery may cause data loss. This is because other battery types may be specified for other environments or may have a shorter lifespan.

Therefore, only use the same type of lithium battery as is already installed.

282 ATCA-7360 Installation and Use (6806800J07S )

Replacing the Battery

Replacement Procedure

To replace the battery, proceed as follows:

1. Remove battery.

PCB and Battery Holder Damage

Removing the battery with a screw driver may damage the PCB or the battery holder. To prevent this damage, do not use a screw driver to remove the battery from its holder.

2. Install the new battery following the "positive" and "negative" signs.

ATCA-7360 Installation and Use (6806800J07S) 283

Replacing the Battery

284 ATCA-7360 Installation and Use (6806800J07S )

Appendix B

B.1 Artesyn Embedded Technologies - Embedded

Computing Documentation

The publications listed below are referenced in this manual. You can obtain electronic copies of

Artesyn Embedded Technologies - Embedded Computing publications by contacting your local Artesyn sales office. For released products, you can also visit our Web site for the latest copies of our product documentation.

1. Go to www.artesyn.com/computing/support/product/technical-documentation.php

2. Under FILTER OPTIONS, click the Document types drop-down list box to select the type of document you are looking for.

3. In the Search text box, type the product name and click GO.

Table B-1 Artesyn Embedded Technologies - Embedded Computing Publications

Document Title

RTM-ATCA-7360 Installation and Use

Basic Blade Services Software for the ATCA-7360

Programmer’s Reference

ATCA-7360 Quick Start Guide

ATCA-7360 Safety Notes Summary

Publication Number

6806800J08

6806800K42

6806800J10

6806800J11

ATCA-7360 Installation and Use (6806800J07S) 285

Related Documentation

B.2 Manufacturers’ Documents

For additional information, refer to the following table for manufacturers’ data sheets or user’s manuals. As an additional help, a source for the listed document is provided. Please note that, while these sources have been verified, the information is subject to change without notice.

Table B-2 Manufacturer’s Documents

Company

Intel

LSI Logic

SMSC

Document Title

6300ESB I/O Controller Data sheet

82546EB/GB Gigabit Ethernet Controller Documentation

6700PXH 64-bit PCI-to-PCI bridge Data sheet

E7520 Memory Controller Data sheet

IPMI V1.5 Specifications

Intel® Xeon

Processor Technical Documents

LSIFC929XL Dual-Channel PCI-X to Fibre Channel Controller

Technical Documents

LPC47S422 Enhanced Super I/O Controller Data sheets and

Application Notes

B.3 Related Specifications

For additional information, refer to the following table for related specifications. As an additional help, a source for the listed document is provided. Please note that, while these sources have been verified, the information is subject to change without notice.

Table B-3 Related Specifications

Organization

PCI-SIG

PICMG

Document Title

PCI Local Bus Specification Revision 2.2

PCI-X Addendum to the PCI Local Bus Specification 1.0

PICMG 3.0 Revision 1.0 Advanced TCA Base Specification

PICMG 3.1 Revision 1.0 Specification

Ethernet/Fiber Channel for AdvancedTCA Systems

286 ATCA-7360 Installation and Use (6806800J07S )

Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies, Inc.

All other product or service names are the property of their respective owners.