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Intel ® Quark™ SoC X1000
Platform Design Guide (PDG)
Revision 002US
June 2014
Order Number: 330258-002US
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Contents—Intel ® Quark™ SoC X1000
Contents
Low Halogen Flame Retardant Stack-Up Considerations .......................................... 19
Low Halogen Background ........................................................................ 19
Choosing a Low Halogen Material.............................................................. 19
Electrical Limits of Low Halogen Material Properties..................................... 19
Backward and Forward Coupling Coefficient Calculation .......................................... 20
Single-Ended and Differential-Impedance Transmission Line Specifications................ 22
Overview of Fiber Weave......................................................................... 23
Fiber Weave Effect versus Transfer Rate and Trace Length........................... 25
Specific Routing Configurations ................................................................ 26
Zig-Zag or Slanted Routing...................................................................... 26
Using Alternate PCB Materials .................................................................. 28
Supported Memory Configurations ............................................................ 29
Memory Population Rules ........................................................................ 29
Reference Documents ............................................................................. 29
Design Constraints-based Routing ............................................................ 29
Single Rank Fly-by Topology with Active VTT Termination ............................ 31
Memory Stackup Guidelines ..................................................................... 36
Memory Configurations and Connectivity ................................................... 37
ODT Signal Connectivity and Support .......................................... 37
Memory Physical Layout Guidelines........................................................... 37
General Routing Guidelines ........................................................ 37
Byte Lane Placement ................................................................. 37
Via Stitching and Placement ....................................................... 38
Memory Bit and Byte Lane Swapping ........................................................ 38
Memory Length Matching Guidelines ......................................................... 38
Length Matching and Length Formulas ......................................... 38
Package Length Compensation ................................................... 38
Memory Decoupling Guidelines................................................................. 38
Memory Reference Voltage and Compensation Guidelines ....................................... 38
SoC DDR Reference Voltage..................................................................... 38
DRAM Reference Voltage ......................................................................... 39
Routing Guidelines for Compensation Signals ............................................. 39
Supported Configuration Options for PCIe* Ports ........................................ 41
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Intel ® Quark™ SoC X1000—Contents
PCI Express* Lane Polarity Inversion.........................................................41
PCI Express* Port Lane Reversal...............................................................42
PCH PCIe* Disabling and Termination Guidelines.........................................42
Length Matching Guidelines......................................................................42
Impedance Compensation and Voltage Reference........................................42
Reference Documents..............................................................................43
Expansion Card Connector Topology..........................................................44
Compliance Documents ...........................................................................47
USB Connector Recommendations.............................................................52
External Connector Recommendations..........................................52
Daughter Card Design Guidelines ................................................53
Stackup and Layer Utilization Guidelines ....................................................53
USB 2.0 Configuration, Connectivity, Block Diagram ...............................................53
Length Matching and Length Formulas.......................................................54
EMI and ESD Protection ...........................................................................54
General Design Considerations .................................................................56
Detailed Routing Requirements.................................................................56
C Signals...........................................................................58
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Contents—Intel ® Quark™ SoC X1000
10.3.1.1 Differential Routing Considerations.............................................. 76
10.3.1.2 Stitching Via Usage and Placement.............................................. 76
10.4.1 Crystal External Load Capacitor Requirements............................................ 78
11.3.1 SPI Single Flash Device Topology Guidelines .............................................. 82
11.3.1.1 SPI Single Flash Device Routing Guideline .................................... 82
11.3.1.2 SPI Single Flash Device Length Matching Requirement ................... 83
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Intel ® Quark™ SoC X1000—Contents
15.3.8 Power-well Isolation Control Signal Requirements ..................................... 103
15.3.11platform_S0_1P0_pwrok Generation ....................................................... 103
15.3.12platform_S0_1P5_pwrok Generation ....................................................... 103
15.3.14Additional Power Sequencing Considerations ............................................ 104
17.3.2 Voltage Regulator Module Current Loop Radiation ..................................... 110
17.4.2 Avoid Signal Traces Too Close to the Edges of Planes................................. 114
17.4.3 Avoid Unnecessary Traces Too Close to IO and Other Connectors ................ 114
17.4.4 EMI Mitigation through Stitching and Decoupling Capacitors ....................... 115
17.4.4.1 Stitching Capacitors................................................................. 116
17.4.4.2 Decoupling Capacitors.............................................................. 118
17.4.5.1 USB Common Mode Choke Recommendation .............................. 120
17.4.6 USB 2.0 Common Mode Chokes .............................................................. 120
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Contents—Intel ® Quark™ SoC X1000
17.4.9.1 Layer Transition...................................................................... 123
17.4.9.2 Clustered Signal Vias............................................................... 123
18.2.3 USB ESD Diode Recommendation ........................................................... 130
18.3.2 USB 2.0 ESD Protection Diode Vendors ................................................... 136
21.1.2.1 RMII Interface Signals ............................................................. 147
21.1.2.2 RMII Reference Clock .............................................................. 147
21.1.3.1 MDIO Connectivity .................................................................. 147
21.2.1 General Design Considerations for PHYs .................................................. 147
21.2.1.1 Clock Source .......................................................................... 148
21.2.1.2 Magnetics Module ................................................................... 148
21.2.1.3 Criteria for Integrated Magnetics Electrical Qualification ............... 148
21.2.2 NVM Configuration for PHY Implementations ............................................ 149
Quark™ SoC X1000 – MDIO/RMII LOM Design Guidelines............................ 151
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Intel ® Quark™ SoC X1000—Contents
21.6.1 PHY Placement Recommendations........................................................... 152
Length Matching and Length Formulas..................................................... 171
Breakout Example and Guidelines ........................................................... 174
Via Placement and Via Usage Optimization ............................................... 175
Bend Optimization Guidelines ................................................................. 177
Exposed Pad* (e-Pad*) Design and SMT Assembly Guide ....................................... 181
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Contents—Intel ® Quark™ SoC X1000
Figures
15 An Example of a PCB Cut Such That Its Edges are Rotated Relative to the Fiber
16 DQ/DM - Data Routing Topology for a Single Rank 4L Fly-by Design - PCB Type 3............. 31
17 DQS - Data Strobes Routing Topology for a Single Rank 4L Fly-by Design - PCB Type 3..... 31
18 ODT/CKE/CS - Control Routing Topology for a Single Rank 4L Fly-by Design - PCB Type 3 . 33
19 MA/BS/CAS/RAS/ WE - Command Routing Topology for a Single Rank 4L Fly–by
20 Clock Routing Topology for a Single Rank 4L Fly-by Design—PCB Type 3 ......................... 35
40 SPI Single Flash Device Routing Guidelines for LSPI0_MOSI, LSPI0_MISO,
Quark™ SoC X1000 Power-up Sequence............................................................ 99
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Intel ® Quark™ SoC X1000—Contents
59 Changing Referencing, Lack of Referencing, Void-crossing, and Split-crossing are Not
63 Stitching Capacitors Could Create Low Impedance Path for Return Currents ................... 116
85 Differential S-parameters from Ceramic 1-line, Si 4-line and Si 6-line
94 Effect of LAN Device Placed Too Close To a RJ-45 Connector or Chassis Opening ............. 153
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Intel ® Quark™ SoC X1000—Contents
Tables
8 DQ/DQS Routing Guidelines and Settings for a Single Rank 4L Fly-by Design—PCB Type 3 .31
9 Control - Routing Guidelines and Settings for a Single Rank 4L Fly-by Design—PCB Type 3.33
10 Command Routing Guidelines and Settings for a Single Rank 4L Fly-by Design—PCB Type
11 Clock Routing Guidelines and settings for a Single Rank 4L Fly-by Design—PCB Type 3 ......36
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Contents—Intel ® Quark™ SoC X1000
64 MDIO Data Signals on the Intel
Quark™ SoC X1000 ................................................. 146
69 Maximum Trace Lengths Based on Trace Geometry and Board Stack-Up........................ 155
71 MAC0_TXDATA<1:0>; MAC0_TXEN; MAC0_MDC; MAC0_MDIO .................................... 165
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Intel ® Quark™ SoC X1000—Revision History
Revision History
Revision
002
001
Description
Removed Section 4.1.7 Difference Between PCIe Ports and Lanes
Updated Figure 35 Clock Integration Distribution Diagram
Removed Section 11.3.2 Dual SPI Devices + Bootflash Topology Guidelines
Removed Section 21.17 Considerations for Layout
Removed Figure A-5 Example of Poor Length Matching
Removed Section A.4 General Differential Stackup Guidelines
Removed Section A.7 General Docking Connector Recommendations for Differential
Interfaces
Other changes are marked with change bars
Initial Public Release
§ §
Date
June 2014
March 2014
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Introduction—Intel ® Quark™ SoC X1000
1.0
Introduction
This Design Guide provides motherboard implementation recommendations for a platform based on the Intel
®
Quark™ SoC X1000 processor. The Intel
®
Quark™ SoC
X1000 Platform Design Guide has been developed to ensure maximum flexibility for board designers while reducing the risk of board related issues. Design recommendations are based on Intel’s simulations and lab experience and are strongly recommended, if not necessary, to meet the timing and signal quality specifications.
Design recommendations are based on the reference platforms designed by Intel. They should be used as an example but may not be applicable to particular designs.
The guidelines recommended in this document are based on experience, simulation, and preliminary validation work done at Intel while developing the Intel ® Quark™ SoC
X1000-based platform. This work is ongoing, and these recommendations are subject to change. Metric units are used in some sections in addition to the standard use of
U.S. customary system of units (USCS). If there is a discrepancy between the metric and USCS units, assume the USCS unit is most accurate. The conversion factor used is
1 inch (1000 mils) = 25.4 mm.
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Figure 1.
Intel ® Quark™ SoC X1000 Block Diagram
Intel® Quark
TM
Core
Intel ® Quark™ SoC X1000—Introduction
JTAG Host Bridge
Clock eSRAM
DDR3
Memory
Controller
AMBA Fabric Legacy Bridge
8254 8259 HPET AP
1.1
Terminology
DPFT
Term Description
Dynamic Platform & Thermal Framework; includes configurable TDP and
Low Power Mode.
§ §
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Stack-Up and PCB Considerations—Intel ® Quark™ SoC X1000
2.0
Note:
2.1
Stack-Up and PCB Considerations
Metric units are used in some sections in addition to the standard use of U.S. customary system of units (USCS). If there is a discrepancy between the metric and
USCS units, assume the USCS unit is most accurate. The conversion factor used is 1 inch (1000 mils) = 25.4 mm.
Printed Circuit Board (PCB) Considerations
Several layer count configurations may be implemented on the platform, provided the trace geometries of the individual microstrip and stripline routing layers fall within the parameter value ranges and the impedance specifications are met. It is important to note that variations in the stack-up of a motherboard, such as changes in the dielectric height, trace widths, and spacing, can impact the impedance, loss, and jitter characteristics of all the interfaces. Such changes may either be intentional or the result of variations encountered during the PCB manufacturing process. In either case, they must be properly considered when designing interconnects.
The following figures depict the set of geometry metrics associated with the external
(microstrip) routing and dual-stripline routing layers for both single-ended and differential signals. The typical values and simulation sweep ranges for each parameter are defined in the following tables. If motherboard parameters (including manufacturing variances) fall outside of the boundaries shown, perform additional simulations to ensure proper signal integrity and specification compliance.
• Design tolerances account for adjustments intentionally included in their design.
• Material tolerances account for any natural variation in the materials being used.
• Manufacturing tolerance considers variations that may occur during the manufacturing process.
• Use the design tolerance to recenter stack-up impedance, but consider the manufacturing tolerance impact when comparing the chosen stack-up to the given recommendation.
The typical values, including the design and material tolerances, are centered around a nominal single line impedance specification of 50 ±15% for microstrip. Many interfaces specify a different nominal single-ended impedance. For more details on the nominal trace width to hit those impedance targets, refer to the individual interface section.
The following general stack-up recommendations should be followed:
• Microstrip layers are assumed to be built from ½ oz. foil, plated up nominally another 1 oz., however, the trace thickness range defined allows for significant process variance around this nominal.
• Based on Intel
1oz. copper.
®
Galileo layout layers 3/4 dual stripline assumed to be built from
• All high-speed signals should reference solid planes over the length of their routing and should not cross plane splits. Ground referencing is preferred.
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Intel ® Quark™ SoC X1000—Stack-Up and PCB Considerations
• Reference plane stitching vias must be used in conjunction with high-speed signal layer transitions that include a reference plane change. Refer to each signal group section for more specification.
• The parameter values for internal and external traces are the final thickness and width after the motherboard materials are laminated, conductors plated, and etched. Intel uses these exact values to generate the associated electrical models for simulation.
Figure 2.
Single-Ended Microstrip Diagram
Figure 3.
Differential-Microstrip Diagram
r2
r1
Pair to pair pitch
Power/GND Plane
Microstrip
Pitch
W
D2
D1
T
Table 1.
Microstrip
D1
D2
r1
r2
Trace Thickness
(0.5 oz. Plated)
Platform Stack-up Parameter Values (Microstrip) (Sheet 1 of 2)
Units mils mils
NA
NA
Min
Value
2.05
0.1
3.45
3.20
- Manufacturing
Tolerance
0.3
0.3
0.15
0.2
- Design/
Material
Tolerance
Typical
Value
0.4
2.75
0.25 0.65
0.3
0
3.9
3.40
+ Design/
Material
Tolerance
+ Manufacturing
Tolerance
Max
Value
0.25 0.30 1.20
0.3
0.15
4.35
0 0.2
3.60
mils 1.30
0.28
0.32
1.90
0.32
0.28 2.50
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Stack-Up and PCB Considerations—Intel ® Quark™ SoC X1000
Table 1.
Microstrip
Platform Stack-up Parameter Values (Microstrip) (Sheet 2 of 2)
Units
Min
Value
- Manufacturing
Tolerance
- Design/
Material
Tolerance
Typical
Value
+ Design/
Material
Tolerance
+ Manufacturing
Tolerance
Trace Width
(Bottom)
Trace Width
(Top) mils mils
3.1
2.1
0.40
0.40
0.5
0.5
4.00
3.00
0.25
0.25
Max
Value
0.40 4.65
0.40 3.65
2.2
2.2.1
2.2.2
2.2.3
Low Halogen Flame Retardant Stack-Up Considerations
Low Halogen Background
FR4 epoxy has been used in the construction of PCBs for decades. Consequently, its electrical properties, which are influenced by brominated flame retardants integrated into the molecular structure of the resin, have been studied extensively. As an environmentally friendly alternative to the halogenated flame retardants in FR4, several new low halogen (LH) formulations were developed by different material suppliers. Unfortunately, each new formulation has a unique electrical performance that differs from FR4. This leads to the current problem: The critical electrical properties of many LH dielectrics currently on the market make it difficult to design high-speed buses without increasing the cost of the system. The range of supported Er values therefore limits the amount of cost added.
The most apparent problem lies with the increased permittivity of the LH dielectric materials compared to FR4. Measurements show that several LH PCB materials on the market can have permittivity values around 5 at 1 GHz (using 1080 glass), while FR4 has permittivity values in the 3.6 - 3.9 range. Increased permittivity requires thicker dielectric layers to achieve the equivalent impedance as FR4. In turn, the thicker dielectric layers lead to an increase in crosstalk which reduces bus performance. If the trace-trace spacing and line widths remain constant (consequently board area consumed remains constant), and the dielectric thickness is adjusted to maintain constant characteristic impedance, the bus performance is reduced for high permittivity values due to increased crosstalk.
Conventional means of reducing crosstalk is to isolate traces as much as practical to reduce the electromagnetic coupling of energy. Unfortunately, modern motherboard designs are often real-estate constrained, requiring extra layers (and therefore cost) to provide additional space for crosstalk compensation when using high permittivity dielectrics.
Choosing a Low Halogen Material
Choosing an LH dielectric material for a specific design requires a compromise between performance and cost, especially when a single design is required to work with both LH and FR4 PCB materials. Consequently, it is impossible to define universal requirements for LH dielectrics that will be adequate for all products on the market. Generally speaking however, the dielectric materials used to design printed circuit boards (PCBs) with high-speed digital interfaces perform better with low permittivity and low losses.
Low permittivity tends to reduce crosstalk noise for given impedance and low loss tangents reduce signal attenuation.
Electrical Limits of Low Halogen Material Properties
Although it is impossible to define electrical limits to universally select “good” materials versus “bad” materials because each design is unique in its implementation, general limits can be chosen that will be adequate for most applications. Simulations were
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Intel ® Quark™ SoC X1000—Stack-Up and PCB Considerations
Table 2.
2.3
2.4
performed on several high-speed buses and validation platforms were built to help identify electrical limits of LH materials that will help ensure 1) adequate bus performance and 2) interchangeability between FR4 and LH material. The layout constraints listed in this document have been designed to function with both standard
FR4 and LH materials if the electrical properties of the LH materials fall within the envelope defined by
Electrical Limits of LH Material Properties
Parameter Environmental Condition
Permittivity (Er)
Loss Tangent (tan )
Moisture Impact on Loss (tan )
Approximate LH Electrical Limits
<4.2 (1080, RC~61%)
<4.3 (RC~50%)
<4.5 (2116, RC~45%)
<0.018 (1080, RC~61%)
<0.014 (1080, RC~50%)
<0.013 (2116, RC~45%)
<0.024(1080, RC~61%)
<0.019(RC=50%)
<0.017 (2116, RC~45%)
Any environmental conditions
50% RH & 75oF
95% RH & 95oF
Note: Approximate limits of desired electrical performance of LH dielectric materials; RC =% Resin Content,
RH = Relative Humidity; 1080 stackups have between ~ 60-65% resin content depending on the layer thickness; Limits established using buses implemented on 1080 material. 2116 (RC=45%) and
RC=50% limits extrapolated from the 1080 data points using the volume ratio of resin to glass and average values of resin density, glass density, glass permittivity, glass tan and glass weight basis.
Although the limits listed in Table 2 are generally lower performance than standard
FR4, simulated and measured data indicate that they are sufficient to ensure proper functionality of the buses listed in this design guide. Since the volume of LH materials on the market is small compared to FR4, the performance envelope was made as large as practical to maximize the number of LH materials that comply without significantly
sacrificing signal integrity. Table 2
does not guarantee equal performance to FR4.
However, if the limits are adhered to, then the risk of signal integrity problems due to the LH material is greatly reduced. Intel bases signal integrity analysis and validation on these ranges.
Designers should also ensure the LH dielectric materials chosen meet all applicable thermal, mechanical and UL flammability requirements.
Reference Planes
• Reference all signal routing layers to a solid ground plane that is continuous over the length of the interconnect. Specific requirements may be defined within the interface design guideline chapters.
• Using a power layer as a reference plane is allowed if the power layer is low noise and there is proper decoupling stitching at reference planes transitions to guarantee high frequency return path continuity. However, this should only be considered as the secondary reference plane on internal layers where a solid continuous ground reference is already present. Even in this case the power plane must be low noise due to the possibility of noise being coupled into the associated signal planes.
• Route noisy power planes, such as VBAT, on the same layers as signals to minimize fringe coupling by proper spacing separation.
Backward and Forward Coupling Coefficient Calculation
Some designs require a stack-up build that is outside of the ranges provided. In this case, compare the routing electrical characteristics versus the Intel recommendation.
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Stack-Up and PCB Considerations—Intel ® Quark™ SoC X1000
Figure 4.
Figure 5.
Comparing the single-ended and differential-impedances is important. However, crosstalk level, which is governed by trace spacing, is not implied by the impedance target. Calculating and comparing backward coupling coefficients is recommended to choose proper trace spacing in cases where the selected stack-up varies from the Intel recommendation.
The coupling coefficients represent the source voltage percentage that is coupled to victim lines. As shown in
, K b
is defined as the backward coupling coefficient.
For backward (near-end) crosstalk, inductive and capacitive coupling are of the same polarity and the noise magnitude is not a function of trace length. The backward coupling coefficient (K b
) values can be used to decide trace spacing.
For forward (far-end) crosstalk, K f
inductive and capacitive coupling are of opposite polarity and the crosstalk magnitude (Vfe) is proportional to both trace length and edge rate. K f
is typically a very small value in most practical designs. Therefore, Intel has not f values in the Design Guide. However, the equation for calculating K provided in
if the value is desired.
f is
K b
values for all interfaces for all routing layers can be found in Table 3
.
They were calculated assuming a nominal or typical stack-up configuration based on the values in
. For single-ended interfaces, the K b
values reflect the crosstalk seen between each typical spacing. For typical spacing differential interfaces, the K b
values reflect the crosstalk seen between each differential pair based on the typical pair-to-pair spacing.
Backward Coupling Coefficient
K
V b
NE
1
4
K b
C ii
C jj
C
V ij
0
L ij
L ii
L jj
,
Forward Coupling Coefficient
K
V
FE f
1
2
K f
C ij
C ii
C jj
Length
* dV dt
L ij
L ii
L jj
L ii
C ii
L jj
C jj
1
/ 4
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Figure 6.
Single-ended Kb Diagram
Intel ® Quark™ SoC X1000—Stack-Up and PCB Considerations
Figure 7.
Differential Kb Diagram
2.5
Single-Ended and Differential-Impedance Transmission
Line Specifications
Table 3 lists breakout trace geometries for various I/O interfaces. Breakout topologies
are mainly decided by package ballout patterns and pitches. So similar geometries will be used for various stack-ups. Refer to interface chapters for the breakout maximum length allowed and signals not listed in this table.
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Stack-Up and PCB Considerations—Intel ® Quark™ SoC X1000
Table 4 lists examples of single-ended and differential impedances specified for
different interfaces. The microstrip single-ended impedance tolerance is ±15%. The stripline and dual-stripline single-ended impedance and differential impedance tolerance is ±10%. The microstrip differential-impedance tolerance is ±15%.
Table 3.
Breakout Geometries for Various I/O Interfaces
I/O Interfaces Component Stack-Up Units
Trace
Width
Minimum
Trace
Spacing
Minimum
Pair-to-
Equivalent
Pair Spacing 1
Minimum Pair-to-
Non-Equivalent
Pair Spacing 1
USB2/ PCIe/
Platform Clocks
DDR3
Default 2
SOC
SOC
SOC
SOC
MS
MS
MS
MS mils mils mils mils
4
4
4
3.5
4
4
4
4
8
NA
NA
NA
8
NA
NA
NA
Notes:
1.
Equivalent pairs mean both pairs have equal swing and signal propagation direction. Non-equivalent pairs mean both pairs have different swing or propagation direction.
2.
Default refers to legacy signals which are not listed in the table, i.e., low speed non-critical signals.
2.6
2.6.1
Minimizing the Effect of Fiber Weave
Overview of Fiber Weave
Fiber weave in the PCB material impacts the routing of high-speed traces. The PCB material is made up of a composite of fiber and resin. The strands of fiber run perpendicular to each other. Depending on the orientation of the weave relative to the trace, there could be either resin or a fiber bundle beneath the trace. Due to the differing dielectric constants of these two materials, a phase skew could be introduced among signals that comprise a differential pair. This phase skew manifests itself as an
AC common mode noise at the receiver, affecting both voltage and timing margin at the receiver. The layout recommendations in this section will minimize the effect of the PCB fiber weave on the routing of differential signals. The choice of a particular mitigation technique is dependent on the configuration and layout of the platform and, hence, this choice is left to the platform designer. Typical printed circuit boards, due to their basic construction consisting of woven fiberglass fabric (Er~6) strengthened and bound together with epoxy resin (Er~3.5), present a non-homogeneous medium for signal
propagation of differential pairs. As shown in Figure 8
, there are several weave types, with the weave strands running horizontal and vertical relative to the board edges. For differential pairs with trace width and spacing comparable to the dimensions of the fiberglass cloth, the PCB’s non-uniform dielectric can give rise to substantial
propagation differences between the conductors of the pair, see Figure 9 .
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Figure 8.
Common Glass Cloths Used in PCB Manufacture
Figure 9.
Note: Weave types above are for illustration purposes only
Inhomogeneous Nature of a PCB as Shown in this Cross-Section
D D +
Epoxy only
Fiberglass w eave bundle
Note: Note the fiber weave bundle and epoxy regions
At high data rates this skew can amount to a substantial fraction of the transmission unit interval, resulting in an increased common mode voltage and a correspondingly degraded differential signal
. In addition, the resulting common mode signal
(ACCM) can become a source of increased crosstalk and EMI in the system, or violate receiver ACCM specifications.
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Figure 10.
Effect of Skew on Differential and Common Mode Signals
Figure 11.
Cross-Section of PCB Indicating Effect of PCB Fiber Weave
Etching / Plating Impacts on Trace Geometries
2.6.2
Table 4.
Fiberglass Bundle Waves
Directly Under Trace
-
Directly Under Trace
Fiber weave effect is noticeable for routing lengths greater than 2” and this effect gets more pronounced for longer trace lengths. There are many approaches to minimize this effect and the next three sections suggest some methods to mitigate this effect. The
AC common mode noise causes considerable degradation of the signal for trace lengths in the range of 5” to 15” for a typical PCB stackup on FR4 material.
Fiber Weave Effect versus Transfer Rate and Trace Length
Max Root Square Sum (RSS) Length vs. Transfer Speed
Transfer Speed
2.5 GT/s
4 GT/s
5 GT/s
6.4 GT/s
8 GT/s
Max RSS length (See note 1)
5”
4”
3”
2.5”
2”
Notes:
1.
The lengths in the table represent total trace lengths that are aligned to the weave (i.e., parallel to the manufacturing panel’s edge). Actual routing may have a significant portion of the length at angles to the
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2.
edge of the board. Those lengths should not be considered in this analysis.
The total length is the Root Square Sum of total vertical and horizontal lengths that run parallel to the weave:
Length = H
1
2
+ H
2
2
+ H
3
2
+ V
1
2
+ V
2
2
+ V
3
2
+ where: H x
V x
= length of each segment routed horizontally, and
=length of each segment routed vertically
The table represents an approximation only, based on simulations of “representative” topology. The exact fiber weave may vary, depending on the exact topology.
2.6.3
Specific Routing Configurations
Some platforms might have their components laid out in a manner that requires nonorthogonal (to the PCB board edge) routing for their high-speed busses. Orthogonal routing up to a maximum length of 2” does not result in a noticeable impact on the differential signals. However, there could be a significant amount of AC Common-Mode voltage introduced between the differential pair that the platform designer will need to consider.
2.6.4
Offset Routing
This involves routing the trace in a straight line with offset in the middle equal to a glass bundle pitch. The glass bundle pitch differs by materials and direction and is dependent on the particular manufacturing process. An example is shown in
For this technique to be applied, a PCB layout tool with this capability would be required.
Figure 12.
An Example of Offset Routing
2.6.5
Zig-Zag or Slanted Routing
If the weave is aligned to the PCB edges, follow a zig-zag or slanted routing of differential traces. Maintain a minimum angle of 10 degrees between the trace and
shows slanted routing. For this technique to be applied, a PCB layout tool with this capability would be required.
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Figure 13.
An Example of Zig-Zag Routing
Figure 14.
An Example of Slanted Routing
2.6.6
Image Rotation
Another solution is to maintain an angle between the trace and the fiber weave pattern is to rotate the weave relative to the edge of the PCB, thereby maintaining differential
trace routes aligned with edges of the PCB (refer Figure 15
). It is recommended the rotation be such that the traces are at a 10 degree angle relative to the fiber weave.
The rotation can be achieved by cutting the PCB board at an angle, as shown in
or by rotating the layout database relative to the edge of the PCB board. The latter requires the use of an appropriate PCB routing software that has this capability.
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Figure 15.
An Example of a PCB Cut Such That Its Edges are Rotated Relative to the Fiber
Weave Pattern
> Glass bundle alignment HVM variation
2.6.7
Using Alternate PCB Materials
The fiber weave effect can also be minimized by using PCB material that exhibits less variation in the dielectric coefficient E r
between the epoxy and glass materials.
§ §
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DDR3 Memory Design Guidelines—Intel ® Quark™ SoC X1000
3.0
3.1
3.1.1
Table 5.
3.1.2
3.1.3
3.1.4
DDR3 Memory Design Guidelines
Memory General Introduction
Intel ® Quark™ SoC X1000 Customer Reference Board (codename Kips Bay) platforms support DDR3 memory technology. The CRB’s SoC memory interface supports a singlechannel of DDR3 memory with 8-bit wide data and up to 2 ranks per channel at 800
MT/s.
This document covers the guidelines to design a Kips Bay platform memory subsystem using Memory Down approach.
Supported Memory Configurations
This Guideline Supports the Following Configurations
Parameter
Supports up to:
Device Densities Supported
Device Widths Supported
Memory capacity
PCB Layers
1 Rank/Channel
DDR3-800
1Gb, 2Gb, 4Gb x8
256MB-1GB
4L
2 Ranks/Channel
DDR3-800
1Gb, 2Gb, 4Gb x8
512MB-2GB
TBD
Memory Population Rules
Rank0 is mandatory; Rank1 is optional; All devices must be of the same bit density.
Reference Documents
See JEDEC Standard for DDR3 SDRAM Specification at http://jedec.org.
DDR3 TLC (Trace Length Calculator):
Clanton_DDR3_4L_single_rank_fly_by_topoology_Trace_Length_Calculator_rev_0_4_
Draft.xlsm
- external version CDI# 523409
Design Constraints-based Routing
Design constraints need to be derived from all of the following sections:
• Memory Stackup Guidelines
• Stackup and Layer Utilization Guidelines
• Memory Block Diagram and Connectivity
• Memory Bit swapping and Byte Lane swapping
• Memory Length Matching Guidelines
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3.2
Table 6.
• Compensation
• Voltage Reference Rules
Memory Signal Description
DDR3 Channel Signal Groups
Signal Name Description
Clock Signal Group
DDR3_CK[0], DDR3_CKB[0]
DDR3_CK[1], DDR3_CKB[1]
Control Signal Group (signals per rank)
Differential Clock pair for Rank0
Differential Clock pair for Rank1
DDR3_CSB[1:0]
DDR3_CKE[1:0]
Chip Select (One per rank)
Clock Enable (One per rank)
DDR3_ODT[1:0]
Command Signal Group (common across ranks)
On-Die Termination Enable (One per rank)
DDR3_MA[15:0]
DDR3_BS[2:0]
DDR3_RASB
DDR3_CASB
DDR3_WEB
Data Signal Group (common across ranks)
DDR3_DQ[15:0]
DDR3_DQS[0], DDR3_DQSB[0]
Memory Address Bus
Bank Select
Row Address Select
Column Address Select
Write Enable
Data Bus
Data Strobe for DQ[7:0]
Data Strobe for DQ[15:8] DDR3_DQS[1], DDR3_DQSB[1]
Miscellaneous
DDR3_DRAMRSTB Reset for all DRAM devices
Table 7.
Note:
Memory Channel Signals Groups Routing
Parameter
Motherboard Topology
Reference Plane
Clock
Differential-Pair
Point-to-Point
Dual Referenced
GND & PWR
Control
Point-to-Point
Command
Point-to-Point
Dual Referenced
GND & PWR
Dual Referenced
GND & PWR
Data
Point-to-Point
Dual Referenced
GND & PWR
Data Strobe
Differential-Pair
Point-to-Point
Dual Referenced
GND & PWR
It is recommended that all of the signals have solid GND referencing planes on both sides. Minimize the size of void if there are voids on reference planes.
3.3
Note:
Memory Topology Guidelines
This chapter presents the various DDR3 topologies possible with Intel
X1000 platforms and associated constraints for PCB layout.
® Quark™ SoC
The SoC package length is labeled as "P1" and available in the Trace Length Calculator.
Refer to CDI #523409.
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3.3.1
Single Rank Fly-by Topology with Active VTT Termination
The topology presented in this chapter is the basic DDR topology for 4 Layer PCB
designs. For PCB stack-up information please refer to Chapter 2.0
Figure 16.
DQ/DM - Data Routing Topology for a Single Rank 4L Fly-by Design - PCB Type
3
DRAM
Tx
Rx
SoC
Package
P1
Breakout
TL1 via
Main
TL2 via
Breakin
TL3
Tx
Rx
Figure 17.
DQS - Data Strobes Routing Topology for a Single Rank 4L Fly-by Design - PCB
Type 3
DRAM
Tx
SoC
Package
P1
Rx
P1
Breakout
TL1 via
TL1
Main
TL2
TL2 via
Breakin
TL3
TL3
Tx
Rx
Table 8.
DQ/DQS Routing Guidelines and Settings for a Single Rank 4L Fly-by Design—
PCB Type 3 (Sheet 1 of 2)
Parameter Routing Guideline / Setting
Transmission Line
Segment
Stackup Layer
(Microstrip / Stripline/
Dual Stripline)
Characteristic
Impedance (DQ/DM)
Characteristic
Impedance (DQS)
TL1
MS
TL2
MS
40 Ω SE 10% (MS)
76 Ω DIFF 10% (MS)
TL3
MS
Trace Width (W)
4.0 mils (SE)
4.0 mils (DIFF)
6.5 mils (SE)
5.3 mils (DIFF)
4.0 mils (SE)
4.0 mils (DIFF)
Trace Spacing (S1):
Between DQ/DM within a data byte min = 4.0 mils min = 13.0 mils min = 4.0 mils
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Table 8.
DQ/DQS Routing Guidelines and Settings for a Single Rank 4L Fly-by Design—
PCB Type 3 (Sheet 2 of 2)
Routing Guideline / Setting Parameter
Trace Spacing (S2):
Between adjacent data bytes’ signals of a channel
Trace Spacing (S3):
Between DQS and
DQS# pair
Trace Spacing (S4):
Between DQS/DSQ# and DQ/DM
Trace Spacing (S5):
Between DQ/DM/DQS group and other DDR group’s signals
Trace Spacing (S6):
Between DQ/DM/DQS group and other non-
DDR signals - excluding power pins
DQ/DQS Trace Segment
Length
DQ/DQS Total trace length
Length matching between DQ/DM and
DQ/DM within a Byte group (including pkg. length)
Length matching between DQ/DM and
DQS/DQS# of a byte
(including pkg. length)
Length matching between Clock and
DQS/DQS# (including pkg. length)
Length matching between DQS and DQS#
(including pkg. length)
Number of vias min = 10.0 mils
4.0 mils min = 4.0 mils min = 4.0 mils min = 10.0 mils max = 300 mils min = 20 mils
4.7 mils min = 13 mils min = 13 mils min = 25 mils min = 500 mils max = 2000 mils
TL1 + TL2 + TL3 = 2600 mils (max)
± 5 mils
Note : All DM/DQ signals length for a given
Byte Group must fall within 10 mils window.
DQ = (DQ/DQSB ± 5 mils)
DQS = (CLK/CLKB - 1.75") ± 0.75"
± 5 mils min = 10.0 mils
4.0 mils min = 4.0 mils min = 4.0 mils min = 10.0 mils max = 300 mils
SoC Buffer Settings:
SoC Read ODT:
DRAM BUffer Settings:
DRAM Runtime:
DRAM Ritter: max = 2 via
RON: 32 Ω
SR: 4V/ns
180 Ω
RON: 34 Ω
120 Ω dynamic ODT not used
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Figure 18.
ODT/CKE/CS - Control Routing Topology for a Single Rank 4L Fly-by Design -
PCB Type 3
Tx
SoC
Package
P1
DRAM DRAM
VTT
Breakout
TL1 via
Main
TL2 via
Main
TL3
Breakin Breakin
TL4 via
Breakout
TL5 TL6 device-to-
-device
Breakin
TL7 via
Breakout
TL8
Termination
TL9
RTT
Table 9.
Control - Routing Guidelines and Settings for a Single Rank 4L Fly-by Design—
PCB Type 3 (Sheet 1 of 2)
Parameter
Transmission Line
Segment
TL1
Stackup Layer
(Microstrip / Stripline/
Dual Stripline)
MS
Characteristic
Impedance (Control
Group)
Trace Width
Trace Spacing (S):
Within the signals in the point-to-point
CTRL Group
Trace Spacing (S1):
Between CTRL Signals and other DDR signals
Trace Spacing (S2):
Between CTRL group and non-DDR signals - excluding power pins
50 Ω
10.0 mils
TL2
MS
SE 10% (MS) min =
4.0 mils min =
4.0 mils min = min =
8.4 mils min =
13 mils min =
20 mils
TL3
MS
4.0 mils 4.2 mils 4.2 mils 4.2 mils 4.2 mils 4.2 mils 4.2 mils 4.2 mils 4.2 mils 4.2 mils min =
6.5 mils min =
6.5 mils min =
20 mils
TL4
MS
Routing Guideline / Setting min =
4.2 mils min =
4.2 mils min =
20 mils
TL5
MS min =
4.0 mils min =
4.0 mils min =
10.0 mils
TL6
MS min =
4.2 mils min =
6.5 mils min =
20 mils
TL7
MS min =
4.0 mils min =
4.0 mils min =
10.0 mils
TL8
MS min =
4.2 mils min =
4.2 mils min =
20 mils
TL9
MS min =
4.2 mils min =
4.2 mils min =
10.0 mils
TL10
MS min =
4.0 mils min =
4.0 mils min =
10.0 mils
Point-to-point CTRL group Trace Segment
Length max =
200 mils min =
1000 mils max =
1700 mils min =
200 mils max =
400 mils min =
200 mils max =
600 mils max =
100 mils min =
500 mils max =
600 mils max =
100 mils min =
300 mils max =
700 mils max =
50 mils max =
100 mils
Point-to-point CTRL group Total trace length
1st DRAM: TL1 + TL2 + TL3 + TL4 + TL10 = 3000 mils (max)
2nd DRAM: TL1 + TL2 + TL3 + TL4 + TL5 + TL6 +TL7 +TL10 = 3800 mils (max)
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Table 9.
Control - Routing Guidelines and Settings for a Single Rank 4L Fly-by Design—
PCB Type 3 (Sheet 2 of 2)
Parameter
Length matching between point-to-point
CTRL signals and all the CLOCKs within a
Channel (including pkg. length)
CTRL = (CLK/CLKB - 50 mils) ± 50 mils
Number of vias
SoC BUffer Settings:
RTT Value max = 4 via
RON: 27 Ω
SR: 1.5 V/ns
36 Ω + 10%
Routing Guideline / Setting
Note: All length matching and total trace length rules are applicable for the SoC to DRAM paths; for termination related segments i.e., TL8 and TL9 only the min and max trace segment length rules apply.
Figure 19.
MA/BS/CAS/RAS/ WE - Command Routing Topology for a Single Rank 4L Fly– by Design—PCB Type 3
Tx
SoC
Package
P1
DRAM DRAM
VTT
Breakout
TL1 via
Main
TL2 via
Main
TL3
Breakin Breakin
TL4 via
Breakout
TL5 TL6 device-to-
-device
Breakin
TL7 via
Breakout
TL8
Termination
TL9
RTT
Table 10.
Command Routing Guidelines and Settings for a Single Rank 4L Fly-by
Design—PCB Type 3 (Sheet 1 of 2)
Parameter
Transmission Line
Segment
TL1 TL2 TL3
Routing Guideline / Setting
TL4 TL5 TL6 TL7 TL8 TL9 TL10
Stackup Layer
(Microstrip / Stripline/
Dual Stripline)
MS MS MS MS MS MS MS MS MS MS
Characteristic
Impedance (Command
Group)
40 Ω SE 10% (MS)
Trace Width
Trace Spacing (S):
Within the signals in the Command Group
4.0 mils min =
4.0 mils
6.5 mils min =
13.0 mils
6.5 mils min =
6.5 mils
4.0 mils min =
4.0 mils
4.0 mils min =
4.0 mils
6.5 mils min =
6.5 mils
4.0 mils min =
4.0 mils
4.0 mils min =
4.0 mils
6.5 mils min =
6.5 mils
4.2 mils min =
4.0 mils
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Table 10.
Command Routing Guidelines and Settings for a Single Rank 4L Fly-by
Design—PCB Type 3 (Sheet 2 of 2)
Parameter
Trace Spacing (S1):
Between Command
Signals and the other
DDR groups min =
4 mils min =
13.0 mils min =
6.5 mils
Routing Guideline / Setting min =
4 mils min =
4 mils min =
6.5 mils min =
4 mils min =
4 mils min =
6.5 mils min =
4 mils
Trace Spacing (S2):
Between CMD group and non-DDR signals - excluding power pins min =
12 mils
CMD group Trace
Segment Length
CMD group Total trace length min =
25.0 mils min =
25.0 mils min =
12 mils min =
12 mils min =
25.0 mils min =
12 mils min =
12 mils min =
25.0 mils min =
12 mils max
= 300 mils min =
500 mils max
=
1700 mils min =
100 mils max
= 750 mils max
= 100 mils max
= 100 mils min =
200 mils max
= 450 mils max
= 100 mils max
= 100 mils min =
50 mils max
= 600 mils min =
50 mils max
= 300 mils
1st DRAM: TL1 + TL2 + TL3 +TL4 + TL10 = 3150 mils (max)
2nd DRAM: TL1 + TL2 + TL3 +TL4 + TL5 + TL6 + TL7 + TL10 = 3800 mils (max)
Length matching between CMD signals and all the CLOCKs within a Channel
(including pkg. length)
CMD = CLK/CLKB ± 150 mils
Number of vias
RTT Value
SoC BUffer Settings
CMD Timings max = 4 via
36 Ω + 10%
RON: 27 Ω
SR: 1.5 V/ns
2N
Note: All length matching and total trace length rules are applicable for the SoC to DRAM paths; for Termination Segments (TL8 + TL9) only the min and max trace segment length rules apply.
Figure 20.
Clock Routing Topology for a Single Rank 4L Fly-by Design—PCB Type 3
DRAM DRAM
Tx
SoC
Package
P1
P1
Breakout
TL1 via
TL1
Main
TL2
TL2
Breakin
Breakin
Cap
Breakin
TL3
TL3 via
TL4 TL5
TL4 TL5
Breakout device-to-
-device
TL6
TL6
Breakin via
Termination
TL7
TL7
RTT
RTT
VTT
Ctt
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Table 11.
Parameter
Transmission Line
Segment
TL1
Stackup Layer (Microstrip
/ Stripline/ Dual
Stripline)
MS
TL2
MS
TL3
MS
Characteristic Impedance
(CLK Group)
66 Ω DIFF 10% (MS)
Trace Width 4.0 mils 7.2 mils
Trace Spacing (S):
Between P and N of a CLK pair
4.0 mils
Trace Spacing (S1):
Between point-to-point
CLK pair to another CLK pair min =
12.0 mils
5.3 mils min = 25 mils
4.0 mils
4.0 mils min = 4 mils
Routing Guideline / Setting
TL4
MS
4.0 mils
4.0 mils min = 4.0 mils
TL5
MS
7.2 mils
5.3 mils min = 25 mils
TL6
MS
4.0 mils
4.0 mils min = 4.0 mils
TL7
MS
7.2 mils
5.3 mils min = 25 mils
TL8
MS
4.0 mils
4.0 mils min = 4.0 mils
Trace Spacing (S2):
Between point-to-point
CLK Group and other DDR groups min = 4 mils
Trace Spacing (S3):
Between point-to-point
CLK Group non-DDR signals min = 4 mils
Point-to-point CLOCK group Trace Segment
Length
Point-to-point CLOCK group Total trace length
Length matching between CK and CKB of
CLOCK (including pkg. length)
± 5 mils min = 25 mils min = 25 mils min = 4.0 mils min =
12.0 mils min = 4.0 mils min = 12 mils min = 10 mils min = 25 mils min = 4.0 mils min = 12 mils min = 25 mils min = 25 mils max =
200 mils min =
500 mils max =
2500 mils max =
100 mils max =
100 mils min =
400 mils max =
600 mils max =
100 mils
1st DRAM: TL1 + TL2 + TL3 + TL8 = 3000 mils (max)
2nd DRAM: TL1 + TL2 + TL3 + TL4 + TL5 + TL6 + TL8 = 3800 mils (max) max =
450 mils min = 4.0 mils min = 4.0 mils max =
200 mils
Number of vias
RTT Value
Cap Value
Ctt Value
SoC BUffer Settings: max = 3 via
30 Ω
1 pF
+ 10%
0.1 F
RON: 26 Ω .
SR: 4V/ns
Note:
Clock Routing Guidelines and settings for a Single Rank 4L Fly-by Design—PCB
Type 3
All length matching and total trace length rules are applicable for the SoC to DRAM paths; for Termination Segment (TL7) only the min and max trace segment length rules apply.
3.3.2
Memory Stackup Guidelines
Refer see
for motherboard stack up details.
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3.3.3
Memory Configurations and Connectivity
Figure 21 shows the DDR3 Memory Down design high level block diagram and memory
channel connectivity.
3.3.3.1
ODT Signal Connectivity and Support
For DDR3 memory-down design, Intel recommends ODT signals to be routed between
SoC and DRAM devices on platform. This way, ODT timings at DRAM device can be fully controlled by the SoC.
Figure 21.
DDR3 Memory Down Block Diagram
Clanton
DDR3 x8
DDR3 x8
DDR3 x8
DDR3 x8
3.3.4
3.3.4.1
Note:
3.3.4.2
Memory Physical Layout Guidelines
General Routing Guidelines
For DDR3 memory down configuration, one CLK pair per rank is needed.
Here are some general DDR3 memory signal group routing guidelines:
• Recommend all of the signals to have GND referencing planes.
• Make sure proper GND stitching in place when signal is making layer transitions.
• Avoid parallel routing between two adjacent layers.
• Tuning length between Differential pairs at the DRAM devices side (some DQS/CLK will have P & N length mismatch)
Byte Lane Placement
• A data channel can be treated as two separate and independent byte lanes for routing.
• Byte lanes may be partitioned between internal routing layers as required to complete the route.
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3.3.4.3
3.3.5
3.3.6
Note:
3.3.6.1
3.3.6.2
3.3.7
3.4
3.4.1
• Each byte lane signal set must be routed as a group on the same layer, to minimize skew within the byte lane.
Via Stitching and Placement
Poor stitching via could lead to significant margin loss, so it is essential to stitch reference planes for signal transition, where the reference plane change took in place.
It is highly recommended to stitch signals both within byte/group and between bytes/ groups. In case of signal transition to a layer in between two reference planes, make sure the stitching via connects to the plane closest to the signal layer. In case signal transition to another routing layer, but the referencing plane still kept the same, no stitching via is required.
Memory Bit and Byte Lane Swapping
• Bits swapping is allowed within the same byte and byte swapping is allowed within the channel. Strobes must always accompany their corresponding bytes.
• DQS/DQSB and CLK/CLKB Swapping : is NOT allowed on either DQS/DQSB or
CLK/CLKB. DQS/DQSB must be connected correctly.
• Clock swapping is not allowed.
Memory Length Matching Guidelines
If swapping is used, the TLC must be adjusted to comply with the required length matching requirements.
Length matching within differential pairs (CLK and DQS) should be performed at the
DRAM side, e.g., at the Break-in trace segment. However, no length matching is required for the SoC breakout or main routing segments.
Length Matching and Length Formulas
Please refer to each individual topology guidelines.
Package Length Compensation
Package length compensation is an integral part of the overall length matching process and is important within individual byte lanes, CMD and CTRL within the channel. The
SoC package traces are not length-matched internally, which makes package length compensation on the motherboard extremely important. Please refer to the DDR3 Trace
Length Calculator for the actual SoC in-package trace lengths.
Memory Decoupling Guidelines
Refer to the CLANTON Power Decoupling (Kips Bay) Reference (ID# 522272).
Memory Reference Voltage and Compensation Guidelines
SoC DDR Reference Voltage
The Intel ® Quark™ SoC X1000 uses an internal circuitry to adjust the reference voltage used to qualify the logic levels on incoming DDR data bits. This capability is used to perform a vertical read data eye training. The DDR_VREF input allows supplying an external reference voltage, but in normal circumstances the internal reference voltage shall be used and DDR_VREF input shall be connected to GND.
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3.4.2
3.4.3
Note:
3.4.4
Note:
Table 12.
3.5
DRAM Reference Voltage
DRAM memory devices need to be supplied with VREF_CA and VREF_DQ reference voltages generated on the platform.
DRAM ZQ Calibration
The Intel
®
Quark™ SoC X1000 supports configurations with separate and shared precision resistors across DRAM devices.
In the case of separate precision resistor for each DRAM device, the ZQ Calibration is performed in parallel on all DRAM devices. This is the most straightforward configuration and is recommended for Intel ® Quark™ SoC X1000 platforms.
To save on the BOM cost in the dual rank configuration it is also valid to share precision resistors between the ranks. In this case the ZQ calibration is performed in series - one rank at the time. The savings for Intel
®
Quark™ SoC X1000 dual rank platforms by using this approach is 4 -> 2 precision resistors with four x8 DRAM devices, and is not as significant as for the products with wider data buses and more ranks.
The precision resistor should be 240 Ohm and connected between ZQ pin and GND. For more details on ZQ signal and calibration refer to the DDR3 JEDEC Specification.
The default mode of operation for the Intel
®
Quark™ SoC X1000 is the Parallel ZQ
Calibration, and this mode is supported in Intel
®
Quark™ SoC X1000 MRC.
Routing Guidelines for Compensation Signals
The SoC uses precision resistors connected to DDR_xxxPU inputs to compensate the drive strength of different buffers. It is important to follow the routing guidelines as well as board level guidelines for these signals in order to get the accuracy in the compensation scheme.
shows the values of different precision resistors that need to be connected to the compensation pins.
The SoC breakout area width and spacing can be reduced to 4 mils, but care needs to be taken to not route any high frequency signals next to the compensation signals.
Precision Resistor Value for DDR3_xxxPU Compensation Inputs
Signal
DDR3_ODTPU
DDR3_DQPU
DDR3_CMDPU
2
2
2
Max
Via
Count
Trace
Width
5 mils
5 mils
5 mils
Isolation Spacing
Resistor
Value
(Pull Down to GND)
10 mils (to any signal) 274 Ω ±1%
10 mils (to any signal) 34 Ω ±1%
10 mils (to any signal) 32.4 Ω ±1%
Max Length
1000 mils
1000 mils
1000 mils
DataMask Guidelines
The Intel
®
Quark™ SoC X1000 does make use of the Data Mask (DM) signals.
Therefore, each DM signal should connect to the appropriate memory device.
§ §
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PCI Express* Design Guidelines—Intel ® Quark™ SoC X1000
4.0
PCI Express* Design Guidelines
4.1
4.1.1
Table 13.
4.1.2
Table 14.
4.1.3
PCIe* General Introduction
Description
The Intel
®
Quark™ SoC X1000 SoC provides two PCI Express* root ports. The PCIe* root ports consist of one lane each configured as a 2x1 port. Each Root Port is PCIe*
2.0 compliant.
PCI Express* Root Ports Speed Support
Speed
PCIe* 1.0
PCIe* 2.0
Bandwidth
2.5 GT/s
5 GT/s
Direction
Each Direction (5 GT/s concurrent)
Each Direction (10 GT/s concurrent)
The PCI Express* topology consists of a transmitter (TX) on one device connected by a differential trace pair to a receiver (RX) on a second device. One of the devices may be located on the baseboard or an add-in card.
Supported Configuration Options for PCIe* Ports
describes the supported configurations for the PCIe ports.
PCIe* Root Ports 1 and2 Supported Configurations
Port 1 x1
Port 2 x1 2x1 mode, one lane to each port
Notes
PCI Express* Lane Polarity Inversion
The PCI Express* Base Spec requires polarity inversion to be supported independently by all receivers across the Link - each differential pair within each Lane of the PCIe
Link handles its own polarity inversion. Polarity inversion is applied, as needed, during the initial training sequence of the Lane. In other words, a Lane will still function correctly even if a positive (TX+) signal from a transmitter is connected to the negative
(RX-) signal of the receiver. Polarity inversion eliminates the need to untangle a trace route to reverse a signal polarity difference within a differential pair and no special configuration settings are necessary in the SoC to enable it. It is important to note that polarity inversion does not imply direction inversion or direction reversal, i.e., the TX differential pair from one device must still connect to the RX differential pair on the
receiving device, per the PCIe Base Spec. Polarity Inversion is not the same as “PCI
Express* Port Lane Reversal” . See Figure 22 for an example.
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Intel ® Quark™ SoC X1000—PCI Express* Design Guidelines
Figure 22.
Polarity Inversion on a TX to RX Interconnect
RX
TX
+
+
-
TX
-
+
+
-
RX
4.1.4
4.1.5
Note:
4.1.6
4.1.7
PCI Express* Port Lane Reversal
As each PCIe port link is a single lane, Lane Reversal is not supported in SoC.
PCH PCIe* Disabling and Termination Guidelines
• If some of the PCI Express ports are not implemented on the platform:
— PETp/n [x] and PERp/n [x] signals may be left unconnected, where 'x' is the port number left no connect.
• If no PCI Express ports are implemented on the platform:
— PETp/n [1:0] and PERp/n [1:0] may be left unconnected.
• Pull-up Wake# to VCC_SUS 3.3 via a 10-k? resistor.
If used, check with latest version of the Intel® Quark SoC x1000 Datasheet for maximum leakage specification on PCIE_WAKE# pin while selecting a pull up resistor in order to ensure Vih at SOC pin is satisfied.
Length Matching Guidelines
The key about differential signal length-matching is that the differential signal pair components (i.e., the p and n signals) must be kept in-phase during the entire length of the traces (from beginning to end). Most board designers try to keep the overall trace length of the individual p and n differential signals matched to within 10 mils
(
) of each other. However, this is not sufficient - or necessarily correct. It is important to do length-matching on a per-segment basis, in order to ensure the differential signals are kept in-phase, which gives optimal differential impedance and
Common Mode rejection. Further length-matching information can be found in
Appendix A, “General Differential Signals Design Guidelines” .
Impedance Compensation and Voltage Reference
The compensation input is used by the circuitry to determine, check and adjust the system buffer output strength and characteristic impedance over temperature, process and voltage variations. This is done by comparing its buffer impedance against a standard reference resistor, RCOMP.
The RCOMP signals should be referenced to VSS. Noisy or switching references should be avoided. As board space allows, it is recommended to add a VSS shield at least 4 mils wide placed between PCIE_IRCOMP/PCIE_RBIAS and adjacent I/O. No shield is needed between PCIE_RBIAS and PCIE_IRCOMP.
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Table 15.
4.1.8
SoC PCI Express* Compensation and Voltage Reference Guidelines
Signal
PCIE_IRCOMP
PCIE_RBIAS
Trace Width
4.2 mils min (breakout)
12-15 mils (trace)
Note: Must maintain low
DC resistance routing (<0.2 ohm).
4.2 mils min (breakout)
12-15 mils (trace)
Note: Must maintain low
DC resistance routing (<0.2 ohm).
Isolation Spacing
At least 12 mils to any adjacent high speed I/O.
At least 12 mils to any adjacent high speed I/O.
Resistor Value
7.5k ohm ±1% pulled toVCC1P5_S0.
7.5k ohm ±1% pulled toVCC1P5_S0.
Length
Max total= 500 mils
Max total= 500 mils
Reference Documents
Table 16.
4.2
4.2.1
PCI Express* Reference Documents
Title
PCI Express Base Specification Rev 2.1
PCI Express Electromechanical Specification Rev2.0
PCIe* Signal Descriptions
Signal Groups
Doc#/Location http://www.pcisig.com/home http://www.pcisig.com/home
Table 17.
4.3
PCI Express* Signal Groups (Standard Card)
Group
Data
Data
Signal Name
PCIE_PETP_0, PCIE_PETN_0
PCIE_PETP_1, PCIE_PETN_1
PCIE_PERP_0, PCIE_PERN_0
PCIE_PERP_1, PCIE_PERN_1
Description
PCI Express* Transmit Differential-Pair
PCI Express* Receive Differential-Pair
PCIe* Topology Guidelines
Table 18.
PCI Express* Card Topologies
Parameter
Topology
Reference Plane
Recommendation
Point to point with AC coupling depending on the topology.
Ground
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Intel ® Quark™ SoC X1000—PCI Express* Design Guidelines
4.3.1
Expansion Card Connector Topology
The Design Guide recommendations are based on surface mount connectors that meet the insertion loss and return loss characteristics as specified in PCI Express* CEM 2.0
Specification. These guidelines include all trace routing on the board and the breakout region.
• For PCI Express* interface composed of x1 links, it is most practical to route the TX signals and RX signals of each link next to each other on the same layer following interleaved routing.
• The PCI Express* expansion card topology simulations showed the lowest margins compared to other PCI Express* interfaces. Additional simulation may be required for different specific design scenarios.
• For a 4 layer board only microstrip (MS) is applicable.
• AC coupling capacitors for PET pair on the motherboard are recommended to be placed very close to the expansion connector. Avoid placing AC caps at the center of the motherboard main route.
Figure 23.
PCI Express* Expansion Card Connector Topology
SoC
Connector
PCIe*
Device
L3 t
+
TX
-
P1
P1
L0 t
L0 t
L1 t
L2 t
AC Coupling Caps
L1 t
L2 t
L1 r
L2 r
L3 t
L4 t
L4 t
+
RX
-
P1
P1
L0 r
L0 r
L1 r
L2 r
Express
Card
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Table 19.
PCI Express* Expansion Card Routing PET to Connector
Transmission Line Segment
PCB Routing Layer(s)
Optional
Stackup Layer (Microstrip /
Stripline/ Dual Stripline)
P1/L0 t
4 Layer
MS
L1 t
4 Layer
MS
L2 t
4 Layer
MS
Characteristic Impedance
90 Ω diff
15% (MS)
4.0 mils
90 Ω diff
15% (MS)
4.0 mils
90 Ω diff
15% (MS)
4.0 mils Trace Width (w) 1
Trace Spacing (S): Between P and N within a diff pair
Trace Spacing(S1): Between
PCIe PET/PER diff pairs 2
Trace Spacing(S2): Between
PCIe PET diff pairs and PER diff pairs 3
Trace Spacing(S3): Between
PCIe diff pairs and other signals 4
4.0 mils
12.0 mils
12.0 mils
12.0 mils
6.0 mils
15.0 mils
18.0 mils
18.0 mils
6.0 mils
15.0 mils
15.0 mils
15.0 mils
PET/ PER Trace Segment
Length max = 400 mils min = 1500 mils max = 3000 mils max = 200 mils
L3 t
4 Layer
MS
90 Ω diff
15% (MS)
4.0 mils
6.0 mils
15.0 mils
15.0 mils
15.0 mils max = 200 mils
L4 t
4 Layer
MS
90 Ω diff 15%
(MS)
4.0 mils
6.0 mils
15.0 mils
15.0 mils
15.0 mils max = 200 mils
1.
2.
3.
It may not be possible to maintain the impedance in the break-in, break-out or other pin fields. For those segments, define the minimum trace width that should be maintained in that segment considering the manufacturing reliability and skin effect lossetc.
Define the edge-to-edge space between differential pairs as multiple of the distance to the nearest continuous reference plane. For example, if the nearest reference plane is 4 mils away from the signal layer then a space of 4xh means the edge-to-edge space from one pair to the next pair is 16 mils.
Space rules between PET diff pairs and PER diff pairs apply to the Interleaved routing when PET and PER pairs are routed in interleave mode on the same layer.
Total Trace Length
Number of vias allowed
TX Total Length = 4000 mils
3 via
Length Matching Rules
Length Matching between P and N within a diff. pair
General
Reference plane
DC Blocking Cap
Capacitor Value, size
Capacitor location
Place the capacitors close to slot connectors
Capacitor Placement
+/- 10 mils
Continuous Ground Only
0.1 µ F
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Table 20.
1.
2.
3.
4.
Place the caps for P and N of a diff pair at exact same location
Symmetrically route the P and N from SOC to the Cap.
Symmetrically route the P and N from cap to the Connector
Stagger the caps of different differential pairs
PCI Express* Expansion Card Routing PER to Connector
Transmission Line Segment
PCB Routing Layer(s) Optional
Stackup Layer (Microstrip / Stripline/
Dual Stripline)
Characteristic Impedance
P1/L0 r
4 Layer
MS
Trace Width (w)
Trace Spacing (S): Between P and N within a diff pair
Trace Spacing(S1): Between PCIe*
PET/PER diff pairs
Trace Spacing(S2): Between PCIe* PET diff pairs and PER diff pairs
Trace Spacing(S3): Between PCIe* diff pairs and other signals
90 Ω diff 15%
(MS)
4.0 mils
4.0 mils
12.0 mils
12.0 mils
12.0 mils
PET/ PER Trace Segment Length
90 Ω
L1 r
4 Layer
MS
diff 15%
(MS)
4.0 mils
6.0 mils
15.0 mils
18.0 mils
18.0 mils
90
L2 r
4 Layer
Ω
MS
diff 15%
(MS)
4.0 mils
6.0 mils
15.0 mils
15.0 mils
15.0 mils max = 400 mils min = 1500 mils max = 3000 mils max = 200 mils
Total Trace Length
Number of vias allowed
RX Total Length = 3600 mils
2 via
Length Matching Rules
Length Matching between P and N within a diff. pair
Length matching between Tx pairs of multiple lanes
Length matching between RX pairs of multiple lanes
General
Reference plane
§ §
+/- 10 mils
+/- 10 mils
+/- 10 mils
Continuous Ground Only
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Universal Serial Bus 2.0 Design Guidelines—Intel ® Quark™ SoC X1000
5.0
Universal Serial Bus 2.0 Design Guidelines
5.1
USB 2.0 General Introduction
5.1.1
Description
The Intel ® Quark™ SoC X1000 supports up to 2 USB 2.0 Host ports that can be used to connect to high-speed, full-speed, and low-speed USB devices via an EHCI controller and/or a OHCI USB controller. The OHCI USB controller provides USB 1.0 & 1.1 support. Additionally the SoC supports a single USB 2.0 Device port that can be used to connect to high-speed and full-speed USB devices. The SoC device controller is also
USB 1.1 capable.
Figure 24.
USB Port Mapping
EHCI Port Muxing
Host Port 0
(Mini PCIe*)
Host Port 1
(MicroUSB Type AB)
Device Port 0
(MicroUSB Type B)
5.1.2
OHCI
Device
Controller
Compliance Documents
Title
USB 2.0 Specification & Compliancy Requirements
Doc #/Location www.usb.org
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5.2
5.2.1
USB 2.0 Signal Descriptions
Signal Groups
Table 21.
5.2.2
Signal Groups
DATA
Group
OVERCURRENT
POWER_EN
Signal Name
USBH0_DP, USBH0_DN
USBH1_DP, USBH1_DN
USBD_DP, USBD_DN
USBH0_OC_B
USBH1_OC_B
USBH0_PWR_EN
USBH1_PWR_EN
Universal Serial Bus Port Differential Pairs
Overcurrent Indicators
Description
Power Enables to Platform Regulators
Note: The connectors must meet the USB2.0 Connector Specification.
Overcurrent Protection
Intel ® Quark™ SoC X1000 has implemented two USB overcurrent signals. The 2 overcurrent pins are connected to the two host USB 2.0 ports. Each of the OC pins
needs to be connected to an external over current protection circuit, see Figure 25
for an example. Each USB port may draw up to 500 mA. The overcurrent protection circuitry needs to be able to support at least 2 A to ensure proper functionality of USB compliant devices. However, if a fault device is plugged into the USB port it should trigger an overcurrent when current drawn is more than 500 mA. Designer must balance between optimum cost and protection level.
When the current rating of the protection circuit has been decided, it is crucial to ensure that the overcurrent layout is designed to support the amount of current expected. For example when the overcurrent circuit is designed to support up to 2A the overcurrent trace layout should be using a big fat trace or plane that can sustain at least 2A of current. Failure to design the trace to support high current may cause the trace on motherboard to burn out and cause permanent damage to the protection circuit. The overcurrent signals require a pull-up to the 3.3 V Suspend Rail with 8.2 k to 10 k resistor.
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Figure 25.
Sample Over Current Protection Circuit
V5 Always on
0.1uF
IN
USB_PWR_EN0
EN
Current Limited
Power Switch
(TPS2051BDBVR)
10K
OUT
OC_N
GND
10K
V3P3 S0
USB_OC0_N
Each overcurrent pin protects one USB port. It is system software's (BIOS) responsibility to program the overcurrent registers of the given USB controller correctly and to make sure that each USB port is protected by only one overcurrent pin.
Operation with more than one overcurrent pin mapped to a port is undefined. See the
Intel ® Quark SoC X1000 Datasheet for more details.
5.3
USB 2.0 Topology Guidelines
5.3.1
External Topologies
The external topology refers to the routing of USB signals to a microUSB connector. It is recommended that each USB data line be routed with a common mode choke and ESD protection.
Figure 26.
USB 2.0 MicroUSB Topology
SoC MicroUSB
ESD
DIODE
TX
Breakout
L
A1
L
A1'
L
B
L
B’
L
C
L
C’
L
E
L
E’
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Table 22.
USB 2.0 External Routing Guidelines MicroUSB
PCB Routing Layer(s) optional
Transmission Line Segment
Routing Layer (Microstrip / Stripline /
Dual Stripline)
Breakout 1
4 Layer
L
A
MS
4 Layer
L
B
MS
4 Layer
L
C
MS
4 Layer
L
E
MS
Characteristic Impedance (Differential)
90 Ω +/-
10%
4.0 mil
90 Ω +/-
10%
4.0 mil
90 Ω +/-
10%
4.0 mil
90 Ω +/-
10%
4.0 mil Trace Width (w)
Trace Spacing (S1): Between P and N of clock pair
Trace Spacing (S2): Between USB2 different pairs
Trace Spacing (S3): Between USB2 pairs and other signals
4.0 mil
6.0 mil
6.0 mil
6.0 mil
15 mil
25 mil
6.0 mil
15 mil
25 mil
6.0 mil
15 mil
25 mil
Trace Segment Length 0.5" max 0.1" - 2.0" 0.2" max 0.5" max
Note: Recommend a cable length of 9" or less for connectivity from a microUSB to panel based standard
USB connector.
Length Matching Rules
Length Matching between P and N within a diff. pair
General
Number of vias
Routing Symmetry
Layer Assignment
Reference plane
MCH Settings
+/- 5 mil max 3 vias
Symmetrical routing of P and N of a diff pair including vias
See recommendations above
Ground Only
Gold_cie69_usb2_tx_drv_hspice_rev1p0_ ww28 vswing = 0.42
Preemp = 0.19054 (40mV)
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Figure 27.
USB 2.0 Mini PCIe Topology
TX
SoC
Breakout
L
A1
L
A1'
L
B
L
B’
L
C
L
C’
L
D
L
D’
Mini
PCIe*
Conn
Table 23.
USB 2.0 External Routing Guidelines Mini PCIe*
PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip / Stripline /
Dual Stripline)
Breakout
4 Layer
L
A
MS
4 Layer
L
B
MS
Characteristic Impedance (Differential)
90 Ω +/-
10%
4.0 mil
90 Ω +/-
10%
4.0 mil Trace Width (w)
Trace Spacing (S1): Between P and N of clock pair
Trace Spacing (S2): Between USB2 different pairs
Trace Spacing (S3): Between USB2 pairs and other signals
4.0 mil
6.0 mil
6.0 mil
6.0 mil
15 mil
25 mil
Trace Segment Length 0.5" max
Note: Can support up to 2" on the Mini PCIe Card
0.1" - 2.0"
4 Layer
L
C
MS
90 Ω +/-
10%
4.0 mil
6.0 mil
15 mil
25 mil
0.2" max
4 Layer
L
D
MS
90 Ω +/-
10%
4.0 mil
6.0 mil
15 mil
25 mil
0.5" max
Length Matching Rules
Length Matching between P and N within a diff. pair
General
Number of vias
Routing Symmetry
Layer Assignment
Reference plane
+/- 5 mil max 3 vias
Symmetrical routing of P and N of a diff pair including vias
See recommendations above
Ground Only
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MCH Settings
Gold_coe69_usb2_tx_drv_hspice_rev1p0_ ww28 vswing = 0.42
Preemp = 0.09527 (20mV)
5.3.2
USB Connector Recommendations
Proper connector choice is critical to ensure adequate USB signal quality. For the Intel ®
Quark™ SoC X1000 the initial recommendation is the use of single USB connectors, empirical data has shown that quad-stack USB connectors may add interference causing poor USB signal quality. Refer to usb.org for a list of tested connectors.
5.3.2.1
External Connector Recommendations
The cable and PCB mating connector must pass the TDR requirements listed in the USB
2.0 Specification
5.3.2.1.1
USB 2.0 Internal Connector
It is possible to define the internal connector pin list based on individual needs.
However, an example connector pin list for 2-port internal cable connection supporting
USB 2.0 is shown below.
Note: The Intel
®
Quark™ SoC X1000 does not support USB 3.0
Figure 28.
Example of Internal Connector Pin Assignment and Description
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5.3.3
Daughter Card
The best way to provide internal support for USB is to use a daughter card and cable assembly. This allows the placement of the EMI/ESD suppression components right at
the USB connector where they will be the most effective. Figure 29
shows the major components associated with a typical USB solution that uses a daughter card.
When designing the motherboard with internal topology support, the system integrator should know which type of cable assembly will be used. If the system integrator plans to use a connector card, ensure that there aren’t duplicate EMI/ESD/thermistor components placed on the motherboard, as this will usually cause drop/droop and signal quality degradation or failure.
Figure 29.
Daughter Card
5.3.3.1
5.4
5.4.1
5.5
Daughter Card Design Guidelines
The following are recommended when designing a USB 2.0 daughter card:
• Place the VBUS bypass capacitor, CMC, and ESD suppression components on the daughter card as close as possible to the connector pins.
• Follow the same layout, routing and impedance control guidelines as specified for motherboards.
• Use the same mating connector pinout as - USB 2.0 Internal Connector Pinout
(Motherboard).
• Minimize the trace length on the daughter card - Less than a 2-inch trace length is recommended.
• Use the same routing guidelines as described in USB 2.0 Stackup Guidelines.
• Power and ground nets should have double vias. Trace lengths should be kept as short as possible.
USB 2.0 Stackup Guidelines
Stackup and Layer Utilization Guidelines
Please see the 4 Layer Stackup Chapters for all IO routing guidelines including USB 2.0.
USB 2.0 Configuration, Connectivity, Block Diagram
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Intel ® Quark™ SoC X1000—Universal Serial Bus 2.0 Design Guidelines
5.5.1
Port Power Delivery
The following is a suggested topology for power distribution of VBUS to USB ports.
These circuits provide two types of protection during dynamic attach and detach situations on the bus: inrush current limiting (droop) and dynamic detach flyback protection. These two types require both bulk capacitance (droop) and filtering capacitance (for dynamic detach flyback voltage filtering). Intel recommends the following:
• Minimize the inductance and resistance between the coupling capacitors and the
USB ports.
• Place capacitors close as possible to the port and the power-carrying traces should be as wide as possible, preferably, a plane.
• Make the power-carrying traces wide enough that the system fuse blows on an overcurrent event. If the system fuse is rated at 1 A, then the power-carrying traces should be wide enough to carry at least 1.5 A.
Good Downstream Power Connection
VCC
100uF 47uF
VCC
470pF
GND
5.6
5.6.1
5.7
5.7.1
5.8
USB 2.0 Length Matching Guidelines
Length Matching and Length Formulas
Please refer to the General Differential Design Guide in Appendix A for length matching
guidelines.
USB 2.0 Additional Guidelines
EMI and ESD Protection
Please refer to
Chapter 17.0, “Electromagnetic Interference”
“Electrostatic Discharge (ESD)” .
USB 2.0 Disabling and Termination Guidelines
If a USB port(s) is not implemented on the platform:
• USB P/N [x] signals can be left unconnected
§ §
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I2C* Interface Design Guidelines—Intel ® Quark™ SoC X1000
6.0
6.1
6.1.1
I
2
C* Interface Design Guidelines
I
2
C* General Introduction
Description
There is a single I wire I
2
2
C* controller in Intel operation is supported. The I the platform.
2
®
Quark™ SoC X1000. The interface is a two-
C serial interface consisting of a serial data line and a serial clock, only 3.3v
C interfaces are intended to support various sensors on
Each I 2 C interface supports standard mode (up to 100 Kb/s) and fast mode (up to 400
Kb/s).Fast mode plus (up to 1 Mb/s) and High speed mode (up to 3.4 Mb/s) are not supported.
Reference Specifications 6.1.2
Title
6.2
6.2.1
I
2
C Specification Version 2.1
I
2
C* Signal Descriptions
Signal Groups
Table 24.
I 2 C Signals
Group
Clock
Data
I2C_CLK
I2C_DATA
Signal Name Description
I 2 C Clock signal
I 2 C Data signal
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Intel ® Quark™ SoC X1000—I2C* Interface Design Guidelines
6.3
6.3.1
6.3.2
Table 25.
I
2
C* Topology Guidelines
General Design Considerations
• I
2
C clock and data signals require pull-up resistors. The pull-up resistor size is dependent on the bus capacitive load (this includes all device leakage currents).
The maximum bus capacitive load for each I
2
C bus is 400 pF. The pull-up resistor cannot be made so large that the bus time constant (Resistance X Capacitance) does not meet the I
2
C rise and fall time specification. Refer to Table 27 for
recommendations on pull-up resistors depending on bus capacitance.
Detailed Routing Requirements
Table below shows detailed routing requirement for I length is dependent on total capacitance of the bus, designer needs to take into consideration the number and types of I for guidance on trace capacitance.
2
C bus. Note that, since I
2
C devices on each I
2
2
C trace
I
2
C* Signal Routing Summary
Parameter
Trace Width
Trace Spacing
Breakout width
Breakout Spacing
Max Breakout Length
Length Matching
Impedance
Stackup Units
MS mils
MS mils
MS mils
MS mils
NA
NA
MS mils mils ohm
I2C_DATA
4
5
3.5
4
500
540
50 ±10%
Routing
Recommendation
I2C_CLK
4
15
500
50 ±15%
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I2C* Interface Design Guidelines—Intel ® Quark™ SoC X1000
6.4
I
2
C* Connectivity
The I 2 C interface is primarily to support various sensors which may have different bandwidth requirements on the platform.
Figure 30.
Example of Devices on I 2 C* Bus
I
2
C*
SOC
Sensors or
Sensor
Hub
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Intel ® Quark™ SoC X1000—I2C* Interface Design Guidelines
6.5
Table 26.
I
2
C* Additional Guidelines
System designers must consider the total bus capacitance, which includes both SoC and device pin capacitance and board trace length capacitance when designing I 2 C bus.
The total bus capacitance must not exceed 400 pF. Table 26 and Table 27
below provide info to help determine total bus capacitance and proper pull-up resistors on the I buses. Analysis of a particular layout is still required to confirm correct operation.
2 C
Bus Capacitance Reference Chart
Device
MCP
Board Trace per
Inch
Pin Capacitance
Capacitance Includes
TBD pF per inch of trace length pF
Units pF
Capacitance
10
TBD
Table 27.
6.6
Example Bus Capacitance/Pull-Up Resistor Relationship
Physical Bus
Segment
Capacitance
10 to 50 pF
50 to 100 pF
10 to 100 pF
100 to 200 pF
200 to 300 pF
300 to 400 pF
Pull-Up Range
(For Vcc = 3.3 V)
100kHz
NA
NA
9 k to 1 k
5 k to 1 k
3.5 k to 1 k
2.5 k to 1 k
Pull-Up Range
(For Vcc = 3.3 V)
400kHz
NA
NA
2.4k
to 0.4 k
1.6 k to 0.4 k
1 k to 0.4 k
0.8 k to 0.4 k
Terminating Unused I
2
C Signals
If I
2
C interfaces are not used, the signals should be terminated with external pull-up or pull-down resistors.
§ §
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SDIO Interface Design Guidelines—Intel ® Quark™ SoC X1000
7.0
SDIO Interface Design Guidelines
7.1
7.1.1
7.2
7.2.1
SDIO General Introduction
Description
Intel
®
Quark™ SoC X1000 implements a single SDIO interface that is only intended for general-purpose connections, such as SD cards. It supports SDIO card specification 3.0 and the MMC specification 3.31, 4.2, and 4.41. Support for up to 400 Mbits/s operation using 8-bit parallel lines (MMC8 mode) and 200 Mbits/s using 4 parallel lines (sd4 mode).
The physical connection supports the dynamic removal/insertion of cards by end users.
SDIO Signal Descriptions
Signal Groups
Table 28.
SDIO Signals
Group
Clock
Data
Command
Power Enable
Signal Name
SD_CLK
SD_DATA_0,
SD_DATA_1,SD_DATA_2,
SD_DATA_3,SD_DATA_4,
SD_DATA_5,SD_DATA_6,
SD_DATA_7
SD_CMD
SD_WP
SD_LED
SD_PWR_B
Description
SDIO Clock signal
SDIO Data signals
SDIO Command Signal
Output from the SoC for controlling device power
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Intel ® Quark™ SoC X1000—SDIO Interface Design Guidelines
7.3
SDIO Topology Guidelines
This section contains information and details for layout and routing guidelines for the
SDIO interfaces.
Figure 31.
SDIO Topology with Connector
SoC
Breakout
L
A
L
B
Rs
L
C
E
S
D
L
D
Connector
CFIOHVTEW NO RCOMP
Table 29.
SDIO Layout Guideline
PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip / Stripline /
Dual Stripline)
Characteristic Impedance (Singleended)
Trace Width (w)
Trace Spacing(S2): Between SDIO
Signals
Trace Spacing(S3): Between SDIO and other signals
Breakout
4 Layer
L
A
MS
50 Ω +/-
15%
4.2 mil
4.2 mil
4.2 mil
4 Layer
50
L
B
MS
Ω +/-
10%
4.2 mil
10 mil
10 mil
4 Layer
L
C
MS
50 Ω +/-
10%
4.2 mil
10 mil
10 mil
4 Layer
MS
50
L
D
Ω +/-
10%
4.2 mil
4.2 mil
4.2 mil
Trace Segment Length 0.5" max 0.1" - 0.8" 0.1" - 3.0" 0.5" max
Note: * Keep La + Lb as short as possible to give the best margin on the overshoot/undershoot violation.
7.4
Data to Clock MB length matching rule 1
Number of vias
Rs
Reference Plane
1. Relates to platform routing, inter-package routing not considered.
< 200mils max 2
33 +/- 5%
Solid Ground Reference
Terminating Unused SDIO Signals
If SDIO interface is not used, it should be terminated properly with external pull-up or
pull-down resistors.See Table 30
regarding internal pull up/down.
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Table 30.
SOC SDIO Pull Up/Down
Pin
SD_CLK
SD_DATA_0,
SD_DATA_1,SD_DATA_2,
SD_DATA_3,SD_DATA_4,
SD_DATA_5,SD_DATA_6,
SD_DATA_7
SD_CMD
SD_PWR_B
SD_WP
SD_LED
Status
External Weak Pull Up or Pull Down as appropriate for strapping
Internal 20K Pull Up
Internal 20K Pull Up
External Weak Pull
Internal 20K Pull Down
No internal Pull Up or Pull Down
§ §
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Intel ® Quark™ SoC X1000—SDIO Interface Design Guidelines
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UART Interface Design Guidelines—Intel ® Quark™ SoC X1000
8.0
UART Interface Design Guidelines
8.1
8.1.1
8.2
8.2.1
General Introduction
Description
The Intel
®
Quark™ SoC X1000 SoC integrates two UART controllers. Each supports up to a max 2.76 Mbit/s. The interfaces support 3.3V only. The controllers can be used in the low-speed, full-speed, and high-speed modes. The UART controllers are based on the 16550 industry standard. The UART interfaces can be utilized to support various sensors or a Bluetooth* device on the platform.
General Purpose Signal Descriptions
Signal Groups
Table 31.
8.3
UART Signals
Group
Data
Control
Signal Name
SIU0_RXD
SIU1_RXD
SIU0_TXD
SIU1_TXD
SIU0_RTS
SIU1_RTS
SIU0_CTS
SIU1_CTS
SIU0_DCD_B
SIU0_DSR_B
SIU0_DTR_B
SIU0_RI_B
Description
Receive Data Input signals
Transmit Data Output signals
Request to Send signals
Clear to Send signals
Data Carrier Ready
Data Set Ready
Data Terminal REady
Ring Indicator
UART Topology Guidelines
This section contains information and details for layout and routing guidelines for the
UART interfaces.
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Intel ® Quark™ SoC X1000—UART Interface Design Guidelines
Figure 32.
UART Topology
SOC
SOC UART
Data &
Control
Signals
BO M
UART Device
Device
Data &
Control
Signals
Table 32.
8.4
8.5
Table 33.
UART Routing Guideline
Parameter
Stackup
(MS/SL/DSL)
Units
Routing
Recommendation
M - Trace Length
M - Trace Width
M - Trace Spacing
BO - Breakout Width
BO - Breakout Spacing
BO - Max Breakout Length
Impedance
MS
MS
MS
MS
MS
MS
MS inch mils mils mils mils mils ohm
1 - 7
4
5
3
3.5
500
50 ±15%
Additional Guidelines
The UART interfaces support 3.3V only. Therefore, if devices connected to the UART interfaces utilize 1.8V, external voltage translation must be implemented on the motherboard to support this configuration.
Terminating Unused UART Signals
If the UART functionality is not utilized, the signals should be terminated properly with external pull-up or pull-down resistors. The SOC implements internal pullup and pull
down on the UART IO, see Table 33 .
UART Internal Pull Up/Down
Pin
SIU0_RXD
SIU1_RXD
SIU0_TXD
SIU1_TXD
SIU0_RTS
SIU1_RTS
SIU0_CTS
SIU1_CTS
SIU0_DCD_B
Input
Output
Output
Input
Input
Direction Pull Up/Down
Internal 20K Pull Up
No Internal Pull up or Pull Down
No Internal Pull up or Pull Down
Internal 20K Pull Up
Internal 20K Pull Up
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Table 33.
UART Internal Pull Up/Down
Pin
SIU0_DSR_B
SIU0_DTR_B
SIU0_RI_B
Input
Output
Input
Direction
§ §
Pull Up/Down
Internal 20K Pull Up
No Internal Pull up or Pull Down
Internal 20K Pull Up
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General Purpose SPI Interface Design Guidelines—Intel ® Quark™ SoC X1000
9.0
9.1
9.1.1
General Purpose SPI Interface Design Guidelines
General Introduction
Description
The two general-purpose SPI interfaces support various devices which use serial protocols for transferring data such as sensors on the platform.
Each interface consists of 5 wires: a clock (CLK), two chip select’s (CS0 & CS1) and 2 data lines (MOSI and MISO). The CS signals are generated from GPIO pins.
The general-purpose SPI is full-duplex synchronous serial interface. The SPI interface operates in master mode only, and supports serial bit rate up to 25Mb/s. Serial data formats may range from 4 to 32 bits in length.
General Purpose Signal Descriptions
Signal Groups
9.2
9.2.1
Table 34.
SPI Signals
Clock
Data
Chip Select
Chip Select
1
2
Group
SPI 0
SPI 1
Signal Name
SPI0_SCK
SPI1_SCK
SPI0_MISO
SPI1_MISO
SPI0_MOSI
SPI1_MOSI
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
Description
Clock signals
Master In Slave Out signals
Master Out Slave In signals
Chip select signals for SPI 0
Chip select signals for SPI 1
1. Though SPI0_SS_B is available as pins in order to support multiple SPI slaves they are not utilized.
2. Though SPI1_SS_B is available as pins in order to support multiple SPI slaves they are not utilized.
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Intel ® Quark™ SoC X1000—General Purpose SPI Interface Design Guidelines
9.3
Topology Guidelines
This section contains preliminary information and details for layout and routing guidelines for the general-purpose SPI interfaces.
Figure 33.
SPI0 Topology
SoC
Breakout
L
A
L
B
Rs
L
C
L
D
SPI Slave
Table 35.
SPI0_MOSI, SPI0_SCK
PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip / Stripline /
Dual Stripline)
Characteristic Impedance (Singleended)
Trace Width (w)
Trace Spacing(S2): Between GPIO
Signals
Trace Spacing(S3): Between GPIO and other signals
Breakout
4 Layer
L
A
MS
4.2 mil
4.2 mil
4.2 mil
4 Layer
L
B
MS
50
4.2 mil
10 mil
10 mil
Ω
4 Layer
L
+/- 10%
C
MS
4.2 mil
10 mil
10 mil
4 Layer
L
D
MS
4.2 mil
4.2 mil
4.2 mil
Trace Segment Length 0.5" max 0.1" - 0.8" 0.1" - 3.0" 0.5" max
Note: * Keep La + Lb as short as possible to give the best margin on the overshoot/undershoot violation.
Table 36.
SPI0_MISO
PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip / Stripline /
Dual Stripline)
Characteristic Impedance (Singleended)
Trace Width (w)
Trace Spacing(S2): Between GPIO
Signals
Breakout
4 Layer
L
A
MS
4.2 mil
4.2 mil
4 Layer
L
B
MS
4 Layer
L
C
MS
50 Ω +/- 10%
4.2 mil 4.2 mil
10 mil 10 mil
4 Layer
L
D
MS
4.2 mil
4.2 mil
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Table 36.
SPI0_MISO
Breakout
Trace Spacing(S3): Between GPIO and other signals
4.2 mil 10 mil 10 mil 4.2 mil
Trace Segment Length 0.5" max 0.1" - 3.0" 0.1" - 0.8" 0.5" max
Note: * Keep Lc + Ld as short as possible to give the best margin on the overshoot/undershoot violation.
Data to Clock MB length matching rule 1
Number of vias
Rs
< 200mils max 2
33ohm +/- 5%
Reference Plane
Buffer
Solid Ground Reference c69p0cfiohvtewtop_3.3V_po
lo
1. This requirement relates to the platform routing and does not include the inter package routing.
Note: The guidelines regarding the routing of the GPIO based CS are TBD.
Figure 34.
SPI1 Topology
SoC
Breakout
L
A
L
B
Rs
L
C
Connector
J11
L
D
SPI SLave
Table 37.
SPI1_MOSI, SPI1_SCK
PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip /
Stripline / Dual Stripline)
Characteristic Impedance
(Single-ended)
Trace Width (w)
Trace Spacing(S2): Between
GPIO Signals
Trace Spacing(S3): Between
GPIO and other signals
Trace Segment Length
Breakout
4 Layer
L
A
MS
4.2 mil
4.2 mil
4.2 mil
0.5"
4 Layer
L
B
MS
4 Layer
L
C
MS
4.2 mil
50 Ω +/- 15%
4.2 mil
10 mil 10 mil
15 mil min = 0.2" max = 0.8"
15 mil min = 0.1" max = 1.5"
4 Layer
L
D
MS
4.2 mil
10 mil
15 mil
0.25" max
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Intel ® Quark™ SoC X1000—General Purpose SPI Interface Design Guidelines
Table 38.
SPI1_MISO
PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip /
Stripline / Dual Stripline)
Characteristic Impedance
(Single-ended)
Trace Width (w)
Trace Spacing(S2): Between
GPIO Signals
Trace Spacing(S3): Between
GPIO and other signals
Trace Segment Length
Breakout
4 Layer
L
A
MS
4.2 mil
4.2 mil
4.2 mil
0.5"
4 Layer
L
B
MS
4 Layer
L
C
MS
4.2 mil
50 Ω +/- 15%
4.2 mil
10 mil 10 mil
15 mil min = 0.1" max = 1.5"
15 mil min = 0.2" max = 0.8"
4 Layer
L
D
MS
4.2 mil
10 mil
15 mil
0.25" max
Note:
Data to Clock MB length matching rule
1
Number of vias
Rs
Reference Plane
< 200mils max 1
33ohm +/- 5%
Solid Ground Reference
1. This requirement relates to the platform routing and does not include the inter package routing.
The guidelines regarding the routing of the GPIO based CS are TBD.
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General Purpose SPI Interface Design Guidelines—Intel ® Quark™ SoC X1000
9.4
Table 39.
Terminating Unused SPI Signals
If the SPI functionality is not utilized, the signals should be terminated properly with external pull-up or pull-down resistors.
SOC SPI Internal Pull Up/ Pull Down
Pin Direction
SPI0_MISO
SPI1_MISO
SPI0_MOSI
SPI1_MOSI
SPI0_SCK
SPI1_SCK
Input
Input
Output
Output
Output
Output
Status
Internal 20K Pull up
Internal 20K Pull up
External Weak Pull Up or Pull Down
External Weak Pull Up or Pull Down
External Weak Pull Up or Pull Down
External Weak Pull Up or Pull Down
§ §
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Platform Clocks Design Guidelines—Intel ® Quark™ SoC X1000
10.0
Platform Clocks Design Guidelines
10.1
Platform Clock General Introduction
10.1.1
Description
Intel
®
Quark™ SoC X1000 implements full integrated clocking mode as the default platform clock solution. In the full-clock integration mode, a 25 MHz crystal oscillator provides the input clock to the Intel
®
Quark™ SoC X1000 integrated clock controller and SoC generates the output clocks that are required by all the platform components.
Figure 35.
Clock Integration Distribution Diagram
S o C
F L E X 3 _ C L K /R M II_ R E F C L K _ 5 0 M
F L E X 0 _ C L K
F L E X 1 _ C L K
F L E X 2 _ C L K
R E F 0 _ O U T C L K _ P /N
R E F 1 _ O U T C L K _ P /N
3 3 M H z
3 3 M H z
4 8 M H z
1 0 0 M H z s s c
1 0 0 M H z s s c
X T A L _ IN
X T A L _ O U T
O S C
M A C P H Y
Note:
2 5 .0 0 0 M H z
REF0_OUTCLK and REF0_OUTCLK default to SSC mode (Spread Spectrum Clock)
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Note:
Note:
10.2
A 25 MHz crystal will be connected to the SoC as an input. This crystal input is used to generate the following platform clock outputs:
• 1x 50 MHz differential sources for RMII_REFCLK_50M
• Two 33 MHz single ended clocks.
• 48 MHz single ended clock.
• Two 100 MHz differential clocks which default to spread spectrum mode.
25 MHz Crystal Requirement: All SoC-based platforms must use a 25 MHz crystal on the platform to generate a differential clock on XTAL_IN/OUT to enable SoC to generate platform clocks. It is critical that this XTAL clock is of good quality and has minimal interference to ensure correct locking of the internal PLL. Intel is not validating use of an external clock buffer oscillator connection to XTAL pins.
Unused SoC Clock Outputs: All unused clocks on SoC can be left as No Connect.
Platform Reference Clock Signal Descriptions
Table 40.
Signal Groups
Clock Type
Input from 25 MHz crystal (Required)
Output Clocks from SoC
Clock Signals
XTAL_IN/XTAL_OUT
CLKSYS25_OUT
REF0_OUTCLK_P
REF0_OUTCLK_N
REF1_OUTCLK_P
REF1_OUTCLK_N
SPI_CLK
FLEX0_CLK
FLEX1_CLK
FLEX2_CLK
RMII_REF_CLK_OUT
Description
25 MHz source clock for Full Clock Integrated mode
Single-ended 25 MHz output to devices.
REF0_CLK: 100MHx 1v differential
REF1_CLK: 100MHz 1v differential
SPI Clocks from SoC
FLEX0_CLK 33.33MHz 3.3v
FLEX1_CLK 33.33MHz 3.3v spread spectrum
FLEX2_CLK 48MHz 3.3v
Reference clock for RMII interface
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Platform Clocks Design Guidelines—Intel ® Quark™ SoC X1000
10.3
10.3.1
Platform Clocks Topology Guidelines
Differential Clock Routing Topology
The following SoC clock outputs utilize the guidelines in this section:
• Differential reference clocks, e.g., REF0_CLK_P/N
Figure 36.
Differential Clock Topology for SoC to Clock Receiver
SoC
+
iCLK TX
-
Dogbone
L
A1
L
A1
Breakout
L
A2
L
A2
L
B
L
B
L
C
L
C
Breakin
L
D
L
D
Mini
PCIe*
Connector
Table 41.
Differential Clock Routing Guidelines
REFCLK0_P & REFCLK0_N Dogbone
PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip /
Stripline / Dual Stripline)
Characteristic Impedance
(Differential)
Trace Width (w)
4 Layer
L
A1
MS
4.0 mil
Trace Spacing (S1): Between P and N of clock pair
Trace Spacing(S2): Between different Clock pairs
4.0 mil
6.0 mil
Trace Spacing(S3): Between
Clock pairs and other signals
6.0 mil
Trace Segment Length 0.05" max
Note: Can support up to 2" on the Mini PCIe Card
L
Breakout
4 Layer
A2
MS
4.0 mil
4.0 mil
6.0 mil
6.0 mil
0.5" max
Main
Route 1
4 Layer
L
B
MS
100 Ω +/- 10%
4.0 mil
15 mil
20 mil
20 mil
1.5" max
4 Layer
L
C
MS
4.0 mil
15 mil
20 mil
20 mil
0.2" max
Breakin
4 Layer
L
D
MS
4.0 mil
15 mil
20 mil
20 mil
0.5" max
Length Matching between P and N within a diff. pair
Number of vias
Reference Plane
Match segments <=10 mils
Match overall length <=10 mils max 3
Continuous Ground only
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10.3.1.1
10.3.1.2
10.3.2
Differential Routing Considerations
When routing differential clocks, note the following recommendations:
• Ground referencing is preferred. However, differential clocks can be routed referenced to other planes through the use of stitching capacitors to provide the appropriate decoupling where the signal crosses planes.
• Do not split up the two halves of a differential clock pair between layers. Route to all agents on the same physical routing layer referenced to ground.
— Typical routing assumes 1 layer transition within 500 mils of the SoC package and a second layer transition within 500 mils of the destination ball.
— If a layer transition is required, both clock traces of the differential clock pair must transition layers at the same length ±100 mils.
— If an additional layer transition is required, use simulations to ensure the skew induced by the vias used to transition between routing layers is compensated in the traces to other agents.
• Do not place vias between adjacent complementary clock traces and avoid differential vias. Vias, placed in one signal of a differential-pair must be matched by a via in the complement. Differential vias can be placed within length BO if needed to shorten length BO.
No length matching is required between different source pairs.
Stitching Via Usage and Placement
Stitching vias must be used when signal traces change layers from top layer to bottom or internal layer. In these cases reference GND layer associated with top signal layer has to be connected with GND reference layer associated with bottom or internal signal layer using GND stitching via. Placing GND stitching via according current guidelines maintains optimal current return path and minimize crosstalk effect.
• Stitching vias should be placed with this spacing:
— 30-mils (0.762-mm) pitch between differential clock via and closest stitching
GND-via.
— Every differential clock via must have at least one GND stitching via with a maximum spacing of 30 mils (0.762 mm).
• Placement of additional stitching vias, where possible, is recommended.
Motherboard GND stitching vias placement for differential clock signals.
Single Ended Clock Routing Topology
Figure 37.
Single Ended Clock Topology for SoC
SoC
Breakout
L
A1
Rs
L
A2
Rs
Rs
L
B
L
B
L
C
L
C
L
D
Receiver A
Receiver B
L
D
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Table 42.
iClock (Single-ended Clocks)
For the Intel
®
Quark™ SoC X1000 use case, one of the flex clocks,
RMII_REF_CLK_OUT clock, is used as a reference to the RMII. This clock is routed to the PHY and also back the SoC integrated MAC.
RMII_REF_CLK_OUT
PCB Routing Layer(s) optional
Transmission Line Segment
Routing Layer (Microstrip /
Stripline / Dual Stripline)
Characteristic Impedance
(Single-ended)
Trace Width (w)
Trace Spacing(S2): Between
Single-ended Clocks
Trace Spacing(S3): Between
Clock and other signals
Trace Segment Length
Breakout
4 Layer
L
A1
MS
4 Layer
L
A2
MS
4 Layer
L
B
MS
4 Layer
L
C
MS
4.2 mil
4.2 mil
4.2 mil
50 Ω +/- 15%
4.2 mil
20 mil
4.2 mil 20 mil
0.5" max 0.8" max
L
A
+ L
A2
<= 500 mil
20 mil
20 mil
0.2" max
4.2 mil
20 mil
20 mil
6" max
4 Layer
L
D
MS
4.2 mil
20 mil
20 mil
1" max
10.4
Length Matching between Single-ended Clocks
Rs
Number of vias
Reference Plane
Total trace length from SoC output
(RMII_REF_CLK_OUT) to external PHY must match the trace length from SoC Output
(RMII_REF_CLK_OUT) to SoC input
(RMII_REF_CLK) within 10mils.
22 ohm +/- 5% max 2
Continuous Ground only
The single ended clocks are driven via clock drivers. The package and board routes should be treated similarly to differential clock routes. They should be fully shielded on both sides with VSS that is applicable to the driver, and with spacing equal to or greater than the standard clock routes should be maintained. They should not be routed over the XTAL_IN and XTAL_OUT traces.
25 MHz Crystal and Associated RC Components
Platforms are required to use the 25 MHz crystal to generate all platform clocks. This requires that on board the following components should be stuffed:
• A 25 MHz crystal
• 2 External Load Capacitors Ce1 and Ce2
• A 1-M bias resistor
below for illustration of the 25 MHz crystal connectivity.
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10.4.1
Crystal External Load Capacitor Requirements
The 25 MHz crystal is physically tuned to operate within the specified frequency range and ppm tolerance with a certain expected capacitive load present. The expected external capacitive load to be used (Ce) consists of the crystal capacitive load plus the pin and trace capacitances. The external load capacitors are important to minimize frequency variations from the crystal by compensating for variable PCB factors related to pin and trace capacitance. Care must be exercised in the selection of the external load capacitors to present the expected capacitive load specified for the crystal in use on the platform.
The appropriate capacitor value for the platform may be determined using the following formula:
C e
= 2 * C
L
- (C s
+ C i
), where:
• C e
= External Load Capacitor Value; (18-27 pF)
• C
L
= Specified Crystal Capacitive Load; (Can be found from crystal datasheet)
• C s
= Board Trace Capacitance (includes crystal pad capacitance); (2-10 pF)
• C i
= SoC Pin Capacitance; (2-3 pF)
Figure 38 illustrates the crystal external load capacitor parameters. Due to vendor
variation in crystal characteristics, layout variations and PCB trace capacitance differences, the above calculation should be performed for each design to determine the precise value of C e
that is optimal for the particular platform.
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Figure 38.
25 MHz Crystal External Load Capacitor Parameters
SO C
C i
1
D river
C i
2
O scillator
C i
P in 2-3pF
1M B ias
R esistor
C s
1
C e
1
25M H z
C
L(crystal parasitic load)
C s
2
C e
2
C s
Trace 2-10pF
10.4.2
Note:
C e
=C e
1=C e
2
E xternal Load C ap on board
18-27pF
25 MHz Crystal Routing Considerations
• Short (< than 1250 mils) shielded traces on XTAL_IN/XTAL_OUT to minimize crosstalk induced jitter.
• Shield XTAL_IN/XTAL_OUT signals and reference to ground planes.
• Highly recommended to not route high frequency signals directly below the crystal.
The oscillator signals are very sensitive to board noise due to very slow shape of waveforms (sine waves). Care should be taken to provide shielding from any noisy signals near traces or under the components associated with oscillator.
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SPI Flash Design Guidelines—Intel ® Quark™ SoC X1000
11.0
SPI Flash Design Guidelines
11.1
11.1.1
11.2
Serial Peripheral Interface (SPI) General Introduction
The following provides general guidelines for compatibility and design recommendations for supporting flash devices.
Description
Intel
®
Quark™ SoC X1000 supports three integrated Serial Peripheral Interface (SPI)
4-pin interfaces that provides a potentially lower-cost alternative for system flash.The
Legacy SPI interface is specifically for the system boot flash and the additional two interfaces are for general purpose use. Each Serial Peripheral Interface is used to support a SPI compatible flash device via an independent GPIO chip select pin. Each
SPI flash device can be up to 64 MBytes (512 Mbits). SoC drives the SPI Interface at either 20 MHz (legacy SPI) or 25Mhz.
Serial Peripheral Interface (SPI) Signal Description
Table 43.
SPI Signals
Signal Name
LSPI_MOSI
LSPI_MISO
LSPI_CLK
LSPI_SS_B
SPI0_MOSI
SPI1_MOSI
SPI0_MISO
SPI1_MISO
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
SPI0_SCK
SPI1_SCK
Data
Group
Data
Clock
Chip Select
Data
Data
Chip Select
Chip Select
Clock
Description
Legacy SPI serial output data from Intel ® the SPI flash device.
Quark™ SoC X1000 to
Legacy SPI serial input data from the SPI flash device to Intel ®
Quark™ SoC X1000.
Legacy SPI Clock output from Intel ® Quark™ SoC X1000
Legacy SPI chip select
SPI serial output data from Intel ® flash device.
Quark™ SoC X1000 to the SPI
SPI serial input data from the SPI flash device to Intel ®
SoC X1000
Quark™
SPI chip selects for SPI 0 Interface
SPI chip select for SPI 1 Interface
SPI Clock output from
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11.3
Serial Peripheral Interface (SPI) Topology Guidelines
This section contains preliminary information and details for layout and routing guidelines for Intel ® Quark™ SoC X1000 SPI interface. The Legacy SPI flash must be directly connected to the Intel considerations.
® Quark™ SoC X1000 Legacy SPI bus in all SKUs. Also, refer to the Serial Flash vendor documentation for additional Serial Flash specific design
SPI Single Flash Device Topology Guidelines 11.3.1
Figure 39.
Legacy SPI Topology (Single Device)
S o C
L S P I_ M O S I
L S P I_ M IS O
S e ria l F la sh
S e ria l In p u t
S e ria l O u tp u t
LS P I_ C LK
L S P I_ S S _ B
C lo ck
C h ip S e le ct
11.3.1.1
SPI Single Flash Device Routing Guideline
Figure 40.
SPI Single Flash Device Routing Guidelines for LSPI0_MOSI, LSPI0_MISO,
LSPI0_CS_N,LSPI0_SCK
SoC
Breakout
L
A
L
B
Rs
L
C
L
D
Legacy SPI
Flash
Device
Table 44.
LSPI0_MOSI, LSPI0_MISO, LSPI_SS_B, LSPI0_SCK (Sheet 1 of 2)
PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip / Stripline /
Dual Stripline)
Characteristic Impedance (Singleended)
Trace Width (w)
Trace Spacing(S2): Between GPIO
Signals
Breakout
4 Layer
L
A
MS
4.2 mil
4.2 mil
4 Layer
L
B
MS
4 Layer
L
C
MS
50 Ω +/- 10%
4.2 mil
10 mil
4.2 mil
10 mil
4 Layer
L
D
MS
4.2 mil
4.2 mil
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Table 44.
11.3.1.2
11.3.2
11.4
LSPI0_MOSI, LSPI0_MISO, LSPI_SS_B, LSPI0_SCK (Sheet 2 of 2)
Trace Spacing(S3): Between GPIO and other signals
4.2 mil 10 mil 10 mil 4.2 mil
Trace Segment Length 0.5" max 0.1" - 0.8" 0.1" - 3.0" 0.5" max
Note: * Keep La + Lb as short as possible to give the best margin on the overshoot/undershoot violation.
SPI Single Flash Device Length Matching Requirement
• LSPI_SCK & LSPI_MOSI must be length matched to within 500mils.
• LSPI_SCK & LSPI_SS_B must be length matched to within 500mils.
Boot BIOS Destination
Intel ® Quark™ SoC X1000 can only boot via the Legacy SPI interface, SPI0 and SPI1 can be used for non-volatile data.
Serial Flash Vendors
The following list of vendors manufacture serial flash devices should not be considered as Intel Approved Devices or vendors. But these devices conform to Intel’s specific requirements. For additional details on the compatibility requirements for SPI devices refer to the latest SoC EDS. Contact the flash vendor directly for information on packaging and density.
VENDOR
ATMEL
MACRONIX
SST/MICROCHIP
NUMONYX/MICRON
WINBOND
SPANSION
EON
AMIC
GIGADEVICE
FIDELIX
Chingis Technology
PMC
WEBSITE http://www.atmel.com/ http://www.mxic.com.tw
http://www.microchip.com
http://www.micron.com/ http://www.winbond.com/ http://www.spansion.com/ http://www.eonssi.com/ http://www.amictechnology.com
http://www.gigadevice.com
http://www.fidelix.co.kr/ http://www.chingistek.com/ http://www.pmcflash.com/
Note: OEMs must fully validate any SPI flash device to ensure compatibility with their platforms. This should not be considered a complete list of SPI vendors and is not an indication of Intel approved devices or vendors. Please contact your preferred flash vendor directly to determine if they have a compatible device.
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RTC Design Guidelines—Intel ® Quark™ SoC X1000
12.0
RTC Design Guidelines
12.1
Real Time Clock General Introduction
12.1.1
Description
the Intel
®
Quark™ SoC X1000 contains a real time clock (RTC) with 256 bytes of battery-backed SRAM. The internal RTC module provides two key functions: keeping date and time and storing system data in its RAM when the system is powered down.
SoC RTC module defaults to using an internal clock source alternatively an external
oscillating source of 32.768 kHz connected on the RTCX1 and RTCX2 balls. Figure 42
shows the external circuitry that comprises the oscillator of SoC RTC.
The SoC uses a crystal circuit to generate a low-swing 32 kHz input sine wave. This input is amplified and driven back to the crystal circuit via the RTCX2 signal. Internal to the SoC, the RTCX1 signal is amplified to drive internal logic as well as generate a free running full swing clock output from the RTC for internal system use. This is illustrated
.
.
Figure 41.
RTCX1 and RTCX2 Relationship in SoC
Low-Swing 32.768kHz
Sine Wave Source
RTCX1
Internal
Oscillator
SUSCLK
SoC
Full-Swing 32.768kHz
Output Signal
12.2
12.2.1
Table 45.
Real Time Clock Signal Descriptions
Signal Groups
RTC Signals
Section
Group
Crystal Input 1
Crystal Input 2
Reset
Signals
RTCX1
RTCX2
RTCRSTB (I_1PAD)
Description
Crystal Input 1
Crystal Input 2
RTC Reset
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Table 45.
12.2.2
RTC Signals
Section
Status
Status
Status
Group Signals
S5_PG (I_2PAD)
RTC_EXT_CLKEN_B
(I_4_PAD)
S0_PG (I_5PAD)
Description
Platform S5 Power Good.
External RTC Clock source enable
Platform S0 Power Good
State Power Good Indicators
S5_PG is an indicator from the platform that the S5 input rails are at 90% of their nominal value. The use of a voltage regulator spec’ed to output a power good at the required level is optimal but a discrete circuit is also applicable.
S0_PG is an indicator from the platform that the S0 input rails are at 90% of their nominal value. The use of a voltage regulator spec’ed to output a power good at the required level is optimal but a discrete circuit is also applicable.
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12.3
12.3.1
Real Time Clock Topology Guidelines
RTC External Example Circuit
M
Figure 42.
Example External Circuitry for the SoC RTC
Schottky Diodes
VCC3P3_S5
1uF
R4
3.6K
R3
1K
C3
0.22F/5.5V
Vbatt
3V Lithium Battery
(Optional Use)
R2
240
32.768 KHz
Xtal
1uF C1
VCCRTC
0.1uF
C2
R1 10M
RTCRSTB
RTCX2
RTCX2
Table 46.
4.
5.
6.
Notes:
1.
2.
3.
7.
8.
9.
10.
11.
Reference designators are arbitrarily assigned.
VCC3P3_S5 is active whenever the system is plugged-in.
Vbatt is voltage provided by the battery and is optional.
VccRTC, RTCX1, and RTCX2 are Intel SoC pins.
VccRTC powers SoC RTC well.
RTCX1 is the input to the internal oscillator. RTCX1 can be driven by external clock generator to desired frequency.
RTCX2 is the feedback for the external crystal. When single ended external clock generator is used, this pin should be grounded.
R1 = 10M R2 = 240 R3 = 1K R4 = 3.6K
R5 = 20K
The exact capacitor values for C1 and C2 must be based on the crystal maker recommendations. Typical values for C1 and C2 are 18 pF, based on crystal load of 12.5 pF.
C3 = 0.22F/5.5V. Panasonic SD Series Super Cap,EEC-SDHD224V, ESR=75
.
Schottky Diodes (Black) are MBR0504T1G, Regular diodes are 1N4148, IN914 equivalents.
RTC Routing Guidelines
Parameter
Total Length
Resistor
Segment/Signal
Name
RTCX1
RTCX2
R1
Stackup
(MS/SL/DSL)
Units
Routing
Recommendation
MS mils
NA
1,000
M 10
Notes:
1.
Spacing, S > 15 mils (0.381 mm).
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12.3.2
12.3.3
General RTC Layout Considerations
The Intel
®
Quark™ SoC X1000 operates in a internally source RTC clock mode by default, the external RTC clock is required in cases where the SoC will be shutdown to
G3. In G3 the RTC is powered and the RTC clock is sourced from an 32kHz platform crystal. The use of an external RTC clock source allows the use of a more precise 32kHz clock.
Since the RTC circuit is very sensitive and requires highly accurate oscillation, reasonable care must be taken during layout and routing of the RTC circuit. Some recommendations are:
• Reduce trace capacitance by minimizing the RTC trace length. Intel SoC recommends a trace length less than 1 inch on each branch (from crystal’s terminal to RTCXn ball). Keep routing on the RTC circuit basic to simplify the trace length measurement and increase accuracy on calculating trace capacitances. Trace capacitance depends on the trace width and dielectric constant of the board’s material. On FR4, a 5-mil trace has approximately 3.3 pF per inch.
• Using a ground guard plane is highly recommended.
The oscillator VCC should be clean; use a filter, such as an RC low-pass, or a ferrite inductor.
External Capacitors
To maintain the RTC accuracy, the external capacitor values C to provide the manufacturer’s specified load capacitance (C
1
and C load
2 should be chosen
) for the crystal when combined with the parasitic capacitance of the trace, socket (if used), and package.
The following equation can be used to choose the external capacitance values:
C
[(C
1
= [(C
+ C in1
1
+ C in1
+ C trace1
+ C
) • (C
2
+ C in2
+ C
2
+ C in2
+ C trace2
)] / trace2
)] + C parasitic
Where:
C load
= Crystal’s load capacitance. This value can be obtained from Crystal’s specification.
Cin1, Cin2 = input capacitances at RTCX1, RTCX2 balls of SoC. These values can be obtained in the SoC data sheet.
C trace1
, C trace2
= Trace length capacitances measured from Crystal terminals to RTCX1, signal traces and the length of the traces. A typical value, based on a 5 mil wide trace and a ½ ounce copper pour, is approximately equal to:
C trace
= trace length • 4pF/inch
C parasitic
= Crystal’s parasitic capacitance. This capacitance is created by the existence of 2 electrode plates and the dielectric constant of the crystal blank inside the Crystal part. Refer to the crystal’s specification to obtain this value.
Ideally, C1, C2 can be chosen such that C1 = C2. Using the equation of C load above, the value of C1, C2 can be calculated to give the best accuracy (closest to 32.768 kHz) of the RTC circuit at room temperature. However, C2 can be chosen such that C2 > C1.
Then C1 can be trimmed to obtain the 32.768 kHz.
In certain conditions, both C1, C2 values can be shifted away from the theoretical values (calculated values from the above equation) to obtain the closest oscillation frequency to 32.768 kHz. When C1, C2 value are smaller then the theoretical values, the RTC oscillation frequency will be higher.
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Note:
12.4
The following example illustrates the use of the practical values C1, C2 in the case that theoretical values cannot guarantee the accuracy of the RTC in low temperature condition:
Example:
According to a required 12 pF load capacitance of a typical crystal that is used with the
SoC, the calculated value of C1 = C2 is 10 pF at room temperature (25 °C) to yield an
32.768 kHz oscillation.
At 0 °C the frequency stability of crystal gives –23 ppm (assumed that the circuit has 0 ppm at 25 °C). This makes the RTC circuit oscillate at 32.767246 kHz instead of 32.768 kHz.
If the values of C1, C2 are chosen to be 6.8 pF instead of 10 pF, this will make the RTC oscillate at higher frequency at room temperature (+23 ppm), but this configuration of
C1, C2 makes the circuit oscillate closer to 32.768 kHz at 0 °C. The 6.8 pF value of C1 and C2 is the practical value .
The temperature dependency of crystal frequency is a parabolic relationship (ppm / degree squared). The effect of changing crystal’s frequency when operating at 0 °C (25
°C below room temperature) is the same when operating at 50 °C (25 °C above room temperature). See crystal datasheet for more details.
RTC External Battery Connection
The RTC requires an external battery connection to maintain its functionality and its
RAM while SoC is not powered by the system.
Example batteries are: Duracell 2032, 2025, or 2016 (or equivalent), which can give many years of operation. Batteries are rated by storage capacity. The battery life can be calculated by dividing the capacity by the average current required. For example, if the battery storage capacity is 170 mAh (assumed usable) and the average current required is 6 µA, the battery life will be at least:
170,000 µAh / 6µA = 28,333 h = 3.2 years.
The voltage of the battery can affect the RTC accuracy. In general, when the battery voltage decays, the RTC accuracy also decreases.
The battery must be connected to SoC via an isolation Schottky diode circuit. The
Schottky diode circuit allows SoC RTC well to be powered by the battery when the system power is not available, but by the system power when it is available. To do this, the diodes are set to be reverse biased when the system power is not available.
Figure 43 is an example of a diode circuit that is used.
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Figure 43.
A Schottky Diode Circuit to Connect RTC External Battery
1.4V drop
VCC3P3_S5
0.5V drop
Schottky Diodes
R4
3.6K
R3
1K
C3
0.22F/5.5V
Vbatt
3V Lithium Battery
(Optional Use)
R2
240
The ESR limits the charge current and is negligible for the RTC input current.
The charge time is ~3-4 minutes but the Hold up time is ~6.7 hours.
1uF 0.1uF
VCCRTC
12.4.1
A standby power supply should be used in a mobile system to provide continuous power to the RTC when available, which will significantly increase the RTC battery life and thereby the RTC accuracy.
Using a rechargeable coin battery or a capacitor with a short projected discharged time can increase the risk of:
• unusable anti-replay blobs
RTC Holdup Calculation
shows Super Capacitor, C3, this is a Panasonic SD Series
Super Cap, value 0.22uF/5.5V. The Panasonic EEC-SDHD224V is used in this example circuit. The SDHD224V has a ESR of 75
The discharge time is calculated as follows;
T = -RC x ln(V/V0)
R: The RTC load = 3V/12uA
1
= 250000.
C: The Super Cap = 0.22F
Therefore RC = 55000
The discharge slope is based on a natural log, ln(V/V0) from 3.6V to 2V
V: 2V, minimum RTC operational voltage.
ln(V/V0) = ln (2/3.6) = -0.43825
Discharge time (T) = -55000 x -0.43825 = 24104 sec = ~6.7hours.
1. Estimated load at 12uA
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12.5
RTC External RTCRST# Circuit
Figure 44.
RTCRST# External Circuit for the SoC RTC
Schottky Diodes
VCC3P3_S5
R4
3.6K
R3
1K
C3
0.22F/5.5V
Vbatt
3V Lithium Battery
(Optional Use)
R2
240
1uF
1uF 0.1uF
VCCRTC
RTCRST#
Table 47.
SoC RTC requires some additional external circuitry. The RTCRST# signal is used to reset the RTC well. The external capacitor and the external resistor between RTCRST# and the RTC battery (VBAT) were selected to create an RC time delay, such that
RTCRST# will go high some time after the battery voltage is valid. The RC time delay should be in the range of 18 ms – 25 ms. When RTCRST# is asserted, bit 2
(RTC_PWR_STS) in the GEN_PMCON_3 (General PM Configuration 3) register is set to
1, and remains set until software clears it. As a result of this, when the system boots, the BIOS knows that the RTC battery has been removed.
The RTCRST# signal may also be used to detect a low battery voltage. RTCRST# will be asserted during a power up from G3 state if the battery voltage is below 2 V. This will set the RTC_PWR_STS bit as described above. If desired, BIOS may request that the user replace the battery.
This RTCRST# circuit is combined with the diode circuit (shown in Figure 43
) whose purpose is to allow the RTC well to be powered by the battery when the system power is not available.
Figure 44 is an example of this circuitry that is used in conjunction with
the external diode circuit.
RTC External RTCRST# Routing Guidelines
Parameter
Total Length
Resistor
Capacitor
Segment/Signal
Name
RTCRST#
R
C
Stackup
(MS/SL/DSL)
Units
Routing
Recommendation
MS mils
NA
8,000 k 10
NA uF 1
NOTES:
1.
2.
3.
4.
Impedance Target 50 ±15% for Microstrip.
Spacing, S > 15 mils (0.381 mm).
RC time delay between 18 ms-25 ms must be met.
Spacing, S > 15 mils (0.381 mm).
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12.6
RTC-Well Input Strap Requirements
All RTC-well inputs must be either pulled up to VCCRTC3P3 or pulled down to ground
while in the G3 state. RTCRST_B, when configured as shown in Figure 44
meets this requirement. This will prevent these nodes from floating in G3, and correspondingly will prevent I
CC
RTC leakage that can cause excessive coin-cell drain. The
RTC_EXT_CLK_EN_B input signal should also be configured with an external 10k pulldown, which selects the external RTC clock source, if operating from a battery in G3.
§ §
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Asynchronous Signals Design Guidelines—Intel ® Quark™ SoC X1000
13.0
Asynchronous Signals Design Guidelines
13.1
13.1.1
13.2
13.2.1
Asynchronous Signals General Introduction
Description
This section describes the topologies and layout recommendations for the asynchronous signals. Refer to the Intel
®
Quark SoC X1000 Datasheet for more details.
Asynchronous Signal Descriptions
Signal Groups
Table 48.
13.3
Warning:
Table 49.
Asynchronous Legacy Signal Group
Signal Name
GPIO[7:0]
Description
General Purpose IO configurable in direction.
Asynchronous Signals Topology Guidelines
This section describes topologies and layout recommendations for the legacy signals.
Although these signals toggle with relatively low frequency, most of them have very high-edge rates.
Inappropriate routing or lack of termination can seriously decrease signal quality and lead to electrical specification violations and even logical system failures. The following guidelines apply to all legacy signals described in this section.
• Watch for termination recommendations. If any of the signals that require platform termination are pulled-up to a voltage higher than VCCST then the reliability and power consumption of the SOC may be affected. Therefore, it is very important to follow the recommended pull-up voltage for these signals.
• The routing guidelines allow the asynchronous signals to be routed using microstrip using 50 ±15% characteristic trace impedance
• Changing reference plane is not recommended and may cause signal integrity degradation. In any case, if such routing can't be avoided, use stitching vias and bypass capacitors between the reference planes near the layer transition.
General trace spacing requirements (for 50 characteristic impedance traces) specified in the following table. W is trace width and S is the space between 2 adjacent traces.
Asynchronous Signal General Routing Guideline
Trace Type
Microstrip
Stackup
(MS/SL/DSL)
MS
Units mils
Trace Width (W) Minimum Spacing (S)
4 12
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13.4
General GPIO Topology Guidelines
This section describes the layout recommendations for GPIO signals [7:0].
Figure 45.
Example GPIO[7:0] Topology level shifted Guideline
SCHOTTKY_4P
ESD Diode
SoC
Breakout
L
A
L
B
Rs
CFIOHVTEW NO RCOMP
Figure 46.
Generic GPIO[7:0] Topology Guideline
L
C
SoC
L
D1
L
D2
Rs
L
D3
Connector
Breakout
L
A
L
B
Rs
L
C
Connector
CFIOHVTEW NO RCOMP
Table 50.
GPIO[7:0]l General Routing Guideline
Breakout
PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip / Stripline /
Dual Stripline)
Characteristic Impedance (Singleended)
Trace Width (w)
Trace Spacing(S2): Between GPIO
Signals
Trace Spacing(S3): Between GPIO and other signals
4 Layer
L
A
MS
4.2 mil
4.2 mil
4.2 mil
Trace Segment Length 0.5"
4 Layer
L
B
MS
4 Layer
L
C
MS
4 Layer
L
D1/
L
D2/
L
D3
MS
50 Ω +/- 15%
4.2 mil 4.2 mil
10 mil 10 mil
4.2 mil
10 mil
10 mil min = 0.2" max = 0.8"
10 mil min = 0.1" max = 2.5"
10 mil
0.25" max
Stub length Less than 1400 mils
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Number of vias
Rs
Reference Plane
2 via
33 ohm +/- 1%
Solid Ground Reference
§ §
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Platform Power Delivery Requirements—Intel ® Quark™ SoC X1000
14.0
Platform Power Delivery Requirements
Table 51.
This chapter provides the recommended way to power up the Intel
®
Quark™ SoC
X1000 from the platform. It is assumed the platform provides a single input voltage
(5v) from which we derive three primary platform voltages (1.0v, 3.3v, and 1.5v). Each of these primary platform voltages are split and subsequently enabled in a specific sequence to ensure proper SoC functioning.
The platform power rails can be categorized based on S5, S3 and S0 power domains on the Intel ® Quark™ SoC X1000.
Recommended Platform Power Delivery
Primary Platform
Voltage
3.3V
1.0V
1.5V
3.3V
1.0V
1.5V
Derivative
Voltage
V3P3_S5
V1P0_S5
V1P5_S5
V3P3_S3
V1P0_S3_IVR
V1P5_S3
Derived from Controlled by
Vin (5V)
Vin (5V)
Platform Power up
Supply: V3P3_S5
Vin (5V) Supply: V1P0_S5
SoC i/p: S5_PGOOD
V3P3_S5
V3P3_S3
SoC o/p: S3_3V3_EN
SoC internal PMU
V1P5_S5 SoC o/p: S3_1V5_EN
SoC i/p: S3_PGOOD
3.3V
1.0V
V3P3_S0
V1P0_S0
V3P3_S5
V1P0_S5
SoC o/p: S0_3V3_EN
SoC o/p: S0_1V0_EN
1.5V
V1P5_S0
SoC i/p: PG_V1P0_S0
V1P5_S5 SoC o/p: S0_1V5_EN
SoC i/p: S0_PGOOD
4.
5.
6.
Notes:
1.
2.
3.
RED: S5 power domain
GREEN: S3 power domain
BLUE: S0 power domain
SoC o/p: Output handshake signal from SoC
SoC i/p: Input handshake signal into the SoC
Internal PMU: On die power management unit
4
5
6
1
2
3
7
8
9
Power-up
Sequence
S5 is the first power domain to ramp up, then S3 and subsequently the S0 power domain. 4 voltage levels exist within each power domain namely 3.3V, 1.5V, 1.8V and
1.0V. The 3.3V, 1.5V and 1.0V power rails are powered from an external power source
(External to the Quark X1000 SoC on the platform). 1.8V on all 3 power domains are powered internally from on-die LDOs. V1P0_S3 is an exception which is powered from an internal on-chip LDO.
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All internal supply voltages are brought out of the SoC package and looped back-in on
the platform (Refer to OVOUT_<name> in Figure 47
). This allows the system designer to disconnect the internal LDO in certain cases and supply the rail with an external
illustrates the recommended platform power delivery.
Note:
Figure 47 is only a block diagram and should not be treated as schematic. Refer to the
Intel
®
Quark™ SoC X1000 reference design schematics for the full implementation.
Figure 47.
Intel
®
Galileo Platform Power Delivery
V3P3_S5
V1P5_S5 vin vout
TPS22920
V1P5_S0 on
RC-Delay
SO_1V5_EN
S0_PGOOD vin vout
TPS22920 on
V3P3_S0
S0_3V3_EN
OVOUT_1P05_S0 V1P05_S0_IVR
OVOUT_1P0_S3
VCC1P0_S3
OVOUT_1P0_S5
V1P0_S3_IVR
V1P0_S5_IVR
OVOUT_1P8_S0 V1P8_S0_IVR
OVOUT_1P8_S3 V1P8_S3_IVR
OVOUT_1P8_S5 V1P8_S5_IVR
V1P0_S5_PG
Lvl shift logic
PLATFORM POWER 5V
EN1
VIN1
PGOOD
VOUT1
V3P3_S5
EN2
VIN2
TPS652510
VOUT2
V1P0_S5
EN3
VIN3
VOUT3
V1P5_S5
V1P0_S5
V3P3_S5
V1P5_S5 vin vout
TPS22920 on
V1P0_S0
RC-Delay vin vout
TPS22920
SO_1V0_EN
PG_V1P0_S0
V3P3_S3 on vin vout
TPS22920
S3_3V3_EN
V1P5_S3 on
S3_1V5_EN
RC-Delay
S3_PGOOD
Intel® Quark
TM
SoC
X1000
The power-up sequence specified in Table 51
is described in detail with Figure 48 . At
each step after the S5_PG signal asserts, the Intel
®
Quark™ SoC X1000 internal power management block enables the subsequent power rails through a process of handshaking. These enable signals are utilized on the platform to control the FET switches which control the S3 and S0 power rails. Power good signals are needed by the Intel
®
Quark™ SoC X1000 power management unit at each power domain boundary crossing.
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Platform Power Delivery Requirements—Intel ® Quark™ SoC X1000
Figure 48.
Intel ® Quark™ SoC X1000 Power-up Sequence
Intel® Quark
TM
SoC X1000 rails (platform implementation may vary)
ALWAYS ON
(**when platform power available)
SUSPEND
(low power)
CORE
VCC3P3_S5
VCC1P0_S5
(Externally derived)
VCC1P8_S5
(internal-derived using SLDO)
VCC1P5_S5
S5_PG
3mS
VCC3P3_S3
VCC1P0_S3
(internal-derived using SLDO)
VCC1P8_S3
(internal-derived using SLDO)
VCC1P5_S3
S3_PG
4mS
VCC3P3_S0
VCC1P05_S0
(internal-derived using SLDO)
VCC1P8_S0
(internal-derived using SLDO)
VCC1P0_S0
VCC1P5_S0
S0_1P0_PG
S0_PG
Core/S0 Rails: 3; Suspend/S3 Rails: 2; S5 Rails: 3; RTC: 1:
§ §
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Platform Reset Considerations—Intel ® Quark™ SoC X1000
15.0
Platform Reset Considerations
15.1
15.1.1
15.2
15.2.1
Table 52.
Platform Reset General Introduction
Description
Platform reset signals is a group of reset signals that control power on sequence, power management, and provide proper reset to all components on the platform. This chapter provides detailed guideline on how to generate and use platform reset signal to ensure functionality of the platform.
Signal Description
Signal Groups
Signals listed in
are identified as platform reset signals from the SoC.
Platform Reset Signals
Group Signal Name Pin Description
S5_PGOOD
S3_PGOOD
PG_V1P0_S0
S0_PGOOD
Power
Management
Power
Management
DRAMPWROK
S0_1V0_EN
S0_1V5_EN
S0_3V3_EN
S3_1V5_EN
S3_3V3_EN
EC_PWRBTN_N
RESET_N
S5_PG
S3_PG
S0_1P0_PG
S0_PG
Platform S5 power is okay
Platform S3 power is okay
Platform S0 power for 1.0v is okay
Platform S0 power for 1.5 is okay
ODRAM_PWROK
S0_1V0_EN
S0_1V5_EN
S0_3V3_EN
S3_1V5_EN
S3_3V3_EN
PWR_BTN
RESET_BTN
DRAM Power OK
Voltage enable for S0 v1.0 rail
Voltage enable for S0 v1.5 rail
Voltage enable for S0 v3.3 rail
Voltage enable for S3 v1.5 rail
Voltage enable for S3 v3.3 rail
Power Button
Reset Button
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15.3
15.3.1
15.3.2
15.3.3
Note:
15.3.4
15.3.5
Note:
15.3.6
15.3.7
Additional Guidelines
S0_3V3_EN Usage Model
S0_3V3_EN is used primary to control platform V3P3 VR so that it will enter a more power efficient mode outside S0. It may also be used to power off all non-critical components outside the S0 state. This signal should be connected to a VR controller to enter low power mode.
S0_1V5_EN Usage Model
S0_1V5_EN is used to power off all non-critical 1.5V components when not in the S0 state.
S0_1V0_EN Usage Model
S0_1V0_EN is used to power off the 1.0v domain and other non-critical components outside the S0 state.
For the S0 state to be in a stable power state all S0 rail enables must be active, in addition to the S3 rail enables.
S3_3V3_EN Usage Model
S3_3V3_EN is used primary to control platform V3P3 VR so that it will enter a more power efficient mode in S4 or S5 state.
S3_1V5_EN Usage Model
S3_1V5_EN is used to power off all non-critical 1.5V components when in S4 or S5 state.
For the S3 state to be in a stable power state all S3 rail enables must be active.
PWRBTN# Usage Model
The Power Button signal (PWRBTN#) on the Intel
®
Quark™ SoC X1000 can be connected directly to the power button on the system’s front panel header. When system power button is pressed, PWRBTN# should be pulled low. The SoC has 2.5ms or more of internal debounce logic on this pin, external debouncing circuit is not required.
Alternatively where a front panel button is not required the PWRBTN can be tied low which results in the SoC auto booting once power is applied in S5.
RSTBTN# Usage Model
The Reset Button signal (RSTBTN#) on SoC can be connected directly to the reset button on the system’s front panel header. When system reset button is pressed,
RSTBTN# should be pulled low. The SoC has 2.6 ms of internal debounce logic on this pin, external debouncing circuit is not required. This button has several functions dependent on system state. If in S3 sleep a RSTBTN press will result in the SOC waking from S3 to S0. If in S0 a RSTBTN press will result in the SOC performing a WARM reset.
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Platform Reset Considerations—Intel ® Quark™ SoC X1000
15.3.8
Power-well Isolation Control Signal Requirements
15.3.9
platform_s5_pwrok Generation
The platform_s5_pwrok signal is generated from the platform regulator V1P5 or equivalent detection logic. The signal should be generated based on the v1p5 rail achieving 90% of its nominal value
Figure 49.
platform_s5_pwrok generation
VCC1P5_S5
1P5 VREG en platform_s5_pg
RC Delay
3P3_gd
POWER BRICK
3P3 VREG en
Tied on
VCC3P3_S5
15.3.10
platform_S3_pwrok Generation
The platform_s3_pwrok signal is generated from the platform power switched S3 V1P5 or equivalent detection logic. The signal should be generated based on the S3 v1p5 rail achieving 90% of its nominal value. The S3 v3p3 and v1p5 rails are enabled by SoC via the v3p3_s3_en and v1p5_s3_en sequence.
15.3.11
platform_S0_1P0_pwrok Generation
The platform_s0_1p0_pwrok signal is generated from the platform regulator S0 V1P0 or equivalent detection logic. The signal should be generated based on the S0 v1p0 rail achieving 90% of its nominal value. The v1p0 rail is enabled by SoC via the v1p0_s0_en.
15.3.12
platform_S0_1P5_pwrok Generation
The platform_s0_1p5_pwrok signal is generated from the platform power switched S0
V1P5 or equivalent detection logic. The signal should be generated based on the S0 v1p5 rail achieving 90% of its nominal value. The S0 v3p3 and v1p5 rails are enabled by SoC via the v3p3_s0_en and v1p5_s0_en sequence.
15.3.13
Glue Logic Device
Glue Logic Devices are available from various vendors to provide an ASIC component that integrates miscellaneous platform logic into a single chip.
Contact your preferred vendor for available glue logic solution.
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15.3.14
Additional Power Sequencing Considerations
It is possible that on rare occasions, wake events can cause the system to immediately wake after entering in S3 power state. In such circumstances it is possible that the SoC will generate the same duration pulse widths on the v3p3_s0_en, v1p5_s0_en and v1p0_s0_en as during normal cold boot. Care should be taken during the platform design to evaluate and account for such events in terms of VR design, power good circuitry design, and overall platform power sequencing in order to ensure timing specifications related to power sequencing are not violated.
15.3.15
Power Sequence Timing Diagram
Figure 50.
Power Sequence Timing
VCC3P3_S5
VCC1P5_S5
VCC1V8_S5
VCC1V0_S5
SLDO power good(internal)
At 75% platform_S5_pwrok
(VCC3P3_S5 @ 90%) negedge_pwr_btn/ auto start
S3_3V3_EN
S3_1V5_EN
VCC3P3_S3
VCC1P8_S3
VCC1P0_S3
VCC1P5_S3 platform_s3_pwrok
(VCC3P3_S3 @ 90%)
S0_3V3_EN
S0_1V5_EN
VCC3P3_S0
VCC1P8_S0
VCC1P5_S0 platform_s0_pwrok
(VCC3P3_S0 @ 90%)
S0_1V0_EN
VCC1P0_S0 platform_1P0_s0_pwrok
(VCC1P0_S0 @ 90%)
SLDO Ramp Time
PLL lock time
FET Ramp Time
SLDO Ramp Time
FET Ramp Time
2 nd
PLL Lock
FET Ramp Time
SLDO Ramp Time
FET Ramp Time
FET Ramp Time
§ §
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Critical Low Speed Signals Design Guidelines—Intel ® Quark™ SoC X1000
16.0
Critical Low Speed Signals Design Guidelines
16.1
16.1.1
16.2
16.2.1
Table 53.
Critical Low Speed Signals General Introduction
Description
Critical Low Speed Signals are identified as critical input signals from the Intel
®
Quark™ SoC X1000 that are low frequency but have huge impact to system functionality or stability. Glitches on these signals may cause system to behave in unpredicted manners or cause unpredicted system shutdown or reset. Although these are low speed signals in nature, glitches may be induced or coupled from nearby high speed signals. Therefore it is important to keep these signals clean from any potential sources of glitches on the platform.
Critical Low Speed Signal Descriptions
Signals Group
Signals listed in
below are identified as critical input signals from the Intel
®
Quark™ SoC X1000 that must be guaranteed glitch free all the time.
Critical Signals
Group Signal Name
RTC RTCRST_B
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
S5_PG
S3_PG
S0_1P0_PG
OSYSPWRGOOD
PWR_BTN
WAKE_B
Description
RTC Reset: When asserted, this signal resets register bits in the
RTC well.
Power OK: When asserted, PWROK is an indication to the SoC that all of its S5 power rails have been stable for 10 ms. S5_PG can be driven asynchronously.
Power OK: When asserted, indicates that power to the S3 power rails are stable.
Power OK: When asserted, indicates that power to the S0 1P0v power rail is stable.
Power OK: When asserted, indicates that power to the S0 1P5v power rail is stable.
Power Button: The Power Button will indicate to the system a request to go to S0. If the system is already in a sleep state S3, this signal will cause a wake event. If PWRBTN# is pressed for more than 4 seconds, this will cause an unconditional transition
(power button override) to the S5 state. Forced shutdown is only active in the S0 state.
PCI Express* Wake Event: Sideband wake signal on PCI
Express asserted by components requesting wake up.
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16.3
Table 54.
Table 55.
Additional Guidelines
All critical signals must stay away from potential glitch or noise sources on the platform. It is recommended to keep all critical signal traces a minimum of 15 mils away from any clock or high speed differential signals with > 4V/ns edge rate, to avoid glitches from crosstalk.
Critical Signals Routing Summary
Parameter
Spacing
Stackup
(MS/SL/DSL)
MS
Units mils
Routing
Recommendation
15mils
Experiment data shows that certain signals have shown high sensitivity to specific frequencies. Routing those signals near to the frequency source will increase the glitches due crosstalk. The relationship of each signals with the frequency it is sensitive to, is listed in
. Designer should try to avoid routing a signal next to the sensitive frequency and the harmonics of its sensitive frequency. If this cannot be avoided, it should be kept a minimal of 15 mils from the respective signal trace.
Frequency Sensitivity
Signal Name
PWR_BTN
WAKE_B
25 MHz
12.5 MHz
Frequency to Avoid
§ §
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Electromagnetic Interference—Intel ® Quark™ SoC X1000
17.0
17.1
17.1.1
17.2
Electromagnetic Interference
Electromagnetic Interference (EMI) General Introduction
Description
The main component of EMI is a radiated electromagnetic wave, which consists of both electric (E-fields) and magnetic (H-fields) waves traveling together and oriented perpendicular to each other. E-fields are created by voltage potentials while H-fields are created by current flow. If a dynamic E-field is present then there must be a corresponding dynamic H-field, and vice versa. Motherboards with fast processors will generate high frequency E and H fields from currents and voltages present in the component silicon and signal traces.
Prevention and containment minimize E and H field emissions from a system.
Prevention minimizes the ability of the motherboard to generate EMI fields.
Containment contains radiated energy within the chassis.
Careful consideration of board layout, trace routing and grounding may significantly reduce the motherboards radiated emissions and make the chassis design easier.
Exercising the System for EMC Testing
Computing platform regulatory testing utilizes software to exercise all parts of the computer thereby generating emissions to gauge EMC compliance. Regulatory standards provide general guidance for Information Technology Equipment (ITE) operating conditions including a description of the exercising software operation but not to the extent necessary to have repeatability across the industry.
Experimentation using a combination of different OEM and commercial exercisers have shown a significant deviation of the EMI signature on the same system. Key variables of the software have been identified that control the EMI signature. These variables are not addressed by the regulatory standard and are implemented at the discretion of the software developer. The attributes that directly impact the EMI signature are:
• Data Sequence: Write-Read-Erase sequence ensures data is not cached which creates period of inactivity.
• Data Pattern: Determines the spectral content as a function of the data-rate clock.
• File Size: Sets the size of the file on the data device where the data pattern is written and read from. This will indirectly impact the duty cycle of the write-readerase sequence and period.
• Block Size: Sets the size of the data block where the data is written and read from.
This will indirectly impact the duty cycle of the write-read-erase sequence and period.
Figure 51 is a time domain capture of the bus activity using each exerciser. While the
software interface is virtually identical for each exerciser, it is clear what is a occurring internally in the exerciser, changes the drive activity which directly correlates to EMI levels.edges. The higher the activity seen on the bus, the higher the EMI levels are.
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Figure 51.
Time Domain Capture of Exerciser Operation
It is recommended to use a write-read-erasure sequence with a random data pattern.
While a repeated pattern is very reproducible, it will produce far worse and unrealistic
EMI levels than a typical real-world application. Applying the video scrolling H pattern to data devices is considered a repeated pattern and is not required. The exercising software should be flexible to allow the user to manually set the file and block sizes.
The time between the write and read cycle is based on the file size. Smaller block sizes will cause higher bus and drive activity. It is recommended to set a very large file size with a very small block size to maximize emissions from the PC.
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Electromagnetic Interference—Intel ® Quark™ SoC X1000
17.3
EMI Source
17.3.1
Current Loop Radiation
Current loop radiation is formed by the forward current and return current. For example, the current loop of signals travelling on a microstrip line is shown in the following figure. The current traveling on the trace is the forward current. The current traveling on the ground plane is the return current. The forward and return currents then form a current loop in between the trace and ground plane. Current loops, like magnetic dipoles, emit signals. The emission intensity is proportional to the current strength and the loop area. Therefore, minimizing the loop area is a key to mitigate
EMI.
Two ways to keep the microstrip-line current loop area small:
• Keep the height of the dielectric in between the trace and ground plane as small as possible.
• Keep the length of the trace as short as possible. In other words, route the signals short.
Figure 52.
Current Loop Radiation of a Transmission Line
A differential line is a good example of current loop radiation cancellation. A differential line is composed of two adjacent traces. Therefore, the current loop from one trace is very similar to the loop from the other. Since the current traveling on these traces are in opposite direction. As a result, the emissions caused by these two loops cancel each other. Please note that the cancellation is maximum when forward and return currents are balanced. Unbalanced current levels induce common mode radiation introduced in
.
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Figure 53.
Radiation Cancellation of a Differential Line
17.3.2
Voltage Regulator Module Current Loop Radiation
The noise from voltage regulator module (VRM) is typically around 50~300MHz.The
two noise peaks at 125 and 250 MHz shown in Figure 54
are an example. VRM noise
can cause both signal integrity (SI) and EMI issues (see Figure 55 ) through the same or
different coupling paths. Besides the coupling paths elimination, the issues can be
resolved effectively by mitigating VRM noise from the source. Figure 56
shows a simplified VRM circuit. The VRM EMI noise can be detrimental when its harmonics coincide with the resonant frequency of the input decoupling path which encompasses input decoupling capacitors and the top and bottom transistors. A practical way to mitigate the VRM noise without sacrificing VR efficiency is to have minimal parasitic
PCB inductance of the current loop indicated above. Several good layout practices are listed in the followings: Have a solid ground plane immediately underneath the VRM circuit and connect the VRM ground to the solid ground plane through vias. These Vias should be placed close to the low-side FET.
• Place the decoupling capacitors very close to the top transistor. The ground pin of the capacitors should be connected to the solid ground plane right underneath.
• Use at least two decoupling capacitors to reduce overall parasitic inductance from the capacitors themselves.
• If transistors are placed at different layers, ground vias should be placed close to the phase node vias.
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Figure 54.
An Example of VR EMI Noise
VR
Figure 55.
VR Noise Can Result In Both SI and EMI Issues
Platform noise
Figure 56.
Simplified Voltage Regulator Module Circuit and VRM EMI Noise
It is also found that the EMI noise is correlated with the ringing at the phase node(Vx).
A way to mitigate the ringing amplitude is to slightly increase the gate resistance of Q1 and/or Q2. However, it should be aware that increasing gate resistance impacts power efficiency of the VRM circuit.
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Figure 57.
The Vx Ripples with/without Gate Resistors (Left: without gate resistor/
Right: with gate resistor)
17.3.3
Besides the 50 to 300MHz EMI noise, the hundreds kHz switching noise can result in signal integrity issues if the noise is coupled to IO nets in proximity. It is critical to trap the noise within the input loop and minimize the noise propagation. Several design methods can be tried to reduce the switching noise (ripple): increase the total input capacitance value, mix the power and Vss via at the phase node, and minimize the size of the phase noise.
Common Mode Radiation
Common mode radiation happens when current travels through an IO cable or when signals are coupled to a heat sink (heat spreader) or power/ground planes. Cable, metal planes, and heat sink then become antennas that radiate. If the antenna is electrically small, it can be an electric dipole (for example IO cable or emission below
300 MHz). Its radiation intensity is proportional to the length of the antenna and signal frequency. However, the intensity becomes the maximum when the signal frequency reaches the antenna resonant frequency. Heat sink radiation and power/ground plane resonances are examples. Heat sink radiation and power/ground plane resonances are catching more attention recently because of the increasing signal speed (frequency).
Another example of common mode radiation is due to the signal timing skew on a differential line. The skew causes the unbalance of the currents traveling on the traces.
As a result, a common mode current is induced and the emission becomes much higher. Besides the timing skew, any unbalance designs in the PCB including the nonhomogeneous PCB material such as FR-4 can result in common mode current on a differential pair. Therefore, differential routings, especially USB2, should follow the EMC design rules mentioned in the following sections.
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Figure 58.
Emission from a Differential line with Various Skews
17.4
17.4.1
EMI Optimization Guideline
Avoid Changing Referencing, Lack of Referencing, Voidcrossing, and Split-crossing
Lack of referencing, reference changing, void-crossing, and split-crossing shown are common practices in order to accommodate all signals and power networks. However, they cause much stronger radiation due to the greatly increased current loop area.
Avoid these layout practices.
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Figure 59.
Changing Referencing, Lack of Referencing, Void-crossing, and Split-crossing are Not Recommended
17.4.2
Avoid Signal Traces Too Close to the Edges of Planes
Signal traces routed too close to the edges of referencing planes excite edge radiations.
It is because the return current distribution on the referencing planes are terminated by the edges. For acceptable radiation have 10×H keep-out area. Edge-to-trace distance should be 10 times greater than then dielectric height (H).
Figure 60.
Signal Traces Should be away from Plane Edges
17.4.3
Avoid Unnecessary Traces Too Close to IO and Other Connectors
Signals couple to connectors more strongly while signal traces are routed too close to the connectors. The coupling signals then radiate through connectors and the attached cables. Increasing distance between traces and connectors can reduce coupling.
Therefore, a 10×H keep-out area should be applied to the connectors H is the dielectric height between signals traces and referencing planes.
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Figure 61.
Keep-out Zone Determined Around IO and Other Connectors
17.4.4
EMI Mitigation through Stitching and Decoupling Capacitors
EMI emission can be mitigated with capacitors, which create low-impedance paths for signals or noises to pass through. These paths could minimize current loop areas or change plane resonant frequencies.
It is important to understand the capacitor model and its relationship with impedance.
A simple capacitor model is a series of resistor (R), inductor(L), and capacitor(C).
Therefore, the impedance of a capacitor can be expressed by the following equation.
Z f = +
fL – ----------
The impedance is a function of frequency. It is lowest when the frequency is at
1 2 LC . This frequency is call the self-resonant frequency. Below this frequency, the impedance is dominated by the capacitor value. Above this frequency, the impedance is dominated by the inductor value. At this frequency, the impedance is determined by the resistor value. The self-resonant frequencies normally are below 100
MHz. As the signal and clock speeds are ever-increasing. The concerned emissions could reach above 100 MHz. The inductor impact is getting more critical. Choosing a capacitor with low inductance is important.
Figure 62.
Simple Capacitor Model and an Example of Capacitor Impedance
Two main EMI mitigation methods using capacitors are introduced in the followings.
They are stitching capacitor and decoupling capacitor.
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17.4.4.1
Stitching Capacitors
Stitching capacitors are used to create return current path for signal traces with different references. Using stitching capacitors for split-crossing is one example. The separated reference planes have different voltages. They are, therefore, not able to be merged. As a result, there is no low impedance path for the return currents. The current loop becomes large and unpredictable. Connecting one or two capacitors between the two planes could provide low impedance return paths. Therefore, the new current loop is controlled.
Figure 63.
Stitching Capacitors Could Create Low Impedance Path for Return Currents
Figure 64 shows an example of stitching capacitor impact on EMI radiation. The
simulated results show the different emissions of a microstrip line with a perfect referencing, a microstrip line with split-crossing, a split-crossing microstrip line with one stitching capacitor, and a split-crossing microstrip line with two stitching capacitors.It is observed that split-crossing results in much higher emission. Placing one stitching capacitor reduces emissions. Placing two stitching capacitors symmetrically to the trace greatly reduces EMI.
Stitching capacitors should be placed as close as possible to the troubled signal traces.
Figure 65 shows different emissions when the stitching capacitors are placed 1-mm and
2-mm away from the trace. To maximize stitching capacitor effect:
• Two capacitors placed symmetrically to the split-crossing trace show much better mitigation than one capacitor only.
• Capacitors should be placed as close as possible to the split-crossing trace.
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Figure 64.
Stitching Capacitors Mitigate EMI (Simulated Results)
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Figure 65.
Stitching Capacitors Should be Close to Traces
17.4.4.2
Decoupling Capacitors
Decoupling capacitors are used to mitigate the noise on power rails or planes. Noise sources on power rails or planes are mainly from voltage regulators and IC chipsets.
Decoupling capacitors connected between power and ground could create shorter return paths for the noise currents. In order to minimize return paths, place capacitors as close as possible to noise sources.
In “Decoupling Capacitors Locations” , option “b” is the best because the decoupling
capacitor is placed closest to the IC and the wider power rail has lower inductance.
“Decoupling Capacitors with Vias”
shows the via locations. Vias should be placed where the traces are decoupled prior to being routed. Locations “a” and “b” are acceptable.
Location “c” is not acceptable since the via is placed before the bypass capacitor.
Location “d” is poor since two capacitors are tied to one via (this is not a good practice). Location “e” is poor since two capacitors are tied to one via and the via is before the capacitor (the via should be on the other side of each capacitor).
Figure 66.
Decoupling Capacitors Locations
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Figure 67.
Decoupling Capacitors with Vias
Other noise sources are from the signal traces adjacent to power planes. Power plane could be considered as an antenna radiating noises coupled from these traces.
Populating decoupling capacitors around the planes is a way of mitigation.
Figure 68.
Decoupling Capacitors Around the Edges of Power Plane
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17.4.5
17.4.5.1
Common Mode Filter
Some IO signals are differential. Differential signals are robust to EMI unless the differential signals are unbalanced.
IO differential lines result in common mode radiation. Common mode filters are generally recommended for mitigating common mode radiation. They should be placed in series with differential lines and close to IO for maximum effect.
USB Common Mode Choke Recommendation
Intel recommends implementing a common-mode choke (CMC) footprint for each USB
2.0 pair. Please refer to Section 17.4.6
recommendations.
17.4.6
USB 2.0 Common Mode Chokes
Testing has shown that common mode chokes can provide required noise attenuation.
A design should include a common mode choke footprint to provide a stuffing option in the event the choke is needed to pass EMI testing.
Figure 69 shows the schematic of a
typical common mode choke and ESD suppression components. Place the choke as close as possible to the USB connector signal pins.
Figure 69.
USB 2.0 Common Mode Choke
Vcc
D+
D -
Common Mode
Choke
ESD Supression
Components
USB A
Connector
Common mode chokes distort full-speed and high-speed signal quality. As the common mode impedance increases, the distortion will increase, so you should test the effects of the common mode choke on full speed and high-speed signal quality. Common mode chokes with a target impedance of 80 to 90 at 100 MHz generally provide adequate noise attenuation.
Finding a common mode choke that meets the designer’s needs is a two-step process:
• Choose a part with the impedance value that provides the required noise attenuation. This is a function of the electrical and mechanical characteristics of the part chosen and the frequency and strength of the noise present on the USB traces that should be suppressed.
• After obtaining a part that gives passing EMI results, the second step is to test the effect this part has on signal quality. Higher impedance common mode chokes generally have a greater damaging effect on signal quality, so care must be used when increasing the impedance without doing thorough testing. Thorough testing
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• Further common mode choke information can be found on the high-speed USB
Platform Design Guides available at www.usb.org.
17.4.7
Spread Spectrum Clocking
Although clock noise is inherently narrow band in nature, there are cases where the clocks are deliberately modulated or “spread”. The most common reason for doing this is to reduce spectral peaks that might otherwise violate FCC and CE requirements for unintentional (EMI) radiation.
The spread spectrum clocking technique reduces radiated emissions by spreading the emissions over a wider frequency band. This band can be broadened, with subsequent reductions in the measured radiation levels, by slowly frequency modulating the clock over a few hundred kHz. Thus, instead of maintaining a constant system frequency,
SSC modulates the clock frequency/period along a predetermined path (i.e., modulation profile) with a predetermined modulation frequency. The modulation frequency is usually selected to be larger than 30 KHz (above the audio band) while small enough not to upset the PC system’s timings.
Figure 70.
Demonstration of Spread Spectrum Clocking (SSC)
H ighest peak
non-SSC
SSC
of f nom f nom
Although the spread spectrum clocking (SSC) technique has been demonstrated to reduce peak radiation by approximately 8 dB and are widely applied in clocking system, clocks are still key radiation sources that cause EMI. Designers must not assume SSC clocking will eliminate EMI problems especially if the technique is not implemented correctly.
Radiated emissions are typically confined in a narrow band centered around clock frequency harmonics. By uniformly distributing the radiation over a band of a few MHz, regulatory measurement levels (in a 120 kHz bandwidth at frequencies below 1 GHz and in a 1 MHz bandwidth at frequencies above 1 GHz) will be reduced.
To conserve the minimum period requirement for bus timing, the SSC clock is modulated between f nom
and ( )f nom
where f nom percentage of f nom
.
1 is the nominal frequency for a constant-frequency clock; specifies the total amount of spreading as a relative
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The frequency modulation in the time-domain results in a frequency-domain energy redistribution of the constant-frequency clock harmonics. The shape of the spectral energy distribution of the SSC is determined by the time-domain modulation profile, while the energy distribution width is determined be the modulation amount ( ). The
the corresponding nominal frequency (+0% / -0.5%). The width of its spectral distribution is between the -3 dB roll-off points. The ratio of this width to the fundamental frequency cannot exceed 0.5%. The total power can be estimated by measuring the power density and integrating over the frequency of interest to obtain total power. Normally, clock signals are “down-spread”, that is, modulated so that all the sideband power is lower than the original center frequency. This prevents “overclocking”, or running clocks higher than specified, a condition that might cause a system to hang.
17.4.8
Signal Scrambling
Most EMI problems in electronic systems can be attributed to repetitive signals. In high-speed communications these repetitive signals are not limited to the clocks. For instance, data that is periodic itself can lead to an EMI problem. To minimize EMI risk due to such events, every character, except for those encoded into special symbols (K codes), and the characters that are within the training sequences are scrambled. In this way the repetitive nature of data such as 'H' patterns, as dictated by the FCC for testing of video interfaces, do not exhibit an increase in EMI over random data. Additional information on the specific scrambling algorithm used can be found in technology specifications, e.g, PCI Express base specification.
Figure 71 shows a comparison of a 100 MHz 50% duty cycle clock unscrambled and
after getting scrambled. The first harmonics show benefit from scrambling, but higher order harmonics are equivalent to the scrambled amplitudes. In fact, a scrambled clock can be worse in terms of impact due to the broadband nature of the signal versus the discrete nature of the unscrambled clock. This is probably more of a concern for RF interference in radio channels than for EMI compliance.
Figure 71.
Spectral Comparison of a Clock Scrambled vs. Unscrambled
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17.4.9
Memory Down
Memory down PCB layout may be challenging to minimize EMI/RFI. Intel recommends the following guidance:
• Place DRAMs closest to CPU.
• Clocks should be at least 3X the trace width away from other traces.
• Solid ground reference to clock, DQ, and DQS.
• Minimize the number of layer transition. There should be at least one ground via nearby each transition.
• No crossing splits (slots and voids).
• No clustered signal vias. They create slots.
• All the traces should be away from the edges of ground planes at least 20X the separation distance between the routing layer and its reference plane.
• IO connector should be at least 1 inch away from clock, DQ, and DQS.
for more detail of topology recommendations.
Note:
17.4.9.1
Layer Transition
Layer transition is not avoidable but PCB designers should minimize the number of transitions. Microstrip lines are used for CPU break-out and DRAM fan-in. PCB designer should also minimize the length of microstrip lines. Therefore, one transition happens close to CPU and one happens close to DRAM. In addition, for each transition, there should be at least one ground via nearby to maintain the low impedance of return current path. For differential signal routing, the ground via placement should be symmetry (See
Figure 72.
Ground Vias Placement
17.4.9.2
Clustered Signal Vias
Clustered signal vias should be avoided. There will be many vias for layer transitions.
PCB designer should avoid clustered signal vias. Clustered signal vias will create long open slots. Signals such as CLK can cross over these slots. Crossing slot results in high return current impedance and induces higher EMI/RFI radiation. To avoid clustered signal vias, one can insert a ground via every few signal vias.
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17.4.10
Cable/Adaptor Shielding
During EMI measurement, one may find some EMI violations are from the IOs such as
USB and HDMI. Intel recommend check the cable/adaptor shielding quality before
implementing a PCB solution, common mode choke for example. Figure 73
shows an example. A mini-HDMI adaptor was used during the EMI measurement. HDMI clock radiated strongly because the adaptor is not well shielded.
Figure 73.
Cable/Adaptor Shielding Impacts EMI Significantly
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17.5
Table 56.
Design Checklist Items
This section provides a checklist that should be reviewed during the design process.
This checklist has been developed over time and experience to reduce the possibility of unwanted emissions. The checklist is shown below. Not every suggestion is 100% effective; attention to appropriate items can help reduce EMI. The design and layout of the board must be reviewed by the appropriate EMC engineer assigned to the project prior to committing to fabrication.
Component Placement Review Checklist
ITEM
NO.
DESCRIPTION
169-1
169-2
169-3
169-4
Clock synthesizers, crystals, oscillators, microprocessor chips and other VLSI packages have been placed in the center of the board, away from board edges, I/O connectors, plane splits and other board mounted connectors to minimize radiation from the board.
Components using the same clock have been placed close to each other and the clock source to minimize clock trace lengths.
Filter components have been placed adjacent to the pin they are filtering on
I/O connectors.
For non-differential clocks, provisions have been made for series termination of clock traces at the source to minimize ringing.
Y/N
Table 57.
General Routing Review Checklist
ITEM
NO.
DESCRIPTION
170-1
170-2
170-3
170-4
170-5
170-6
170-7
170-8
170-9
170-10
170-11
Board stack-up designed to insure that all clocks and high-speed (> 1 MHz) traces are routed in layers adjacent to power or ground planes.
Power planes have been recessed from the edge of the board.
Clock traces have been laid out first and kept as short as possible, consistent with the need for matched clock trace lengths in the clock nets.
Clock and High-Speed traces do not change layers and do not cross breaks in power or ground planes. Stitching capacitors must be used in areas were reference breaks are unavoidable.
Clock and High-Speed traces have been kept away from board edges and traces leading to connectors (internal or external connections).
Clock and High-Speed differential traces have been laid out to minimize length, consistent with the need for matched trace lengths to minimize signal skew.
Do not route traces under clock generating circuits or other large high speed devices.
Ground pads with the same footprint as the part have been provided on the component side of the board away from oscillators or clocks. These ground pads are tied to the ground plane(s) of the board with multiple vias.
Provisions have been made for bonding the board ground system to the chassis at multiple points. The best locations are at connectors and noise sources (clocks, microprocessors, etc.).
Provisions have been made for grounding the heat plate or heat sink on the SOC(if applied) to the board ground structure with a maximum spacing between ground points of 375 mils
(9.525 mm); 10 .
Contiguous memory referencing topology must be maintained.
Y/N
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Table 58.
I/O Routing Review Checklist
ITEM
NO.
171-1
171-2
171-3
DESCRIPTION
All I/O connectors have been provided with a low impedance bond to chassis for their shield structure.
All non-ground nets routed externally, should have a filter present.
I/O connector traces route to ESD protection before any other device.
Y/N
Table 59.
Decoupling/Filtering Review Checklist
ITEM
NO.
DESCRIPTION
172-1
172-2
172-3
172-4
SMT bypass capacitors are connected directly to power and ground planes with minimum trace length between the part and via.
Bypass capacitor values have been selected to insure minimum impedance in the frequency range(s) of interest.
Filter capacitors (line to ground) have been provided a low impedance path to chassis as close to the capacitor as possible.
All pins on audio connectors have been filtered with both line to ground capacitors and series inductors and/or ferrite beads with the capacitor placed between the inductor/bead and the circuits in the system. These filter elements have been located at the I/O connector.
Y/N
§ §
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18.0
18.1
18.1.1
Electrostatic Discharge (ESD)
Electrostatic Discharge (ESD) General Introduction
Description
All electronic equipment that is sold into the European Union and mutually recognized countries, must possess the CE mark which designates it has passed a required set of test standards; these test requirements include system testing for ESD protection. The purpose of the ESD test is to demonstrate that a system can withstand static discharges encountered in normal handling and system operation. It is important to emphasize designing for ESD in the early project stages help reduce costly and time consuming debug and design changes late in the development cycle.
Besides standard regulatory requirements for system-level ESD, an emerging threat to component reliability and quality has been the direct and indirect discharge of ESD to the signals and pins of user accessible I/O interfaces; hot-plug. Traditional silicon level
ESD protection, meant to handle JEDEC and ESDA procedures, may not be able to respond to the 200ps to 1ns high inrush current of an IEC 61000-4-2 ESD type event.
Depending on the ESD characteristics and level encountered, the failure mode of semiconductors will behave and occur differently. Outside the instantaneous logic error or catastrophic failure, repetitive ESD stress may produce degradation of failures over time and is referred to as latent ESD defects. This occurs when an ESD pulse is not strong enough to destroy a device but alternatively causes undetected degradation.
Although the device may suffer this degradation, it may still function within data sheet parameters. A device can be subjected to numerous weak ESD pulses, with each one further degrading a device before it succumbs to a noticeable failure. There is no known practical methodology able to screen for devices with latent defects.
The IEC 61000-4-2 ESD pulse is a transient with a very fast rising edge. The IEC
61000-4-2 specification defines the time domain waveform of the ESD pulse. The risetime of the waveform is between 0.7 ns to 1 ns with a specified peak current of
3.75 A/kV. Additional current waveform requirements are 2 A/kV at 30 ns and 1 A/kV at
60 ns.
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Figure 74.
IEC 61000-4-2 ESD Waveform
Intel ® Quark™ SoC X1000—Electrostatic Discharge (ESD)
18.1.2
Reference Specifications
18.2
IEC 61000-4-2
Title Location http://www.iec.ch/
ESD Protection
Selection criteria for discreet ESD protection devices must include consideration for the electrical constraints of the interface needing protection. Many discreet semiconductor
ESD manufacturers now manufacturer devices for specific low- and high-speed interfaces.
When considering an ESD protection device, it is recommended to select a device with the highest rating against IEC 61000-4-2 air and contact discharge. Typically, the device should be able to withstand a minimum air discharge of ±15 kV and a contact discharge of ±8 kV. Clamping or holding voltage is another parameter that must be selected based on the EOS (Electrical Over Stress) rating of the interface. The lower the clamping voltage rating, the less residual energy will couple to the interface. As signaling BW increases, capacitive loading becomes a serious concern when placing a device on a high-speed interface. The maximum capacitive loading must be considered as it relates to line-to-line and line-to-ground loading. Many devices are being designed to work in the sub-pF range to handle the lower load requirements of high-speed interfaces.
ESD device selection is summarized as:
1) Can withstand IEC ESD levels
2) Determine maximum clamping voltage before EOS
3) Determine maximum capacitive loading allowed
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18.2.1
ESD Ground-Fill
Reducing sensitivity to Electrostatic Discharge (ESD) to ensure Intel products comply with ESD standards can be a time and cost intensive effort. This section recommends changes to the printed circuit board design that will reduce ESD sensitivity by implementing a low impedance ESD current path to ground, thereby, reducing the coupling to sensitive circuitry.
18.2.2
Ground-Fill Background
The premise of system ESD is that the discharge produces a surge through the chassis that induces voltage and current fields within the system. The induced fields produce negative effects to the board and components. The strength of the field coupling is limited by the ESD spectral content, the chassis material thickness and skin depth, size of coupled object, and proximity to the source. The coupling mechanism is a product of mutual inductance and capacitance shown in
Figure 75 . The energy is high-pass filtered
according to the dimensions of the victim as expressed in equations (1).
Figure 75.
Mutual L and C (Lm, Cm) Coupling
The induced voltage can be express as (1):
V
2
V
1
1 k 2 jk sin cos
sin
0
/( 2 is the ¼
λ
0
)
It is therefore expected that short and thin transmission lines couple very little energy from the chassis discharge, while larger structures like a heatsink, packages, long and thick power traces will couple the bulk of the energy. However, as signal noise margins have shrunk over time, it does not take very much induced noise to disrupt these signals. The area of the chassis that historically has high ESD coupling is the I/O area due to the many penetrations in the chassis necessary to allow the I/O to connect to peripherals. How well these I/O connections are RF bridged, directly impacts the strength of the coupled noise. Along with good I/O shield ground connections, printed circuit board grounding has been heavily depended on to dampen/reduce the coupled energy.
It is the intention to use the naturally occurring coupling to dampen the ESD energy at the most sensitive I/O area through the creation of an electrical large ground fill structure. A metal ground shape will act as a low-pass filter which effectively lowers the
Q of coupled circuits. The thickness of the ground fill is required to be greater than the calculated skin depth otherwise currents will form on both sides of the plane. The skin depth can be calculated in the following expression:
1
f
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To dampen the ESD energy it will be necessary to create the ground fill large enough to create a strong mutual coupling that has low enough impedance where the energy can be directed to ground. The results would be a drastic reduction in trace coupled noise.
Ground-Fill Procedural Recommendations:
This section describes the step-by-step process used to design an effective ESD ground shape for ESD protection using an example design.
1. Locate the ground shape at the input/output (I.O.) edge of the board on all layers except the ground layer, which should be a solid layer with no spits. Ground shape is highlighted in yellow.
Figure 76.
Ground Shape Along the I/O Edge of the Board
18.2.3
18.2.4
2. The ground shape should be continuous along the edge, outside of any traces. Keep the gap between the ground shape and other shapes or traces at least 20 mils. The minimum shape neck width is 50 mils.
3. Ideally, the ground shape on each layer should connect to at least two mounting holes for noise current to return to the chassis. If the ground shape cannot connect to the mounting holes on every layer, then connections to the mounting holes on at least one layer besides the ground layer should be sufficient, assuming the vertical stitching is ample.
4. The ground shape is useless without proper vertical stitching to the ground layer.
Connector holes can be considered stitching vias. Add vias throughout the length of the ground shape, no more than 300 mils apart, close to the board’s edge.
USB ESD Diode Recommendation
Intel recommends placing ESD protection devices for each USB 2.0 data pair. Selection of USB 2.0 ESD diode should be particularly careful and should be different due to
different speeds. Please refer to Section 18.3.1
for USB 2.0 for specific ESD diode
recommendation.
Series RC Filters
Conventionally ESD protection circuits are composed with ESD diodes or varistors.
These non-linear components are activated typically at high voltage (>10 V) to guide injected ESD current from sensitive parts such as ICs. They are very effective when the
ESD noise is injected directly into sensitive parts and signal lines. However, when the
ESD noise is injected into system ground and/or chassis, the capacitively/inductively
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Electrostatic Discharge (ESD)—Intel ® Quark™ SoC X1000 coupled ESD noises show alternative behaviors. These noises typically have lower voltage level (<10 V). They do not activate the aforementioned ESD protection circuits, such as ESD diode, but are still capable of upsetting the system. Therefore, they may have very limited effects against such ESD events.
A series RC filter may be applied sensitive asynchronous nets to enhance the system robustness under such circumstances. This filter can reject high-frequency components in injected ESD noise even when ESD diodes are not activated. The peak voltage and current may be significantly reduced. Due to the low-pass nature of this filter, Intel does not recommend applying this filter to high-speed links. This filter may degrade signal integrity of high speed signaling.
The schematic of this filter is shown in Figure 77
. It is a combination of series capacitors and resistors, shunted from the signal line to the ground. Intel recommends the component values of R=10 and C=100 nF for a 50 transmission line. The
frequency response of this filter is depicted in Figure 78
. The first pole can be found around 10 KHz, while the knee point is around 100 MHz. This suppresses highfrequency components of ESD noise with negligible impacts to asynchronous signaling.
Intel’s recommendation provides the typical value as a starting point. The components value may be adjusted accordingly to meet pin/signal requirements. It is noted that this filter needs to be placed within 100 mil form the victims (sensitive IC pins) as possible, to ensure the protection effectiveness.
Figure 77.
Series RC Filter for ESD Mitigation on Asynchronous Nets
Figure 78.
Frequency Response of The Series RC Filter
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The effectiveness of this series RC-filter is shown in Figure 79
. The magnitude of the sharp peak is effectively reduced by 75% with the series RC filter. The filter has significant impacts on ESD robustness, since this sharp peak contains huge amounts of high-frequency components and is typically the origination of most problematic symptoms in the system. This filter can also suppress the ringing of ESD noise on the transmission line. Typically asynchronous nets are terminated with small capacitance instead of 50 load. This causes impedance mismatch and thus ringing, especially for long traces. Ringing contains high-frequency components and increases local peakvoltage. It may degrade ESD robustness of the system. It has been demonstrated in
Figure 79 that the ringing is significantly reduced with the series RC filter.
The impact of the series RC filter to signal integrity is analyzed in Figure 80
. The rising and falling edges of the signal remain relatively fast with the presence of the series RC filter. The rising time is about 2.84 ns, measured from 30% to 70% of the signal level.
This is sufficiently fast for most of asynchronous nets. One drawback of this filter is that the duration required to reach 99% of the signal level is about 10 s. However, for operation of typical digital circuits, this has negligible impacts because reaching 99% of the signal level is not required.
Figure 79.
ESD Noise Suppression Using Series RC Filters
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Figure 80.
Signal Integrity Analysis With Series RC Filters
18.2.5
Sensitive Nets
Understanding the sensitivity of each signal nets to ESD noise may be very helpful for designing and debugging a system for ESD. Certain nets on the platform may have higher sensitivity to ESD noise and have severe impacts to the system. They need extra care in circuit layout. The aforementioned ESD protection circuits may also be populated for such nets to ensure the ESD robustness of the system. It is critical to identify such sensitive nets among hundreds of nets on the platform and narrow down the potential victims to ESD injections. This significantly reduces the required time and cost to solve ESD-related issues.
A test approach to assess net sensitivities on Intel platforms has been developed. In this approach, Transmission line pulser (TLP) is employed to generate a sharp and short pulse to emulate ESD noise. Rising time and pulse width of this pulse are typically less than 5 ns and 50 ns, respectively. It is injected into the system through a TLP probe that directly touch the net under test with ohmic contact, as shown in
commonly-used ESD guns that have large unshielded tip and chassis, the TLP probe is shielded to the very tip and has very limited coupling to proximity nets. This approach focuses on one single net and eliminates the possibilities of stimulating proximity nets.
On the contrast, using ESD guns to investigate net sensitivity may be quite misleading.
Direct-zapping using ESD guns may stimulate proximity nets and make it difficult to isolate the sensitivity from these proximity nets.
The tested sensitive nets are listed in
Table 60 . The typical symptoms when these nets
are upset are also included. This may be helpful for victim identifying during system debugging.
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Figure 81.
Circuit Diagram of Direct Injection Method
Table 60.
18.3
18.3.1
Tested Sensitive Nets
Net Name
Rtc_Rst
25M Xtal_Out platform_s5_pwrok
Dram_Rst# platform_s3_pwrok platform_s0_1p0_pwrok platform_s0_1P5_pwrok
From
Xtal
Xtal
PM
CPU
PM
PM
PM
To
SOC
SOC
SOC
DDR3
SOC
SOC
SOC
Reboot
Reboot
Reboot
Reboot
Reboot
Reboot
Reboot
Typical Symptoms
USB ESD Component Selection Guidelines
USB 2.0 ESD Protection
USB components and ICs are heavily subjected to frequent human contact due to its hot plugging usage model nature where there is a high frequency of insertion and removal of various USB devices from the USB ports. As a result, USB ports are easily exposed to ESD strikes from the human body that can destroy both the USB host and devices on the platform. ESD discharges from human contact could easily go up to
~35kV under extreme cases; therefore USB ports need to be protected.
There are currently a vast variety of ESD protection devices that are readily available in the market such as Metal Oxide Varistors (MOVs), Zener Diode, Transient Voltage
Suppressor (TVS), Polymer devices and dual rail clamp diodes. Classic USB (1.0/1.1) provided ESD suppression using in line ferrites and capacitors that formed a low pass filter. This technique doesn’t work for USB 2.0 due to the much higher signal rate of high-speed data. With 480Mbps of data rate, USB 2.0 is very sensitive to parasitic capacitance in it’s signal path. A tiny amount of parasitic capacitance in the pF range could distort USB signal, possibly causing the USB signal to fail and devices not working properly. In order to meet the stringent requirement on device capacitive load, the Dual
Rail Clamp Diodes, which have the lowest capacitance among the ESD protection devices, is found to be the best option for USB 2.0 ESD protection.
circuitry of a dual rail clamp diode.
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Figure 82.
USB 2.0 ESD Protection Devices
+ 5 V
D i o d e
D i o d e
+ -
D u a l R a i l C l a m p
D i o d e / D i o d e A r r a y
Figure 83.
Typical Integrated Diode Array Package
Proper placement of any ESD protection device is on the data lines between the
common mode choke and the USB connector data pins as shown in Figure 84
. The ESD protection devices should be placed as close to the USB connector as possible so that when ESD strikes occur, the discharges can be quickly absorbed or diverted to the ground/power plane before it is coupled to another signal path nearby. Proper placement of ESD protection device can improve the effectiveness of protecting the system against ESD strikes. Other types of low-capacitance ESD protection devices may work as well but were not investigated. As with the common mode choke solution, the Dual Rail Clamp Diode ESD protection device is needed.
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Figure 84.
Layout Example of USB 2.0 with ESD Diode Array
Close To Port or Connector
Note:
18.3.2
USBP
USBN
Diode
Array
Common
Mode Choke
Using ESD protection devices with higher parasitic capacitance would impact the
USB2.0 signal quality and thus limit the routing solution space of USB.
Further ESD information is detailed in the high speed USB Platform Design Guides available at www.usb.org/developers/docs.html
Recommended characteristics of an ideal ESD Protection Diode for USB2.0 are:
• Able to withstand at least 8kV of ESD strikes, complying to IEC 61000-4-2 standard.
• Low Capacitance, <2pF to minimize signal distortion at high speed data rate.
• Fast response time to protect from the fast rise time of ESD surge pulses.
• Low Leakage Current to minimize static power consumption.
• Integrated and reduced package dimension for better real estate and smaller parasitic package effect.
• High reliability -Robustness to drive and absorb repetitive ESD conditions without damage.
USB 2.0 ESD Protection Diode Vendors
ESD suppression is always recommended by Intel. However Intel does not recommend a specific part/device or circuit for ESD suppression because each solution is board/ chassis/usage model specific.The following vendors manufacture ESD protection Diode for USB2.0 which conform to the IEC 61000-4-2 standard. Please contact ESD protection device vendors for more specific details on devices availability, packaging option, how to place and optimize ESD, and datasheet.
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CalMicro:
ONSemi: http://www.calmicro.com
http://www.onsemi.com
Philips: http://www.philips.com
Protek Devices: http://www.protekdevices.com
SEMTECH:
STMicro: http://www.semtech.com
http://www.st.com
Note: This is not an extensive list. There may be others. Please check with your preferred vendor to determine if a compatible device is available.
Figure 85.
Differential S-parameters from Ceramic 1-line, Si 4-line and Si 6-line
ESD Protection Devices.
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18.4
Table 61.
Design Checklist Items
This section provides a checklist that should be reviewed during the design process.
This checklist has been developed over time and experience to reduce the possibility of unwanted ESD risk. The checklist is shown below. Not every suggestion is 100% effective; attention to appropriate items can help reduce ESD risk. The design and layout of the board must be reviewed by the appropriate ESD engineer assigned to the project prior to committing to fabrication.
ESD Checklist
ITEM
NO.
173-1
173-2
173-3
DESCRIPTION
All hot-plug interfaces, should have ESD protection present.
Implement a ground shape continuous along the board edge, outside of any traces. Keep the gap between the ground shape and other shapes or traces at least 20 mils. The minimum shape neck width is 50 mils. The minimum fill area should be 20% of the connector footprint under each connector.
Add stitching vias throughout the length of the ground shape, no more than 300 mils apart, close to the board’s edge (connector holes can be considered stitching vias).
Y/N
§ §
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Platform Debug and Test Hooks—Intel ® Quark™ SoC X1000
19.0
19.1
19.1.1
19.2
19.2.1
19.3
19.3.1
Platform Debug and Test Hooks
Platform Debug and Test Hooks General Introduction
Description
Intel is committed to reducing debug time and cost for OEMs and system integrators.
Many debug features and test hooks can be designed into the platform to help reduce these factors. The following section provides an overview of the Intel
®
X1000 debug and test hooks.
Quark™ SoC
Platform Debug Port
JTAG Probe - The Intel ®
Intel ®
Merged XDP connector.
Quark™ SoC X1000 uses this option to impact the nature of
Quark™ SoC X1000-based designs where there is no room to support a 60-pin
• Keep Out Zone (KOZ) is required around processor.
• JTAG routing on the platform is required.
• Provides access to SoC JTAG signals, processor configuration signals and others.
• Provides access to SoC test interface signals. A Logic Analyzer (LA) connector footprint is not required.
Signal Routing Guidelines
JTAG signal routing topology requirements are different from previous designs.
Guidelines for routing the JTAG pins can be found in the Intel
Platform - Debug Port Design Guide.
® Quark™ SoC X1000
JTAG Boundary Scan
The SoC includes a JTAG (TAP) port compatible with the IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1 Specification . The TAP controller is accessed serially through the five pins TCK, TMS, TDI, TDO, and TRST_B#. Additionally routing the PRDY_B and PREQ_B to the header would be advantageous from a debug perspective.
TMS, TDI and TDO operate synchronously with TCK which is independent of all other clock within the SOC. TRST_B#, per the specification, is an optional signal. This 5-pin interface can be used for test and debug purposes. System board interconnects can be
DC tested using the boundary scan logic in pads.
Terminating Unused JTAG Signals
When unused, all JTAG pins should be pulled according to the following table.
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Table 62.
19.4
19.4.1
JTAG PullUp / PullDown Requirements
Pin Direction
TCK
TDI
TMS
TRST_B
TDO
PREQ_B
PRDY_B
Input
Input
Input
Input
Output
Input
Output
PullUp/PullDowns
Internal 20K Pull Down
Internal 20K Pull Up
Internal 20K Pull Up
Internal 20K Pull Up
Internal 1K Pull Up
Internal 20K Pull Up
None
Additional Debug Support Guidelines
Test Points Requirements
Intel recommends users at least provide through-hole vias in a location that is probe accessible (avoid location that is blocked by thermal solutions or other mechanical components) and/or pull-up/pull-down resistors, for all the test points so that Intel would be able to access them when debug by Intel is required.
These test points are for debug and validation purposes, when adding test points effort must ensure they are not at the detriment of signal integrity.
§ §
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Design for Testability (DFT)—Intel ® Quark™ SoC X1000
20.0
20.1
20.1.1
20.1.2
Design for Testability (DFT)
DFT General Introduction
Description
This section provides guidelines for implementing Design for Testability (DFT) on this platform for supporting customer to define their DFT into their product in order to maximize test coverage in manufacturing tests.
All interfaces will support a minimum of one test bead per signal and a maximum of two test beads per signal. When implementing DFT, it is recommended to use existing vias, pads or pins wherever possible. If existing vias or pads can not be used, they may be added but the total number of vias specified for each interface can not be exceeded.
Reference Documents
20.2
VREG Controller’s data sheet
Intel ® Quark SoC X1000 Datasheet
Title Location
TBD https://communities.intel.com/ community/makers/ documentation/ quarkdocuments
DFT Configuration, Connectivity, Block Diagram
DFT probe points can be placed anywhere on the trace. It is preferred to place test beads directly on the trace or vias. However, if beads can not be placed directly on the trace, the stub to the bead should be less than 50 mils (1.27 mm), shown in
Test beads for differential signals should be matched on the differential pair within ±5 mils. If required, it is ok to break the differential pair spacing requirements for a short route in order to place both test beads in a matched location.
Example is shown in Figure 87 . Also, it is recommended to place test beads at the end
or beginning of a trace in order to avoid signal reflection/refraction.
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Figure 86.
Example of Test Bead on a Stub (Not Preferred)
Stub
<50 mils
Figure 87.
Example of Differential Test Bead with Matched Placement
Table 63.
Bead Parameters (Sheet 1 of 2)
Parameter
Test Bead Width
Test Bead Length
Test Bead Diameter mils mils mils
Test Bead Height (before being hit by probe) mils
Test Bead Height (after being hit by probe)
Typical Bead-to-Bead Pitch requirement 1 mils mils
Units
Recommendation
Beads formed over solder-mask-openings
4-7
20
NA
7-8
5
50
Beads placed on existing vias
NA
NA
20
5-6
5
50
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Table 63.
Bead Parameters (Sheet 2 of 2)
Recommendation
Parameter Units
Beads formed over solder-mask-openings
Beads placed on existing vias
Typical Bead-to-Component Pitch requirement 1
Typical flying probe diameter mils mils
25
36
25
36
Notes:
1.
2.
Bead-to-Bead pitch and bead-to-component requirements are based on the bed-of-nails or probe capabilities. Customers should work with their specific vendors to determine what the minimum placement requirements are.
This is the actual diameter of the probe being used to take measurements. Customers should work with their specific vendors to determine what their minimum flying probe diameter is.
Figure 88.
Bead Formed Over Solder-Mask Opening
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Figure 89.
Bead Placed on Existing Via
Intel ® Quark™ SoC X1000—Design for Testability (DFT)
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LAN Design Considerations and Guidelines—Intel ® Quark™ SoC X1000
21.0
LAN Design Considerations and Guidelines
The Intel
®
Quark™ SoC X1000 incorporates an integrated 10/100 Mbps MAC controller
that can be used with an external PHY shown in Figure 90
. Its bus master capabilities enable the component to process high-level commands and perform multiple operations, which lowers processor use by off loading communication tasks from the processor.
The SoC, which hereinafter refers to the integrated MAC within the SoC, supports an
MDIO interface for manageability. The integrated MAC supports multi-speed operation
(10/100 Mbps). The integrated MAC also operates in full-duplex at all supported speeds or half-duplex at 10/100 Mbps as well as adhering to the IEEE 802.3x Flow Control
Specification.
Figure 90.
SOC/PHY Interface Connections
M A C 0
M D IO _ 0
R M II_ 0
P H Y 0
S o C
M A C 1
M D IO _ 1
R M II_ 1
P H Y 1
Note: The following sections are based on the TI DP83848I Port 10/100 Mb/s Ethernet PHY.
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Table 64.
MDIO Data Signals on the Intel ® Quark™ SoC X1000
Group
MAC_0 Data
MAC_1 Data
PHY Signal Name
MDIO
MDIO
SOC Signal Name
MAC0 MDIO
MAC1_MDIO
Description
MDIO data
MDIO data
Table 65.
RMII Signals
Group
MAC_0
Data
MAC_0
Data
MAC_1
Data
MAC_1
Data
MAC_0 Ctrl
PHY Signal Name
TXD_0
TXD_1
RXD_0
RXD_1
TXD_0
TXD_1
RXD_0
RXD_1
TX_EN
MAC_0 Ctrl
MAC_1 Ctrl
MAC_1 Ctrl
RX_DV
TX_EN
RX_DV
SOC Signal Name
MAC0_RXDATA[1:0]
MAC0_TXDATA[1:0]
MAC1_RXDATA[1:0]
MAC1_TXDATA[1:0]
MAC0_TXEN
MAC0_RXDV
MAC1_TXEN
MAC1_RXDV
Description
SoC receive data
SoC transmit data
SoC receive data
SoC transmit data
SoC MAC0 transmit enable
SoC MAC0 Receive data valid
SoC MAC1 transmit enable
SoC MAC1 Receive data valid
Table 66.
21.1
21.1.1
Clock and Reset Signals
Group PHY Signal Name
Clock MDC
SOC Signal Name
MAC0_MDC
Clock
Clock
MDC
X1
MAC1_MDC
RMII_REF_CLK
Description
MAC0 management data clock
MAC1 management data clock
RMII PHY reference clock
PHY Overview
The PHY is a single port compact component designed for 10/100Mbps operation. The
PHY provides a standard IEEE 802.3u Ethernet interface for 100BASE-TX, and 10BASE-
T applications.
PHY Interconnects
The main interfaces for either PHY are MDIO and RMII on the host side and Media
Dependent Interface (MDI) on the link side. Transmit traffic is received from the SoC as
RMII packets on the host interconnect and transmitted as Ethernet packets on the MDI link. Receive traffic arrives as Ethernet packets on the MDI link and transferred to the
SoC through the RMII interconnect.
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21.1.2
21.1.2.1
21.1.2.2
21.1.3
21.1.3.1
Note:
21.2
21.2.1
RMII Interface
RMII Interface Signals
The signals used to connect between the SoC and the PHY in this mode are:
• Two receive data bits running at 10/100 Mb/s for Rx.
• Two transmit data bits running at 10/100 Mb/s for Tx.
• 50 MHz reference clock input to the PHY is generated by the SOC.
• Transmit enable indicator from SOC to PHY.
• Receive data valid from PHY to SOc with receive data.
The PHY transmit/receive pins are output/input signals and are connected to the SOC
as listed in Table 64 through Table 66 .
RMII Reference Clock
The RMII Interface uses a 50 MHz reference clock, denoted RMII_REF_CLK. This signal is generated from the SoC and routed to the PHY port and in to the MAC port reference clock.
The frequency tolerance for the RMII reference clock is ±50 ppm.
MDIO Interface
MDIO is a low speed (2.5 MHz) serial bus used to connect various components in a system. MDIO is used as an interface to pass management and configuration messages between the PHY and the SOC
The MDIO uses two primary signals: MDC and MDIO, to communicate. MDC is pulled up with a 4.7k
resistor and MDIO is pulled up with a 1.5k
resistor.
MDIO Connectivity
Table 64 through Table 66 list the relationship between PHY MDIO pins to the SoC LAN
MDIO pins.
The MDIO signals (MDIO and MDC) cannot be connected to any other devices other than the integrated MAC. Connect the MDIO and MDC pins to the integrated MAC0/1
MDIO and MDC pins, respectively.
Platform LAN Design Guidelines
These sections provide recommendations for selecting components and connecting special pins. For Ethernet designs, the main elements are Intel ® Quark™ SoC X1000,
PHYs, a magnetics modules, RJ-45 connectors and a clock source.
General Design Considerations for PHYs
Sound engineering practices must be followed with respect to unused inputs by terminating them with pull-up or pull-down resistors, unless otherwise specified in a datasheet, design guide or reference schematic. Pull-up or pull-down resistors must not be attached to any balls identified as “No Connect.” These devices might have special test modes that could be entered unintentionally.
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21.2.1.1
21.2.1.2
21.2.1.3
Table 67.
Clock Source
All designs require a 50 MHz clock source. The PHY uses the 50 MHz source to generate internal clocks for both the PHY circuits and the RMII interface. SoC generates this
50Mhz reference clock internally and is passed out of the SoC for routing to the PHY and back to the MAC reference clock port. This methodology manages the clock skew externally rather than resolving it internally.There are three steps to crystal qualification:
1. Verify that the vendor’s published specifications in the component datasheet meet the required conditions for frequency, frequency tolerance, temperature, oscillation mode and load capacitance as specified in the respective datasheet.
2. Perform physical layer conformance testing and EMC (FCC and EN) testing in real systems.
3. Independently measure the component’s electrical parameters in real systems.
Measure frequency at a test output to avoid test probe loading effects at the PHY.
Check that the measured behavior is consistent from sample to sample and that measurements meet the published specifications. For crystals, it is also important to examine startup behavior while varying system voltage and temperature.
Magnetics Module
The magnetics module has a critical effect on overall IEEE and emissions conformance.
The device should meet the performance required for a design with reasonable margin to allow for manufacturing variation. Carefully qualifying new magnetics modules prevents problems that might arise because of interactions with other components or the printed circuit board itself.
The steps involved in magnetics module qualification are similar to those for crystal qualification:
1. Verify that the vendor’s published specifications in the component datasheet meet or exceed the required IEEE specifications.
2. Independently measure the component’s electrical parameters on the test bench, checking samples from multiple lots. Check that the measured behavior is consistent from sample to sample and that measurements meet the published specifications.
3. Perform physical layer conformance testing and EMC (FCC and EN) testing in real systems. Vary temperature and voltage while performing system level tests.
Criteria for Integrated Magnetics Electrical Qualification
The following table gives the criteria used to qualify integrated magnetics.
Integrated Magnetics Recommended Qualification Criteria (Sheet 1 of 2) w/8 mA DC bias; at 25C 400 uH Min Open Circuit
Inductance
(OCL) w/8 mA DC bias; at 0C to 70C 350 uH Min
Insertion Loss
100 kHz through 999 kHz
1.0 MHz through 60.0 MHz
60.1 MHz through 80.0 MHz
80.1 MHz through 100.0 MHz
100.1 MHz through 125.0 MHz
1 dB Max
0.6 dB Max
0.8 dB Max
1.0 dB Max
2.4 dB Max
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Table 67.
21.2.2
21.2.3
Integrated Magnetics Recommended Qualification Criteria (Sheet 2 of 2)
Return Loss
1.0 MHz through 40.0 MHz
40.1 MHz through 100.0 MHz
When reference impedance is 85
Ohms, 100 Ohms, and 115
Ohms.Note that R.L. values may vary with MDI trace lengths. The
LAN magnetics may need to be measured in the platform where it will be used.
18.0 dB Min
12 – 20 * LOG (Freq in MHz / 80) dB Min
Crosstalk
Isolation
Discrete
Modules
1.0 MHz through 29.9 MHz
30.0 MHz through 250.0 MHz
250.1 MHz through 375.0 MHz
-50.3+(8.8*(Freq in MHz / 30)) dB Max
-(26 -(16.8*(LOG(Freq in MHz / 250 MHz)))) dB Max
-26.0 dB Max
Crosstalk
Isolation
Integrated
Modules
(Proposed)
1.0 MHz through 10 MHz
10.0 MHz through 100.0 MHz
100 MHz through 375.0 MHz
-50.8+(8.8*(Freq in MHz / 10)) dB Max
-(26 -(16.8*(LOG(Freq in MHz / 100 MHz)))) dB Max
-26.0 dB Max
Diff to CMR
CM to CMR
Hi-Voltage
Isolation
1 MHz through 29.9 MHz
30.0 MHz through 500 MHz
1 MHz through 270 MHz
270.1 MHz through 300 MHz
300.1 MHz through 500 MHz
1500 Vrms at 50 or 60 Hz for 60 sec.
or:2250 Vdc for 60 seconds
-40.2+(5.3*((Freq in MHz / 30)) dB Max
-(22-(14*(LOG((Freq in MHz / 250)))) dB Max
-57+(38*((Freq in MHz / 270)) dB Max
-17-2*((300-(Freq in MHz) / 30) dB Max
-17 dB Max
Minimum
NVM Configuration for PHY Implementations
The LAN configuration is programmed via the legacy SPI Flash, which is connected to the SoC. Several words of the non-volatile memory are accessed automatically by the
SoC after reset to provide pre-boot configuration data before it is accessed by host software. The NVM space is used by software for storing the MAC address, serial numbers, and additional information. More details may be obtained from the
Datasheet.
Intel has a software utility called EEupdate that is used to program the SPI Flash images in development or production line environments. A copy of this program can be obtained through your Intel representative.
LED Example
Where the PHY has LED outputs that can be configured via the NVM. An example
hardware configuration is shown in Figure 91
.
Refer to the Datasheet for details regarding the programming of the LED’s and the various modes.
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Figure 91.
LED Hardware Configuration
LED2
330 ohm
Yellow
Green
LED1
VCC3P3
Green
330 ohm
LED0
21.2.3.1
RBIAS
RBIAS requires external resistor connection to bias the internal analog section of the device. The input is sensitive to the resistor value. Resistors of 1% tolerance must be used. Connect RBIAS through a 4.87 k 1% pull-down resistor to ground and then place it no more than one half inch (0.5”) away from the PHY.
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21.3
Intel
®
Quark™ SoC X1000 – MDIO/RMII LOM Design
Guidelines
This section contains guidelines on how to implement a SoC/PHY single solution on a system motherboard. It should not be treated as a specification, and the system designer must ensure through simulations or other techniques that the system meets the specified timings. The following are guidelines for both SoC MDIO and RMII interfaces.
Figure 92.
Single PHY Solution Interconnect
RMII
SoC
MAC0_TXDATA_1
MAC0_TXDATA_0
MAC0_RXDATA_1
MAC0_RXDATA_0
RXDATA[1]
RXDATA[0]
TXDATA[1]
TXDATA[0]
PHY
RMII_REF_CLK
MAC0_RXDV
MAC0_TXEN
REFCLK/X1
RX_DV
TX_EN
MAC0_MDIO
MAC0_MDC
MDIO
MDIO
MDC
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21.4
21.5
21.6
21.6.1
General Layout Guidelines
PHY interface signals must be carefully routed on the motherboard to meet the timing and signal quality requirements of their respective interface specifications. The following are some general guidelines that should be followed in designing a LAN solution. It is recommended that the board designer simulate the board routing to verify that the specifications are met for flight times and skews due to trace mismatch and crosstalk.
Layout Considerations
Critical signal traces should be kept as short as possible to decrease the likelihood of effects by high frequency noise of other signals, including noise carried on power and ground planes. This can also reduce capacitive loading.
Since the transmission line medium extends onto the printed circuit board, layout and routing of differential signal pairs must be done carefully.
For the PHY, system level tests should be performed at two speeds.
Guidelines for Component Placement
Component placement can affect signal quality, emissions, and component operating temperature. Careful component placement can:
• Decrease potential problems directly related to electromagnetic interference (EMI), which could cause failure to meet applicable government test specifications. In this case, place the PHY more than one inch from the edge of the board.
• Simplify the task of routing traces. To some extent, component orientation affects the complexity of trace routing. The overall objective is to minimize turns and crossovers between traces.
PHY Placement Recommendations
Minimizing the amount of space needed for the PHY is important because other interfaces compete for physical space on a motherboard near the connector. The PHY circuits need to be as close as possible to the connector.
The following figure illustrates some basic placement distance guidelines. To simplify the diagram, it shows only two differential pairs, but the layout can be generalized for a
100MbE system with four analog pairs. The ideal placement for the PHY (LAN silicon) is approximately one inch behind the magnetics module.
While it is generally a good idea to minimize lengths and distances, this figure also illustrates the need to keep the PHY away from the edge of the board and the magnetics module for best EMI performance.
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Figure 93.
PLC Placement: At Least One Inch from I/O Backplane
Figure 94.
Effect of LAN Device Placed Too Close To a RJ-45 Connector or Chassis
Opening
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21.7
21.8
Note:
Table 68.
MDI Differential-Pair Trace Routing for LAN Design
Trace routing considerations are important to minimize the effects of crosstalk and propagation delays on sections of the board where high-speed signals exist. Signal traces should be kept as short as possible to decrease interference from other signals, including those propagated through power and ground planes.
Signal Trace Geometry
One of the key factors in controlling trace EMI radiation are the trace length and the ratio of trace-width to trace-height above the reference plane. To minimize trace inductance, high-speed signals and signal layers that are close to a reference or power plane should be as short and wide as practical. Ideally, the trace-width to trace-height above the ground plane ratio is between 1:1 and 3:1. To maintain trace impedance, the width of the trace should be modified when changing from one board layer to another if the two layers are not equidistant from the neighboring planes.
Each pair of signals should have a differential impedance of 100 ±15%.
When performing a board layout, the automatic router feature of the CAD tool must not route the differential pairs without intervention. In most cases, the differential pairs will require manual routing.
Measuring trace impedance for layout designs targeting 100 often results in lower actual impedance due to over-etching. Designers should verify actual trace impedance and adjust the layout accordingly. If the actual impedance is consistently low, a target of 105 to 110 should compensate for over-etching.
It is necessary to compensate for trace-to-trace edge coupling, which can lower the differential impedance by up to 10 , when the traces within a pair are closer than 30 mils (edge-to-edge).
MDI Routing Summary
Signal group
Microstrip uncoupled single-ended impedance specification
Microstrip uncoupled differential impedance specification
Microstrip nominal trace width
Microstrip nominal trace space
Microstrip trace length
Microstrip pair-to-pair space (edge-toedge)
Parameter
Microstrip bus-to-bus spacing
Main Route Guidelines
MDI_PLUS[0:3]
MDI_MINUS[0:3]
50 ±10%
Breakout
Guidelines 1
100 ±15%
Design dependent
Design dependent
4 in (101.6 mm) maximum
7 times the thickness of the thinnest adjacent dielectric layer
7 times the thickness of the thinnest adjacent dielectric layer
Design dependent
Design dependent
Notes
2,3
4
3,5
6,7
Notes:
1.
2.
Pair-to-pair spacing 3 times the dielectric thickness for a maximum distance of 500 mils from the pin.
Board designers should ideally target 100 ±15%. If it’s not feasible (due to board stack-up) it is recommended that board designers use a 95 ±10% target differential impedance for MDI with the expectation that the center of the impedance is always targeted at 95 . The ±10% tolerance is
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Table 69.
Note:
3.
4.
5.
6.
7.
provided to allow for board manufacturing process variations and not lower target impedances. The minimum value of impedance cannot be lower than 85 .
Simulation shows 80 differential trace impedances degrade MDI return loss measurements by approximately 1 dB from that of 90 .
Stripline is NOT recommended due to thinner more resistive signal layers.
Use a minimum of 21 mil (0.533 mm) pair-to-pair spacing for board designs that use the CRB design stack-up. Using dielectrics that are thicker than the CRB stack-up might require larger pair-to-pair spacing.
For applications that require a longer MDI trace length of more than 8 inches (20.32 mm), it is recommended that thicker dielectric or lower Er materials be used. This permits higher differential trace
impedance and wider, lower loss traces. Refer to Table 69
for examples of microstrip trace geometries for common circuit board materials.
Intel® Quark™ SoC designs without LAN switch can range up to ~8 inches. Refer to Table 69
for trace length information.
Maximum Trace Lengths Based on Trace Geometry and Board Stack-Up
Dielectric
Thickness
(mils)
3.3
3.3
4
4
4
2.7
2.7
2.7
3.3
Dielectric
Constant
(DK) at
1 MHz
4.1
4.1
4.2
4.2
4.2
4.05
4.05
4.05
4.1
Width /
Space/
Width
(mils)
4/10/4
4/10/4
4/10/4
4.2/9/4.2
4.2/9/4.2
4.2/9/4.2
5/9/5
5/9/5
5/9/5
Pair-to-
Pair Space
(mils)
23
23
28
28
28
19
19
19
23
Nominal
Impedance
(Ohms)
95 2
95 2
95
100 2
100
100
100 2
100
100
Impedance
Tolerance
(±%)
10
17 2
15
10
17 2
15 2
10
17 2
15
Maximum
Trace Length
(inches) 1
4.6
6
4.5
5.3
7
3.5
4
5
4
Notes:
1.
2.
Longer MDI trace lengths may be achievable, but may make it more difficult to achieve IEEE conformance. Simulations have shown deviations are possible if traces are kept short. Longer traces are possible; use cost considerations and stack-up tolerance for differential pairs to determine length requirements.
Deviations from 100? nominal and/or tolerances greater than 15% decrease the maximum length for
IEEE conformance.
Use the MDI Differential Trace Calculator to determine the maximum MDI trace length for your trace geometry and board stack-up. Contact your Intel representative for access.
The following factors can limit the maximum MDI differential trace lengths for IEEE conformance:
• Dielectric thickness
• Dielectric constant
• Nominal differential trace impedance
• Trace impedance tolerance
• Copper trace losses
• Additional devices, such as switches, in the MDI path may impact IEEE conformance
Board geometry should also be factored in when setting trace length.
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Figure 95.
MDI Trace Geometry
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21.9
Trace Length and Symmetry
The differential traces should be equal in total length to within 10 mils (0.254 mm) per segment within each pair and as symmetrical as possible. Asymmetrical and unequal length traces in the differential pairs contribute to common mode noise. If a choice has to be made between matching lengths and fixing symmetry, more emphasis should be placed on fixing symmetry. Common mode noise can degrade the receive circuit’s performance and contribute to radiated emissions.
The intra-pair length matching on the pairs must be within 10 mils on a segment by segment basis. An MDI segment is defined as any trace within the same layer. For example, transitioning from one layer to another through a via is considered as two separate MDI segments.
The end to end total trace lengths within each differential pair must match as shown in the figure titled MDI Trace Geometry. The end to end trace length is defined as the total
MDI length from one component to another regardless of layer transitions.
The pair to pair length matching is not as critical as the intra-pair length matching but it should be within 2 inches.
When using Microstrip, the MDI traces should be at least 7x the thinnest adjacent dielectric away from the edge of an adjacent reference plane.
Figure 96.
MDI Differential Trace Geometry
Keep trace-to-trace length difference within each segment to less than 10 mils.
PHY
PHY
MDI0+
MDI0-
LAN Switch
MDI0+
MDI0-
Magnetics
MDI0+
MDI0-
RJ45
Connector
Keep overall trace-to-trace length difference within 30 mils.
21.10
Impedance Discontinuities
Impedance discontinuities cause unwanted signal reflections. Vias (signal through holes) and other transmission line irregularities should be minimized. If vias must be used, a reasonable budget is four or less per differential trace. Unused pads and stub traces should also be avoided.
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21.11
21.12
21.13
Caution:
Note:
Reducing Circuit Inductance
Traces should be routed over a continuous reference plane with no interruptions. If there are vacant areas on a reference or power plane, the signal conductors should not cross the vacant area. This causes impedance mismatches and associated radiated noise levels.
Signal Isolation
To maintain best signal integrity, keep digital signals far away from the analog traces. If digital signals on other board layers cannot be separated by a ground plane, they should be routed perpendicular to the differential pairs. If there is another PHY on the board, the differential pairs from that circuit must be kept away.
Other rules to follow for signal isolation include:
• Separate and group signals by function on separate layers if possible. If possible, maintain at least a gap of 30 mils between all differential pairs (Ethernet) and other nets, but group associated differential pairs together.
• Physically group together all components associated with one clock trace to reduce trace length and radiation.
• Isolate I/O signals from high-speed signals to minimize crosstalk, which can increase EMI emission and susceptibility to EMI from other signals.
• Avoid routing high-speed LAN traces near other high-frequency signals associated with a video controller, cache controller, processor, switching power supplies, or other similar devices.
Power and Ground Planes
Good grounding requires minimizing inductance levels in the interconnections and keeping ground returns short, signal loop areas small, and power inputs bypassed to signal return. This will significantly reduce EMI radiation.
The following guidelines help reduce circuit inductance in both backplanes and motherboards:
• Route traces over a continuous plane with no interruptions. Do not route over a split power or ground plane. If there are vacant areas on a ground or power plane, avoid routing signals over the vacant area. This will increase inductance and EMI radiation levels.
• All ground vias should be connected to every ground plane; and every power via, to all power planes at equal potential. This helps reduce circuit inductance.
• Physically locate grounds between a signal path and its return. This will minimize the loop area.
• Split the ground plane beneath a magnetics module. The RJ-45 connector side of the transformer module should have chassis ground beneath it.
DO NOT do this, if the RJ-45 connector has integrated USB.
All impedance-controlled signals should be routed in reference to a solid plane. If there are plane splits on a reference layer and the signal traces cross those splits then stitching capacitors should be used within 40 mils of where the crossing occurs. See
If signals transition from one reference layer to another reference layer then stitching capacitors or connecting vias should be used based on the following:
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If the transition is from power-referenced layer to a ground-referenced layer or from one voltage-power referenced layer to a different voltage-power referenced layer, then stitching capacitors should be used within 40 mils of the transition.
If the transition is from one ground-referenced layer to another ground-referenced layer or is from a power-referenced layer to the same net power-referenced layer, then connecting vias should be used within 40 mils of the transition.
Figure 97.
Trace Transitioning Layers and Crossing Plane Splits
Transitioning Reference Layers
Top Layer
Crossing Plane Splits-Use Stitching Capacitors
+3.3 Vdc plane via
Stitching capacitor
<40 mils
10 pF
Lower Layer
GND plane
3.3 Vdc plane
Do not run trace under edge of a plane
5.0 Vdc plane Trace
Board
Layers
Connection Vias
GND to GND
10 pF Distance from stitching capacitor to any via is <40 mils { copper
3.3 V power
GND copper
<40 mils copper
GND copper power copper
GND copper
<40 mils
Connection Vias
PWR to same PWR copper
PWR 3.3 Vdc copper
GND copper
PWR 3.3 Vdc copper
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Figure 98.
Via Connecting GND to GND
6
7
4
5
Layers
1
2
3
Layers
Coupling
GND
VCC
PWR
VCC
GND
MDI Trace
<40 mils Via
Figure 99.
Stitching Capacitor between Vias Connecting GND to GND
Layers
1
Inter-Layer
Coupling
2 GND
H1
3
4
H2
Power
<40 mils
H1<<H2: No via, same GND V
+
H1>>H2: Stitching capacitor required
H1~H2: Stitching capacitor required
10 pF Stitching
Capacitor and Vias
PWR1
PWR2
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21.14
Traces for Decoupling Capacitors
Traces between decoupling and I/O filter capacitors should be as short and wide as practical. Long and thin traces are more inductive and reduce the intended effect of decoupling capacitors. Also, for similar reasons, traces to I/O signals and signal terminations should be as short as possible. Vias to the decoupling capacitors should be sufficiently large in diameter to decrease series inductance. Refer to the Power Delivery section for the PHY in regards to actual placement requirements of the capacitors.
21.15
Ground Planes under a Magnetics Module
The magnetics module chassis or output ground (secondary side of transformer) should be separated from the digital or input ground (primary side) by a physical separation of
100 mils minimum. Splitting the ground planes beneath the transformer minimizes noise coupling between the primary and secondary sides of the transformer and between the adjacent coils in the magnetics. This arrangement also improves the common mode choke functionality of magnetics module.
Caution: DO NOT do this if the RJ-45 connector has integrated USB.
illustrates the split plane layout for a discrete magnetics module. Capacitors are used to interconnect chassis ground and signal ground.
shows the preferred method for implementing a ground split under an integrated magnetics module/RJ-45 connector.
Figure 100. Ideal Ground Split Implementation
Board Edge RJ/Mag.
Chassis
GND
Capacitor
Stuffing
Options
RJ Shield connected to
Chassis
GND
Capacitor
Stuffing
Options
C1 C2 C3
C4 C5
Digital
GND
C6
Resistive
Terminations
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Table 70.
Capacitor Stuffing Option Recommended Values
Capacitors
C3, C4
C1, C2, C5, C6
4.7 µF or 10 µF
470 pF to 0.1 µF
Value
The placement of C1 through C6 may also differ for each board design (in other words, not all of the capacitors may need to be populated). Also, the capacitors may not be needed on both sides of the magnetics module.
Note: If using an integrated magnetics module without USB, provide a separate chassis ground “island” to ground around the RJ-45 connector. The split in the ground plane should be at least 20 mils wide.
Some integrated magnetics modules/RJ-45 connectors have recently incorporated the
USB into the device. For this type of magnetics module, a chassis ground moat may not be feasible due to the digital ground required for the USB pins and their placement relative to the magnetics pins. Thus, a continuous digital ground without any moats or
splits must be used. Figure 101
provides an example of this.
Figure 101. Ground Layout with USB
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21.16
21.17
21.18
21.19
21.20
Light Emitting Diodes
The device has three high-current outputs to directly drive LEDs for link, activity and speed indication. Since LEDs are likely to be integral to a magnetics module, take care to route the LED traces away from potential sources of EMI noise. In some cases, it may be desirable to attach filter capacitors.
LAN LED traces should be placed at least 6x (side by side separation) the dielectric height from sources of noise (ex: signaling traces) and susceptible signal traces (ex: reset signals) on the same or adjacent layers.
LAN LED traces should be placed at least 7x (broadside coupling) the dielectric height from sources of noise (ex: signaling traces) and susceptible signal traces (ex: reset signals) on the same or adjacent layers.
Vibrational Mode
Crystals in the frequency range referenced above are available in both fundamental and third overtone. Unless there is a special need for third overtone, fundamental mode crystals should be used.
Nominal Frequency
The Ethernet controller uses a crystal frequency of 50.000 MHz. The 50 MHz input is used to generate a 125 MHz transmit clock for 100BASE-TX operation, and 10 MHz and
20 MHz transmit clocks, for 10BASE-T operation.
Frequency Tolerance
The frequency tolerance for an Ethernet Platform LAN Connect device is dictated by the
IEEE 802.3 specification as ±50 parts per million (ppm). This measurement is referenced to a standard temperature of 25 °C.
Troubleshooting Common Physical Layout Issues
The following is a list of common physical layer design and layout mistakes in LAN on
Motherboard (LOM) designs.
1. Lack of symmetry between the two traces within a differential pair. Asymmetry can create common-mode noise and distort the waveforms. For each component and via that one trace encounters, the other trace should encounter the same component or a via at the same distance from the Ethernet silicon.
2. Unequal length of the two traces within a differential pair. Inequalities create common-mode noise and will distort the transmit or receive waveforms.
3. Excessive distance between the Ethernet silicon and the magnetics. Long traces on
FR4 fiberglass epoxy substrate will attenuate the analog signals. In addition, any impedance mismatch in the traces will be aggravated if they are longer than the four-inch guideline.
4. Routing any other trace parallel to and close to one of the differential traces.
Crosstalk getting onto the receive channel will cause degraded long cable BER.
Crosstalk getting onto the transmit channel can cause excessive EMI emissions and can cause poor transmit BER on long cables. At a minimum, for stripline other signals should be kept at least 6x the height of the thinnest adjacent dielectric layer. For microsrip it is 7x. The only possible exceptions are in the vicinities where the traces enter or exit the magnetics, the RJ-45 connector, and the Ethernet silicon.
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5. Using a low-quality magnetics module.
6. Reusing an out-of-date physical layer schematic in a Ethernet silicon design. The terminations and decoupling can be different from one PHY to another.
7. Incorrect differential trace impedances. It is important to have about a 100 impedance between the two traces within a differential pair. This becomes even more important as the differential traces become longer. To calculate differential impedance, many impedance calculators only multiply the single-ended impedance by two. This does not take into account edge-to-edge capacitive coupling between the two traces. When the two traces within a differential pair are kept close to each other, the edge coupling can lower the effective differential impedance by 5 to
20 .
Short traces will have fewer problems if the differential impedance is slightly off target.
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21.21
21.22
Power Delivery
In general planes should be used to deliver 3.3 Vdc and the Core voltage. Not using planes can cause resistive voltage drop and/or inductive voltage drop (due to transient or static currents). Some of the symptoms of these voltage drops can include higher
EMI, radiated immunity, radiated emissions, IEEE conformance issues, and register corruption.
Decoupling capacitors (0.1 uF and smaller) should be placed within 250 mils of the LAN device. They also should be distributed around the PHY and some should be in close proximity to the power pins.
The bulk capacitors (1.0 uF or greater) should be placed within 1 inch if using a trace
(50 mils wide or wider) or within 1.5 inches if using a plane.
Routing Guidelines
Table 71.
MAC0_TXDATA<1:0>; MAC0_TXEN; MAC0_MDC; MAC0_MDIO
Breakout
PCB Routing Layer(s)
Optional
Transmission Line Segment
Routing Layer (Microstrip /
Stripline / Dual Stripline)
Characteristic Impedance
(Single-ended)
Trace Width (w)
Trace Spacing(S2): Between
RMII Signals
Trace Spacing(S3): Between
RMII and other signals
4 Layer
L a
MS
4.2 mil
4.2 mil
4.2 mil
4 Layer
L b
MS
4 Layer
50 Ω +/- 10%
4.2 mil
10 mil
10 mil
L c
MS
4.2 mil
10 mil
10 mil
4 Layer
L d
MS
4.2 mil
4.2 mil
4.2 mil
Trace Segment Length 0.5" max 0.1" - 0.8" 0.1" - 3.0" 0.5" max
Note: * Keep La + Lb as short as possible to give the best margin on the overshoot/undershoot violation.
Table 72.
MAC0_RXDATA<1:0>; MAC0_RXDV
Breakout
PCB Routing Layer(s)
Optional
Transmission Line Segment
Routing Layer (Microstrip /
Stripline / Dual Stripline)
Characteristic Impedance
(Single-ended)
Trace Width (w)
4 Layer
L a
MS
4.2 mil
4 Layer
L b
MS
4 Layer
L c
MS
50 Ω +/- 10%
4.2 mil 4.2 mil
4 Layer
L d
MS
4.2 mil
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Table 72.
MAC0_RXDATA<1:0>; MAC0_RXDV
Breakout
Trace Spacing(S2): Between
RMII Signals
Trace Spacing(S3): Between
RMII and other signals
4.2 mil
4.2 mil
10 mil
10 mil
10 mil
10 mil
4.2 mil
4.2 mil
Trace Segment Length 0.5" max 0.1" - 3.0" 0.1" - 0.8" 0.5" max
Note: * Keep Lc + Ld as short as possible to give the best margin on the overshoot/undershoot violation.
Number of vias
Rs
Reference Plane max 2
33ohm +/- 5%
Solid Ground Reference
SoC
+
TX
-
+
RX
-
CFIOHVTEW NO RCOMP
Breakout
La Lb
Rs
Lc Ld
§ §
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Wireless Modules and Antenna Design Guidelines—Intel ® Quark™ SoC X1000
22.0
22.1
22.2
22.2.1
Wireless Modules and Antenna Design Guidelines
Introduction
There are a broad range of Wireless modules available suited to different regulatory, performance and user requirements. This chapter shall discuss choice of antenna materials, placement options and coexistence considerations for Intel ®
X1000-based designs.
Quark™ SoC
Co-existence of multiple wireless modules and their antennas, among themselves and with the other systems and parts in the device can become a major problem if not considered in the initial stages of design.
SoC may support radios for:
• WiFi
• Bluetooth* (BT)
• ZigBee (802.15.4)
WLAN System Integration Considerations
Antenna Integration into the Platform
The goal of successful antenna integration on the system is four-fold:
1. Maintain good antenna efficiency for all antennas taken separately .
2. Ensure that platform noise coupling into each antenna is minimized (in-band noise).
3. Isolation between antennas is adequate to allow for: a. Typical simultaneous radio usage scenarios to be supported (co-existence) b. For radios supporting MIMO (multiple input and multiple output) or diversity, the spatial correlation and mutual coupling are low enough that maximum benefit can be derived from the additional radio chain
The following must be considered when deciding placement of antennas:
Antenna size – Larger sizes tend to provide better performance (gain, bandwidth, efficiency).
Separation of radiation element from lossy structures including LCD enclosure : Larger separation will provide higher bandwidth. In general, lower operational frequencies require larger separation compared to higher operational frequencies. Also, larger bandwidth considerations require larger separation from nearby metallic structures.
Isolation between antenna ports : Larger spatial separation is one way of increasing the isolation between ports of radio modules that operate in bands that are close to one another.
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22.2.2
Cable routing : Cable routing that avoids regions of high noise and minimizes cable lengths allow for noise and losses to be minimized.
Cable thickness (loss) : Thick cable (e.g., 1.37 mm) tends to be less lossy while being more expensive compared to thin cable (e.g., 1.13 mm). Double shielded cable is useful in ensuring that radio module sensitivity degradation is limited
Antenna Orientation : In some instances where the antennas have polarization discrimination, the relative orientation of the antennas can be used to enhance performance.
Distance from Noisy components : Impact of noisy components of the LCD, especially the timing controller chip in the display row-column drivers and un-shielded
USB web cameras on the antenna must be considered. Modules must be shielded and antenna placement and cable routing must be optimized to minimize noise pickup by the antennas.
Antenna Coexistence
22.2.3
Radios Operating
Simultaneously
Acceptable Performance Metric
WLAN interference to BT
BT interference to WLAN
WLAN to ZigBee
BT to ZigBee
While WLAN link is active, BT voice performance, as measured by Mean Opinion
Score should not degrade below 3.5. Co-existence scheme between WLAN and
BT should be enabled.
While BT link (Stereo audio) is active, care should be taken to ensure that the
WLAN Radio is not de-sensed by more than acceptable levels. Contact WLAN module vendors for this information. (De-sense is measured through throughput vs. received power curves, with and without interference).
When WLAN connection is active, ZigBee performance should not degrade from when ZigBee alone is active.
When BT headset is being used with Stereo Audio, ZigBee performance should not degrade from when ZigBee alone is active.
WiFi Module
There is a broad offering of Intel and third-party WiFi modules supporting various
802.11 standards. Offerings are also differentiated by the number of inputs and outputs. In addition to cost, system integrators can keep in mind antenna placement options and wireless performance/quality requirements while making choices. MIMOcapable Wireless modules will provide additional flexibility in antenna placement in addition to providing better throughput. WiFi+BT integrated modules would be a good option for systems support Bluetooth as well, as these modules will ensure better coexistence and connectivity of both WLAN and Bluetooth. The current Intel
®
Quark™
SoC X1000 guideline is that the WiFi connectivity is provided via a daughter card/ module.
The major design considerations for placement of a WiFi module on the platform are:
• Location of the module with respect to unintentional radiation sources on the platform (eg., DDR interface, platform clocks, and even emissions from peripherals)
• Placement of the module within an all-metal chassis without signal degradation
• Shielding of the module
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22.2.4
22.2.5
22.2.6
WiFi Module Connector Types
As WiFi modules are mounted on the platform, connectors plugging into them will add to the total z-height. OEM’s can select connectors of low z-heights to keep the total zheight down. There are miniature coaxial RF connectors available in the market today with z-heights of the order of 2.5 mm to 1.4 mm.
WiFi Antenna Placement
SoC systems are more likely to use metal enclosures for manufacturing reasons. In addition, antenna clearances will be much lesser than on conventional Thin and Light designs due to tighter z-height budgets. Both factors will create significant challenges in ensuring signal quality and reception comparable to a laptop with a plastic chassis and larger z-height budgets. System designers will have to strike a compromise between signal quality and cost while integrating antennas into the system.
The antenna should be placed as close to the module as possible to reduce losses in the board and/or cables, which can affect performance (throughput/range) directly. It is also important to ensure that the antenna is not covered by or in close proximity to the user’s body and/or metallic body worn accessories. This is for two reasons; detuning of the antenna and high Specific Absorption Ratio (SAR) numbers. In addition the antenna should be kept away from noisy circuits and components such as the processor, memory, display (unshielded) etc. Minimum distances need to be maintained from metal parts depending on the type of antenna used.
The design must incorporate non conducting surfaces around the antenna for WiFi connectivity.
Maximizing the distance between the antenna and body to beyond the limit used for modular approval will allow for a reduction in test cases. This is best achieved by placing the antenna as close to the A-surface as possible.
Antenna performance is severely degraded if it is enclosed by metal or in close proximity to metal. Studies indicate that acceptable gains are possible with antenna separations of 5-mm to 10-mm from metal enclosures.
Antenna Placement
When there is a metal surface surrounding the antenna, it is recommended to have plastic sections or insert molded plastic in the metal panel to maintain WiFi connectivity. Other options include cutouts and also placing antennas on the sides of the motherboard enclosure. In this case, care should be taken to ensure EMI from adjacent IO connectors does not interfere with the antenna reception.
The following placement options may be considered for closed lid operation:
1.
Base mounted WLAN antennas: Incorporating 3G antennas in the same area will likely require additional components to achieve a compliant solution. Platform noise pickup from base mounted antennas needs to be measured before committing to a particular location as there is a higher risk of impact from platform noise with the use of base mounted antennas.
2.
Slot antennas cut into the chassis: Slots can be cut into the surface of the antenna, near the apex of the lid and the cutout can be covered with plastic inserts.
Such an antenna would be integrated into the chassis and special care must be given to the feeding mechanism, especially when materials not amenable to soldering such as aluminum are used. There are no discrete antennas with this solution. Multiple antenna SKUs will imply multiple chassis SKUs, so this option will need to be considered very early in the design cycle.
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22.2.7
22.2.8
22.2.9
22.3
22.3.1
Antenna Cabling
The antenna cable is a lossy structure and hence needs to be as short as possible.
Design choices can help reduce the cable length to the absolute minimum achievable.Studies have shown that acceptable performance metrics (loss/VSWR) can been achieved with1.37mm diameter/double shielded cables.
Platform Noise Mitigation
Straddle mounted/Mid-mounted connectors help in reducing the EMI from the platform by reducing the lengths of connector pins which act as radiating elements. This is an additional benefit over and above the z-height saving that straddle-mounted connectors provide.
EMI sources on the platform (eg. right-angle connectors, large inductors etc.) will need to be identified by probing and may require to be shielded to cut down on EMI and improve antenna performance.
System designers must be aware of noise impact from several high speed digital interfaces there is the possibility of leakage from the connector.
Antenna Material Choices
• FPC (Flex Printed Circuit): This methodology has the advantage of printing antennas on flexible strips of film or plastic. The antennas will be extremely thin and can be accommodated easily into narrow spaces and can also be bent around corners. Prototyping and testing is also easier than other options. However care should be taken to ensure that the antenna is assembled in the exact same shape and orientation that it was validated in.
• Stamped Metal: Stamped metal antennas are low cost but will require an initial tooling cost, which may increase with the number of prototypes in the process of fine-tuning the antenna.
• LDS (Laser Direct Structuring): LDS is a process of antenna design and manufacturing that allows for low-cost, rapid prototyping. With the LDS technique the antenna can be etched onto almost any surface, thus providing many options for antenna integration.
• Chip Antennas on high Dielectric material: Another technique involves utilizing antennas built on high dielectric materials such as ceramic chip antennas. While the over the air coupling mechanism in such antennas is identical to antenna built with air core or low dielectric, the surface waves in the dielectric are tightly confined to the respective antennas providing enhancement in port to port antenna isolation.
Chip antennas have the added benefit of smaller size, though there could be tradeoffs associated with providing adequate keep out zones to maximize performance.
ZigBee System Integration Considerations
SoC based platforms supporting ZigBee (802.15.4)
ZigBee Antenna Placement
Similarly to module based WiFi solutions Zigbee solutions shall be based on daughter card/modules. The antenna placement guideline for such a module should be extracted from the relevant Zigbee device datasheet.
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General Differential Signals Design Guidelines—Intel ® Quark™ SoC X1000
Appendix A General Differential Signals Design Guidelines
A.1
A.2
Introduction
The guidelines in this chapter are to improve routing for differential signals, such as
PCIe* or USB. The signal routing, via placement and bend optimization examples below apply to all high speed interfaces.
General Differential Routing Guidelines
• Do not route traces under power connectors, power modules, voltages regulators, other interface connectors, crystals, oscillators, clock synthesizers, magnetic devices or ICs that use and/or duplicate clocks. To minimize reflection, Do not place stubs, test points, test vias on the route. Utilize vias and connector pads as test points instead. If a stub is unavoidable in the design, the total of all the stubs on a particular line should not be greater than 200 mils. Simulation may be required based on the interface.
• It can be helpful for testability to route the TX and RX pairs for a given port on the same layer and close to each other to help ensure that the pairs share similar signaling characteristics. If the groups of traces are similar, a measure of RX pair layout quality can be approximated by using the results from actively testing the TX pair's signal quality.
• Separate signal traces into similar categories, and route similar signal traces together (such as routing differential pairs together).
• Keep signals clear of the core logic set. High current transients are produced during internal state transitions and can be very difficult to filter out.
A.3
General Differential Length Matching Guidelines
A.3.1
Length Matching and Length Formulas
Follow the specific interface length matching guidelines if provided. If not provided, use the below as a general guideline.
Table A-1. General Differential Pair Length Matching
Within Layer Max Mismatch
Total Length Max Mismatch
Description Units mils mils
Routing
Recommendation
+/- 15
+/- 10
The following are the length matching guidelines for differential-pairs:
• Each signal and its complement in a differential-pair should be length matched whenever possible on a layer-by-layer basis at the point of discontinuity. ‘Withinlayer’ matching means that differential pairs should be matched within 15mils
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• When trace length matching occurs, the matching should be made as close as
possible to the point where the length variation occurs, as shown in Figure A-1 , so
the discontinuity won’t propagate across the channel. For example, length matching in a chipset breakout area or connector pin field should occur within the first 125 mils (3.175 mm) of the structure that causes the length mismatch.
• Serpentine layout introduces discontinuity to the channel and should be minimized so as to make it transparent to the signal. This is done by making its electrical length shorter than the signal rise time. In general, keeping serpentine routing length <100 mils is adequate. Trace spacing should not become greater than two times the original spacing. See
.
• In determining the overall length of a given signal in a differential-pair, use pad or pin edge-to-edge distances rather than the total etch present, unless the amount of trace routing inside each pad is identical. The amount of etch within a given pad is electrically part of the pad itself. In other words, only the etch outside of the pad edge is relevant to the overall length of a differential-pair. For example:
— If the P signal of the differential-pair has an extra 5 mils (0.127 mm) of etch length compared to the N signal, and the extra 5 mils (0.127 mm) occurs due to extra etch extending into a component pad, the two signals should be considered identical length.
— Similarly, trying to length match signals by adding etch inside a pad boundary
(such as extra bends inside the pad itself) does not produce the intended length matching effect on the interconnection (see
).
Figure A-1. Length Matching Example
Figure A-2. Serpentining Example
< 100 m ils
F
S2
A B C D
E
G
Re com m e nde d dim e nsions: A =B=C=D,
E=F=G=3W (W =trace w idth) and S2<2S1
S 1
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Figure A-3. Etch Located Within a Pad Example
Figure A-4. Example of Good Length Matching
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A.4
General Differential Optimization Guidelines
A.4.1
Breakout Example and Guidelines
Maintain differential routing rules in package breakout areas.
Figure A-5. SoC Package Breakout Example
Caution:
Caution:
Guidelines are as follows:
• Differential-pair pitch is measured from the center of each trace in the differential-pair. The distance from the center of either trace in a differential-pair to the same point of reference on an adjacent differential-pair is described as interpair pitch (IPP) . See
for the illustration of differential-pair pitch and IPP.
• Differential-pair space is measured from the edge of each trace in the differential-pair. The distance from the edge of one trace in a differential-pair to the near edge of an adjacent differential-pair is described as pair-to-pair space. See
Figure A-6 for the illustration of differential-pair space and pair-to-pair space.
• Maintain the best possible lateral routing symmetry between the two signals of a
differential-pair. (See Figure A-7 ).
• Breakout routing geometries can be found in the Stackup and PCB Considerations section.
Maintain routing symmetry between the two signals of a differential-pair. Failure to maintain symmetry introduces an AC common mode voltage.
Reduced trace width will increase losses due to skin effects and reduced spacing will increase crosstalk. Therefore, it is recommended to keep breakout routing as short as possible.
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Figure A-6. Differential-Pair Spacing Diagram
IPP
W PTPS
Pitch
DPS
Figure A-7. Symmetrical and Non-Symmetrical Routing Example
Avoid: Non-symmetrical Routing
Preferred: Symmetrical Routing
A.4.2
Via Placement and Via Usage Optimization
• Vias impact the overall loss and jitter budget. Route signals with a minimal number of vias.
• The via count can be reduced but not increased from the maximum interface via requirements given in this document.
• Remove pads from unused internal layers to minimize excess via capacitance.
• The differential-pair via placement must be symmetrical. Vias on the differentialpair should not only match in number but also in relative location.
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Figure A-8. Via Pair Example
Intel ® Quark™ SoC X1000—General Differential Signals Design Guidelines
Figure A-9. Example - Via Placement 1
• The symmetric via pattern in
Figure A-10 below minimizes crosstalk between 2
differential pair, therefore the recommendation is to implement the pattern according to area availability.
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Figure A-10. Example - Via Placement 2
• For differential interfaces it is recommended 1:1 ratio of signal to GND via everywhere it is possible (
Figure A-11. Package Breakout Example - Via Placement 3
A.4.3
Bend Optimization Guidelines
Bends are a necessary component in routing differential signals. Guidelines for bends are as follows:
• Keep bends to a minimum. Bends can introduce common mode noise into the system, which can affect the signal integrity of the differential signal pair.
• If bends are required, they should be at a 135-degree angle or greater; there should be no 90-degree bends or turns. An adequate air gap should be maintained between the inside traces of a bend. The gap should be 4 times the trace width or greater. The lengths of the segments in a bend should be 1.5 times the trace width
and
• Match the number of left bends to the number of right bends to minimize skew due to length differences between each signal of the differential-pair.
• Alternate between left and right bends.
Matching the number of right and left turns and alternating bends helps to minimize the amount of skew between rising or falling edges, which minimizes the differential to common mode conversion.
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Figure A-12. Acceptable Bends vs. Tight Bends Example
P referred -
N ot C onsidered “T ight B ends”
Figure A-13. Maximum Bend Angle
A void! -
“T ight B ends”
A.5
Note:
Note:
General Differential Reference Planes Guidelines
Guidelines for reference planes are as follows:
Even when routed as coupled differential-pairs, one trace can experience more coupling to its reference plane than to its routing pair.
• Traces should avoid discontinuities in the reference plane, such as splits and other voids.
— A good plane reference helps to minimize any AC common mode voltage found on the differential-pair as well as benefiting signal quality and minimizing EMI.
• When routing near the edge of their reference plane, traces should maintain at least a 40-mil space keepout from the edge of the plane.
Referencing signals going over a board-to-board connector must be considered and stitching capacitors should be added at the connector as appropriate. For example, if a differential-pair is GND-referenced on the motherboard and the pair is V between V
CC
and GND.
CC
referenced on the daughter card, then stitching capacitors must be added at the connector
• One reference plane should be used for the entire length of the trace route.
— If this cannot be accomplished, stitching vias must be used to tie the two planes together. The vias should be located within 200 mils and in symmetry with the two signal vias to minimize return path discontinuities.
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• Differential signals should not cross any plane splits or voids. However, it may be necessary for a trace to be partially routed over a via anti-pad void in the chipset escape area. The amount of the trace that is over the void should be minimized in the length and percentage of the width of the trace. At worst, no more than half of the trace width should be over the via anti-pad at any given time.
— If crossing a plane split is necessary, proper placement of stitching caps can minimize the adverse effects on EMI and signal quality performance caused by crossing the split. Stitching capacitors are small-valued capacitors (1 µF or lower in value) that bridge voltage plane splits close to where high-speed signals or clocks cross the plane split. The capacitor ends should tie to each plane separated by the split. They are also used to bridge, or bypass, power and ground planes close to where a high-speed signal changes layers.
— As an example of bridging plane splits, a plane split that separates V
V
CC3_3
V
CC3_3
5REF
5REF
and
planes should have a stitching cap placed near any high-speed signal crossing. One side of the cap should tie to V and the other side should tie to
. Stitching caps provide a high frequency current return path across plane splits. They minimize the impedance discontinuity and current loop area that crossing a plane split creates.
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Exposed Pad* (e-Pad*) Design and SMT Assembly Guide—Intel ® Quark™ SoC X1000
Appendix B Exposed Pad* (e-Pad*) Design and SMT
Assembly Guide
B.1
B.2
Note:
Overview
This section provides general information about ePAD and SMT assemblies. Chip packages have exposed die pads on the bottom of each package to provide electrical interconnections with the printed circuit board. These ePADs also provide excellent thermal performance through efficient heat paths to the PCB.
Packages with ePADs are very popular due to their low cost. Note that this section only provides basic information and references in regards to the ePAD. It is recommended that each customer consult their Fab and assembly house to obtain more details on how to implement the ePAD package design. Each fab and assembly house might need to tune the land pattern/stencil and create a solution that best suits their methodology and process.
PCB Design Requirements
In order to maximize both heat removal and electrical performance, a land pattern must be incorporated on the PCB within the footprint of the package corresponding to the exposed metal pad or exposed heat slug of the package as shown in the following figures. Refer to the specific product datasheet for actual dimensions.
Due to the package size, a via-in-pad configuration must be used Figure 101 and Figure
102 are general guidelines see Figure 103 for -specific via-in-pad thermal pattern recommendations.
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Figure 102. Typical ePAD* Land Pattern
Figure 103. Typical Thermal Pad and Via Recommendations
Note:
Note:
Encroached and uncapped via configurations have voids less than the maximum allowable void percentage. Uncapped via provides a path for trapped air to escape during the reflow soldering process.
Secondary side solder bumps might be seen in an uncapped via design. This must be considered when placing components on the opposite side of the PHY.
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Figure 104. Recommended Thermal Via Patterns
B.3
B.4
Note:
Note:
Note:
Board Mounting Guidelines
The following are general recommendations for mounting a QFN-48 device on the PCB.
This should serve as the starting point in assembly process development and it is recommended that the process should be developed based on past experience in mounting standard, non-thermally/electrically enhanced packages.
Stencil Design
For maximum thermal/electrical performance, it is required that the exposed pad/slug on the package be soldered to the land pattern on the PCB. This can be achieved by applying solder paste on both the pattern for lead attachment as well as on the land pattern for the exposed pad. While for standard (non-thermally/ -electrically enhanced) lead-frame based packages the stencil thickness depends on the lead pitch and package co-planarity, the package standoff must also be considered for the thermally/ electrically enhanced packages to determine the stencil thickness. In this case, a stencil foil thickness in the range of 5 - 6 mils (or 0.127—0.152 mm) is recommended; likely or practically, a choice of either 5 mils or 6 mils. Tolerance wise, it should not be worse than ±0.5 mil.
Industry specialists typically use ±0.1-mil tolerance on stencil for its feasible precision.
The aperture openings should be the same as the solder mask openings on the land pattern. Since a large stencil opening may result in poor release, the aperture opening should be subdivided into an array of smaller openings, similar to the thermal land pattern shown in Figure 104.
Refer to the specific product datasheet for actual dimensions.
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Figure 105. Stencil Design Recommendation
B.5
Assembly Process Flow
Figure 105 shows the typical process flow for mounting packages to the PCB.
Figure 106. Assembly Flow
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B.6
Reflow Guidelines
The typical reflow profile consists of four sections. In the preheat section, the PCB assembly should be preheated at the rate of 1 to 2 °C/sec to start the solvent evaporation and to avoid thermal shock. The assembly should then be thermally soaked for 60 to 120 seconds to remove solder paste volatiles and for activation of flux.
The reflow section of the profile, the time above liquidus should be between 45 to 60 seconds with a peak temperature in the range of 245 to 250 °C, and the duration at the peak should not exceed 30 seconds. Finally, the assembly should undergo cool down in the fourth section of the profile. A typical profile band is provided in Figure 106, in which 220 °C is referred to as an approximation of the liquidus point. The actual profile parameters depend upon the solder paste used and specific recommendations from the solder paste manufacturers should be followed.
Figure 107. Typical Profile Band
Note:
4.
5.
6.
7.
Notes:
1.
2.
3.
Preheat: 125 °C -220 °C, 150 - 210 s at 0.4 k/s to 1.0 k/s
Time at T > 220 °C: 60 - 90 s
Peak Temperature: 245-250 °C
Peak time: 10 - 30 s
Cooling rate: <= 6 k/s
Time from 25 °C to Peak: 240 – 360 s
Intel recommends a maximum solder void of 50% after reflow.
Contact your Intel representative for any designs unable to meet the recommended guidance for E-pad implementation.
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