PQI DiskOnModule Datasheet


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PQI DiskOnModule Datasheet | Manualzz

DG Series Datasheet

Revision History

Revision No History

A.0 First document announced.

Draft Date Remark

01/26/05 Preliminary

TABLE OF CONTENTS

1. Description…………………………………………………….……. 1

2. Features………………………………………………………….…. 1

3. Introduction………………………………………………….……… 2

4. Revision History..........................................................……....... 2

5. Specification………………………………………………..…….... 3

6. Installation Guide………………………………………………….. 5

7. Block Diagram………….……………………………………….…. 7

8. Pin Signal Assignment………………….………………………… 9

9. Interface Signal Assignments….……………..…….……………. 10

10. Signal Description………………...………………………...….…. 11

11. Interface Register Definition……………….…..…….……..……. 13

12. Physical Outline……………………………………………..…….. 16

Power Quotient International

IC STORAGE SPECIALIST

DiskOnModule

TM

DG Series

Description

PQI’s DiskOnModule DG series based on NAND type flash memory controller technology. This product complies with 44 PIN IDE (ATA) standard interface and is suitable for data storage memory medium for portable system. By using DiskOnModule it is possible to operate good performance for the portable system which have IDE interface slots.

Features

• High Performance

• Non-volatile Flash Memory

The DOM is implemented by using NAND type flash memory, which is a high density, non-volatile read/write device. Flash data retention is guaranteed for at least 10 years, with no battery or other power source required.

• 100% True IDE Mode HDD Compatible

• Broad Operating System and Processors Supports

• Capacities 16MB~1.5GB

• Low Power Consumption

• Robust Error Correction

• High Reliability

1

Introduction

1.About This Manual

This manual provides instructions for the installation and specification of PQI's

DiskOnModule, DiskOnModule is designed for use in PCs, and their respective compatible computers.

2.What is DiskOnModule?

PQI's DiskOnModule is a storage device based on flash memory technology, which emulates an ordinary magnetic hard disk. The DiskOnModule series products provide an all in one module solution for solid-state flash disk. The DiskOnModule is suitable for use in portable and embedded systems which have limited space and power consumption.

Unlike standard IDE drives, no signal cable and extra, special space is required. The DiskOnModule is a solid-state solution for IDE Hard Disk drive, which has no moving parts. That provides a good stability in a moving system.The

DiskOnModule products are also free from extra and special algorithm or some firmware driver. Just plug the DiskOnModule into the IDE slot and play it,users can play the DiskOnModule as same as the Hard Disk Drives.

The DiskOnModule family provides the capacities ranging from 16MB up to

2GB. In the future, the capacity will be increased up to 4GB.

2

Specification

Environment Specifications

Temperature (Industrial) Operating

Non-Operating

Temperature (WideTemp) Operating

Non-Operating

Relative Humidity

Shock

Configuration

Capacity

Sector size

Operating

Non-operating

0 to +70

-40 to +85

-40 to +80

-55 to +95

8% to 95% (with no condensation)

1000G

1000G

16Mbytes to 1.5Gbytes

512bytes

System Performance

Media transfer rate *note1

Interface burst transfer rate

PIO mode 2

Read

Write

4.3 MB/sec

3.3 MB/sec

8.3 MB/sec

Reliability

MTBF

ECC

1,000,000 hours

22bit per 256bytes

Power Requirement

Voltage DC +3.3V± 5%

DC +5.0V±10%

Power Consumption

Read 30mA (typ.)

Write 28mA (typ.)

Stand by 3mA (typ.)

*note1 : There will be different figures shown in different platforms.

3

Capacity Specifications

Capacity Cylinder

16MB 1000

32MB

64MB

128MB

192MB

256MB

512MB

1024MB

1536MB

500

500

500

750

1000

1015

2031

3047

16

16

16

16

Head

2

8

8

16

16

Sector

16

16

32

32

32

32

63

63

63

Total sectors

32000

64000

128000

256000

384000

512000

1023120

2047248

3071376

4

Installation Guide

BEFORE YOU BEGIN

To protect your DOM from static discharge by making sure you are well grounded before touching the DOM. We recommend wearing a grounded wrist strap throughout the installation process.

STEP 1

1. Make sure your computer is turned off before you open the case.

2. Plug the DOM carefully into the IDE slot on your computer or host adapter.

Caution: Make sure to align pin1 on the computer or host adapter interface connector with pin 1 on your DOM. Pin 1 is indicated by a triangle on the DOM connector.

3.Connect the power cable of the DOM to an unused power connector of the computer.

Caution: If you need to remove your DOM, use BOTH HANDS to carefully pull out it.

4.Check all cable connections and then replace your computer cover.

STEP 2

Before you format or partition your new DOM, you must configure your computer's

BIOS so that the computer can recognize your new DOM.

1.Turn your computer on. As your computer start up, watch the screen for a message describing how to run the system setup program (sometimes called BIOS or CMOS setup). This is usually done by pressing a special key, such as DELETE,ESC, or F1, during startup. See your computer manual for details. Press the appropriate key to run the system setup program.

2.If your BIOS provides automatic drive detection (an "AUTO" drive type), select this option. (If you use Normal/CHS mode to partition your DOM, you can get the maximum formatted capacity.)

This allows your computer to configure itself automatically for your new DOM.

If your BIOS dose not provide automatic drive detection, select "User-defined" drive setting and enter the CHS values from the table.

BIOS Settings (see specification)

Capacity Cylinders Heads Sectors

(unformatted)

3. Save the settings and exit the System Setup program.

(your computer will automatically reboot)

After you configure your computer, you can use the standard DOS commands to partition and format your DOM, as described below.

STEP 3

To partition your new DOM, for example use Microsoft® DOS program :

1. Insert a bootable DOS diskette into your diskette drive and restart your computer.

2.Insert a DOS program diskette that contains the FDISK.EXE

and FORMAT.COM

programs into your diskette drive. Use the same DOS version that is on your bootable diskette. At the A: prompt, type FDISK and press ENTER .

3.If you have two IDE devices installed, the FDISK menu displays five options.

5

Option five allows you to select the drive you want to partition. Make sure that your new drive is selected.

4.Select "Create DOS partition or logical DOS drive" by pressing 1. Then press

ENTER.

5.Select " Create primary DOS partition " by pressing 1 again. Then press ENTER .

Create your first drive partition. If you are creating a partition that will be used to boot your computer (drive C), make sure that the partition is marked active.

6.Create an extended partition and additional logical drives as necessary, until all the space on your new hard drive has been partitioned.

7.When the partitioning is complete, FDISK reboots your computer.

Caution: Make sure to use the correct drive letters so that you do not format a drive that already contains data.

8.At the A: prompt, type format c:/s , where c is the letter of your first new partition,

Repeat the format process for all the new partitions you have created.

9.After you format your DOM, it is ready to use.

6

Master/Slave

External Option

X`tal

DATA

FLASH

ARRAY

Block Diagram

Regulator

ATA(IDE)

Interface

Hvcc

Vcc

DD0 to DD15

CS0, CS1

RESET

DA0 to DA2

DIOR

DIOW

INTRQ

IORDY

Flash

Controller

DATA

BUFFER

Flash memory bus

DASP , PDIAG

Control signal

7

About Our Flash Management

In order to gain the best management for flash memory, PQI DiskOnModule supports an efficient and swift algorithm. Due to the life of flash memory is limited, PQI try to increase the life of our flash product through the following arrangement. There are some blocks are reserved in flash memory and these blocks would not be used in normal operation. Once any block is fail, one of these reserved blocks will replace it and the data of the fail block would be transferred to the reserved block for keeping the data’s accuracy. After we used the above arrangement in flash memory, the life of the device will be longer than the device without it. When all of the reserved blocks have replaced t he b a d bl o c k s , t h e d e v i c e wi l l b e l o c k ed au t o m a t i c al l y t o p r ev e nt programming, but the data can still be read out for back up.

Because the block of flash memory has a limited life, when the host writes data in the same address, PQI DiskOnModule does not to program data into the same physical place of the flash memory in purpose, our algorithm will get the data precisely when the host wants to read the data.

ECC (Error Correction Code) feature also be built in our hardware and firmware, it will correct 1 bit errors, and detect 2 bits errors when they happened. ECC ensured the accuracy of the data, and decreased the effect of the cross talking on the bus.

8

Pin Signal Assignment

The signals assigned for 44/40-pin applications are described in Table 1

Table 1 – Signal assignments for 44-pin ATA

Signal name Connector contact

Conductor Connector contact

RESET- 1 1 2 2

Signal name

Ground

DD7

DD6

3

5

3

5

4

6

4

6

DD8

DD9

DIOW-

DIOR-

IORDY

DMACK-

INTRQ

DA1

DA0

DD5

DD4

DD3

DD2

DD1

DD0

Ground

DMARQ

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

CS0- 37 37 38 38

DASP-

+5 V (logic)

(see note)

Ground(return)

(see note)

39

41

43

39

41

43

40

42

44

NOTE – Pins which are additional to those of the 40-pin cable.

40

42

44

16

18

20

22

8

10

12

14

32

34

36

24

26

28

30

DD10

DD11

DD12

DD13

DD14

DD15

(keypin) or Vcc

Ground

Ground

Ground

CSEL

Ground reserved

PDIAG-

DA2

CS1-

Ground

+5 V (Motor)

(see note)

TYPE- (0=ATA)

(see note)

9

Interface Signal Assignments And Descriptions

Signal summary

The physical interface consists of receivers and drivers communicating through a set of conductors using an asynchronous interface protocol. Table 2 defines the signal names.

Description

Cable select

Chip select0

Chip select1

Table 2 - Interface signal name assignments

Host Dir Dev Acronym

(see note) CSEL

CS0-

CS1-

DD0 ~ DD15 Data bus bit 0 ~ Data Bus bit 15

Device active or slave (Device 1) present

Device address bit 0

Device address bit 1

(see note) DASP-

DA0

DA1

Device address bit 2

DMA acknowledge

DMA request

Interrupt request

I/O read

I/O ready

I/O write

DA2

DMACK-

DMARQ

INTRQ

DIOR-

IORDY

DIOW-

Passed diagnostics

Reset

(see note) PDIAG-

RESET-

NOTE – See signal descriptions for information on source of these signals

10

Signal Descriptions

CS0- (CHIP SELECT 0)

This is the chip select signal from the host used to select the Command Block registers.

CS1 – (CHIP SELECT 1)

This is the chip select signal from the host used to select the Control Block registers.

DA2, DA1, AND DA0 (DEVICE ADDRESS)

This is the 3-bit binary coded address asserted by the host to access a register or data port in the device.

DASP – (Device active, device 1 present)

This is a time-multiplexed signal which indicates that a device is active, or that Device 1 is present. This signal shall be an open collector output and each device shall have a 10 k pull-up resistor.

If the host connects to the DASP- signal for the illumination of an LED or for any other purpose, the host shall ensure that the signal level seen on the ATA interface for DASP- shall maintain

V

O H

and V

O L

compatibility, given the I

O H

and I

O L

requirements of the DASP- device drivers.

DD (15:0) (Device data)

This is an 8- or 16-bit bi-directional data interface between the host and the device. The lower 8 bits are used for 8-bit register transfers.

DIOR- (Device I/O read)

This is the read strobe signal from the host. The falling edge of DIOR- enables data from the device onto the signals, DD (7:0) or DD (15:0). The rising edge of DIOR- latches data at the host and the host shall not act on the data until it is latched.

DIOW- (Device I/O write)

This is the Write strobe signal from the host. This rising edge of DIOW- latches data from the signals, DD (7:0) or DD (15:0), into the device. The device shall not act on the data until it is latched.

DMACK- (DMA acknowledge)

This signal shall be used by the host in response to DMARQ to initiate DMA transfers.

DMARQ (DMA request)

This signal, used for DMA data transfer between host and device, shall be asserted by the device when it is ready to transfer data to or from the host. The direction of data transfer is controlled by DIOR- and DIOW-. This signal is used in a handshake manner with DMACK- i.e., the device shall wait until the host asserts DMACK- before negating DMARQ, and re-asserting DMARQ if there is more data to transfer.

This line shall be released (high impedance state) whenever the device is not selected or is selected and no DMA command is in progress. When enabled by DMA transfer, it shall be driven high and low by the device.

When a DMA operation is enabled, CS0- and CS1- shall not be asserted and transfers shall be 16-bits wide.

11

INTRQ (Device interrupt)

This signal is used to interrupt the host system. INTRQ is asserted only when the device has a pending interrupt, the device is selected, and the host has cleared the nIEN bit in the Device

Control register. If the nIEN bit is equal to one, or the device is not selected, this output is in a high im pedance state, regardless of the presence or absence of pending interrupt.

The pending interrupt condition shall be set by: the completion of a command; or at the beginning of each data block to be transferred for PIO transfers except for the first data block for FORMAT TRACK. WRITE SECTOR(S), WRITE BUFFER, and WRITE LONG commands.

The pending interrupt condition shall be cleared by: assertion of RESET-; or the setting of the SRST bit of the Device Control register; or the host writing the Command register; or

The host reading the Status register.

IOCS 16- (Device 16-bit I/O)

Obsolete.

IORDY (I/O channel ready)

This signal is negated to extend the host transfer cycle of any host register access (Read or Write) when the device is not ready to respond to a data transfer request.

If actively asserted, the signal only be enabled during DIOR-/DIOW- cycles to the selected device. If open collector, when IORDY is not negated, it shall be in the high-impedance

(undriven) state.

This use of IORDY is required for PIO modes 3 and above and otherwise optional.

PDIAG - (Passed diagnostics)

This signal shall be asserted by Device 1 to indicate to Device 0 that it has completed diagnostics. A 10 k pull-up resistor shall be used on this signal by each device.

The host shall not connect to the PDIAG-signal.

RESET- (Device reset)

This signal from the host system shall be asserted beginning with the application of power and held asserted until at least 25 s after voltage levels have stabilized within tolerance during power on and negated thereafter unless some event requires that the device(s) be reset following power on.

ATA devices shall not recognize a signal assertion shorter than 20 ns valid reset signal.

Devices may respond to any signal assertion greater than 20 ns, and shall recognize a signal equal to or greater than 25 s.

CSEL (Cable select)

The device is configured as either Device 0 or Device 1 depending upon the value of

CSEL.

12

Interface Register Definitions And Descriptions

Device addressing considerations

In traditional controller operation, only the selected device receives commands from the host following selection. In this standard, the register contents go to both devices (and their embedded controllers.) The host discriminates between the two by using the DEV bit in the

Device/Head register.

Data is transferred in parallel either to or from host memory to the device’s buffer under the direction of commands previously transferred from the host. The device performs all of the operations necessary to properly write data to, or read data from, the media. Data read from the media is stored in the device’s buffer pending transfer to the host memory and data is transferred from the host memory to the device’s buffer to be written to the media.

The devices using this interface shall be programmed by the host computer to perform commands and return status to the host at command completion. When two devices are daisychained on the interface, commands are written in parallel to both devices, and for all except the EXECUTE DEVICE DIAGNOSTICS command, only the selected device executes the command. On an EXECUTE DEVICE DIAGNOSTICS command addressed to Device 0, both devices shall execute the command, and Device 1 shall post its status to

Device 0 via PDIAG-.

Devices are selected by the DEV bit in the Device/Head register. When the DEV bit is equal to zero, Device 0 is selected. When the DEV bit is equal to one, Device 1 is selected.

When devices are daisy chained, one shall be set as Device 0 and the other as Device 1.

I/O register descriptions

Communication to or from the device is through an I/O Register that routes the input or output data to or from registers addressed by the signals from the host (CS0-, CS1-, DA

(2:0), DIOR-, AND DIOW-).

The Command Block Registers are used for sending commands to the device or posting status from the device. The Control Block Registers are used for device control and to post alternate status.

Anytime a command is in progress, that is, from the time the Command register is written until the device has completed the command and posted ending status, the device shall have either

BSY or DRQ set to one. If the Command Block registers are read by the host when BSY or

DRQ is set to one, the content of all register bits and fields except BSY and DRQ in the Status and Alternate Status registers is indeterminate. If the host writes to any Command Block r egis t er wh en BS Y o r DRQ is set t o o ne, th e res ults are ind et erm in at e and may result in the command in progress ending with a command abort error.

When performing PIO transfers, BSY and DRQ shall both be cleared to zero within 400 ns of the transfer of the final byte of data. This assertion signals the completion of a PIO data transfer command.

Table 3 lists these registers and the addresses that select them.

13

N N

Table 3 - I/O port functions and selection address

Addresses

CS0- CS1- DA2 DA1 DA0

× × ×

Functions

Read (DIOR-) Write (DIOW-)

N

N

N

N

A

A

A

A

A

A

A

A

N

N

N

N

0

1

1

1

0

0

0

0

×

0

1

1

0

0

1

1

×

×

0

1

0

1

0

1

Data bus high impedance

Note used

Control block registers

Data bus high impedance

Note used

Data bus high impedance

Alternate Status

(see note1)

Note used

Device Control

Not used

Command block registers

Data

Error

Sector Count

Sector Number

LBA (7:0) (see note 2)

Data

Features

Sector Count

Sector Number

LBA (7:0) (see note 2)

A

A

A

N

N

N

1

1

1

0

0

1

1

×

0

1

0

1

×

Cylinder Low

LBA (15:8) (see note 2)

Cylinder High

LBA (23:16) (see note 2)

Device/Head

LBA (27:24) (see note 2)

Cylinder Low

LBA (15:8) (see note

2)

Cylinder High

LBA (23:16) (see note

2)

Device/Head

LBA (27:24) (see note

2)

Command

Invalid address

A

A

N

A

1

×

Status

Invalid address

Key:

A = signal asserted, N = signal negated, × = don’t care

NOTES_

1 This register is obsolete. It is recommended that a device not respond to a read of this address. If a device does respond, it shall not drive the DD7 signal to prevent possible conflict with floppy disk implementations.

2 Mapping of registers in LBA translation.

Each register description in the following clauses contain the following format:

ADDRESS – the CS and DA address of the register.

DIRECTION – indicates if the register is read/write, read only, or write only from the host.

ACCESS RESTRICTIONS – indicates when the register may be accessed.

EFFECT – indicates the effect of accessing the register.

FUNCTIONAL DESCRIPTION – describes the function of the register.

FIELD/BIT DESCRIPTION – describes the content of the register.

14

[Duplicate Data, Error and Feature register]

During word access, the address space occupied by the Data Register interferes with the space occupied by the Error register and Feature register, and reference cannot be made to these registers. Therefore, the PC Card ATA Standard provides an area where the copy of each register does not duplicate in the contiguous I/O mode and memory map mode. The even-numbered address of the data register is provided in the offset "08h", and the odd-numbered address of the data register is located in the offset "09h". The copy of

Error/Feature register is provided at the ODh.

Duplicate Data register

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Data Word

Odd Data Byte Only Even or Even-Odd Data Byte

Duplicate registers Access

Data register

Word Data register

Word Data register

Even Byte Data register

Odd Byte Data register

Odd Byte Data register

Error/Feature register

Error/Feature register

Error/Feature register

CE2#

0

0

1

1

0

1

0

0

CE#

0

0

0

0

1

0

1

0

A0

0

1

0

1

×

1

×

×

Offset

0h,8h

1h,9h

0h,8h

9h

8h,9h

1h,0Dh

0h,1h

0Ch,0Dh

Data Bus

D15-D0

D15-D0

D7-D0

D7-D0

D15-D8

D7-D0

D15-D8

D15-D8

Initial value of task file register

After resetting and execution of the Execute Device Diagnostic command, the task file register is initialized as follows:

Sector Count register 01h

Sector Number register 01h

Cylinder Lo register 00h

Cylinder High register 00h

A0h Device/Head register

15

Physical Outline

DG0XXXX44NX0 (44 PIN)

A

MASTER

SALVE

A Detail S=2:1

M

S

16

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