Adlink cPCI-6840 6U CompactPCI® Highly Integrated Intel® Pentium® M Processor PCI™ 64-bit/66 MHz Universal Blade Owner's Manual
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cPCI-6840 Series
6U CompactPCI Pentium M
Single Board Computer
User’s Manual
Manual Rev. 2.20
Revision Date: August 5, 2008
Part No: 50-15031-2030
Advance Technologies; Automate the World.
Revision History
Revision Release Date
2.00
2.10
2.20
2005/01/19
2005/06/15
2008/08/05
Description of Change(s)
Initial Release
Correct specification errors, typos
Update CPU support, GbE Controller version,
Baseboard Management Controller, add cPCI-R6841P, IPMI instructions
cPCI-6840
Preface
Copyright 2008 ADLINK Technology Inc.
This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK.
We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.
Trademarks
Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.
Preface iii
iv
Using this Manual
Audience and Scope
The cPCI-6840 User’s Manual is intended for hardware technicians and systems operators with knowledge of installing, configuring and operating industrial grade CompactPCI modules.
Manual Organization
This manual is organized as follows:
Introduces the cPCI-6840, its specifications, features, and package contents.
Chapter 2, Jumpers and Connectors: Presents the board
layout, connector pin assignments, and jumper setup.
Explains how to install necessary components on the cPCI-6840.
Chapter 4, Windows Driver Installation:
Describes the driver installation procedures.
Describes the operation of the cPCI-6840’s watchdog timer and PXE Environment.
Describes the Intelligent
Platform Management Interface.
Important Safety Instructions: Presents safety instructions
all users must follow for the proper setup, installation and usage of equipment and/or software.
Contact information for ADLINK’s worldwide offices.
Preface
cPCI-6840
Conventions
Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.
Additional information, aids, and tips that help users perform tasks.
CAUTION:
Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.
WARNING:
Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.
Preface v
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vi Preface
cPCI-6840
Table of Contents
Revision History...................................................................... ii
Preface .................................................................................... iii
Table of Contents.................................................................. vii
List of Tables.......................................................................... ix
List of Figures ........................................................................ xi
1 Introduction ........................................................................ 1
Main Functions .................................................................... 3
Features............................................................................... 8
Product List.......................................................................... 9
Specifications..................................................................... 11
Unpacking Checklist .......................................................... 18
2 Jumpers and Connectors ................................................ 19
cPCI-6840 and cPCI-6840V Board Outline ....................... 20
cPCI-6840/V Connector Pin Assignments ......................... 22
cPCI-6840/V Switch and Jumper Settings......................... 34
RTM Board Outline ............................................................ 36
RTM Connectors Pin Assignments.................................... 38
RTM Switch and Jumper Setting ....................................... 45
3 Getting Started ................................................................. 47
CPU and Heatsink ............................................................. 48
Memory Module Installation ............................................... 49
HDD Installation on Main Board – for cPCI-6840 .............. 50
HDD Installation on Main Board – for cPCI-6840V............ 52
HDD Installation on RTM ................................................... 54
CF Installation on RTM ...................................................... 54
PCI Mezzanine Card (PMC) Installation ............................ 54
RTM Installation................................................................. 55
Main Board Installation ..................................................... 55
4 Windows Driver Installation ............................................ 57
Chipset Drivers Installation ................................................ 57
VGA Driver Installation ...................................................... 58
LAN Driver Installation ....................................................... 58
Table of Contents vii
5 Utilities ............................................................................... 59
Watchdog Timer................................................................. 59
Intel Preboot Execution Environment (PXE) ...................... 64
6 IPMI User Guide ................................................................ 65
Introduction ........................................................................ 65
Summary of Commands Supported by BMR-AVR-cPCI ... 65
OEM Commands Summary Table ..................................... 67
CompactPCI Address Map ................................................ 71
IPMI Sensors List............................................................... 71
Known Issues..................................................................... 72
Relevant Documents.......................................................... 72
Important Safety Instructions............................................... 73
Getting Service ...................................................................... 75
viii Table of Contents
cPCI-6840
List of Tables
Table 1-1: cPCI-6840 Configurations ........................................ 9
Table 1-2: Power Ratings ........................................................ 14
Table 1-3: I/O Connectivity Table ............................................ 17
Table 2-1: Ethernet LED Status ............................................... 22
Table 2-2: Switch and Jumper Functions ................................ 34
Table 2-3: JP1 Settings ........................................................... 34
Table 2-4: JP3 Settings ........................................................... 35
Table 2-5: RTM Switch and Jumper Settings .......................... 45
Table 2-6: LAN Dip Switch Settings ......................................... 45
Table 2-7: CF Master/Slave Jumper Settings .......................... 46
Table 2-8: cPCI-R6841(P) Switch Settings .............................. 46
Table 2-9: JP3 Settings ........................................................... 46
Table 3-1: DDR SDRAM Memory Capacity ............................. 49
List of Tables ix
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x List of Tables
cPCI-6840
List of Figures
Figure 1-1: cPCI-6840 Block Diagram ......................................... 2
Figure 2-1: cPCI-6840 Front and Top View ............................... 20
Figure 2-2: cPCI-6840V Front and Top View............................. 21
Figure 2-3: cPCI-R6840 Board Layout....................................... 36
Figure 2-4: cPCI-R6841P Diagram ............................................ 37
Figure 3-1: Heatsink installation................................................. 48
Figure 3-2: cPCI-6840 2.5” Hard Disk Installation ..................... 51
Figure 3-3: cPCI-6840V 2.5” Hard Disk Installation ................... 53
Figure 5-1: WDT Block Diagram ................................................ 59
List of Figures xi
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xii List of Figures
cPCI-6840
1 Introduction
The cPCI-6840 is a 6U CompactPCI single board computer based on Intel® Pentium® M processor, 855GME and 6300ESB chipset.
The Pentium® M processor comes with 1MB L2 cache in FCmPGA package. The operating frequency ranges from 1.3GHz up to 1.6GHz. The cPCI-6840 is designed to be forward compatible with future 1.7GHz or higher speed Pentium® M compatible processor. The combination of the longevity of the Intel® 855GME and 6300ESB chipset and low power consumption of the Pentium® M CPU make the cPCI-6840 the best solution for embedded applications.
The 855GME supports 400MHz FSB and DDR333 memory up to
2GB. Two 200 pins SO-DIMM sockets support up to a maximum
2GB DIMM with 144-bit wide PC2700 registered DDR memory. A
32-bit 3D graphic controller is integrated to provide analog VGA or
LVDS output.
The low power consumption 6300ESB south bridge provides dual
PCI buses (PCI 64 bit/66-MHz and 32-bit/33MHz) to maximize I/O bandwidth. The I/O features are highly integrated, including four
USB 2.0 port, two UART, two E-IDE channels, two Serial ATA ports, and a watchdog timer.
The 6300ESB’s PCI 64 bit/66 MHz bus connects to two PMC sites, a dual port GbE controller 82546GB, and the universal PCIto-PCI bridge PLX PCI-6540. The two 64-bit/66MHz PMC sites provide extreme expansion capability and flexibility for varieties of applications. The upper PMC site provides the rear I/O (Jn4 of
PMC) capability for either SCSI PMC or telecom PMC modules.
The CompactPCI bus is based on the universal PCI-to-PCI bridge chip PCI-6540 (made by PLX Technology), providing either a transparent or non-transparent PCI interface. cPCI-6840 can be used as either a system slot or peripheral slot. cPCI-6840 can also be a server blade for stand alone operation on any non-system slot (without PCI bus). The cPCI-6840 is hot-swappable on peripheral slot or non-PCI bus slot which provide the best MTTR performance for telecom applications.
The cPCI-6840 is equipped with three Gigabit Ethernet (GbE) ports. Two GbE ports use the 82546GB dual ports GbE controllers
Introduction 1
on the 66MHz PCI bus to achieve the full communication bandwidth between the LAN and CPU. These two ports are connected to J3 (or rear I/O) which conform to the PICMG 2.16 specification.
The third LAN port uses a 82541PI GbE controller on the 32bit/33MHz PCI bus.
A Management Controller (BMC) (which follows the Intelligent
Platform Management Interface (IPMI) v1.0 specification), is built into the system to meet the demands of high reliability and serviceability.
Please refer to the following block diagram for the cPCI-6840 architecture.
RGB DB-15
OUTPUT
LVDS A
J3
J3
RGB
J3
LVDS A
CHRONTEL
CH7301A-T
DVO TO DVI
DVO C
USB2.0 0/1
USB2.0 2/3
SIDE
PIDE
SATA J5
J3
J5
PSB
100MHz
4x
NORTH
BRIDGE
855GME
HI1.5
66MHz
4x
SOUTH BRIDGE
HANCE RAPIDS
6300ESB
J5
BMC
FWH
KBMS
J3
KBMS
DDR SODIMM x2
TOTAL MAX 2GB
GIGA LAN
82541
SINGLE PORT
J5
PIM or
RIO
Figure 1-1: cPCI-6840 Block Diagram
GIGA LAN
82546
DUAL PORT
UNIVERSAL
BRIDGE
PLX PCI6540
J3
PICMG 2.16
OR
REAR IO
2 Introduction
cPCI-6840
1.1
Main Functions
The following sections explain the main functions on cPCI-6840
CPU Support
The cPCI-6840 SBC is designed for the Intel® Pentium® M and
Celeron® M Processors. The standard cPCI-6840 SBC comes with CPU socket which can be installed with
μ
FC-PGA2 package
CPU, with the following options:
X
X
Pentium® M 1.3GHz, 1.4GHz, 1.5GHz, 1.6GHz, 1.7GHz,
1.8GHz, and 2.0GHz
Celeron® M 1.3GHz
The Low Voltage (LV) or Ultra Low Voltage (ULV) version of the
Pentium® M or Celeron® M Processors, which are in
μ
FCBGA2 packages, can also be mounted on the cPCI-6840 SBC. However,
μ
FCBGA2 CPU support is reserved for OEM programs only. The possible CPU options include:
X
X
LV Pentium® M 1.1, 1.2, 1.3GHz
ULV Celeron® M 600MHz
CompactPCI Bus Interface
The PLX Technology PCI-6540 is a tri-mode universal PCI-to-PCI
Bridge and is used to implement the system/peripheral slot on the cPCI-6840. The tri-mode bridge is capable of operating in Transparent, Non-Transparent or Universal mode. The PCI-6540 Non-
Transparent mode permits independent memory mapping of both primary and secondary buses with powerful configuration options to support intelligent subsystems. The Universal mode permits jumper-less configuration between application to CompactPCI interface at Peripheral Slot and System Slot. With the Universal option, the PCI-6540 Bridge can be configured as a transparent bridge in a System Slot supporting a host, or as a Non-Transparent bridge in a Peripheral Slot as an intelligent subsystem. These options allow the cPCI-6840 board to be inserted into both the
Peripheral Slot and the System Slot.
The cPCI-6840 CompactPCI bus supports up to 64 bit/66 MHz
PCI, as well as allowing the host bus and subsystem bus to
Introduction 3
4 operate at different speeds. Together with 64-bit to 32-bit access conversion, system architects can utilize the bridge and connect slower or higher speed controllers on primary or secondary bus, hence supporting independent speed and data bus frequency on either side of the PCI bus. The 64-bit/66 MHz PCI bus is backward compatible with 64-bit/33 MHz PCI, 32-bit/66 MHz PCI and 32bit/33 MHz PCI busses. The SBC design is compliant with the
PICMG 2.1 hot-swap specification so it can be hot-swappable in the peripheral slots. The cPCI-6840 can also be a hot-swappable server blade for stand alone operation on any non-PCI backplane without a system slot.
PCI Mezzanine Card (PMC) Interface
The cPCI-6840 supports up to two PMC slots at 64-bit/66 MHz
PCI, providing expansion capability and flexibility for varieties of applications. The Jn4 rear I/O of the upper PMC site (PMC2) are implemented by connecting to the CompactPCI J5 connector, which complies with the PICMG 2.3 specification.
When the ADLINK SCSI PMC module (PMC-8631) is installed in
PMC2 along with the cPCI-R6840 RTM, it can provide SCSI-320 interfaces on the rear panel of the Rear I/O Transition Module
(RTM) for external storage devices. Some telecom PMC modules may also utilize the J24 rear I/O connection and the PMC Interface
Module (PIM) site on the RTM to provide telecom I/O connection on the rear panel. The cPCI-R6841P RTM provides a PIM site.
IDE Interfaces
The cPCI-6840 supports dual Ultra ATA100 IDE channels. Primary
IDE is implemented on the cPCI-6840 and Secondary IDE is routed to the RTM via J5 connector. Two 44-pin connectors for 2.5
inches IDE drives are reserved on both Primary and Secondary
IDE interfaces.
The space of lower PMC site (PMC1) shall be used for installing the 2.5 inches IDE HDD, flash disk, or a CompactFlash carrier baord, DB-6840CF. When an application installs a storage device on the SBC, the PMC1 is occupied. Also note that the PMC1 connectors are not available on the cPCI-6840V because its front panel is occupied by VGA and PS2 keyboard/mouse connectors.
Introduction
cPCI-6840
On the RTM, the Secondary IDE is implemented on a Compact-
Flash socket and a 44-pin connectors for 2.5 inches IDE drive.
Gigabit Ethernet Ports
The cPCI-6840 has three 10/100/1000Mbps Ethernet (GbE) ports.
Every port is assigned a unique static MAC Address.
The onboard Intel® 82546GB dual-port Gigabit Ethernet controller provides two Ethernet ports. The 82546GB is connected to the 64bit/66 MHz PCI bus to achieve the full communications bandwidth.
The 82546GB supports IEEE 802.3x compliant flow control and
IEEE 802.3ab compliant 10/100/1000 Mbps auto-negotiation. The two GbE ports are connected to J3 based on PICMG 2.16 specifications.
The third LAN port uses a 82541PI controller on the 32-bit/33 MHz
PCI bus. The RJ-45 connector of the third LAN port is on the front panel for system management or serviceability requirement. Users can disable or enable the third LAN port from the BIOS menu.
Universal Serial Bus (USB)
The cPCI-6840 provides four USB version 2.0 ports. Two ports are on the front panel and another two ports are on the RTM. The Universal Serial Bus (USB) provides a common interface to versatile peripherals such as keyboard, mouse, printer, USB flash disk, etc.
Serial I/O
Two serial ports are supported on cPCI-6840. COM1 is available as a RJ45 connector on the front panel. COM2 is also a standard
RJ-45 connector on the rear panel of RTM. Both ports are be configured as Data Terminal Equipment (DTE). Firmware initializes the two serial ports as COM1 and COM2 with ISA I/O base addresses of 3F8h and 2F8h respectively. This default configuration also assigns COM1 to IRQ4 and COM2 to IRQ3. Optional
COM3 and COM4 ports are available for ODM/OEM projects via the Winbond 83627HG. COM3 may be accessed via a cable, however COM4 may require a custom RTM.
Introduction 5
6
Keyboard/Mouse Controller
The cPCI-6840 uses a Winbond W83627HG to implement the keyboard/mouse controller. The controller is fully 8042 compatible.
The cPCI-6840V provides a combo PS2 connector on the front panel. Both cPCI-6840 and 6840V route the keyboard and mouse signals to the J3.
Power Ramp Circuitry
The cPCI-6840 features a power controller with power ramp circuitry to allow the board's voltages to be ramped in a controlled fashion. The power ramp circuitry eliminates any large voltage or current spikes caused by hot-swapping boards. This controlled ramping is a requirement of the CompactPCI hot-swap specification, PICMG 2.1 Version 1.0. The cPCI-6840's power controller unconditionally resets the board when it detects that the 3.3V, 5V, and 12V supplies are below an acceptable operating limit. These limits are defined as 4.75V (5V supply), 3.0V (3.3V supply), and
10.0V (+12V supply).
Watchdog Timer
Application can utilize watchdog timer to monitor system operation and to recover the operation when an abnormal and unexpected occurrence arises. The timeout period of the watchdog timer can be programmed from one micro second to ten minutes. Failure to strobe the watchdog timer within the programmed time period may result in an interrupt or reset request. A register bit can be enabled to indicate if the watchdog timer caused the interrupt or reset event. This watchdog timer register can be cleared by the system or auto-cleared after power-up, enabling system software to take appropriate action if the watchdog generated the reboot. Please refer Chapter 5, "Watchdog Timer," for more information.
Hardware Monitoring
The cPCI-6840 series use Winbond W83627HG to detect system voltages and temperatures. When it detects the voltages or temperatures over the safety range, it will inform the south bridge
6300ESB to send the signals out halting the system in order to protect the CPU board.
Introduction
cPCI-6840
Operating System Support
The cPCI-6840 is compatible with Microsoft® Windows 2000, Windows 2003 Server, Windows XP, Red Hat Linux 9 and VxWorks
5.5. The device drivers for Windows are included in the ADLINK
CD. For Linux support and VxWork BSP, please contact ADLINK.
Baseboard Management
A baseboard management controller is implemented such that the system manager can control or get status form cPCI-6840 through the Intelligent Platform Management Bus (IPMB). The firmware is based on the Intelligent Platform Management Interface (IPMI) specification version 1.5. Please refer to Chapter 6 for the IPMI
User Guide.
Introduction 7
8
1.2
Features
X Low power consumption, support Intel® Pentium® M and
Celeron® M CPU from 1.3G up to 1.6G, and forward compatible to future higher speed CPU.
X
X
X
X
X
X
X
Low power consumption Intel® 855GME and 6300ESB embedded chipset, provides longevity for OEM.
Compliant with PICMG 2.0, 2.1, 2.9, and 2.16 specifications.
64-bit/66MHz CompactPCI interface based on PCI specifications, universal operations as system slot SBC or peripheral SBC.
Two 64-bit/66MHz PMC sites, PMC rear I/O is reserved, optional PIM on RTM.
Two 200-Pin SODIMM sockets support up to 2GB PC2700
DDR ECC SDRAM.
Provides both IDE and Serial ATA interface for storage devices.
Full feature I/O ports, including VGA, KB, MS, four USB 2.0, two COM ports, optional DVI, SCSI.
Introduction
cPCI-6840
1.3
Product List
The cPCI-6840 series products include the following SBCs and
Rear I/O Transition Modules (RTM):
SBC
X
X cPCI-6840: Pentium® M SBC with two PMC sites cPCI-6840V: Pentium® M SBC with VGA/Keyboard/Mouse on the front panel, and one PMC site
RTM
X
X
X cPCI-R6840: RTM with SCSI rear I/O connector and DVI interface cPCI-R6841: RTM with IDE drive bay cPCI-R6841P: RTM with PMC Interface Module (PIM) site
The following table shows the possible combinations and configurations of cPCI-6840 SBC and RTM.
SBC
6840
6840V
RTM options none
R6840
R6841
R6841P none
R6840
R6841
R6841P
Front panel
VGA
KB/MS
SBC Features
PMC
Sites
RTM Features
IDE
(5)
HDD option
IDE
(5)
HDD option
PIM
Site
SCSI
(5)
and DVI connectors on rear faceplate
No
Yes
PMC1
(1,2)
PMC2
(3)
PMC1
(1)
PMC2
PMC1
(1)
PMC2
PMC1
(1)
PMC2
PMC2
PMC2
(3)
PMC2
PMC2
Yes
Yes
(1)
(1)
No
Yes
No
No
Yes
No
No
No
Yes
No
No
Yes
N/A
N/A
Yes
No
No
Yes
No
No
(3)
(3)
Table 1-1: cPCI-6840 Configurations
Introduction 9
Note 1 : When an IDE HDD is installed on the front board, it occupies the PMC1 (lower PMC) site.
Note 2 : When cPCI-6840 is functioning as a standalone without
RTM, the PMC1 site shall be occupied by IDE storage device.
Note 3 : The PMC-8631 is a SCSI-320 PMC module with rear I/O capability. When installing the PMC-8631 on the PMC2 (upper
PMC) site, the cPCI-R6840/6840V can provide SCSI interfaces on the RTM and rear faceplate.
Note 4 : The PIM will only work with a PMC module with rear I/O connectivity on PMC2 site.
Note 5 : Should the user choose the SBC and RTM configuration, first consider where the storage device will be installed. Users can choose external SCSI device, IDE device on the
RTM, or IDE device on the SBC.
10 Introduction
cPCI-6840
1.4
Specifications
cPCI-6840V SBC Specifications
CompactPCI Compliancy
X
X
X
X
X
X
PICMG 2.0 CompactPCI Rev. 3.0
PICMG 2.1 CompactPCI hot-swap specification R2.0
PICMG 2.3 PMC I/O R1.0
PICMG 2.9 System Management Bus
PICMG 2.16 CompactPCI Packet Switch Backplane R1.0
PCI Rev.2.1 compliant
Form Factor
X
X
Standard 6U CompactPCI (board size: 233.35mm x 160mm)
One slot (4TE or 4HP, 20.32mm) width
CPU/Cache
X
X
Single Intel® Pentium® M 1.6/1.8 GHz or Celeron® M
1.3GHz Processors with µFC-PGA package
1MB/2MB on die L2 cache, 400MHz FSB
Chipset
X
X
X
X
X
X
X
Intel® 855GME Graphic Memory Controller Hub (GMCH)
Intel® 6300ESB I/O Hub
Host Memory
X
X
Two SO-DIMM sockets, 2GB maximum
Suppprt DDR333 SDRAM
BIOS
X
Phoenix/Award Plug and Play BIOS with 4Mb Flash ROM
BIOS write protection, provide anti-virus capability
Bootable from USB storage devices including USB-Floppy,
USB-ZIP, USB-CD-ROM, and USB-HDD.
DMI BIOS Support: Desktop Management Interface (DMI)
Onboard Ethernet ports can be disabled by BIOS setting
(Intel® 82541PI Only)
Option OEM BIOS features
Z Customized OEM splash image / power on screen
Introduction 11
12
Due to BIOS limitations, enabling the remote console function may occupy the same memory space as other
ROM mapping add-on or boot-up devices such as Preboot Agent of Ethernet Boot ROM, SCSI Boot ROM, or add-on EIDE Boot ROM. It is recommended that only one ROM-mapping add-on or boot-up device be enabled when enabling the remote console function.
CompactPCI Bus Controller
X
X
X
PLXtech PCI-6540 Univeral PCI-to-PCI bridge, supports transparent and non-transparent mode
PCI Rev 2.1 compliant
Supports 64-bit/66 MHz, 64-bit/33 MHz, 32-bit/33 MHz, and
32-bit/33 MHz
Graphic
X
X
X
X
Integrated in 855GME Graphic Memory Controller Hub
Shared memory, up to 32MB
Dual channel display
Front panel analog VGA DB-15 connector is available on cPCI-6840V only.
X LVDS and analog VGA signals are available on the J3 for
RTM
Gigabit Ethernet
X
X
X
Three 10/100/1000bps Gigabit Ethernet ports
Dual GbE ports with Intel® 82546GB Ethernet controller, based on local 64-bit/66 PCI bus connected to J3 for Packet
Switched Backplane (PSB) or RTM rear access
Single GbE port with Intel® 82541PI Ethernet controller, based on 32-bit/33 PCI bus, RJ-45 connector on the front panel.
Onboard Peripherals
X Integrated in Intel® 6300ESB south bridge.
Introduction
cPCI-6840
X
X
Bus master IDE controller supports two ultra ATA-100 interfaces.
Z Primary IDE is on SBC with 44-pin IDE connector. A 2.5 inches IDE HDD can be mounted on the lower PMC site.
Z Secondary IDE ports is on J5 for RTM extension.
Four USB ports with USB Spec Rev. 2.0 compliant.
Z
Z
USB 0, 1 are on the front panel.
USB 2, 3 are on the RTM.
X
X
X
Z USB ports support 0.5A@5V for peripherals with individual over-current protection.
Two SATA ports on RTM with data transfer rates up to 150
MB/s.
Two RS-232 serial ports. COM1 on the front with RJ-45 type connector. COM2 is on the J3 and can be accessed on the
RTM.
PS2 keyboard / mouse connector on the front panel and
RTM.
Front Panel LED Indicators and Reset
X
X
Four LEDs on the front panel including storage access LED
(RED), Power LED (GREEN), hot-swap status (Blue), and
Watchdog timer LED (Yellow).
Flush tact switch for system reset.
IPMI Interface
X
X
Supports PICMG 2.9 secondary system managing bus.
Implements IPMI functions as defined in the IPMI specification v 1.5
Atmel ATMEGA128L Baseboard Management Controller
(BMC)
Real -Time Clock and Nonvolatile Memory
X
X
X
Build into Intel® 6300ESB southbridge RTC.
Battery-backed memory is used for BIOS configuration
Separate 3V coin cell CR2032 battery used for RTC and nonvolatile memory
Introduction 13
14
Environment
X
X
X
X
Operating temperature: 0 to 55°C
Storage temperature: -20 to 80°C
(1)
Humidity: 5% to 95% non-condensed
Shock: 15G peak-to-peak, 11ms duration, non-operation
X Vibration:
(2)
Z
Z
Non-operation: 1.88Grms, 5-500Hz, each axis
Operation: 0.5Grms, 5-500Hz, each axis, with 2.5” HDD
Safety Certificate and Test
X
X
CE, FCC Class A
X
All plastic material, PCB and Battery used are all UL-94V0 certified
Designed for NEBS 3.0 requirement
Power Requirement
(3)
Configuration +5V +3.3V +12V -12V Total
Single Pentium 1.6G 512MB RAM,
20GB HDD
10.0A
4.1A
0.2A
0 > 61.2W
Table 1-2: Power Ratings
Note 1 : Certified with ADLINK thermal design. The thermal performance is dependent on the chassis cooling design. Forced air-cooling with 50 CFM is required. Temperature limit of optional mass storage devices can impact the thermal specification.
Note 2 : Operational vibration is limited by the 2.5 inches HDD. When application requires higher definition for anti-vibration, we recommend using Flash disk or CompactFlash.
Note 3 : The power requirement is measured by Windows 2000 and a few computing power stressed application software. The following devices are installed when testing the power consumption: DDR333 RAM, a 20GB HDD, a 16MB CF, keyboard, mouse, and GbE. The power requirements for 5V and
3.3V rails are varied for different applications. This table lists the peak power requirement of 5V and 3.3V for different applications. The total power requirement is listed.
Introduction
cPCI-6840 cPCI-R6840 RTM Specifications
Form Factor
X
X
X
Standard 6U CompactPCI rear I/O (board size:
233.35x80mm2)
1-slot (4TE/HP, 20.32mm) wide
CompactPCI connectors: with rJ3 and rJ5, without rJ1, rJ2 and rJ4 connectors. AB type connector is used on rJ3 and rJ5.
Faceplate I/O Connectors
X
X
X
X
X
X
X
Two GbE ports on RJ-45 connectors
Serial COM2 ports on RJ-45 connectors
Two USB ports: USB2, USB3 (type A connector)
DVI connector
X
SCSI connector (need use with ADLINK PMC-8631 SCSI module)
DB-15 VGA connector
On Board Connectors
X IDE: Secondary IDE supported on one 44-pin connector, and one CompactFlash type-II socket.
Serial ATA: Two S-ATA connectors
LVDS cPCI-R6841, cPCI-R6841P Specifications
Form Factor
X
X
Standard 6U CompactPCI rear I/O (board size:
233.35x80mm2)
1-slot (4TE/HP, 20.32mm) wide
X CompactPCI connectors: with rJ3 and rJ5, without rJ1, rJ2 and rJ4 connectors. AB type connector is used on rJ3 and rJ5
Faceplate I/O Connectors
X
X
Two GbE ports on RJ-45 connectors
Serial COM2 ports on RJ-45 connectors
Introduction 15
X
X
X
X
X
Two USB ports: USB2, USB3 (type A connector)
VGA DB-15 connector
X PS2 Keyboard and Mouse connector
On Board Connectors
X IDE: Secondary IDE supported on one 44-pin connector, and one CompactFlash type-II socket. 2.5 inches HDD space is reserved (cPCI-R6841 only)
Serial ATA: Two SATA connectors
LVDS
PIM socket (cPCI-R6841P only)
16 Introduction
cPCI-6840
I/O Connectivity
I/O cPCI-6840
Faceplate
On board cPCI-6840V CPCI cPCI-R6840
Faceplate
On board
J3/
J5
On board
Faceplate
Serial Port
(COM1)
Serial Port
(COM2)
USB (port 0, port 1)
USB (port 2, port 3)
Gigabit Ethernet Port 1
Gigabit Ethernet Port 2
Gigabit Ethernet Port 3
Primary IDE
RJ-45
--
Y
--
--
--
RJ-45
--
--
--
--
--
2.16
2.16
--
44-pin
RJ-45
--
Y
--
--
--
RJ-45
--
--
--
--
--
2.16
2.16
--
44-pin
--
J3
--
J5
J3
J3
--
--
--
--
--
--
--
--
--
--
RJ-45
--
Y
RJ-45
RJ-45
--
--
Secondary
IDE
Reset button
PMC1 (lower)
--
Y
--
--
--
Y
--
Y
--
--
--
--
J5
--
--
--
40-pin
44-pin
CF
--
--
--
--
--
PMC2 (upper) -Y -Y J5 --cPCI-R6841(P)
On board
--
--
--
--
--
--
--
Faceplate
--
RJ-45
--
Y
RJ-45
RJ-45
--
--
40-pin
44-pin
CF
--
--
--
--
--
--
PIM
(cPCI-
R6841P only)
PIM
(cPCI-
R6841P only)
SCSI via
PMC2 J24
PS2 KB/MS
VGA
SATA
LVDS
--
--
--
--
--
--
--
--
--
--
Y --
Y --
DB-15
--
--
--
--
--
J5
J3
J3
J5
J3
SCSI
--
--
Y
Y
SCSI
--
DB-15
--
--
--
--
--
Y
Y
--
Y
DB-15
--
--
Table 1-3: I/O Connectivity Table
Introduction 17
18
1.5
Unpacking Checklist
Check the shipping carton for any damage. If the shipping carton and contents are damaged, notify the dealer for a replacement.
Retain the shipping carton and packing materials for inspection by the dealer. Obtain authorization before returning any product to
ADLINK.
Check the following items are included in the package, if there are any items missing, please contact your dealer:
SBC:
X
X
X
X
X
X
X
The cPCI-6840 or cPCI-6840V SBC (May be equipped with different specifications of CPU, RAM, and HDD).
This User’s Manual
ADLINK CD
X RJ45-DB9 Cable
RTM: cPCI-R6840, cPCI-R6841, or cPCI-R6841P RTM
HDD bracket and 44-pin IDE cable (cPCI-R6840/1 only)
SATA HDD cable and power cable
PS2 Y-cable (for cPCI-R6841(P) only)
The packaging of OEM versions with non-standard configuration, functionality, or package may vary according to different configuration requests.
CAUTION:
The boards must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the anti-static bag shipped with the product to handle the board. Wear a grounded wrist strap when servicing
Introduction
cPCI-6840
2 Jumpers and Connectors
This chapter illustrates the board layout, connector pin assignments, and jumper setup. Users should be familiar with the products before use. The following sections are included:
X
X
X
X
X
X cPCI-6840 and cPCI-6840V board outline cPCI-6840/6840V connectors pin assignments cPCI-6840/6840V jumpers setting cPCI-R684x series RTM board outline cPCI-R684x series RTM connectors pin assignments cPCI-R684x series RTM jumpers settings
Jumpers and Connectors 19
2.1
cPCI-6840 and cPCI-6840V Board Outline
20
Figure 2-1: cPCI-6840 Front and Top View
Jumpers and Connectors
cPCI-6840
Figure 2-2: cPCI-6840V Front and Top View
Jumpers and Connectors 21
22
2.2
cPCI-6840/V Connector Pin Assignments
USB Connectors
PIN
1
2
3
4
SIGNAL
VCC
USB-
USB+
Ground
Ethernet (RJ-45) Connector
Pin # Signal Name
7
8
5
6
3
4
1
2
LAN_TDP1
LAN_TDN1
LAN_RDP2
LAN_RDP3
LAN_RDN3
LAN_RDN2
LAN_TDP4
LAN_TDN4
Function
Transmit Data1 +
Transmit Data1 -
Receive Data2 +
Receive Data3 +
Receive Data3 -
Receive Data2 +
Transmit Data4 +
Transmit Data4 -
Status
Network link is not established
10 Mbps
(10 BaseT)
Link
Active
100 Mbps
(100 BaseTX)
Link
1000 Mbps
(1000 BaseT)
Active
Link
Active
Left LED
(Amber)
OFF
Amber
Blinking Amber
Amber
Blinking Amber
Amber
Blinking Amber
Table 2-1: Ethernet LED Status
Right LED
(Yellow or Amber)
OFF
OFF
OFF
Yellow
Yellow
Amber
Amber
Jumpers and Connectors
cPCI-6840
VGA Connector (on cPCI-6840V only)
Signal Name Pin Pin Signal Name
Red
Blue
GND
GND
+5V
N.C.
HSYNC
DDCCLK
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
Green
N.C.
GND
GND
GND
DDCDAT
VSYNC
PS2 Connector (on cPCI-6840V only)
Pin Signal Function
1 KBDATA Keyboard Data
2 MSDATA Mouse Data
3 GND Ground
4 +5V Power
5 KBCLK Keyboard Clock
6 MSCLK Mouse Clock
RS-232 Serial Port Connector
Pin Signal Name
3
4
1 DCD, Data carrier detect
2 RTS, Request to send
DSR, Data set ready
TXD, Transmit data
5
6
RXD, Receive data
GND, ground
7 CTS, Clear to send
8 DTR, Data terminal ready
Jumpers and Connectors 23
24
IDE Connector
Signal Name Pin Pin Signal Name
BRSTDRVJ 1 2
DDP7
DDP6
3
5
4
6
DDP5
DDP4
DDP3
DDP2
7
9
11
13
8
10
12
14
DDP1
DDP0
15 16
17 18
GND 19 20
PDDREQ 21 22
PDIOWJ
PDIORJ
23 24
25 26
PIORDY 27 28
PDDACKJ 29 30
IRQ14
DAP1
DAP0
CS1P
31 32
33 34
35 36
37 38
IDEACTPJ 39 40
+5V 41 42
GND 43 44
DDP14
DDP15
NC
GND
GND
GND
PCSEL
GND
GND
DDP8
DDP9
DDP10
DDP11
DDP12
DDP13
NC
DIAG
DAP2
CS3PJ
GND
+5V
NC
Jumpers and Connectors
cPCI-6840
General Purpose LED definitions
LED Color Status Description
IDE Media Access Red
OFF
ON IDE access
OFF System is not power-on or power failed
Power OK Green
ON
OFF
Hot-swap status Blue
WDT LED
ON
OFF
Yellow
Blinking
IDE idle
Power ON
Board inserted and power on OK.
Board inserted but not power on yet.
WDT is not enabled
WDT is enabled
Jumpers and Connectors 25
PMC Connector Pin Assignments (J11, J21)
Signal
Name
VIO(4)
P1FRAME#
GND
DEVSL
GND
N/C
PAR
VIO(4)
AD12
AD9
GND
AD6
AD4
VIO(4)
AD2
AD0
GND
TCK(3)
GND
INTB#
BM1(1)
INTD#
GND
CLKP1
GND
REQ0#
VIO(4)
AD28
AD25
GND
AD22
AD19
J11/J21
Pin
J11/J21
Pin
55
57
59
61
63
47
49
51
53
39
41
43
45
31
33
35
37
23
25
27
29
15
17
19
21
7
9
11
13
1
3
5
56
58
60
62
64
48
50
52
54
40
42
44
46
32
34
36
38
24
26
28
30
16
18
20
22
8
10
12
14
2
4
6
Signal
Name
Signal
Name
-12V +12V
INTA# TMS(2)
INTC# TDI(2)
+5V
N/C
GND
N/C
+3.3V
BM2(2)
GND RST#
GNT0# +3.3V
+5V PME#
AD31
AD27
AD30
GND
GND AD24
CBE3# IDSEL
AD21
+5V
+3.3V
AD18
AD17
GND
AD16
GND
IRDY# TRDY#
+5V GND
LOCK# PERR#
N/C +3.3V
GND
AD15
CBE1#
AD14
AD11 M66EN
+5V AD8
CBE0#
AD5
AD7
+3.3V
GND
AD3
N/C
N/C
AD1 GND
+5V ACK64#
REQ64# GND
J11/J21
Pin
J11/J21
Pin
55
57
59
61
63
47
49
51
53
39
41
43
45
31
33
35
37
23
25
27
29
15
17
19
21
7
9
11
13
1
3
5
56
58
60
62
64
48
50
52
54
40
42
44
46
32
34
36
38
24
26
28
30
16
18
20
22
8
10
12
14
2
4
6
Signal
Name
CBE2#
IDSL_B(1)
+3.3V
STOP#
GND
SERR#
GND
AD13
AD10
+3.3V
REQ_B#(1)
GNT_B#(1)
GND
EREADY(1)
RSTOUT#(1)
+3.3V
Monarch#(1)
TRST#(3)
TDO(1)
GND
N/C
N/C
+3.3V
BM3(3)
BM4(3)
GND
AD29
AD26
+3.3V
AD23
AD20
GND
26 Jumpers and Connectors
cPCI-6840
PMC Connector Pin Assignments (J13, J23, J24)
Signal
Name
J13, J23
Pin
GND
AD47
AD45
VIO(4)
AD43
AD41
GND
AD39
AD37
GND
AD35
AD33
AD59
AD57
VIO(4)
AD55
AD53
GND
AD51
AD49
N/C
GND
CBE[6]
CBE[5]
VIO(4)
AD63
AD61
GND
41
43
45
47
33
35
37
39
49
51
53
55
25
27
29
31
17
19
21
23
9
11
13
15
5
7
1
3
42
44
46
48
34
36
38
40
50
52
54
56
26
28
30
32
18
20
22
24
10
12
14
16
6
8
2
4
J13, J23
Pin
Signal
Name
Signal
Name
J24(5)
Pin
J24(5)
Pin
GND PMCIO1
CBE[7] PMCIO3
CBE[6] PMCIO5
GND PMCIO7
PAR64 PMCIO9 9
AD62 PMCIO11 11
GND PMCIO13 13
AD60 PMCIO15 15
5
7
1
3
AD58 PMCIO17 17
GND PMCIO19 19
AD56 PMCIO21 21
AD54 PMCIO23 23
GND PMCIO25 25
AD52 PMCIO27 27
AD50 PMCIO29 29
GND PMCIO31 31
AD48 PMCIO33 33
AD46 PMCIO35 35
GND PMCIO37 37
AD44 PMCIO39 39
AD42 PMCIO41 41
GND PMCIO43 43
AD40 PMCIO45 45
AD38 PMCIO47 47
GND PMCIO49 49
AD36 PMCIO51 51
AD34 PMCIO53 53
GND PMCIO55 55
Signal
Name
6
8
2
4
PMCIO2
PMCIO4
PMCIO6
PMCIO8
10 PMCIO10
12 PMCIO12
14 PMCIO14
16 PMCIO16
18 PMCIO18
20 PMCIO20
22 PMCIO22
24 PMCIO24
26 PMCIO26
28 PMCIO28
30 PMCIO30
32 PMCIO32
34 PMCIO34
36 PMCIO36
38 PMCIO38
40 PMCIO40
42 PMCIO42
44 PMCIO44
46 PMCIO46
48 PMCIO48
50 PMCIO50
52 PMCIO52
54 PMCIO54
56 PMCIO56
Jumpers and Connectors 27
Signal
Name
J13, J23
Pin
VIO(4)
N/C
N/C
GND
57
59
61
63
J13, J23
Pin
58
60
62
64
Signal
Name
Signal
Name
J24(5)
Pin
J24(5)
Pin
AD32 PMCIO57 57
N/C PMCIO59 59
GND PMCIO61 61
N/C PMCIO63 63
58
Signal
Name
PMCIO58
60 PMCIO60
62 PMCIO62
64 PMCIO64
Note 1 : These signals are not connected on the board.
Note 2 : These signals are pulled high on the board.
Note 3 : These signals are pulled low on the board.
Note 4 : The VIO signals by default set to +3.3V via zero ohm resistors. Therefore, DO NOT apply any 5V only PMC module to the PMC sockets.
Note 5 : J24 signals are connected to the CompactPCI J5 connector.
To use these signals, the RTM needs to be either custom designed for special purposes or have a PIM connector available on RTM.
28 Jumpers and Connectors
cPCI-6840
CompactPCI J1 Pin Assignment
Pin Z A B C D E F
25 GND
24 GND
23 GND
+5V
AD [1]
+3.3V
22 GND
21 GND
AD [7]
+3.3V
20 GND AD [12]
19 GND +3.3V
18 GND SERR#
17 GND +3.3V
16 GND DEVSEL#
15 GND +3.3V
12-14
11 GND AD [18]
10 GND AD [21]
9 GND C/BE[3]#
REQ64# ENUM#(4) +3.3V
+5V
AD [4]
GND
AD [9]
GND
AD [15]
V (I/O)
AD [3]
+3.3V
AD [8]
V (I/O)
AD [14]
AD [0]
+5V
AD [6]
AD [11]
GND
+5V
ACK64#
AD [2]
AD [5]
AD [10]
AD [13]
GND
GND
GND
GND
M66EN C/BE [0]# GND
GND
GND
GND +3.3V
PAR C/BE [1]# GND
IPMB_SCL IPMB_SDA GND PERR# GND
GND
FRAME#
V (I/O)
IRDY#
STOP#
BDSEL
LOCK#
TRDY#
GND
GND
AD [17]
GND
IDSE
Key
AD [16]
+3.3V
AD [23]
GND C/BE [2]# GND
AD [20] AD [19] GND
GND AD [22] GND
8 GND AD [26]
7 GND AD [30]
GND
AD [29]
V (I/O)
AD [28]
AD[25] AD [24] GND
GND AD [27] GND
6 GND REQ# GND +3.3V
CLK
5 GND Reserved(1) Reserved(1) PCIRST# GND
AD [31]
GNT#
GND
GND
4 GND IPMB_PWR HEALTHY#
3 GND INTA# INTB#
2 GND
1 GND
TCK(3)
+5V
+5V
-12V
V
INTC#
TMS(2)
TRST#(3)
INTP(1)
+5V
TDO(1)
+12V
INTS
INTD#
TDI(2)
+5V
GND
GND
GND
GND
Note 1 : These signals are not connected.
Note 2 : These signals are pulled high on the board.
Note 3 : These signals are pulled low on the board.
Note 4 : To support PICMG 2.1 hot-swap for peripheral boards, the backplane should bus all peripheral slots ENUM# together to the system slot. The ENUM# signal can be polled by software or generates interrupt.
Jumpers and Connectors 29
CompactPCI J2 Pin Assignment
Pin Z A B C D E F
22 GND GA4(2) GA3(2)
21 GND CLK6
20 GND CLK5
GND
GND
GA2(2)
BRSV(1)
BRSV(1)
GA1(2)
BRSV(1)
GND
GA0(2) GND
BRSV(1) GND
BRSV(1) GND
19 GND GND GND ICMBSDA(1) ICMBSCL(1) ICMBALR(1) GND
18 GND BRSV(1) BRSV(1) BRSV(1) GND BRSV(1) GND
17 GND BRSV(1) GND
16 GND BRSV(1) BRSV(1)
PRST#
DEG#
REQ6#
GND
GNT6#
BRSV(1)
GND
GND
15 GND BRSV(1) GND
14 GND AD [35] AD [34]
13 GND AD [38] GND
12 GND AD [42] AD [41]
11 GND AD [45] GND
10 GND AD [49] AD [48]
9 GND AD [52] GND
8 GND AD [56] AD [55]
FAL#
AD [33]
V (I/O)
AD [40]
V (I/O)
AD [47]
V (I/O)
AD [54]
REQ5#
GND
AD [37]
GND
AD [44]
GND
AD [51]
GND
GNT5#
AD [32]
AD [36]
AD [39]
AD [43]
AD [46]
AD [50]
AD [53]
GND
GND
GND
GND
GND
GND
GND
GND
7 GND AD [59] GND
6 GND AD [63] AD [62]
V (I/O)
AD [61]
5 GND C/BE [5]# GND V (I/O)
4 GND V (I/O) BRSV(1) C/BE [7]#
3 GND CLK4
2 GND CLK2
1 GND CLK1
GND
CLK3
GND
GNT3#
SYSEN#
REQ1#
AD [58]
GND
C/BE [4]#
GND
REQ#4
GNT2#
GNT1#
AD [57]
AD [60]
GND
GND
PAR 64 GND
C/BE [6]# GND
GNT4#
REQ3#
REQ2#
GND
GND
GND
Note 1 : These signals are not connected.
Note 2 : These signals are pulled high on the board.
Note 3 : These signals are pulled low on the board.
30 Jumpers and Connectors
cPCI-6840
CompactPCI J3 Pin Assignment
Pin Z A B C D E F
19 GND GND
18 GND LPA_DA+
17 GND LPA_DB+
GND
LPA_DA-
LPA_DB-
16 GND LPB_DA+
15 GND LPB_DB+
LPB_DA-
LPB_DB-
14 GND GND GND
13 GND LANA_1G# LANA_100#
12 GND
11 GND
LINKB#
IYAM0
LANB_100#
IYAM1
GND
GND
GND
GND
GND
2.5V
ACTA#
ACTB#
IYAM2
GND
LPA_DC+
LPA_DD+
LPB_DC+
LPB_DD+
GND
LINKA#
5V(1)
IYAM3
GND GND
LPA_DCGND
LPA_DDGND
LPB_DCGND
LPB_DDGND
GND GND
LANB_1G# GND
5V(1) GND
ICLKAM GND
10 GND
9 GND
8 GND
7 GND
6 GND
IYAP0
IYBM0
IYBP0
CTS#
HSYNC
IYAP1
IYBM1
IYBP1
DSR#
VSYNC
IYAP2
IYBM2
IYBP2
RTS#
SIN
IYAP3
IYBM3
IYBP3
DTR#
SOUT
ICLKAP
ICLKBM
ICLKBP
NC
DCD#
GND
GND
GND
GND
GND
5 GND RED GREEN BLUE DDCDATA DDCCLK GND
4 GND TMDS1_TX1N TMDS1_TX2N TMDS1_TX3N TMDS1_TXCN TMDS_I2CC GND
3 GND TMDS1_TX1P TMDS1_TX2P TMDS1_TX3P TMDS1_TXCP TMDS_I2CD GND
2 GND LVDS_VDDEN LVDS_TEN LVDS_TCTL NC HTPLG GND
1 GND KBCLK KBDATA MSCLK MSDATA 3.3V(1) GND
Note : The +3.3V and +5V power lines are supplied from the main board to the RTM.
Jumpers and Connectors 31
32
CompactPCI J3 Signal Descriptions
Signals
KBCLK,
KBDATA,
MSCLK,
MSDATA
TMDS1_TX1P/
N, TX2P/N,
TX3P/N,
TXCP/N,
TMDS_I2CC/I2
CD, HTPLG
HSYNC,
VSYNC, RED,
GREEN, BLUE,
DDCDATA,
DDCCLK
Description Signals Description
Keyboard and
Mouse signals
TMDS signals for DVI interfaced panel
CRT signals
IYAM0/AP0,
IYAM1/AP1,
IYAM2/AP2,
IYAM3/AP3,
ICLKAM/AP,
IYBM0, IYBM1,
IYBM2, IYBM3,
ICLKBM,
IYBP0, IYBP1,
IYBP2, IYBP3,
ICLKBP,
LVDS_VDDEN,
LVDS_TEN,
LVDS_TCTL.
LANA_1G#,
LANA_100#,
ACTA#,
LINKA#,
LANB_1G#,
LANB_100#,
ACTB#, LINKB#
LPA_DA+/DA-,
LPA_DB+/DB-,
LPA_DC+/DC-,
LPA_DD+/DD-,
LPB_DA+/DA-,
LPB_DB+/DB-,
LPB_DC+/DC-,
LPB_DD+/DD-,
LVDS Signals
LED Signals for
Rear GbE LAN
Connectors
GbE Signals for
PICMG 2.16 or
Rear Connectors
CTS#, DSR#,
RTS#, DTR#,
SIN, SOUT,
DCD#
Serial port signals
Jumpers and Connectors
cPCI-6840
CompactPCI J5 Pin Assignment
Pin Z A B C D E F
22 GND PMC I/O 5 PMC I/O 4 PMC I/O 3 PMC I/O 2
21 GND PMC I/O 10 PMC I/O 9 PMC I/O 8 PMC I/O 7
PMC I/O 1
PMC I/O 6
GND
GND
20 GND PMC I/O 15 PMC I/O 14 PMC I/O 13 PMC I/O 12 PMC I/O 11 GND
19 GND PMC I/O 20 PMC I/O 19 PMC I/O 18 PMC I/O 17 PMC I/O 16 GND
18 GND PMC I/O 25 PMC I/O 24 PMC I/O 23 PMC I/O 22 PMC I/O 21 GND
17 GND PMC I/O 30 PMC I/O 29 PMC I/O 28 PMC I/O 27 PMC I/O 26 GND
16 GND PMC I/O 35 PMC I/O 34 PMC I/O 33 PMC I/O 32 PMC I/O 31 GND
15 GND PMC I/O 40 PMC I/O 39 PMC I/O 38 PMC I/O 37 PMC I/O 36 GND
14 GND PMC I/O 45 PMC I/O 44 PMC I/O 43 PMC I/O 42 PMC I/O 41 GND
13 GND PMC I/O 50 PMC I/O 49 PMC I/O 48 PMC I/O 47 PMC I/O 46 GND
12 GND PMC I/O 55 PMC I/O 54 PMC I/O 53 PMC I/O 52 PMC I/O 51 GND
11 GND PMC I/O 60 PMC I/O 59 PMC I/O 58 PMC I/O 57 PMC I/O 56 GND
10 GND PMC VIO(1) PMC I/O 64 PMC I/O 63 PMC I/O 62 PMC I/O 61 GND
9 GND D15 D14 D13 D12 D11 GND
8 GND
7 GND
D10
D5
D9
D4
D8
D3
D7
D2
D6
D1
GND
GND
6 GND
5 GND
4 GND
D0
DIAG
CS#1
REQ
IRQ15
CS#3
IOW#
ACK#
A0
IORDY
ACT#
A1
IOR#
RST#
A2
GND
GND
GND
3 GND SATA1_TXN SATA1_TXP
2 GND SATA2_TXN SATA2_TXP
1 GND USB2_DN
RSVD
5VS (2)
SATA1_RXN
SATA2_RXN
USB2_DP USB_OC# USB3_DN
SATA1_RXP GND
SATA2_RXP GND
USB3_DP GND
Note 1 : The VIO is connected to the VIO plane (default is +3.3V) of the PMC slot #2.
Jumpers and Connectors 33
34
2.3
cPCI-6840/V Switch and Jumper Settings
The following table lists the switch and jumpers on the cPCI-6840 and cPCI-6840V.
Switch Function
SW1 Reset
JP1
JP3
Enforce SYSEN#
Clear CMOS Content
Miniature switch on ejector Hot-swappable front panel ejector
Table 2-2: Switch and Jumper Functions
SW1: Reset Button
SW1 is a push-button on the front panel. Pressing SW1 generates a hard reset.
JP1: Enforce System Enable
Status JP1
1 2 3
SYSEN# Open (Default)
1 2 3
SYSEN# GND
Table 2-3: JP1 Settings
The system enable signal (SYSEN#) is located on the Compact-
PCI J2 connector’s C2 position. The SYSEN# is used to determine the operation mode of the SBC. When the SYSEN# on the backplane is tightened to GND, then the SBC will boot as a Compact-
PCI system slot otherwise the SBC will boot as a CompactPCI peripheral slot.
However, for some “none PCI bus” backplanes, the SYSEN# pin on the backplane is floating. Install JP1 will short the SYSEN# signal to GND and enforce the cPCI-6840/V as a system slot SBC.
Please note do not install JP1 when the cPCI-6840 is installed in a peripheral slot of CompacPCI system.
Jumpers and Connectors
cPCI-6840
JP3: Clear CMOS
Status
Normal operation (Default)
JP3
1 2 3
1 2 3
Clear CMOS
Table 2-4: JP3 Settings
The CMOS RAM stores the real time clock (RTC) information,
BIOS configuration, and default BIOS setting. The CMOS is powered by the button cell battery when the system is power off.
Please follow the following steps to erase the CMOS RAM data:
1. Unplug the SBC from system
2. Short pins 2 and 3 of JP3, then reinstall the jumper to normal location
3. Insert the SBC back to the chassis.
Miniature Switch on the Front Panel Lower Ejector:
The miniature switch is designed for power control and hot-swap control. When the cPCI-6840 is plugged into system slot, the whole system will not be powered up until the lower ejector is closed. It will issue a power button signal when users open the lower ejector. When the cPCI-6840 is plugged into a peripheral slot, the entire system will not be powered up until the lower ejector is closed and it will send out an ENUM# signal to the system to indicate that a board has been plugged into the CompactPCI backplane. When the lower ejector is opened, the cPCI-6840 will send out an ENUM# to the system and wait for the command from system.
Jumpers and Connectors 35
2.4
RTM Board Outline
The differences between cPCI-R6840 and cPCI-R6841 are described as following. The cPCI-R6840 implements a DVI connector and two SCSI connectors. The cPCI-R6841 implements a
PS2 connector and four screw holes for 2.5’ HDD and PIM connectors (mouted either in the 2.5” HDD bay or with the PIM card on the cPCI-R6841). cPCI-R6840 Top View and Faceplate
36
Figure 2-3: cPCI-R6840 Board Layout
Jumpers and Connectors
cPCI-R6841P Top View and Faceplate cPCI-6840
Figure 2-4: cPCI-R6841P Diagram
Jumpers and Connectors 37
2.5
RTM Connectors Pin Assignments
The USB, GbE LAN, IDE, RS-232 COM2, VGA, and PS2 Keyboard/Mouse combo connector pin assignments on the cPCI-R684X series RTM are identical to those on the SBC. Please refer to section 2.3 for pin assignments.
The CompactFlash, DVI, LVDS, SATA, IDE, PIM, and SCSI connector pin assignments are illustrated in the following sections.
38 Jumpers and Connectors
cPCI-6840
CompactFlash Connector
The CompactFlash is shared with Secondary IDE. Only two devices can be installed simultaneously
Jumpers and Connectors
Signal Name Pin Pin Signal Name
GND
GND
GND
GND
GND
+5V
GND
GND
GND
SDD3
SDD4
SDD5
SDD6
SDD7
SDCS#1
GND
GND
SDA2
SDA1
SDA0
SDD0
SDD1
SDD2
IOIS16#
GND
1 26
2 27
3 28
4 29
5 30
6 31
7 32
GND
SDD11
SDD12
SDD13
SDD14
SDD15
SDCS#3
8 33
9 34
10 35
11 36
GND
SDIOR#
SDIOW#
+5V
12 37 IDEIRQ15
13 38 +5V
14 39
15 40
PCSEL
NC
16 41 SIDERST#
17 42 SIORDY
18 43 NC
19 44 SDDACK#
20 45 IDEACT#
21 46 S66DECT
22 47
23 48
SDD8
SDD9
24 49
25 50
SDD10
GND
39
DVI Connector (cPCI-R6840 only)
Pin Signal Pin Signal
1
2
3
TX216 HTPLG
TX2+ 17 TX0-
GND 18 TX0+
4
5
NC
NC
19 GND
20 NC
6 I2CCLK 21 NC
7 I2CDATA 22 GND
12
13
14
15
8 VSYNC 23 TXC+
9 TX124 TXC-
10 TX1+ 25 RED
11 GND 26 GREEN
NC
NC
+5V
GND
27
30
BLUE
28 HSYNC
29 GND
GND
40 Jumpers and Connectors
cPCI-6840
LVDS A and LVDS B connectors
Pin Signal Pin Signal
1 3.3V
12 IYP2
2 3.3V
13 GND
3 GND 14 ICLKM
4 GND 15 ICLKP
5 IYM0 16 GND
6 IYP0 17 IYM3
7 GND 18 IYP3
8 IYM1 19 GND
9 IYP1 20 GND
10 GND 21 GND
11 IYM2 22 GND
SATA1 and SATA2 connectors
Pin Signal
8
9
1 GND
2 TXP
3 TXN
4 GND
5 RXN
6 RXP
7 GND
NC
NC
SCSI Connector (cPCI-R6840 only)
There are two SCSI-68 connectors on cPCI-R6840: the CN10 is onboard 180 degrees connector for inner chassis SCSI drives; the
CN14 is on the rear faceplate for external SCSI drives connection.
Jumpers and Connectors 41
42
PIM Connector (cPCI-R6841P only)
JN1 JN2
Signal Pin Pin Signal Signal Pin Pin Signal
PMCIO01 1 2 PMCIO02 NC
PMCIO03 3 4 PMCIO04 NC
PMCIO05 5 6 PMCIO06 5V
1 2
3 4
5 6
NC
NC
NC
PMCIO07 7 8 PMCIO08 NC
PMCIO09 9 10 PMCIO10 NC
7 8 NC
9 10 3.3V
PMCIO11 11 12 PMCIO12 NC 11 12 NC
PMCIO13 13 14 PMCIO14 GND 13 14 NC
PMCIO15 15 16 PMCIO16 NC 15 16 NC
PMCIO17 17 18 PMCIO18 NC 17 18 GND
PMCIO19 19 20 PMCIO20 NC 19 20 NC
PMCIO21 21 22 PMCIO22 5V 21 22 NC
PMCIO23 23 24 PMCIO24 NC 23 24 NC
PMCIO25 25 26 PMCIO26 NC 25 26 3.3V
PMCIO27 27 28 PMCIO28 NC 27 28 NC
PMCIO29 29 30 PMCIO30 GND 29 30 NC
PMCIO31 31 32 PMCIO32 NC 31 32 NC
PMCIO33 33 34 PMCIO34 NC 33 34 GND
PMCIO35 35 36 PMCIO36 NC 35 36 NC
PMCIO37 37 38 PMCIO38 5V 37 38 NC
PMCIO39 39 40 PMCIO40 NC 39 40 NC
PMCIO41 41 42 PMCIO42 NC 41 42 3.3V
PMCIO43 43 44 PMCIO44 NC 43 44 NC
PMCIO45 45 46 PMCIO46 GND 45 46 NC
PMCIO47 47 48 PMCIO48 NC 47 48 NC
PMCIO49 49 50 PMCIO50 NC 49 50 GND
PMCIO51 51 52 PMCIO52 NC 51 52 NC
PMCIO53 53 54 PMCIO54 5V 53 54 NC
PMCIO55 55 56 PMCIO56 NC 55 56 NC
PMCIO57 57 58 PMCIO58 NC 57 58 3.3V
PMCIO59 59 60 PMCIO60 NC 59 60 NC
PMCIO61 61 62 PMCIO62 NC 61 62 NC
PMCIO63 63 64 PMCIO64 NC 63 64 NC
Jumpers and Connectors
cPCI-6840
Secondary IDE .
There are three Secondary IDE connectors (40-pin,
44-pin, CompactFlash), but only two devices can be installed simultaneously
Pin Signal Pin Signal Pin Signal
6
7
4
5
1 Reset 16 D14 31 IRQ
2 GND 17
3 D7 18
D0
D15
32 IOIS16#
33 A1
D8
D6
19
20
GND
NC
34
35
D9 21 REQ 36
DIAG
A0
A2
D5 22 GND 37 CS#1
8 D10 23 IOW# 38 CS#3
9 D4 24 GND 39 ACT#
10 D11 25 IOR# 40 GND
11 D3 26 GND 41 5V
12 D12 27 IORDY 42 5V
13 D2 28 NC 43 GND
14 D13 29 ACK#
15 D1 30 GND
44 NC
GigaLAN Connectors
Pin Signal Pin Signal Pin Signal
1 MX0+ 6 VCC 11 LAN_1G#
2 MX07 MX2+ 12 LAN_100#
3 MX1+ 8 MX213 LINKA#
4 MX19 MX3+
5 VCC 10 MX3-
14 ACT#
Jumpers and Connectors 43
44
PS2 connector
USB connectors
Pin Signal Pin Signal Pin Signal
1 KBDATA 3 GND 5 KBCLK
2 MSDATA 4 VCC 6 MSCLK
Pin Signal
1 VCC
2 DN
3 DP
4 GND
CRT connector
Pin Signal Pin Signal Pin Signal
4
5
1 RED 6 GND 11 NC
2 GREEN 7 GND 12 DDC_DATA
3 BLUE 8 GND 13 HSYNC
NC 9 GND 14 VSYNC
GND 10 GND 15 DDC_CLK
COM port connector
Pin Signal Pin Signal
1 DCD# 5 SIN#
2 RTS# 6 GND
3 DSR# 7 CTS#
4 SOUT# 8 DTR#
Jumpers and Connectors
cPCI-6840
2.6
RTM Switch and Jumper Setting
cPCI-R6840
Switch Functions
SW1 and SW2 Enable either 2.16 plane or RTM LAN2 access
SW3 and SW4 Enable either 2.16 plane or RTM LAN1 access
SW5
CN9
Enable rear VGA signals
Determine the CF as master or slave
Table 2-5: RTM Switch and Jumper Settings
LAN1 and LAN2 Dip Switches on RTM
The cPCI-6840 supports LAN1 and LAN2 on both the 2.16
backplane and rear I/O. PICMG 2.16 backplane and rear I/O cannot be accessed simultaneously. SW1 and SW2 must be set to either the 2.16 backplane or the RTM. The table below shows how to set the DIP switches to enable either the 2.16
backplane or RTM for LAN1 and LAN2.
Connect to:
PICMG 2.16 Backplane
Rear faceplate RJ-45 connectors
LAN2 (SW1 and SW2) LAN1 (SW3 and SW4)
All OFF
All ON (default)
All OFF
All ON (default)
Table 2-6: LAN Dip Switch Settings
All switches in the SW1, SW2, SW3, and SW4 bank must all be either ON or OFF. 2.16 backplane and rear
LAN1 and LAN2 cannot be accessed simultaneously.
SW5: VGA Signal Enable
The cPCI-6840 supports VGA outputs to both front and rear panels. If SW5 on the RTM is set all off, the RGB signal won’t be connected to the rear connector. Users should set SW5 on to enable the rear VGA signal output (default: All ON).
Jumpers and Connectors 45
46
Master/Slave Selection of Compact Flash (CN9)
The cPCI-R6840 RTM uses a jumper (CN9) to determine master or slave IDE state of the CompactFlash disk.
CF Status CN9
1 2 3
Slave (default)
1 2 3
Master
Table 2-7: CF Master/Slave Jumper Settings cPCI-R6841(P) Jumpers and Other Settings
SW1, SW4
SW2, SW3
SW5
All ON (default)
All OFF
All ON (default)
All OFF
All ON (default)
All OFF
LAN2 rear panel
LAN2 2.16 backplane
LAN1 rear panel
LAN1 2.16 backplane
Rear VGA on
Rear VGA off
Table 2-8: cPCI-R6841(P) Switch Settings
Master/Slave Selection of Compact Flash (CN8)
The cPCI-R6841(P) RTM uses a jumper (CN8) to determine master or slave IDE state of the CompactFlash disk
CF Status CN8
1 2 3
Slave (default
1 2 3
Master
Table 2-9: JP3 Settings
Jumpers and Connectors
cPCI-6840
3 Getting Started
This chapter explains how to install necessary components on the cPCI-6840/cPCI-6840V and cPCI-R6840 and cPCI-R6841(P)
RTMs, including:
X
X
X
X
X
X
X
X
X
CPU and heat sink
Memory module installation
HDD installation on main board – for cPCI-6840
HDD installation on main board – for cPCI-6840V
HDD installation on RTM
CF installation on RTM
PMC installation
RTM installation
Main board installation
Getting Started 47
3.1
CPU and Heatsink
The cPCI-6840 and cPCI-6840V support the Intel® Pentium® M processor. The heat sink is necessary to help the CPU heat dissipation. Please follow the illustration below to install your heat sink.
48
Figure 3-1: Heatsink installation
Getting Started
cPCI-6840
3.2
Memory Module Installation
The cPCI-6840 series SBC supports up to two sockets of 200-pin
PC2700 ECC DDR-SDRAM. The maximum memory capacity is
2GB. If memory modules are pre-installed when the package is received, this section may be skipped.
The GMCH system memory controller directly supports the following:
X
X
X
One channel of PC1600/2100/2700 SO-DIMM DDR
SDRAM memory
DDR SDRAM devices with densities of 128-Mb, 256-Mb, and 512-Mb technology
Up to 2GB (512-Mb technology) using high density devices with two SO-DIMMs
Technology Width
128Mb
256Mb
512Mb
128Mb
256Mb
512Mb
16
16
16
8
8
8
System
Memory
Capacity
256MB
512MB
1GB
256MB
512MB
1GB
System Memory
Capacity with Stacked
Memory
-
-
-
512MB
1GB
2GB
Table 3-1: DDR SDRAM Memory Capacity
While installing the memory, ensure that the SODIMM modules are firmly seated in its sockets and do not interfere with any components.
Getting Started 49
3.3
HDD Installation on Main Board – for cPCI-6840
A slim-type 2.5-inch HDD can be mounted to the cPCI-6840 main board. If a HDD is pre-installed the cPCI-6840 this section may be skipped.
1. Remove the PMC from the PMC slot if any.
2. Screw the bolts on to the HDD and attach a 44-pin IDE cable.
3. Install the assembly onto the board; tighten the four screws from the bottom side of the main board to secure the HDD in to place.
4. Attach the other end of the 44-pin IDE cable to CN6 onboard.
Please follow the picture shown below to install your 2.5” Hard
Disk.
50 Getting Started
cPCI-6840
Figure 3-2: cPCI-6840 2.5” Hard Disk Installation
Getting Started 51
3.4
HDD Installation on Main Board – for cPCI-6840V
A slim-type 2.5-inch HDD can be mounted to the cPCI-6840V main board. If a HDD is pre-installed when the cPCI-6840V is received, this section may be skipped.
1. Screw the HDD on the HDD bracket and attach 44-pin
IDE cable.
2. Install the assembly on to the board; tighten the three screws from the bottom side of the main board to secure the HDD in place.
3. Attach the other end of the 44-pin IDE cable to CN6 on board.
Please follow the illustration shown below to install your 2.5” Hard
Disk.
52 Getting Started
cPCI-6840
Figure 3-3: cPCI-6840V 2.5” Hard Disk Installation
Getting Started 53
54
3.5
HDD Installation on RTM
A 2.5-inch HDD or Flash Disk can be installed on the cPCI-R6841 directly. If a HDD is pre-installed when the cPCI-R6841 is received, please skip this section.
1. Attach the IDE cable to the HDD or Flash Disk
2. Put the HDD on component side of the RTM, align the
HDD mounting holes with the holes on the PCB.
3. Tighten the four screws from the bottom side of the RTM to secure the HDD in place
4. Connect the IDE cable to the 44-pin connector.
3.6
CF Installation on RTM
The CompactFlash card is widely applied in digital consumer devices such as PDAs, digital cameras and MP3 players. Due to its CF anti-shock, anti-vibration, better environment tolerance, low power consumption, small form factor, and high reliability characteristics, it has been widely accepted in mission critical embedded applications.
The CompactFlash socket is available on the (cPCI-R6840 and cPCI-R6841(P) rear transition modules.
3.7
PCI Mezzanine Card (PMC) Installation
The PMC slots are designed as 3.3V and/or as a universal PCI interfaces. The PMC sites are keyed to prevent users from installing a 5V only PMC module.
Refer to section 2.2 for detailed PMC I/O signal routing. If a HDD is mounted to the main board, the HDD will occupy one of the
PMC slots.
To install the PMC modules:
1. Prepare an ESD protected area including an anti-ESD table and ESD strap. Attach the ESD strap to your wrist and connect the end of the ESD strap to ground of the anti-ESD table.
2. Remove the PMC panel from the front panel.
Getting Started
cPCI-6840
3. Install the PMC module on to the PMC sockets.
4. Screw the PMC mounting bolts to the main board from the bottom side up to fix the PMC module in place.
3.8
RTM Installation
This section describes important information regarding the use of the rear I/O connections. Refer to previous sections for peripheral connectivity of all I/O ports on the RTM. When installing the cPCI-
6840 series and related RTM, make sure the RTM is the correct model that matches each other.
Note : Use the correct RTM to enable functions (I/O interfaces) on rear side. The RTM or system board can be damaged if the incorrect RTM is used.
Some I/O ports are supported on both the front board and the
RTM, including Keyboard, Mouse, VGA and USB. These I/O ports can be connected either via the front or rear modules but DO NOT access these ports on both front and rear simultaneously.
3.9
Main Board Installation
Use the following procedure to install the cPCI-6840/cPCI-6840V main board to its CompactPCI chassis.
1. Refer to the relevant chassis user manual for pre-preparation of the chassis before installing the main board.
Users need to assign a slot to the board. Be sure to select the correct slot (system or peripheral) depending on the operational purpose of the board. The system power may now be powered on.
2. Remove the blank face panel from the slot.
3. Align the top and bottom edges of the board with the card guides on the chassis then slide the board into the chassis until resistance is felt. If the system power is on, the blue LED (hot-swap status) should light up.
4. Move the upper and lower ejectors in an inward direction simultaneously. Note that slight resistance will be felt while inserting the board. If this resistance is more than under normal conditions, check to ensure that there are
Getting Started 55
no pins bent on the backplane and that the board’s connector pins are aligned properly with the connectors on the backplane.
5. Verify that the board is seated properly. With the board in place and the blue LED on, wait for the blue LED to go out before proceeding to the next step.
6. Secure the two screws hidden behind the upper and lower ejector; connect the proper cables to the board.
56 Getting Started
cPCI-6840
4 Windows Driver Installation
The following sections show the driver installation procedures for
Windows 2000, Windows XP or Windows Server 2003. When installing the Windows drivers, we recommend the following steps:
1. Fully install the Windows properly before installing any driver. Most of the standard I/O devices’ driver will be installed during the standard Windows installation.
2. Install the chipset driver.
3. Install the graphic driver and utilities.
4. Install the LAN drivers.
It is recommended that the chipset, graphic, and LAN drivers provided on the ADLINK CD be used to ensure compatibility. Please contact ADLINK for support for Linux drivers and VxWorks BSP.
4.1
Chipset Drivers Installation
1. Ensure Windows 2000/XP/Windows Server 2003 be fully installed and running prior to executing the “Intel Chipset
Software Installation Utility”.
2. Close any running applications.
3. The files are stored in an integrated application setup program. This program is designed for a Windows 2000,
XP and Windows Server 2003.
4. Locate the directory X:\cPCI\cPCI-6840\Chipset in the
CD-ROM, and then run “infinst_enu.exe”.
5. Click 'Next' on the Welcome screen to read and agree to the license agreement. Click Yes if you agree to continue. NOTE: If you click No, the program will terminate.
6. Click ‘Next’ on Readme Information screen to install INF files.
7. Click 'Finish' to restart the system when prompted to do so.
8. Follow the screen instructions and use the default settings to complete the setup when Windows 2000/XP/
Windows Driver Installation 57
58
Windows Server 2003 re-starts. Upon re-start, Windows will display that it has found new hardware and is installing drivers for them. If New Hardware Found dialog box is displayed requesting the location of the drivers, use the mouse to click on the scrollbar and click on the <Windows directory>.
9. Select Yes, when prompted to re-start Windows 2000/
XP/Windows Server 2003.
4.2
VGA Driver Installation
1. Boot Windows 2000/XP/Windows Server 2003.
2. The driver is included in the driver CD. Run the win2k_xp142.exe under the following directory:
X:\cPCI\cPCI-6840\VGA.
3. Click ‘Next’ on the Welcome screen. Select ‘Typical’ on the setup type screen and click Next’.
4. Use default program folders on Select Program Folder screen. Click ‘Next’ to install driver.
5. Finally, click 'Finish' to restart.
4.3
LAN Driver Installation
This section describes the LAN driver installation for the Intel®
82541PI and Intel® 82546GB onboard Ethernet controllers. The relevant drivers are located in the following driver CD directory:
1. Boot Windows 2000/XP/Windows Server 2003.
2. The driver is included in the driver CD. Run the
PRO2KXP.exe under the following directory:
X:\cPCI\cPCI-6840\LAN.
3. Read the license agreement. Click 'I accept the terms in the license agreement’ if you agree to continue.
4. Location to Save Files, click Next to save files in folder.
5. Intel® PRO Network Connections. Click Install Software to install drivers and Intel PROSet.
Windows Driver Installation
cPCI-6840
5 Utilities
5.1
Watchdog Timer
This section explains the operation of the cPCI-6840’s watchdog timer. It provides an overview of watchdog operation and features, as well as a sample code to help you learn how the watchdog timer works.
WDT Overview
The primary function of the watchdog timer is to monitor the cPCI-
6840’s operation and to generate IRQ or reset the system if the software fails to function as programmed. The major features of the watchdog timer are:
X
X
Enabled and disabled through software control
Armed and strobed through software control
PCI
PCI
Configuration
Registers
Preload Value 1 Preload Value 2
Down-Counter
Reset/ Interrupt Control Logic
WDT_TOUT#
(External)
Figure 5-1: WDT Block Diagram
IRQ/SMI
(Internal)
Utilities 59
60
The cPCI-6840’s custom watchdog timer circuit is integrated in the
6300ESB south bridge.
The Intel® 6300ESB ICH includes a two-stage Watchdog Timer
(WDT) that provides a resolution ranging from one micro second to ten minutes. The timer uses a 35-bit Down-Counter. The counter is loaded with the value from the first Preload register. The timer is then enabled and it starts counting down. The time at which the WDT first starts counting down is called the first stage. If the host fails to reload the WDT before the 35-bit down counter reaches zero the WDT generates an internal interrupt. After the interrupt is generated, the WDT loads the value from the second
Preload register into the WDT’s 35-bit Down-Counter and starts counting down. The WDT is now in the second stage. If the host still fails to reload the WDT before the second timeout, the WDT drives the WDT_TOUT# pin low. The WDT_TOUT# pin is held low until the system is reset.
The WDT of 6300ESB also supports multiple modes, WDT and free-running. Free-running mode is a one stage timer and it will toggle WDT_TOUT# after programmable time. WDT mode is a two stage timer and its operation is described as above.
Configuration Registers
The Intel® 6300ESB ICH WDT, appears to BIOS as PCI Bus 0,
Device 29, Function 4, and has the standard set of PCI Configuration register. The configuration registers is described below.
Offset 10H: Base Address Register (BAR)
This register determines the memory base for WDT downcounter setting. It will be used to set Preload value 1 register,
Preload value 2 register, General Interrupt Status register and
Reload register.
Preload Value 1 & 2 registers
These two registers are used to hold the preload value for the
WDT timer. Its value will be automatically transferred into the down-counter every time the WDT enters the first stage and second stage. Preload Value 1 register locates at Base + 00H and Preload Value 2 register locates at Base + 04H. Only bit
[19:0] are settable. The register unlocking sequence is neces-
Utilities
cPCI-6840 sary when writing to the Preload registers. The following is the procedure of how to write a value into preload value 1 and 2 register.
1. Write 80H to offset BAR + 0CH.
2. Write 86H to offset BAR + 0CH.
3. Write desired value to preload register. (BAR + 00H or
BAR + 04H)
General Interrupt Status Register
This register is at Base + 08H. Bit 0 is set when the first stage of down-counter reaches zero.
X
X
Bit 0 = 0 – No Interrupt
Bit 1 = 1 – Interrupt Active
Note : This bit is not set in free running mode.
Reload Register
This register is at Base + 0CH. Write 1 to bit 8 will reload the down-counter’s value. Following is the procedure of how to prevent a timeout.
1. Write 80H to offset BAR + 0CH
2. Write 86H to offset BAR + 0CH
3. Write a ‘1’ to RELOAD[8] of the reload register
Offset 60 – 61H: WDT Configuration Register
X
X
X
Bit 5 indicates whether or not the WDT will toggle the
WDT_TOUT# pin when WDT times out. (0 = Enabled, 1 =
Disabled)
Bit 2 provides two options for prescaling the main downcounter. (0 = 1ms – 10min, 1 = 1us – 1sec)
Bit [1:0] allows the user to choose the type of interrupt desired when the WDT reached the end of the first stage without being reset. (00 = IRQ, 01 = reserved, 10 = SMI, 11
= Disabled)
Note : The WDT doesn’t support SMI. IRQ uses APIC 1, INT 10 and it is active low, level triggered.
Utilities 61
62
Offset 68H: WDT Lock Register
X
X
Bit 2 is used to choose the functionality of the timer. (0 =
Watchdog Timer mode, 1 = Free running mode) The free running mode ignores the first stage and only uses Preload
Value 2. In free running mode it is not necessary to reload the timer as it is done automatically every time the down counter reaches zero.
Bit 1 enables or disables the WDT. (0 = Disabled, 1 =
Enabled)
X Bit 0 will lock the values of this register until a hard reset occurs or power is cycled. (0 = unlocked, 1 = locked) The default is Unlocked.
GPIO Control Registers
There are three GPIOs on cPCI-6840 relate to watchdog timer.
They are listed as following. The GPIO control base port is 480H.
WDT_TOUT# pin selection
WDT_TOUT# signal is multiplexed with GPIO32. When using
WDT, this signal must be switched to WDT_TOUT# function. It uses bit 0 of GPIOBASE + 30H to set WDT_TOUT function. (0
= WDT_TOUT#, 1 = GPIO32)
RESET hardware circuit selection
GPO24 of 6300ESB is designed to control reset circuit. When
GPO24 is low, system will reset according to the level of
WDT_TOUT# signal. When GPO24 is high, system will not be reset by WDT_TOUT#. Set bit 24 of GPIOBASE + 04H to 0 for output use. Bit 24 of GPIOBASE + 0CH determines the level of
GPO24. (0 = Low, 1 = High) There already exists a setting in
BIOS setup menu. (Integrated Peripherals page) User can set this item before programming WDT.
WDT LED Control
GPO25 of 6300ESB is designed to control WDT LED. Two features of WDT LED are supported on cPCI-6840. WDT LED lights or blinks.
Utilities
cPCI-6840
WDT LED light
Set bit 25 of GPIOBASE + 04H to 0. Bit 25 of GPIOBASE +
0CH determines the state of WDT LED. (0=light, 1=dark)
WDT LED blink
Set bit 25 of GPIOBASE + 04H to 0. Bit 25 of GPIOBASE +
18H enables WDT LED blinking function. (0=function normally,
1=enable blinking) The high and low times have approximately
0.5 seconds each.
WDT Programming Procedure
1. Set BIOS Setting in Integrated Peripherals\Onboard
Device Page Watch Dog Timer Item to “Enabled”.
2. Make sure WDT_TOUT# signal is functional. (Not
GPIO32 function).
3. Set WDT output enable, presecaler and interrupt type into WDT configuration register.
4. Obtain control base from Base Address register.
5. Program Preload register’s value according to unlocking sequence.
6. Set WDT timer mode into WDT Lock Register.
7. Enable WDT from WDT Lock register and program the functionality of WDT LED.
To prevent the timer from causing an interrupt or driving
WDT_TOUT#, the timer must be reloaded periodically. The frequency of reloads required is dependent on the value of the preload values. To reload the down-counter, the register unlocking sequence must be performed.
If the user wishes to disable WDT, set bit 1 of WDT Lock Register to 0.
Utilities
ADLINK provides a demo DOS utility, HRWDT.EXE
. It is included in the driver CD. Run “ hrwdt /?
” under the following directory:
X:\CHIPDRV\WDT\HRWDT for a more detailed description.
Utilities 63
64
The user can also download the Intel® WDT demo windows application from Intel® driver download center.
5.2
Intel Preboot Execution Environment (PXE)
The cPCI-6840 series supports Intel® Preboot Execution Environment (PXE), which provides the capability of boot up or executing an OS installation through the Ethernet ports. There should be a
DHCP server in the network with one or more servers running
PXE and MTFTP services. It could be a Windows NT or Windows
2000 server running DHCP, PXE and MTFTP service or a dedicated DHCP server with one or more additional server running
PXE and MTFTP service. This section describes the major items required for building a network environment with PXE support.
1. Setup a DHCP server with PXE tag configuration.
2. Install the PXE and MTFTP services
3. Make boot image file on PXE server (that is the boot server).
4. Enable the PXE boot function on the client computer.
For further details, please refer to pdkrel30.pdf under the directory
X:\Utility\PXE_PDK.
Utilities
cPCI-6840
6 IPMI User Guide
6.1
Introduction
This chapter is written for those who already have a basic understanding of the newest implementation of the baseboard management controller (BMC) of the Intelligent Platform Management
Interface (IPMI) specification rev. 1.5. It also describes the OEM extension IPMI command usages which are not listed in the IPMI specification.
6.2
Summary of Commands Supported by BMR-
AVR-cPCI
The table below lists all the commands supported by the BMR-
AVR-cPCI. The rightmost column indicates if a particular command is required by PICMG 3.0/ PICMG 2.9, or is optional.
IPMI
Command
Spec
IPM Device “Global” Commands
Get Device ID
Cold Reset
Warm Reset
Get Self Test Results
Get Device GUID
17.1
17.2
17.3
17.4
17.8
NetFn
Broadcast “Get Device ID” 17.9
IPMI Messaging Support Commands
18.7
Send Message
BMC Watchdog Timer
Reset Watchdog Timer
Set Watchdog Timer
Get Watchdog Timer
21.5
21.6
21.7
App
App
App
App
App
App
App
App
App
App
Event Commands
Set Event Receiver
Get Event Receiver
23.1
23.2
Platform Event (a.k.a.
“Event Message”)
Sensor Device Commands
23.3
S/E
S/E
S/E
CMD
IPM Controller Req
(PICMG 3.0/ 2.9)
01h Mandatory/Mandatory
02h Optional/Optional
03h Optional/Optional
04h Mandatory/Mandatory
08h Optional/Optional
01h Mandatory/Mandatory
34h Optional
22h Mandatory/Optional
24h Mandatory/Optional
25h Mandatory/Optional
00h Mandatory/Optional
01h Mandatory/Optional
02h Mandatory/Optional
IPMI User Guide 65
Get Device SDR Info
Get Device SDR
Reserve Device SDR
Repository
Set Sensor Hysteresis
Get Sensor Hysteresis
29.2
29.3
29.4
Set Sensor Threshold
Get Sensor Threshold
29.6
29.7
29.8
29.9
Set Sensor Event Enable 29.10
Get Sensor Event Enable 29.11
Get Sensor Event Status 29.13
29.14
29.16
Get Sensor Reading
Get Sensor Type
FRU Device Commands
Get FRU Inventory Area
Info
Read FRU Data
Write FRU Data
28.1
28.2
28.3
S/E
S/E
S/E
S/E
S/E
S/E
S/E
S/E
S/E
S/E
S/E
S/E
20h
21h
Mandatory/Optional
Mandatory/Optional
22h Mandatory/Optional
24h Optional/Optional
25h Optional/Optional
26h Optional/Optional
27h Optional/Optional
28h Optional/Optional
29h Optional/Optional
2Bh Optional/Optional
2Dh Mandatory/Optional
2Fh Optional/Optional
Storage 10h Mandatory/Optional
Storage 11h Mandatory/Optional
Storage 12h Mandatory/Optional
66 IPMI User Guide
cPCI-6840
6.3
OEM Commands Summary Table
Command
OemShowRevision
OemRescanGaInput
OemTestFunction
OemReportGeoAddress
OemEnableSmbus
OemDisableSmbus
OemDispDebugVariable
OemResetHost
OemPowerOff
OemPowerOn
NetFn Code
OEM (C0h)
OEM (C0h)
OEM (C0h)
OEM (C0h)
OEM (C0h)
OEM (C0h)
OEM (C0h)
OEM (C0h)
OEM (C0h)
OEM (C0h)
Cmd Code
12h
22h
30h
F0h
F2h
F3h
F4h
F5h
F6h
F7h
OemShowRevision
This command is used to show the current information of the firmware including the firmware revision, the product ID, and additional features.
Action
Request
Response
7
8
9
10
5
6
3
4
Byte
0
1
0
1
2
Value
C0h
12h
Complete Code
A5h
*Firmware Rev
*Firmware Rev
*Firmware Rev
*Product ID
*Product ID
*Product ID
*Special info
*Special info
5Ah
Description
NetFn/LUN for OEM
OEM defined command
00h means OK
Internal check byte. Always A5h
‘V’ in ASCII code for verification
Revision info high byte
Revision info low byte
‘P’ in ASCII code for verification
Product info high byte
Product info low byte
‘S’ in ASCII code for verification
Addition info byte
Internal check byte. Always 5Ah
IPMI User Guide 67
68
OemRescanGaInput
This command is used to rescan the geo-address input pins and reset the IPMB address according to the input value.
Action
Request
1
Response 0
Byte Value
0 C0h
1
22h
Complete Code
New IPMB address
Description
NetFn/LUN for OEM
OEM defined command
00h means OK
New IPMB address value
OemTestFunction
Internal test purposes only.
OemReportGeoAddress
This command can report the IPMB address, the GA pin input status, and the event forwarding control value.
Action
Request
1
Response 0
1
2
3
Byte Value
0 C0h
F0h
Complete Code
IPMB address
GA value
Control value
Description
NetFn/LUN for OEM
OEM defined command
00h means OK
IPMB address value
GA pin input status
Current control value of event forwarding
OemEnableSmbus
This command is used to turn on the I2C bus when it is off during boot up process. Usually BIOS will perform this command after booting in boards with ServerWorks chipset.
Action
Request
1
Response 0
Byte Value
0 C0h
F2h
Complete Code
Description
NetFn/LUN for OEM
OEM defined command
00h means OK
IPMI User Guide
cPCI-6840
OemDisableSmbus
This command is used to shut down I2C bus access.
Action
Request
1
Response 0
Byte Value
0 C0h
F3h
Complete Code
Description
NetFn/LUN for OEM
OEM defined command
00h means OK
OemDispDebugVariable
This command can report up to 5 interval values for debug purposes. For developers only.
Action
Request
1
Response 0
Byte Value
0 C0h
1
F4h
Complete Code
*Debug variable 1
2
3
*Debug variable 2
*Debug variable 3
4
5
*Debug variable 4
*Debug variable 5
Description
NetFn/LUN for OEM
OEM defined command
00h means OK
OemResetHost
This command is implemented to control the system’s status if rebooting is required. Operators can control the system remotely.
Action
Request
1
Response 0
Byte Value
0 C0h
F5h
Complete Code
Description
NetFn/LUN for OEM
OEM defined command
00h means OK
IPMI User Guide 69
OemPowerOff
This command is implemented to control the system’s status if power-off is required. Operators can control the system remotely.
Action
Request
1
Response 0
Byte Value
0 C0h
F6h
Complete Code
Description
NetFn/LUN for OEM
OEM defined command
00h means OK
OemPowerOn
This command is implemented to control the system’s status if power-on is required. Operators can control the system remotely.
Action
Request
1
Response 0
Byte Value
0 C0h
F7h
Complete Code
Description
NetFn/LUN for OEM
OEM defined command
00h means OK
70 IPMI User Guide
cPCI-6840
6.4
CompactPCI Address Map
Since we may insert more than one system in a single chassis, we allocate each IPMB address based on GA input as peripheral cards. The CompactPCI Peripheral Address Mapping Table is given below.
6.5
IPMI Sensors List
Sensor name Sensor
Number
01h
02h
03h
04h
05h
BMC Watchdog
3.3
5V
12V
SYSTEM Temp
Normal
Reading
Remark
3.3 V
5 V
12 V
25 °C
IPMI User Guide 71
6.6
Known Issues
Timestamp resets after power up:
There is no real time clock built-in with the BMC in our IPMI solution. As a result, the internal timer resets itself after power up.
SDR records readonly:
Due to the hardware design, all sensor data records (SDR) are stored in Flash ROM. Flash ROM cannot be accessed randomly.
6.7
Relevant Documents
Document Title
Intelligent Platform
Management Interface
Specification v1.5
PICMG 2.9 D1.0
CompactPCI System
Management Specification
Intelligent Platform
Management Bus
Communications Protocol
Specification v0.9
Revision
Document
Revision 1.1
February 20, 2002
January 21, 2000
Document
Revision 0.15
June 24, 1997
Source
Intel Corp. http:// www.intel.com/design/ servers/ipmi/license_ipmi.htm
Intel Corp.
http://www.intel.com/design/ servers/ipmi/license_ipmi.htm
72 IPMI User Guide
cPCI-3920
Important Safety Instructions
Please read and follow all instructions marked on the product and in the documentation before operating the system. Retain all safety and operating instructions for future use.
X
X
X
X
X
X
X
X
X
X
X
X
X
Please read these safety instructions carefully.
Please keep this User’s Manual for future reference.
The equipment should be operated within the recommended operating temperature.
The equipment should be operated only from the type of power source indicated on the rating label. Make sure the voltage of the power source is correct when connecting the equipment to the power outlet.
If the user’s equipment has a voltage selector switch, make sure that the switch is set to the proper position for the area.
The voltage selector switch is set at the factory to the correct voltage.
For pluggable equipment, ensure they are installed near a socket-outlet that is easily accessible.
Secure the power cord to prevent unnecessary accidents.
Do not place anything over the power cord.
If the equipment will not be in use for long periods of time, disconnect the equipment from mains to avoid being damaged by transient overvoltage.
All cautions and warnings on the equipment should be noted.
Please keep this equipment away from humidity.
Do not use this equipment near water or a heat source.
Place this equipment on a reliable surface when installing.
A drop or fall could cause injury.
Never pour any liquid into the opening, this could cause fire or electrical shock.
Important Safety Instructions 73
X
X
X
Openings in the case are provided for ventilation. Do not block or cover these openings. Make sure there is adequate space around the system for ventilation when setting up the work area. Never insert objects of any kind into the ventilation openings.
To avoid electrical shock, always unplug all power and modem cables from the wall outlets before removing covers.
Lithium Battery provided (real time clock battery)
“CAUTION - Risk of explosion if battery is replaced by an incorrect type. Dispose used batteries as instructed in the instructions”
X
X
Z
Z
Z
The equipment should be checked by service personnel if one of the following situation arises:
Z The power cord or plug is damaged.
Liquid has penetrated the equipment.
The equipment has been exposed to moisture.
Z
The equipment is not functioning or does not function according to the user’s manual.
The equipment has been dropped and damaged.
Z If the equipment has obvious sign of breakage.
Never open the equipment. For safety reasons, the equipment should only be opened by qualified service personnel.
74 Important Safety Instructions
cPCI-3920
Getting Service
Contact us should you require any service or assistance.
ADLINK Technology Inc. (Headquarters)
Web Site:
Sales & Service:
Telephone No.:
Fax No.:
Mailing Address: http://www.adlinktech.com
+886-2-8226-5877
+886-2-8226-5717
9F No. 166 Jian Yi Road, Chungho City,
Taipei 235, Taiwan
ADLINK Technology America Inc.
Sales & Service:
Toll-Free:
Fax No.:
Mailing Address: [email protected]
+1-866-4 ADLINK
+1-949-727-2099
8900 Research Drive, Irvine,
CA 92618, USA
ADLINK Technology Co. Ltd. (Beijing)
Sales & Service:
Telephone No.:
Fax No.:
Mailing Address: [email protected]
+86-10-5885-8666
+86-10-5885-8625
Rm. 801, Power Creative E, No. 1, B/D
Shang Di East Rd.
Beijing, 100085 China
ADLINK Technology Co. Ltd. (Shanghai)
Sales & Service:
Telephone No.:
Fax No.:
Mailing Address: [email protected]
+86-21-6495-5210
+86-21-5450-0414
4F, Bldg. 39, No.333 Qinjiang Road,
Cao He Jing High-Tech Park
Shanghai, 200233 China
ADLINK Technology Co. Ltd. (Shenzhen)
Sales & Service:
Telephone No.:
Fax No.:
Mailing Address: [email protected]
+86-755-2643-4858
+86-755-2664-6353
2F, C Block, Bld. A1,
Cyber-Tech Zone, Gao Xin Ave. Sec 7,
High-Tech Industrial Park S.,
Shenzhen, 518054 China
Getting Service 75
76
ADLINK Technology Inc. (European Liaison Office)
Sales & Service:
Telephone No.:
Fax No.:
Mailing Address: [email protected]
+49-211-495-5552
+49-211-495-5557
Nord Carree 3, 40477
Düsseldorf, Germany
ADLINK Technology Japan Corp.
Sales & Service:
Telephone No.:
Fax No.:
Mailing Address: [email protected]
+81-3-4455-3722
+81-3-5333-6040
Asahiseimei Hatagaya Bld. 8Fl. 1-1-2
Hatagaya Shibuya-ku, Tokyo, Japan
ADLINK Technology Inc. (South Korea Liaison Office)
Sales & Service:
Telephone No.:
Fax No.:
Mailing Address: [email protected]
+82-2-2057-0565
+82-2-2057-0563
#402, Dongsung B/D, 60-12,
Nonhyeon-dong Gangnam-gu,
Seoul, 135-010, South Korea
ADLINK Technology Singapore Pte. Ltd.
Sales & Service:
Telephone No.:
Fax No.:
Mailing Address: [email protected]
+65-6844-2261
+65-6844-2263
84 Genting Lane #07-02A,
Cityneon Design Center,
Singapore 349584
ADLINK Technology Singapore Pte. Ltd. (India Liaison Office)
Sales & Service:
Telephone No.:
Fax No.:
Mailing Address: [email protected]
+91-80-6560-5817
+91-80-2244-3548
No. 1357, Ground Floor, "Anupama",
Aurobindo Marg JP Nagar (Ph-1)
Bangalor, Karnataka 560078, India
Getting Service

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