ST STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx advanced Arm®-based 32-bit MCUs Reference Manual
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RM0008
Reference manual
STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and
STM32F107xx advanced Arm
®
-based 32-bit MCUs
Introduction
This reference manual is addressed to application developers.
It provides complete information on how to use the STM32F101xx, STM32F102xx,
STM32F103xx and STM32F105xx/STM32F107xx microcontroller memory and peripherals.
These devices, featuring different memory sizes, packages and peripherals, are referred to as STM32F10xxx throughout the document, unless otherwise specified.
For ordering information, mechanical and electrical device characteristics refer to the low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to the low- and medium-density STM32F102xx datasheets and to the STM32F105xx/STM32F107xx connectivity line datasheet.
For information on programming, erasing and protection of the internal Flash memory refer to:
PM0075 for low-, medium- high-density and connectivity line STM32F10xxx devices
PM0068 for XL-density STM32F10xxx devices.
For information on the Arm ® Cortex ® -M3 core, refer to PM0056, STM32F10xxx Cortex ® -M3 programming manual .
Related documents
Available from www.st.com
:
STM32F101xx, STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx datasheets
STM32F10xxx Cortex ® -M3 programming manual (PM0056)
STM32F10xxx Flash memory programming manual (PM0075)
STM32F10xxx XL-density Flash memory programming manual (PM0068)
February 2021 RM0008 Rev 21 1/1136 www.st.com
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Contents
Contents
RM0008
Overview of the manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . 65
Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Independent A/D and D/A converter supply and reference voltage . . . . 68
Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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Power on reset (POR)/power down reset (PDR) . . . . . . . . . . . . . . . . . . 70
Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 70
Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Auto-wakeup (AWU) from low-power mode . . . . . . . . . . . . . . . . . . . . . . 77
Power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . . . . . . 79
Backup registers (BKP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Backup data register x (BKP_DRx) (x = 1 ..42) . . . . . . . . . . . . . . . . . . . 83
RTC clock calibration register (BKP_RTCCR) . . . . . . . . . . . . . . . . . . . . 83
Backup control register (BKP_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Backup control/status register (BKP_CSR) . . . . . . . . . . . . . . . . . . . . . . 84
Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 101
Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 106
APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 109
AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 111
APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 112
APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 115
Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 118
Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Connectivity line devices: reset and clock control (RCC) . . . . . . . . . 123
Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 134
Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 141
APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 142
AHB Peripheral Clock enable register (RCC_AHBENR) . . . . . . . . . . . 145
APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 146
APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 148
Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 150
Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
AHB peripheral clock reset register (RCC_AHBRSTR) . . . . . . . . . . . . 153
Clock configuration register2 (RCC_CFGR2) . . . . . . . . . . . . . . . . . . . 154
RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
General-purpose and alternate-function I/Os
GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Alternate functions (AF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Software remapping of I/O alternate functions . . . . . . . . . . . . . . . . . . 162
GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
GPIO configurations for device peripherals . . . . . . . . . . . . . . . . . . . . . 166
Port configuration register low (GPIOx_CRL) (x=A..G) . . . . . . . . . . . . 171
Port configuration register high (GPIOx_CRH) (x=A..G) . . . . . . . . . . . 172
Port input data register (GPIOx_IDR) (x=A..G) . . . . . . . . . . . . . . . . . . 172
Port output data register (GPIOx_ODR) (x=A..G) . . . . . . . . . . . . . . . . 173
Port bit set/reset register (GPIOx_BSRR) (x=A..G) . . . . . . . . . . . . . . . 173
Port bit reset register (GPIOx_BRR) (x=A..G) . . . . . . . . . . . . . . . . . . . 174
Port configuration lock register (GPIOx_LCKR) (x=A..G) . . . . . . . . . . 174
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Alternate function I/O and debug configuration (AFIO) . . . . . . . . . . . . . 175
Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 . . . . 175
Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 . . . . . . . . . . 175
CAN1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
CAN2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
JTAG/SWD alternate function remapping . . . . . . . . . . . . . . . . . . . . . . 176
ADC alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Timer alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
USART alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . 180
I2C1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
SPI1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
SPI3/I2S3 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . 181
Ethernet alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . 181
Event control register (AFIO_EVCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 183
AF remap and debug I/O configuration register (AFIO_MAPR) . . . . . 184
External interrupt configuration register 1 (AFIO_EXTICR1) . . . . . . . . 191
External interrupt configuration register 2 (AFIO_EXTICR2) . . . . . . . . 191
External interrupt configuration register 3 (AFIO_EXTICR3) . . . . . . . . 192
External interrupt configuration register 4 (AFIO_EXTICR4) . . . . . . . . 192
AF remap and debug I/O configuration register2 (AFIO_MAPR2) . . . 193
GPIO and AFIO register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 197
SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . 207
Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
External interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . 209
Interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
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Rising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . 212
Falling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . 212
Software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . 213
Pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Single conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Continuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Channel-by-channel programmable sample time . . . . . . . . . . . . . . . . . . 225
Conversion on external trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Injected simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Regular simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Fast interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Slow interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Alternate trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Independent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Combined regular/injected simultaneous mode . . . . . . . . . . . . . . . . . . 233
Combined regular simultaneous + alternate trigger mode . . . . . . . . . . 233
Combined injected simultaneous + interleaved . . . . . . . . . . . . . . . . . . 234
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11.12.1 ADC status register (ADC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
11.12.2 ADC control register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
11.12.3 ADC control register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
11.12.4 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 244
11.12.5 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 245
11.12.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . 245
11.12.7 ADC watchdog high threshold register (ADC_HTR) . . . . . . . . . . . . . . 246
11.12.8 ADC watchdog low threshold register (ADC_LTR) . . . . . . . . . . . . . . . 246
11.12.9 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 247
11.12.10 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 248
11.12.11 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 249
11.12.12 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 250
11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . . . . . . . . . . . 251
11.12.14 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 251
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
DAC output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Dual DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Independent trigger without wave generation . . . . . . . . . . . . . . . . . . . 261
Independent trigger with same LFSR generation . . . . . . . . . . . . . . . . 262
Independent trigger with different LFSR generation . . . . . . . . . . . . . . 262
Independent trigger with same triangle generation . . . . . . . . . . . . . . . 262
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Independent trigger with different triangle generation . . . . . . . . . . . . . 263
Simultaneous software start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Simultaneous trigger without wave generation . . . . . . . . . . . . . . . . . . 263
Simultaneous trigger with same LFSR generation . . . . . . . . . . . . . . . 264
Simultaneous trigger with different LFSR generation . . . . . . . . . . . . . 264
12.4.10 Simultaneous trigger with same triangle generation . . . . . . . . . . . . . . 264
12.4.11 Simultaneous trigger with different triangle generation . . . . . . . . . . . . 265
DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
DAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . 268
DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
12.5.10 DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
12.5.11 DUAL DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
12.5.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 272
12.5.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 272
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 274
DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
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Programmable data width, data alignment and endians . . . . . . . . . . . 279
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 284
DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 285
DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Advanced-control timers (TIM1 and TIM8) . . . . . . . . . . . . . . . . . . . . . 292
TIM1 and TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
TIM1 and TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
TIM1 and TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
14.3.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 321
14.3.13 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 326
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14.3.19 TIMx and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 334
TIM1 and TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
TIM1 and TIM8 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . 338
TIM1 and TIM8 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . 339
TIM1 and TIM8 slave mode control register (TIMx_SMCR) . . . . . . . . 342
TIM1 and TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . 344
TIM1 and TIM8 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . 346
TIM1 and TIM8 event generation register (TIMx_EGR) . . . . . . . . . . . . 347
TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . 349
TIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . 351
TIM1 and TIM8 capture/compare enable register (TIMx_CCER) . . . . 353
14.4.10 TIM1 and TIM8 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 356
14.4.11 TIM1 and TIM8 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 356
14.4.12 TIM1 and TIM8 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . 356
14.4.13 TIM1 and TIM8 repetition counter register (TIMx_RCR) . . . . . . . . . . . 357
14.4.14 TIM1 and TIM8 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . 357
14.4.15 TIM1 and TIM8 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . 358
14.4.16 TIM1 and TIM8 capture/compare register 3 (TIMx_CCR3) . . . . . . . . . 358
14.4.17 TIM1 and TIM8 capture/compare register 4 (TIMx_CCR4) . . . . . . . . . 359
14.4.18 TIM1 and TIM8 break and dead-time register (TIMx_BDTR) . . . . . . . 359
14.4.19 TIM1 and TIM8 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . 361
14.4.20 TIM1 and TIM8 DMA address for full transfer (TIMx_DMAR) . . . . . . . 362
General-purpose timers (TIM2 to TIM5) . . . . . . . . . . . . . . . . . . . . . . . . 365
TIM2 to TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
RM0008 Rev 21 11/1136
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Contents
RM0008
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
15.3.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 391
15.3.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 395
TIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 404
TIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 406
TIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . 407
TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 409
TIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
TIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 412
TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 413
TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . 416
TIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . 417
15.4.12 TIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 419
15.4.13 TIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 419
15.4.14 TIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 420
15.4.15 TIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 420
15.4.16 TIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 420
15.4.17 TIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 421
15.4.18 TIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 421
General-purpose timers (TIM9 to TIM14) . . . . . . . . . . . . . . . . . . . . . . . 425
TIM9 to TIM14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
TIM9 to TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
TIM9/TIM12 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
TIM10/TIM11 and TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . 427
TIM9 to TIM14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
12/1136 RM0008 Rev 21
RM0008 Contents
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
PWM input mode (only for TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
16.3.11 TIM9/12 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . 443
TIM9 and TIM12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
TIM9/12 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 447
TIM9/12 slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . 448
TIM9/12 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . . 449
TIM9/12 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
TIM9/12 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . 451
TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . 452
TIM9/12 capture/compare enable register (TIMx_CCER) . . . . . . . . . . 455
TIM9/12 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
TIM9/12 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
16.4.10 TIM9/12 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . 456
16.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . 457
16.4.12 TIM9/12 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . 457
TIM10/11/13/14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
TIM10/11/13/14 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . 460
TIM10/11/13/14 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . 461
TIM10/11/13/14 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . 461
TIM10/11/13/14 event generation register (TIMx_EGR) . . . . . . . . . . . 462
TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) . . 462
TIM10/11/13/14 capture/compare enable register (TIMx_CCER) . . . . 465
TIM10/11/13/14 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 466
TIM10/11/13/14 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 466
TIM10/11/13/14 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . 466
RM0008 Rev 21 13/1136
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Contents
RM0008
16.5.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . 467
Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
TIM6 and TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
TIM6 and TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
TIM6 and TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . 470
TIM6 and TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
TIM6 and TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . 476
TIM6 and TIM7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . 478
TIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . 478
TIM6 and TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . 479
TIM6 and TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . 479
TIM6 and TIM7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 479
TIM6 and TIM7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 480
TIM6 and TIM7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . 480
TIM6 and TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
Resetting RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Reading RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Configuring RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
RTC control register high (RTC_CRH) . . . . . . . . . . . . . . . . . . . . . . . . 487
RTC control register low (RTC_CRL) . . . . . . . . . . . . . . . . . . . . . . . . . 488
RTC prescaler load register (RTC_PRLH / RTC_PRLL) . . . . . . . . . . . 489
RTC prescaler divider register (RTC_DIVH / RTC_DIVL) . . . . . . . . . . 490
14/1136 RM0008 Rev 21
RM0008
Contents
RTC counter register (RTC_CNTH / RTC_CNTL) . . . . . . . . . . . . . . . . 491
RTC alarm register high (RTC_ALRH / RTC_ALRL) . . . . . . . . . . . . . . 492
RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 505
Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . 507
FSMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 510
External device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .511
RM0008 Rev 21 15/1136
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Contents
RM0008
NOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
NAND/PC Card address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
NOR Flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 515
NOR Flash/PSRAM controller asynchronous transactions . . . . . . . . . 517
Synchronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
NOR/PSRAM control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
NAND Flash/PC Card controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
NAND Flash / PC Card supported memories and transactions . . . . . . 551
Timing diagrams for NAND and PC Card . . . . . . . . . . . . . . . . . . . . . . 551
NAND Flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
NAND Flash prewait functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
PC Card/CompactFlash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
NAND Flash/PC Card control registers . . . . . . . . . . . . . . . . . . . . . . . . 557
FSMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . 566
SDIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
SDIO AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
Card identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
Operating voltage range validation . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Card identification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Stream access, stream write and stream read (MultiMediaCard only) 584
Erase: group erase and sector erase . . . . . . . . . . . . . . . . . . . . . . . . . 585
Wide bus selection or deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
16/1136 RM0008 Rev 21
RM0008 Contents
22.4.14 Commands and responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
R1 (normal response command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
R2 (CID, CSD register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
SDIO I/O card-specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
SDIO I/O read wait operation by SDIO_D2 signalling . . . . . . . . . . . . . 604
SDIO read wait operation by stopping SDIO_CK . . . . . . . . . . . . . . . . 605
SDIO suspend/resume operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
CE-ATA specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Command completion signal disable . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Command completion signal enable . . . . . . . . . . . . . . . . . . . . . . . . . . 606
Aborting CMD61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
SDIO power control register (SDIO_POWER) . . . . . . . . . . . . . . . . . . . 607
SDI clock control register (SDIO_CLKCR) . . . . . . . . . . . . . . . . . . . . . 607
SDIO argument register (SDIO_ARG) . . . . . . . . . . . . . . . . . . . . . . . . . 608
SDIO command register (SDIO_CMD) . . . . . . . . . . . . . . . . . . . . . . . . 609
SDIO command response register (SDIO_RESPCMD) . . . . . . . . . . . 610
SDIO response 1..4 register (SDIO_RESPx) . . . . . . . . . . . . . . . . . . . 610
SDIO data timer register (SDIO_DTIMER) . . . . . . . . . . . . . . . . . . . . . 611
SDIO data length register (SDIO_DLEN) . . . . . . . . . . . . . . . . . . . . . . 611
SDIO data control register (SDIO_DCTRL) . . . . . . . . . . . . . . . . . . . . . 612
22.9.10 SDIO data counter register (SDIO_DCOUNT) . . . . . . . . . . . . . . . . . . 613
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Contents
RM0008
22.9.11 SDIO status register (SDIO_STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
22.9.12 SDIO interrupt clear register (SDIO_ICR) . . . . . . . . . . . . . . . . . . . . . . 615
22.9.13 SDIO mask register (SDIO_MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
22.9.14 SDIO FIFO counter register (SDIO_FIFOCNT) . . . . . . . . . . . . . . . . . . 619
22.9.15 SDIO data FIFO register (SDIO_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . 620
Universal serial bus full-speed device interface (USB) . . . . . . . . . . . 622
USB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
Description of USB blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
Generic USB device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
Double-buffered endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Isochronous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
Suspend/Resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Endpoint-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
USB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
bxCAN general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
CAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Control, status and configuration registers . . . . . . . . . . . . . . . . . . . . . 655
bxCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Sleep mode (low-power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
18/1136 RM0008 Rev 21
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Contents
Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 659
bxCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
CAN control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
CAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
bxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
2 S features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
Configuring the SPI in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
Configuring the SPI in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 707
Configuring the SPI for half-duplex communication . . . . . . . . . . . . . . . 707
Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 708
SPI communication using DMA (direct memory addressing) . . . . . . . . 719
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Contents
RM0008
S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
2
S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
2 S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
2
S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
2 S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
SPI control register 1 (SPI_CR1) (not used in I
2
S mode) . . . . . . . . . . 742
SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
SPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
SPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
SPI CRC polynomial register (SPI_CRCPR) (not used in I
2
S mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
SPI RX CRC register (SPI_RXCRCR) (not used in I
2 S mode) . . . . . . 747
SPI TX CRC register (SPI_TXCRCR) (not used in I
S mode) . . . . . . . 748
S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . . 748
S prescaler register (SPI_I2SPR) . . . . . . . . . . . . . . . . . . . . . . . 750
Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 752
C introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
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C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
C debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
2 C Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
2
C Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
2 C Own address register 1 (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . 776
2
C Own address register 2 (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . 776
2 C Data register (I2C_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
2
C Status register 1 (I2C_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
2 C Status register 2 (I2C_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
2
C Clock control register (I2C_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . 781
2 C TRISE register (I2C_TRISE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
Fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
USART receiver’s tolerance to clock deviation . . . . . . . . . . . . . . . . . . 800
Multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
LIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 803
USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
27.3.10 Single-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 807
27.3.13 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . 812
USART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
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RM0008
Status register (USART_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
Data register (USART_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
Baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
Guard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . . 826
USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
USB on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . . . 828
OTG_FS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
Host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
Peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
OTG_FS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
OTG full-speed core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
Full-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
OTG dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
HNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
SRP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
SRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
Peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
SRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
OTG low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
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Dynamic update of the OTG_FS_HFIR register . . . . . . . . . . . . . . . . . . . 845
28.16 OTG_FS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
28.16.5 OTG_FS power and clock gating control register
(OTG_FS_PCGCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
28.17 OTG_FS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
Ethernet (ETH): media access control (MAC) with
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Contents RM0008
Ethernet functional description: SMI, MII and RMII . . . . . . . . . . . . . . . . 972
Station management interface: SMI . . . . . . . . . . . . . . . . . . . . . . . . . . 972
Media-independent interface: MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Reduced media-independent interface: RMII . . . . . . . . . . . . . . . . . . . 977
Ethernet functional description: MAC 802.3 . . . . . . . . . . . . . . . . . . . . . . 979
MAC 802.3 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
MAC frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
MAC frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
MAC loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
MAC management counters: MMC . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
Power management: PMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
Precision time protocol (IEEE1588 PTP) . . . . . . . . . . . . . . . . . . . . . . 1004
Ethernet functional description: DMA controller operation . . . . . . . . . . 1010
Initialization of a transfer using DMA . . . . . . . . . . . . . . . . . . . . . . . . . 1011
Host bus burst access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
Host data buffer alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
Buffer size calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
Error response to DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
Tx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
Rx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
Ethernet register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
MAC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
MMC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
IEEE 1588 time stamp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
DMA register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Ethernet register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
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Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
Reference Arm® documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . 1081
Mechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . 1082
Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . 1083
Using serial wire and releasing the unused debug pins as GPIOs . . 1085
STM32F10xxx JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . 1085
ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
Boundary scan TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
®
-M3 TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
® -M3 JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090
SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090
SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . 1091
DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093
31.11 Capability of the debugger host to connect under system reset . . . . . 1096
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RM0008
31.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . 1097
31.14.2 Time stamp packets, synchronization and overflow packets . . . . . . . 1097
31.15 ETM (Embedded Trace Macrocell™) . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
31.15.2 ETM signal protocol and packet types . . . . . . . . . . . . . . . . . . . . . . . . 1099
31.16 MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . .1100
31.16.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 1100
31.16.2 Debug support for timers, watchdog, bxCAN and I
C . . . . . . . . . . . . 1101
31.16.3 Debug MCU configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 1101
31.17.4 TPUI frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . 1107
31.17.5 Transmission of the synchronization frame packet . . . . . . . . . . . . . . 1107
31.17.8 TRACECLKIN connection inside the STM32F10xxx . . . . . . . . . . . . . 1108
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List of tables
List of tables
ADC1 external trigger injected conversion alternate function remapping . . . . . . . . . . . . . 177
ADC1 external trigger regular conversion alternate function remapping . . . . . . . . . . . . . 177
ADC2 external trigger injected conversion alternate function remapping . . . . . . . . . . . . . 177
ADC2 external trigger regular conversion alternate function remapping . . . . . . . . . . . . . 178
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List of tables RM0008
Programmable data width and endian behavior (when bits PINC = MINC = 1) . . . . . . . . 279
Minimum and maximum timeout values @36 MHz (f
PCLK1
) . . . . . . . . . . . . . . . . . . . . . . . 503
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Table 108. NOR Flash/PSRAM controller: example of supported memories and transactions . . . . . 516
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List of tables RM0008
Table 183. Audio-frequency precision using standard 8 MHz HSE
Table 184. Audio-frequency precision using standard 25 MHz and PLL3
Table 185. Audio-frequency precision using standard 14.7456 MHz and PLL3
2 S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
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® -M3 AHB-AP registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094
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List of figures
List of figures
RM0008
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Fast interleaved mode on 1 channel in continuous conversion mode . . . . . . . . . . . . . . . 231
Alternate trigger: 4 injected channels (each ADC) in discontinuous model . . . . . . . . . . . 233
DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 260
DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 261
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DMA block diagram in low-, medium- high- and XL-density devices . . . . . . . . . . . . . . . . 276
Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 299
Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 299
Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 303
Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 304
Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 305
Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 306
Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 306
Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 307
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List of figures RM0008
Figure 107. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 372
Figure 108. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 372
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Figure 154. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 432
Figure 180. RTC second and alarm waveform example with PR=0003, ALARM=00004 . . . . . . . . . . 486
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List of figures RM0008
Figure 241. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and
Figure 242. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0,
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2
2
2
S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . . . . . . . . . . . . . . 725
S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . . 725
2 S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . . . . . 726
2 S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
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Figure 361. Block diagram of STM32 MCU and Cortex ®
-M3-level debug support . . . . . . . . . . . . . . 1080
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Overview of the manual
1 Overview of the manual
RM0008
Legend for
: the section in each row applies to products in columns marked with “
"
Table 1. Sections related to each STM32F10xxx product
Reference
Section 2: Documentation conventions
Section 3: Memory and bus architecture
Section 4: CRC calculation unit
Section 5: Power control (PWR)
Section 6: Backup registers (BKP)
Section 7: Low-, medium-, high- and XLdensity reset and clock control (RCC)
Section 8: Connectivity line devices: reset and clock control (RCC)
Section 9: General-purpose and alternatefunction I/Os (GPIOs and AFIOs)
Section 10: Interrupts and events
Section 13: Direct memory access controller (DMA)
Section 11: Analog-to-digital converter
Section 12: Digital-to-analog converter
Section 14: Advanced-control timers (TIM1 and TIM8)
Section 15: General-purpose timers (TIM2 to TIM5)
Section 16: General-purpose timers (TIM9 to TIM14)
Section 17: Basic timers (TIM6 and TIM7)
Section 18: Real-time clock (RTC)
(1)
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Table 1. Sections related to each STM32F10xxx product (continued)
Reference
Section 19: Independent watchdog (IWDG)
Section 20: Window watchdog (WWDG)
Section 21: Flexible static memory controller (FSMC)
Section 22: Secure digital input/output interface (SDIO)
Section 23: Universal serial bus full-speed device interface (USB)
Section 24: Controller area network
Section 25: Serial peripheral interface
Section 26: Inter-integrated circuit (I2C) interface
Section 27: Universal synchronous asynchronous receiver transmitter
Section 28: USB on-the-go full-speed
Section 29: Ethernet (ETH): media access control (MAC) with DMA controller
Section 30: Device electronic signature
Section 31: Debug support (DBG)
1. Available only on XL-density devices.
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Overview of the manual RM0008
Legend for
:
The section in this row must be read when using the peripherals in columns with “
"
The section in this row can optionally be read when using the peripherals in columns with “
"
Table 2. Sections related to each peripheral
Reference
Section 3: Memory and bus architecture
Section 4: CRC calculation unit
Section 5: Power control (PWR)
Section 6: Backup registers (BKP)
Section 7: Low-, medium-, high- and XLdensity reset and clock control (RCC)
Section 8: Connectivity line devices: reset and clock control (RCC)
Section 9: Generalpurpose and alternatefunction I/Os (GPIOs and AFIOs)
Section 10: Interrupts and events
Section 13: Direct memory access controller (DMA)
Section 11: Analog-todigital converter (ADC)
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Table 2. Sections related to each peripheral (continued)
Reference
Section 12: Digital-toanalog converter (DAC)
Section 14: Advancedcontrol timers (TIM1 and TIM8)
Section 15: Generalpurpose timers (TIM2 to
Section 16: Generalpurpose timers (TIM9 to
Section 17: Basic timers (TIM6 and TIM7)
Section 18: Real-time clock (RTC)
Section 20: Window watchdog (WWDG)
Section 21: Flexible static memory controller
Section 22: Secure digital input/output interface (SDIO)
Section 23: Universal serial bus full-speed device interface (USB)
Section 24: Controller area network (bxCAN)
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Overview of the manual
Table 2. Sections related to each peripheral (continued)
RM0008
Reference
Section 25: Serial peripheral interface
Section 26: Interintegrated circuit (I2C) interface
Section 27: Universal synchronous asynchronous receiver transmitter (USART)
Section 28: USB onthe-go full-speed
(ETH): media access control (MAC) with DMA controller
Section 30: Device electronic signature
Section 31: Debug support (DBG)
44/1136 RM0008 Rev 21
RM0008 Documentation conventions
The STM32F10xxx devices have an Arm
®(a)
Cortex
®
-M3 core.
2.2 List of abbreviations for registers
The following abbreviations are used in register descriptions: read/write (rw) read-only (r) write-only (w)
Software can read and write to these bits.
Software can only read these bits.
Software can only write to this bit. Reading the bit returns the reset value.
read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on the bit value.
read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on the bit value.
read/clear by read
(rc_r) read/set (rs)
Software can read this bit. Reading this bit automatically clears it to ‘0’. Writing ‘0’ has no effect on the bit value.
Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value.
read-only write trigger (rt_w) toggle (t)
Reserved (Res.)
Software can read this bit. Writing ‘0’ or ‘1’ triggers an event but has no effect on the bit value.
Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect.
Reserved bit, must be kept at reset value.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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Documentation conventions RM0008
2.3 Glossary
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Word: data of 32-bit length.
Half-word: data of 16-bit length.
Byte: data of 8-bit length.
For peripheral availability and number across all STM32F10xxx sales types, refer to the low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to the low- and medium-density STM32F102xx datasheets and to the connectivity line devices,
STM32F105xx/STM32F107xx.
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3 Memory and bus architecture
Memory and bus architecture
In low-, medium-, high- and XL-density devices, the main system consists of:
Four masters:
– Cortex
®
-M3 core DCode bus (D-bus) and System bus (S-bus)
– GP-DMA1 & 2 (general-purpose DMA)
Four slaves:
– Internal SRAM
– Internal Flash memory
– FSMC
– AHB to APBx (APB1 or APB2), which connect all the APB peripherals
These are interconnected using a multilayer AHB bus architecture as shown in Figure 1
:
Figure 1. System architecture (low-, medium-, XL-density devices)
ICode
FLITF
Flash
DCode
Cortex-M3
Sys tem
SRAM
DMA1
DMA
FSMC
SDIO
Ch.1
Ch.2
Ch.7
AHB system bus
Reset & clock control (RCC)
Bridge 2
Bridge 1
APB2
APB 1
DMA2
DMA Request
ADC1
ADC2
ADC3
USART1
SPI1
TIM1
TIM8
GPIOA
GPIOB
GPIOC DAC
GPIOD
GPIOE
PWR
BKP
SPI2/I2S
IWDG
GPIOF
GPIOG bxCAN
USB
WWDG
RTC
EXTI
AFIO
I2C2
I2C1
UART5
UART4
USART3
TIM7
TIM6
TIM5
TIM4
TIM3
Ch.1
Ch.2
Ch.5
DMA request ai14800c
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Memory and bus architecture RM0008
In connectivity line devices the main system consists of:
Five masters:
– Cortex ® -M3 core DCode bus (D-bus) and System bus (S-bus)
– GP-DMA1 & 2 (general-purpose DMA)
– Ethernet DMA
Three slaves:
– Internal SRAM
– Internal Flash memory
– AHB to APB bridges (AHB to APBx), which connect all the APB peripherals
These are interconnected using a multilayer AHB bus architecture as shown in Figure 2
:
Figure 2. System architecture in connectivity line devices
ICode
FLITF
Flash
DCode
Cortex-M3
Sys tem
SRAM
DMA1
DMA
Reset & clock control (RCC)
Ch.1
Ch.2
AHB system bus Bridge 2
Bridge 1
APB2
Ch.7
DMA2
Ch.1
Ch.2
DMA request
APB 1
ADC1
ADC2
USART1
SPI1
TIM1
GPIOA
GPIOB
GPIOC DAC
GPIOD PWR SPI2/I2S
GPIOE
EXTI
AFIO
BKP
CAN1
CAN2
IWDG
WWDG
RTC
I2C2
I2C1
TIM7
TIM6
UART5
UART4
TIM5
TIM4
USART3 TIM3
TIM2
DMA request
Ch.5
Ethernet MAC
USB OTG FS
ICode bus
This bus connects the Instruction bus of the Cortex
®
-M3 core to the Flash memory instruction interface. Prefetching is performed on this bus.
ai15810
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Note:
Memory and bus architecture
DCode bus
This bus connects the DCode bus (literal load and debug access) of the Cortex ® -M3 core to the Flash memory Data interface.
System bus
This bus connects the system bus of the Cortex ® -M3 core (peripherals bus) to a BusMatrix which manages the arbitration between the core and the DMA.
DMA bus
This bus connects the AHB master interface of the DMA to the BusMatrix which manages the access of CPU DCode and DMA to SRAM, Flash memory and peripherals.
BusMatrix
The BusMatrix manages the access arbitration between the core system bus and the DMA master bus. The arbitration uses a Round Robin algorithm. In connectivity line devices, the
BusMatrix is composed of five masters (CPU DCode, System bus, Ethernet DMA, DMA1 and DMA2 bus) and three slaves (FLITF, SRAM and AHB2APB bridges). In other devices, the BusMatrix is composed of four masters (CPU DCode, System bus, DMA1 bus and
DMA2 bus) and four slaves (FLITF, SRAM, FSMC and AHB2APB bridges).
AHB peripherals are connected on system bus through a BusMatrix to allow DMA access.
AHB/APB bridges (APB)
The two AHB/APB bridges provide full synchronous connections between the AHB and the
2 APB buses. APB1 is limited to 36 MHz, APB2 operates at full speed (up to 72 MHz depending on the device).
for the address mapping of the peripherals connected to each bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF).
Before using a peripheral you have to enable its clock in the RCC_AHBENR,
RCC_APB2ENR or RCC_APB1ENR register.
When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.
For the detailed mapping of peripheral registers refer to the related sections.
The addressable memory space is divided into 8 main blocks, each of 512 MB.
All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved”). Refer to the Memory map figure in the corresponding product datasheet.
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Memory and bus architecture RM0008
See the datasheet corresponding to your device for a comprehensive diagram of the memory map.
gives the boundary addresses of the peripherals available in all
STM32F10xxx devices.
Boundary address
Table 3. Register boundary addresses
Peripheral Bus
0xA000 0000 - 0xA000 0FFF FSMC
0x5000 0000 - 0x5003 FFFF USB OTG FS
0x4003 0000 - 0x4FFF FFFF Reserved
0x4002 8000 - 0x4002 9FFF
0x4002 3400 - 0x4002 7FFF
0x4002 3000 - 0x4002 33FF
0x4002 2000 - 0x4002 23FF
0x4002 1400 - 0x4002 1FFF
0x4002 1000 - 0x4002 13FF
0x4002 0800 - 0x4002 0FFF
0x4002 0400 - 0x4002 07FF
Ethernet
Reserved
CRC
Flash memory interface
Reserved
Reset and clock control RCC
Reserved
DMA2
0x4002 0000 - 0x4002 03FF
0x4001 8400 - 0x4001 FFFF
0x4001 8000 - 0x4001 83FF
DMA1
Reserved
SDIO
AHB
Register map
-
-
-
-
-
-
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RM0008 Memory and bus architecture
Boundary address
Table 3. Register boundary addresses (continued)
0x4001 5800 - 0x4001 7FFF
0x4001 5400 - 0x4001 57FF
Reserved
TIM11 timer
0x4001 5000 - 0x4001 53FF TIM10 timer
0x4001 4C00 - 0x4001 4FFF TIM9 timer
0x4001 4000 - 0x4001 4BFF Reserved
0x4001 3C00 - 0x4001 3FFF ADC3
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
USART1
TIM8 timer
0x4001 3000 - 0x4001 33FF SPI1
0x4001 2C00 - 0x4001 2FFF TIM1 timer
0x4001 2800 - 0x4001 2BFF
0x4001 2400 - 0x4001 27FF
ADC2
ADC1
0x4001 2000 - 0x4001 23FF GPIO Port G
0x4001 1C00 - 0x4001 1FFF GPIO Port F
0x4001 1800 - 0x4001 1BFF GPIO Port E
0x4001 1400 - 0x4001 17FF
0x4001 1000 - 0x4001 13FF
GPIO Port D
GPIO Port C
0x4001 0C00 - 0x4001 0FFF GPIO Port B
0x4001 0800 - 0x4001 0BFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
GPIO Port A
EXTI
AFIO
Peripheral Bus
APB2
Register map
-
-
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Memory and bus architecture RM0008
Boundary address
Table 3. Register boundary addresses (continued)
Peripheral Bus Register map
0x4000 7800 - 0x4000 FFFF
0x4000 7400 - 0x4000 77FF
Reserved
DAC
0x4000 7000 - 0x4000 73FF Power control PWR
0x4000 6C00 - 0x4000 6FFF Backup registers (BKP)
0x4000 6400 - 0x4000 67FF bxCAN1
0x4000 6800 - 0x4000 6BFF bxCAN2
0x4000 6000
(1)
- 0x4000 63FF Shared USB/CAN SRAM 512 bytes
0x4000 5C00 - 0x4000 5FFF USB device FS registers
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
I2C2
I2C1
0x4000 5000 - 0x4000 53FF UART5
0x4000 4C00 - 0x4000 4FFF UART4
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
USART3
USART2
Reserved
0x4000 3C00 - 0x4000 3FFF SPI3/I2S
0x4000 3800 - 0x4000 3BFF SPI2/I2S
0x4000 3400 - 0x4000 37FF Reserved
0x4000 3000 - 0x4000 33FF Independent watchdog (IWDG)
0x4000 2C00 - 0x4000 2FFF Window watchdog (WWDG)
0x4000 2800 - 0x4000 2BFF RTC
0x4000 2400 - 0x4000 27FF
0x4000 2000 - 0x4000 23FF
Reserved
TIM14 timer
0x4000 1C00 - 0x4000 1FFF TIM13 timer
0x4000 1800 - 0x4000 1BFF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
TIM12 timer
TIM7 timer
TIM6 timer
0x4000 0C00 - 0x4000 0FFF TIM5 timer
0x4000 0800 - 0x4000 0BFF TIM4 timer
0x4000 0400 - 0x4000 07FF TIM3 timer
0x4000 0000 - 0x4000 03FF TIM2 timer
APB1
-
-
-
-
-
1. This shared SRAM can be fully accessed only in low-, medium-, high- and XL-density devices, not in connectivity line devices.
52/1136 RM0008 Rev 21
RM0008 Memory and bus architecture
The STM32F10xxx features up to 96 Kbytes of static SRAM. It can be accessed as bytes, half-words (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000.
The Cortex ® -M3 memory map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region.
In the STM32F10xxx both peripheral registers and SRAM are mapped in a bit-band region.
This allows single bit-band write and read operations to be performed. The operations are only available for Cortex ® -M3 accesses, not from other bus masters (e.g. DMA).
A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + ( byte_offset x 32) + ( bit_number × 4) where: bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit.
bit_band_base is the starting address of the alias region byte_offset is the number of the byte in the bit-band region that contains the targeted bit bit_number is the bit position (0-7) of the targeted bit.
Example:
The following example shows how to map bit 2 of the byte located at SRAM address
0x20000300 in the alias region:
0x22006008 = 0x22000000 + (0x300*32) + (2*4).
Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit
2 of the byte at SRAM address 0x20000300.
Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM address 0x20000300 (0x01: bit set; 0x00: bit reset).
For more information on Bit-Banding refer to the Cortex ® -M3 Technical Reference Manual .
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Memory and bus architecture RM0008
The high-performance Flash memory module has the following key features:
For XL-density devices: density of up to 1 Mbyte with dual bank architecture for readwhile-write (RWW) capability:
– bank 1: fixed size of 512 Kbytes
– bank 2: up to 512 Kbytes
For other devices: density of up to 512 Kbytes
Memory organization: the Flash memory is organized as a main block and an information block:
– Main memory block of size: up to 128 Kbytes × 64 bits divided into 512 pages of 2 Kbytes each (see
for XL-density devices up to 4 Kb × 64 bits divided into 32 pages of 1 Kbyte each for low-density devices
up to 16 Kb × 64 bits divided into 128 pages of 1 Kbyte each for medium-density devices (see
up to 64 Kb × 64 bits divided into 256 pages of 2 Kbytes each (see Table 6 ) for
high-density devices up to 32 Kbit × 64 bits divided into 128 pages of 2 Kbytes each (see
) for connectivity line devices
– Information block of size:
770 × 64 bits for XL-density devices (see Table 8 )
2360 × 64 bits for connectivity line devices (see Table 7
)
258 × 64 bits for other devices (see
The Flash memory interface (FLITF) features:
Read interface with prefetch buffer (2x64-bit words)
Option byte Loader
Flash Program / Erase operation
Read / Write protection
Block
Main memory
Table 4. Flash module organization (low-density devices)
Name Base addresses
Page 0
Page 1
Page 2
Page 3
Page 4
.
.
.
Page 31
0x0800 0000 - 0x0800 03FF
0x0800 0400 - 0x0800 07FF
0x0800 0800 - 0x0800 0BFF
0x0800 0C00 - 0x0800 0FFF
0x0800 1000 - 0x0800 13FF
.
.
.
0x0800 7C00 - 0x0800 7FFF
Size (bytes)
1 K
1 K
1 K
1 K
1 K
.
.
.
1 K
54/1136 RM0008 Rev 21
RM0008 Memory and bus architecture
Table 4. Flash module organization (low-density devices) (continued)
Block Name Base addresses Size (bytes)
Information block
Flash memory interface registers
System memory
Option bytes
FLASH_ACR
FLASH_KEYR
FLASH_OPTKEYR
FLASH_SR
FLASH_CR
FLASH_AR
Reserved
FLASH_OBR
FLASH_WRPR
0x1FFF F000 - 0x1FFF F7FF
0x1FFF F800 - 0x1FFF F80F
0x4002 2000 - 0x4002 2003
0x4002 2004 - 0x4002 2007
0x4002 2008 - 0x4002 200B
0x4002 200C - 0x4002 200F
0x4002 2010 - 0x4002 2013
0x4002 2014 - 0x4002 2017
0x4002 2018 - 0x4002 201B
0x4002 201C - 0x4002 201F
0x4002 2020 - 0x4002 2023
4
4
4
4
2 K
16
4
4
4
4
4
Block
Table 5. Flash module organization (medium-density devices)
Name Base addresses Size (bytes)
Main memory
Information block
Flash memory interface registers
Page 0
Page 1
Page 2
Page 3
Page 4
.
.
.
Page 127
System memory
Option bytes
FLASH_ACR
FLASH_KEYR
FLASH_OPTKEYR
FLASH_SR
FLASH_CR
FLASH_AR
Reserved
FLASH_OBR
FLASH_WRPR
0x0800 0000 - 0x0800 03FF
0x0800 0400 - 0x0800 07FF
0x0800 0800 - 0x0800 0BFF
0x0800 0C00 - 0x0800 0FFF
0x0800 1000 - 0x0800 13FF
.
.
.
0x0801 FC00 - 0x0801 FFFF
0x1FFF F000 - 0x1FFF F7FF
0x1FFF F800 - 0x1FFF F80F
0x4002 2000 - 0x4002 2003
0x4002 2004 - 0x4002 2007
0x4002 2008 - 0x4002 200B
0x4002 200C - 0x4002 200F
0x4002 2010 - 0x4002 2013
0x4002 2014 - 0x4002 2017
0x4002 2018 - 0x4002 201B
0x4002 201C - 0x4002 201F
0x4002 2020 - 0x4002 2023
4
4
4
16
4
4
4
4
4
4
1 K
.
.
.
1 K
2 K
1 K
1 K
1 K
1 K
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Memory and bus architecture RM0008
Block
Main memory
Flash memory interface registers
Table 6. Flash module organization (high-density devices)
Name Base addresses Size (bytes)
Information block
Page 0
Page 1
Page 2
Page 3
.
.
.
Page 255
System memory
Option bytes
FLASH_ACR
FLASH_KEYR
FLASH_OPTKEYR
FLASH_SR
FLASH_CR
FLASH_AR
Reserved
FLASH_OBR
FLASH_WRPR
0x0800 0000 - 0x0800 07FF
0x0800 0800 - 0x0800 0FFF
0x0800 1000 - 0x0800 17FF
0x0800 1800 - 0x0800 1FFF
.
.
.
0x0807 F800 - 0x0807 FFFF
0x1FFF F000 - 0x1FFF F7FF
0x1FFF F800 - 0x1FFF F80F
0x4002 2000 - 0x4002 2003
0x4002 2004 - 0x4002 2007
0x4002 2008 - 0x4002 200B
0x4002 200C - 0x4002 200F
0x4002 2010 - 0x4002 2013
0x4002 2014 - 0x4002 2017
0x4002 2018 - 0x4002 201B
0x4002 201C - 0x4002 201F
0x4002 2020 - 0x4002 2023
2 K
16
4
4
4
4
2 K
2 K
2 K
2 K
.
.
.
2 K
4
4
4
4
4
Block
Table 7. Flash module organization (connectivity line devices)
Name Base addresses Size (bytes)
Main memory
Information block
Page 0
Page 1
Page 2
Page 3
.
.
.
Page 127
System memory
Option bytes
0x0800 0000 - 0x0800 07FF
0x0800 0800 - 0x0800 0FFF
0x0800 1000 - 0x0800 17FF
0x0800 1800 - 0x0800 1FFF
.
.
.
0x0803 F800 - 0x0803 FFFF
0x1FFF B000 - 0x1FFF F7FF
0x1FFF F800 - 0x1FFF F80F
2 K
2 K
2 K
2 K
.
.
.
2 K
18 K
16
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Table 7. Flash module organization (connectivity line devices) (continued)
Block Name Base addresses Size (bytes)
Flash memory interface registers
FLASH_ACR
FLASH_KEYR
FLASH_OPTKEYR
FLASH_SR
FLASH_CR
FLASH_AR
Reserved
FLASH_OBR
FLASH_WRPR
0x4002 2000 - 0x4002 2003
0x4002 2004 - 0x4002 2007
0x4002 2008 - 0x4002 200B
0x4002 200C - 0x4002 200F
0x4002 2010 - 0x4002 2013
0x4002 2014 - 0x4002 2017
0x4002 2018 - 0x4002 201B
0x4002 201C - 0x4002 201F
0x4002 2020 - 0x4002 2023
4
4
4
4
4
4
4
4
4
Block
Main memory
Bank 1
Bank 2
Information block
Table 8. XL-density Flash module organization
Name Base addresses
Page 0
Page 1
...
Page 255
Page 256
Page 257
.
.
.
Page 511
System memory
Option bytes
0x0800 0000 - 0x0800 07FF
0x0800 0800 - 0x0800 0FFF
...
0x0807 F800 - 0x0807 FFFF
0x0808 0000 - 0x0808 07FF
0x0808 0800 - 0x0808 0FFF
.
.
.
0x080F F800 - 0x080F FFFF
0x1FFF E000 - 0x1FFF F7FF
0x1FFF F800 - 0x1FFF F80F
Size (bytes)
2 K
2 K
...
2 K
2 K
2 K
2 K
6 K
.
.
.
16
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Block
Table 8. XL-density Flash module organization (continued)
Name Base addresses Size (bytes)
Flash memory interface registers
FLASH_ACR
FLASH_KEYR
FLASH_OPTKEYR
FLASH_SR
FLASH_CR
FLASH_AR
Reserved
FLASH_OBR
FLASH_WRPR
Reserved
FLASH_KEYR2
Reserved
FLASH_SR2
FLASH_CR2
FLASH_AR2
0x4002 2000 - 0x4002 2003
0x4002 2004 - 0x4002 2007
0x4002 2008 - 0x4002 200B
0x4002 200C - 0x4002 200F
0x4002 2010 - 0x4002 2013
0x4002 2014 - 0x4002 2017
0x4002 2018 - 0x4002 201B
0x4002 201C - 0x4002 201F
0x4002 2020 - 0x4002 2023
0x4002 2024 - 0x4002 2043
0x4002 2044 - 0x4002 2047
0x4002 2048 - 0x4002 204B
0x4002 204C - 0x4002 204F
0x4002 2050 - 0x4002 2053
0x4002 2054 - 0x4002 2057
4
4
4
4
4
4
32
4
4
4
4
4
4
4
4
Note:
Note:
For further information on the Flash memory interface registers, refer to the:“STM32F10xxx
XL-density Flash programming manual” (PM0068) for XL-density devices, “STM32F10xxx
Flash programming manual” (PM0075) for other devices.
Reading the Flash memory
Flash memory instructions and data access are performed through the AHB bus. The prefetch block is used for instruction fetches through the ICode bus. Arbitration is performed in the Flash memory interface, and priority is given to data access on the DCode bus.
Read accesses can be performed with the following configuration options:
Latency: number of wait states for a read operation programmed on-the-fly
Prefetch buffer (2 x 64-bit blocks): it is enabled after reset; a whole block can be replaced with a single read from the Flash memory as the size of the block matches the bandwidth of the Flash memory. Thanks to the prefetch buffer, faster CPU execution is possible as the CPU fetches one word at a time with the next word readily available in the prefetch buffer
Half cycle: for power optimization
These options have to be used in accordance with the Flash memory access time. The wait states represent the ratio of the SYSCLK (system clock) period to the Flash memory access time:
- 0 wait states, if 0 < SYSCLK 24 MHz
- 1 wait state, if 24 MHz < SYSCLK 48 MHz
- 2 wait states, if 48 MHz < SYSCLK 72 MHz
Half cycle configuration is not available in combination with a prescaler on the AHB. The system clock (SYSCLK) should be equal to the HCLK clock. This feature can therefore be
58/1136 RM0008 Rev 21
RM0008 Memory and bus architecture used only with a low-frequency clock of 8 MHz or less. It can be generated from the HSI or the HSE but not from the PLL.
The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock.
The prefetch buffer must be switched on/off only when SYSCLK is lower than 24 MHz and no prescaler is applied on the AHB clock (SYSCLK must be equal to HCLK). The prefetch buffer is usually switched on/off during the initialization routine, while the microcontroller is running on the internal 8 MHz RC (HSI) oscillator.
Using DMA: DMA accesses Flash memory on the DCode bus and has priority over ICode instructions. The DMA provides one free cycle after each transfer. Some instructions can be performed together with DMA transfer.
Programming and erasing the Flash memory
The Flash memory can be programmed 16 bits (half words) at a time.
For write and erase operations on the Flash memory (write/erase), the internal RC oscillator
(HSI) must be ON.
The Flash memory erase operation can be performed at page level or on the whole Flash area (mass-erase). The mass-erase does not affect the information blocks.
To ensure that there is no over-programming, the Flash Programming and Erase Controller blocks are clocked by a fixed clock.
The End of write operation (programming or erasing) can trigger an interrupt. This interrupt can be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the interrupt is served only after an exit from WFI.
The FLASH_ACR register is used to enable/disable prefetch and half cycle access, and to control the Flash memory access time according to the CPU frequency. The tables below provide the bit map and bit descriptions for this register.
For complete information on Flash memory operations and register configurations, refer to the STM32F10xxx Flash programming manual (PM0075) or to the XL STM32F10xxx Flash programming manual (PM0068).
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Memory and bus architecture
31
15
RM0008
Flash access control register (FLASH_ACR)
Address offset: 0x00
Reset value: 0x0000 0030
30 29
14 13
28
12
27
11
26
10
Reserved
25
9
24 23
8
Reserved
7
22
6
21 20 19
5 4 3
PRFTBS PRFTBE HLFCYA r rw rw
18 17 16
2 rw
1
LATENCY rw
0 rw
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 PRFTBS : Prefetch buffer status
This bit provides the status of the prefetch buffer.
0: Prefetch buffer is disabled
1: Prefetch buffer is enabled
Bit 4 PRFTBE : Prefetch buffer enable
0: Prefetch is disabled
1: Prefetch is enabled
Bit 3 HLFCYA : Flash half cycle access enable
0: Half cycle is disabled
1: Half cycle is enabled
Bits 2:0 LATENCY : Latency
These bits represent the ratio of the SYSCLK (system clock) period to the Flash access time.
000 Zero wait state, if 0 < SYSCLK 24 MHz
001 One wait state, if 24 MHz < SYSCLK 48 MHz
010 Two wait states, if 48 MHz < SYSCLK 72 MHz
In the STM32F10xxx, 3 different boot modes can be selected through BOOT[1:0] pins as
Table 9. Boot modes
Boot mode selection pins
BOOT1 x
0
1
BOOT0
0
1
1
Boot mode
Main Flash memory
System memory
Embedded SRAM
Aliasing
Main Flash memory is selected as boot space
System memory is selected as boot space
Embedded SRAM is selected as boot space
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RM0008
Note:
Note:
Memory and bus architecture
The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after Reset to select the required boot mode.
The BOOT pins are also re-sampled when exiting from Standby mode. Consequently they must be kept in the required Boot mode configuration in Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004.
Due to its fixed memory map, the code area starts from address 0x0000 0000 (accessed through the ICode/DCode buses) while the data area (SRAM) starts from address
0x2000 0000 (accessed through the system bus). The Cortex ® -M3 CPU always fetches the reset vector on the ICode bus, which implies to have the boot space available only in the code area (typically, Flash memory). STM32F10xxx microcontrollers implement a special mechanism to be able to boot also from SRAM and not only from main Flash memory and
System memory.
Depending on the selected boot mode, main Flash memory, system memory or SRAM is accessible as follows:
Boot from main Flash memory: the main Flash memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x800 0000).
In other words, the Flash memory contents can be accessed starting from address
0x0000 0000 or 0x800 0000.
Boot from system memory: the system memory is aliased in the boot memory space
(0x0000 0000), but still accessible from its original memory space (0x1FFF B000 in connectivity line devices, 0x1FFF F000 in other devices).
Boot from the embedded SRAM: SRAM is accessible only at address 0x2000 0000.
When booting from SRAM, in the application initialization code, you have to relocate the vector table in SRAM using the NVIC exception table and offset register.
For XL-density devices, when booting from the main Flash memory, you have an option to boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected.
You can choose to boot from Flash memory bank 2 by clearing the BFB2 bit in the user option bytes. When this bit is cleared and the boot pins are in the boot from main Flash memory configuration, the device boots from system memory, and the boot loader jumps to execute the user application programmed in Flash memory bank 2. For further details refer to AN2606.
When booting from Bank2 in the applications initialization code, relocate the vector table to the Bank2 base address. (0x0808 0000) using the NVIC exception table and offset register.
Embedded boot loader
The embedded boot loader is located in the System memory, programmed by ST during production. It is used to reprogram the Flash memory with one of the available serial interfaces:
In low-, medium- and high-density devices the bootoader is activated through the
USART1 interface.
In XL-density devices the boot loader is activated through the following interfaces:
USART1 or USART2 (remapped).
In connectivity line devices the boot loader can be activated through one of the following interfaces: USART1, USART2 (remapped), CAN2 (remapped) or USB OTG
FS in Device mode (DFU: device firmware upgrade).
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Memory and bus architecture
Note:
RM0008
The USART peripheral operates with the internal 8 MHz oscillator (HSI). The CAN and
USB OTG FS, however, can only function if an external 8 MHz, 14.7456 MHz or
25 MHz clock (HSE) is present.
For further details refer to AN2606.
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4 CRC calculation unit
CRC calculation unit
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
4.2
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
CRC main features
Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
– X
32
+ X
26
+ X
23
+ X
22
+ X
16
+ X
12
+ X
11
+ X
10
+X
8
+ X
7
+ X
5
+ X
4
+ X
2
+ X + 1
Single input/output 32-bit data register
CRC computation done in 4 AHB clock cycles (HCLK)
General-purpose 8-bit register (can be used for temporary storage)
The block diagram is shown in
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CRC calculation unit RM0008
Figure 3. CRC calculation unit block diagram
AHB bus
32-bit (read access)
Data register (output)
4.3
CRC computation (polynomial: 0x4C11DB7)
32-bit (write access)
Data register (input) ai14968
CRC functional description
The CRC calculation unit mainly consists of a single 32-bit data register, which:
is used as an input register to enter new data in the CRC calculator (when writing into the register)
holds the result of the previous CRC calculation (when reading the register)
Each write operation into the data register creates a combination of the previous CRC value and the new one (CRC computation is done on the whole 32-bit data word, and not byte per byte).
The write operation is stalled until the end of the CRC computation, thus allowing back-toback write accesses or consecutive write and read accesses.
The CRC calculator can be reset to 0xFFFF FFFF with the RESET control bit in the
CRC_CR register. This operation does not affect the contents of the CRC_IDR register.
The CRC calculation unit contains two data registers and a control register.
The peripheral
The CRC registers have to be accessed by words (32 bits).
31 rw
30
Address offset: 0x00
Reset value: 0xFFFF FFFF
29 28 27 26 25 rw
15 rw
14 rw rw
13 rw
12 rw
11 rw rw rw rw
10 rw
9 rw rw
24 23
DR [31:16] rw rw
8
DR [15:0]
7 rw rw
22 21 20 19 18 17 16 rw
6 rw
5 rw
4 rw
3 rw
2 rw
1 rw rw rw rw rw rw rw
0 rw
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RM0008 CRC calculation unit
Bits 31:0 Data register bits
Used as an input register when writing new data into the CRC calculator.
Holds the previous CRC calculation result when it is read.
4.4.2
31
15
30
14
Independent data register (CRC_IDR)
Address offset: 0x04
Reset value: 0x0000 0000
29 28 27 26 25
13 12 11 10 9
24 23
Reserved
8 7
22
6
Reserved rw rw
21 20 19 18 17 16
5 rw
4
IDR[7:0]
3 rw rw
2 rw
1 rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 General-purpose 8-bit data register bits
Can be used as a temporary storage location for one byte.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register.
0 rw
4.4.3
31
15
30
14
Control register (CRC_CR)
Address offset: 0x08
Reset value: 0x0000 0000
29 28 27 26 25
13 12 11 10 9
24 23
Reserved
8 7
Reserved
22
6
21
5
20
4
19
3
18
2
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 RESET bit
Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF.
This bit can only be set, it is automatically cleared by hardware.
17 16
1 0
RESET w
4.4.4 CRC register map
The following table provides the CRC register map and reset values.
Table 10. CRC calculation unit register map and reset values
Offset Register 31-24 23-16 15-8 7 6 5 4 3 2 1
0x00
CRC_DR
Reset value
Data register
0xFFFF FFFF
0
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CRC calculation unit RM0008
Table 10. CRC calculation unit register map and reset values (continued)
Offset Register 31-24 23-16 15-8 7 6 5 4 3 2 1 0
0x04
0x08
CRC_IDR
Reset value
CRC_CR
Reset value
Reserved
Reserved
Independent data register
0x00
RESET
0
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5 Power control (PWR)
Power control (PWR)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to the whole STM32F101xx family, unless otherwise specified.
The device requires a 2.0-to-3.6 V operating voltage supply (V
DD is used to supply the internal 1.8 V digital power.
). An embedded regulator
The real-time clock (RTC) and backup registers can be powered from the V
BAT when the main V
DD
supply is powered off.
voltage
RM0008 Rev 21 67/80
80
Power control (PWR)
Figure 4. Power supply overview
(V
SSA
) V
REF-
(from 2.4 V up to V
DDA
) V
REF+
(V
DD
(V
SS
)
)
V
DDA
V
SSA
V
DDA
domain
A/D converter
D/A converter
Temp. sensor
Reset block
PLL
V
V
SS
DD
V
BAT
V
DD
domain
I/O Ring
Standby circuitry
(Wakeup logic,
IWDG)
Voltage Regulator
1.8 V domain
Core
Memories digital
peripherals
Low voltage detector
Backup domain
LSE crystal 32K osc
BKP registers
RCC BDCR register
RTC
RM0008
5.1.1
1. V
DDA
and V
SSA
must be connected to V
DD
and V
SS
, respectively.
Independent A/D and D/A converter supply and reference voltage
To improve conversion accuracy, the ADC and the DAC have an independent power supply which can be separately filtered and shielded from noise on the PCB.
The ADC and DAC voltage supply input is available on a separate V
DDA
pin.
An isolated supply ground connection is provided on pin V
SSA
.
When available (according to package), V
REF-
must be tied to V
SSA
.
On 100-pin and 144-pin packages
To ensure a better accuracy on low-voltage inputs and outputs, the user can connect a separate external reference voltage on V
REF+
. V
REF+
is the highest voltage, represented by the full scale value, for an analog input (ADC) or output (DAC) signal. The voltage on V
REF+ can range from 2.4 V to V
DDA
.
On 64-pin packages and packages with less pins
The V
REF+
and V
REF-
pins are not available, they are internally connected to the ADC voltage supply (V
DDA
) and ground (V
SSA
).
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RM0008 Power control (PWR)
Note:
To retain the content of the Backup registers and supply the RTC function when V
DD turned off, V
BAT or by another source.
is pin can be connected to an optional standby voltage supplied by a battery
The V
BAT
pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 IOs, allowing the RTC to operate even when the main digital supply (V
V
BAT
DD
) is turned off. The switch to the
supply is controlled by the Power Down Reset embedded in the Reset block.
Warning: During t
RSTTEMPO
(temporization at V connected to V
BAT
.
During the startup phase, if V
DD
DD
startup) or after a PDR is detected, the power switch between V
BAT and V
DD
remains
is established in less than
(Refer to the datasheet for the value of t t
RSTTEMPO and V
DD
> V
BAT through an internal diode connected between V
DD power switch (V
BAT
).
If the power supply/battery connected to the V
BAT
RSTTEMPO
+ 0.6 V, a current may be injected into V
BAT
and the
)
pin cannot support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the V
BAT
pin.
If no external battery is used in the application, it is recommended to connect V
BAT externally to V
DD to AN2586).
with a 100 nF external ceramic decoupling capacitor (for more details refer
When the backup domain is supplied by V
DD following functions are available:
(analog switch connected to V
DD
), the
PC14 and PC15 can be used as either GPIO or LSE pins
PC13 can be used as GPIO, TAMPER pin, RTC Calibration Clock, RTC Alarm or second output (refer to
Section 6: Backup registers (BKP)
)
Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of
GPIOs PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive a LED).
When the backup domain is supplied by V
BAT
V
DD
(analog switch connected to V
is not present), the following functions are available:
BAT
because
PC14 and PC15 can be used as LSE pins only
PC13 can be used as TAMPER pin, RTC Alarm or Second output (refer to
Section 6.4.2: RTC clock calibration register (BKP_RTCCR) ).
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Power control (PWR) RM0008
The voltage regulator is always enabled after Reset. It works in three different modes depending on the application modes.
In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories and digital peripherals).
In Stop mode the regulator supplies low-power to the 1.8 V domain, preserving contents of registers and SRAM
In Standby Mode, the regulator is powered off. The contents of the registers and SRAM are lost except for the Standby circuitry and the Backup Domain.
5.2.1 Power on reset (POR)/power down reset (PDR)
The device has an integrated POR/PDR circuitry that allows proper operation starting from/down to 2 V.
The device remains in Reset mode when V
DD
V
POR/PDR
/V
DDA is below a specified threshold,
, without the need for an external reset circuit. For more details concerning the power on/power down reset threshold, refer to the electrical characteristics of the datasheet.
VDD/VDDA
Figure 5. Power on reset/power down reset waveform
PDR
VPOR/PDR rising edge
VPOR/PDR falling edge
40 mV hysteresis
PDR
Temporization tRSTTEMPO
5.2.2
Reset
MS30431V2
Programmable voltage detector (PVD)
The PVD can be used to monitor the V
DD
/V
DDA
power supply by comparing it to a threshold selected by the PLS[2:0] bits in the
Power control register (PWR_CR) .
The PVD is enabled by setting the PVDE bit.
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RM0008 Power control (PWR)
A PVDO flag is available, in the
Power control/status register (PWR_CSR) , to indicate if
V
DD
/V
DDA
is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The
PVD output interrupt can be generated when V and/or when V
DD
/V
DDA
DD
/V
DDA
drops below the PVD threshold
rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks.
Figure 6. PVD thresholds
VDD
PVD threshold 100 mV hysteresis
PVD output
MS30432V2
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Power control (PWR) RM0008
By default, the microcontroller is in Run mode after a system or a power Reset. Several lowpower modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources.
The STM32F10xxx devices feature three low-power modes:
Sleep mode (CPU clock off, all peripherals including Cortex ® -M3 core peripherals like
NVIC, SysTick, etc. are kept running)
Stop mode (all clocks are stopped)
Standby mode (1.8V domain powered-off)
In addition, the power consumption in Run mode can be reduce by one of the following means:
Slowing down the system clocks
Gating the clocks to the APB and AHB peripherals when they are unused.
Mode name Entry
Table 11. Low-power mode summary
Wakeup
Effect on 1.8V domain clocks
Effect on V
DD domain clocks
Voltage regulator
Sleep
(Sleep now or
Sleep-on -exit)
Stop
Standby
WFI
WFE
PDDS bit +
SLEEPDEEP bit +
WFI or WFE
Any interrupt
Wakeup event
PDDS and LPDS bits + SLEEPDEEP bit + WFI or WFE
Any EXTI line
(configured in the
EXTI registers)
WKUP pin rising edge, RTC alarm, external reset in
NRST pin,
IWDG reset
CPU clock OFF no effect on other clocks or analog clock sources
None
All 1.8V domain clocks OFF
ON
HSI and HSE oscillators OFF
ON or in low-power mode
(depends on Power control register
)
OFF
In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode.
For more details refer to Section 7.3.2: Clock configuration register (RCC_CFGR)
.
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5.3.2
Power control (PWR)
Peripheral clock gating
In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption.
To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.
Peripheral clock gating is controlled by the
AHB peripheral clock enable register
,
APB1 peripheral clock enable register (RCC_APB1ENR)
and
APB2 peripheral clock enable register (RCC_APB2ENR)
.
Entering Sleep mode
The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for
Event) instructions. Two options are available to select the Sleep mode entry mechanism, depending on the SLEEPONEXIT bit in the Cortex
®
-M3 System Control register:
Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon as WFI or WFE instruction is executed.
Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as it exits the lowest priority ISR.
In the Sleep mode, all I/O pins keep the same state as in the Run mode.
and
Table 13 for details on how to enter Sleep mode.
Exiting Sleep mode
If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode.
If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as an event occurs. The wakeup event can be generated either by:
enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex ® -M3 System Control register. When the MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit.
and
Table 13 for more details on how to exit Sleep mode.
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Power control (PWR)
Sleep-on-exit
Mode entry
Mode exit
Wakeup latency
RM0008
Sleep-now mode
Mode entry
Mode exit
Wakeup latency
Table 12. Sleep-now
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 0
Refer to the Cortex ® -M3 System Control register.
If WFI was used for entry:
Interrupt: Refer to Section 10.1.2: Interrupt and exception vectors
If WFE was used for entry
Wakeup event: Refer to
Section 10.2.3: Wakeup event management
None
Table 13. Sleep-on-exit
Description
WFI (wait for interrupt) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex
®
-M3 System Control register.
Interrupt: refer to Section 10.1.2: Interrupt and exception vectors .
None
The Stop mode is based on the Cortex ® -M3 deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode.
In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC oscillators are disabled. SRAM and register contents are preserved.
In the Stop mode, all I/O pins keep the same state as in the Run mode.
Entering Stop mode
for details on how to enter the Stop mode.
To further reduce power consumption in Stop mode, the internal voltage regulator can be put
in low-power mode. This is configured by the LPDS bit of the Power control register
If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory access is finished.
If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB access is finished.
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Note:
Power control (PWR)
In Stop mode, the following features can be selected by programming individual control bits:
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See
Section 19.3: IWDG functional description
.
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the
Control/status register (RCC_CSR)
.
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
Backup domain control register (RCC_BDCR) .
The ADC or DAC can also consume power during the Stop mode, unless they are disabled before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit in the DAC_CR register must both be written to 0.
If the application needs to disable the external clock before entering Stop mode, the HSEON bit must first be disabled and the system clock switched to HSI. Otherwise, if the HSEON bit remains enabled and the external clock (external oscillator) is removed when entering Stop mode, the clock security system (CSS) feature must be enabled to detect any external oscillator failure and avoid a malfunction behavior when entering stop mode.
Exiting Stop mode
for more details on how to exit Stop mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.
When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.
Stop mode
Table 14. Stop mode
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– Set SLEEPDEEP bit in Cortex
®
-M3 System Control register
– Clear PDDS bit in Power Control register (PWR_CR)
– Select the voltage regulator mode by configuring LPDS bit in PWR_CR
Mode entry
Mode exit
Wakeup latency
Note:
To enter Stop mode, all EXTI Line pending bits (in Pending register
), all peripheral interrupt pending bits, and RTC Alarm flag must be reset. Otherwise, the Stop mode entry procedure is ignored and program execution continues.
If WFI was used for entry:
Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). Refer to Section 10.1.2:
Interrupt and exception vectors .
If WFE was used for entry:
Any EXTI Line configured in event mode. Refer to Section 10.2.3:
HSI RC wakeup time + regulator wakeup time from Low-power mode
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Power control (PWR) RM0008
The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex
®
-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for registers in the Backup domain
and Standby circuitry (see Figure 4
).
Entering Standby mode
for more details on how to enter Standby mode.
In Standby mode, the following features can be selected by programming individual control bits:
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See
Section 19.3: IWDG functional description
.
Real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR)
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR).
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
Backup domain control register (RCC_BDCR)
Exiting Standby mode
The microcontroller exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin or the rising edge of an RTC alarm occurs (see
Figure 179: RTC simplified block diagram ). All registers are reset after wakeup from
Standby except for Power control/status register (PWR_CSR)
.
After waking up from Standby mode, program execution restarts in the same way as after a
indicates that the MCU was in Standby mode.
for more details on how to exit Standby mode.
Standby mode
Mode entry
Mode exit
Wakeup latency
Table 15. Standby mode
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– Set SLEEPDEEP in Cortex
®
-M3 System Control register
– Set PDDS bit in Power Control register (PWR_CR)
– Clear WUF bit in Power Control/Status register (PWR_CSR)
– No interrupt (for WFI) or event (for WFI) is pending
WKUP pin rising edge, RTC alarm event’s rising edge, external Reset in
NRST pin, IWDG Reset.
Reset phase
76/80 RM0008 Rev 21
RM0008
5.3.6
Power control (PWR)
I/O states in Standby mode
In Standby mode, all I/O pins are high impedance except:
Reset pad (still available)
TAMPER pin if configured for tamper or calibration out
WKUP pin, if enabled
Debug mode
By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex
®
-M3 core is no longer clocked.
However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to
Section 31.16.1: Debug support for low-power modes
.
Auto-wakeup (AWU) from low-power mode
The RTC can be used to wakeup the MCU from low-power mode without depending on an external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the
Backup domain control register (RCC_BDCR)
:
Low-power 32.768 kHz external crystal oscillator (LSE OSC).
This clock source provides a precise time base with very low-power consumption (less than 1µA added consumption in typical conditions)
Low-power internal RC Oscillator (LSI RC)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC Oscillator is designed to add minimum power consumption.
To wakeup from Stop mode with an RTC alarm event, it is necessary to:
Configure the EXTI Line 17 to be sensitive to rising edge
Configure the RTC to generate the RTC alarm
To wakeup from Standby mode, there is no need to configure the EXTI Line 17.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
31
15
Address offset: 0x00
Reset value: 0x0000 0000 (reset by wakeup from Standby mode)
30 29 28 27 26 25 20
14 13 12
Reserved
11 10 9
24 23
Reserved
8 7
DBP rw rw
22
6
PLS[2:0] rw
21
5 rw
19 18 17 16
4 3 2 1 0
PVDE CSBF CWUF PDDS LPDS rw rc_w1 rc_w1 rw rw
RM0008 Rev 21 77/80
80
Power control (PWR) RM0008
Bits 31:9 Reserved, must be kept at reset value..
Bit 8 DBP : Disable backup domain write protection.
In reset state, the RTC and backup registers are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC and Backup registers disabled
1: Access to RTC and Backup registers enabled
Note: If the HSE divided by 128 is used as the RTC clock, this bit must remain set to 1.
Bits 7:5 PLS[2:0]: PVD level selection.
These bits are written by software to select the voltage threshold detected by the programmable voltage detector
000: 2.2V
001: 2.3V
010: 2.4V
011: 2.5V
100: 2.6V
101: 2.7V
110: 2.8V
111: 2.9V
Note: Refer to the electrical characteristics of the datasheet for more details.
Bit 4 PVDE: programmable voltage detector enable.
This bit is set and cleared by software.
0: PVD disabled
1: PVD enabled
Bit 3 CSBF : Clear standby flag.
This bit is always read as 0.
0: No effect
1: Clear the SBF Standby Flag (write).
Bit 2 CWUF: Clear wakeup flag.
This bit is always read as 0.
0: No effect
1: Clear the WUF Wakeup Flag after 2 System clock cycles . (write)
Bit 1 PDDS : Power down deepsleep.
This bit is set and cleared by software. It works together with the LPDS bit.
0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the
LPDS bit.
1: Enter Standby mode when the CPU enters Deepsleep.
Bit 0 LPDS: Low-power deepsleep.
This bit is set and cleared by software. It works together with the PDDS bit.
0: Voltage regulator on during Stop mode
1: Voltage regulator in low-power mode during Stop mode
78/80 RM0008 Rev 21
RM0008 Power control (PWR)
5.4.2
31
15
Power control/status register (PWR_CSR)
Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
30 29
14
28 27
13 12
Reserved
11
26
10
25
9
24 23
Reserved
8
EWUP
7 rw
22 21 20
6 5
Reserved
4
19
3
18 17
2
PVDO r
1
SBF r
16
0
WUF r
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 EWUP: Enable WKUP pin
This bit is set and cleared by software.
0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup the device from Standby mode.
1: WKUP pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin wakes-up the system from Standby mode).
Note: This bit is reset by a system Reset.
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 PVDO: PVD output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
0: V
DD
/V
DDA
1: V
DD
/V
DDA
is higher than the PVD threshold selected with the PLS[2:0] bits.
is lower than the PVD threshold selected with the PLS[2:0] bits.
Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after
Standby or reset until the PVDE bit is set.
Bit 1 SBF: Standby flag
This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down reset)
or by setting the CSBF bit in the Power control register (PWR_CR)
0: Device has not been in Standby mode
1: Device has been in Standby mode
Bit 0 WUF: Wakeup flag
This bit is set by hardware and cleared by hardware, by a system reset or by setting the
CWUF bit in the
Power control register (PWR_CR)
0: No wakeup event occurred
1: A wakeup event was received from the WKUP pin or from the RTC alarm
Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the
EWUP bit) when the WKUP pin level is already high.
RM0008 Rev 21 79/80
80
Power control (PWR) RM0008
The following table summarizes the PWR registers.
Table 16. PWR register map and reset values
Offset Register
0x000
PWR_CR
Reset value
0x004
PWR_CSR
Reset value
Reserved
Reserved
for the register boundary addresses.
PLS
[2:0]
0 0 0 0 0 0 0 0 0
Reserved
0 0 0 0
80/80 RM0008 Rev 21
RM0008 Backup registers (BKP)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to the whole STM32F101xx family, unless otherwise specified.
6.2
The backup registers are forty two 16-bit registers for storing 84 bytes of user application data.
They are implemented in the backup domain that remains powered on by V
BAT
V
DD mode or by a system reset or power reset.
when the
power is switched off. They are not reset when the device wakes up from Standby
In addition, the BKP control registers are used to manage the Tamper detection feature and
RTC calibration.
After reset, access to the Backup registers and RTC is disabled and the Backup domain
(BKP) is protected against possible parasitic write access. To enable access to the Backup registers and the RTC, proceed as follows:
enable the power and backup interface clocks by setting the PWREN and BKPEN bits in the RCC_APB1ENR register
set the DBP bit in the Power control register (PWR_CR) to enable access to the
Backup registers and RTC.
BKP main features
20-byte data registers (in medium-density and low-density devices) or 84-byte data registers (in high-density, XL-density and connectivity line devices)
Status/control register for managing tamper detection with interrupt capability
Calibration register for storing the RTC calibration value
Possibility to output the RTC Calibration Clock, RTC Alarm pulse or Second pulse on
TAMPER pin PC13 (when this pin is not used for tamper detection)
RM0008 Rev 21 81/1136
89
Backup registers (BKP)
6.3 BKP functional description
RM0008
Note:
The TAMPER pin generates a Tamper detection event when the pin changes from 0 to 1 or
from 1 to 0 depending on the TPAL bit in the Backup control register (BKP_CR) . A tamper
detection event resets all data backup registers.
However to avoid losing Tamper events, the signal used for edge detection is logically
ANDed with the Tamper enable in order to detect a Tamper event in case it occurs before the TAMPER pin is enabled.
When TPAL=0: If the TAMPER pin is already high before it is enabled (by setting TPE bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled (while there was no rising edge on the TAMPER pin after TPE was set)
When TPAL=1: If the TAMPER pin is already low before it is enabled (by setting the
TPE bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled
(while there was no falling edge on the TAMPER pin after TPE was set)
By setting the TPIE bit in the BKP_CSR register, an interrupt is generated when a Tamper detection event occurs.
After a Tamper event has been detected and cleared, the TAMPER pin should be disabled and then re-enabled with TPE before writing to the backup data registers (BKP_DRx) again.
This prevents software from writing to the backup data registers (BKP_DRx), while the
TAMPER pin value still indicates a Tamper detection. This is equivalent to a level detection on the TAMPER pin.
Tamper detection is still active when V
DD
power is switched off. To avoid unwanted resetting of the data backup registers, the TAMPER pin should be externally tied to the correct level.
For measurement purposes, the RTC clock with a frequency divided by 64 can be output on
the TAMPER pin. This is enabled by setting the CCO bit in the RTC clock calibration register
.
The clock can be slowed down by up to 121 ppm by configuring CAL[6:0] bits.
For more details about RTC calibration and how to use it to improve timekeeping accuracy, refer to AN2604 " STM32F101xx and STM32F103xx RTC calibration ”.
82/1136 RM0008 Rev 21
RM0008 Backup registers (BKP)
Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
15 rw
14 rw
Address offset: 0x04 to 0x28, 0x40 to 0xBC
Reset value: 0x0000 0000
13 12 11 10 9 rw rw rw rw rw
8 7 rw
D[15:0] rw
6 5 4 3 2 1 0 rw rw rw rw rw rw rw
Bits 15:0 D[15:0] Backup data
These bits can be written with user data.
Note: The BKP_DRx registers are not reset by a System reset or Power reset or when the device wakes up from Standby mode.
They are reset by a Backup Domain reset or by a TAMPER pin event (if the TAMPER pin function is activated).
15 14
Address offset: 0x2C
Reset value: 0x0000 0000
13 12 11 10
Reserved
9 8 7
ASOS ASOE CCO rw rw rw
6 5 4 rw
3
CAL[6:0] rw
2 rw
1 0 rw rw rw rw
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 ASOS: Alarm or second output selection
When the ASOE bit is set, the ASOS bit can be used to select whether the signal output on the TAMPER pin is the RTC Second pulse signal or the Alarm pulse signal:
0: RTC Alarm pulse output selected
1: RTC Second pulse output selected
Note: This bit is reset only by a Backup domain reset.
RM0008 Rev 21 83/1136
89
Backup registers (BKP) RM0008
Bit 8 ASOE: Alarm or second output enable
Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the
TAMPER pin depending on the ASOS bit.
The output pulse duration is one RTC clock period. The TAMPER pin must not be enabled while the ASOE bit is set.
Note: This bit is reset only by a Backup domain reset.
Bit 7 CCO: Calibration clock output
0: No effect
1: Setting this bit outputs the RTC clock with a frequency divided by 64 on the TAMPER pin.
The TAMPER pin must not be enabled while the CCO bit is set in order to avoid unwanted
Tamper detection.
Note: This bit is reset when the V
DD
supply is powered off.
Bit 6:0 CAL[6:0]: Calibration value
This value indicates the number of clock pulses that will be ignored every 2^20 clock pulses.
This allows the calibration of the RTC, slowing down the clock by steps of 1000000/2^20
PPM.
The clock of the RTC can be slowed down from 0 to 121PPM.
15
Note:
14
Address offset: 0x30
Reset value: 0x0000 0000
13 12 11 10 9 8
Reserved
7 6 5 4 3 2
Bits 15:2 Reserved, must be kept at reset value.
Bit 1 TPAL: TAMPER pin active level
0: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set).
1: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set).
Bit 0 TPE: TAMPER pin enable
0: The TAMPER pin is free for general purpose I/O
1: Tamper alternate I/O function is activated.
1
TPAL rw
0
TPE rw
Setting the TPAL and TPE bits at the same time is always safe, however resetting both at the same time can generate a spurious Tamper event. For this reason it is recommended to change the TPAL bit only when the TPE bit is reset.
15
Address offset: 0x34
Reset value: 0x0000 0000
14 13 12
Reserved
11 10 9
TIF r
8
TEF r
7 6 5
Reserved
4 3 2
TPIE rw
1
CTI w
0
CTE w
84/1136 RM0008 Rev 21
RM0008 Backup registers (BKP)
6.4.5
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 TIF: Tamper interrupt flag
This bit is set by hardware when a Tamper event is detected and the TPIE bit is set. It is cleared by writing 1 to the CTI bit (also clears the interrupt). It is also cleared if the TPIE bit is reset.
0: No Tamper interrupt
1: A Tamper interrupt occurred
Note: This bit is reset only by a system reset and wakeup from Standby mode.
Bit 8 TEF: Tamper event flag
This bit is set by hardware when a Tamper event is detected. It is cleared by writing 1 to the
CTE bit.
0: No Tamper event
1: A Tamper event occurred
Note: A Tamper event resets all the BKP_DRx registers. They are held in reset as long as the
TEF bit is set. If a write to the BKP_DRx registers is performed while this bit is set, the value will not be stored.
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 TPIE: TAMPER pin interrupt enable
0: Tamper interrupt disabled
1: Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register
Note: A Tamper interrupt does not wake up the core from low-power modes.
This bit is reset only by a system reset and wakeup from Standby mode.
Bit 1 CTI: Clear tamper interrupt
This bit is write only, and is always read as 0.
0: No effect
1: Clear the Tamper interrupt and the TIF Tamper interrupt flag.
Bit 0 CTE: Clear tamper event
This bit is write only, and is always read as 0.
0: No effect
1: Reset the TEF Tamper event flag (and the Tamper detector)
BKP register map
BKP registers are mapped as 16-bit addressable registers as described in the table below:
Table 17. BKP register map and reset values
Offset Register
0x00
0x04
BKP_DR1
Reset value
Reserved
Reserved
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RM0008 Rev 21 85/1136
89
Backup registers (BKP)
Table 17. BKP register map and reset values (continued)
Offset Register
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2
0x30
0x34
BKP_DR2
Reset value
BKP_DR3
Reset value
BKP_DR4
Reset value
BKP_DR5
Reset value
BKP_DR6
Reset value
BKP_DR7
Reset value
BKP_DR8
Reset value
BKP_DR9
Reset value
BKP_DR10
Reset value
BKP_RTCCR
Reset value
BKP_CR
Reset value
BKP_CSR
Reset value
0x38
0x3C
0x40
BKP_DR11
Reset value
86/1136
RM0008
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CAL[6:0]
0 0 0 0 0 0 0 0 0 0
0 0
Reserved
0 0 0 0 0
Reserved
Reserved
Reserved
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RM0008 Rev 21
RM0008
Offset Register
0x44
0x48
0x4C
0x50
0x54
0x58
0x5C
0x60
0x64
0x68
0x6C
0x70
0x74
0x78
Reset value
BKP_DR19
Reset value
BKP_DR20
Reset value
BKP_DR21
Reset value
BKP_DR22
Reset value
BKP_DR23
Reset value
BKP_DR24
Reset value
BKP_DR25
Reset value
BKP_DR12
Reset value
BKP_DR13
Reset value
BKP_DR14
Reset value
BKP_DR15
Reset value
BKP_DR16
Reset value
BKP_DR17
Reset value
BKP_DR18
Backup registers (BKP)
Table 17. BKP register map and reset values (continued)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RM0008 Rev 21
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
87/1136
89
Backup registers (BKP)
Table 17. BKP register map and reset values (continued)
Offset Register
0x7C
0x80
0x84
0x88
0x8C
0x90
0x94
0x98
0x9C
0xA0
0xA4
0xA8
0xAC
0xB0
Reset value
BKP_DR33
Reset value
BKP_DR34
Reset value
BKP_DR35
Reset value
BKP_DR36
Reset value
BKP_DR37
Reset value
BKP_DR38
Reset value
BKP_DR39
Reset value
BKP_DR26
Reset value
BKP_DR27
Reset value
BKP_DR28
Reset value
BKP_DR29
Reset value
BKP_DR30
Reset value
BKP_DR31
Reset value
BKP_DR32
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RM0008
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
88/1136 RM0008 Rev 21
RM0008 Backup registers (BKP)
Table 17. BKP register map and reset values (continued)
Offset Register
0xB4
0xB8
0xBC
BKP_DR40
Reset value
BKP_DR41
Reset value
BKP_DR42
Reset value
Reserved
Reserved
Reserved
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
for the register boundary addresses.
RM0008 Rev 21 89/1136
89
Low-, medium-, high- and XL-density reset and clock control (RCC)
7
RM0008
Low-, medium-, high- and XL-density reset and clock control (RCC)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to low-, medium-, high- and XL-density STM32F10xxx devices.
7.1 Reset
There are three types of reset, defined as system reset, power reset and backup domain reset.
A system reset sets all registers to their reset values (unless specified otherwise in the register description) except the reset flags in the clock controller CSR register and the
registers in the Backup domain (see Figure 4
).
A system reset is generated when one of the following events occurs:
1.
A low level on the NRST pin (external reset)
2. Window watchdog end of count condition (WWDG reset)
3. Independent watchdog end of count condition (IWDG reset)
4. A software reset (SW reset) (see
)
5. Low-power management reset (see
)
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see
Section 7.3.10: Control/status register (RCC_CSR)
).
Software reset
The SYSRESETREQ bit in Cortex
®
-M3 Application Interrupt and Reset Control register must be set to force a software reset on the device. Refer to the STM32F10xxx Cortex
®
-M3 programming manual
) for more details.
90/1136 RM0008 Rev 21
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Low-power management reset
There are two ways to generate a low-power management reset:
1.
Reset generated when entering Standby mode:
This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.
2. Reset when entering Stop mode:
This type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode.
For further information on the User Option Bytes, refer to the STM32F10xxx Flash programming manual.
A power reset is generated when one of the following events occurs:
1.
Power-on/power-down reset (POR/PDR reset)
2. When exiting Standby mode
A power reset sets all registers to their reset values except the Backup domain (see
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map.
The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each reset source
(external or internal reset). In case of an external reset, the reset pulse is generated while the NRST pin is asserted low.
Figure 7. Simplified diagram of the reset circuit
V
DD
/V
DDA
R
PU
External reset
NRST
Filter
System reset
Pulse generator
(min 20 μs)
WWDG reset
IWDG reset
Power reset
Software reset
Low-power management reset ai16095c
RM0008 Rev 21 91/1136
122
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
The backup domain has two specific resets that affect only the backup domain (see
A backup domain reset is generated when one of the following events occurs:
1.
Software reset, triggered by setting the BDRST bit in the Backup domain control register (RCC_BDCR)
.
2. V
DD
or V
BAT
power on, if both supplies have previously been powered off.
7.2 Clocks
Three different clock sources can be used to drive the system clock (SYSCLK):
HSI oscillator clock
HSE oscillator clock
PLL clock
The devices have the following two secondary clock sources:
40 kHz low speed internal RC (LSI RC), which drives the independent watchdog and optionally the RTC used for Auto-wakeup from Stop/Standby mode.
32.768 kHz low speed external crystal (LSE crystal), which optionally drives the real-time clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize power consumption.
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OSC_OUT
OSC_IN
OSC32_IN
OSC32_OUT
Figure 8. Clock tree
USB
Prescaler
/1, 1.5
48 MHz
FLITFCLK to Flash programming interface
USBCLK to USB interface
I2S3CLK to I2S3
Peripheral clock enable
I2S2CLK to I2S2
8 MHz
HSI RC
PLLSRC
4-16 MHz
HSE OSC
HSI
PLLMUL
..., x16 x2, x3, x4
PLL
/2
PLLXTPRE
HSI
PLLCLK
HSE
SW
SYSCLK
CSS
72 MHz
max
Peripheral clock enable
Peripheral clock enable
AHB
Prescaler
/1, 2..512
SDIOCLK to SDIO
FSMCCLK to FSMC
Peripheral clock enable
72 MHz max
HCLK to AHB bus, core, memory and DMA
/8
Clock
Enable
APB1
Prescaler
/1, 2, 4, 8, 16 to Cortex System timer
FCLK Cortex free running clock
36 MHz max
Peripheral Clock
Enable
PCLK1 to APB1 peripherals
TIM2,3,4,5,6,7,12,13,14
If (APB1 prescaler =1) x1 to TIM2,3,4,5,6,7,12,13,14 else x2
TIMXCLK
Peripheral Clock
Enable
APB2
Prescaler
/1, 2, 4, 8, 16
72 MHz max PCLK2
Peripheral Clock
Enable peripherals to APB2
/2
LSE OSC
32.768 kHz
/128
LSE
RTCCLK to RTC
TIM1,8,9,10,11 timers
If (APB2 prescaler =1) x1 else x2 to TIM1,8,9,10 and 11
TIMxCLK
Peripheral Clock
Enable
ADC
Prescaler
/2, 4, 6, 8 to ADC1, 2 or 3
ADCCLK 14 MHz max
LSI RC
40 kHz
RTCSEL[1:0]
LSI to Independent Watchdog (IWDG)
IWDGCLK
/2
HCLK/2
To SDIO AHB interface
Peripheral clock enable
MCO
Main
Clock Output
MCO
/2 PLLCLK
HSI
HSE
SYSCLK
Legend:
HSE = High-speed external clock signal
HSI = High-speed internal clock signal
LSI = Low-speed internal clock signal
LSE = Low -speed external clock signal ai14752e
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For full details about the internal and external clock source characteristics refer to the “Electrical characteristics” section in your device datasheet.
Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is
36 MHz. The SDIO AHB interface is clocked with a fixed frequency equal to HCLK/2
The RCC feeds the Cortex ® System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex ® clock
(HCLK), configurable in the SysTick Control and Status register. The ADCs are clocked by the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8.
The Flash memory programming interface clock (FLITFCLK) is always the HSI clock.
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The timer clock frequencies are automatically fixed by hardware. There are two cases:
1.
if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected.
2. otherwise, they are set to twice (×2) the frequency of the APB domain to which the timers are connected.
FCLK acts as Cortex ® -M3 free-running clock. For more details refer to Arm ®
Cortex-M3 r1p1 Technical Reference Manual (TRM) .
The high speed external clock signal (HSE) can be generated from two possible clock sources:
HSE external crystal/ceramic resonator
HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.
Clock source
Figure 9. HSE/ LSE clock sources
Hardware configuration
External clock
External source
OSC_OUT
(HiZ)
Crystal / ceramic resonators
OSC_IN OSC_OUT
C
L1
Load capacitors
C
L2
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External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
25 MHz. You select this mode by setting the HSEBYP and HSEON
cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See
External crystal/ceramic resonator (HSE crystal)
The 4 to 16 MHz external oscillator has the advantage of producing a very accurate rate on the main clock.
The associated hardware configuration is shown in
Figure 9 . Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag in the
Clock control register (RCC_CR) indicates if the high-speed
external oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the
The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used directly as a system clock or divided by 2 to be used as PLL input.
The HSI RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator.
Calibration
RC oscillator frequencies can vary because of manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T
A
=25°C.
If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. The HSI frequency in the application can be trimmed using the
HSITRIM[4:0] bits in the Clock control register (RCC_CR) .
The HSIRDY flag in the
Clock control register (RCC_CR) indicates if the HSI RC is stable or
not. At startup, the HSI RC output clock is not released until this bit is set by hardware.
The HSI RC can be switched on and off using the HSION bit in the
.
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to
Section 7.2.7: Clock security system (CSS) .
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7.2.3 PLL
The internal PLL can be used to multiply the HSI RC output or HSE crystal output clock frequency. Refer to
Clock control register (RCC_CR)
.
The PLL configuration (selection of HSI oscillator divided by 2 or HSE oscillator for PLL input clock, and multiplication factor) must be done before enabling the PLL. Once the PLL enabled, these parameters cannot be changed.
If the USB interface is used in the application, the PLL must be programmed to output 48 or
72 MHz. This is needed to provide a 48 MHz USBCLK.
The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the advantage providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in
Backup domain control register (RCC_BDCR)
.
The LSERDY flag in the
Backup domain control register (RCC_BDCR)
indicates if the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the
Clock interrupt register (RCC_CIR) .
External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the
~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left
.
Note:
The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the
.
The LSIRDY flag in the Control/status register (RCC_CSR)
indicates if the low-speed internal oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the
LSI calibration is only available on high-density, XL-density and connectivity line devices.
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7.2.6
7.2.7
Note:
Low-, medium-, high- and XL-density reset and clock control (RCC)
LSI calibration
The frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for these peripherals) with an acceptable accuracy.
This calibration is performed by measuring the LSI clock frequency with respect to TIM5 input clock (TIM5CLK). According to this measurement done at the precision of the HSE oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an accurate time base or can compute accurate IWDG timeout.
Use the following procedure to calibrate the LSI:
1.
Enable TIM5 timer and configure channel4 in input capture mode
2. Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock internally to TIM5 channel4 input capture for calibration purpose.
3. Measure the frequency of LSI clock using the TIM5 Capture/compare 4 event or interrupt.
4. Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending on the desired time base and/or to compute the IWDG timeout.
System clock (SYSCLK) selection
After a system reset, the HSI oscillator is selected as system clock. When a clock source is used directly or through the PLL as system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. Status bits in the
Clock control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently
used as system clock.
Clock security system (CSS)
Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock failure event is sent to the break input of the advanced-control timers (TIM1 and TIM8) and an interrupt is generated to inform the software about the failure (Clock Security System
Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the
Cortex ® -M3 NMI (Non-Maskable Interrupt) exception vector.
Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is automatically generated. The NMI will be executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by setting the CSSC bit in the
Clock interrupt register (RCC_CIR)
.
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock to the HSI oscillator and the disabling of the HSE oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too.
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The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected
by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR) .
This selection cannot be modified without resetting the Backup domain.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.
Consequently:
If LSE is selected as RTC clock:
– The RTC continues to work even if the V
DD
V
BAT
supply is maintained.
supply is switched off, provided the
If LSI is selected as Auto-Wakeup unit (AWU) clock:
– The AWU state is not guaranteed if the V
DD
supply is powered off. Refer to
for more details on LSI calibration.
If the HSE clock divided by 128 is used as the RTC clock:
– The RTC state is not guaranteed if the V
DD
supply is powered off or if the internal voltage regulator is powered off (removing power from the 1.8 V domain).
– The DPB bit (disable backup domain write protection) in the Power controller
register must be set to 1 (refer to Section 5.4.1: Power control register
If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG.
The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One of 4 clock signals can be selected as the MCO clock.
SYSCLK
HSI
HSE
PLL clock divided by 2
The selection is controlled by the MCO[2:0] bits of the
.
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Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.
31
15 r
Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-word and byte access
30 29
14 13
28
Reserved
27
12 11
HSICAL[7:0] r r
26
10
25
PLL
RDY r
9
24
PLLON rw
8
23
7
22 21
Reserved
20
6 5
HSITRIM[4:0]
4 rw rw rw
19
CSS
ON rw
3
18
HSE
BYP rw
2 rw
Res.
17
HSE
RDY r
1
HSI
RDY r
16
HSE
ON rw
0
HSION rw r r r r r rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 PLLRDY: PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: PLL enable
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the
PLL clock is used as system clock or is selected to become the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 CSSON: Clock security system enable
Set and cleared by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected.
0: Clock detector OFF
1: Clock detector ON (Clock detector ON if the HSE oscillator is ready , OFF if not).
Bit 18 HSEBYP: External high-speed clock bypass
Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.
0: external 4-16 MHz oscillator not bypassed
1: external 4-16 MHz oscillator bypassed with external clock
Bit 17 HSERDY: External high-speed clock ready flag
Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the
HSE oscillator clock to fall down after HSEON reset.
0: HSE oscillator not ready
1: HSE oscillator ready
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Bit 16 HSEON: HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration
These bits are initialized automatically at startup.
Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the internal HSI RC.
The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8
MHz ± 1%. The trimming step (F hsitrim steps.
) is around 40 kHz between two consecutive HSICAL
Bit 2 Reserved, must be kept at reset value.
Bit 1 HSIRDY: Internal high-speed clock ready flag
Set by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit is cleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles.
0: internal 8 MHz RC oscillator not ready
1: internal 8 MHz RC oscillator ready
Bit 0 HSION: Internal high-speed clock enable
Set and cleared by software.
Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby mode or in case of failure of the external 4-16 MHz oscillator used directly or indirectly as system clock. This bit cannot be reset if the internal 8 MHz RC is used directly or indirectly as system clock or is selected to become the system clock.
0: internal 8 MHz RC oscillator OFF
1: internal 8 MHz RC oscillator ON
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Address offset: 0x04
Reset value: 0x0000 0000
Access: 0 wait state 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during clock source switch.
31 30 29
15 14
ADCPRE[1:0] rw rw
Reserved
28 27
13 rw
12
PPRE2[2:0] rw
11 rw
26 25
MCO[2:0]
24 rw
10 rw rw
9
PPRE1[2:0] rw rw
8 rw
23
Res.
7 rw
22
USB
PRE rw
21 rw
6 5
HPRE[3:0] rw rw
20 19
PLLMUL[3:0] rw
4 rw
18 rw rw
3 2
SWS[1:0] r r
17
PLL
XTPRE rw
16
PLL
SRC rw
1
SW[1:0]
0 rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:24 MCO: Microcontroller clock output
Set and cleared by software.
0xx: No clock
100: System clock (SYSCLK) selected
101: HSI clock selected
110: HSE clock selected
111: PLL clock divided by 2 selected
Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.
When the System Clock is selected to output to the MCO pin, make sure that this clock does not exceed 50 MHz (the maximum IO speed).
Bit 22 USBPRE: USB prescaler
Set and cleared by software to generate 48 MHz USB clock. This bit must be valid before enabling the USB clock in the RCC_APB1ENR register. This bit can’t be reset if the USB clock is enabled.
0: PLL clock is divided by 1.5
1: PLL clock is not divided
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Bits 21:18 PLLMUL: PLL multiplication factor
These bits are written by software to define the PLL multiplication factor. These bits can be written only when PLL is disabled.
Caution: The PLL output frequency must not exceed 72 MHz.
0000: PLL input clock x 2
0001: PLL input clock x 3
0010: PLL input clock x 4
0011: PLL input clock x 5
0100: PLL input clock x 6
0101: PLL input clock x 7
0110: PLL input clock x 8
0111: PLL input clock x 9
1000: PLL input clock x 10
1001: PLL input clock x 11
1010: PLL input clock x 12
1011: PLL input clock x 13
1100: PLL input clock x 14
1101: PLL input clock x 15
1110: PLL input clock x 16
1111: PLL input clock x 16
Bit 17 PLLXTPRE: HSE divider for PLL entry
Set and cleared by software to divide HSE before PLL entry. This bit can be written only when PLL is disabled.
0: HSE clock not divided
1: HSE clock divided by 2
Bit 16 PLLSRC: PLL entry clock source
Set and cleared by software to select PLL clock source. This bit can be written only when
PLL is disabled.
0: HSI oscillator clock / 2 selected as PLL input clock
1: HSE oscillator clock selected as PLL input clock
Bits 15:14 ADCPRE: ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADCs.
00: PCLK2 divided by 2
01: PCLK2 divided by 4
10: PCLK2 divided by 6
11: PCLK2 divided by 8
Bits 13:11 PPRE2: APB high-speed prescaler (APB2)
Set and cleared by software to control the division factor of the APB high-speed clock
(PCLK2).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
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Bits 10:8 PPRE1: APB low-speed prescaler (APB1)
Set and cleared by software to control the division factor of the APB low-speed clock
(PCLK1).
Warning: the software has to set correctly these bits to not exceed 36 MHz on this domain.
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Bits 7:4 HPRE: AHB prescaler
Set and cleared by software to control the division factor of the AHB clock.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Note: The prefetch buffer must be kept on when using a prescaler different from 1 on the
AHB clock. Refer to Reading the Flash memory section for more details.
Bits 3:2 SWS: System clock switch status
Set and cleared by hardware to indicate which clock source is used as system clock.
00: HSI oscillator used as system clock
01: HSE oscillator used as system clock
10: PLL used as system clock
11: not applicable
Bits 1:0 SW: System clock switch
Set and cleared by software to select SYSCLK source.
Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security
System is enabled).
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: not allowed
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7.3.3 Clock interrupt register (RCC_CIR)
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
15
30 29
14
Reserved
13
28 27
Reserved
26 25 24
12
PLL
RDYIE rw
11
HSE
RDYIE rw
10
HSI
RDYIE rw
9
LSE
RDYIE rw
8
LSI
RDYIE rw
23
CSSC w
7
CSSF r
22
6
21
Reserved
5
Reserved
20
PLL
RDYC w
4
PLL
RDYF r
19
HSE
RDYC w
3
HSE
RDYF r
18
HSI
RDYC w
2
HSI
RDYF r
17
LSE
RDYC w
1
LSE
RDYF r
16
LSI
RDYC w
0
LSI
RDYF r
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Bits 22:21 Reserved, must be kept at reset value.
Bit 20 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: PLLRDYF cleared
Bit 19 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: HSERDYF cleared
Bit 18 HSIRDYC: HSI ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: HSIRDYF cleared
Bit 17 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
Bit 16 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 PLLRDYIE: PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
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Bit 11 HSERDYIE: HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the external 4-16 MHz oscillator stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Bit 10 HSIRDYIE: HSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC oscillator stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
Bit 9 LSERDYIE: LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Bit 8 LSIRDYIE: LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by internal RC 40 kHz oscillator stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
Bit 7 CSSF: Clock security system interrupt flag
Set by hardware when a failure is detected in the external 4-16 MHz oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 PLLRDYF: PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Bit3 HSERDYF: HSE ready interrupt flag
Set by hardware when External High Speed clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the external 4-16 MHz oscillator
1: Clock ready interrupt caused by the external 4-16 MHz oscillator
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Bit 2 HSIRDYF: HSI ready interrupt flag
Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is set.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the internal 8 MHz RC oscillator
1: Clock ready interrupt caused by the internal 8 MHz RC oscillator
Bit 1 LSERDYF: LSE ready interrupt flag
Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the external 32 kHz oscillator
1: Clock ready interrupt caused by the external 32 kHz oscillator
Bit 0 LSIRDYF: LSI ready interrupt flag
Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the internal RC 40 kHz oscillator
1: Clock ready interrupt caused by the internal RC 40 kHz oscillator
Address offset: 0x0C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28
15
ADC3
RST rw
14
USART1
RST rw
13
TIM8
RST rw
12
SPI1
RST rw
27 26
Reserved
25 24
11
TIM1
RST rw
10
ADC2
RST rw
9
ADC1
RST rw
8
IOPG
RST rw
23
7
IOPF
RST rw
22
6
IOPE
RST rw
21
TIM11
RST rw
5
IOPD
RST rw
20
TIM10
RST rw
4
IOPC
RST rw
19
TIM9
RST rw
3
IOPB
RST rw
18
2
IOPA
RST rw
17
Reserved
1
Res.
Res.
16
0
AFIO
RST rw
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 TIM11RST: TIM11 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM11 timer
Bit 20 TIM10RST: TIM10 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM10 timer
Bit 19 TIM9RST: TIM9 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM9 timer
Bits 18:16 Reserved, always read as 0.
106/1136 RM0008 Rev 21
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Bit 15 ADC3RST: ADC3 interface reset
Set and cleared by software.
0: No effect
1: Reset ADC3 interface
Bit 14 USART1RST: USART1 reset
Set and cleared by software.
0: No effect
1: Reset USART1
Bit 13 TIM8RST: TIM8 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM8 timer
Bit 12 SPI1RST: SPI1 reset
Set and cleared by software.
0: No effect
1: Reset SPI1
Bit 11 TIM1RST: TIM1 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
Bit 10 ADC2RST: ADC 2 interface reset
Set and cleared by software.
0: No effect
1: Reset ADC 2 interface
Bit 9 ADC1RST: ADC 1 interface reset
Set and cleared by software.
0: No effect
1: Reset ADC 1 interface
Bit 8 IOPGRST: IO port G reset
Set and cleared by software.
0: No effect
1: Reset IO port G
Bit 7 IOPFRST: IO port F reset
Set and cleared by software.
0: No effect
1: Reset IO port F
Bit 6 IOPERST: IO port E reset
Set and cleared by software.
0: No effect
1: Reset IO port E
Bit 5 IOPDRST: IO port D reset
Set and cleared by software.
0: No effect
1: Reset IO port D
RM0008 Rev 21 107/1136
122
Low-, medium-, high- and XL-density reset and clock control (RCC)
Bit 4 IOPCRST: IO port C reset
Set and cleared by software.
0: No effect
1: Reset IO port C
Bit 3 IOPBRST: IO port B reset
Set and cleared by software.
0: No effect
1: Reset IO port B
Bit 2 IOPARST: IO port A reset
Set and cleared by software.
0: No effect
1: Reset IO port A
Bit 1 Reserved, must be kept at reset value.
Bit 0 AFIORST: Alternate function IO reset
Set and cleared by software.
0: No effect
1: Reset Alternate Function
RM0008
108/1136 RM0008 Rev 21
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
15
SPI3
RST rw
31 30
Reserved
14
SPI2
RST rw
29
DAC
RST rw
13
Reserved
28
PWR
RST rw
12
27
BKP
RST rw
11
WWDG
RST rw
26
Res.
10
Reserved
25
CAN
RST rw
9
24
Res.
8
TIM14
RST rw
23
USB
RST
22
I2C2
RST rw
7
TIM13
RST rw rw
6
TIM12
RST rw
21
I2C1
RST rw
5
TIM7
RST rw
20
UART5
RST
UART4
RST rw
4
TIM6
RST rw
19 rw
3
TIM5
RST rw
18
USART
3
RST rw
2
TIM4
RST rw
17
USART
2
RST rw
1
TIM3
RST rw
16
Res.
0
TIM2
RST rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACRST: DAC interface reset
Set and cleared by software.
0: No effect
1: Reset DAC interface
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
0: No effect
1: Reset power interface
Bit 27 BKPRST: Backup interface reset
Set and cleared by software.
0: No effect
1: Reset backup interface
Bit 26 Reserved, must be kept at reset value.
Bit 25 CANRST: CAN reset
Set and cleared by software.
0: No effect
1: Reset CAN
Bit 24 Reserved, always read as 0.
Bit 23 USBRST: USB reset
Set and cleared by software.
0: No effect
1: Reset USB
Bit 22 I2C2RST: I2C2 reset
Set and cleared by software.
0: No effect
1: Reset I2C2
Bit 21 I2C1RST: I2C1 reset
Set and cleared by software.
0: No effect
1: Reset I2C1
RM0008 Rev 21 109/1136
122
Low-, medium-, high- and XL-density reset and clock control (RCC)
Bit 20 UART5RST: USART5 reset
Set and cleared by software.
0: No effect
1: Reset USART5
Bit 19 UART4RST: USART4 reset
Set and cleared by software.
0: No effect
1: Reset USART4
Bit 18 USART3RST: USART3 reset
Set and cleared by software.
0: No effect
1: Reset USART3
Bit 17 USART2RST: USART2 reset
Set and cleared by software.
0: No effect
1: Reset USART2
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3RST: SPI3 reset
Set and cleared by software.
0: No effect
1: Reset SPI3
Bit 14 SPI2RST: SPI2 reset
Set and cleared by software.
0: No effect
1: Reset SPI2
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGRST: Window watchdog reset
Set and cleared by software.
0: No effect
1: Reset window watchdog
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 TIM14RST: TIM14 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM14
Bit 7 TIM13RST: TIM13 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM13
Bit 6 TIM12RST: TIM12 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM12
110/1136 RM0008 Rev 21
RM0008
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Bit 5 TIM7RST: TIM7 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM7
Bit 4 TIM6RST: TIM6 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM6
Bit 3 TIM5RST: TIM5 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM5
Bit 2 TIM4RST: TIM4 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM4
Bit 1 TIM3RST: TIM3 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM3
Bit 0 TIM2RST: TIM2 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM2
7.3.6
Note:
31
15
AHB peripheral clock enable register (RCC_AHBENR)
Address offset: 0x14
Reset value: 0x0000 0014
Access: no wait state, word, half-word and byte access
When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0.
30 29 28 27 26 25
14 13
Reserved
12 11 10
SDIO
EN rw
9
Res.
24 23
Reserved
7 8
FSMC
EN rw
Res.
22
6
CRCE
N rw
21 20
5
Res.
4
FLITF
EN rw
19 18 17 16
3
Res.
2
SRAM
EN rw
1
DMA2
EN rw
0
DMA1
EN rw
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 SDIOEN: SDIO clock enable
Set and cleared by software.
0: SDIO clock disabled
1: SDIO clock enabled
Bits 9 Reserved, always read as 0.
RM0008 Rev 21 111/1136
122
Low-, medium-, high- and XL-density reset and clock control (RCC)
7.3.7
Note:
RM0008
Bit 8 FSMCEN: FSMC clock enable
Set and cleared by software.
0: FSMC clock disabled
1: FSMC clock enabled
Bit 7 Reserved, always read as 0.
Bit 6 CRCEN: CRC clock enable
Set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Bit 5 Reserved, must be kept at reset value.
Bit 4 FLITFEN: FLITF clock enable
Set and cleared by software to disable/enable FLITF clock during Sleep mode.
0: FLITF clock disabled during Sleep mode
1: FLITF clock enabled during Sleep mode
Bit 3 Reserved, must be kept at reset value.
Bit 2 SRAMEN: SRAM interface clock enable
Set and cleared by software to disable/enable SRAM interface clock during Sleep mode.
0: SRAM interface clock disabled during Sleep mode.
1: SRAM interface clock enabled during Sleep mode
Bit 1 DMA2EN: DMA2 clock enable
Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Bit 0 DMA1EN: DMA1 clock enable
Set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
APB2 peripheral clock enable register (RCC_APB2ENR)
Address: 0x18
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in the APB2 domain is on going. In this case, wait states are inserted until the access to APB2 peripheral is finished.
When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0.
112/1136 RM0008 Rev 21
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
31 30 29 28 27 26
Reserved
25 24 23
15
ADC3
EN rw
14
USART
1EN rw
13
TIM8
EN rw
12
SPI1
EN rw
11
TIM1
EN rw
10
ADC2
EN rw
9
ADC1
EN rw
8
IOPG
EN rw
7
IOPF
EN rw
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 TIM11EN: TIM11 timer clock enable
Set and cleared by software.
0: TIM11 timer clock disabled
1: TIM11 timer clock enabled
Bit 20 TIM10EN: TIM10 timer clock enable
Set and cleared by software.
0: TIM10 timer clock disabled
1: TIM10 timer clock enabled
Bit 19 TIM9EN: TIM9 timer clock enable
Set and cleared by software.
0: TIM9 timer clock disabled
1: TIM9 timer clock enabled
Bits 18:16 Reserved, always read as 0.
Bit 15 ADC3EN: ADC3 interface clock enable
Set and cleared by software.
0: ADC3 interface clock disabled
1: ADC3 interface clock enabled
Bit 14 USART1EN: USART1 clock enable
Set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Bit 13 TIM8EN: TIM8 Timer clock enable
Set and cleared by software.
0: TIM8 timer clock disabled
1: TIM8 timer clock enabled
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bit 11 TIM1EN: TIM1 timer clock enable
Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1 timer clock enabled
Bit 10 ADC2EN: ADC 2 interface clock enable
Set and cleared by software.
0: ADC 2 interface clock disabled
1: ADC 2 interface clock enabled
22
6
IOPE
EN rw
21
TIM11
EN rw
5
IOPD
EN rw
20
TIM10
EN rw
4
IOPC
EN rw
19
TIM9
EN rw
3
IOPB
EN rw
18
2
IOPA
EN rw
17
Reserved
1
Res.
16
0
AFIO
EN rw
RM0008 Rev 21 113/1136
122
Low-, medium-, high- and XL-density reset and clock control (RCC)
Bit 9 ADC1EN: ADC 1 interface clock enable
Set and cleared by software.
0: ADC 1 interface disabled
1: ADC 1 interface clock enabled
Bit 8 IOPGEN: IO port G clock enable
Set and cleared by software.
0: IO port G clock disabled
1: IO port G clock enabled
Bit 7 IOPFEN: IO port F clock enable
Set and cleared by software.
0: IO port F clock disabled
1: IO port F clock enabled
Bit 6 IOPEEN: IO port E clock enable
Set and cleared by software.
0: IO port E clock disabled
1: IO port E clock enabled
Bit 5 IOPDEN: IO port D clock enable
Set and cleared by software.
0: IO port D clock disabled
1: IO port D clock enabled
Bit 4 IOPCEN: IO port C clock enable
Set and cleared by software.
0: IO port C clock disabled
1: IO port C clock enabled
Bit 3 IOPBEN: IO port B clock enable
Set and cleared by software.
0: IO port B clock disabled
1: IO port B clock enabled
Bit 2 IOPAEN: IO port A clock enable
Set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled
Bit 1 Reserved, must be kept at reset value.
Bit 0 AFIOEN: Alternate function IO clock enable
Set and cleared by software.
0: Alternate Function IO clock disabled
1: Alternate Function IO clock enabled
RM0008
114/1136 RM0008 Rev 21
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
7.3.8
Note:
APB1 peripheral clock enable register (RCC_APB1ENR)
Address: 0x1C
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going. In this case, wait states are inserted until this access to APB1 peripheral is finished.
When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0.
15
SPI3
EN rw
31 30
Reserved
14
SPI2
EN rw
29
DAC
EN rw
13
Reserved
28
PWR
EN rw
12
27
BKP
EN rw
11
WWD
GEN rw
26
Res.
10
25
CAN
EN rw
9
Reserved
24
Res.
8
TIM14
EN rw
23
USB
EN rw
7
TIM13
EN rw
22
I2C2
EN rw
6
TIM12
EN rw
21
I2C1
EN rw
5
TIM7
EN rw
20
UART5
EN rw
4
TIM6
EN rw
19
UART4
EN rw
3
TIM5
EN rw
18
USART3
EN rw
2
TIM4
EN rw
17
USART2
EN rw
1
TIM3
EN rw
16
Res.
0
TIM2
EN rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACEN: DAC interface clock enable
Set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Bit 27 BKPEN: Backup interface clock enable
Set and cleared by software.
0: Backup interface clock disabled
1: Backup interface clock enabled
Bit 26 Reserved, must be kept at reset value.
Bit 25 CANEN: CAN clock enable
Set and cleared by software.
0: CAN clock disabled
1: CAN clock enabled
Bit 24 Reserved, always read as 0.
Bit 23 USBEN: USB clock enable
Set and cleared by software.
0: USB clock disabled
1: USB clock enabled
RM0008 Rev 21 115/1136
122
Low-, medium-, high- and XL-density reset and clock control (RCC)
Bit 22 I2C2EN: I2C2 clock enable
Set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
Bit 21 I2C1EN: I2C1 clock enable
Set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
Bit 20 UART5EN: USART5 clock enable
Set and cleared by software.
0: USART5 clock disabled
1: USART5 clock enabled
Bit 19 UART4EN: USART4 clock enable
Set and cleared by software.
0: USART4 clock disabled
1: USART4 clock enabled
Bit 18 USART3EN: USART3 clock enable
Set and cleared by software.
0: USART3 clock disabled
1: USART3 clock enabled
Bit 17 USART2EN: USART2 clock enable
Set and cleared by software.
0: USART2 clock disabled
1: USART2 clock enabled
Bits 16 Reserved, always read as 0.
Bit 15 SPI3EN: SPI 3 clock enable
Set and cleared by software.
0: SPI 3 clock disabled
1: SPI 3 clock enabled
Bit 14 SPI2EN: SPI2 clock enable
Set and cleared by software.
0: SPI2 clock disabled
1: SPI2 clock enabled
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable
Set and cleared by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 TIM14EN: TIM14 timer clock enable
Set and cleared by software.
0: TIM14 clock disabled
1: TIM14 clock enabled
116/1136 RM0008 Rev 21
RM0008
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Bit 7 TIM13EN: TIM13 timer clock enable
Set and cleared by software.
0: TIM13 clock disabled
1: TIM13 clock enabled
Bit 6 TIM12EN: TIM12 timer clock enable
Set and cleared by software.
0: TIM12 clock disabled
1: TIM12 clock enabled
Bit 5 TIM7EN: TIM7 timer clock enable
Set and cleared by software.
0: TIM7 clock disabled
1: TIM7 clock enabled
Bit 4 TIM6EN: TIM6 timer clock enable
Set and cleared by software.
0: TIM6 clock disabled
1: TIM6 clock enabled
Bit 3 TIM5EN: TIM5 timer clock enable
Set and cleared by software.
0: TIM5 clock disabled
1: TIM5 clock enabled
Bit 2 TIM4EN: TIM4 timer clock enable
Set and cleared by software.
0: TIM4 clock disabled
1: TIM4 clock enabled
Bit 1 TIM3EN: TIM3 timer clock enable
Set and cleared by software.
0: TIM3 clock disabled
1: TIM3 clock enabled
Bit 0 TIM2EN: TIM2 timer clock enable
Set and cleared by software.
0: TIM2 clock disabled
1: TIM2 clock enabled
RM0008 Rev 21 117/1136
122
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
Note:
31
15
RTC
EN rw
Address offset: 0x20
Reset value: 0x0000 0000, reset by Backup domain Reset.
Access: 0 wait state 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
The LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register
are in the Backup domain. As a result, after Reset, these bits are write-
protected and the DBP bit in the Power control register (PWR_CR)
has to be set before
these can be modified. Refer to Section 5: Power control (PWR)
for further information.
These bits are only reset after a Backup domain Reset (see Section 7.1.3: Backup domain reset
). Any internal or external Reset will not have any effect on these bits.
30 29
14 13
28
12
Reserved
27
11
26
10
25 24
Reserved
23
9 8
RTCSEL[1:0] rw rw
7
22
6
21
5
Reserved
20
4
19
3
18
2
LSE
BYP rw
17
1
LSE
RDY r
16
BDRST rw
0
LSEON rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 BDRST: Backup domain software reset
Set and cleared by software.
0: Reset not activated
1: Resets the entire Backup domain
Bit 15 RTCEN: RTC clock enable
Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit can be used to reset them.
00: No clock
01: LSE oscillator clock used as RTC clock
10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by 128 used as RTC clock
Bits 7:3 Reserved, must be kept at reset value.
118/1136 RM0008 Rev 21
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
Bit 2 LSEBYP: External low-speed oscillator bypass
Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY: External low-speed oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles.
0: External 32 kHz oscillator not ready
1: External 32 kHz oscillator ready
Bit 0 LSEON: External low-speed oscillator enable
Set and cleared by software.
0: External 32 kHz oscillator OFF
1: External 32 kHz oscillator ON
7.3.10 Control/status register (RCC_CSR)
Address: 0x24
Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only.
Access: 0 wait state 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
31
LPWR
RSTF rw
15
30
WWDG
RSTF
29
IWDG
RSTF rw
14 rw
13
28
SFT
RSTF rw
12
27
POR
RSTF rw
11
26
PIN
RSTF rw
10
25
Res.
9
24
RMVF rw
8
23
7
22
6
21
5
20
4
19
Reserved
3
18
2
17 16
Reserved
1
LSI
RDY r
0
LSION rw
RM0008 Rev 21 119/1136
122
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008
120/1136
Bit 31 LPWRRSTF: Low-power reset flag
Set by hardware when a Low-power management reset occurs.
Cleared by writing to the RMVF bit.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to
Bit 30 WWDGRSTF: Window watchdog reset flag
Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF: Independent watchdog reset flag
Set by hardware when an independent watchdog reset from V
DD
Cleared by writing to the RMVF bit.
domain occurs.
0: No watchdog reset occurred
1: Watchdog reset occurred
Bit 28 SFTRSTF: Software reset flag
Set by hardware when a software reset occurs.
Cleared by writing to the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 PORRSTF: POR/PDR reset flag
Set by hardware when a POR/PDR reset occurs.
Cleared by writing to the RMVF bit.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred
Bit 26 PINRSTF: PIN reset flag
Set by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 Reserved, must be kept at reset value.
Bit 24 RMVF: Remove reset flag
Set by software to clear the reset flags.
0: No effect
1: Clear the reset flags
Bits 23:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY: Internal low-speed oscillator ready
Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.
After the LSION bit is cleared, LSIRDY goes low after 3 internal RC 40 kHz oscillator clock cycles.
0: Internal RC 40 kHz oscillator not ready
1: Internal RC 40 kHz oscillator ready
Bit 0 LSION: Internal low-speed oscillator enable
Set and cleared by software.
0: Internal RC 40 kHz oscillator OFF
1: Internal RC 40 kHz oscillator ON
RM0008 Rev 21
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)
7.3.11 RCC register map
The following table gives the RCC register map and the reset values.
Table 18. RCC register map and reset values
Offset Register
0x00
0x04
0x08
RCC_CR
Reset value
RCC_CFGR
Reset value
RCC_CIR
Reset value
0x0C
RCC_APB2RSTR
Reset value
0x010
RCC_APB1RSTR
0x14
Reset value
RCC_AHBENR
Reset value
0x18
RCC_APB2ENR
Reset value
0x1C
RCC_APB1ENR
Reset value
0x20
RCC_BDCR
Reset value
Reserved
Reserved
0 0
MCO
[2:0]
0 0 0
HSICAL[7:0] HSITRIM[4:0]
Reserved
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
PLLMUL
[3:0]
ADC
PRE
[1:0]
PPRE2
[2:0]
PPRE1
[2:0]
HPRE[3:0]
SWS
[1:0]
1 1
SW
[1:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
0 0 0 0
Reserved
0 0 0 0
0
0
0
0
0
0
0 0
0 0 0 0 0 0 0 0 0
Reserved
0
Rese rved
0 0 0 0 0 0 0 0 0
Reserved
0 0 0 1 1 0 0
0 0 0
Reserve d
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
0
0 0 0
0
0
0
0
0
0
0
0
0
0
0
0 0 0
0
0
0
0
0
0
0 0
0
0
0 0
0
0
Reserved
0 0 0 0 0 0 0 0 0
RTC
SEL
[1:0]
0 0
Reserved
0 0 0
RM0008 Rev 21 121/1136
122
Low-, medium-, high- and XL-density reset and clock control (RCC)
Table 18. RCC register map and reset values (continued)
Offset Register
0x24
RCC_CSR
Reset value 0 0 0 0 1 1 0
Reserved
for the register boundary addresses.
RM0008
0 0
122/1136 RM0008 Rev 21
RM0008
8
Connectivity line devices: reset and clock control (RCC)
Connectivity line devices: reset and clock control
(RCC)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to all connectivity line devices, unless otherwise specified.
8.1 Reset
There are three types of reset, defined as system reset, power reset and backup domain reset.
A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see Figure 4
).
A system reset is generated when one of the following events occurs:
1.
A low level on the NRST pin (external reset)
2. Window watchdog end of count condition (WWDG reset)
3. Independent watchdog end of count condition (IWDG reset)
4. A software reset (SW reset) (see
)
5. Low-power management reset (see
)
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see
Section 8.3.10: Control/status register (RCC_CSR)
).
Software reset
The SYSRESETREQ bit in Cortex
®
-M3 Application Interrupt and Reset Control register must be set to force a software reset on the device. Refer to the STM32F10xxx Cortex
®
-M3 programming manual
) for more details.
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Low-power management reset
There are two ways to generate a low-power management reset:
1.
Reset generated when entering Standby mode:
This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.
2. Reset when entering Stop mode:
This type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode.
For further information on the User Option Bytes, refer to the STM32F10xxx Flash programming manual.
A power reset is generated when one of the following events occurs:
1.
Power-on/power-down reset (POR/PDR reset)
2. When exiting Standby mode
A power reset sets all registers to their reset values except the Backup domain (see
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map. For more
details, refer to Table 63: Vector table for other STM32F10xxx devices .
The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each reset source
(external or internal reset). In case of an external reset, the reset pulse is generated while the NRST pin is asserted low.
Figure 10. Simplified diagram of the reset circuit
V
DD
/V
DDA
R
PU
External reset
NRST
Filter
System reset
Pulse generator
(min 20 μs)
WWDG reset
IWDG reset
Power reset
Software reset
Low-power management reset ai16095c
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RM0008 Connectivity line devices: reset and clock control (RCC)
The backup domain has two specific resets that affect only the backup domain (see
A backup domain reset is generated when one of the following events occurs:
1.
Software reset, triggered by setting the BDRST bit in the Backup domain control register (RCC_BDCR)
.
2. V
DD
or V
BAT
power on, if both supplies have previously been powered off.
8.2 Clocks
Three different clock sources can be used to drive the system clock (SYSCLK):
HSI oscillator clock
HSE oscillator clock
PLL clock
The devices have the following two secondary clock sources:
40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and optionally the RTC used for Auto-wakeup from Stop/Standby mode.
32.768 kHz low speed external crystal (LSE crystal) which optionally drives the realtime clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize power consumption.
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Figure 11. Clock tree
OSC32_IN
OSC32_OUT
OSC_IN
OSC_OUT
40 kHz
LSI
RC
32.768 kHz
LSE
OSC
XT1 to MCO
3-25 MHz
HSE
OSC to independent watchdog
IWDGCLK
LSI
LSE to RTC
RTCCLK
/128
RTCSEL[1:0]
HSE
CSS to Flash prog. IF FLITFCLK
8 MHz
HSI RC PLLMUL
/2
/1,2,3....
..../15, /16
PREDIV1
PREDIV1SCR
PLLSCR
PLL2MUL
HSI x4, x5,... x9, PLLCLK x6.5
SW
PLLVCO (2 × PLLCLK)
USB prescaler
/2,3
OTGFSCLK
48 MHz to USB OTG FS x8, x9,... x14, x16, x20 to I2S2 interface PREDIV2
/1,2,3....
..../15, /16
PLL3MUL PLL2CLK to MCO x8, x9,... x14, x16, x20
PLL3VCO
(2 × PLL3CLK) to I2S3 interface
PLL3CLK to MCO
SYSCLK system clock
MCO
MCO[3:0]
HSE
HSI
PLLCLK/2
PLL2CLK
PLL3CLK/2
PLL3CLK
XT1
SYSCLK
72 MHz max.
(see note1)
AHB prescaler
/1,/2 ../512
/8
APB1 prescaler
/1, 2, 4, 8, 16
HCLK to AHB bus, core memory and DMA to Cortex System timer
FCLK Cortex free running clock
36 MHz max
Peripheral clock enable
PCLK1 to APB1 peripherals
TIM2,3,4,5,6,7
If(APB1 prescaler =1) x1 else x2
Peripheral clock enable to TIM2,3,4,5,
6 & 7
TIMxCLK
APB2 prescaler
/1, 2, 4, 8, 16
72 MHz max
Peripheral clock enable
PCLK2 to APB2 peripherals
Ethernet
PHY
ETH_MII_TX_CLK
ETH_MII_RX_CLK
/2, /20
MACTXCLK
MII_RMII_SEL in AFIO_MAPR
MACRXCLK to Ethernet MAC
MACRMIICLK
TIM1
If(APB2 prescaler =1) x1 else x2
Peripheral clock enable to TIM1
TIMxCLK
ADC prescaler
/2, 4, 6, 8
ADCCLK
14 MHz max to ADC1,2 ai15699d
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.
2. For full details about the internal and external clock source characteristics, refer to the “Electrical characteristics” section in your device datasheet.
The advanced clock controller features 3 PLLs to provide a high degree of flexibility to the application in the choice of the external crystal or oscillator to run the core and peripherals at the highest frequency and guarantee the appropriate frequency for the Ethernet and USB
OTG FS.
A single 25 MHz crystal can clock the entire system and all peripherals including the
Ethernet and USB OTG FS peripherals. In order to achieve high-quality audio performance, an audio crystal can be used. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 96 kHz with less than 0.5% accuracy.
For more details about clock configuration for applications requiring Ethernet, USB OTG FS and/or I 2 S (audio), refer to "Appendix A Applicative block diagrams" in your connectivity line device datasheet.
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Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is
36 MHz.
All peripheral clocks are derived from the system clock (SYSCLK) except:
The Flash memory programming interface clock (FLITFCLK) is always the HSI clock
The USB OTG FS 48 MHz clock which is derived from the PLL VCO clock (2 ×
PLLCLK), followed by a programmable prescaler (divide by 3 or 2). This selection is made through the OTGFSPRE bit in the RCC_CFGR register. For proper USB OTG FS operation, the PLL should be configured to output 72 MHz or 48 MHz.
The I2S2 and I2S3 clocks which can be derived from the system clock (SYSCLK) or the PLL3 VCO clock (2 × PLL3CLK). This selection is made through the I2SxSRC bit in the RCC_CFGR2 register. For more information on PLL3 and how to configure the I2S
clock to achieve high-quality audio performance, refer to Section 25.4.3: Clock generator .
The Ethernet MAC clocks (TX, RX and RMII) which are provided from the external
PHY. For further information on the Ethernet configuration, refer to Section 29.4.4:
When the Ethernet is used, the AHB clock frequency must be at least 25 MHz.
The RCC feeds the Cortex ® System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex ® clock
(HCLK), configurable in the SysTick Control and Status register. The ADCs are clocked by the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8.
The timer clock frequencies are automatically fixed by hardware. There are two cases:
1.
if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected.
2. otherwise, they are set to twice (×2) the frequency of the APB domain to which the timers are connected.
FCLK acts as Cortex ® -M3 free-running clock. For more details refer to Arm ®
Cortex-M3 r1p1 Technical Reference Manual (TRM) .
The high speed external clock signal (HSE) can be generated from two possible clock sources:
HSE external crystal/ceramic resonator
HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.
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Clock source
Figure 12. HSE/ LSE clock sources
Hardware configuration
RM0008
External clock
OSC_OUT
(HiZ)
External source
OSC_IN OSC_OUT
Crystal/ceramic resonators
C
L1
C
L2
Load capacitors
External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
50 MHz. Select this mode by setting the HSEBYP and HSEON
cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See
.
External crystal/ceramic resonator (HSE crystal)
The 3 to 25 MHz external oscillator has the advantage of producing a very accurate rate on the main clock.
The associated hardware configuration is shown in
. Refer to the electrical characteristics section of the datasheet for more details.
The HSERDY flag in the
Clock control register (RCC_CR) indicates if the high-speed
external oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the
The HSE crystal can be switched on and off using the HSEON bit in the
Clock control register (RCC_CR) .
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The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used directly as a system clock or divided by 2 to be used as PLL input.
The HSI RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator.
RM0008 Rev 21
RM0008 Connectivity line devices: reset and clock control (RCC)
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T
A
= 25 °C.
If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the Clock control register (RCC_CR) .
The HSIRDY flag in the
Clock control register (RCC_CR) indicates if the HSI RC is stable or
not. At startup, the HSI RC output clock is not released until this bit is set by hardware.
The HSI RC can be switched on and off using the HSION bit in the
.
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to
Section 8.2.7: Clock security system (CSS) .
8.2.3 PLLs
The main PLL provides a frequency multiplier starting from one of the following clock sources:
HSI clock divided by 2
HSE or PLL2 clock through a configurable divider
Clock control register (RCC_CR)
.
PLL2 and PLL3 are clocked by HSE through a specific configurable divider. Refer to
and Clock configuration register2 (RCC_CFGR2)
The configuration of each PLL (selection of clock source, predivision factor and multiplication factor) must be done before enabling the PLL. Each PLL should be enabled after its input clock becomes stable (ready flag). Once the PLL is enabled, these parameters can not be changed.
When changing the entry clock source of the main PLL, the original clock source must be switched off only after the selection of the new clock source (done through bit PLLSRC in the Clock configuration register (RCC_CFGR)).
The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the advantage providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in
Backup domain control register (RCC_BDCR)
.
The LSERDY flag in the
Backup domain control register (RCC_BDCR)
indicates if the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the
Clock interrupt register (RCC_CIR) .
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External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the
~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left
8.2.6
The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the
.
The LSIRDY flag in the Control/status register (RCC_CSR)
indicates if the low-speed internal oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the
LSI calibration
The frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for these peripherals) with an acceptable accuracy.
This calibration is performed by measuring the LSI clock frequency with respect to TIM5 input clock (TIM5CLK). According to this measurement done at the precision of the HSE oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an accurate time base or can compute accurate IWDG timeout.
Use the following procedure to calibrate the LSI:
1.
Enable TIM5 timer and configure channel4 in input capture mode
2. Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock internally to TIM5 channel4 input capture for calibration purpose.
3. Measure the frequency of LSI clock using the TIM5 Capture/compare 4 event or interrupt.
4. Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending on the desired time base and/or to compute the IWDG timeout.
System clock (SYSCLK) selection
After a system reset, the HSI oscillator is selected as system clock. When a clock source is used directly or through the PLL as the system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. Status bits in the
Clock control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently
used as system clock.
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RM0008
8.2.7
Note:
Connectivity line devices: reset and clock control (RCC)
Clock security system (CSS)
Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. a failure is detected on the HSE clock, the HSE Oscillator is automatically disabled, a clock failure event is sent to the break input of the TIM1 Advanced control timer and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex
®
-M3 NMI
(Non-Maskable Interrupt) exception vector.
Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is automatically generated. The NMI will be executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by setting the CSSC bit in the
Clock interrupt register (RCC_CIR)
.
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock directly or through PLL2, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock to the HSI oscillator and the disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL (directly or through PLL2) used as system clock when the failure occurs, the PLL is disabled too.
The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected
by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR) .
This selection cannot be modified without resetting the Backup domain.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.
Consequently:
If LSE is selected as RTC clock:
– The RTC continues to work even if the V
DD
V
BAT
supply is maintained.
supply is switched off, provided the
If LSI is selected as Auto-Wakeup unit (AWU) clock:
– The AWU state is not guaranteed if the V
DD
supply is powered off. Refer to
for more details on LSI calibration.
If the HSE clock divided by 128 is used as RTC clock:
– The RTC state is not guaranteed if the V
DD
supply is powered off or if the internal voltage regulator is powered off (removing power from the 1.8 V domain).
– The DPB bit (Disable backup domain write protection) in the Power controller
register must be set to 1 (refer to Section 5.4.1: Power control register
If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG.
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The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One of 8 clock signals can be selected as the MCO clock.
SYSCLK
HSI
HSE
PLL clock divided by 2 selected
PLL2 clock selected
PLL3 clock divided by 2 selected
XT1 external 3-25 MHz oscillator clock selected (for Ethernet)
PLL3 clock selected (for Ethernet)
The selected clock to output onto MCO must not exceed 50 MHz (the maximum I/O speed).
The selection is controlled by the MCO[3:0] bits of the
.
Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.
Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-word and byte access
31
Reserved
15 r
30
14 r
29
PLL3
RDY r
13 r
28
PLL3
ON
27
PLL2
RDY rw
12 r
11
HSICAL[7:0] r r
26
PLL2
ON rw
10
25
PLLRD
Y r
9
24
PLLON rw
8 r r r
23
7
22 21
Reserved
20
6 5 4 rw
HSITRIM[4:0] rw rw
19
CSSON rw
3
18
HSEBY
P rw
2 rw
Res.
17
HSERD
Y
16
HSEON r
1 rw
0
HSIRDY HSION r rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 PLL3RDY : PLL3 clock ready flag
Set by hardware to indicate that the PLL3 is locked.
0: PLL3 unlocked
1: PLL3 locked
Bit 28 PLL3ON : PLL3 enable
Set and cleared by software to enable PLL3.
Cleared by hardware when entering Stop or Standby mode.
0: PLL3 OFF
1: PLL3 ON
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RM0008 Connectivity line devices: reset and clock control (RCC)
Bit 27 PLL2RDY : PLL2 clock ready flag
Set by hardware to indicate that the PLL2 is locked.
0: PLL2 unlocked
1: PLL2 locked
Bit 26 PLL2ON : PLL2 enable
Set and cleared by software to enable PLL2.
Cleared by hardware when entering Stop or Standby mode. This bit can not be cleared if the
PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock).
0: PLL2 OFF
1: PLL2 ON
Bit 25 PLLRDY : PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON : PLL enable
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the
PLL clock is used as system clock or is selected to become the system clock. Software must disable the USB OTG FS clock before clearing this bit.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 CSSON : Clock security system enable
Set and cleared by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected.
0: Clock detector OFF
1: Clock detector ON (Clock detector ON if the HSE oscillator is ready, OFF if not)
Bit 18 HSEBYP : External high-speed clock bypass
Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.
0: external 3-25 MHz oscillator not bypassed
1: external 3-25 MHz oscillator bypassed with external clock
Bit 17 HSERDY : External high-speed clock ready flag
Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the
HSE oscillator clock to fall down after HSEON reset.
0: HSE oscillator not ready
1: HSE oscillator ready
Bit 16 HSEON : HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:8 HSICAL[7:0] : Internal high-speed clock calibration
These bits are initialized automatically at startup.
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Bits 7:3 HSITRIM[4:0] : Internal high-speed clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the internal HSI RC.
The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8
MHz ± 1%. The trimming step (F hsitrim steps.
) is around 40 kHz between two consecutive HSICAL
Bit 2 Reserved, must be kept at reset value.
Bit 1 HSIRDY : Internal high-speed clock ready flag
Set by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit is cleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles.
0: Internal 8 MHz RC oscillator not ready
1: Internal 8 MHz RC oscillator ready
Bit 0 HSION : Internal high-speed clock enable
Set and cleared by software.
Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby mode or in case of failure of the external 3-25 MHz oscillator used directly or indirectly as system clock. This bit can not be cleared if the internal 8 MHz RC is used directly or indirectly as system clock or is selected to become the system clock.
0: Internal 8 MHz RC oscillator OFF
1: Internal 8 MHz RC oscillator ON
31
Address offset: 0x04
Reset value: 0x0000 0000
Access: 0 wait state 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during a clock source switch.
30 29 28 27
15 14
ADC PRE[1:0] rw rw
Reserved
13 rw
12
PPRE2[2:0] rw rw
11 rw
26 25 24
MCO[3:0] rw
10 rw rw
9
PPRE1[2:0] rw rw
8 rw
23
Res.
7 rw
22 21
OTGFS
PRE rw rw
6 5
HPRE[3:0] rw rw
20 19 18
PLLMUL[3:0] rw
4 rw rw rw
3 2
SWS[1:0] r r
17
PLL
XTPRE rw
16
PLL
SRC rw
1
SW[1:0]
0 rw rw
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RM0008 Connectivity line devices: reset and clock control (RCC)
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:24 MCO[3:0] : Microcontroller clock output
Set and cleared by software.
00xx: No clock
0100: System clock (SYSCLK) selected
0101: HSI clock selected
0110: HSE clock selected
0111: PLL clock divided by 2 selected
1000: PLL2 clock selected
1001: PLL3 clock divided by 2 selected
1010: XT1 external 3-25 MHz oscillator clock selected (for Ethernet)
1011: PLL3 clock selected (for Ethernet)
Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.
The selected clock to output onto the MCO pin must not exceed 50 MHz (the maximum I/O speed).
Bit 22 OTGFSPRE : USB OTG FS prescaler
Set and cleared by software to generate the 48 MHz USB OTG FS clock. This bit must be valid before enabling the OTG FS clock in the RCC_APB1ENR register. This bit can not be cleared if the
OTG FS clock is enabled.
0: PLL VCO (2 × PLLCLK) clock is divided by 3 (PLL must be configured to output 72 MHz)
1: PLL VCO (2 × PLLCLK) clock is divided by 2 (PLL must be configured to output 48 MHz)
Bits 21:18 PLLMUL[3:0] : PLL multiplication factor
These bits are written by software to define the PLL multiplication factor. They can be written only when PLL is disabled.
000x: Reserved
0010: PLL input clock x 4
0011: PLL input clock x 5
0100: PLL input clock x 6
0101: PLL input clock x 7
0110: PLL input clock x 8
0111: PLL input clock x 9
10xx: Reserved
1100: Reserved
1101: PLL input clock x 6.5
111x: Reserved
Caution: The PLL output frequency must not exceed 72 MHz.
Bit 17 PLLXTPRE : LSB of division factor PREDIV1
Set and cleared by software to select the least significant bit of the PREDIV1 division factor. It is the same bit as bit(0) in the RCC_CFGR2 register, so modifying bit(0) in the RCC_CFGR2 register changes this bit accordingly.
If bits[3:1] in register RCC_CFGR2 are not set, this bit controls if PREDIV1 divides its input clock by
2 (PLLXTPRE=1) or not (PLLXTPRE=0).
This bit can be written only when PLL is disabled.
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Bit 16 PLLSRC : PLL entry clock source
Set and cleared by software to select PLL clock source. This bit can be written only when PLL is disabled.
0: HSI oscillator clock / 2 selected as PLL input clock
1: Clock from PREDIV1 selected as PLL input clock
Note: When changing the main PLL’s entry clock source, the original clock source must be switched off only after the selection of the new clock source.
Bits 14:14 ADCPRE[1:0] : ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADCs.
00: PCLK2 divided by 2
01: PCLK2 divided by 4
10: PCLK2 divided by 6
11: PCLK2 divided by 8
Bits 13:11 PPRE2[2:0] : APB high-speed prescaler (APB2)
Set and cleared by software to control the division factor of the APB High speed clock (PCLK2).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Bits 10:8 PPRE1[2:0] : APB Low-speed prescaler (APB1)
Set and cleared by software to control the division factor of the APB Low speed clock (PCLK1).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Caution: Software must configure these bits ensure that the frequency in this domain does not exceed 36 MHz.
136/1136 RM0008 Rev 21
RM0008 Connectivity line devices: reset and clock control (RCC)
Bits 7:4 HPRE[3:0] : AHB prescaler
Set and cleared by software to control AHB clock division factor.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Note: The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock.
Refer to the section
for more details.
Caution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.
Bits 3:2 SWS[1:0] : System clock switch status
Set and cleared by hardware to indicate which clock source is used as system clock.
00: HSI oscillator used as system clock
01: HSE oscillator used as system clock
10: PLL used as system clock
11: Not applicable
Bits 1:0 SW[1:0] : System clock Switch
Set and cleared by software to select SYSCLK source.
Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is enabled).
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: Not allowed
8.3.3 Clock interrupt register (RCC_CIR)
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
15
Res.
30 29 28 27
Reserved
26 25 24
14
PLL3
RDYIE rw
13
PLL2
RDYIE rw
12
PLL
RDYIE rw
11
HSE
RDYIE rw
10
HSI
RDYIE rw
9
LSE
RDYIE rw
8
LSI
RDYIE rw
23
CSSC w
7
CSSF r
22
PLL3
RDYC w
6
PLL3
RDYF r
21
PLL2
RDYC w
5
PLL2
RDYF r
20
PLL
RDYC w
4
PLL
RDYF r
19
HSE
RDYC w
3
HSE
RDYF r
18
HSI
RDYC w
2
HSI
RDYF r
17
LSE
RDYC w
1
LSE
RDYF r
16
LSI
RDYC w
0
LSI
RDYF r
RM0008 Rev 21 137/1136
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Connectivity line devices: reset and clock control (RCC)
138/1136
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CSSC : Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Bit 22 PLL3RDYC : PLL3 Ready Interrupt Clear
This bit is set by software to clear the PLL3RDYF flag.
0: No effect
1: Clear PLL3RDYF flag
Bit 21 PLL2RDYC : PLL2 Ready Interrupt Clear
This bit is set by software to clear the PLL2RDYF flag.
0: No effect
1: Clear PLL2RDYF flag
Bit 20 PLLRDYC : PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag
Bit 19 HSERDYC : HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag
Bit 18 HSIRDYC : HSI ready interrupt clear
This bit is set by software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag
Bit 17 LSERDYC : LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: Clear LSERDYF flag
Bit 16 LSIRDYC : LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: Clear LSIRDYF flag
Bit 15 Reserved, must be kept at reset value.
Bit 14 PLL3RDYIE : PLL3 Ready Interrupt Enable
Set and cleared by software to enable/disable interrupt caused by PLL3 lock.
0: PLL3 lock interrupt disabled
1: PLL3 lock interrupt enabled
Bit 13 PLL2RDYIE : PLL2 Ready Interrupt Enable
Set and cleared by software to enable/disable interrupt caused by PLL2 lock.
0: PLL2 lock interrupt disabled
1: PLL2 lock interrupt enabled
Bit 12 PLLRDYIE : PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
RM0008 Rev 21
RM0008
RM0008 Connectivity line devices: reset and clock control (RCC)
Bit 11 HSERDYIE : HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the external 3-25 MHz oscillator stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Bit 10 HSIRDYIE : HSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC oscillator stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
Bit 9 LSERDYIE : LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Bit 8 LSIRDYIE : LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by internal RC 40 kHz oscillator stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
Bit 7 CSSF : Clock security system interrupt flag
Set by hardware when a failure is detected in the external 3-25 MHz oscillator. It is cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bit 6 PLL3RDYF : PLL3 Ready Interrupt flag
Set by hardware when the PLL3 locks and PLL3RDYIE is set. It is cleared by software setting the PLL3RDYC bit.
0: No clock ready interrupt caused by PLL3 lock
1: Clock ready interrupt caused by PLL3 lock
Bit 5 PLL2RDYF : PLL2 Ready Interrupt flag
Set by hardware when the PLL2 locks and PLL2RDYDIE is set. It is cleared by software setting the PLL2RDYC bit.
0: No clock ready interrupt caused by PLL2 lock
1: Clock ready interrupt caused by PLL2 lock
Bit 4 PLLRDYF : PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYDIE is set. It is cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Bit3 HSERDYF : HSE ready interrupt flag
Set by hardware when External High Speed clock becomes stable and HSERDYIE is set. It is cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the external 3-25 MHz oscillator
1: Clock ready interrupt caused by the external 3-25 MHz oscillator
RM0008 Rev 21 139/1136
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Connectivity line devices: reset and clock control (RCC) RM0008
Bit 2 HSIRDYF : HSI ready interrupt flag
Set by hardware when the Internal High Speed clock becomes stable and HSIRDYIE is set.
It is cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the internal 8 MHz RC oscillator
1: Clock ready interrupt caused by the internal 8 MHz RC oscillator
Bit 1 LSERDYF : LSE ready interrupt flag
Set by hardware when the External Low Speed clock becomes stable and LSERDYIE is set.
It is cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the external 32 kHz oscillator
1: Clock ready interrupt caused by the external 32 kHz oscillator
Bit 0 LSIRDYF : LSI ready interrupt flag
Set by hardware when Internal Low Speed clock becomes stable and LSIRDYIE is set. It is cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the internal RC 40 kHz oscillator
1: Clock ready interrupt caused by the internal RC 40 kHz oscillator
140/1136 RM0008 Rev 21
RM0008 Connectivity line devices: reset and clock control (RCC)
Address offset: 0x0C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28
15
Res.
14
USART1
RST rw
13
Res.
12
SPI1
RST rw
27 26 25 24 23
Reserved
8 7 11
TIM1
RST rw
10
ADC2
RST rw
9
ADC1
RST rw
Reserved
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 USART1RST : USART1 reset
Set and cleared by software.
0: No effect
1: Reset USART1
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST : SPI 1 reset
Set and cleared by software.
0: No effect
1: Reset SPI 1
Bit 11 TIM1RST : TIM1 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
Bit 10 ADC2RST : ADC 2 interface reset
Set and cleared by software.
0: No effect
1: Reset ADC 2 interface
Bit 9 ADC1RST : ADC 1 interface reset
Set and cleared by software.
0: No effect
1: Reset ADC 1 interface
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 IOPERST : I/O port E reset
Set and cleared by software.
0: No effect
1: Reset I:O port E
Bit 5 IOPDRST : I/O port D reset
Set and cleared by software.
0: No effect
1: Reset I/O port D
22 21 20 19 18
6
IOPE
RST rw
5
IOPD
RST rw
4
IOPC
RST rw
3
IOPB
RST rw
2
IOPA
RST rw
17 16
1
Res.
0
AFIO
RST rw
RM0008 Rev 21 141/1136
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Connectivity line devices: reset and clock control (RCC)
Bit 4 IOPCRST : IO port C reset
Set and cleared by software.
0: No effect
1: Reset I/O port C
Bit 3 IOPBRST : IO port B reset
Set and cleared by software.
0: No effect
1: Reset I/O port B
Bit 2 IOPARST : I/O port A reset
Set and cleared by software.
0: No effect
1: Reset I/O port A
Bit 1 Reserved, must be kept at reset value.
Bit 0 AFIORST : Alternate function I/O reset
Set and cleared by software.
0: No effect
1: Reset Alternate Function
RM0008
Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
15
SPI3
RST rw
31 30
Reserved
14
SPI2
RST rw
29
DAC
RST rw
13
Reserved
28
PWR
RST rw
12
27
BKP
RST rw
11
WWDG
RST rw
26
CAN2
RST rw
10
25
CAN1
RST rw
9
24
Reserved
8
Reserved
23
7
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACRST : DAC interface reset
Set and cleared by software.
0: No effect
1: Reset DAC interface
Bit 28 PWRRST : Power interface reset
Set and cleared by software.
0: No effect
1: Reset power interface
Bit 27 BKPRST : Backup interface reset
Set and cleared by software.
0: No effect
1: Reset backup interface
22
I2C2
RST rw
6
21
I2C1
RST rw
5
TIM7
RST rw
20
UART5
RST rw
4
TIM6
RST rw
19
UART4
RST rw
3
TIM5
RST rw
18
USART3
RST rw
2
TIM4
RST rw
17
USART2
RST rw
1
TIM3
RST rw
16
Res.
0
TIM2
RST rw
142/1136 RM0008 Rev 21
RM0008 Connectivity line devices: reset and clock control (RCC)
Bit 26 CAN2RST : CAN2 reset
Set and cleared by software.
0: No effect
1: Reset CAN2
Bit 25 CAN1RST : CAN1 reset
Set and cleared by software.
0: No effect
1: Reset CAN1
Bits 24:23 Reserved, must be kept at reset value.
Bit 22 I2C2RST : I2C 2 reset
Set and cleared by software.
0: No effect
1: Reset I2C 2
Bit 21 I2C1RST : I2C1 reset
Set and cleared by software.
0: No effect
1: Reset I2C 1
Bit 20 UART5RST : USART 5 reset
Set and cleared by software.
0: No effect
1: Reset USART 5
Bit 19 UART4RST : USART 4 reset
Set and cleared by software.
0: No effect
1: Reset USART 4
Bit 18 USART3RST : USART 3 reset
Set and cleared by software.
0: No effect
1: Reset USART 3
Bit 17 USART2RST : USART 2 reset
Set and cleared by software.
0: No effect
1: Reset USART 2
Bits 16 Reserved, must be kept at reset value.
Bit 15 SPI3RST : SPI3 reset
Set and cleared by software.
0: No effect
1: Reset SPI 3
Bit 14 SPI2RST : SPI2 reset
Set and cleared by software.
0: No effect
1: Reset SPI2
Bits 13:12 Reserved, must be kept at reset value.
RM0008 Rev 21 143/1136
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Connectivity line devices: reset and clock control (RCC)
Bit 11 WWDGRST : Window watchdog reset
Set and cleared by software.
0: No effect
1: Reset window watchdog
Bits 10:6 Reserved, must be kept at reset value.
Bit 5 TIM7RST : Timer 7 reset
Set and cleared by software.
0: No effect
1: Reset timer 7
Bit 4 TIM6RST : Timer 6 reset
Set and cleared by software.
0: No effect
1: Reset timer 6
Bit 3 TIM5RST : Timer 5 reset
Set and cleared by software.
0: No effect
1: Reset timer 5
Bit 2 TIM4RST : Timer 4 reset
Set and cleared by software.
0: No effect
1: Reset timer 4
Bit 1 TIM3RST : Timer 3 reset
Set and cleared by software.
0: No effect
1: Reset timer 3
Bit 0 TIM2RST : Timer 2 reset
Set and cleared by software.
0: No effect
1: Reset timer 2
RM0008
144/1136 RM0008 Rev 21
RM0008 Connectivity line devices: reset and clock control (RCC)
8.3.6 AHB Peripheral Clock enable register (RCC_AHBENR)
Address offset: 0x14
Reset value: 0x0000 0014
Access: no wait state, word, half-word and byte access
31 30 29 28 27
15 14
ETHMAC
TXEN
ETHMA
CEN rw rw
13
Res.
12
OTGFS
EN rw
11
26
10
25
9
Reserved
24
Reserved
8
23
7
22 21 20 19
6
CRCEN rw
5 4
Res.
FLITFEN rw
3
Res.
18
2
SRAM
EN rw
17
1
DMA2
EN rw
16
ETHMAC
RXEN rw
0
DMA1
EN rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 ETHMACRXEN : Ethernet MAC RX clock enable
Set and cleared by software.
0: Ethernet MAC RX clock disabled
1: Ethernet MAC RX clock enabled
Note: In the RMII mode, if this clock is enabled, the RMII clock of the MAC is also enabled.
Bit 15 ETHMACTXEN : Ethernet MAC TX clock enable
Set and cleared by software.
0: Ethernet MAC TX clock disabled
1: Ethernet MAC TX clock enabled
Note: In the RMII mode, if this clock is enabled, the RMII clock of the MAC is also enabled.
Bit 14 ETHMACEN : Ethernet MAC clock enable
Set and cleared by software. Selection of PHY interface (MII/RMII) must be done before enabling the MAC clock.
0: Ethernet MAC clock disabled
1: Ethernet MAC clock enabled
Bit 13 Reserved, must be kept at reset value.
Bit 12 OTGFSEN : USB OTG FS clock enable
Set and cleared by software.
0: USB OTG FS clock disabled
1: USB OTG FS clock enabled
Bits 11:7 Reserved, must be kept at reset value.
Bit 6 CRCEN : CRC clock enable
Set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Bit 5 Reserved, must be kept at reset value.
Bit 4 FLITFEN : FLITF clock enable
Set and cleared by software to disable/enable FLITF clock during sleep mode.
0: FLITF clock disabled during Sleep mode
1: FLITF clock enabled during Sleep mode
RM0008 Rev 21 145/1136
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Connectivity line devices: reset and clock control (RCC) RM0008
Bit 3 Reserved, must be kept at reset value.
Bit 2 SRAMEN : SRAM interface clock enable
Set and cleared by software to disable/enable SRAM interface clock during Sleep mode.
0: SRAM interface clock disabled during Sleep mode
1: SRAM interface clock enabled during Sleep mode
Bit 1 DMA2EN : DMA2 clock enable
Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Bit 0 DMA1EN : DMA1 clock enable
Set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
8.3.7 APB2 peripheral clock enable register (RCC_APB2ENR)
Address: 0x18
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in the APB2 domain is on going. In this case, wait states are inserted until the access to APB2 peripheral is finished.
31 30 29 28 27 26 25
12
SPI1
EN rw
11
TIM1
EN rw
10
ADC2
EN rw
9
ADC1
EN rw
24 23
Reserved
8 7 15
Res.
14
USART
1EN rw
13
Res.
Reserved
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 USART1EN : USART1 clock enable
Set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN : SPI 1 clock enable
Set and cleared by software.
0: SPI 1 clock disabled
1: SPI 1 clock enabled
Bit 11 TIM1EN : TIM1 Timer clock enable
Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1 timer clock enabled
22 21 20 19 18
6
IOPE
EN rw
5
IOPD
EN rw
4
IOPC
EN rw
3
IOPB
EN rw
2
IOPA
EN rw
17
1
Res.
16
0
AFIO
EN rw
146/1136 RM0008 Rev 21
RM0008 Connectivity line devices: reset and clock control (RCC)
Bit 10 ADC2EN : ADC 2 interface clock enable
Set and cleared by software.
0: ADC 2 interface clock disabled
1: ADC 2 interface clock enabled
Bit 9 ADC1EN : ADC 1 interface clock enable
Set and cleared by software.
0: ADC 1 interface disabled
1: ADC 1 interface clock enabled
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 IOPEEN : I/O port E clock enable
Set and cleared by software.
0: I/O port E clock disabled
1: I/O port E clock enabled
Bit 5 IOPDEN : I/O port D clock enable
Set and cleared by software.
0: I/O port D clock disabled
1: I/O port D clock enabled
Bit 4 IOPCEN : I/O port C clock enable
Set and cleared by software.
0: I/O port C clock disabled
1:I/O port C clock enabled
Bit 3 IOPBEN : I/O port B clock enable
Set and cleared by software.
0: I/O port B clock disabled
1:I/O port B clock enabled
Bit 2 IOPAEN : I/O port A clock enable
Set and cleared by software.
0: I/O port A clock disabled
1:I/O port A clock enabled
Bit 1 Reserved, must be kept at reset value.
Bit 0 AFIOEN : Alternate function I/O clock enable
Set and cleared by software.
0: Alternate Function I/O clock disabled
1:Alternate Function I/O clock enabled
RM0008 Rev 21 147/1136
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Connectivity line devices: reset and clock control (RCC) RM0008
8.3.8 APB1 peripheral clock enable register (RCC_APB1ENR)
Address: 0x1C
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going. In this case, wait states are inserted until this access to APB1 peripheral is finished.
15
SPI3
EN rw
31 30
Reserved
14
SPI2
EN rw
29
DAC
EN rw
13
Reserved
28
PWR
EN rw
12
27
BKP
EN rw
11
WWD
GEN rw
26
CAN2
EN rw
10
25
CAN1
EN rw
9
24
Reserved
8
Reserved
23
7
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACEN : DAC interface clock enable
Set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Bit 28 PWREN : Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Bit 27 BKPEN : Backup interface clock enable
Set and cleared by software.
0: Backup interface clock disabled
1: Backup interface clock enabled
Bit 26 CAN2EN : CAN2 clock enable
Set and cleared by software.
0: CAN2 clock disabled
1: CAN2 clock enabled
Bit 25 CAN1EN : CAN1 clock enable
Set and cleared by software.
0: CAN1 clock disabled
1: CAN1 clock enabled
Bits 24:23 Reserved, must be kept at reset value.
Bit 22 I2C2EN : I2C 2 clock enable
Set and cleared by software.
0: I2C 2 clock disabled
1: I2C 2 clock enabled
22
I2C2
EN rw
6
21
I2C1
EN rw
5
TIM7
EN rw
20
UART5E
N rw
4
TIM6
EN rw
19
UART4E
N rw
18 17
USART3
EN
USART2
EN rw rw
3
TIM5
EN rw
2
TIM4
EN rw
1
TIM3
EN rw
16
Res.
0
TIM2
EN rw
148/1136 RM0008 Rev 21
RM0008 Connectivity line devices: reset and clock control (RCC)
Bit 21 I2C1EN : I2C 1 clock enable
Set and cleared by software.
0: I2C 1 clock disabled
1: I2C 1 clock enabled
Bit 20 UART5EN : USART 5 clock enable
Set and cleared by software.
0: USART 5 clock disabled
1: USART 5 clock enabled
Bit 19 UART4EN : USART 4 clock enable
Set and cleared by software.
0: USART 4 clock disabled
1: USART 4 clock enabled
Bit 18 USART3EN : USART 3 clock enable
Set and cleared by software.
0: USART 3 clock disabled
1: USART 3 clock enabled
Bit 17 USART2EN : USART 2 clock enable
Set and cleared by software.
0: USART 2 clock disabled
1: USART 2 clock enabled
Bits 16 Reserved, must be kept at reset value.
Bit 15 SPI3EN : SPI 3 clock enable
Set and cleared by software.
0: SPI 3 clock disabled
1: SPI 3 clock enabled
Bit 14 SPI2EN : SPI 2 clock enable
Set and cleared by software.
0: SPI 2 clock disabled
1: SPI 2 clock enabled
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN : Window watchdog clock enable
Set and cleared by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bits 10:6 Reserved, must be kept at reset value.
Bit 5 TIM7EN : Timer 7 clock enable
Set and cleared by software.
0: Timer 7 clock disabled
1: Timer 7 clock enabled
Bit 4 TIM6EN : Timer 6 clock enable
Set and cleared by software.
0: Timer 6 clock disabled
1: Timer 6 clock enabled
RM0008 Rev 21 149/1136
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Connectivity line devices: reset and clock control (RCC)
Bit 3 TIM5EN : Timer 5 clock enable
Set and cleared by software.
0: Timer 5 clock disabled
1: Timer 5 clock enabled
Bit 2 TIM4EN : Timer 4 clock enable
Set and cleared by software.
0: Timer 4 clock disabled
1: Timer 4 clock enabled
Bit 1 TIM3EN : Timer 3 clock enable
Set and cleared by software.
0: Timer 3 clock disabled
1: Timer 3 clock enabled
Bit 0 TIM2EN : Timer 2 clock enable
Set and cleared by software.
0: Timer 2 clock disabled
1: Timer 2 clock enabled
RM0008
Note:
31
15
RTC
EN rw
Address: 0x20
Reset value: 0x0000 0000, reset by Backup domain Reset.
Access: 0 wait state 3, word, half-word and byte access
Wait states are inserted in the case of successive accesses to this register.
LSEON, LSEBYP, RTCSEL and RTCEN bits of the
Backup domain control register
are in the Backup domain. As a result, after Reset, these bits are write-
protected and the DBP bit in the Power control register (PWR_CR)
has to be set before
these can be modified. Refer to Section 6: Backup registers (BKP)
for further information.
These bits are only reset after a Backup domain Reset (see Section 8.1.3: Backup domain reset
). Any internal or external Reset will not have any effect on these bits.
30 29 28 27 26 22 21 20 19 18
14 13 12
Reserved
11 10
25 24
Reserved
23
9 8
RTCSEL[1:0] rw rw
7 6 5
Reserved
4 3 2
LSE
BYP rw
17
1
LSE
RDY r
16
BDRST rw
0
LSEON rw
150/1136 RM0008 Rev 21
RM0008 Connectivity line devices: reset and clock control (RCC)
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 BDRST : Backup domain software reset
Set and cleared by software.
0: Reset not activated
1: Resets the entire Backup domain
Bit 15 RTCEN : RTC clock enable
Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0] : RTC clock source selection
Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit can be used to reset the RTCSEL[1:0] bits.
00: No clock
01: LSE oscillator clock used as RTC clock
10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by 128 used as RTC clock
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 LSEBYP : External Low Speed oscillator bypass
Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY : External Low Speed oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low speed oscillator clock cycles
0: External 32 kHz oscillator not ready
1: External 32 kHz oscillator ready
Bit 0 LSEON : External Low Speed oscillator enable
Set and cleared by software.
0: External 32 kHz oscillator OFF
1: External 32 kHz oscillator ON
RM0008 Rev 21 151/1136
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Connectivity line devices: reset and clock control (RCC) RM0008
8.3.10 Control/status register (RCC_CSR)
Address: 0x24
Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only.
Access: 0 wait state 3, word, half-word and byte access
Wait states are inserted in the case of successive accesses to this register.
31
LPWR
RSTF rw
15
30
WWDG
RSTF rw
29
IWDG
RSTF rw
14 13
28
SFT
RSTF rw
12
27
POR
RSTF rw
11
26
PIN
RSTF rw
10
25
Res.
24
RMVF rw
8
23 22 21 20 19
Reserved
18 17 16
9
Reserved
7 6 5 4 3 2 1
LSI
RDY r
0
LSION rw
Bit 31 LPWRRSTF : Low-power reset flag
Set by hardware when a Low-power management reset occurs. It is cleared by writing to the
RMVF bit.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to
.
Bit 30 WWDGRSTF : Window watchdog reset flag
Set by hardware when a window watchdog reset occurs. It is cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF : Independent watchdog reset flag
Set by hardware when an independent watchdog reset from V
DD cleared by writing to the RMVF bit.
domain occurs. It is
0: No watchdog reset occurred
1: Watchdog reset occurred
Bit 28 SFTRSTF : Software reset flag
Set by hardware when a software reset occurs. It is cleared by writing to the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 PORRSTF : POR/PDR reset flag
Set by hardware when a POR/PDR reset occurs. It is cleared by writing to the RMVF bit.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred
Bit 26 PINRSTF : PIN reset flag
Set by hardware when a reset from the NRST pin occurs. It is cleared by writing to the
RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 Reserved, must be kept at reset value.
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RM0008 Connectivity line devices: reset and clock control (RCC)
Bit 24 RMVF : Remove reset flag
Set by software to clear the reset flags.
0: No effect
1: Clear the reset flags
Bits 23:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY : Internal low speed oscillator ready
Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.
After the LSION bit is cleared, LSIRDY goes low after 3 internal 40 kHz RC oscillator clock cycles.
0: Internal RC 40 kHz oscillator not ready
1: Internal RC 40 kHz oscillator ready
Bit 0 LSION : Internal low speed oscillator enable
Set and cleared by software.
0: Internal RC 40 kHz oscillator OFF
1: Internal RC 40 kHz oscillator ON
8.3.11 AHB peripheral clock reset register (RCC_AHBRSTR)
Address offset: 0x28
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 22 21 20
10 9
24
Reserved
8
23
7 6 5 4
19
3 15
Res.
14
ETHMAC
RST rw
13
Res.
12
OTGFSR
ST rw
11
Reserved
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 ETHMACRST Ethernet MAC reset
Set and cleared by software.
0: No effect
1: Reset ETHERNET MAC
Bit 13 Reserved, must be kept at reset value.
Bit 12 OTGFSRST USB OTG FS reset
Set and cleared by software.
0: No effect
1: Reset USB OTG FS
Bits 11:0 Reserved, must be kept at reset value.
18
2
17
1
16
0
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Connectivity line devices: reset and clock control (RCC) RM0008
31
15 rw
Address offset: 0x2C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
30 29
14 13
PLL3MUL[3:0] rw rw
28
12 rw
27
11 rw
26 25
Reserved
10 9
PLL2MUL[3:0] rw rw
24
8 rw
23
7 rw
22 21
6 5
PREDIV2[3:0] rw rw
20
4 rw
19
3 rw
18
I2S3SR
C
17
I2S2SR
C rw
2 rw
1
PREDIV1[3:0] rw rw
16
PREDIV
1SRC rw
0 rw
7
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 I2S3SRC : I2S3 clock source
Set and cleared by software to select I2S3 clock source. This bit must be valid before enabling I2S3 clock.
0: System clock (SYSCLK) selected as I2S3 clock entry
1: PLL3 VCO clock selected as I2S3 clock entry
Bit 17 I2S2SRC : I2S2 clock source
Set and cleared by software to select I2S2 clock source. This bit must be valid before enabling I2S2 clock.
0: System clock (SYSCLK) selected as I2S2 clock entry
1: PLL3 VCO clock selected as I2S2 clock entry
Bit 16 PREDIV1SRC : PREDIV1 entry clock source
Set and cleared by software to select PREDIV1 clock source. This bit can be written only when PLL is disabled.
0: HSE oscillator clock selected as PREDIV1 clock entry
1: PLL2 selected as PREDIV1 clock entry
Bits 15:12 PLL3MUL[3:0] : PLL3 Multiplication Factor
Set and cleared by software to control PLL3 multiplication factor. These bits can be written only when PLL3 is disabled.
00xx: Reserved
010x: Reserved
0110: PLL3 clock entry x 8
0111: PLL3 clock entry x 9
1000: PLL3 clock entry x 10
1001: PLL3 clock entry x 11
1010: PLL3 clock entry x 12
1011: PLL3 clock entry x 13
1100: PLL3 clock entry x 14
1101: Reserved
1110: PLL3 clock entry x 16
1111: PLL3 clock entry x 20
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RM0008 Connectivity line devices: reset and clock control (RCC)
Bits 11:8 PLL2MUL[3:0] : PLL2 Multiplication Factor
Set and cleared by software to control PLL2 multiplication factor. These bits can be written only when PLL2 is disabled.
00xx: Reserved
010x: Reserved
0110: PLL2 clock entry x 8
0111: PLL2 clock entry x 9
1000: PLL2 clock entry x 10
1001: PLL2 clock entry x 11
1010: PLL2 clock entry x 12
1011: PLL2 clock entry x 13
1100: PLL2 clock entry x 14
1101: Reserved
1110: PLL2 clock entry x 16
1111: PLL2 clock entry x 20
Bits 7:4 PREDIV2[3:0] : PREDIV2 division factor
Set and cleared by software to select PREDIV2 division factor. These bits can be written only when both PLL2 and PLL3 are disabled.
0000: PREDIV2 input clock not divided
0001: PREDIV2 input clock divided by 2
0010: PREDIV2 input clock divided by 3
0011: PREDIV2 input clock divided by 4
0100: PREDIV2 input clock divided by 5
0101: PREDIV2 input clock divided by 6
0110: PREDIV2 input clock divided by 7
0111: PREDIV2 input clock divided by 8
1000: PREDIV2 input clock divided by 9
1001: PREDIV2 input clock divided by 10
1010: PREDIV2 input clock divided by 11
1011: PREDIV2 input clock divided by 12
1100: PREDIV2 input clock divided by 13
1101: PREDIV2 input clock divided by 14
1110: PREDIV2 input clock divided by 15
1111: PREDIV2 input clock divided by 16
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Connectivity line devices: reset and clock control (RCC) RM0008
Bits 3:0 PREDIV1[3:0] : PREDIV1 division factor
Set and cleared by software to select PREDIV1 division factor. These bits can be written only when PLL is disabled.
Note: Bit(0) is the same as bit(17) in the RCC_CFGR register, so modifying bit(17) in the
RCC_CFGR register changes Bit(0) accordingly.
0000: PREDIV1 input clock not divided
0001: PREDIV1 input clock divided by 2
0010: PREDIV1 input clock divided by 3
0011: PREDIV1 input clock divided by 4
0100: PREDIV1 input clock divided by 5
0101: PREDIV1 input clock divided by 6
0110: PREDIV1 input clock divided by 7
0111: PREDIV1 input clock divided by 8
1000: PREDIV1 input clock divided by 9
1001: PREDIV1 input clock divided by 10
1010: PREDIV1 input clock divided by 11
1011: PREDIV1 input clock divided by 12
1100: PREDIV1 input clock divided by 13
1101: PREDIV1 input clock divided by 14
1110: PREDIV1 input clock divided by 15
1111: PREDIV1 input clock divided by 16
8.3.13 RCC register map
The following table gives the RCC register map and the reset values.
Table 19. RCC register map and reset values
Offset Register
0x000
0x004
RCC_CR
Reset value
RCC_CFGR
Reset value
Rese rved
0 0 0 0 0 0
Reserved
MCO [3:0]
0 0 0 0
HSICAL[7:0] HSITRIM[4:0]
Reserved
0 0 0 0 x x x x x x x x 1 0 0 0 0 1 1
PLLMUL
[3:0]
ADC
PRE
[1:0]
PPRE2
[2:0]
PPRE1
[2:0]
HPRE[3:0]
SWS
[1:0]
SW
[1:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x008
RCC_CIR
Reset value
Reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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RM0008
Offset Register
Connectivity line devices: reset and clock control (RCC)
Table 19. RCC register map and reset values (continued)
0x00C
RCC_APB2RSTR
Reset value
0x010
RCC_APB1RSTR Rese rved
Reset value
0 0 0 0 0
Reserved
0 0 0 0 0 0
0
0 0
0 0 0 0
0
Reserved
0 0 0 0 0 0
0 0 0 0 0 0
0x014
RCC_AHBENR
Reset value
0x018 RCC_APB2ENR
Reset value
Reserved
0x01C
RCC_APB1ENR Rese rved
Reset value
0 0 0 0 0
Reserved
0 0 0 0 0 0
0 0 0
0
0 0
0
0
Reserved
0 0 0 0
Reserved
0 1 1 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0x020
RCC_BDCR
Reset value
Reserved
0x024
RCC_CSR
Reset value
0 0 0 0 1 1 0
0x028
RCC_AHBSTR
Reset value
Reserved
0 0
0
Reserved
Reserved
0
0 0
Reserved
Reserved
0 0 0
0 0
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Connectivity line devices: reset and clock control (RCC)
Table 19. RCC register map and reset values (continued)
Offset Register
RM0008
0x02C
RCC_CFGR2
Reset value
Reserved
PLL3MUL
[3:0]
PLL2MUL
[3:0]
PREDIV2[3:
0]
PREDIV1[3:
0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
for the register boundary addresses.
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RM0008
9
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
General-purpose and alternate-function I/Os
(GPIOs and AFIOs)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to the whole STM32F10xxx family, unless otherwise specified.
9.1 GPIO functional description
Each of the general-purpose I/O ports has two 32-bit configuration registers (GPIOx_CRL,
GPIOx_CRH), two 32-bit data registers (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register
(GPIOx_LCKR).
Subject to the specific hardware characteristics of each I/O port listed in the datasheet , each port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software in several modes:
Input floating
Input pull-up
Input-pull-down
Analog
Output open-drain
Output push-pull
Alternate function push-pull
Alternate function open-drain
Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words (half-word or byte accesses are not allowed). The purpose of the
GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIO registers. This way, there is no risk that an IRQ occurs between the read and the modify access.
shows the basic structure of an I/O Port bit.
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General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Figure 13. Basic structure of a standard I/O port bit
RM0008
To on-chip peripheral
Analog Input
Alternate Function Input on/off
Read
Write
Read/write
From on-chip peripheral Alternate Function Output
TTL Schmitt
trigger
Input driver
Output driver
Output control on/off
V
DD on/off
V
SS
V
DD
P-MOS
V
SS
N-MOS
Push-pull, open-drain or disabled
V
DD
Protection diode
I/O pin
V
SS
Protection diode ai14781
Figure 14. Basic structure of a 5-Volt tolerant I/O port bit
To on-chip peripheral
Analog Input
Alternate Function Input on/off
Read
Write
Read/write
From on-chip peripheral
Alternate Function Output
TTL Schmitt
trigger
Input driver
Output driver
Output control on/off
V
DD on/off
V
SS
V
DD
P-MOS
V
SS
N-MOS
Push-pull, open-drain or disabled
V
DD_FT
(1)
I/O pin
V
SS
Protection diode ai14782
1. V
DD_FT
is a potential specific to 5-Volt tolerant I/Os, and different from V
DD
.
160/1136 RM0008 Rev 21
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Configuration mode
General purpose output
Alternate Function output
Input
Table 20. Port bit configuration table
Push-pull
Open-drain
Push-pull
Open-drain
Analog
Input floating
Input pull-down
Input pull-up
CNF1 CNF0 MODE1 MODE0
0
1
0
1
0
1
0
1
0
1
0
01
10
11
00
PxODR register
0 or 1
0 or 1
Don’t care
Don’t care
Don’t care
Don’t care
0
1
MODE[1:0]
00
01
10
11
Table 21. Output MODE bits
Meaning
Reserved
Maximum output speed 10 MHz
Maximum output speed 2 MHz
Maximum output speed 50 MHz
9.1.2
During and just after reset, the alternate functions are not active and the I/O ports are configured in Input Floating mode (CNFx[1:0]=01b, MODEx[1:0]=00b).
The JTAG pins are in input PU/PD after reset:
PA15: JTDI in PU
PA14: JTCK in PD
PA13: JTMS in PU
PB4: NJTRST in PU
When configured as output, the value written to the Output Data register (GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in Push-Pull mode or Open-Drain mode (only the N-MOS is activated when outputting 0).
The Input Data register (GPIOx_IDR) captures the data present on the I/O pin at every
APB2 clock cycle.
All GPIO pins have an internal weak pull-up and weak pull-down that can be activated or not when configured as input.
Atomic bit set or reset
There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is possible to modify only one or several bits in a single atomic APB2 write access. This is achieved by programming to ‘1’ the Bit Set/Reset register (GPIOx_BSRR, or
RM0008 Rev 21 161/1136
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General-purpose and alternate-function I/Os (GPIOs and AFIOs)
9.1.3
9.1.4
Note:
9.1.5
RM0008 for reset only GPIOx_BRR) to select the bits to modify. The unselected bits will not be modified.
External interrupt/wakeup lines
All ports have external interrupt capability. To use external interrupt lines, the port must be
configured in input mode. For more information on external interrupts, refer to Section 10.2:
External interrupt/event controller (EXTI)
and
Section 10.2.3: Wakeup event management .
Alternate functions (AF)
It is necessary to program the Port Bit Configuration register before using a default alternate function.
For alternate function inputs, the port must be configured in Input mode (floating, pullup or pull-down) and the input pin must be driven externally.
It is also possible to emulate the AFI input pin by software by programming the GPIO controller. In this case, the port should be configured in Alternate Function Output mode.
And obviously, the corresponding port should not be driven externally as it will be driven by the software using the GPIO controller.
For alternate function outputs, the port must be configured in Alternate Function Output mode (Push-Pull or Open-Drain).
For bidirectional Alternate Functions, the port bit must be configured in Alternate
Function Output mode (Push-Pull or Open-Drain). In this case the input driver is configured in input floating mode
If a port bit is configured as Alternate Function Output, this disconnects the output register and connects the pin to the output signal of an on-chip peripheral.
If software configures a GPIO pin as Alternate Function Output, but peripheral is not activated, its output is not specified.
Software remapping of I/O alternate functions
To optimize the number of peripheral I/O functions for different device packages, it is possible to remap some alternate functions to some other pins. This is achieved by software, by programming the corresponding registers (refer to
. In that case, the alternate functions are no longer mapped to their original assignations.
The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence has been applied on a port bit, it is no longer possible to modify the value of the port bit until the next reset.
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RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
When the I/O Port is programmed as Input:
The Output Buffer is disabled
The Schmitt Trigger Input is activated
The weak pull-up and pull-down resistors are activated or not depending on input configuration (pull-up, pull-down or floating):
The data present on the I/O pin is sampled into the Input Data register every APB2 clock cycle
A read access to the Input Data register obtains the I/O State.
shows the Input Configuration of the I/O Port bit.
Figure 15. Input floating/pull up/pull down configurations on/off
V
DD on
Read
Write
TTL Schmitt
trigger
V
DD
or V
DD_FT
(1) protection diode
I/O pin input driver output driver on/off
V
SS
V
SS protection diode
Read/write ai14783
1. V
DD_FT
is a potential specific to 5-Volt tolerant I/Os, and different from V
DD
.
When the I/O Port is programmed as Output:
The Output Buffer is enabled:
– Open Drain Mode: A “0” in the Output register activates the N-MOS while a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated)
– Push-Pull Mode: A “0” in the Output register activates the N-MOS while a “1” in the
Output register activates the P-MOS
The Schmitt Trigger Input is activated.
The weak pull-up and pull-down resistors are disabled.
The data present on the I/O pin is sampled into the Input Data register every APB2 clock cycle
A read access to the Input Data register gets the I/O state in open drain mode
A read access to the Output Data register gets the last written value in Push-Pull mode
shows the Output configuration of the I/O Port bit.
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General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Figure 16. Output configuration
9.1.9
RM0008 on
Read
V
DD
or V
DD_FT
(1)
Write
Input driver
TTL Schmitt
trigger Protection diode
I/O pin
Output driver V
DD
Protection diode
P-MOS
Output control
V
SS
Read/write
V
SS
N-MOS
Push-pull or
Open-drain ai14784
1. V
DD_FT
is a potential specific to 5-Volt tolerant I/Os, and different from V
DD
.
Alternate function configuration
When the I/O Port is programmed as Alternate Function:
The Output Buffer is turned on in Open Drain or Push-Pull configuration
The Output Buffer is driven by the signal coming from the peripheral (alternate function out)
The Schmitt Trigger Input is activated
The weak pull-up and pull-down resistors are disabled.
The data present on the I/O pin is sampled into the Input Data register every APB2 clock cycle
A read access to the Input Data register gets the I/O state in open drain mode
A read access to the Output Data register gets the last written value in Push-Pull mode
shows the Alternate Function Configuration of the I/O Port bit. Also, refer to
for further information.
A set of Alternate Function I/O registers allows the user to remap some alternate functions
to different pins. Refer to Section 9.3: Alternate function I/O and debug configuration (AFIO) .
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RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Figure 17. Alternate function configuration
To on-chip peripheral
Alternate Function Input
Read on
Write
Read/write
From on-chip peripheral
Alternate Function Output
TTL Schmitt
trigger
Input driver
Output driver
Output control
1. V
DD_FT
is a potential specific to 5-Volt tolerant I/Os, and different from V
DD
.
V
DD
P-MOS
V
SS
N-MOS push-pull or open-drain
V
DD
or V
DD_FT
(1)
Protection diode
I/O pin
VSS
Protection diode ai14785
When the I/O Port is programmed as Analog configuration:
The Output Buffer is disabled.
The Schmitt Trigger Input is de-activated providing zero consumption for every analog value of the I/O pin. The output of the Schmitt Trigger is forced to a constant value (0).
The weak pull-up and pull-down resistors are disabled.
Read access to the Input Data register gets the value “0”.
shows the high impedance-analog configuration of the I/O Port bit.
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General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Figure 18. High impedance-analog configuration
To on-chip peripheral
Read
Analog Input
Write
Input driver off
0
TTL Schmitt
trigger
RM0008
V
DD
or V
DD_FT
(1)
Protection diode
I/O pin
V
SS
Protection diode
Read/write
From on-chip peripheral ai14786
Table 33 give the GPIO configurations of the device peripherals.
TIM1/8 pinout
TIM1/8_CHx
TIM1/8_CHxN
TIM1/8_BKIN
TIM1/8_ETR
Table 22. Advanced timers TIM1 and TIM8
Configuration GPIO configuration
Input capture channel x Input floating
Output compare channel x Alternate function push-pull
Complementary output channel x Alternate function push-pull
Break input
External trigger timer input
Input floating
Input floating
TIM2/3/4/5 pinout
Table 23. General-purpose timers TIM2/3/4/5
Configuration GPIO configuration
TIM2/3/4/5_CHx
TIM2/3/4/5_ETR
Input capture channel x
Output compare channel x
External trigger timer input
Input floating
Alternate function push-pull
Input floating
USART pinout
USARTx_TX
(1)
Table 24. USARTs
Configuration
Full duplex
Half duplex synchronous mode
GPIO configuration
Alternate function push-pull
Alternate function push-pull
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RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
USART pinout
Table 24. USARTs (continued)
Configuration GPIO configuration
USARTx_RX
USARTx_CK
USARTx_RTS
USARTx_CTS
Full duplex
Half duplex synchronous mode
Synchronous mode
Hardware flow control
Hardware flow control
Input floating / Input pull-up
Not used. Can be used as a general IO
Alternate function push-pull
Alternate function push-pull
Input floating/ Input pull-up
1. The USART_TX pin can also be configured as alternate function open drain.
Table 25. SPI
SPI pinout Configuration GPIO configuration
SPIx_SCK
SPIx_MOSI
SPIx_MISO
SPIx_NSS
Master
Slave
Full duplex / master
Full duplex / slave
Alternate function push-pull
Input floating
Alternate function push-pull
Input floating / Input pull-up
Simplex bidirectional data wire / master Alternate function push-pull
Simplex bidirectional data wire/ slave Not used. Can be used as a GPIO
Full duplex / master
Full duplex / slave (point to point)
Input floating / Input pull-up
Alternate function push-pull
Full duplex / slave (multi-slave) Alternate function open drain
Simplex bidirectional data wire / master Not used. Can be used as a GPIO
Simplex bidirectional data wire/ slave
(point to point)
Simplex bidirectional data wire/ slave
(multi-slave)
Alternate function push-pull
Alternate function open drain
Hardware master /slave Input floating/ Input pull-up / Input pull-down
Hardware master/ NSS output enabled Alternate function push-pull
Software Not used. Can be used as a GPIO
I2S pinout
I2Sx_ WS
I2Sx_CK
I2Sx_SD
Master
Slave
Master
Slave
Transmitter
Receiver
Configuration
Table 26. I2S
GPIO configuration
Alternate function push-pull
Input floating
Alternate function push-pull
Input floating
Alternate function push-pull
Input floating/ Input pull-up/ Input pull-down
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General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Table 26. I2S (continued)
Configuration GPIO configuration I2S pinout
I2Sx_MCK
Slave Not used. Can be used as a GPIO
RM0008
I2C pinout
I2Cx_SCL
I2Cx_SDA
Table 27. I2C
Configuration
I2C clock
I2C Data I/O
GPIO configuration
Alternate function open drain
Alternate function open drain
BxCAN pinout
CAN_TX (Transmit data line)
CAN_RX (Receive data line)
Table 28. bxCAN
GPIO configuration
Alternate function push-pull
Input floating / Input pull-up
USB pinout
Table 29. USB (1)
GPIO configuration
USB_DM / USB_DP
As soon as the USB is enabled, these pins are automatically connected to the USB internal transceiver.
1. This table applies to low-, medium-, high and XL-density devices only.
Table 30. OTG_FS pin configuration
(1)
OTG_FS pinout Configuration GPIO configuration
OTG_FS_SOF
OTG_FS_VBUS
(2)
OTG_FS_ID
OTG_FS_DM
Host
Device
OTG
Host
Device
OTG
Host
Device
OTG
Host
Device
OTG
AF push-pull, if used
AF push-pull, if used
AF push-pull, if used
Input floating
Input floating
Input floating
No need if the Force host mode is selected by software
(FHMOD set in the OTG_FS_GUSBCFG register)
No need if the Force device mode is selected by software
(FDMOD set in the OTG_FS_GUSBCFG register)
Input pull-up
Controlled automatically by the USB power-down
Controlled automatically by the USB power-down
Controlled automatically by the USB power-down
168/1136 RM0008 Rev 21
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Table 30. OTG_FS pin configuration (1) (continued)
OTG_FS pinout Configuration GPIO configuration
OTG_FS_DP
Host
Device
OTG
Controlled automatically by the USB power-down
Controlled automatically by the USB power-down
Controlled automatically by the USB power-down
1. This table applies to connectivity line devices only.
2. For the OTG_FS_VBUS pin (PA9) to be used by another shared peripheral or as a general-purpose IO, the
PHY Power-down mode has to be active (clear bit 16 in the OTG_FS_GCCFG register).
SDIO_CK
SDIO_CMD
SDIO[D7:D0]
SDIO pinout
Table 31. SDIO
GPIO configuration
Alternate function push-pull
Alternate function push-pull
Alternate function push-pull
The GPIO configuration of the ADC inputs should be analog.
Figure 19. ADC / DAC
ADC/DAC pin GPIO configuration
ADC/DAC Analog
FSMC pinout
FSMC_A[25:0]
FSMC_D[15:0]
FSMC_CK
FSMC_NOE
FSMC_NWE
FSMC_NE[4:1]
FSMC_NCE[3:2]
FSMC_NCE4_1
FSMC_NCE4_2
FSMC_NWAIT
FSMC_CD
FSMC_NIOS16,
FSMC_INTR
FSMC_INT[3:2]
FSMC_NL
FSMC_NBL[1:0]
FSMC_NIORD, FSMC_NIOWR
FSMC_NREG
Table 32. FSMC
GPIO configuration
Alternate function push-pull
Alternate function push-pull
Alternate function push-pull
Alternate function push-pull
Input floating/ Input pull-up
Input floating
Alternate function push-pull
Alternate function push-pull
RM0008 Rev 21 169/1136
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General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Pins
TAMPER-RTC pin
MCO
EXTI input lines
RM0008
Table 33. Other IOs
Alternate function
RTC output
Tamper event input
Clock output
External input interrupts
GPIO configuration
Forced by hardware when configuring the
BKP_CR and BKP_RTCCR registers
Alternate function push-pull
Input floating / input pull-up / input pull-down
170/1136 RM0008 Rev 21
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).
Address offset: 0x00
Reset value: 0x4444 4444
31 30
CNF7[1:0] rw rw
15 14
CNF3[1:0] rw rw
29 28
MODE7[1:0] rw rw
13 12
MODE3[1:0] rw rw
27 26
CNF6[1:0] rw rw
11 10
CNF2[1:0] rw rw
25 24
MODE6[1:0] rw rw
9 8
MODE2[1:0] rw rw
23 22
CNF5[1:0] rw rw
7 6
CNF1[1:0] rw rw
21 20
MODE5[1:0] rw rw
5 4
MODE1[1:0] rw rw
19 18
CNF4[1:0] rw rw
3 2
CNF0[1:0] rw rw
Bits 31:30, 27:26,
23:22, 19:18, 15:14,
11:10, 7:6, 3:2
CNFy[1:0]: Port x configuration bits (y= 0 .. 7)
These bits are written by software to configure the corresponding I/O port.
Refer to
Table 20: Port bit configuration table .
In input mode (MODE[1:0]=00) :
00: Analog mode
01: Floating input (reset state)
10: Input with pull-up / pull-down
11: Reserved
In output mode (MODE[1:0]
>
00) :
00: General purpose output push-pull
01: General purpose output Open-drain
10: Alternate function output Push-pull
11: Alternate function output Open-drain
Bits 29:28, 25:24,
21:20, 17:16, 13:12,
9:8, 5:4, 1:0
MODEy[1:0]: Port x mode bits (y= 0 .. 7)
These bits are written by software to configure the corresponding I/O port.
Refer to
Table 20: Port bit configuration table .
00: Input mode (reset state)
01: Output mode, max speed 10 MHz.
10: Output mode, max speed 2 MHz.
11: Output mode, max speed 50 MHz.
17 16
MODE4[1:0] rw rw
1 0
MODE0[1:0] rw rw
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General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
Address offset: 0x04
Reset value: 0x4444 4444
31 30
CNF15[1:0] rw
15 rw
14
CNF11[1:0] rw rw
29 28
MODE15[1:0] rw
13 rw
12
MODE11[1:0] rw rw
27 26
CNF14[1:0] rw
11 rw
10
CNF10[1:0] rw rw
25 24
MODE14[1:0] rw
9 rw
8
MODE10[1:0] rw rw
23 22
CNF13[1:0] rw
7 rw
6
CNF9[1:0] rw rw
21 20
MODE13[1:0] rw
5 rw
4
MODE9[1:0] rw rw
19 18
CNF12[1:0] rw
3 rw
2
CNF8[1:0] rw rw
Bits 31:30, 27:26,
23:22, 19:18, 15:14,
11:10, 7:6, 3:2
CNFy[1:0]: Port x configuration bits (y= 8 .. 15)
These bits are written by software to configure the corresponding I/O port.
Refer to Table 20: Port bit configuration table .
In input mode (MODE[1:0]=00) :
00: Analog mode
01: Floating input (reset state)
10: Input with pull-up / pull-down
11: Reserved
In output mode (MODE[1:0]
>
00) :
00: General purpose output push-pull
01: General purpose output Open-drain
10: Alternate function output Push-pull
11: Alternate function output Open-drain
Bits 29:28, 25:24,
21:20, 17:16, 13:12,
9:8, 5:4, 1:0
MODEy[1:0]: Port x mode bits (y= 8 .. 15)
These bits are written by software to configure the corresponding I/O port.
Refer to Table 20: Port bit configuration table .
00: Input mode (reset state)
01: Output mode, max speed 10 MHz.
10: Output mode, max speed 2 MHz.
11: Output mode, max speed 50 MHz.
17 16
MODE12[1:0] rw
1 rw
0
MODE8[1:0] rw rw
9.2.3 Port input data register (GPIOx_IDR) (x=A..G)
Address offset: 0x08h
Reset value: 0x0000 XXXX
31 30 29 28 27 26 25
15 14 13 12 11 10 9
IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9 r r r r r r r
24 23
8
Reserved
7
IDR8 r
IDR7 r
22
6
IDR6 r
21
5
IDR5 r
20
4
IDR4 r
19
3
IDR3 r
18
2
IDR2 r
17
1
IDR1 r
16
0
IDR0 r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 IDRy: Port input data (y= 0 .. 15)
These bits are read only and can be accessed in Word mode only. They contain the input value of the corresponding I/O port.
172/1136 RM0008 Rev 21
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
9.2.4 Port output data register (GPIOx_ODR) (x=A..G)
Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ODRy: Port output data (y= 0 .. 15)
These bits can be read and written by software and can be accessed in Word mode only.
Note: For atomic bit set/reset, the ODR bits can be individually set and cleared by writing to the GPIOx_BSRR register (x = A .. G).
Address offset: 0x10
Reset value: 0x0000 0000
31
BR15 w
15
BS15 w
30
BR14 w
29
BR13 w
14
BS14 w
13
BS13 w
28
BR12 w
12
BS12 w
27
BR11 w
11
BS11 w
26
BR10 w
10
BS10 w
25
BR9 w
9
BS9 w
24
BR8 w
8
BS8 w
23
BR7 w
7
BS7 w
22
BR6 w
6
BS6 w
21
BR5 w
5
BS5 w
20
BR4 w
4
BS4 w
Bits 31:16 BRy: Port x Reset bit y (y= 0 .. 15)
These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BSy: Port x Set bit y (y= 0 .. 15)
These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Set the corresponding ODRx bit
19
BR3 w
3
BS3 w
18
BR2 w
2
BS2 w
17
BR1 w
1
BS1 w
16
BR0 w
0
BS0 w
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General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
9.2.6 Port bit reset register (GPIOx_BRR) (x=A..G)
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29 28 27
15
BR15 w
14
BR14 w
13
BR13 w
12
BR12 w
11
BR11 w
26
10
BR10 w
25
9
BR9 w
24
Reserved
23
8
BR8 w
7
BR7 w
22
6
BR6 w
21
5
BR5 w
20
4
BR4 w
19
Bits 31:16 Reserved
Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15)
These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit
3
BR3 w
18 17 16
2
BR2 w
1
BR1 w
0
BR0 w
9.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G)
This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit it is no longer possible to modify the value of the port bit until the next reset.
Each lock bit freezes the corresponding 4 bits of the control register (CRL, CRH).
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
LCKK rw
0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
174/1136 RM0008 Rev 21
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Bits 31:17 Reserved
Bit 16 LCKK[16]: Lock key
This bit can be read anytime. It can only be modified using the Lock Key Writing Sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. GPIOx_LCKR register is locked until the next reset.
LOCK key writing sequence:
Write 1
Write 0
Write 1
Read 0
Read 1 (this read is optional but confirms that the lock is active)
Note: During the LOCK Key Writing sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence will abort the lock.
Bits 15:0 LCKy: Port x Lock bit y (y= 0 .. 15)
These bits are read write but can only be written when the LCKK bit is 0.
0: Port configuration not locked
1: Port configuration locked.
9.3 Alternate function I/O and debug configuration (AFIO)
To optimize the number of peripherals available for the 64-pin or the 100-pin or the 144-pin package, it is possible to remap some alternate functions to some other pins. This is achieved by software, by programming the
AF remap and debug I/O configuration register
(AFIO_MAPR) . In this case, the alternate functions are no longer mapped to their original
assignations.
Note:
The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose I/O
PC14 and PC15, respectively, when the LSE oscillator is off. The LSE has priority over the
GP IOs function.
The PC14/PC15 GPIO functionality is lost when the 1.8 V domain is powered off (by entering standby mode) or when the backup domain is supplied by V supplied). In this case the IOs are set in analog mode.
BAT
(V
DD
no more
Refer to the note on IO usage restrictions in Section 5.1.2: Battery backup domain
.
Note:
The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose I/O PD0/PD1 by programming the PD01_REMAP bit in the
AF remap and debug I/O configuration register
This remap is available only on 36-, 48- and 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping).
The external interrupt/event function is not remapped. PD0 and PD1 cannot be used for external interrupt/event generation on 36-, 48- and 64-pin packages.
RM0008 Rev 21 175/1136
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General-purpose and alternate-function I/Os (GPIOs and AFIOs)
9.3.3
9.3.4
CAN1 alternate function remapping
RM0008
The CAN signals can be mapped on Port A, Port B or Port D as shown in
. For port
D, remapping is not possible in devices delivered in 36-, 48- and 64-pin packages.
Alternate function
(1)
Table 34. CAN1 alternate function remapping
CAN_REMAP[1:0] =
“00”
CAN_REMAP[1:0] =
“10”
(2)
CAN_REMAP[1:0] =
“11”
(3)
CAN1_RX or CAN_RX
CAN1_TX or CAN_RX
PA11
PA12
PB8
PB9
PD0
PD1
1. CAN1_RX and CAN1_TX in connectivity line devices; CAN_RX and CAN_TX in other devices with a single
CAN interface.
2. Remap not available on 36-pin package
3. This remapping is available only on 100-pin and 144-pin packages, when PD0 and PD1 are not remapped on OSC-IN and OSC-OUT.
CAN2 alternate function remapping
CAN2 is available in connectivity line devices. The external signal can be remapped as
.
Table 35. CAN2 alternate function remapping
Alternate function CAN2_REMAP = “0” CAN2_REMAP = “1”
CAN2_RX
CAN2_TX
PB12
PB13
PB5
PB6
9.3.5 JTAG/SWD alternate function remapping
The debug interface signals are mapped on the GPIO ports as shown in
Alternate function
Table 36. Debug interface signals
GPIO port
JTMS / SWDIO
JTCK / SWCLK
JTDI
PA13
PA14
PA15
JTDO / TRACESWO PB3
NJTRST PB4
TRACECK PE2
TRACED0
TRACED1
TRACED2
TRACED3
PE3
PE4
PE5
PE6
176/1136 RM0008 Rev 21
RM0008
9.3.6
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
To optimize the number of free GPIOs during debugging, this mapping can be configured in
SWJ _CFG
[2:0]
Table 37. Debug port mapping
SWJ I/O pin assigned
Available debug ports PA13 /
JTMS/
SWDIO
PA14 /
JTCK/S
WCLK
PA15 /
JTDI
PB3 / JTDO/
TRACE
SWO
PB4/
NJTRST
000
001
010
100
Other
Full SWJ (JTAG-DP + SW-DP)
(Reset state)
Full SWJ (JTAG-DP + SW-DP) but without NJTRST
JTAG-DP Disabled and
SW-DP Enabled
JTAG-DP Disabled and
SW-DP Disabled
Forbidden
1. Released only if not using asynchronous trace.
X
X
X
Free
-
X
X
X
Free
-
X
X
Free
Free
-
X x
Free
(1)
Free
-
X
Free
Free
Free
-
ADC alternate function remapping
Refer to AF remap and debug I/O configuration register (AFIO_MAPR)
.
Table 38. ADC1 external trigger injected conversion alternate function remapping (1)
Alternate function ADC1_ETRGINJ_REMAP = 0 ADC1_ETRGINJ_REMAP = 1
ADC1 external trigger injected conversion
ADC1 external trigger injected conversion is connected to EXTI15
ADC1 external trigger injected conversion is connected to
TIM8_CH4
1. Remap available only for high-density and XL-density devices.
Table 39. ADC1 external trigger regular conversion alternate function remapping (1)
Alternate function ADC1_ETRGREG_REMAP = 0 ADC1_ETRGREG_REMAP = 1
ADC1 external trigger regular conversion
ADC1 external trigger regular conversion is connected to EXTI11
ADC1 external trigger regular conversion is connected to
TIM8_TRGO
1. Remap available only for high-density and XL-density devices.
Table 40. ADC2 external trigger injected conversion alternate function remapping (1)
Alternate function ADC2_ETRGINJ_REMAP = 0 ADC2_ETRGINJ_REMAP = 1
ADC2 external trigger injected conversion
ADC2 external trigger injected conversion is connected to EXTI 15
ADC2 external trigger injected conversion is connected to
TIM8_CH4
1. Remap available only for high-density and XL-density devices.
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General-purpose and alternate-function I/Os (GPIOs and AFIOs)
9.3.7
RM0008
Table 41. ADC2 external trigger regular conversion alternate function remapping (1)
Alternate function ADC2_ETRGREG_REG = 0 ADC2_ETRGREG_REG = 1
ADC2 external trigger regular conversion
ADC2 external trigger regular conversion is connected to
EXTI11
1. Remap available only for high-density and XL-density devices.
ADC2 external trigger regular conversion is connected to
TIM8_TRGO
Timer alternate function remapping
Timer 4 channels 1 to 4 can be remapped from Port B to Port D. Other timer remapping possibilities are listed in
. Refer to AF remap and debug I/O configuration register (AFIO_MAPR) .
Alternate function
Table 42. TIM5 alternate function remapping
(1)
TIM5CH4_IREMAP = 0 TIM5CH4_IREMAP = 1
TIM5_CH4
TIM5 Channel4 is connected to PA3
LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
1. Remap available only for high-density, XL-density and connectivity line devices.
Table 43. TIM4 alternate function remapping
Alternate function TIM4_REMAP = 0 TIM4_REMAP = 1 (1)
TIM4_CH1
TIM4_CH2
PB6
PB7
TIM4_CH3
TIM4_CH4
PB8
PB9
1. Remap available only for 100-pin and for 144-pin package.
PD12
PD13
PD14
PD15
Table 44. TIM3 alternate function remapping
Alternate function
TIM3_REMAP[1:0] =
“00” (no remap)
TIM3_REMAP[1:0] =
“10” (partial remap)
TIM3_REMAP[1:0] =
“11” (full remap) (1)
TIM3_CH1
TIM3_CH2
PA6
PA7
TIM3_CH3
TIM3_CH4
PB0
PB1
1. Remap available only for 64-pin, 100-pin and 144-pin packages.
PB4
PB5
PC6
PC7
PC8
PC9
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RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Alternate function
Table 45. TIM2 alternate function remapping
TIM2_REMAP
[1:0] = “00”
(no remap)
TIM2_REMAP
[1:0] = “01”
(partial remap)
TIM2_REMAP
[1:0] = “10”
(partial remap) (1)
TIM2_REMAP
[1:0] = “11”
(full remap) (1)
TIM2_CH1_ETR
(2)
TIM2_CH2
TIM2_CH3
TIM2_CH4
PA0
PA1
PA2
PA3
PA15
PB3
PA0
PA1
PB10
PB11
PA15
PB3
1. Remap not available on 36-pin package.
2. TIM_CH1 and TIM_ETR share the same pin but cannot be used at the same time (which is why we have this notation: TIM2_CH1_ETR).
Table 46. TIM1 alternate function remapping
Alternate functions mapping
TIM1_REMAP[1:0] =
“00” (no remap)
TIM1_REMAP[1:0] =
“01” (partial remap)
TIM1_REMAP[1:0] =
“11” (full remap)
(1)
TIM1_ETR
TIM1_CH1
PA12
PA8
TIM1_CH2
TIM1_CH3
TIM1_CH4
TIM1_BKIN
TIM1_CH1N
TIM1_CH2N
TIM1_CH3N
PB12
(2)
PB13
PB14
2)
PB15
(2)
1. Remap available only for 100-pin and 144-pin packages.
2. Remap not available on 36-pin package.
PA9
PA10
PA11
PA6
PA7
PB0
PB1
PE7
PE9
PE11
PE13
PE14
PE15
PE8
PE10
PE12
Alternate function
Table 47. TIM9 remapping (1)
TIM9_REMAP = 0 TIM9_REMAP = 1
TIM9_CH1
TIM9_CH2
PA2
PA3
PE5
PE6
.
Alternate function
Table 48. TIM10 remapping
(1)
TIM10_REMAP = 0 TIM10_REMAP = 1
TIM10_CH1 PB8 PF6
.
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General-purpose and alternate-function I/Os (GPIOs and AFIOs)
9.3.8
RM0008
Alternate function
Table 49. TIM11 remapping (1)
TIM11_REMAP = 0 TIM11_REMAP = 1
TIM11_CH1 PB9 PF7
.
Alternate function
Table 50. TIM13 remapping (1)
TIM13_REMAP = 0 TIM13_REMAP = 1
TIM13_CH1 PA6 PF8
1. Refer to the AF remap and debug I/O configuration register
Section 9.4.7: AF remap and debug I/O configuration register2 (AFIO_MAPR2)
.
Alternate function
Table 51. TIM14 remapping (1)
TIM14_REMAP = 0 TIM14_REMAP = 1
TIM14_CH1 PA7 PF9
.
USART alternate function remapping
Refer to AF remap and debug I/O configuration register (AFIO_MAPR)
.
Alternate function
Table 52. USART3 remapping
USART3_REMAP[1:0]
= “00” (no remap)
USART3_REMAP[1:0] =
“01” (partial remap) (1)
USART3_REMAP[1:0]
= “11” (full remap) (2)
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
USART3_RTS
PB10
PB11
PB12
PB13
PB14
1. Remap available only for 64-pin, 100-pin and 144-pin packages
2. Remap available only for 100-pin and 144-pin packages.
PC10
PC11
PC12
PD8
PD9
PD10
PD11
PD12
Alternate functions
Table 53. USART2 remapping
USART2_REMAP = 0
USART2_CTS
USART2_RTS
USART2_TX
USART2_RX
USART2_CK
1. Remap available only for 100-pin and 144-pin packages.
PA0
PA1
PA2
PA3
PA4
USART2_REMAP = 1
(1)
PD3
PD4
PD5
PD6
PD7
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RM0008
9.3.9
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Alternate function
Table 54. USART1 remapping
USART1_REMAP = 0
USART1_TX
USART1_RX
PA9
PA10
USART1_REMAP = 1
PB6
PB7
I2C1 alternate function remapping
Refer to AF remap and debug I/O configuration register (AFIO_MAPR)
Table 55. I2C1 remapping
Alternate function
I2C1_SCL
I2C1_SDA
1. Remap not available on 36-pin package.
I2C1_REMAP = 0
PB6
PB7
I2C1_REMAP = 1
(1)
PB8
PB9
Refer to AF remap and debug I/O configuration register (AFIO_MAPR)
Alternate function
SPI1_NSS
SPI1_SCK
SPI1_MISO
SPI1_MOSI
Table 56. SPI1 remapping
SPI1_REMAP = 0
PA4
PA5
PA6
PA7
SPI1_REMAP = 1
PA15
PB3
PB4
PB5
9.3.11 SPI3/I2S3 alternate function remapping
Refer to AF remap and debug I/O configuration register (AFIO_MAPR)
. This remap is available only in connectivity line devices.
Alternate function
Table 57. SPI3/I2S3 remapping
SPI3_REMAP = 0
SPI3_NSS / I2S3_WS
SPI3_SCK / I2S3_CK
SPI3_MISO
SPI3_MOSI / I2S3_SD
PA15
PB3
PB4
PB5
SPI3_REMAP = 1
PA4
PC10
PC11
PC12
Refer to AF remap and debug I/O configuration register (AFIO_MAPR)
. Ethernet is available only in connectivity line devices.
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General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Alternate function
RX_DV-CRS_DV
RXD0
RXD1
RXD2
RXD3
Table 58. ETH remapping
ETH_REMAP = 0
PA7
PC4
PC5
PB0
PB1
RM0008
ETH_REMAP = 1
PD8
PD9
PD10
PD11
PD12
182/1136 RM0008 Rev 21
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Note:
Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.
To read/write the AFIO_EVCR, AFIO_MAPR and AFIO_EXTICRX registers, the AFIO clock should first be enabled. Refer to
Section 7.3.7: APB2 peripheral clock enable register
The peripheral registers have to be accessed by words (32-bit).
31
15
30
Address offset: 0x00
Reset value: 0x0000 0000
29 28 27 26 25
14 13 12 11
Reserved
10 9
24 23
Reserved
8 7
EVOE rw
22 21 20
6 rw
5
PORT[2:0] rw
4 rw
19
3 rw
18 17
2 1 rw
PIN[3:0] rw
16
0 rw
Bits 31:8 Reserved
Bit 7 EVOE: Event output enable
Set and cleared by software. When set the EVENTOUT Cortex
®
output is connected to the
I/O selected by the PORT[2:0] and PIN[3:0] bits.
Bits 6:4 PORT[2:0] : Port selection
Set and cleared by software. Select the port used to output the Cortex
®
EVENTOUT signal.
Note: The EVENTOUT signal output capability is not extended to ports PF and PG.
000: PA selected
001: PB selected
010: PC selected
011: PD selected
100: PE selected
Bits 3:0 PIN[3:0]: Pin selection (x = A .. E)
Set and cleared by software. Select the pin used to output the Cortex ® EVENTOUT signal.
0000: Px0 selected
0001: Px1 selected
0010: Px2 selected
0011: Px3 selected
...
1111: Px15 selected
RM0008 Rev 21 183/1136
196
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
9.4.2 AF remap and debug I/O configuration register (AFIO_MAPR)
Address offset: 0x04
Reset value: 0x0000 0000
Memory map and bit definitions for low-, medium- high- and XL-density devices:
31
15
PD01_
REMAP rw
30 29
Reserved
28
14 13
CAN_REMAP
[1:0] rw rw
12
TIM4_
REMAP rw
27
11
26 w
10
25
SWJ_
CFG[2:0] w
9
24 w
8
TIM3_REMAP
[1:0] rw rw
TIM2_REMAP
[1:0] rw rw
23
7
22
Reserved
6
TIM1_REMAP
[1:0] rw rw
21
5
20
ADC2_E
TRGREG
_REMAP rw
4
USART3_
REMAP[1:0] rw rw
19
ADC2_E
TRGINJ_
REMAP rw
3
USART2_
REMAP rw
18
ADC1_E
TRGREG
_REMAP rw
2
USART1_
REMAP rw
17
ADC1_E
TRGINJ_
REMAP
16
TIM5CH4
_IREMAP rw
1
I2C1_
REMAP rw rw
0
SPI1_
REMAP rw
Bits 31:27 Reserved
Bits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration
These bits are write-only (when read, the value is undefined). They are used to configure the
SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD access to the Cortex
® debug port. The default state after reset is SWJ ON without trace.
This allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS /
JTCK pin.
000: Full SWJ (JTAG-DP + SW-DP): Reset State
001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
010: JTAG-DP Disabled and SW-DP Enabled
100: JTAG-DP Disabled and SW-DP Disabled
Other combinations: no effect
Bits 23:21 Reserved.
Bits 20 ADC2_ETRGREG_REMAP: ADC 2 external trigger regular conversion remapping
Set and cleared by software. This bit controls the trigger input connected to ADC2 external trigger regular conversion. When this bit is reset, the ADC2 external trigger regular conversion is connected to EXTI11. When this bit is set, the ADC2 external event regular conversion is connected to TIM8_TRGO.
Bits 19 ADC2_ETRGINJ_REMAP: ADC 2 external trigger injected conversion remapping
Set and cleared by software. This bit controls the trigger input connected to ADC2 external trigger injected conversion. When this bit is reset, the ADC2 external trigger injected conversion is connected to EXTI15. When this bit is set, the ADC2 external event injected conversion is connected to TIM8_Channel4.
Bits 18 ADC1_ETRGREG_REMAP: ADC 1 external trigger regular conversion remapping
Set and cleared by software. This bit controls the trigger input connected to ADC1
External trigger regular conversion. When reset the ADC1 External trigger regular conversion is connected to EXTI11. When set the ADC1 External Event regular conversion is connected to TIM8 TRGO.
184/1136 RM0008 Rev 21
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Bits 17 ADC1_ETRGINJ_REMAP: ADC 1 External trigger injected conversion remapping
Set and cleared by software. This bit controls the trigger input connected to ADC1
External trigger injected conversion. When reset the ADC1 External trigger injected conversion is connected to EXTI15. When set the ADC1 External Event injected conversion is connected to TIM8 Channel4.
Bits 16 TIM5CH4_IREMAP: TIM5 channel4 internal remap
Set and cleared by software. This bit controls the TIM5_CH4 internal mapping. When reset the timer TIM5_CH4 is connected to PA3. When set the LSI internal clock is connected to
TIM5_CH4 input for calibration purpose.
Note: This bit is available only in high density value line devices.
Bit 15 PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT
This bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO functionality. When the HSE oscillator is not used (application running on internal 8 MHz RC)
PD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 36-, 48- and 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping).
0: No remapping of PD0 and PD1
1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT,
Bits 14:13 CAN_REMAP[1:0]: CAN alternate function remapping
These bits are set and cleared by software. They control the mapping of alternate functions
CAN_RX and CAN_TX in devices with a single CAN interface.
00: CAN_RX mapped to PA11, CAN_TX mapped to PA12
01: Not used
10: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
11: CAN_RX mapped to PD0, CAN_TX mapped to PD1
Bit 12 TIM4_REMAP: TIM4 remapping
This bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 onto the GPIO ports.
0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
Note: TIM4_ETR on PE0 is not re-mapped.
Bits 11:10 TIM3_REMAP[1:0]: TIM3 remapping
These bits are set and cleared by software. They control the mapping of TIM3 channels 1 to
4 on the GPIO ports.
00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
01: Not used
10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
Note: TIM3_ETR on PE0 is not re-mapped.
Bits 9:8 TIM2_REMAP[1:0]: TIM2 remapping
These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to
4 and external trigger (ETR) on the GPIO ports.
00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
RM0008 Rev 21 185/1136
196
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
Bits 7:6 TIM1_REMAP[1:0]: TIM1 remapping
These bits are set and cleared by software. They control the mapping of TIM1 channels 1 to
4, 1N to 3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports.
00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12,
CH1N/PB13, CH2N/PB14, CH3N/PB15)
01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6,
CH1N/PA7, CH2N/PB0, CH3N/PB1)
10: not used
11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15,
CH1N/PE8, CH2N/PE10, CH3N/PE12)
Bits 5:4 USART3_REMAP[1:0]: USART3 remapping
These bits are set and cleared by software. They control the mapping of USART3 CTS,
RTS,CK,TX and RX alternate functions on the GPIO ports.
00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
10: not used
11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
Bit 3 USART2_REMAP: USART2 remapping
This bit is set and cleared by software. It controls the mapping of USART2 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports.
0: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
Bit 2 USART1_REMAP: USART1 remapping
This bit is set and cleared by software. It controls the mapping of USART1 TX and RX alternate functions on the GPIO ports.
0: No remap (TX/PA9, RX/PA10)
1: Remap (TX/PB6, RX/PB7)
Bit 1 I2C1_REMAP: I2C1 remapping
This bit is set and cleared by software. It controls the mapping of I2C1 SCL and SDA alternate functions on the GPIO ports.
0: No remap (SCL/PB6, SDA/PB7)
1: Remap (SCL/PB8, SDA/PB9)
Bit 0 SPI1_REMAP: SPI1 remapping
This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO,
MOSI alternate functions on the GPIO ports.
0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
186/1136 RM0008 Rev 21
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Memory map and bit definitions for connectivity line devices:
31
Res.
15
PD01_
REMA
P rw
30
PTP_P
PS_RE
MAP rw
14
29
TIM2IT
R1_
IREMA
P rw
13
CAN1_REMAP rw
[1:0] rw
28
SPI3_
REMA
P rw
12
TIM4_
REMA
P rw
27
Res.
11 w
10
TIM3_REMAP
[1:0] rw
26 rw
25
SWJ_
CFG[2:0] w
9 rw
24 w
8
TIM2_REMAP
[1:0] rw
23
MII_R
MII_SE
L
CAN2_
REMA
P
ETH_R
EMAP rw
7 rw
6
TIM1_REMAP
[1:0] rw
22 rw
21 rw
5 rw
20
4
USART3_
REMAP[1:0] rw
19 18 17 16
Reserved
3
USART2
_
REMAP rw
2
USART1
_
REMAP rw
1
I2C1_
REMA
P rw
TIM5C
H4_IRE
MAP rw
0
SPI1_
REMA
P rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 PTP_PPS_REMAP: Ethernet PTP PPS remapping
This bit is set and cleared by software. It enables the Ethernet MAC PPS_PTS to be output on the PB5 pin.
0: PTP_PPS not output on PB5 pin.
1: PTP_PPS is output on PB5 pin.
Note: This bit is available only in connectivity line devices and is reserved otherwise.
Bit 29 TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping
This bit is set and cleared by software. It controls the TIM2_ITR1 internal mapping.
0: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
1: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
Note: This bit is available only in connectivity line devices and is reserved otherwise.
Bit 28 SPI3_REMAP: SPI3/I2S3 remapping
This bit is set and cleared by software. It controls the mapping of SPI3_NSS/I2S3_WS,
SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD alternate functions on the GPIO ports.
0: No remap (SPI_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4,
SPI3_MOSI-I2S3_SD/PB5)
1: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11,
SPI3_MOSI-I2S3_SD/PC12)
Note: This bit is available only in connectivity line devices and is reserved otherwise.
Bit 27 Reserved
Bits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration
These bits are write-only (when read, the value is undefined). They are used to configure the
SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD access to the Cortex
®
debug port. The default state after reset is SWJ ON without trace.
This allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS /
JTCK pin.
000: Full SWJ (JTAG-DP + SW-DP): Reset State
001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
010: JTAG-DP Disabled and SW-DP Enabled
100: JTAG-DP Disabled and SW-DP Disabled
Other combinations: no effect
RM0008 Rev 21 187/1136
196
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
Bit 23 MII_RMII_SEL: MII or RMII selection
This bit is set and cleared by software. It configures the Ethernet MAC internally for use with an external MII or RMII PHY.
0: Configure Ethernet MAC for connection with an MII PHY
1: Configure Ethernet MAC for connection with an RMII PHY
Note: This bit is available only in connectivity line devices and is reserved otherwise.
Bit 22 CAN2_REMAP: CAN2 I/O remapping
This bit is set and cleared by software. It controls the CAN2_TX and CAN2_RX pins.
0: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
1: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
Note: This bit is available only in connectivity line devices and is reserved otherwise.
Bit 21 ETH_REMAP: Ethernet MAC I/O remapping
This bit is set and cleared by software. It controls the Ethernet MAC connections with the
PHY.
0: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
1: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
Note: This bit is available only in connectivity line devices and is reserved otherwise.
Bits 20:17 Reserved
Bits 16 TIM5CH4_IREMAP: TIM5 channel4 internal remap
Set and cleared by software. This bit controls the TIM5_CH4 internal mapping. When reset the timer TIM5_CH4 is connected to PA3. When set the LSI internal clock is connected to
TIM5_CH4 input for calibration purpose.
Bit 15 PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT
This bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO functionality. When the HSE oscillator is not used (application running on internal 8 MHz RC)
PD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 36-, 48- and 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping).
0: No remapping of PD0 and PD1
1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT,
Bits 14:13 CAN1_REMAP[1:0] : CAN 1 alternate function remapping
These bits are set and cleared by software. They control the mapping of alternate functions
CAN1_RX and CAN1_TX.
00: CAN1_RX mapped to PA11, CAN1_TX mapped to PA12
01: Not used
10: CAN1_RX mapped to PB8, CAN1_TX mapped to PB9 (not available on 36-pin package)
11: CAN1_RX mapped to PD0, CAN1_TX mapped to PD1
Bit 12 TIM4_REMAP: TIM4 remapping
This bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 onto the GPIO ports.
0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
Note: TIM4_ETR on PE0 is not re-mapped.
188/1136 RM0008 Rev 21
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Bits 11:10 TIM3_REMAP[1:0]: TIM3 remapping
These bits are set and cleared by software. They control the mapping of TIM3 channels 1 to
4 on the GPIO ports.
00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
01: Not used
10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
Note: TIM3_ETR on PE0 is not re-mapped.
Bits 9:8 TIM2_REMAP[1:0]: TIM2 remapping
These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to
4 and external trigger (ETR) on the GPIO ports.
00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
Bits 7:6 TIM1_REMAP[1:0]: TIM1 remapping
These bits are set and cleared by software. They control the mapping of TIM1 channels 1 to
4, 1N to 3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports.
00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12,
CH1N/PB13, CH2N/PB14, CH3N/PB15)
01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6,
CH1N/PA7, CH2N/PB0, CH3N/PB1)
10: not used
11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15,
CH1N/PE8, CH2N/PE10, CH3N/PE12)
Bits 5:4 USART3_REMAP[1:0]: USART3 remapping
These bits are set and cleared by software. They control the mapping of USART3 CTS,
RTS,CK,TX and RX alternate functions on the GPIO ports.
00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
10: not used
11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
Bit 3 USART2_REMAP: USART2 remapping
This bit is set and cleared by software. It controls the mapping of USART2 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports.
0: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
RM0008 Rev 21 189/1136
196
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
Bit 2 USART1_REMAP: USART1 remapping
This bit is set and cleared by software. It controls the mapping of USART1 TX and RX alternate functions on the GPIO ports.
0: No remap (TX/PA9, RX/PA10)
1: Remap (TX/PB6, RX/PB7)
Bit 1 I2C1_REMAP: I2C1 remapping
This bit is set and cleared by software. It controls the mapping of I2C1 SCL and SDA alternate functions on the GPIO ports.
0: No remap (SCL/PB6, SDA/PB7)
1: Remap (SCL/PB8, SDA/PB9)
Bit 0 SPI1_REMAP: SPI1 remapping
This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO,
MOSI alternate functions on the GPIO ports.
0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
190/1136 RM0008 Rev 21
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
9.4.3
31
15 rw
30
External interrupt configuration register 1 (AFIO_EXTICR1)
Address offset: 0x08
Reset value: 0x0000
29 28 27 26 25 22 21 20 19 18
12 11
24 23
Reserved
8 7 4 3 14 13
EXTI3[3:0] rw rw rw rw
10 9
EXTI2[3:0] rw rw rw rw
6 5
EXTI1[3:0] rw rw rw rw
17
2 1
EXTI0[3:0] rw rw
16
0 rw
Bits 31:16 Reserved
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 0 to 3)
These bits are written by software to select the source input for EXTIx external interrupt.
Refer to Section 10.2.5: External interrupt/event line mapping
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
9.4.4
31
15 rw
30
External interrupt configuration register 2 (AFIO_EXTICR2)
Address offset: 0x0C
Reset value: 0x0000
29 28 27 26 25 22 21 20 19 18
12 11
24 23
Reserved
8 7 4 3 14 13
EXTI7[3:0] rw rw rw rw
10 9
EXTI6[3:0] rw rw rw rw
6 5
EXTI5[3:0] rw rw rw rw
17
2 1
EXTI4[3:0] rw rw
16
0
Bits 31:16 Reserved
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 4 to 7)
These bits are written by software to select the source input for EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin rw
RM0008 Rev 21 191/1136
196
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
9.4.5
31
15 rw
30
External interrupt configuration register 3 (AFIO_EXTICR3)
Address offset: 0x10
Reset value: 0x0000
29 28 27 26 25 22 21 20 19 18
12 11
24 23
Reserved
8 7 4 3 14 13
EXTI11[3:0] rw rw rw rw
10 9
EXTI10[3:0] rw rw rw rw
6 5
EXTI9[3:0] rw rw rw rw
17
2 1
EXTI8[3:0] rw rw
Bits 31:16 Reserved
Bits 15:0 EXTIx[3:0] : EXTI x configuration (x= 8 to 11)
These bits are written by software to select the source input for EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
16
0 rw
9.4.6
31
15 rw
30
External interrupt configuration register 4 (AFIO_EXTICR4)
Address offset: 0x14
Reset value: 0x0000
29 28 27 26 25 22 21 20 19 18
12 11
24 23
Reserved
8 7 4 3 14 13
EXTI15[3:0] rw rw rw rw
10 9
EXTI14[3:0] rw rw rw rw
6 5
EXTI13[3:0] rw rw rw rw
17
2 1
EXTI12[3:0] rw rw
Bits 31:16 Reserved
Bits 15:0 EXTIx[3:0] : EXTI x configuration (x= 12 to 15)
These bits are written by software to select the source input for EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
16
0 rw
192/1136 RM0008 Rev 21
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)
9.4.7
31
15
30
14
AF remap and debug I/O configuration register2 (AFIO_MAPR2)
Address offset: 0x1C
Reset value: 0x0000 0000
29
13
Reserved
28
12
27
11
26 25 24 23
Reserved
10
FSM
C_NA
DV
9 8 7
TIM14_
REMA
P
TIM13_
REMA
P
TIM11_
REMA
P
22
6
TIM10_
REMA
P rw rw rw rw rw
21
5
TIM9_
REMA
P rw
20
4
19
3
18
2
Reserved
17
1
16
0
Bits 31:11 Reserved.
Bit 10 FSMC_NADV: NADV connect/disconnect
This bit is set and cleared by software. It controls the use of the optional FSMC_NADV signal.
0: The NADV signal is connected to the output (default)
1: The NADV signal is not connected. The I/O pin can be used by another peripheral.
Bit 9 TIM14_REMAP: TIM14 remapping
This bit is set and cleared by software. It controls the mapping of the TIM14_CH1 alternate function onto the GPIO ports.
0: No remap (PA7)
1: Remap (PF9)
Bit 8 TIM13_REMAP: TIM13 remapping
This bit is set and cleared by software. It controls the mapping of the TIM13_CH1 alternate function onto the GPIO ports.
0: No remap (PA6)
1: Remap (PF8)
Bit 7 TIM11_REMAP: TIM11 remapping
This bit is set and cleared by software. It controls the mapping of the TIM11_CH1 alternate function onto the GPIO ports.
0: No remap (PB9)
1: Remap (PF7)
Bit 6 TIM10_REMAP: TIM10 remapping
This bit is set and cleared by software. It controls the mapping of the TIM10_CH1 alternate function onto the GPIO ports.
0: No remap (PB8)
1: Remap (PF6)
Bit 5 TIM9_REMAP: TIM9 remapping
This bit is set and cleared by software. It controls the mapping of the TIM9_CH1 and
TIM9_CH2 alternate functions onto the GPIO ports.
0: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3)
1: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6)
Bits 4:0 Reserved.
RM0008 Rev 21 193/1136
196
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
9.5 GPIO and AFIO register maps
The following tables give the GPIO and AFIO register map and the reset values.
for the register boundary addresses.
Table 59. GPIO register map and reset values
RM0008
Register
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
GPIOx
_CRL
CNF
7
[1:0]
MODE
7
[1:0]
CNF
6
[1:0]
MODE
6
[1:0]
CNF
5
[1:0]
MODE
5
[1:0]
CNF
4
[1:0]
MODE
4
[1:0]
CNF
3
[1:0]
MOD
E3
[1:0]
CNF
2
[1:0]
MODE
2
[1:0]
CNF
1
[1:0]
MOD
E1
[1:0]
CNF
0
[1:0]
MODE
0
[1:0]
Reset value 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
GPIOx
_CRH
CNF
15
[1:0]
MODE
15
[1:0]
CNF
14
[1:0]
MODE
14
[1:0]
CNF
13
[1:0]
MODE
13
[1:0]
CNF
12
[1:0]
MODE
12
[1:0]
CNF
11
[1:0]
MOD
E11
[1:0]
CNF
10
[1:0]
MODE
10
[1:0]
CNF
9
[1:0]
MOD
E9
[1:0]
CNF
8
[1:0]
MODE
8
[1:0]
Reset value 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
GPIOx
_IDR
IDRy
Reserved
Reset value
GPIOx
_ODR Reserved
0 0 0 0 0 0 0 0 0
ODRy
0 0 0 0 0 0 0
Reset value
GPIOx
_BSRR
BR[15:0]
0 0 0 0 0 0 0 0 0
BSR[15:0]
0 0 0 0 0 0 0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx
_BRR
Reset value
Reserved
0 0 0 0 0 0 0
BR[15:0]
0 0 0 0 0 0 0 0 0
GPIOx
_LCKR
Reset value
Reserved
0 0 0 0 0 0 0 0
LCK[15:0]
0 0 0 0 0 0 0 0 0
194/1136 RM0008 Rev 21
RM0008
Offset Register
0x00
AFIO_EVCR
Reset value
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Table 60. AFIO register map and reset values
Reserved
PORT[2:
0]
PIN[3:0]
0 0 0 0 0 0 0
0x04
AFIO_MAPR low-, medium-, high- and XLdensity devices
Reserved
Reserve d
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x04
AFIO_MAPR connectivity line devices
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x04
AFIO_MAPR
Reserved
SWJ_
CFG[2:0] Reserved
0x08
0x0C
0x10
0x14
Reset value
AFIO_EXTICR1
Reset value
AFIO_EXTICR2
Reset value
AFIO_EXTICR3
Reset value
AFIO_EXTICR4
Reset value
0x1C
AFIO_MAPR
2
Reset value
0 0 0
Reserved
Reserved
Reserved
Reserved
Reserved
RM0008 Rev 21
0 0
EXTI3[3:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
Reserved
195/1136
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General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Table 60. AFIO register map and reset values (continued)
Offset Register
RM0008
0x1C
AFIO_MAPR2
Reset value
Reserved Res.
0 0 0 0 0 0 0 0 0 0 0
196/1136 RM0008 Rev 21
RM0008
10 Interrupts and events
Interrupts and events
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to the whole STM32F10xxx family, unless otherwise specified.
10.1 Nested vectored interrupt controller (NVIC)
Features
68 (not including the sixteen Cortex ® -M3 interrupt lines)
16 programmable priority levels (4 bits of interrupt priority are used)
Low-latency exception and interrupt handling
Power management control
Implementation of System Control registers
The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to STM32F10xxx Cortex ® -M3 programming manual (see
Related documents on page 1 ).
The SysTick calibration value is set to 9000, which gives a reference time base of 1 ms with the SysTick clock set to 9 MHz (max HCLK/8).
RM0008 Rev 21 197/1136
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Interrupts and events RM0008
10.1.2 Interrupt and exception vectors
are the vector tables for connectivity line and other STM32F10xxx devices, respectively.
Table 61. Vector table for connectivity line devices
Type of priority
Acronym Description Address
198/1136
-
-3
-2
fixed fixed
-
Reset
NMI
-
-
-
-
-1 fixed HardFault
0 settable MemManage
1 settable BusFault
2 settable UsageFault
-
3 settable SVCall
-
-
-
4
-
5
6 settable
settable settable
-
Debug Monitor
PendSV
SysTick
0 7 settable WWDG
1 8 settable PVD
2 9 settable TAMPER
3 10 settable RTC
4 11 settable FLASH
5 12 settable RCC
6 13 settable EXTI0
7 14 settable EXTI1
8 15 settable EXTI2
9 16 settable EXTI3
10 17 settable EXTI4
Reserved
Reset
Non maskable interrupt. The RCC
Clock Security System (CSS) is linked to the NMI vector.
All class of fault
Memory management
Pre-fetch fault, memory access fault
Undefined instruction or illegal state
Reserved
0x0000_0000
0x0000_0004
0x0000_0008
0x0000_000C
0x0000_0010
0x0000_0014
0x0000_0018
0x0000_001C -
0x0000_002B
System service call via SWI instruction
Debug Monitor
Reserved
0x0000_002C
0x0000_0030
0x0000_0034
Pendable request for system service 0x0000_0038
System tick timer 0x0000_003C
Window Watchdog interrupt 0x0000_0040
PVD through EXTI Line detection interrupt
Tamper interrupt
0x0000_0044
RTC global interrupt
Flash global interrupt
RCC global interrupt
0x0000_0048
0x0000_004C
0x0000_0050
0x0000_0054
EXTI Line0 interrupt
EXTI Line1 interrupt
EXTI Line2 interrupt
EXTI Line3 interrupt
EXTI Line4 interrupt
0x0000_0058
0x0000_005C
0x0000_0060
0x0000_0064
0x0000_0068
RM0008 Rev 21
RM0008 Interrupts and events
Table 61. Vector table for connectivity line devices (continued)
Type of priority
Acronym Description Address
11 18 settable DMA1_Channel1
12 19 settable DMA1_Channel2
13 20 settable DMA1_Channel3
14 21 settable DMA1_Channel4
15 22 settable DMA1_Channel5
16 23 settable DMA1_Channel6
17 24 settable DMA1_Channel7
18 25 settable ADC1_2
19 26 settable CAN1_TX
20 27 settable CAN1_RX0
21 28 settable CAN1_RX1
22 29 settable CAN1_SCE
23 30 settable EXTI9_5
24 31 settable TIM1_BRK
25 32 settable TIM1_UP
26 33 settable TIM1_TRG_COM
27 34 settable TIM1_CC
28 35 settable TIM2
29 36 settable TIM3
30 37 settable TIM4
31 38 settable I2C1_EV
32 39 settable I2C1_ER
33 40 settable I2C2_EV
34 41 settable I2C2_ER
35 42 settable SPI1
36 43 settable SPI2
37 44 settable USART1
38 45 settable USART2
39 46 settable USART3
DMA1 Channel1 global interrupt
DMA1 Channel2 global interrupt
DMA1 Channel3 global interrupt
DMA1 Channel4 global interrupt
DMA1 Channel5 global interrupt
DMA1 Channel6 global interrupt
DMA1 Channel7 global interrupt
ADC1 and ADC2 global interrupt
CAN1 TX interrupts
CAN1 RX0 interrupts
CAN1 RX1 interrupt
CAN1 SCE interrupt
EXTI Line[9:5] interrupts
TIM1 Break interrupt
TIM1 Update interrupt
TIM1 Trigger and Commutation interrupts
TIM1 Capture Compare interrupt
TIM2 global interrupt
TIM3 global interrupt
TIM4 global interrupt
I
2
C1 event interrupt
I
2
C1 error interrupt
I
2
C2 event interrupt
I
2
C2 error interrupt
SPI1 global interrupt
SPI2 global interrupt
USART1 global interrupt
USART2 global interrupt
USART3 global interrupt
0x0000_00A8
0x0000_00AC
0x0000_00B0
0x0000_00B4
0x0000_00B8
0x0000_00BC
0x0000_00C0
0x0000_00C4
0x0000_00C8
0x0000_00CC
0x0000_00D0
0x0000_00D4
0x0000_00D8
0x0000_00DC
0x0000_006C
0x0000_0070
0x0000_0074
0x0000_0078
0x0000_007C
0x0000_0080
0x0000_0084
0x0000_0088
0x0000_008C
0x0000_0090
0x0000_0094
0x0000_0098
0x0000_009C
0x0000_00A0
0x0000_00A4
RM0008 Rev 21 199/1136
214
Interrupts and events
Table 61. Vector table for connectivity line devices (continued)
Type of priority
Acronym Description Address
RM0008
40
41
42
47
48
49 settable settable settable
EXTI15_10
RTCAlarm
OTG_FS_WKUP
-
50 57 settable TIM5
51 58 settable SPI3
52 59 settable UART4
53 60 settable UART5
54 61 settable TIM6
55 62 settable TIM7
56 63 settable DMA2_Channel1
57 64 settable DMA2_Channel2
58 65 settable DMA2_Channel3
59 66 settable DMA2_Channel4
60 67 settable DMA2_Channel5
61 68 settable ETH
62 69 settable ETH_WKUP
63 70 settable CAN2_TX
64 71 settable CAN2_RX0
65 72 settable CAN2_RX1
66 73 settable CAN2_SCE
67 74 settable OTG_FS
EXTI Line[15:10] interrupts
RTC alarm through EXTI line interrupt
USB On-The-Go FS Wakeup through EXTI line interrupt
Reserved
TIM5 global interrupt
SPI3 global interrupt
UART4 global interrupt
UART5 global interrupt
TIM6 global interrupt
TIM7 global interrupt
DMA2 Channel1 global interrupt
DMA2 Channel2 global interrupt
DMA2 Channel3 global interrupt
DMA2 Channel4 global interrupt
DMA2 Channel5 global interrupt
Ethernet global interrupt
Ethernet Wakeup through EXTI line interrupt
CAN2 TX interrupts
CAN2 RX0 interrupts
CAN2 RX1 interrupt
CAN2 SCE interrupt
USB On The Go FS global interrupt
0x0000_00E0
0x0000_00E4
0x0000_00E8
0x0000_00EC -
0x0000_0104
0x0000_0108
0x0000_010C
0x0000_0110
0x0000_0114
0x0000_0118
0x0000_011C
0x0000_0120
0x0000_0124
0x0000_0128
0x0000_012C
0x0000_0130
0x0000_0134
0x0000_0138
0x0000_013C
0x0000_0140
0x0000_0144
0x0000_0148
0x0000_014C
200/1136 RM0008 Rev 21
RM0008
Table 62. Vector table for XL-density devices
Type of priority
Acronym Description
Interrupts and events
Address
- -
-3 fixed
-2 fixed
-
Reset
NMI
-1 fixed HardFault
0 settable MemManage
1 settable BusFault
2 settable UsageFault
- -
3 settable SVCall
4 settable Debug Monitor
- -
5 settable PendSV
6 settable SysTick
0 7 settable WWDG
1 8 settable PVD
2 9 settable TAMPER
3 10 settable RTC
4 11 settable FLASH
5 12 settable RCC
6 13 settable EXTI0
7 14 settable EXTI1
8 15 settable EXTI2
9 16 settable EXTI3
10 17 settable EXTI4
11 18 settable DMA1_Channel1
12 19 settable DMA1_Channel2
13 20 settable DMA1_Channel3
Reserved
Reset
0x0000_0000
0x0000_0004
Nonmaskable interrupt. The RCC
Clock Security System (CSS) is linked to the NMI vector.
All class of fault
0x0000_0008
0x0000_000C
Memory management 0x0000_0010
Prefetch fault, memory access fault 0x0000_0014
Undefined instruction or illegal state 0x0000_0018
Reserved
0x0000_001C -
0x0000_002B
System service call via SWI instruction
Debug monitor
Systick timer
0x0000_002C
0x0000_0030
Reserved 0x0000_0034
Pendable request for system service 0x0000_0038
0x0000_003C
0x0000_0040 Window watchdog interrupt
PVD through EXTI Line detection interrupt
0x0000_0044
Tamper interrupt
RTC global interrupt
Flash global interrupt
RCC global interrupt
EXTI Line0 interrupt
EXTI Line1 interrupt
0x0000_0048
0x0000_004C
0x0000_0050
0x0000_0054
0x0000_0058
0x0000_005C
EXTI Line2 interrupt
EXTI Line3 interrupt
EXTI Line4 interrupt
DMA1 Channel1 global interrupt
DMA1 Channel2 global interrupt
DMA1 Channel3 global interrupt
0x0000_0060
0x0000_0064
0x0000_0068
0x0000_006C
0x0000_0070
0x0000_0074
RM0008 Rev 21 201/1136
214
Interrupts and events
Table 62. Vector table for XL-density devices (continued)
Type of priority
Acronym Description Address
RM0008
14 21 settable DMA1_Channel4
15 22 settable DMA1_Channel5
16 23 settable DMA1_Channel6
17 24 settable DMA1_Channel7
18 25 settable ADC1_2
19 26 settable USB_HP_CAN_TX
20 27 settable USB_LP_CAN_RX0
21 28 settable CAN_RX1
22 29 settable CAN_SCE
23 30 settable EXTI9_5
24 31 settable TIM1_BRK_TIM9
25 32 settable TIM1_UP_TIM10
26 33 settable TIM1_TRG_COM_TIM11
27 34 settable TIM1_CC
28 35 settable TIM2
29 36 settable TIM3
30 37 settable TIM4
31 38 settable I2C1_EV
32 39 settable I2C1_ER
33 40 settable I2C2_EV
34 41 settable I2C2_ER
35 42 settable SPI1
36 43 settable SPI2
37 44 settable USART1
38 45 settable USART2
39 46 settable USART3
40 47 settable EXTI15_10
DMA1 Channel4 global interrupt
DMA1 Channel5 global interrupt
DMA1 Channel6 global interrupt
DMA1 Channel7 global interrupt
0x0000_0078
0x0000_007C
0x0000_0080
0x0000_0084
0x0000_0088 ADC1 and ADC2 global interrupt
USB high priority or CAN TX interrupts
USB low priority or CAN RX0 interrupts
CAN RX1 interrupt
CAN SCE interrupt
EXTI Line[9:5] interrupts
0x0000_008C
0x0000_0090
0x0000_0094
0x0000_0098
0x0000_009C
TIM1 Break interrupt and TIM9 global interrupt
0x0000_00A0
TIM1 Update interrupt and TIM10 global interrupt
TIM1 Trigger and Commutation interrupts and TIM11 global interrupt
0x0000_00A4
0x0000_00A8
TIM1 Capture Compare interrupt
TIM2 global interrupt
TIM3 global interrupt
TIM4 global interrupt
I2C1 event interrupt
I2C1 error interrupt
0x0000_00AC
0x0000_00B0
0x0000_00B4
0x0000_00B8
0x0000_00BC
0x0000_00C0
I2C2 event interrupt
I2C2 error interrupt
SPI1 global interrupt
SPI2 global interrupt
USART1 global interrupt
USART2 global interrupt
USART3 global interrupt
EXTI Line[15:10] interrupts
0x0000_00C4
0x0000_00C8
0x0000_00CC
0x0000_00D0
0x0000_00D4
0x0000_00D8
0x0000_00DC
0x0000_00E0
202/1136 RM0008 Rev 21
RM0008 Interrupts and events
Table 62. Vector table for XL-density devices (continued)
Type of priority
Acronym Description Address
41 48 settable RTCAlarm
42 49 settable USBWakeUp
43 50 settable TIM8_BRK_TIM12
44 51 settable TIM8_UP_TIM13
45 52 settable TIM8_TRG_COM_TIM14
46 53 settable TIM8_CC
47 54 settable ADC3
48 55 settable FSMC
49 56 settable SDIO
50 57 settable TIM5
51 58 settable SPI3
52 59 settable UART4
53 60 settable UART5
54 61 settable TIM6
55 62 settable TIM7
56 63 settable DMA2_Channel1
57 64 settable DMA2_Channel2
58 65 settable DMA2_Channel3
59 66 settable DMA2_Channel4_5
RTC alarm through EXTI line interrupt
USB wakeup from suspend through
EXTI line interrupt
TIM8 Break interrupt and TIM12 global interrupt
TIM8 Update interrupt and TIM13 global interrupt
TIM8 Trigger and Commutation interrupts and TIM14 global interrupt
TIM8 Capture Compare interrupt
ADC3 global interrupt
FSMC global interrupt
SDIO global interrupt
TIM5 global interrupt
SPI3 global interrupt
UART4 global interrupt
UART5 global interrupt
TIM6 global interrupt
TIM7 global interrupt
DMA2 Channel1 global interrupt
DMA2 Channel2 global interrupt
DMA2 Channel3 global interrupt
DMA2 Channel4 and DMA2
Channel5 global interrupts
0x0000_00E4
0x0000_00E8
0x0000_00EC
0x0000_00F0
0x0000_00F4
0x0000_00F8
0x0000_00FC
0x0000_0100
0x0000_0104
0x0000_0108
0x0000_010C
0x0000_0110
0x0000_0114
0x0000_0118
0x0000_011C
0x0000_0120
0x0000_0124
0x0000_0128
0x0000_012C
RM0008 Rev 21 203/1136
214
Interrupts and events
Table 63. Vector table for other STM32F10xxx devices
Type of priority
Acronym Description Address
RM0008
204/1136
-
-
-
-
-
-
-
-
-3
-2
-1
0
1
2
-
fixed fixed fixed settable settable settable
-
-
-
Reset
NMI
HardFault
MemManage
BusFault
UsageFault
3 settable SVCall
-
-
4
settable
-
Debug Monitor
5 settable PendSV
6 settable SysTick
0 7 settable WWDG
1 8 settable PVD
2 9 settable TAMPER
3 10 settable RTC
4 11 settable FLASH
5 12 settable RCC
6 13 settable EXTI0
7 14 settable EXTI1
8 15 settable EXTI2
9 16 settable EXTI3
10 17 settable EXTI4
11 18 settable DMA1_Channel1
12 19 settable DMA1_Channel2
13 20 settable DMA1_Channel3
Reserved
Reset
Non maskable interrupt. The RCC
Clock Security System (CSS) is linked to the NMI vector.
All class of fault
Memory management
Prefetch fault, memory access fault
Undefined instruction or illegal state
Reserved
0x0000_0000
0x0000_0004
0x0000_0008
0x0000_000C
0x0000_0010
0x0000_0014
0x0000_0018
0x0000_001C -
0x0000_002B
System service call via SWI instruction
Debug Monitor
System tick timer
0x0000_002C
0x0000_0030
Reserved 0x0000_0034
Pendable request for system service 0x0000_0038
0x0000_003C
0x0000_0040 Window watchdog interrupt
PVD through EXTI Line detection interrupt
0x0000_0044
Tamper interrupt
RTC global interrupt
Flash global interrupt
RCC global interrupt
EXTI Line0 interrupt
EXTI Line1 interrupt
0x0000_0048
0x0000_004C
0x0000_0050
0x0000_0054
0x0000_0058
0x0000_005C
EXTI Line2 interrupt
EXTI Line3 interrupt
EXTI Line4 interrupt
DMA1 Channel1 global interrupt
DMA1 Channel2 global interrupt
DMA1 Channel3 global interrupt
0x0000_0060
0x0000_0064
0x0000_0068
0x0000_006C
0x0000_0070
0x0000_0074
RM0008 Rev 21
RM0008 Interrupts and events
Table 63. Vector table for other STM32F10xxx devices (continued)
Type of priority
Acronym Description Address
14 21 settable DMA1_Channel4
15 22 settable DMA1_Channel5
16 23 settable DMA1_Channel6
17 24 settable DMA1_Channel7
18 25 settable ADC1_2
19 26 settable
USB_HP_CAN_
TX
20 27 settable
USB_LP_CAN_
RX0
21 28 settable CAN_RX1
22 29 settable CAN_SCE
23 30 settable EXTI9_5
24 31 settable TIM1_BRK
25 32 settable TIM1_UP
26 33 settable TIM1_TRG_COM
27 34 settable TIM1_CC
28 35 settable TIM2
29 36 settable TIM3
30 37 settable TIM4
31 38 settable I2C1_EV
32 39 settable I2C1_ER
33 40 settable I2C2_EV
34 41 settable I2C2_ER
35 42 settable SPI1
36 43 settable SPI2
37 44 settable USART1
38 45 settable USART2
39 46 settable USART3
40 47 settable EXTI15_10
41 48 settable RTCAlarm
DMA1 Channel4 global interrupt
DMA1 Channel5 global interrupt
DMA1 Channel6 global interrupt
DMA1 Channel7 global interrupt
ADC1 and ADC2 global interrupt
USB High Priority or CAN TX interrupts
USB Low Priority or CAN RX0 interrupts
CAN RX1 interrupt
CAN SCE interrupt
EXTI Line[9:5] interrupts
TIM1 Break interrupt
TIM1 Update interrupt
TIM1 Trigger and Commutation interrupts
TIM1 Capture Compare interrupt
TIM2 global interrupt
TIM3 global interrupt
TIM4 global interrupt
I
2
C1 event interrupt
I
2
C1 error interrupt
I
2
C2 event interrupt
I
2
C2 error interrupt
SPI1 global interrupt
SPI2 global interrupt
USART1 global interrupt
USART2 global interrupt
USART3 global interrupt
EXTI Line[15:10] interrupts
RTC alarm through EXTI line interrupt
RM0008 Rev 21
0x0000_0078
0x0000_007C
0x0000_0080
0x0000_0084
0x0000_0088
0x0000_008C
0x0000_0090
0x0000_0094
0x0000_0098
0x0000_009C
0x0000_00A0
0x0000_00A4
0x0000_00A8
0x0000_00AC
0x0000_00B0
0x0000_00B4
0x0000_00B8
0x0000_00BC
0x0000_00C0
0x0000_00C4
0x0000_00C8
0x0000_00CC
0x0000_00D0
0x0000_00D4
0x0000_00D8
0x0000_00DC
0x0000_00E0
0x0000_00E4
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Table 63. Vector table for other STM32F10xxx devices (continued)
RM0008
Type of priority
Acronym Description Address
42
43
44
45
49
50
51
52 settable settable settable settable
USBWakeup
TIM8_BRK
TIM8_UP
TIM8_TRG_COM
46 53 settable TIM8_CC
47 54 settable ADC3
48 55 settable FSMC
49 56 settable SDIO
50 57 settable TIM5
51 58 settable SPI3
USB wakeup from suspend through
EXTI line interrupt
TIM8 Break interrupt
TIM8 Update interrupt
TIM8 Trigger and Commutation interrupts
TIM8 Capture Compare interrupt
ADC3 global interrupt
FSMC global interrupt
SDIO global interrupt
TIM5 global interrupt
SPI3 global interrupt
52 59 settable UART4
53 60 settable UART5
54 61 settable TIM6
UART4 global interrupt
UART5 global interrupt
TIM6 global interrupt
55 62 settable TIM7
56 63 settable DMA2_Channel1
57 64 settable DMA2_Channel2
TIM7 global interrupt
DMA2 Channel1 global interrupt
DMA2 Channel2 global interrupt
58 65 settable DMA2_Channel3
59 66 settable DMA2_Channel4_5
DMA2 Channel3 global interrupt
DMA2 Channel4 and DMA2
Channel5 global interrupts
0x0000_00E8
0x0000_00EC
0x0000_00F0
0x0000_00F4
0x0000_00F8
0x0000_00FC
0x0000_0100
0x0000_0104
0x0000_0108
0x0000_010C
0x0000_0110
0x0000_0114
0x0000_0118
0x0000_011C
0x0000_0120
0x0000_0124
0x0000_0128
0x0000_012C
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RM0008 Interrupts and events
The external interrupt/event controller consists of up to 20 edge detectors in connectivity line devices, or 19 edge detectors in other devices for generating event/interrupt requests.
Each input line can be independently configured to select the type (event or interrupt) and the corresponding trigger event (rising or falling or both). Each line can also masked independently. A pending register maintains the status line of the interrupt requests
The EXTI controller main features are the following:
Independent trigger and mask on each interrupt/event line
Dedicated status bit for each interrupt line
Generation of up to 20 software event/interrupt requests
Detection of external signal with pulse width lower than APB2 clock period. Refer to the electrical characteristics section of the datasheet for details on this parameter.
The block diagram is shown in
.
Figure 20. External interrupt/event controller block diagram
AMBA APB bus
PCLK2
Peripheral interface
19 19 19 19 19
To NVIC interrupt controller
19
Pending request register
Interrupt mask register
19
Software interrupt event register
19
Rising trigger selection register
19
Falling trigger selection register
19
19
Pulse generator 19 19
Edge detect circuit
Input
Line
Event mask register
MS19816V1
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Interrupts and events RM0008
The STM32F10xxx is able to handle external or internal events in order to wake up the core
(WFE). The wakeup event can be generated either by:
enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex ® -M3 System Control register. When the MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
In connectivity line devices, Ethernet wakeup events also have the WFE wakeup capability.
To use an external line as a wakeup event, refer to
Section 10.2.4: Functional description
.
To generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register.
When the selected edge occurs on the external interrupt line, an interrupt request is generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a ‘1’ in the pending register.
To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’ to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set
An interrupt/event request can also be generated by software by writing a ‘1’ in the software interrupt/event register.
Hardware interrupt selection
To configure the 20 lines as interrupt sources, use the following procedure:
Configure the mask bits of the 20 Interrupt lines (EXTI_IMR)
Configure the Trigger Selection bits of the Interrupt lines (EXTI_RTSR and
EXTI_FTSR)
Configure the enable and mask bits that control the NVIC IRQ channel mapped to the
External Interrupt Controller (EXTI) so that an interrupt coming from one of the 20 lines can be correctly acknowledged.
Hardware event selection
To configure the 20 lines as event sources, use the following procedure:
Configure the mask bits of the 20 Event lines (EXTI_EMR)
Configure the Trigger Selection bits of the Event lines (EXTI_RTSR and EXTI_FTSR)
208/1136 RM0008 Rev 21
RM0008 Interrupts and events
Software interrupt/event selection
The 20 lines can be configured as software interrupt/event lines. The following is the procedure to generate a software interrupt.
Configure the mask bits of the 20 Interrupt/Event lines (EXTI_IMR, EXTI_EMR)
Set the required bit of the software interrupt register (EXTI_SWIER)
The 112 GPIOs are connected to the 16 external interrupt/event lines in the following manner:
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Interrupts and events
Figure 21. External interrupt/event GPIO mapping
EXTI0[3:0] bits in AFIO_EXTICR1 register
PA1
PB1
PC1
PD1
PE1
PF1
PG1
PA0
PB0
PC0
PD0
PE0
PF0
PG0
EXTI0
EXTI1[3:0] bits in AFIO_EXTICR1 register
EXTI1
RM0008
210/1136
EXTI15[3:0] bits in AFIO_EXTICR4 register
PA15
PB15
PC15
PD15
PE15
PF15
PG15
EXTI15
1. To configure the AFIO_EXTICRx for the mapping of external interrupt/event lines onto GPIOs, the AFIO
clock should first be enabled. Refer to Section 7.3.7: APB2 peripheral clock enable register
for connectivity line devices.
The four other EXTI lines are connected as follows:
EXTI line 16 is connected to the PVD output
EXTI line 17 is connected to the RTC Alarm event
EXTI line 18 is connected to the USB Wakeup event
EXTI line 19 is connected to the Ethernet Wakeup event (available only in connectivity line devices)
RM0008 Rev 21
RM0008 Interrupts and events
10.3
EXTI
registers
Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).
10.3.1 Interrupt mask register (EXTI_IMR)
Address offset: 0x00
Reset value: 0x0000 0000
31 30 29 28 27 26 25
Reserved
15 14 13 12 11 10
MR15 MR14 MR13 MR12 MR11 MR10 rw rw rw rw rw rw
9
MR9 rw
24
8
MR8 rw
23
7
MR7 rw
22
6
MR6 rw
21
5
MR5 rw
20
4
MR4 rw
19 18 17 16
MR19 MR18 MR17 MR16 rw rw rw rw
3 2 1 0
MR3 MR2 MR1 MR0 rw rw rw rw
Bits 31:20 Reserved, must be kept at reset value (0).
Bits 19:0 MRx: Interrupt Mask on line x
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
Note: Bit 19 is used in connectivity line devices only and is reserved otherwise.
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28 27 26 25
Reserved
15 14 13 12 11 10
MR15 MR14 MR13 MR12 MR11 MR10 rw rw rw rw rw rw
9
MR9 rw
24
8
MR8 rw
23
7
MR7 rw
22
6
MR6 rw
21
5
MR5 rw
20
4
MR4 rw
19 18 17 16
MR19 MR18 MR17 MR16 rw rw rw rw
3 2 1 0
MR3 rw
MR2 rw
MR1 rw
MR0 rw
Bits 31:20 Reserved, must be kept at reset value (0).
Bits 19:0 MRx: Event mask on line x
0: Event request from Line x is masked
1: Event request from Line x is not masked
Note: Bit 19 is used in connectivity line devices only and is reserved otherwise.
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Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28 27 26 25
Reserved
15 14 13 12 11 10
TR15 TR14 TR13 TR12 TR11 TR10 rw rw rw rw rw rw
9
TR9 rw
24
8
TR8 rw
23
7
TR7 rw
22
6
TR6 rw
21
5
TR5 rw
20
4
TR4 rw
19 18
TR19 TR18 rw
3 rw
2
TR3 rw
TR2 rw
17
TR17 rw
1
TR1 rw
Bits 31:20 Reserved, must be kept at reset value (0).
Bits 19:0 TRx: Rising trigger event configuration bit of line x
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.
Note: Bit 19 is used in connectivity line devices only and is reserved otherwise.
16
TR16 rw
0
TR0 rw
Note: The external wakeup lines are edge triggered, no glitches must be generated on these lines.
If a rising edge on external interrupt line occurs during writing of EXTI_RTSR register, the pending bit will not be set.
Rising and Falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition.
Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29 28 27 26 25
Reserved
15 14 13 12 11 10
TR15 TR14 TR13 TR12 TR11 TR10 rw rw rw rw rw rw
9
TR9 rw
24
8
TR8 rw
23
7
TR7 rw
22
6
TR6 rw
21
5
TR5 rw
20
4
TR4 rw
Bits 31:20 Reserved, must be kept at reset value (0).
Bits 19:0 TRx: Falling trigger event configuration bit of line x
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.
Note: Bit 19 used in connectivity line devices and is reserved otherwise.
19 18
TR19 TR18 rw rw
3 2
TR3 rw
TR2 rw
17
TR17 rw
1
TR1 rw
16
TR16 rw
0
TR0 rw
Note: The external wakeup lines are edge triggered, no glitches must be generated on these lines.
If a falling edge on external interrupt line occurs during writing of EXTI_FTSR register, the pending bit will not be set.
Rising and Falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition.
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RM0008 Interrupts and events
Address offset: 0x10
Reset value: 0x0000 0000
31 30 29 28 27 26 25
Reserved
15
SWIER
15 rw
14
SWIER
14 rw
13
SWIER
13 rw
12
SWIER
12 rw
11
SWIER
11 rw
10
SWIER
10 rw
9
SWIER
9 rw
24
8
SWIER
8 rw
23 22 21 20
7
SWIER
7 rw
6
SWIER
6 rw
5
SWIER
5 rw
4
SWIER
4 rw
19
SWIER
19 rw
3
18
SWIER
18 rw
2
SWIER
3 rw
SWIER
2 rw
17
SWIER
17 rw
1
SWIER
1 rw
16
SWIER
16 rw
0
SWIER
0 rw
Bits 31:20 Reserved, must be kept at reset value (0).
Bits 19:0 SWIERx: Software interrupt on line x
If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is set to
'0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a 1 into the bit).
Note: Bit 19 used in connectivity line devices and is reserved otherwise.
10.3.6 Pending register (EXTI_PR)
Address offset: 0x14
Reset value: undefined
31 30 29 28 27
15 14 13 12 11
PR15 PR14 PR13 PR12 PR11
26
Reserved
10
PR10
25
9
PR9
24
8
PR8
23
7
PR7
22
6
PR6
21
5
PR5
20
4
PR4
19 18 17 16
PR19 PR18 PR17 PR16 rc_w1 rc_w1 rc_w1 rc_w1
3 2 1 0
PR3 PR2 PR1 PR0 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:20 Reserved, must be kept at reset value (0).
Bits 19:0 PRx: Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a ‘1’ into the bit.
Note: Bit 19 is used in connectivity line devices only and is reserved otherwise.
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10.3.7 EXTI register map
The following table gives the EXTI register map and the reset values. Bits 19 in all registers are used in connectivity line devices and reserved otherwise.
Table 64. External interrupt/event controller register map and reset values
Offset Register
0x00
0x04
0x08
0x0C
0x10
0x14
EXTI_IMR
Reset value
EXTI_EMR
Reset value
EXTI_RTSR
Reset value
EXTI_FTSR
Reset value
EXTI_SWIER
Reset value
EXTI_PR
Reset value
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MR[19:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MR[19:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TR[19:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TR[19:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SWIER[19:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PR[19:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
for the register boundary addresses.
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RM0008
11
Analog-to-digital converter (ADC)
Analog-to-digital converter (ADC)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to the whole STM32F10xxx family, unless otherwise specified.
The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18 multiplexed channels allowing it measure signals from sixteen external and two internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned
16-bit data register.
The analog watchdog feature allows the application to detect if the input voltage goes outside the user-defined high or low thresholds.
The ADC input clock is generated from the PCLK2 clock divided by a prescaler and it must not exceed 14 MHz, refer to
for low-, medium-, high- and XL-density devices, and to
Figure 11 for connectivity line devices.
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Analog-to-digital converter (ADC) RM0008
11.2 ADC main features
Note:
12-bit resolution
Interrupt generation at End of Conversion, End of Injected conversion and Analog watchdog event
Single and continuous conversion modes
Scan mode for automatic conversion of channel 0 to channel ‘n’
Self-calibration
Data alignment with in-built data coherency
Channel by channel programmable sampling time
External trigger option for both regular and injected conversion
Discontinuous mode
Dual mode (on devices with 2 ADCs or more)
ADC conversion time:
– STM32F103xx performance line devices: 1 µs at 56 MHz (1.17 µs at 72 MHz)
– STM32F101xx access line devices: 1 µs at 28 MHz (1.55 µs at 36 MHz)
– STM32F102xx USB access line devices: 1.2 µs at 48 MHz
– STM32F105xx and STM32F107xx devices: 1 µs at 56 MHz (1.17 µs at 72 MHz)
ADC supply requirement: 2.4 V to 3.6 V
ADC input range: V
REF-
V
IN
V
REF+
DMA request generation during regular channel conversion
The block diagram of the ADC is shown in Figure 22 .
V
REF-
,if available (depending on package), must be tied to V
SSA
.
11.3 ADC functional description
shows a single ADC block diagram and
Table 65 gives the ADC pin description.
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RM0008 Analog-to-digital converter (ADC)
Figure 22. Single ADC block diagram
Interrupt
Flags enable bits
End of conversion
EOC
End of injected conversion
JEOC
Analog watchdog event
AWD
EOCIE
JEOCIE
AWDIE
Analog watchdog
Compare Result
High Threshold (12 bits)
Low Threshold (12 bits)
ADC Interrupt to NVIC
V
REF+
V
REF-
V
DDA
V
SSA
ADCx_IN0
ADCx_IN1
Analog
MUX
Injected data registers
(4 x 16 bits)
Regular data register
(16 bits)
DMA request
GPIO
Ports up to 4 up to 16
Analog to digital converter
ADCCLK
ADCx_IN15
Injected
channels
Regular
channels
Temp. sensor
V
REFINT
JEXTSEL[2:0] bits
TIM1_TRGO
TIM1_CH4
TIM2_TRGO
TIM2_CH1
TIM3_CH4
TIM4_TRGO
JEXTRIG bit
Start trigger
(injected group)
EXTI_15
TIM8_CH4
(2)
ADCx-ETRGINJ_REMAP bit
EXTSEL[2:0] bits
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM2_CH2
TIM3_TRGO
TIM4_CH4
Start trigger
(regular group)
EXTI_11
TIM8_TRGO
(2)
ADCx_ETRGREG_REMAP bit
EXTRIG bit
From ADC prescaler
JEXTSEL[2:0] bits
TIM1_TRGO
TIM1_CH4
TIM4_CH3
TIM8_CH2
TIM8_CH4
TIM5_TRGO
TIM5_CH4
JEXTRIG bit
Start trigger
(injected group)
EXTSEL[2:0] bits
TIM3_CH1
TIM2_CH3
TIM1_CH3
TIM8_CH1
TIM8_TRGO
TIM5_CH1
TIM5_CH3
EXTRIG bit
Start trigger
(regular group)
Triggers for ADC3
(1) ai14802d
1. ADC3 has regular and injected conversion triggers different from those of ADC1 and ADC2.
2. TIM8_CH4 and TIM8_TRGO with their corresponding remap bits exist only in High-density and XL-density products.
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Name Signal type
Table 65. ADC pins
Remarks
V
REF+
V
DDA
(1)
Input, analog reference positive
Input, analog supply
The higher/positive reference voltage for the ADC,
2.4 V V
REF+
V
DDA
Analog power supply equal to V
DD
2.4 V V
DDA
3.6 V
and
The lower/negative reference voltage for the ADC,
V
REF-
= V
SSA
V
V
REF-
SSA
(1)
Input, analog reference negative
Input, analog supply ground
ADCx_IN[15:0] Analog signals
Ground for analog power supply equal to V
Up to 21 analog channels
(2)
1. V
DDA
and V
SSA
have to be connected to V
DD
and V
SS
, respectively.
2. For full details about the ADC I/O pins, refer to the “Pinouts and pin descriptions” section of the corresponding device datasheet.
SS
The ADC can be powered-on by setting the ADON bit in the ADC_CR2 register. When the
ADON bit is set for the first time, it wakes up the ADC from Power Down mode.
Conversion starts when ADON bit is set for a second time by software after ADC power-up time (t
STAB
).
The conversion can be stopped, and the ADC put in power down mode by resetting the
ADON bit. In this mode the ADC consumes almost no power (only a few µA).
The ADCCLK clock provided by the Clock Controller is synchronous with the PCLK2 (APB2 clock). The RCC controller has a dedicated programmable prescaler for the ADC clock,
refer to Low-, medium-, high- and XL-density reset and clock control (RCC) for more details.
218/1136
There are 16 multiplexed channels. It is possible to organize the conversions in two groups: regular and injected. A group consists of a sequence of conversions which can be done on any channel and in any order. For instance, it is possible to do the conversion in the following order: Ch3, Ch8, Ch2, Ch2, Ch0, Ch2, Ch2, Ch15.
The regular group is composed of up to 16 conversions. The regular channels and their order in the conversion sequence must be selected in the ADC_SQRx registers.
The total number of conversions in the regular group must be written in the L[3:0] bits in the ADC_SQR1 register.
The injected group is composed of up to 4 conversions. The injected channels and their order in the conversion sequence must be selected in the ADC_JSQR register.
The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register.
If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current conversion is reset and a new start pulse is sent to the ADC to convert the new chosen group.
RM0008 Rev 21
RM0008 Analog-to-digital converter (ADC)
Note:
Temperature sensor/V
REFINT
internal channels
The temperature sensor is connected to channel ADCx_IN16 and the internal reference voltage V
REFINT
is connected to ADCx_IN17. These two internal channels can be selected and converted as injected or regular channels.
The sensor and V
REFINT
are only available on the master ADC1 peripheral.
11.3.4 Single conversion mode
In Single conversion mode the ADC does one conversion. This mode is started either by setting the ADON bit in the ADC_CR2 register (for a regular channel only) or by external trigger (for a regular or injected channel), while the CONT bit is 0.
Once the conversion of the selected channel is complete:
If a regular channel was converted:
– The converted data is stored in the 16-bit ADC_DR register
– The EOC (End Of Conversion) flag is set
– and an interrupt is generated if the EOCIE is set.
If an injected channel was converted:
– The converted data is stored in the 16-bit ADC_DRJ1 register
– The JEOC (End Of Conversion Injected) flag is set
– and an interrupt is generated if the JEOCIE bit is set.
The ADC is then stopped.
11.3.5 Continuous conversion mode
In continuous conversion mode ADC starts another conversion as soon as it finishes one.
This mode is started either by external trigger or by setting the ADON bit in the ADC_CR2 register, while the CONT bit is 1.
After each conversion:
If a regular channel was converted:
– The converted data is stored in the 16-bit ADC_DR register
– The EOC (End Of Conversion) flag is set
– An interrupt is generated if the EOCIE is set.
If an injected channel was converted:
– The converted data is stored in the 16-bit ADC_DRJ1 register
– The JEOC (End Of Conversion Injected) flag is set
– An interrupt is generated if the JEOCIE bit is set.
As shown in
, the ADC needs a stabilization time of t
STAB
before it starts converting accurately. After the start of ADC conversion and after 14 clock cycles, the EOC flag is set and the 16-bit ADC Data register contains the result of the conversion.
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Analog-to-digital converter (ADC) RM0008
Figure 23. Timing diagram
ADC_CLK
ADON
SWSTART/
JSWSTART
ADC
EOC tSTAB
Start 1st conversion
ADC conversion
Conversion time
(total conv. time)
Start next conversion
Next ADC conversion
Software clears the EOC bit ai16047b
220/1136
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a low threshold or above a high threshold. These thresholds are programmed in the
12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be enabled by using the AWDIE bit in the ADC_CR1 register.
The threshold value is independent of the alignment selected by the ALIGN bit in the
ADC_CR2 register. The comparison is done before the alignment (see
The analog watchdog can be enabled on one or more channels by configuring the
ADC_CR1 register as shown in
Figure 24. Analog watchdog guarded area
Analog voltage
Higher threshold
Lower threshold
HTR
Guarded area
LTR ai16048
Table 66. Analog watchdog channel selection
ADC_CR1 register control bits (x = don’t care)
Channels to be guarded by analog watchdog
AWDSGL bit AWDEN bit JAWDEN bit
None
All injected channels
All regular channels x
0
0
0
0
1
0
1
0
RM0008 Rev 21
RM0008 Analog-to-digital converter (ADC)
Table 66. Analog watchdog channel selection (continued)
ADC_CR1 register control bits (x = don’t care)
Channels to be guarded by analog watchdog
AWDSGL bit AWDEN bit JAWDEN bit
All regular and injected channels
Single
(1)
injected channel
Single
regular channel
Single
regular or injected channel
1. Selected by AWDCH[4:0] bits
0
1
1
1
1
0
1
1
1
1
0
1
This mode is used to scan a group of analog channels.
Scan mode can be selected by setting the SCAN bit in the ADC_CR1 register. Once this bit is set, ADC scans all the channels selected in the ADC_SQRx registers (for regular channels) or in the ADC_JSQR (for injected channels). A single conversion is performed for each channel of the group. After each end of conversion the next channel of the group is converted automatically. If the CONT bit is set, conversion does not stop at the last selected group channel but continues again from the first selected group channel.
When using scan mode, DMA bit must be set and the direct memory access controller is used to transfer the converted data of regular group channels to SRAM after each update of the ADC_DR register.
The injected channel converted data is always stored in the ADC_JDRx registers.
11.3.9 Injected channel management
Note:
Triggered injection
To use triggered injection, the JAUTO bit must be cleared and SCAN bit must be set in the
ADC_CR1 register.
1.
Start conversion of a group of regular channels either by external trigger or by setting the ADON bit in the ADC_CR2 register.
2. If an external injected trigger occurs during the regular group channel conversion, the current conversion is reset and the injected channel sequence is converted in Scan once mode.
3. Then, the regular group channel conversion is resumed from the last interrupted regular conversion. If a regular event occurs during an injected conversion, it doesn’t interrupt it but the regular sequence is executed at the end of the injected sequence.
shows the timing diagram.
When using triggered injection, the interval between trigger events must be longer than the injection sequence. For instance, if the sequence length is 28 ADC clock cycles (that is two conversions with a 1.5 clock-period sampling time), the minimum interval between triggers must be 29 ADC clock cycles.
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Note:
RM0008
Auto-injection
If the JAUTO bit is set, then the injected group channels are automatically converted after the regular group channels. This can be used to convert a sequence of up to 20 conversions programmed in the ADC_SQRx and ADC_JSQR registers.
In this mode, external trigger on injected channels must be disabled.
If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected channels are continuously converted.
For ADC clock prescalers ranging from 4 to 8, a delay of 1 ADC clock period is automatically inserted when switching from regular to injected sequence (respectively injected to regular).
When the ADC clock prescaler is set to 2, the delay is 2 ADC clock periods.
It is not possible to use both auto-injected and discontinuous modes simultaneously.
Figure 25. Injected conversion latency
ADCCLK
Injection event
Reset ADC max latency
(1)
SOC
1. The maximum latency value can be found in the electrical characteristics of the STM32F101xx and
STM32F103xx datasheets.
ai16049
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Regular group
This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to convert a short sequence of n conversions (n <=8) which is a part of the sequence of conversions selected in the ADC_SQRx registers. The value of n is specified by writing to the DISCNUM[2:0] bits in the ADC_CR1 register.
When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx registers until all the conversions in the sequence are done. The total sequence length is defined by the L[3:0] bits in the ADC_SQR1 register.
Example: n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10 first trigger: sequence converted 0, 1, 2. An EOC event is generated at each
RM0008 Rev 21
RM0008
Note:
Note:
Analog-to-digital converter (ADC) conversion second trigger: sequence converted 3, 6, 7. An EOC event is generated at each conversion third trigger: sequence converted 9, 10. An EOC event is generated at each conversion fourth trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion
When a regular group is converted in discontinuous mode, no rollover will occur. When all sub groups are converted, the next trigger starts conversion of the first sub-group.
In the example above, the fourth trigger reconverts the first sub-group channels 0, 1 and 2.
Injected group
This mode is enabled by setting the JDISCEN bit in the ADC_CR1 register. It can be used to convert the sequence selected in the ADC_JSQR register, channel by channel, after an external trigger event.
When an external trigger occurs, it starts the next channel conversions selected in the
ADC_JSQR registers until all the conversions in the sequence are done. The total sequence length is defined by the JL[1:0] bits in the ADC_JSQR register.
Example: n = 1, channels to be converted = 1, 2, 3 first trigger: channel 1 converted second trigger: channel 2 converted third trigger: channel 3 converted and EOC and JEOC events generated fourth trigger: channel 1
When all injected channels are converted, the next trigger starts the conversion of the first injected channel. In the example above, the fourth trigger reconverts the first injected channel 1.
It is not possible to use both auto-injected and discontinuous modes simultaneously.
The user must avoid setting discontinuous mode for both regular and injected groups together. Discontinuous mode must be enabled only for one group conversion.
11.4 Calibration
Note:
The ADC has an built-in self calibration mode. Calibration significantly reduces accuracy errors due to internal capacitor bank variations. During calibration, an error-correction code
(digital word) is calculated for each capacitor, and during all subsequent conversions, the error contribution of each capacitor is removed using this code.
Calibration is started by setting the CAL bit in the ADC_CR2 register. Once calibration is over, the CAL bit is reset by hardware and normal conversion can be performed. It is recommended to calibrate the ADC once at power-on. The calibration codes are stored in the ADC_DR as soon as the calibration phase ends.
It is recommended to perform a calibration after each power-up.
Before starting a calibration, the ADC must have been in power-on state (ADON bit = ‘1’) for at least two ADC clock cycles.
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Figure 26. Calibration timing diagram
CLK
CAL
ADC
Conversion
Calibration ongoing t
CAL
Calibration Reset by Hardware
Normal ADC Conversion
RM0008
ALIGN bit in the ADC_CR2 register selects the alignment of data stored after conversion.
Data can be left or right aligned as shown in
and
The injected group channels converted data value is decreased by the user-defined offset written in the ADC_JOFRx registers so the result can be a negative value. The SEXT bit is the extended sign value.
For regular group channels no offset is subtracted so only twelve bits are significant.
Figure 27. Right alignment of data
Injected group
SEXT SEXT SEXT SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Regular group
0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ai16050
Figure 28. Left alignment of data
Injected group
SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0
Regular group
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 ai16051
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ADC samples the input voltage for a number of ADC_CLK cycles which can be modified using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be sampled with a different sample time.
The total conversion time is calculated as follows:
Tconv = Sampling time + 12.5 cycles
Example:
With an ADCCLK = 14 MHz and a sampling time of 1.5 cycles:
Tconv = 1.5 + 12.5 = 14 cycles = 1 µs
11.7 Conversion on external trigger
Note:
Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the EXT-
TRIG control bit is set then external events are able to trigger a conversion. The EXT-
SEL[2:0] and JEXTSEL[2:0] control bits allow the application to select decide which out of 8 possible events can trigger conversion for the regular and injected groups.
When an external trigger is selected for ADC regular or injected conversion, only the rising edge of the signal can start the conversion.
Table 67. External trigger for regular channels for ADC1 and ADC2
Source Type EXTSEL[2:0]
TIM1_CC1 event
TIM1_CC2 event
TIM1_CC3 event
TIM2_CC2 event
TIM3_TRGO event
TIM4_CC4 event
Internal signal from on-chip timers
EXTI line 11 / TIM8_TRGO event
(1)(2)
External pin / Internal signal from on-chip timers
Software control bit
110
SWSTART 111
1. The TIM8_TRGO event exists only in high-density and XL-density devices.
2. The selection of the external trigger EXTI line11 or TIM8_TRGO event for regular channels is done, respectively. through configuration bits ADC1_ETRGREG_REMAP and ADC2_ETRGREG_REMAP for
ADC1 and ADC2.
000
001
010
011
100
101
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Table 68. External trigger for injected channels for ADC1 and ADC2
Source Connection type JEXTSEL[2:0]
TIM1_TRGO event
TIM1_CC4 event
TIM2_TRGO event
TIM2_CC1 event
TIM3_CC4 event
TIM4_TRGO event
Internal signal from on-chip timers
000
001
010
011
100
101
EXTI line 15/TIM8_CC4 event
(1)(2)
External pin/Internal signal from onchip timers
Software control bit
110
JSWSTART 111
1. The TIM8_CC4 event exists only in high-density and XL-density devices.
2. The selection of the external trigger EXTI line15 or TIM8_CC4 event for injected channels is done through configuration bits ADC1_ETRGINJ_REMAP and ADC2_ETRGINJ_REMAP for ADC1 and ADC2, respectively.
Table 69. External trigger for regular channels for ADC3
Source Connection type EXTSEL[2:0]
TIM3_CC1 event
TIM2_CC3 event
TIM1_CC3 event
TIM8_CC1 event
TIM8_TRGO event
TIM5_CC1 event
TIM5_CC3 event
SWSTART
Internal signal from on-chip timers
Software control bit
000
001
010
011
100
101
110
111
Table 70. External trigger for injected channels for ADC3
Source Connection type JEXTSEL[2:0]
TIM1_TRGO event
TIM1_CC4 event
TIM4_CC3 event
TIM8_CC2 event
TIM8_CC4 event
TIM5_TRGO event
TIM5_CC4 event
JSWSTART
Internal signal from on-chip timers
Software control bit
100
101
110
111
000
001
010
011
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RM0008 Analog-to-digital converter (ADC)
The software source trigger events can be generated by setting a bit in a register
(SWSTART and JSWSTART in ADC_CR2).
A regular group conversion can be interrupted by an injected trigger.
Note:
Since converted regular channels value are stored in a unique data register, it is necessary to use DMA for conversion of more than one regular channel. This avoids the loss of data already stored in the ADC_DR register.
Only the end of conversion of a regular channel generates a DMA request, which allows the transfer of its converted data from the ADC_DR register to the destination location selected by the user.
Only ADC1 and ADC3 have this DMA capability. ADC2-converted data can be transferred in dual ADC mode using DMA thanks to master ADC1.
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Note:
Note:
In devices with two ADCs or more, dual ADC mode can be used (see
).
In dual ADC mode the start of conversion is triggered alternately or simultaneously by the
ADC1 master to the ADC2 slave, depending on the mode selected by the DUALMOD[2:0] bits in the ADC1_CR1 register.
In dual mode, when configuring conversion to be triggered by an external event, the user must set the trigger for the master only and set a software trigger for the slave to prevent spurious triggers to start unwanted slave conversion. However, external triggers must be enabled on both master and slave ADCs.
The following six possible modes are implemented:
– Injected simultaneous mode
– Regular simultaneous mode
– Fast interleaved mode
– Slow interleaved mode
– Alternate trigger mode
– Independent mode
It is also possible to use the previous modes combined in the following ways:
– Injected simultaneous mode + Regular simultaneous mode
– Regular simultaneous mode + Alternate trigger mode
– Injected simultaneous mode + Interleaved mode
In dual ADC mode, to read the slave converted data on the master data register, the DMA bit must be enabled even if it is not used to transfer converted regular channel data.
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RM0008 Analog-to-digital converter (ADC)
Figure 29. Dual ADC block diagram (1)
Regular data register
Injected data registers
(4 x 16 bits)
ADCx_IN0
ADCx_IN1
ADCx_IN15
GPIO
Ports
Temp. sensor
V
REFINT
EXTI_11
Start trigger mux
(regular group)
EXTI_15
Start trigger mux
(injected group)
Regular
channels injected
channels internal triggers
ADC2 (Slave)
Regular data register
(16 bits) (2)
Injected data registers
(4 x 16 bits)
Regular
channels
Injected
channels
Dual mode
control
ADC1 (Master)
1.
External triggers are present on ADC2 but are not shown for the purposes of this diagram.
2.
In some dual ADC modes, the ADC1 data register (ADC1_DR) contains both ADC1 and ADC2 regular converted data over the entire 32 bits.
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11.9.1 Injected simultaneous mode
Note:
Note:
This mode converts an injected channel group. The source of external trigger comes from the injected group mux of ADC1 (selected by the JEXTSEL[2:0] bits in the ADC1_CR2 register). A simultaneous trigger is provided to ADC2.
Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel).
At the end of conversion event on ADC1 or ADC2:
The converted data is stored in the ADC_JDRx registers of each ADC interface.
An JEOC interrupt is generated (if enabled on one of the two ADC interfaces) when the
ADC1/ADC2 injected channels are all converted.
In simultaneous mode, exactly the same sampling time should be configured for the two channels that will be sampled simultaneously by ACD1 and ADC2.
Figure 30. Injected simultaneous mode on 4 channels
ADC2
ADC1
Trigger
CH0
CH3
CH1
CH2
CH2
CH1
Sampling
Conversion
CH3
CH0
End of injected conversion on ADC1 and ADC2
11.9.2 Regular simultaneous mode
Note:
Note:
This mode is performed on a regular channel group. The source of the external trigger comes from the regular group mux of ADC1 (selected by the EXTSEL[2:0] bits in the
ADC1_CR2 register). A simultaneous trigger is provided to the ADC2.
Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel).
At the end of conversion event on ADC1 or ADC2:
A 32-bit DMA transfer request is generated (if DMA bit is set) which transfers to SRAM the ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the ADC1 converted data in the lower halfword.
An EOC interrupt is generated (if enabled on one of the two ADC interfaces) when
ADC1/ADC2 regular channels are all converted.
In regular simultaneous mode, exactly the same sampling time should be configured for the two channels that will be sampled simultaneously by ACD1 and ADC2.
Figure 31. Regular simultaneous mode on 16 channels
ADC1
ADC2
Trigger
CH0
CH15
CH1
CH14
CH2
CH13
CH3
CH12
...
...
Sampling
Conversion
CH15
CH0
End of conversion on ADC1 and ADC2
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RM0008 Analog-to-digital converter (ADC)
11.9.3 Fast interleaved mode
Note:
This mode can be started only on a regular channel group (usually one channel). The source of external trigger comes from the regular channel mux of ADC1. After an external trigger occurs:
ADC2 starts immediately and
ADC1 starts after a delay of 7 ADC clock cycles.
If CONT bit is set on both ADC1 and ADC2 the selected regular channels of both ADCs are continuously converted.
After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit
DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the
ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the
ADC1 converted data in the lower half-word.
The maximum sampling time allowed is <7 ADCCLK cycles to avoid the overlap between
ADC1 and ADC2 sampling phases in the event that they convert the same channel.
Figure 32. Fast interleaved mode on 1 channel in continuous conversion mode
End of conversion on ADC2
Sampling
Conversion
ADC2
ADC1
CH0
CH0
...
...
CH0
CH0
Trigger
End of conversion on ADC1
7 ADCCLK cycles
MS40509V1
11.9.4 Slow interleaved mode
Note:
Note:
This mode can be started only on a regular channel group (only one channel). The source of external trigger comes from regular channel mux of ADC1. After external trigger occurs:
ADC2 starts immediately and
ADC1 starts after a delay of 14 ADC clock cycles.
ADC2 starts after a second delay of 14 ADC cycles, and so on.
The maximum sampling time allowed is <14 ADCCLK cycles to avoid an overlap with the next conversion.
After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit
DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the
ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the
ADC1 converted data in the lower halfword.
A new ADC2 start is automatically generated after 28 ADC clock cycles
CONT bit can not be set in the mode since it continuously converts the selected regular channel.
The application must ensure that no external trigger for injected channel occurs when interleaved mode is enabled.
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Analog-to-digital converter (ADC)
Figure 33. Slow interleaved mode on 1 channel
End of conversion on ADC2
ADC2
ADC1
Trigger
CH0
CH0
CH0
CH0
End of conversion on ADC1
14 ADCCLK cycles
28 ADCCLK cycles
RM0008
Sampling
Conversion
232/1136
This mode can be started only on an injected channel group. The source of external trigger comes from the injected group mux of ADC1.
When the first trigger occurs, all injected group channels in ADC1 are converted.
When the second trigger arrives, all injected group channels in ADC2 are converted
and so on.
A JEOC interrupt, if enabled, is generated after all injected group channels of ADC1 are converted.
A JEOC interrupt, if enabled, is generated after all injected group channels of ADC2 are converted.
If another external trigger occurs after all injected group channels have been converted then the alternate trigger process restarts by converting ADC1 injected group channels.
1 st
trigger
Figure 34. Alternate trigger: injected channel group of each ADC
3 rd
trigger n th
trigger
EOC, JEOC on ADC1
EOC, JEOC on ADC1
Sampling
Conversion
ADC1
ADC2
...
2 nd
trigger
EOC, JEOC on ADC2
4 th
trigger
EOC, JEOC on ADC2
(n+1) th
trigger
MS47570V1
If the injected discontinuous mode is enabled for both ADC1 and ADC2:
When the first trigger occurs, the first injected channel in ADC1 is converted.
When the second trigger arrives, the first injected channel in ADC2 are converted
and so on....
A JEOC interrupt, if enabled, is generated after all injected group channels of ADC1 are converted.
A JEOC interrupt, if enabled, is generated after all injected group channels of ADC2 are converted.
RM0008 Rev 21
RM0008 Analog-to-digital converter (ADC)
If another external trigger occurs after all injected group channels have been converted then the alternate trigger process restarts.
Figure 35. Alternate trigger: 4 injected channels (each ADC) in discontinuous model first trigger third trigger 5th trigger 7th trigger
JEOC on ADC1
Sampling
Conversion
ADC1
ADC2 second trigger fourth trigger 6th trigger 8th trigger
JEOC on ADC2
In this mode the dual ADC synchronization is bypassed and each ADC interfaces works independently.
11.9.7 Combined regular/injected simultaneous mode
Note:
It is possible to interrupt simultaneous conversion of a regular group to start simultaneous conversion of an injected group.
In combined regular/injected simultaneous mode, exactly the same sampling time should be configured for the two channels that will be sampled simultaneously by ACD1 and ADC2.
11.9.8 Combined regular simultaneous + alternate trigger mode
Note:
It is possible to interrupt regular group simultaneous conversion to start alternate trigger conversion of an injected group.
Figure 36 shows the behavior of an alternate trigger
interrupting a regular simultaneous conversion.
The injected alternate conversion is immediately started after the injected event arrives. If regular conversion is already running, in order to ensure synchronization after the injected conversion, the regular conversion of both (master/slave) ADCs is stopped and resumed synchronously at the end of the injected conversion.
In combined regular simultaneous + alternate trigger mode, exactly the same sampling time should be configured for the two channels that will be sampled simultaneously by ACD1 and
ADC2.
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Figure 36. Alternate + Regular simultaneous
1
st
trigger
RM0008
ADC MASTER reg
CH1 CH2 CH3 CH3 CH4 CH4 CH5
ADC MASTER inj
CH1
ADC SLAVE reg
CH5 CH6 CH7 CH7 CH8 CH8 CH9
ADC SLAVE inj
CH1
Synchro not lost
2
nd
trigger
MS47571V1
If a trigger occurs during an injected conversion that has interrupted a regular conversion, it
shows the behavior in this case (the second trigger is ignored).
Figure 37. Case of trigger occurring during injected conversion
1st trigger 3rd trigger
ADC1 reg
ADC1 inj
ADC2 reg
ADC2 inj
CH0
CH3
CH1
CH5
CH2
CH0
CH6
CH2
CH6
CH3
CH7
CH0
CH3
CH7
CH4
CH0
CH8
2nd trigger 2nd trigger ai16063
11.9.9 Combined injected simultaneous + interleaved
Note:
It is possible to interrupt an interleaved conversion with an injected event. In this case the interleaved conversion is interrupted and the injected conversion starts, at the end of the injected sequence the interleaved conversion is resumed.
shows the behavior using an example.
When the ADC clock prescaler is set to 4, the interleaved mode does not recover with evenly spaced sampling periods: the sampling interval is 8 ADC clock periods followed by 6
ADC clock periods, instead of 7 clock periods followed by 7 clock periods.
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RM0008 Analog-to-digital converter (ADC)
Figure 38. Interleaved single channel with injected sequence CH11, CH12
ADC1
ADC2 CH0
CH0
CH0
CH0
CH0
CH0
Sampling
Conversion
Trigger
CH11
CH12
CH12
CH11
CH0 CH0
CH0 CH0
Note:
The temperature sensor can be used to measure the junction temperature (T
J device.
) of the
The temperature sensor is internally connected to the ADCx_IN16 input channel which is used to convert the sensor output voltage into a digital value. The recommended sampling time for the temperature sensor is 17.1 µs.
The block diagram of the temperature sensor is shown in
When not in use, this sensor can be put in power down mode.
The TSVREFE bit must be set to enable both internal channels: ADCx_IN16 (temperature sensor) and ADCx_IN17 (V
REFINT
) conversion.
The temperature sensor output voltage changes linearly with temperature. The offset of this line varies from chip to chip due to process variations (up to 45 °C from one chip to another).
The internal temperature sensor is more suited to applications that detect temperature variations instead of absolute temperatures. If accurate temperature readings are needed, an external temperature sensor part should be used.
Figure 39. Temperature sensor and V
REFINT
channel block diagram
TSVREFE control bit
Temperature sensor
Internal power block
VSENSE
VREFINT
ADC1_IN16
ADC1
ADC1_IN17
Converted data
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Note:
RM0008
Reading the temperature
To use the sensor:
1.
Select the ADCx_IN16 input channel.
2. Select a sample time of 17.1 µs
3. Set the TSVREFE bit in the ADC control register 2 (ADC_CR2)
to wake up the temperature sensor from power down mode.
4. Start the ADC conversion by setting the ADON bit (or by external trigger).
5. Read the resulting V
SENSE
data in the ADC data register
6. Obtain the temperature using the following formula:
Temperature (in °C) = {(V
25
- V
SENSE
) / Avg_Slope} + 25.
Where,
V
25
= V
SENSE
value for 25° C and
Avg_Slope = Average Slope for curve between Temperature vs. V
SENSE mV/° C or µV/ °C).
(given in
Refer to the Electrical characteristics section for the actual values of V
25
Avg_Slope.
and
The sensor has a startup time after waking from power down mode before it can output
V
SENSE
at the correct level. The ADC also has a startup time after power-on, so to minimize the delay, the ADON and TSVREFE bits should be set at the same time.
Note:
An interrupt can be produced on end of conversion for regular and injected groups and when the analog watchdog status bit is set. Separate interrupt enable bits are available for flexibility.
ADC1 and ADC2 interrupts are mapped onto the same interrupt vector. ADC3 interrupts are mapped onto a separate interrupt vector.
Two other flags are present in the ADC_SR register, but there is no interrupt associated with them:
JSTRT (Start of conversion for injected group channels)
STRT (Start of conversion for regular group channels)
Table 71. ADC interrupts
Interrupt event Event flag
End of conversion regular group
End of conversion injected group
Analog watchdog status bit is set
EOC
JEOC
AWD
Enable Control bit
EOCIE
JEOCIE
AWDIE
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RM0008 Analog-to-digital converter (ADC)
Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).
11.12.1 ADC status register (ADC_SR)
Address offset: 0x00
Reset value: 0x0000 0000
31
15
30 29 28 27 26 25
11 10
Reserved
9
24 23
8
Reserved
7
22 21 20 19 18 17 16
14 13 12 6 5 4 3 2 1 0
STRT JSTRT JEOC EOC AWD rc_w0 rc_w0 rc_w0 rc_w0 rc_w0
Bits 31:5 Reserved, must be kept at reset value.
Bit 4 STRT: Regular channel Start flag
This bit is set by hardware when regular channel conversion starts. It is cleared by software.
0: No regular channel conversion started
1: Regular channel conversion has started
Bit 3 JSTRT: Injected channel Start flag
This bit is set by hardware when injected channel group conversion starts. It is cleared by software.
0: No injected group conversion started
1: Injected group conversion has started
Bit 2 JEOC: Injected channel end of conversion
This bit is set by hardware at the end of all injected group channel conversion. It is cleared by software.
0: Conversion is not complete
1: Conversion complete
Bit 1 EOC: End of conversion
This bit is set by hardware at the end of a group channel conversion (regular or injected). It is cleared by software or by reading the ADC_DR.
0: Conversion is not complete
1: Conversion complete
Bit 0 AWD: Analog watchdog flag
This bit is set by hardware when the converted voltage crosses the values programmed in the ADC_LTR and ADC_HTR registers. It is cleared by software.
0: No Analog watchdog event occurred
1: Analog watchdog event occurred
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Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
15 14 13 rw
DISCNUM[2:0] rw rw
28 27
Reserved
26 25
12
JDISCE
N rw
11
DISC
EN rw
10
JAUTO rw
9
AWD
SGL rw
24
8
SCAN rw
23
AWDE
N rw
7
JEOC
IE rw
22
JAWDE
N rw
6
AWDIE rw
21 20
Reserved
5
EOCIE rw
4 rw
19 rw
3
18 17
DUALMOD[3:0] rw
2 rw
1 rw
AWDCH[4:0] rw rw
16 rw
0 rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 AWDEN: Analog watchdog enable on regular channels
This bit is set/reset by software.
0: Analog watchdog disabled on regular channels
1: Analog watchdog enabled on regular channels
Bit 22 JAWDEN: Analog watchdog enable on injected channels
This bit is set/reset by software.
0: Analog watchdog disabled on injected channels
1: Analog watchdog enabled on injected channels
Bits 21:20 Reserved, must be kept at reset value.
Bits 19:16 DUALMOD[3:0] : Dual mode selection
These bits are written by software to select the operating mode.
0000: Independent mode.
0001: Combined regular simultaneous + injected simultaneous mode
0010: Combined regular simultaneous + alternate trigger mode
0011: Combined injected simultaneous + fast interleaved mode
0100: Combined injected simultaneous + slow Interleaved mode
0101: Injected simultaneous mode only
0110: Regular simultaneous mode only
0111: Fast interleaved mode only
1000: Slow interleaved mode only
1001: Alternate trigger mode only
Note: These bits are reserved in ADC2 and ADC3.
In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change.
Bits 15:13 DISCNUM[2:0] : Discontinuous mode channel count
These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger.
000: 1 channel
001: 2 channels
.......
111: 8 channels
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Bit 12 JDISCEN : Discontinuous mode on injected channels
This bit set and cleared by software to enable/disable discontinuous mode on injected group channels
0: Discontinuous mode on injected channels disabled
1: Discontinuous mode on injected channels enabled
Bit 11 DISCEN : Discontinuous mode on regular channels
This bit set and cleared by software to enable/disable Discontinuous mode on regular channels.
0: Discontinuous mode on regular channels disabled
1: Discontinuous mode on regular channels enabled
Bit 10 JAUTO: Automatic Injected Group conversion
This bit set and cleared by software to enable/disable automatic injected group conversion after regular group conversion.
0: Automatic injected group conversion disabled
1: Automatic injected group conversion enabled
Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode
This bit set and cleared by software to enable/disable the analog watchdog on the channel identified by the AWDCH[4:0] bits.
0: Analog watchdog enabled on all channels
1: Analog watchdog enabled on a single channel
Bit 8 SCAN: Scan mode
This bit is set and cleared by software to enable/disable Scan mode. In Scan mode, the inputs selected through the ADC_SQRx or ADC_JSQRx registers are converted.
0: Scan mode disabled
1: Scan mode enabled
Note: An EOC or JEOC interrupt is generated only on the end of conversion of the last channel if the corresponding EOCIE or JEOCIE bit is set
Bit 7 JEOCIE : Interrupt enable for injected channels
This bit is set and cleared by software to enable/disable the end of conversion interrupt for injected channels.
0: JEOC interrupt disabled
1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
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Analog-to-digital converter (ADC) RM0008
Bit 6 AWDIE : Analog watchdog interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Bit 5 EOCIE: Interrupt enable for EOC
This bit is set and cleared by software to enable/disable the End of Conversion interrupt.
0: EOC interrupt disabled
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits
These bits are set and cleared by software. They select the input channel to be guarded by the Analog watchdog.
00000: ADC analog Channel0
00001: ADC analog Channel1
....
01111: ADC analog Channel15
10000: ADC analog Channel16
10001: ADC analog Channel17
Other values: reserved.
Note: ADC1 analog Channel16 and Channel17 are internally connected to the temperature sensor and to V
REFINT
, respectively.
ADC2 analog inputs Channel16 and Channel17 are internally connected to V
SS
.
ADC3 analog inputs Channel9, Channel14, Channel15, Channel16 and Channel17 are connected to V
SS
.
Address offset: 0x08
Reset value: 0x0000 0000
30 29 28 27 26 25 31
Reserved
15
JEXTT
RIG rw
14 13 12 rw
JEXTSEL[2:0] rw rw
11
ALIGN rw
10 9
Reserved
Res.
24
8
DMA rw
23
TSVRE
FE rw
7
22
SWSTA
RT rw
6
21
JSWST
ART rw
5
20
EXTTR
IG rw
4
Reserved
19 18
EXTSEL[2:0]
17 rw
3
RST
CAL rw rw
2
CAL rw rw
1
CONT rw
16
Res.
0
ADON rw
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RM0008 Analog-to-digital converter (ADC)
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 TSVREFE : Temperature sensor and V
REFINT
enable
This bit is set and cleared by software to enable/disable the temperature sensor and V
REFINT channel. In devices with dual ADCs this bit is present only in ADC1.
0: Temperature sensor and V
REFINT
1: Temperature sensor and V
REFINT
channel disabled
channel enabled
Bit 22 SWSTART : Start conversion of regular channels
This bit is set by software to start conversion and cleared by hardware as soon as conversion starts. It starts a conversion of a group of regular channels if SWSTART is selected as trigger event by the EXTSEL[2:0] bits.
0: Reset state
1: Starts conversion of regular channels
Bit 21 JSWSTART : Start conversion of injected channels
This bit is set by software and cleared by software or by hardware as soon as the conversion starts. It starts a conversion of a group of injected channels (if JSWSTART is selected as trigger event by the JEXTSEL[2:0] bits.
0: Reset state
1: Starts conversion of injected channels
Bit 20 EXTTRIG : External trigger conversion mode for regular channels
This bit is set and cleared by software to enable/disable the external trigger used to start conversion of a regular channel group.
0: Conversion on external event disabled
1: Conversion on external event enabled
Bits 19:17 EXTSEL[2:0] : External event select for regular group
These bits select the external event used to trigger the start of conversion of a regular group:
For ADC1 and ADC2, the assigned triggers are:
000: Timer 1 CC1 event
001: Timer 1 CC2 event
010: Timer 1 CC3 event
011: Timer 2 CC2 event
100: Timer 3 TRGO event
101: Timer 4 CC4 event
110: EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XLdensity devices)
111: SWSTART
For ADC3, the assigned triggers are:
000: Timer 3 CC1 event
001: Timer 2 CC3 event
010: Timer 1 CC3 event
011: Timer 8 CC1 event
100: Timer 8 TRGO event
101: Timer 5 CC1 event
110: Timer 5 CC3 event
111: SWSTART
Bit 16 Reserved, must be kept at reset value.
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Analog-to-digital converter (ADC) RM0008
Bit 15 JEXTTRIG : External trigger conversion mode for injected channels
This bit is set and cleared by software to enable/disable the external trigger used to start conversion of an injected channel group.
0: Conversion on external event disabled
1: Conversion on external event enabled
Bits 14:12 JEXTSEL[2:0] : External event select for injected group
These bits select the external event used to trigger the start of conversion of an injected group:
For ADC1 and ADC2 the assigned triggers are:
000: Timer 1 TRGO event
001: Timer 1 CC4 event
010: Timer 2 TRGO event
011: Timer 2 CC1 event
100: Timer 3 CC4 event
101: Timer 4 TRGO event
110: EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XLdensity devices)
111: JSWSTART
For ADC3 the assigned triggers are:
000: Timer 1 TRGO event
001: Timer 1 CC4 event
010: Timer 4 CC3 event
011: Timer 8 CC2 event
100: Timer 8 CC4 event
101: Timer 5 TRGO event
110: Timer 5 CC4 event
111: JSWSTART
Bit 11 ALIGN : Data alignment
This bit is set and cleared by software. Refer to
and
0: Right Alignment
1: Left Alignment
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 DMA : Direct memory access mode
This bit is set and cleared by software. Refer to the DMA controller chapter for more details.
0: DMA mode disabled
1: DMA mode enabled
Only ADC1 and ADC3 can generate a DMA request.
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 RSTCAL: Reset calibration
This bit is set by software and cleared by hardware. It is cleared after the calibration registers are initialized.
0: Calibration register initialized.
1: Initialize calibration register.
Note: If RSTCAL is set when conversion is ongoing, additional cycles are required to clear the calibration registers.
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Bit 2 CAL: A/D Calibration
This bit is set by software to start the calibration. It is reset by hardware after calibration is complete.
0: Calibration completed
1: Enable calibration
Bit 1 CONT: Continuous conversion
This bit is set and cleared by software. If set conversion takes place continuously till this bit is reset.
0: Single conversion mode
1: Continuous conversion mode
Bit 0 ADON : A/D converter ON / OFF
This bit is set and cleared by software. If this bit holds a value of zero and a 1 is written to it then it wakes up the ADC from Power Down state.
Conversion starts when this bit holds a value of 1 and a 1 is written to it. The application should allow a delay of t
STAB between power up and start of conversion. Refer to
0: Disable ADC conversion/calibration and go to power down mode.
1: Enable ADC and to start conversion
Note: If any other bit in this register apart from ADON is changed at the same time, then conversion is not triggered. This is to prevent triggering an erroneous conversion.
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31
15
SMP
15_0 rw
Address offset: 0x0C
Reset value: 0x0000 0000
29 28 27 26 25 30
Reserved
14 13 12 rw
SMP14[2:0] rw rw
11 10 9 rw
SMP13[2:0] rw rw
24
8
23 rw
7
22
SMP17[2:0] rw
6
21 rw
5 rw
SMP12[2:0] rw rw
20 rw
4
19
SMP16[2:0] rw
3 rw
SMP11[2:0] rw rw
18 rw
2
17 rw
1
16
SMP15[2:1] rw
0 rw
SMP10[2:0] rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:0 SMPx[2:0]: Channel x Sample time selection
These bits are written by software to select the sample time individually for each channel.
During sample cycles channel selection bits must remain unchanged.
000: 1.5 cycles
001: 7.5 cycles
010: 13.5 cycles
011: 28.5 cycles
100: 41.5 cycles
101: 55.5 cycles
110: 71.5 cycles
111: 239.5 cycles
Note: ADC1 analog Channel16 and Channel 17 are internally connected to the temperature sensor and to V
REFINT
, respectively.
ADC2 analog input Channel16 and Channel17 are internally connected to V
SS
.
ADC3 analog inputs Channel14, Channel15, Channel16 and Channel17 are connected to V
SS
.
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RM0008 Analog-to-digital converter (ADC)
31 30
Reserved
Res.
15 14
SMP
5_0 rw rw
Address offset: 0x10
Reset value: 0x0000 0000
29 rw
13
28
SMP9[2:0] rw
12
SMP4[2:0] rw rw
27 rw
11 rw
26 rw
10
SMP3[2:0] rw
25
SMP8[2:0] rw
9 rw
24 rw
8 rw
23 rw
7
SMP2[2:0] rw
22
SMP7[2:0] rw
6 rw
21 rw
5 rw
20 rw
4
SMP1[2:0] rw
19
SMP6[2:0] rw
3 rw
18 rw
2 rw
17 16
SMP5[2:1] rw
1 rw
0
SMP0[2:0] rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:0 SMPx[2:0]: Channel x Sample time selection
These bits are written by software to select the sample time individually for each channel.
During sample cycles channel selection bits must remain unchanged.
000: 1.5 cycles
001: 7.5 cycles
010: 13.5 cycles
011: 28.5 cycles
100: 41.5 cycles
101: 55.5 cycles
110: 71.5 cycles
111: 239.5 cycles
Note: ADC3 analog input Channel9 is connected to V
SS
.
11.12.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)
31 30
Address offset: 0x14-0x20
Reset value: 0x0000 0000
29 28 27 26 25 22 21 20 19 18 17
15 14 13 12 11 10 9
24 23
Reserved
8 7 4 3 2 1
Reserved rw rw rw rw rw
6 5
JOFFSETx[11:0] rw rw rw rw rw rw
16
0 rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 JOFFSETx[11:0] : Data offset for injected channel x
These bits are written by software to define the offset to be subtracted from the raw converted data when converting injected channels. The conversion result can be read from in the ADC_JDRx registers.
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11.12.7 ADC watchdog high threshold register (ADC_HTR)
31 30
Address offset: 0x24
Reset value: 0x0000 0FFF
29 28 27 26 25 22 21 20
15 14 13 12 11 10 9
24 23
Reserved
8 7 4
Reserved rw rw rw rw rw
6
HT[11:0]
5 rw rw rw
19
3 rw
18
2
17
1 rw rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 HT[11:0]: Analog watchdog high threshold
These bits are written by software to define the high threshold for the analog watchdog.
16
0 rw
Note: The software can write to these registers when an ADC conversion is ongoing. The programmed value will be effective when the next conversion is complete. Writing to this register is performed with a write delay that can create uncertainty on the effective time at which the new value is programmed.
11.12.8 ADC watchdog low threshold register (ADC_LTR)
31 30
Address offset: 0x28
Reset value: 0x0000 0000
29 28 27 26 25 22 21 20
15 14 13 12 11 10 9
24 23
8
Reserved
7 4
Reserved rw rw rw rw rw
6 5 rw
LT[11:0] rw rw
19
3
18
2
17
1 rw rw rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 LT[11:0]: Analog watchdog low threshold
These bits are written by software to define the low threshold for the analog watchdog.
16
0 rw
Note: The software can write to these registers when an ADC conversion is ongoing. The programmed value will be effective when the next conversion is complete. Writing to this register is performed with a write delay that can create uncertainty on the effective time at which the new value is programmed.
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RM0008 Analog-to-digital converter (ADC)
31
15
SQ16_0 rw
30
Address offset: 0x2C
Reset value: 0x0000 0000
29 28 27 26 25
14 rw
Reserved
13 rw
12
SQ15[4:0] rw
11 rw
10 rw
9 rw
24 23
8 rw rw
7
SQ14[4:0] rw
22
L[3:0]
21 rw
6 rw
5 rw rw
20 rw
4
19 rw
3 rw
18 17
SQ16[4:1] rw
2 rw
1
SQ13[4:0] rw rw
16 rw
0 rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:20 L[3:0] : Regular channel sequence length
These bits are written by software to define the total number of conversions in the regular channel conversion sequence.
0000: 1 conversion
0001: 2 conversions
.....
1111: 16 conversions
Bits 19:15 SQ16[4:0] : 16th conversion in regular sequence
These bits are written by software with the channel number (0..17) assigned as the 16th in the conversion sequence.
Bits 14:10 SQ15[4:0] : 15th conversion in regular sequence
Bits 9:5 SQ14[4:0] : 1fourth conversion in regular sequence
Bits 4:0 SQ13[4:0] : 13th conversion in regular sequence
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31 30
Reserved
15
SQ10_
0 rw
14 rw
Address offset: 0x30
Reset value: 0x0000 0000
29 rw
13
28 rw
12
27
SQ12[4:0] rw
11
26 rw
10 rw
SQ9[4:0] rw rw rw
25 rw
9 rw
24 rw
8 rw
23 rw
7
SQ8[4:0] rw
22
SQ11[4:0] rw
6 rw
21 rw
5 rw
20 rw
4
19 rw
3 rw
18 17
SQ10[4:1] rw
2 rw
1
SQ7[4:0] rw rw
16 rw
0 rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:26 SQ12[4:0] : 1 2th conversion in regular sequence
These bits are written by software with the channel number (0..17) assigned as the 12th in the sequence to be converted.
Bits 24:20 SQ11[4:0] : 11th conversion in regular sequence
Bits 19:15 SQ10[4:0] : 10th conversion in regular sequence
Bits 14:10 SQ9[4:0]: 9th conversion in regular sequence
Bits 9:5 SQ8[4:0] : 8th conversion in regular sequence
Bits 4:0 SQ7[4:0] : 7th conversion in regular sequence
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RM0008 Analog-to-digital converter (ADC)
31 30
Reserved
15
SQ4_0 rw
14 rw
Address offset: 0x34
Reset value: 0x0000 0000
29 rw
13 rw
28 rw
12
SQ3[4:0] rw
27
SQ6[4:0] rw
11 rw
26 rw
10 rw
25 rw
9 rw
24 rw
8 rw
23 rw
7
SQ2[4:0] rw
22
SQ5[4:0] rw
6 rw
21 rw
5 rw
20 rw
4
19 rw
3 rw
18 17
SQ4[4:1] rw
2 rw
1
SQ1[4:0] rw rw
16 rw
0 rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:25 SQ6[4:0] : 6th conversion in regular sequence
These bits are written by software with the channel number (0..17) assigned as the 6th in the sequence to be converted.
Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence
Bits 19:15 SQ4[4:0] : fourth conversion in regular sequence
Bits 14:10 SQ3[4:0] : third conversion in regular sequence
Bits 9:5 SQ2[4:0]: second conversion in regular sequence
Bits 4:0 SQ1[4:0] : first conversion in regular sequence
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11.12.12 ADC injected sequence register (ADC_JSQR)
31 30
Address offset: 0x38
Reset value: 0x0000 0000
29 28 27 26 25 24 23 22
15
JSQ4_0 rw
14 rw
Reserved
13 rw
12
JSQ3[4:0] rw
11 rw
10 rw
9 rw
8 rw
7
JSQ2[4:0] rw
6 rw
21
JL[1:0]
20 rw
5 rw
4 rw rw
19 rw
3 rw
18 17
JSQ4[4:1] rw
2 rw
1
JSQ1[4:0] rw rw
16 rw
0 rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:20 JL[1:0] : Injected sequence length
These bits are written by software to define the total number of conversions in the injected channel conversion sequence.
00: 1 conversion
01: 2 conversions
10: 3 conversions
11: 4 conversions
Bits 19:15 JSQ4[4:0] : fourth conversion in injected sequence (when JL[1:0] = 3)
(1)
These bits are written by software with the channel number (0..17) assigned as the fourth in the sequence to be converted.
Note: Unlike a regular conversion sequence, if JL[1:0] length is less than four, the channels are converted in a sequence starting from (4-JL). Example: ADC_JSQR[21:0] = 10
00011 00011 00111 00010 means that a scan conversion will convert the following channel sequence: 7, 3, 3. (not 2, 7, 3)
Bits 14:10 JSQ3[4:0]: third conversion in injected sequence (when JL[1:0] = 3)
Bits 9:5 JSQ2[4:0] : second conversion in injected sequence (when JL[1:0] = 3)
Bits 4:0 JSQ1[4:0] : first conversion in injected sequence (when JL[1:0] = 3)
1. When JL=3 ( 4 injected conversions in the sequencer), the ADC converts the channels in this order:
JSQ1[4:0] >> JSQ2[4:0] >> JSQ3[4:0] >> JSQ4[4:0]
When JL=2 ( 3 injected conversions in the sequencer), the ADC converts the channels in this order:
JSQ2[4:0] >> JSQ3[4:0] >> JSQ4[4:0]
When JL=1 ( 2 injected conversions in the sequencer), the ADC converts the channels in this order:
JSQ3[4:0] >> JSQ4[4:0]
When JL=0 (1 injected conversion in the sequencer), the ADC converts only JSQ4[4:0] channel
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RM0008 Analog-to-digital converter (ADC)
11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4)
31 30
Address offset: 0x3C - 0x48
Reset value: 0x0000 0000
29 28 27 26 25 22 21 20
15 r
14 r
13 r
12 r
11 r
10 r
9 r
24 23
Reserved
8 7
JDATA[15:0] r r
6 r
5 r
4 r
19
3
18
2
17
1
16
0 r r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 JDATA[15:0] : Injected data
These bits are read only. They contain the conversion result from injected channel x. The data is left or right-aligned as shown in
31 r
15 r
30
Address offset: 0x4C
Reset value: 0x0000 0000
29 28 27 26 25 r
14 r
13 r
12 r
11 r
10 r
9
24 23
ADC2DATA[15:0] r
8 r
7 r
DATA[15:0] r
22 r r
6
21 r
5
20 r
4
19 r
3
18 r
2
17 r
1
16 r
0 r r r r r r r r r r r r
Bits 31:16 ADC2DATA[15:0]: ADC2 data
In ADC1: In dual mode, these bits contain the regular data of ADC2. Refer to
.
In ADC2 and ADC3: these bits are not used.
Bits 15:0 DATA[15:0] : Regular data
These bits are read only. They contain the conversion result from the regular channels. The
data is left or right-aligned as shown in Figure 27 and Figure 28 .
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11.12.15 ADC register map
The following table summarizes the ADC registers.
Table 72. ADC register map and reset values
Offset Register
RM0008
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
ADC_SR
Reset value
ADC_CR1
Reset value
ADC_CR2
Reset value
ADC_SMPR1
Reset value
ADC_SMPR2
Reset value
ADC_JOFR1
Reset value
ADC_JOFR2
Reset value
ADC_JOFR3
Reset value
ADC_JOFR4
Reset value
ADC_HTR
Reset value
ADC_LTR
Reset value
ADC_SQR1
Reset value
Reserved
Reserved
0 0
Reserved
0 0 0 0 0
DUALMOD
[3:0]
DISC
NUM
[2:0]
AWDCH[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EXTSEL
[2:0]
JEXTSE
L
[2:0]
Reserved
0 0 0 0 0 0 0 0 0 0 0 0
Sample time bits SMPx_x
0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Sample time bits SMPx_x
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
JOFFSET1[11:0]
0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
JOFFSET2[11:0]
0 0 0 0 0 0 0 0 0 0 0 0
Reserved
JOFFSET3[11:0]
0 0 0 0 0 0 0 0 0 0 0 0
JOFFSET4[11:0]
Reserved
0 0 0 0 0 0 0 0 0 0 0 0
HT[11:0]
Reserved
0 0 0 0 0 0 0 0 0 0 0 0
Reserved
LT[11:0]
0 0 0 0 0 0 0 0 0 0 0 0
L[3:0]
SQ16[4:0] 16th conversion in regular sequence bits
SQ15[4:0] 15th conversion in regular sequence bits
SQ14[4:0]
1fourth conversion in regular sequence bits
SQ13[4:0] 13th conversion in regular sequence bits
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Table 72. ADC register map and reset values (continued)
Offset Register
0x30
0x34
0x38
0x3C
0x40
0x44
0x48
0x4C
Reset value
ADC_JDR1
Reset value
ADC_JDR2
Reset value
ADC_JDR3
Reset value
ADC_JDR4
Reset value
ADC_DR
Reset value
ADC_SQR2
Reset value
ADC_SQR3
Reset value
ADC_JSQR
SQ12[4:0] 12th conversion in regular sequence bits
SQ11[4:0] 11th conversion in regular sequence bits
SQ10[4:0] 10th conversion in regular sequence bits
SQ9[4:0] 9th conversion in regular sequence bits
SQ8[4:0] 8th conversion in regular sequence bits
SQ7[4:0] 7th conversion in regular sequence bits
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SQ6[4:0] 6th conversion in regular sequence bits
SQ5[4:0] 5th conversion in regular sequence bits
SQ4[4:0] fourth conversion in regular sequence bits
SQ3[4:0] third conversion in regular sequence bits
SQ2[4:0] second conversion in regular sequence bits
SQ1[4:0] first conversion in regular sequence bits
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
JL[1:
0]
JSQ4[4:0] fourthconversion in injected sequence bits
JSQ3[4:0] third conversion in injected sequence bits
JSQ2[4:0] second conversion in injected sequence bits
JSQ1[4:0] first conversion in injected sequence bits
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
JDATA[15:0]
Reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
JDATA[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
JDATA[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
JDATA[15:0]
ADC2DATA[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Regular DATA[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
for the register boundary addresses.
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Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to connectivity line, high-density and XL-density STM32F101xx and
STM32F103xx devices only.
The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In
12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each with its own converter. In dual DAC channel mode, conversions could be done independently or simultaneously when both channels are grouped together for synchronous update operation. An input reference pin V
REF+ resolution.
(shared with ADC) is available for better
12.2 DAC main features
Two DAC converters: one output channel each
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
External triggers for conversion
Input voltage reference V
REF+
The block diagram of a DAC channel is shown in Figure 40 and the pin description is given
in
254/1136 RM0008 Rev 21
RM0008 Digital-to-analog converter (DAC)
Figure 40. DAC channel block diagram
Note:
DAC control register
TSELx[2:0] bits
SWTR IGx
TIM2_T RGO
TIM4_T RGO
TIM5_T RGO
TIM6_T RGO
TIM7_T RGO
TIM8_T RGO (1)
DMAENx
EXTI_9
DHRx
12- bit
Control logicx
LFSRx tr ianglex
DM A req ue stx
TENx
MAMPx[3:0] bits
WAVENx[1:0] bits
12-bit
DORx
12-bit
V
DDA
V
SSA
V
R EF+
Digital-to-analog converterx
DAC_ OU Tx ai14708c
1. In connectivity line devices, the TIM8_TRGO trigger is replaced by TIM3_TRGO.
Table 73. DAC pins
Name Signal type Remarks
V
REF+
Input, analog reference positive
The higher/positive reference voltage for the DAC,
2.4 V V
REF+
V
DDA
(3.3 V)
V
DDA
V
SSA
Input, analog supply
Input, analog supply ground
DAC_OUTx Analog output signal
Analog power supply
Ground for analog power supply
DAC channelx analog output
Once DAC channelx is enabled, the corresponding GPIO pin (PA4 or PA5) is automatically connected to the analog converter output (DAC_OUTx). To avoid parasitic consumption, the
PA4 or PA5 pin should first be configured to analog (AIN).
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12.3 DAC functional description
12.3.1 DAC channel enable
Note:
Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time t
WAKEUP
.
The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital interface is enabled even if the ENx bit is reset.
12.3.2 DAC output buffer enable
The DAC integrates two output buffers that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier.
Each DAC channel output buffer can be enabled and disabled using the corresponding
BOFFx bit in the DAC_CR register.
Depending on the selected configuration mode, the data has to be written in the specified register as described below:
Single DAC channelx, there are three possibilities:
– 8-bit right alignment: user has to load data into DAC_DHR8Rx [7:0] bits (stored into DHRx[11:4] bits)
– 12-bit left alignment: user has to load data into DAC_DHR12Lx [15:4] bits (stored into DHRx[11:0] bits)
– 12-bit right alignment: user has to load data into DAC_DHR12Rx [11:0] bits (stored into DHRx[11:0] bits)
Depending on the loaded DAC_DHRyyyx register, the data written by the user will be shifted and stored into the DHRx (Data Holding registerx, that are internal non-memory-mapped registers). The DHRx register will then be loaded into the DORx register either automatically, by software trigger or by an external event trigger.
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Figure 41. Data registers in single DAC channel mode
31 24 15 7 0
8-bit right aligned
12-bit left aligned
12-bit right aligned ai14710
Dual DAC channels, there are three possibilities:
– 8-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR8RD [7:0] bits (stored into DHR1[11:4] bits) and data for DAC channel2 to be loaded into
DAC_DHR8RD [15:8] bits (stored into DHR2[11:4] bits)
– 12-bit left alignment: data for DAC channel1 to be loaded into DAC_DHR12LD
[15:4] bits (stored into DHR1[11:0] bits) and data for DAC channel2 to be loaded into DAC_DHR12LD [31:20] bits (stored into DHR2[11:0] bits)
– 12-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR12RD
[11:0] bits (stored into DHR1[11:0] bits) and data for DAC channel2 to be loaded into DAC_DHR12RD [27:16] bits (stored into DHR2[11:0] bits)
Depending on the loaded DAC_DHRyyyD register, the data written by the user will be shifted and stored into the DHR1 and DHR2 (Data Holding registers, that are internal nonmemory-mapped registers). The DHR1 and DHR2 registers will then be loaded into the
DOR1 and DOR2 registers, respectively, either automatically, by software trigger or by an external event trigger.
Figure 42. Data registers in dual DAC channel mode
31 24 15 7 0
8-bit right aligned
12-bit left aligned
12-bit right aligned ai14709
The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write on DAC_DHR8Rx, DAC_DHR12Lx,
DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12LD).
Data stored into the DAC_DHRx register are automatically transferred to the DAC_DORx register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later.
When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time of t
SETTLING the analog output load.
that depends on the power supply voltage and
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Digital-to-analog converter (DAC) RM0008
Figure 43. Timing diagram for conversion with trigger disabled TEN = 0
APB1_CLK
DHR 0x1AC
DOR 0x1AC t
SETTLING
Output voltage available on DAC_OUT pin ai14711b
Digital inputs are converted to output voltages on a linear conversion between 0 and V
REF+
.
The analog output voltages on each DAC channel pin are determined by the equation
4096
If the TENx control bit is set, conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[2:0] control bits determine which one, out of 8
possible events, will trigger conversion, as shown in Table 74
.
Source
Timer 6 TRGO event
Timer 3 TRGO event in connectivity line devices or
Timer 8 TRGO in high-density and
XL-density devices
Timer 7 TRGO event
Timer 5 TRGO event
Timer 2 TRGO event
Timer 4 TRGO event
EXTI line9
SWTRIG
Table 74. External triggers
Type
Internal signal from on-chip timers
External pin
Software control bit
TSEL[2:0]
000
001
010
011
100
101
110
111
Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on the selected external interrupt line 9, the last data stored into the DAC_DHRx register is transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1 cycles after the trigger occurs.
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Note:
Digital-to-analog converter (DAC)
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the
DAC_DHRx register contents.
TSELx[2:0] bit cannot be changed when the ENx bit is set.
When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx-to-
DAC_DORx register transfer.
Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests.
A DAC DMA request is generated when an external trigger (but not a software trigger) occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred to the DAC_DORx register.
In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one
DMA request is needed, you should set only the corresponding DMAENx bit. In this way, the application can manage both DAC channels in dual mode by using one DMA request and a unique DMA channel.
The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgement of the last request, then the new request will not be serviced and no error is reported
In order to generate a variable-amplitude pseudonoise, a Linear Feedback Shift register is available. The DAC noise generation is selected by setting WAVEx[1:0] to “01”. The preloaded value in the LFSR is 0xAAA. This register is updated, three APB1 clock cycles after each trigger event, following a specific calculation algorithm.
Figure 44. DAC LFSR register calculation algorithm
XOR
X
12
11 10 9 8 7 6
X
6
5 4
X
4
3 2 1
X
0
X
0
12
NOR
MS47561V1
The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register.
If LFSR is 0x0000, a ‘1’ is injected into it (antilock-up mechanism).
It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.
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Digital-to-analog converter (DAC) RM0008
Figure 45. DAC conversion (SW trigger enabled) with LFSR wave generation
APB1_CLK
DHR 0x00
Note:
DOR 0xAAA 0xD55
SWTRIG ai14714
DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR register.
It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.
DAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three APB1 clock cycles after each trigger event. The value of this counter is then added to the DAC_DHRx register without overflow and the sum is stored into the
DAC_DORx register. The triangle counter is incremented while it is less than the maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is reached, the counter is decremented down to 0, then incremented again and so on.
It is possible to reset triangle wave generation by resetting WAVEx[1:0] bits.
Figure 46. DAC triangle wave generation
MAMPx[3:0] max amplitude
+ DAC_DHRx base value
Decrementation
Incrementation
DAC_DHRx base value
0 ai14715c
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RM0008 Digital-to-analog converter (DAC)
Figure 47. DAC conversion (SW trigger enabled) with triangle wave generation
APB1_CLK
DHR 0xABE
DOR 0xABE 0xABF 0xAC0
Note:
SWTRIG ai14714
DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR register.
MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed.
12.4 Dual DAC channel conversion
To efficiently use the bus bandwidth in applications that require the two DAC channels at the same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A unique register access is then required to drive both DAC channels at the same time.
Eleven possible conversion modes are possible using the two DAC channels and these dual registers. All the conversion modes can nevertheless be obtained using separate DHRx registers if needed.
All modes are described in the paragraphs below.
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1
(three APB1 clock cycles later).
When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2
(three APB1 clock cycles later).
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To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in the MAMPx[3:0] bits
Load the dual DAC channel data into the desired DHR register (DHR12RD, DHR12LD or DHR8RD)
When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). Then the LFSR2 counter is updated.
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR masks values in the MAMP1[3:0] and MAMP2[3:0] bits
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by
MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1
(three APB1 clock cycles later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by
MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three APB1 clock cycles later). Then the LFSR2 counter is updated.
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum amplitude value in the MAMPx[3:0] bits
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into
RM0008 Rev 21
RM0008 Digital-to-analog converter (DAC)
DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into
DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated.
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register part and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated.
12.4.6 Simultaneous software start
To configure the DAC in this conversion mode, the following sequence is required:
Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
In this configuration, one APB1 clock cycle later, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively.
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits
Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and
DAC_DOR2, respectively (after three APB1 clock cycles).
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Digital-to-analog converter (DAC) RM0008
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in the MAMPx[3:0] bits
Load the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or
DHR8RD)
When a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The
LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The LFSR2 counter is then updated.
12.4.9 Simultaneous trigger with different LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR masks values using the MAMP1[3:0] and MAMP2[3:0] bits
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The LFSR1 counter is then updated.
At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The LFSR2 counter is then updated.
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum amplitude value using the MAMPx[3:0] bits
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three
APB1 clock cycles later). The DAC channel1 triangle counter is then updated.
At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is
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RM0008 Digital-to-analog converter (DAC) added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated.
12.4.11 Simultaneous trigger with different triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
Set the two DAC channel trigger enable bits TEN1 and TEN2
Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits
Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three APB1 clock cycles later). Then the DAC channel1 triangle counter is updated.
At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated.
The peripheral registers have to be accessed by words (32-bit).
12.5.1 DAC control register (DAC_CR)
31
15
Address offset: 0x00
30
Reserved
14
Reserved
Reset value: 0x0000 0000
29
13
28
DMA
EN2 rw
12
DMA
EN1 rw
27 rw
11 rw
26
MAMP2[3:0] rw
10 rw
9
MAMP1[3:0] rw
25 rw
24 rw
8 rw
23 22
WAVE2[1:0] rw
7 rw
6
WAVE1[1:0] rw rw
21 20
TSEL2[2:0]
19 rw
5 rw
4 rw
3 rw
TSEL1[2:0] rw rw
18 17 16
TEN2 BOFF2 EN2 rw
2 rw
1 rw
0
TEN1 BOFF1 EN1 rw rw rw
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Digital-to-analog converter (DAC) RM0008
Bits 31:29 Reserved.
Bit 28 DMAEN2 : DAC channel2 DMA enable
This bit is set and cleared by software.
0: DAC channel2 DMA mode disabled
1: DAC channel2 DMA mode enabled
Bit 27:24 MAMP2[3:0] : DAC channel2 mask/amplitude selector
These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode.
0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
Bit 23:22 WAVE2[1:0] : DAC channel2 noise/triangle wave generation enable
These bits are set/reset by software.
00: wave generation disabled
01: Noise wave generation enabled
1x: Triangle wave generation enabled
Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
Bits 21:19 TSEL2[2:0] : DAC channel2 trigger selection
These bits select the external event used to trigger DAC channel2
000: Timer 6 TRGO event
001: Timer 3 TRGO event in connectivity line devices, Timer 8 TRGO in high-density and
XL-density devices
010: Timer 7 TRGO event
011: Timer 5 TRGO event
100: Timer 2 TRGO event
101: Timer 4 TRGO event
110: External line9
111: Software trigger
Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
Bit 18 TEN2 : DAC channel2 trigger enable
This bit set and cleared by software to enable/disable DAC channel2 trigger
0: DAC channel2 trigger disabled and data written into DAC_DHRx register is transferred one APB1 clock cycle later to the DAC_DOR2 register.
1: DAC channel2 trigger enabled and data transfer from DAC_DHRx register is transferred three APB1 clock cycles later to the DAC_DOR2 register.
Note: When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx to
DAC_DOR2 register transfer.
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Bit 17 BOFF2 : DAC channel2 output buffer disable
This bit set and cleared by software to enable/disable DAC channel2 output buffer.
0: DAC channel2 output buffer enabled
1: DAC channel2 output buffer disabled
Bit 16 EN2 : DAC channel2 enable
This bit set and cleared by software to enable/disable DAC channel2.
0: DAC channel2 disabled
1: DAC channel2 enabled
Bits 15:13 Reserved.
Bit 12 DMAEN1 : DAC channel1 DMA enable
This bit is set and cleared by software.
0: DAC channel1 DMA mode disabled
1: DAC channel1 DMA mode enabled
Bits 11:8 MAMP1[3:0] : DAC channel1 mask/amplitude selector
These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode.
0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
Bits 7:6 WAVE1[1:0] : DAC channel1 noise/triangle wave generation enable
These bits are set/reset by software.
00: wave generation disabled
01: Noise wave generation enabled
1x: Triangle wave generation enabled
Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
Bits 5:3 TSEL1[2:0] : DAC channel1 trigger selection
These bits select the external event used to trigger DAC channel1
000: Timer 6 TRGO event
001: Timer 3 TRGO event in connectivity line devices, Timer 8 TRGO in high-density and
XL-density devices
010: Timer 7 TRGO event
011: Timer 5 TRGO event
100: Timer 2 TRGO event
101: Timer 4 TRGO event
110: External line9
111: Software trigger
Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
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Bit 2 TEN1 : DAC channel1 trigger enable
This bit set and cleared by software to enable/disable DAC channel1 trigger
0: DAC channel1 trigger disabled and data written into DAC_DHRx register is transferred one APB1 clock cycle later to the DAC_DOR1 register.
1: DAC channel1 trigger enabled and data transfer from DAC_DHRx register is transferred three APB1 clock cycles later to the DAC_DOR1 register.
Note: When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx to
DAC_DOR1 register transfer.
Bit 1 BOFF1 : DAC channel1 output buffer disable
This bit set and cleared by software to enable/disable DAC channel1 output buffer.
0: DAC channel1 output buffer enabled
1: DAC channel1 output buffer disabled
Bit 0 EN1 : DAC channel1 enable
This bit set and cleared by software to enable/disable DAC channel1.
0: DAC channel1 disabled
1: DAC channel1 enabled
31
15
30
Address offset: 0x04
Reset value: 0x0000 0000
29 28 27 26 25
14
24 23
Reserved
8 7
22 21 20 19 18 17 16
13 12 11 10 9
Reserved
6 5 4 3 2 1
SWTRI
G2 w
0
SWTRI
G1 w
Bits 31:2 Reserved.
Bit 1 SWTRIG2 : DAC channel2 software trigger
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disabled
1: Software trigger enabled
Note: This bit is reset by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value is loaded to the DAC_DOR2 register.
Bit 0 SWTRIG1 : DAC channel1 software trigger
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disabled
1: Software trigger enabled
Note: This bit is reset by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value is loaded to the DAC_DOR1 register.
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RM0008 Digital-to-analog converter (DAC)
12.5.3 DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1)
31 30
Address offset: 0x08
Reset value: 0x0000 0000
29 28 27 26 25 22 21 20 19
15 14 13 12 11 10 9
24 23
Reserved
8 7 4 3
Reserved rw rw rw rw rw
6 5
DACC1DHR[11:0] rw rw rw rw
18
2 rw
Bits 31:12 Reserved.
Bit 11:0 DACC1DHR[11:0] : DAC channel1 12-bit right-aligned data
These bits are written by software which specify 12-bit data for DAC channel1.
17
1 rw
16
0 rw
12.5.4 DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1)
31 30
Address offset: 0x0C
Reset value: 0x0000 0000
29 28 27 26 25 22 21 20 19
15 14 13 12 11
24 23
8
Reserved
7 6 5 4 3 rw rw rw rw rw
10 9
DACC1DHR[11:0] rw rw rw rw rw rw rw
Bits 31:16 Reserved.
Bit 15:4 DACC1DHR[11:0] : DAC channel1 12-bit left-aligned data
These bits are written by software which specify 12-bit data for DAC channel1.
Bits 3:0 Reserved.
18 17
2 1
Reserved
12.5.5 DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1)
31 30
Address offset: 0x10
Reset value: 0x0000 0000
29 28 27 26 25 22 21 20 19
15 14 13 12 11 10 9
24 23
8
Reserved
7 6 5
Reserved rw rw rw
4 3
DACC1DHR[7:0] rw rw
18
2 rw
Bits 31:8 Reserved.
Bits 7:0 DACC1DHR[7:0] : DAC channel1 8-bit right-aligned data
These bits are written by software which specify 8-bit data for DAC channel1.
17
1 rw
16
0
16
0 rw
RM0008 Rev 21 269/1136
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Digital-to-analog converter (DAC)
12.5.6 DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2)
31 30
Address offset: 0x14
Reset value: 0x0000 0000
29 28 27 26 25 22 21 20 19
15 14 13 12 11 10 9
24 23
Reserved
8 7 4 3
Reserved rw rw rw rw rw
6 5
DACC2DHR[11:0] rw rw rw rw
18
2 rw
Bits 31:12 Reserved.
Bits 11:0 DACC2DHR[11:0] : DAC channel2 12-bit right-aligned data
These bits are written by software which specify 12-bit data for DAC channel2.
17
1 rw
RM0008
16
0 rw
12.5.7 DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2)
31 30
Address offset: 0x18
Reset value: 0x0000 0000
29 28 27 26 25 22 21 20 19
15 14 13 12 11
24 23
8
Reserved
7 6 5 4 3 rw rw rw rw rw
10 9
DACC2DHR[11:0] rw rw rw rw rw rw rw
18 17
2 1
Reserved
Bits 31:16 Reserved.
Bits 15:4 DACC2DHR[11:0] : DAC channel2 12-bit left-aligned data
These bits are written by software which specify 12-bit data for DAC channel2.
Bits 3:0 Reserved.
12.5.8 DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2)
31 30
Address offset: 0x1C
Reset value: 0x0000 0000
29 28 27 26 25 22 21 20 19
15 14 13 12 11 10 9
24 23
8
Reserved
7 6 5
Reserved rw rw rw
4 3
DACC2DHR[7:0] rw rw
18
2 rw
Bits 31:8 Reserved.
Bits 7:0 DACC2DHR[7:0] : DAC channel2 8-bit right-aligned data
These bits are written by software which specify 8-bit data for DAC channel2.
17
1 rw
16
0 rw
16
0
270/1136 RM0008 Rev 21
RM0008 Digital-to-analog converter (DAC)
12.5.9 Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD)
31 30
Address offset: 0x20
Reset value: 0x0000 0000
29 28 27 26 25 24 23 20
15
Reserved
14 13
Reserved
12 rw
11 rw rw
10 rw rw
9 rw rw
8 rw rw
7 rw
22 21
DACC2DHR[11:0] rw
6 rw
5
DACC1DHR[11:0] rw rw rw
4 rw
19 rw
3 rw
18 rw
2 rw
Bits 31:28 Reserved.
Bits 27:16 DACC2DHR[11:0] : DAC channel2 12-bit right-aligned data
These bits are written by software which specify 12-bit data for DAC channel2.
Bits 15:12 Reserved.
Bits 11:0 DACC1DHR[11:0] : DAC channel1 12-bit right-aligned data
These bits are written by software which specify 12-bit data for DAC channel1.
17 rw
1 rw
16 rw
0 rw
12.5.10 DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD)
31 rw
15 rw
30 rw
14 rw
Address offset: 0x24
Reset value: 0x0000 0000
29 rw
13 rw
28 rw
12 rw
27 rw
11 rw
26 25
DACC2DHR[11:0] rw rw
10 9
DACC1DHR[11:0] rw rw
24 rw
8 rw
23 rw
7 rw
22 rw
6 rw
21 rw
5 rw
20 rw
4 rw
19
3
18 17
Reserved
2 1
Reserved
Bits 31:20 DACC2DHR[11:0] : DAC channel2 12-bit left-aligned data
These bits are written by software, which specifies 12-bit data for DAC channel2.
Bits 19:16 Reserved.
Bits 15:4 DACC1DHR[11:0] : DAC channel1 12-bit left-aligned data
These bits are written by software, which specifies 12-bit data for DAC channel1.
Bits 3:0 Reserved.
16
0
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Digital-to-analog converter (DAC)
12.5.11 DUAL DAC 8-bit right aligned data holding register
(DAC_DHR8RD)
31 30
Address offset: 0x28
Reset value: 0x0000 0000
29 28 27 26 25 22 21 20
15 14 13 10 9
24 23
Reserved
8 7 6 5 rw rw rw
12 11
DACC2DHR[7:0] rw rw rw rw rw rw rw rw
19
4 3
DACC1DHR[7:0] rw rw
18
2 rw
Bits 31:16 Reserved.
Bits 15:8 DACC2DHR[7:0] : DAC channel2 8-bit right-aligned data
These bits are written by software which specify 8-bit data for DAC channel2.
Bits 7:0 DACC1DHR[7:0] : DAC channel1 8-bit right-aligned data
These bits are written by software which specify 8-bit data for DAC channel1.
17
1 rw
RM0008
16
0 rw
12.5.12 DAC channel1 data output register (DAC_DOR1)
31 30
Address offset: 0x2C
Reset value: 0x0000 0000
29 28 27 26 25 22 21 20
15 14 13 12 11 10 9
24 23
8
Reserved
7 4
Reserved r r r r r
6 5
DACC1DOR[11:0] r r r
19
Bits 31:12 Reserved.
Bit 11:0 DACC1DOR[11:0] : DAC channel1 data output
These bits are read only, they contain data output for DAC channel1.
r
3
12.5.13 DAC channel2 data output register (DAC_DOR2)
31 30
Address offset: 0x30
Reset value: 0x0000 0000
29 28 27 26 25 22 21 20
15 14 13 12 11 10 9
24 23
Reserved
8 7 4
Reserved r r r r r
6 5
DACC2DOR[11:0] r r r
19
3 r
18
2 r
17
1 r
18 17
2 r
1 r
16
0 r
16
0 r
Bits 31:12 Reserved.
Bit 11:0 DACC2DOR[11:0] : DAC channel2 data output
These bits are read only, they contain data output for DAC channel2.
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RM0008
12.5.14 DAC register map
The following table summarizes the DAC registers.
Table 75. DAC register map
Digital-to-analog converter (DAC)
Offset Register
0x00
DAC_CR
Reset value
Res.
MAMP2[3:0]
WAV
E2[2:
0]
TSEL2[2
:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
MAMP1[3:0]
WAV
E1[2:
0]
TSEL1
[2:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
DAC_SWTRIGR
Reserved
Reset value
DAC_DHR12R1
Reset value
DAC_DHR12L1
Reset value
DAC_DHR8R1
Reset value
DAC_DHR12R2
Reset value
DAC_DHR12L2
Reset value
DAC_DHR8R2
DAC_DHR12RD
Reset value
DAC_DHR12LD
Reset value
DAC_DHR8RD
Reset value
DAC_DOR1
Reset value
DAC_DOR2
Reset value
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DACC2DHR[11:0]
0 0 0 0 0 0 0 0 0 0 0 0
DACC2DHR[11:0]
0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
Reserved
0 0
DACC1DHR[11:0]
0 0 0 0 0 0 0 0 0 0 0 0
DACC1DHR[11:0]
0 0 0 0 0 0 0 0 0 0 0 0
Reserved
DACC1DHR[7:0]
0 0 0 0 0 0 0 0
DACC2DHR[11:0]
0 0 0 0 0 0 0 0 0 0 0 0
DACC2DHR[11:0]
0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
DACC2DHR[7:0]
0 0 0 0 0 0 0 0
DACC1DHR[11:0]
0 0 0 0 0 0 0 0 0 0 0 0
DACC1DHR[11:0]
0 0 0 0 0 0 0 0 0 0 0 0
Reserved
DACC2DHR[7:0] DACC1DHR[7:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DACC1DOR[11:0]
0 0 0 0 0 0 0 0 0 0 0 0
DACC2DOR[11:0]
0 0 0 0 0 0 0 0 0 0 0 0
Note:
for the register boundary addresses.
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Direct memory access controller (DMA)
13 Direct memory access controller (DMA)
RM0008
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to the whole STM32F10xxx family, unless otherwise specified.
Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations.
The two DMA controllers have 12 channels in total (7 for DMA1 and 5 for DMA2), each dedicated to managing memory access requests from one or more peripherals. It has an arbiter for handling the priority between DMA requests.
13.2 DMA main features
12 independently configurable channels (requests): 7 for DMA1 and 5 for DMA2
Each of the 12 channels is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software.
Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high , high , medium , low ) or hardware in case of equality
(request 1 has priority over request 2, etc.)
Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size.
Support for circular buffer management
3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel
Memory-to-memory transfer
Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers
Access to Flash, SRAM, APB1, APB2 and AHB peripherals as source and destination
Programmable number of data to be transferred: up to 65536
The block diagram is shown in
.
274/1136 RM0008 Rev 21
RM0008 Direct memory access controller (DMA)
DMA1
Figure 48. DMA block diagram in connectivity line devices
ICode
FLITF
Flash
DCode
Cortex-M3
Sys tem
SRAM
DMA Ch.1
Ch.2
Reset & clock control (RCC)
Ch.7
Bridge 1
Bridge 2
APB2
Arbiter
DMA2
AHB Slave
Ch.1
Ch.2
DMA request
DMA request
ADC1
USART1
SPI1
TIM1
APB1
SPI3/I2S
I2C2
I2C1
SPI2/I2S
TIM7
UART4 TIM6
USART3 TIM5
USART2
TIM4
TIM3
TIM2
Ch.5
Arbiter
AHB Slave
Ethernet MAC
USB OTG FS ai15811b
RM0008 Rev 21 275/1136
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Direct memory access controller (DMA) RM0008
Figure 49. DMA block diagram in low-, medium- high- and XL-density devices
ICode
FLITF
Flash
DCode
Cortex-M3
Sys tem
SRAM
DMA1 Ch.1
Ch.2
DMA FSMC
SDIO
Ch.7
AHB System Bridge 2
Bridge 1
APB1
APB2
Arbiter
DMA2
AHB Slave
Ch.1
Ch.2
DMA request
DMA request
USART2
USART3
UART4
SPI/I2S2
SPI/I2S3
I2C1
I2C2
TIM2
TIM3
TIM 4
TIM5
TIM6
TIM7
USART1
SPI1
ADC1
ADC3
TIM1
TIM8
Ch.5
Arbiter
DMA request
AHB Slave
Reset & clock control
(RCC) ai14801b
1. The DMA2 controller is available only in high-density and XL-density devices.
1. ADC3, SPI/I2S3, UART4, SDIO, TIM5, TIM6, DAC, TIM7, TIM8 DMA requests are available only in highdensity devices
13.3 DMA functional description
The DMA controller performs direct memory transfer by sharing the system bus with the
Cortex ® -M3 core. The DMA request may stop the CPU access to the system bus for some bus cycles, when the CPU and DMA are targeting the same destination (memory or peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the CPU.
After an event, the peripheral sends a request signal to the DMA Controller. The DMA controller serves the request depending on the channel priorities. As soon as the DMA
Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA
Controller. The peripheral releases its request as soon as it gets the Acknowledge from the
DMA Controller. Once the request is deasserted by the peripheral, the DMA Controller release the Acknowledge. If there are more requests, the peripheral can initiate the next transaction.
276/1136 RM0008 Rev 21
RM0008 Direct memory access controller (DMA)
In summary, each DMA transfer consists of three operations:
The loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the
DMA_CPARx or DMA_CMARx register
The storage of the data loaded to the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register
The post-decrementing of the DMA_CNDTRx register, which contains the number of transactions that have still to be performed.
13.3.2 Arbiter
Note:
The arbiter manages the channel requests based on their priority and launches the peripheral/memory access sequences.
The priorities are managed in two stages:
Software: each channel priority can be configured in the DMA_CCRx register. There are four levels:
– Very high priority
– High priority
– Medium priority
– Low priority
Hardware: if 2 requests have the same software priority level, the channel with the lowest number will get priority versus the channel with the highest number. For example, channel 2 gets priority over channel 4.
In high-density, XL-density and connectivity line devices, the DMA1 controller has priority over the DMA2 controller.
Each channel can handle DMA transfer between a peripheral register located at a fixed address and a memory address. The amount of data to be transferred (up to 65535) is programmable. The register which contains the amount of data items to be transferred is decremented after each transaction.
Programmable data sizes
Transfer data sizes of the peripheral and memory are fully programmable through the
PSIZE and MSIZE bits in the DMA_CCRx register.
Pointer incrementation
Peripheral and memory pointers can optionally be automatically post-incremented after each transaction depending on the PINC and MINC bits in the DMA_CCRx register. If incremented mode is enabled, the address of the next transfer will be the address of the previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer address is the one programmed in the DMA_CPARx/DMA_CMARx registers. During transfer operations, these registers keep the initially programmed value. The current
RM0008 Rev 21 277/1136
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Direct memory access controller (DMA)
Note:
RM0008 transfer addresses (in the current internal peripheral/memory address register) are not accessible by software.
If the channel is configured in noncircular mode, no DMA request is served after the last transfer (that is once the number of data items to be transferred has reached zero). In order to reload a new number of data items to be transferred into the DMA_CNDTRx register, the
DMA channel must be disabled.
If a DMA channel is disabled, the DMA registers are not reset. The DMA channel registers
(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during the channel configuration phase.
In circular mode, after the last transfer, the DMA_CNDTRx register is automatically reloaded with the initially programmed value. The current internal address registers are reloaded with the base address values from the DMA_CPARx/DMA_CMARx registers.
Channel configuration procedure
The following sequence should be followed to configure a DMA channelx (where x is the channel number).
1.
Set the peripheral register address in the DMA_CPARx register. The data will be moved from/ to this address to/ from the memory after the peripheral event.
2. Set the memory address in the DMA_CMARx register. The data will be written to or read from this memory after the peripheral event.
3. Configure the total number of data to be transferred in the DMA_CNDTRx register.
After each peripheral event, this value will be decremented.
4. Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register
5. Configure data transfer direction, circular mode, peripheral & memory incremented mode, peripheral & memory data size, and interrupt after half and/or full transfer in the
DMA_CCRx register
6. Activate the channel by setting the ENABLE bit in the DMA_CCRx register.
As soon as the channel is enabled, it can serve any DMA request from the peripheral connected on the channel.
Once half of the bytes are transferred, the half-transfer flag (HTIF) is set and an interrupt is generated if the Half-Transfer Interrupt Enable bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag (TCIF) is set and an interrupt is generated if the Transfer
Complete Interrupt Enable bit (TCIE) is set.
Circular mode
Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_CCRx register.
When circular mode is activated, the number of data to be transferred is automatically reloaded with the initial value programmed during the channel configuration phase, and the
DMA requests continue to be served.
Memory-to-memory mode
The DMA channels can also work without being triggered by a request from a peripheral.
This mode is called Memory to Memory mode.
If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as soon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx
278/1136 RM0008 Rev 21
RM0008 Direct memory access controller (DMA) register. The transfer stops once the DMA_CNDTRx register reaches zero. Memory to
Memory mode may not be used at the same time as Circular mode.
13.3.4 Programmable data width, data alignment and endians
When PSIZE and MSIZE are not equal, the DMA performs some data alignments as described in
Table 76. Programmable data width and endian behavior (when bits PINC = MINC = 1)
Source port width
Destination port width
Number of data items to transfer
(NDT)
Source content: address / data
Transfer operations
Destination content: address / data
8
8
8
16
16
16
32
32
32
8
16
32
8
16
32
8
16
32
4
4
4
4
4
4
4
4
4
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
1: READ B0[7:0] @0x0 then WRITE B0[7:0] @0x0
2: READ B1[7:0] @0x1 then WRITE B1[7:0] @0x1
3: READ B2[7:0] @0x2 then WRITE B2[7:0] @0x2
4: READ B3[7:0] @0x3 then WRITE B3[7:0] @0x3
1: READ B0[7:0] @0x0 then WRITE 00B0[15:0] @0x0
2: READ B1[7:0] @0x1 then WRITE 00B1[15:0] @0x2
3: READ B3[7:0] @0x2 then WRITE 00B2[15:0] @0x4
4: READ B4[7:0] @0x3 then WRITE 00B3[15:0] @0x6
1: READ B0[7:0] @0x0 then WRITE 000000B0[31:0] @0x0
2: READ B1[7:0] @0x1 then WRITE 000000B1[31:0] @0x4
3: READ B3[7:0] @0x2 then WRITE 000000B2[31:0] @0x8
4: READ B4[7:0] @0x3 then WRITE 000000B3[31:0] @0xC
1: READ B1B0[15:0] @0x0 then WRITE B0[7:0] @0x0
2: READ B3B2[15:0] @0x2 then WRITE B2[7:0] @0x1
3: READ B5B4[15:0] @0x4 then WRITE B4[7:0] @0x2
4: READ B7B6[15:0] @0x6 then WRITE B6[7:0] @0x3
1: READ B1B0[15:0] @0x0 then WRITE B1B0[15:0] @0x0
2: READ B3B2[15:0] @0x2 then WRITE B3B2[15:0] @0x2
3: READ B5B4[15:0] @0x4 then WRITE B5B4[15:0] @0x4
4: READ B7B6[15:0] @0x6 then WRITE B7B6[15:0] @0x6
1: READ B1B0[15:0] @0x0 then WRITE 0000B1B0[31:0] @0x0
2: READ B3B2[15:0] @0x2 then WRITE 0000B3B2[31:0] @0x4
3: READ B5B4[15:0] @0x4 then WRITE 0000B5B4[31:0] @0x8
4: READ B7B6[15:0] @0x6 then WRITE 0000B7B6[31:0] @0xC
1: READ B3B2B1B0[31:0] @0x0 then WRITE B0[7:0] @0x0
2: READ B7B6B5B4[31:0] @0x4 then WRITE B4[7:0] @0x1
3: READ BBBAB9B8[31:0] @0x8 then WRITE B8[7:0] @0x2
4: READ BFBEBDBC[31:0] @0xC then WRITE BC[7:0] @0x3
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
@0x0 / 00B0
@0x2 / 00B1
@0x4 / 00B2
@0x6 / 00B3
@0x0 / 000000B0
@0x4 / 000000B1
@0x8 / 000000B2
@0xC / 000000B3
@0x0 / B0
@0x1 / B2
@0x2 / B4
@0x3 / B6
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
@0x0 / 0000B1B0
@0x4 / 0000B3B2
@0x8 / 0000B5B4
@0xC / 0000B7B6
@0x0 / B0
@0x1 / B4
@0x2 / B8
@0x3 / BC
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
1: READ B3B2B1B0[31:0] @0x0 then WRITE B1B0[7:0] @0x0
2: READ B7B6B5B4[31:0] @0x4 then WRITE B5B4[7:0] @0x1
3: READ BBBAB9B8[31:0] @0x8 then WRITE B9B8[7:0] @0x2
4: READ BFBEBDBC[31:0] @0xC then WRITE BDBC[7:0] @0x3
@0x0 / B1B0
@0x2 / B5B4
@0x4 / B9B8
@0x6 / BDBC
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
1: READ B3B2B1B0[31:0] @0x0 then WRITE B3B2B1B0[31:0] @0x0
2: READ B7B6B5B4[31:0] @0x4 then WRITE B7B6B5B4[31:0] @0x4
3: READ BBBAB9B8[31:0] @0x8 then WRITE BBBAB9B8[31:0] @0x8
4: READ BFBEBDBC[31:0] @0xC then WRITE BFBEBDBC[31:0] @0xC
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
Addressing an AHB peripheral that does not support byte or halfword write operations
When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does not support byte or halfword write operations (when HSIZE is not used by the peripheral)
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To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD” with HSIZE = HalfWord
To write the byte “0xAB”, the DMA sets the HWDATA bus to “0xABABABAB” with
HSIZE = Byte
Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the
HSIZE data into account, it will transform any AHB byte or halfword operation into a 32-bit
APB operation in the following manner:
an AHB byte write operation of the data “0xB0” to 0x0 (or to 0x1, 0x2 or 0x3) will be converted to an APB word write operation of the data “0xB0B0B0B0” to 0x0
an AHB halfword write operation of the data “0xB1B0” to 0x0 (or to 0x2) will be converted to an APB word write operation of the data “0xB1B0B1B0” to 0x0
For instance, to write the APB backup registers (16-bit registers aligned to a 32-bit address boundary), the memory source size (MSIZE) must be configured to “16-bit” and the peripheral destination size (PSIZE) to “32-bit”.
A DMA transfer error can be generated by reading from or writing to a reserved address space. When a DMA transfer error occurs during a DMA read or a write access, the faulty channel is automatically disabled through a hardware clear of its EN bit in the corresponding
Channel configuration register (DMA_CCRx). The channel's transfer error interrupt flag
(TEIF) in the DMA_IFR register is set and an interrupt is generated if the transfer error interrupt enable bit (TEIE) in the DMA_CCRx register is set.
13.3.6 Interrupts
An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for each DMA channel. Separate interrupt enable bits are available for flexibility.
Half-transfer
Transfer complete
Transfer error
Table 77. DMA interrupt requests
Interrupt event Event flag
HTIF
TCIF
TEIF
Enable Control bit
HTIE
TCIE
TEIE
Note: In high-density and XL-density devices, DMA2 Channel4 and DMA2 Channel5 interrupts are mapped onto the same interrupt vector. In connectivity line devices, DMA2 Channel4 and DMA2 Channel5 interrupts have separate interrupt vectors. All other DMA1 and DMA2
Channel interrupts have their own interrupt vector.
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USART3_TX
TIM1_CH1
TIM2_UP
TIM3_CH3
SPI1_RX
USART3_RX
TIM1_CH2
TIM3_CH4
TIM3_UP
SPI1_TX
USART1_TX
TIM1_CH4
TIM1_TRIG
TIM1_COM
TIM4_CH2
SPI/I2S2_RX
I2C2_TX
USART1_RX
TIM1_UP
SPI/I2S2_TX
TIM2_CH1
TIM4_CH3
I2C2_RX
USART2_RX
TIM1_CH3
TIM3_CH1
TIM3_TRIG
I2C1_TX
DMA1 controller
The 7 requests from the peripherals (TIMx[1,2,3,4], ADC1, SPI1, SPI/I2S2, I2Cx[1,2] and
USARTx[1,2,3]) are simply logically ORed before entering the DMA1, this means that only one request must be enabled at a time. Refer to
The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral.
Figure 50. DMA1 request mapping
Peripheral
request signals
ADC1
TIM2_CH3
TIM4_CH1
USART2_TX
TIM2_CH2
TIM2_CH4
TIM4_UP
I2C1_RX
HW request 1
Fixed hardware priority
High priority
Channel 1
SW trigger (MEM2MEM bit)
Channel 1 EN bit
HW request 2
Channel 2
SW trigger (MEM2MEM bit)
Channel 2 EN bit
HW request 3
Channel 3
SW trigger (MEM2MEM bit)
Channel 3 EN bit
HW request 4
Channel 4
SW trigger (MEM2MEM bit)
Channel 4 EN bit internal
DMA1
request
HW request 5
SW trigger (MEM2MEM bit)
Channel 5 EN bit
Channel 5
HW REQUEST 6
Channel 6
SW TRIGGER (MEM2MEM bit)
Channel 6 EN bit
HW request 7
Channel 7
SW trigger (MEM2MEM bit)
Low priority
Channel 7 EN bit
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Table 78 lists the DMA requests for each channel.
Table 78. Summary of DMA1 requests for each channel
Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7
ADC1
SPI/I
2
S
USART
I
2
C
TIM1
TIM2
TIM3
TIM4
ADC1
-
-
-
-
-
SPI1_RX
TIM1_CH1
-
SPI1_TX
-
-
SPI2/I2S2_RX SPI2/I2S2_TX
TIM1_CH4
TIM1_TRIG
TIM1_COM
TIM1_UP
-
-
USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX
I2C2_TX I2C2_RX I2C1_TX I2C1_RX
TIM1_CH3 -
-
-
TIM2_CH3 TIM2_UP TIM2_CH1 -
TIM2_CH2
TIM2_CH4
-
TIM4_CH1
TIM3_CH3
-
TIM3_CH4
TIM3_UP
-
-
TIM4_CH2
-
TIM4_CH3
TIM3_CH1
TIM3_TRIG
-
-
TIM4_UP
Note:
DMA2 controller
The five requests from the peripherals (TIMx[5,6,7,8], ADC3, SPI/I2S3, UART4,
DAC_Channel[1,2] and SDIO) are simply logically ORed before entering the DMA2, this means that only one request must be enabled at a time. Refer to
The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral.
The DMA2 controller and its relative requests are available only in high-density, XL-density and connectivity line devices.
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Peripheral request signals
Figure 51. DMA2 request mapping
Fixed hardware priority
TIM5_CH4
TIM5_TRIG
TIM8_CH3
TIM8_UP
SPI/I2S3_RX
HW request 1
SW trigger (MEM2MEM bit)
Channel 1
HIGH PRIORITY
TIM8_CH4
TIM8_TRIG
TIM8_COM
TIM5_CH3
TIM5_UP
SPI/I2S3_TX
TIM8_CH1
UART4_RX
TIM6_UP/DAC_Channel1
Channel 1 EN bit
HW request 2
Channel 2
SW trigger (MEM2MEM bit)
Channel 2 EN bit
HW request 3
Channel 3
SW trigger (MEM2MEM bit)
Channel 3 EN bit
TIM5_CH2
SDIO
TIM7_UP/DAC_Channel2
HW request 4
Channel 4 internal
DMA2
request
SW trigger (MEM2MEM bit)
Channel 4 EN bit
ADC3
TIM8_CH2
TIM5_CH1
UART4_TX
HW request 5
SW trigger (MEM2MEM bit)
Channel 5 EN bit
Table 79 lists the DMA2 requests for each channel.
Channel 5
LOW PRIORITY
Peripherals
ADC3
SPI/I2S3
UART4
SDIO
(1)
(1)
TIM5
Table 79. Summary of DMA2 requests for each channel
Channel 1 Channel 2
-
SPI/I2S3_RX SPI/I2S3_TX
-
-
TIM5_CH4
TIM5_TRIG
-
-
TIM5_CH3
TIM5_UP
Channel 3
-
-
Channel 4
UART4_RX -
-
-
-
-
SDIO
TIM5_CH2
Channel 5
ADC3
-
UART4_TX
-
TIM5_CH1
TIM6/
DAC_Channel1
-
TIM6_UP/
DAC_Channel1
-
TIM7 -
TIM7_UP/
DAC_Channel2
-
TIM8
TIM8_CH3
TIM8_UP
TIM8_CH4
TIM8_TRIG
TIM8_COM
TIM8_CH1 -
1. ADC3, SDIO and TIM8 DMA requests are available only in high-density and XL-density devices.
TIM8_CH2
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Note:
Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.
In the following registers, all bits related to channel6 and channel7 are not relevant for
DMA2 since it has only 5 channels.
The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32bit).
13.4.1 DMA interrupt status register (DMA_ISR)
Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
Reserved
28 27 26 25
TEIF7 HTIF7 TCIF7 r r r
15 14 13 12 11 10 9
TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 r r r r r r r
24
GIF7 r
8
GIF3 r
23 22 21
TEIF6 HTIF6 TCIF6 r r r
7 6 5
TEIF2 HTIF2 TCIF2 r r r
20
GIF6 r
4
GIF2 r
19 18 17
TEIF5 HTIF5 TCIF5 r r r
3 2 1
TEIF1 HTIF1 TCIF1 r r r
16
GIF5 r
0
GIF1 r
Bits 31:28 Reserved, must be kept at reset value.
Bits 27, 23, 19, 15,
11, 7, 3
TEIFx: Channel x transfer error flag (x = 1 ..7)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer error (TE) on channel x
1: A transfer error (TE) occurred on channel x
Bits 26, 22, 18, 14,
10, 6, 2
HTIFx: Channel x half transfer flag (x = 1 ..7)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No half transfer (HT) event on channel x
1: A half transfer (HT) event occurred on channel x
Bits 25, 21, 17, 13,
9, 5, 1
TCIFx: Channel x transfer complete flag (x = 1 ..7)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer complete (TC) event on channel x
1: A transfer complete (TC) event occurred on channel x
Bits 24, 20, 16, 12,
8, 4, 0
GIFx: Channel x global interrupt flag (x = 1 ..7)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No TE, HT or TC event on channel x
1: A TE, HT or TC event occurred on channel x
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13.4.2 DMA interrupt flag clear register (DMA_IFCR)
Address offset: 0x04
Reset value: 0x0000 0000
31
15
CTEIF
4 w
30 29
Reserved
28
14
CHTIF
4 w
13
CTCIF
4 w
12
CGIF4 w
27
CTEIF
7 w
11
CTEIF
3 w
26
CHTIF
7 w
10
CHTIF
3 w
25
CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5 w
9 w
8 w
7 w
6 w
5 w
4 w
3 w
2 w
1 w
0
CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1 w
24 w
23 w
22 w
21 w
20 w
19 w
18 w
17 w
16 w
Bits 31:28 Reserved, must be kept at reset value.
Bits 27, 23, 19, 15,
11, 7, 3
CTEIFx: Channel x transfer error clear (x = 1 ..7)
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding TEIF flag in the DMA_ISR register
Bits 26, 22, 18, 14,
10, 6, 2
CHTIFx: Channel x half transfer clear (x = 1 ..7)
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding HTIF flag in the DMA_ISR register
Bits 25, 21, 17, 13,
9, 5, 1
CTCIFx: Channel x transfer complete clear (x = 1 ..7)
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding TCIF flag in the DMA_ISR register
Bits 24, 20, 16, 12,
8, 4, 0
CGIFx: Channel x global interrupt clear (x = 1 ..7)
This bit is set and cleared by software.
0: No effect
1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register
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13.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7, where x = channel number)
Address offset: 0x08 + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
31 30 29
15
Res.
14
MEM2
MEM rw
28
13
PL[1:0]
12 rw rw
27 26
11 10
MSIZE[1:0] rw rw
25
9
PSIZE[1:0]
24 23
Reserved
8 7
MINC rw rw rw
22
6
PINC rw
21
5
CIRC rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 MEM2MEM: Memory to memory mode
This bit is set and cleared by software.
0: Memory to memory mode disabled
1: Memory to memory mode enabled
Bits 13:12 PL[1:0]: Channel priority level
These bits are set and cleared by software.
00: Low
01: Medium
10: High
11: Very high
Bits 11:10 MSIZE[1:0]: Memory size
These bits are set and cleared by software.
00: 8-bits
01: 16-bits
10: 32-bits
11: Reserved
Bits 9:8 PSIZE[1:0]: Peripheral size
These bits are set and cleared by software.
00: 8-bits
01: 16-bits
10: 32-bits
11: Reserved
Bit 7 MINC: Memory increment mode
This bit is set and cleared by software.
0: Memory increment mode disabled
1: Memory increment mode enabled
Bit 6 PINC: Peripheral increment mode
This bit is set and cleared by software.
0: Peripheral increment mode disabled
1: Peripheral increment mode enabled
Bit 5 CIRC: Circular mode
This bit is set and cleared by software.
0: Circular mode disabled
1: Circular mode enabled
20
4
DIR rw
19
3
TEIE rw
18
2
HTIE rw
17
1
TCIE rw
16
0
EN rw
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RM0008 Direct memory access controller (DMA)
Bit 4 DIR: Data transfer direction
This bit is set and cleared by software.
0: Read from peripheral
1: Read from memory
Bit 3 TEIE: Transfer error interrupt enable
This bit is set and cleared by software.
0: TE interrupt disabled
1: TE interrupt enabled
Bit 2 HTIE: Half transfer interrupt enable
This bit is set and cleared by software.
0: HT interrupt disabled
1: HT interrupt enabled
Bit 1 TCIE: Transfer complete interrupt enable
This bit is set and cleared by software.
0: TC interrupt disabled
1: TC interrupt enabled
Bit 0 EN: Channel enable
This bit is set and cleared by software.
0: Channel disabled
1: Channel enabled
13.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number)
Address offset: 0x0C + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
31
15 rw
30 29
14 rw
13 rw
28
12 rw
27
11 rw
26
10 rw
25
9 rw
24 23
8
Reserved
7 rw
NDT rw
22
6 rw
21
5 rw
20
4 rw
19
3 rw
18
2 rw
17
1 rw
16
0 rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 NDT[15:0]: Number of data to transfer
Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer.
Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in autoreload mode.
If this register is zero, no transaction can be served whether the channel is enabled or not.
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13.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number)
Address offset: 0x10 + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
This register must not be written when the channel is enabled.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 PA[31:0]: Peripheral address
Base address of the peripheral data register from/to which the data will be read/written.
When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address.
When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
13.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number)
Address offset: 0x14 + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
This register must not be written when the channel is enabled.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 MA[31:0]: Memory address
Base address of the memory area from/to which the data will be read/written.
When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address.
When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
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The following table gives the DMA register map and the reset values.
Table 80. DMA register map and reset values
Offset Register
0x000
0x004
DMA_ISR
Reset value
DMA_IFCR
Reset value
Reserved
Reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x008
DMA_CCR1
Reserved
PL
[1:0]
0x00C
0x010
0x014
0x018
Reset value
DMA_CNDTR1
Reset value
DMA_CPAR1
Reset value
DMA_CMAR1
Reset value
Reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PA[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
0x01C
DMA_CCR2
Reserved
PL
[1:0]
0x020
0x024
0x028
0x02C
Reset value
DMA_CNDTR2
Reset value
DMA_CPAR2
Reset value
DMA_CMAR2
Reset value
Reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PA[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
0x030
DMA_CCR3
Reserved
PL
[1:0]
0x034
0x038
0x03C
0x040
Reset value
DMA_CNDTR3
Reset value
DMA_CPAR3
Reset value
DMA_CMAR3
Reset value
Reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PA[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
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Table 80. DMA register map and reset values (continued)
Offset Register
RM0008
0x044
DMA_CCR4
Reserved
PL
[1:0]
0x048
0x04C
0x050
0x054
Reset value
DMA_CNDTR4
Reset value
DMA_CPAR4
Reset value
DMA_CMAR4
Reset value
Reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PA[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
0x058
DMA_CCR5
Reserved
PL
[1:0]
0x05C
0x060
0x064
0x068
Reset value
DMA_CNDTR5
Reset value
DMA_CPAR5
Reset value
DMA_CMAR5
Reset value
Reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PA[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
0x06C
DMA_CCR6
Reserved
PL
[1:0]
0x070
0x074
0x078
0x07C
Reset value
DMA_CNDTR6
Reset value
DMA_CPAR6
Reset value
DMA_CMAR6
Reset value
Reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PA[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
0x080
DMA_CCR7
Reserved
PL
[1:0]
0x084
0x088
Reset value
DMA_CNDTR7
Reset value
DMA_CPAR7
Reset value
Reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PA[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Table 80. DMA register map and reset values (continued)
Offset Register
0x08C
0x090
DMA_CMAR7
Reset value
MA[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
for the register boundary addresses.
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Advanced-control timers (TIM1 and TIM8)
14 Advanced-control timers (TIM1 and TIM8)
RM0008
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Low- and medium-density STM32F103xx devices, and the STM32F105xx/STM32F107xx connectivity line devices, contain one advanced-control timer (TIM1) whereas high-density and XL-density STM32F103xx devices feature two advance-control timers (TIM1 and
TIM8).
14.1 TIM1 and TIM8 introduction
The advanced-control timers (TIM1 and TIM8) consist of a 16-bit auto-reload counter driven by a programmable prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.
The advanced-control (TIM1 and TIM8) and general-purpose (TIMx) timers are completely independent, and do not share any resources. They can be synchronized together as described in
.
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TIM1 and TIM8 timer features include:
16-bit up, down, up/down auto-reload counter.
16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65536.
Up to 4 independent channels for:
– Input capture
– Output compare
– PWM generation (Edge and Center-aligned Mode)
– One-pulse mode output
Complementary outputs with programmable dead-time
Synchronization circuit to control the timer with external signals and to interconnect several timers together.
Repetition counter to update the timer registers only after a given number of cycles of the counter.
Break input to put the timer’s output signals in reset state or in a known state.
Interrupt/DMA generation on the following events:
– Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)
– Trigger event (counter start, stop, initialization or count by internal/external trigger)
– Input capture
– Output compare
– Break input
Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes
Trigger input for external clock or cycle-by-cycle current management
RM0008 Rev 21 293/1136
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Advanced-control timers (TIM1 and TIM8)
Figure 52. Advanced-control timer block diagram
Internal clock (CK_INT)
CK_TIM18 from RCC
ETR
Polarity selection,
Edge detector and Prescaler
ETRP
ETRF
Input filter
ITR0
ITR1
ITR2
ITR3
TRC
TGI
TRGI
TIF_ED
Trigger controller
Slave mode controller
TRGO
Reset,
Enable,
Up/Down,
Count TI1FP1
TI2FP2
Encoder interface
To other timers
To DAC and ADC
REP Register
UI
U
RM0008
U
AutoReload
Register
TI2
TI3
TI4
BRK
TI1
Input filter &
Edge detector
TI1FP1
TI1FP2
TRC
Input filter &
Edge detector
TI2FP1
TI2FP2
TRC
Input filter &
Edge detector
TI3FP3
TI3FP4
TRC
Input filter &
Edge detector
TI4FP3
TI4FP4
TRC
Polarity selection
CK_PSC
IC1
IC2
IC3
IC4
Repetition counter
PSC
(prescaler)
CK_CNT
Prescaler
CC1I
IC1PS
CC2I
Prescaler
IC2PS
CC3I
U
Prescaler
IC3PS
CC4I
U
IC4PS
Prescaler
U
CNT
(counter)
CC1I
Capture/Compare
1 Register
OC1REF
CC2I
Capture/Compare
2 Register
OC2REF
Capture/Compare
3 Register
Capture/Compare
4 Register
CC3I
OC3REF
CC4I
DTG[7:0] registers
OC4REF
DTG
DTG
DTG
Output control
Output control
OC2N
Output control
Output control
OC3
OC4
BI
Clock failure event from clock controller
CSS (Clock Security System)
Interrupt & DMA output
Event
MS39906V3
294/1136 RM0008 Rev 21
RM0008 Advanced-control timers (TIM1 and TIM8)
14.3 TIM1 and TIM8 functional description
The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.
The time-base unit includes:
Counter register (TIMx_CNT)
Prescaler register (TIMx_PSC)
Auto-reload register (TIMx_ARR)
Repetition counter register (TIMx_RCR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detailed for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.
and
Figure 54 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:
RM0008 Rev 21 295/1136
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Advanced-control timers (TIM1 and TIM8) RM0008
Figure 53. Counter timing diagram with prescaler division change from 1 to 2
CK_PSC
CEN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Prescaler control register
F7
0
F8 F9 FA FB
Write a new value in TIMx_PSC
Prescaler buffer
0
FC 00 01
1
1
02 03
Prescaler counter
0 0 1 0 1 0 1 0 1
MS31076V2
Figure 54. Counter timing diagram with prescaler division change from 1 to 4
CK_PSC
CEN
Timerclock = CK_CNT
Counter register
Update event (UEV)
F7 F8 F9
0
Prescaler control register
Write a new value in TIMx_PSC
0
Prescaler buffer
0
Prescaler counter
FA FB FC 00
3
3
01
0 1 2 3 0 1 2 3
MS31077V2
296/1136 RM0008 Rev 21
RM0008 Advanced-control timers (TIM1 and TIM8)
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register plus one
(TIMx_RCR+1). Else the update event is generated at each counter overflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
The repetition counter is reloaded with the content of TIMx_RCR register,
The auto-reload shadow register is updated with the preload value (TIMx_ARR),
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).
The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.
Figure 55. Counter timing diagram, internal clock divided by 1
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
RM0008 Rev 21
MS31078V3
297/1136
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Advanced-control timers (TIM1 and TIM8)
Figure 56. Counter timing diagram, internal clock divided by 2
RM0008
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register 0034 0035 0036 0000 0001 0002 0003
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MS31079V3
Figure 57. Counter timing diagram, internal clock divided by 4
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
0035 0036 0000 0001
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MS31080V3
Figure 58. Counter timing diagram, internal clock divided by N
CK_PSC
Timerclock = CK_CNT
Counter register
1F 20 00
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MS31081V3
298/1136 RM0008 Rev 21
RM0008 Advanced-control timers (TIM1 and TIM8)
Figure 59. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
CK_PSC
CEN
Timerclock = CK_CNT
Counter register
31
Counter overflow
32 33 34 35 36 00 01 02 03 04 05 06 07
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register FF 36
Write a new value in TIMx_ARR
MS31082V3
Figure 60. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
CK_PSC
CEN
Timerclock = CK_CNT
Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07
Counter overflow
Update event (UEV)
Update interrupt flag
(UIF)
Auto-reload preload register
F5
Auto-reload shadow register
Write a new value in TIMx_ARR
F5
36
36
MS31083V2
RM0008 Rev 21 299/1136
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Advanced-control timers (TIM1 and TIM8) RM0008
Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.
If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register plus one
(TIMx_RCR+1). Else the update event is generated at each counter underflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
The repetition counter is reloaded with the content of TIMx_RCR register
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register)
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one
The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.
300/1136 RM0008 Rev 21
RM0008 Advanced-control timers (TIM1 and TIM8)
Figure 61. Counter timing diagram, internal clock divided by 1
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F
Counter underflow
(cnt_udf)
Update event (UEV)
Update interrupt flag
(UIF)
MS31184V1
Figure 62. Counter timing diagram, internal clock divided by 2
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
0002 0001 0000 0036 0035 0034 0033
Counter underflow
Update event (UEV)
Update interrupt flag
(UIF)
MS31185V1
RM0008 Rev 21 301/1136
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Advanced-control timers (TIM1 and TIM8)
Figure 63. Counter timing diagram, internal clock divided by 4
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register 0001 0000 0036 0035
RM0008
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 64. Counter timing diagram, internal clock divided by N
MS40510V1
CK_PSC
Timerclock = CK_CNT
Counter register 20 1F 00 36
Counter underflow
Update event (UEV)
Update interrupt flag
(UIF)
MS31187V1
302/1136 RM0008 Rev 21
RM0008 Advanced-control timers (TIM1 and TIM8)
Figure 65. Counter timing diagram, update event when repetition counter is not used
CK_PSC
CEN
Timerclock = CK_CNT
Counter register
Counter underflow
05 04 03 02 01 00 36 35 34 33 32 31 30 2F
Update event (UEV)
Update interrupt flag
(UIF)
Auto-reload preload register
FF 36
Write a new value in TIMx_ARR
MS31188V1
Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3,
CMS = "11").
In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
RM0008 Rev 21 303/1136
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Advanced-control timers (TIM1 and TIM8) RM0008
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
The repetition counter is reloaded with the content of TIMx_RCR register
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register)
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock frequencies.
Figure 66. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
CK_PSC
CEN
Timerclock = CK_CNT
Counter register
Counter underflow
Counter overflow
04 03 02 01 00 01 02 03 04 05 06 05 04 03
Update event (UEV)
Update interrupt flag (UIF)
1.
Here, center-aligned mode 1 is used (for more details refer to
Section 14.4: TIM1 and TIM8 registers ).
Figure 67. Counter timing diagram, internal clock divided by 2
CK_PSC
MS31189V2
CNT_EN
Timerclock = CK_CNT
Counter register 0003 0002 0001 0000 0001 0002 0003
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
MS31190V2
304/1136 RM0008 Rev 21
RM0008 Advanced-control timers (TIM1 and TIM8)
Figure 68. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
0034 0035 0036 0035
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
1.
Center-aligned mode 2 or 3 is used with an UIF on overflow.
Figure 69. Counter timing diagram, internal clock divided by N
CK_PSC
MS31191V2
Timerclock = CK_CNT
Counter register 20
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
1F 01 00
MS31192V2
RM0008 Rev 21 305/1136
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Advanced-control timers (TIM1 and TIM8) RM0008
Figure 70. Counter timing diagram, update event with ARPE=1 (counter underflow)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
06 05 04 03 02 01 00 01 02 03 04 05 06 07
Update interrupt flag (UIF)
Auto-reload preload register FD 36
Write a new value in TIMx_ARR
Auto-reload active register
FD 36
MS31193V3
Figure 71. Counter timing diagram, Update event with ARPE=1 (counter overflow)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
FD
Write a new value in TIMx_ARR
Auto-reload active register FD
36
36
MS31194V2
Section 14.3.1: Time-base unit
describes how the update event (UEV) is generated with respect to the counter overflows/underflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N+1 counter overflows or underflows, where N is the value in the TIMx_RCR repetition counter register.
306/1136 RM0008 Rev 21
RM0008 Advanced-control timers (TIM1 and TIM8)
The repetition counter is decremented:
At each counter overflow in upcounting mode,
At each counter underflow in downcounting mode,
At each counter overflow and at each counter underflow in center-aligned mode.
Although this limits the maximum number of repetition to 128 PWM cycles, it makes it possible to update the duty cycle twice per PWM period. When refreshing compare registers only once per PWM period in center-aligned mode, maximum resolution is
2xT ck
, due to the symmetry of the pattern.
The repetition counter is an auto-reload type; the repetition rate is maintained as defined by the TIMx_RCR register value (refer to
). When the update event is generated by software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the TIMx_RCR register.
In center-aligned mode, for odd values of RCR, the update event occurs either on the overflow or on the underflow depending on when the RCR register was written and when the counter was started. If the RCR was written before starting the counter, the UEV occurs on the overflow. If the RCR was written after starting the counter, the UEV occurs on the underflow. For example for RCR = 3, the UEV is generated on each 4th overflow or underflow event depending on when RCR was written.
Figure 72. Update rate examples depending on mode and TIMx_RCR register settings
Counter
TIMx_CNT
Counter-aligned mode
Upcounting
Edge-aligned mode
Downcounting
TIMx_RCR = 0
UEV
TIMx_RCR = 1
UEV
TIMx_RCR = 2
UEV
TIMx_RCR = 3
UEV
TIMx_RCR = 3 and re-synchronization
UEV
(by SW) (by SW) (by SW)
UEV
Update event : Preload registers transferred to active registers and update interrupt generated
Update Event if the repetition counter underflow occurs when the counter is equal to the auto-reload value.
MSv31195V1
RM0008 Rev 21 307/1136
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Advanced-control timers (TIM1 and TIM8) RM0008
The counter clock can be provided by the following clock sources:
Internal clock (CK_INT)
External clock mode1: external input pin
External clock mode2: external trigger input ETR
Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, the user can configure Timer 1 to act as a prescaler for Timer 2. Refer to
Using one timer as prescaler for another timer for more details.
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.
shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.
Figure 73. Control circuit in normal mode, internal clock divided by 1
Internal clock
CEN=CNT_EN
UG
CNT_INIT
Counter clock = CK_CNT = CK_PSC
Counter register 31 3 2 33 34 35 36 00 01 02 03 04 05 06 07
MS31085V2
External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on a selected input.
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RM0008 Advanced-control timers (TIM1 and TIM8)
Figure 74. TI2 external clock connection example
TIMx_SMCR
TS[2:0]
TI2
Filter
ICF[3:0]
TIMx_CCMR1
Edge detector
TI2F_Rising
TI2F_Falling
0
1
CC2P
TIMx_CCER
ITRx
TI1_ED
TI1FP1
TI2FP2
ETRF
0xx
100
101
110
111 or
TI2F or
TI1F or
TRGI
ETRF
CK_INT
(internal clock)
Encoder mode
External clock mode 1
External clock mode 2
Internal clock mode
ECE SMS[2:0]
TIMx_SMCR
CK_PSC
Note:
MS31196V1
For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure:
1.
Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000).
3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register.
4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.
5. Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register.
6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The capture prescaler is not used for triggering, so the user does not need to configure it.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input.
RM0008 Rev 21 309/1136
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Advanced-control timers (TIM1 and TIM8)
Figure 75. Control circuit in external clock mode 1
TI2
CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
TIF
34 35
Write TIF=0
RM0008
36
ETR pin
MS31087V2
External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
gives an overview of the external trigger input block.
Figure 76. External trigger input block
ETR
0
1
Divider
/1, /2, /4, /8
ETP
TIMx_SMCR
ETPS[1:0]
TIMx_SMCR
ETRP f
DTS
Filter downcounter
ETF[3:0]
TIMx_SMCR or
TI2F or
TI1F or Encoder mode
TRGI
ETRF
CK_INT
(internal clock)
External clock mode 1
External clock mode 2
Internal clock mode
CK_PSC
ECE SMS[2:0]
TIMx_SMCR
MS33116V1
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RM0008 Advanced-control timers (TIM1 and TIM8)
For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure:
1.
As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal.
Figure 77. Control circuit in external clock mode 2 f
CK_INT
CNT_EN
ETR
ETRP
ETRF
Counter clock =
CK_INT =CK_PSC
Counter register 34 35 36
MS33111V2
Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
give an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS).
RM0008 Rev 21 311/1136
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Advanced-control timers (TIM1 and TIM8) RM0008
Figure 78. Capture/compare channel (example: channel 1 input stage)
TI1F_ED
To the slave mode controller
TI1 f
DTS
Filter downcounter
TI1F
ICF[3:0]
TIMx_CCMR1
Edge detector
TI1F_Rising
TI1F_Falling
CC1P/CC1NP
TIMx_CCER
TI2F_Rising
(from channel 2)
TI2F_Falling
(from channel 2)
0
1
0 TI1FP1
1
TI2FP1
01
10
IC1 Divider
/1, /2, /4, /8
IC1PS
TRC
(from slave mode controller)
11
CC1S[1:0] ICPS[1:0]
TIMx_CCMR1
CC1E
TIMx_CCER
MS33115V1
The output stage generates an intermediate waveform that is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Figure 79. Capture/compare channel 1 main circuit
APB Bus
Read CCR1H
S
Read CCR1L
R
CC1S[1]
CC1S[0]
IC1PS
CC1E
MCU-peripheral interface
8 8
S write CCR1H write_in_progress read_in_progress
Input mode
Capture/compare preload register capture_transfer
Capture/compare shadow register
Capture compare_transfer
Comparator
Output mode
CNT>CCR1
R write CCR1L
CC1S[1]
CC1S[0]
OC1PE
OC1PE
UEV
(from time base unit)
TIMx_CCMR1
Counter
CNT=CCR1
CC1G
TIMx_EGR
MS31089V3
312/1136 RM0008 Rev 21
RM0008 Advanced-control timers (TIM1 and TIM8)
ETRF
Figure 80. Output stage of capture/compare channel (channel 1 to 3)
To the master mode controller
0
CNT>CCR1
Output mode
CNT=CCR1 controller
OCxREF
(1)
OC5REF
OC1REF
Output selector
OC1REFC
OC1_DT
Dead-time generator
OC1N_DT
‘0’
‘0’ x0
01
11
11
10
0x
1
CC1P
TIM1_CCER
0
1
Output enable circuit
Output enable circuit
OC1
OC1N
OC1CE OC1M[3:0]
TIM1_CCMR1
DTG[7:0]
TIM1_BDTR
CC1NE CC1E TIM1_CCER
CC1NE CC1E
TIM1_CCER
CC1NP
TIM1_CCER
MOE OSSI OSSR
TIM1_BDTR
MS35909V1
Figure 81. Output stage of capture/compare channel (channel 4)
To the master mode controller
ETR
CNT>CCR4
CNT>CCR4
Output mode controller
OC4REF
0
1
CC4P
TIM1_CCER
Output enable circuit
OC4
CC4E TIM1_CCER
OC1M[3:0]
TIM1_CCMR2
MOE OSSI TIM1_BDTR
OIS4 TIM1_CR2
MS37370V1
The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.
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Note:
In Input capture mode, the Capture/Compare registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when written to ‘0’.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure:
Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only.
Program the needed input filter duration with respect to the signal connected to the timer (by programming ICxF bits in the TIMx_CCMRx register if the input is a TIx input).
Let’s imagine that, when toggling, the input signal is not stable during at must five internal clock cycles. We must program a filter duration longer than these five clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected (sampled at f
DTS the TIMx_CCMR1 register.
frequency). Then write IC1F bits to 0011 in
Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in the TIMx_CCER register (rising edge in this case).
Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIMx_CCMR1 register).
Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.
When an input capture occurs:
The TIMx_CCR1 register gets the value of the counter on the active transition.
CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared.
An interrupt is generated depending on the CC1IE bit.
A DMA request is generated depending on the CC1DE bit.
In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data.
IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register.
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14.3.7 PWM input mode
This mode is a particular case of input capture mode. The procedure is the same except:
Two ICx signals are mapped on the same TIx input.
These 2 ICx signals are active on edges with opposite polarity.
One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode.
For example, user can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value):
Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected).
Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P bit to ‘0’ (active on rising edge).
Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected).
Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ (active on falling edge).
Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register
(TI1FP1 selected).
Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.
Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.
Figure 82. PWM input mode timing
1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only
TI1FP1 and TI2FP2 are connected to the slave mode controller.
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14.3.8 Forced output mode
In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, the user just needs to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=0 (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below.
14.3.9 Output compare mode
This function is used to control an output waveform or indicating when a period of time has elapsed.
When a match is found between the capture/compare register and the counter, the output compare function:
Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.
Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One Pulse mode).
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Procedure:
1.
Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CCxIE bit if an interrupt request is to be generated.
4. Select the output mode. For example:
– Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx
– Write OCxPE = 0 to disable preload register
– Write CCxP = 0 to select active high polarity
– Write CCxE = 1 to enable the output
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in
.
Figure 83. Output compare mode, toggle on OC1.
Write B201h in the CC1R register
TIM1_CNT 0039
TIM1_CCR1
OC1REF= OC1
003A
003A
003B B200
B201
B201
Match detected on CCR1
Interrupt generated if enabled
MS31092V2
Pulse Width Modulation mode allows generating a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. The corresponding preload register must be enabled by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, the user must initialize all the registers by setting the UG bit in the TIMx_EGR register.
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OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).
Refer to the TIMx_CCER register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx TIMx_CNT or TIMx_CNT TIMx_CCRx (depending on the direction of the counter).
The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register.
PWM edge-aligned mode
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to
.
In the following example, we consider PWM mode 1. The reference PWM signal
OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’.
shows some edge-aligned PWM waveforms in an example where
TIMx_ARR=8.
Figure 84. Edge-aligned PWM waveforms (ARR=8)
Counter register
CCRx=4
OCXREF
CCxIF
0 1 2 3 4 5 6 7 8 0 1
CCRx=8
OCXREF
CCxIF
CCRx>8
OCXREF ‘1’
CCxIF
CCRx=0
OCXREF ‘0’
CCxIF
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Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to
In PWM mode 1, the reference signal OCxRef is low as long as
TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals).
The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
Center-aligned mode (up/down counting)
.
shows some center-aligned PWM waveforms in an example where:
TIMx_ARR=8,
PWM mode is the PWM mode 1,
The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register.
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Counter register
Figure 85. Center-aligned PWM waveforms (ARR=8)
0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1
CCRx = 4
OCxREF
CCxIF CMS=01
CMS=10
CMS=11
CCRx = 7
OCxREF
CCxIF
CCRx = 8
OCxREF
'1'
CMS=10 or 11
CCxIF CMS=01
CMS=10
CMS=11
CCRx > 8
OCxREF
'1'
CCxIF
CMS=01
CMS=10
CMS=11
CCRx = 0
OCxREF
'0'
CCxIF CMS=01
CMS=10
CMS=11 ai14681b
Hints on using center-aligned mode:
When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.
Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular:
– The direction is not updated if the user writes a value in the counter greater than the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it will continue to count up.
– The direction is updated if the user writes 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated.
The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running.
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The advanced-control timers (TIM1 and TIM8) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs.
This time is generally known as dead-time and it has to be adjust it depending on the devices connected to the outputs and their characteristics (intrinsic delays of level-shifters, delays due to power switches...)
User can select the polarity of the outputs (main output OCx or complementary OCxN) independently for each output. This is done by writing to the CCxP and CCxNP bits in the
TIMx_CCER register.
The complementary signals OCx and OCxN are activated by a combination of several control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx,
OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to Table 83
for more details. In particular, the dead-time is activated when switching to the IDLE state
(MOE falling down to 0).
Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. DTG[7:0] bits of the TIMx_BDTR register are used to control the dead-time generation for all channels. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high:
The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge.
The OCxN output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge.
If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated.
The following figures show the relationships between the output signals of the dead-time generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1,
CCxE=1 and CCxNE=1 in these examples)
Figure 86. Complementary output with dead-time insertion.
OCxREF
OCx delay
OCxN delay
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Figure 87. Dead-time waveforms with delay greater than the negative pulse.
OCxREF
OCx
OCxN delay
MS31096V1
Figure 88. Dead-time waveforms with delay greater than the positive pulse.
OCxREF
OCx
OCxN delay
Note:
MS31097V1
The dead-time delay is the same for each of the channels and is programmable with the
for delay calculation.
Re-directing OCxREF to OCx or OCxN
In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER register.
This allows the user to send a specific waveform (such as PWM or static active level) on one output while the complementary remains at its inactive level. Other possibilities are to have both outputs at inactive level or both outputs active and complementary with dead-time.
When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when
OCxREF is low.
14.3.12 Using the break function
When using the break function, the output enable signals and inactive levels are modified according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register,
OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs cannot be set both to active level at a given time. Refer to
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Note:
Advanced-control timers (TIM1 and TIM8)
The break source can be either the break input pin or a clock failure event, generated by the
Clock Security System (CSS), from the Reset Clock Controller. For further information on the Clock Security System, refer to
Section 7.2.7: Clock security system (CSS) .
When exiting from reset, the break circuit is disabled and the MOE bit is low. User can enable the break function by setting the BKE bit in the TIMx_BDTR register. The break input polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1
APB clock period to correctly read back the bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous and the synchronous signals. In particular, if MOE is written to 1 whereas it was low, a delay
(dummy instruction) must be inserted before reading it correctly. This is because the user writes an asynchronous signal, but reads a synchronous signal.
When a break occurs (selected level on the break input):
The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or in reset state (selected by the OSSI bit). This feature functions even if the MCU oscillator is off.
Each output channel is driven with the level programmed in the OISx bit in the
TIMx_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable output else the enable output remains high.
When complementary outputs are used:
– The outputs are first put in reset state inactive state (depending on the polarity).
This is done asynchronously so that it works even if no clock is provided to the timer.
– If the timer clock is still present, then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the OISx and OISxN bits after a dead-time. Even in this case, OCx and OCxN cannot be driven to their active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).
– If OSSI=0 then the timer releases the enable outputs else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high.
The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be generated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if the BDE bit in the TIMx_DIER register is set.
If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again at the next update event UEV. This can be used to perform a regulation, for instance.
Else, MOE remains low until it is written to ‘1’ again. In this case, it can be used for security and the break input can be connected to an alarm from power drivers, thermal sensors or any security components.
The break inputs is acting on level. Thus, the MOE cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF cannot be cleared.
The break can be generated by the BRK input which has a programmable polarity and an enable bit BKE in the TIMx_BDTR register.
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There are two solutions to generate a break:
By using the BRK input which has a programmable polarity and an enable bit BKE in the TIMx_BDTR register
By software through the BG bit of the TIMx_EGR register.
In addition to the break input and the output management, a write protection has been implemented inside the break circuit to safeguard the application. It allows freezing the configuration of several parameters (dead-time duration, OCx/OCxN polarities and state when disabled, OCxM configurations, break enable and polarity). The user can choose from three levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to
Section 14.4.18: TIM1 and TIM8 break and dead-time register (TIMx_BDTR) . The LOCK
bits can be written only once after an MCU reset.
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shows an example of behavior of the outputs in response to a break.
Figure 89. Output behavior in response to a break.
BREAK (MOE )
OCxREF
OCx
(OCxN not implemented, CCxP=0, OISx=1)
OCx
(OCxN not implemented, CCxP=0, OISx=0)
OCx
(OCxN not implemented, CCxP=1, OISx=1)
OCx
(OCxN not implemented, CCxP=1, OISx=0)
OCx
OCxN delay delay
(CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay
OCx
OCxN delay delay
(CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1) delay
OCx
OCxN
(CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1) delay
OCx
OCxN
(CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0) delay
OCx
OCxN
(CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1)
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The OCxREF signal for a given channel can be driven Low by applying a High level to the
ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The
OCxREF signal remains Low until the next update event, UEV, occurs.
This function can only be used in output compare and PWM modes, and does not work in forced mode.
For example, the ETR signal can be connected to the output of a comparator to be used for current handling. In this case, the ETR must be configured as follow:
1.
The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR register set to ‘00’.
2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to
‘0’.
3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be configured according to the user needs.
shows the behavior of the OCxREF signal when the ETRF Input becomes High, for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in
PWM mode.
Figure 90. Clearing TIMx OCxREF
Counter (CNT)
(CCRx)
ETRF
OCxREF (OCxCE = ‘0’)
OCxREF (OCxCE = ‘1’)
ETRF becomes high ETRF still high
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When complementary outputs are used on a channel, preload bits are available on the
OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the
COM commutation event. The user can thus program in advance the configuration for the next step and change the configuration of all the channels at the same time. COM can be generated by software by setting the COM bit in the TIMx_EGR register or by hardware (on
TRGI rising edge).
A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can generate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request
(if the COMDE bit is set in the TIMx_DIER register).
describes the behavior of the OCx and OCxN outputs when a COM event occurs, in 3 different examples of programmed configurations.
Figure 91. 6-step generation, COM example (OSSR=1)
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One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. Select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be:
In upcounting: CNT < CCRx ARR (in particular, 0 < CCRx)
In downcounting: CNT > CCRx
Figure 92. Example of one pulse mode.
TI2
OC1REF
OC1
TIM1_ARR
TIM1_CCR1
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DELAY t
PULSE t
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For example the user may want to generate a positive pulse on OC1 with a length of t
PULSE and after a delay of t
DELAY
as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.
TI2FP2 must detect a rising edge, write CC2P=’0’ in the TIMx_CCER register.
Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in the TIMx_SMCR register.
TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register
(trigger mode).
The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).
The t
DELAY is defined by the value written in the TIMx_CCR1 register.
The t
PULSE
is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1).
Let us say the user wants to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the
RM0008 Rev 21
RM0008 Advanced-control timers (TIM1 and TIM8) auto-reload value. To do this, enable PWM mode 2 by writing OC1M=111 in the
TIMx_CCMR1 register. The user can optionally enable the preload registers by writing
OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case the compare value must be written in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0’ in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
The user only wants one pulse (Single mode), so '1’ must be written in the OPM bit in the
TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected.
Particular case: OCx fast enable:
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay t
DELAY
min we can get.
If the user wants to output a waveform with the minimum delay, the OCxFE bit in the
TIMx_CCMRx register must be set. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and
SMS=’011’ if it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. When needed, the user can program the input filter as well.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 81 . The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So user must configure TIMx_ARR before starting. in the same way, the capture, compare, prescaler, repetition counter, trigger output features continue to work as normal. Encoder mode and
External clock mode 2 are not compatible and must not be selected together.
In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor.
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Table 81 summarizes the possible combinations, assuming TI1 and TI2 do not switch at the
same time.
Active edge
Counting on
TI1 only
Counting on
TI2 only
Counting on
TI1 and TI2
Table 81. Counting direction versus encoder signals
TI1FP1 signal
Level on opposite signal
(TI1FP1 for TI2, TI2FP2 for TI1)
Rising Falling
TI2FP2 signal
Rising Falling
High
Low
High
Low
High
Low
Down Up
Up Down
No Count No Count
No Count No Count
Down Up
Up Down
No Count No Count
No Count No Count
Up Down
Down
Up
Down
Up
Down
Up
An external incremental encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset.
gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following:
CC1S=’01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1).
CC2S=’01’ (TIMx_CCMR2 register, TI1FP2 mapped on TI2).
CC1P=’0’, and IC1F = ‘0000’ (TIMx_CCER register, TI1FP1 non-inverted,
TI1FP1=TI1).
CC2P=’0’, and IC2F = ‘0000’ (TIMx_CCER register, TI1FP2 non-inverted, TI1FP2=
TI2).
SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling edges).
CEN=’1’ (TIMx_CR1 register, Counter enabled).
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Figure 93. Example of counter operation in encoder interface mode.
forward jitter backward jitter forward
TI1
TI2
Counter up down up
MS33107V1
gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’).
Figure 94. Example of encoder interface mode with TI1FP1 polarity inverted.
forward jitter backward jitter forward
TI1
TI2
Counter down up down
MS33108V1
The timer, when configured in Encoder Interface mode provides information on the sensor’s current position.The user can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. This can be done by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a
DMA request generated by a real-time clock.
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14.3.17 Timer input XOR function
The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and
TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input capture. An example of this feature used to interface Hall sensors is given in
.
14.3.18 Interfacing with Hall sensors
This is done using the advanced-control timers (TIM1 or TIM8) to generate PWM signals to drive the motor and another timer TIMx (TIM2, TIM3, TIM4 or TIM5) referred to as
“interfacing timer” in
Figure 95 . The “interfacing timer” captures the 3 timer input pins
(TIMx_CH1, TIMx_CH2, and TIMx_CH3) connected through a XOR to the TI1 input channel
(selected by setting the TI1S bit in the TIMx_CR2 register).
The slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus, each time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a time base triggered by any change on the Hall inputs.
On the “interfacing timer”, capture/compare channel 1 is configured in capture mode,
capture signal is TRC (see Figure 78 ). The captured value, which corresponds to the time
elapsed between 2 changes on the inputs, gives information about motor speed.
The “interfacing timer” can be used in output mode to generate a pulse which changes the configuration of the channels of the advanced-control timer (TIM1 or TIM8) (by triggering a
COM event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this, the interfacing timer channel must be programmed so that a positive pulse is generated after a programmed delay (in output compare or PWM mode). This pulse is sent to the advanced-control timer (TIM1 or TIM8) through the TRGO output.
Example: the user wants to change the PWM configuration of the advanced-control timer
TIM1 after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers.
Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the
TIMx_CR2 register to ‘1’,
Program the time base: write the TIMx_ARR to the max value (the counter must be cleared by the TI1 change. Set the prescaler to get a maximum counter period longer than the time between 2 changes on the sensors,
Program channel 1 in capture mode (TRC selected): write the CC1S bits in the
TIMx_CCMR1 register to ‘11’. The user can also program the digital filter if needed,
Program channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to ‘111’ and the CC2S bits to ‘00’ in the TIMx_CCMR1 register,
Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 register to ‘101’,
In the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the timer is programmed to generate PWM signals, the capture/compare control signals are preloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the trigger input (CCUS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are written after a COM event for the next step (this can be done in an interrupt subroutine generated by the rising edge of OC2REF).
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describes this example.
Figure 95. Example of Hall sensor interface
TIH1
TIH2
TIH3
Counter (CNT)
(CCR2)
CCR1
TRGO=OC2REF
C7A3 C7A8 C794 C7A5 C7AB C796
COM
OC1
OC1N
OC2
OC2N
OC3
OC3N
Write CCxE, CCxNE and OCxM for next step ai17335b
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14.3.19 TIMx and external trigger synchronization
The TIMx timer can be synchronized with an external trigger in several modes: Reset mode,
Gated mode and Trigger mode.
Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so there’s no need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write
CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edges only).
Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
Start the counter by writing CEN=1 in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input.
Figure 96. Control circuit in reset mode
TI1
UG
Counter clock = CK_CNT = CK_PSC
Counter register
30 31 32 33 34 35 36 00 01 02 03 00 01 02 03
TIF
MS31401V3
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Slave mode: Gated mode
The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so the user does not need to configure it. The
CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register.
Write CC1P=1 in TIMx_CCER register to validate the polarity (and detect low level only).
Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input.
Figure 97. Control circuit in gated mode
TI1
CNT_EN
Counter clock = ck_cnt = ck_psc
Counter register 30 31 32 33 34 35 36 37 38
TIF
Write TIF=0
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Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so there’s no need to configure it. The CC2S bits are configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write CC2P=1 in TIMx_CCER register to validate the polarity (and detect low level only).
Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input.
Figure 98. Control circuit in trigger mode
TI2
CNT_EN
Counter clock = ck_cnt = ck_psc
Counter register 34 35 36 37 38
TIF
MS31403V2
Slave mode: external clock mode 2 + trigger mode
The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input (in reset mode, gated mode or trigger mode). It is recommended not to select ETR as TRGI through the TS bits of
TIMx_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs:
1.
Configure the external trigger input circuit by programming the TIMx_SMCR register as follows:
– ETF = 0000: no filter
– ETPS = 00: prescaler disabled
– ETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2.
2. Configure the channel 1 as follows, to detect rising edges on TI:
– IC1F=0000: no filter.
– The capture prescaler is not used for triggering and does not need to be configured.
– CC1S=01 in TIMx_CCMR1 register to select only the input capture source
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– CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edge only).
3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input.
Figure 99. Control circuit in external clock mode 2 + trigger mode
TI1
CEN/CNT_EN
ETR
Counter clock = CK_CNT = CK_PSC
Counter register
TIF
34 35 36
MS33110V1
Note:
The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 15.3.15: Timer synchronization for details.
The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
When the microcontroller enters debug mode (Cortex ® -M3 core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
For safety purposes, when the counter is stopped (DBG_TIMx_STOP = 1 in
DBGMCU_APBx_FZ register), the outputs are disabled (as if the MOE bit was reset). The outputs can either be forced to an inactive state (OSSI bit = 1), or have their control taken over by the GPIO controller (OSSI bit = 0) to force them to Hi-Z.
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14.4 TIM1 and TIM8 registers
for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
14.4.1 TIM1 and TIM8 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
15 14 13 12
Reserved
11 10 9 8
CKD[1:0] rw rw
7
ARPE rw
6 5
CMS[1:0] rw rw
4
DIR rw
3
OPM rw
2
URS rw
1
UDIS rw
0
CEN rw
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0] : Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (t
DTS
)used by the dead-time generators and the digital filters
(ETR, TIx),
00: t
DTS
=t
CK_INT
01: t
DTS
=2*t
CK_INT
10: t
DTS
=4*t
CK_INT
11: Reserved, do not program this value
Bit 7 ARPE : Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:5 CMS[1:0] : Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)
Bit 4 DIR : Direction
0: Counter used as upcounter
1: Counter used as downcounter
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
Bit 3 OPM : One pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
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Bit 2 URS : Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Bit 1 UDIS : Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN : Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
14.4.2 TIM1 and TIM8 control register 2 (TIMx_CR2)
Address offset: 0x04
Reset value: 0x0000
15
Res.
14 13 12 11 10 9 8
OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 rw rw rw rw rw rw rw
7
TI1S rw
Bit 15 Reserved, must be kept at reset value.
Bit 14 OIS4 : Output Idle state 4 (OC4 output) refer to OIS1 bit
Bit 13 OIS3N : Output Idle state 3 (OC3N output) refer to OIS1N bit
Bit 12 OIS3 : Output Idle state 3 (OC3 output) refer to OIS1 bit
Bit 11 OIS2N : Output Idle state 2 (OC2N output) refer to OIS1N bit
Bit 10 OIS2 : Output Idle state 2 (OC2 output) refer to OIS1 bit
6 rw
5
MMS[2:0] rw
4 rw
3 2
CCDS CCUS rw rw
1
Res.
0
CCPC rw
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Bit 9 OIS1N : Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
Bit 8 OIS1 : Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
Bit 7 TI1S : TI1 selection
0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Bits 6:4 MMS[2:0] : Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO).
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Compare - OC3REF signal is used as trigger output (TRGO)
111: Compare - OC4REF signal is used as trigger output (TRGO)
Note: The clock of the slave timer and ADC must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
Bit 3 CCDS : Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
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Bit 2 CCUS : Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, must be kept at reset value.
Bit 0 CCPC : Capture/compare preloaded control
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on
TRGI, depending on the CCUS bit).
Note: This bit acts only on channels that have a complementary output.
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14.4.3 TIM1 and TIM8 slave mode control register (TIMx_SMCR)
Address offset: 0x08
Reset value: 0x0000
RM0008
15
ETP rw
14
ECE rw
13 12
ETPS[1:0] rw rw
11 rw
10
ETF[3:0]
9 rw rw
8 rw
7
MSM rw
6 rw
5
TS[2:0] rw
4 rw
3
Res.
Res.
2 rw
1
SMS[2:0] rw
0 rw
Bit 15 ETP : External trigger polarity
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge.
1: ETR is inverted, active at low level or falling edge.
Bit 14 ECE : External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with
TRGI connected to ETRF (SMS=111 and TS=111).
2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 111).
3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
Bits 13:12 ETPS[1:0] : External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8
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Bits 11:8 ETF[3:0] : External trigger filter
This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
0000: No filter, sampling is done at f
DTS
0001: f
SAMPLING
=f
CK_INT
, N=2
0010: f
SAMPLING
=f
CK_INT
, N=4
, N=8 0011: f
SAMPLING
0100: f
SAMPLING
0101: f
SAMPLING
0110: f
SAMPLING
=f
CK_INT
=f
DTS
=f
DTS
=f
DTS
/2, N=6
/2, N=8
/4, N=6
/4, N=8 0111: f
SAMPLING
=f
DTS
1000: f
SAMPLING
1001: f
SAMPLING
1010: f
SAMPLING
1011: f
SAMPLING
1100: f
SAMPLING
=f
DTS
=f
DTS
=f
DTS
=f
DTS
=f
DTS
/8, N=6
/8, N=8
/16, N=5
/16, N=6
/16, N=8
/32, N=5 1101: f
SAMPLING
1110: f
SAMPLING
1111: f
SAMPLING
=f
DTS
=f
DTS
=f
DTS
/32, N=6
/32, N=8
Bit 7 MSM: Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 6:4 TS[2:0]: Trigger selection
This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0)
001: Internal Trigger 1 (ITR1)
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
See
Table 82 for more details on ITRx meaning for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
Bit 3 Reserved, must be kept at reset value.
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Bits 2:0 SMS: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control register description.
000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal.
The clock of the slave timer must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
Slave TIM
Table 82. TIMx Internal trigger connection
(1)
ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011)
TIM1
TIM8
TIM5_TRGO
TIM1_TRGO
TIM2_TRGO
TIM2_TRGO
TIM3_TRGO
TIM4_TRGO
1. When a timer is not present in the product, the corresponding trigger ITRx is not available.
TIM4_TRGO
TIM5_TRGO
14.4.4 TIM1 and TIM8 DMA/interrupt enable register (TIMx_DIER)
15
Res.
Address offset: 0x0C
Reset value: 0x0000
14 13 12 11 10 9 8
TDE COMDE CC4DE CC3DE CC2DE CC1DE UDE rw rw rw rw rw rw rw
7
BIE rw
6
TIE rw
5 4 3 2 1
COMIE CC4IE CC3IE CC2IE CC1IE rw rw rw rw rw
Bit 15 Reserved, must be kept at reset value.
Bit 14 TDE : Trigger DMA request enable
0: Trigger DMA request disabled
1: Trigger DMA request enabled
Bit 13 COMDE : COM DMA request enable
0: COM DMA request disabled
1: COM DMA request enabled
0
UIE rw
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Bit 12 CC4DE : Capture/Compare 4 DMA request enable
0: CC4 DMA request disabled
1: CC4 DMA request enabled
Bit 11 CC3DE : Capture/Compare 3 DMA request enable
0: CC3 DMA request disabled
1: CC3 DMA request enabled
Bit 10 CC2DE : Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled
1: CC2 DMA request enabled
Bit 9 CC1DE : Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 8 UDE : Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE : Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 TIE : Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Bit 5 COMIE : COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bit 4 CC4IE : Capture/Compare 4 interrupt enable
0: CC4 interrupt disabled
1: CC4 interrupt enabled
Bit 3 CC3IE : Capture/Compare 3 interrupt enable
0: CC3 interrupt disabled
1: CC3 interrupt enabled
Bit 2 CC2IE : Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE : Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE : Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled
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14.4.5 TIM1 and TIM8 status register (TIMx_SR)
15
Address offset: 0x10
14
Reserved
Reset value: 0x0000
13 12 11 10 9 8
CC4OF CC3OF CC2OF CC1OF Res.
rc_w0 rc_w0 rc_w0 rc_w0 Res.
7
BIF
6
TIF
5 4
COMIF CC4IF
3
CC3IF
2
CC2IF
1
CC1IF
0
UIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CC4OF : Capture/Compare 4 overcapture flag refer to CC1OF description
Bit 11 CC3OF : Capture/Compare 3 overcapture flag refer to CC1OF description
Bit 10 CC2OF : Capture/Compare 2 overcapture flag refer to CC1OF description
Bit 9 CC1OF : Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
Bit 8 Reserved, must be kept at reset value.
Bit 7 BIF : Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
0: No break event occurred.
1: An active level has been detected on the break input.
Bit 6 TIF : Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
Bit 5 COMIF : COM interrupt flag
This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE,
CCxNE, OCxM - have been updated). It is cleared by software.
0: No COM event occurred.
1: COM interrupt pending.
Bit 4 CC4IF : Capture/Compare 4 interrupt flag refer to CC1IF description
Bit 3 CC3IF : Capture/Compare 3 interrupt flag refer to CC1IF description
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Bit 2 CC2IF : Capture/Compare 2 interrupt flag refer to CC1IF description
Bit 1 CC1IF : Capture/Compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow (in downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity)
Bit 0 UIF : Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow or underflow regarding the repetition counter value (update if repetition counter
= 0) and if the UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and
UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by a trigger event (refer to
Section 14.4.3: TIM1 and TIM8 slave mode control register (TIMx_SMCR)
), if URS=0 and UDIS=0 in the TIMx_CR1 register.
14.4.6 TIM1 and TIM8 event generation register (TIMx_EGR)
15 14
Address offset: 0x14
Reset value: 0x0000
13 12 11 10 9 8
Reserved
7
BG w
6
TG w
5 4 3 2 1
COMG CC4G CC3G CC2G CC1G w w w w w
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 BG : Break generation
This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0: No action
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
Bit 6 TG : Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
0
UG w
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Bit 5 COMG : Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware
0: No action
1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels having a complementary output.
Bit 4 CC4G : Capture/Compare 4 generation refer to CC1G description
Bit 3 CC3G : Capture/Compare 3 generation refer to CC1G description
Bit 2 CC2G : Capture/Compare 2 generation refer to CC1G description
Bit 1 CC1G : Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG : Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).
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14.4.7 TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1)
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So the user must take care that the same bit can have a different meaning for the input stage and for the output stage.
15
OC2
CE rw
14 13
OC2M[2:0]
12
IC2F[3:0] rw rw rw
11
OC2
PE
10
OC2
FE
IC2PSC[1:0] rw rw
Output compare mode:
9
CC2S[1:0] rw
8 rw
7
OC1
CE rw
6 5
OC1M[2:0]
IC1F[3:0] rw rw
4 rw
3
OC1
PE
2
OC1
FE
IC1PSC[1:0] rw rw
1
CC1S[1:0] rw
0 rw
Bit 15 OC2CE: Output compare 2 clear enable
Bits 14:12 OC2M[2:0] : Output compare 2 mode
Bit 11 OC2PE : Output compare 2 preload enable
Bit 10 OC2FE : Output compare 2 fast enable
Bits 9:8 CC2S[1:0] : Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
Bit 7 OC1CE: Output compare 1 clear enable
OC1CE: Output compare 1 Clear Enable
0: OC1Ref is not affected by the ETRF Input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input
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Bits 6:4 OC1M : Output compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
2: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode.
Bit 3 OC1PE : Output compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE : Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S : Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).
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Input capture mode
Bits 15:12 IC2F : Input capture 2 filter
Bits 11:10 IC2PSC[1:0] : Input capture 2 prescaler
Bits 9:8 CC2S : Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
Bits 7:4 IC1F[3:0] : Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
0000: No filter, sampling is done at f
DTS
0001: f
SAMPLING
0010: f
SAMPLING
0011: f
SAMPLING
=f
CK_INT
=f
CK_INT
=f
CK_INT
, N=2
, N=4
, N=8
/2, N=6 0100: f
SAMPLING
0101: f
SAMPLING
0110: f
SAMPLING
=f
DTS
=f
DTS
=f
DTS
0111: f
SAMPLING
=f
DTS
/2, N=8
/4, N=6
/4, N=8
1000: f
SAMPLING
1001: f
SAMPLING
1010: f
SAMPLING
1011: f
SAMPLING
=f
DTS
=f
DTS
=f
DTS
=f
DTS
/8, N=6
/8, N=8
/16, N=5
/16, N=6
/16, N=8 1100: f
SAMPLING
1101: f
SAMPLING
1110: f
SAMPLING
=f
DTS
=f
DTS
=f
DTS
1111: f
SAMPLING
=f
DTS
/32, N=5
/32, N=6
/32, N=8
Bits 3:2 IC1PSC : Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S : Capture/Compare 1 Selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).
14.4.8 TIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2)
Address offset: 0x1C
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15
OC4
CE rw
Reset value: 0x0000
14
Refer to the above CCMR1 register description.
13
OC4M[2:0]
IC4F[3:0] rw rw
12 rw
11 10
OC4
PE
OC4
FE
IC4PSC[1:0] rw rw
9 8
CC4S[1:0] rw rw
7
OC3
CE.
rw
6 5
OC3M[2:0]
IC3F[3:0] rw rw
4 rw
Output compare mode
3 2
OC3
PE
OC3
FE
IC3PSC[1:0] rw rw
1
CC3S[1:0] rw
0 rw
Bit 15 OC4CE: Output compare 4 clear enable
Bits 14:12 OC4M : Output compare 4 mode
Bit 11 OC4PE : Output compare 4 preload enable
Bit 10 OC4FE : Output compare 4 fast enable
Bits 9:8 CC4S : Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).
Bit 7 OC3CE: Output compare 3 clear enable
Bits 6:4 OC3M : Output compare 3 mode
Bit 3 OC3PE : Output compare 3 preload enable
Bit 2 OC3FE : Output compare 3 fast enable
Bits 1:0 CC3S : Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).
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RM0008 Advanced-control timers (TIM1 and TIM8)
Input capture mode
Bits 15:12 IC4F : Input capture 4 filter
Bits 11:10 IC4PSC : Input capture 4 prescaler
Bits 9:8 CC4S : Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).
Bits 7:4 IC3F : Input capture 3 filter
Bits 3:2 IC3PSC : Input capture 3 prescaler
Bits 1:0 CC3S : Capture/compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).
14.4.9 TIM1 and TIM8 capture/compare enable register (TIMx_CCER)
15
CC4NP rw
Address offset: 0x20
14
Res.
Reset value: 0x0000
13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4P CC4E CC3NP CC3NE CC3P CC3E CC2NP CC2NE CC2P CC2E CC1NP CC1NE CC1P CC1E rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 15 CC4NP : Capture/Compare 4 complementary output polarity refer to CC1NP description
Bit 14 Reserved, must be kept at reset value.
Bit 13 CC4P : Capture/Compare 4 output polarity refer to CC1P description
Bit 12 CC4E : Capture/Compare 4 output enable refer to CC1E description
Bit 11 CC3NP : Capture/Compare 3 complementary output polarity refer to CC1NP description
Bit 10 CC3NE : Capture/Compare 3 complementary output enable refer to CC1NE description
Bit 9 CC3P : Capture/Compare 3 output polarity refer to CC1P description
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Bit 8 CC3E : Capture/Compare 3 output enable refer to CC1E description
Bit 7 CC2NP : Capture/Compare 2 complementary output polarity refer to CC1NP description
Bit 6 CC2NE : Capture/Compare 2 complementary output enable refer to CC1NE description
Bit 5 CC2P : Capture/Compare 2 output polarity refer to CC1P description
Bit 4 CC2E : Capture/Compare 2 output enable refer to CC1E description
Bit 3 CC1NP : Capture/Compare 1 complementary output polarity
0: OC1N active high.
1: OC1N active low.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output).
Bit 2 CC1NE : Capture/Compare 1 complementary output enable
0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1E bits.
Bit 1 CC1P : Capture/Compare 1 output polarity
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
This bit selects whether IC1 or IC1 is used for trigger or capture operations.
0: non-inverted: capture is done on a rising edge of IC1. When used as external trigger, IC1 is non-inverted.
1: inverted: capture is done on a falling edge of IC1. When used as external trigger, IC1 is inverted.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Bit 0 CC1E : Capture/Compare 1 output enable
CC1 channel configured as output:
0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits.
1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1NE bits.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled.
1: Capture enabled.
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Table 83. Output control bits for complementary OCx and OCxN channels with break feature
Control bits Output states
(1)
MOE bit
OSSI bit
OSSR bit
CCxE bit
CCxNE bit
OCx output state OCxN output state
1 X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Output Disabled (not driven by the timer), OCx=0, OCx_EN=0
Output Disabled (not driven by the timer), OCxN=0, OCxN_EN=0
Output Disabled (not driven by the timer), OCx=0, OCx_EN=0
OCxREF + Polarity OCxN=OCxREF xor CCxNP, OCxN_EN=1
OCxREF + Polarity
OCx=OCxREF xor CCxP,
OCx_EN=1
OCREF + Polarity + dead-time
OCx_EN=1
Output Disabled (not driven by the timer)
OCxN=0, OCxN_EN=0
Complementary to OCREF (not
OCREF) + Polarity + dead-time
OCxN_EN=1
Output Disabled (not driven by the timer)
OCx=CCxP, OCx_EN=0
Output Disabled (not driven by the timer)
OCxN=CCxNP, OCxN_EN=0
Off-State (output enabled with inactive state)
OCx=CCxP, OCx_EN=1
OCxREF + Polarity
OCx=OCxREF xor CCxP,
OCx_EN=1
OCREF + Polarity + dead-time
OCx_EN=1
OCxREF + Polarity
OCxN=OCxREF xor CCxNP,
OCxN_EN=1
Off-State (output enabled with inactive state)
OCxN=CCxNP, OCxN_EN=1
Complementary to OCREF (not
OCREF) + Polarity + dead-time
OCxN_EN=1
0
0
1
1
1
0
0
0
X
1
0
0
1
0
0
1
1
0
1
0
0
1
0
Output Disabled (not driven by the timer)
Asynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP,
OCxN_EN=0
Then if the clock is present: OCx=OISx and OCxN=OISxN after a dead-time, assuming that OISx and OISxN do not correspond to OCX and OCxN both in active state.
1 1 1
Off-State (output enabled with inactive state)
Asynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP,
OCxN_EN=1
Then if the clock is present: OCx=OISx and OCxN=OISxN after a dead-time, assuming that OISx and OISxN do not correspond to OCX and OCxN both in active state
1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept cleared.
Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIOand AFIO registers.
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14.4.10 TIM1 and TIM8 counter (TIMx_CNT)
15 14
Address offset: 0x24
Reset value: 0x0000
13 12 11 10 9 rw rw rw rw rw rw rw
8 7
CNT[15:0] rw rw
Bits 15:0 CNT[15:0] : Counter value
6 rw
5 rw
4 rw
3 rw
2 rw
1 rw
RM0008
14.4.11 TIM1 and TIM8 prescaler (TIMx_PSC)
15 14
Address offset: 0x28
Reset value: 0x0000
13 12 11 10 9 rw rw rw rw rw rw rw
8 7
PSC[15:0] rw rw
6 rw
5 4 3 2 1 0 rw rw rw rw rw rw
Bits 15:0 PSC[15:0] : Prescaler value
The counter clock frequency (CK_CNT) is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).
14.4.12 TIM1 and TIM8 auto-reload register (TIMx_ARR)
15 14
Address offset: 0x2C
Reset value: 0xFFFF
13 12 11 10 9 6 5 rw rw rw rw rw rw rw
8 7
ARR[15:0] rw rw rw rw
4 rw
3 2 1 0 rw rw rw rw
Bits 15:0 ARR[15:0] : Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to Section 14.3.1: Time-base unit for more details about ARR update and behavior.
The counter is blocked while the auto-reload value is null.
0 rw
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14.4.13 TIM1 and TIM8 repetition counter register (TIMx_RCR)
15 14
Address offset: 0x30
Reset value: 0x0000
13 12 11 10 9 8 7 6 5
Reserved rw rw rw
4
REP[7:0]
3 rw rw
2 1 0 rw rw rw
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 REP[7:0] : Repetition counter value
These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event.
It means in PWM mode (REP+1) corresponds to:
– the number of PWM periods in edge-aligned mode
– the number of half PWM period in center-aligned mode.
14.4.14 TIM1 and TIM8 capture/compare register 1 (TIMx_CCR1)
15 14
Address offset: 0x34
Reset value: 0x0000
13 12 11 10 9 6 5 4 3 rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro
8 7
CCR1[15:0] rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro
2 rw/ro
1 0 rw/ro rw/ro
Bits 15:0 CCR1[15:0] : Capture/Compare 1 value
If channel CC1 is configured as output :
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1 is configured as input :
CCR1 is the counter value transferred by the last input capture 1 event (IC1). The
TIMx_CCR1 register is read-only and cannot be programmed.
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14.4.15 TIM1 and TIM8 capture/compare register 2 (TIMx_CCR2)
15 14
Address offset: 0x38
Reset value: 0x0000
13 12 11 10 9 6 5 4 3 rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro
8 7
CCR2[15:0] rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro
2 rw/ro
1 0 rw/ro rw/ro
Bits 15:0 CCR2[15:0] : Capture/Compare 2 value
If channel CC2 is configured as output :
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input :
CCR2 is the counter value transferred by the last input capture 2 event (IC2). The
TIMx_CCR2 register is read-only and cannot be programmed.
14.4.16 TIM1 and TIM8 capture/compare register 3 (TIMx_CCR3)
15 14
Address offset: 0x3C
Reset value: 0x0000
13 12 11 10 9 6 5 4 3 rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro
8 7
CCR3[15:0] rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro
2 rw/ro
1 0 rw/ro rw/ro
Bits 15:0 CCR3[15:0] : Capture/Compare value
If channel CC3 is configured as output :
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register
(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC3 output.
If channel CC3 is configured as input :
CCR3 is the counter value transferred by the last input capture 3 event (IC3). The
TIMx_CCR3 register is read-only and cannot be programmed.
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14.4.17 TIM1 and TIM8 capture/compare register 4 (TIMx_CCR4)
15 14
Address offset: 0x40
Reset value: 0x0000
13 12 11 10 9 6 5 4 3 rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro
8 7
CCR4[15:0] rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro
2 rw/ro
1 0 rw/ro rw/ro
Bits 15:0 CCR4[15:0] : Capture/Compare value
If channel CC4 is configured as output :
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register
(bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC4 output.
If channel CC4 is configured as input :
CCR4 is the counter value transferred by the last input capture 4 event (IC4). The
TIMx_CCR3 register is read-only and cannot be programmed.
14.4.18 TIM1 and TIM8 break and dead-time register (TIMx_BDTR)
15
MOE rw
Address offset: 0x44
14
AOE rw
Reset value: 0x0000
13
BKP rw
12 11 10
BKE OSSR OSSI rw rw rw
9 8
LOCK[1:0] rw rw
7 rw
6 rw
5 rw
4 3
DTG[7:0] rw rw
2 rw
Note:
1 0 rw rw
As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
Bit 15 MOE : Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output.
0: OC and OCN outputs are disabled or forced to idle state.
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register).
See OC/OCN enable description for more details (
Section 14.4.9: TIM1 and TIM8 capture/compare enable register (TIMx_CCER)
).
Bit 14 AOE : Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is not be active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
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Bit 13 BKP : Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 12 BKE : Break enable
0: Break inputs (BRK and CSS clock failure event) disabled
1; Break inputs (BRK and CSS clock failure event) enabled
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 11 OSSR : Off-state selection for Run mode
This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer.
See OC/OCN enable description for more details (
Section 14.4.9: TIM1 and TIM8 capture/compare enable register (TIMx_CCER)
).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
Bit 10 OSSI : Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details (
Section 14.4.9: TIM1 and TIM8 capture/compare enable register (TIMx_CCER)
).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or
CCxNE=1. OC/OCN enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
Bits 9:8 LOCK[1:0] : Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected.
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIMx_CCMRx registers, as long as the related channel is configured in output through the
CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
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Bits 7:0 DTG[7:0] : Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x t
DTG[7:5]=111 => DT=(32+DTG[4:0])xt dtg
Example if T
DTS
0 to 15875 ns by 125 ns steps, dtg
with t
DTG[7:5]=10x => DT=(64+DTG[5:0])xt dtg
DTG[7:5]=110 => DT=(32+DTG[4:0])xt dtg dtg
=t
DTS
.
with T
with T dtg
=2xt dtg
with T dtg
=8xt
DTS
.
DTS
=16xt
.
DTS
.
=125ns (8MHz), dead-time possible values are:
16 us to 31750 ns by 250 ns steps,
32 us to 63us by 1 us steps,
64 us to 126 us by 2 us steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIMx_BDTR register).
14.4.19 TIM1 and TIM8 DMA control register (TIMx_DCR)
15 14
Reserved
Address offset: 0x48
Reset value: 0x0000
13 12 11 rw rw
10
DBL[4:0] rw
9 rw
8 rw
7 6
Reserved
5 4 rw
3 rw
2
DBA[4:0] rw
1 rw
0 rw
Bits 15:13 Reserved, must be kept at reset value.
Bits 12:8 DBL[4:0] : DMA burst length
This 5-bit vector defines the number of DMA transfers (the timer detects a burst transfer when a read or a write access to the TIMx_DMAR register address is performed). the TIMx_DMAR address)
00000: 1 transfer
00001: 2 transfers
00010: 3 transfers
...
10001: 18 transfers
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DBA[4:0] : DMA base address
This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
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14.4.20 TIM1 and TIM8 DMA address for full transfer (TIMx_DMAR)
31 30
Address offset: 0x4C
Reset value: 0x0000 0000
29 28 27 26 25 22 21 20 19 rw
15 rw rw
14 rw rw
13 rw rw
12 rw rw
11 rw rw
10 rw rw
9 rw
24 23
DMAB[31:16] rw
8 rw
7
DMAB[15:0] rw rw rw
6 rw rw
5 rw rw
4 rw rw
3 rw
18 rw
2 rw
17 rw
1
16 rw
0 rw rw
Bits 31:0 DMAB[31:0] : DMA register for burst accesses
A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the
DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
Note:
Example of how to use the DMA burst feature
In this example the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers.
This is done in the following steps:
1.
Configure the corresponding DMA channel as follows:
– DMA channel peripheral address is the DMAR register address
– DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers.
– Number of data to transfer = 3 (See note below).
– Circular mode disabled.
2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:
DBL = 3 transfers, DBA = 0xE.
3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).
5. Enable the DMA channel
This example is for the case where every CCRx register to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer should be 6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to
CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4.
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14.4.21 TIM1 and TIM8 register map
TIM1 and TIM8 registers are mapped as 16-bit addressable registers as described in the table below:
Table 84. TIM1 and TIM8 register map and reset values
Offset Register
0x00
0x04
0x08
TIMx_CR1
Reset value
TIMx_CR2
Reset value
TIMx_SMCR
Reset value
TIMx_DIER
0x0C
Reset value
TIMx_SR
0x10
Reset value
TIMx_EGR
0x14
0x18
0x1C
Reset value
TIMx_CCMR1
Output compare mode
Reset value
TIMx_CCMR1
Input capture mode
Reset value
TIMx_CCMR2
Output compare mode
Reset value
TIMx_CCMR2
Input capture mode
Reset value
TIMx_CCER
0x20
0x24
0x28
Reset value
TIMx_CNT
Reset value
TIMx_PSC
Reset value
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CKD
[1:0]
CMS
[1:0]
0 0 0 0 0 0 0 0 0 0
MMS[2:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
ETP
S
[1:0]
ETF[3:0] TS[2:0]
0 0 0 0 0 0 0 0 0 0 0 0
SMS[2:0]
0 0
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
OC2M
[2:0]
CC2S
[1:0]
0 0 0 0 0 0 0 0
OC1M
[2:0]
CC1
S
[1:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IC2F[3:0]
IC2
PSC
[1:0]
CC2S
[1:0]
IC1F[3:0]
IC1
PSC
[1:0]
CC1
S
[1:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OC4M
[2:0]
CC4S
[1:0]
OC3M
[2:0]
CC3
S
[1:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IC4F[3:0]
IC4
PSC
[1:0]
CC4S
[1:0]
IC3F[3:0]
IC3
PSC
[1:0]
CC3
S
[1:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CNT[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PSC[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Register
Table 84. TIM1 and TIM8 register map and reset values (continued)
Offset
0x2C
0x30
0x34
0x38
0x3C
0x40
0x44
0x48
0x4C
TIMx_ARR
Reset value
TIMx_RCR
Reset value
TIMx_CCR1
Reset value
TIMx_CCR2
Reset value
TIMx_CCR3
Reset value
TIMx_CCR4
Reset value
TIMx_BDTR
Reset value
TIMx_DCR
Reset value
TIMx_DMAR
Reset value
ARR[15:0]
Reserved
Reserved
Reserved
Reserved
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
REP[7:0]
0 0 0 0 0 0 0 0
CCR1[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCR2[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCR3[15:0]
Reserved
Reserved
Reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCR4[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LOCK
[1:0]
DT[7:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
DBL[4:0]
0 0 0 0 0
Reserved
DBA[4:0]
0 0 0 0 0
DMAB[31:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Refer to Section 3.3: Memory map
for the register boundary addresses.
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15
General-purpose timers (TIM2 to TIM5)
General-purpose timers (TIM2 to TIM5)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to the whole STM32F10xxx family, unless otherwise specified.
15.1 TIM2 to TIM5 introduction
The general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input signals ( input capture ) or generating output waveforms ( output compare and PWM ).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.
The timers are completely independent, and do not share any resources. They can be synchronized together as described in
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15.2 TIMx main features
General-purpose TIMx timer features include:
16-bit up, down, up/down auto-reload counter.
16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536.
Up to 4 independent channels for:
– Input capture
– Output compare
– PWM generation (Edge- and Center-aligned modes)
– One-pulse mode output
Synchronization circuit to control the timer with external signals and to interconnect several timers.
Interrupt/DMA generation on the following events:
– Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)
– Trigger event (counter start, stop, initialization or count by internal/external trigger)
– Input capture
– Output compare
Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes
Trigger input for external clock or cycle-by-cycle current management
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Figure 100. General-purpose timer block diagram
TIMx_ETR
Internal clock (CK_INT)
TIMxCLK from RCC
ETR
ITR0
ITR1
ITR2
ITR3
Polarity selection & edge detector & prescaler
ETRP
Input filter
ITR
TRC
TI1F_ED
ETRF
Trigger controller
TRGO to other timers to DAC/ADC
TGI
TRGI
Slave controller mode
Reset, enable, up, count
TIMx_CH1
XOR
TI1
TI2
TIMx_CH2
TIMx_CH3
TIMx_CH4
TI3
TI4
TI1FP1
TI2FP2
Encoder interface
Input filter & edge detector
Input filter & edge detector
Input filter & edge detector
Input filter & edge detector
U
Auto-reload register
UI
CK_PSC
TI1FP1
TI1FP2
IC1
PSC prescaler
CK_CNT
CC1I
U
Prescaler
Stop, clear or up/down
IC1PS
U
+/CNT counter
CC1I
Capture/Compare 1 register
OC1REF
TRC
TI2FP1
TI2FP2
TRC
CC2I
U
IC2
Prescaler
IC2PS
Capture/Compare 2 register
CC2I
OC2REF
CC3I
U
TI3FP3
TI3FP4
IC3
Prescaler
IC3PS
CC3I
Capture/Compare 3 register
OC3REF
TRC
TI4FP3
TI4FP4
TRC
CC4I
U
IC4
Prescaler
IC4PS
Capture/Compare 4 register
CC4I
OC4REF
ETRF
Output control
OC1
TIMx_CH1
Output control
Output control
Output control
OC2
OC3
OC4
TIMx_CH2
TIMx_CH3
TIMx_CH4
Notes:
Reg
Preload registers transferred to active registers on U event according to control bit
Event
Interrupt & DMA output
MS19673V1
RM0008 Rev 21 367/1136
424
General-purpose timers (TIM2 to TIM5)
15.3 TIMx functional description
RM0008
The main block of the programmable timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.
The time-base unit includes:
Counter register (TIMx_CNT)
Prescaler register (TIMx_PSC):
Auto-Reload register (TIMx_ARR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling).
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.
Figure 101 and Figure 102 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:
368/1136 RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5)
Figure 101. Counter timing diagram with prescaler division change from 1 to 2
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Prescaler control register
F7 F8 F9 FA FB FC 00
0
Write a new value in TIMx_PSC
Prescaler buffer
0
01
1
1
02 03
Prescaler counter 0 0 1 0 1 0 1 0 1
MS35833V1
Figure 102. Counter timing diagram with prescaler division change from 1 to 4
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register F7 F8 F9 FA FB FC
Update event (UEV)
Prescaler control register 0
Write a new value in TIMx_PSC
Prescaler buffer 0
Prescaler counter 0
00
3
3
01
0 1 2 3 0 1 2 3
MS35834V1
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
An Update event can be generated at each counter overflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register.
This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate
RM0008 Rev 21 369/1136
424
General-purpose timers (TIM2 to TIM5) RM0008 does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register)
The auto-reload shadow register is updated with the preload value (TIMx_ARR)
The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.
Figure 103. Counter timing diagram, internal clock divided by 1
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
31 32 33 34 35 36 00 01 02 03 04 05 06 07
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 104. Counter timing diagram, internal clock divided by 2
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register 0034 0035 0036 0000 0001 0002 0003
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MS35836V1
MS35835V1
370/1136 RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5)
Figure 105. Counter timing diagram, internal clock divided by 4
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register 0035 0036 0000 0001
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MSv37301V1
Figure 106. Counter timing diagram, internal clock divided by N
CK_INT
Timerclock = CK_CNT
Counter register 1F 20 00
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MSv37302V1
RM0008 Rev 21 371/1136
424
General-purpose timers (TIM2 to TIM5) RM0008
Figure 107. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded)
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register 31
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
32 33 34 35 36 00 01 02 03 04 05 06 07
Auto-reload register FF 36
Write a new value in TIMx_ARR
MSv37303V1
Figure 108. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded)
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07
F5 36
Auto-reload shadow register F5 36
Write a new value in TIMx_ARR
MSv37304V1
Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.
An Update event can be generate at each counter underflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller)
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the
372/1136 RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5) preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one.
The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.
Figure 109. Counter timing diagram, internal clock divided by 1
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F
Counter underflow (cnt_udf)
Update event (UEV)
Update interrupt flag (UIF)
MSv37305V1
RM0008 Rev 21 373/1136
424
General-purpose timers (TIM2 to TIM5)
Figure 110. Counter timing diagram, internal clock divided by 2
RM0008
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register 0002 0001 0000 0036 0035 0034 0033
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 111. Counter timing diagram, internal clock divided by 4
MSv37306V1
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register 0001 0000 0036 0035
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Figure 112. Counter timing diagram, internal clock divided by N
CK_INT
MS40511V1
Timerclock = CK_CNT
Counter register 20 1F 00 36
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MS37340V1
374/1136 RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5)
Figure 113. Counter timing diagram, Update event
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register FF 36
Write a new value in TIMx_ARR
MS37341V1
Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3,
CMS = "11").
In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event.
RM0008 Rev 21 375/1136
424
General-purpose timers (TIM2 to TIM5) RM0008
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock frequencies.
Figure 114. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
Counter underflow
Counter overflow
04 03 02 01 00 01 02 03 04 05 06 05 04 03
Update event (UEV)
Update interrupt flag (UIF)
MS37342V1
.
Figure 115. Counter timing diagram, internal clock divided by 2
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register 0003 0002 0001 0000 0001 0002 0003
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
MS37343V1
376/1136 RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5)
Figure 116. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register 0034 0035 0036 0035
Counter overflow (cnt_ovf)
Update event (UEV)
Update interrupt flag (UIF)
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
Figure 117. Counter timing diagram, internal clock divided by N
CK_INT
MS37344V1
Timerclock = CK_CNT
Counter register 20 1F 01 00
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
MS37345V1
RM0008 Rev 21 377/1136
424
General-purpose timers (TIM2 to TIM5)
36
36
RM0008
Figure 118. Counter timing diagram, Update event with ARPE=1 (counter underflow)
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register 06 05 04 03 02 01 00 01 02 03 04 05 06 07
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register FD 36
Write a new value in TIMx_ARR
Auto-reload active register FD 36
MS37360V1
Figure 119. Counter timing diagram, Update event with ARPE=1 (counter overflow)
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register FD
Write a new value in TIMx_ARR
Auto-reload active register FD
MS37361V1
378/1136 RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5)
The counter clock can be provided by the following clock sources:
Internal clock (CK_INT)
External clock mode1: external input pin (TIx)
External clock mode2: external trigger input (ETR).
Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, Timer1 can be configured to act as a prescaler for Timer 2. Refer to
Using one timer as prescaler for another timer
for more details.
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the
CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 120 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
Figure 120. Control circuit in normal mode, internal clock divided by 1
Internal clock
CEN=CNT_EN
UG
CNT_INIT
Counter clock = CK_CNT = CK_PSC
Counter register 31 3 2 33 34 35 36 00 01 02 03 04 05 06 07
MS31085V2
External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on a selected input.
RM0008 Rev 21 379/1136
424
General-purpose timers (TIM2 to TIM5) RM0008
Figure 121. TI2 external clock connection example
TIMx_SMCR
TS[2:0]
TI2
Filter
ICF[3:0]
TIMx_CCMR1
Edge detector
TI2F_Rising
TI2F_Falling
0
1
CC2P
TIMx_CCER
ITRx
TI1_ED
TI1FP1
TI2FP2
ETRF
0xx
100
101
110
111 or
TI2F or
TI1F or
TRGI
ETRF
CK_INT
(internal clock)
Encoder mode
External clock mode 1
External clock mode 2
Internal clock mode
ECE SMS[2:0]
TIMx_SMCR
CK_PSC
Note:
MS31196V1
For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure:
1.
Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the
TIMx_CCMR1 register.
2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000).
The capture prescaler is not used for triggering, so there’s no need to configure it.
3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register.
4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.
5. Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register.
6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input.
380/1136 RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5)
Figure 122. Control circuit in external clock mode 1
TI2
CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
TIF
34 35 36
Write TIF=0
MS31087V2
External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
Figure 123 gives an overview of the external trigger input block.
Figure 123. External trigger input block
ETR pin
ETR
0
1
Divider
/1, /2, /4, /8
ETP
TIMx_SMCR
ETPS[1:0]
TIMx_SMCR or
TI2F or
TI1F or Encoder mode
ETRP
CK_INT
Filter downcounter
ETF[3:0]
TIMx_SMCR
TRGI External clock mode 1
CK_PSC
ETRF External clock mode 2
CK_INT
(internal clock)
Internal clock mode
ECE SMS[2:0]
TIMx_SMCR
MS37365V1
For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure:
1.
As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
RM0008 Rev 21 381/1136
424
General-purpose timers (TIM2 to TIM5) RM0008
The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal.
Figure 124. Control circuit in external clock mode 2
CK_INT
CNT_EN
ETR
ETRP
ETRF
Counter clock = CK_INT =CK_PSC
Counter register
34 35 36
MS37362V1
Each Capture/Compare channel (see
Figure 125 ) is built around a capture/compare register
(including a shadow register), an input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS).
Figure 125. Capture/compare channel (example: channel 1 input stage)
TI1F_ED
To the slave mode controller
TI1 f
DTS
Filter downcounter
TI1F
ICF[3:0]
TIMx_CCMR1
Edge detector
TI1F_Rising
TI1F_Falling
CC1P/CC1NP
TIMx_CCER
TI2F_Rising
(from channel 2)
TI2F_Falling
(from channel 2)
0
1
0 TI1FP1
1
TI2FP1
01
10
IC1 Divider
/1, /2, /4, /8
IC1PS
TRC
(from slave mode controller)
11
CC1S[1:0] ICPS[1:0]
TIMx_CCMR1
CC1E
TIMx_CCER
MS33115V1
382/1136 RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5)
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Figure 126. Capture/compare channel 1 main circuit
APB Bus
Read CCR1H
S
Read CCR1L
R
CC1S[1]
CC1S[0]
IC1PS
CC1E
CC1G
TIMx_EGR
MCU-peripheral interface
8 8
S write CCR1H write_in_progress read_in_progress
Input mode
Capture/compare preload register capture_transfer
Capture/compare shadow register
Capture compare_transfer
Comparator
Output mode
CNT>CCR1
R write CCR1L
CC1S[1]
CC1S[0]
OC1PE
UEV
(from time base unit)
OC1PE
TIMx_CCMR1
Counter
CNT=CCR1
MS33144V1
Figure 127. Output stage of capture/compare channel (channel 1)
ETRF
To the master mode controller
0
1
Output
Enable
Circuit
TIMx_CNT > TIMx_CCR1
TIMx_CNT = TIMx_CCR1
Output mode controller oc1ref
CC1P
TIMx_CCER
OC1
CC1E
TIMx_CCER
OC1M[2:0]
TIMx_CCMR1 ai17187b
The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.
RM0008 Rev 21 383/1136
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General-purpose timers (TIM2 to TIM5) RM0008
Note:
In Input capture mode, the Capture/Compare registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to 0 or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when written to 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure:
Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only.
Program the needed input filter duration with respect to the signal connected to the timer (by programming the ICxF bits in the TIMx_CCMRx register if the input is one of the TIx inputs). Let’s imagine that, when toggling, the input signal is not stable during at must five internal clock cycles. We must program a filter duration longer than these five clock cycles. We can validate a transition on TI1 when eight consecutive samples with the new level have been detected (sampled at f
DTS
0011 in the TIMx_CCMR1 register.
frequency). Then write IC1F bits to
Select the edge of the active transition on the TI1 channel by writing the CC1P bit to 0 in the TIMx_CCER register (rising edge in this case).
Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the
TIMx_CCMR1 register).
Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.
When an input capture occurs:
The TIMx_CCR1 register gets the value of the counter on the active transition.
CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared.
An interrupt is generated depending on the CC1IE bit.
A DMA request is generated depending on the CC1DE bit.
In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data.
IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register.
384/1136 RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5)
15.3.6 PWM input mode
This mode is a particular case of input capture mode. The procedure is the same except:
Two ICx signals are mapped on the same TIx input.
These 2 ICx signals are active on edges with opposite polarity.
One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode.
For example, the user can measure the period (in TIMx_CCR1 register) and the duty cycle
(in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure
(depending on CK_INT frequency and prescaler value):
Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected).
Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P to ‘0’ (active on rising edge).
Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected).
Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ (active on falling edge).
Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register
(TI1FP1 selected).
Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.
Enable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register.
Figure 128. PWM input mode timing
TI1
0000 0001 0003 0004 0000 TIMx_CNT 0004
TIMx_CCR1
TIMx_CCR2
0002
0004
0002
IC1 capture
IC2 capture reset counter
IC2 capture measurement
IC1 capture period measurement ai15413
1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only
TI1FP1 and TI2FP2 are connected to the slave mode controller.
RM0008 Rev 21 385/1136
424
General-purpose timers (TIM2 to TIM5) RM0008
15.3.7 Forced output mode
In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.
To force an output compare signal (ocxref/OCx) to its active level, the user just needs to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
e.g.: CCxP=0 (OCx active high) => OCx is forced to high level.
ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the next section.
15.3.8 Output compare mode
This function is used to control an output waveform or indicating when a period of time has elapsed.
When a match is found between the capture/compare register and the counter, the output compare function:
Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.
Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on ocxref and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode).
Procedure:
1.
Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be generated.
4. Select the output mode. For example, the user must write OCxM=011, OCxPE=0,
CCxP=0 and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx preload is not used, OCx is enabled and active high.
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
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RM0008 General-purpose timers (TIM2 to TIM5)
The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in
Figure 129. Output compare mode, toggle on OC1
Write B201h in the CC1R register
TIMx_CNT
TIMx_CCR1
0039 003A
003A
003B B200
B201
B201
OC1REF = OC1
Match detected on CCR1
Interrupt generated if enabled
MS37363V1
Pulse width modulation mode allows generating a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. The user must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, the user has to initialize all the registers by setting the
UG bit in the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx TIMx_CNT or TIMx_CNT TIMx_CCRx (depending on the direction of the counter). However, to comply with the ETRF (OCREF can be cleared by an external event through the ETR signal until the next PWM period), the OCREF signal is asserted only:
When the result of the comparison changes, or
When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from the “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes
(OCxM=‘110 or ‘111).
This forces the PWM by software while the timer is running.
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The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register.
PWM edge-aligned mode
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to
.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1.
If the compare value is 0 then OCxREF is held at ‘0. Figure 130 shows some edge-aligned
PWM waveforms in an example where TIMx_ARR=8.
Figure 130. Edge-aligned PWM waveforms (ARR=8)
Counter register
CCRx=4
OCXREF
CCxIF
0 1 2 3 4 5 6 7 8 0 1
CCRx=8
OCXREF
CCxIF
CCRx>8
OCXREF ‘1’
CCxIF
CCRx=0
OCXREF ‘0’
CCxIF
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Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Downcounting mode
.
In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in
TIMx_ARR, then ocxref is held at ‘1. 0% PWM is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts
RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5) up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
Center-aligned mode (up/down counting)
.
Figure 131 shows some center-aligned PWM waveforms in an example where:
TIMx_ARR=8,
PWM mode is the PWM mode 1,
The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register.
Figure 131. Center-aligned PWM waveforms (ARR=8)
Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1
CCRx = 4
OCxREF
CCxIF CMS=01
CMS=10
CMS=11
CCRx = 7
OCxREF
CCxIF
CCRx = 8
OCxREF
'1'
CMS=10 or 11
CCxIF
CMS=01
CMS=10
CMS=11
CCRx > 8
OCxREF
'1'
CCxIF CMS=01
CMS=10
CMS=11
CCRx = 0
OCxREF
'0'
CCxIF CMS=01
CMS=10
CMS=11 ai14681b
Hints on using center-aligned mode:
When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit
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General-purpose timers (TIM2 to TIM5) RM0008 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.
Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular:
– The direction is not updated if the user writes a value in the counter that is greater than the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up.
– The direction is updated if the user writes 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated.
The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running.
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. Select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be:
In upcounting: CNT<CCRx ARR (in particular, 0<CCRx),
In downcounting: CNT>CCRx.
Figure 132. Example of one-pulse mode
TI2
OC1REF
OC1
TIM1_ARR
TIM1_CCR1
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DELAY t
PULSE t
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For example the user may want to generate a positive pulse on OC1 with a length of t
PULSE and after a delay of t
DELAY
as soon as a positive edge is detected on the TI2 input pin.
RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5)
Let’s use TI2FP2 as trigger 1:
Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register.
TI2FP2 must detect a rising edge, write CC2P=0 in the TIMx_CCER register.
Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in the TIMx_SMCR register.
TI2FP2 is used to start the counter by writing SMS to ‘110 in the TIMx_SMCR register
(trigger mode).
The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).
The t
DELAY is defined by the value written in the TIMx_CCR1 register.
The t
PULSE
is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR + 1).
Let us say user wants to build a waveform with a transition from ‘0 to ‘1 when a compare match occurs and a transition from ‘1 to ‘0 when the counter reaches the auto-reload value. To do this enable PWM mode 2 by writing OC1M=111 in the
TIMx_CCMR1 register. The user can optionally enable the preload registers by writing
OC1PE=1 in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case write the compare value in the TIMx_CCR1 register, the auto-reload value in the
TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0 in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
User only wants one pulse (Single mode), so write '1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the
Repetitive mode is selected.
Particular case: OCx fast enable:
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay t
DELAY
min we can get.
To output a waveform with the minimum delay, the user can set the OCxFE bit in the
TIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
The OCxREF signal for a given channel can be driven Low by applying a High level to the
ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to '1'). The
OCxREF signal remains Low until the next update event, UEV, occurs.
This function can only be used in output compare and PWM modes, and does not work in forced mode.
For example, the ETR signal can be connected to the output of a comparator to be used for current handling. In this case, ETR must be configured as follows:
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1.
The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00.
2. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is cleared to 0.
3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs.
Figure 133 shows the behavior of the OCxREF signal when the ETRF input becomes high,
for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in
PWM mode.
Figure 133. Clearing TIMx OCxREF
(CCRx)
Counter (CNT)
ETRF
OCxREF (OCxCE = ‘0’)
OCxREF (OCxCE = ‘1’)
ETRF becomes high ETRF still high
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To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. When needed, program the input filter as well.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 85 . The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So the user must configure TIMx_ARR before starting. In the same way, the capture, compare, prescaler, trigger output features continue to work as normal.
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RM0008 General-purpose timers (TIM2 to TIM5)
In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor.
The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time.
Active edge
Counting on
TI1 only
Counting on
TI2 only
Counting on
TI1 and TI2
Table 85. Counting direction versus encoder signals
Level on opposite signal (TI1FP1 for
TI2, TI2FP2 for TI1)
TI1FP1 signal
Rising Falling
TI2FP2 signal
Rising Falling
High
Low
High
Low
High
Low
Down
Up
No Count
No Count
Down
Up
Up
Down
No Count
No Count
Up
Down
No Count
No Count
Up
Down
Up
Down
No Count
No Count
Down
Up
Down
Up
An external incremental encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset.
Figure 134 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following:
CC1S= ‘01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1)
CC2S= ‘01’ (TIMx_CCMR2 register, TI2FP2 mapped on TI2)
CC1P= ‘0’, CC1NP = ‘0’, IC1F =’0000’ (TIMx_CCER register, TI1FP1 noninverted,
TI1FP1=TI1)
CC2P= ‘0’, CC2NP = ‘0’, IC2F =’0000’ (TIMx_CCER register, TI2FP2 noninverted,
TI2FP2=TI2)
SMS= ‘011’ (TIMx_SMCR register, both inputs are active on both rising and falling edges)
CEN = 1 (TIMx_CR1 register, Counter is enabled)
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Figure 134. Example of counter operation in encoder interface mode forward jitter backward jitter forward
TI1
TI2
RM0008
Counter up down up
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Figure 135 gives an example of counter behavior when TI1FP1 polarity is inverted (same
configuration as above except CC1P=1).
Figure 135. Example of encoder interface mode with TI1FP1 polarity inverted forward jitter backward jitter forward
TI1
TI2
Counter down up down
MS33108V1
The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. The user can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. The user can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a
DMA request generated by a Real-Time clock.
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RM0008 General-purpose timers (TIM2 to TIM5)
15.3.13 Timer input XOR function
The TI1S bit in the TIM1_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input capture.
An example of this feature used to interface Hall sensors is given in
15.3.14 Timers and external trigger synchronization
The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode.
Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so the user does not need to configure it. The
CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edges only).
Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
Start the counter by writing CEN=1 in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
Figure 136 shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay
between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input.
Figure 136. Control circuit in reset mode
TI1
UG
Counter clock = CK_CNT = CK_PSC
Counter register
30 31 32 33 34 35 36 00 01 02 03 00 01 02 03
TIF
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Slave mode: Gated mode
The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so the user does not need to configure it. The
CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register.
Write CC1P=1 in TIMx_CCER register to validate the polarity (and detect low level only).
Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input.
Figure 137. Control circuit in gated mode
TI1
CNT_EN
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Counter clock = CK_CNT = CK_PSC
Counter register 30 31 32 33
TIF
34 35 36 37 38
Write TIF=0
MS40512V1
Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so the user does not need to configure it. CC2S bits are selecting the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write
CC2P=1 in TIMx_CCER register to validate the polarity (and detect low level only).
Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5)
The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input.
Figure 138. Control circuit in trigger mode
TI2
CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
34 35 36 37 38
TIF
MS37386V1
Slave mode: External Clock mode 2 + trigger mode
The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input when operating in reset mode, gated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS bits of TIMx_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs:
1.
Configure the external trigger input circuit by programming the TIMx_SMCR register as follows:
– ETF = 0000: no filter
– ETPS = 00: prescaler disabled
– ETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2.
2. Configure the channel 1 as follows, to detect rising edges on TI:
– IC1F = 0000: no filter.
– The capture prescaler is not used for triggering and does not need to be configured.
– CC1S = 01 in TIMx_CCMR1 register to select only the input capture source
– CC1P = 0 in TIMx_CCER register to validate the polarity (and detect rising edge only).
3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input.
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Figure 139. Control circuit in external clock mode 2 + trigger mode
RM0008
TI1
CEN/CNT_EN
ETR
Counter clock = CK_CNT = CK_PSC
Counter register
TIF
34 35 36
MS33110V1
Note:
The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master mode, it can reset, start, stop or clock the counter of another Timer configured in Slave mode.
Figure 140 presents an overview of the trigger selection and the master mode selection
blocks.
The clock of the slave timer must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
Using one timer as prescaler for another timer
Figure 140. Master/Slave timer example
TIM1 TIM2
Clock
UEV
Prescaler Counter
MMS
Master mode control
TRGO1 ITR0
TS
SMS
Slave mode control
CK_PSC
Prescaler
Input trigger selection
Counter
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RM0008
Note:
Note:
General-purpose timers (TIM2 to TIM5)
For example, the user can configure Timer 1 to act as a prescaler for Timer 2 (see
Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each update event UEV. If you write MMS=010 in the TIM1_CR2 register, a rising edge is output on TRGO1 each time an update event is generated.
To connect the TRGO1 output of Timer 1 to Timer 2, Timer 2 must be configured in slave mode using ITR0 as internal trigger. You select this through the TS bits in the
TIM2_SMCR register (writing TS=000).
Then you put the slave mode controller in external clock mode 1 (write SMS=111 in the
TIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the periodic Timer 1 trigger signal (which correspond to the timer 1 counter overflow).
Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1 register).
If OCx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to clock the counter of timer 2.
Using one timer to enable another timer
In this example, we control the enable of Timer 2 with the output compare 1 of Timer 1.
for connections. Timer 2 counts on the divided internal clock only when
OC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (f
CK_CNT
= f
CK_INT
/3).
Configure Timer 1 master mode to send its Output compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register).
Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).
Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register).
Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).
Enable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).
Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).
The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer 2 counter enable signal.
Figure 141. Gating timer 2 with OC1REF of timer 1
CK_INT
TIMER1-OC1REF
TIMER1-CNT
FC FD FE FF 00 01
TIMER2-CNT
TIMER2-TIF
3045 3046 3047 3048
Write TIF = 0
MS37388V1
In the example in Figure 141 , the Timer 2 counter and prescaler are not initialized before
being started. So they start counting from their current value. It is possible to start from a given value by resetting both timers before starting Timer 1. You can then write any value
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General-purpose timers (TIM2 to TIM5) RM0008 you want in the timer counters. The timers can easily be reset by software using the UG bit in the TIMx_EGR registers.
In the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts from 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both timers. Timer 2 stops when Timer 1 is disabled by writing ‘0 to the CEN bit in the TIM1_CR1 register:
Configure Timer 1 master mode to send its Output compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register).
Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).
Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register).
Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).
Reset Timer 1 by writing ‘1 in UG bit (TIM1_EGR register).
Reset Timer 2 by writing ‘1 in UG bit (TIM2_EGR register).
Initialize Timer 2 to 0xE7 by writing ‘0xE7’ in the timer 2 counter (TIM2_CNTL).
Enable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).
Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).
Stop Timer 1 by writing ‘0 in the CEN bit (TIM1_CR1 register).
Figure 142. Gating timer 2 with Enable of timer 1
CK_INT
TIMER1-CEN=CNT_EN
TIMER1-CNT_INIT
TIMER1-CNT
TIMER2-CNT
TIMER2-CNT_INIT
TIMER2-write CNT
TIMER2-TIF
75
AB 00
00
E7
01
E8
02
E9
Write TIF = 0
MS37389V1
400/1136 RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5)
Using one timer to start another timer
In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to
Figure 140 for connections. Timer 2 starts counting from its current value (which can be
nonzero) on the divided internal clock as soon as the update event is generated by Timer 1.
When Timer 2 receives the trigger signal its CEN bit is automatically set and the counter counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (f
CK_CNT
= f
CK_INT
/3).
Configure Timer 1 master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIM1_CR2 register).
Configure the Timer 1 period (TIM1_ARR registers).
Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register).
Configure Timer 2 in trigger mode (SMS=110 in TIM2_SMCR register).
Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).
Figure 143. Triggering timer 2 with update of timer 1
CK_INT
TIMER1-UEV
TIMER1-CNT
TIMER2-CNT
FD FE
45
FF 00
46
01
47
02
48
TIMER2-CEN=CNT_EN
TIMER2-TIF
Write TIF = 0
MS37390V1
As in the previous example, the user can initialize both counters before starting counting.
Figure 144 shows the behavior with the same configuration as in
but in trigger mode instead of gated mode (SMS=110 in the TIM2_SMCR register).
RM0008 Rev 21 401/1136
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General-purpose timers (TIM2 to TIM5)
Figure 144. Triggering timer 2 with Enable of timer 1
CK_INT
Note:
RM0008
TIMER1-CEN=CNT_EN
TIMER1-CNT_INIT
TIMER1-CNT
75
TIMER2-CNT
TIMER2-CNT_INIT
TIMER2-write CNT
TIMER2-TIF
CD 00
00
E7
01
E8
02
E9 EA
Write TIF = 0
MS37391V1
Starting 2 timers synchronously in response to an external trigger
In this example, we set the enable of timer 1 when its TI1 input rises, and the enable of
Timer 2 with the enable of Timer 1. Refer to
Figure 140 for connections. To ensure the
counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer 2):
Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the
TIM1_CR2 register).
Configure Timer 1 slave mode to get the input trigger from TI1 (TS=100 in the
TIM1_SMCR register).
Configure Timer 1 in trigger mode (SMS=110 in the TIM1_SMCR register).
Configure the Timer 1 in Master/Slave mode by writing MSM=1 (TIM1_SMCR register).
Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register).
Configure Timer 2 in trigger mode (SMS=110 in the TIM2_SMCR register).
When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on the internal clock and both TIF flags are set.
In this example both timers are initialized before starting (by setting their respective UG bits). Both counters starts from 0, but you can easily insert an offset between them by writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode insert a delay between CNT_EN and CK_PSC on timer 1.
402/1136 RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5)
Figure 145. Triggering timer 1 and 2 with timer 1 TI1 input
CK_INT
TIMER1-TI1
TIMER1-CEN=CNT_EN
TIMER1-CK_PSC
TIMER1-CNT
TIMER1-TIF
TIMER2-CEN=CNT_EN
TIMER2-CK_PSC
TIMER2-CNT
TIMER2-TIF
00
00
01 02 03 04 05 06 07 08 09
01 02 03 04 05 06 07 08 09
MS37392V1
When the microcontroller enters debug mode (Cortex ® -M3 core - halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
.
RM0008 Rev 21 403/1136
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General-purpose timers (TIM2 to TIM5) RM0008
Refer to
for a list of abbreviations used in register descriptions.
The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
15.4.1 TIMx control register 1 (TIMx_CR1)
15 14
Address offset: 0x00
Reset value: 0x0000
13 12 11 10
Reserved
9 8
CKD[1:0] rw rw
7
ARPE rw
6 5 rw
CMS rw
4
DIR rw
3
OPM rw
2
URS rw
1
UDIS rw
0
CEN rw
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 CKD : Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),
00: t
DTS
= t
CK_INT
01: t
DTS
= 2 × t
CK_INT
10: t
DTS
= 4 × t
CK_INT
11: Reserved
Bit 7 ARPE : Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:5 CMS : Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)
Bit 4 DIR : Direction
0: Counter used as upcounter
1: Counter used as downcounter
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
Bit 3 OPM : One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
404/1136 RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5)
Bit 2 URS : Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Bit 1 UDIS : Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN : Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
CEN is cleared automatically in one-pulse mode, when an update event occurs.
RM0008 Rev 21 405/1136
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General-purpose timers (TIM2 to TIM5) RM0008
15.4.2 TIMx control register 2 (TIMx_CR2)
15 14
Address offset: 0x04
Reset value: 0x0000
13 12 11 10 9 8
Reserved
7
TI1S rw
6 rw
5
MMS[2:0] rw
4 rw
3
CCDS rw
2 1
Reserved
0
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 TI1S : TI1 selection
0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
See also Section 14.3.18: Interfacing with Hall sensors
Bits 6:4 MMS[2:0] : Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO)
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Compare - OC3REF signal is used as trigger output (TRGO)
111: Compare - OC4REF signal is used as trigger output (TRGO)
Note: The clock of the slave timer and ADC must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
Bit 3 CCDS : Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bits 2:0 Reserved, must be kept at reset value.
406/1136 RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5)
15.4.3 TIMx slave mode control register (TIMx_SMCR)
15
ETP rw
Address offset: 0x08
14
ECE rw
Reset value: 0x0000
13 12
ETPS[1:0] rw rw
11 rw
10
ETF[3:0]
9 rw rw
8 rw
7
MSM rw
6 rw
5
TS[2:0] rw
4 rw
3
Res.
2 rw
1
SMS[2:0] rw
0 rw
Bit 15 ETP : External trigger polarity
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge
1: ETR is inverted, active at low level or falling edge
Bit 14 ECE : External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=111).
2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to
ETRF in this case (TS bits must not be 111).
3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
Bits 13:12 ETPS : External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8
Bits 11:8 ETF[3:0] : External trigger filter
This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
0000: No filter, sampling is done at f
DTS
0001: f
SAMPLING
=f
CK_INT
0010: f
SAMPLING
0011: f
SAMPLING
0100: f
SAMPLING
0101: f
SAMPLING
0110: f
SAMPLING
=f
CK_INT
=f
CK_INT
=f
DTS
=f
DTS
=f
DTS
, N=2
, N=4
, N=8²
/2, N=6
/2, N=8
/4, N=6²
/4, N=8 0111: f
SAMPLING
1000: f
SAMPLING
1001: f
SAMPLING
1010: f
SAMPLING
1011: f
SAMPLING
1100: f
SAMPLING
=f
DTS
=f
DTS
=f
DTS
=f
DTS
=f
DTS
=f
DTS
/8, N=6
/8, N=8
/16, N=5
/16, N=6
/16, N=8
/32, N=5 1101: f
SAMPLING
1110: f
SAMPLING
1111: f
SAMPLING
=f
DTS
=f
DTS
=f
DTS
/32, N=6
/32, N=8
RM0008 Rev 21 407/1136
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General-purpose timers (TIM2 to TIM5) RM0008
Bit 7 MSM: Master/Slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 6:4 TS: Trigger selection
This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0).
001: Internal Trigger 1 (ITR1).
010: Internal Trigger 2 (ITR2).
011: Internal Trigger 3 (ITR3).
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
See
Table 86: TIMx Internal trigger connection
for more details on ITRx meaning for each
Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 SMS: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control register description.
000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
110: Trigger mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
111: External Clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100).
Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal.
The clock of the slave timer must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
408/1136 RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5)
Slave TIM
Table 86. TIMx Internal trigger connection (1)
ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010)
TIM2
TIM3
TIM4
TIM5
TIM1
TIM1
TIM1
TIM2
TIM8
TIM2
TIM2
TIM3
TIM3
TIM5
TIM3
TIM4
1. When a timer is not present in the product, the corresponding trigger ITRx is not available.
ITR3 (TS = 011)
TIM4
TIM4
TIM8
TIM8
15.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)
15
Res.
14
TDE rw
Address offset: 0x0C
Reset value: 0x0000
13
Res
12 11 10 9 8
CC4DE CC3DE CC2DE CC1DE UDE rw rw rw rw rw
7
Res.
6
TIE rw
5
Res
4 3 2 1
CC4IE CC3IE CC2IE CC1IE rw rw rw rw
Bit 15 Reserved, must be kept at reset value.
Bit 14 TDE : Trigger DMA request enable
0: Trigger DMA request disabled.
1: Trigger DMA request enabled.
Bit 13 Reserved, always read as 0
Bit 12 CC4DE : Capture/Compare 4 DMA request enable
0: CC4 DMA request disabled.
1: CC4 DMA request enabled.
Bit 11 CC3DE : Capture/Compare 3 DMA request enable
0: CC3 DMA request disabled.
1: CC3 DMA request enabled.
Bit 10 CC2DE : Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled.
1: CC2 DMA request enabled.
Bit 9 CC1DE : Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled.
1: CC1 DMA request enabled.
Bit 8 UDE : Update DMA request enable
0: Update DMA request disabled.
1: Update DMA request enabled.
Bit 7 Reserved, must be kept at reset value.
Bit 6 TIE : Trigger interrupt enable
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
Bit 5 Reserved, must be kept at reset value.
0
UIE rw
RM0008 Rev 21 409/1136
424
General-purpose timers (TIM2 to TIM5)
Bit 4 CC4IE : Capture/Compare 4 interrupt enable
0: CC4 interrupt disabled.
1: CC4 interrupt enabled.
Bit 3 CC3IE : Capture/Compare 3 interrupt enable
0: CC3 interrupt disabled.
1: CC3 interrupt enabled.
Bit 2 CC2IE : Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled.
1: CC2 interrupt enabled.
Bit 1 CC1IE : Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled.
1: CC1 interrupt enabled.
Bit 0 UIE : Update interrupt enable
0: Update interrupt disabled.
1: Update interrupt enabled.
RM0008
15 14
Reserved
Address offset: 0x10
Reset value: 0x0000
13 12 11 10 9
CC4OF CC3OF CC2OF CC1OF rc_w0 rc_w0 rc_w0 rc_w0
8 7
Reserved
6
TIF rc_w0
5
Res
4 3 2 1 0
CC4IF CC3IF CC2IF CC1IF UIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0
Bit 15:13 Reserved, must be kept at reset value.
Bit 12 CC4OF : Capture/Compare 4 overcapture flag refer to CC1OF description
Bit 11 CC3OF : Capture/Compare 3 overcapture flag refer to CC1OF description
Bit 10 CC2OF : Capture/compare 2 overcapture flag refer to CC1OF description
Bit 9 CC1OF : Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 TIF : Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
Bit 5 Reserved, must be kept at reset value.
410/1136 RM0008 Rev 21
RM0008 General-purpose timers (TIM2 to TIM5)
Bit 4 CC4IF : Capture/Compare 4 interrupt flag refer to CC1IF description
Bit 3 CC3IF : Capture/Compare 3 interrupt flag refer to CC1IF description
Bit 2 CC2IF : Capture/Compare 2 interrupt flag refer to CC1IF description
Bit 1 CC1IF : Capture/compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software.
0: No match.
1: The content of the counter TIMx_CNT has matched the content of the TIMx_CCR1 register.
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred.
1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity).
Bit 0 UIF : Update interrupt flag
– This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow or underflow and if the UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and
UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register.
RM0008 Rev 21 411/1136
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General-purpose timers (TIM2 to TIM5) RM0008
15 14
Address offset: 0x14
Reset value: 0x0000
13 12 11 10
Reserved
9 8 7 6
TG w
5
Res.
4 3 2 1
CC4G CC3G CC2G CC1G w w w w
0
UG w
Bits 15:7 Reserved, must be kept at reset value.
Bit 6 TG : Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4G : Capture/compare 4 generation refer to CC1G description
Bit 3 CC3G : Capture/compare 3 generation refer to CC1G description
Bit 2 CC2G : Capture/compare 2 generation refer to CC1G description
Bit 1 CC1G : Capture/compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured